/src/build/lib/Target/AArch64/AArch64GenFastISel.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* "Fast" Instruction Selector for the AArch64 target *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | |
10 | | // FastEmit Immediate Predicate functions. |
11 | 0 | static bool Predicate_imm0_31(int64_t Imm) { |
12 | 0 |
|
13 | 0 | return ((uint64_t)Imm) < 32; |
14 | 0 |
|
15 | 0 | } |
16 | 0 | static bool Predicate_imm0_63(int64_t Imm) { |
17 | 0 |
|
18 | 0 | return ((uint64_t)Imm) < 64; |
19 | 0 |
|
20 | 0 | } |
21 | 0 | static bool Predicate_imm32_0_31(int64_t Imm) { |
22 | 0 |
|
23 | 0 | return ((uint64_t)Imm) < 32; |
24 | 0 |
|
25 | 0 | } |
26 | 0 | static bool Predicate_tbz_imm0_31_diag(int64_t Imm) { |
27 | 0 |
|
28 | 0 | return (((uint32_t)Imm) < 32); |
29 | 0 |
|
30 | 0 | } |
31 | 0 | static bool Predicate_tbz_imm32_63(int64_t Imm) { |
32 | 0 |
|
33 | 0 | return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64); |
34 | 0 |
|
35 | 0 | } |
36 | 0 | static bool Predicate_VectorIndexD(int64_t Imm) { |
37 | 0 | return ((uint64_t)Imm) < 2; |
38 | 0 | } |
39 | 0 | static bool Predicate_VectorIndexS(int64_t Imm) { |
40 | 0 | return ((uint64_t)Imm) < 4; |
41 | 0 | } |
42 | 0 | static bool Predicate_VectorIndexH(int64_t Imm) { |
43 | 0 | return ((uint64_t)Imm) < 8; |
44 | 0 | } |
45 | 0 | static bool Predicate_VectorIndexB(int64_t Imm) { |
46 | 0 | return ((uint64_t)Imm) < 16; |
47 | 0 | } |
48 | 0 | static bool Predicate_VectorIndex0(int64_t Imm) { |
49 | 0 | return ((uint64_t)Imm) == 0; |
50 | 0 | } |
51 | 0 | static bool Predicate_imm0_255(int64_t Imm) { |
52 | |
|
53 | 0 | return ((uint32_t)Imm) < 256; |
54 | |
|
55 | 0 | } |
56 | 0 | static bool Predicate_vecshiftL64(int64_t Imm) { |
57 | 0 |
|
58 | 0 | return (((uint32_t)Imm) < 64); |
59 | 0 |
|
60 | 0 | } |
61 | 0 | static bool Predicate_vecshiftL32(int64_t Imm) { |
62 | 0 |
|
63 | 0 | return (((uint32_t)Imm) < 32); |
64 | 0 |
|
65 | 0 | } |
66 | 0 | static bool Predicate_vecshiftR64(int64_t Imm) { |
67 | 0 |
|
68 | 0 | return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65); |
69 | 0 |
|
70 | 0 | } |
71 | 0 | static bool Predicate_vecshiftL8(int64_t Imm) { |
72 | 0 |
|
73 | 0 | return (((uint32_t)Imm) < 8); |
74 | 0 |
|
75 | 0 | } |
76 | 0 | static bool Predicate_vecshiftL16(int64_t Imm) { |
77 | 0 |
|
78 | 0 | return (((uint32_t)Imm) < 16); |
79 | 0 |
|
80 | 0 | } |
81 | 0 | static bool Predicate_vecshiftR8(int64_t Imm) { |
82 | 0 |
|
83 | 0 | return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9); |
84 | 0 |
|
85 | 0 | } |
86 | 0 | static bool Predicate_vecshiftR16(int64_t Imm) { |
87 | 0 |
|
88 | 0 | return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17); |
89 | 0 |
|
90 | 0 | } |
91 | 0 | static bool Predicate_vecshiftR32(int64_t Imm) { |
92 | 0 |
|
93 | 0 | return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33); |
94 | 0 |
|
95 | 0 | } |
96 | 0 | static bool Predicate_simm8_32b(int64_t Imm) { |
97 | 0 | return Imm >= -128 && Imm < 128; |
98 | 0 | } |
99 | 0 | static bool Predicate_simm8_64b(int64_t Imm) { |
100 | 0 | return Imm >= -128 && Imm < 128; |
101 | 0 | } |
102 | 0 | static bool Predicate_uimm8_32b(int64_t Imm) { |
103 | 0 | return Imm >= 0 && Imm < 256; |
104 | 0 | } |
105 | 0 | static bool Predicate_uimm8_64b(int64_t Imm) { |
106 | 0 | return Imm >= 0 && Imm < 256; |
107 | 0 | } |
108 | 0 | static bool Predicate_simm6_32b(int64_t Imm) { |
109 | 0 | return Imm >= -32 && Imm < 32; |
110 | 0 | } |
111 | | |
112 | | |
113 | | // FastEmit functions for AArch64ISD::THREAD_POINTER. |
114 | | |
115 | 0 | unsigned fastEmit_AArch64ISD_THREAD_POINTER_MVT_i64_(MVT RetVT) { |
116 | 0 | if (RetVT.SimpleTy != MVT::i64) |
117 | 0 | return 0; |
118 | 0 | return fastEmitInst_(AArch64::MOVbaseTLS, &AArch64::GPR64RegClass); |
119 | 0 | } |
120 | | |
121 | 0 | unsigned fastEmit_AArch64ISD_THREAD_POINTER_(MVT VT, MVT RetVT) { |
122 | 0 | switch (VT.SimpleTy) { |
123 | 0 | case MVT::i64: return fastEmit_AArch64ISD_THREAD_POINTER_MVT_i64_(RetVT); |
124 | 0 | default: return 0; |
125 | 0 | } |
126 | 0 | } |
127 | | |
128 | | // Top-level FastEmit function. |
129 | | |
130 | 0 | unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode) override { |
131 | 0 | switch (Opcode) { |
132 | 0 | case AArch64ISD::THREAD_POINTER: return fastEmit_AArch64ISD_THREAD_POINTER_(VT, RetVT); |
133 | 0 | default: return 0; |
134 | 0 | } |
135 | 0 | } |
136 | | |
137 | | // FastEmit functions for AArch64ISD::CALL. |
138 | | |
139 | 0 | unsigned fastEmit_AArch64ISD_CALL_MVT_i64_r(MVT RetVT, unsigned Op0) { |
140 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
141 | 0 | return 0; |
142 | 0 | if (( MF->getSubtarget<AArch64Subtarget>().hardenSlsBlr() )) { |
143 | 0 | return fastEmitInst_r(AArch64::BLRNoIP, &AArch64::GPR64noipRegClass, Op0); |
144 | 0 | } |
145 | 0 | if (( !MF->getSubtarget<AArch64Subtarget>().hardenSlsBlr() )) { |
146 | 0 | return fastEmitInst_r(AArch64::BLR, &AArch64::GPR64RegClass, Op0); |
147 | 0 | } |
148 | 0 | return 0; |
149 | 0 | } |
150 | | |
151 | 0 | unsigned fastEmit_AArch64ISD_CALL_r(MVT VT, MVT RetVT, unsigned Op0) { |
152 | 0 | switch (VT.SimpleTy) { |
153 | 0 | case MVT::i64: return fastEmit_AArch64ISD_CALL_MVT_i64_r(RetVT, Op0); |
154 | 0 | default: return 0; |
155 | 0 | } |
156 | 0 | } |
157 | | |
158 | | // FastEmit functions for AArch64ISD::CMEQz. |
159 | | |
160 | 0 | unsigned fastEmit_AArch64ISD_CMEQz_MVT_v8i8_r(MVT RetVT, unsigned Op0) { |
161 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
162 | 0 | return 0; |
163 | 0 | if ((Subtarget->hasNEON())) { |
164 | 0 | return fastEmitInst_r(AArch64::CMEQv8i8rz, &AArch64::FPR64RegClass, Op0); |
165 | 0 | } |
166 | 0 | return 0; |
167 | 0 | } |
168 | | |
169 | 0 | unsigned fastEmit_AArch64ISD_CMEQz_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
170 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
171 | 0 | return 0; |
172 | 0 | if ((Subtarget->hasNEON())) { |
173 | 0 | return fastEmitInst_r(AArch64::CMEQv16i8rz, &AArch64::FPR128RegClass, Op0); |
174 | 0 | } |
175 | 0 | return 0; |
176 | 0 | } |
177 | | |
178 | 0 | unsigned fastEmit_AArch64ISD_CMEQz_MVT_v4i16_r(MVT RetVT, unsigned Op0) { |
179 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
180 | 0 | return 0; |
181 | 0 | if ((Subtarget->hasNEON())) { |
182 | 0 | return fastEmitInst_r(AArch64::CMEQv4i16rz, &AArch64::FPR64RegClass, Op0); |
183 | 0 | } |
184 | 0 | return 0; |
185 | 0 | } |
186 | | |
187 | 0 | unsigned fastEmit_AArch64ISD_CMEQz_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
188 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
189 | 0 | return 0; |
190 | 0 | if ((Subtarget->hasNEON())) { |
191 | 0 | return fastEmitInst_r(AArch64::CMEQv8i16rz, &AArch64::FPR128RegClass, Op0); |
192 | 0 | } |
193 | 0 | return 0; |
194 | 0 | } |
195 | | |
196 | 0 | unsigned fastEmit_AArch64ISD_CMEQz_MVT_v2i32_r(MVT RetVT, unsigned Op0) { |
197 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
198 | 0 | return 0; |
199 | 0 | if ((Subtarget->hasNEON())) { |
200 | 0 | return fastEmitInst_r(AArch64::CMEQv2i32rz, &AArch64::FPR64RegClass, Op0); |
201 | 0 | } |
202 | 0 | return 0; |
203 | 0 | } |
204 | | |
205 | 0 | unsigned fastEmit_AArch64ISD_CMEQz_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
206 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
207 | 0 | return 0; |
208 | 0 | if ((Subtarget->hasNEON())) { |
209 | 0 | return fastEmitInst_r(AArch64::CMEQv4i32rz, &AArch64::FPR128RegClass, Op0); |
210 | 0 | } |
211 | 0 | return 0; |
212 | 0 | } |
213 | | |
214 | 0 | unsigned fastEmit_AArch64ISD_CMEQz_MVT_v1i64_r(MVT RetVT, unsigned Op0) { |
215 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
216 | 0 | return 0; |
217 | 0 | if ((Subtarget->hasNEON())) { |
218 | 0 | return fastEmitInst_r(AArch64::CMEQv1i64rz, &AArch64::FPR64RegClass, Op0); |
219 | 0 | } |
220 | 0 | return 0; |
221 | 0 | } |
222 | | |
223 | 0 | unsigned fastEmit_AArch64ISD_CMEQz_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
224 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
225 | 0 | return 0; |
226 | 0 | if ((Subtarget->hasNEON())) { |
227 | 0 | return fastEmitInst_r(AArch64::CMEQv2i64rz, &AArch64::FPR128RegClass, Op0); |
228 | 0 | } |
229 | 0 | return 0; |
230 | 0 | } |
231 | | |
232 | 0 | unsigned fastEmit_AArch64ISD_CMEQz_r(MVT VT, MVT RetVT, unsigned Op0) { |
233 | 0 | switch (VT.SimpleTy) { |
234 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_CMEQz_MVT_v8i8_r(RetVT, Op0); |
235 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_CMEQz_MVT_v16i8_r(RetVT, Op0); |
236 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_CMEQz_MVT_v4i16_r(RetVT, Op0); |
237 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_CMEQz_MVT_v8i16_r(RetVT, Op0); |
238 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_CMEQz_MVT_v2i32_r(RetVT, Op0); |
239 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_CMEQz_MVT_v4i32_r(RetVT, Op0); |
240 | 0 | case MVT::v1i64: return fastEmit_AArch64ISD_CMEQz_MVT_v1i64_r(RetVT, Op0); |
241 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_CMEQz_MVT_v2i64_r(RetVT, Op0); |
242 | 0 | default: return 0; |
243 | 0 | } |
244 | 0 | } |
245 | | |
246 | | // FastEmit functions for AArch64ISD::CMGEz. |
247 | | |
248 | 0 | unsigned fastEmit_AArch64ISD_CMGEz_MVT_v8i8_r(MVT RetVT, unsigned Op0) { |
249 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
250 | 0 | return 0; |
251 | 0 | if ((Subtarget->hasNEON())) { |
252 | 0 | return fastEmitInst_r(AArch64::CMGEv8i8rz, &AArch64::FPR64RegClass, Op0); |
253 | 0 | } |
254 | 0 | return 0; |
255 | 0 | } |
256 | | |
257 | 0 | unsigned fastEmit_AArch64ISD_CMGEz_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
258 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
259 | 0 | return 0; |
260 | 0 | if ((Subtarget->hasNEON())) { |
261 | 0 | return fastEmitInst_r(AArch64::CMGEv16i8rz, &AArch64::FPR128RegClass, Op0); |
262 | 0 | } |
263 | 0 | return 0; |
264 | 0 | } |
265 | | |
266 | 0 | unsigned fastEmit_AArch64ISD_CMGEz_MVT_v4i16_r(MVT RetVT, unsigned Op0) { |
267 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
268 | 0 | return 0; |
269 | 0 | if ((Subtarget->hasNEON())) { |
270 | 0 | return fastEmitInst_r(AArch64::CMGEv4i16rz, &AArch64::FPR64RegClass, Op0); |
271 | 0 | } |
272 | 0 | return 0; |
273 | 0 | } |
274 | | |
275 | 0 | unsigned fastEmit_AArch64ISD_CMGEz_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
276 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
277 | 0 | return 0; |
278 | 0 | if ((Subtarget->hasNEON())) { |
279 | 0 | return fastEmitInst_r(AArch64::CMGEv8i16rz, &AArch64::FPR128RegClass, Op0); |
280 | 0 | } |
281 | 0 | return 0; |
282 | 0 | } |
283 | | |
284 | 0 | unsigned fastEmit_AArch64ISD_CMGEz_MVT_v2i32_r(MVT RetVT, unsigned Op0) { |
285 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
286 | 0 | return 0; |
287 | 0 | if ((Subtarget->hasNEON())) { |
288 | 0 | return fastEmitInst_r(AArch64::CMGEv2i32rz, &AArch64::FPR64RegClass, Op0); |
289 | 0 | } |
290 | 0 | return 0; |
291 | 0 | } |
292 | | |
293 | 0 | unsigned fastEmit_AArch64ISD_CMGEz_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
294 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
295 | 0 | return 0; |
296 | 0 | if ((Subtarget->hasNEON())) { |
297 | 0 | return fastEmitInst_r(AArch64::CMGEv4i32rz, &AArch64::FPR128RegClass, Op0); |
298 | 0 | } |
299 | 0 | return 0; |
300 | 0 | } |
301 | | |
302 | 0 | unsigned fastEmit_AArch64ISD_CMGEz_MVT_v1i64_r(MVT RetVT, unsigned Op0) { |
303 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
304 | 0 | return 0; |
305 | 0 | if ((Subtarget->hasNEON())) { |
306 | 0 | return fastEmitInst_r(AArch64::CMGEv1i64rz, &AArch64::FPR64RegClass, Op0); |
307 | 0 | } |
308 | 0 | return 0; |
309 | 0 | } |
310 | | |
311 | 0 | unsigned fastEmit_AArch64ISD_CMGEz_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
312 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
313 | 0 | return 0; |
314 | 0 | if ((Subtarget->hasNEON())) { |
315 | 0 | return fastEmitInst_r(AArch64::CMGEv2i64rz, &AArch64::FPR128RegClass, Op0); |
316 | 0 | } |
317 | 0 | return 0; |
318 | 0 | } |
319 | | |
320 | 0 | unsigned fastEmit_AArch64ISD_CMGEz_r(MVT VT, MVT RetVT, unsigned Op0) { |
321 | 0 | switch (VT.SimpleTy) { |
322 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_CMGEz_MVT_v8i8_r(RetVT, Op0); |
323 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_CMGEz_MVT_v16i8_r(RetVT, Op0); |
324 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_CMGEz_MVT_v4i16_r(RetVT, Op0); |
325 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_CMGEz_MVT_v8i16_r(RetVT, Op0); |
326 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_CMGEz_MVT_v2i32_r(RetVT, Op0); |
327 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_CMGEz_MVT_v4i32_r(RetVT, Op0); |
328 | 0 | case MVT::v1i64: return fastEmit_AArch64ISD_CMGEz_MVT_v1i64_r(RetVT, Op0); |
329 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_CMGEz_MVT_v2i64_r(RetVT, Op0); |
330 | 0 | default: return 0; |
331 | 0 | } |
332 | 0 | } |
333 | | |
334 | | // FastEmit functions for AArch64ISD::CMGTz. |
335 | | |
336 | 0 | unsigned fastEmit_AArch64ISD_CMGTz_MVT_v8i8_r(MVT RetVT, unsigned Op0) { |
337 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
338 | 0 | return 0; |
339 | 0 | if ((Subtarget->hasNEON())) { |
340 | 0 | return fastEmitInst_r(AArch64::CMGTv8i8rz, &AArch64::FPR64RegClass, Op0); |
341 | 0 | } |
342 | 0 | return 0; |
343 | 0 | } |
344 | | |
345 | 0 | unsigned fastEmit_AArch64ISD_CMGTz_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
346 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
347 | 0 | return 0; |
348 | 0 | if ((Subtarget->hasNEON())) { |
349 | 0 | return fastEmitInst_r(AArch64::CMGTv16i8rz, &AArch64::FPR128RegClass, Op0); |
350 | 0 | } |
351 | 0 | return 0; |
352 | 0 | } |
353 | | |
354 | 0 | unsigned fastEmit_AArch64ISD_CMGTz_MVT_v4i16_r(MVT RetVT, unsigned Op0) { |
355 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
356 | 0 | return 0; |
357 | 0 | if ((Subtarget->hasNEON())) { |
358 | 0 | return fastEmitInst_r(AArch64::CMGTv4i16rz, &AArch64::FPR64RegClass, Op0); |
359 | 0 | } |
360 | 0 | return 0; |
361 | 0 | } |
362 | | |
363 | 0 | unsigned fastEmit_AArch64ISD_CMGTz_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
364 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
365 | 0 | return 0; |
366 | 0 | if ((Subtarget->hasNEON())) { |
367 | 0 | return fastEmitInst_r(AArch64::CMGTv8i16rz, &AArch64::FPR128RegClass, Op0); |
368 | 0 | } |
369 | 0 | return 0; |
370 | 0 | } |
371 | | |
372 | 0 | unsigned fastEmit_AArch64ISD_CMGTz_MVT_v2i32_r(MVT RetVT, unsigned Op0) { |
373 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
374 | 0 | return 0; |
375 | 0 | if ((Subtarget->hasNEON())) { |
376 | 0 | return fastEmitInst_r(AArch64::CMGTv2i32rz, &AArch64::FPR64RegClass, Op0); |
377 | 0 | } |
378 | 0 | return 0; |
379 | 0 | } |
380 | | |
381 | 0 | unsigned fastEmit_AArch64ISD_CMGTz_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
382 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
383 | 0 | return 0; |
384 | 0 | if ((Subtarget->hasNEON())) { |
385 | 0 | return fastEmitInst_r(AArch64::CMGTv4i32rz, &AArch64::FPR128RegClass, Op0); |
386 | 0 | } |
387 | 0 | return 0; |
388 | 0 | } |
389 | | |
390 | 0 | unsigned fastEmit_AArch64ISD_CMGTz_MVT_v1i64_r(MVT RetVT, unsigned Op0) { |
391 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
392 | 0 | return 0; |
393 | 0 | if ((Subtarget->hasNEON())) { |
394 | 0 | return fastEmitInst_r(AArch64::CMGTv1i64rz, &AArch64::FPR64RegClass, Op0); |
395 | 0 | } |
396 | 0 | return 0; |
397 | 0 | } |
398 | | |
399 | 0 | unsigned fastEmit_AArch64ISD_CMGTz_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
400 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
401 | 0 | return 0; |
402 | 0 | if ((Subtarget->hasNEON())) { |
403 | 0 | return fastEmitInst_r(AArch64::CMGTv2i64rz, &AArch64::FPR128RegClass, Op0); |
404 | 0 | } |
405 | 0 | return 0; |
406 | 0 | } |
407 | | |
408 | 0 | unsigned fastEmit_AArch64ISD_CMGTz_r(MVT VT, MVT RetVT, unsigned Op0) { |
409 | 0 | switch (VT.SimpleTy) { |
410 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_CMGTz_MVT_v8i8_r(RetVT, Op0); |
411 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_CMGTz_MVT_v16i8_r(RetVT, Op0); |
412 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_CMGTz_MVT_v4i16_r(RetVT, Op0); |
413 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_CMGTz_MVT_v8i16_r(RetVT, Op0); |
414 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_CMGTz_MVT_v2i32_r(RetVT, Op0); |
415 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_CMGTz_MVT_v4i32_r(RetVT, Op0); |
416 | 0 | case MVT::v1i64: return fastEmit_AArch64ISD_CMGTz_MVT_v1i64_r(RetVT, Op0); |
417 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_CMGTz_MVT_v2i64_r(RetVT, Op0); |
418 | 0 | default: return 0; |
419 | 0 | } |
420 | 0 | } |
421 | | |
422 | | // FastEmit functions for AArch64ISD::CMLEz. |
423 | | |
424 | 0 | unsigned fastEmit_AArch64ISD_CMLEz_MVT_v8i8_r(MVT RetVT, unsigned Op0) { |
425 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
426 | 0 | return 0; |
427 | 0 | if ((Subtarget->hasNEON())) { |
428 | 0 | return fastEmitInst_r(AArch64::CMLEv8i8rz, &AArch64::FPR64RegClass, Op0); |
429 | 0 | } |
430 | 0 | return 0; |
431 | 0 | } |
432 | | |
433 | 0 | unsigned fastEmit_AArch64ISD_CMLEz_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
434 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
435 | 0 | return 0; |
436 | 0 | if ((Subtarget->hasNEON())) { |
437 | 0 | return fastEmitInst_r(AArch64::CMLEv16i8rz, &AArch64::FPR128RegClass, Op0); |
438 | 0 | } |
439 | 0 | return 0; |
440 | 0 | } |
441 | | |
442 | 0 | unsigned fastEmit_AArch64ISD_CMLEz_MVT_v4i16_r(MVT RetVT, unsigned Op0) { |
443 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
444 | 0 | return 0; |
445 | 0 | if ((Subtarget->hasNEON())) { |
446 | 0 | return fastEmitInst_r(AArch64::CMLEv4i16rz, &AArch64::FPR64RegClass, Op0); |
447 | 0 | } |
448 | 0 | return 0; |
449 | 0 | } |
450 | | |
451 | 0 | unsigned fastEmit_AArch64ISD_CMLEz_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
452 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
453 | 0 | return 0; |
454 | 0 | if ((Subtarget->hasNEON())) { |
455 | 0 | return fastEmitInst_r(AArch64::CMLEv8i16rz, &AArch64::FPR128RegClass, Op0); |
456 | 0 | } |
457 | 0 | return 0; |
458 | 0 | } |
459 | | |
460 | 0 | unsigned fastEmit_AArch64ISD_CMLEz_MVT_v2i32_r(MVT RetVT, unsigned Op0) { |
461 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
462 | 0 | return 0; |
463 | 0 | if ((Subtarget->hasNEON())) { |
464 | 0 | return fastEmitInst_r(AArch64::CMLEv2i32rz, &AArch64::FPR64RegClass, Op0); |
465 | 0 | } |
466 | 0 | return 0; |
467 | 0 | } |
468 | | |
469 | 0 | unsigned fastEmit_AArch64ISD_CMLEz_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
470 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
471 | 0 | return 0; |
472 | 0 | if ((Subtarget->hasNEON())) { |
473 | 0 | return fastEmitInst_r(AArch64::CMLEv4i32rz, &AArch64::FPR128RegClass, Op0); |
474 | 0 | } |
475 | 0 | return 0; |
476 | 0 | } |
477 | | |
478 | 0 | unsigned fastEmit_AArch64ISD_CMLEz_MVT_v1i64_r(MVT RetVT, unsigned Op0) { |
479 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
480 | 0 | return 0; |
481 | 0 | if ((Subtarget->hasNEON())) { |
482 | 0 | return fastEmitInst_r(AArch64::CMLEv1i64rz, &AArch64::FPR64RegClass, Op0); |
483 | 0 | } |
484 | 0 | return 0; |
485 | 0 | } |
486 | | |
487 | 0 | unsigned fastEmit_AArch64ISD_CMLEz_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
488 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
489 | 0 | return 0; |
490 | 0 | if ((Subtarget->hasNEON())) { |
491 | 0 | return fastEmitInst_r(AArch64::CMLEv2i64rz, &AArch64::FPR128RegClass, Op0); |
492 | 0 | } |
493 | 0 | return 0; |
494 | 0 | } |
495 | | |
496 | 0 | unsigned fastEmit_AArch64ISD_CMLEz_r(MVT VT, MVT RetVT, unsigned Op0) { |
497 | 0 | switch (VT.SimpleTy) { |
498 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_CMLEz_MVT_v8i8_r(RetVT, Op0); |
499 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_CMLEz_MVT_v16i8_r(RetVT, Op0); |
500 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_CMLEz_MVT_v4i16_r(RetVT, Op0); |
501 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_CMLEz_MVT_v8i16_r(RetVT, Op0); |
502 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_CMLEz_MVT_v2i32_r(RetVT, Op0); |
503 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_CMLEz_MVT_v4i32_r(RetVT, Op0); |
504 | 0 | case MVT::v1i64: return fastEmit_AArch64ISD_CMLEz_MVT_v1i64_r(RetVT, Op0); |
505 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_CMLEz_MVT_v2i64_r(RetVT, Op0); |
506 | 0 | default: return 0; |
507 | 0 | } |
508 | 0 | } |
509 | | |
510 | | // FastEmit functions for AArch64ISD::CMLTz. |
511 | | |
512 | 0 | unsigned fastEmit_AArch64ISD_CMLTz_MVT_v8i8_r(MVT RetVT, unsigned Op0) { |
513 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
514 | 0 | return 0; |
515 | 0 | if ((Subtarget->hasNEON())) { |
516 | 0 | return fastEmitInst_r(AArch64::CMLTv8i8rz, &AArch64::FPR64RegClass, Op0); |
517 | 0 | } |
518 | 0 | return 0; |
519 | 0 | } |
520 | | |
521 | 0 | unsigned fastEmit_AArch64ISD_CMLTz_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
522 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
523 | 0 | return 0; |
524 | 0 | if ((Subtarget->hasNEON())) { |
525 | 0 | return fastEmitInst_r(AArch64::CMLTv16i8rz, &AArch64::FPR128RegClass, Op0); |
526 | 0 | } |
527 | 0 | return 0; |
528 | 0 | } |
529 | | |
530 | 0 | unsigned fastEmit_AArch64ISD_CMLTz_MVT_v4i16_r(MVT RetVT, unsigned Op0) { |
531 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
532 | 0 | return 0; |
533 | 0 | if ((Subtarget->hasNEON())) { |
534 | 0 | return fastEmitInst_r(AArch64::CMLTv4i16rz, &AArch64::FPR64RegClass, Op0); |
535 | 0 | } |
536 | 0 | return 0; |
537 | 0 | } |
538 | | |
539 | 0 | unsigned fastEmit_AArch64ISD_CMLTz_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
540 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
541 | 0 | return 0; |
542 | 0 | if ((Subtarget->hasNEON())) { |
543 | 0 | return fastEmitInst_r(AArch64::CMLTv8i16rz, &AArch64::FPR128RegClass, Op0); |
544 | 0 | } |
545 | 0 | return 0; |
546 | 0 | } |
547 | | |
548 | 0 | unsigned fastEmit_AArch64ISD_CMLTz_MVT_v2i32_r(MVT RetVT, unsigned Op0) { |
549 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
550 | 0 | return 0; |
551 | 0 | if ((Subtarget->hasNEON())) { |
552 | 0 | return fastEmitInst_r(AArch64::CMLTv2i32rz, &AArch64::FPR64RegClass, Op0); |
553 | 0 | } |
554 | 0 | return 0; |
555 | 0 | } |
556 | | |
557 | 0 | unsigned fastEmit_AArch64ISD_CMLTz_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
558 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
559 | 0 | return 0; |
560 | 0 | if ((Subtarget->hasNEON())) { |
561 | 0 | return fastEmitInst_r(AArch64::CMLTv4i32rz, &AArch64::FPR128RegClass, Op0); |
562 | 0 | } |
563 | 0 | return 0; |
564 | 0 | } |
565 | | |
566 | 0 | unsigned fastEmit_AArch64ISD_CMLTz_MVT_v1i64_r(MVT RetVT, unsigned Op0) { |
567 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
568 | 0 | return 0; |
569 | 0 | if ((Subtarget->hasNEON())) { |
570 | 0 | return fastEmitInst_r(AArch64::CMLTv1i64rz, &AArch64::FPR64RegClass, Op0); |
571 | 0 | } |
572 | 0 | return 0; |
573 | 0 | } |
574 | | |
575 | 0 | unsigned fastEmit_AArch64ISD_CMLTz_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
576 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
577 | 0 | return 0; |
578 | 0 | if ((Subtarget->hasNEON())) { |
579 | 0 | return fastEmitInst_r(AArch64::CMLTv2i64rz, &AArch64::FPR128RegClass, Op0); |
580 | 0 | } |
581 | 0 | return 0; |
582 | 0 | } |
583 | | |
584 | 0 | unsigned fastEmit_AArch64ISD_CMLTz_r(MVT VT, MVT RetVT, unsigned Op0) { |
585 | 0 | switch (VT.SimpleTy) { |
586 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_CMLTz_MVT_v8i8_r(RetVT, Op0); |
587 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_CMLTz_MVT_v16i8_r(RetVT, Op0); |
588 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_CMLTz_MVT_v4i16_r(RetVT, Op0); |
589 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_CMLTz_MVT_v8i16_r(RetVT, Op0); |
590 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_CMLTz_MVT_v2i32_r(RetVT, Op0); |
591 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_CMLTz_MVT_v4i32_r(RetVT, Op0); |
592 | 0 | case MVT::v1i64: return fastEmit_AArch64ISD_CMLTz_MVT_v1i64_r(RetVT, Op0); |
593 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_CMLTz_MVT_v2i64_r(RetVT, Op0); |
594 | 0 | default: return 0; |
595 | 0 | } |
596 | 0 | } |
597 | | |
598 | | // FastEmit functions for AArch64ISD::DUP. |
599 | | |
600 | 0 | unsigned fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v8i8_r(unsigned Op0) { |
601 | 0 | if ((Subtarget->hasNEON())) { |
602 | 0 | return fastEmitInst_r(AArch64::DUPv8i8gpr, &AArch64::FPR64RegClass, Op0); |
603 | 0 | } |
604 | 0 | return 0; |
605 | 0 | } |
606 | | |
607 | 0 | unsigned fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v16i8_r(unsigned Op0) { |
608 | 0 | if ((Subtarget->hasNEON())) { |
609 | 0 | return fastEmitInst_r(AArch64::DUPv16i8gpr, &AArch64::FPR128RegClass, Op0); |
610 | 0 | } |
611 | 0 | return 0; |
612 | 0 | } |
613 | | |
614 | 0 | unsigned fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v4i16_r(unsigned Op0) { |
615 | 0 | if ((Subtarget->hasNEON())) { |
616 | 0 | return fastEmitInst_r(AArch64::DUPv4i16gpr, &AArch64::FPR64RegClass, Op0); |
617 | 0 | } |
618 | 0 | return 0; |
619 | 0 | } |
620 | | |
621 | 0 | unsigned fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v8i16_r(unsigned Op0) { |
622 | 0 | if ((Subtarget->hasNEON())) { |
623 | 0 | return fastEmitInst_r(AArch64::DUPv8i16gpr, &AArch64::FPR128RegClass, Op0); |
624 | 0 | } |
625 | 0 | return 0; |
626 | 0 | } |
627 | | |
628 | 0 | unsigned fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v2i32_r(unsigned Op0) { |
629 | 0 | if ((Subtarget->hasNEON())) { |
630 | 0 | return fastEmitInst_r(AArch64::DUPv2i32gpr, &AArch64::FPR64RegClass, Op0); |
631 | 0 | } |
632 | 0 | return 0; |
633 | 0 | } |
634 | | |
635 | 0 | unsigned fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v4i32_r(unsigned Op0) { |
636 | 0 | if ((Subtarget->hasNEON())) { |
637 | 0 | return fastEmitInst_r(AArch64::DUPv4i32gpr, &AArch64::FPR128RegClass, Op0); |
638 | 0 | } |
639 | 0 | return 0; |
640 | 0 | } |
641 | | |
642 | 0 | unsigned fastEmit_AArch64ISD_DUP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
643 | 0 | switch (RetVT.SimpleTy) { |
644 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v8i8_r(Op0); |
645 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v16i8_r(Op0); |
646 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v4i16_r(Op0); |
647 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v8i16_r(Op0); |
648 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v2i32_r(Op0); |
649 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v4i32_r(Op0); |
650 | 0 | default: return 0; |
651 | 0 | } |
652 | 0 | } |
653 | | |
654 | 0 | unsigned fastEmit_AArch64ISD_DUP_MVT_i64_r(MVT RetVT, unsigned Op0) { |
655 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
656 | 0 | return 0; |
657 | 0 | if ((Subtarget->hasNEON())) { |
658 | 0 | return fastEmitInst_r(AArch64::DUPv2i64gpr, &AArch64::FPR128RegClass, Op0); |
659 | 0 | } |
660 | 0 | return 0; |
661 | 0 | } |
662 | | |
663 | 0 | unsigned fastEmit_AArch64ISD_DUP_r(MVT VT, MVT RetVT, unsigned Op0) { |
664 | 0 | switch (VT.SimpleTy) { |
665 | 0 | case MVT::i32: return fastEmit_AArch64ISD_DUP_MVT_i32_r(RetVT, Op0); |
666 | 0 | case MVT::i64: return fastEmit_AArch64ISD_DUP_MVT_i64_r(RetVT, Op0); |
667 | 0 | default: return 0; |
668 | 0 | } |
669 | 0 | } |
670 | | |
671 | | // FastEmit functions for AArch64ISD::FCMEQz. |
672 | | |
673 | 0 | unsigned fastEmit_AArch64ISD_FCMEQz_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
674 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
675 | 0 | return 0; |
676 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
677 | 0 | return fastEmitInst_r(AArch64::FCMEQv4i16rz, &AArch64::FPR64RegClass, Op0); |
678 | 0 | } |
679 | 0 | return 0; |
680 | 0 | } |
681 | | |
682 | 0 | unsigned fastEmit_AArch64ISD_FCMEQz_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
683 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
684 | 0 | return 0; |
685 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
686 | 0 | return fastEmitInst_r(AArch64::FCMEQv8i16rz, &AArch64::FPR128RegClass, Op0); |
687 | 0 | } |
688 | 0 | return 0; |
689 | 0 | } |
690 | | |
691 | 0 | unsigned fastEmit_AArch64ISD_FCMEQz_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
692 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
693 | 0 | return 0; |
694 | 0 | if ((Subtarget->hasNEON())) { |
695 | 0 | return fastEmitInst_r(AArch64::FCMEQv2i32rz, &AArch64::FPR64RegClass, Op0); |
696 | 0 | } |
697 | 0 | return 0; |
698 | 0 | } |
699 | | |
700 | 0 | unsigned fastEmit_AArch64ISD_FCMEQz_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
701 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
702 | 0 | return 0; |
703 | 0 | if ((Subtarget->hasNEON())) { |
704 | 0 | return fastEmitInst_r(AArch64::FCMEQv4i32rz, &AArch64::FPR128RegClass, Op0); |
705 | 0 | } |
706 | 0 | return 0; |
707 | 0 | } |
708 | | |
709 | 0 | unsigned fastEmit_AArch64ISD_FCMEQz_MVT_v1f64_r(MVT RetVT, unsigned Op0) { |
710 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
711 | 0 | return 0; |
712 | 0 | if ((Subtarget->hasNEON())) { |
713 | 0 | return fastEmitInst_r(AArch64::FCMEQv1i64rz, &AArch64::FPR64RegClass, Op0); |
714 | 0 | } |
715 | 0 | return 0; |
716 | 0 | } |
717 | | |
718 | 0 | unsigned fastEmit_AArch64ISD_FCMEQz_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
719 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
720 | 0 | return 0; |
721 | 0 | if ((Subtarget->hasNEON())) { |
722 | 0 | return fastEmitInst_r(AArch64::FCMEQv2i64rz, &AArch64::FPR128RegClass, Op0); |
723 | 0 | } |
724 | 0 | return 0; |
725 | 0 | } |
726 | | |
727 | 0 | unsigned fastEmit_AArch64ISD_FCMEQz_r(MVT VT, MVT RetVT, unsigned Op0) { |
728 | 0 | switch (VT.SimpleTy) { |
729 | 0 | case MVT::v4f16: return fastEmit_AArch64ISD_FCMEQz_MVT_v4f16_r(RetVT, Op0); |
730 | 0 | case MVT::v8f16: return fastEmit_AArch64ISD_FCMEQz_MVT_v8f16_r(RetVT, Op0); |
731 | 0 | case MVT::v2f32: return fastEmit_AArch64ISD_FCMEQz_MVT_v2f32_r(RetVT, Op0); |
732 | 0 | case MVT::v4f32: return fastEmit_AArch64ISD_FCMEQz_MVT_v4f32_r(RetVT, Op0); |
733 | 0 | case MVT::v1f64: return fastEmit_AArch64ISD_FCMEQz_MVT_v1f64_r(RetVT, Op0); |
734 | 0 | case MVT::v2f64: return fastEmit_AArch64ISD_FCMEQz_MVT_v2f64_r(RetVT, Op0); |
735 | 0 | default: return 0; |
736 | 0 | } |
737 | 0 | } |
738 | | |
739 | | // FastEmit functions for AArch64ISD::FCMGEz. |
740 | | |
741 | 0 | unsigned fastEmit_AArch64ISD_FCMGEz_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
742 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
743 | 0 | return 0; |
744 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
745 | 0 | return fastEmitInst_r(AArch64::FCMGEv4i16rz, &AArch64::FPR64RegClass, Op0); |
746 | 0 | } |
747 | 0 | return 0; |
748 | 0 | } |
749 | | |
750 | 0 | unsigned fastEmit_AArch64ISD_FCMGEz_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
751 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
752 | 0 | return 0; |
753 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
754 | 0 | return fastEmitInst_r(AArch64::FCMGEv8i16rz, &AArch64::FPR128RegClass, Op0); |
755 | 0 | } |
756 | 0 | return 0; |
757 | 0 | } |
758 | | |
759 | 0 | unsigned fastEmit_AArch64ISD_FCMGEz_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
760 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
761 | 0 | return 0; |
762 | 0 | if ((Subtarget->hasNEON())) { |
763 | 0 | return fastEmitInst_r(AArch64::FCMGEv2i32rz, &AArch64::FPR64RegClass, Op0); |
764 | 0 | } |
765 | 0 | return 0; |
766 | 0 | } |
767 | | |
768 | 0 | unsigned fastEmit_AArch64ISD_FCMGEz_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
769 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
770 | 0 | return 0; |
771 | 0 | if ((Subtarget->hasNEON())) { |
772 | 0 | return fastEmitInst_r(AArch64::FCMGEv4i32rz, &AArch64::FPR128RegClass, Op0); |
773 | 0 | } |
774 | 0 | return 0; |
775 | 0 | } |
776 | | |
777 | 0 | unsigned fastEmit_AArch64ISD_FCMGEz_MVT_v1f64_r(MVT RetVT, unsigned Op0) { |
778 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
779 | 0 | return 0; |
780 | 0 | if ((Subtarget->hasNEON())) { |
781 | 0 | return fastEmitInst_r(AArch64::FCMGEv1i64rz, &AArch64::FPR64RegClass, Op0); |
782 | 0 | } |
783 | 0 | return 0; |
784 | 0 | } |
785 | | |
786 | 0 | unsigned fastEmit_AArch64ISD_FCMGEz_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
787 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
788 | 0 | return 0; |
789 | 0 | if ((Subtarget->hasNEON())) { |
790 | 0 | return fastEmitInst_r(AArch64::FCMGEv2i64rz, &AArch64::FPR128RegClass, Op0); |
791 | 0 | } |
792 | 0 | return 0; |
793 | 0 | } |
794 | | |
795 | 0 | unsigned fastEmit_AArch64ISD_FCMGEz_r(MVT VT, MVT RetVT, unsigned Op0) { |
796 | 0 | switch (VT.SimpleTy) { |
797 | 0 | case MVT::v4f16: return fastEmit_AArch64ISD_FCMGEz_MVT_v4f16_r(RetVT, Op0); |
798 | 0 | case MVT::v8f16: return fastEmit_AArch64ISD_FCMGEz_MVT_v8f16_r(RetVT, Op0); |
799 | 0 | case MVT::v2f32: return fastEmit_AArch64ISD_FCMGEz_MVT_v2f32_r(RetVT, Op0); |
800 | 0 | case MVT::v4f32: return fastEmit_AArch64ISD_FCMGEz_MVT_v4f32_r(RetVT, Op0); |
801 | 0 | case MVT::v1f64: return fastEmit_AArch64ISD_FCMGEz_MVT_v1f64_r(RetVT, Op0); |
802 | 0 | case MVT::v2f64: return fastEmit_AArch64ISD_FCMGEz_MVT_v2f64_r(RetVT, Op0); |
803 | 0 | default: return 0; |
804 | 0 | } |
805 | 0 | } |
806 | | |
807 | | // FastEmit functions for AArch64ISD::FCMGTz. |
808 | | |
809 | 0 | unsigned fastEmit_AArch64ISD_FCMGTz_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
810 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
811 | 0 | return 0; |
812 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
813 | 0 | return fastEmitInst_r(AArch64::FCMGTv4i16rz, &AArch64::FPR64RegClass, Op0); |
814 | 0 | } |
815 | 0 | return 0; |
816 | 0 | } |
817 | | |
818 | 0 | unsigned fastEmit_AArch64ISD_FCMGTz_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
819 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
820 | 0 | return 0; |
821 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
822 | 0 | return fastEmitInst_r(AArch64::FCMGTv8i16rz, &AArch64::FPR128RegClass, Op0); |
823 | 0 | } |
824 | 0 | return 0; |
825 | 0 | } |
826 | | |
827 | 0 | unsigned fastEmit_AArch64ISD_FCMGTz_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
828 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
829 | 0 | return 0; |
830 | 0 | if ((Subtarget->hasNEON())) { |
831 | 0 | return fastEmitInst_r(AArch64::FCMGTv2i32rz, &AArch64::FPR64RegClass, Op0); |
832 | 0 | } |
833 | 0 | return 0; |
834 | 0 | } |
835 | | |
836 | 0 | unsigned fastEmit_AArch64ISD_FCMGTz_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
837 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
838 | 0 | return 0; |
839 | 0 | if ((Subtarget->hasNEON())) { |
840 | 0 | return fastEmitInst_r(AArch64::FCMGTv4i32rz, &AArch64::FPR128RegClass, Op0); |
841 | 0 | } |
842 | 0 | return 0; |
843 | 0 | } |
844 | | |
845 | 0 | unsigned fastEmit_AArch64ISD_FCMGTz_MVT_v1f64_r(MVT RetVT, unsigned Op0) { |
846 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
847 | 0 | return 0; |
848 | 0 | if ((Subtarget->hasNEON())) { |
849 | 0 | return fastEmitInst_r(AArch64::FCMGTv1i64rz, &AArch64::FPR64RegClass, Op0); |
850 | 0 | } |
851 | 0 | return 0; |
852 | 0 | } |
853 | | |
854 | 0 | unsigned fastEmit_AArch64ISD_FCMGTz_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
855 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
856 | 0 | return 0; |
857 | 0 | if ((Subtarget->hasNEON())) { |
858 | 0 | return fastEmitInst_r(AArch64::FCMGTv2i64rz, &AArch64::FPR128RegClass, Op0); |
859 | 0 | } |
860 | 0 | return 0; |
861 | 0 | } |
862 | | |
863 | 0 | unsigned fastEmit_AArch64ISD_FCMGTz_r(MVT VT, MVT RetVT, unsigned Op0) { |
864 | 0 | switch (VT.SimpleTy) { |
865 | 0 | case MVT::v4f16: return fastEmit_AArch64ISD_FCMGTz_MVT_v4f16_r(RetVT, Op0); |
866 | 0 | case MVT::v8f16: return fastEmit_AArch64ISD_FCMGTz_MVT_v8f16_r(RetVT, Op0); |
867 | 0 | case MVT::v2f32: return fastEmit_AArch64ISD_FCMGTz_MVT_v2f32_r(RetVT, Op0); |
868 | 0 | case MVT::v4f32: return fastEmit_AArch64ISD_FCMGTz_MVT_v4f32_r(RetVT, Op0); |
869 | 0 | case MVT::v1f64: return fastEmit_AArch64ISD_FCMGTz_MVT_v1f64_r(RetVT, Op0); |
870 | 0 | case MVT::v2f64: return fastEmit_AArch64ISD_FCMGTz_MVT_v2f64_r(RetVT, Op0); |
871 | 0 | default: return 0; |
872 | 0 | } |
873 | 0 | } |
874 | | |
875 | | // FastEmit functions for AArch64ISD::FCMLEz. |
876 | | |
877 | 0 | unsigned fastEmit_AArch64ISD_FCMLEz_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
878 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
879 | 0 | return 0; |
880 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
881 | 0 | return fastEmitInst_r(AArch64::FCMLEv4i16rz, &AArch64::FPR64RegClass, Op0); |
882 | 0 | } |
883 | 0 | return 0; |
884 | 0 | } |
885 | | |
886 | 0 | unsigned fastEmit_AArch64ISD_FCMLEz_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
887 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
888 | 0 | return 0; |
889 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
890 | 0 | return fastEmitInst_r(AArch64::FCMLEv8i16rz, &AArch64::FPR128RegClass, Op0); |
891 | 0 | } |
892 | 0 | return 0; |
893 | 0 | } |
894 | | |
895 | 0 | unsigned fastEmit_AArch64ISD_FCMLEz_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
896 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
897 | 0 | return 0; |
898 | 0 | if ((Subtarget->hasNEON())) { |
899 | 0 | return fastEmitInst_r(AArch64::FCMLEv2i32rz, &AArch64::FPR64RegClass, Op0); |
900 | 0 | } |
901 | 0 | return 0; |
902 | 0 | } |
903 | | |
904 | 0 | unsigned fastEmit_AArch64ISD_FCMLEz_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
905 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
906 | 0 | return 0; |
907 | 0 | if ((Subtarget->hasNEON())) { |
908 | 0 | return fastEmitInst_r(AArch64::FCMLEv4i32rz, &AArch64::FPR128RegClass, Op0); |
909 | 0 | } |
910 | 0 | return 0; |
911 | 0 | } |
912 | | |
913 | 0 | unsigned fastEmit_AArch64ISD_FCMLEz_MVT_v1f64_r(MVT RetVT, unsigned Op0) { |
914 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
915 | 0 | return 0; |
916 | 0 | if ((Subtarget->hasNEON())) { |
917 | 0 | return fastEmitInst_r(AArch64::FCMLEv1i64rz, &AArch64::FPR64RegClass, Op0); |
918 | 0 | } |
919 | 0 | return 0; |
920 | 0 | } |
921 | | |
922 | 0 | unsigned fastEmit_AArch64ISD_FCMLEz_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
923 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
924 | 0 | return 0; |
925 | 0 | if ((Subtarget->hasNEON())) { |
926 | 0 | return fastEmitInst_r(AArch64::FCMLEv2i64rz, &AArch64::FPR128RegClass, Op0); |
927 | 0 | } |
928 | 0 | return 0; |
929 | 0 | } |
930 | | |
931 | 0 | unsigned fastEmit_AArch64ISD_FCMLEz_r(MVT VT, MVT RetVT, unsigned Op0) { |
932 | 0 | switch (VT.SimpleTy) { |
933 | 0 | case MVT::v4f16: return fastEmit_AArch64ISD_FCMLEz_MVT_v4f16_r(RetVT, Op0); |
934 | 0 | case MVT::v8f16: return fastEmit_AArch64ISD_FCMLEz_MVT_v8f16_r(RetVT, Op0); |
935 | 0 | case MVT::v2f32: return fastEmit_AArch64ISD_FCMLEz_MVT_v2f32_r(RetVT, Op0); |
936 | 0 | case MVT::v4f32: return fastEmit_AArch64ISD_FCMLEz_MVT_v4f32_r(RetVT, Op0); |
937 | 0 | case MVT::v1f64: return fastEmit_AArch64ISD_FCMLEz_MVT_v1f64_r(RetVT, Op0); |
938 | 0 | case MVT::v2f64: return fastEmit_AArch64ISD_FCMLEz_MVT_v2f64_r(RetVT, Op0); |
939 | 0 | default: return 0; |
940 | 0 | } |
941 | 0 | } |
942 | | |
943 | | // FastEmit functions for AArch64ISD::FCMLTz. |
944 | | |
945 | 0 | unsigned fastEmit_AArch64ISD_FCMLTz_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
946 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
947 | 0 | return 0; |
948 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
949 | 0 | return fastEmitInst_r(AArch64::FCMLTv4i16rz, &AArch64::FPR64RegClass, Op0); |
950 | 0 | } |
951 | 0 | return 0; |
952 | 0 | } |
953 | | |
954 | 0 | unsigned fastEmit_AArch64ISD_FCMLTz_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
955 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
956 | 0 | return 0; |
957 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
958 | 0 | return fastEmitInst_r(AArch64::FCMLTv8i16rz, &AArch64::FPR128RegClass, Op0); |
959 | 0 | } |
960 | 0 | return 0; |
961 | 0 | } |
962 | | |
963 | 0 | unsigned fastEmit_AArch64ISD_FCMLTz_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
964 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
965 | 0 | return 0; |
966 | 0 | if ((Subtarget->hasNEON())) { |
967 | 0 | return fastEmitInst_r(AArch64::FCMLTv2i32rz, &AArch64::FPR64RegClass, Op0); |
968 | 0 | } |
969 | 0 | return 0; |
970 | 0 | } |
971 | | |
972 | 0 | unsigned fastEmit_AArch64ISD_FCMLTz_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
973 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
974 | 0 | return 0; |
975 | 0 | if ((Subtarget->hasNEON())) { |
976 | 0 | return fastEmitInst_r(AArch64::FCMLTv4i32rz, &AArch64::FPR128RegClass, Op0); |
977 | 0 | } |
978 | 0 | return 0; |
979 | 0 | } |
980 | | |
981 | 0 | unsigned fastEmit_AArch64ISD_FCMLTz_MVT_v1f64_r(MVT RetVT, unsigned Op0) { |
982 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
983 | 0 | return 0; |
984 | 0 | if ((Subtarget->hasNEON())) { |
985 | 0 | return fastEmitInst_r(AArch64::FCMLTv1i64rz, &AArch64::FPR64RegClass, Op0); |
986 | 0 | } |
987 | 0 | return 0; |
988 | 0 | } |
989 | | |
990 | 0 | unsigned fastEmit_AArch64ISD_FCMLTz_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
991 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
992 | 0 | return 0; |
993 | 0 | if ((Subtarget->hasNEON())) { |
994 | 0 | return fastEmitInst_r(AArch64::FCMLTv2i64rz, &AArch64::FPR128RegClass, Op0); |
995 | 0 | } |
996 | 0 | return 0; |
997 | 0 | } |
998 | | |
999 | 0 | unsigned fastEmit_AArch64ISD_FCMLTz_r(MVT VT, MVT RetVT, unsigned Op0) { |
1000 | 0 | switch (VT.SimpleTy) { |
1001 | 0 | case MVT::v4f16: return fastEmit_AArch64ISD_FCMLTz_MVT_v4f16_r(RetVT, Op0); |
1002 | 0 | case MVT::v8f16: return fastEmit_AArch64ISD_FCMLTz_MVT_v8f16_r(RetVT, Op0); |
1003 | 0 | case MVT::v2f32: return fastEmit_AArch64ISD_FCMLTz_MVT_v2f32_r(RetVT, Op0); |
1004 | 0 | case MVT::v4f32: return fastEmit_AArch64ISD_FCMLTz_MVT_v4f32_r(RetVT, Op0); |
1005 | 0 | case MVT::v1f64: return fastEmit_AArch64ISD_FCMLTz_MVT_v1f64_r(RetVT, Op0); |
1006 | 0 | case MVT::v2f64: return fastEmit_AArch64ISD_FCMLTz_MVT_v2f64_r(RetVT, Op0); |
1007 | 0 | default: return 0; |
1008 | 0 | } |
1009 | 0 | } |
1010 | | |
1011 | | // FastEmit functions for AArch64ISD::FRECPE. |
1012 | | |
1013 | 0 | unsigned fastEmit_AArch64ISD_FRECPE_MVT_f32_r(MVT RetVT, unsigned Op0) { |
1014 | 0 | if (RetVT.SimpleTy != MVT::f32) |
1015 | 0 | return 0; |
1016 | 0 | return fastEmitInst_r(AArch64::FRECPEv1i32, &AArch64::FPR32RegClass, Op0); |
1017 | 0 | } |
1018 | | |
1019 | 0 | unsigned fastEmit_AArch64ISD_FRECPE_MVT_f64_r(MVT RetVT, unsigned Op0) { |
1020 | 0 | if (RetVT.SimpleTy != MVT::f64) |
1021 | 0 | return 0; |
1022 | 0 | return fastEmitInst_r(AArch64::FRECPEv1i64, &AArch64::FPR64RegClass, Op0); |
1023 | 0 | } |
1024 | | |
1025 | 0 | unsigned fastEmit_AArch64ISD_FRECPE_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
1026 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
1027 | 0 | return 0; |
1028 | 0 | return fastEmitInst_r(AArch64::FRECPEv2f32, &AArch64::FPR64RegClass, Op0); |
1029 | 0 | } |
1030 | | |
1031 | 0 | unsigned fastEmit_AArch64ISD_FRECPE_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
1032 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
1033 | 0 | return 0; |
1034 | 0 | return fastEmitInst_r(AArch64::FRECPEv4f32, &AArch64::FPR128RegClass, Op0); |
1035 | 0 | } |
1036 | | |
1037 | 0 | unsigned fastEmit_AArch64ISD_FRECPE_MVT_v1f64_r(MVT RetVT, unsigned Op0) { |
1038 | 0 | if (RetVT.SimpleTy != MVT::v1f64) |
1039 | 0 | return 0; |
1040 | 0 | return fastEmitInst_r(AArch64::FRECPEv1i64, &AArch64::FPR64RegClass, Op0); |
1041 | 0 | } |
1042 | | |
1043 | 0 | unsigned fastEmit_AArch64ISD_FRECPE_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
1044 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
1045 | 0 | return 0; |
1046 | 0 | return fastEmitInst_r(AArch64::FRECPEv2f64, &AArch64::FPR128RegClass, Op0); |
1047 | 0 | } |
1048 | | |
1049 | 0 | unsigned fastEmit_AArch64ISD_FRECPE_MVT_nxv8f16_r(MVT RetVT, unsigned Op0) { |
1050 | 0 | if (RetVT.SimpleTy != MVT::nxv8f16) |
1051 | 0 | return 0; |
1052 | 0 | if ((Subtarget->hasSVEorSME())) { |
1053 | 0 | return fastEmitInst_r(AArch64::FRECPE_ZZ_H, &AArch64::ZPRRegClass, Op0); |
1054 | 0 | } |
1055 | 0 | return 0; |
1056 | 0 | } |
1057 | | |
1058 | 0 | unsigned fastEmit_AArch64ISD_FRECPE_MVT_nxv4f32_r(MVT RetVT, unsigned Op0) { |
1059 | 0 | if (RetVT.SimpleTy != MVT::nxv4f32) |
1060 | 0 | return 0; |
1061 | 0 | if ((Subtarget->hasSVEorSME())) { |
1062 | 0 | return fastEmitInst_r(AArch64::FRECPE_ZZ_S, &AArch64::ZPRRegClass, Op0); |
1063 | 0 | } |
1064 | 0 | return 0; |
1065 | 0 | } |
1066 | | |
1067 | 0 | unsigned fastEmit_AArch64ISD_FRECPE_MVT_nxv2f64_r(MVT RetVT, unsigned Op0) { |
1068 | 0 | if (RetVT.SimpleTy != MVT::nxv2f64) |
1069 | 0 | return 0; |
1070 | 0 | if ((Subtarget->hasSVEorSME())) { |
1071 | 0 | return fastEmitInst_r(AArch64::FRECPE_ZZ_D, &AArch64::ZPRRegClass, Op0); |
1072 | 0 | } |
1073 | 0 | return 0; |
1074 | 0 | } |
1075 | | |
1076 | 0 | unsigned fastEmit_AArch64ISD_FRECPE_r(MVT VT, MVT RetVT, unsigned Op0) { |
1077 | 0 | switch (VT.SimpleTy) { |
1078 | 0 | case MVT::f32: return fastEmit_AArch64ISD_FRECPE_MVT_f32_r(RetVT, Op0); |
1079 | 0 | case MVT::f64: return fastEmit_AArch64ISD_FRECPE_MVT_f64_r(RetVT, Op0); |
1080 | 0 | case MVT::v2f32: return fastEmit_AArch64ISD_FRECPE_MVT_v2f32_r(RetVT, Op0); |
1081 | 0 | case MVT::v4f32: return fastEmit_AArch64ISD_FRECPE_MVT_v4f32_r(RetVT, Op0); |
1082 | 0 | case MVT::v1f64: return fastEmit_AArch64ISD_FRECPE_MVT_v1f64_r(RetVT, Op0); |
1083 | 0 | case MVT::v2f64: return fastEmit_AArch64ISD_FRECPE_MVT_v2f64_r(RetVT, Op0); |
1084 | 0 | case MVT::nxv8f16: return fastEmit_AArch64ISD_FRECPE_MVT_nxv8f16_r(RetVT, Op0); |
1085 | 0 | case MVT::nxv4f32: return fastEmit_AArch64ISD_FRECPE_MVT_nxv4f32_r(RetVT, Op0); |
1086 | 0 | case MVT::nxv2f64: return fastEmit_AArch64ISD_FRECPE_MVT_nxv2f64_r(RetVT, Op0); |
1087 | 0 | default: return 0; |
1088 | 0 | } |
1089 | 0 | } |
1090 | | |
1091 | | // FastEmit functions for AArch64ISD::FRSQRTE. |
1092 | | |
1093 | 0 | unsigned fastEmit_AArch64ISD_FRSQRTE_MVT_f32_r(MVT RetVT, unsigned Op0) { |
1094 | 0 | if (RetVT.SimpleTy != MVT::f32) |
1095 | 0 | return 0; |
1096 | 0 | return fastEmitInst_r(AArch64::FRSQRTEv1i32, &AArch64::FPR32RegClass, Op0); |
1097 | 0 | } |
1098 | | |
1099 | 0 | unsigned fastEmit_AArch64ISD_FRSQRTE_MVT_f64_r(MVT RetVT, unsigned Op0) { |
1100 | 0 | if (RetVT.SimpleTy != MVT::f64) |
1101 | 0 | return 0; |
1102 | 0 | return fastEmitInst_r(AArch64::FRSQRTEv1i64, &AArch64::FPR64RegClass, Op0); |
1103 | 0 | } |
1104 | | |
1105 | 0 | unsigned fastEmit_AArch64ISD_FRSQRTE_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
1106 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
1107 | 0 | return 0; |
1108 | 0 | return fastEmitInst_r(AArch64::FRSQRTEv2f32, &AArch64::FPR64RegClass, Op0); |
1109 | 0 | } |
1110 | | |
1111 | 0 | unsigned fastEmit_AArch64ISD_FRSQRTE_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
1112 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
1113 | 0 | return 0; |
1114 | 0 | return fastEmitInst_r(AArch64::FRSQRTEv4f32, &AArch64::FPR128RegClass, Op0); |
1115 | 0 | } |
1116 | | |
1117 | 0 | unsigned fastEmit_AArch64ISD_FRSQRTE_MVT_v1f64_r(MVT RetVT, unsigned Op0) { |
1118 | 0 | if (RetVT.SimpleTy != MVT::v1f64) |
1119 | 0 | return 0; |
1120 | 0 | return fastEmitInst_r(AArch64::FRSQRTEv1i64, &AArch64::FPR64RegClass, Op0); |
1121 | 0 | } |
1122 | | |
1123 | 0 | unsigned fastEmit_AArch64ISD_FRSQRTE_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
1124 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
1125 | 0 | return 0; |
1126 | 0 | return fastEmitInst_r(AArch64::FRSQRTEv2f64, &AArch64::FPR128RegClass, Op0); |
1127 | 0 | } |
1128 | | |
1129 | 0 | unsigned fastEmit_AArch64ISD_FRSQRTE_MVT_nxv8f16_r(MVT RetVT, unsigned Op0) { |
1130 | 0 | if (RetVT.SimpleTy != MVT::nxv8f16) |
1131 | 0 | return 0; |
1132 | 0 | if ((Subtarget->hasSVEorSME())) { |
1133 | 0 | return fastEmitInst_r(AArch64::FRSQRTE_ZZ_H, &AArch64::ZPRRegClass, Op0); |
1134 | 0 | } |
1135 | 0 | return 0; |
1136 | 0 | } |
1137 | | |
1138 | 0 | unsigned fastEmit_AArch64ISD_FRSQRTE_MVT_nxv4f32_r(MVT RetVT, unsigned Op0) { |
1139 | 0 | if (RetVT.SimpleTy != MVT::nxv4f32) |
1140 | 0 | return 0; |
1141 | 0 | if ((Subtarget->hasSVEorSME())) { |
1142 | 0 | return fastEmitInst_r(AArch64::FRSQRTE_ZZ_S, &AArch64::ZPRRegClass, Op0); |
1143 | 0 | } |
1144 | 0 | return 0; |
1145 | 0 | } |
1146 | | |
1147 | 0 | unsigned fastEmit_AArch64ISD_FRSQRTE_MVT_nxv2f64_r(MVT RetVT, unsigned Op0) { |
1148 | 0 | if (RetVT.SimpleTy != MVT::nxv2f64) |
1149 | 0 | return 0; |
1150 | 0 | if ((Subtarget->hasSVEorSME())) { |
1151 | 0 | return fastEmitInst_r(AArch64::FRSQRTE_ZZ_D, &AArch64::ZPRRegClass, Op0); |
1152 | 0 | } |
1153 | 0 | return 0; |
1154 | 0 | } |
1155 | | |
1156 | 0 | unsigned fastEmit_AArch64ISD_FRSQRTE_r(MVT VT, MVT RetVT, unsigned Op0) { |
1157 | 0 | switch (VT.SimpleTy) { |
1158 | 0 | case MVT::f32: return fastEmit_AArch64ISD_FRSQRTE_MVT_f32_r(RetVT, Op0); |
1159 | 0 | case MVT::f64: return fastEmit_AArch64ISD_FRSQRTE_MVT_f64_r(RetVT, Op0); |
1160 | 0 | case MVT::v2f32: return fastEmit_AArch64ISD_FRSQRTE_MVT_v2f32_r(RetVT, Op0); |
1161 | 0 | case MVT::v4f32: return fastEmit_AArch64ISD_FRSQRTE_MVT_v4f32_r(RetVT, Op0); |
1162 | 0 | case MVT::v1f64: return fastEmit_AArch64ISD_FRSQRTE_MVT_v1f64_r(RetVT, Op0); |
1163 | 0 | case MVT::v2f64: return fastEmit_AArch64ISD_FRSQRTE_MVT_v2f64_r(RetVT, Op0); |
1164 | 0 | case MVT::nxv8f16: return fastEmit_AArch64ISD_FRSQRTE_MVT_nxv8f16_r(RetVT, Op0); |
1165 | 0 | case MVT::nxv4f32: return fastEmit_AArch64ISD_FRSQRTE_MVT_nxv4f32_r(RetVT, Op0); |
1166 | 0 | case MVT::nxv2f64: return fastEmit_AArch64ISD_FRSQRTE_MVT_nxv2f64_r(RetVT, Op0); |
1167 | 0 | default: return 0; |
1168 | 0 | } |
1169 | 0 | } |
1170 | | |
1171 | | // FastEmit functions for AArch64ISD::PROBED_ALLOCA. |
1172 | | |
1173 | 0 | unsigned fastEmit_AArch64ISD_PROBED_ALLOCA_MVT_i64_r(MVT RetVT, unsigned Op0) { |
1174 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
1175 | 0 | return 0; |
1176 | 0 | return fastEmitInst_r(AArch64::PROBED_STACKALLOC_DYN, &AArch64::GPR64commonRegClass, Op0); |
1177 | 0 | } |
1178 | | |
1179 | 0 | unsigned fastEmit_AArch64ISD_PROBED_ALLOCA_r(MVT VT, MVT RetVT, unsigned Op0) { |
1180 | 0 | switch (VT.SimpleTy) { |
1181 | 0 | case MVT::i64: return fastEmit_AArch64ISD_PROBED_ALLOCA_MVT_i64_r(RetVT, Op0); |
1182 | 0 | default: return 0; |
1183 | 0 | } |
1184 | 0 | } |
1185 | | |
1186 | | // FastEmit functions for AArch64ISD::REV16. |
1187 | | |
1188 | 0 | unsigned fastEmit_AArch64ISD_REV16_MVT_v8i8_r(MVT RetVT, unsigned Op0) { |
1189 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
1190 | 0 | return 0; |
1191 | 0 | if ((Subtarget->hasNEON())) { |
1192 | 0 | return fastEmitInst_r(AArch64::REV16v8i8, &AArch64::FPR64RegClass, Op0); |
1193 | 0 | } |
1194 | 0 | return 0; |
1195 | 0 | } |
1196 | | |
1197 | 0 | unsigned fastEmit_AArch64ISD_REV16_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
1198 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
1199 | 0 | return 0; |
1200 | 0 | if ((Subtarget->hasNEON())) { |
1201 | 0 | return fastEmitInst_r(AArch64::REV16v16i8, &AArch64::FPR128RegClass, Op0); |
1202 | 0 | } |
1203 | 0 | return 0; |
1204 | 0 | } |
1205 | | |
1206 | 0 | unsigned fastEmit_AArch64ISD_REV16_r(MVT VT, MVT RetVT, unsigned Op0) { |
1207 | 0 | switch (VT.SimpleTy) { |
1208 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_REV16_MVT_v8i8_r(RetVT, Op0); |
1209 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_REV16_MVT_v16i8_r(RetVT, Op0); |
1210 | 0 | default: return 0; |
1211 | 0 | } |
1212 | 0 | } |
1213 | | |
1214 | | // FastEmit functions for AArch64ISD::REV32. |
1215 | | |
1216 | 0 | unsigned fastEmit_AArch64ISD_REV32_MVT_v8i8_r(MVT RetVT, unsigned Op0) { |
1217 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
1218 | 0 | return 0; |
1219 | 0 | if ((Subtarget->hasNEON())) { |
1220 | 0 | return fastEmitInst_r(AArch64::REV32v8i8, &AArch64::FPR64RegClass, Op0); |
1221 | 0 | } |
1222 | 0 | return 0; |
1223 | 0 | } |
1224 | | |
1225 | 0 | unsigned fastEmit_AArch64ISD_REV32_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
1226 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
1227 | 0 | return 0; |
1228 | 0 | if ((Subtarget->hasNEON())) { |
1229 | 0 | return fastEmitInst_r(AArch64::REV32v16i8, &AArch64::FPR128RegClass, Op0); |
1230 | 0 | } |
1231 | 0 | return 0; |
1232 | 0 | } |
1233 | | |
1234 | 0 | unsigned fastEmit_AArch64ISD_REV32_MVT_v4i16_r(MVT RetVT, unsigned Op0) { |
1235 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
1236 | 0 | return 0; |
1237 | 0 | if ((Subtarget->hasNEON())) { |
1238 | 0 | return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0); |
1239 | 0 | } |
1240 | 0 | return 0; |
1241 | 0 | } |
1242 | | |
1243 | 0 | unsigned fastEmit_AArch64ISD_REV32_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
1244 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
1245 | 0 | return 0; |
1246 | 0 | if ((Subtarget->hasNEON())) { |
1247 | 0 | return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0); |
1248 | 0 | } |
1249 | 0 | return 0; |
1250 | 0 | } |
1251 | | |
1252 | 0 | unsigned fastEmit_AArch64ISD_REV32_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
1253 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
1254 | 0 | return 0; |
1255 | 0 | return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0); |
1256 | 0 | } |
1257 | | |
1258 | 0 | unsigned fastEmit_AArch64ISD_REV32_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
1259 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
1260 | 0 | return 0; |
1261 | 0 | return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0); |
1262 | 0 | } |
1263 | | |
1264 | 0 | unsigned fastEmit_AArch64ISD_REV32_MVT_v4bf16_r(MVT RetVT, unsigned Op0) { |
1265 | 0 | if (RetVT.SimpleTy != MVT::v4bf16) |
1266 | 0 | return 0; |
1267 | 0 | return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0); |
1268 | 0 | } |
1269 | | |
1270 | 0 | unsigned fastEmit_AArch64ISD_REV32_MVT_v8bf16_r(MVT RetVT, unsigned Op0) { |
1271 | 0 | if (RetVT.SimpleTy != MVT::v8bf16) |
1272 | 0 | return 0; |
1273 | 0 | return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0); |
1274 | 0 | } |
1275 | | |
1276 | 0 | unsigned fastEmit_AArch64ISD_REV32_r(MVT VT, MVT RetVT, unsigned Op0) { |
1277 | 0 | switch (VT.SimpleTy) { |
1278 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_REV32_MVT_v8i8_r(RetVT, Op0); |
1279 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_REV32_MVT_v16i8_r(RetVT, Op0); |
1280 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_REV32_MVT_v4i16_r(RetVT, Op0); |
1281 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_REV32_MVT_v8i16_r(RetVT, Op0); |
1282 | 0 | case MVT::v4f16: return fastEmit_AArch64ISD_REV32_MVT_v4f16_r(RetVT, Op0); |
1283 | 0 | case MVT::v8f16: return fastEmit_AArch64ISD_REV32_MVT_v8f16_r(RetVT, Op0); |
1284 | 0 | case MVT::v4bf16: return fastEmit_AArch64ISD_REV32_MVT_v4bf16_r(RetVT, Op0); |
1285 | 0 | case MVT::v8bf16: return fastEmit_AArch64ISD_REV32_MVT_v8bf16_r(RetVT, Op0); |
1286 | 0 | default: return 0; |
1287 | 0 | } |
1288 | 0 | } |
1289 | | |
1290 | | // FastEmit functions for AArch64ISD::REV64. |
1291 | | |
1292 | 0 | unsigned fastEmit_AArch64ISD_REV64_MVT_v8i8_r(MVT RetVT, unsigned Op0) { |
1293 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
1294 | 0 | return 0; |
1295 | 0 | if ((Subtarget->hasNEON())) { |
1296 | 0 | return fastEmitInst_r(AArch64::REV64v8i8, &AArch64::FPR64RegClass, Op0); |
1297 | 0 | } |
1298 | 0 | return 0; |
1299 | 0 | } |
1300 | | |
1301 | 0 | unsigned fastEmit_AArch64ISD_REV64_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
1302 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
1303 | 0 | return 0; |
1304 | 0 | if ((Subtarget->hasNEON())) { |
1305 | 0 | return fastEmitInst_r(AArch64::REV64v16i8, &AArch64::FPR128RegClass, Op0); |
1306 | 0 | } |
1307 | 0 | return 0; |
1308 | 0 | } |
1309 | | |
1310 | 0 | unsigned fastEmit_AArch64ISD_REV64_MVT_v4i16_r(MVT RetVT, unsigned Op0) { |
1311 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
1312 | 0 | return 0; |
1313 | 0 | if ((Subtarget->hasNEON())) { |
1314 | 0 | return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0); |
1315 | 0 | } |
1316 | 0 | return 0; |
1317 | 0 | } |
1318 | | |
1319 | 0 | unsigned fastEmit_AArch64ISD_REV64_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
1320 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
1321 | 0 | return 0; |
1322 | 0 | if ((Subtarget->hasNEON())) { |
1323 | 0 | return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0); |
1324 | 0 | } |
1325 | 0 | return 0; |
1326 | 0 | } |
1327 | | |
1328 | 0 | unsigned fastEmit_AArch64ISD_REV64_MVT_v2i32_r(MVT RetVT, unsigned Op0) { |
1329 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
1330 | 0 | return 0; |
1331 | 0 | if ((Subtarget->hasNEON())) { |
1332 | 0 | return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0); |
1333 | 0 | } |
1334 | 0 | return 0; |
1335 | 0 | } |
1336 | | |
1337 | 0 | unsigned fastEmit_AArch64ISD_REV64_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
1338 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
1339 | 0 | return 0; |
1340 | 0 | if ((Subtarget->hasNEON())) { |
1341 | 0 | return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0); |
1342 | 0 | } |
1343 | 0 | return 0; |
1344 | 0 | } |
1345 | | |
1346 | 0 | unsigned fastEmit_AArch64ISD_REV64_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
1347 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
1348 | 0 | return 0; |
1349 | 0 | return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0); |
1350 | 0 | } |
1351 | | |
1352 | 0 | unsigned fastEmit_AArch64ISD_REV64_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
1353 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
1354 | 0 | return 0; |
1355 | 0 | return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0); |
1356 | 0 | } |
1357 | | |
1358 | 0 | unsigned fastEmit_AArch64ISD_REV64_MVT_v4bf16_r(MVT RetVT, unsigned Op0) { |
1359 | 0 | if (RetVT.SimpleTy != MVT::v4bf16) |
1360 | 0 | return 0; |
1361 | 0 | return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0); |
1362 | 0 | } |
1363 | | |
1364 | 0 | unsigned fastEmit_AArch64ISD_REV64_MVT_v8bf16_r(MVT RetVT, unsigned Op0) { |
1365 | 0 | if (RetVT.SimpleTy != MVT::v8bf16) |
1366 | 0 | return 0; |
1367 | 0 | return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0); |
1368 | 0 | } |
1369 | | |
1370 | 0 | unsigned fastEmit_AArch64ISD_REV64_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
1371 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
1372 | 0 | return 0; |
1373 | 0 | return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0); |
1374 | 0 | } |
1375 | | |
1376 | 0 | unsigned fastEmit_AArch64ISD_REV64_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
1377 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
1378 | 0 | return 0; |
1379 | 0 | return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0); |
1380 | 0 | } |
1381 | | |
1382 | 0 | unsigned fastEmit_AArch64ISD_REV64_r(MVT VT, MVT RetVT, unsigned Op0) { |
1383 | 0 | switch (VT.SimpleTy) { |
1384 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_REV64_MVT_v8i8_r(RetVT, Op0); |
1385 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_REV64_MVT_v16i8_r(RetVT, Op0); |
1386 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_REV64_MVT_v4i16_r(RetVT, Op0); |
1387 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_REV64_MVT_v8i16_r(RetVT, Op0); |
1388 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_REV64_MVT_v2i32_r(RetVT, Op0); |
1389 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_REV64_MVT_v4i32_r(RetVT, Op0); |
1390 | 0 | case MVT::v4f16: return fastEmit_AArch64ISD_REV64_MVT_v4f16_r(RetVT, Op0); |
1391 | 0 | case MVT::v8f16: return fastEmit_AArch64ISD_REV64_MVT_v8f16_r(RetVT, Op0); |
1392 | 0 | case MVT::v4bf16: return fastEmit_AArch64ISD_REV64_MVT_v4bf16_r(RetVT, Op0); |
1393 | 0 | case MVT::v8bf16: return fastEmit_AArch64ISD_REV64_MVT_v8bf16_r(RetVT, Op0); |
1394 | 0 | case MVT::v2f32: return fastEmit_AArch64ISD_REV64_MVT_v2f32_r(RetVT, Op0); |
1395 | 0 | case MVT::v4f32: return fastEmit_AArch64ISD_REV64_MVT_v4f32_r(RetVT, Op0); |
1396 | 0 | default: return 0; |
1397 | 0 | } |
1398 | 0 | } |
1399 | | |
1400 | | // FastEmit functions for AArch64ISD::SADDLP. |
1401 | | |
1402 | 0 | unsigned fastEmit_AArch64ISD_SADDLP_MVT_v8i8_r(MVT RetVT, unsigned Op0) { |
1403 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
1404 | 0 | return 0; |
1405 | 0 | if ((Subtarget->hasNEON())) { |
1406 | 0 | return fastEmitInst_r(AArch64::SADDLPv8i8_v4i16, &AArch64::FPR64RegClass, Op0); |
1407 | 0 | } |
1408 | 0 | return 0; |
1409 | 0 | } |
1410 | | |
1411 | 0 | unsigned fastEmit_AArch64ISD_SADDLP_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
1412 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
1413 | 0 | return 0; |
1414 | 0 | if ((Subtarget->hasNEON())) { |
1415 | 0 | return fastEmitInst_r(AArch64::SADDLPv16i8_v8i16, &AArch64::FPR128RegClass, Op0); |
1416 | 0 | } |
1417 | 0 | return 0; |
1418 | 0 | } |
1419 | | |
1420 | 0 | unsigned fastEmit_AArch64ISD_SADDLP_MVT_v4i16_r(MVT RetVT, unsigned Op0) { |
1421 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
1422 | 0 | return 0; |
1423 | 0 | if ((Subtarget->hasNEON())) { |
1424 | 0 | return fastEmitInst_r(AArch64::SADDLPv4i16_v2i32, &AArch64::FPR64RegClass, Op0); |
1425 | 0 | } |
1426 | 0 | return 0; |
1427 | 0 | } |
1428 | | |
1429 | 0 | unsigned fastEmit_AArch64ISD_SADDLP_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
1430 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
1431 | 0 | return 0; |
1432 | 0 | if ((Subtarget->hasNEON())) { |
1433 | 0 | return fastEmitInst_r(AArch64::SADDLPv8i16_v4i32, &AArch64::FPR128RegClass, Op0); |
1434 | 0 | } |
1435 | 0 | return 0; |
1436 | 0 | } |
1437 | | |
1438 | 0 | unsigned fastEmit_AArch64ISD_SADDLP_MVT_v2i32_r(MVT RetVT, unsigned Op0) { |
1439 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
1440 | 0 | return 0; |
1441 | 0 | if ((Subtarget->hasNEON())) { |
1442 | 0 | return fastEmitInst_r(AArch64::SADDLPv2i32_v1i64, &AArch64::FPR64RegClass, Op0); |
1443 | 0 | } |
1444 | 0 | return 0; |
1445 | 0 | } |
1446 | | |
1447 | 0 | unsigned fastEmit_AArch64ISD_SADDLP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
1448 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
1449 | 0 | return 0; |
1450 | 0 | if ((Subtarget->hasNEON())) { |
1451 | 0 | return fastEmitInst_r(AArch64::SADDLPv4i32_v2i64, &AArch64::FPR128RegClass, Op0); |
1452 | 0 | } |
1453 | 0 | return 0; |
1454 | 0 | } |
1455 | | |
1456 | 0 | unsigned fastEmit_AArch64ISD_SADDLP_r(MVT VT, MVT RetVT, unsigned Op0) { |
1457 | 0 | switch (VT.SimpleTy) { |
1458 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_SADDLP_MVT_v8i8_r(RetVT, Op0); |
1459 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_SADDLP_MVT_v16i8_r(RetVT, Op0); |
1460 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_SADDLP_MVT_v4i16_r(RetVT, Op0); |
1461 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_SADDLP_MVT_v8i16_r(RetVT, Op0); |
1462 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_SADDLP_MVT_v2i32_r(RetVT, Op0); |
1463 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_SADDLP_MVT_v4i32_r(RetVT, Op0); |
1464 | 0 | default: return 0; |
1465 | 0 | } |
1466 | 0 | } |
1467 | | |
1468 | | // FastEmit functions for AArch64ISD::SITOF. |
1469 | | |
1470 | 0 | unsigned fastEmit_AArch64ISD_SITOF_MVT_f16_r(MVT RetVT, unsigned Op0) { |
1471 | 0 | if (RetVT.SimpleTy != MVT::f16) |
1472 | 0 | return 0; |
1473 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
1474 | 0 | return fastEmitInst_r(AArch64::SCVTFv1i16, &AArch64::FPR16RegClass, Op0); |
1475 | 0 | } |
1476 | 0 | return 0; |
1477 | 0 | } |
1478 | | |
1479 | 0 | unsigned fastEmit_AArch64ISD_SITOF_MVT_f32_r(MVT RetVT, unsigned Op0) { |
1480 | 0 | if (RetVT.SimpleTy != MVT::f32) |
1481 | 0 | return 0; |
1482 | 0 | if ((Subtarget->hasNEON())) { |
1483 | 0 | return fastEmitInst_r(AArch64::SCVTFv1i32, &AArch64::FPR32RegClass, Op0); |
1484 | 0 | } |
1485 | 0 | return 0; |
1486 | 0 | } |
1487 | | |
1488 | 0 | unsigned fastEmit_AArch64ISD_SITOF_MVT_f64_r(MVT RetVT, unsigned Op0) { |
1489 | 0 | if (RetVT.SimpleTy != MVT::f64) |
1490 | 0 | return 0; |
1491 | 0 | if ((Subtarget->hasNEON())) { |
1492 | 0 | return fastEmitInst_r(AArch64::SCVTFv1i64, &AArch64::FPR64RegClass, Op0); |
1493 | 0 | } |
1494 | 0 | return 0; |
1495 | 0 | } |
1496 | | |
1497 | 0 | unsigned fastEmit_AArch64ISD_SITOF_r(MVT VT, MVT RetVT, unsigned Op0) { |
1498 | 0 | switch (VT.SimpleTy) { |
1499 | 0 | case MVT::f16: return fastEmit_AArch64ISD_SITOF_MVT_f16_r(RetVT, Op0); |
1500 | 0 | case MVT::f32: return fastEmit_AArch64ISD_SITOF_MVT_f32_r(RetVT, Op0); |
1501 | 0 | case MVT::f64: return fastEmit_AArch64ISD_SITOF_MVT_f64_r(RetVT, Op0); |
1502 | 0 | default: return 0; |
1503 | 0 | } |
1504 | 0 | } |
1505 | | |
1506 | | // FastEmit functions for AArch64ISD::SUNPKHI. |
1507 | | |
1508 | 0 | unsigned fastEmit_AArch64ISD_SUNPKHI_MVT_nxv16i8_r(MVT RetVT, unsigned Op0) { |
1509 | 0 | if (RetVT.SimpleTy != MVT::nxv8i16) |
1510 | 0 | return 0; |
1511 | 0 | if ((Subtarget->hasSVEorSME())) { |
1512 | 0 | return fastEmitInst_r(AArch64::SUNPKHI_ZZ_H, &AArch64::ZPRRegClass, Op0); |
1513 | 0 | } |
1514 | 0 | return 0; |
1515 | 0 | } |
1516 | | |
1517 | 0 | unsigned fastEmit_AArch64ISD_SUNPKHI_MVT_nxv8i16_r(MVT RetVT, unsigned Op0) { |
1518 | 0 | if (RetVT.SimpleTy != MVT::nxv4i32) |
1519 | 0 | return 0; |
1520 | 0 | if ((Subtarget->hasSVEorSME())) { |
1521 | 0 | return fastEmitInst_r(AArch64::SUNPKHI_ZZ_S, &AArch64::ZPRRegClass, Op0); |
1522 | 0 | } |
1523 | 0 | return 0; |
1524 | 0 | } |
1525 | | |
1526 | 0 | unsigned fastEmit_AArch64ISD_SUNPKHI_MVT_nxv4i32_r(MVT RetVT, unsigned Op0) { |
1527 | 0 | if (RetVT.SimpleTy != MVT::nxv2i64) |
1528 | 0 | return 0; |
1529 | 0 | if ((Subtarget->hasSVEorSME())) { |
1530 | 0 | return fastEmitInst_r(AArch64::SUNPKHI_ZZ_D, &AArch64::ZPRRegClass, Op0); |
1531 | 0 | } |
1532 | 0 | return 0; |
1533 | 0 | } |
1534 | | |
1535 | 0 | unsigned fastEmit_AArch64ISD_SUNPKHI_r(MVT VT, MVT RetVT, unsigned Op0) { |
1536 | 0 | switch (VT.SimpleTy) { |
1537 | 0 | case MVT::nxv16i8: return fastEmit_AArch64ISD_SUNPKHI_MVT_nxv16i8_r(RetVT, Op0); |
1538 | 0 | case MVT::nxv8i16: return fastEmit_AArch64ISD_SUNPKHI_MVT_nxv8i16_r(RetVT, Op0); |
1539 | 0 | case MVT::nxv4i32: return fastEmit_AArch64ISD_SUNPKHI_MVT_nxv4i32_r(RetVT, Op0); |
1540 | 0 | default: return 0; |
1541 | 0 | } |
1542 | 0 | } |
1543 | | |
1544 | | // FastEmit functions for AArch64ISD::SUNPKLO. |
1545 | | |
1546 | 0 | unsigned fastEmit_AArch64ISD_SUNPKLO_MVT_nxv16i8_r(MVT RetVT, unsigned Op0) { |
1547 | 0 | if (RetVT.SimpleTy != MVT::nxv8i16) |
1548 | 0 | return 0; |
1549 | 0 | if ((Subtarget->hasSVEorSME())) { |
1550 | 0 | return fastEmitInst_r(AArch64::SUNPKLO_ZZ_H, &AArch64::ZPRRegClass, Op0); |
1551 | 0 | } |
1552 | 0 | return 0; |
1553 | 0 | } |
1554 | | |
1555 | 0 | unsigned fastEmit_AArch64ISD_SUNPKLO_MVT_nxv8i16_r(MVT RetVT, unsigned Op0) { |
1556 | 0 | if (RetVT.SimpleTy != MVT::nxv4i32) |
1557 | 0 | return 0; |
1558 | 0 | if ((Subtarget->hasSVEorSME())) { |
1559 | 0 | return fastEmitInst_r(AArch64::SUNPKLO_ZZ_S, &AArch64::ZPRRegClass, Op0); |
1560 | 0 | } |
1561 | 0 | return 0; |
1562 | 0 | } |
1563 | | |
1564 | 0 | unsigned fastEmit_AArch64ISD_SUNPKLO_MVT_nxv4i32_r(MVT RetVT, unsigned Op0) { |
1565 | 0 | if (RetVT.SimpleTy != MVT::nxv2i64) |
1566 | 0 | return 0; |
1567 | 0 | if ((Subtarget->hasSVEorSME())) { |
1568 | 0 | return fastEmitInst_r(AArch64::SUNPKLO_ZZ_D, &AArch64::ZPRRegClass, Op0); |
1569 | 0 | } |
1570 | 0 | return 0; |
1571 | 0 | } |
1572 | | |
1573 | 0 | unsigned fastEmit_AArch64ISD_SUNPKLO_r(MVT VT, MVT RetVT, unsigned Op0) { |
1574 | 0 | switch (VT.SimpleTy) { |
1575 | 0 | case MVT::nxv16i8: return fastEmit_AArch64ISD_SUNPKLO_MVT_nxv16i8_r(RetVT, Op0); |
1576 | 0 | case MVT::nxv8i16: return fastEmit_AArch64ISD_SUNPKLO_MVT_nxv8i16_r(RetVT, Op0); |
1577 | 0 | case MVT::nxv4i32: return fastEmit_AArch64ISD_SUNPKLO_MVT_nxv4i32_r(RetVT, Op0); |
1578 | 0 | default: return 0; |
1579 | 0 | } |
1580 | 0 | } |
1581 | | |
1582 | | // FastEmit functions for AArch64ISD::UADDLP. |
1583 | | |
1584 | 0 | unsigned fastEmit_AArch64ISD_UADDLP_MVT_v8i8_r(MVT RetVT, unsigned Op0) { |
1585 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
1586 | 0 | return 0; |
1587 | 0 | if ((Subtarget->hasNEON())) { |
1588 | 0 | return fastEmitInst_r(AArch64::UADDLPv8i8_v4i16, &AArch64::FPR64RegClass, Op0); |
1589 | 0 | } |
1590 | 0 | return 0; |
1591 | 0 | } |
1592 | | |
1593 | 0 | unsigned fastEmit_AArch64ISD_UADDLP_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
1594 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
1595 | 0 | return 0; |
1596 | 0 | if ((Subtarget->hasNEON())) { |
1597 | 0 | return fastEmitInst_r(AArch64::UADDLPv16i8_v8i16, &AArch64::FPR128RegClass, Op0); |
1598 | 0 | } |
1599 | 0 | return 0; |
1600 | 0 | } |
1601 | | |
1602 | 0 | unsigned fastEmit_AArch64ISD_UADDLP_MVT_v4i16_r(MVT RetVT, unsigned Op0) { |
1603 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
1604 | 0 | return 0; |
1605 | 0 | if ((Subtarget->hasNEON())) { |
1606 | 0 | return fastEmitInst_r(AArch64::UADDLPv4i16_v2i32, &AArch64::FPR64RegClass, Op0); |
1607 | 0 | } |
1608 | 0 | return 0; |
1609 | 0 | } |
1610 | | |
1611 | 0 | unsigned fastEmit_AArch64ISD_UADDLP_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
1612 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
1613 | 0 | return 0; |
1614 | 0 | if ((Subtarget->hasNEON())) { |
1615 | 0 | return fastEmitInst_r(AArch64::UADDLPv8i16_v4i32, &AArch64::FPR128RegClass, Op0); |
1616 | 0 | } |
1617 | 0 | return 0; |
1618 | 0 | } |
1619 | | |
1620 | 0 | unsigned fastEmit_AArch64ISD_UADDLP_MVT_v2i32_r(MVT RetVT, unsigned Op0) { |
1621 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
1622 | 0 | return 0; |
1623 | 0 | if ((Subtarget->hasNEON())) { |
1624 | 0 | return fastEmitInst_r(AArch64::UADDLPv2i32_v1i64, &AArch64::FPR64RegClass, Op0); |
1625 | 0 | } |
1626 | 0 | return 0; |
1627 | 0 | } |
1628 | | |
1629 | 0 | unsigned fastEmit_AArch64ISD_UADDLP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
1630 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
1631 | 0 | return 0; |
1632 | 0 | if ((Subtarget->hasNEON())) { |
1633 | 0 | return fastEmitInst_r(AArch64::UADDLPv4i32_v2i64, &AArch64::FPR128RegClass, Op0); |
1634 | 0 | } |
1635 | 0 | return 0; |
1636 | 0 | } |
1637 | | |
1638 | 0 | unsigned fastEmit_AArch64ISD_UADDLP_r(MVT VT, MVT RetVT, unsigned Op0) { |
1639 | 0 | switch (VT.SimpleTy) { |
1640 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_UADDLP_MVT_v8i8_r(RetVT, Op0); |
1641 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_UADDLP_MVT_v16i8_r(RetVT, Op0); |
1642 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_UADDLP_MVT_v4i16_r(RetVT, Op0); |
1643 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_UADDLP_MVT_v8i16_r(RetVT, Op0); |
1644 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_UADDLP_MVT_v2i32_r(RetVT, Op0); |
1645 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_UADDLP_MVT_v4i32_r(RetVT, Op0); |
1646 | 0 | default: return 0; |
1647 | 0 | } |
1648 | 0 | } |
1649 | | |
1650 | | // FastEmit functions for AArch64ISD::UITOF. |
1651 | | |
1652 | 0 | unsigned fastEmit_AArch64ISD_UITOF_MVT_f16_r(MVT RetVT, unsigned Op0) { |
1653 | 0 | if (RetVT.SimpleTy != MVT::f16) |
1654 | 0 | return 0; |
1655 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
1656 | 0 | return fastEmitInst_r(AArch64::UCVTFv1i16, &AArch64::FPR16RegClass, Op0); |
1657 | 0 | } |
1658 | 0 | return 0; |
1659 | 0 | } |
1660 | | |
1661 | 0 | unsigned fastEmit_AArch64ISD_UITOF_MVT_f32_r(MVT RetVT, unsigned Op0) { |
1662 | 0 | if (RetVT.SimpleTy != MVT::f32) |
1663 | 0 | return 0; |
1664 | 0 | if ((Subtarget->hasNEON())) { |
1665 | 0 | return fastEmitInst_r(AArch64::UCVTFv1i32, &AArch64::FPR32RegClass, Op0); |
1666 | 0 | } |
1667 | 0 | return 0; |
1668 | 0 | } |
1669 | | |
1670 | 0 | unsigned fastEmit_AArch64ISD_UITOF_MVT_f64_r(MVT RetVT, unsigned Op0) { |
1671 | 0 | if (RetVT.SimpleTy != MVT::f64) |
1672 | 0 | return 0; |
1673 | 0 | if ((Subtarget->hasNEON())) { |
1674 | 0 | return fastEmitInst_r(AArch64::UCVTFv1i64, &AArch64::FPR64RegClass, Op0); |
1675 | 0 | } |
1676 | 0 | return 0; |
1677 | 0 | } |
1678 | | |
1679 | 0 | unsigned fastEmit_AArch64ISD_UITOF_r(MVT VT, MVT RetVT, unsigned Op0) { |
1680 | 0 | switch (VT.SimpleTy) { |
1681 | 0 | case MVT::f16: return fastEmit_AArch64ISD_UITOF_MVT_f16_r(RetVT, Op0); |
1682 | 0 | case MVT::f32: return fastEmit_AArch64ISD_UITOF_MVT_f32_r(RetVT, Op0); |
1683 | 0 | case MVT::f64: return fastEmit_AArch64ISD_UITOF_MVT_f64_r(RetVT, Op0); |
1684 | 0 | default: return 0; |
1685 | 0 | } |
1686 | 0 | } |
1687 | | |
1688 | | // FastEmit functions for AArch64ISD::UUNPKHI. |
1689 | | |
1690 | 0 | unsigned fastEmit_AArch64ISD_UUNPKHI_MVT_nxv16i8_r(MVT RetVT, unsigned Op0) { |
1691 | 0 | if (RetVT.SimpleTy != MVT::nxv8i16) |
1692 | 0 | return 0; |
1693 | 0 | if ((Subtarget->hasSVEorSME())) { |
1694 | 0 | return fastEmitInst_r(AArch64::UUNPKHI_ZZ_H, &AArch64::ZPRRegClass, Op0); |
1695 | 0 | } |
1696 | 0 | return 0; |
1697 | 0 | } |
1698 | | |
1699 | 0 | unsigned fastEmit_AArch64ISD_UUNPKHI_MVT_nxv8i16_r(MVT RetVT, unsigned Op0) { |
1700 | 0 | if (RetVT.SimpleTy != MVT::nxv4i32) |
1701 | 0 | return 0; |
1702 | 0 | if ((Subtarget->hasSVEorSME())) { |
1703 | 0 | return fastEmitInst_r(AArch64::UUNPKHI_ZZ_S, &AArch64::ZPRRegClass, Op0); |
1704 | 0 | } |
1705 | 0 | return 0; |
1706 | 0 | } |
1707 | | |
1708 | 0 | unsigned fastEmit_AArch64ISD_UUNPKHI_MVT_nxv4i32_r(MVT RetVT, unsigned Op0) { |
1709 | 0 | if (RetVT.SimpleTy != MVT::nxv2i64) |
1710 | 0 | return 0; |
1711 | 0 | if ((Subtarget->hasSVEorSME())) { |
1712 | 0 | return fastEmitInst_r(AArch64::UUNPKHI_ZZ_D, &AArch64::ZPRRegClass, Op0); |
1713 | 0 | } |
1714 | 0 | return 0; |
1715 | 0 | } |
1716 | | |
1717 | 0 | unsigned fastEmit_AArch64ISD_UUNPKHI_r(MVT VT, MVT RetVT, unsigned Op0) { |
1718 | 0 | switch (VT.SimpleTy) { |
1719 | 0 | case MVT::nxv16i8: return fastEmit_AArch64ISD_UUNPKHI_MVT_nxv16i8_r(RetVT, Op0); |
1720 | 0 | case MVT::nxv8i16: return fastEmit_AArch64ISD_UUNPKHI_MVT_nxv8i16_r(RetVT, Op0); |
1721 | 0 | case MVT::nxv4i32: return fastEmit_AArch64ISD_UUNPKHI_MVT_nxv4i32_r(RetVT, Op0); |
1722 | 0 | default: return 0; |
1723 | 0 | } |
1724 | 0 | } |
1725 | | |
1726 | | // FastEmit functions for AArch64ISD::UUNPKLO. |
1727 | | |
1728 | 0 | unsigned fastEmit_AArch64ISD_UUNPKLO_MVT_nxv16i8_r(MVT RetVT, unsigned Op0) { |
1729 | 0 | if (RetVT.SimpleTy != MVT::nxv8i16) |
1730 | 0 | return 0; |
1731 | 0 | if ((Subtarget->hasSVEorSME())) { |
1732 | 0 | return fastEmitInst_r(AArch64::UUNPKLO_ZZ_H, &AArch64::ZPRRegClass, Op0); |
1733 | 0 | } |
1734 | 0 | return 0; |
1735 | 0 | } |
1736 | | |
1737 | 0 | unsigned fastEmit_AArch64ISD_UUNPKLO_MVT_nxv8i16_r(MVT RetVT, unsigned Op0) { |
1738 | 0 | if (RetVT.SimpleTy != MVT::nxv4i32) |
1739 | 0 | return 0; |
1740 | 0 | if ((Subtarget->hasSVEorSME())) { |
1741 | 0 | return fastEmitInst_r(AArch64::UUNPKLO_ZZ_S, &AArch64::ZPRRegClass, Op0); |
1742 | 0 | } |
1743 | 0 | return 0; |
1744 | 0 | } |
1745 | | |
1746 | 0 | unsigned fastEmit_AArch64ISD_UUNPKLO_MVT_nxv4i32_r(MVT RetVT, unsigned Op0) { |
1747 | 0 | if (RetVT.SimpleTy != MVT::nxv2i64) |
1748 | 0 | return 0; |
1749 | 0 | if ((Subtarget->hasSVEorSME())) { |
1750 | 0 | return fastEmitInst_r(AArch64::UUNPKLO_ZZ_D, &AArch64::ZPRRegClass, Op0); |
1751 | 0 | } |
1752 | 0 | return 0; |
1753 | 0 | } |
1754 | | |
1755 | 0 | unsigned fastEmit_AArch64ISD_UUNPKLO_r(MVT VT, MVT RetVT, unsigned Op0) { |
1756 | 0 | switch (VT.SimpleTy) { |
1757 | 0 | case MVT::nxv16i8: return fastEmit_AArch64ISD_UUNPKLO_MVT_nxv16i8_r(RetVT, Op0); |
1758 | 0 | case MVT::nxv8i16: return fastEmit_AArch64ISD_UUNPKLO_MVT_nxv8i16_r(RetVT, Op0); |
1759 | 0 | case MVT::nxv4i32: return fastEmit_AArch64ISD_UUNPKLO_MVT_nxv4i32_r(RetVT, Op0); |
1760 | 0 | default: return 0; |
1761 | 0 | } |
1762 | 0 | } |
1763 | | |
1764 | | // FastEmit functions for ISD::ABS. |
1765 | | |
1766 | 0 | unsigned fastEmit_ISD_ABS_MVT_i32_r(MVT RetVT, unsigned Op0) { |
1767 | 0 | if (RetVT.SimpleTy != MVT::i32) |
1768 | 0 | return 0; |
1769 | 0 | if ((Subtarget->hasCSSC())) { |
1770 | 0 | return fastEmitInst_r(AArch64::ABSWr, &AArch64::GPR32RegClass, Op0); |
1771 | 0 | } |
1772 | 0 | return 0; |
1773 | 0 | } |
1774 | | |
1775 | 0 | unsigned fastEmit_ISD_ABS_MVT_i64_r(MVT RetVT, unsigned Op0) { |
1776 | 0 | if (RetVT.SimpleTy != MVT::i64) |
1777 | 0 | return 0; |
1778 | 0 | if ((!Subtarget->hasCSSC())) { |
1779 | 0 | return fastEmitInst_r(AArch64::ABSv1i64, &AArch64::FPR64RegClass, Op0); |
1780 | 0 | } |
1781 | 0 | if ((Subtarget->hasCSSC())) { |
1782 | 0 | return fastEmitInst_r(AArch64::ABSXr, &AArch64::GPR64RegClass, Op0); |
1783 | 0 | } |
1784 | 0 | return 0; |
1785 | 0 | } |
1786 | | |
1787 | 0 | unsigned fastEmit_ISD_ABS_MVT_v8i8_r(MVT RetVT, unsigned Op0) { |
1788 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
1789 | 0 | return 0; |
1790 | 0 | if ((Subtarget->hasNEON())) { |
1791 | 0 | return fastEmitInst_r(AArch64::ABSv8i8, &AArch64::FPR64RegClass, Op0); |
1792 | 0 | } |
1793 | 0 | return 0; |
1794 | 0 | } |
1795 | | |
1796 | 0 | unsigned fastEmit_ISD_ABS_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
1797 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
1798 | 0 | return 0; |
1799 | 0 | if ((Subtarget->hasNEON())) { |
1800 | 0 | return fastEmitInst_r(AArch64::ABSv16i8, &AArch64::FPR128RegClass, Op0); |
1801 | 0 | } |
1802 | 0 | return 0; |
1803 | 0 | } |
1804 | | |
1805 | 0 | unsigned fastEmit_ISD_ABS_MVT_v4i16_r(MVT RetVT, unsigned Op0) { |
1806 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
1807 | 0 | return 0; |
1808 | 0 | if ((Subtarget->hasNEON())) { |
1809 | 0 | return fastEmitInst_r(AArch64::ABSv4i16, &AArch64::FPR64RegClass, Op0); |
1810 | 0 | } |
1811 | 0 | return 0; |
1812 | 0 | } |
1813 | | |
1814 | 0 | unsigned fastEmit_ISD_ABS_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
1815 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
1816 | 0 | return 0; |
1817 | 0 | if ((Subtarget->hasNEON())) { |
1818 | 0 | return fastEmitInst_r(AArch64::ABSv8i16, &AArch64::FPR128RegClass, Op0); |
1819 | 0 | } |
1820 | 0 | return 0; |
1821 | 0 | } |
1822 | | |
1823 | 0 | unsigned fastEmit_ISD_ABS_MVT_v2i32_r(MVT RetVT, unsigned Op0) { |
1824 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
1825 | 0 | return 0; |
1826 | 0 | if ((Subtarget->hasNEON())) { |
1827 | 0 | return fastEmitInst_r(AArch64::ABSv2i32, &AArch64::FPR64RegClass, Op0); |
1828 | 0 | } |
1829 | 0 | return 0; |
1830 | 0 | } |
1831 | | |
1832 | 0 | unsigned fastEmit_ISD_ABS_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
1833 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
1834 | 0 | return 0; |
1835 | 0 | if ((Subtarget->hasNEON())) { |
1836 | 0 | return fastEmitInst_r(AArch64::ABSv4i32, &AArch64::FPR128RegClass, Op0); |
1837 | 0 | } |
1838 | 0 | return 0; |
1839 | 0 | } |
1840 | | |
1841 | 0 | unsigned fastEmit_ISD_ABS_MVT_v1i64_r(MVT RetVT, unsigned Op0) { |
1842 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
1843 | 0 | return 0; |
1844 | 0 | if ((Subtarget->hasNEON())) { |
1845 | 0 | return fastEmitInst_r(AArch64::ABSv1i64, &AArch64::FPR64RegClass, Op0); |
1846 | 0 | } |
1847 | 0 | return 0; |
1848 | 0 | } |
1849 | | |
1850 | 0 | unsigned fastEmit_ISD_ABS_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
1851 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
1852 | 0 | return 0; |
1853 | 0 | if ((Subtarget->hasNEON())) { |
1854 | 0 | return fastEmitInst_r(AArch64::ABSv2i64, &AArch64::FPR128RegClass, Op0); |
1855 | 0 | } |
1856 | 0 | return 0; |
1857 | 0 | } |
1858 | | |
1859 | 0 | unsigned fastEmit_ISD_ABS_r(MVT VT, MVT RetVT, unsigned Op0) { |
1860 | 0 | switch (VT.SimpleTy) { |
1861 | 0 | case MVT::i32: return fastEmit_ISD_ABS_MVT_i32_r(RetVT, Op0); |
1862 | 0 | case MVT::i64: return fastEmit_ISD_ABS_MVT_i64_r(RetVT, Op0); |
1863 | 0 | case MVT::v8i8: return fastEmit_ISD_ABS_MVT_v8i8_r(RetVT, Op0); |
1864 | 0 | case MVT::v16i8: return fastEmit_ISD_ABS_MVT_v16i8_r(RetVT, Op0); |
1865 | 0 | case MVT::v4i16: return fastEmit_ISD_ABS_MVT_v4i16_r(RetVT, Op0); |
1866 | 0 | case MVT::v8i16: return fastEmit_ISD_ABS_MVT_v8i16_r(RetVT, Op0); |
1867 | 0 | case MVT::v2i32: return fastEmit_ISD_ABS_MVT_v2i32_r(RetVT, Op0); |
1868 | 0 | case MVT::v4i32: return fastEmit_ISD_ABS_MVT_v4i32_r(RetVT, Op0); |
1869 | 0 | case MVT::v1i64: return fastEmit_ISD_ABS_MVT_v1i64_r(RetVT, Op0); |
1870 | 0 | case MVT::v2i64: return fastEmit_ISD_ABS_MVT_v2i64_r(RetVT, Op0); |
1871 | 0 | default: return 0; |
1872 | 0 | } |
1873 | 0 | } |
1874 | | |
1875 | | // FastEmit functions for ISD::BITCAST. |
1876 | | |
1877 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v8i8_r(unsigned Op0) { |
1878 | 0 | if ((!Subtarget->isLittleEndian())) { |
1879 | 0 | return fastEmitInst_r(AArch64::REV64v8i8, &AArch64::FPR64RegClass, Op0); |
1880 | 0 | } |
1881 | 0 | return 0; |
1882 | 0 | } |
1883 | | |
1884 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v4i16_r(unsigned Op0) { |
1885 | 0 | if ((!Subtarget->isLittleEndian())) { |
1886 | 0 | return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0); |
1887 | 0 | } |
1888 | 0 | return 0; |
1889 | 0 | } |
1890 | | |
1891 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v2i32_r(unsigned Op0) { |
1892 | 0 | if ((!Subtarget->isLittleEndian())) { |
1893 | 0 | return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0); |
1894 | 0 | } |
1895 | 0 | return 0; |
1896 | 0 | } |
1897 | | |
1898 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v4f16_r(unsigned Op0) { |
1899 | 0 | if ((!Subtarget->isLittleEndian())) { |
1900 | 0 | return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0); |
1901 | 0 | } |
1902 | 0 | return 0; |
1903 | 0 | } |
1904 | | |
1905 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v4bf16_r(unsigned Op0) { |
1906 | 0 | if ((!Subtarget->isLittleEndian())) { |
1907 | 0 | return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0); |
1908 | 0 | } |
1909 | 0 | return 0; |
1910 | 0 | } |
1911 | | |
1912 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v2f32_r(unsigned Op0) { |
1913 | 0 | if ((!Subtarget->isLittleEndian())) { |
1914 | 0 | return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0); |
1915 | 0 | } |
1916 | 0 | return 0; |
1917 | 0 | } |
1918 | | |
1919 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0) { |
1920 | 0 | switch (RetVT.SimpleTy) { |
1921 | 0 | case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v8i8_r(Op0); |
1922 | 0 | case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v4i16_r(Op0); |
1923 | 0 | case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v2i32_r(Op0); |
1924 | 0 | case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v4f16_r(Op0); |
1925 | 0 | case MVT::v4bf16: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v4bf16_r(Op0); |
1926 | 0 | case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v2f32_r(Op0); |
1927 | 0 | default: return 0; |
1928 | 0 | } |
1929 | 0 | } |
1930 | | |
1931 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_f64_r(unsigned Op0) { |
1932 | 0 | if ((!Subtarget->isLittleEndian())) { |
1933 | 0 | return fastEmitInst_r(AArch64::REV64v8i8, &AArch64::FPR64RegClass, Op0); |
1934 | 0 | } |
1935 | 0 | return 0; |
1936 | 0 | } |
1937 | | |
1938 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4i16_r(unsigned Op0) { |
1939 | 0 | if ((!Subtarget->isLittleEndian())) { |
1940 | 0 | return fastEmitInst_r(AArch64::REV16v8i8, &AArch64::FPR64RegClass, Op0); |
1941 | 0 | } |
1942 | 0 | return 0; |
1943 | 0 | } |
1944 | | |
1945 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2i32_r(unsigned Op0) { |
1946 | 0 | if ((!Subtarget->isLittleEndian())) { |
1947 | 0 | return fastEmitInst_r(AArch64::REV32v8i8, &AArch64::FPR64RegClass, Op0); |
1948 | 0 | } |
1949 | 0 | return 0; |
1950 | 0 | } |
1951 | | |
1952 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1i64_r(unsigned Op0) { |
1953 | 0 | if ((!Subtarget->isLittleEndian())) { |
1954 | 0 | return fastEmitInst_r(AArch64::REV64v8i8, &AArch64::FPR64RegClass, Op0); |
1955 | 0 | } |
1956 | 0 | return 0; |
1957 | 0 | } |
1958 | | |
1959 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4f16_r(unsigned Op0) { |
1960 | 0 | if ((!Subtarget->isLittleEndian())) { |
1961 | 0 | return fastEmitInst_r(AArch64::REV16v8i8, &AArch64::FPR64RegClass, Op0); |
1962 | 0 | } |
1963 | 0 | return 0; |
1964 | 0 | } |
1965 | | |
1966 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4bf16_r(unsigned Op0) { |
1967 | 0 | if ((!Subtarget->isLittleEndian())) { |
1968 | 0 | return fastEmitInst_r(AArch64::REV16v8i8, &AArch64::FPR64RegClass, Op0); |
1969 | 0 | } |
1970 | 0 | return 0; |
1971 | 0 | } |
1972 | | |
1973 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2f32_r(unsigned Op0) { |
1974 | 0 | if ((!Subtarget->isLittleEndian())) { |
1975 | 0 | return fastEmitInst_r(AArch64::REV32v8i8, &AArch64::FPR64RegClass, Op0); |
1976 | 0 | } |
1977 | 0 | return 0; |
1978 | 0 | } |
1979 | | |
1980 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1f64_r(unsigned Op0) { |
1981 | 0 | if ((!Subtarget->isLittleEndian())) { |
1982 | 0 | return fastEmitInst_r(AArch64::REV64v8i8, &AArch64::FPR64RegClass, Op0); |
1983 | 0 | } |
1984 | 0 | return 0; |
1985 | 0 | } |
1986 | | |
1987 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8i8_r(MVT RetVT, unsigned Op0) { |
1988 | 0 | switch (RetVT.SimpleTy) { |
1989 | 0 | case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_f64_r(Op0); |
1990 | 0 | case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4i16_r(Op0); |
1991 | 0 | case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2i32_r(Op0); |
1992 | 0 | case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1i64_r(Op0); |
1993 | 0 | case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4f16_r(Op0); |
1994 | 0 | case MVT::v4bf16: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4bf16_r(Op0); |
1995 | 0 | case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2f32_r(Op0); |
1996 | 0 | case MVT::v1f64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1f64_r(Op0); |
1997 | 0 | default: return 0; |
1998 | 0 | } |
1999 | 0 | } |
2000 | | |
2001 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8i16_r(unsigned Op0) { |
2002 | 0 | if ((!Subtarget->isLittleEndian())) { |
2003 | 0 | return fastEmitInst_r(AArch64::REV16v16i8, &AArch64::FPR128RegClass, Op0); |
2004 | 0 | } |
2005 | 0 | return 0; |
2006 | 0 | } |
2007 | | |
2008 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4i32_r(unsigned Op0) { |
2009 | 0 | if ((!Subtarget->isLittleEndian())) { |
2010 | 0 | return fastEmitInst_r(AArch64::REV32v16i8, &AArch64::FPR128RegClass, Op0); |
2011 | 0 | } |
2012 | 0 | return 0; |
2013 | 0 | } |
2014 | | |
2015 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2i64_r(unsigned Op0) { |
2016 | 0 | if ((!Subtarget->isLittleEndian())) { |
2017 | 0 | return fastEmitInst_r(AArch64::REV64v16i8, &AArch64::FPR128RegClass, Op0); |
2018 | 0 | } |
2019 | 0 | return 0; |
2020 | 0 | } |
2021 | | |
2022 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8f16_r(unsigned Op0) { |
2023 | 0 | if ((!Subtarget->isLittleEndian())) { |
2024 | 0 | return fastEmitInst_r(AArch64::REV16v16i8, &AArch64::FPR128RegClass, Op0); |
2025 | 0 | } |
2026 | 0 | return 0; |
2027 | 0 | } |
2028 | | |
2029 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8bf16_r(unsigned Op0) { |
2030 | 0 | if ((!Subtarget->isLittleEndian())) { |
2031 | 0 | return fastEmitInst_r(AArch64::REV16v16i8, &AArch64::FPR128RegClass, Op0); |
2032 | 0 | } |
2033 | 0 | return 0; |
2034 | 0 | } |
2035 | | |
2036 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4f32_r(unsigned Op0) { |
2037 | 0 | if ((!Subtarget->isLittleEndian())) { |
2038 | 0 | return fastEmitInst_r(AArch64::REV32v16i8, &AArch64::FPR128RegClass, Op0); |
2039 | 0 | } |
2040 | 0 | return 0; |
2041 | 0 | } |
2042 | | |
2043 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2f64_r(unsigned Op0) { |
2044 | 0 | if ((!Subtarget->isLittleEndian())) { |
2045 | 0 | return fastEmitInst_r(AArch64::REV64v16i8, &AArch64::FPR128RegClass, Op0); |
2046 | 0 | } |
2047 | 0 | return 0; |
2048 | 0 | } |
2049 | | |
2050 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
2051 | 0 | switch (RetVT.SimpleTy) { |
2052 | 0 | case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8i16_r(Op0); |
2053 | 0 | case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4i32_r(Op0); |
2054 | 0 | case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2i64_r(Op0); |
2055 | 0 | case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8f16_r(Op0); |
2056 | 0 | case MVT::v8bf16: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8bf16_r(Op0); |
2057 | 0 | case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4f32_r(Op0); |
2058 | 0 | case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2f64_r(Op0); |
2059 | 0 | default: return 0; |
2060 | 0 | } |
2061 | 0 | } |
2062 | | |
2063 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_f64_r(unsigned Op0) { |
2064 | 0 | if ((!Subtarget->isLittleEndian())) { |
2065 | 0 | return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0); |
2066 | 0 | } |
2067 | 0 | return 0; |
2068 | 0 | } |
2069 | | |
2070 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v8i8_r(unsigned Op0) { |
2071 | 0 | if ((!Subtarget->isLittleEndian())) { |
2072 | 0 | return fastEmitInst_r(AArch64::REV16v8i8, &AArch64::FPR64RegClass, Op0); |
2073 | 0 | } |
2074 | 0 | return 0; |
2075 | 0 | } |
2076 | | |
2077 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2i32_r(unsigned Op0) { |
2078 | 0 | if ((!Subtarget->isLittleEndian())) { |
2079 | 0 | return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0); |
2080 | 0 | } |
2081 | 0 | return 0; |
2082 | 0 | } |
2083 | | |
2084 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1i64_r(unsigned Op0) { |
2085 | 0 | if ((!Subtarget->isLittleEndian())) { |
2086 | 0 | return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0); |
2087 | 0 | } |
2088 | 0 | return 0; |
2089 | 0 | } |
2090 | | |
2091 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2f32_r(unsigned Op0) { |
2092 | 0 | if ((!Subtarget->isLittleEndian())) { |
2093 | 0 | return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0); |
2094 | 0 | } |
2095 | 0 | return 0; |
2096 | 0 | } |
2097 | | |
2098 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1f64_r(unsigned Op0) { |
2099 | 0 | if ((!Subtarget->isLittleEndian())) { |
2100 | 0 | return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0); |
2101 | 0 | } |
2102 | 0 | return 0; |
2103 | 0 | } |
2104 | | |
2105 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4i16_r(MVT RetVT, unsigned Op0) { |
2106 | 0 | switch (RetVT.SimpleTy) { |
2107 | 0 | case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_f64_r(Op0); |
2108 | 0 | case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v8i8_r(Op0); |
2109 | 0 | case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2i32_r(Op0); |
2110 | 0 | case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1i64_r(Op0); |
2111 | 0 | case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2f32_r(Op0); |
2112 | 0 | case MVT::v1f64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1f64_r(Op0); |
2113 | 0 | default: return 0; |
2114 | 0 | } |
2115 | 0 | } |
2116 | | |
2117 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v16i8_r(unsigned Op0) { |
2118 | 0 | if ((!Subtarget->isLittleEndian())) { |
2119 | 0 | return fastEmitInst_r(AArch64::REV16v16i8, &AArch64::FPR128RegClass, Op0); |
2120 | 0 | } |
2121 | 0 | return 0; |
2122 | 0 | } |
2123 | | |
2124 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4i32_r(unsigned Op0) { |
2125 | 0 | if ((!Subtarget->isLittleEndian())) { |
2126 | 0 | return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0); |
2127 | 0 | } |
2128 | 0 | return 0; |
2129 | 0 | } |
2130 | | |
2131 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2i64_r(unsigned Op0) { |
2132 | 0 | if ((!Subtarget->isLittleEndian())) { |
2133 | 0 | return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0); |
2134 | 0 | } |
2135 | 0 | return 0; |
2136 | 0 | } |
2137 | | |
2138 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4f32_r(unsigned Op0) { |
2139 | 0 | if ((!Subtarget->isLittleEndian())) { |
2140 | 0 | return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0); |
2141 | 0 | } |
2142 | 0 | return 0; |
2143 | 0 | } |
2144 | | |
2145 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2f64_r(unsigned Op0) { |
2146 | 0 | if ((!Subtarget->isLittleEndian())) { |
2147 | 0 | return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0); |
2148 | 0 | } |
2149 | 0 | return 0; |
2150 | 0 | } |
2151 | | |
2152 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
2153 | 0 | switch (RetVT.SimpleTy) { |
2154 | 0 | case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v16i8_r(Op0); |
2155 | 0 | case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4i32_r(Op0); |
2156 | 0 | case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2i64_r(Op0); |
2157 | 0 | case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4f32_r(Op0); |
2158 | 0 | case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2f64_r(Op0); |
2159 | 0 | default: return 0; |
2160 | 0 | } |
2161 | 0 | } |
2162 | | |
2163 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_f64_r(unsigned Op0) { |
2164 | 0 | if ((!Subtarget->isLittleEndian())) { |
2165 | 0 | return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0); |
2166 | 0 | } |
2167 | 0 | return 0; |
2168 | 0 | } |
2169 | | |
2170 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v8i8_r(unsigned Op0) { |
2171 | 0 | if ((!Subtarget->isLittleEndian())) { |
2172 | 0 | return fastEmitInst_r(AArch64::REV32v8i8, &AArch64::FPR64RegClass, Op0); |
2173 | 0 | } |
2174 | 0 | return 0; |
2175 | 0 | } |
2176 | | |
2177 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4i16_r(unsigned Op0) { |
2178 | 0 | if ((!Subtarget->isLittleEndian())) { |
2179 | 0 | return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0); |
2180 | 0 | } |
2181 | 0 | return 0; |
2182 | 0 | } |
2183 | | |
2184 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1i64_r(unsigned Op0) { |
2185 | 0 | if ((!Subtarget->isLittleEndian())) { |
2186 | 0 | return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0); |
2187 | 0 | } |
2188 | 0 | return 0; |
2189 | 0 | } |
2190 | | |
2191 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4f16_r(unsigned Op0) { |
2192 | 0 | if ((!Subtarget->isLittleEndian())) { |
2193 | 0 | return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0); |
2194 | 0 | } |
2195 | 0 | return 0; |
2196 | 0 | } |
2197 | | |
2198 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4bf16_r(unsigned Op0) { |
2199 | 0 | if ((!Subtarget->isLittleEndian())) { |
2200 | 0 | return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0); |
2201 | 0 | } |
2202 | 0 | return 0; |
2203 | 0 | } |
2204 | | |
2205 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1f64_r(unsigned Op0) { |
2206 | 0 | if ((!Subtarget->isLittleEndian())) { |
2207 | 0 | return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0); |
2208 | 0 | } |
2209 | 0 | return 0; |
2210 | 0 | } |
2211 | | |
2212 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2i32_r(MVT RetVT, unsigned Op0) { |
2213 | 0 | switch (RetVT.SimpleTy) { |
2214 | 0 | case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_f64_r(Op0); |
2215 | 0 | case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v8i8_r(Op0); |
2216 | 0 | case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4i16_r(Op0); |
2217 | 0 | case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1i64_r(Op0); |
2218 | 0 | case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4f16_r(Op0); |
2219 | 0 | case MVT::v4bf16: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4bf16_r(Op0); |
2220 | 0 | case MVT::v1f64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1f64_r(Op0); |
2221 | 0 | default: return 0; |
2222 | 0 | } |
2223 | 0 | } |
2224 | | |
2225 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v16i8_r(unsigned Op0) { |
2226 | 0 | if ((!Subtarget->isLittleEndian())) { |
2227 | 0 | return fastEmitInst_r(AArch64::REV32v16i8, &AArch64::FPR128RegClass, Op0); |
2228 | 0 | } |
2229 | 0 | return 0; |
2230 | 0 | } |
2231 | | |
2232 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8i16_r(unsigned Op0) { |
2233 | 0 | if ((!Subtarget->isLittleEndian())) { |
2234 | 0 | return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0); |
2235 | 0 | } |
2236 | 0 | return 0; |
2237 | 0 | } |
2238 | | |
2239 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2i64_r(unsigned Op0) { |
2240 | 0 | if ((!Subtarget->isLittleEndian())) { |
2241 | 0 | return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0); |
2242 | 0 | } |
2243 | 0 | return 0; |
2244 | 0 | } |
2245 | | |
2246 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8f16_r(unsigned Op0) { |
2247 | 0 | if ((!Subtarget->isLittleEndian())) { |
2248 | 0 | return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0); |
2249 | 0 | } |
2250 | 0 | return 0; |
2251 | 0 | } |
2252 | | |
2253 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8bf16_r(unsigned Op0) { |
2254 | 0 | if ((!Subtarget->isLittleEndian())) { |
2255 | 0 | return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0); |
2256 | 0 | } |
2257 | 0 | return 0; |
2258 | 0 | } |
2259 | | |
2260 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2f64_r(unsigned Op0) { |
2261 | 0 | if ((!Subtarget->isLittleEndian())) { |
2262 | 0 | return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0); |
2263 | 0 | } |
2264 | 0 | return 0; |
2265 | 0 | } |
2266 | | |
2267 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
2268 | 0 | switch (RetVT.SimpleTy) { |
2269 | 0 | case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v16i8_r(Op0); |
2270 | 0 | case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8i16_r(Op0); |
2271 | 0 | case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2i64_r(Op0); |
2272 | 0 | case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8f16_r(Op0); |
2273 | 0 | case MVT::v8bf16: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8bf16_r(Op0); |
2274 | 0 | case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2f64_r(Op0); |
2275 | 0 | default: return 0; |
2276 | 0 | } |
2277 | 0 | } |
2278 | | |
2279 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v8i8_r(unsigned Op0) { |
2280 | 0 | if ((!Subtarget->isLittleEndian())) { |
2281 | 0 | return fastEmitInst_r(AArch64::REV64v8i8, &AArch64::FPR64RegClass, Op0); |
2282 | 0 | } |
2283 | 0 | return 0; |
2284 | 0 | } |
2285 | | |
2286 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4i16_r(unsigned Op0) { |
2287 | 0 | if ((!Subtarget->isLittleEndian())) { |
2288 | 0 | return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0); |
2289 | 0 | } |
2290 | 0 | return 0; |
2291 | 0 | } |
2292 | | |
2293 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2i32_r(unsigned Op0) { |
2294 | 0 | if ((!Subtarget->isLittleEndian())) { |
2295 | 0 | return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0); |
2296 | 0 | } |
2297 | 0 | return 0; |
2298 | 0 | } |
2299 | | |
2300 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4f16_r(unsigned Op0) { |
2301 | 0 | if ((!Subtarget->isLittleEndian())) { |
2302 | 0 | return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0); |
2303 | 0 | } |
2304 | 0 | return 0; |
2305 | 0 | } |
2306 | | |
2307 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4bf16_r(unsigned Op0) { |
2308 | 0 | if ((!Subtarget->isLittleEndian())) { |
2309 | 0 | return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0); |
2310 | 0 | } |
2311 | 0 | return 0; |
2312 | 0 | } |
2313 | | |
2314 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2f32_r(unsigned Op0) { |
2315 | 0 | if ((!Subtarget->isLittleEndian())) { |
2316 | 0 | return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0); |
2317 | 0 | } |
2318 | 0 | return 0; |
2319 | 0 | } |
2320 | | |
2321 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v1i64_r(MVT RetVT, unsigned Op0) { |
2322 | 0 | switch (RetVT.SimpleTy) { |
2323 | 0 | case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v8i8_r(Op0); |
2324 | 0 | case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4i16_r(Op0); |
2325 | 0 | case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2i32_r(Op0); |
2326 | 0 | case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4f16_r(Op0); |
2327 | 0 | case MVT::v4bf16: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4bf16_r(Op0); |
2328 | 0 | case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2f32_r(Op0); |
2329 | 0 | default: return 0; |
2330 | 0 | } |
2331 | 0 | } |
2332 | | |
2333 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v16i8_r(unsigned Op0) { |
2334 | 0 | if ((!Subtarget->isLittleEndian())) { |
2335 | 0 | return fastEmitInst_r(AArch64::REV64v16i8, &AArch64::FPR128RegClass, Op0); |
2336 | 0 | } |
2337 | 0 | return 0; |
2338 | 0 | } |
2339 | | |
2340 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8i16_r(unsigned Op0) { |
2341 | 0 | if ((!Subtarget->isLittleEndian())) { |
2342 | 0 | return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0); |
2343 | 0 | } |
2344 | 0 | return 0; |
2345 | 0 | } |
2346 | | |
2347 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4i32_r(unsigned Op0) { |
2348 | 0 | if ((!Subtarget->isLittleEndian())) { |
2349 | 0 | return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0); |
2350 | 0 | } |
2351 | 0 | return 0; |
2352 | 0 | } |
2353 | | |
2354 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8f16_r(unsigned Op0) { |
2355 | 0 | if ((!Subtarget->isLittleEndian())) { |
2356 | 0 | return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0); |
2357 | 0 | } |
2358 | 0 | return 0; |
2359 | 0 | } |
2360 | | |
2361 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8bf16_r(unsigned Op0) { |
2362 | 0 | if ((!Subtarget->isLittleEndian())) { |
2363 | 0 | return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0); |
2364 | 0 | } |
2365 | 0 | return 0; |
2366 | 0 | } |
2367 | | |
2368 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4f32_r(unsigned Op0) { |
2369 | 0 | if ((!Subtarget->isLittleEndian())) { |
2370 | 0 | return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0); |
2371 | 0 | } |
2372 | 0 | return 0; |
2373 | 0 | } |
2374 | | |
2375 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
2376 | 0 | switch (RetVT.SimpleTy) { |
2377 | 0 | case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v16i8_r(Op0); |
2378 | 0 | case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8i16_r(Op0); |
2379 | 0 | case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4i32_r(Op0); |
2380 | 0 | case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8f16_r(Op0); |
2381 | 0 | case MVT::v8bf16: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8bf16_r(Op0); |
2382 | 0 | case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4f32_r(Op0); |
2383 | 0 | default: return 0; |
2384 | 0 | } |
2385 | 0 | } |
2386 | | |
2387 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4f16_MVT_f64_r(unsigned Op0) { |
2388 | 0 | if ((!Subtarget->isLittleEndian())) { |
2389 | 0 | return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0); |
2390 | 0 | } |
2391 | 0 | return 0; |
2392 | 0 | } |
2393 | | |
2394 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v8i8_r(unsigned Op0) { |
2395 | 0 | if ((!Subtarget->isLittleEndian())) { |
2396 | 0 | return fastEmitInst_r(AArch64::REV16v8i8, &AArch64::FPR64RegClass, Op0); |
2397 | 0 | } |
2398 | 0 | return 0; |
2399 | 0 | } |
2400 | | |
2401 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v2i32_r(unsigned Op0) { |
2402 | 0 | if ((!Subtarget->isLittleEndian())) { |
2403 | 0 | return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0); |
2404 | 0 | } |
2405 | 0 | return 0; |
2406 | 0 | } |
2407 | | |
2408 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v1i64_r(unsigned Op0) { |
2409 | 0 | if ((!Subtarget->isLittleEndian())) { |
2410 | 0 | return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0); |
2411 | 0 | } |
2412 | 0 | return 0; |
2413 | 0 | } |
2414 | | |
2415 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v2f32_r(unsigned Op0) { |
2416 | 0 | if ((!Subtarget->isLittleEndian())) { |
2417 | 0 | return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0); |
2418 | 0 | } |
2419 | 0 | return 0; |
2420 | 0 | } |
2421 | | |
2422 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v1f64_r(unsigned Op0) { |
2423 | 0 | if ((!Subtarget->isLittleEndian())) { |
2424 | 0 | return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0); |
2425 | 0 | } |
2426 | 0 | return 0; |
2427 | 0 | } |
2428 | | |
2429 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
2430 | 0 | switch (RetVT.SimpleTy) { |
2431 | 0 | case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_f64_r(Op0); |
2432 | 0 | case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v8i8_r(Op0); |
2433 | 0 | case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v2i32_r(Op0); |
2434 | 0 | case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v1i64_r(Op0); |
2435 | 0 | case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v2f32_r(Op0); |
2436 | 0 | case MVT::v1f64: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v1f64_r(Op0); |
2437 | 0 | default: return 0; |
2438 | 0 | } |
2439 | 0 | } |
2440 | | |
2441 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v16i8_r(unsigned Op0) { |
2442 | 0 | if ((!Subtarget->isLittleEndian())) { |
2443 | 0 | return fastEmitInst_r(AArch64::REV16v16i8, &AArch64::FPR128RegClass, Op0); |
2444 | 0 | } |
2445 | 0 | return 0; |
2446 | 0 | } |
2447 | | |
2448 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4i32_r(unsigned Op0) { |
2449 | 0 | if ((!Subtarget->isLittleEndian())) { |
2450 | 0 | return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0); |
2451 | 0 | } |
2452 | 0 | return 0; |
2453 | 0 | } |
2454 | | |
2455 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2i64_r(unsigned Op0) { |
2456 | 0 | if ((!Subtarget->isLittleEndian())) { |
2457 | 0 | return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0); |
2458 | 0 | } |
2459 | 0 | return 0; |
2460 | 0 | } |
2461 | | |
2462 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4f32_r(unsigned Op0) { |
2463 | 0 | if ((!Subtarget->isLittleEndian())) { |
2464 | 0 | return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0); |
2465 | 0 | } |
2466 | 0 | return 0; |
2467 | 0 | } |
2468 | | |
2469 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2f64_r(unsigned Op0) { |
2470 | 0 | if ((!Subtarget->isLittleEndian())) { |
2471 | 0 | return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0); |
2472 | 0 | } |
2473 | 0 | return 0; |
2474 | 0 | } |
2475 | | |
2476 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
2477 | 0 | switch (RetVT.SimpleTy) { |
2478 | 0 | case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v16i8_r(Op0); |
2479 | 0 | case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4i32_r(Op0); |
2480 | 0 | case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2i64_r(Op0); |
2481 | 0 | case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4f32_r(Op0); |
2482 | 0 | case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2f64_r(Op0); |
2483 | 0 | default: return 0; |
2484 | 0 | } |
2485 | 0 | } |
2486 | | |
2487 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4bf16_MVT_f64_r(unsigned Op0) { |
2488 | 0 | if ((!Subtarget->isLittleEndian())) { |
2489 | 0 | return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0); |
2490 | 0 | } |
2491 | 0 | return 0; |
2492 | 0 | } |
2493 | | |
2494 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4bf16_MVT_v8i8_r(unsigned Op0) { |
2495 | 0 | if ((!Subtarget->isLittleEndian())) { |
2496 | 0 | return fastEmitInst_r(AArch64::REV16v8i8, &AArch64::FPR64RegClass, Op0); |
2497 | 0 | } |
2498 | 0 | return 0; |
2499 | 0 | } |
2500 | | |
2501 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4bf16_MVT_v2i32_r(unsigned Op0) { |
2502 | 0 | if ((!Subtarget->isLittleEndian())) { |
2503 | 0 | return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0); |
2504 | 0 | } |
2505 | 0 | return 0; |
2506 | 0 | } |
2507 | | |
2508 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4bf16_MVT_v1i64_r(unsigned Op0) { |
2509 | 0 | if ((!Subtarget->isLittleEndian())) { |
2510 | 0 | return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0); |
2511 | 0 | } |
2512 | 0 | return 0; |
2513 | 0 | } |
2514 | | |
2515 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4bf16_MVT_v2f32_r(unsigned Op0) { |
2516 | 0 | if ((!Subtarget->isLittleEndian())) { |
2517 | 0 | return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0); |
2518 | 0 | } |
2519 | 0 | return 0; |
2520 | 0 | } |
2521 | | |
2522 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4bf16_MVT_v1f64_r(unsigned Op0) { |
2523 | 0 | if ((!Subtarget->isLittleEndian())) { |
2524 | 0 | return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0); |
2525 | 0 | } |
2526 | 0 | return 0; |
2527 | 0 | } |
2528 | | |
2529 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4bf16_r(MVT RetVT, unsigned Op0) { |
2530 | 0 | switch (RetVT.SimpleTy) { |
2531 | 0 | case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v4bf16_MVT_f64_r(Op0); |
2532 | 0 | case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v4bf16_MVT_v8i8_r(Op0); |
2533 | 0 | case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v4bf16_MVT_v2i32_r(Op0); |
2534 | 0 | case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v4bf16_MVT_v1i64_r(Op0); |
2535 | 0 | case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v4bf16_MVT_v2f32_r(Op0); |
2536 | 0 | case MVT::v1f64: return fastEmit_ISD_BITCAST_MVT_v4bf16_MVT_v1f64_r(Op0); |
2537 | 0 | default: return 0; |
2538 | 0 | } |
2539 | 0 | } |
2540 | | |
2541 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8bf16_MVT_v16i8_r(unsigned Op0) { |
2542 | 0 | if ((!Subtarget->isLittleEndian())) { |
2543 | 0 | return fastEmitInst_r(AArch64::REV16v16i8, &AArch64::FPR128RegClass, Op0); |
2544 | 0 | } |
2545 | 0 | return 0; |
2546 | 0 | } |
2547 | | |
2548 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8bf16_MVT_v4i32_r(unsigned Op0) { |
2549 | 0 | if ((!Subtarget->isLittleEndian())) { |
2550 | 0 | return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0); |
2551 | 0 | } |
2552 | 0 | return 0; |
2553 | 0 | } |
2554 | | |
2555 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8bf16_MVT_v2i64_r(unsigned Op0) { |
2556 | 0 | if ((!Subtarget->isLittleEndian())) { |
2557 | 0 | return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0); |
2558 | 0 | } |
2559 | 0 | return 0; |
2560 | 0 | } |
2561 | | |
2562 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8bf16_MVT_v4f32_r(unsigned Op0) { |
2563 | 0 | if ((!Subtarget->isLittleEndian())) { |
2564 | 0 | return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0); |
2565 | 0 | } |
2566 | 0 | return 0; |
2567 | 0 | } |
2568 | | |
2569 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8bf16_MVT_v2f64_r(unsigned Op0) { |
2570 | 0 | if ((!Subtarget->isLittleEndian())) { |
2571 | 0 | return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0); |
2572 | 0 | } |
2573 | 0 | return 0; |
2574 | 0 | } |
2575 | | |
2576 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v8bf16_r(MVT RetVT, unsigned Op0) { |
2577 | 0 | switch (RetVT.SimpleTy) { |
2578 | 0 | case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v8bf16_MVT_v16i8_r(Op0); |
2579 | 0 | case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v8bf16_MVT_v4i32_r(Op0); |
2580 | 0 | case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v8bf16_MVT_v2i64_r(Op0); |
2581 | 0 | case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v8bf16_MVT_v4f32_r(Op0); |
2582 | 0 | case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v8bf16_MVT_v2f64_r(Op0); |
2583 | 0 | default: return 0; |
2584 | 0 | } |
2585 | 0 | } |
2586 | | |
2587 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_f64_r(unsigned Op0) { |
2588 | 0 | if ((!Subtarget->isLittleEndian())) { |
2589 | 0 | return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0); |
2590 | 0 | } |
2591 | 0 | return 0; |
2592 | 0 | } |
2593 | | |
2594 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v8i8_r(unsigned Op0) { |
2595 | 0 | if ((!Subtarget->isLittleEndian())) { |
2596 | 0 | return fastEmitInst_r(AArch64::REV32v8i8, &AArch64::FPR64RegClass, Op0); |
2597 | 0 | } |
2598 | 0 | return 0; |
2599 | 0 | } |
2600 | | |
2601 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4i16_r(unsigned Op0) { |
2602 | 0 | if ((!Subtarget->isLittleEndian())) { |
2603 | 0 | return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0); |
2604 | 0 | } |
2605 | 0 | return 0; |
2606 | 0 | } |
2607 | | |
2608 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1i64_r(unsigned Op0) { |
2609 | 0 | if ((!Subtarget->isLittleEndian())) { |
2610 | 0 | return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0); |
2611 | 0 | } |
2612 | 0 | return 0; |
2613 | 0 | } |
2614 | | |
2615 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4f16_r(unsigned Op0) { |
2616 | 0 | if ((!Subtarget->isLittleEndian())) { |
2617 | 0 | return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0); |
2618 | 0 | } |
2619 | 0 | return 0; |
2620 | 0 | } |
2621 | | |
2622 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4bf16_r(unsigned Op0) { |
2623 | 0 | if ((!Subtarget->isLittleEndian())) { |
2624 | 0 | return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0); |
2625 | 0 | } |
2626 | 0 | return 0; |
2627 | 0 | } |
2628 | | |
2629 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1f64_r(unsigned Op0) { |
2630 | 0 | if ((!Subtarget->isLittleEndian())) { |
2631 | 0 | return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0); |
2632 | 0 | } |
2633 | 0 | return 0; |
2634 | 0 | } |
2635 | | |
2636 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
2637 | 0 | switch (RetVT.SimpleTy) { |
2638 | 0 | case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_f64_r(Op0); |
2639 | 0 | case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v8i8_r(Op0); |
2640 | 0 | case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4i16_r(Op0); |
2641 | 0 | case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1i64_r(Op0); |
2642 | 0 | case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4f16_r(Op0); |
2643 | 0 | case MVT::v4bf16: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4bf16_r(Op0); |
2644 | 0 | case MVT::v1f64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1f64_r(Op0); |
2645 | 0 | default: return 0; |
2646 | 0 | } |
2647 | 0 | } |
2648 | | |
2649 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v16i8_r(unsigned Op0) { |
2650 | 0 | if ((!Subtarget->isLittleEndian())) { |
2651 | 0 | return fastEmitInst_r(AArch64::REV32v16i8, &AArch64::FPR128RegClass, Op0); |
2652 | 0 | } |
2653 | 0 | return 0; |
2654 | 0 | } |
2655 | | |
2656 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8i16_r(unsigned Op0) { |
2657 | 0 | if ((!Subtarget->isLittleEndian())) { |
2658 | 0 | return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0); |
2659 | 0 | } |
2660 | 0 | return 0; |
2661 | 0 | } |
2662 | | |
2663 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2i64_r(unsigned Op0) { |
2664 | 0 | if ((!Subtarget->isLittleEndian())) { |
2665 | 0 | return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0); |
2666 | 0 | } |
2667 | 0 | return 0; |
2668 | 0 | } |
2669 | | |
2670 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8f16_r(unsigned Op0) { |
2671 | 0 | if ((!Subtarget->isLittleEndian())) { |
2672 | 0 | return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0); |
2673 | 0 | } |
2674 | 0 | return 0; |
2675 | 0 | } |
2676 | | |
2677 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8bf16_r(unsigned Op0) { |
2678 | 0 | if ((!Subtarget->isLittleEndian())) { |
2679 | 0 | return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0); |
2680 | 0 | } |
2681 | 0 | return 0; |
2682 | 0 | } |
2683 | | |
2684 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2f64_r(unsigned Op0) { |
2685 | 0 | if ((!Subtarget->isLittleEndian())) { |
2686 | 0 | return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0); |
2687 | 0 | } |
2688 | 0 | return 0; |
2689 | 0 | } |
2690 | | |
2691 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
2692 | 0 | switch (RetVT.SimpleTy) { |
2693 | 0 | case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v16i8_r(Op0); |
2694 | 0 | case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8i16_r(Op0); |
2695 | 0 | case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2i64_r(Op0); |
2696 | 0 | case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8f16_r(Op0); |
2697 | 0 | case MVT::v8bf16: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8bf16_r(Op0); |
2698 | 0 | case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2f64_r(Op0); |
2699 | 0 | default: return 0; |
2700 | 0 | } |
2701 | 0 | } |
2702 | | |
2703 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v8i8_r(unsigned Op0) { |
2704 | 0 | if ((!Subtarget->isLittleEndian())) { |
2705 | 0 | return fastEmitInst_r(AArch64::REV64v8i8, &AArch64::FPR64RegClass, Op0); |
2706 | 0 | } |
2707 | 0 | return 0; |
2708 | 0 | } |
2709 | | |
2710 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v4i16_r(unsigned Op0) { |
2711 | 0 | if ((!Subtarget->isLittleEndian())) { |
2712 | 0 | return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0); |
2713 | 0 | } |
2714 | 0 | return 0; |
2715 | 0 | } |
2716 | | |
2717 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v2i32_r(unsigned Op0) { |
2718 | 0 | if ((!Subtarget->isLittleEndian())) { |
2719 | 0 | return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0); |
2720 | 0 | } |
2721 | 0 | return 0; |
2722 | 0 | } |
2723 | | |
2724 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v4f16_r(unsigned Op0) { |
2725 | 0 | if ((!Subtarget->isLittleEndian())) { |
2726 | 0 | return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0); |
2727 | 0 | } |
2728 | 0 | return 0; |
2729 | 0 | } |
2730 | | |
2731 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v4bf16_r(unsigned Op0) { |
2732 | 0 | if ((!Subtarget->isLittleEndian())) { |
2733 | 0 | return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0); |
2734 | 0 | } |
2735 | 0 | return 0; |
2736 | 0 | } |
2737 | | |
2738 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v2f32_r(unsigned Op0) { |
2739 | 0 | if ((!Subtarget->isLittleEndian())) { |
2740 | 0 | return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0); |
2741 | 0 | } |
2742 | 0 | return 0; |
2743 | 0 | } |
2744 | | |
2745 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v1f64_r(MVT RetVT, unsigned Op0) { |
2746 | 0 | switch (RetVT.SimpleTy) { |
2747 | 0 | case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v8i8_r(Op0); |
2748 | 0 | case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v4i16_r(Op0); |
2749 | 0 | case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v2i32_r(Op0); |
2750 | 0 | case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v4f16_r(Op0); |
2751 | 0 | case MVT::v4bf16: return fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v4bf16_r(Op0); |
2752 | 0 | case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v2f32_r(Op0); |
2753 | 0 | default: return 0; |
2754 | 0 | } |
2755 | 0 | } |
2756 | | |
2757 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v16i8_r(unsigned Op0) { |
2758 | 0 | if ((!Subtarget->isLittleEndian())) { |
2759 | 0 | return fastEmitInst_r(AArch64::REV64v16i8, &AArch64::FPR128RegClass, Op0); |
2760 | 0 | } |
2761 | 0 | return 0; |
2762 | 0 | } |
2763 | | |
2764 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8i16_r(unsigned Op0) { |
2765 | 0 | if ((!Subtarget->isLittleEndian())) { |
2766 | 0 | return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0); |
2767 | 0 | } |
2768 | 0 | return 0; |
2769 | 0 | } |
2770 | | |
2771 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4i32_r(unsigned Op0) { |
2772 | 0 | if ((!Subtarget->isLittleEndian())) { |
2773 | 0 | return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0); |
2774 | 0 | } |
2775 | 0 | return 0; |
2776 | 0 | } |
2777 | | |
2778 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8f16_r(unsigned Op0) { |
2779 | 0 | if ((!Subtarget->isLittleEndian())) { |
2780 | 0 | return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0); |
2781 | 0 | } |
2782 | 0 | return 0; |
2783 | 0 | } |
2784 | | |
2785 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8bf16_r(unsigned Op0) { |
2786 | 0 | if ((!Subtarget->isLittleEndian())) { |
2787 | 0 | return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0); |
2788 | 0 | } |
2789 | 0 | return 0; |
2790 | 0 | } |
2791 | | |
2792 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4f32_r(unsigned Op0) { |
2793 | 0 | if ((!Subtarget->isLittleEndian())) { |
2794 | 0 | return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0); |
2795 | 0 | } |
2796 | 0 | return 0; |
2797 | 0 | } |
2798 | | |
2799 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
2800 | 0 | switch (RetVT.SimpleTy) { |
2801 | 0 | case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v16i8_r(Op0); |
2802 | 0 | case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8i16_r(Op0); |
2803 | 0 | case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4i32_r(Op0); |
2804 | 0 | case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8f16_r(Op0); |
2805 | 0 | case MVT::v8bf16: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8bf16_r(Op0); |
2806 | 0 | case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4f32_r(Op0); |
2807 | 0 | default: return 0; |
2808 | 0 | } |
2809 | 0 | } |
2810 | | |
2811 | 0 | unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0) { |
2812 | 0 | switch (VT.SimpleTy) { |
2813 | 0 | case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0); |
2814 | 0 | case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v8i8_r(RetVT, Op0); |
2815 | 0 | case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v16i8_r(RetVT, Op0); |
2816 | 0 | case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v4i16_r(RetVT, Op0); |
2817 | 0 | case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v8i16_r(RetVT, Op0); |
2818 | 0 | case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v2i32_r(RetVT, Op0); |
2819 | 0 | case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v4i32_r(RetVT, Op0); |
2820 | 0 | case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v1i64_r(RetVT, Op0); |
2821 | 0 | case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v2i64_r(RetVT, Op0); |
2822 | 0 | case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v4f16_r(RetVT, Op0); |
2823 | 0 | case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v8f16_r(RetVT, Op0); |
2824 | 0 | case MVT::v4bf16: return fastEmit_ISD_BITCAST_MVT_v4bf16_r(RetVT, Op0); |
2825 | 0 | case MVT::v8bf16: return fastEmit_ISD_BITCAST_MVT_v8bf16_r(RetVT, Op0); |
2826 | 0 | case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v2f32_r(RetVT, Op0); |
2827 | 0 | case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v4f32_r(RetVT, Op0); |
2828 | 0 | case MVT::v1f64: return fastEmit_ISD_BITCAST_MVT_v1f64_r(RetVT, Op0); |
2829 | 0 | case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v2f64_r(RetVT, Op0); |
2830 | 0 | default: return 0; |
2831 | 0 | } |
2832 | 0 | } |
2833 | | |
2834 | | // FastEmit functions for ISD::BITREVERSE. |
2835 | | |
2836 | 0 | unsigned fastEmit_ISD_BITREVERSE_MVT_i32_r(MVT RetVT, unsigned Op0) { |
2837 | 0 | if (RetVT.SimpleTy != MVT::i32) |
2838 | 0 | return 0; |
2839 | 0 | return fastEmitInst_r(AArch64::RBITWr, &AArch64::GPR32RegClass, Op0); |
2840 | 0 | } |
2841 | | |
2842 | 0 | unsigned fastEmit_ISD_BITREVERSE_MVT_i64_r(MVT RetVT, unsigned Op0) { |
2843 | 0 | if (RetVT.SimpleTy != MVT::i64) |
2844 | 0 | return 0; |
2845 | 0 | return fastEmitInst_r(AArch64::RBITXr, &AArch64::GPR64RegClass, Op0); |
2846 | 0 | } |
2847 | | |
2848 | 0 | unsigned fastEmit_ISD_BITREVERSE_MVT_v8i8_r(MVT RetVT, unsigned Op0) { |
2849 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
2850 | 0 | return 0; |
2851 | 0 | if ((Subtarget->hasNEON())) { |
2852 | 0 | return fastEmitInst_r(AArch64::RBITv8i8, &AArch64::FPR64RegClass, Op0); |
2853 | 0 | } |
2854 | 0 | return 0; |
2855 | 0 | } |
2856 | | |
2857 | 0 | unsigned fastEmit_ISD_BITREVERSE_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
2858 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
2859 | 0 | return 0; |
2860 | 0 | if ((Subtarget->hasNEON())) { |
2861 | 0 | return fastEmitInst_r(AArch64::RBITv16i8, &AArch64::FPR128RegClass, Op0); |
2862 | 0 | } |
2863 | 0 | return 0; |
2864 | 0 | } |
2865 | | |
2866 | 0 | unsigned fastEmit_ISD_BITREVERSE_r(MVT VT, MVT RetVT, unsigned Op0) { |
2867 | 0 | switch (VT.SimpleTy) { |
2868 | 0 | case MVT::i32: return fastEmit_ISD_BITREVERSE_MVT_i32_r(RetVT, Op0); |
2869 | 0 | case MVT::i64: return fastEmit_ISD_BITREVERSE_MVT_i64_r(RetVT, Op0); |
2870 | 0 | case MVT::v8i8: return fastEmit_ISD_BITREVERSE_MVT_v8i8_r(RetVT, Op0); |
2871 | 0 | case MVT::v16i8: return fastEmit_ISD_BITREVERSE_MVT_v16i8_r(RetVT, Op0); |
2872 | 0 | default: return 0; |
2873 | 0 | } |
2874 | 0 | } |
2875 | | |
2876 | | // FastEmit functions for ISD::BRIND. |
2877 | | |
2878 | 0 | unsigned fastEmit_ISD_BRIND_MVT_i64_r(MVT RetVT, unsigned Op0) { |
2879 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
2880 | 0 | return 0; |
2881 | 0 | return fastEmitInst_r(AArch64::BR, &AArch64::GPR64RegClass, Op0); |
2882 | 0 | } |
2883 | | |
2884 | 0 | unsigned fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0) { |
2885 | 0 | switch (VT.SimpleTy) { |
2886 | 0 | case MVT::i64: return fastEmit_ISD_BRIND_MVT_i64_r(RetVT, Op0); |
2887 | 0 | default: return 0; |
2888 | 0 | } |
2889 | 0 | } |
2890 | | |
2891 | | // FastEmit functions for ISD::BSWAP. |
2892 | | |
2893 | 0 | unsigned fastEmit_ISD_BSWAP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
2894 | 0 | if (RetVT.SimpleTy != MVT::i32) |
2895 | 0 | return 0; |
2896 | 0 | return fastEmitInst_r(AArch64::REVWr, &AArch64::GPR32RegClass, Op0); |
2897 | 0 | } |
2898 | | |
2899 | 0 | unsigned fastEmit_ISD_BSWAP_MVT_i64_r(MVT RetVT, unsigned Op0) { |
2900 | 0 | if (RetVT.SimpleTy != MVT::i64) |
2901 | 0 | return 0; |
2902 | 0 | return fastEmitInst_r(AArch64::REVXr, &AArch64::GPR64RegClass, Op0); |
2903 | 0 | } |
2904 | | |
2905 | 0 | unsigned fastEmit_ISD_BSWAP_r(MVT VT, MVT RetVT, unsigned Op0) { |
2906 | 0 | switch (VT.SimpleTy) { |
2907 | 0 | case MVT::i32: return fastEmit_ISD_BSWAP_MVT_i32_r(RetVT, Op0); |
2908 | 0 | case MVT::i64: return fastEmit_ISD_BSWAP_MVT_i64_r(RetVT, Op0); |
2909 | 0 | default: return 0; |
2910 | 0 | } |
2911 | 0 | } |
2912 | | |
2913 | | // FastEmit functions for ISD::CTLZ. |
2914 | | |
2915 | 0 | unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0) { |
2916 | 0 | if (RetVT.SimpleTy != MVT::i32) |
2917 | 0 | return 0; |
2918 | 0 | return fastEmitInst_r(AArch64::CLZWr, &AArch64::GPR32RegClass, Op0); |
2919 | 0 | } |
2920 | | |
2921 | 0 | unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0) { |
2922 | 0 | if (RetVT.SimpleTy != MVT::i64) |
2923 | 0 | return 0; |
2924 | 0 | return fastEmitInst_r(AArch64::CLZXr, &AArch64::GPR64RegClass, Op0); |
2925 | 0 | } |
2926 | | |
2927 | 0 | unsigned fastEmit_ISD_CTLZ_MVT_v8i8_r(MVT RetVT, unsigned Op0) { |
2928 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
2929 | 0 | return 0; |
2930 | 0 | if ((Subtarget->hasNEON())) { |
2931 | 0 | return fastEmitInst_r(AArch64::CLZv8i8, &AArch64::FPR64RegClass, Op0); |
2932 | 0 | } |
2933 | 0 | return 0; |
2934 | 0 | } |
2935 | | |
2936 | 0 | unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
2937 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
2938 | 0 | return 0; |
2939 | 0 | if ((Subtarget->hasNEON())) { |
2940 | 0 | return fastEmitInst_r(AArch64::CLZv16i8, &AArch64::FPR128RegClass, Op0); |
2941 | 0 | } |
2942 | 0 | return 0; |
2943 | 0 | } |
2944 | | |
2945 | 0 | unsigned fastEmit_ISD_CTLZ_MVT_v4i16_r(MVT RetVT, unsigned Op0) { |
2946 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
2947 | 0 | return 0; |
2948 | 0 | if ((Subtarget->hasNEON())) { |
2949 | 0 | return fastEmitInst_r(AArch64::CLZv4i16, &AArch64::FPR64RegClass, Op0); |
2950 | 0 | } |
2951 | 0 | return 0; |
2952 | 0 | } |
2953 | | |
2954 | 0 | unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
2955 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
2956 | 0 | return 0; |
2957 | 0 | if ((Subtarget->hasNEON())) { |
2958 | 0 | return fastEmitInst_r(AArch64::CLZv8i16, &AArch64::FPR128RegClass, Op0); |
2959 | 0 | } |
2960 | 0 | return 0; |
2961 | 0 | } |
2962 | | |
2963 | 0 | unsigned fastEmit_ISD_CTLZ_MVT_v2i32_r(MVT RetVT, unsigned Op0) { |
2964 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
2965 | 0 | return 0; |
2966 | 0 | if ((Subtarget->hasNEON())) { |
2967 | 0 | return fastEmitInst_r(AArch64::CLZv2i32, &AArch64::FPR64RegClass, Op0); |
2968 | 0 | } |
2969 | 0 | return 0; |
2970 | 0 | } |
2971 | | |
2972 | 0 | unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
2973 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
2974 | 0 | return 0; |
2975 | 0 | if ((Subtarget->hasNEON())) { |
2976 | 0 | return fastEmitInst_r(AArch64::CLZv4i32, &AArch64::FPR128RegClass, Op0); |
2977 | 0 | } |
2978 | 0 | return 0; |
2979 | 0 | } |
2980 | | |
2981 | 0 | unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
2982 | 0 | switch (VT.SimpleTy) { |
2983 | 0 | case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0); |
2984 | 0 | case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0); |
2985 | 0 | case MVT::v8i8: return fastEmit_ISD_CTLZ_MVT_v8i8_r(RetVT, Op0); |
2986 | 0 | case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0); |
2987 | 0 | case MVT::v4i16: return fastEmit_ISD_CTLZ_MVT_v4i16_r(RetVT, Op0); |
2988 | 0 | case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0); |
2989 | 0 | case MVT::v2i32: return fastEmit_ISD_CTLZ_MVT_v2i32_r(RetVT, Op0); |
2990 | 0 | case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0); |
2991 | 0 | default: return 0; |
2992 | 0 | } |
2993 | 0 | } |
2994 | | |
2995 | | // FastEmit functions for ISD::CTPOP. |
2996 | | |
2997 | 0 | unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
2998 | 0 | if (RetVT.SimpleTy != MVT::i32) |
2999 | 0 | return 0; |
3000 | 0 | if ((Subtarget->hasCSSC())) { |
3001 | 0 | return fastEmitInst_r(AArch64::CNTWr, &AArch64::GPR32RegClass, Op0); |
3002 | 0 | } |
3003 | 0 | return 0; |
3004 | 0 | } |
3005 | | |
3006 | 0 | unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0) { |
3007 | 0 | if (RetVT.SimpleTy != MVT::i64) |
3008 | 0 | return 0; |
3009 | 0 | if ((Subtarget->hasCSSC())) { |
3010 | 0 | return fastEmitInst_r(AArch64::CNTXr, &AArch64::GPR64RegClass, Op0); |
3011 | 0 | } |
3012 | 0 | return 0; |
3013 | 0 | } |
3014 | | |
3015 | 0 | unsigned fastEmit_ISD_CTPOP_MVT_v8i8_r(MVT RetVT, unsigned Op0) { |
3016 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
3017 | 0 | return 0; |
3018 | 0 | if ((Subtarget->hasNEON())) { |
3019 | 0 | return fastEmitInst_r(AArch64::CNTv8i8, &AArch64::FPR64RegClass, Op0); |
3020 | 0 | } |
3021 | 0 | return 0; |
3022 | 0 | } |
3023 | | |
3024 | 0 | unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
3025 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
3026 | 0 | return 0; |
3027 | 0 | if ((Subtarget->hasNEON())) { |
3028 | 0 | return fastEmitInst_r(AArch64::CNTv16i8, &AArch64::FPR128RegClass, Op0); |
3029 | 0 | } |
3030 | 0 | return 0; |
3031 | 0 | } |
3032 | | |
3033 | 0 | unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0) { |
3034 | 0 | switch (VT.SimpleTy) { |
3035 | 0 | case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0); |
3036 | 0 | case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0); |
3037 | 0 | case MVT::v8i8: return fastEmit_ISD_CTPOP_MVT_v8i8_r(RetVT, Op0); |
3038 | 0 | case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0); |
3039 | 0 | default: return 0; |
3040 | 0 | } |
3041 | 0 | } |
3042 | | |
3043 | | // FastEmit functions for ISD::CTTZ. |
3044 | | |
3045 | 0 | unsigned fastEmit_ISD_CTTZ_MVT_i32_r(MVT RetVT, unsigned Op0) { |
3046 | 0 | if (RetVT.SimpleTy != MVT::i32) |
3047 | 0 | return 0; |
3048 | 0 | if ((Subtarget->hasCSSC())) { |
3049 | 0 | return fastEmitInst_r(AArch64::CTZWr, &AArch64::GPR32RegClass, Op0); |
3050 | 0 | } |
3051 | 0 | return 0; |
3052 | 0 | } |
3053 | | |
3054 | 0 | unsigned fastEmit_ISD_CTTZ_MVT_i64_r(MVT RetVT, unsigned Op0) { |
3055 | 0 | if (RetVT.SimpleTy != MVT::i64) |
3056 | 0 | return 0; |
3057 | 0 | if ((Subtarget->hasCSSC())) { |
3058 | 0 | return fastEmitInst_r(AArch64::CTZXr, &AArch64::GPR64RegClass, Op0); |
3059 | 0 | } |
3060 | 0 | return 0; |
3061 | 0 | } |
3062 | | |
3063 | 0 | unsigned fastEmit_ISD_CTTZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
3064 | 0 | switch (VT.SimpleTy) { |
3065 | 0 | case MVT::i32: return fastEmit_ISD_CTTZ_MVT_i32_r(RetVT, Op0); |
3066 | 0 | case MVT::i64: return fastEmit_ISD_CTTZ_MVT_i64_r(RetVT, Op0); |
3067 | 0 | default: return 0; |
3068 | 0 | } |
3069 | 0 | } |
3070 | | |
3071 | | // FastEmit functions for ISD::FABS. |
3072 | | |
3073 | 0 | unsigned fastEmit_ISD_FABS_MVT_f16_r(MVT RetVT, unsigned Op0) { |
3074 | 0 | if (RetVT.SimpleTy != MVT::f16) |
3075 | 0 | return 0; |
3076 | 0 | if ((Subtarget->hasFullFP16())) { |
3077 | 0 | return fastEmitInst_r(AArch64::FABSHr, &AArch64::FPR16RegClass, Op0); |
3078 | 0 | } |
3079 | 0 | return 0; |
3080 | 0 | } |
3081 | | |
3082 | 0 | unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0) { |
3083 | 0 | if (RetVT.SimpleTy != MVT::f32) |
3084 | 0 | return 0; |
3085 | 0 | if ((Subtarget->hasFPARMv8())) { |
3086 | 0 | return fastEmitInst_r(AArch64::FABSSr, &AArch64::FPR32RegClass, Op0); |
3087 | 0 | } |
3088 | 0 | return 0; |
3089 | 0 | } |
3090 | | |
3091 | 0 | unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0) { |
3092 | 0 | if (RetVT.SimpleTy != MVT::f64) |
3093 | 0 | return 0; |
3094 | 0 | if ((Subtarget->hasFPARMv8())) { |
3095 | 0 | return fastEmitInst_r(AArch64::FABSDr, &AArch64::FPR64RegClass, Op0); |
3096 | 0 | } |
3097 | 0 | return 0; |
3098 | 0 | } |
3099 | | |
3100 | 0 | unsigned fastEmit_ISD_FABS_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
3101 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
3102 | 0 | return 0; |
3103 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
3104 | 0 | return fastEmitInst_r(AArch64::FABSv4f16, &AArch64::FPR64RegClass, Op0); |
3105 | 0 | } |
3106 | 0 | return 0; |
3107 | 0 | } |
3108 | | |
3109 | 0 | unsigned fastEmit_ISD_FABS_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
3110 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
3111 | 0 | return 0; |
3112 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
3113 | 0 | return fastEmitInst_r(AArch64::FABSv8f16, &AArch64::FPR128RegClass, Op0); |
3114 | 0 | } |
3115 | 0 | return 0; |
3116 | 0 | } |
3117 | | |
3118 | 0 | unsigned fastEmit_ISD_FABS_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
3119 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
3120 | 0 | return 0; |
3121 | 0 | if ((Subtarget->hasNEON())) { |
3122 | 0 | return fastEmitInst_r(AArch64::FABSv2f32, &AArch64::FPR64RegClass, Op0); |
3123 | 0 | } |
3124 | 0 | return 0; |
3125 | 0 | } |
3126 | | |
3127 | 0 | unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
3128 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
3129 | 0 | return 0; |
3130 | 0 | if ((Subtarget->hasNEON())) { |
3131 | 0 | return fastEmitInst_r(AArch64::FABSv4f32, &AArch64::FPR128RegClass, Op0); |
3132 | 0 | } |
3133 | 0 | return 0; |
3134 | 0 | } |
3135 | | |
3136 | 0 | unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
3137 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
3138 | 0 | return 0; |
3139 | 0 | if ((Subtarget->hasNEON())) { |
3140 | 0 | return fastEmitInst_r(AArch64::FABSv2f64, &AArch64::FPR128RegClass, Op0); |
3141 | 0 | } |
3142 | 0 | return 0; |
3143 | 0 | } |
3144 | | |
3145 | 0 | unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0) { |
3146 | 0 | switch (VT.SimpleTy) { |
3147 | 0 | case MVT::f16: return fastEmit_ISD_FABS_MVT_f16_r(RetVT, Op0); |
3148 | 0 | case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0); |
3149 | 0 | case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0); |
3150 | 0 | case MVT::v4f16: return fastEmit_ISD_FABS_MVT_v4f16_r(RetVT, Op0); |
3151 | 0 | case MVT::v8f16: return fastEmit_ISD_FABS_MVT_v8f16_r(RetVT, Op0); |
3152 | 0 | case MVT::v2f32: return fastEmit_ISD_FABS_MVT_v2f32_r(RetVT, Op0); |
3153 | 0 | case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0); |
3154 | 0 | case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0); |
3155 | 0 | default: return 0; |
3156 | 0 | } |
3157 | 0 | } |
3158 | | |
3159 | | // FastEmit functions for ISD::FCEIL. |
3160 | | |
3161 | 0 | unsigned fastEmit_ISD_FCEIL_MVT_f16_r(MVT RetVT, unsigned Op0) { |
3162 | 0 | if (RetVT.SimpleTy != MVT::f16) |
3163 | 0 | return 0; |
3164 | 0 | if ((Subtarget->hasFullFP16())) { |
3165 | 0 | return fastEmitInst_r(AArch64::FRINTPHr, &AArch64::FPR16RegClass, Op0); |
3166 | 0 | } |
3167 | 0 | return 0; |
3168 | 0 | } |
3169 | | |
3170 | 0 | unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0) { |
3171 | 0 | if (RetVT.SimpleTy != MVT::f32) |
3172 | 0 | return 0; |
3173 | 0 | if ((Subtarget->hasFPARMv8())) { |
3174 | 0 | return fastEmitInst_r(AArch64::FRINTPSr, &AArch64::FPR32RegClass, Op0); |
3175 | 0 | } |
3176 | 0 | return 0; |
3177 | 0 | } |
3178 | | |
3179 | 0 | unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0) { |
3180 | 0 | if (RetVT.SimpleTy != MVT::f64) |
3181 | 0 | return 0; |
3182 | 0 | if ((Subtarget->hasFPARMv8())) { |
3183 | 0 | return fastEmitInst_r(AArch64::FRINTPDr, &AArch64::FPR64RegClass, Op0); |
3184 | 0 | } |
3185 | 0 | return 0; |
3186 | 0 | } |
3187 | | |
3188 | 0 | unsigned fastEmit_ISD_FCEIL_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
3189 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
3190 | 0 | return 0; |
3191 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
3192 | 0 | return fastEmitInst_r(AArch64::FRINTPv4f16, &AArch64::FPR64RegClass, Op0); |
3193 | 0 | } |
3194 | 0 | return 0; |
3195 | 0 | } |
3196 | | |
3197 | 0 | unsigned fastEmit_ISD_FCEIL_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
3198 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
3199 | 0 | return 0; |
3200 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
3201 | 0 | return fastEmitInst_r(AArch64::FRINTPv8f16, &AArch64::FPR128RegClass, Op0); |
3202 | 0 | } |
3203 | 0 | return 0; |
3204 | 0 | } |
3205 | | |
3206 | 0 | unsigned fastEmit_ISD_FCEIL_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
3207 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
3208 | 0 | return 0; |
3209 | 0 | if ((Subtarget->hasNEON())) { |
3210 | 0 | return fastEmitInst_r(AArch64::FRINTPv2f32, &AArch64::FPR64RegClass, Op0); |
3211 | 0 | } |
3212 | 0 | return 0; |
3213 | 0 | } |
3214 | | |
3215 | 0 | unsigned fastEmit_ISD_FCEIL_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
3216 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
3217 | 0 | return 0; |
3218 | 0 | if ((Subtarget->hasNEON())) { |
3219 | 0 | return fastEmitInst_r(AArch64::FRINTPv4f32, &AArch64::FPR128RegClass, Op0); |
3220 | 0 | } |
3221 | 0 | return 0; |
3222 | 0 | } |
3223 | | |
3224 | 0 | unsigned fastEmit_ISD_FCEIL_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
3225 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
3226 | 0 | return 0; |
3227 | 0 | if ((Subtarget->hasNEON())) { |
3228 | 0 | return fastEmitInst_r(AArch64::FRINTPv2f64, &AArch64::FPR128RegClass, Op0); |
3229 | 0 | } |
3230 | 0 | return 0; |
3231 | 0 | } |
3232 | | |
3233 | 0 | unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0) { |
3234 | 0 | switch (VT.SimpleTy) { |
3235 | 0 | case MVT::f16: return fastEmit_ISD_FCEIL_MVT_f16_r(RetVT, Op0); |
3236 | 0 | case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0); |
3237 | 0 | case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0); |
3238 | 0 | case MVT::v4f16: return fastEmit_ISD_FCEIL_MVT_v4f16_r(RetVT, Op0); |
3239 | 0 | case MVT::v8f16: return fastEmit_ISD_FCEIL_MVT_v8f16_r(RetVT, Op0); |
3240 | 0 | case MVT::v2f32: return fastEmit_ISD_FCEIL_MVT_v2f32_r(RetVT, Op0); |
3241 | 0 | case MVT::v4f32: return fastEmit_ISD_FCEIL_MVT_v4f32_r(RetVT, Op0); |
3242 | 0 | case MVT::v2f64: return fastEmit_ISD_FCEIL_MVT_v2f64_r(RetVT, Op0); |
3243 | 0 | default: return 0; |
3244 | 0 | } |
3245 | 0 | } |
3246 | | |
3247 | | // FastEmit functions for ISD::FFLOOR. |
3248 | | |
3249 | 0 | unsigned fastEmit_ISD_FFLOOR_MVT_f16_r(MVT RetVT, unsigned Op0) { |
3250 | 0 | if (RetVT.SimpleTy != MVT::f16) |
3251 | 0 | return 0; |
3252 | 0 | if ((Subtarget->hasFullFP16())) { |
3253 | 0 | return fastEmitInst_r(AArch64::FRINTMHr, &AArch64::FPR16RegClass, Op0); |
3254 | 0 | } |
3255 | 0 | return 0; |
3256 | 0 | } |
3257 | | |
3258 | 0 | unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0) { |
3259 | 0 | if (RetVT.SimpleTy != MVT::f32) |
3260 | 0 | return 0; |
3261 | 0 | if ((Subtarget->hasFPARMv8())) { |
3262 | 0 | return fastEmitInst_r(AArch64::FRINTMSr, &AArch64::FPR32RegClass, Op0); |
3263 | 0 | } |
3264 | 0 | return 0; |
3265 | 0 | } |
3266 | | |
3267 | 0 | unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0) { |
3268 | 0 | if (RetVT.SimpleTy != MVT::f64) |
3269 | 0 | return 0; |
3270 | 0 | if ((Subtarget->hasFPARMv8())) { |
3271 | 0 | return fastEmitInst_r(AArch64::FRINTMDr, &AArch64::FPR64RegClass, Op0); |
3272 | 0 | } |
3273 | 0 | return 0; |
3274 | 0 | } |
3275 | | |
3276 | 0 | unsigned fastEmit_ISD_FFLOOR_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
3277 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
3278 | 0 | return 0; |
3279 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
3280 | 0 | return fastEmitInst_r(AArch64::FRINTMv4f16, &AArch64::FPR64RegClass, Op0); |
3281 | 0 | } |
3282 | 0 | return 0; |
3283 | 0 | } |
3284 | | |
3285 | 0 | unsigned fastEmit_ISD_FFLOOR_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
3286 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
3287 | 0 | return 0; |
3288 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
3289 | 0 | return fastEmitInst_r(AArch64::FRINTMv8f16, &AArch64::FPR128RegClass, Op0); |
3290 | 0 | } |
3291 | 0 | return 0; |
3292 | 0 | } |
3293 | | |
3294 | 0 | unsigned fastEmit_ISD_FFLOOR_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
3295 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
3296 | 0 | return 0; |
3297 | 0 | if ((Subtarget->hasNEON())) { |
3298 | 0 | return fastEmitInst_r(AArch64::FRINTMv2f32, &AArch64::FPR64RegClass, Op0); |
3299 | 0 | } |
3300 | 0 | return 0; |
3301 | 0 | } |
3302 | | |
3303 | 0 | unsigned fastEmit_ISD_FFLOOR_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
3304 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
3305 | 0 | return 0; |
3306 | 0 | if ((Subtarget->hasNEON())) { |
3307 | 0 | return fastEmitInst_r(AArch64::FRINTMv4f32, &AArch64::FPR128RegClass, Op0); |
3308 | 0 | } |
3309 | 0 | return 0; |
3310 | 0 | } |
3311 | | |
3312 | 0 | unsigned fastEmit_ISD_FFLOOR_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
3313 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
3314 | 0 | return 0; |
3315 | 0 | if ((Subtarget->hasNEON())) { |
3316 | 0 | return fastEmitInst_r(AArch64::FRINTMv2f64, &AArch64::FPR128RegClass, Op0); |
3317 | 0 | } |
3318 | 0 | return 0; |
3319 | 0 | } |
3320 | | |
3321 | 0 | unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0) { |
3322 | 0 | switch (VT.SimpleTy) { |
3323 | 0 | case MVT::f16: return fastEmit_ISD_FFLOOR_MVT_f16_r(RetVT, Op0); |
3324 | 0 | case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0); |
3325 | 0 | case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0); |
3326 | 0 | case MVT::v4f16: return fastEmit_ISD_FFLOOR_MVT_v4f16_r(RetVT, Op0); |
3327 | 0 | case MVT::v8f16: return fastEmit_ISD_FFLOOR_MVT_v8f16_r(RetVT, Op0); |
3328 | 0 | case MVT::v2f32: return fastEmit_ISD_FFLOOR_MVT_v2f32_r(RetVT, Op0); |
3329 | 0 | case MVT::v4f32: return fastEmit_ISD_FFLOOR_MVT_v4f32_r(RetVT, Op0); |
3330 | 0 | case MVT::v2f64: return fastEmit_ISD_FFLOOR_MVT_v2f64_r(RetVT, Op0); |
3331 | 0 | default: return 0; |
3332 | 0 | } |
3333 | 0 | } |
3334 | | |
3335 | | // FastEmit functions for ISD::FNEARBYINT. |
3336 | | |
3337 | 0 | unsigned fastEmit_ISD_FNEARBYINT_MVT_f16_r(MVT RetVT, unsigned Op0) { |
3338 | 0 | if (RetVT.SimpleTy != MVT::f16) |
3339 | 0 | return 0; |
3340 | 0 | if ((Subtarget->hasFullFP16())) { |
3341 | 0 | return fastEmitInst_r(AArch64::FRINTIHr, &AArch64::FPR16RegClass, Op0); |
3342 | 0 | } |
3343 | 0 | return 0; |
3344 | 0 | } |
3345 | | |
3346 | 0 | unsigned fastEmit_ISD_FNEARBYINT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
3347 | 0 | if (RetVT.SimpleTy != MVT::f32) |
3348 | 0 | return 0; |
3349 | 0 | if ((Subtarget->hasFPARMv8())) { |
3350 | 0 | return fastEmitInst_r(AArch64::FRINTISr, &AArch64::FPR32RegClass, Op0); |
3351 | 0 | } |
3352 | 0 | return 0; |
3353 | 0 | } |
3354 | | |
3355 | 0 | unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
3356 | 0 | if (RetVT.SimpleTy != MVT::f64) |
3357 | 0 | return 0; |
3358 | 0 | if ((Subtarget->hasFPARMv8())) { |
3359 | 0 | return fastEmitInst_r(AArch64::FRINTIDr, &AArch64::FPR64RegClass, Op0); |
3360 | 0 | } |
3361 | 0 | return 0; |
3362 | 0 | } |
3363 | | |
3364 | 0 | unsigned fastEmit_ISD_FNEARBYINT_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
3365 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
3366 | 0 | return 0; |
3367 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
3368 | 0 | return fastEmitInst_r(AArch64::FRINTIv4f16, &AArch64::FPR64RegClass, Op0); |
3369 | 0 | } |
3370 | 0 | return 0; |
3371 | 0 | } |
3372 | | |
3373 | 0 | unsigned fastEmit_ISD_FNEARBYINT_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
3374 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
3375 | 0 | return 0; |
3376 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
3377 | 0 | return fastEmitInst_r(AArch64::FRINTIv8f16, &AArch64::FPR128RegClass, Op0); |
3378 | 0 | } |
3379 | 0 | return 0; |
3380 | 0 | } |
3381 | | |
3382 | 0 | unsigned fastEmit_ISD_FNEARBYINT_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
3383 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
3384 | 0 | return 0; |
3385 | 0 | if ((Subtarget->hasNEON())) { |
3386 | 0 | return fastEmitInst_r(AArch64::FRINTIv2f32, &AArch64::FPR64RegClass, Op0); |
3387 | 0 | } |
3388 | 0 | return 0; |
3389 | 0 | } |
3390 | | |
3391 | 0 | unsigned fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
3392 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
3393 | 0 | return 0; |
3394 | 0 | if ((Subtarget->hasNEON())) { |
3395 | 0 | return fastEmitInst_r(AArch64::FRINTIv4f32, &AArch64::FPR128RegClass, Op0); |
3396 | 0 | } |
3397 | 0 | return 0; |
3398 | 0 | } |
3399 | | |
3400 | 0 | unsigned fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
3401 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
3402 | 0 | return 0; |
3403 | 0 | if ((Subtarget->hasNEON())) { |
3404 | 0 | return fastEmitInst_r(AArch64::FRINTIv2f64, &AArch64::FPR128RegClass, Op0); |
3405 | 0 | } |
3406 | 0 | return 0; |
3407 | 0 | } |
3408 | | |
3409 | 0 | unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
3410 | 0 | switch (VT.SimpleTy) { |
3411 | 0 | case MVT::f16: return fastEmit_ISD_FNEARBYINT_MVT_f16_r(RetVT, Op0); |
3412 | 0 | case MVT::f32: return fastEmit_ISD_FNEARBYINT_MVT_f32_r(RetVT, Op0); |
3413 | 0 | case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0); |
3414 | 0 | case MVT::v4f16: return fastEmit_ISD_FNEARBYINT_MVT_v4f16_r(RetVT, Op0); |
3415 | 0 | case MVT::v8f16: return fastEmit_ISD_FNEARBYINT_MVT_v8f16_r(RetVT, Op0); |
3416 | 0 | case MVT::v2f32: return fastEmit_ISD_FNEARBYINT_MVT_v2f32_r(RetVT, Op0); |
3417 | 0 | case MVT::v4f32: return fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(RetVT, Op0); |
3418 | 0 | case MVT::v2f64: return fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(RetVT, Op0); |
3419 | 0 | default: return 0; |
3420 | 0 | } |
3421 | 0 | } |
3422 | | |
3423 | | // FastEmit functions for ISD::FNEG. |
3424 | | |
3425 | 0 | unsigned fastEmit_ISD_FNEG_MVT_f16_r(MVT RetVT, unsigned Op0) { |
3426 | 0 | if (RetVT.SimpleTy != MVT::f16) |
3427 | 0 | return 0; |
3428 | 0 | if ((Subtarget->hasFullFP16())) { |
3429 | 0 | return fastEmitInst_r(AArch64::FNEGHr, &AArch64::FPR16RegClass, Op0); |
3430 | 0 | } |
3431 | 0 | return 0; |
3432 | 0 | } |
3433 | | |
3434 | 0 | unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0) { |
3435 | 0 | if (RetVT.SimpleTy != MVT::f32) |
3436 | 0 | return 0; |
3437 | 0 | if ((Subtarget->hasFPARMv8())) { |
3438 | 0 | return fastEmitInst_r(AArch64::FNEGSr, &AArch64::FPR32RegClass, Op0); |
3439 | 0 | } |
3440 | 0 | return 0; |
3441 | 0 | } |
3442 | | |
3443 | 0 | unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0) { |
3444 | 0 | if (RetVT.SimpleTy != MVT::f64) |
3445 | 0 | return 0; |
3446 | 0 | if ((Subtarget->hasFPARMv8())) { |
3447 | 0 | return fastEmitInst_r(AArch64::FNEGDr, &AArch64::FPR64RegClass, Op0); |
3448 | 0 | } |
3449 | 0 | return 0; |
3450 | 0 | } |
3451 | | |
3452 | 0 | unsigned fastEmit_ISD_FNEG_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
3453 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
3454 | 0 | return 0; |
3455 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
3456 | 0 | return fastEmitInst_r(AArch64::FNEGv4f16, &AArch64::FPR64RegClass, Op0); |
3457 | 0 | } |
3458 | 0 | return 0; |
3459 | 0 | } |
3460 | | |
3461 | 0 | unsigned fastEmit_ISD_FNEG_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
3462 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
3463 | 0 | return 0; |
3464 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
3465 | 0 | return fastEmitInst_r(AArch64::FNEGv8f16, &AArch64::FPR128RegClass, Op0); |
3466 | 0 | } |
3467 | 0 | return 0; |
3468 | 0 | } |
3469 | | |
3470 | 0 | unsigned fastEmit_ISD_FNEG_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
3471 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
3472 | 0 | return 0; |
3473 | 0 | if ((Subtarget->hasNEON())) { |
3474 | 0 | return fastEmitInst_r(AArch64::FNEGv2f32, &AArch64::FPR64RegClass, Op0); |
3475 | 0 | } |
3476 | 0 | return 0; |
3477 | 0 | } |
3478 | | |
3479 | 0 | unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
3480 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
3481 | 0 | return 0; |
3482 | 0 | if ((Subtarget->hasNEON())) { |
3483 | 0 | return fastEmitInst_r(AArch64::FNEGv4f32, &AArch64::FPR128RegClass, Op0); |
3484 | 0 | } |
3485 | 0 | return 0; |
3486 | 0 | } |
3487 | | |
3488 | 0 | unsigned fastEmit_ISD_FNEG_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
3489 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
3490 | 0 | return 0; |
3491 | 0 | if ((Subtarget->hasNEON())) { |
3492 | 0 | return fastEmitInst_r(AArch64::FNEGv2f64, &AArch64::FPR128RegClass, Op0); |
3493 | 0 | } |
3494 | 0 | return 0; |
3495 | 0 | } |
3496 | | |
3497 | 0 | unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0) { |
3498 | 0 | switch (VT.SimpleTy) { |
3499 | 0 | case MVT::f16: return fastEmit_ISD_FNEG_MVT_f16_r(RetVT, Op0); |
3500 | 0 | case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0); |
3501 | 0 | case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0); |
3502 | 0 | case MVT::v4f16: return fastEmit_ISD_FNEG_MVT_v4f16_r(RetVT, Op0); |
3503 | 0 | case MVT::v8f16: return fastEmit_ISD_FNEG_MVT_v8f16_r(RetVT, Op0); |
3504 | 0 | case MVT::v2f32: return fastEmit_ISD_FNEG_MVT_v2f32_r(RetVT, Op0); |
3505 | 0 | case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0); |
3506 | 0 | case MVT::v2f64: return fastEmit_ISD_FNEG_MVT_v2f64_r(RetVT, Op0); |
3507 | 0 | default: return 0; |
3508 | 0 | } |
3509 | 0 | } |
3510 | | |
3511 | | // FastEmit functions for ISD::FP_EXTEND. |
3512 | | |
3513 | 0 | unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(unsigned Op0) { |
3514 | 0 | if ((Subtarget->hasFPARMv8())) { |
3515 | 0 | return fastEmitInst_r(AArch64::FCVTSHr, &AArch64::FPR32RegClass, Op0); |
3516 | 0 | } |
3517 | 0 | return 0; |
3518 | 0 | } |
3519 | | |
3520 | 0 | unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(unsigned Op0) { |
3521 | 0 | if ((Subtarget->hasFPARMv8())) { |
3522 | 0 | return fastEmitInst_r(AArch64::FCVTDHr, &AArch64::FPR64RegClass, Op0); |
3523 | 0 | } |
3524 | 0 | return 0; |
3525 | 0 | } |
3526 | | |
3527 | 0 | unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_r(MVT RetVT, unsigned Op0) { |
3528 | 0 | switch (RetVT.SimpleTy) { |
3529 | 0 | case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(Op0); |
3530 | 0 | case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(Op0); |
3531 | 0 | default: return 0; |
3532 | 0 | } |
3533 | 0 | } |
3534 | | |
3535 | 0 | unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0) { |
3536 | 0 | if (RetVT.SimpleTy != MVT::f64) |
3537 | 0 | return 0; |
3538 | 0 | if ((Subtarget->hasFPARMv8())) { |
3539 | 0 | return fastEmitInst_r(AArch64::FCVTDSr, &AArch64::FPR64RegClass, Op0); |
3540 | 0 | } |
3541 | 0 | return 0; |
3542 | 0 | } |
3543 | | |
3544 | 0 | unsigned fastEmit_ISD_FP_EXTEND_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
3545 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
3546 | 0 | return 0; |
3547 | 0 | return fastEmitInst_r(AArch64::FCVTLv4i16, &AArch64::FPR128RegClass, Op0); |
3548 | 0 | } |
3549 | | |
3550 | 0 | unsigned fastEmit_ISD_FP_EXTEND_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
3551 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
3552 | 0 | return 0; |
3553 | 0 | return fastEmitInst_r(AArch64::FCVTLv2i32, &AArch64::FPR128RegClass, Op0); |
3554 | 0 | } |
3555 | | |
3556 | 0 | unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) { |
3557 | 0 | switch (VT.SimpleTy) { |
3558 | 0 | case MVT::f16: return fastEmit_ISD_FP_EXTEND_MVT_f16_r(RetVT, Op0); |
3559 | 0 | case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0); |
3560 | 0 | case MVT::v4f16: return fastEmit_ISD_FP_EXTEND_MVT_v4f16_r(RetVT, Op0); |
3561 | 0 | case MVT::v2f32: return fastEmit_ISD_FP_EXTEND_MVT_v2f32_r(RetVT, Op0); |
3562 | 0 | default: return 0; |
3563 | 0 | } |
3564 | 0 | } |
3565 | | |
3566 | | // FastEmit functions for ISD::FP_ROUND. |
3567 | | |
3568 | 0 | unsigned fastEmit_ISD_FP_ROUND_MVT_f32_r(MVT RetVT, unsigned Op0) { |
3569 | 0 | if (RetVT.SimpleTy != MVT::f16) |
3570 | 0 | return 0; |
3571 | 0 | if ((Subtarget->hasFPARMv8())) { |
3572 | 0 | return fastEmitInst_r(AArch64::FCVTHSr, &AArch64::FPR16RegClass, Op0); |
3573 | 0 | } |
3574 | 0 | return 0; |
3575 | 0 | } |
3576 | | |
3577 | 0 | unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(unsigned Op0) { |
3578 | 0 | if ((Subtarget->hasFPARMv8())) { |
3579 | 0 | return fastEmitInst_r(AArch64::FCVTHDr, &AArch64::FPR16RegClass, Op0); |
3580 | 0 | } |
3581 | 0 | return 0; |
3582 | 0 | } |
3583 | | |
3584 | 0 | unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(unsigned Op0) { |
3585 | 0 | if ((Subtarget->hasFPARMv8())) { |
3586 | 0 | return fastEmitInst_r(AArch64::FCVTSDr, &AArch64::FPR32RegClass, Op0); |
3587 | 0 | } |
3588 | 0 | return 0; |
3589 | 0 | } |
3590 | | |
3591 | 0 | unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0) { |
3592 | 0 | switch (RetVT.SimpleTy) { |
3593 | 0 | case MVT::f16: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(Op0); |
3594 | 0 | case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(Op0); |
3595 | 0 | default: return 0; |
3596 | 0 | } |
3597 | 0 | } |
3598 | | |
3599 | 0 | unsigned fastEmit_ISD_FP_ROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
3600 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
3601 | 0 | return 0; |
3602 | 0 | return fastEmitInst_r(AArch64::FCVTNv4i16, &AArch64::FPR64RegClass, Op0); |
3603 | 0 | } |
3604 | | |
3605 | 0 | unsigned fastEmit_ISD_FP_ROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
3606 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
3607 | 0 | return 0; |
3608 | 0 | return fastEmitInst_r(AArch64::FCVTNv2i32, &AArch64::FPR64RegClass, Op0); |
3609 | 0 | } |
3610 | | |
3611 | 0 | unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0) { |
3612 | 0 | switch (VT.SimpleTy) { |
3613 | 0 | case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f32_r(RetVT, Op0); |
3614 | 0 | case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0); |
3615 | 0 | case MVT::v4f32: return fastEmit_ISD_FP_ROUND_MVT_v4f32_r(RetVT, Op0); |
3616 | 0 | case MVT::v2f64: return fastEmit_ISD_FP_ROUND_MVT_v2f64_r(RetVT, Op0); |
3617 | 0 | default: return 0; |
3618 | 0 | } |
3619 | 0 | } |
3620 | | |
3621 | | // FastEmit functions for ISD::FP_TO_SINT. |
3622 | | |
3623 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_f16_MVT_i32_r(unsigned Op0) { |
3624 | 0 | if ((Subtarget->hasFullFP16())) { |
3625 | 0 | return fastEmitInst_r(AArch64::FCVTZSUWHr, &AArch64::GPR32RegClass, Op0); |
3626 | 0 | } |
3627 | 0 | return 0; |
3628 | 0 | } |
3629 | | |
3630 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_f16_MVT_i64_r(unsigned Op0) { |
3631 | 0 | if ((Subtarget->hasFullFP16())) { |
3632 | 0 | return fastEmitInst_r(AArch64::FCVTZSUXHr, &AArch64::GPR64RegClass, Op0); |
3633 | 0 | } |
3634 | 0 | return 0; |
3635 | 0 | } |
3636 | | |
3637 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_f16_r(MVT RetVT, unsigned Op0) { |
3638 | 0 | switch (RetVT.SimpleTy) { |
3639 | 0 | case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f16_MVT_i32_r(Op0); |
3640 | 0 | case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f16_MVT_i64_r(Op0); |
3641 | 0 | default: return 0; |
3642 | 0 | } |
3643 | 0 | } |
3644 | | |
3645 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(unsigned Op0) { |
3646 | 0 | if ((Subtarget->hasFPARMv8())) { |
3647 | 0 | return fastEmitInst_r(AArch64::FCVTZSUWSr, &AArch64::GPR32RegClass, Op0); |
3648 | 0 | } |
3649 | 0 | return 0; |
3650 | 0 | } |
3651 | | |
3652 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(unsigned Op0) { |
3653 | 0 | if ((Subtarget->hasFPARMv8())) { |
3654 | 0 | return fastEmitInst_r(AArch64::FCVTZSUXSr, &AArch64::GPR64RegClass, Op0); |
3655 | 0 | } |
3656 | 0 | return 0; |
3657 | 0 | } |
3658 | | |
3659 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
3660 | 0 | switch (RetVT.SimpleTy) { |
3661 | 0 | case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(Op0); |
3662 | 0 | case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(Op0); |
3663 | 0 | default: return 0; |
3664 | 0 | } |
3665 | 0 | } |
3666 | | |
3667 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(unsigned Op0) { |
3668 | 0 | if ((Subtarget->hasFPARMv8())) { |
3669 | 0 | return fastEmitInst_r(AArch64::FCVTZSUWDr, &AArch64::GPR32RegClass, Op0); |
3670 | 0 | } |
3671 | 0 | return 0; |
3672 | 0 | } |
3673 | | |
3674 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(unsigned Op0) { |
3675 | 0 | if ((Subtarget->hasFPARMv8())) { |
3676 | 0 | return fastEmitInst_r(AArch64::FCVTZSUXDr, &AArch64::GPR64RegClass, Op0); |
3677 | 0 | } |
3678 | 0 | return 0; |
3679 | 0 | } |
3680 | | |
3681 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
3682 | 0 | switch (RetVT.SimpleTy) { |
3683 | 0 | case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(Op0); |
3684 | 0 | case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(Op0); |
3685 | 0 | default: return 0; |
3686 | 0 | } |
3687 | 0 | } |
3688 | | |
3689 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
3690 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
3691 | 0 | return 0; |
3692 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
3693 | 0 | return fastEmitInst_r(AArch64::FCVTZSv4f16, &AArch64::FPR64RegClass, Op0); |
3694 | 0 | } |
3695 | 0 | return 0; |
3696 | 0 | } |
3697 | | |
3698 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
3699 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
3700 | 0 | return 0; |
3701 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
3702 | 0 | return fastEmitInst_r(AArch64::FCVTZSv8f16, &AArch64::FPR128RegClass, Op0); |
3703 | 0 | } |
3704 | 0 | return 0; |
3705 | 0 | } |
3706 | | |
3707 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
3708 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
3709 | 0 | return 0; |
3710 | 0 | if ((Subtarget->hasNEON())) { |
3711 | 0 | return fastEmitInst_r(AArch64::FCVTZSv2f32, &AArch64::FPR64RegClass, Op0); |
3712 | 0 | } |
3713 | 0 | return 0; |
3714 | 0 | } |
3715 | | |
3716 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
3717 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
3718 | 0 | return 0; |
3719 | 0 | if ((Subtarget->hasNEON())) { |
3720 | 0 | return fastEmitInst_r(AArch64::FCVTZSv4f32, &AArch64::FPR128RegClass, Op0); |
3721 | 0 | } |
3722 | 0 | return 0; |
3723 | 0 | } |
3724 | | |
3725 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
3726 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
3727 | 0 | return 0; |
3728 | 0 | if ((Subtarget->hasNEON())) { |
3729 | 0 | return fastEmitInst_r(AArch64::FCVTZSv2f64, &AArch64::FPR128RegClass, Op0); |
3730 | 0 | } |
3731 | 0 | return 0; |
3732 | 0 | } |
3733 | | |
3734 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
3735 | 0 | switch (VT.SimpleTy) { |
3736 | 0 | case MVT::f16: return fastEmit_ISD_FP_TO_SINT_MVT_f16_r(RetVT, Op0); |
3737 | 0 | case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0); |
3738 | 0 | case MVT::f64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_r(RetVT, Op0); |
3739 | 0 | case MVT::v4f16: return fastEmit_ISD_FP_TO_SINT_MVT_v4f16_r(RetVT, Op0); |
3740 | 0 | case MVT::v8f16: return fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(RetVT, Op0); |
3741 | 0 | case MVT::v2f32: return fastEmit_ISD_FP_TO_SINT_MVT_v2f32_r(RetVT, Op0); |
3742 | 0 | case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0); |
3743 | 0 | case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0); |
3744 | 0 | default: return 0; |
3745 | 0 | } |
3746 | 0 | } |
3747 | | |
3748 | | // FastEmit functions for ISD::FP_TO_UINT. |
3749 | | |
3750 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_f16_MVT_i32_r(unsigned Op0) { |
3751 | 0 | if ((Subtarget->hasFullFP16())) { |
3752 | 0 | return fastEmitInst_r(AArch64::FCVTZUUWHr, &AArch64::GPR32RegClass, Op0); |
3753 | 0 | } |
3754 | 0 | return 0; |
3755 | 0 | } |
3756 | | |
3757 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_f16_MVT_i64_r(unsigned Op0) { |
3758 | 0 | if ((Subtarget->hasFullFP16())) { |
3759 | 0 | return fastEmitInst_r(AArch64::FCVTZUUXHr, &AArch64::GPR64RegClass, Op0); |
3760 | 0 | } |
3761 | 0 | return 0; |
3762 | 0 | } |
3763 | | |
3764 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_f16_r(MVT RetVT, unsigned Op0) { |
3765 | 0 | switch (RetVT.SimpleTy) { |
3766 | 0 | case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f16_MVT_i32_r(Op0); |
3767 | 0 | case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f16_MVT_i64_r(Op0); |
3768 | 0 | default: return 0; |
3769 | 0 | } |
3770 | 0 | } |
3771 | | |
3772 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(unsigned Op0) { |
3773 | 0 | if ((Subtarget->hasFPARMv8())) { |
3774 | 0 | return fastEmitInst_r(AArch64::FCVTZUUWSr, &AArch64::GPR32RegClass, Op0); |
3775 | 0 | } |
3776 | 0 | return 0; |
3777 | 0 | } |
3778 | | |
3779 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(unsigned Op0) { |
3780 | 0 | if ((Subtarget->hasFPARMv8())) { |
3781 | 0 | return fastEmitInst_r(AArch64::FCVTZUUXSr, &AArch64::GPR64RegClass, Op0); |
3782 | 0 | } |
3783 | 0 | return 0; |
3784 | 0 | } |
3785 | | |
3786 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
3787 | 0 | switch (RetVT.SimpleTy) { |
3788 | 0 | case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(Op0); |
3789 | 0 | case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(Op0); |
3790 | 0 | default: return 0; |
3791 | 0 | } |
3792 | 0 | } |
3793 | | |
3794 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(unsigned Op0) { |
3795 | 0 | if ((Subtarget->hasFPARMv8())) { |
3796 | 0 | return fastEmitInst_r(AArch64::FCVTZUUWDr, &AArch64::GPR32RegClass, Op0); |
3797 | 0 | } |
3798 | 0 | return 0; |
3799 | 0 | } |
3800 | | |
3801 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(unsigned Op0) { |
3802 | 0 | if ((Subtarget->hasFPARMv8())) { |
3803 | 0 | return fastEmitInst_r(AArch64::FCVTZUUXDr, &AArch64::GPR64RegClass, Op0); |
3804 | 0 | } |
3805 | 0 | return 0; |
3806 | 0 | } |
3807 | | |
3808 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
3809 | 0 | switch (RetVT.SimpleTy) { |
3810 | 0 | case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(Op0); |
3811 | 0 | case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(Op0); |
3812 | 0 | default: return 0; |
3813 | 0 | } |
3814 | 0 | } |
3815 | | |
3816 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
3817 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
3818 | 0 | return 0; |
3819 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
3820 | 0 | return fastEmitInst_r(AArch64::FCVTZUv4f16, &AArch64::FPR64RegClass, Op0); |
3821 | 0 | } |
3822 | 0 | return 0; |
3823 | 0 | } |
3824 | | |
3825 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
3826 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
3827 | 0 | return 0; |
3828 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
3829 | 0 | return fastEmitInst_r(AArch64::FCVTZUv8f16, &AArch64::FPR128RegClass, Op0); |
3830 | 0 | } |
3831 | 0 | return 0; |
3832 | 0 | } |
3833 | | |
3834 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
3835 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
3836 | 0 | return 0; |
3837 | 0 | if ((Subtarget->hasNEON())) { |
3838 | 0 | return fastEmitInst_r(AArch64::FCVTZUv2f32, &AArch64::FPR64RegClass, Op0); |
3839 | 0 | } |
3840 | 0 | return 0; |
3841 | 0 | } |
3842 | | |
3843 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
3844 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
3845 | 0 | return 0; |
3846 | 0 | if ((Subtarget->hasNEON())) { |
3847 | 0 | return fastEmitInst_r(AArch64::FCVTZUv4f32, &AArch64::FPR128RegClass, Op0); |
3848 | 0 | } |
3849 | 0 | return 0; |
3850 | 0 | } |
3851 | | |
3852 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
3853 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
3854 | 0 | return 0; |
3855 | 0 | if ((Subtarget->hasNEON())) { |
3856 | 0 | return fastEmitInst_r(AArch64::FCVTZUv2f64, &AArch64::FPR128RegClass, Op0); |
3857 | 0 | } |
3858 | 0 | return 0; |
3859 | 0 | } |
3860 | | |
3861 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
3862 | 0 | switch (VT.SimpleTy) { |
3863 | 0 | case MVT::f16: return fastEmit_ISD_FP_TO_UINT_MVT_f16_r(RetVT, Op0); |
3864 | 0 | case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0); |
3865 | 0 | case MVT::f64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_r(RetVT, Op0); |
3866 | 0 | case MVT::v4f16: return fastEmit_ISD_FP_TO_UINT_MVT_v4f16_r(RetVT, Op0); |
3867 | 0 | case MVT::v8f16: return fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(RetVT, Op0); |
3868 | 0 | case MVT::v2f32: return fastEmit_ISD_FP_TO_UINT_MVT_v2f32_r(RetVT, Op0); |
3869 | 0 | case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0); |
3870 | 0 | case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0); |
3871 | 0 | default: return 0; |
3872 | 0 | } |
3873 | 0 | } |
3874 | | |
3875 | | // FastEmit functions for ISD::FRINT. |
3876 | | |
3877 | 0 | unsigned fastEmit_ISD_FRINT_MVT_f16_r(MVT RetVT, unsigned Op0) { |
3878 | 0 | if (RetVT.SimpleTy != MVT::f16) |
3879 | 0 | return 0; |
3880 | 0 | if ((Subtarget->hasFullFP16())) { |
3881 | 0 | return fastEmitInst_r(AArch64::FRINTXHr, &AArch64::FPR16RegClass, Op0); |
3882 | 0 | } |
3883 | 0 | return 0; |
3884 | 0 | } |
3885 | | |
3886 | 0 | unsigned fastEmit_ISD_FRINT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
3887 | 0 | if (RetVT.SimpleTy != MVT::f32) |
3888 | 0 | return 0; |
3889 | 0 | if ((Subtarget->hasFPARMv8())) { |
3890 | 0 | return fastEmitInst_r(AArch64::FRINTXSr, &AArch64::FPR32RegClass, Op0); |
3891 | 0 | } |
3892 | 0 | return 0; |
3893 | 0 | } |
3894 | | |
3895 | 0 | unsigned fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
3896 | 0 | if (RetVT.SimpleTy != MVT::f64) |
3897 | 0 | return 0; |
3898 | 0 | if ((Subtarget->hasFPARMv8())) { |
3899 | 0 | return fastEmitInst_r(AArch64::FRINTXDr, &AArch64::FPR64RegClass, Op0); |
3900 | 0 | } |
3901 | 0 | return 0; |
3902 | 0 | } |
3903 | | |
3904 | 0 | unsigned fastEmit_ISD_FRINT_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
3905 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
3906 | 0 | return 0; |
3907 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
3908 | 0 | return fastEmitInst_r(AArch64::FRINTXv4f16, &AArch64::FPR64RegClass, Op0); |
3909 | 0 | } |
3910 | 0 | return 0; |
3911 | 0 | } |
3912 | | |
3913 | 0 | unsigned fastEmit_ISD_FRINT_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
3914 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
3915 | 0 | return 0; |
3916 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
3917 | 0 | return fastEmitInst_r(AArch64::FRINTXv8f16, &AArch64::FPR128RegClass, Op0); |
3918 | 0 | } |
3919 | 0 | return 0; |
3920 | 0 | } |
3921 | | |
3922 | 0 | unsigned fastEmit_ISD_FRINT_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
3923 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
3924 | 0 | return 0; |
3925 | 0 | if ((Subtarget->hasNEON())) { |
3926 | 0 | return fastEmitInst_r(AArch64::FRINTXv2f32, &AArch64::FPR64RegClass, Op0); |
3927 | 0 | } |
3928 | 0 | return 0; |
3929 | 0 | } |
3930 | | |
3931 | 0 | unsigned fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
3932 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
3933 | 0 | return 0; |
3934 | 0 | if ((Subtarget->hasNEON())) { |
3935 | 0 | return fastEmitInst_r(AArch64::FRINTXv4f32, &AArch64::FPR128RegClass, Op0); |
3936 | 0 | } |
3937 | 0 | return 0; |
3938 | 0 | } |
3939 | | |
3940 | 0 | unsigned fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
3941 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
3942 | 0 | return 0; |
3943 | 0 | if ((Subtarget->hasNEON())) { |
3944 | 0 | return fastEmitInst_r(AArch64::FRINTXv2f64, &AArch64::FPR128RegClass, Op0); |
3945 | 0 | } |
3946 | 0 | return 0; |
3947 | 0 | } |
3948 | | |
3949 | 0 | unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
3950 | 0 | switch (VT.SimpleTy) { |
3951 | 0 | case MVT::f16: return fastEmit_ISD_FRINT_MVT_f16_r(RetVT, Op0); |
3952 | 0 | case MVT::f32: return fastEmit_ISD_FRINT_MVT_f32_r(RetVT, Op0); |
3953 | 0 | case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0); |
3954 | 0 | case MVT::v4f16: return fastEmit_ISD_FRINT_MVT_v4f16_r(RetVT, Op0); |
3955 | 0 | case MVT::v8f16: return fastEmit_ISD_FRINT_MVT_v8f16_r(RetVT, Op0); |
3956 | 0 | case MVT::v2f32: return fastEmit_ISD_FRINT_MVT_v2f32_r(RetVT, Op0); |
3957 | 0 | case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0); |
3958 | 0 | case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0); |
3959 | 0 | default: return 0; |
3960 | 0 | } |
3961 | 0 | } |
3962 | | |
3963 | | // FastEmit functions for ISD::FROUND. |
3964 | | |
3965 | 0 | unsigned fastEmit_ISD_FROUND_MVT_f16_r(MVT RetVT, unsigned Op0) { |
3966 | 0 | if (RetVT.SimpleTy != MVT::f16) |
3967 | 0 | return 0; |
3968 | 0 | if ((Subtarget->hasFullFP16())) { |
3969 | 0 | return fastEmitInst_r(AArch64::FRINTAHr, &AArch64::FPR16RegClass, Op0); |
3970 | 0 | } |
3971 | 0 | return 0; |
3972 | 0 | } |
3973 | | |
3974 | 0 | unsigned fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0) { |
3975 | 0 | if (RetVT.SimpleTy != MVT::f32) |
3976 | 0 | return 0; |
3977 | 0 | if ((Subtarget->hasFPARMv8())) { |
3978 | 0 | return fastEmitInst_r(AArch64::FRINTASr, &AArch64::FPR32RegClass, Op0); |
3979 | 0 | } |
3980 | 0 | return 0; |
3981 | 0 | } |
3982 | | |
3983 | 0 | unsigned fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0) { |
3984 | 0 | if (RetVT.SimpleTy != MVT::f64) |
3985 | 0 | return 0; |
3986 | 0 | if ((Subtarget->hasFPARMv8())) { |
3987 | 0 | return fastEmitInst_r(AArch64::FRINTADr, &AArch64::FPR64RegClass, Op0); |
3988 | 0 | } |
3989 | 0 | return 0; |
3990 | 0 | } |
3991 | | |
3992 | 0 | unsigned fastEmit_ISD_FROUND_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
3993 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
3994 | 0 | return 0; |
3995 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
3996 | 0 | return fastEmitInst_r(AArch64::FRINTAv4f16, &AArch64::FPR64RegClass, Op0); |
3997 | 0 | } |
3998 | 0 | return 0; |
3999 | 0 | } |
4000 | | |
4001 | 0 | unsigned fastEmit_ISD_FROUND_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
4002 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
4003 | 0 | return 0; |
4004 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
4005 | 0 | return fastEmitInst_r(AArch64::FRINTAv8f16, &AArch64::FPR128RegClass, Op0); |
4006 | 0 | } |
4007 | 0 | return 0; |
4008 | 0 | } |
4009 | | |
4010 | 0 | unsigned fastEmit_ISD_FROUND_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
4011 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
4012 | 0 | return 0; |
4013 | 0 | if ((Subtarget->hasNEON())) { |
4014 | 0 | return fastEmitInst_r(AArch64::FRINTAv2f32, &AArch64::FPR64RegClass, Op0); |
4015 | 0 | } |
4016 | 0 | return 0; |
4017 | 0 | } |
4018 | | |
4019 | 0 | unsigned fastEmit_ISD_FROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
4020 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
4021 | 0 | return 0; |
4022 | 0 | if ((Subtarget->hasNEON())) { |
4023 | 0 | return fastEmitInst_r(AArch64::FRINTAv4f32, &AArch64::FPR128RegClass, Op0); |
4024 | 0 | } |
4025 | 0 | return 0; |
4026 | 0 | } |
4027 | | |
4028 | 0 | unsigned fastEmit_ISD_FROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
4029 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
4030 | 0 | return 0; |
4031 | 0 | if ((Subtarget->hasNEON())) { |
4032 | 0 | return fastEmitInst_r(AArch64::FRINTAv2f64, &AArch64::FPR128RegClass, Op0); |
4033 | 0 | } |
4034 | 0 | return 0; |
4035 | 0 | } |
4036 | | |
4037 | 0 | unsigned fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, unsigned Op0) { |
4038 | 0 | switch (VT.SimpleTy) { |
4039 | 0 | case MVT::f16: return fastEmit_ISD_FROUND_MVT_f16_r(RetVT, Op0); |
4040 | 0 | case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0); |
4041 | 0 | case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0); |
4042 | 0 | case MVT::v4f16: return fastEmit_ISD_FROUND_MVT_v4f16_r(RetVT, Op0); |
4043 | 0 | case MVT::v8f16: return fastEmit_ISD_FROUND_MVT_v8f16_r(RetVT, Op0); |
4044 | 0 | case MVT::v2f32: return fastEmit_ISD_FROUND_MVT_v2f32_r(RetVT, Op0); |
4045 | 0 | case MVT::v4f32: return fastEmit_ISD_FROUND_MVT_v4f32_r(RetVT, Op0); |
4046 | 0 | case MVT::v2f64: return fastEmit_ISD_FROUND_MVT_v2f64_r(RetVT, Op0); |
4047 | 0 | default: return 0; |
4048 | 0 | } |
4049 | 0 | } |
4050 | | |
4051 | | // FastEmit functions for ISD::FROUNDEVEN. |
4052 | | |
4053 | 0 | unsigned fastEmit_ISD_FROUNDEVEN_MVT_f16_r(MVT RetVT, unsigned Op0) { |
4054 | 0 | if (RetVT.SimpleTy != MVT::f16) |
4055 | 0 | return 0; |
4056 | 0 | if ((Subtarget->hasFullFP16())) { |
4057 | 0 | return fastEmitInst_r(AArch64::FRINTNHr, &AArch64::FPR16RegClass, Op0); |
4058 | 0 | } |
4059 | 0 | return 0; |
4060 | 0 | } |
4061 | | |
4062 | 0 | unsigned fastEmit_ISD_FROUNDEVEN_MVT_f32_r(MVT RetVT, unsigned Op0) { |
4063 | 0 | if (RetVT.SimpleTy != MVT::f32) |
4064 | 0 | return 0; |
4065 | 0 | if ((Subtarget->hasFPARMv8())) { |
4066 | 0 | return fastEmitInst_r(AArch64::FRINTNSr, &AArch64::FPR32RegClass, Op0); |
4067 | 0 | } |
4068 | 0 | return 0; |
4069 | 0 | } |
4070 | | |
4071 | 0 | unsigned fastEmit_ISD_FROUNDEVEN_MVT_f64_r(MVT RetVT, unsigned Op0) { |
4072 | 0 | if (RetVT.SimpleTy != MVT::f64) |
4073 | 0 | return 0; |
4074 | 0 | if ((Subtarget->hasFPARMv8())) { |
4075 | 0 | return fastEmitInst_r(AArch64::FRINTNDr, &AArch64::FPR64RegClass, Op0); |
4076 | 0 | } |
4077 | 0 | return 0; |
4078 | 0 | } |
4079 | | |
4080 | 0 | unsigned fastEmit_ISD_FROUNDEVEN_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
4081 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
4082 | 0 | return 0; |
4083 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
4084 | 0 | return fastEmitInst_r(AArch64::FRINTNv4f16, &AArch64::FPR64RegClass, Op0); |
4085 | 0 | } |
4086 | 0 | return 0; |
4087 | 0 | } |
4088 | | |
4089 | 0 | unsigned fastEmit_ISD_FROUNDEVEN_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
4090 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
4091 | 0 | return 0; |
4092 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
4093 | 0 | return fastEmitInst_r(AArch64::FRINTNv8f16, &AArch64::FPR128RegClass, Op0); |
4094 | 0 | } |
4095 | 0 | return 0; |
4096 | 0 | } |
4097 | | |
4098 | 0 | unsigned fastEmit_ISD_FROUNDEVEN_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
4099 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
4100 | 0 | return 0; |
4101 | 0 | if ((Subtarget->hasNEON())) { |
4102 | 0 | return fastEmitInst_r(AArch64::FRINTNv2f32, &AArch64::FPR64RegClass, Op0); |
4103 | 0 | } |
4104 | 0 | return 0; |
4105 | 0 | } |
4106 | | |
4107 | 0 | unsigned fastEmit_ISD_FROUNDEVEN_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
4108 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
4109 | 0 | return 0; |
4110 | 0 | if ((Subtarget->hasNEON())) { |
4111 | 0 | return fastEmitInst_r(AArch64::FRINTNv4f32, &AArch64::FPR128RegClass, Op0); |
4112 | 0 | } |
4113 | 0 | return 0; |
4114 | 0 | } |
4115 | | |
4116 | 0 | unsigned fastEmit_ISD_FROUNDEVEN_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
4117 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
4118 | 0 | return 0; |
4119 | 0 | if ((Subtarget->hasNEON())) { |
4120 | 0 | return fastEmitInst_r(AArch64::FRINTNv2f64, &AArch64::FPR128RegClass, Op0); |
4121 | 0 | } |
4122 | 0 | return 0; |
4123 | 0 | } |
4124 | | |
4125 | 0 | unsigned fastEmit_ISD_FROUNDEVEN_r(MVT VT, MVT RetVT, unsigned Op0) { |
4126 | 0 | switch (VT.SimpleTy) { |
4127 | 0 | case MVT::f16: return fastEmit_ISD_FROUNDEVEN_MVT_f16_r(RetVT, Op0); |
4128 | 0 | case MVT::f32: return fastEmit_ISD_FROUNDEVEN_MVT_f32_r(RetVT, Op0); |
4129 | 0 | case MVT::f64: return fastEmit_ISD_FROUNDEVEN_MVT_f64_r(RetVT, Op0); |
4130 | 0 | case MVT::v4f16: return fastEmit_ISD_FROUNDEVEN_MVT_v4f16_r(RetVT, Op0); |
4131 | 0 | case MVT::v8f16: return fastEmit_ISD_FROUNDEVEN_MVT_v8f16_r(RetVT, Op0); |
4132 | 0 | case MVT::v2f32: return fastEmit_ISD_FROUNDEVEN_MVT_v2f32_r(RetVT, Op0); |
4133 | 0 | case MVT::v4f32: return fastEmit_ISD_FROUNDEVEN_MVT_v4f32_r(RetVT, Op0); |
4134 | 0 | case MVT::v2f64: return fastEmit_ISD_FROUNDEVEN_MVT_v2f64_r(RetVT, Op0); |
4135 | 0 | default: return 0; |
4136 | 0 | } |
4137 | 0 | } |
4138 | | |
4139 | | // FastEmit functions for ISD::FSQRT. |
4140 | | |
4141 | 0 | unsigned fastEmit_ISD_FSQRT_MVT_f16_r(MVT RetVT, unsigned Op0) { |
4142 | 0 | if (RetVT.SimpleTy != MVT::f16) |
4143 | 0 | return 0; |
4144 | 0 | if ((Subtarget->hasFullFP16())) { |
4145 | 0 | return fastEmitInst_r(AArch64::FSQRTHr, &AArch64::FPR16RegClass, Op0); |
4146 | 0 | } |
4147 | 0 | return 0; |
4148 | 0 | } |
4149 | | |
4150 | 0 | unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
4151 | 0 | if (RetVT.SimpleTy != MVT::f32) |
4152 | 0 | return 0; |
4153 | 0 | if ((Subtarget->hasFPARMv8())) { |
4154 | 0 | return fastEmitInst_r(AArch64::FSQRTSr, &AArch64::FPR32RegClass, Op0); |
4155 | 0 | } |
4156 | 0 | return 0; |
4157 | 0 | } |
4158 | | |
4159 | 0 | unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
4160 | 0 | if (RetVT.SimpleTy != MVT::f64) |
4161 | 0 | return 0; |
4162 | 0 | if ((Subtarget->hasFPARMv8())) { |
4163 | 0 | return fastEmitInst_r(AArch64::FSQRTDr, &AArch64::FPR64RegClass, Op0); |
4164 | 0 | } |
4165 | 0 | return 0; |
4166 | 0 | } |
4167 | | |
4168 | 0 | unsigned fastEmit_ISD_FSQRT_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
4169 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
4170 | 0 | return 0; |
4171 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
4172 | 0 | return fastEmitInst_r(AArch64::FSQRTv4f16, &AArch64::FPR64RegClass, Op0); |
4173 | 0 | } |
4174 | 0 | return 0; |
4175 | 0 | } |
4176 | | |
4177 | 0 | unsigned fastEmit_ISD_FSQRT_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
4178 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
4179 | 0 | return 0; |
4180 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
4181 | 0 | return fastEmitInst_r(AArch64::FSQRTv8f16, &AArch64::FPR128RegClass, Op0); |
4182 | 0 | } |
4183 | 0 | return 0; |
4184 | 0 | } |
4185 | | |
4186 | 0 | unsigned fastEmit_ISD_FSQRT_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
4187 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
4188 | 0 | return 0; |
4189 | 0 | if ((Subtarget->hasNEON())) { |
4190 | 0 | return fastEmitInst_r(AArch64::FSQRTv2f32, &AArch64::FPR64RegClass, Op0); |
4191 | 0 | } |
4192 | 0 | return 0; |
4193 | 0 | } |
4194 | | |
4195 | 0 | unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
4196 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
4197 | 0 | return 0; |
4198 | 0 | if ((Subtarget->hasNEON())) { |
4199 | 0 | return fastEmitInst_r(AArch64::FSQRTv4f32, &AArch64::FPR128RegClass, Op0); |
4200 | 0 | } |
4201 | 0 | return 0; |
4202 | 0 | } |
4203 | | |
4204 | 0 | unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
4205 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
4206 | 0 | return 0; |
4207 | 0 | if ((Subtarget->hasNEON())) { |
4208 | 0 | return fastEmitInst_r(AArch64::FSQRTv2f64, &AArch64::FPR128RegClass, Op0); |
4209 | 0 | } |
4210 | 0 | return 0; |
4211 | 0 | } |
4212 | | |
4213 | 0 | unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0) { |
4214 | 0 | switch (VT.SimpleTy) { |
4215 | 0 | case MVT::f16: return fastEmit_ISD_FSQRT_MVT_f16_r(RetVT, Op0); |
4216 | 0 | case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0); |
4217 | 0 | case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0); |
4218 | 0 | case MVT::v4f16: return fastEmit_ISD_FSQRT_MVT_v4f16_r(RetVT, Op0); |
4219 | 0 | case MVT::v8f16: return fastEmit_ISD_FSQRT_MVT_v8f16_r(RetVT, Op0); |
4220 | 0 | case MVT::v2f32: return fastEmit_ISD_FSQRT_MVT_v2f32_r(RetVT, Op0); |
4221 | 0 | case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0); |
4222 | 0 | case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0); |
4223 | 0 | default: return 0; |
4224 | 0 | } |
4225 | 0 | } |
4226 | | |
4227 | | // FastEmit functions for ISD::FTRUNC. |
4228 | | |
4229 | 0 | unsigned fastEmit_ISD_FTRUNC_MVT_f16_r(MVT RetVT, unsigned Op0) { |
4230 | 0 | if (RetVT.SimpleTy != MVT::f16) |
4231 | 0 | return 0; |
4232 | 0 | if ((Subtarget->hasFullFP16())) { |
4233 | 0 | return fastEmitInst_r(AArch64::FRINTZHr, &AArch64::FPR16RegClass, Op0); |
4234 | 0 | } |
4235 | 0 | return 0; |
4236 | 0 | } |
4237 | | |
4238 | 0 | unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0) { |
4239 | 0 | if (RetVT.SimpleTy != MVT::f32) |
4240 | 0 | return 0; |
4241 | 0 | if ((Subtarget->hasFPARMv8())) { |
4242 | 0 | return fastEmitInst_r(AArch64::FRINTZSr, &AArch64::FPR32RegClass, Op0); |
4243 | 0 | } |
4244 | 0 | return 0; |
4245 | 0 | } |
4246 | | |
4247 | 0 | unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0) { |
4248 | 0 | if (RetVT.SimpleTy != MVT::f64) |
4249 | 0 | return 0; |
4250 | 0 | if ((Subtarget->hasFPARMv8())) { |
4251 | 0 | return fastEmitInst_r(AArch64::FRINTZDr, &AArch64::FPR64RegClass, Op0); |
4252 | 0 | } |
4253 | 0 | return 0; |
4254 | 0 | } |
4255 | | |
4256 | 0 | unsigned fastEmit_ISD_FTRUNC_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
4257 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
4258 | 0 | return 0; |
4259 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
4260 | 0 | return fastEmitInst_r(AArch64::FRINTZv4f16, &AArch64::FPR64RegClass, Op0); |
4261 | 0 | } |
4262 | 0 | return 0; |
4263 | 0 | } |
4264 | | |
4265 | 0 | unsigned fastEmit_ISD_FTRUNC_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
4266 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
4267 | 0 | return 0; |
4268 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
4269 | 0 | return fastEmitInst_r(AArch64::FRINTZv8f16, &AArch64::FPR128RegClass, Op0); |
4270 | 0 | } |
4271 | 0 | return 0; |
4272 | 0 | } |
4273 | | |
4274 | 0 | unsigned fastEmit_ISD_FTRUNC_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
4275 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
4276 | 0 | return 0; |
4277 | 0 | if ((Subtarget->hasNEON())) { |
4278 | 0 | return fastEmitInst_r(AArch64::FRINTZv2f32, &AArch64::FPR64RegClass, Op0); |
4279 | 0 | } |
4280 | 0 | return 0; |
4281 | 0 | } |
4282 | | |
4283 | 0 | unsigned fastEmit_ISD_FTRUNC_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
4284 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
4285 | 0 | return 0; |
4286 | 0 | if ((Subtarget->hasNEON())) { |
4287 | 0 | return fastEmitInst_r(AArch64::FRINTZv4f32, &AArch64::FPR128RegClass, Op0); |
4288 | 0 | } |
4289 | 0 | return 0; |
4290 | 0 | } |
4291 | | |
4292 | 0 | unsigned fastEmit_ISD_FTRUNC_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
4293 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
4294 | 0 | return 0; |
4295 | 0 | if ((Subtarget->hasNEON())) { |
4296 | 0 | return fastEmitInst_r(AArch64::FRINTZv2f64, &AArch64::FPR128RegClass, Op0); |
4297 | 0 | } |
4298 | 0 | return 0; |
4299 | 0 | } |
4300 | | |
4301 | 0 | unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0) { |
4302 | 0 | switch (VT.SimpleTy) { |
4303 | 0 | case MVT::f16: return fastEmit_ISD_FTRUNC_MVT_f16_r(RetVT, Op0); |
4304 | 0 | case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0); |
4305 | 0 | case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0); |
4306 | 0 | case MVT::v4f16: return fastEmit_ISD_FTRUNC_MVT_v4f16_r(RetVT, Op0); |
4307 | 0 | case MVT::v8f16: return fastEmit_ISD_FTRUNC_MVT_v8f16_r(RetVT, Op0); |
4308 | 0 | case MVT::v2f32: return fastEmit_ISD_FTRUNC_MVT_v2f32_r(RetVT, Op0); |
4309 | 0 | case MVT::v4f32: return fastEmit_ISD_FTRUNC_MVT_v4f32_r(RetVT, Op0); |
4310 | 0 | case MVT::v2f64: return fastEmit_ISD_FTRUNC_MVT_v2f64_r(RetVT, Op0); |
4311 | 0 | default: return 0; |
4312 | 0 | } |
4313 | 0 | } |
4314 | | |
4315 | | // FastEmit functions for ISD::LLROUND. |
4316 | | |
4317 | 0 | unsigned fastEmit_ISD_LLROUND_MVT_f16_r(MVT RetVT, unsigned Op0) { |
4318 | 0 | if (RetVT.SimpleTy != MVT::i64) |
4319 | 0 | return 0; |
4320 | 0 | if ((Subtarget->hasFullFP16())) { |
4321 | 0 | return fastEmitInst_r(AArch64::FCVTASUXHr, &AArch64::GPR64RegClass, Op0); |
4322 | 0 | } |
4323 | 0 | return 0; |
4324 | 0 | } |
4325 | | |
4326 | 0 | unsigned fastEmit_ISD_LLROUND_MVT_f32_r(MVT RetVT, unsigned Op0) { |
4327 | 0 | if (RetVT.SimpleTy != MVT::i64) |
4328 | 0 | return 0; |
4329 | 0 | return fastEmitInst_r(AArch64::FCVTASUXSr, &AArch64::GPR64RegClass, Op0); |
4330 | 0 | } |
4331 | | |
4332 | 0 | unsigned fastEmit_ISD_LLROUND_MVT_f64_r(MVT RetVT, unsigned Op0) { |
4333 | 0 | if (RetVT.SimpleTy != MVT::i64) |
4334 | 0 | return 0; |
4335 | 0 | return fastEmitInst_r(AArch64::FCVTASUXDr, &AArch64::GPR64RegClass, Op0); |
4336 | 0 | } |
4337 | | |
4338 | 0 | unsigned fastEmit_ISD_LLROUND_r(MVT VT, MVT RetVT, unsigned Op0) { |
4339 | 0 | switch (VT.SimpleTy) { |
4340 | 0 | case MVT::f16: return fastEmit_ISD_LLROUND_MVT_f16_r(RetVT, Op0); |
4341 | 0 | case MVT::f32: return fastEmit_ISD_LLROUND_MVT_f32_r(RetVT, Op0); |
4342 | 0 | case MVT::f64: return fastEmit_ISD_LLROUND_MVT_f64_r(RetVT, Op0); |
4343 | 0 | default: return 0; |
4344 | 0 | } |
4345 | 0 | } |
4346 | | |
4347 | | // FastEmit functions for ISD::LROUND. |
4348 | | |
4349 | 0 | unsigned fastEmit_ISD_LROUND_MVT_f16_MVT_i32_r(unsigned Op0) { |
4350 | 0 | if ((Subtarget->hasFullFP16())) { |
4351 | 0 | return fastEmitInst_r(AArch64::FCVTASUWHr, &AArch64::GPR32RegClass, Op0); |
4352 | 0 | } |
4353 | 0 | return 0; |
4354 | 0 | } |
4355 | | |
4356 | 0 | unsigned fastEmit_ISD_LROUND_MVT_f16_MVT_i64_r(unsigned Op0) { |
4357 | 0 | if ((Subtarget->hasFullFP16())) { |
4358 | 0 | return fastEmitInst_r(AArch64::FCVTASUXHr, &AArch64::GPR64RegClass, Op0); |
4359 | 0 | } |
4360 | 0 | return 0; |
4361 | 0 | } |
4362 | | |
4363 | 0 | unsigned fastEmit_ISD_LROUND_MVT_f16_r(MVT RetVT, unsigned Op0) { |
4364 | 0 | switch (RetVT.SimpleTy) { |
4365 | 0 | case MVT::i32: return fastEmit_ISD_LROUND_MVT_f16_MVT_i32_r(Op0); |
4366 | 0 | case MVT::i64: return fastEmit_ISD_LROUND_MVT_f16_MVT_i64_r(Op0); |
4367 | 0 | default: return 0; |
4368 | 0 | } |
4369 | 0 | } |
4370 | | |
4371 | 0 | unsigned fastEmit_ISD_LROUND_MVT_f32_MVT_i32_r(unsigned Op0) { |
4372 | 0 | return fastEmitInst_r(AArch64::FCVTASUWSr, &AArch64::GPR32RegClass, Op0); |
4373 | 0 | } |
4374 | | |
4375 | 0 | unsigned fastEmit_ISD_LROUND_MVT_f32_MVT_i64_r(unsigned Op0) { |
4376 | 0 | return fastEmitInst_r(AArch64::FCVTASUXSr, &AArch64::GPR64RegClass, Op0); |
4377 | 0 | } |
4378 | | |
4379 | 0 | unsigned fastEmit_ISD_LROUND_MVT_f32_r(MVT RetVT, unsigned Op0) { |
4380 | 0 | switch (RetVT.SimpleTy) { |
4381 | 0 | case MVT::i32: return fastEmit_ISD_LROUND_MVT_f32_MVT_i32_r(Op0); |
4382 | 0 | case MVT::i64: return fastEmit_ISD_LROUND_MVT_f32_MVT_i64_r(Op0); |
4383 | 0 | default: return 0; |
4384 | 0 | } |
4385 | 0 | } |
4386 | | |
4387 | 0 | unsigned fastEmit_ISD_LROUND_MVT_f64_MVT_i32_r(unsigned Op0) { |
4388 | 0 | return fastEmitInst_r(AArch64::FCVTASUWDr, &AArch64::GPR32RegClass, Op0); |
4389 | 0 | } |
4390 | | |
4391 | 0 | unsigned fastEmit_ISD_LROUND_MVT_f64_MVT_i64_r(unsigned Op0) { |
4392 | 0 | return fastEmitInst_r(AArch64::FCVTASUXDr, &AArch64::GPR64RegClass, Op0); |
4393 | 0 | } |
4394 | | |
4395 | 0 | unsigned fastEmit_ISD_LROUND_MVT_f64_r(MVT RetVT, unsigned Op0) { |
4396 | 0 | switch (RetVT.SimpleTy) { |
4397 | 0 | case MVT::i32: return fastEmit_ISD_LROUND_MVT_f64_MVT_i32_r(Op0); |
4398 | 0 | case MVT::i64: return fastEmit_ISD_LROUND_MVT_f64_MVT_i64_r(Op0); |
4399 | 0 | default: return 0; |
4400 | 0 | } |
4401 | 0 | } |
4402 | | |
4403 | 0 | unsigned fastEmit_ISD_LROUND_r(MVT VT, MVT RetVT, unsigned Op0) { |
4404 | 0 | switch (VT.SimpleTy) { |
4405 | 0 | case MVT::f16: return fastEmit_ISD_LROUND_MVT_f16_r(RetVT, Op0); |
4406 | 0 | case MVT::f32: return fastEmit_ISD_LROUND_MVT_f32_r(RetVT, Op0); |
4407 | 0 | case MVT::f64: return fastEmit_ISD_LROUND_MVT_f64_r(RetVT, Op0); |
4408 | 0 | default: return 0; |
4409 | 0 | } |
4410 | 0 | } |
4411 | | |
4412 | | // FastEmit functions for ISD::SINT_TO_FP. |
4413 | | |
4414 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f16_r(unsigned Op0) { |
4415 | 0 | if ((Subtarget->hasFullFP16())) { |
4416 | 0 | return fastEmitInst_r(AArch64::SCVTFUWHri, &AArch64::FPR16RegClass, Op0); |
4417 | 0 | } |
4418 | 0 | return 0; |
4419 | 0 | } |
4420 | | |
4421 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) { |
4422 | 0 | if ((Subtarget->hasFPARMv8())) { |
4423 | 0 | return fastEmitInst_r(AArch64::SCVTFUWSri, &AArch64::FPR32RegClass, Op0); |
4424 | 0 | } |
4425 | 0 | return 0; |
4426 | 0 | } |
4427 | | |
4428 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) { |
4429 | 0 | if ((Subtarget->hasFPARMv8())) { |
4430 | 0 | return fastEmitInst_r(AArch64::SCVTFUWDri, &AArch64::FPR64RegClass, Op0); |
4431 | 0 | } |
4432 | 0 | return 0; |
4433 | 0 | } |
4434 | | |
4435 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
4436 | 0 | switch (RetVT.SimpleTy) { |
4437 | 0 | case MVT::f16: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f16_r(Op0); |
4438 | 0 | case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0); |
4439 | 0 | case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0); |
4440 | 0 | default: return 0; |
4441 | 0 | } |
4442 | 0 | } |
4443 | | |
4444 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f16_r(unsigned Op0) { |
4445 | 0 | if ((Subtarget->hasFullFP16())) { |
4446 | 0 | return fastEmitInst_r(AArch64::SCVTFUXHri, &AArch64::FPR16RegClass, Op0); |
4447 | 0 | } |
4448 | 0 | return 0; |
4449 | 0 | } |
4450 | | |
4451 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(unsigned Op0) { |
4452 | 0 | if ((Subtarget->hasFPARMv8())) { |
4453 | 0 | return fastEmitInst_r(AArch64::SCVTFUXSri, &AArch64::FPR32RegClass, Op0); |
4454 | 0 | } |
4455 | 0 | return 0; |
4456 | 0 | } |
4457 | | |
4458 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(unsigned Op0) { |
4459 | 0 | if ((Subtarget->hasFPARMv8())) { |
4460 | 0 | return fastEmitInst_r(AArch64::SCVTFUXDri, &AArch64::FPR64RegClass, Op0); |
4461 | 0 | } |
4462 | 0 | return 0; |
4463 | 0 | } |
4464 | | |
4465 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0) { |
4466 | 0 | switch (RetVT.SimpleTy) { |
4467 | 0 | case MVT::f16: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f16_r(Op0); |
4468 | 0 | case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(Op0); |
4469 | 0 | case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(Op0); |
4470 | 0 | default: return 0; |
4471 | 0 | } |
4472 | 0 | } |
4473 | | |
4474 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0) { |
4475 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
4476 | 0 | return 0; |
4477 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
4478 | 0 | return fastEmitInst_r(AArch64::SCVTFv4f16, &AArch64::FPR64RegClass, Op0); |
4479 | 0 | } |
4480 | 0 | return 0; |
4481 | 0 | } |
4482 | | |
4483 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
4484 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
4485 | 0 | return 0; |
4486 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
4487 | 0 | return fastEmitInst_r(AArch64::SCVTFv8f16, &AArch64::FPR128RegClass, Op0); |
4488 | 0 | } |
4489 | 0 | return 0; |
4490 | 0 | } |
4491 | | |
4492 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0) { |
4493 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
4494 | 0 | return 0; |
4495 | 0 | if ((Subtarget->hasNEON())) { |
4496 | 0 | return fastEmitInst_r(AArch64::SCVTFv2f32, &AArch64::FPR64RegClass, Op0); |
4497 | 0 | } |
4498 | 0 | return 0; |
4499 | 0 | } |
4500 | | |
4501 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
4502 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
4503 | 0 | return 0; |
4504 | 0 | if ((Subtarget->hasNEON())) { |
4505 | 0 | return fastEmitInst_r(AArch64::SCVTFv4f32, &AArch64::FPR128RegClass, Op0); |
4506 | 0 | } |
4507 | 0 | return 0; |
4508 | 0 | } |
4509 | | |
4510 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
4511 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
4512 | 0 | return 0; |
4513 | 0 | if ((Subtarget->hasNEON())) { |
4514 | 0 | return fastEmitInst_r(AArch64::SCVTFv2f64, &AArch64::FPR128RegClass, Op0); |
4515 | 0 | } |
4516 | 0 | return 0; |
4517 | 0 | } |
4518 | | |
4519 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) { |
4520 | 0 | switch (VT.SimpleTy) { |
4521 | 0 | case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0); |
4522 | 0 | case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0); |
4523 | 0 | case MVT::v4i16: return fastEmit_ISD_SINT_TO_FP_MVT_v4i16_r(RetVT, Op0); |
4524 | 0 | case MVT::v8i16: return fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(RetVT, Op0); |
4525 | 0 | case MVT::v2i32: return fastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(RetVT, Op0); |
4526 | 0 | case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0); |
4527 | 0 | case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0); |
4528 | 0 | default: return 0; |
4529 | 0 | } |
4530 | 0 | } |
4531 | | |
4532 | | // FastEmit functions for ISD::SPLAT_VECTOR. |
4533 | | |
4534 | 0 | unsigned fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_nxv16i8_r(unsigned Op0) { |
4535 | 0 | if ((Subtarget->hasSVEorSME())) { |
4536 | 0 | return fastEmitInst_r(AArch64::DUP_ZR_B, &AArch64::ZPRRegClass, Op0); |
4537 | 0 | } |
4538 | 0 | return 0; |
4539 | 0 | } |
4540 | | |
4541 | 0 | unsigned fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_nxv8i16_r(unsigned Op0) { |
4542 | 0 | if ((Subtarget->hasSVEorSME())) { |
4543 | 0 | return fastEmitInst_r(AArch64::DUP_ZR_H, &AArch64::ZPRRegClass, Op0); |
4544 | 0 | } |
4545 | 0 | return 0; |
4546 | 0 | } |
4547 | | |
4548 | 0 | unsigned fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_nxv4i32_r(unsigned Op0) { |
4549 | 0 | if ((Subtarget->hasSVEorSME())) { |
4550 | 0 | return fastEmitInst_r(AArch64::DUP_ZR_S, &AArch64::ZPRRegClass, Op0); |
4551 | 0 | } |
4552 | 0 | return 0; |
4553 | 0 | } |
4554 | | |
4555 | 0 | unsigned fastEmit_ISD_SPLAT_VECTOR_MVT_i32_r(MVT RetVT, unsigned Op0) { |
4556 | 0 | switch (RetVT.SimpleTy) { |
4557 | 0 | case MVT::nxv16i8: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_nxv16i8_r(Op0); |
4558 | 0 | case MVT::nxv8i16: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_nxv8i16_r(Op0); |
4559 | 0 | case MVT::nxv4i32: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_nxv4i32_r(Op0); |
4560 | 0 | default: return 0; |
4561 | 0 | } |
4562 | 0 | } |
4563 | | |
4564 | 0 | unsigned fastEmit_ISD_SPLAT_VECTOR_MVT_i64_r(MVT RetVT, unsigned Op0) { |
4565 | 0 | if (RetVT.SimpleTy != MVT::nxv2i64) |
4566 | 0 | return 0; |
4567 | 0 | if ((Subtarget->hasSVEorSME())) { |
4568 | 0 | return fastEmitInst_r(AArch64::DUP_ZR_D, &AArch64::ZPRRegClass, Op0); |
4569 | 0 | } |
4570 | 0 | return 0; |
4571 | 0 | } |
4572 | | |
4573 | 0 | unsigned fastEmit_ISD_SPLAT_VECTOR_r(MVT VT, MVT RetVT, unsigned Op0) { |
4574 | 0 | switch (VT.SimpleTy) { |
4575 | 0 | case MVT::i32: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_r(RetVT, Op0); |
4576 | 0 | case MVT::i64: return fastEmit_ISD_SPLAT_VECTOR_MVT_i64_r(RetVT, Op0); |
4577 | 0 | default: return 0; |
4578 | 0 | } |
4579 | 0 | } |
4580 | | |
4581 | | // FastEmit functions for ISD::STRICT_FCEIL. |
4582 | | |
4583 | 0 | unsigned fastEmit_ISD_STRICT_FCEIL_MVT_f16_r(MVT RetVT, unsigned Op0) { |
4584 | 0 | if (RetVT.SimpleTy != MVT::f16) |
4585 | 0 | return 0; |
4586 | 0 | if ((Subtarget->hasFullFP16())) { |
4587 | 0 | return fastEmitInst_r(AArch64::FRINTPHr, &AArch64::FPR16RegClass, Op0); |
4588 | 0 | } |
4589 | 0 | return 0; |
4590 | 0 | } |
4591 | | |
4592 | 0 | unsigned fastEmit_ISD_STRICT_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0) { |
4593 | 0 | if (RetVT.SimpleTy != MVT::f32) |
4594 | 0 | return 0; |
4595 | 0 | if ((Subtarget->hasFPARMv8())) { |
4596 | 0 | return fastEmitInst_r(AArch64::FRINTPSr, &AArch64::FPR32RegClass, Op0); |
4597 | 0 | } |
4598 | 0 | return 0; |
4599 | 0 | } |
4600 | | |
4601 | 0 | unsigned fastEmit_ISD_STRICT_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0) { |
4602 | 0 | if (RetVT.SimpleTy != MVT::f64) |
4603 | 0 | return 0; |
4604 | 0 | if ((Subtarget->hasFPARMv8())) { |
4605 | 0 | return fastEmitInst_r(AArch64::FRINTPDr, &AArch64::FPR64RegClass, Op0); |
4606 | 0 | } |
4607 | 0 | return 0; |
4608 | 0 | } |
4609 | | |
4610 | 0 | unsigned fastEmit_ISD_STRICT_FCEIL_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
4611 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
4612 | 0 | return 0; |
4613 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
4614 | 0 | return fastEmitInst_r(AArch64::FRINTPv4f16, &AArch64::FPR64RegClass, Op0); |
4615 | 0 | } |
4616 | 0 | return 0; |
4617 | 0 | } |
4618 | | |
4619 | 0 | unsigned fastEmit_ISD_STRICT_FCEIL_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
4620 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
4621 | 0 | return 0; |
4622 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
4623 | 0 | return fastEmitInst_r(AArch64::FRINTPv8f16, &AArch64::FPR128RegClass, Op0); |
4624 | 0 | } |
4625 | 0 | return 0; |
4626 | 0 | } |
4627 | | |
4628 | 0 | unsigned fastEmit_ISD_STRICT_FCEIL_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
4629 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
4630 | 0 | return 0; |
4631 | 0 | if ((Subtarget->hasNEON())) { |
4632 | 0 | return fastEmitInst_r(AArch64::FRINTPv2f32, &AArch64::FPR64RegClass, Op0); |
4633 | 0 | } |
4634 | 0 | return 0; |
4635 | 0 | } |
4636 | | |
4637 | 0 | unsigned fastEmit_ISD_STRICT_FCEIL_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
4638 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
4639 | 0 | return 0; |
4640 | 0 | if ((Subtarget->hasNEON())) { |
4641 | 0 | return fastEmitInst_r(AArch64::FRINTPv4f32, &AArch64::FPR128RegClass, Op0); |
4642 | 0 | } |
4643 | 0 | return 0; |
4644 | 0 | } |
4645 | | |
4646 | 0 | unsigned fastEmit_ISD_STRICT_FCEIL_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
4647 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
4648 | 0 | return 0; |
4649 | 0 | if ((Subtarget->hasNEON())) { |
4650 | 0 | return fastEmitInst_r(AArch64::FRINTPv2f64, &AArch64::FPR128RegClass, Op0); |
4651 | 0 | } |
4652 | 0 | return 0; |
4653 | 0 | } |
4654 | | |
4655 | 0 | unsigned fastEmit_ISD_STRICT_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0) { |
4656 | 0 | switch (VT.SimpleTy) { |
4657 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_FCEIL_MVT_f16_r(RetVT, Op0); |
4658 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FCEIL_MVT_f32_r(RetVT, Op0); |
4659 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FCEIL_MVT_f64_r(RetVT, Op0); |
4660 | 0 | case MVT::v4f16: return fastEmit_ISD_STRICT_FCEIL_MVT_v4f16_r(RetVT, Op0); |
4661 | 0 | case MVT::v8f16: return fastEmit_ISD_STRICT_FCEIL_MVT_v8f16_r(RetVT, Op0); |
4662 | 0 | case MVT::v2f32: return fastEmit_ISD_STRICT_FCEIL_MVT_v2f32_r(RetVT, Op0); |
4663 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FCEIL_MVT_v4f32_r(RetVT, Op0); |
4664 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FCEIL_MVT_v2f64_r(RetVT, Op0); |
4665 | 0 | default: return 0; |
4666 | 0 | } |
4667 | 0 | } |
4668 | | |
4669 | | // FastEmit functions for ISD::STRICT_FFLOOR. |
4670 | | |
4671 | 0 | unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_f16_r(MVT RetVT, unsigned Op0) { |
4672 | 0 | if (RetVT.SimpleTy != MVT::f16) |
4673 | 0 | return 0; |
4674 | 0 | if ((Subtarget->hasFullFP16())) { |
4675 | 0 | return fastEmitInst_r(AArch64::FRINTMHr, &AArch64::FPR16RegClass, Op0); |
4676 | 0 | } |
4677 | 0 | return 0; |
4678 | 0 | } |
4679 | | |
4680 | 0 | unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0) { |
4681 | 0 | if (RetVT.SimpleTy != MVT::f32) |
4682 | 0 | return 0; |
4683 | 0 | if ((Subtarget->hasFPARMv8())) { |
4684 | 0 | return fastEmitInst_r(AArch64::FRINTMSr, &AArch64::FPR32RegClass, Op0); |
4685 | 0 | } |
4686 | 0 | return 0; |
4687 | 0 | } |
4688 | | |
4689 | 0 | unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0) { |
4690 | 0 | if (RetVT.SimpleTy != MVT::f64) |
4691 | 0 | return 0; |
4692 | 0 | if ((Subtarget->hasFPARMv8())) { |
4693 | 0 | return fastEmitInst_r(AArch64::FRINTMDr, &AArch64::FPR64RegClass, Op0); |
4694 | 0 | } |
4695 | 0 | return 0; |
4696 | 0 | } |
4697 | | |
4698 | 0 | unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
4699 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
4700 | 0 | return 0; |
4701 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
4702 | 0 | return fastEmitInst_r(AArch64::FRINTMv4f16, &AArch64::FPR64RegClass, Op0); |
4703 | 0 | } |
4704 | 0 | return 0; |
4705 | 0 | } |
4706 | | |
4707 | 0 | unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
4708 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
4709 | 0 | return 0; |
4710 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
4711 | 0 | return fastEmitInst_r(AArch64::FRINTMv8f16, &AArch64::FPR128RegClass, Op0); |
4712 | 0 | } |
4713 | 0 | return 0; |
4714 | 0 | } |
4715 | | |
4716 | 0 | unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
4717 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
4718 | 0 | return 0; |
4719 | 0 | if ((Subtarget->hasNEON())) { |
4720 | 0 | return fastEmitInst_r(AArch64::FRINTMv2f32, &AArch64::FPR64RegClass, Op0); |
4721 | 0 | } |
4722 | 0 | return 0; |
4723 | 0 | } |
4724 | | |
4725 | 0 | unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
4726 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
4727 | 0 | return 0; |
4728 | 0 | if ((Subtarget->hasNEON())) { |
4729 | 0 | return fastEmitInst_r(AArch64::FRINTMv4f32, &AArch64::FPR128RegClass, Op0); |
4730 | 0 | } |
4731 | 0 | return 0; |
4732 | 0 | } |
4733 | | |
4734 | 0 | unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
4735 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
4736 | 0 | return 0; |
4737 | 0 | if ((Subtarget->hasNEON())) { |
4738 | 0 | return fastEmitInst_r(AArch64::FRINTMv2f64, &AArch64::FPR128RegClass, Op0); |
4739 | 0 | } |
4740 | 0 | return 0; |
4741 | 0 | } |
4742 | | |
4743 | 0 | unsigned fastEmit_ISD_STRICT_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0) { |
4744 | 0 | switch (VT.SimpleTy) { |
4745 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_FFLOOR_MVT_f16_r(RetVT, Op0); |
4746 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FFLOOR_MVT_f32_r(RetVT, Op0); |
4747 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FFLOOR_MVT_f64_r(RetVT, Op0); |
4748 | 0 | case MVT::v4f16: return fastEmit_ISD_STRICT_FFLOOR_MVT_v4f16_r(RetVT, Op0); |
4749 | 0 | case MVT::v8f16: return fastEmit_ISD_STRICT_FFLOOR_MVT_v8f16_r(RetVT, Op0); |
4750 | 0 | case MVT::v2f32: return fastEmit_ISD_STRICT_FFLOOR_MVT_v2f32_r(RetVT, Op0); |
4751 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FFLOOR_MVT_v4f32_r(RetVT, Op0); |
4752 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FFLOOR_MVT_v2f64_r(RetVT, Op0); |
4753 | 0 | default: return 0; |
4754 | 0 | } |
4755 | 0 | } |
4756 | | |
4757 | | // FastEmit functions for ISD::STRICT_FNEARBYINT. |
4758 | | |
4759 | 0 | unsigned fastEmit_ISD_STRICT_FNEARBYINT_MVT_f16_r(MVT RetVT, unsigned Op0) { |
4760 | 0 | if (RetVT.SimpleTy != MVT::f16) |
4761 | 0 | return 0; |
4762 | 0 | if ((Subtarget->hasFullFP16())) { |
4763 | 0 | return fastEmitInst_r(AArch64::FRINTIHr, &AArch64::FPR16RegClass, Op0); |
4764 | 0 | } |
4765 | 0 | return 0; |
4766 | 0 | } |
4767 | | |
4768 | 0 | unsigned fastEmit_ISD_STRICT_FNEARBYINT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
4769 | 0 | if (RetVT.SimpleTy != MVT::f32) |
4770 | 0 | return 0; |
4771 | 0 | if ((Subtarget->hasFPARMv8())) { |
4772 | 0 | return fastEmitInst_r(AArch64::FRINTISr, &AArch64::FPR32RegClass, Op0); |
4773 | 0 | } |
4774 | 0 | return 0; |
4775 | 0 | } |
4776 | | |
4777 | 0 | unsigned fastEmit_ISD_STRICT_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
4778 | 0 | if (RetVT.SimpleTy != MVT::f64) |
4779 | 0 | return 0; |
4780 | 0 | if ((Subtarget->hasFPARMv8())) { |
4781 | 0 | return fastEmitInst_r(AArch64::FRINTIDr, &AArch64::FPR64RegClass, Op0); |
4782 | 0 | } |
4783 | 0 | return 0; |
4784 | 0 | } |
4785 | | |
4786 | 0 | unsigned fastEmit_ISD_STRICT_FNEARBYINT_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
4787 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
4788 | 0 | return 0; |
4789 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
4790 | 0 | return fastEmitInst_r(AArch64::FRINTIv4f16, &AArch64::FPR64RegClass, Op0); |
4791 | 0 | } |
4792 | 0 | return 0; |
4793 | 0 | } |
4794 | | |
4795 | 0 | unsigned fastEmit_ISD_STRICT_FNEARBYINT_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
4796 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
4797 | 0 | return 0; |
4798 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
4799 | 0 | return fastEmitInst_r(AArch64::FRINTIv8f16, &AArch64::FPR128RegClass, Op0); |
4800 | 0 | } |
4801 | 0 | return 0; |
4802 | 0 | } |
4803 | | |
4804 | 0 | unsigned fastEmit_ISD_STRICT_FNEARBYINT_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
4805 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
4806 | 0 | return 0; |
4807 | 0 | if ((Subtarget->hasNEON())) { |
4808 | 0 | return fastEmitInst_r(AArch64::FRINTIv2f32, &AArch64::FPR64RegClass, Op0); |
4809 | 0 | } |
4810 | 0 | return 0; |
4811 | 0 | } |
4812 | | |
4813 | 0 | unsigned fastEmit_ISD_STRICT_FNEARBYINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
4814 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
4815 | 0 | return 0; |
4816 | 0 | if ((Subtarget->hasNEON())) { |
4817 | 0 | return fastEmitInst_r(AArch64::FRINTIv4f32, &AArch64::FPR128RegClass, Op0); |
4818 | 0 | } |
4819 | 0 | return 0; |
4820 | 0 | } |
4821 | | |
4822 | 0 | unsigned fastEmit_ISD_STRICT_FNEARBYINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
4823 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
4824 | 0 | return 0; |
4825 | 0 | if ((Subtarget->hasNEON())) { |
4826 | 0 | return fastEmitInst_r(AArch64::FRINTIv2f64, &AArch64::FPR128RegClass, Op0); |
4827 | 0 | } |
4828 | 0 | return 0; |
4829 | 0 | } |
4830 | | |
4831 | 0 | unsigned fastEmit_ISD_STRICT_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
4832 | 0 | switch (VT.SimpleTy) { |
4833 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_FNEARBYINT_MVT_f16_r(RetVT, Op0); |
4834 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FNEARBYINT_MVT_f32_r(RetVT, Op0); |
4835 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FNEARBYINT_MVT_f64_r(RetVT, Op0); |
4836 | 0 | case MVT::v4f16: return fastEmit_ISD_STRICT_FNEARBYINT_MVT_v4f16_r(RetVT, Op0); |
4837 | 0 | case MVT::v8f16: return fastEmit_ISD_STRICT_FNEARBYINT_MVT_v8f16_r(RetVT, Op0); |
4838 | 0 | case MVT::v2f32: return fastEmit_ISD_STRICT_FNEARBYINT_MVT_v2f32_r(RetVT, Op0); |
4839 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FNEARBYINT_MVT_v4f32_r(RetVT, Op0); |
4840 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FNEARBYINT_MVT_v2f64_r(RetVT, Op0); |
4841 | 0 | default: return 0; |
4842 | 0 | } |
4843 | 0 | } |
4844 | | |
4845 | | // FastEmit functions for ISD::STRICT_FP_EXTEND. |
4846 | | |
4847 | 0 | unsigned fastEmit_ISD_STRICT_FP_EXTEND_MVT_f16_MVT_f32_r(unsigned Op0) { |
4848 | 0 | if ((Subtarget->hasFPARMv8())) { |
4849 | 0 | return fastEmitInst_r(AArch64::FCVTSHr, &AArch64::FPR32RegClass, Op0); |
4850 | 0 | } |
4851 | 0 | return 0; |
4852 | 0 | } |
4853 | | |
4854 | 0 | unsigned fastEmit_ISD_STRICT_FP_EXTEND_MVT_f16_MVT_f64_r(unsigned Op0) { |
4855 | 0 | if ((Subtarget->hasFPARMv8())) { |
4856 | 0 | return fastEmitInst_r(AArch64::FCVTDHr, &AArch64::FPR64RegClass, Op0); |
4857 | 0 | } |
4858 | 0 | return 0; |
4859 | 0 | } |
4860 | | |
4861 | 0 | unsigned fastEmit_ISD_STRICT_FP_EXTEND_MVT_f16_r(MVT RetVT, unsigned Op0) { |
4862 | 0 | switch (RetVT.SimpleTy) { |
4863 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f16_MVT_f32_r(Op0); |
4864 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f16_MVT_f64_r(Op0); |
4865 | 0 | default: return 0; |
4866 | 0 | } |
4867 | 0 | } |
4868 | | |
4869 | 0 | unsigned fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0) { |
4870 | 0 | if (RetVT.SimpleTy != MVT::f64) |
4871 | 0 | return 0; |
4872 | 0 | if ((Subtarget->hasFPARMv8())) { |
4873 | 0 | return fastEmitInst_r(AArch64::FCVTDSr, &AArch64::FPR64RegClass, Op0); |
4874 | 0 | } |
4875 | 0 | return 0; |
4876 | 0 | } |
4877 | | |
4878 | 0 | unsigned fastEmit_ISD_STRICT_FP_EXTEND_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
4879 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
4880 | 0 | return 0; |
4881 | 0 | return fastEmitInst_r(AArch64::FCVTLv4i16, &AArch64::FPR128RegClass, Op0); |
4882 | 0 | } |
4883 | | |
4884 | 0 | unsigned fastEmit_ISD_STRICT_FP_EXTEND_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
4885 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
4886 | 0 | return 0; |
4887 | 0 | return fastEmitInst_r(AArch64::FCVTLv2i32, &AArch64::FPR128RegClass, Op0); |
4888 | 0 | } |
4889 | | |
4890 | 0 | unsigned fastEmit_ISD_STRICT_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) { |
4891 | 0 | switch (VT.SimpleTy) { |
4892 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f16_r(RetVT, Op0); |
4893 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(RetVT, Op0); |
4894 | 0 | case MVT::v4f16: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_v4f16_r(RetVT, Op0); |
4895 | 0 | case MVT::v2f32: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_v2f32_r(RetVT, Op0); |
4896 | 0 | default: return 0; |
4897 | 0 | } |
4898 | 0 | } |
4899 | | |
4900 | | // FastEmit functions for ISD::STRICT_FP_ROUND. |
4901 | | |
4902 | 0 | unsigned fastEmit_ISD_STRICT_FP_ROUND_MVT_f32_r(MVT RetVT, unsigned Op0) { |
4903 | 0 | if (RetVT.SimpleTy != MVT::f16) |
4904 | 0 | return 0; |
4905 | 0 | if ((Subtarget->hasFPARMv8())) { |
4906 | 0 | return fastEmitInst_r(AArch64::FCVTHSr, &AArch64::FPR16RegClass, Op0); |
4907 | 0 | } |
4908 | 0 | return 0; |
4909 | 0 | } |
4910 | | |
4911 | 0 | unsigned fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_MVT_f16_r(unsigned Op0) { |
4912 | 0 | if ((Subtarget->hasFPARMv8())) { |
4913 | 0 | return fastEmitInst_r(AArch64::FCVTHDr, &AArch64::FPR16RegClass, Op0); |
4914 | 0 | } |
4915 | 0 | return 0; |
4916 | 0 | } |
4917 | | |
4918 | 0 | unsigned fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_MVT_f32_r(unsigned Op0) { |
4919 | 0 | if ((Subtarget->hasFPARMv8())) { |
4920 | 0 | return fastEmitInst_r(AArch64::FCVTSDr, &AArch64::FPR32RegClass, Op0); |
4921 | 0 | } |
4922 | 0 | return 0; |
4923 | 0 | } |
4924 | | |
4925 | 0 | unsigned fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0) { |
4926 | 0 | switch (RetVT.SimpleTy) { |
4927 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_MVT_f16_r(Op0); |
4928 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_MVT_f32_r(Op0); |
4929 | 0 | default: return 0; |
4930 | 0 | } |
4931 | 0 | } |
4932 | | |
4933 | 0 | unsigned fastEmit_ISD_STRICT_FP_ROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
4934 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
4935 | 0 | return 0; |
4936 | 0 | return fastEmitInst_r(AArch64::FCVTNv4i16, &AArch64::FPR64RegClass, Op0); |
4937 | 0 | } |
4938 | | |
4939 | 0 | unsigned fastEmit_ISD_STRICT_FP_ROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
4940 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
4941 | 0 | return 0; |
4942 | 0 | return fastEmitInst_r(AArch64::FCVTNv2i32, &AArch64::FPR64RegClass, Op0); |
4943 | 0 | } |
4944 | | |
4945 | 0 | unsigned fastEmit_ISD_STRICT_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0) { |
4946 | 0 | switch (VT.SimpleTy) { |
4947 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f32_r(RetVT, Op0); |
4948 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(RetVT, Op0); |
4949 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FP_ROUND_MVT_v4f32_r(RetVT, Op0); |
4950 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FP_ROUND_MVT_v2f64_r(RetVT, Op0); |
4951 | 0 | default: return 0; |
4952 | 0 | } |
4953 | 0 | } |
4954 | | |
4955 | | // FastEmit functions for ISD::STRICT_FP_TO_SINT. |
4956 | | |
4957 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f16_MVT_i32_r(unsigned Op0) { |
4958 | 0 | if ((Subtarget->hasFullFP16())) { |
4959 | 0 | return fastEmitInst_r(AArch64::FCVTZSUWHr, &AArch64::GPR32RegClass, Op0); |
4960 | 0 | } |
4961 | 0 | return 0; |
4962 | 0 | } |
4963 | | |
4964 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f16_MVT_i64_r(unsigned Op0) { |
4965 | 0 | if ((Subtarget->hasFullFP16())) { |
4966 | 0 | return fastEmitInst_r(AArch64::FCVTZSUXHr, &AArch64::GPR64RegClass, Op0); |
4967 | 0 | } |
4968 | 0 | return 0; |
4969 | 0 | } |
4970 | | |
4971 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f16_r(MVT RetVT, unsigned Op0) { |
4972 | 0 | switch (RetVT.SimpleTy) { |
4973 | 0 | case MVT::i32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f16_MVT_i32_r(Op0); |
4974 | 0 | case MVT::i64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f16_MVT_i64_r(Op0); |
4975 | 0 | default: return 0; |
4976 | 0 | } |
4977 | 0 | } |
4978 | | |
4979 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_MVT_i32_r(unsigned Op0) { |
4980 | 0 | if ((Subtarget->hasFPARMv8())) { |
4981 | 0 | return fastEmitInst_r(AArch64::FCVTZSUWSr, &AArch64::GPR32RegClass, Op0); |
4982 | 0 | } |
4983 | 0 | return 0; |
4984 | 0 | } |
4985 | | |
4986 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_MVT_i64_r(unsigned Op0) { |
4987 | 0 | if ((Subtarget->hasFPARMv8())) { |
4988 | 0 | return fastEmitInst_r(AArch64::FCVTZSUXSr, &AArch64::GPR64RegClass, Op0); |
4989 | 0 | } |
4990 | 0 | return 0; |
4991 | 0 | } |
4992 | | |
4993 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
4994 | 0 | switch (RetVT.SimpleTy) { |
4995 | 0 | case MVT::i32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_MVT_i32_r(Op0); |
4996 | 0 | case MVT::i64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_MVT_i64_r(Op0); |
4997 | 0 | default: return 0; |
4998 | 0 | } |
4999 | 0 | } |
5000 | | |
5001 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_MVT_i32_r(unsigned Op0) { |
5002 | 0 | if ((Subtarget->hasFPARMv8())) { |
5003 | 0 | return fastEmitInst_r(AArch64::FCVTZSUWDr, &AArch64::GPR32RegClass, Op0); |
5004 | 0 | } |
5005 | 0 | return 0; |
5006 | 0 | } |
5007 | | |
5008 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_MVT_i64_r(unsigned Op0) { |
5009 | 0 | if ((Subtarget->hasFPARMv8())) { |
5010 | 0 | return fastEmitInst_r(AArch64::FCVTZSUXDr, &AArch64::GPR64RegClass, Op0); |
5011 | 0 | } |
5012 | 0 | return 0; |
5013 | 0 | } |
5014 | | |
5015 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
5016 | 0 | switch (RetVT.SimpleTy) { |
5017 | 0 | case MVT::i32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_MVT_i32_r(Op0); |
5018 | 0 | case MVT::i64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_MVT_i64_r(Op0); |
5019 | 0 | default: return 0; |
5020 | 0 | } |
5021 | 0 | } |
5022 | | |
5023 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
5024 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
5025 | 0 | return 0; |
5026 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
5027 | 0 | return fastEmitInst_r(AArch64::FCVTZSv4f16, &AArch64::FPR64RegClass, Op0); |
5028 | 0 | } |
5029 | 0 | return 0; |
5030 | 0 | } |
5031 | | |
5032 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
5033 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
5034 | 0 | return 0; |
5035 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
5036 | 0 | return fastEmitInst_r(AArch64::FCVTZSv8f16, &AArch64::FPR128RegClass, Op0); |
5037 | 0 | } |
5038 | 0 | return 0; |
5039 | 0 | } |
5040 | | |
5041 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
5042 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
5043 | 0 | return 0; |
5044 | 0 | if ((Subtarget->hasNEON())) { |
5045 | 0 | return fastEmitInst_r(AArch64::FCVTZSv2f32, &AArch64::FPR64RegClass, Op0); |
5046 | 0 | } |
5047 | 0 | return 0; |
5048 | 0 | } |
5049 | | |
5050 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
5051 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
5052 | 0 | return 0; |
5053 | 0 | if ((Subtarget->hasNEON())) { |
5054 | 0 | return fastEmitInst_r(AArch64::FCVTZSv4f32, &AArch64::FPR128RegClass, Op0); |
5055 | 0 | } |
5056 | 0 | return 0; |
5057 | 0 | } |
5058 | | |
5059 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
5060 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
5061 | 0 | return 0; |
5062 | 0 | if ((Subtarget->hasNEON())) { |
5063 | 0 | return fastEmitInst_r(AArch64::FCVTZSv2f64, &AArch64::FPR128RegClass, Op0); |
5064 | 0 | } |
5065 | 0 | return 0; |
5066 | 0 | } |
5067 | | |
5068 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
5069 | 0 | switch (VT.SimpleTy) { |
5070 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f16_r(RetVT, Op0); |
5071 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_r(RetVT, Op0); |
5072 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_r(RetVT, Op0); |
5073 | 0 | case MVT::v4f16: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v4f16_r(RetVT, Op0); |
5074 | 0 | case MVT::v8f16: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v8f16_r(RetVT, Op0); |
5075 | 0 | case MVT::v2f32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v2f32_r(RetVT, Op0); |
5076 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0); |
5077 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0); |
5078 | 0 | default: return 0; |
5079 | 0 | } |
5080 | 0 | } |
5081 | | |
5082 | | // FastEmit functions for ISD::STRICT_FP_TO_UINT. |
5083 | | |
5084 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f16_MVT_i32_r(unsigned Op0) { |
5085 | 0 | if ((Subtarget->hasFullFP16())) { |
5086 | 0 | return fastEmitInst_r(AArch64::FCVTZUUWHr, &AArch64::GPR32RegClass, Op0); |
5087 | 0 | } |
5088 | 0 | return 0; |
5089 | 0 | } |
5090 | | |
5091 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f16_MVT_i64_r(unsigned Op0) { |
5092 | 0 | if ((Subtarget->hasFullFP16())) { |
5093 | 0 | return fastEmitInst_r(AArch64::FCVTZUUXHr, &AArch64::GPR64RegClass, Op0); |
5094 | 0 | } |
5095 | 0 | return 0; |
5096 | 0 | } |
5097 | | |
5098 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f16_r(MVT RetVT, unsigned Op0) { |
5099 | 0 | switch (RetVT.SimpleTy) { |
5100 | 0 | case MVT::i32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f16_MVT_i32_r(Op0); |
5101 | 0 | case MVT::i64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f16_MVT_i64_r(Op0); |
5102 | 0 | default: return 0; |
5103 | 0 | } |
5104 | 0 | } |
5105 | | |
5106 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_MVT_i32_r(unsigned Op0) { |
5107 | 0 | if ((Subtarget->hasFPARMv8())) { |
5108 | 0 | return fastEmitInst_r(AArch64::FCVTZUUWSr, &AArch64::GPR32RegClass, Op0); |
5109 | 0 | } |
5110 | 0 | return 0; |
5111 | 0 | } |
5112 | | |
5113 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_MVT_i64_r(unsigned Op0) { |
5114 | 0 | if ((Subtarget->hasFPARMv8())) { |
5115 | 0 | return fastEmitInst_r(AArch64::FCVTZUUXSr, &AArch64::GPR64RegClass, Op0); |
5116 | 0 | } |
5117 | 0 | return 0; |
5118 | 0 | } |
5119 | | |
5120 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
5121 | 0 | switch (RetVT.SimpleTy) { |
5122 | 0 | case MVT::i32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_MVT_i32_r(Op0); |
5123 | 0 | case MVT::i64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_MVT_i64_r(Op0); |
5124 | 0 | default: return 0; |
5125 | 0 | } |
5126 | 0 | } |
5127 | | |
5128 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_MVT_i32_r(unsigned Op0) { |
5129 | 0 | if ((Subtarget->hasFPARMv8())) { |
5130 | 0 | return fastEmitInst_r(AArch64::FCVTZUUWDr, &AArch64::GPR32RegClass, Op0); |
5131 | 0 | } |
5132 | 0 | return 0; |
5133 | 0 | } |
5134 | | |
5135 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_MVT_i64_r(unsigned Op0) { |
5136 | 0 | if ((Subtarget->hasFPARMv8())) { |
5137 | 0 | return fastEmitInst_r(AArch64::FCVTZUUXDr, &AArch64::GPR64RegClass, Op0); |
5138 | 0 | } |
5139 | 0 | return 0; |
5140 | 0 | } |
5141 | | |
5142 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
5143 | 0 | switch (RetVT.SimpleTy) { |
5144 | 0 | case MVT::i32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_MVT_i32_r(Op0); |
5145 | 0 | case MVT::i64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_MVT_i64_r(Op0); |
5146 | 0 | default: return 0; |
5147 | 0 | } |
5148 | 0 | } |
5149 | | |
5150 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
5151 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
5152 | 0 | return 0; |
5153 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
5154 | 0 | return fastEmitInst_r(AArch64::FCVTZUv4f16, &AArch64::FPR64RegClass, Op0); |
5155 | 0 | } |
5156 | 0 | return 0; |
5157 | 0 | } |
5158 | | |
5159 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
5160 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
5161 | 0 | return 0; |
5162 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
5163 | 0 | return fastEmitInst_r(AArch64::FCVTZUv8f16, &AArch64::FPR128RegClass, Op0); |
5164 | 0 | } |
5165 | 0 | return 0; |
5166 | 0 | } |
5167 | | |
5168 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
5169 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
5170 | 0 | return 0; |
5171 | 0 | if ((Subtarget->hasNEON())) { |
5172 | 0 | return fastEmitInst_r(AArch64::FCVTZUv2f32, &AArch64::FPR64RegClass, Op0); |
5173 | 0 | } |
5174 | 0 | return 0; |
5175 | 0 | } |
5176 | | |
5177 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
5178 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
5179 | 0 | return 0; |
5180 | 0 | if ((Subtarget->hasNEON())) { |
5181 | 0 | return fastEmitInst_r(AArch64::FCVTZUv4f32, &AArch64::FPR128RegClass, Op0); |
5182 | 0 | } |
5183 | 0 | return 0; |
5184 | 0 | } |
5185 | | |
5186 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
5187 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
5188 | 0 | return 0; |
5189 | 0 | if ((Subtarget->hasNEON())) { |
5190 | 0 | return fastEmitInst_r(AArch64::FCVTZUv2f64, &AArch64::FPR128RegClass, Op0); |
5191 | 0 | } |
5192 | 0 | return 0; |
5193 | 0 | } |
5194 | | |
5195 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
5196 | 0 | switch (VT.SimpleTy) { |
5197 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f16_r(RetVT, Op0); |
5198 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_r(RetVT, Op0); |
5199 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_r(RetVT, Op0); |
5200 | 0 | case MVT::v4f16: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v4f16_r(RetVT, Op0); |
5201 | 0 | case MVT::v8f16: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v8f16_r(RetVT, Op0); |
5202 | 0 | case MVT::v2f32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v2f32_r(RetVT, Op0); |
5203 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0); |
5204 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0); |
5205 | 0 | default: return 0; |
5206 | 0 | } |
5207 | 0 | } |
5208 | | |
5209 | | // FastEmit functions for ISD::STRICT_FRINT. |
5210 | | |
5211 | 0 | unsigned fastEmit_ISD_STRICT_FRINT_MVT_f16_r(MVT RetVT, unsigned Op0) { |
5212 | 0 | if (RetVT.SimpleTy != MVT::f16) |
5213 | 0 | return 0; |
5214 | 0 | if ((Subtarget->hasFullFP16())) { |
5215 | 0 | return fastEmitInst_r(AArch64::FRINTXHr, &AArch64::FPR16RegClass, Op0); |
5216 | 0 | } |
5217 | 0 | return 0; |
5218 | 0 | } |
5219 | | |
5220 | 0 | unsigned fastEmit_ISD_STRICT_FRINT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
5221 | 0 | if (RetVT.SimpleTy != MVT::f32) |
5222 | 0 | return 0; |
5223 | 0 | if ((Subtarget->hasFPARMv8())) { |
5224 | 0 | return fastEmitInst_r(AArch64::FRINTXSr, &AArch64::FPR32RegClass, Op0); |
5225 | 0 | } |
5226 | 0 | return 0; |
5227 | 0 | } |
5228 | | |
5229 | 0 | unsigned fastEmit_ISD_STRICT_FRINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
5230 | 0 | if (RetVT.SimpleTy != MVT::f64) |
5231 | 0 | return 0; |
5232 | 0 | if ((Subtarget->hasFPARMv8())) { |
5233 | 0 | return fastEmitInst_r(AArch64::FRINTXDr, &AArch64::FPR64RegClass, Op0); |
5234 | 0 | } |
5235 | 0 | return 0; |
5236 | 0 | } |
5237 | | |
5238 | 0 | unsigned fastEmit_ISD_STRICT_FRINT_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
5239 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
5240 | 0 | return 0; |
5241 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
5242 | 0 | return fastEmitInst_r(AArch64::FRINTXv4f16, &AArch64::FPR64RegClass, Op0); |
5243 | 0 | } |
5244 | 0 | return 0; |
5245 | 0 | } |
5246 | | |
5247 | 0 | unsigned fastEmit_ISD_STRICT_FRINT_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
5248 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
5249 | 0 | return 0; |
5250 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
5251 | 0 | return fastEmitInst_r(AArch64::FRINTXv8f16, &AArch64::FPR128RegClass, Op0); |
5252 | 0 | } |
5253 | 0 | return 0; |
5254 | 0 | } |
5255 | | |
5256 | 0 | unsigned fastEmit_ISD_STRICT_FRINT_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
5257 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
5258 | 0 | return 0; |
5259 | 0 | if ((Subtarget->hasNEON())) { |
5260 | 0 | return fastEmitInst_r(AArch64::FRINTXv2f32, &AArch64::FPR64RegClass, Op0); |
5261 | 0 | } |
5262 | 0 | return 0; |
5263 | 0 | } |
5264 | | |
5265 | 0 | unsigned fastEmit_ISD_STRICT_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
5266 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
5267 | 0 | return 0; |
5268 | 0 | if ((Subtarget->hasNEON())) { |
5269 | 0 | return fastEmitInst_r(AArch64::FRINTXv4f32, &AArch64::FPR128RegClass, Op0); |
5270 | 0 | } |
5271 | 0 | return 0; |
5272 | 0 | } |
5273 | | |
5274 | 0 | unsigned fastEmit_ISD_STRICT_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
5275 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
5276 | 0 | return 0; |
5277 | 0 | if ((Subtarget->hasNEON())) { |
5278 | 0 | return fastEmitInst_r(AArch64::FRINTXv2f64, &AArch64::FPR128RegClass, Op0); |
5279 | 0 | } |
5280 | 0 | return 0; |
5281 | 0 | } |
5282 | | |
5283 | 0 | unsigned fastEmit_ISD_STRICT_FRINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
5284 | 0 | switch (VT.SimpleTy) { |
5285 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_FRINT_MVT_f16_r(RetVT, Op0); |
5286 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FRINT_MVT_f32_r(RetVT, Op0); |
5287 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FRINT_MVT_f64_r(RetVT, Op0); |
5288 | 0 | case MVT::v4f16: return fastEmit_ISD_STRICT_FRINT_MVT_v4f16_r(RetVT, Op0); |
5289 | 0 | case MVT::v8f16: return fastEmit_ISD_STRICT_FRINT_MVT_v8f16_r(RetVT, Op0); |
5290 | 0 | case MVT::v2f32: return fastEmit_ISD_STRICT_FRINT_MVT_v2f32_r(RetVT, Op0); |
5291 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FRINT_MVT_v4f32_r(RetVT, Op0); |
5292 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FRINT_MVT_v2f64_r(RetVT, Op0); |
5293 | 0 | default: return 0; |
5294 | 0 | } |
5295 | 0 | } |
5296 | | |
5297 | | // FastEmit functions for ISD::STRICT_FROUND. |
5298 | | |
5299 | 0 | unsigned fastEmit_ISD_STRICT_FROUND_MVT_f16_r(MVT RetVT, unsigned Op0) { |
5300 | 0 | if (RetVT.SimpleTy != MVT::f16) |
5301 | 0 | return 0; |
5302 | 0 | if ((Subtarget->hasFullFP16())) { |
5303 | 0 | return fastEmitInst_r(AArch64::FRINTAHr, &AArch64::FPR16RegClass, Op0); |
5304 | 0 | } |
5305 | 0 | return 0; |
5306 | 0 | } |
5307 | | |
5308 | 0 | unsigned fastEmit_ISD_STRICT_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0) { |
5309 | 0 | if (RetVT.SimpleTy != MVT::f32) |
5310 | 0 | return 0; |
5311 | 0 | if ((Subtarget->hasFPARMv8())) { |
5312 | 0 | return fastEmitInst_r(AArch64::FRINTASr, &AArch64::FPR32RegClass, Op0); |
5313 | 0 | } |
5314 | 0 | return 0; |
5315 | 0 | } |
5316 | | |
5317 | 0 | unsigned fastEmit_ISD_STRICT_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0) { |
5318 | 0 | if (RetVT.SimpleTy != MVT::f64) |
5319 | 0 | return 0; |
5320 | 0 | if ((Subtarget->hasFPARMv8())) { |
5321 | 0 | return fastEmitInst_r(AArch64::FRINTADr, &AArch64::FPR64RegClass, Op0); |
5322 | 0 | } |
5323 | 0 | return 0; |
5324 | 0 | } |
5325 | | |
5326 | 0 | unsigned fastEmit_ISD_STRICT_FROUND_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
5327 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
5328 | 0 | return 0; |
5329 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
5330 | 0 | return fastEmitInst_r(AArch64::FRINTAv4f16, &AArch64::FPR64RegClass, Op0); |
5331 | 0 | } |
5332 | 0 | return 0; |
5333 | 0 | } |
5334 | | |
5335 | 0 | unsigned fastEmit_ISD_STRICT_FROUND_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
5336 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
5337 | 0 | return 0; |
5338 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
5339 | 0 | return fastEmitInst_r(AArch64::FRINTAv8f16, &AArch64::FPR128RegClass, Op0); |
5340 | 0 | } |
5341 | 0 | return 0; |
5342 | 0 | } |
5343 | | |
5344 | 0 | unsigned fastEmit_ISD_STRICT_FROUND_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
5345 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
5346 | 0 | return 0; |
5347 | 0 | if ((Subtarget->hasNEON())) { |
5348 | 0 | return fastEmitInst_r(AArch64::FRINTAv2f32, &AArch64::FPR64RegClass, Op0); |
5349 | 0 | } |
5350 | 0 | return 0; |
5351 | 0 | } |
5352 | | |
5353 | 0 | unsigned fastEmit_ISD_STRICT_FROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
5354 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
5355 | 0 | return 0; |
5356 | 0 | if ((Subtarget->hasNEON())) { |
5357 | 0 | return fastEmitInst_r(AArch64::FRINTAv4f32, &AArch64::FPR128RegClass, Op0); |
5358 | 0 | } |
5359 | 0 | return 0; |
5360 | 0 | } |
5361 | | |
5362 | 0 | unsigned fastEmit_ISD_STRICT_FROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
5363 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
5364 | 0 | return 0; |
5365 | 0 | if ((Subtarget->hasNEON())) { |
5366 | 0 | return fastEmitInst_r(AArch64::FRINTAv2f64, &AArch64::FPR128RegClass, Op0); |
5367 | 0 | } |
5368 | 0 | return 0; |
5369 | 0 | } |
5370 | | |
5371 | 0 | unsigned fastEmit_ISD_STRICT_FROUND_r(MVT VT, MVT RetVT, unsigned Op0) { |
5372 | 0 | switch (VT.SimpleTy) { |
5373 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_FROUND_MVT_f16_r(RetVT, Op0); |
5374 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FROUND_MVT_f32_r(RetVT, Op0); |
5375 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FROUND_MVT_f64_r(RetVT, Op0); |
5376 | 0 | case MVT::v4f16: return fastEmit_ISD_STRICT_FROUND_MVT_v4f16_r(RetVT, Op0); |
5377 | 0 | case MVT::v8f16: return fastEmit_ISD_STRICT_FROUND_MVT_v8f16_r(RetVT, Op0); |
5378 | 0 | case MVT::v2f32: return fastEmit_ISD_STRICT_FROUND_MVT_v2f32_r(RetVT, Op0); |
5379 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FROUND_MVT_v4f32_r(RetVT, Op0); |
5380 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FROUND_MVT_v2f64_r(RetVT, Op0); |
5381 | 0 | default: return 0; |
5382 | 0 | } |
5383 | 0 | } |
5384 | | |
5385 | | // FastEmit functions for ISD::STRICT_FROUNDEVEN. |
5386 | | |
5387 | 0 | unsigned fastEmit_ISD_STRICT_FROUNDEVEN_MVT_f16_r(MVT RetVT, unsigned Op0) { |
5388 | 0 | if (RetVT.SimpleTy != MVT::f16) |
5389 | 0 | return 0; |
5390 | 0 | if ((Subtarget->hasFullFP16())) { |
5391 | 0 | return fastEmitInst_r(AArch64::FRINTNHr, &AArch64::FPR16RegClass, Op0); |
5392 | 0 | } |
5393 | 0 | return 0; |
5394 | 0 | } |
5395 | | |
5396 | 0 | unsigned fastEmit_ISD_STRICT_FROUNDEVEN_MVT_f32_r(MVT RetVT, unsigned Op0) { |
5397 | 0 | if (RetVT.SimpleTy != MVT::f32) |
5398 | 0 | return 0; |
5399 | 0 | if ((Subtarget->hasFPARMv8())) { |
5400 | 0 | return fastEmitInst_r(AArch64::FRINTNSr, &AArch64::FPR32RegClass, Op0); |
5401 | 0 | } |
5402 | 0 | return 0; |
5403 | 0 | } |
5404 | | |
5405 | 0 | unsigned fastEmit_ISD_STRICT_FROUNDEVEN_MVT_f64_r(MVT RetVT, unsigned Op0) { |
5406 | 0 | if (RetVT.SimpleTy != MVT::f64) |
5407 | 0 | return 0; |
5408 | 0 | if ((Subtarget->hasFPARMv8())) { |
5409 | 0 | return fastEmitInst_r(AArch64::FRINTNDr, &AArch64::FPR64RegClass, Op0); |
5410 | 0 | } |
5411 | 0 | return 0; |
5412 | 0 | } |
5413 | | |
5414 | 0 | unsigned fastEmit_ISD_STRICT_FROUNDEVEN_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
5415 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
5416 | 0 | return 0; |
5417 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
5418 | 0 | return fastEmitInst_r(AArch64::FRINTNv4f16, &AArch64::FPR64RegClass, Op0); |
5419 | 0 | } |
5420 | 0 | return 0; |
5421 | 0 | } |
5422 | | |
5423 | 0 | unsigned fastEmit_ISD_STRICT_FROUNDEVEN_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
5424 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
5425 | 0 | return 0; |
5426 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
5427 | 0 | return fastEmitInst_r(AArch64::FRINTNv8f16, &AArch64::FPR128RegClass, Op0); |
5428 | 0 | } |
5429 | 0 | return 0; |
5430 | 0 | } |
5431 | | |
5432 | 0 | unsigned fastEmit_ISD_STRICT_FROUNDEVEN_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
5433 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
5434 | 0 | return 0; |
5435 | 0 | if ((Subtarget->hasNEON())) { |
5436 | 0 | return fastEmitInst_r(AArch64::FRINTNv2f32, &AArch64::FPR64RegClass, Op0); |
5437 | 0 | } |
5438 | 0 | return 0; |
5439 | 0 | } |
5440 | | |
5441 | 0 | unsigned fastEmit_ISD_STRICT_FROUNDEVEN_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
5442 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
5443 | 0 | return 0; |
5444 | 0 | if ((Subtarget->hasNEON())) { |
5445 | 0 | return fastEmitInst_r(AArch64::FRINTNv4f32, &AArch64::FPR128RegClass, Op0); |
5446 | 0 | } |
5447 | 0 | return 0; |
5448 | 0 | } |
5449 | | |
5450 | 0 | unsigned fastEmit_ISD_STRICT_FROUNDEVEN_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
5451 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
5452 | 0 | return 0; |
5453 | 0 | if ((Subtarget->hasNEON())) { |
5454 | 0 | return fastEmitInst_r(AArch64::FRINTNv2f64, &AArch64::FPR128RegClass, Op0); |
5455 | 0 | } |
5456 | 0 | return 0; |
5457 | 0 | } |
5458 | | |
5459 | 0 | unsigned fastEmit_ISD_STRICT_FROUNDEVEN_r(MVT VT, MVT RetVT, unsigned Op0) { |
5460 | 0 | switch (VT.SimpleTy) { |
5461 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_FROUNDEVEN_MVT_f16_r(RetVT, Op0); |
5462 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FROUNDEVEN_MVT_f32_r(RetVT, Op0); |
5463 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FROUNDEVEN_MVT_f64_r(RetVT, Op0); |
5464 | 0 | case MVT::v4f16: return fastEmit_ISD_STRICT_FROUNDEVEN_MVT_v4f16_r(RetVT, Op0); |
5465 | 0 | case MVT::v8f16: return fastEmit_ISD_STRICT_FROUNDEVEN_MVT_v8f16_r(RetVT, Op0); |
5466 | 0 | case MVT::v2f32: return fastEmit_ISD_STRICT_FROUNDEVEN_MVT_v2f32_r(RetVT, Op0); |
5467 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FROUNDEVEN_MVT_v4f32_r(RetVT, Op0); |
5468 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FROUNDEVEN_MVT_v2f64_r(RetVT, Op0); |
5469 | 0 | default: return 0; |
5470 | 0 | } |
5471 | 0 | } |
5472 | | |
5473 | | // FastEmit functions for ISD::STRICT_FSQRT. |
5474 | | |
5475 | 0 | unsigned fastEmit_ISD_STRICT_FSQRT_MVT_f16_r(MVT RetVT, unsigned Op0) { |
5476 | 0 | if (RetVT.SimpleTy != MVT::f16) |
5477 | 0 | return 0; |
5478 | 0 | if ((Subtarget->hasFullFP16())) { |
5479 | 0 | return fastEmitInst_r(AArch64::FSQRTHr, &AArch64::FPR16RegClass, Op0); |
5480 | 0 | } |
5481 | 0 | return 0; |
5482 | 0 | } |
5483 | | |
5484 | 0 | unsigned fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
5485 | 0 | if (RetVT.SimpleTy != MVT::f32) |
5486 | 0 | return 0; |
5487 | 0 | if ((Subtarget->hasFPARMv8())) { |
5488 | 0 | return fastEmitInst_r(AArch64::FSQRTSr, &AArch64::FPR32RegClass, Op0); |
5489 | 0 | } |
5490 | 0 | return 0; |
5491 | 0 | } |
5492 | | |
5493 | 0 | unsigned fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
5494 | 0 | if (RetVT.SimpleTy != MVT::f64) |
5495 | 0 | return 0; |
5496 | 0 | if ((Subtarget->hasFPARMv8())) { |
5497 | 0 | return fastEmitInst_r(AArch64::FSQRTDr, &AArch64::FPR64RegClass, Op0); |
5498 | 0 | } |
5499 | 0 | return 0; |
5500 | 0 | } |
5501 | | |
5502 | 0 | unsigned fastEmit_ISD_STRICT_FSQRT_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
5503 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
5504 | 0 | return 0; |
5505 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
5506 | 0 | return fastEmitInst_r(AArch64::FSQRTv4f16, &AArch64::FPR64RegClass, Op0); |
5507 | 0 | } |
5508 | 0 | return 0; |
5509 | 0 | } |
5510 | | |
5511 | 0 | unsigned fastEmit_ISD_STRICT_FSQRT_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
5512 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
5513 | 0 | return 0; |
5514 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
5515 | 0 | return fastEmitInst_r(AArch64::FSQRTv8f16, &AArch64::FPR128RegClass, Op0); |
5516 | 0 | } |
5517 | 0 | return 0; |
5518 | 0 | } |
5519 | | |
5520 | 0 | unsigned fastEmit_ISD_STRICT_FSQRT_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
5521 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
5522 | 0 | return 0; |
5523 | 0 | if ((Subtarget->hasNEON())) { |
5524 | 0 | return fastEmitInst_r(AArch64::FSQRTv2f32, &AArch64::FPR64RegClass, Op0); |
5525 | 0 | } |
5526 | 0 | return 0; |
5527 | 0 | } |
5528 | | |
5529 | 0 | unsigned fastEmit_ISD_STRICT_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
5530 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
5531 | 0 | return 0; |
5532 | 0 | if ((Subtarget->hasNEON())) { |
5533 | 0 | return fastEmitInst_r(AArch64::FSQRTv4f32, &AArch64::FPR128RegClass, Op0); |
5534 | 0 | } |
5535 | 0 | return 0; |
5536 | 0 | } |
5537 | | |
5538 | 0 | unsigned fastEmit_ISD_STRICT_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
5539 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
5540 | 0 | return 0; |
5541 | 0 | if ((Subtarget->hasNEON())) { |
5542 | 0 | return fastEmitInst_r(AArch64::FSQRTv2f64, &AArch64::FPR128RegClass, Op0); |
5543 | 0 | } |
5544 | 0 | return 0; |
5545 | 0 | } |
5546 | | |
5547 | 0 | unsigned fastEmit_ISD_STRICT_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0) { |
5548 | 0 | switch (VT.SimpleTy) { |
5549 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_FSQRT_MVT_f16_r(RetVT, Op0); |
5550 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(RetVT, Op0); |
5551 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(RetVT, Op0); |
5552 | 0 | case MVT::v4f16: return fastEmit_ISD_STRICT_FSQRT_MVT_v4f16_r(RetVT, Op0); |
5553 | 0 | case MVT::v8f16: return fastEmit_ISD_STRICT_FSQRT_MVT_v8f16_r(RetVT, Op0); |
5554 | 0 | case MVT::v2f32: return fastEmit_ISD_STRICT_FSQRT_MVT_v2f32_r(RetVT, Op0); |
5555 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FSQRT_MVT_v4f32_r(RetVT, Op0); |
5556 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FSQRT_MVT_v2f64_r(RetVT, Op0); |
5557 | 0 | default: return 0; |
5558 | 0 | } |
5559 | 0 | } |
5560 | | |
5561 | | // FastEmit functions for ISD::STRICT_FTRUNC. |
5562 | | |
5563 | 0 | unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_f16_r(MVT RetVT, unsigned Op0) { |
5564 | 0 | if (RetVT.SimpleTy != MVT::f16) |
5565 | 0 | return 0; |
5566 | 0 | if ((Subtarget->hasFullFP16())) { |
5567 | 0 | return fastEmitInst_r(AArch64::FRINTZHr, &AArch64::FPR16RegClass, Op0); |
5568 | 0 | } |
5569 | 0 | return 0; |
5570 | 0 | } |
5571 | | |
5572 | 0 | unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0) { |
5573 | 0 | if (RetVT.SimpleTy != MVT::f32) |
5574 | 0 | return 0; |
5575 | 0 | if ((Subtarget->hasFPARMv8())) { |
5576 | 0 | return fastEmitInst_r(AArch64::FRINTZSr, &AArch64::FPR32RegClass, Op0); |
5577 | 0 | } |
5578 | 0 | return 0; |
5579 | 0 | } |
5580 | | |
5581 | 0 | unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0) { |
5582 | 0 | if (RetVT.SimpleTy != MVT::f64) |
5583 | 0 | return 0; |
5584 | 0 | if ((Subtarget->hasFPARMv8())) { |
5585 | 0 | return fastEmitInst_r(AArch64::FRINTZDr, &AArch64::FPR64RegClass, Op0); |
5586 | 0 | } |
5587 | 0 | return 0; |
5588 | 0 | } |
5589 | | |
5590 | 0 | unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
5591 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
5592 | 0 | return 0; |
5593 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
5594 | 0 | return fastEmitInst_r(AArch64::FRINTZv4f16, &AArch64::FPR64RegClass, Op0); |
5595 | 0 | } |
5596 | 0 | return 0; |
5597 | 0 | } |
5598 | | |
5599 | 0 | unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
5600 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
5601 | 0 | return 0; |
5602 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
5603 | 0 | return fastEmitInst_r(AArch64::FRINTZv8f16, &AArch64::FPR128RegClass, Op0); |
5604 | 0 | } |
5605 | 0 | return 0; |
5606 | 0 | } |
5607 | | |
5608 | 0 | unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
5609 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
5610 | 0 | return 0; |
5611 | 0 | if ((Subtarget->hasNEON())) { |
5612 | 0 | return fastEmitInst_r(AArch64::FRINTZv2f32, &AArch64::FPR64RegClass, Op0); |
5613 | 0 | } |
5614 | 0 | return 0; |
5615 | 0 | } |
5616 | | |
5617 | 0 | unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
5618 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
5619 | 0 | return 0; |
5620 | 0 | if ((Subtarget->hasNEON())) { |
5621 | 0 | return fastEmitInst_r(AArch64::FRINTZv4f32, &AArch64::FPR128RegClass, Op0); |
5622 | 0 | } |
5623 | 0 | return 0; |
5624 | 0 | } |
5625 | | |
5626 | 0 | unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
5627 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
5628 | 0 | return 0; |
5629 | 0 | if ((Subtarget->hasNEON())) { |
5630 | 0 | return fastEmitInst_r(AArch64::FRINTZv2f64, &AArch64::FPR128RegClass, Op0); |
5631 | 0 | } |
5632 | 0 | return 0; |
5633 | 0 | } |
5634 | | |
5635 | 0 | unsigned fastEmit_ISD_STRICT_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0) { |
5636 | 0 | switch (VT.SimpleTy) { |
5637 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_FTRUNC_MVT_f16_r(RetVT, Op0); |
5638 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FTRUNC_MVT_f32_r(RetVT, Op0); |
5639 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FTRUNC_MVT_f64_r(RetVT, Op0); |
5640 | 0 | case MVT::v4f16: return fastEmit_ISD_STRICT_FTRUNC_MVT_v4f16_r(RetVT, Op0); |
5641 | 0 | case MVT::v8f16: return fastEmit_ISD_STRICT_FTRUNC_MVT_v8f16_r(RetVT, Op0); |
5642 | 0 | case MVT::v2f32: return fastEmit_ISD_STRICT_FTRUNC_MVT_v2f32_r(RetVT, Op0); |
5643 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FTRUNC_MVT_v4f32_r(RetVT, Op0); |
5644 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FTRUNC_MVT_v2f64_r(RetVT, Op0); |
5645 | 0 | default: return 0; |
5646 | 0 | } |
5647 | 0 | } |
5648 | | |
5649 | | // FastEmit functions for ISD::STRICT_LLROUND. |
5650 | | |
5651 | 0 | unsigned fastEmit_ISD_STRICT_LLROUND_MVT_f16_r(MVT RetVT, unsigned Op0) { |
5652 | 0 | if (RetVT.SimpleTy != MVT::i64) |
5653 | 0 | return 0; |
5654 | 0 | if ((Subtarget->hasFullFP16())) { |
5655 | 0 | return fastEmitInst_r(AArch64::FCVTASUXHr, &AArch64::GPR64RegClass, Op0); |
5656 | 0 | } |
5657 | 0 | return 0; |
5658 | 0 | } |
5659 | | |
5660 | 0 | unsigned fastEmit_ISD_STRICT_LLROUND_MVT_f32_r(MVT RetVT, unsigned Op0) { |
5661 | 0 | if (RetVT.SimpleTy != MVT::i64) |
5662 | 0 | return 0; |
5663 | 0 | return fastEmitInst_r(AArch64::FCVTASUXSr, &AArch64::GPR64RegClass, Op0); |
5664 | 0 | } |
5665 | | |
5666 | 0 | unsigned fastEmit_ISD_STRICT_LLROUND_MVT_f64_r(MVT RetVT, unsigned Op0) { |
5667 | 0 | if (RetVT.SimpleTy != MVT::i64) |
5668 | 0 | return 0; |
5669 | 0 | return fastEmitInst_r(AArch64::FCVTASUXDr, &AArch64::GPR64RegClass, Op0); |
5670 | 0 | } |
5671 | | |
5672 | 0 | unsigned fastEmit_ISD_STRICT_LLROUND_r(MVT VT, MVT RetVT, unsigned Op0) { |
5673 | 0 | switch (VT.SimpleTy) { |
5674 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_LLROUND_MVT_f16_r(RetVT, Op0); |
5675 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_LLROUND_MVT_f32_r(RetVT, Op0); |
5676 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_LLROUND_MVT_f64_r(RetVT, Op0); |
5677 | 0 | default: return 0; |
5678 | 0 | } |
5679 | 0 | } |
5680 | | |
5681 | | // FastEmit functions for ISD::STRICT_LROUND. |
5682 | | |
5683 | 0 | unsigned fastEmit_ISD_STRICT_LROUND_MVT_f16_MVT_i32_r(unsigned Op0) { |
5684 | 0 | if ((Subtarget->hasFullFP16())) { |
5685 | 0 | return fastEmitInst_r(AArch64::FCVTASUWHr, &AArch64::GPR32RegClass, Op0); |
5686 | 0 | } |
5687 | 0 | return 0; |
5688 | 0 | } |
5689 | | |
5690 | 0 | unsigned fastEmit_ISD_STRICT_LROUND_MVT_f16_MVT_i64_r(unsigned Op0) { |
5691 | 0 | if ((Subtarget->hasFullFP16())) { |
5692 | 0 | return fastEmitInst_r(AArch64::FCVTASUXHr, &AArch64::GPR64RegClass, Op0); |
5693 | 0 | } |
5694 | 0 | return 0; |
5695 | 0 | } |
5696 | | |
5697 | 0 | unsigned fastEmit_ISD_STRICT_LROUND_MVT_f16_r(MVT RetVT, unsigned Op0) { |
5698 | 0 | switch (RetVT.SimpleTy) { |
5699 | 0 | case MVT::i32: return fastEmit_ISD_STRICT_LROUND_MVT_f16_MVT_i32_r(Op0); |
5700 | 0 | case MVT::i64: return fastEmit_ISD_STRICT_LROUND_MVT_f16_MVT_i64_r(Op0); |
5701 | 0 | default: return 0; |
5702 | 0 | } |
5703 | 0 | } |
5704 | | |
5705 | 0 | unsigned fastEmit_ISD_STRICT_LROUND_MVT_f32_MVT_i32_r(unsigned Op0) { |
5706 | 0 | return fastEmitInst_r(AArch64::FCVTASUWSr, &AArch64::GPR32RegClass, Op0); |
5707 | 0 | } |
5708 | | |
5709 | 0 | unsigned fastEmit_ISD_STRICT_LROUND_MVT_f32_MVT_i64_r(unsigned Op0) { |
5710 | 0 | return fastEmitInst_r(AArch64::FCVTASUXSr, &AArch64::GPR64RegClass, Op0); |
5711 | 0 | } |
5712 | | |
5713 | 0 | unsigned fastEmit_ISD_STRICT_LROUND_MVT_f32_r(MVT RetVT, unsigned Op0) { |
5714 | 0 | switch (RetVT.SimpleTy) { |
5715 | 0 | case MVT::i32: return fastEmit_ISD_STRICT_LROUND_MVT_f32_MVT_i32_r(Op0); |
5716 | 0 | case MVT::i64: return fastEmit_ISD_STRICT_LROUND_MVT_f32_MVT_i64_r(Op0); |
5717 | 0 | default: return 0; |
5718 | 0 | } |
5719 | 0 | } |
5720 | | |
5721 | 0 | unsigned fastEmit_ISD_STRICT_LROUND_MVT_f64_MVT_i32_r(unsigned Op0) { |
5722 | 0 | return fastEmitInst_r(AArch64::FCVTASUWDr, &AArch64::GPR32RegClass, Op0); |
5723 | 0 | } |
5724 | | |
5725 | 0 | unsigned fastEmit_ISD_STRICT_LROUND_MVT_f64_MVT_i64_r(unsigned Op0) { |
5726 | 0 | return fastEmitInst_r(AArch64::FCVTASUXDr, &AArch64::GPR64RegClass, Op0); |
5727 | 0 | } |
5728 | | |
5729 | 0 | unsigned fastEmit_ISD_STRICT_LROUND_MVT_f64_r(MVT RetVT, unsigned Op0) { |
5730 | 0 | switch (RetVT.SimpleTy) { |
5731 | 0 | case MVT::i32: return fastEmit_ISD_STRICT_LROUND_MVT_f64_MVT_i32_r(Op0); |
5732 | 0 | case MVT::i64: return fastEmit_ISD_STRICT_LROUND_MVT_f64_MVT_i64_r(Op0); |
5733 | 0 | default: return 0; |
5734 | 0 | } |
5735 | 0 | } |
5736 | | |
5737 | 0 | unsigned fastEmit_ISD_STRICT_LROUND_r(MVT VT, MVT RetVT, unsigned Op0) { |
5738 | 0 | switch (VT.SimpleTy) { |
5739 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_LROUND_MVT_f16_r(RetVT, Op0); |
5740 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_LROUND_MVT_f32_r(RetVT, Op0); |
5741 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_LROUND_MVT_f64_r(RetVT, Op0); |
5742 | 0 | default: return 0; |
5743 | 0 | } |
5744 | 0 | } |
5745 | | |
5746 | | // FastEmit functions for ISD::STRICT_SINT_TO_FP. |
5747 | | |
5748 | 0 | unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f16_r(unsigned Op0) { |
5749 | 0 | if ((Subtarget->hasFullFP16())) { |
5750 | 0 | return fastEmitInst_r(AArch64::SCVTFUWHri, &AArch64::FPR16RegClass, Op0); |
5751 | 0 | } |
5752 | 0 | return 0; |
5753 | 0 | } |
5754 | | |
5755 | 0 | unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) { |
5756 | 0 | if ((Subtarget->hasFPARMv8())) { |
5757 | 0 | return fastEmitInst_r(AArch64::SCVTFUWSri, &AArch64::FPR32RegClass, Op0); |
5758 | 0 | } |
5759 | 0 | return 0; |
5760 | 0 | } |
5761 | | |
5762 | 0 | unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) { |
5763 | 0 | if ((Subtarget->hasFPARMv8())) { |
5764 | 0 | return fastEmitInst_r(AArch64::SCVTFUWDri, &AArch64::FPR64RegClass, Op0); |
5765 | 0 | } |
5766 | 0 | return 0; |
5767 | 0 | } |
5768 | | |
5769 | 0 | unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
5770 | 0 | switch (RetVT.SimpleTy) { |
5771 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f16_r(Op0); |
5772 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0); |
5773 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0); |
5774 | 0 | default: return 0; |
5775 | 0 | } |
5776 | 0 | } |
5777 | | |
5778 | 0 | unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_MVT_f16_r(unsigned Op0) { |
5779 | 0 | if ((Subtarget->hasFullFP16())) { |
5780 | 0 | return fastEmitInst_r(AArch64::SCVTFUXHri, &AArch64::FPR16RegClass, Op0); |
5781 | 0 | } |
5782 | 0 | return 0; |
5783 | 0 | } |
5784 | | |
5785 | 0 | unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_MVT_f32_r(unsigned Op0) { |
5786 | 0 | if ((Subtarget->hasFPARMv8())) { |
5787 | 0 | return fastEmitInst_r(AArch64::SCVTFUXSri, &AArch64::FPR32RegClass, Op0); |
5788 | 0 | } |
5789 | 0 | return 0; |
5790 | 0 | } |
5791 | | |
5792 | 0 | unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_MVT_f64_r(unsigned Op0) { |
5793 | 0 | if ((Subtarget->hasFPARMv8())) { |
5794 | 0 | return fastEmitInst_r(AArch64::SCVTFUXDri, &AArch64::FPR64RegClass, Op0); |
5795 | 0 | } |
5796 | 0 | return 0; |
5797 | 0 | } |
5798 | | |
5799 | 0 | unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0) { |
5800 | 0 | switch (RetVT.SimpleTy) { |
5801 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_MVT_f16_r(Op0); |
5802 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_MVT_f32_r(Op0); |
5803 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_MVT_f64_r(Op0); |
5804 | 0 | default: return 0; |
5805 | 0 | } |
5806 | 0 | } |
5807 | | |
5808 | 0 | unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0) { |
5809 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
5810 | 0 | return 0; |
5811 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
5812 | 0 | return fastEmitInst_r(AArch64::SCVTFv4f16, &AArch64::FPR64RegClass, Op0); |
5813 | 0 | } |
5814 | 0 | return 0; |
5815 | 0 | } |
5816 | | |
5817 | 0 | unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
5818 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
5819 | 0 | return 0; |
5820 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
5821 | 0 | return fastEmitInst_r(AArch64::SCVTFv8f16, &AArch64::FPR128RegClass, Op0); |
5822 | 0 | } |
5823 | 0 | return 0; |
5824 | 0 | } |
5825 | | |
5826 | 0 | unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0) { |
5827 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
5828 | 0 | return 0; |
5829 | 0 | if ((Subtarget->hasNEON())) { |
5830 | 0 | return fastEmitInst_r(AArch64::SCVTFv2f32, &AArch64::FPR64RegClass, Op0); |
5831 | 0 | } |
5832 | 0 | return 0; |
5833 | 0 | } |
5834 | | |
5835 | 0 | unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
5836 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
5837 | 0 | return 0; |
5838 | 0 | if ((Subtarget->hasNEON())) { |
5839 | 0 | return fastEmitInst_r(AArch64::SCVTFv4f32, &AArch64::FPR128RegClass, Op0); |
5840 | 0 | } |
5841 | 0 | return 0; |
5842 | 0 | } |
5843 | | |
5844 | 0 | unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
5845 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
5846 | 0 | return 0; |
5847 | 0 | if ((Subtarget->hasNEON())) { |
5848 | 0 | return fastEmitInst_r(AArch64::SCVTFv2f64, &AArch64::FPR128RegClass, Op0); |
5849 | 0 | } |
5850 | 0 | return 0; |
5851 | 0 | } |
5852 | | |
5853 | 0 | unsigned fastEmit_ISD_STRICT_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) { |
5854 | 0 | switch (VT.SimpleTy) { |
5855 | 0 | case MVT::i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(RetVT, Op0); |
5856 | 0 | case MVT::i64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_r(RetVT, Op0); |
5857 | 0 | case MVT::v4i16: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i16_r(RetVT, Op0); |
5858 | 0 | case MVT::v8i16: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v8i16_r(RetVT, Op0); |
5859 | 0 | case MVT::v2i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v2i32_r(RetVT, Op0); |
5860 | 0 | case MVT::v4i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0); |
5861 | 0 | case MVT::v2i64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0); |
5862 | 0 | default: return 0; |
5863 | 0 | } |
5864 | 0 | } |
5865 | | |
5866 | | // FastEmit functions for ISD::STRICT_UINT_TO_FP. |
5867 | | |
5868 | 0 | unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f16_r(unsigned Op0) { |
5869 | 0 | if ((Subtarget->hasFullFP16())) { |
5870 | 0 | return fastEmitInst_r(AArch64::UCVTFUWHri, &AArch64::FPR16RegClass, Op0); |
5871 | 0 | } |
5872 | 0 | return 0; |
5873 | 0 | } |
5874 | | |
5875 | 0 | unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) { |
5876 | 0 | if ((Subtarget->hasFPARMv8())) { |
5877 | 0 | return fastEmitInst_r(AArch64::UCVTFUWSri, &AArch64::FPR32RegClass, Op0); |
5878 | 0 | } |
5879 | 0 | return 0; |
5880 | 0 | } |
5881 | | |
5882 | 0 | unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) { |
5883 | 0 | if ((Subtarget->hasFPARMv8())) { |
5884 | 0 | return fastEmitInst_r(AArch64::UCVTFUWDri, &AArch64::FPR64RegClass, Op0); |
5885 | 0 | } |
5886 | 0 | return 0; |
5887 | 0 | } |
5888 | | |
5889 | 0 | unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
5890 | 0 | switch (RetVT.SimpleTy) { |
5891 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f16_r(Op0); |
5892 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0); |
5893 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0); |
5894 | 0 | default: return 0; |
5895 | 0 | } |
5896 | 0 | } |
5897 | | |
5898 | 0 | unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i64_MVT_f16_r(unsigned Op0) { |
5899 | 0 | if ((Subtarget->hasFullFP16())) { |
5900 | 0 | return fastEmitInst_r(AArch64::UCVTFUXHri, &AArch64::FPR16RegClass, Op0); |
5901 | 0 | } |
5902 | 0 | return 0; |
5903 | 0 | } |
5904 | | |
5905 | 0 | unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i64_MVT_f32_r(unsigned Op0) { |
5906 | 0 | if ((Subtarget->hasFPARMv8())) { |
5907 | 0 | return fastEmitInst_r(AArch64::UCVTFUXSri, &AArch64::FPR32RegClass, Op0); |
5908 | 0 | } |
5909 | 0 | return 0; |
5910 | 0 | } |
5911 | | |
5912 | 0 | unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i64_MVT_f64_r(unsigned Op0) { |
5913 | 0 | if ((Subtarget->hasFPARMv8())) { |
5914 | 0 | return fastEmitInst_r(AArch64::UCVTFUXDri, &AArch64::FPR64RegClass, Op0); |
5915 | 0 | } |
5916 | 0 | return 0; |
5917 | 0 | } |
5918 | | |
5919 | 0 | unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0) { |
5920 | 0 | switch (RetVT.SimpleTy) { |
5921 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i64_MVT_f16_r(Op0); |
5922 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i64_MVT_f32_r(Op0); |
5923 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i64_MVT_f64_r(Op0); |
5924 | 0 | default: return 0; |
5925 | 0 | } |
5926 | 0 | } |
5927 | | |
5928 | 0 | unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0) { |
5929 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
5930 | 0 | return 0; |
5931 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
5932 | 0 | return fastEmitInst_r(AArch64::UCVTFv4f16, &AArch64::FPR64RegClass, Op0); |
5933 | 0 | } |
5934 | 0 | return 0; |
5935 | 0 | } |
5936 | | |
5937 | 0 | unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
5938 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
5939 | 0 | return 0; |
5940 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
5941 | 0 | return fastEmitInst_r(AArch64::UCVTFv8f16, &AArch64::FPR128RegClass, Op0); |
5942 | 0 | } |
5943 | 0 | return 0; |
5944 | 0 | } |
5945 | | |
5946 | 0 | unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0) { |
5947 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
5948 | 0 | return 0; |
5949 | 0 | if ((Subtarget->hasNEON())) { |
5950 | 0 | return fastEmitInst_r(AArch64::UCVTFv2f32, &AArch64::FPR64RegClass, Op0); |
5951 | 0 | } |
5952 | 0 | return 0; |
5953 | 0 | } |
5954 | | |
5955 | 0 | unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
5956 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
5957 | 0 | return 0; |
5958 | 0 | if ((Subtarget->hasNEON())) { |
5959 | 0 | return fastEmitInst_r(AArch64::UCVTFv4f32, &AArch64::FPR128RegClass, Op0); |
5960 | 0 | } |
5961 | 0 | return 0; |
5962 | 0 | } |
5963 | | |
5964 | 0 | unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
5965 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
5966 | 0 | return 0; |
5967 | 0 | if ((Subtarget->hasNEON())) { |
5968 | 0 | return fastEmitInst_r(AArch64::UCVTFv2f64, &AArch64::FPR128RegClass, Op0); |
5969 | 0 | } |
5970 | 0 | return 0; |
5971 | 0 | } |
5972 | | |
5973 | 0 | unsigned fastEmit_ISD_STRICT_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) { |
5974 | 0 | switch (VT.SimpleTy) { |
5975 | 0 | case MVT::i32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_r(RetVT, Op0); |
5976 | 0 | case MVT::i64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i64_r(RetVT, Op0); |
5977 | 0 | case MVT::v4i16: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i16_r(RetVT, Op0); |
5978 | 0 | case MVT::v8i16: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v8i16_r(RetVT, Op0); |
5979 | 0 | case MVT::v2i32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v2i32_r(RetVT, Op0); |
5980 | 0 | case MVT::v4i32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0); |
5981 | 0 | case MVT::v2i64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0); |
5982 | 0 | default: return 0; |
5983 | 0 | } |
5984 | 0 | } |
5985 | | |
5986 | | // FastEmit functions for ISD::TRUNCATE. |
5987 | | |
5988 | 0 | unsigned fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, unsigned Op0) { |
5989 | 0 | if (RetVT.SimpleTy != MVT::i32) |
5990 | 0 | return 0; |
5991 | 0 | return fastEmitInst_extractsubreg(RetVT, Op0, AArch64::sub_32); |
5992 | 0 | } |
5993 | | |
5994 | 0 | unsigned fastEmit_ISD_TRUNCATE_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
5995 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
5996 | 0 | return 0; |
5997 | 0 | if ((Subtarget->hasNEON())) { |
5998 | 0 | return fastEmitInst_r(AArch64::XTNv8i8, &AArch64::FPR64RegClass, Op0); |
5999 | 0 | } |
6000 | 0 | return 0; |
6001 | 0 | } |
6002 | | |
6003 | 0 | unsigned fastEmit_ISD_TRUNCATE_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
6004 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
6005 | 0 | return 0; |
6006 | 0 | if ((Subtarget->hasNEON())) { |
6007 | 0 | return fastEmitInst_r(AArch64::XTNv4i16, &AArch64::FPR64RegClass, Op0); |
6008 | 0 | } |
6009 | 0 | return 0; |
6010 | 0 | } |
6011 | | |
6012 | 0 | unsigned fastEmit_ISD_TRUNCATE_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
6013 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
6014 | 0 | return 0; |
6015 | 0 | if ((Subtarget->hasNEON())) { |
6016 | 0 | return fastEmitInst_r(AArch64::XTNv2i32, &AArch64::FPR64RegClass, Op0); |
6017 | 0 | } |
6018 | 0 | return 0; |
6019 | 0 | } |
6020 | | |
6021 | 0 | unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0) { |
6022 | 0 | switch (VT.SimpleTy) { |
6023 | 0 | case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0); |
6024 | 0 | case MVT::v8i16: return fastEmit_ISD_TRUNCATE_MVT_v8i16_r(RetVT, Op0); |
6025 | 0 | case MVT::v4i32: return fastEmit_ISD_TRUNCATE_MVT_v4i32_r(RetVT, Op0); |
6026 | 0 | case MVT::v2i64: return fastEmit_ISD_TRUNCATE_MVT_v2i64_r(RetVT, Op0); |
6027 | 0 | default: return 0; |
6028 | 0 | } |
6029 | 0 | } |
6030 | | |
6031 | | // FastEmit functions for ISD::UINT_TO_FP. |
6032 | | |
6033 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f16_r(unsigned Op0) { |
6034 | 0 | if ((Subtarget->hasFullFP16())) { |
6035 | 0 | return fastEmitInst_r(AArch64::UCVTFUWHri, &AArch64::FPR16RegClass, Op0); |
6036 | 0 | } |
6037 | 0 | return 0; |
6038 | 0 | } |
6039 | | |
6040 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) { |
6041 | 0 | if ((Subtarget->hasFPARMv8())) { |
6042 | 0 | return fastEmitInst_r(AArch64::UCVTFUWSri, &AArch64::FPR32RegClass, Op0); |
6043 | 0 | } |
6044 | 0 | return 0; |
6045 | 0 | } |
6046 | | |
6047 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) { |
6048 | 0 | if ((Subtarget->hasFPARMv8())) { |
6049 | 0 | return fastEmitInst_r(AArch64::UCVTFUWDri, &AArch64::FPR64RegClass, Op0); |
6050 | 0 | } |
6051 | 0 | return 0; |
6052 | 0 | } |
6053 | | |
6054 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
6055 | 0 | switch (RetVT.SimpleTy) { |
6056 | 0 | case MVT::f16: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f16_r(Op0); |
6057 | 0 | case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0); |
6058 | 0 | case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0); |
6059 | 0 | default: return 0; |
6060 | 0 | } |
6061 | 0 | } |
6062 | | |
6063 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f16_r(unsigned Op0) { |
6064 | 0 | if ((Subtarget->hasFullFP16())) { |
6065 | 0 | return fastEmitInst_r(AArch64::UCVTFUXHri, &AArch64::FPR16RegClass, Op0); |
6066 | 0 | } |
6067 | 0 | return 0; |
6068 | 0 | } |
6069 | | |
6070 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f32_r(unsigned Op0) { |
6071 | 0 | if ((Subtarget->hasFPARMv8())) { |
6072 | 0 | return fastEmitInst_r(AArch64::UCVTFUXSri, &AArch64::FPR32RegClass, Op0); |
6073 | 0 | } |
6074 | 0 | return 0; |
6075 | 0 | } |
6076 | | |
6077 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f64_r(unsigned Op0) { |
6078 | 0 | if ((Subtarget->hasFPARMv8())) { |
6079 | 0 | return fastEmitInst_r(AArch64::UCVTFUXDri, &AArch64::FPR64RegClass, Op0); |
6080 | 0 | } |
6081 | 0 | return 0; |
6082 | 0 | } |
6083 | | |
6084 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0) { |
6085 | 0 | switch (RetVT.SimpleTy) { |
6086 | 0 | case MVT::f16: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f16_r(Op0); |
6087 | 0 | case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f32_r(Op0); |
6088 | 0 | case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f64_r(Op0); |
6089 | 0 | default: return 0; |
6090 | 0 | } |
6091 | 0 | } |
6092 | | |
6093 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0) { |
6094 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
6095 | 0 | return 0; |
6096 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
6097 | 0 | return fastEmitInst_r(AArch64::UCVTFv4f16, &AArch64::FPR64RegClass, Op0); |
6098 | 0 | } |
6099 | 0 | return 0; |
6100 | 0 | } |
6101 | | |
6102 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
6103 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
6104 | 0 | return 0; |
6105 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
6106 | 0 | return fastEmitInst_r(AArch64::UCVTFv8f16, &AArch64::FPR128RegClass, Op0); |
6107 | 0 | } |
6108 | 0 | return 0; |
6109 | 0 | } |
6110 | | |
6111 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0) { |
6112 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
6113 | 0 | return 0; |
6114 | 0 | if ((Subtarget->hasNEON())) { |
6115 | 0 | return fastEmitInst_r(AArch64::UCVTFv2f32, &AArch64::FPR64RegClass, Op0); |
6116 | 0 | } |
6117 | 0 | return 0; |
6118 | 0 | } |
6119 | | |
6120 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
6121 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
6122 | 0 | return 0; |
6123 | 0 | if ((Subtarget->hasNEON())) { |
6124 | 0 | return fastEmitInst_r(AArch64::UCVTFv4f32, &AArch64::FPR128RegClass, Op0); |
6125 | 0 | } |
6126 | 0 | return 0; |
6127 | 0 | } |
6128 | | |
6129 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
6130 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
6131 | 0 | return 0; |
6132 | 0 | if ((Subtarget->hasNEON())) { |
6133 | 0 | return fastEmitInst_r(AArch64::UCVTFv2f64, &AArch64::FPR128RegClass, Op0); |
6134 | 0 | } |
6135 | 0 | return 0; |
6136 | 0 | } |
6137 | | |
6138 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) { |
6139 | 0 | switch (VT.SimpleTy) { |
6140 | 0 | case MVT::i32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_r(RetVT, Op0); |
6141 | 0 | case MVT::i64: return fastEmit_ISD_UINT_TO_FP_MVT_i64_r(RetVT, Op0); |
6142 | 0 | case MVT::v4i16: return fastEmit_ISD_UINT_TO_FP_MVT_v4i16_r(RetVT, Op0); |
6143 | 0 | case MVT::v8i16: return fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(RetVT, Op0); |
6144 | 0 | case MVT::v2i32: return fastEmit_ISD_UINT_TO_FP_MVT_v2i32_r(RetVT, Op0); |
6145 | 0 | case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0); |
6146 | 0 | case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0); |
6147 | 0 | default: return 0; |
6148 | 0 | } |
6149 | 0 | } |
6150 | | |
6151 | | // FastEmit functions for ISD::VECREDUCE_ADD. |
6152 | | |
6153 | 0 | unsigned fastEmit_ISD_VECREDUCE_ADD_MVT_v8i8_r(MVT RetVT, unsigned Op0) { |
6154 | 0 | if (RetVT.SimpleTy != MVT::i8) |
6155 | 0 | return 0; |
6156 | 0 | return fastEmitInst_r(AArch64::ADDVv8i8v, &AArch64::FPR8RegClass, Op0); |
6157 | 0 | } |
6158 | | |
6159 | 0 | unsigned fastEmit_ISD_VECREDUCE_ADD_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
6160 | 0 | if (RetVT.SimpleTy != MVT::i8) |
6161 | 0 | return 0; |
6162 | 0 | return fastEmitInst_r(AArch64::ADDVv16i8v, &AArch64::FPR8RegClass, Op0); |
6163 | 0 | } |
6164 | | |
6165 | 0 | unsigned fastEmit_ISD_VECREDUCE_ADD_MVT_v4i16_r(MVT RetVT, unsigned Op0) { |
6166 | 0 | if (RetVT.SimpleTy != MVT::i16) |
6167 | 0 | return 0; |
6168 | 0 | return fastEmitInst_r(AArch64::ADDVv4i16v, &AArch64::FPR16RegClass, Op0); |
6169 | 0 | } |
6170 | | |
6171 | 0 | unsigned fastEmit_ISD_VECREDUCE_ADD_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
6172 | 0 | if (RetVT.SimpleTy != MVT::i16) |
6173 | 0 | return 0; |
6174 | 0 | return fastEmitInst_r(AArch64::ADDVv8i16v, &AArch64::FPR16RegClass, Op0); |
6175 | 0 | } |
6176 | | |
6177 | 0 | unsigned fastEmit_ISD_VECREDUCE_ADD_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
6178 | 0 | if (RetVT.SimpleTy != MVT::i32) |
6179 | 0 | return 0; |
6180 | 0 | return fastEmitInst_r(AArch64::ADDVv4i32v, &AArch64::FPR32RegClass, Op0); |
6181 | 0 | } |
6182 | | |
6183 | 0 | unsigned fastEmit_ISD_VECREDUCE_ADD_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
6184 | 0 | if (RetVT.SimpleTy != MVT::i64) |
6185 | 0 | return 0; |
6186 | 0 | return fastEmitInst_r(AArch64::ADDPv2i64p, &AArch64::FPR64RegClass, Op0); |
6187 | 0 | } |
6188 | | |
6189 | 0 | unsigned fastEmit_ISD_VECREDUCE_ADD_r(MVT VT, MVT RetVT, unsigned Op0) { |
6190 | 0 | switch (VT.SimpleTy) { |
6191 | 0 | case MVT::v8i8: return fastEmit_ISD_VECREDUCE_ADD_MVT_v8i8_r(RetVT, Op0); |
6192 | 0 | case MVT::v16i8: return fastEmit_ISD_VECREDUCE_ADD_MVT_v16i8_r(RetVT, Op0); |
6193 | 0 | case MVT::v4i16: return fastEmit_ISD_VECREDUCE_ADD_MVT_v4i16_r(RetVT, Op0); |
6194 | 0 | case MVT::v8i16: return fastEmit_ISD_VECREDUCE_ADD_MVT_v8i16_r(RetVT, Op0); |
6195 | 0 | case MVT::v4i32: return fastEmit_ISD_VECREDUCE_ADD_MVT_v4i32_r(RetVT, Op0); |
6196 | 0 | case MVT::v2i64: return fastEmit_ISD_VECREDUCE_ADD_MVT_v2i64_r(RetVT, Op0); |
6197 | 0 | default: return 0; |
6198 | 0 | } |
6199 | 0 | } |
6200 | | |
6201 | | // FastEmit functions for ISD::VECREDUCE_FADD. |
6202 | | |
6203 | 0 | unsigned fastEmit_ISD_VECREDUCE_FADD_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
6204 | 0 | if (RetVT.SimpleTy != MVT::f32) |
6205 | 0 | return 0; |
6206 | 0 | return fastEmitInst_r(AArch64::FADDPv2i32p, &AArch64::FPR32RegClass, Op0); |
6207 | 0 | } |
6208 | | |
6209 | 0 | unsigned fastEmit_ISD_VECREDUCE_FADD_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
6210 | 0 | if (RetVT.SimpleTy != MVT::f64) |
6211 | 0 | return 0; |
6212 | 0 | return fastEmitInst_r(AArch64::FADDPv2i64p, &AArch64::FPR64RegClass, Op0); |
6213 | 0 | } |
6214 | | |
6215 | 0 | unsigned fastEmit_ISD_VECREDUCE_FADD_r(MVT VT, MVT RetVT, unsigned Op0) { |
6216 | 0 | switch (VT.SimpleTy) { |
6217 | 0 | case MVT::v2f32: return fastEmit_ISD_VECREDUCE_FADD_MVT_v2f32_r(RetVT, Op0); |
6218 | 0 | case MVT::v2f64: return fastEmit_ISD_VECREDUCE_FADD_MVT_v2f64_r(RetVT, Op0); |
6219 | 0 | default: return 0; |
6220 | 0 | } |
6221 | 0 | } |
6222 | | |
6223 | | // FastEmit functions for ISD::VECREDUCE_FMAX. |
6224 | | |
6225 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMAX_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
6226 | 0 | if (RetVT.SimpleTy != MVT::f16) |
6227 | 0 | return 0; |
6228 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
6229 | 0 | return fastEmitInst_r(AArch64::FMAXNMVv4i16v, &AArch64::FPR16RegClass, Op0); |
6230 | 0 | } |
6231 | 0 | return 0; |
6232 | 0 | } |
6233 | | |
6234 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMAX_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
6235 | 0 | if (RetVT.SimpleTy != MVT::f16) |
6236 | 0 | return 0; |
6237 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
6238 | 0 | return fastEmitInst_r(AArch64::FMAXNMVv8i16v, &AArch64::FPR16RegClass, Op0); |
6239 | 0 | } |
6240 | 0 | return 0; |
6241 | 0 | } |
6242 | | |
6243 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMAX_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
6244 | 0 | if (RetVT.SimpleTy != MVT::f32) |
6245 | 0 | return 0; |
6246 | 0 | return fastEmitInst_r(AArch64::FMAXNMPv2i32p, &AArch64::FPR32RegClass, Op0); |
6247 | 0 | } |
6248 | | |
6249 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMAX_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
6250 | 0 | if (RetVT.SimpleTy != MVT::f32) |
6251 | 0 | return 0; |
6252 | 0 | if ((Subtarget->hasNEON())) { |
6253 | 0 | return fastEmitInst_r(AArch64::FMAXNMVv4i32v, &AArch64::FPR32RegClass, Op0); |
6254 | 0 | } |
6255 | 0 | return 0; |
6256 | 0 | } |
6257 | | |
6258 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMAX_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
6259 | 0 | if (RetVT.SimpleTy != MVT::f64) |
6260 | 0 | return 0; |
6261 | 0 | return fastEmitInst_r(AArch64::FMAXNMPv2i64p, &AArch64::FPR64RegClass, Op0); |
6262 | 0 | } |
6263 | | |
6264 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMAX_r(MVT VT, MVT RetVT, unsigned Op0) { |
6265 | 0 | switch (VT.SimpleTy) { |
6266 | 0 | case MVT::v4f16: return fastEmit_ISD_VECREDUCE_FMAX_MVT_v4f16_r(RetVT, Op0); |
6267 | 0 | case MVT::v8f16: return fastEmit_ISD_VECREDUCE_FMAX_MVT_v8f16_r(RetVT, Op0); |
6268 | 0 | case MVT::v2f32: return fastEmit_ISD_VECREDUCE_FMAX_MVT_v2f32_r(RetVT, Op0); |
6269 | 0 | case MVT::v4f32: return fastEmit_ISD_VECREDUCE_FMAX_MVT_v4f32_r(RetVT, Op0); |
6270 | 0 | case MVT::v2f64: return fastEmit_ISD_VECREDUCE_FMAX_MVT_v2f64_r(RetVT, Op0); |
6271 | 0 | default: return 0; |
6272 | 0 | } |
6273 | 0 | } |
6274 | | |
6275 | | // FastEmit functions for ISD::VECREDUCE_FMAXIMUM. |
6276 | | |
6277 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMAXIMUM_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
6278 | 0 | if (RetVT.SimpleTy != MVT::f16) |
6279 | 0 | return 0; |
6280 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
6281 | 0 | return fastEmitInst_r(AArch64::FMAXVv4i16v, &AArch64::FPR16RegClass, Op0); |
6282 | 0 | } |
6283 | 0 | return 0; |
6284 | 0 | } |
6285 | | |
6286 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMAXIMUM_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
6287 | 0 | if (RetVT.SimpleTy != MVT::f16) |
6288 | 0 | return 0; |
6289 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
6290 | 0 | return fastEmitInst_r(AArch64::FMAXVv8i16v, &AArch64::FPR16RegClass, Op0); |
6291 | 0 | } |
6292 | 0 | return 0; |
6293 | 0 | } |
6294 | | |
6295 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMAXIMUM_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
6296 | 0 | if (RetVT.SimpleTy != MVT::f32) |
6297 | 0 | return 0; |
6298 | 0 | return fastEmitInst_r(AArch64::FMAXPv2i32p, &AArch64::FPR32RegClass, Op0); |
6299 | 0 | } |
6300 | | |
6301 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMAXIMUM_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
6302 | 0 | if (RetVT.SimpleTy != MVT::f32) |
6303 | 0 | return 0; |
6304 | 0 | if ((Subtarget->hasNEON())) { |
6305 | 0 | return fastEmitInst_r(AArch64::FMAXVv4i32v, &AArch64::FPR32RegClass, Op0); |
6306 | 0 | } |
6307 | 0 | return 0; |
6308 | 0 | } |
6309 | | |
6310 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMAXIMUM_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
6311 | 0 | if (RetVT.SimpleTy != MVT::f64) |
6312 | 0 | return 0; |
6313 | 0 | return fastEmitInst_r(AArch64::FMAXPv2i64p, &AArch64::FPR64RegClass, Op0); |
6314 | 0 | } |
6315 | | |
6316 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMAXIMUM_r(MVT VT, MVT RetVT, unsigned Op0) { |
6317 | 0 | switch (VT.SimpleTy) { |
6318 | 0 | case MVT::v4f16: return fastEmit_ISD_VECREDUCE_FMAXIMUM_MVT_v4f16_r(RetVT, Op0); |
6319 | 0 | case MVT::v8f16: return fastEmit_ISD_VECREDUCE_FMAXIMUM_MVT_v8f16_r(RetVT, Op0); |
6320 | 0 | case MVT::v2f32: return fastEmit_ISD_VECREDUCE_FMAXIMUM_MVT_v2f32_r(RetVT, Op0); |
6321 | 0 | case MVT::v4f32: return fastEmit_ISD_VECREDUCE_FMAXIMUM_MVT_v4f32_r(RetVT, Op0); |
6322 | 0 | case MVT::v2f64: return fastEmit_ISD_VECREDUCE_FMAXIMUM_MVT_v2f64_r(RetVT, Op0); |
6323 | 0 | default: return 0; |
6324 | 0 | } |
6325 | 0 | } |
6326 | | |
6327 | | // FastEmit functions for ISD::VECREDUCE_FMIN. |
6328 | | |
6329 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMIN_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
6330 | 0 | if (RetVT.SimpleTy != MVT::f16) |
6331 | 0 | return 0; |
6332 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
6333 | 0 | return fastEmitInst_r(AArch64::FMINNMVv4i16v, &AArch64::FPR16RegClass, Op0); |
6334 | 0 | } |
6335 | 0 | return 0; |
6336 | 0 | } |
6337 | | |
6338 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMIN_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
6339 | 0 | if (RetVT.SimpleTy != MVT::f16) |
6340 | 0 | return 0; |
6341 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
6342 | 0 | return fastEmitInst_r(AArch64::FMINNMVv8i16v, &AArch64::FPR16RegClass, Op0); |
6343 | 0 | } |
6344 | 0 | return 0; |
6345 | 0 | } |
6346 | | |
6347 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMIN_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
6348 | 0 | if (RetVT.SimpleTy != MVT::f32) |
6349 | 0 | return 0; |
6350 | 0 | return fastEmitInst_r(AArch64::FMINNMPv2i32p, &AArch64::FPR32RegClass, Op0); |
6351 | 0 | } |
6352 | | |
6353 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMIN_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
6354 | 0 | if (RetVT.SimpleTy != MVT::f32) |
6355 | 0 | return 0; |
6356 | 0 | if ((Subtarget->hasNEON())) { |
6357 | 0 | return fastEmitInst_r(AArch64::FMINNMVv4i32v, &AArch64::FPR32RegClass, Op0); |
6358 | 0 | } |
6359 | 0 | return 0; |
6360 | 0 | } |
6361 | | |
6362 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMIN_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
6363 | 0 | if (RetVT.SimpleTy != MVT::f64) |
6364 | 0 | return 0; |
6365 | 0 | return fastEmitInst_r(AArch64::FMINNMPv2i64p, &AArch64::FPR64RegClass, Op0); |
6366 | 0 | } |
6367 | | |
6368 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMIN_r(MVT VT, MVT RetVT, unsigned Op0) { |
6369 | 0 | switch (VT.SimpleTy) { |
6370 | 0 | case MVT::v4f16: return fastEmit_ISD_VECREDUCE_FMIN_MVT_v4f16_r(RetVT, Op0); |
6371 | 0 | case MVT::v8f16: return fastEmit_ISD_VECREDUCE_FMIN_MVT_v8f16_r(RetVT, Op0); |
6372 | 0 | case MVT::v2f32: return fastEmit_ISD_VECREDUCE_FMIN_MVT_v2f32_r(RetVT, Op0); |
6373 | 0 | case MVT::v4f32: return fastEmit_ISD_VECREDUCE_FMIN_MVT_v4f32_r(RetVT, Op0); |
6374 | 0 | case MVT::v2f64: return fastEmit_ISD_VECREDUCE_FMIN_MVT_v2f64_r(RetVT, Op0); |
6375 | 0 | default: return 0; |
6376 | 0 | } |
6377 | 0 | } |
6378 | | |
6379 | | // FastEmit functions for ISD::VECREDUCE_FMINIMUM. |
6380 | | |
6381 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMINIMUM_MVT_v4f16_r(MVT RetVT, unsigned Op0) { |
6382 | 0 | if (RetVT.SimpleTy != MVT::f16) |
6383 | 0 | return 0; |
6384 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
6385 | 0 | return fastEmitInst_r(AArch64::FMINVv4i16v, &AArch64::FPR16RegClass, Op0); |
6386 | 0 | } |
6387 | 0 | return 0; |
6388 | 0 | } |
6389 | | |
6390 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMINIMUM_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
6391 | 0 | if (RetVT.SimpleTy != MVT::f16) |
6392 | 0 | return 0; |
6393 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
6394 | 0 | return fastEmitInst_r(AArch64::FMINVv8i16v, &AArch64::FPR16RegClass, Op0); |
6395 | 0 | } |
6396 | 0 | return 0; |
6397 | 0 | } |
6398 | | |
6399 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMINIMUM_MVT_v2f32_r(MVT RetVT, unsigned Op0) { |
6400 | 0 | if (RetVT.SimpleTy != MVT::f32) |
6401 | 0 | return 0; |
6402 | 0 | return fastEmitInst_r(AArch64::FMINPv2i32p, &AArch64::FPR32RegClass, Op0); |
6403 | 0 | } |
6404 | | |
6405 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMINIMUM_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
6406 | 0 | if (RetVT.SimpleTy != MVT::f32) |
6407 | 0 | return 0; |
6408 | 0 | if ((Subtarget->hasNEON())) { |
6409 | 0 | return fastEmitInst_r(AArch64::FMINVv4i32v, &AArch64::FPR32RegClass, Op0); |
6410 | 0 | } |
6411 | 0 | return 0; |
6412 | 0 | } |
6413 | | |
6414 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMINIMUM_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
6415 | 0 | if (RetVT.SimpleTy != MVT::f64) |
6416 | 0 | return 0; |
6417 | 0 | return fastEmitInst_r(AArch64::FMINPv2i64p, &AArch64::FPR64RegClass, Op0); |
6418 | 0 | } |
6419 | | |
6420 | 0 | unsigned fastEmit_ISD_VECREDUCE_FMINIMUM_r(MVT VT, MVT RetVT, unsigned Op0) { |
6421 | 0 | switch (VT.SimpleTy) { |
6422 | 0 | case MVT::v4f16: return fastEmit_ISD_VECREDUCE_FMINIMUM_MVT_v4f16_r(RetVT, Op0); |
6423 | 0 | case MVT::v8f16: return fastEmit_ISD_VECREDUCE_FMINIMUM_MVT_v8f16_r(RetVT, Op0); |
6424 | 0 | case MVT::v2f32: return fastEmit_ISD_VECREDUCE_FMINIMUM_MVT_v2f32_r(RetVT, Op0); |
6425 | 0 | case MVT::v4f32: return fastEmit_ISD_VECREDUCE_FMINIMUM_MVT_v4f32_r(RetVT, Op0); |
6426 | 0 | case MVT::v2f64: return fastEmit_ISD_VECREDUCE_FMINIMUM_MVT_v2f64_r(RetVT, Op0); |
6427 | 0 | default: return 0; |
6428 | 0 | } |
6429 | 0 | } |
6430 | | |
6431 | | // FastEmit functions for ISD::VECREDUCE_SMAX. |
6432 | | |
6433 | 0 | unsigned fastEmit_ISD_VECREDUCE_SMAX_MVT_v8i8_r(MVT RetVT, unsigned Op0) { |
6434 | 0 | if (RetVT.SimpleTy != MVT::i8) |
6435 | 0 | return 0; |
6436 | 0 | return fastEmitInst_r(AArch64::SMAXVv8i8v, &AArch64::FPR8RegClass, Op0); |
6437 | 0 | } |
6438 | | |
6439 | 0 | unsigned fastEmit_ISD_VECREDUCE_SMAX_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
6440 | 0 | if (RetVT.SimpleTy != MVT::i8) |
6441 | 0 | return 0; |
6442 | 0 | return fastEmitInst_r(AArch64::SMAXVv16i8v, &AArch64::FPR8RegClass, Op0); |
6443 | 0 | } |
6444 | | |
6445 | 0 | unsigned fastEmit_ISD_VECREDUCE_SMAX_MVT_v4i16_r(MVT RetVT, unsigned Op0) { |
6446 | 0 | if (RetVT.SimpleTy != MVT::i16) |
6447 | 0 | return 0; |
6448 | 0 | return fastEmitInst_r(AArch64::SMAXVv4i16v, &AArch64::FPR16RegClass, Op0); |
6449 | 0 | } |
6450 | | |
6451 | 0 | unsigned fastEmit_ISD_VECREDUCE_SMAX_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
6452 | 0 | if (RetVT.SimpleTy != MVT::i16) |
6453 | 0 | return 0; |
6454 | 0 | return fastEmitInst_r(AArch64::SMAXVv8i16v, &AArch64::FPR16RegClass, Op0); |
6455 | 0 | } |
6456 | | |
6457 | 0 | unsigned fastEmit_ISD_VECREDUCE_SMAX_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
6458 | 0 | if (RetVT.SimpleTy != MVT::i32) |
6459 | 0 | return 0; |
6460 | 0 | return fastEmitInst_r(AArch64::SMAXVv4i32v, &AArch64::FPR32RegClass, Op0); |
6461 | 0 | } |
6462 | | |
6463 | 0 | unsigned fastEmit_ISD_VECREDUCE_SMAX_r(MVT VT, MVT RetVT, unsigned Op0) { |
6464 | 0 | switch (VT.SimpleTy) { |
6465 | 0 | case MVT::v8i8: return fastEmit_ISD_VECREDUCE_SMAX_MVT_v8i8_r(RetVT, Op0); |
6466 | 0 | case MVT::v16i8: return fastEmit_ISD_VECREDUCE_SMAX_MVT_v16i8_r(RetVT, Op0); |
6467 | 0 | case MVT::v4i16: return fastEmit_ISD_VECREDUCE_SMAX_MVT_v4i16_r(RetVT, Op0); |
6468 | 0 | case MVT::v8i16: return fastEmit_ISD_VECREDUCE_SMAX_MVT_v8i16_r(RetVT, Op0); |
6469 | 0 | case MVT::v4i32: return fastEmit_ISD_VECREDUCE_SMAX_MVT_v4i32_r(RetVT, Op0); |
6470 | 0 | default: return 0; |
6471 | 0 | } |
6472 | 0 | } |
6473 | | |
6474 | | // FastEmit functions for ISD::VECREDUCE_SMIN. |
6475 | | |
6476 | 0 | unsigned fastEmit_ISD_VECREDUCE_SMIN_MVT_v8i8_r(MVT RetVT, unsigned Op0) { |
6477 | 0 | if (RetVT.SimpleTy != MVT::i8) |
6478 | 0 | return 0; |
6479 | 0 | return fastEmitInst_r(AArch64::SMINVv8i8v, &AArch64::FPR8RegClass, Op0); |
6480 | 0 | } |
6481 | | |
6482 | 0 | unsigned fastEmit_ISD_VECREDUCE_SMIN_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
6483 | 0 | if (RetVT.SimpleTy != MVT::i8) |
6484 | 0 | return 0; |
6485 | 0 | return fastEmitInst_r(AArch64::SMINVv16i8v, &AArch64::FPR8RegClass, Op0); |
6486 | 0 | } |
6487 | | |
6488 | 0 | unsigned fastEmit_ISD_VECREDUCE_SMIN_MVT_v4i16_r(MVT RetVT, unsigned Op0) { |
6489 | 0 | if (RetVT.SimpleTy != MVT::i16) |
6490 | 0 | return 0; |
6491 | 0 | return fastEmitInst_r(AArch64::SMINVv4i16v, &AArch64::FPR16RegClass, Op0); |
6492 | 0 | } |
6493 | | |
6494 | 0 | unsigned fastEmit_ISD_VECREDUCE_SMIN_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
6495 | 0 | if (RetVT.SimpleTy != MVT::i16) |
6496 | 0 | return 0; |
6497 | 0 | return fastEmitInst_r(AArch64::SMINVv8i16v, &AArch64::FPR16RegClass, Op0); |
6498 | 0 | } |
6499 | | |
6500 | 0 | unsigned fastEmit_ISD_VECREDUCE_SMIN_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
6501 | 0 | if (RetVT.SimpleTy != MVT::i32) |
6502 | 0 | return 0; |
6503 | 0 | return fastEmitInst_r(AArch64::SMINVv4i32v, &AArch64::FPR32RegClass, Op0); |
6504 | 0 | } |
6505 | | |
6506 | 0 | unsigned fastEmit_ISD_VECREDUCE_SMIN_r(MVT VT, MVT RetVT, unsigned Op0) { |
6507 | 0 | switch (VT.SimpleTy) { |
6508 | 0 | case MVT::v8i8: return fastEmit_ISD_VECREDUCE_SMIN_MVT_v8i8_r(RetVT, Op0); |
6509 | 0 | case MVT::v16i8: return fastEmit_ISD_VECREDUCE_SMIN_MVT_v16i8_r(RetVT, Op0); |
6510 | 0 | case MVT::v4i16: return fastEmit_ISD_VECREDUCE_SMIN_MVT_v4i16_r(RetVT, Op0); |
6511 | 0 | case MVT::v8i16: return fastEmit_ISD_VECREDUCE_SMIN_MVT_v8i16_r(RetVT, Op0); |
6512 | 0 | case MVT::v4i32: return fastEmit_ISD_VECREDUCE_SMIN_MVT_v4i32_r(RetVT, Op0); |
6513 | 0 | default: return 0; |
6514 | 0 | } |
6515 | 0 | } |
6516 | | |
6517 | | // FastEmit functions for ISD::VECREDUCE_UMAX. |
6518 | | |
6519 | 0 | unsigned fastEmit_ISD_VECREDUCE_UMAX_MVT_v8i8_r(MVT RetVT, unsigned Op0) { |
6520 | 0 | if (RetVT.SimpleTy != MVT::i8) |
6521 | 0 | return 0; |
6522 | 0 | return fastEmitInst_r(AArch64::UMAXVv8i8v, &AArch64::FPR8RegClass, Op0); |
6523 | 0 | } |
6524 | | |
6525 | 0 | unsigned fastEmit_ISD_VECREDUCE_UMAX_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
6526 | 0 | if (RetVT.SimpleTy != MVT::i8) |
6527 | 0 | return 0; |
6528 | 0 | return fastEmitInst_r(AArch64::UMAXVv16i8v, &AArch64::FPR8RegClass, Op0); |
6529 | 0 | } |
6530 | | |
6531 | 0 | unsigned fastEmit_ISD_VECREDUCE_UMAX_MVT_v4i16_r(MVT RetVT, unsigned Op0) { |
6532 | 0 | if (RetVT.SimpleTy != MVT::i16) |
6533 | 0 | return 0; |
6534 | 0 | return fastEmitInst_r(AArch64::UMAXVv4i16v, &AArch64::FPR16RegClass, Op0); |
6535 | 0 | } |
6536 | | |
6537 | 0 | unsigned fastEmit_ISD_VECREDUCE_UMAX_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
6538 | 0 | if (RetVT.SimpleTy != MVT::i16) |
6539 | 0 | return 0; |
6540 | 0 | return fastEmitInst_r(AArch64::UMAXVv8i16v, &AArch64::FPR16RegClass, Op0); |
6541 | 0 | } |
6542 | | |
6543 | 0 | unsigned fastEmit_ISD_VECREDUCE_UMAX_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
6544 | 0 | if (RetVT.SimpleTy != MVT::i32) |
6545 | 0 | return 0; |
6546 | 0 | return fastEmitInst_r(AArch64::UMAXVv4i32v, &AArch64::FPR32RegClass, Op0); |
6547 | 0 | } |
6548 | | |
6549 | 0 | unsigned fastEmit_ISD_VECREDUCE_UMAX_r(MVT VT, MVT RetVT, unsigned Op0) { |
6550 | 0 | switch (VT.SimpleTy) { |
6551 | 0 | case MVT::v8i8: return fastEmit_ISD_VECREDUCE_UMAX_MVT_v8i8_r(RetVT, Op0); |
6552 | 0 | case MVT::v16i8: return fastEmit_ISD_VECREDUCE_UMAX_MVT_v16i8_r(RetVT, Op0); |
6553 | 0 | case MVT::v4i16: return fastEmit_ISD_VECREDUCE_UMAX_MVT_v4i16_r(RetVT, Op0); |
6554 | 0 | case MVT::v8i16: return fastEmit_ISD_VECREDUCE_UMAX_MVT_v8i16_r(RetVT, Op0); |
6555 | 0 | case MVT::v4i32: return fastEmit_ISD_VECREDUCE_UMAX_MVT_v4i32_r(RetVT, Op0); |
6556 | 0 | default: return 0; |
6557 | 0 | } |
6558 | 0 | } |
6559 | | |
6560 | | // FastEmit functions for ISD::VECREDUCE_UMIN. |
6561 | | |
6562 | 0 | unsigned fastEmit_ISD_VECREDUCE_UMIN_MVT_v8i8_r(MVT RetVT, unsigned Op0) { |
6563 | 0 | if (RetVT.SimpleTy != MVT::i8) |
6564 | 0 | return 0; |
6565 | 0 | return fastEmitInst_r(AArch64::UMINVv8i8v, &AArch64::FPR8RegClass, Op0); |
6566 | 0 | } |
6567 | | |
6568 | 0 | unsigned fastEmit_ISD_VECREDUCE_UMIN_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
6569 | 0 | if (RetVT.SimpleTy != MVT::i8) |
6570 | 0 | return 0; |
6571 | 0 | return fastEmitInst_r(AArch64::UMINVv16i8v, &AArch64::FPR8RegClass, Op0); |
6572 | 0 | } |
6573 | | |
6574 | 0 | unsigned fastEmit_ISD_VECREDUCE_UMIN_MVT_v4i16_r(MVT RetVT, unsigned Op0) { |
6575 | 0 | if (RetVT.SimpleTy != MVT::i16) |
6576 | 0 | return 0; |
6577 | 0 | return fastEmitInst_r(AArch64::UMINVv4i16v, &AArch64::FPR16RegClass, Op0); |
6578 | 0 | } |
6579 | | |
6580 | 0 | unsigned fastEmit_ISD_VECREDUCE_UMIN_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
6581 | 0 | if (RetVT.SimpleTy != MVT::i16) |
6582 | 0 | return 0; |
6583 | 0 | return fastEmitInst_r(AArch64::UMINVv8i16v, &AArch64::FPR16RegClass, Op0); |
6584 | 0 | } |
6585 | | |
6586 | 0 | unsigned fastEmit_ISD_VECREDUCE_UMIN_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
6587 | 0 | if (RetVT.SimpleTy != MVT::i32) |
6588 | 0 | return 0; |
6589 | 0 | return fastEmitInst_r(AArch64::UMINVv4i32v, &AArch64::FPR32RegClass, Op0); |
6590 | 0 | } |
6591 | | |
6592 | 0 | unsigned fastEmit_ISD_VECREDUCE_UMIN_r(MVT VT, MVT RetVT, unsigned Op0) { |
6593 | 0 | switch (VT.SimpleTy) { |
6594 | 0 | case MVT::v8i8: return fastEmit_ISD_VECREDUCE_UMIN_MVT_v8i8_r(RetVT, Op0); |
6595 | 0 | case MVT::v16i8: return fastEmit_ISD_VECREDUCE_UMIN_MVT_v16i8_r(RetVT, Op0); |
6596 | 0 | case MVT::v4i16: return fastEmit_ISD_VECREDUCE_UMIN_MVT_v4i16_r(RetVT, Op0); |
6597 | 0 | case MVT::v8i16: return fastEmit_ISD_VECREDUCE_UMIN_MVT_v8i16_r(RetVT, Op0); |
6598 | 0 | case MVT::v4i32: return fastEmit_ISD_VECREDUCE_UMIN_MVT_v4i32_r(RetVT, Op0); |
6599 | 0 | default: return 0; |
6600 | 0 | } |
6601 | 0 | } |
6602 | | |
6603 | | // FastEmit functions for ISD::VECTOR_REVERSE. |
6604 | | |
6605 | 0 | unsigned fastEmit_ISD_VECTOR_REVERSE_MVT_nxv2i1_r(MVT RetVT, unsigned Op0) { |
6606 | 0 | if (RetVT.SimpleTy != MVT::nxv2i1) |
6607 | 0 | return 0; |
6608 | 0 | if ((Subtarget->hasSVEorSME())) { |
6609 | 0 | return fastEmitInst_r(AArch64::REV_PP_D, &AArch64::PPRRegClass, Op0); |
6610 | 0 | } |
6611 | 0 | return 0; |
6612 | 0 | } |
6613 | | |
6614 | 0 | unsigned fastEmit_ISD_VECTOR_REVERSE_MVT_nxv4i1_r(MVT RetVT, unsigned Op0) { |
6615 | 0 | if (RetVT.SimpleTy != MVT::nxv4i1) |
6616 | 0 | return 0; |
6617 | 0 | if ((Subtarget->hasSVEorSME())) { |
6618 | 0 | return fastEmitInst_r(AArch64::REV_PP_S, &AArch64::PPRRegClass, Op0); |
6619 | 0 | } |
6620 | 0 | return 0; |
6621 | 0 | } |
6622 | | |
6623 | 0 | unsigned fastEmit_ISD_VECTOR_REVERSE_MVT_nxv8i1_r(MVT RetVT, unsigned Op0) { |
6624 | 0 | if (RetVT.SimpleTy != MVT::nxv8i1) |
6625 | 0 | return 0; |
6626 | 0 | if ((Subtarget->hasSVEorSME())) { |
6627 | 0 | return fastEmitInst_r(AArch64::REV_PP_H, &AArch64::PPRRegClass, Op0); |
6628 | 0 | } |
6629 | 0 | return 0; |
6630 | 0 | } |
6631 | | |
6632 | 0 | unsigned fastEmit_ISD_VECTOR_REVERSE_MVT_nxv16i1_r(MVT RetVT, unsigned Op0) { |
6633 | 0 | if (RetVT.SimpleTy != MVT::nxv16i1) |
6634 | 0 | return 0; |
6635 | 0 | if ((Subtarget->hasSVEorSME())) { |
6636 | 0 | return fastEmitInst_r(AArch64::REV_PP_B, &AArch64::PPRRegClass, Op0); |
6637 | 0 | } |
6638 | 0 | return 0; |
6639 | 0 | } |
6640 | | |
6641 | 0 | unsigned fastEmit_ISD_VECTOR_REVERSE_MVT_nxv16i8_r(MVT RetVT, unsigned Op0) { |
6642 | 0 | if (RetVT.SimpleTy != MVT::nxv16i8) |
6643 | 0 | return 0; |
6644 | 0 | if ((Subtarget->hasSVEorSME())) { |
6645 | 0 | return fastEmitInst_r(AArch64::REV_ZZ_B, &AArch64::ZPRRegClass, Op0); |
6646 | 0 | } |
6647 | 0 | return 0; |
6648 | 0 | } |
6649 | | |
6650 | 0 | unsigned fastEmit_ISD_VECTOR_REVERSE_MVT_nxv8i16_r(MVT RetVT, unsigned Op0) { |
6651 | 0 | if (RetVT.SimpleTy != MVT::nxv8i16) |
6652 | 0 | return 0; |
6653 | 0 | if ((Subtarget->hasSVEorSME())) { |
6654 | 0 | return fastEmitInst_r(AArch64::REV_ZZ_H, &AArch64::ZPRRegClass, Op0); |
6655 | 0 | } |
6656 | 0 | return 0; |
6657 | 0 | } |
6658 | | |
6659 | 0 | unsigned fastEmit_ISD_VECTOR_REVERSE_MVT_nxv4i32_r(MVT RetVT, unsigned Op0) { |
6660 | 0 | if (RetVT.SimpleTy != MVT::nxv4i32) |
6661 | 0 | return 0; |
6662 | 0 | if ((Subtarget->hasSVEorSME())) { |
6663 | 0 | return fastEmitInst_r(AArch64::REV_ZZ_S, &AArch64::ZPRRegClass, Op0); |
6664 | 0 | } |
6665 | 0 | return 0; |
6666 | 0 | } |
6667 | | |
6668 | 0 | unsigned fastEmit_ISD_VECTOR_REVERSE_MVT_nxv2i64_r(MVT RetVT, unsigned Op0) { |
6669 | 0 | if (RetVT.SimpleTy != MVT::nxv2i64) |
6670 | 0 | return 0; |
6671 | 0 | if ((Subtarget->hasSVEorSME())) { |
6672 | 0 | return fastEmitInst_r(AArch64::REV_ZZ_D, &AArch64::ZPRRegClass, Op0); |
6673 | 0 | } |
6674 | 0 | return 0; |
6675 | 0 | } |
6676 | | |
6677 | 0 | unsigned fastEmit_ISD_VECTOR_REVERSE_MVT_nxv2f16_r(MVT RetVT, unsigned Op0) { |
6678 | 0 | if (RetVT.SimpleTy != MVT::nxv2f16) |
6679 | 0 | return 0; |
6680 | 0 | if ((Subtarget->hasSVEorSME())) { |
6681 | 0 | return fastEmitInst_r(AArch64::REV_ZZ_D, &AArch64::ZPRRegClass, Op0); |
6682 | 0 | } |
6683 | 0 | return 0; |
6684 | 0 | } |
6685 | | |
6686 | 0 | unsigned fastEmit_ISD_VECTOR_REVERSE_MVT_nxv4f16_r(MVT RetVT, unsigned Op0) { |
6687 | 0 | if (RetVT.SimpleTy != MVT::nxv4f16) |
6688 | 0 | return 0; |
6689 | 0 | if ((Subtarget->hasSVEorSME())) { |
6690 | 0 | return fastEmitInst_r(AArch64::REV_ZZ_S, &AArch64::ZPRRegClass, Op0); |
6691 | 0 | } |
6692 | 0 | return 0; |
6693 | 0 | } |
6694 | | |
6695 | 0 | unsigned fastEmit_ISD_VECTOR_REVERSE_MVT_nxv8f16_r(MVT RetVT, unsigned Op0) { |
6696 | 0 | if (RetVT.SimpleTy != MVT::nxv8f16) |
6697 | 0 | return 0; |
6698 | 0 | if ((Subtarget->hasSVEorSME())) { |
6699 | 0 | return fastEmitInst_r(AArch64::REV_ZZ_H, &AArch64::ZPRRegClass, Op0); |
6700 | 0 | } |
6701 | 0 | return 0; |
6702 | 0 | } |
6703 | | |
6704 | 0 | unsigned fastEmit_ISD_VECTOR_REVERSE_MVT_nxv2bf16_r(MVT RetVT, unsigned Op0) { |
6705 | 0 | if (RetVT.SimpleTy != MVT::nxv2bf16) |
6706 | 0 | return 0; |
6707 | 0 | if ((Subtarget->hasSVEorSME())) { |
6708 | 0 | return fastEmitInst_r(AArch64::REV_ZZ_D, &AArch64::ZPRRegClass, Op0); |
6709 | 0 | } |
6710 | 0 | return 0; |
6711 | 0 | } |
6712 | | |
6713 | 0 | unsigned fastEmit_ISD_VECTOR_REVERSE_MVT_nxv4bf16_r(MVT RetVT, unsigned Op0) { |
6714 | 0 | if (RetVT.SimpleTy != MVT::nxv4bf16) |
6715 | 0 | return 0; |
6716 | 0 | if ((Subtarget->hasSVEorSME())) { |
6717 | 0 | return fastEmitInst_r(AArch64::REV_ZZ_S, &AArch64::ZPRRegClass, Op0); |
6718 | 0 | } |
6719 | 0 | return 0; |
6720 | 0 | } |
6721 | | |
6722 | 0 | unsigned fastEmit_ISD_VECTOR_REVERSE_MVT_nxv8bf16_r(MVT RetVT, unsigned Op0) { |
6723 | 0 | if (RetVT.SimpleTy != MVT::nxv8bf16) |
6724 | 0 | return 0; |
6725 | 0 | if ((Subtarget->hasSVEorSME())) { |
6726 | 0 | return fastEmitInst_r(AArch64::REV_ZZ_H, &AArch64::ZPRRegClass, Op0); |
6727 | 0 | } |
6728 | 0 | return 0; |
6729 | 0 | } |
6730 | | |
6731 | 0 | unsigned fastEmit_ISD_VECTOR_REVERSE_MVT_nxv2f32_r(MVT RetVT, unsigned Op0) { |
6732 | 0 | if (RetVT.SimpleTy != MVT::nxv2f32) |
6733 | 0 | return 0; |
6734 | 0 | if ((Subtarget->hasSVEorSME())) { |
6735 | 0 | return fastEmitInst_r(AArch64::REV_ZZ_D, &AArch64::ZPRRegClass, Op0); |
6736 | 0 | } |
6737 | 0 | return 0; |
6738 | 0 | } |
6739 | | |
6740 | 0 | unsigned fastEmit_ISD_VECTOR_REVERSE_MVT_nxv4f32_r(MVT RetVT, unsigned Op0) { |
6741 | 0 | if (RetVT.SimpleTy != MVT::nxv4f32) |
6742 | 0 | return 0; |
6743 | 0 | if ((Subtarget->hasSVEorSME())) { |
6744 | 0 | return fastEmitInst_r(AArch64::REV_ZZ_S, &AArch64::ZPRRegClass, Op0); |
6745 | 0 | } |
6746 | 0 | return 0; |
6747 | 0 | } |
6748 | | |
6749 | 0 | unsigned fastEmit_ISD_VECTOR_REVERSE_MVT_nxv2f64_r(MVT RetVT, unsigned Op0) { |
6750 | 0 | if (RetVT.SimpleTy != MVT::nxv2f64) |
6751 | 0 | return 0; |
6752 | 0 | if ((Subtarget->hasSVEorSME())) { |
6753 | 0 | return fastEmitInst_r(AArch64::REV_ZZ_D, &AArch64::ZPRRegClass, Op0); |
6754 | 0 | } |
6755 | 0 | return 0; |
6756 | 0 | } |
6757 | | |
6758 | 0 | unsigned fastEmit_ISD_VECTOR_REVERSE_r(MVT VT, MVT RetVT, unsigned Op0) { |
6759 | 0 | switch (VT.SimpleTy) { |
6760 | 0 | case MVT::nxv2i1: return fastEmit_ISD_VECTOR_REVERSE_MVT_nxv2i1_r(RetVT, Op0); |
6761 | 0 | case MVT::nxv4i1: return fastEmit_ISD_VECTOR_REVERSE_MVT_nxv4i1_r(RetVT, Op0); |
6762 | 0 | case MVT::nxv8i1: return fastEmit_ISD_VECTOR_REVERSE_MVT_nxv8i1_r(RetVT, Op0); |
6763 | 0 | case MVT::nxv16i1: return fastEmit_ISD_VECTOR_REVERSE_MVT_nxv16i1_r(RetVT, Op0); |
6764 | 0 | case MVT::nxv16i8: return fastEmit_ISD_VECTOR_REVERSE_MVT_nxv16i8_r(RetVT, Op0); |
6765 | 0 | case MVT::nxv8i16: return fastEmit_ISD_VECTOR_REVERSE_MVT_nxv8i16_r(RetVT, Op0); |
6766 | 0 | case MVT::nxv4i32: return fastEmit_ISD_VECTOR_REVERSE_MVT_nxv4i32_r(RetVT, Op0); |
6767 | 0 | case MVT::nxv2i64: return fastEmit_ISD_VECTOR_REVERSE_MVT_nxv2i64_r(RetVT, Op0); |
6768 | 0 | case MVT::nxv2f16: return fastEmit_ISD_VECTOR_REVERSE_MVT_nxv2f16_r(RetVT, Op0); |
6769 | 0 | case MVT::nxv4f16: return fastEmit_ISD_VECTOR_REVERSE_MVT_nxv4f16_r(RetVT, Op0); |
6770 | 0 | case MVT::nxv8f16: return fastEmit_ISD_VECTOR_REVERSE_MVT_nxv8f16_r(RetVT, Op0); |
6771 | 0 | case MVT::nxv2bf16: return fastEmit_ISD_VECTOR_REVERSE_MVT_nxv2bf16_r(RetVT, Op0); |
6772 | 0 | case MVT::nxv4bf16: return fastEmit_ISD_VECTOR_REVERSE_MVT_nxv4bf16_r(RetVT, Op0); |
6773 | 0 | case MVT::nxv8bf16: return fastEmit_ISD_VECTOR_REVERSE_MVT_nxv8bf16_r(RetVT, Op0); |
6774 | 0 | case MVT::nxv2f32: return fastEmit_ISD_VECTOR_REVERSE_MVT_nxv2f32_r(RetVT, Op0); |
6775 | 0 | case MVT::nxv4f32: return fastEmit_ISD_VECTOR_REVERSE_MVT_nxv4f32_r(RetVT, Op0); |
6776 | 0 | case MVT::nxv2f64: return fastEmit_ISD_VECTOR_REVERSE_MVT_nxv2f64_r(RetVT, Op0); |
6777 | 0 | default: return 0; |
6778 | 0 | } |
6779 | 0 | } |
6780 | | |
6781 | | // Top-level FastEmit function. |
6782 | | |
6783 | 0 | unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0) override { |
6784 | 0 | switch (Opcode) { |
6785 | 0 | case AArch64ISD::CALL: return fastEmit_AArch64ISD_CALL_r(VT, RetVT, Op0); |
6786 | 0 | case AArch64ISD::CMEQz: return fastEmit_AArch64ISD_CMEQz_r(VT, RetVT, Op0); |
6787 | 0 | case AArch64ISD::CMGEz: return fastEmit_AArch64ISD_CMGEz_r(VT, RetVT, Op0); |
6788 | 0 | case AArch64ISD::CMGTz: return fastEmit_AArch64ISD_CMGTz_r(VT, RetVT, Op0); |
6789 | 0 | case AArch64ISD::CMLEz: return fastEmit_AArch64ISD_CMLEz_r(VT, RetVT, Op0); |
6790 | 0 | case AArch64ISD::CMLTz: return fastEmit_AArch64ISD_CMLTz_r(VT, RetVT, Op0); |
6791 | 0 | case AArch64ISD::DUP: return fastEmit_AArch64ISD_DUP_r(VT, RetVT, Op0); |
6792 | 0 | case AArch64ISD::FCMEQz: return fastEmit_AArch64ISD_FCMEQz_r(VT, RetVT, Op0); |
6793 | 0 | case AArch64ISD::FCMGEz: return fastEmit_AArch64ISD_FCMGEz_r(VT, RetVT, Op0); |
6794 | 0 | case AArch64ISD::FCMGTz: return fastEmit_AArch64ISD_FCMGTz_r(VT, RetVT, Op0); |
6795 | 0 | case AArch64ISD::FCMLEz: return fastEmit_AArch64ISD_FCMLEz_r(VT, RetVT, Op0); |
6796 | 0 | case AArch64ISD::FCMLTz: return fastEmit_AArch64ISD_FCMLTz_r(VT, RetVT, Op0); |
6797 | 0 | case AArch64ISD::FRECPE: return fastEmit_AArch64ISD_FRECPE_r(VT, RetVT, Op0); |
6798 | 0 | case AArch64ISD::FRSQRTE: return fastEmit_AArch64ISD_FRSQRTE_r(VT, RetVT, Op0); |
6799 | 0 | case AArch64ISD::PROBED_ALLOCA: return fastEmit_AArch64ISD_PROBED_ALLOCA_r(VT, RetVT, Op0); |
6800 | 0 | case AArch64ISD::REV16: return fastEmit_AArch64ISD_REV16_r(VT, RetVT, Op0); |
6801 | 0 | case AArch64ISD::REV32: return fastEmit_AArch64ISD_REV32_r(VT, RetVT, Op0); |
6802 | 0 | case AArch64ISD::REV64: return fastEmit_AArch64ISD_REV64_r(VT, RetVT, Op0); |
6803 | 0 | case AArch64ISD::SADDLP: return fastEmit_AArch64ISD_SADDLP_r(VT, RetVT, Op0); |
6804 | 0 | case AArch64ISD::SITOF: return fastEmit_AArch64ISD_SITOF_r(VT, RetVT, Op0); |
6805 | 0 | case AArch64ISD::SUNPKHI: return fastEmit_AArch64ISD_SUNPKHI_r(VT, RetVT, Op0); |
6806 | 0 | case AArch64ISD::SUNPKLO: return fastEmit_AArch64ISD_SUNPKLO_r(VT, RetVT, Op0); |
6807 | 0 | case AArch64ISD::UADDLP: return fastEmit_AArch64ISD_UADDLP_r(VT, RetVT, Op0); |
6808 | 0 | case AArch64ISD::UITOF: return fastEmit_AArch64ISD_UITOF_r(VT, RetVT, Op0); |
6809 | 0 | case AArch64ISD::UUNPKHI: return fastEmit_AArch64ISD_UUNPKHI_r(VT, RetVT, Op0); |
6810 | 0 | case AArch64ISD::UUNPKLO: return fastEmit_AArch64ISD_UUNPKLO_r(VT, RetVT, Op0); |
6811 | 0 | case ISD::ABS: return fastEmit_ISD_ABS_r(VT, RetVT, Op0); |
6812 | 0 | case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0); |
6813 | 0 | case ISD::BITREVERSE: return fastEmit_ISD_BITREVERSE_r(VT, RetVT, Op0); |
6814 | 0 | case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0); |
6815 | 0 | case ISD::BSWAP: return fastEmit_ISD_BSWAP_r(VT, RetVT, Op0); |
6816 | 0 | case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0); |
6817 | 0 | case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0); |
6818 | 0 | case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0); |
6819 | 0 | case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0); |
6820 | 0 | case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0); |
6821 | 0 | case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0); |
6822 | 0 | case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0); |
6823 | 0 | case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0); |
6824 | 0 | case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0); |
6825 | 0 | case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0); |
6826 | 0 | case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0); |
6827 | 0 | case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0); |
6828 | 0 | case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0); |
6829 | 0 | case ISD::FROUND: return fastEmit_ISD_FROUND_r(VT, RetVT, Op0); |
6830 | 0 | case ISD::FROUNDEVEN: return fastEmit_ISD_FROUNDEVEN_r(VT, RetVT, Op0); |
6831 | 0 | case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0); |
6832 | 0 | case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0); |
6833 | 0 | case ISD::LLROUND: return fastEmit_ISD_LLROUND_r(VT, RetVT, Op0); |
6834 | 0 | case ISD::LROUND: return fastEmit_ISD_LROUND_r(VT, RetVT, Op0); |
6835 | 0 | case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0); |
6836 | 0 | case ISD::SPLAT_VECTOR: return fastEmit_ISD_SPLAT_VECTOR_r(VT, RetVT, Op0); |
6837 | 0 | case ISD::STRICT_FCEIL: return fastEmit_ISD_STRICT_FCEIL_r(VT, RetVT, Op0); |
6838 | 0 | case ISD::STRICT_FFLOOR: return fastEmit_ISD_STRICT_FFLOOR_r(VT, RetVT, Op0); |
6839 | 0 | case ISD::STRICT_FNEARBYINT: return fastEmit_ISD_STRICT_FNEARBYINT_r(VT, RetVT, Op0); |
6840 | 0 | case ISD::STRICT_FP_EXTEND: return fastEmit_ISD_STRICT_FP_EXTEND_r(VT, RetVT, Op0); |
6841 | 0 | case ISD::STRICT_FP_ROUND: return fastEmit_ISD_STRICT_FP_ROUND_r(VT, RetVT, Op0); |
6842 | 0 | case ISD::STRICT_FP_TO_SINT: return fastEmit_ISD_STRICT_FP_TO_SINT_r(VT, RetVT, Op0); |
6843 | 0 | case ISD::STRICT_FP_TO_UINT: return fastEmit_ISD_STRICT_FP_TO_UINT_r(VT, RetVT, Op0); |
6844 | 0 | case ISD::STRICT_FRINT: return fastEmit_ISD_STRICT_FRINT_r(VT, RetVT, Op0); |
6845 | 0 | case ISD::STRICT_FROUND: return fastEmit_ISD_STRICT_FROUND_r(VT, RetVT, Op0); |
6846 | 0 | case ISD::STRICT_FROUNDEVEN: return fastEmit_ISD_STRICT_FROUNDEVEN_r(VT, RetVT, Op0); |
6847 | 0 | case ISD::STRICT_FSQRT: return fastEmit_ISD_STRICT_FSQRT_r(VT, RetVT, Op0); |
6848 | 0 | case ISD::STRICT_FTRUNC: return fastEmit_ISD_STRICT_FTRUNC_r(VT, RetVT, Op0); |
6849 | 0 | case ISD::STRICT_LLROUND: return fastEmit_ISD_STRICT_LLROUND_r(VT, RetVT, Op0); |
6850 | 0 | case ISD::STRICT_LROUND: return fastEmit_ISD_STRICT_LROUND_r(VT, RetVT, Op0); |
6851 | 0 | case ISD::STRICT_SINT_TO_FP: return fastEmit_ISD_STRICT_SINT_TO_FP_r(VT, RetVT, Op0); |
6852 | 0 | case ISD::STRICT_UINT_TO_FP: return fastEmit_ISD_STRICT_UINT_TO_FP_r(VT, RetVT, Op0); |
6853 | 0 | case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0); |
6854 | 0 | case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0); |
6855 | 0 | case ISD::VECREDUCE_ADD: return fastEmit_ISD_VECREDUCE_ADD_r(VT, RetVT, Op0); |
6856 | 0 | case ISD::VECREDUCE_FADD: return fastEmit_ISD_VECREDUCE_FADD_r(VT, RetVT, Op0); |
6857 | 0 | case ISD::VECREDUCE_FMAX: return fastEmit_ISD_VECREDUCE_FMAX_r(VT, RetVT, Op0); |
6858 | 0 | case ISD::VECREDUCE_FMAXIMUM: return fastEmit_ISD_VECREDUCE_FMAXIMUM_r(VT, RetVT, Op0); |
6859 | 0 | case ISD::VECREDUCE_FMIN: return fastEmit_ISD_VECREDUCE_FMIN_r(VT, RetVT, Op0); |
6860 | 0 | case ISD::VECREDUCE_FMINIMUM: return fastEmit_ISD_VECREDUCE_FMINIMUM_r(VT, RetVT, Op0); |
6861 | 0 | case ISD::VECREDUCE_SMAX: return fastEmit_ISD_VECREDUCE_SMAX_r(VT, RetVT, Op0); |
6862 | 0 | case ISD::VECREDUCE_SMIN: return fastEmit_ISD_VECREDUCE_SMIN_r(VT, RetVT, Op0); |
6863 | 0 | case ISD::VECREDUCE_UMAX: return fastEmit_ISD_VECREDUCE_UMAX_r(VT, RetVT, Op0); |
6864 | 0 | case ISD::VECREDUCE_UMIN: return fastEmit_ISD_VECREDUCE_UMIN_r(VT, RetVT, Op0); |
6865 | 0 | case ISD::VECTOR_REVERSE: return fastEmit_ISD_VECTOR_REVERSE_r(VT, RetVT, Op0); |
6866 | 0 | default: return 0; |
6867 | 0 | } |
6868 | 0 | } |
6869 | | |
6870 | | // FastEmit functions for AArch64ISD::ADDP. |
6871 | | |
6872 | 0 | unsigned fastEmit_AArch64ISD_ADDP_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
6873 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
6874 | 0 | return 0; |
6875 | 0 | if ((Subtarget->hasNEON())) { |
6876 | 0 | return fastEmitInst_rr(AArch64::ADDPv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
6877 | 0 | } |
6878 | 0 | return 0; |
6879 | 0 | } |
6880 | | |
6881 | 0 | unsigned fastEmit_AArch64ISD_ADDP_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
6882 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
6883 | 0 | return 0; |
6884 | 0 | if ((Subtarget->hasNEON())) { |
6885 | 0 | return fastEmitInst_rr(AArch64::ADDPv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
6886 | 0 | } |
6887 | 0 | return 0; |
6888 | 0 | } |
6889 | | |
6890 | 0 | unsigned fastEmit_AArch64ISD_ADDP_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
6891 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
6892 | 0 | return 0; |
6893 | 0 | if ((Subtarget->hasNEON())) { |
6894 | 0 | return fastEmitInst_rr(AArch64::ADDPv4i16, &AArch64::FPR64RegClass, Op0, Op1); |
6895 | 0 | } |
6896 | 0 | return 0; |
6897 | 0 | } |
6898 | | |
6899 | 0 | unsigned fastEmit_AArch64ISD_ADDP_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
6900 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
6901 | 0 | return 0; |
6902 | 0 | if ((Subtarget->hasNEON())) { |
6903 | 0 | return fastEmitInst_rr(AArch64::ADDPv8i16, &AArch64::FPR128RegClass, Op0, Op1); |
6904 | 0 | } |
6905 | 0 | return 0; |
6906 | 0 | } |
6907 | | |
6908 | 0 | unsigned fastEmit_AArch64ISD_ADDP_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
6909 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
6910 | 0 | return 0; |
6911 | 0 | if ((Subtarget->hasNEON())) { |
6912 | 0 | return fastEmitInst_rr(AArch64::ADDPv2i32, &AArch64::FPR64RegClass, Op0, Op1); |
6913 | 0 | } |
6914 | 0 | return 0; |
6915 | 0 | } |
6916 | | |
6917 | 0 | unsigned fastEmit_AArch64ISD_ADDP_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
6918 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
6919 | 0 | return 0; |
6920 | 0 | if ((Subtarget->hasNEON())) { |
6921 | 0 | return fastEmitInst_rr(AArch64::ADDPv4i32, &AArch64::FPR128RegClass, Op0, Op1); |
6922 | 0 | } |
6923 | 0 | return 0; |
6924 | 0 | } |
6925 | | |
6926 | 0 | unsigned fastEmit_AArch64ISD_ADDP_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
6927 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
6928 | 0 | return 0; |
6929 | 0 | if ((Subtarget->hasNEON())) { |
6930 | 0 | return fastEmitInst_rr(AArch64::ADDPv2i64, &AArch64::FPR128RegClass, Op0, Op1); |
6931 | 0 | } |
6932 | 0 | return 0; |
6933 | 0 | } |
6934 | | |
6935 | 0 | unsigned fastEmit_AArch64ISD_ADDP_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
6936 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
6937 | 0 | return 0; |
6938 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
6939 | 0 | return fastEmitInst_rr(AArch64::FADDPv4f16, &AArch64::FPR64RegClass, Op0, Op1); |
6940 | 0 | } |
6941 | 0 | return 0; |
6942 | 0 | } |
6943 | | |
6944 | 0 | unsigned fastEmit_AArch64ISD_ADDP_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
6945 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
6946 | 0 | return 0; |
6947 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
6948 | 0 | return fastEmitInst_rr(AArch64::FADDPv8f16, &AArch64::FPR128RegClass, Op0, Op1); |
6949 | 0 | } |
6950 | 0 | return 0; |
6951 | 0 | } |
6952 | | |
6953 | 0 | unsigned fastEmit_AArch64ISD_ADDP_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
6954 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
6955 | 0 | return 0; |
6956 | 0 | if ((Subtarget->hasNEON())) { |
6957 | 0 | return fastEmitInst_rr(AArch64::FADDPv2f32, &AArch64::FPR64RegClass, Op0, Op1); |
6958 | 0 | } |
6959 | 0 | return 0; |
6960 | 0 | } |
6961 | | |
6962 | 0 | unsigned fastEmit_AArch64ISD_ADDP_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
6963 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
6964 | 0 | return 0; |
6965 | 0 | if ((Subtarget->hasNEON())) { |
6966 | 0 | return fastEmitInst_rr(AArch64::FADDPv4f32, &AArch64::FPR128RegClass, Op0, Op1); |
6967 | 0 | } |
6968 | 0 | return 0; |
6969 | 0 | } |
6970 | | |
6971 | 0 | unsigned fastEmit_AArch64ISD_ADDP_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
6972 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
6973 | 0 | return 0; |
6974 | 0 | if ((Subtarget->hasNEON())) { |
6975 | 0 | return fastEmitInst_rr(AArch64::FADDPv2f64, &AArch64::FPR128RegClass, Op0, Op1); |
6976 | 0 | } |
6977 | 0 | return 0; |
6978 | 0 | } |
6979 | | |
6980 | 0 | unsigned fastEmit_AArch64ISD_ADDP_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
6981 | 0 | switch (VT.SimpleTy) { |
6982 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_ADDP_MVT_v8i8_rr(RetVT, Op0, Op1); |
6983 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_ADDP_MVT_v16i8_rr(RetVT, Op0, Op1); |
6984 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_ADDP_MVT_v4i16_rr(RetVT, Op0, Op1); |
6985 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_ADDP_MVT_v8i16_rr(RetVT, Op0, Op1); |
6986 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_ADDP_MVT_v2i32_rr(RetVT, Op0, Op1); |
6987 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_ADDP_MVT_v4i32_rr(RetVT, Op0, Op1); |
6988 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_ADDP_MVT_v2i64_rr(RetVT, Op0, Op1); |
6989 | 0 | case MVT::v4f16: return fastEmit_AArch64ISD_ADDP_MVT_v4f16_rr(RetVT, Op0, Op1); |
6990 | 0 | case MVT::v8f16: return fastEmit_AArch64ISD_ADDP_MVT_v8f16_rr(RetVT, Op0, Op1); |
6991 | 0 | case MVT::v2f32: return fastEmit_AArch64ISD_ADDP_MVT_v2f32_rr(RetVT, Op0, Op1); |
6992 | 0 | case MVT::v4f32: return fastEmit_AArch64ISD_ADDP_MVT_v4f32_rr(RetVT, Op0, Op1); |
6993 | 0 | case MVT::v2f64: return fastEmit_AArch64ISD_ADDP_MVT_v2f64_rr(RetVT, Op0, Op1); |
6994 | 0 | default: return 0; |
6995 | 0 | } |
6996 | 0 | } |
6997 | | |
6998 | | // FastEmit functions for AArch64ISD::BIC. |
6999 | | |
7000 | 0 | unsigned fastEmit_AArch64ISD_BIC_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7001 | 0 | if (RetVT.SimpleTy != MVT::nxv16i8) |
7002 | 0 | return 0; |
7003 | 0 | if ((Subtarget->hasSVEorSME())) { |
7004 | 0 | return fastEmitInst_rr(AArch64::BIC_ZZZ, &AArch64::ZPRRegClass, Op0, Op1); |
7005 | 0 | } |
7006 | 0 | return 0; |
7007 | 0 | } |
7008 | | |
7009 | 0 | unsigned fastEmit_AArch64ISD_BIC_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7010 | 0 | if (RetVT.SimpleTy != MVT::nxv8i16) |
7011 | 0 | return 0; |
7012 | 0 | if ((Subtarget->hasSVEorSME())) { |
7013 | 0 | return fastEmitInst_rr(AArch64::BIC_ZZZ, &AArch64::ZPRRegClass, Op0, Op1); |
7014 | 0 | } |
7015 | 0 | return 0; |
7016 | 0 | } |
7017 | | |
7018 | 0 | unsigned fastEmit_AArch64ISD_BIC_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7019 | 0 | if (RetVT.SimpleTy != MVT::nxv4i32) |
7020 | 0 | return 0; |
7021 | 0 | if ((Subtarget->hasSVEorSME())) { |
7022 | 0 | return fastEmitInst_rr(AArch64::BIC_ZZZ, &AArch64::ZPRRegClass, Op0, Op1); |
7023 | 0 | } |
7024 | 0 | return 0; |
7025 | 0 | } |
7026 | | |
7027 | 0 | unsigned fastEmit_AArch64ISD_BIC_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7028 | 0 | if (RetVT.SimpleTy != MVT::nxv2i64) |
7029 | 0 | return 0; |
7030 | 0 | if ((Subtarget->hasSVEorSME())) { |
7031 | 0 | return fastEmitInst_rr(AArch64::BIC_ZZZ, &AArch64::ZPRRegClass, Op0, Op1); |
7032 | 0 | } |
7033 | 0 | return 0; |
7034 | 0 | } |
7035 | | |
7036 | 0 | unsigned fastEmit_AArch64ISD_BIC_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
7037 | 0 | switch (VT.SimpleTy) { |
7038 | 0 | case MVT::nxv16i8: return fastEmit_AArch64ISD_BIC_MVT_nxv16i8_rr(RetVT, Op0, Op1); |
7039 | 0 | case MVT::nxv8i16: return fastEmit_AArch64ISD_BIC_MVT_nxv8i16_rr(RetVT, Op0, Op1); |
7040 | 0 | case MVT::nxv4i32: return fastEmit_AArch64ISD_BIC_MVT_nxv4i32_rr(RetVT, Op0, Op1); |
7041 | 0 | case MVT::nxv2i64: return fastEmit_AArch64ISD_BIC_MVT_nxv2i64_rr(RetVT, Op0, Op1); |
7042 | 0 | default: return 0; |
7043 | 0 | } |
7044 | 0 | } |
7045 | | |
7046 | | // FastEmit functions for AArch64ISD::CMEQ. |
7047 | | |
7048 | 0 | unsigned fastEmit_AArch64ISD_CMEQ_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7049 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
7050 | 0 | return 0; |
7051 | 0 | if ((Subtarget->hasNEON())) { |
7052 | 0 | return fastEmitInst_rr(AArch64::CMEQv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
7053 | 0 | } |
7054 | 0 | return 0; |
7055 | 0 | } |
7056 | | |
7057 | 0 | unsigned fastEmit_AArch64ISD_CMEQ_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7058 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
7059 | 0 | return 0; |
7060 | 0 | if ((Subtarget->hasNEON())) { |
7061 | 0 | return fastEmitInst_rr(AArch64::CMEQv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
7062 | 0 | } |
7063 | 0 | return 0; |
7064 | 0 | } |
7065 | | |
7066 | 0 | unsigned fastEmit_AArch64ISD_CMEQ_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7067 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
7068 | 0 | return 0; |
7069 | 0 | if ((Subtarget->hasNEON())) { |
7070 | 0 | return fastEmitInst_rr(AArch64::CMEQv4i16, &AArch64::FPR64RegClass, Op0, Op1); |
7071 | 0 | } |
7072 | 0 | return 0; |
7073 | 0 | } |
7074 | | |
7075 | 0 | unsigned fastEmit_AArch64ISD_CMEQ_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7076 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
7077 | 0 | return 0; |
7078 | 0 | if ((Subtarget->hasNEON())) { |
7079 | 0 | return fastEmitInst_rr(AArch64::CMEQv8i16, &AArch64::FPR128RegClass, Op0, Op1); |
7080 | 0 | } |
7081 | 0 | return 0; |
7082 | 0 | } |
7083 | | |
7084 | 0 | unsigned fastEmit_AArch64ISD_CMEQ_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7085 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
7086 | 0 | return 0; |
7087 | 0 | if ((Subtarget->hasNEON())) { |
7088 | 0 | return fastEmitInst_rr(AArch64::CMEQv2i32, &AArch64::FPR64RegClass, Op0, Op1); |
7089 | 0 | } |
7090 | 0 | return 0; |
7091 | 0 | } |
7092 | | |
7093 | 0 | unsigned fastEmit_AArch64ISD_CMEQ_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7094 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
7095 | 0 | return 0; |
7096 | 0 | if ((Subtarget->hasNEON())) { |
7097 | 0 | return fastEmitInst_rr(AArch64::CMEQv4i32, &AArch64::FPR128RegClass, Op0, Op1); |
7098 | 0 | } |
7099 | 0 | return 0; |
7100 | 0 | } |
7101 | | |
7102 | 0 | unsigned fastEmit_AArch64ISD_CMEQ_MVT_v1i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7103 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
7104 | 0 | return 0; |
7105 | 0 | if ((Subtarget->hasNEON())) { |
7106 | 0 | return fastEmitInst_rr(AArch64::CMEQv1i64, &AArch64::FPR64RegClass, Op0, Op1); |
7107 | 0 | } |
7108 | 0 | return 0; |
7109 | 0 | } |
7110 | | |
7111 | 0 | unsigned fastEmit_AArch64ISD_CMEQ_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7112 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
7113 | 0 | return 0; |
7114 | 0 | if ((Subtarget->hasNEON())) { |
7115 | 0 | return fastEmitInst_rr(AArch64::CMEQv2i64, &AArch64::FPR128RegClass, Op0, Op1); |
7116 | 0 | } |
7117 | 0 | return 0; |
7118 | 0 | } |
7119 | | |
7120 | 0 | unsigned fastEmit_AArch64ISD_CMEQ_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
7121 | 0 | switch (VT.SimpleTy) { |
7122 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_CMEQ_MVT_v8i8_rr(RetVT, Op0, Op1); |
7123 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_CMEQ_MVT_v16i8_rr(RetVT, Op0, Op1); |
7124 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_CMEQ_MVT_v4i16_rr(RetVT, Op0, Op1); |
7125 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_CMEQ_MVT_v8i16_rr(RetVT, Op0, Op1); |
7126 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_CMEQ_MVT_v2i32_rr(RetVT, Op0, Op1); |
7127 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_CMEQ_MVT_v4i32_rr(RetVT, Op0, Op1); |
7128 | 0 | case MVT::v1i64: return fastEmit_AArch64ISD_CMEQ_MVT_v1i64_rr(RetVT, Op0, Op1); |
7129 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_CMEQ_MVT_v2i64_rr(RetVT, Op0, Op1); |
7130 | 0 | default: return 0; |
7131 | 0 | } |
7132 | 0 | } |
7133 | | |
7134 | | // FastEmit functions for AArch64ISD::CMGE. |
7135 | | |
7136 | 0 | unsigned fastEmit_AArch64ISD_CMGE_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7137 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
7138 | 0 | return 0; |
7139 | 0 | if ((Subtarget->hasNEON())) { |
7140 | 0 | return fastEmitInst_rr(AArch64::CMGEv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
7141 | 0 | } |
7142 | 0 | return 0; |
7143 | 0 | } |
7144 | | |
7145 | 0 | unsigned fastEmit_AArch64ISD_CMGE_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7146 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
7147 | 0 | return 0; |
7148 | 0 | if ((Subtarget->hasNEON())) { |
7149 | 0 | return fastEmitInst_rr(AArch64::CMGEv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
7150 | 0 | } |
7151 | 0 | return 0; |
7152 | 0 | } |
7153 | | |
7154 | 0 | unsigned fastEmit_AArch64ISD_CMGE_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7155 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
7156 | 0 | return 0; |
7157 | 0 | if ((Subtarget->hasNEON())) { |
7158 | 0 | return fastEmitInst_rr(AArch64::CMGEv4i16, &AArch64::FPR64RegClass, Op0, Op1); |
7159 | 0 | } |
7160 | 0 | return 0; |
7161 | 0 | } |
7162 | | |
7163 | 0 | unsigned fastEmit_AArch64ISD_CMGE_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7164 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
7165 | 0 | return 0; |
7166 | 0 | if ((Subtarget->hasNEON())) { |
7167 | 0 | return fastEmitInst_rr(AArch64::CMGEv8i16, &AArch64::FPR128RegClass, Op0, Op1); |
7168 | 0 | } |
7169 | 0 | return 0; |
7170 | 0 | } |
7171 | | |
7172 | 0 | unsigned fastEmit_AArch64ISD_CMGE_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7173 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
7174 | 0 | return 0; |
7175 | 0 | if ((Subtarget->hasNEON())) { |
7176 | 0 | return fastEmitInst_rr(AArch64::CMGEv2i32, &AArch64::FPR64RegClass, Op0, Op1); |
7177 | 0 | } |
7178 | 0 | return 0; |
7179 | 0 | } |
7180 | | |
7181 | 0 | unsigned fastEmit_AArch64ISD_CMGE_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7182 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
7183 | 0 | return 0; |
7184 | 0 | if ((Subtarget->hasNEON())) { |
7185 | 0 | return fastEmitInst_rr(AArch64::CMGEv4i32, &AArch64::FPR128RegClass, Op0, Op1); |
7186 | 0 | } |
7187 | 0 | return 0; |
7188 | 0 | } |
7189 | | |
7190 | 0 | unsigned fastEmit_AArch64ISD_CMGE_MVT_v1i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7191 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
7192 | 0 | return 0; |
7193 | 0 | if ((Subtarget->hasNEON())) { |
7194 | 0 | return fastEmitInst_rr(AArch64::CMGEv1i64, &AArch64::FPR64RegClass, Op0, Op1); |
7195 | 0 | } |
7196 | 0 | return 0; |
7197 | 0 | } |
7198 | | |
7199 | 0 | unsigned fastEmit_AArch64ISD_CMGE_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7200 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
7201 | 0 | return 0; |
7202 | 0 | if ((Subtarget->hasNEON())) { |
7203 | 0 | return fastEmitInst_rr(AArch64::CMGEv2i64, &AArch64::FPR128RegClass, Op0, Op1); |
7204 | 0 | } |
7205 | 0 | return 0; |
7206 | 0 | } |
7207 | | |
7208 | 0 | unsigned fastEmit_AArch64ISD_CMGE_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
7209 | 0 | switch (VT.SimpleTy) { |
7210 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_CMGE_MVT_v8i8_rr(RetVT, Op0, Op1); |
7211 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_CMGE_MVT_v16i8_rr(RetVT, Op0, Op1); |
7212 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_CMGE_MVT_v4i16_rr(RetVT, Op0, Op1); |
7213 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_CMGE_MVT_v8i16_rr(RetVT, Op0, Op1); |
7214 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_CMGE_MVT_v2i32_rr(RetVT, Op0, Op1); |
7215 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_CMGE_MVT_v4i32_rr(RetVT, Op0, Op1); |
7216 | 0 | case MVT::v1i64: return fastEmit_AArch64ISD_CMGE_MVT_v1i64_rr(RetVT, Op0, Op1); |
7217 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_CMGE_MVT_v2i64_rr(RetVT, Op0, Op1); |
7218 | 0 | default: return 0; |
7219 | 0 | } |
7220 | 0 | } |
7221 | | |
7222 | | // FastEmit functions for AArch64ISD::CMGT. |
7223 | | |
7224 | 0 | unsigned fastEmit_AArch64ISD_CMGT_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7225 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
7226 | 0 | return 0; |
7227 | 0 | if ((Subtarget->hasNEON())) { |
7228 | 0 | return fastEmitInst_rr(AArch64::CMGTv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
7229 | 0 | } |
7230 | 0 | return 0; |
7231 | 0 | } |
7232 | | |
7233 | 0 | unsigned fastEmit_AArch64ISD_CMGT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7234 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
7235 | 0 | return 0; |
7236 | 0 | if ((Subtarget->hasNEON())) { |
7237 | 0 | return fastEmitInst_rr(AArch64::CMGTv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
7238 | 0 | } |
7239 | 0 | return 0; |
7240 | 0 | } |
7241 | | |
7242 | 0 | unsigned fastEmit_AArch64ISD_CMGT_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7243 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
7244 | 0 | return 0; |
7245 | 0 | if ((Subtarget->hasNEON())) { |
7246 | 0 | return fastEmitInst_rr(AArch64::CMGTv4i16, &AArch64::FPR64RegClass, Op0, Op1); |
7247 | 0 | } |
7248 | 0 | return 0; |
7249 | 0 | } |
7250 | | |
7251 | 0 | unsigned fastEmit_AArch64ISD_CMGT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7252 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
7253 | 0 | return 0; |
7254 | 0 | if ((Subtarget->hasNEON())) { |
7255 | 0 | return fastEmitInst_rr(AArch64::CMGTv8i16, &AArch64::FPR128RegClass, Op0, Op1); |
7256 | 0 | } |
7257 | 0 | return 0; |
7258 | 0 | } |
7259 | | |
7260 | 0 | unsigned fastEmit_AArch64ISD_CMGT_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7261 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
7262 | 0 | return 0; |
7263 | 0 | if ((Subtarget->hasNEON())) { |
7264 | 0 | return fastEmitInst_rr(AArch64::CMGTv2i32, &AArch64::FPR64RegClass, Op0, Op1); |
7265 | 0 | } |
7266 | 0 | return 0; |
7267 | 0 | } |
7268 | | |
7269 | 0 | unsigned fastEmit_AArch64ISD_CMGT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7270 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
7271 | 0 | return 0; |
7272 | 0 | if ((Subtarget->hasNEON())) { |
7273 | 0 | return fastEmitInst_rr(AArch64::CMGTv4i32, &AArch64::FPR128RegClass, Op0, Op1); |
7274 | 0 | } |
7275 | 0 | return 0; |
7276 | 0 | } |
7277 | | |
7278 | 0 | unsigned fastEmit_AArch64ISD_CMGT_MVT_v1i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7279 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
7280 | 0 | return 0; |
7281 | 0 | if ((Subtarget->hasNEON())) { |
7282 | 0 | return fastEmitInst_rr(AArch64::CMGTv1i64, &AArch64::FPR64RegClass, Op0, Op1); |
7283 | 0 | } |
7284 | 0 | return 0; |
7285 | 0 | } |
7286 | | |
7287 | 0 | unsigned fastEmit_AArch64ISD_CMGT_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7288 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
7289 | 0 | return 0; |
7290 | 0 | if ((Subtarget->hasNEON())) { |
7291 | 0 | return fastEmitInst_rr(AArch64::CMGTv2i64, &AArch64::FPR128RegClass, Op0, Op1); |
7292 | 0 | } |
7293 | 0 | return 0; |
7294 | 0 | } |
7295 | | |
7296 | 0 | unsigned fastEmit_AArch64ISD_CMGT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
7297 | 0 | switch (VT.SimpleTy) { |
7298 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_CMGT_MVT_v8i8_rr(RetVT, Op0, Op1); |
7299 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_CMGT_MVT_v16i8_rr(RetVT, Op0, Op1); |
7300 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_CMGT_MVT_v4i16_rr(RetVT, Op0, Op1); |
7301 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_CMGT_MVT_v8i16_rr(RetVT, Op0, Op1); |
7302 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_CMGT_MVT_v2i32_rr(RetVT, Op0, Op1); |
7303 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_CMGT_MVT_v4i32_rr(RetVT, Op0, Op1); |
7304 | 0 | case MVT::v1i64: return fastEmit_AArch64ISD_CMGT_MVT_v1i64_rr(RetVT, Op0, Op1); |
7305 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_CMGT_MVT_v2i64_rr(RetVT, Op0, Op1); |
7306 | 0 | default: return 0; |
7307 | 0 | } |
7308 | 0 | } |
7309 | | |
7310 | | // FastEmit functions for AArch64ISD::CMHI. |
7311 | | |
7312 | 0 | unsigned fastEmit_AArch64ISD_CMHI_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7313 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
7314 | 0 | return 0; |
7315 | 0 | if ((Subtarget->hasNEON())) { |
7316 | 0 | return fastEmitInst_rr(AArch64::CMHIv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
7317 | 0 | } |
7318 | 0 | return 0; |
7319 | 0 | } |
7320 | | |
7321 | 0 | unsigned fastEmit_AArch64ISD_CMHI_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7322 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
7323 | 0 | return 0; |
7324 | 0 | if ((Subtarget->hasNEON())) { |
7325 | 0 | return fastEmitInst_rr(AArch64::CMHIv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
7326 | 0 | } |
7327 | 0 | return 0; |
7328 | 0 | } |
7329 | | |
7330 | 0 | unsigned fastEmit_AArch64ISD_CMHI_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7331 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
7332 | 0 | return 0; |
7333 | 0 | if ((Subtarget->hasNEON())) { |
7334 | 0 | return fastEmitInst_rr(AArch64::CMHIv4i16, &AArch64::FPR64RegClass, Op0, Op1); |
7335 | 0 | } |
7336 | 0 | return 0; |
7337 | 0 | } |
7338 | | |
7339 | 0 | unsigned fastEmit_AArch64ISD_CMHI_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7340 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
7341 | 0 | return 0; |
7342 | 0 | if ((Subtarget->hasNEON())) { |
7343 | 0 | return fastEmitInst_rr(AArch64::CMHIv8i16, &AArch64::FPR128RegClass, Op0, Op1); |
7344 | 0 | } |
7345 | 0 | return 0; |
7346 | 0 | } |
7347 | | |
7348 | 0 | unsigned fastEmit_AArch64ISD_CMHI_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7349 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
7350 | 0 | return 0; |
7351 | 0 | if ((Subtarget->hasNEON())) { |
7352 | 0 | return fastEmitInst_rr(AArch64::CMHIv2i32, &AArch64::FPR64RegClass, Op0, Op1); |
7353 | 0 | } |
7354 | 0 | return 0; |
7355 | 0 | } |
7356 | | |
7357 | 0 | unsigned fastEmit_AArch64ISD_CMHI_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7358 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
7359 | 0 | return 0; |
7360 | 0 | if ((Subtarget->hasNEON())) { |
7361 | 0 | return fastEmitInst_rr(AArch64::CMHIv4i32, &AArch64::FPR128RegClass, Op0, Op1); |
7362 | 0 | } |
7363 | 0 | return 0; |
7364 | 0 | } |
7365 | | |
7366 | 0 | unsigned fastEmit_AArch64ISD_CMHI_MVT_v1i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7367 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
7368 | 0 | return 0; |
7369 | 0 | if ((Subtarget->hasNEON())) { |
7370 | 0 | return fastEmitInst_rr(AArch64::CMHIv1i64, &AArch64::FPR64RegClass, Op0, Op1); |
7371 | 0 | } |
7372 | 0 | return 0; |
7373 | 0 | } |
7374 | | |
7375 | 0 | unsigned fastEmit_AArch64ISD_CMHI_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7376 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
7377 | 0 | return 0; |
7378 | 0 | if ((Subtarget->hasNEON())) { |
7379 | 0 | return fastEmitInst_rr(AArch64::CMHIv2i64, &AArch64::FPR128RegClass, Op0, Op1); |
7380 | 0 | } |
7381 | 0 | return 0; |
7382 | 0 | } |
7383 | | |
7384 | 0 | unsigned fastEmit_AArch64ISD_CMHI_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
7385 | 0 | switch (VT.SimpleTy) { |
7386 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_CMHI_MVT_v8i8_rr(RetVT, Op0, Op1); |
7387 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_CMHI_MVT_v16i8_rr(RetVT, Op0, Op1); |
7388 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_CMHI_MVT_v4i16_rr(RetVT, Op0, Op1); |
7389 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_CMHI_MVT_v8i16_rr(RetVT, Op0, Op1); |
7390 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_CMHI_MVT_v2i32_rr(RetVT, Op0, Op1); |
7391 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_CMHI_MVT_v4i32_rr(RetVT, Op0, Op1); |
7392 | 0 | case MVT::v1i64: return fastEmit_AArch64ISD_CMHI_MVT_v1i64_rr(RetVT, Op0, Op1); |
7393 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_CMHI_MVT_v2i64_rr(RetVT, Op0, Op1); |
7394 | 0 | default: return 0; |
7395 | 0 | } |
7396 | 0 | } |
7397 | | |
7398 | | // FastEmit functions for AArch64ISD::CMHS. |
7399 | | |
7400 | 0 | unsigned fastEmit_AArch64ISD_CMHS_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7401 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
7402 | 0 | return 0; |
7403 | 0 | if ((Subtarget->hasNEON())) { |
7404 | 0 | return fastEmitInst_rr(AArch64::CMHSv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
7405 | 0 | } |
7406 | 0 | return 0; |
7407 | 0 | } |
7408 | | |
7409 | 0 | unsigned fastEmit_AArch64ISD_CMHS_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7410 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
7411 | 0 | return 0; |
7412 | 0 | if ((Subtarget->hasNEON())) { |
7413 | 0 | return fastEmitInst_rr(AArch64::CMHSv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
7414 | 0 | } |
7415 | 0 | return 0; |
7416 | 0 | } |
7417 | | |
7418 | 0 | unsigned fastEmit_AArch64ISD_CMHS_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7419 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
7420 | 0 | return 0; |
7421 | 0 | if ((Subtarget->hasNEON())) { |
7422 | 0 | return fastEmitInst_rr(AArch64::CMHSv4i16, &AArch64::FPR64RegClass, Op0, Op1); |
7423 | 0 | } |
7424 | 0 | return 0; |
7425 | 0 | } |
7426 | | |
7427 | 0 | unsigned fastEmit_AArch64ISD_CMHS_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7428 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
7429 | 0 | return 0; |
7430 | 0 | if ((Subtarget->hasNEON())) { |
7431 | 0 | return fastEmitInst_rr(AArch64::CMHSv8i16, &AArch64::FPR128RegClass, Op0, Op1); |
7432 | 0 | } |
7433 | 0 | return 0; |
7434 | 0 | } |
7435 | | |
7436 | 0 | unsigned fastEmit_AArch64ISD_CMHS_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7437 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
7438 | 0 | return 0; |
7439 | 0 | if ((Subtarget->hasNEON())) { |
7440 | 0 | return fastEmitInst_rr(AArch64::CMHSv2i32, &AArch64::FPR64RegClass, Op0, Op1); |
7441 | 0 | } |
7442 | 0 | return 0; |
7443 | 0 | } |
7444 | | |
7445 | 0 | unsigned fastEmit_AArch64ISD_CMHS_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7446 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
7447 | 0 | return 0; |
7448 | 0 | if ((Subtarget->hasNEON())) { |
7449 | 0 | return fastEmitInst_rr(AArch64::CMHSv4i32, &AArch64::FPR128RegClass, Op0, Op1); |
7450 | 0 | } |
7451 | 0 | return 0; |
7452 | 0 | } |
7453 | | |
7454 | 0 | unsigned fastEmit_AArch64ISD_CMHS_MVT_v1i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7455 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
7456 | 0 | return 0; |
7457 | 0 | if ((Subtarget->hasNEON())) { |
7458 | 0 | return fastEmitInst_rr(AArch64::CMHSv1i64, &AArch64::FPR64RegClass, Op0, Op1); |
7459 | 0 | } |
7460 | 0 | return 0; |
7461 | 0 | } |
7462 | | |
7463 | 0 | unsigned fastEmit_AArch64ISD_CMHS_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7464 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
7465 | 0 | return 0; |
7466 | 0 | if ((Subtarget->hasNEON())) { |
7467 | 0 | return fastEmitInst_rr(AArch64::CMHSv2i64, &AArch64::FPR128RegClass, Op0, Op1); |
7468 | 0 | } |
7469 | 0 | return 0; |
7470 | 0 | } |
7471 | | |
7472 | 0 | unsigned fastEmit_AArch64ISD_CMHS_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
7473 | 0 | switch (VT.SimpleTy) { |
7474 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_CMHS_MVT_v8i8_rr(RetVT, Op0, Op1); |
7475 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_CMHS_MVT_v16i8_rr(RetVT, Op0, Op1); |
7476 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_CMHS_MVT_v4i16_rr(RetVT, Op0, Op1); |
7477 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_CMHS_MVT_v8i16_rr(RetVT, Op0, Op1); |
7478 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_CMHS_MVT_v2i32_rr(RetVT, Op0, Op1); |
7479 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_CMHS_MVT_v4i32_rr(RetVT, Op0, Op1); |
7480 | 0 | case MVT::v1i64: return fastEmit_AArch64ISD_CMHS_MVT_v1i64_rr(RetVT, Op0, Op1); |
7481 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_CMHS_MVT_v2i64_rr(RetVT, Op0, Op1); |
7482 | 0 | default: return 0; |
7483 | 0 | } |
7484 | 0 | } |
7485 | | |
7486 | | // FastEmit functions for AArch64ISD::FCMEQ. |
7487 | | |
7488 | 0 | unsigned fastEmit_AArch64ISD_FCMEQ_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7489 | 0 | if (RetVT.SimpleTy != MVT::i32) |
7490 | 0 | return 0; |
7491 | 0 | if ((Subtarget->hasNEON())) { |
7492 | 0 | return fastEmitInst_rr(AArch64::FCMEQ32, &AArch64::FPR32RegClass, Op0, Op1); |
7493 | 0 | } |
7494 | 0 | return 0; |
7495 | 0 | } |
7496 | | |
7497 | 0 | unsigned fastEmit_AArch64ISD_FCMEQ_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7498 | 0 | if (RetVT.SimpleTy != MVT::i64) |
7499 | 0 | return 0; |
7500 | 0 | if ((Subtarget->hasNEON())) { |
7501 | 0 | return fastEmitInst_rr(AArch64::FCMEQ64, &AArch64::FPR64RegClass, Op0, Op1); |
7502 | 0 | } |
7503 | 0 | return 0; |
7504 | 0 | } |
7505 | | |
7506 | 0 | unsigned fastEmit_AArch64ISD_FCMEQ_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7507 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
7508 | 0 | return 0; |
7509 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
7510 | 0 | return fastEmitInst_rr(AArch64::FCMEQv4f16, &AArch64::FPR64RegClass, Op0, Op1); |
7511 | 0 | } |
7512 | 0 | return 0; |
7513 | 0 | } |
7514 | | |
7515 | 0 | unsigned fastEmit_AArch64ISD_FCMEQ_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7516 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
7517 | 0 | return 0; |
7518 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
7519 | 0 | return fastEmitInst_rr(AArch64::FCMEQv8f16, &AArch64::FPR128RegClass, Op0, Op1); |
7520 | 0 | } |
7521 | 0 | return 0; |
7522 | 0 | } |
7523 | | |
7524 | 0 | unsigned fastEmit_AArch64ISD_FCMEQ_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7525 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
7526 | 0 | return 0; |
7527 | 0 | if ((Subtarget->hasNEON())) { |
7528 | 0 | return fastEmitInst_rr(AArch64::FCMEQv2f32, &AArch64::FPR64RegClass, Op0, Op1); |
7529 | 0 | } |
7530 | 0 | return 0; |
7531 | 0 | } |
7532 | | |
7533 | 0 | unsigned fastEmit_AArch64ISD_FCMEQ_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7534 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
7535 | 0 | return 0; |
7536 | 0 | if ((Subtarget->hasNEON())) { |
7537 | 0 | return fastEmitInst_rr(AArch64::FCMEQv4f32, &AArch64::FPR128RegClass, Op0, Op1); |
7538 | 0 | } |
7539 | 0 | return 0; |
7540 | 0 | } |
7541 | | |
7542 | 0 | unsigned fastEmit_AArch64ISD_FCMEQ_MVT_v1f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7543 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
7544 | 0 | return 0; |
7545 | 0 | if ((Subtarget->hasNEON())) { |
7546 | 0 | return fastEmitInst_rr(AArch64::FCMEQ64, &AArch64::FPR64RegClass, Op0, Op1); |
7547 | 0 | } |
7548 | 0 | return 0; |
7549 | 0 | } |
7550 | | |
7551 | 0 | unsigned fastEmit_AArch64ISD_FCMEQ_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7552 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
7553 | 0 | return 0; |
7554 | 0 | if ((Subtarget->hasNEON())) { |
7555 | 0 | return fastEmitInst_rr(AArch64::FCMEQv2f64, &AArch64::FPR128RegClass, Op0, Op1); |
7556 | 0 | } |
7557 | 0 | return 0; |
7558 | 0 | } |
7559 | | |
7560 | 0 | unsigned fastEmit_AArch64ISD_FCMEQ_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
7561 | 0 | switch (VT.SimpleTy) { |
7562 | 0 | case MVT::f32: return fastEmit_AArch64ISD_FCMEQ_MVT_f32_rr(RetVT, Op0, Op1); |
7563 | 0 | case MVT::f64: return fastEmit_AArch64ISD_FCMEQ_MVT_f64_rr(RetVT, Op0, Op1); |
7564 | 0 | case MVT::v4f16: return fastEmit_AArch64ISD_FCMEQ_MVT_v4f16_rr(RetVT, Op0, Op1); |
7565 | 0 | case MVT::v8f16: return fastEmit_AArch64ISD_FCMEQ_MVT_v8f16_rr(RetVT, Op0, Op1); |
7566 | 0 | case MVT::v2f32: return fastEmit_AArch64ISD_FCMEQ_MVT_v2f32_rr(RetVT, Op0, Op1); |
7567 | 0 | case MVT::v4f32: return fastEmit_AArch64ISD_FCMEQ_MVT_v4f32_rr(RetVT, Op0, Op1); |
7568 | 0 | case MVT::v1f64: return fastEmit_AArch64ISD_FCMEQ_MVT_v1f64_rr(RetVT, Op0, Op1); |
7569 | 0 | case MVT::v2f64: return fastEmit_AArch64ISD_FCMEQ_MVT_v2f64_rr(RetVT, Op0, Op1); |
7570 | 0 | default: return 0; |
7571 | 0 | } |
7572 | 0 | } |
7573 | | |
7574 | | // FastEmit functions for AArch64ISD::FCMGE. |
7575 | | |
7576 | 0 | unsigned fastEmit_AArch64ISD_FCMGE_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7577 | 0 | if (RetVT.SimpleTy != MVT::i32) |
7578 | 0 | return 0; |
7579 | 0 | if ((Subtarget->hasNEON())) { |
7580 | 0 | return fastEmitInst_rr(AArch64::FCMGE32, &AArch64::FPR32RegClass, Op0, Op1); |
7581 | 0 | } |
7582 | 0 | return 0; |
7583 | 0 | } |
7584 | | |
7585 | 0 | unsigned fastEmit_AArch64ISD_FCMGE_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7586 | 0 | if (RetVT.SimpleTy != MVT::i64) |
7587 | 0 | return 0; |
7588 | 0 | if ((Subtarget->hasNEON())) { |
7589 | 0 | return fastEmitInst_rr(AArch64::FCMGE64, &AArch64::FPR64RegClass, Op0, Op1); |
7590 | 0 | } |
7591 | 0 | return 0; |
7592 | 0 | } |
7593 | | |
7594 | 0 | unsigned fastEmit_AArch64ISD_FCMGE_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7595 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
7596 | 0 | return 0; |
7597 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
7598 | 0 | return fastEmitInst_rr(AArch64::FCMGEv4f16, &AArch64::FPR64RegClass, Op0, Op1); |
7599 | 0 | } |
7600 | 0 | return 0; |
7601 | 0 | } |
7602 | | |
7603 | 0 | unsigned fastEmit_AArch64ISD_FCMGE_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7604 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
7605 | 0 | return 0; |
7606 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
7607 | 0 | return fastEmitInst_rr(AArch64::FCMGEv8f16, &AArch64::FPR128RegClass, Op0, Op1); |
7608 | 0 | } |
7609 | 0 | return 0; |
7610 | 0 | } |
7611 | | |
7612 | 0 | unsigned fastEmit_AArch64ISD_FCMGE_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7613 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
7614 | 0 | return 0; |
7615 | 0 | if ((Subtarget->hasNEON())) { |
7616 | 0 | return fastEmitInst_rr(AArch64::FCMGEv2f32, &AArch64::FPR64RegClass, Op0, Op1); |
7617 | 0 | } |
7618 | 0 | return 0; |
7619 | 0 | } |
7620 | | |
7621 | 0 | unsigned fastEmit_AArch64ISD_FCMGE_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7622 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
7623 | 0 | return 0; |
7624 | 0 | if ((Subtarget->hasNEON())) { |
7625 | 0 | return fastEmitInst_rr(AArch64::FCMGEv4f32, &AArch64::FPR128RegClass, Op0, Op1); |
7626 | 0 | } |
7627 | 0 | return 0; |
7628 | 0 | } |
7629 | | |
7630 | 0 | unsigned fastEmit_AArch64ISD_FCMGE_MVT_v1f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7631 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
7632 | 0 | return 0; |
7633 | 0 | if ((Subtarget->hasNEON())) { |
7634 | 0 | return fastEmitInst_rr(AArch64::FCMGE64, &AArch64::FPR64RegClass, Op0, Op1); |
7635 | 0 | } |
7636 | 0 | return 0; |
7637 | 0 | } |
7638 | | |
7639 | 0 | unsigned fastEmit_AArch64ISD_FCMGE_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7640 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
7641 | 0 | return 0; |
7642 | 0 | if ((Subtarget->hasNEON())) { |
7643 | 0 | return fastEmitInst_rr(AArch64::FCMGEv2f64, &AArch64::FPR128RegClass, Op0, Op1); |
7644 | 0 | } |
7645 | 0 | return 0; |
7646 | 0 | } |
7647 | | |
7648 | 0 | unsigned fastEmit_AArch64ISD_FCMGE_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
7649 | 0 | switch (VT.SimpleTy) { |
7650 | 0 | case MVT::f32: return fastEmit_AArch64ISD_FCMGE_MVT_f32_rr(RetVT, Op0, Op1); |
7651 | 0 | case MVT::f64: return fastEmit_AArch64ISD_FCMGE_MVT_f64_rr(RetVT, Op0, Op1); |
7652 | 0 | case MVT::v4f16: return fastEmit_AArch64ISD_FCMGE_MVT_v4f16_rr(RetVT, Op0, Op1); |
7653 | 0 | case MVT::v8f16: return fastEmit_AArch64ISD_FCMGE_MVT_v8f16_rr(RetVT, Op0, Op1); |
7654 | 0 | case MVT::v2f32: return fastEmit_AArch64ISD_FCMGE_MVT_v2f32_rr(RetVT, Op0, Op1); |
7655 | 0 | case MVT::v4f32: return fastEmit_AArch64ISD_FCMGE_MVT_v4f32_rr(RetVT, Op0, Op1); |
7656 | 0 | case MVT::v1f64: return fastEmit_AArch64ISD_FCMGE_MVT_v1f64_rr(RetVT, Op0, Op1); |
7657 | 0 | case MVT::v2f64: return fastEmit_AArch64ISD_FCMGE_MVT_v2f64_rr(RetVT, Op0, Op1); |
7658 | 0 | default: return 0; |
7659 | 0 | } |
7660 | 0 | } |
7661 | | |
7662 | | // FastEmit functions for AArch64ISD::FCMGT. |
7663 | | |
7664 | 0 | unsigned fastEmit_AArch64ISD_FCMGT_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7665 | 0 | if (RetVT.SimpleTy != MVT::i32) |
7666 | 0 | return 0; |
7667 | 0 | if ((Subtarget->hasNEON())) { |
7668 | 0 | return fastEmitInst_rr(AArch64::FCMGT32, &AArch64::FPR32RegClass, Op0, Op1); |
7669 | 0 | } |
7670 | 0 | return 0; |
7671 | 0 | } |
7672 | | |
7673 | 0 | unsigned fastEmit_AArch64ISD_FCMGT_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7674 | 0 | if (RetVT.SimpleTy != MVT::i64) |
7675 | 0 | return 0; |
7676 | 0 | if ((Subtarget->hasNEON())) { |
7677 | 0 | return fastEmitInst_rr(AArch64::FCMGT64, &AArch64::FPR64RegClass, Op0, Op1); |
7678 | 0 | } |
7679 | 0 | return 0; |
7680 | 0 | } |
7681 | | |
7682 | 0 | unsigned fastEmit_AArch64ISD_FCMGT_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7683 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
7684 | 0 | return 0; |
7685 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
7686 | 0 | return fastEmitInst_rr(AArch64::FCMGTv4f16, &AArch64::FPR64RegClass, Op0, Op1); |
7687 | 0 | } |
7688 | 0 | return 0; |
7689 | 0 | } |
7690 | | |
7691 | 0 | unsigned fastEmit_AArch64ISD_FCMGT_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7692 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
7693 | 0 | return 0; |
7694 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
7695 | 0 | return fastEmitInst_rr(AArch64::FCMGTv8f16, &AArch64::FPR128RegClass, Op0, Op1); |
7696 | 0 | } |
7697 | 0 | return 0; |
7698 | 0 | } |
7699 | | |
7700 | 0 | unsigned fastEmit_AArch64ISD_FCMGT_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7701 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
7702 | 0 | return 0; |
7703 | 0 | if ((Subtarget->hasNEON())) { |
7704 | 0 | return fastEmitInst_rr(AArch64::FCMGTv2f32, &AArch64::FPR64RegClass, Op0, Op1); |
7705 | 0 | } |
7706 | 0 | return 0; |
7707 | 0 | } |
7708 | | |
7709 | 0 | unsigned fastEmit_AArch64ISD_FCMGT_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7710 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
7711 | 0 | return 0; |
7712 | 0 | if ((Subtarget->hasNEON())) { |
7713 | 0 | return fastEmitInst_rr(AArch64::FCMGTv4f32, &AArch64::FPR128RegClass, Op0, Op1); |
7714 | 0 | } |
7715 | 0 | return 0; |
7716 | 0 | } |
7717 | | |
7718 | 0 | unsigned fastEmit_AArch64ISD_FCMGT_MVT_v1f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7719 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
7720 | 0 | return 0; |
7721 | 0 | if ((Subtarget->hasNEON())) { |
7722 | 0 | return fastEmitInst_rr(AArch64::FCMGT64, &AArch64::FPR64RegClass, Op0, Op1); |
7723 | 0 | } |
7724 | 0 | return 0; |
7725 | 0 | } |
7726 | | |
7727 | 0 | unsigned fastEmit_AArch64ISD_FCMGT_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7728 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
7729 | 0 | return 0; |
7730 | 0 | if ((Subtarget->hasNEON())) { |
7731 | 0 | return fastEmitInst_rr(AArch64::FCMGTv2f64, &AArch64::FPR128RegClass, Op0, Op1); |
7732 | 0 | } |
7733 | 0 | return 0; |
7734 | 0 | } |
7735 | | |
7736 | 0 | unsigned fastEmit_AArch64ISD_FCMGT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
7737 | 0 | switch (VT.SimpleTy) { |
7738 | 0 | case MVT::f32: return fastEmit_AArch64ISD_FCMGT_MVT_f32_rr(RetVT, Op0, Op1); |
7739 | 0 | case MVT::f64: return fastEmit_AArch64ISD_FCMGT_MVT_f64_rr(RetVT, Op0, Op1); |
7740 | 0 | case MVT::v4f16: return fastEmit_AArch64ISD_FCMGT_MVT_v4f16_rr(RetVT, Op0, Op1); |
7741 | 0 | case MVT::v8f16: return fastEmit_AArch64ISD_FCMGT_MVT_v8f16_rr(RetVT, Op0, Op1); |
7742 | 0 | case MVT::v2f32: return fastEmit_AArch64ISD_FCMGT_MVT_v2f32_rr(RetVT, Op0, Op1); |
7743 | 0 | case MVT::v4f32: return fastEmit_AArch64ISD_FCMGT_MVT_v4f32_rr(RetVT, Op0, Op1); |
7744 | 0 | case MVT::v1f64: return fastEmit_AArch64ISD_FCMGT_MVT_v1f64_rr(RetVT, Op0, Op1); |
7745 | 0 | case MVT::v2f64: return fastEmit_AArch64ISD_FCMGT_MVT_v2f64_rr(RetVT, Op0, Op1); |
7746 | 0 | default: return 0; |
7747 | 0 | } |
7748 | 0 | } |
7749 | | |
7750 | | // FastEmit functions for AArch64ISD::FCMP. |
7751 | | |
7752 | 0 | unsigned fastEmit_AArch64ISD_FCMP_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7753 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
7754 | 0 | return 0; |
7755 | 0 | if ((Subtarget->hasFullFP16())) { |
7756 | 0 | return fastEmitInst_rr(AArch64::FCMPHrr, &AArch64::FPR16RegClass, Op0, Op1); |
7757 | 0 | } |
7758 | 0 | return 0; |
7759 | 0 | } |
7760 | | |
7761 | 0 | unsigned fastEmit_AArch64ISD_FCMP_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7762 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
7763 | 0 | return 0; |
7764 | 0 | if ((Subtarget->hasFPARMv8())) { |
7765 | 0 | return fastEmitInst_rr(AArch64::FCMPSrr, &AArch64::FPR32RegClass, Op0, Op1); |
7766 | 0 | } |
7767 | 0 | return 0; |
7768 | 0 | } |
7769 | | |
7770 | 0 | unsigned fastEmit_AArch64ISD_FCMP_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7771 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
7772 | 0 | return 0; |
7773 | 0 | if ((Subtarget->hasFPARMv8())) { |
7774 | 0 | return fastEmitInst_rr(AArch64::FCMPDrr, &AArch64::FPR64RegClass, Op0, Op1); |
7775 | 0 | } |
7776 | 0 | return 0; |
7777 | 0 | } |
7778 | | |
7779 | 0 | unsigned fastEmit_AArch64ISD_FCMP_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
7780 | 0 | switch (VT.SimpleTy) { |
7781 | 0 | case MVT::f16: return fastEmit_AArch64ISD_FCMP_MVT_f16_rr(RetVT, Op0, Op1); |
7782 | 0 | case MVT::f32: return fastEmit_AArch64ISD_FCMP_MVT_f32_rr(RetVT, Op0, Op1); |
7783 | 0 | case MVT::f64: return fastEmit_AArch64ISD_FCMP_MVT_f64_rr(RetVT, Op0, Op1); |
7784 | 0 | default: return 0; |
7785 | 0 | } |
7786 | 0 | } |
7787 | | |
7788 | | // FastEmit functions for AArch64ISD::FRECPS. |
7789 | | |
7790 | 0 | unsigned fastEmit_AArch64ISD_FRECPS_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7791 | 0 | if (RetVT.SimpleTy != MVT::f32) |
7792 | 0 | return 0; |
7793 | 0 | return fastEmitInst_rr(AArch64::FRECPS32, &AArch64::FPR32RegClass, Op0, Op1); |
7794 | 0 | } |
7795 | | |
7796 | 0 | unsigned fastEmit_AArch64ISD_FRECPS_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7797 | 0 | if (RetVT.SimpleTy != MVT::f64) |
7798 | 0 | return 0; |
7799 | 0 | return fastEmitInst_rr(AArch64::FRECPS64, &AArch64::FPR64RegClass, Op0, Op1); |
7800 | 0 | } |
7801 | | |
7802 | 0 | unsigned fastEmit_AArch64ISD_FRECPS_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7803 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
7804 | 0 | return 0; |
7805 | 0 | return fastEmitInst_rr(AArch64::FRECPSv2f32, &AArch64::FPR64RegClass, Op0, Op1); |
7806 | 0 | } |
7807 | | |
7808 | 0 | unsigned fastEmit_AArch64ISD_FRECPS_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7809 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
7810 | 0 | return 0; |
7811 | 0 | return fastEmitInst_rr(AArch64::FRECPSv4f32, &AArch64::FPR128RegClass, Op0, Op1); |
7812 | 0 | } |
7813 | | |
7814 | 0 | unsigned fastEmit_AArch64ISD_FRECPS_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7815 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
7816 | 0 | return 0; |
7817 | 0 | return fastEmitInst_rr(AArch64::FRECPSv2f64, &AArch64::FPR128RegClass, Op0, Op1); |
7818 | 0 | } |
7819 | | |
7820 | 0 | unsigned fastEmit_AArch64ISD_FRECPS_MVT_nxv8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7821 | 0 | if (RetVT.SimpleTy != MVT::nxv8f16) |
7822 | 0 | return 0; |
7823 | 0 | if ((Subtarget->hasSVEorSME())) { |
7824 | 0 | return fastEmitInst_rr(AArch64::FRECPS_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
7825 | 0 | } |
7826 | 0 | return 0; |
7827 | 0 | } |
7828 | | |
7829 | 0 | unsigned fastEmit_AArch64ISD_FRECPS_MVT_nxv4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7830 | 0 | if (RetVT.SimpleTy != MVT::nxv4f32) |
7831 | 0 | return 0; |
7832 | 0 | if ((Subtarget->hasSVEorSME())) { |
7833 | 0 | return fastEmitInst_rr(AArch64::FRECPS_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
7834 | 0 | } |
7835 | 0 | return 0; |
7836 | 0 | } |
7837 | | |
7838 | 0 | unsigned fastEmit_AArch64ISD_FRECPS_MVT_nxv2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7839 | 0 | if (RetVT.SimpleTy != MVT::nxv2f64) |
7840 | 0 | return 0; |
7841 | 0 | if ((Subtarget->hasSVEorSME())) { |
7842 | 0 | return fastEmitInst_rr(AArch64::FRECPS_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
7843 | 0 | } |
7844 | 0 | return 0; |
7845 | 0 | } |
7846 | | |
7847 | 0 | unsigned fastEmit_AArch64ISD_FRECPS_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
7848 | 0 | switch (VT.SimpleTy) { |
7849 | 0 | case MVT::f32: return fastEmit_AArch64ISD_FRECPS_MVT_f32_rr(RetVT, Op0, Op1); |
7850 | 0 | case MVT::f64: return fastEmit_AArch64ISD_FRECPS_MVT_f64_rr(RetVT, Op0, Op1); |
7851 | 0 | case MVT::v2f32: return fastEmit_AArch64ISD_FRECPS_MVT_v2f32_rr(RetVT, Op0, Op1); |
7852 | 0 | case MVT::v4f32: return fastEmit_AArch64ISD_FRECPS_MVT_v4f32_rr(RetVT, Op0, Op1); |
7853 | 0 | case MVT::v2f64: return fastEmit_AArch64ISD_FRECPS_MVT_v2f64_rr(RetVT, Op0, Op1); |
7854 | 0 | case MVT::nxv8f16: return fastEmit_AArch64ISD_FRECPS_MVT_nxv8f16_rr(RetVT, Op0, Op1); |
7855 | 0 | case MVT::nxv4f32: return fastEmit_AArch64ISD_FRECPS_MVT_nxv4f32_rr(RetVT, Op0, Op1); |
7856 | 0 | case MVT::nxv2f64: return fastEmit_AArch64ISD_FRECPS_MVT_nxv2f64_rr(RetVT, Op0, Op1); |
7857 | 0 | default: return 0; |
7858 | 0 | } |
7859 | 0 | } |
7860 | | |
7861 | | // FastEmit functions for AArch64ISD::FRSQRTS. |
7862 | | |
7863 | 0 | unsigned fastEmit_AArch64ISD_FRSQRTS_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7864 | 0 | if (RetVT.SimpleTy != MVT::f32) |
7865 | 0 | return 0; |
7866 | 0 | return fastEmitInst_rr(AArch64::FRSQRTS32, &AArch64::FPR32RegClass, Op0, Op1); |
7867 | 0 | } |
7868 | | |
7869 | 0 | unsigned fastEmit_AArch64ISD_FRSQRTS_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7870 | 0 | if (RetVT.SimpleTy != MVT::f64) |
7871 | 0 | return 0; |
7872 | 0 | return fastEmitInst_rr(AArch64::FRSQRTS64, &AArch64::FPR64RegClass, Op0, Op1); |
7873 | 0 | } |
7874 | | |
7875 | 0 | unsigned fastEmit_AArch64ISD_FRSQRTS_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7876 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
7877 | 0 | return 0; |
7878 | 0 | return fastEmitInst_rr(AArch64::FRSQRTSv2f32, &AArch64::FPR64RegClass, Op0, Op1); |
7879 | 0 | } |
7880 | | |
7881 | 0 | unsigned fastEmit_AArch64ISD_FRSQRTS_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7882 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
7883 | 0 | return 0; |
7884 | 0 | return fastEmitInst_rr(AArch64::FRSQRTSv4f32, &AArch64::FPR128RegClass, Op0, Op1); |
7885 | 0 | } |
7886 | | |
7887 | 0 | unsigned fastEmit_AArch64ISD_FRSQRTS_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7888 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
7889 | 0 | return 0; |
7890 | 0 | return fastEmitInst_rr(AArch64::FRSQRTSv2f64, &AArch64::FPR128RegClass, Op0, Op1); |
7891 | 0 | } |
7892 | | |
7893 | 0 | unsigned fastEmit_AArch64ISD_FRSQRTS_MVT_nxv8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7894 | 0 | if (RetVT.SimpleTy != MVT::nxv8f16) |
7895 | 0 | return 0; |
7896 | 0 | if ((Subtarget->hasSVEorSME())) { |
7897 | 0 | return fastEmitInst_rr(AArch64::FRSQRTS_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
7898 | 0 | } |
7899 | 0 | return 0; |
7900 | 0 | } |
7901 | | |
7902 | 0 | unsigned fastEmit_AArch64ISD_FRSQRTS_MVT_nxv4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7903 | 0 | if (RetVT.SimpleTy != MVT::nxv4f32) |
7904 | 0 | return 0; |
7905 | 0 | if ((Subtarget->hasSVEorSME())) { |
7906 | 0 | return fastEmitInst_rr(AArch64::FRSQRTS_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
7907 | 0 | } |
7908 | 0 | return 0; |
7909 | 0 | } |
7910 | | |
7911 | 0 | unsigned fastEmit_AArch64ISD_FRSQRTS_MVT_nxv2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7912 | 0 | if (RetVT.SimpleTy != MVT::nxv2f64) |
7913 | 0 | return 0; |
7914 | 0 | if ((Subtarget->hasSVEorSME())) { |
7915 | 0 | return fastEmitInst_rr(AArch64::FRSQRTS_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
7916 | 0 | } |
7917 | 0 | return 0; |
7918 | 0 | } |
7919 | | |
7920 | 0 | unsigned fastEmit_AArch64ISD_FRSQRTS_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
7921 | 0 | switch (VT.SimpleTy) { |
7922 | 0 | case MVT::f32: return fastEmit_AArch64ISD_FRSQRTS_MVT_f32_rr(RetVT, Op0, Op1); |
7923 | 0 | case MVT::f64: return fastEmit_AArch64ISD_FRSQRTS_MVT_f64_rr(RetVT, Op0, Op1); |
7924 | 0 | case MVT::v2f32: return fastEmit_AArch64ISD_FRSQRTS_MVT_v2f32_rr(RetVT, Op0, Op1); |
7925 | 0 | case MVT::v4f32: return fastEmit_AArch64ISD_FRSQRTS_MVT_v4f32_rr(RetVT, Op0, Op1); |
7926 | 0 | case MVT::v2f64: return fastEmit_AArch64ISD_FRSQRTS_MVT_v2f64_rr(RetVT, Op0, Op1); |
7927 | 0 | case MVT::nxv8f16: return fastEmit_AArch64ISD_FRSQRTS_MVT_nxv8f16_rr(RetVT, Op0, Op1); |
7928 | 0 | case MVT::nxv4f32: return fastEmit_AArch64ISD_FRSQRTS_MVT_nxv4f32_rr(RetVT, Op0, Op1); |
7929 | 0 | case MVT::nxv2f64: return fastEmit_AArch64ISD_FRSQRTS_MVT_nxv2f64_rr(RetVT, Op0, Op1); |
7930 | 0 | default: return 0; |
7931 | 0 | } |
7932 | 0 | } |
7933 | | |
7934 | | // FastEmit functions for AArch64ISD::PMULL. |
7935 | | |
7936 | 0 | unsigned fastEmit_AArch64ISD_PMULL_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7937 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
7938 | 0 | return 0; |
7939 | 0 | if ((Subtarget->hasNEON())) { |
7940 | 0 | return fastEmitInst_rr(AArch64::PMULLv8i8, &AArch64::FPR128RegClass, Op0, Op1); |
7941 | 0 | } |
7942 | 0 | return 0; |
7943 | 0 | } |
7944 | | |
7945 | 0 | unsigned fastEmit_AArch64ISD_PMULL_MVT_v1i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7946 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
7947 | 0 | return 0; |
7948 | 0 | if ((Subtarget->hasAES())) { |
7949 | 0 | return fastEmitInst_rr(AArch64::PMULLv1i64, &AArch64::FPR128RegClass, Op0, Op1); |
7950 | 0 | } |
7951 | 0 | return 0; |
7952 | 0 | } |
7953 | | |
7954 | 0 | unsigned fastEmit_AArch64ISD_PMULL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
7955 | 0 | switch (VT.SimpleTy) { |
7956 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_PMULL_MVT_v8i8_rr(RetVT, Op0, Op1); |
7957 | 0 | case MVT::v1i64: return fastEmit_AArch64ISD_PMULL_MVT_v1i64_rr(RetVT, Op0, Op1); |
7958 | 0 | default: return 0; |
7959 | 0 | } |
7960 | 0 | } |
7961 | | |
7962 | | // FastEmit functions for AArch64ISD::PTEST. |
7963 | | |
7964 | 0 | unsigned fastEmit_AArch64ISD_PTEST_MVT_nxv16i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7965 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
7966 | 0 | return 0; |
7967 | 0 | if ((Subtarget->hasSVEorSME())) { |
7968 | 0 | return fastEmitInst_rr(AArch64::PTEST_PP, &AArch64::PPRRegClass, Op0, Op1); |
7969 | 0 | } |
7970 | 0 | return 0; |
7971 | 0 | } |
7972 | | |
7973 | 0 | unsigned fastEmit_AArch64ISD_PTEST_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
7974 | 0 | switch (VT.SimpleTy) { |
7975 | 0 | case MVT::nxv16i1: return fastEmit_AArch64ISD_PTEST_MVT_nxv16i1_rr(RetVT, Op0, Op1); |
7976 | 0 | default: return 0; |
7977 | 0 | } |
7978 | 0 | } |
7979 | | |
7980 | | // FastEmit functions for AArch64ISD::PTEST_ANY. |
7981 | | |
7982 | 0 | unsigned fastEmit_AArch64ISD_PTEST_ANY_MVT_nxv16i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
7983 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
7984 | 0 | return 0; |
7985 | 0 | if ((Subtarget->hasSVEorSME())) { |
7986 | 0 | return fastEmitInst_rr(AArch64::PTEST_PP_ANY, &AArch64::PPRRegClass, Op0, Op1); |
7987 | 0 | } |
7988 | 0 | return 0; |
7989 | 0 | } |
7990 | | |
7991 | 0 | unsigned fastEmit_AArch64ISD_PTEST_ANY_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
7992 | 0 | switch (VT.SimpleTy) { |
7993 | 0 | case MVT::nxv16i1: return fastEmit_AArch64ISD_PTEST_ANY_MVT_nxv16i1_rr(RetVT, Op0, Op1); |
7994 | 0 | default: return 0; |
7995 | 0 | } |
7996 | 0 | } |
7997 | | |
7998 | | // FastEmit functions for AArch64ISD::SMULL. |
7999 | | |
8000 | 0 | unsigned fastEmit_AArch64ISD_SMULL_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8001 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
8002 | 0 | return 0; |
8003 | 0 | if ((Subtarget->hasNEON())) { |
8004 | 0 | return fastEmitInst_rr(AArch64::SMULLv8i8_v8i16, &AArch64::FPR128RegClass, Op0, Op1); |
8005 | 0 | } |
8006 | 0 | return 0; |
8007 | 0 | } |
8008 | | |
8009 | 0 | unsigned fastEmit_AArch64ISD_SMULL_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8010 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
8011 | 0 | return 0; |
8012 | 0 | if ((Subtarget->hasNEON())) { |
8013 | 0 | return fastEmitInst_rr(AArch64::SMULLv4i16_v4i32, &AArch64::FPR128RegClass, Op0, Op1); |
8014 | 0 | } |
8015 | 0 | return 0; |
8016 | 0 | } |
8017 | | |
8018 | 0 | unsigned fastEmit_AArch64ISD_SMULL_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8019 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
8020 | 0 | return 0; |
8021 | 0 | if ((Subtarget->hasNEON())) { |
8022 | 0 | return fastEmitInst_rr(AArch64::SMULLv2i32_v2i64, &AArch64::FPR128RegClass, Op0, Op1); |
8023 | 0 | } |
8024 | 0 | return 0; |
8025 | 0 | } |
8026 | | |
8027 | 0 | unsigned fastEmit_AArch64ISD_SMULL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
8028 | 0 | switch (VT.SimpleTy) { |
8029 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_SMULL_MVT_v8i8_rr(RetVT, Op0, Op1); |
8030 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_SMULL_MVT_v4i16_rr(RetVT, Op0, Op1); |
8031 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_SMULL_MVT_v2i32_rr(RetVT, Op0, Op1); |
8032 | 0 | default: return 0; |
8033 | 0 | } |
8034 | 0 | } |
8035 | | |
8036 | | // FastEmit functions for AArch64ISD::STRICT_FCMP. |
8037 | | |
8038 | 0 | unsigned fastEmit_AArch64ISD_STRICT_FCMP_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8039 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
8040 | 0 | return 0; |
8041 | 0 | if ((Subtarget->hasFullFP16())) { |
8042 | 0 | return fastEmitInst_rr(AArch64::FCMPHrr, &AArch64::FPR16RegClass, Op0, Op1); |
8043 | 0 | } |
8044 | 0 | return 0; |
8045 | 0 | } |
8046 | | |
8047 | 0 | unsigned fastEmit_AArch64ISD_STRICT_FCMP_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8048 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
8049 | 0 | return 0; |
8050 | 0 | if ((Subtarget->hasFPARMv8())) { |
8051 | 0 | return fastEmitInst_rr(AArch64::FCMPSrr, &AArch64::FPR32RegClass, Op0, Op1); |
8052 | 0 | } |
8053 | 0 | return 0; |
8054 | 0 | } |
8055 | | |
8056 | 0 | unsigned fastEmit_AArch64ISD_STRICT_FCMP_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8057 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
8058 | 0 | return 0; |
8059 | 0 | if ((Subtarget->hasFPARMv8())) { |
8060 | 0 | return fastEmitInst_rr(AArch64::FCMPDrr, &AArch64::FPR64RegClass, Op0, Op1); |
8061 | 0 | } |
8062 | 0 | return 0; |
8063 | 0 | } |
8064 | | |
8065 | 0 | unsigned fastEmit_AArch64ISD_STRICT_FCMP_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
8066 | 0 | switch (VT.SimpleTy) { |
8067 | 0 | case MVT::f16: return fastEmit_AArch64ISD_STRICT_FCMP_MVT_f16_rr(RetVT, Op0, Op1); |
8068 | 0 | case MVT::f32: return fastEmit_AArch64ISD_STRICT_FCMP_MVT_f32_rr(RetVT, Op0, Op1); |
8069 | 0 | case MVT::f64: return fastEmit_AArch64ISD_STRICT_FCMP_MVT_f64_rr(RetVT, Op0, Op1); |
8070 | 0 | default: return 0; |
8071 | 0 | } |
8072 | 0 | } |
8073 | | |
8074 | | // FastEmit functions for AArch64ISD::STRICT_FCMPE. |
8075 | | |
8076 | 0 | unsigned fastEmit_AArch64ISD_STRICT_FCMPE_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8077 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
8078 | 0 | return 0; |
8079 | 0 | if ((Subtarget->hasFullFP16())) { |
8080 | 0 | return fastEmitInst_rr(AArch64::FCMPEHrr, &AArch64::FPR16RegClass, Op0, Op1); |
8081 | 0 | } |
8082 | 0 | return 0; |
8083 | 0 | } |
8084 | | |
8085 | 0 | unsigned fastEmit_AArch64ISD_STRICT_FCMPE_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8086 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
8087 | 0 | return 0; |
8088 | 0 | if ((Subtarget->hasFPARMv8())) { |
8089 | 0 | return fastEmitInst_rr(AArch64::FCMPESrr, &AArch64::FPR32RegClass, Op0, Op1); |
8090 | 0 | } |
8091 | 0 | return 0; |
8092 | 0 | } |
8093 | | |
8094 | 0 | unsigned fastEmit_AArch64ISD_STRICT_FCMPE_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8095 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
8096 | 0 | return 0; |
8097 | 0 | if ((Subtarget->hasFPARMv8())) { |
8098 | 0 | return fastEmitInst_rr(AArch64::FCMPEDrr, &AArch64::FPR64RegClass, Op0, Op1); |
8099 | 0 | } |
8100 | 0 | return 0; |
8101 | 0 | } |
8102 | | |
8103 | 0 | unsigned fastEmit_AArch64ISD_STRICT_FCMPE_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
8104 | 0 | switch (VT.SimpleTy) { |
8105 | 0 | case MVT::f16: return fastEmit_AArch64ISD_STRICT_FCMPE_MVT_f16_rr(RetVT, Op0, Op1); |
8106 | 0 | case MVT::f32: return fastEmit_AArch64ISD_STRICT_FCMPE_MVT_f32_rr(RetVT, Op0, Op1); |
8107 | 0 | case MVT::f64: return fastEmit_AArch64ISD_STRICT_FCMPE_MVT_f64_rr(RetVT, Op0, Op1); |
8108 | 0 | default: return 0; |
8109 | 0 | } |
8110 | 0 | } |
8111 | | |
8112 | | // FastEmit functions for AArch64ISD::TBL. |
8113 | | |
8114 | 0 | unsigned fastEmit_AArch64ISD_TBL_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8115 | 0 | if (RetVT.SimpleTy != MVT::nxv16i8) |
8116 | 0 | return 0; |
8117 | 0 | if ((Subtarget->hasSVEorSME())) { |
8118 | 0 | return fastEmitInst_rr(AArch64::TBL_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op1); |
8119 | 0 | } |
8120 | 0 | return 0; |
8121 | 0 | } |
8122 | | |
8123 | 0 | unsigned fastEmit_AArch64ISD_TBL_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8124 | 0 | if (RetVT.SimpleTy != MVT::nxv8i16) |
8125 | 0 | return 0; |
8126 | 0 | if ((Subtarget->hasSVEorSME())) { |
8127 | 0 | return fastEmitInst_rr(AArch64::TBL_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
8128 | 0 | } |
8129 | 0 | return 0; |
8130 | 0 | } |
8131 | | |
8132 | 0 | unsigned fastEmit_AArch64ISD_TBL_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8133 | 0 | if (RetVT.SimpleTy != MVT::nxv4i32) |
8134 | 0 | return 0; |
8135 | 0 | if ((Subtarget->hasSVEorSME())) { |
8136 | 0 | return fastEmitInst_rr(AArch64::TBL_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
8137 | 0 | } |
8138 | 0 | return 0; |
8139 | 0 | } |
8140 | | |
8141 | 0 | unsigned fastEmit_AArch64ISD_TBL_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8142 | 0 | if (RetVT.SimpleTy != MVT::nxv2i64) |
8143 | 0 | return 0; |
8144 | 0 | if ((Subtarget->hasSVEorSME())) { |
8145 | 0 | return fastEmitInst_rr(AArch64::TBL_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
8146 | 0 | } |
8147 | 0 | return 0; |
8148 | 0 | } |
8149 | | |
8150 | 0 | unsigned fastEmit_AArch64ISD_TBL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
8151 | 0 | switch (VT.SimpleTy) { |
8152 | 0 | case MVT::nxv16i8: return fastEmit_AArch64ISD_TBL_MVT_nxv16i8_rr(RetVT, Op0, Op1); |
8153 | 0 | case MVT::nxv8i16: return fastEmit_AArch64ISD_TBL_MVT_nxv8i16_rr(RetVT, Op0, Op1); |
8154 | 0 | case MVT::nxv4i32: return fastEmit_AArch64ISD_TBL_MVT_nxv4i32_rr(RetVT, Op0, Op1); |
8155 | 0 | case MVT::nxv2i64: return fastEmit_AArch64ISD_TBL_MVT_nxv2i64_rr(RetVT, Op0, Op1); |
8156 | 0 | default: return 0; |
8157 | 0 | } |
8158 | 0 | } |
8159 | | |
8160 | | // FastEmit functions for AArch64ISD::TRN1. |
8161 | | |
8162 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8163 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
8164 | 0 | return 0; |
8165 | 0 | if ((Subtarget->hasNEON())) { |
8166 | 0 | return fastEmitInst_rr(AArch64::TRN1v8i8, &AArch64::FPR64RegClass, Op0, Op1); |
8167 | 0 | } |
8168 | 0 | return 0; |
8169 | 0 | } |
8170 | | |
8171 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8172 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
8173 | 0 | return 0; |
8174 | 0 | if ((Subtarget->hasNEON())) { |
8175 | 0 | return fastEmitInst_rr(AArch64::TRN1v16i8, &AArch64::FPR128RegClass, Op0, Op1); |
8176 | 0 | } |
8177 | 0 | return 0; |
8178 | 0 | } |
8179 | | |
8180 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8181 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
8182 | 0 | return 0; |
8183 | 0 | if ((Subtarget->hasNEON())) { |
8184 | 0 | return fastEmitInst_rr(AArch64::TRN1v4i16, &AArch64::FPR64RegClass, Op0, Op1); |
8185 | 0 | } |
8186 | 0 | return 0; |
8187 | 0 | } |
8188 | | |
8189 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8190 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
8191 | 0 | return 0; |
8192 | 0 | if ((Subtarget->hasNEON())) { |
8193 | 0 | return fastEmitInst_rr(AArch64::TRN1v8i16, &AArch64::FPR128RegClass, Op0, Op1); |
8194 | 0 | } |
8195 | 0 | return 0; |
8196 | 0 | } |
8197 | | |
8198 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8199 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
8200 | 0 | return 0; |
8201 | 0 | if ((Subtarget->hasNEON())) { |
8202 | 0 | return fastEmitInst_rr(AArch64::TRN1v2i32, &AArch64::FPR64RegClass, Op0, Op1); |
8203 | 0 | } |
8204 | 0 | return 0; |
8205 | 0 | } |
8206 | | |
8207 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8208 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
8209 | 0 | return 0; |
8210 | 0 | if ((Subtarget->hasNEON())) { |
8211 | 0 | return fastEmitInst_rr(AArch64::TRN1v4i32, &AArch64::FPR128RegClass, Op0, Op1); |
8212 | 0 | } |
8213 | 0 | return 0; |
8214 | 0 | } |
8215 | | |
8216 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8217 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
8218 | 0 | return 0; |
8219 | 0 | if ((Subtarget->hasNEON())) { |
8220 | 0 | return fastEmitInst_rr(AArch64::TRN1v2i64, &AArch64::FPR128RegClass, Op0, Op1); |
8221 | 0 | } |
8222 | 0 | return 0; |
8223 | 0 | } |
8224 | | |
8225 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8226 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
8227 | 0 | return 0; |
8228 | 0 | if ((Subtarget->hasNEON())) { |
8229 | 0 | return fastEmitInst_rr(AArch64::TRN1v4i16, &AArch64::FPR64RegClass, Op0, Op1); |
8230 | 0 | } |
8231 | 0 | return 0; |
8232 | 0 | } |
8233 | | |
8234 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8235 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
8236 | 0 | return 0; |
8237 | 0 | if ((Subtarget->hasNEON())) { |
8238 | 0 | return fastEmitInst_rr(AArch64::TRN1v8i16, &AArch64::FPR128RegClass, Op0, Op1); |
8239 | 0 | } |
8240 | 0 | return 0; |
8241 | 0 | } |
8242 | | |
8243 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_v4bf16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8244 | 0 | if (RetVT.SimpleTy != MVT::v4bf16) |
8245 | 0 | return 0; |
8246 | 0 | if ((Subtarget->hasNEON())) { |
8247 | 0 | return fastEmitInst_rr(AArch64::TRN1v4i16, &AArch64::FPR64RegClass, Op0, Op1); |
8248 | 0 | } |
8249 | 0 | return 0; |
8250 | 0 | } |
8251 | | |
8252 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_v8bf16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8253 | 0 | if (RetVT.SimpleTy != MVT::v8bf16) |
8254 | 0 | return 0; |
8255 | 0 | if ((Subtarget->hasNEON())) { |
8256 | 0 | return fastEmitInst_rr(AArch64::TRN1v8i16, &AArch64::FPR128RegClass, Op0, Op1); |
8257 | 0 | } |
8258 | 0 | return 0; |
8259 | 0 | } |
8260 | | |
8261 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8262 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
8263 | 0 | return 0; |
8264 | 0 | if ((Subtarget->hasNEON())) { |
8265 | 0 | return fastEmitInst_rr(AArch64::TRN1v2i32, &AArch64::FPR64RegClass, Op0, Op1); |
8266 | 0 | } |
8267 | 0 | return 0; |
8268 | 0 | } |
8269 | | |
8270 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8271 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
8272 | 0 | return 0; |
8273 | 0 | if ((Subtarget->hasNEON())) { |
8274 | 0 | return fastEmitInst_rr(AArch64::TRN1v4i32, &AArch64::FPR128RegClass, Op0, Op1); |
8275 | 0 | } |
8276 | 0 | return 0; |
8277 | 0 | } |
8278 | | |
8279 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8280 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
8281 | 0 | return 0; |
8282 | 0 | if ((Subtarget->hasNEON())) { |
8283 | 0 | return fastEmitInst_rr(AArch64::TRN1v2i64, &AArch64::FPR128RegClass, Op0, Op1); |
8284 | 0 | } |
8285 | 0 | return 0; |
8286 | 0 | } |
8287 | | |
8288 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv2i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8289 | 0 | if (RetVT.SimpleTy != MVT::nxv2i1) |
8290 | 0 | return 0; |
8291 | 0 | if ((Subtarget->hasSVEorSME())) { |
8292 | 0 | return fastEmitInst_rr(AArch64::TRN1_PPP_D, &AArch64::PPRRegClass, Op0, Op1); |
8293 | 0 | } |
8294 | 0 | return 0; |
8295 | 0 | } |
8296 | | |
8297 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv4i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8298 | 0 | if (RetVT.SimpleTy != MVT::nxv4i1) |
8299 | 0 | return 0; |
8300 | 0 | if ((Subtarget->hasSVEorSME())) { |
8301 | 0 | return fastEmitInst_rr(AArch64::TRN1_PPP_S, &AArch64::PPRRegClass, Op0, Op1); |
8302 | 0 | } |
8303 | 0 | return 0; |
8304 | 0 | } |
8305 | | |
8306 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv8i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8307 | 0 | if (RetVT.SimpleTy != MVT::nxv8i1) |
8308 | 0 | return 0; |
8309 | 0 | if ((Subtarget->hasSVEorSME())) { |
8310 | 0 | return fastEmitInst_rr(AArch64::TRN1_PPP_H, &AArch64::PPRRegClass, Op0, Op1); |
8311 | 0 | } |
8312 | 0 | return 0; |
8313 | 0 | } |
8314 | | |
8315 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv16i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8316 | 0 | if (RetVT.SimpleTy != MVT::nxv16i1) |
8317 | 0 | return 0; |
8318 | 0 | if ((Subtarget->hasSVEorSME())) { |
8319 | 0 | return fastEmitInst_rr(AArch64::TRN1_PPP_B, &AArch64::PPRRegClass, Op0, Op1); |
8320 | 0 | } |
8321 | 0 | return 0; |
8322 | 0 | } |
8323 | | |
8324 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8325 | 0 | if (RetVT.SimpleTy != MVT::nxv16i8) |
8326 | 0 | return 0; |
8327 | 0 | if ((Subtarget->hasSVEorSME())) { |
8328 | 0 | return fastEmitInst_rr(AArch64::TRN1_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op1); |
8329 | 0 | } |
8330 | 0 | return 0; |
8331 | 0 | } |
8332 | | |
8333 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8334 | 0 | if (RetVT.SimpleTy != MVT::nxv8i16) |
8335 | 0 | return 0; |
8336 | 0 | if ((Subtarget->hasSVEorSME())) { |
8337 | 0 | return fastEmitInst_rr(AArch64::TRN1_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
8338 | 0 | } |
8339 | 0 | return 0; |
8340 | 0 | } |
8341 | | |
8342 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8343 | 0 | if (RetVT.SimpleTy != MVT::nxv4i32) |
8344 | 0 | return 0; |
8345 | 0 | if ((Subtarget->hasSVEorSME())) { |
8346 | 0 | return fastEmitInst_rr(AArch64::TRN1_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
8347 | 0 | } |
8348 | 0 | return 0; |
8349 | 0 | } |
8350 | | |
8351 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8352 | 0 | if (RetVT.SimpleTy != MVT::nxv2i64) |
8353 | 0 | return 0; |
8354 | 0 | if ((Subtarget->hasSVEorSME())) { |
8355 | 0 | return fastEmitInst_rr(AArch64::TRN1_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
8356 | 0 | } |
8357 | 0 | return 0; |
8358 | 0 | } |
8359 | | |
8360 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv2f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8361 | 0 | if (RetVT.SimpleTy != MVT::nxv2f16) |
8362 | 0 | return 0; |
8363 | 0 | if ((Subtarget->hasSVEorSME())) { |
8364 | 0 | return fastEmitInst_rr(AArch64::TRN1_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
8365 | 0 | } |
8366 | 0 | return 0; |
8367 | 0 | } |
8368 | | |
8369 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8370 | 0 | if (RetVT.SimpleTy != MVT::nxv4f16) |
8371 | 0 | return 0; |
8372 | 0 | if ((Subtarget->hasSVEorSME())) { |
8373 | 0 | return fastEmitInst_rr(AArch64::TRN1_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
8374 | 0 | } |
8375 | 0 | return 0; |
8376 | 0 | } |
8377 | | |
8378 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8379 | 0 | if (RetVT.SimpleTy != MVT::nxv8f16) |
8380 | 0 | return 0; |
8381 | 0 | if ((Subtarget->hasSVEorSME())) { |
8382 | 0 | return fastEmitInst_rr(AArch64::TRN1_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
8383 | 0 | } |
8384 | 0 | return 0; |
8385 | 0 | } |
8386 | | |
8387 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv8bf16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8388 | 0 | if (RetVT.SimpleTy != MVT::nxv8bf16) |
8389 | 0 | return 0; |
8390 | 0 | if ((Subtarget->hasSVEorSME())) { |
8391 | 0 | return fastEmitInst_rr(AArch64::TRN1_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
8392 | 0 | } |
8393 | 0 | return 0; |
8394 | 0 | } |
8395 | | |
8396 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8397 | 0 | if (RetVT.SimpleTy != MVT::nxv2f32) |
8398 | 0 | return 0; |
8399 | 0 | if ((Subtarget->hasSVEorSME())) { |
8400 | 0 | return fastEmitInst_rr(AArch64::TRN1_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
8401 | 0 | } |
8402 | 0 | return 0; |
8403 | 0 | } |
8404 | | |
8405 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8406 | 0 | if (RetVT.SimpleTy != MVT::nxv4f32) |
8407 | 0 | return 0; |
8408 | 0 | if ((Subtarget->hasSVEorSME())) { |
8409 | 0 | return fastEmitInst_rr(AArch64::TRN1_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
8410 | 0 | } |
8411 | 0 | return 0; |
8412 | 0 | } |
8413 | | |
8414 | 0 | unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8415 | 0 | if (RetVT.SimpleTy != MVT::nxv2f64) |
8416 | 0 | return 0; |
8417 | 0 | if ((Subtarget->hasSVEorSME())) { |
8418 | 0 | return fastEmitInst_rr(AArch64::TRN1_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
8419 | 0 | } |
8420 | 0 | return 0; |
8421 | 0 | } |
8422 | | |
8423 | 0 | unsigned fastEmit_AArch64ISD_TRN1_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
8424 | 0 | switch (VT.SimpleTy) { |
8425 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_TRN1_MVT_v8i8_rr(RetVT, Op0, Op1); |
8426 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_TRN1_MVT_v16i8_rr(RetVT, Op0, Op1); |
8427 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_TRN1_MVT_v4i16_rr(RetVT, Op0, Op1); |
8428 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_TRN1_MVT_v8i16_rr(RetVT, Op0, Op1); |
8429 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_TRN1_MVT_v2i32_rr(RetVT, Op0, Op1); |
8430 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_TRN1_MVT_v4i32_rr(RetVT, Op0, Op1); |
8431 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_TRN1_MVT_v2i64_rr(RetVT, Op0, Op1); |
8432 | 0 | case MVT::v4f16: return fastEmit_AArch64ISD_TRN1_MVT_v4f16_rr(RetVT, Op0, Op1); |
8433 | 0 | case MVT::v8f16: return fastEmit_AArch64ISD_TRN1_MVT_v8f16_rr(RetVT, Op0, Op1); |
8434 | 0 | case MVT::v4bf16: return fastEmit_AArch64ISD_TRN1_MVT_v4bf16_rr(RetVT, Op0, Op1); |
8435 | 0 | case MVT::v8bf16: return fastEmit_AArch64ISD_TRN1_MVT_v8bf16_rr(RetVT, Op0, Op1); |
8436 | 0 | case MVT::v2f32: return fastEmit_AArch64ISD_TRN1_MVT_v2f32_rr(RetVT, Op0, Op1); |
8437 | 0 | case MVT::v4f32: return fastEmit_AArch64ISD_TRN1_MVT_v4f32_rr(RetVT, Op0, Op1); |
8438 | 0 | case MVT::v2f64: return fastEmit_AArch64ISD_TRN1_MVT_v2f64_rr(RetVT, Op0, Op1); |
8439 | 0 | case MVT::nxv2i1: return fastEmit_AArch64ISD_TRN1_MVT_nxv2i1_rr(RetVT, Op0, Op1); |
8440 | 0 | case MVT::nxv4i1: return fastEmit_AArch64ISD_TRN1_MVT_nxv4i1_rr(RetVT, Op0, Op1); |
8441 | 0 | case MVT::nxv8i1: return fastEmit_AArch64ISD_TRN1_MVT_nxv8i1_rr(RetVT, Op0, Op1); |
8442 | 0 | case MVT::nxv16i1: return fastEmit_AArch64ISD_TRN1_MVT_nxv16i1_rr(RetVT, Op0, Op1); |
8443 | 0 | case MVT::nxv16i8: return fastEmit_AArch64ISD_TRN1_MVT_nxv16i8_rr(RetVT, Op0, Op1); |
8444 | 0 | case MVT::nxv8i16: return fastEmit_AArch64ISD_TRN1_MVT_nxv8i16_rr(RetVT, Op0, Op1); |
8445 | 0 | case MVT::nxv4i32: return fastEmit_AArch64ISD_TRN1_MVT_nxv4i32_rr(RetVT, Op0, Op1); |
8446 | 0 | case MVT::nxv2i64: return fastEmit_AArch64ISD_TRN1_MVT_nxv2i64_rr(RetVT, Op0, Op1); |
8447 | 0 | case MVT::nxv2f16: return fastEmit_AArch64ISD_TRN1_MVT_nxv2f16_rr(RetVT, Op0, Op1); |
8448 | 0 | case MVT::nxv4f16: return fastEmit_AArch64ISD_TRN1_MVT_nxv4f16_rr(RetVT, Op0, Op1); |
8449 | 0 | case MVT::nxv8f16: return fastEmit_AArch64ISD_TRN1_MVT_nxv8f16_rr(RetVT, Op0, Op1); |
8450 | 0 | case MVT::nxv8bf16: return fastEmit_AArch64ISD_TRN1_MVT_nxv8bf16_rr(RetVT, Op0, Op1); |
8451 | 0 | case MVT::nxv2f32: return fastEmit_AArch64ISD_TRN1_MVT_nxv2f32_rr(RetVT, Op0, Op1); |
8452 | 0 | case MVT::nxv4f32: return fastEmit_AArch64ISD_TRN1_MVT_nxv4f32_rr(RetVT, Op0, Op1); |
8453 | 0 | case MVT::nxv2f64: return fastEmit_AArch64ISD_TRN1_MVT_nxv2f64_rr(RetVT, Op0, Op1); |
8454 | 0 | default: return 0; |
8455 | 0 | } |
8456 | 0 | } |
8457 | | |
8458 | | // FastEmit functions for AArch64ISD::TRN2. |
8459 | | |
8460 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8461 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
8462 | 0 | return 0; |
8463 | 0 | if ((Subtarget->hasNEON())) { |
8464 | 0 | return fastEmitInst_rr(AArch64::TRN2v8i8, &AArch64::FPR64RegClass, Op0, Op1); |
8465 | 0 | } |
8466 | 0 | return 0; |
8467 | 0 | } |
8468 | | |
8469 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8470 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
8471 | 0 | return 0; |
8472 | 0 | if ((Subtarget->hasNEON())) { |
8473 | 0 | return fastEmitInst_rr(AArch64::TRN2v16i8, &AArch64::FPR128RegClass, Op0, Op1); |
8474 | 0 | } |
8475 | 0 | return 0; |
8476 | 0 | } |
8477 | | |
8478 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8479 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
8480 | 0 | return 0; |
8481 | 0 | if ((Subtarget->hasNEON())) { |
8482 | 0 | return fastEmitInst_rr(AArch64::TRN2v4i16, &AArch64::FPR64RegClass, Op0, Op1); |
8483 | 0 | } |
8484 | 0 | return 0; |
8485 | 0 | } |
8486 | | |
8487 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8488 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
8489 | 0 | return 0; |
8490 | 0 | if ((Subtarget->hasNEON())) { |
8491 | 0 | return fastEmitInst_rr(AArch64::TRN2v8i16, &AArch64::FPR128RegClass, Op0, Op1); |
8492 | 0 | } |
8493 | 0 | return 0; |
8494 | 0 | } |
8495 | | |
8496 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8497 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
8498 | 0 | return 0; |
8499 | 0 | if ((Subtarget->hasNEON())) { |
8500 | 0 | return fastEmitInst_rr(AArch64::TRN2v2i32, &AArch64::FPR64RegClass, Op0, Op1); |
8501 | 0 | } |
8502 | 0 | return 0; |
8503 | 0 | } |
8504 | | |
8505 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8506 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
8507 | 0 | return 0; |
8508 | 0 | if ((Subtarget->hasNEON())) { |
8509 | 0 | return fastEmitInst_rr(AArch64::TRN2v4i32, &AArch64::FPR128RegClass, Op0, Op1); |
8510 | 0 | } |
8511 | 0 | return 0; |
8512 | 0 | } |
8513 | | |
8514 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8515 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
8516 | 0 | return 0; |
8517 | 0 | if ((Subtarget->hasNEON())) { |
8518 | 0 | return fastEmitInst_rr(AArch64::TRN2v2i64, &AArch64::FPR128RegClass, Op0, Op1); |
8519 | 0 | } |
8520 | 0 | return 0; |
8521 | 0 | } |
8522 | | |
8523 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8524 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
8525 | 0 | return 0; |
8526 | 0 | if ((Subtarget->hasNEON())) { |
8527 | 0 | return fastEmitInst_rr(AArch64::TRN2v4i16, &AArch64::FPR64RegClass, Op0, Op1); |
8528 | 0 | } |
8529 | 0 | return 0; |
8530 | 0 | } |
8531 | | |
8532 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8533 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
8534 | 0 | return 0; |
8535 | 0 | if ((Subtarget->hasNEON())) { |
8536 | 0 | return fastEmitInst_rr(AArch64::TRN2v8i16, &AArch64::FPR128RegClass, Op0, Op1); |
8537 | 0 | } |
8538 | 0 | return 0; |
8539 | 0 | } |
8540 | | |
8541 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_v4bf16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8542 | 0 | if (RetVT.SimpleTy != MVT::v4bf16) |
8543 | 0 | return 0; |
8544 | 0 | if ((Subtarget->hasNEON())) { |
8545 | 0 | return fastEmitInst_rr(AArch64::TRN2v4i16, &AArch64::FPR64RegClass, Op0, Op1); |
8546 | 0 | } |
8547 | 0 | return 0; |
8548 | 0 | } |
8549 | | |
8550 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_v8bf16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8551 | 0 | if (RetVT.SimpleTy != MVT::v8bf16) |
8552 | 0 | return 0; |
8553 | 0 | if ((Subtarget->hasNEON())) { |
8554 | 0 | return fastEmitInst_rr(AArch64::TRN2v8i16, &AArch64::FPR128RegClass, Op0, Op1); |
8555 | 0 | } |
8556 | 0 | return 0; |
8557 | 0 | } |
8558 | | |
8559 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8560 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
8561 | 0 | return 0; |
8562 | 0 | if ((Subtarget->hasNEON())) { |
8563 | 0 | return fastEmitInst_rr(AArch64::TRN2v2i32, &AArch64::FPR64RegClass, Op0, Op1); |
8564 | 0 | } |
8565 | 0 | return 0; |
8566 | 0 | } |
8567 | | |
8568 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8569 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
8570 | 0 | return 0; |
8571 | 0 | if ((Subtarget->hasNEON())) { |
8572 | 0 | return fastEmitInst_rr(AArch64::TRN2v4i32, &AArch64::FPR128RegClass, Op0, Op1); |
8573 | 0 | } |
8574 | 0 | return 0; |
8575 | 0 | } |
8576 | | |
8577 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8578 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
8579 | 0 | return 0; |
8580 | 0 | if ((Subtarget->hasNEON())) { |
8581 | 0 | return fastEmitInst_rr(AArch64::TRN2v2i64, &AArch64::FPR128RegClass, Op0, Op1); |
8582 | 0 | } |
8583 | 0 | return 0; |
8584 | 0 | } |
8585 | | |
8586 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv2i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8587 | 0 | if (RetVT.SimpleTy != MVT::nxv2i1) |
8588 | 0 | return 0; |
8589 | 0 | if ((Subtarget->hasSVEorSME())) { |
8590 | 0 | return fastEmitInst_rr(AArch64::TRN2_PPP_D, &AArch64::PPRRegClass, Op0, Op1); |
8591 | 0 | } |
8592 | 0 | return 0; |
8593 | 0 | } |
8594 | | |
8595 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv4i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8596 | 0 | if (RetVT.SimpleTy != MVT::nxv4i1) |
8597 | 0 | return 0; |
8598 | 0 | if ((Subtarget->hasSVEorSME())) { |
8599 | 0 | return fastEmitInst_rr(AArch64::TRN2_PPP_S, &AArch64::PPRRegClass, Op0, Op1); |
8600 | 0 | } |
8601 | 0 | return 0; |
8602 | 0 | } |
8603 | | |
8604 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv8i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8605 | 0 | if (RetVT.SimpleTy != MVT::nxv8i1) |
8606 | 0 | return 0; |
8607 | 0 | if ((Subtarget->hasSVEorSME())) { |
8608 | 0 | return fastEmitInst_rr(AArch64::TRN2_PPP_H, &AArch64::PPRRegClass, Op0, Op1); |
8609 | 0 | } |
8610 | 0 | return 0; |
8611 | 0 | } |
8612 | | |
8613 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv16i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8614 | 0 | if (RetVT.SimpleTy != MVT::nxv16i1) |
8615 | 0 | return 0; |
8616 | 0 | if ((Subtarget->hasSVEorSME())) { |
8617 | 0 | return fastEmitInst_rr(AArch64::TRN2_PPP_B, &AArch64::PPRRegClass, Op0, Op1); |
8618 | 0 | } |
8619 | 0 | return 0; |
8620 | 0 | } |
8621 | | |
8622 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8623 | 0 | if (RetVT.SimpleTy != MVT::nxv16i8) |
8624 | 0 | return 0; |
8625 | 0 | if ((Subtarget->hasSVEorSME())) { |
8626 | 0 | return fastEmitInst_rr(AArch64::TRN2_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op1); |
8627 | 0 | } |
8628 | 0 | return 0; |
8629 | 0 | } |
8630 | | |
8631 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8632 | 0 | if (RetVT.SimpleTy != MVT::nxv8i16) |
8633 | 0 | return 0; |
8634 | 0 | if ((Subtarget->hasSVEorSME())) { |
8635 | 0 | return fastEmitInst_rr(AArch64::TRN2_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
8636 | 0 | } |
8637 | 0 | return 0; |
8638 | 0 | } |
8639 | | |
8640 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8641 | 0 | if (RetVT.SimpleTy != MVT::nxv4i32) |
8642 | 0 | return 0; |
8643 | 0 | if ((Subtarget->hasSVEorSME())) { |
8644 | 0 | return fastEmitInst_rr(AArch64::TRN2_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
8645 | 0 | } |
8646 | 0 | return 0; |
8647 | 0 | } |
8648 | | |
8649 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8650 | 0 | if (RetVT.SimpleTy != MVT::nxv2i64) |
8651 | 0 | return 0; |
8652 | 0 | if ((Subtarget->hasSVEorSME())) { |
8653 | 0 | return fastEmitInst_rr(AArch64::TRN2_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
8654 | 0 | } |
8655 | 0 | return 0; |
8656 | 0 | } |
8657 | | |
8658 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv2f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8659 | 0 | if (RetVT.SimpleTy != MVT::nxv2f16) |
8660 | 0 | return 0; |
8661 | 0 | if ((Subtarget->hasSVEorSME())) { |
8662 | 0 | return fastEmitInst_rr(AArch64::TRN2_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
8663 | 0 | } |
8664 | 0 | return 0; |
8665 | 0 | } |
8666 | | |
8667 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8668 | 0 | if (RetVT.SimpleTy != MVT::nxv4f16) |
8669 | 0 | return 0; |
8670 | 0 | if ((Subtarget->hasSVEorSME())) { |
8671 | 0 | return fastEmitInst_rr(AArch64::TRN2_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
8672 | 0 | } |
8673 | 0 | return 0; |
8674 | 0 | } |
8675 | | |
8676 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8677 | 0 | if (RetVT.SimpleTy != MVT::nxv8f16) |
8678 | 0 | return 0; |
8679 | 0 | if ((Subtarget->hasSVEorSME())) { |
8680 | 0 | return fastEmitInst_rr(AArch64::TRN2_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
8681 | 0 | } |
8682 | 0 | return 0; |
8683 | 0 | } |
8684 | | |
8685 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv8bf16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8686 | 0 | if (RetVT.SimpleTy != MVT::nxv8bf16) |
8687 | 0 | return 0; |
8688 | 0 | if ((Subtarget->hasSVEorSME())) { |
8689 | 0 | return fastEmitInst_rr(AArch64::TRN2_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
8690 | 0 | } |
8691 | 0 | return 0; |
8692 | 0 | } |
8693 | | |
8694 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8695 | 0 | if (RetVT.SimpleTy != MVT::nxv2f32) |
8696 | 0 | return 0; |
8697 | 0 | if ((Subtarget->hasSVEorSME())) { |
8698 | 0 | return fastEmitInst_rr(AArch64::TRN2_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
8699 | 0 | } |
8700 | 0 | return 0; |
8701 | 0 | } |
8702 | | |
8703 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8704 | 0 | if (RetVT.SimpleTy != MVT::nxv4f32) |
8705 | 0 | return 0; |
8706 | 0 | if ((Subtarget->hasSVEorSME())) { |
8707 | 0 | return fastEmitInst_rr(AArch64::TRN2_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
8708 | 0 | } |
8709 | 0 | return 0; |
8710 | 0 | } |
8711 | | |
8712 | 0 | unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8713 | 0 | if (RetVT.SimpleTy != MVT::nxv2f64) |
8714 | 0 | return 0; |
8715 | 0 | if ((Subtarget->hasSVEorSME())) { |
8716 | 0 | return fastEmitInst_rr(AArch64::TRN2_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
8717 | 0 | } |
8718 | 0 | return 0; |
8719 | 0 | } |
8720 | | |
8721 | 0 | unsigned fastEmit_AArch64ISD_TRN2_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
8722 | 0 | switch (VT.SimpleTy) { |
8723 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_TRN2_MVT_v8i8_rr(RetVT, Op0, Op1); |
8724 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_TRN2_MVT_v16i8_rr(RetVT, Op0, Op1); |
8725 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_TRN2_MVT_v4i16_rr(RetVT, Op0, Op1); |
8726 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_TRN2_MVT_v8i16_rr(RetVT, Op0, Op1); |
8727 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_TRN2_MVT_v2i32_rr(RetVT, Op0, Op1); |
8728 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_TRN2_MVT_v4i32_rr(RetVT, Op0, Op1); |
8729 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_TRN2_MVT_v2i64_rr(RetVT, Op0, Op1); |
8730 | 0 | case MVT::v4f16: return fastEmit_AArch64ISD_TRN2_MVT_v4f16_rr(RetVT, Op0, Op1); |
8731 | 0 | case MVT::v8f16: return fastEmit_AArch64ISD_TRN2_MVT_v8f16_rr(RetVT, Op0, Op1); |
8732 | 0 | case MVT::v4bf16: return fastEmit_AArch64ISD_TRN2_MVT_v4bf16_rr(RetVT, Op0, Op1); |
8733 | 0 | case MVT::v8bf16: return fastEmit_AArch64ISD_TRN2_MVT_v8bf16_rr(RetVT, Op0, Op1); |
8734 | 0 | case MVT::v2f32: return fastEmit_AArch64ISD_TRN2_MVT_v2f32_rr(RetVT, Op0, Op1); |
8735 | 0 | case MVT::v4f32: return fastEmit_AArch64ISD_TRN2_MVT_v4f32_rr(RetVT, Op0, Op1); |
8736 | 0 | case MVT::v2f64: return fastEmit_AArch64ISD_TRN2_MVT_v2f64_rr(RetVT, Op0, Op1); |
8737 | 0 | case MVT::nxv2i1: return fastEmit_AArch64ISD_TRN2_MVT_nxv2i1_rr(RetVT, Op0, Op1); |
8738 | 0 | case MVT::nxv4i1: return fastEmit_AArch64ISD_TRN2_MVT_nxv4i1_rr(RetVT, Op0, Op1); |
8739 | 0 | case MVT::nxv8i1: return fastEmit_AArch64ISD_TRN2_MVT_nxv8i1_rr(RetVT, Op0, Op1); |
8740 | 0 | case MVT::nxv16i1: return fastEmit_AArch64ISD_TRN2_MVT_nxv16i1_rr(RetVT, Op0, Op1); |
8741 | 0 | case MVT::nxv16i8: return fastEmit_AArch64ISD_TRN2_MVT_nxv16i8_rr(RetVT, Op0, Op1); |
8742 | 0 | case MVT::nxv8i16: return fastEmit_AArch64ISD_TRN2_MVT_nxv8i16_rr(RetVT, Op0, Op1); |
8743 | 0 | case MVT::nxv4i32: return fastEmit_AArch64ISD_TRN2_MVT_nxv4i32_rr(RetVT, Op0, Op1); |
8744 | 0 | case MVT::nxv2i64: return fastEmit_AArch64ISD_TRN2_MVT_nxv2i64_rr(RetVT, Op0, Op1); |
8745 | 0 | case MVT::nxv2f16: return fastEmit_AArch64ISD_TRN2_MVT_nxv2f16_rr(RetVT, Op0, Op1); |
8746 | 0 | case MVT::nxv4f16: return fastEmit_AArch64ISD_TRN2_MVT_nxv4f16_rr(RetVT, Op0, Op1); |
8747 | 0 | case MVT::nxv8f16: return fastEmit_AArch64ISD_TRN2_MVT_nxv8f16_rr(RetVT, Op0, Op1); |
8748 | 0 | case MVT::nxv8bf16: return fastEmit_AArch64ISD_TRN2_MVT_nxv8bf16_rr(RetVT, Op0, Op1); |
8749 | 0 | case MVT::nxv2f32: return fastEmit_AArch64ISD_TRN2_MVT_nxv2f32_rr(RetVT, Op0, Op1); |
8750 | 0 | case MVT::nxv4f32: return fastEmit_AArch64ISD_TRN2_MVT_nxv4f32_rr(RetVT, Op0, Op1); |
8751 | 0 | case MVT::nxv2f64: return fastEmit_AArch64ISD_TRN2_MVT_nxv2f64_rr(RetVT, Op0, Op1); |
8752 | 0 | default: return 0; |
8753 | 0 | } |
8754 | 0 | } |
8755 | | |
8756 | | // FastEmit functions for AArch64ISD::UMULL. |
8757 | | |
8758 | 0 | unsigned fastEmit_AArch64ISD_UMULL_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8759 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
8760 | 0 | return 0; |
8761 | 0 | if ((Subtarget->hasNEON())) { |
8762 | 0 | return fastEmitInst_rr(AArch64::UMULLv8i8_v8i16, &AArch64::FPR128RegClass, Op0, Op1); |
8763 | 0 | } |
8764 | 0 | return 0; |
8765 | 0 | } |
8766 | | |
8767 | 0 | unsigned fastEmit_AArch64ISD_UMULL_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8768 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
8769 | 0 | return 0; |
8770 | 0 | if ((Subtarget->hasNEON())) { |
8771 | 0 | return fastEmitInst_rr(AArch64::UMULLv4i16_v4i32, &AArch64::FPR128RegClass, Op0, Op1); |
8772 | 0 | } |
8773 | 0 | return 0; |
8774 | 0 | } |
8775 | | |
8776 | 0 | unsigned fastEmit_AArch64ISD_UMULL_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8777 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
8778 | 0 | return 0; |
8779 | 0 | if ((Subtarget->hasNEON())) { |
8780 | 0 | return fastEmitInst_rr(AArch64::UMULLv2i32_v2i64, &AArch64::FPR128RegClass, Op0, Op1); |
8781 | 0 | } |
8782 | 0 | return 0; |
8783 | 0 | } |
8784 | | |
8785 | 0 | unsigned fastEmit_AArch64ISD_UMULL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
8786 | 0 | switch (VT.SimpleTy) { |
8787 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_UMULL_MVT_v8i8_rr(RetVT, Op0, Op1); |
8788 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_UMULL_MVT_v4i16_rr(RetVT, Op0, Op1); |
8789 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_UMULL_MVT_v2i32_rr(RetVT, Op0, Op1); |
8790 | 0 | default: return 0; |
8791 | 0 | } |
8792 | 0 | } |
8793 | | |
8794 | | // FastEmit functions for AArch64ISD::UZP1. |
8795 | | |
8796 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8797 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
8798 | 0 | return 0; |
8799 | 0 | if ((Subtarget->hasNEON())) { |
8800 | 0 | return fastEmitInst_rr(AArch64::UZP1v8i8, &AArch64::FPR64RegClass, Op0, Op1); |
8801 | 0 | } |
8802 | 0 | return 0; |
8803 | 0 | } |
8804 | | |
8805 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8806 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
8807 | 0 | return 0; |
8808 | 0 | if ((Subtarget->hasNEON())) { |
8809 | 0 | return fastEmitInst_rr(AArch64::UZP1v16i8, &AArch64::FPR128RegClass, Op0, Op1); |
8810 | 0 | } |
8811 | 0 | return 0; |
8812 | 0 | } |
8813 | | |
8814 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8815 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
8816 | 0 | return 0; |
8817 | 0 | if ((Subtarget->hasNEON())) { |
8818 | 0 | return fastEmitInst_rr(AArch64::UZP1v4i16, &AArch64::FPR64RegClass, Op0, Op1); |
8819 | 0 | } |
8820 | 0 | return 0; |
8821 | 0 | } |
8822 | | |
8823 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8824 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
8825 | 0 | return 0; |
8826 | 0 | if ((Subtarget->hasNEON())) { |
8827 | 0 | return fastEmitInst_rr(AArch64::UZP1v8i16, &AArch64::FPR128RegClass, Op0, Op1); |
8828 | 0 | } |
8829 | 0 | return 0; |
8830 | 0 | } |
8831 | | |
8832 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8833 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
8834 | 0 | return 0; |
8835 | 0 | if ((Subtarget->hasNEON())) { |
8836 | 0 | return fastEmitInst_rr(AArch64::UZP1v2i32, &AArch64::FPR64RegClass, Op0, Op1); |
8837 | 0 | } |
8838 | 0 | return 0; |
8839 | 0 | } |
8840 | | |
8841 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8842 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
8843 | 0 | return 0; |
8844 | 0 | if ((Subtarget->hasNEON())) { |
8845 | 0 | return fastEmitInst_rr(AArch64::UZP1v4i32, &AArch64::FPR128RegClass, Op0, Op1); |
8846 | 0 | } |
8847 | 0 | return 0; |
8848 | 0 | } |
8849 | | |
8850 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8851 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
8852 | 0 | return 0; |
8853 | 0 | if ((Subtarget->hasNEON())) { |
8854 | 0 | return fastEmitInst_rr(AArch64::UZP1v2i64, &AArch64::FPR128RegClass, Op0, Op1); |
8855 | 0 | } |
8856 | 0 | return 0; |
8857 | 0 | } |
8858 | | |
8859 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8860 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
8861 | 0 | return 0; |
8862 | 0 | if ((Subtarget->hasNEON())) { |
8863 | 0 | return fastEmitInst_rr(AArch64::UZP1v4i16, &AArch64::FPR64RegClass, Op0, Op1); |
8864 | 0 | } |
8865 | 0 | return 0; |
8866 | 0 | } |
8867 | | |
8868 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8869 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
8870 | 0 | return 0; |
8871 | 0 | if ((Subtarget->hasNEON())) { |
8872 | 0 | return fastEmitInst_rr(AArch64::UZP1v8i16, &AArch64::FPR128RegClass, Op0, Op1); |
8873 | 0 | } |
8874 | 0 | return 0; |
8875 | 0 | } |
8876 | | |
8877 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_v4bf16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8878 | 0 | if (RetVT.SimpleTy != MVT::v4bf16) |
8879 | 0 | return 0; |
8880 | 0 | if ((Subtarget->hasNEON())) { |
8881 | 0 | return fastEmitInst_rr(AArch64::UZP1v4i16, &AArch64::FPR64RegClass, Op0, Op1); |
8882 | 0 | } |
8883 | 0 | return 0; |
8884 | 0 | } |
8885 | | |
8886 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_v8bf16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8887 | 0 | if (RetVT.SimpleTy != MVT::v8bf16) |
8888 | 0 | return 0; |
8889 | 0 | if ((Subtarget->hasNEON())) { |
8890 | 0 | return fastEmitInst_rr(AArch64::UZP1v8i16, &AArch64::FPR128RegClass, Op0, Op1); |
8891 | 0 | } |
8892 | 0 | return 0; |
8893 | 0 | } |
8894 | | |
8895 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8896 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
8897 | 0 | return 0; |
8898 | 0 | if ((Subtarget->hasNEON())) { |
8899 | 0 | return fastEmitInst_rr(AArch64::UZP1v2i32, &AArch64::FPR64RegClass, Op0, Op1); |
8900 | 0 | } |
8901 | 0 | return 0; |
8902 | 0 | } |
8903 | | |
8904 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8905 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
8906 | 0 | return 0; |
8907 | 0 | if ((Subtarget->hasNEON())) { |
8908 | 0 | return fastEmitInst_rr(AArch64::UZP1v4i32, &AArch64::FPR128RegClass, Op0, Op1); |
8909 | 0 | } |
8910 | 0 | return 0; |
8911 | 0 | } |
8912 | | |
8913 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8914 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
8915 | 0 | return 0; |
8916 | 0 | if ((Subtarget->hasNEON())) { |
8917 | 0 | return fastEmitInst_rr(AArch64::UZP1v2i64, &AArch64::FPR128RegClass, Op0, Op1); |
8918 | 0 | } |
8919 | 0 | return 0; |
8920 | 0 | } |
8921 | | |
8922 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv2i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8923 | 0 | if (RetVT.SimpleTy != MVT::nxv2i1) |
8924 | 0 | return 0; |
8925 | 0 | if ((Subtarget->hasSVEorSME())) { |
8926 | 0 | return fastEmitInst_rr(AArch64::UZP1_PPP_D, &AArch64::PPRRegClass, Op0, Op1); |
8927 | 0 | } |
8928 | 0 | return 0; |
8929 | 0 | } |
8930 | | |
8931 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv4i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8932 | 0 | if (RetVT.SimpleTy != MVT::nxv4i1) |
8933 | 0 | return 0; |
8934 | 0 | if ((Subtarget->hasSVEorSME())) { |
8935 | 0 | return fastEmitInst_rr(AArch64::UZP1_PPP_S, &AArch64::PPRRegClass, Op0, Op1); |
8936 | 0 | } |
8937 | 0 | return 0; |
8938 | 0 | } |
8939 | | |
8940 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv8i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8941 | 0 | if (RetVT.SimpleTy != MVT::nxv8i1) |
8942 | 0 | return 0; |
8943 | 0 | if ((Subtarget->hasSVEorSME())) { |
8944 | 0 | return fastEmitInst_rr(AArch64::UZP1_PPP_H, &AArch64::PPRRegClass, Op0, Op1); |
8945 | 0 | } |
8946 | 0 | return 0; |
8947 | 0 | } |
8948 | | |
8949 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv16i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8950 | 0 | if (RetVT.SimpleTy != MVT::nxv16i1) |
8951 | 0 | return 0; |
8952 | 0 | if ((Subtarget->hasSVEorSME())) { |
8953 | 0 | return fastEmitInst_rr(AArch64::UZP1_PPP_B, &AArch64::PPRRegClass, Op0, Op1); |
8954 | 0 | } |
8955 | 0 | return 0; |
8956 | 0 | } |
8957 | | |
8958 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8959 | 0 | if (RetVT.SimpleTy != MVT::nxv16i8) |
8960 | 0 | return 0; |
8961 | 0 | if ((Subtarget->hasSVEorSME())) { |
8962 | 0 | return fastEmitInst_rr(AArch64::UZP1_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op1); |
8963 | 0 | } |
8964 | 0 | return 0; |
8965 | 0 | } |
8966 | | |
8967 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8968 | 0 | if (RetVT.SimpleTy != MVT::nxv8i16) |
8969 | 0 | return 0; |
8970 | 0 | if ((Subtarget->hasSVEorSME())) { |
8971 | 0 | return fastEmitInst_rr(AArch64::UZP1_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
8972 | 0 | } |
8973 | 0 | return 0; |
8974 | 0 | } |
8975 | | |
8976 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8977 | 0 | if (RetVT.SimpleTy != MVT::nxv4i32) |
8978 | 0 | return 0; |
8979 | 0 | if ((Subtarget->hasSVEorSME())) { |
8980 | 0 | return fastEmitInst_rr(AArch64::UZP1_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
8981 | 0 | } |
8982 | 0 | return 0; |
8983 | 0 | } |
8984 | | |
8985 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8986 | 0 | if (RetVT.SimpleTy != MVT::nxv2i64) |
8987 | 0 | return 0; |
8988 | 0 | if ((Subtarget->hasSVEorSME())) { |
8989 | 0 | return fastEmitInst_rr(AArch64::UZP1_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
8990 | 0 | } |
8991 | 0 | return 0; |
8992 | 0 | } |
8993 | | |
8994 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv2f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
8995 | 0 | if (RetVT.SimpleTy != MVT::nxv2f16) |
8996 | 0 | return 0; |
8997 | 0 | if ((Subtarget->hasSVEorSME())) { |
8998 | 0 | return fastEmitInst_rr(AArch64::UZP1_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
8999 | 0 | } |
9000 | 0 | return 0; |
9001 | 0 | } |
9002 | | |
9003 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9004 | 0 | if (RetVT.SimpleTy != MVT::nxv4f16) |
9005 | 0 | return 0; |
9006 | 0 | if ((Subtarget->hasSVEorSME())) { |
9007 | 0 | return fastEmitInst_rr(AArch64::UZP1_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
9008 | 0 | } |
9009 | 0 | return 0; |
9010 | 0 | } |
9011 | | |
9012 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9013 | 0 | if (RetVT.SimpleTy != MVT::nxv8f16) |
9014 | 0 | return 0; |
9015 | 0 | if ((Subtarget->hasSVEorSME())) { |
9016 | 0 | return fastEmitInst_rr(AArch64::UZP1_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
9017 | 0 | } |
9018 | 0 | return 0; |
9019 | 0 | } |
9020 | | |
9021 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv8bf16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9022 | 0 | if (RetVT.SimpleTy != MVT::nxv8bf16) |
9023 | 0 | return 0; |
9024 | 0 | if ((Subtarget->hasSVEorSME())) { |
9025 | 0 | return fastEmitInst_rr(AArch64::UZP1_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
9026 | 0 | } |
9027 | 0 | return 0; |
9028 | 0 | } |
9029 | | |
9030 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9031 | 0 | if (RetVT.SimpleTy != MVT::nxv2f32) |
9032 | 0 | return 0; |
9033 | 0 | if ((Subtarget->hasSVEorSME())) { |
9034 | 0 | return fastEmitInst_rr(AArch64::UZP1_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
9035 | 0 | } |
9036 | 0 | return 0; |
9037 | 0 | } |
9038 | | |
9039 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9040 | 0 | if (RetVT.SimpleTy != MVT::nxv4f32) |
9041 | 0 | return 0; |
9042 | 0 | if ((Subtarget->hasSVEorSME())) { |
9043 | 0 | return fastEmitInst_rr(AArch64::UZP1_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
9044 | 0 | } |
9045 | 0 | return 0; |
9046 | 0 | } |
9047 | | |
9048 | 0 | unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9049 | 0 | if (RetVT.SimpleTy != MVT::nxv2f64) |
9050 | 0 | return 0; |
9051 | 0 | if ((Subtarget->hasSVEorSME())) { |
9052 | 0 | return fastEmitInst_rr(AArch64::UZP1_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
9053 | 0 | } |
9054 | 0 | return 0; |
9055 | 0 | } |
9056 | | |
9057 | 0 | unsigned fastEmit_AArch64ISD_UZP1_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
9058 | 0 | switch (VT.SimpleTy) { |
9059 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_UZP1_MVT_v8i8_rr(RetVT, Op0, Op1); |
9060 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_UZP1_MVT_v16i8_rr(RetVT, Op0, Op1); |
9061 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_UZP1_MVT_v4i16_rr(RetVT, Op0, Op1); |
9062 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_UZP1_MVT_v8i16_rr(RetVT, Op0, Op1); |
9063 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_UZP1_MVT_v2i32_rr(RetVT, Op0, Op1); |
9064 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_UZP1_MVT_v4i32_rr(RetVT, Op0, Op1); |
9065 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_UZP1_MVT_v2i64_rr(RetVT, Op0, Op1); |
9066 | 0 | case MVT::v4f16: return fastEmit_AArch64ISD_UZP1_MVT_v4f16_rr(RetVT, Op0, Op1); |
9067 | 0 | case MVT::v8f16: return fastEmit_AArch64ISD_UZP1_MVT_v8f16_rr(RetVT, Op0, Op1); |
9068 | 0 | case MVT::v4bf16: return fastEmit_AArch64ISD_UZP1_MVT_v4bf16_rr(RetVT, Op0, Op1); |
9069 | 0 | case MVT::v8bf16: return fastEmit_AArch64ISD_UZP1_MVT_v8bf16_rr(RetVT, Op0, Op1); |
9070 | 0 | case MVT::v2f32: return fastEmit_AArch64ISD_UZP1_MVT_v2f32_rr(RetVT, Op0, Op1); |
9071 | 0 | case MVT::v4f32: return fastEmit_AArch64ISD_UZP1_MVT_v4f32_rr(RetVT, Op0, Op1); |
9072 | 0 | case MVT::v2f64: return fastEmit_AArch64ISD_UZP1_MVT_v2f64_rr(RetVT, Op0, Op1); |
9073 | 0 | case MVT::nxv2i1: return fastEmit_AArch64ISD_UZP1_MVT_nxv2i1_rr(RetVT, Op0, Op1); |
9074 | 0 | case MVT::nxv4i1: return fastEmit_AArch64ISD_UZP1_MVT_nxv4i1_rr(RetVT, Op0, Op1); |
9075 | 0 | case MVT::nxv8i1: return fastEmit_AArch64ISD_UZP1_MVT_nxv8i1_rr(RetVT, Op0, Op1); |
9076 | 0 | case MVT::nxv16i1: return fastEmit_AArch64ISD_UZP1_MVT_nxv16i1_rr(RetVT, Op0, Op1); |
9077 | 0 | case MVT::nxv16i8: return fastEmit_AArch64ISD_UZP1_MVT_nxv16i8_rr(RetVT, Op0, Op1); |
9078 | 0 | case MVT::nxv8i16: return fastEmit_AArch64ISD_UZP1_MVT_nxv8i16_rr(RetVT, Op0, Op1); |
9079 | 0 | case MVT::nxv4i32: return fastEmit_AArch64ISD_UZP1_MVT_nxv4i32_rr(RetVT, Op0, Op1); |
9080 | 0 | case MVT::nxv2i64: return fastEmit_AArch64ISD_UZP1_MVT_nxv2i64_rr(RetVT, Op0, Op1); |
9081 | 0 | case MVT::nxv2f16: return fastEmit_AArch64ISD_UZP1_MVT_nxv2f16_rr(RetVT, Op0, Op1); |
9082 | 0 | case MVT::nxv4f16: return fastEmit_AArch64ISD_UZP1_MVT_nxv4f16_rr(RetVT, Op0, Op1); |
9083 | 0 | case MVT::nxv8f16: return fastEmit_AArch64ISD_UZP1_MVT_nxv8f16_rr(RetVT, Op0, Op1); |
9084 | 0 | case MVT::nxv8bf16: return fastEmit_AArch64ISD_UZP1_MVT_nxv8bf16_rr(RetVT, Op0, Op1); |
9085 | 0 | case MVT::nxv2f32: return fastEmit_AArch64ISD_UZP1_MVT_nxv2f32_rr(RetVT, Op0, Op1); |
9086 | 0 | case MVT::nxv4f32: return fastEmit_AArch64ISD_UZP1_MVT_nxv4f32_rr(RetVT, Op0, Op1); |
9087 | 0 | case MVT::nxv2f64: return fastEmit_AArch64ISD_UZP1_MVT_nxv2f64_rr(RetVT, Op0, Op1); |
9088 | 0 | default: return 0; |
9089 | 0 | } |
9090 | 0 | } |
9091 | | |
9092 | | // FastEmit functions for AArch64ISD::UZP2. |
9093 | | |
9094 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9095 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
9096 | 0 | return 0; |
9097 | 0 | if ((Subtarget->hasNEON())) { |
9098 | 0 | return fastEmitInst_rr(AArch64::UZP2v8i8, &AArch64::FPR64RegClass, Op0, Op1); |
9099 | 0 | } |
9100 | 0 | return 0; |
9101 | 0 | } |
9102 | | |
9103 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9104 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
9105 | 0 | return 0; |
9106 | 0 | if ((Subtarget->hasNEON())) { |
9107 | 0 | return fastEmitInst_rr(AArch64::UZP2v16i8, &AArch64::FPR128RegClass, Op0, Op1); |
9108 | 0 | } |
9109 | 0 | return 0; |
9110 | 0 | } |
9111 | | |
9112 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9113 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
9114 | 0 | return 0; |
9115 | 0 | if ((Subtarget->hasNEON())) { |
9116 | 0 | return fastEmitInst_rr(AArch64::UZP2v4i16, &AArch64::FPR64RegClass, Op0, Op1); |
9117 | 0 | } |
9118 | 0 | return 0; |
9119 | 0 | } |
9120 | | |
9121 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9122 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
9123 | 0 | return 0; |
9124 | 0 | if ((Subtarget->hasNEON())) { |
9125 | 0 | return fastEmitInst_rr(AArch64::UZP2v8i16, &AArch64::FPR128RegClass, Op0, Op1); |
9126 | 0 | } |
9127 | 0 | return 0; |
9128 | 0 | } |
9129 | | |
9130 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9131 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
9132 | 0 | return 0; |
9133 | 0 | if ((Subtarget->hasNEON())) { |
9134 | 0 | return fastEmitInst_rr(AArch64::UZP2v2i32, &AArch64::FPR64RegClass, Op0, Op1); |
9135 | 0 | } |
9136 | 0 | return 0; |
9137 | 0 | } |
9138 | | |
9139 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9140 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
9141 | 0 | return 0; |
9142 | 0 | if ((Subtarget->hasNEON())) { |
9143 | 0 | return fastEmitInst_rr(AArch64::UZP2v4i32, &AArch64::FPR128RegClass, Op0, Op1); |
9144 | 0 | } |
9145 | 0 | return 0; |
9146 | 0 | } |
9147 | | |
9148 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9149 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
9150 | 0 | return 0; |
9151 | 0 | if ((Subtarget->hasNEON())) { |
9152 | 0 | return fastEmitInst_rr(AArch64::UZP2v2i64, &AArch64::FPR128RegClass, Op0, Op1); |
9153 | 0 | } |
9154 | 0 | return 0; |
9155 | 0 | } |
9156 | | |
9157 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9158 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
9159 | 0 | return 0; |
9160 | 0 | if ((Subtarget->hasNEON())) { |
9161 | 0 | return fastEmitInst_rr(AArch64::UZP2v4i16, &AArch64::FPR64RegClass, Op0, Op1); |
9162 | 0 | } |
9163 | 0 | return 0; |
9164 | 0 | } |
9165 | | |
9166 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9167 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
9168 | 0 | return 0; |
9169 | 0 | if ((Subtarget->hasNEON())) { |
9170 | 0 | return fastEmitInst_rr(AArch64::UZP2v8i16, &AArch64::FPR128RegClass, Op0, Op1); |
9171 | 0 | } |
9172 | 0 | return 0; |
9173 | 0 | } |
9174 | | |
9175 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_v4bf16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9176 | 0 | if (RetVT.SimpleTy != MVT::v4bf16) |
9177 | 0 | return 0; |
9178 | 0 | if ((Subtarget->hasNEON())) { |
9179 | 0 | return fastEmitInst_rr(AArch64::UZP2v4i16, &AArch64::FPR64RegClass, Op0, Op1); |
9180 | 0 | } |
9181 | 0 | return 0; |
9182 | 0 | } |
9183 | | |
9184 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_v8bf16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9185 | 0 | if (RetVT.SimpleTy != MVT::v8bf16) |
9186 | 0 | return 0; |
9187 | 0 | if ((Subtarget->hasNEON())) { |
9188 | 0 | return fastEmitInst_rr(AArch64::UZP2v8i16, &AArch64::FPR128RegClass, Op0, Op1); |
9189 | 0 | } |
9190 | 0 | return 0; |
9191 | 0 | } |
9192 | | |
9193 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9194 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
9195 | 0 | return 0; |
9196 | 0 | if ((Subtarget->hasNEON())) { |
9197 | 0 | return fastEmitInst_rr(AArch64::UZP2v2i32, &AArch64::FPR64RegClass, Op0, Op1); |
9198 | 0 | } |
9199 | 0 | return 0; |
9200 | 0 | } |
9201 | | |
9202 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9203 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
9204 | 0 | return 0; |
9205 | 0 | if ((Subtarget->hasNEON())) { |
9206 | 0 | return fastEmitInst_rr(AArch64::UZP2v4i32, &AArch64::FPR128RegClass, Op0, Op1); |
9207 | 0 | } |
9208 | 0 | return 0; |
9209 | 0 | } |
9210 | | |
9211 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9212 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
9213 | 0 | return 0; |
9214 | 0 | if ((Subtarget->hasNEON())) { |
9215 | 0 | return fastEmitInst_rr(AArch64::UZP2v2i64, &AArch64::FPR128RegClass, Op0, Op1); |
9216 | 0 | } |
9217 | 0 | return 0; |
9218 | 0 | } |
9219 | | |
9220 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv2i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9221 | 0 | if (RetVT.SimpleTy != MVT::nxv2i1) |
9222 | 0 | return 0; |
9223 | 0 | if ((Subtarget->hasSVEorSME())) { |
9224 | 0 | return fastEmitInst_rr(AArch64::UZP2_PPP_D, &AArch64::PPRRegClass, Op0, Op1); |
9225 | 0 | } |
9226 | 0 | return 0; |
9227 | 0 | } |
9228 | | |
9229 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv4i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9230 | 0 | if (RetVT.SimpleTy != MVT::nxv4i1) |
9231 | 0 | return 0; |
9232 | 0 | if ((Subtarget->hasSVEorSME())) { |
9233 | 0 | return fastEmitInst_rr(AArch64::UZP2_PPP_S, &AArch64::PPRRegClass, Op0, Op1); |
9234 | 0 | } |
9235 | 0 | return 0; |
9236 | 0 | } |
9237 | | |
9238 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv8i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9239 | 0 | if (RetVT.SimpleTy != MVT::nxv8i1) |
9240 | 0 | return 0; |
9241 | 0 | if ((Subtarget->hasSVEorSME())) { |
9242 | 0 | return fastEmitInst_rr(AArch64::UZP2_PPP_H, &AArch64::PPRRegClass, Op0, Op1); |
9243 | 0 | } |
9244 | 0 | return 0; |
9245 | 0 | } |
9246 | | |
9247 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv16i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9248 | 0 | if (RetVT.SimpleTy != MVT::nxv16i1) |
9249 | 0 | return 0; |
9250 | 0 | if ((Subtarget->hasSVEorSME())) { |
9251 | 0 | return fastEmitInst_rr(AArch64::UZP2_PPP_B, &AArch64::PPRRegClass, Op0, Op1); |
9252 | 0 | } |
9253 | 0 | return 0; |
9254 | 0 | } |
9255 | | |
9256 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9257 | 0 | if (RetVT.SimpleTy != MVT::nxv16i8) |
9258 | 0 | return 0; |
9259 | 0 | if ((Subtarget->hasSVEorSME())) { |
9260 | 0 | return fastEmitInst_rr(AArch64::UZP2_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op1); |
9261 | 0 | } |
9262 | 0 | return 0; |
9263 | 0 | } |
9264 | | |
9265 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9266 | 0 | if (RetVT.SimpleTy != MVT::nxv8i16) |
9267 | 0 | return 0; |
9268 | 0 | if ((Subtarget->hasSVEorSME())) { |
9269 | 0 | return fastEmitInst_rr(AArch64::UZP2_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
9270 | 0 | } |
9271 | 0 | return 0; |
9272 | 0 | } |
9273 | | |
9274 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9275 | 0 | if (RetVT.SimpleTy != MVT::nxv4i32) |
9276 | 0 | return 0; |
9277 | 0 | if ((Subtarget->hasSVEorSME())) { |
9278 | 0 | return fastEmitInst_rr(AArch64::UZP2_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
9279 | 0 | } |
9280 | 0 | return 0; |
9281 | 0 | } |
9282 | | |
9283 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9284 | 0 | if (RetVT.SimpleTy != MVT::nxv2i64) |
9285 | 0 | return 0; |
9286 | 0 | if ((Subtarget->hasSVEorSME())) { |
9287 | 0 | return fastEmitInst_rr(AArch64::UZP2_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
9288 | 0 | } |
9289 | 0 | return 0; |
9290 | 0 | } |
9291 | | |
9292 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv2f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9293 | 0 | if (RetVT.SimpleTy != MVT::nxv2f16) |
9294 | 0 | return 0; |
9295 | 0 | if ((Subtarget->hasSVEorSME())) { |
9296 | 0 | return fastEmitInst_rr(AArch64::UZP2_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
9297 | 0 | } |
9298 | 0 | return 0; |
9299 | 0 | } |
9300 | | |
9301 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9302 | 0 | if (RetVT.SimpleTy != MVT::nxv4f16) |
9303 | 0 | return 0; |
9304 | 0 | if ((Subtarget->hasSVEorSME())) { |
9305 | 0 | return fastEmitInst_rr(AArch64::UZP2_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
9306 | 0 | } |
9307 | 0 | return 0; |
9308 | 0 | } |
9309 | | |
9310 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9311 | 0 | if (RetVT.SimpleTy != MVT::nxv8f16) |
9312 | 0 | return 0; |
9313 | 0 | if ((Subtarget->hasSVEorSME())) { |
9314 | 0 | return fastEmitInst_rr(AArch64::UZP2_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
9315 | 0 | } |
9316 | 0 | return 0; |
9317 | 0 | } |
9318 | | |
9319 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv8bf16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9320 | 0 | if (RetVT.SimpleTy != MVT::nxv8bf16) |
9321 | 0 | return 0; |
9322 | 0 | if ((Subtarget->hasSVEorSME())) { |
9323 | 0 | return fastEmitInst_rr(AArch64::UZP2_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
9324 | 0 | } |
9325 | 0 | return 0; |
9326 | 0 | } |
9327 | | |
9328 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9329 | 0 | if (RetVT.SimpleTy != MVT::nxv2f32) |
9330 | 0 | return 0; |
9331 | 0 | if ((Subtarget->hasSVEorSME())) { |
9332 | 0 | return fastEmitInst_rr(AArch64::UZP2_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
9333 | 0 | } |
9334 | 0 | return 0; |
9335 | 0 | } |
9336 | | |
9337 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9338 | 0 | if (RetVT.SimpleTy != MVT::nxv4f32) |
9339 | 0 | return 0; |
9340 | 0 | if ((Subtarget->hasSVEorSME())) { |
9341 | 0 | return fastEmitInst_rr(AArch64::UZP2_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
9342 | 0 | } |
9343 | 0 | return 0; |
9344 | 0 | } |
9345 | | |
9346 | 0 | unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9347 | 0 | if (RetVT.SimpleTy != MVT::nxv2f64) |
9348 | 0 | return 0; |
9349 | 0 | if ((Subtarget->hasSVEorSME())) { |
9350 | 0 | return fastEmitInst_rr(AArch64::UZP2_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
9351 | 0 | } |
9352 | 0 | return 0; |
9353 | 0 | } |
9354 | | |
9355 | 0 | unsigned fastEmit_AArch64ISD_UZP2_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
9356 | 0 | switch (VT.SimpleTy) { |
9357 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_UZP2_MVT_v8i8_rr(RetVT, Op0, Op1); |
9358 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_UZP2_MVT_v16i8_rr(RetVT, Op0, Op1); |
9359 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_UZP2_MVT_v4i16_rr(RetVT, Op0, Op1); |
9360 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_UZP2_MVT_v8i16_rr(RetVT, Op0, Op1); |
9361 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_UZP2_MVT_v2i32_rr(RetVT, Op0, Op1); |
9362 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_UZP2_MVT_v4i32_rr(RetVT, Op0, Op1); |
9363 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_UZP2_MVT_v2i64_rr(RetVT, Op0, Op1); |
9364 | 0 | case MVT::v4f16: return fastEmit_AArch64ISD_UZP2_MVT_v4f16_rr(RetVT, Op0, Op1); |
9365 | 0 | case MVT::v8f16: return fastEmit_AArch64ISD_UZP2_MVT_v8f16_rr(RetVT, Op0, Op1); |
9366 | 0 | case MVT::v4bf16: return fastEmit_AArch64ISD_UZP2_MVT_v4bf16_rr(RetVT, Op0, Op1); |
9367 | 0 | case MVT::v8bf16: return fastEmit_AArch64ISD_UZP2_MVT_v8bf16_rr(RetVT, Op0, Op1); |
9368 | 0 | case MVT::v2f32: return fastEmit_AArch64ISD_UZP2_MVT_v2f32_rr(RetVT, Op0, Op1); |
9369 | 0 | case MVT::v4f32: return fastEmit_AArch64ISD_UZP2_MVT_v4f32_rr(RetVT, Op0, Op1); |
9370 | 0 | case MVT::v2f64: return fastEmit_AArch64ISD_UZP2_MVT_v2f64_rr(RetVT, Op0, Op1); |
9371 | 0 | case MVT::nxv2i1: return fastEmit_AArch64ISD_UZP2_MVT_nxv2i1_rr(RetVT, Op0, Op1); |
9372 | 0 | case MVT::nxv4i1: return fastEmit_AArch64ISD_UZP2_MVT_nxv4i1_rr(RetVT, Op0, Op1); |
9373 | 0 | case MVT::nxv8i1: return fastEmit_AArch64ISD_UZP2_MVT_nxv8i1_rr(RetVT, Op0, Op1); |
9374 | 0 | case MVT::nxv16i1: return fastEmit_AArch64ISD_UZP2_MVT_nxv16i1_rr(RetVT, Op0, Op1); |
9375 | 0 | case MVT::nxv16i8: return fastEmit_AArch64ISD_UZP2_MVT_nxv16i8_rr(RetVT, Op0, Op1); |
9376 | 0 | case MVT::nxv8i16: return fastEmit_AArch64ISD_UZP2_MVT_nxv8i16_rr(RetVT, Op0, Op1); |
9377 | 0 | case MVT::nxv4i32: return fastEmit_AArch64ISD_UZP2_MVT_nxv4i32_rr(RetVT, Op0, Op1); |
9378 | 0 | case MVT::nxv2i64: return fastEmit_AArch64ISD_UZP2_MVT_nxv2i64_rr(RetVT, Op0, Op1); |
9379 | 0 | case MVT::nxv2f16: return fastEmit_AArch64ISD_UZP2_MVT_nxv2f16_rr(RetVT, Op0, Op1); |
9380 | 0 | case MVT::nxv4f16: return fastEmit_AArch64ISD_UZP2_MVT_nxv4f16_rr(RetVT, Op0, Op1); |
9381 | 0 | case MVT::nxv8f16: return fastEmit_AArch64ISD_UZP2_MVT_nxv8f16_rr(RetVT, Op0, Op1); |
9382 | 0 | case MVT::nxv8bf16: return fastEmit_AArch64ISD_UZP2_MVT_nxv8bf16_rr(RetVT, Op0, Op1); |
9383 | 0 | case MVT::nxv2f32: return fastEmit_AArch64ISD_UZP2_MVT_nxv2f32_rr(RetVT, Op0, Op1); |
9384 | 0 | case MVT::nxv4f32: return fastEmit_AArch64ISD_UZP2_MVT_nxv4f32_rr(RetVT, Op0, Op1); |
9385 | 0 | case MVT::nxv2f64: return fastEmit_AArch64ISD_UZP2_MVT_nxv2f64_rr(RetVT, Op0, Op1); |
9386 | 0 | default: return 0; |
9387 | 0 | } |
9388 | 0 | } |
9389 | | |
9390 | | // FastEmit functions for AArch64ISD::ZIP1. |
9391 | | |
9392 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9393 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
9394 | 0 | return 0; |
9395 | 0 | if ((Subtarget->hasNEON())) { |
9396 | 0 | return fastEmitInst_rr(AArch64::ZIP1v8i8, &AArch64::FPR64RegClass, Op0, Op1); |
9397 | 0 | } |
9398 | 0 | return 0; |
9399 | 0 | } |
9400 | | |
9401 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9402 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
9403 | 0 | return 0; |
9404 | 0 | if ((Subtarget->hasNEON())) { |
9405 | 0 | return fastEmitInst_rr(AArch64::ZIP1v16i8, &AArch64::FPR128RegClass, Op0, Op1); |
9406 | 0 | } |
9407 | 0 | return 0; |
9408 | 0 | } |
9409 | | |
9410 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9411 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
9412 | 0 | return 0; |
9413 | 0 | if ((Subtarget->hasNEON())) { |
9414 | 0 | return fastEmitInst_rr(AArch64::ZIP1v4i16, &AArch64::FPR64RegClass, Op0, Op1); |
9415 | 0 | } |
9416 | 0 | return 0; |
9417 | 0 | } |
9418 | | |
9419 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9420 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
9421 | 0 | return 0; |
9422 | 0 | if ((Subtarget->hasNEON())) { |
9423 | 0 | return fastEmitInst_rr(AArch64::ZIP1v8i16, &AArch64::FPR128RegClass, Op0, Op1); |
9424 | 0 | } |
9425 | 0 | return 0; |
9426 | 0 | } |
9427 | | |
9428 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9429 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
9430 | 0 | return 0; |
9431 | 0 | if ((Subtarget->hasNEON())) { |
9432 | 0 | return fastEmitInst_rr(AArch64::ZIP1v2i32, &AArch64::FPR64RegClass, Op0, Op1); |
9433 | 0 | } |
9434 | 0 | return 0; |
9435 | 0 | } |
9436 | | |
9437 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9438 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
9439 | 0 | return 0; |
9440 | 0 | if ((Subtarget->hasNEON())) { |
9441 | 0 | return fastEmitInst_rr(AArch64::ZIP1v4i32, &AArch64::FPR128RegClass, Op0, Op1); |
9442 | 0 | } |
9443 | 0 | return 0; |
9444 | 0 | } |
9445 | | |
9446 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9447 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
9448 | 0 | return 0; |
9449 | 0 | if ((Subtarget->hasNEON())) { |
9450 | 0 | return fastEmitInst_rr(AArch64::ZIP1v2i64, &AArch64::FPR128RegClass, Op0, Op1); |
9451 | 0 | } |
9452 | 0 | return 0; |
9453 | 0 | } |
9454 | | |
9455 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9456 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
9457 | 0 | return 0; |
9458 | 0 | if ((Subtarget->hasNEON())) { |
9459 | 0 | return fastEmitInst_rr(AArch64::ZIP1v4i16, &AArch64::FPR64RegClass, Op0, Op1); |
9460 | 0 | } |
9461 | 0 | return 0; |
9462 | 0 | } |
9463 | | |
9464 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9465 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
9466 | 0 | return 0; |
9467 | 0 | if ((Subtarget->hasNEON())) { |
9468 | 0 | return fastEmitInst_rr(AArch64::ZIP1v8i16, &AArch64::FPR128RegClass, Op0, Op1); |
9469 | 0 | } |
9470 | 0 | return 0; |
9471 | 0 | } |
9472 | | |
9473 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_v4bf16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9474 | 0 | if (RetVT.SimpleTy != MVT::v4bf16) |
9475 | 0 | return 0; |
9476 | 0 | if ((Subtarget->hasNEON())) { |
9477 | 0 | return fastEmitInst_rr(AArch64::ZIP1v4i16, &AArch64::FPR64RegClass, Op0, Op1); |
9478 | 0 | } |
9479 | 0 | return 0; |
9480 | 0 | } |
9481 | | |
9482 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_v8bf16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9483 | 0 | if (RetVT.SimpleTy != MVT::v8bf16) |
9484 | 0 | return 0; |
9485 | 0 | if ((Subtarget->hasNEON())) { |
9486 | 0 | return fastEmitInst_rr(AArch64::ZIP1v8i16, &AArch64::FPR128RegClass, Op0, Op1); |
9487 | 0 | } |
9488 | 0 | return 0; |
9489 | 0 | } |
9490 | | |
9491 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9492 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
9493 | 0 | return 0; |
9494 | 0 | if ((Subtarget->hasNEON())) { |
9495 | 0 | return fastEmitInst_rr(AArch64::ZIP1v2i32, &AArch64::FPR64RegClass, Op0, Op1); |
9496 | 0 | } |
9497 | 0 | return 0; |
9498 | 0 | } |
9499 | | |
9500 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9501 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
9502 | 0 | return 0; |
9503 | 0 | if ((Subtarget->hasNEON())) { |
9504 | 0 | return fastEmitInst_rr(AArch64::ZIP1v4i32, &AArch64::FPR128RegClass, Op0, Op1); |
9505 | 0 | } |
9506 | 0 | return 0; |
9507 | 0 | } |
9508 | | |
9509 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9510 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
9511 | 0 | return 0; |
9512 | 0 | if ((Subtarget->hasNEON())) { |
9513 | 0 | return fastEmitInst_rr(AArch64::ZIP1v2i64, &AArch64::FPR128RegClass, Op0, Op1); |
9514 | 0 | } |
9515 | 0 | return 0; |
9516 | 0 | } |
9517 | | |
9518 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv2i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9519 | 0 | if (RetVT.SimpleTy != MVT::nxv2i1) |
9520 | 0 | return 0; |
9521 | 0 | if ((Subtarget->hasSVEorSME())) { |
9522 | 0 | return fastEmitInst_rr(AArch64::ZIP1_PPP_D, &AArch64::PPRRegClass, Op0, Op1); |
9523 | 0 | } |
9524 | 0 | return 0; |
9525 | 0 | } |
9526 | | |
9527 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv4i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9528 | 0 | if (RetVT.SimpleTy != MVT::nxv4i1) |
9529 | 0 | return 0; |
9530 | 0 | if ((Subtarget->hasSVEorSME())) { |
9531 | 0 | return fastEmitInst_rr(AArch64::ZIP1_PPP_S, &AArch64::PPRRegClass, Op0, Op1); |
9532 | 0 | } |
9533 | 0 | return 0; |
9534 | 0 | } |
9535 | | |
9536 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv8i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9537 | 0 | if (RetVT.SimpleTy != MVT::nxv8i1) |
9538 | 0 | return 0; |
9539 | 0 | if ((Subtarget->hasSVEorSME())) { |
9540 | 0 | return fastEmitInst_rr(AArch64::ZIP1_PPP_H, &AArch64::PPRRegClass, Op0, Op1); |
9541 | 0 | } |
9542 | 0 | return 0; |
9543 | 0 | } |
9544 | | |
9545 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv16i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9546 | 0 | if (RetVT.SimpleTy != MVT::nxv16i1) |
9547 | 0 | return 0; |
9548 | 0 | if ((Subtarget->hasSVEorSME())) { |
9549 | 0 | return fastEmitInst_rr(AArch64::ZIP1_PPP_B, &AArch64::PPRRegClass, Op0, Op1); |
9550 | 0 | } |
9551 | 0 | return 0; |
9552 | 0 | } |
9553 | | |
9554 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9555 | 0 | if (RetVT.SimpleTy != MVT::nxv16i8) |
9556 | 0 | return 0; |
9557 | 0 | if ((Subtarget->hasSVEorSME())) { |
9558 | 0 | return fastEmitInst_rr(AArch64::ZIP1_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op1); |
9559 | 0 | } |
9560 | 0 | return 0; |
9561 | 0 | } |
9562 | | |
9563 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9564 | 0 | if (RetVT.SimpleTy != MVT::nxv8i16) |
9565 | 0 | return 0; |
9566 | 0 | if ((Subtarget->hasSVEorSME())) { |
9567 | 0 | return fastEmitInst_rr(AArch64::ZIP1_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
9568 | 0 | } |
9569 | 0 | return 0; |
9570 | 0 | } |
9571 | | |
9572 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9573 | 0 | if (RetVT.SimpleTy != MVT::nxv4i32) |
9574 | 0 | return 0; |
9575 | 0 | if ((Subtarget->hasSVEorSME())) { |
9576 | 0 | return fastEmitInst_rr(AArch64::ZIP1_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
9577 | 0 | } |
9578 | 0 | return 0; |
9579 | 0 | } |
9580 | | |
9581 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9582 | 0 | if (RetVT.SimpleTy != MVT::nxv2i64) |
9583 | 0 | return 0; |
9584 | 0 | if ((Subtarget->hasSVEorSME())) { |
9585 | 0 | return fastEmitInst_rr(AArch64::ZIP1_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
9586 | 0 | } |
9587 | 0 | return 0; |
9588 | 0 | } |
9589 | | |
9590 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv2f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9591 | 0 | if (RetVT.SimpleTy != MVT::nxv2f16) |
9592 | 0 | return 0; |
9593 | 0 | if ((Subtarget->hasSVEorSME())) { |
9594 | 0 | return fastEmitInst_rr(AArch64::ZIP1_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
9595 | 0 | } |
9596 | 0 | return 0; |
9597 | 0 | } |
9598 | | |
9599 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9600 | 0 | if (RetVT.SimpleTy != MVT::nxv4f16) |
9601 | 0 | return 0; |
9602 | 0 | if ((Subtarget->hasSVEorSME())) { |
9603 | 0 | return fastEmitInst_rr(AArch64::ZIP1_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
9604 | 0 | } |
9605 | 0 | return 0; |
9606 | 0 | } |
9607 | | |
9608 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9609 | 0 | if (RetVT.SimpleTy != MVT::nxv8f16) |
9610 | 0 | return 0; |
9611 | 0 | if ((Subtarget->hasSVEorSME())) { |
9612 | 0 | return fastEmitInst_rr(AArch64::ZIP1_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
9613 | 0 | } |
9614 | 0 | return 0; |
9615 | 0 | } |
9616 | | |
9617 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv8bf16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9618 | 0 | if (RetVT.SimpleTy != MVT::nxv8bf16) |
9619 | 0 | return 0; |
9620 | 0 | if ((Subtarget->hasSVEorSME())) { |
9621 | 0 | return fastEmitInst_rr(AArch64::ZIP1_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
9622 | 0 | } |
9623 | 0 | return 0; |
9624 | 0 | } |
9625 | | |
9626 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9627 | 0 | if (RetVT.SimpleTy != MVT::nxv2f32) |
9628 | 0 | return 0; |
9629 | 0 | if ((Subtarget->hasSVEorSME())) { |
9630 | 0 | return fastEmitInst_rr(AArch64::ZIP1_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
9631 | 0 | } |
9632 | 0 | return 0; |
9633 | 0 | } |
9634 | | |
9635 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9636 | 0 | if (RetVT.SimpleTy != MVT::nxv4f32) |
9637 | 0 | return 0; |
9638 | 0 | if ((Subtarget->hasSVEorSME())) { |
9639 | 0 | return fastEmitInst_rr(AArch64::ZIP1_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
9640 | 0 | } |
9641 | 0 | return 0; |
9642 | 0 | } |
9643 | | |
9644 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9645 | 0 | if (RetVT.SimpleTy != MVT::nxv2f64) |
9646 | 0 | return 0; |
9647 | 0 | if ((Subtarget->hasSVEorSME())) { |
9648 | 0 | return fastEmitInst_rr(AArch64::ZIP1_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
9649 | 0 | } |
9650 | 0 | return 0; |
9651 | 0 | } |
9652 | | |
9653 | 0 | unsigned fastEmit_AArch64ISD_ZIP1_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
9654 | 0 | switch (VT.SimpleTy) { |
9655 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_ZIP1_MVT_v8i8_rr(RetVT, Op0, Op1); |
9656 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_ZIP1_MVT_v16i8_rr(RetVT, Op0, Op1); |
9657 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_ZIP1_MVT_v4i16_rr(RetVT, Op0, Op1); |
9658 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_ZIP1_MVT_v8i16_rr(RetVT, Op0, Op1); |
9659 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_ZIP1_MVT_v2i32_rr(RetVT, Op0, Op1); |
9660 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_ZIP1_MVT_v4i32_rr(RetVT, Op0, Op1); |
9661 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_ZIP1_MVT_v2i64_rr(RetVT, Op0, Op1); |
9662 | 0 | case MVT::v4f16: return fastEmit_AArch64ISD_ZIP1_MVT_v4f16_rr(RetVT, Op0, Op1); |
9663 | 0 | case MVT::v8f16: return fastEmit_AArch64ISD_ZIP1_MVT_v8f16_rr(RetVT, Op0, Op1); |
9664 | 0 | case MVT::v4bf16: return fastEmit_AArch64ISD_ZIP1_MVT_v4bf16_rr(RetVT, Op0, Op1); |
9665 | 0 | case MVT::v8bf16: return fastEmit_AArch64ISD_ZIP1_MVT_v8bf16_rr(RetVT, Op0, Op1); |
9666 | 0 | case MVT::v2f32: return fastEmit_AArch64ISD_ZIP1_MVT_v2f32_rr(RetVT, Op0, Op1); |
9667 | 0 | case MVT::v4f32: return fastEmit_AArch64ISD_ZIP1_MVT_v4f32_rr(RetVT, Op0, Op1); |
9668 | 0 | case MVT::v2f64: return fastEmit_AArch64ISD_ZIP1_MVT_v2f64_rr(RetVT, Op0, Op1); |
9669 | 0 | case MVT::nxv2i1: return fastEmit_AArch64ISD_ZIP1_MVT_nxv2i1_rr(RetVT, Op0, Op1); |
9670 | 0 | case MVT::nxv4i1: return fastEmit_AArch64ISD_ZIP1_MVT_nxv4i1_rr(RetVT, Op0, Op1); |
9671 | 0 | case MVT::nxv8i1: return fastEmit_AArch64ISD_ZIP1_MVT_nxv8i1_rr(RetVT, Op0, Op1); |
9672 | 0 | case MVT::nxv16i1: return fastEmit_AArch64ISD_ZIP1_MVT_nxv16i1_rr(RetVT, Op0, Op1); |
9673 | 0 | case MVT::nxv16i8: return fastEmit_AArch64ISD_ZIP1_MVT_nxv16i8_rr(RetVT, Op0, Op1); |
9674 | 0 | case MVT::nxv8i16: return fastEmit_AArch64ISD_ZIP1_MVT_nxv8i16_rr(RetVT, Op0, Op1); |
9675 | 0 | case MVT::nxv4i32: return fastEmit_AArch64ISD_ZIP1_MVT_nxv4i32_rr(RetVT, Op0, Op1); |
9676 | 0 | case MVT::nxv2i64: return fastEmit_AArch64ISD_ZIP1_MVT_nxv2i64_rr(RetVT, Op0, Op1); |
9677 | 0 | case MVT::nxv2f16: return fastEmit_AArch64ISD_ZIP1_MVT_nxv2f16_rr(RetVT, Op0, Op1); |
9678 | 0 | case MVT::nxv4f16: return fastEmit_AArch64ISD_ZIP1_MVT_nxv4f16_rr(RetVT, Op0, Op1); |
9679 | 0 | case MVT::nxv8f16: return fastEmit_AArch64ISD_ZIP1_MVT_nxv8f16_rr(RetVT, Op0, Op1); |
9680 | 0 | case MVT::nxv8bf16: return fastEmit_AArch64ISD_ZIP1_MVT_nxv8bf16_rr(RetVT, Op0, Op1); |
9681 | 0 | case MVT::nxv2f32: return fastEmit_AArch64ISD_ZIP1_MVT_nxv2f32_rr(RetVT, Op0, Op1); |
9682 | 0 | case MVT::nxv4f32: return fastEmit_AArch64ISD_ZIP1_MVT_nxv4f32_rr(RetVT, Op0, Op1); |
9683 | 0 | case MVT::nxv2f64: return fastEmit_AArch64ISD_ZIP1_MVT_nxv2f64_rr(RetVT, Op0, Op1); |
9684 | 0 | default: return 0; |
9685 | 0 | } |
9686 | 0 | } |
9687 | | |
9688 | | // FastEmit functions for AArch64ISD::ZIP2. |
9689 | | |
9690 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9691 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
9692 | 0 | return 0; |
9693 | 0 | if ((Subtarget->hasNEON())) { |
9694 | 0 | return fastEmitInst_rr(AArch64::ZIP2v8i8, &AArch64::FPR64RegClass, Op0, Op1); |
9695 | 0 | } |
9696 | 0 | return 0; |
9697 | 0 | } |
9698 | | |
9699 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9700 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
9701 | 0 | return 0; |
9702 | 0 | if ((Subtarget->hasNEON())) { |
9703 | 0 | return fastEmitInst_rr(AArch64::ZIP2v16i8, &AArch64::FPR128RegClass, Op0, Op1); |
9704 | 0 | } |
9705 | 0 | return 0; |
9706 | 0 | } |
9707 | | |
9708 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9709 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
9710 | 0 | return 0; |
9711 | 0 | if ((Subtarget->hasNEON())) { |
9712 | 0 | return fastEmitInst_rr(AArch64::ZIP2v4i16, &AArch64::FPR64RegClass, Op0, Op1); |
9713 | 0 | } |
9714 | 0 | return 0; |
9715 | 0 | } |
9716 | | |
9717 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9718 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
9719 | 0 | return 0; |
9720 | 0 | if ((Subtarget->hasNEON())) { |
9721 | 0 | return fastEmitInst_rr(AArch64::ZIP2v8i16, &AArch64::FPR128RegClass, Op0, Op1); |
9722 | 0 | } |
9723 | 0 | return 0; |
9724 | 0 | } |
9725 | | |
9726 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9727 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
9728 | 0 | return 0; |
9729 | 0 | if ((Subtarget->hasNEON())) { |
9730 | 0 | return fastEmitInst_rr(AArch64::ZIP2v2i32, &AArch64::FPR64RegClass, Op0, Op1); |
9731 | 0 | } |
9732 | 0 | return 0; |
9733 | 0 | } |
9734 | | |
9735 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9736 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
9737 | 0 | return 0; |
9738 | 0 | if ((Subtarget->hasNEON())) { |
9739 | 0 | return fastEmitInst_rr(AArch64::ZIP2v4i32, &AArch64::FPR128RegClass, Op0, Op1); |
9740 | 0 | } |
9741 | 0 | return 0; |
9742 | 0 | } |
9743 | | |
9744 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9745 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
9746 | 0 | return 0; |
9747 | 0 | if ((Subtarget->hasNEON())) { |
9748 | 0 | return fastEmitInst_rr(AArch64::ZIP2v2i64, &AArch64::FPR128RegClass, Op0, Op1); |
9749 | 0 | } |
9750 | 0 | return 0; |
9751 | 0 | } |
9752 | | |
9753 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9754 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
9755 | 0 | return 0; |
9756 | 0 | if ((Subtarget->hasNEON())) { |
9757 | 0 | return fastEmitInst_rr(AArch64::ZIP2v4i16, &AArch64::FPR64RegClass, Op0, Op1); |
9758 | 0 | } |
9759 | 0 | return 0; |
9760 | 0 | } |
9761 | | |
9762 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9763 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
9764 | 0 | return 0; |
9765 | 0 | if ((Subtarget->hasNEON())) { |
9766 | 0 | return fastEmitInst_rr(AArch64::ZIP2v8i16, &AArch64::FPR128RegClass, Op0, Op1); |
9767 | 0 | } |
9768 | 0 | return 0; |
9769 | 0 | } |
9770 | | |
9771 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_v4bf16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9772 | 0 | if (RetVT.SimpleTy != MVT::v4bf16) |
9773 | 0 | return 0; |
9774 | 0 | if ((Subtarget->hasNEON())) { |
9775 | 0 | return fastEmitInst_rr(AArch64::ZIP2v4i16, &AArch64::FPR64RegClass, Op0, Op1); |
9776 | 0 | } |
9777 | 0 | return 0; |
9778 | 0 | } |
9779 | | |
9780 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_v8bf16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9781 | 0 | if (RetVT.SimpleTy != MVT::v8bf16) |
9782 | 0 | return 0; |
9783 | 0 | if ((Subtarget->hasNEON())) { |
9784 | 0 | return fastEmitInst_rr(AArch64::ZIP2v8i16, &AArch64::FPR128RegClass, Op0, Op1); |
9785 | 0 | } |
9786 | 0 | return 0; |
9787 | 0 | } |
9788 | | |
9789 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9790 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
9791 | 0 | return 0; |
9792 | 0 | if ((Subtarget->hasNEON())) { |
9793 | 0 | return fastEmitInst_rr(AArch64::ZIP2v2i32, &AArch64::FPR64RegClass, Op0, Op1); |
9794 | 0 | } |
9795 | 0 | return 0; |
9796 | 0 | } |
9797 | | |
9798 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9799 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
9800 | 0 | return 0; |
9801 | 0 | if ((Subtarget->hasNEON())) { |
9802 | 0 | return fastEmitInst_rr(AArch64::ZIP2v4i32, &AArch64::FPR128RegClass, Op0, Op1); |
9803 | 0 | } |
9804 | 0 | return 0; |
9805 | 0 | } |
9806 | | |
9807 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9808 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
9809 | 0 | return 0; |
9810 | 0 | if ((Subtarget->hasNEON())) { |
9811 | 0 | return fastEmitInst_rr(AArch64::ZIP2v2i64, &AArch64::FPR128RegClass, Op0, Op1); |
9812 | 0 | } |
9813 | 0 | return 0; |
9814 | 0 | } |
9815 | | |
9816 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv2i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9817 | 0 | if (RetVT.SimpleTy != MVT::nxv2i1) |
9818 | 0 | return 0; |
9819 | 0 | if ((Subtarget->hasSVEorSME())) { |
9820 | 0 | return fastEmitInst_rr(AArch64::ZIP2_PPP_D, &AArch64::PPRRegClass, Op0, Op1); |
9821 | 0 | } |
9822 | 0 | return 0; |
9823 | 0 | } |
9824 | | |
9825 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv4i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9826 | 0 | if (RetVT.SimpleTy != MVT::nxv4i1) |
9827 | 0 | return 0; |
9828 | 0 | if ((Subtarget->hasSVEorSME())) { |
9829 | 0 | return fastEmitInst_rr(AArch64::ZIP2_PPP_S, &AArch64::PPRRegClass, Op0, Op1); |
9830 | 0 | } |
9831 | 0 | return 0; |
9832 | 0 | } |
9833 | | |
9834 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv8i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9835 | 0 | if (RetVT.SimpleTy != MVT::nxv8i1) |
9836 | 0 | return 0; |
9837 | 0 | if ((Subtarget->hasSVEorSME())) { |
9838 | 0 | return fastEmitInst_rr(AArch64::ZIP2_PPP_H, &AArch64::PPRRegClass, Op0, Op1); |
9839 | 0 | } |
9840 | 0 | return 0; |
9841 | 0 | } |
9842 | | |
9843 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv16i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9844 | 0 | if (RetVT.SimpleTy != MVT::nxv16i1) |
9845 | 0 | return 0; |
9846 | 0 | if ((Subtarget->hasSVEorSME())) { |
9847 | 0 | return fastEmitInst_rr(AArch64::ZIP2_PPP_B, &AArch64::PPRRegClass, Op0, Op1); |
9848 | 0 | } |
9849 | 0 | return 0; |
9850 | 0 | } |
9851 | | |
9852 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9853 | 0 | if (RetVT.SimpleTy != MVT::nxv16i8) |
9854 | 0 | return 0; |
9855 | 0 | if ((Subtarget->hasSVEorSME())) { |
9856 | 0 | return fastEmitInst_rr(AArch64::ZIP2_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op1); |
9857 | 0 | } |
9858 | 0 | return 0; |
9859 | 0 | } |
9860 | | |
9861 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9862 | 0 | if (RetVT.SimpleTy != MVT::nxv8i16) |
9863 | 0 | return 0; |
9864 | 0 | if ((Subtarget->hasSVEorSME())) { |
9865 | 0 | return fastEmitInst_rr(AArch64::ZIP2_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
9866 | 0 | } |
9867 | 0 | return 0; |
9868 | 0 | } |
9869 | | |
9870 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9871 | 0 | if (RetVT.SimpleTy != MVT::nxv4i32) |
9872 | 0 | return 0; |
9873 | 0 | if ((Subtarget->hasSVEorSME())) { |
9874 | 0 | return fastEmitInst_rr(AArch64::ZIP2_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
9875 | 0 | } |
9876 | 0 | return 0; |
9877 | 0 | } |
9878 | | |
9879 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9880 | 0 | if (RetVT.SimpleTy != MVT::nxv2i64) |
9881 | 0 | return 0; |
9882 | 0 | if ((Subtarget->hasSVEorSME())) { |
9883 | 0 | return fastEmitInst_rr(AArch64::ZIP2_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
9884 | 0 | } |
9885 | 0 | return 0; |
9886 | 0 | } |
9887 | | |
9888 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv2f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9889 | 0 | if (RetVT.SimpleTy != MVT::nxv2f16) |
9890 | 0 | return 0; |
9891 | 0 | if ((Subtarget->hasSVEorSME())) { |
9892 | 0 | return fastEmitInst_rr(AArch64::ZIP2_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
9893 | 0 | } |
9894 | 0 | return 0; |
9895 | 0 | } |
9896 | | |
9897 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9898 | 0 | if (RetVT.SimpleTy != MVT::nxv4f16) |
9899 | 0 | return 0; |
9900 | 0 | if ((Subtarget->hasSVEorSME())) { |
9901 | 0 | return fastEmitInst_rr(AArch64::ZIP2_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
9902 | 0 | } |
9903 | 0 | return 0; |
9904 | 0 | } |
9905 | | |
9906 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9907 | 0 | if (RetVT.SimpleTy != MVT::nxv8f16) |
9908 | 0 | return 0; |
9909 | 0 | if ((Subtarget->hasSVEorSME())) { |
9910 | 0 | return fastEmitInst_rr(AArch64::ZIP2_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
9911 | 0 | } |
9912 | 0 | return 0; |
9913 | 0 | } |
9914 | | |
9915 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv8bf16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9916 | 0 | if (RetVT.SimpleTy != MVT::nxv8bf16) |
9917 | 0 | return 0; |
9918 | 0 | if ((Subtarget->hasSVEorSME())) { |
9919 | 0 | return fastEmitInst_rr(AArch64::ZIP2_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
9920 | 0 | } |
9921 | 0 | return 0; |
9922 | 0 | } |
9923 | | |
9924 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9925 | 0 | if (RetVT.SimpleTy != MVT::nxv2f32) |
9926 | 0 | return 0; |
9927 | 0 | if ((Subtarget->hasSVEorSME())) { |
9928 | 0 | return fastEmitInst_rr(AArch64::ZIP2_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
9929 | 0 | } |
9930 | 0 | return 0; |
9931 | 0 | } |
9932 | | |
9933 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9934 | 0 | if (RetVT.SimpleTy != MVT::nxv4f32) |
9935 | 0 | return 0; |
9936 | 0 | if ((Subtarget->hasSVEorSME())) { |
9937 | 0 | return fastEmitInst_rr(AArch64::ZIP2_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
9938 | 0 | } |
9939 | 0 | return 0; |
9940 | 0 | } |
9941 | | |
9942 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9943 | 0 | if (RetVT.SimpleTy != MVT::nxv2f64) |
9944 | 0 | return 0; |
9945 | 0 | if ((Subtarget->hasSVEorSME())) { |
9946 | 0 | return fastEmitInst_rr(AArch64::ZIP2_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
9947 | 0 | } |
9948 | 0 | return 0; |
9949 | 0 | } |
9950 | | |
9951 | 0 | unsigned fastEmit_AArch64ISD_ZIP2_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
9952 | 0 | switch (VT.SimpleTy) { |
9953 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_ZIP2_MVT_v8i8_rr(RetVT, Op0, Op1); |
9954 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_ZIP2_MVT_v16i8_rr(RetVT, Op0, Op1); |
9955 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_ZIP2_MVT_v4i16_rr(RetVT, Op0, Op1); |
9956 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_ZIP2_MVT_v8i16_rr(RetVT, Op0, Op1); |
9957 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_ZIP2_MVT_v2i32_rr(RetVT, Op0, Op1); |
9958 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_ZIP2_MVT_v4i32_rr(RetVT, Op0, Op1); |
9959 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_ZIP2_MVT_v2i64_rr(RetVT, Op0, Op1); |
9960 | 0 | case MVT::v4f16: return fastEmit_AArch64ISD_ZIP2_MVT_v4f16_rr(RetVT, Op0, Op1); |
9961 | 0 | case MVT::v8f16: return fastEmit_AArch64ISD_ZIP2_MVT_v8f16_rr(RetVT, Op0, Op1); |
9962 | 0 | case MVT::v4bf16: return fastEmit_AArch64ISD_ZIP2_MVT_v4bf16_rr(RetVT, Op0, Op1); |
9963 | 0 | case MVT::v8bf16: return fastEmit_AArch64ISD_ZIP2_MVT_v8bf16_rr(RetVT, Op0, Op1); |
9964 | 0 | case MVT::v2f32: return fastEmit_AArch64ISD_ZIP2_MVT_v2f32_rr(RetVT, Op0, Op1); |
9965 | 0 | case MVT::v4f32: return fastEmit_AArch64ISD_ZIP2_MVT_v4f32_rr(RetVT, Op0, Op1); |
9966 | 0 | case MVT::v2f64: return fastEmit_AArch64ISD_ZIP2_MVT_v2f64_rr(RetVT, Op0, Op1); |
9967 | 0 | case MVT::nxv2i1: return fastEmit_AArch64ISD_ZIP2_MVT_nxv2i1_rr(RetVT, Op0, Op1); |
9968 | 0 | case MVT::nxv4i1: return fastEmit_AArch64ISD_ZIP2_MVT_nxv4i1_rr(RetVT, Op0, Op1); |
9969 | 0 | case MVT::nxv8i1: return fastEmit_AArch64ISD_ZIP2_MVT_nxv8i1_rr(RetVT, Op0, Op1); |
9970 | 0 | case MVT::nxv16i1: return fastEmit_AArch64ISD_ZIP2_MVT_nxv16i1_rr(RetVT, Op0, Op1); |
9971 | 0 | case MVT::nxv16i8: return fastEmit_AArch64ISD_ZIP2_MVT_nxv16i8_rr(RetVT, Op0, Op1); |
9972 | 0 | case MVT::nxv8i16: return fastEmit_AArch64ISD_ZIP2_MVT_nxv8i16_rr(RetVT, Op0, Op1); |
9973 | 0 | case MVT::nxv4i32: return fastEmit_AArch64ISD_ZIP2_MVT_nxv4i32_rr(RetVT, Op0, Op1); |
9974 | 0 | case MVT::nxv2i64: return fastEmit_AArch64ISD_ZIP2_MVT_nxv2i64_rr(RetVT, Op0, Op1); |
9975 | 0 | case MVT::nxv2f16: return fastEmit_AArch64ISD_ZIP2_MVT_nxv2f16_rr(RetVT, Op0, Op1); |
9976 | 0 | case MVT::nxv4f16: return fastEmit_AArch64ISD_ZIP2_MVT_nxv4f16_rr(RetVT, Op0, Op1); |
9977 | 0 | case MVT::nxv8f16: return fastEmit_AArch64ISD_ZIP2_MVT_nxv8f16_rr(RetVT, Op0, Op1); |
9978 | 0 | case MVT::nxv8bf16: return fastEmit_AArch64ISD_ZIP2_MVT_nxv8bf16_rr(RetVT, Op0, Op1); |
9979 | 0 | case MVT::nxv2f32: return fastEmit_AArch64ISD_ZIP2_MVT_nxv2f32_rr(RetVT, Op0, Op1); |
9980 | 0 | case MVT::nxv4f32: return fastEmit_AArch64ISD_ZIP2_MVT_nxv4f32_rr(RetVT, Op0, Op1); |
9981 | 0 | case MVT::nxv2f64: return fastEmit_AArch64ISD_ZIP2_MVT_nxv2f64_rr(RetVT, Op0, Op1); |
9982 | 0 | default: return 0; |
9983 | 0 | } |
9984 | 0 | } |
9985 | | |
9986 | | // FastEmit functions for ISD::ABDS. |
9987 | | |
9988 | 0 | unsigned fastEmit_ISD_ABDS_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9989 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
9990 | 0 | return 0; |
9991 | 0 | if ((Subtarget->hasNEON())) { |
9992 | 0 | return fastEmitInst_rr(AArch64::SABDv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
9993 | 0 | } |
9994 | 0 | return 0; |
9995 | 0 | } |
9996 | | |
9997 | 0 | unsigned fastEmit_ISD_ABDS_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
9998 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
9999 | 0 | return 0; |
10000 | 0 | if ((Subtarget->hasNEON())) { |
10001 | 0 | return fastEmitInst_rr(AArch64::SABDv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
10002 | 0 | } |
10003 | 0 | return 0; |
10004 | 0 | } |
10005 | | |
10006 | 0 | unsigned fastEmit_ISD_ABDS_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10007 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
10008 | 0 | return 0; |
10009 | 0 | if ((Subtarget->hasNEON())) { |
10010 | 0 | return fastEmitInst_rr(AArch64::SABDv4i16, &AArch64::FPR64RegClass, Op0, Op1); |
10011 | 0 | } |
10012 | 0 | return 0; |
10013 | 0 | } |
10014 | | |
10015 | 0 | unsigned fastEmit_ISD_ABDS_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10016 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
10017 | 0 | return 0; |
10018 | 0 | if ((Subtarget->hasNEON())) { |
10019 | 0 | return fastEmitInst_rr(AArch64::SABDv8i16, &AArch64::FPR128RegClass, Op0, Op1); |
10020 | 0 | } |
10021 | 0 | return 0; |
10022 | 0 | } |
10023 | | |
10024 | 0 | unsigned fastEmit_ISD_ABDS_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10025 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
10026 | 0 | return 0; |
10027 | 0 | if ((Subtarget->hasNEON())) { |
10028 | 0 | return fastEmitInst_rr(AArch64::SABDv2i32, &AArch64::FPR64RegClass, Op0, Op1); |
10029 | 0 | } |
10030 | 0 | return 0; |
10031 | 0 | } |
10032 | | |
10033 | 0 | unsigned fastEmit_ISD_ABDS_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10034 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
10035 | 0 | return 0; |
10036 | 0 | if ((Subtarget->hasNEON())) { |
10037 | 0 | return fastEmitInst_rr(AArch64::SABDv4i32, &AArch64::FPR128RegClass, Op0, Op1); |
10038 | 0 | } |
10039 | 0 | return 0; |
10040 | 0 | } |
10041 | | |
10042 | 0 | unsigned fastEmit_ISD_ABDS_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
10043 | 0 | switch (VT.SimpleTy) { |
10044 | 0 | case MVT::v8i8: return fastEmit_ISD_ABDS_MVT_v8i8_rr(RetVT, Op0, Op1); |
10045 | 0 | case MVT::v16i8: return fastEmit_ISD_ABDS_MVT_v16i8_rr(RetVT, Op0, Op1); |
10046 | 0 | case MVT::v4i16: return fastEmit_ISD_ABDS_MVT_v4i16_rr(RetVT, Op0, Op1); |
10047 | 0 | case MVT::v8i16: return fastEmit_ISD_ABDS_MVT_v8i16_rr(RetVT, Op0, Op1); |
10048 | 0 | case MVT::v2i32: return fastEmit_ISD_ABDS_MVT_v2i32_rr(RetVT, Op0, Op1); |
10049 | 0 | case MVT::v4i32: return fastEmit_ISD_ABDS_MVT_v4i32_rr(RetVT, Op0, Op1); |
10050 | 0 | default: return 0; |
10051 | 0 | } |
10052 | 0 | } |
10053 | | |
10054 | | // FastEmit functions for ISD::ABDU. |
10055 | | |
10056 | 0 | unsigned fastEmit_ISD_ABDU_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10057 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
10058 | 0 | return 0; |
10059 | 0 | if ((Subtarget->hasNEON())) { |
10060 | 0 | return fastEmitInst_rr(AArch64::UABDv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
10061 | 0 | } |
10062 | 0 | return 0; |
10063 | 0 | } |
10064 | | |
10065 | 0 | unsigned fastEmit_ISD_ABDU_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10066 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
10067 | 0 | return 0; |
10068 | 0 | if ((Subtarget->hasNEON())) { |
10069 | 0 | return fastEmitInst_rr(AArch64::UABDv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
10070 | 0 | } |
10071 | 0 | return 0; |
10072 | 0 | } |
10073 | | |
10074 | 0 | unsigned fastEmit_ISD_ABDU_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10075 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
10076 | 0 | return 0; |
10077 | 0 | if ((Subtarget->hasNEON())) { |
10078 | 0 | return fastEmitInst_rr(AArch64::UABDv4i16, &AArch64::FPR64RegClass, Op0, Op1); |
10079 | 0 | } |
10080 | 0 | return 0; |
10081 | 0 | } |
10082 | | |
10083 | 0 | unsigned fastEmit_ISD_ABDU_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10084 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
10085 | 0 | return 0; |
10086 | 0 | if ((Subtarget->hasNEON())) { |
10087 | 0 | return fastEmitInst_rr(AArch64::UABDv8i16, &AArch64::FPR128RegClass, Op0, Op1); |
10088 | 0 | } |
10089 | 0 | return 0; |
10090 | 0 | } |
10091 | | |
10092 | 0 | unsigned fastEmit_ISD_ABDU_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10093 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
10094 | 0 | return 0; |
10095 | 0 | if ((Subtarget->hasNEON())) { |
10096 | 0 | return fastEmitInst_rr(AArch64::UABDv2i32, &AArch64::FPR64RegClass, Op0, Op1); |
10097 | 0 | } |
10098 | 0 | return 0; |
10099 | 0 | } |
10100 | | |
10101 | 0 | unsigned fastEmit_ISD_ABDU_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10102 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
10103 | 0 | return 0; |
10104 | 0 | if ((Subtarget->hasNEON())) { |
10105 | 0 | return fastEmitInst_rr(AArch64::UABDv4i32, &AArch64::FPR128RegClass, Op0, Op1); |
10106 | 0 | } |
10107 | 0 | return 0; |
10108 | 0 | } |
10109 | | |
10110 | 0 | unsigned fastEmit_ISD_ABDU_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
10111 | 0 | switch (VT.SimpleTy) { |
10112 | 0 | case MVT::v8i8: return fastEmit_ISD_ABDU_MVT_v8i8_rr(RetVT, Op0, Op1); |
10113 | 0 | case MVT::v16i8: return fastEmit_ISD_ABDU_MVT_v16i8_rr(RetVT, Op0, Op1); |
10114 | 0 | case MVT::v4i16: return fastEmit_ISD_ABDU_MVT_v4i16_rr(RetVT, Op0, Op1); |
10115 | 0 | case MVT::v8i16: return fastEmit_ISD_ABDU_MVT_v8i16_rr(RetVT, Op0, Op1); |
10116 | 0 | case MVT::v2i32: return fastEmit_ISD_ABDU_MVT_v2i32_rr(RetVT, Op0, Op1); |
10117 | 0 | case MVT::v4i32: return fastEmit_ISD_ABDU_MVT_v4i32_rr(RetVT, Op0, Op1); |
10118 | 0 | default: return 0; |
10119 | 0 | } |
10120 | 0 | } |
10121 | | |
10122 | | // FastEmit functions for ISD::ADD. |
10123 | | |
10124 | 0 | unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10125 | 0 | if (RetVT.SimpleTy != MVT::i32) |
10126 | 0 | return 0; |
10127 | 0 | return fastEmitInst_rr(AArch64::ADDWrr, &AArch64::GPR32RegClass, Op0, Op1); |
10128 | 0 | } |
10129 | | |
10130 | 0 | unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10131 | 0 | if (RetVT.SimpleTy != MVT::i64) |
10132 | 0 | return 0; |
10133 | 0 | return fastEmitInst_rr(AArch64::ADDXrr, &AArch64::GPR64RegClass, Op0, Op1); |
10134 | 0 | } |
10135 | | |
10136 | 0 | unsigned fastEmit_ISD_ADD_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10137 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
10138 | 0 | return 0; |
10139 | 0 | if ((Subtarget->hasNEON())) { |
10140 | 0 | return fastEmitInst_rr(AArch64::ADDv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
10141 | 0 | } |
10142 | 0 | return 0; |
10143 | 0 | } |
10144 | | |
10145 | 0 | unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10146 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
10147 | 0 | return 0; |
10148 | 0 | if ((Subtarget->hasNEON())) { |
10149 | 0 | return fastEmitInst_rr(AArch64::ADDv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
10150 | 0 | } |
10151 | 0 | return 0; |
10152 | 0 | } |
10153 | | |
10154 | 0 | unsigned fastEmit_ISD_ADD_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10155 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
10156 | 0 | return 0; |
10157 | 0 | if ((Subtarget->hasNEON())) { |
10158 | 0 | return fastEmitInst_rr(AArch64::ADDv4i16, &AArch64::FPR64RegClass, Op0, Op1); |
10159 | 0 | } |
10160 | 0 | return 0; |
10161 | 0 | } |
10162 | | |
10163 | 0 | unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10164 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
10165 | 0 | return 0; |
10166 | 0 | if ((Subtarget->hasNEON())) { |
10167 | 0 | return fastEmitInst_rr(AArch64::ADDv8i16, &AArch64::FPR128RegClass, Op0, Op1); |
10168 | 0 | } |
10169 | 0 | return 0; |
10170 | 0 | } |
10171 | | |
10172 | 0 | unsigned fastEmit_ISD_ADD_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10173 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
10174 | 0 | return 0; |
10175 | 0 | if ((Subtarget->hasNEON())) { |
10176 | 0 | return fastEmitInst_rr(AArch64::ADDv2i32, &AArch64::FPR64RegClass, Op0, Op1); |
10177 | 0 | } |
10178 | 0 | return 0; |
10179 | 0 | } |
10180 | | |
10181 | 0 | unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10182 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
10183 | 0 | return 0; |
10184 | 0 | if ((Subtarget->hasNEON())) { |
10185 | 0 | return fastEmitInst_rr(AArch64::ADDv4i32, &AArch64::FPR128RegClass, Op0, Op1); |
10186 | 0 | } |
10187 | 0 | return 0; |
10188 | 0 | } |
10189 | | |
10190 | 0 | unsigned fastEmit_ISD_ADD_MVT_v1i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10191 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
10192 | 0 | return 0; |
10193 | 0 | if ((Subtarget->hasNEON())) { |
10194 | 0 | return fastEmitInst_rr(AArch64::ADDv1i64, &AArch64::FPR64RegClass, Op0, Op1); |
10195 | 0 | } |
10196 | 0 | return 0; |
10197 | 0 | } |
10198 | | |
10199 | 0 | unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10200 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
10201 | 0 | return 0; |
10202 | 0 | if ((Subtarget->hasNEON())) { |
10203 | 0 | return fastEmitInst_rr(AArch64::ADDv2i64, &AArch64::FPR128RegClass, Op0, Op1); |
10204 | 0 | } |
10205 | 0 | return 0; |
10206 | 0 | } |
10207 | | |
10208 | 0 | unsigned fastEmit_ISD_ADD_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10209 | 0 | if (RetVT.SimpleTy != MVT::nxv16i8) |
10210 | 0 | return 0; |
10211 | 0 | if ((Subtarget->hasSVEorSME())) { |
10212 | 0 | return fastEmitInst_rr(AArch64::ADD_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op1); |
10213 | 0 | } |
10214 | 0 | return 0; |
10215 | 0 | } |
10216 | | |
10217 | 0 | unsigned fastEmit_ISD_ADD_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10218 | 0 | if (RetVT.SimpleTy != MVT::nxv8i16) |
10219 | 0 | return 0; |
10220 | 0 | if ((Subtarget->hasSVEorSME())) { |
10221 | 0 | return fastEmitInst_rr(AArch64::ADD_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
10222 | 0 | } |
10223 | 0 | return 0; |
10224 | 0 | } |
10225 | | |
10226 | 0 | unsigned fastEmit_ISD_ADD_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10227 | 0 | if (RetVT.SimpleTy != MVT::nxv4i32) |
10228 | 0 | return 0; |
10229 | 0 | if ((Subtarget->hasSVEorSME())) { |
10230 | 0 | return fastEmitInst_rr(AArch64::ADD_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
10231 | 0 | } |
10232 | 0 | return 0; |
10233 | 0 | } |
10234 | | |
10235 | 0 | unsigned fastEmit_ISD_ADD_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10236 | 0 | if (RetVT.SimpleTy != MVT::nxv2i64) |
10237 | 0 | return 0; |
10238 | 0 | if ((Subtarget->hasSVEorSME())) { |
10239 | 0 | return fastEmitInst_rr(AArch64::ADD_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
10240 | 0 | } |
10241 | 0 | return 0; |
10242 | 0 | } |
10243 | | |
10244 | 0 | unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
10245 | 0 | switch (VT.SimpleTy) { |
10246 | 0 | case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1); |
10247 | 0 | case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1); |
10248 | 0 | case MVT::v8i8: return fastEmit_ISD_ADD_MVT_v8i8_rr(RetVT, Op0, Op1); |
10249 | 0 | case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op1); |
10250 | 0 | case MVT::v4i16: return fastEmit_ISD_ADD_MVT_v4i16_rr(RetVT, Op0, Op1); |
10251 | 0 | case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op1); |
10252 | 0 | case MVT::v2i32: return fastEmit_ISD_ADD_MVT_v2i32_rr(RetVT, Op0, Op1); |
10253 | 0 | case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op1); |
10254 | 0 | case MVT::v1i64: return fastEmit_ISD_ADD_MVT_v1i64_rr(RetVT, Op0, Op1); |
10255 | 0 | case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op1); |
10256 | 0 | case MVT::nxv16i8: return fastEmit_ISD_ADD_MVT_nxv16i8_rr(RetVT, Op0, Op1); |
10257 | 0 | case MVT::nxv8i16: return fastEmit_ISD_ADD_MVT_nxv8i16_rr(RetVT, Op0, Op1); |
10258 | 0 | case MVT::nxv4i32: return fastEmit_ISD_ADD_MVT_nxv4i32_rr(RetVT, Op0, Op1); |
10259 | 0 | case MVT::nxv2i64: return fastEmit_ISD_ADD_MVT_nxv2i64_rr(RetVT, Op0, Op1); |
10260 | 0 | default: return 0; |
10261 | 0 | } |
10262 | 0 | } |
10263 | | |
10264 | | // FastEmit functions for ISD::AND. |
10265 | | |
10266 | 0 | unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10267 | 0 | if (RetVT.SimpleTy != MVT::i32) |
10268 | 0 | return 0; |
10269 | 0 | return fastEmitInst_rr(AArch64::ANDWrr, &AArch64::GPR32RegClass, Op0, Op1); |
10270 | 0 | } |
10271 | | |
10272 | 0 | unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10273 | 0 | if (RetVT.SimpleTy != MVT::i64) |
10274 | 0 | return 0; |
10275 | 0 | return fastEmitInst_rr(AArch64::ANDXrr, &AArch64::GPR64RegClass, Op0, Op1); |
10276 | 0 | } |
10277 | | |
10278 | 0 | unsigned fastEmit_ISD_AND_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10279 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
10280 | 0 | return 0; |
10281 | 0 | if ((Subtarget->hasNEON())) { |
10282 | 0 | return fastEmitInst_rr(AArch64::ANDv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
10283 | 0 | } |
10284 | 0 | return 0; |
10285 | 0 | } |
10286 | | |
10287 | 0 | unsigned fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10288 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
10289 | 0 | return 0; |
10290 | 0 | if ((Subtarget->hasNEON())) { |
10291 | 0 | return fastEmitInst_rr(AArch64::ANDv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
10292 | 0 | } |
10293 | 0 | return 0; |
10294 | 0 | } |
10295 | | |
10296 | 0 | unsigned fastEmit_ISD_AND_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10297 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
10298 | 0 | return 0; |
10299 | 0 | if ((Subtarget->hasNEON())) { |
10300 | 0 | return fastEmitInst_rr(AArch64::ANDv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
10301 | 0 | } |
10302 | 0 | return 0; |
10303 | 0 | } |
10304 | | |
10305 | 0 | unsigned fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10306 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
10307 | 0 | return 0; |
10308 | 0 | if ((Subtarget->hasNEON())) { |
10309 | 0 | return fastEmitInst_rr(AArch64::ANDv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
10310 | 0 | } |
10311 | 0 | return 0; |
10312 | 0 | } |
10313 | | |
10314 | 0 | unsigned fastEmit_ISD_AND_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10315 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
10316 | 0 | return 0; |
10317 | 0 | if ((Subtarget->hasNEON())) { |
10318 | 0 | return fastEmitInst_rr(AArch64::ANDv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
10319 | 0 | } |
10320 | 0 | return 0; |
10321 | 0 | } |
10322 | | |
10323 | 0 | unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10324 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
10325 | 0 | return 0; |
10326 | 0 | if ((Subtarget->hasNEON())) { |
10327 | 0 | return fastEmitInst_rr(AArch64::ANDv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
10328 | 0 | } |
10329 | 0 | return 0; |
10330 | 0 | } |
10331 | | |
10332 | 0 | unsigned fastEmit_ISD_AND_MVT_v1i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10333 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
10334 | 0 | return 0; |
10335 | 0 | if ((Subtarget->hasNEON())) { |
10336 | 0 | return fastEmitInst_rr(AArch64::ANDv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
10337 | 0 | } |
10338 | 0 | return 0; |
10339 | 0 | } |
10340 | | |
10341 | 0 | unsigned fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10342 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
10343 | 0 | return 0; |
10344 | 0 | if ((Subtarget->hasNEON())) { |
10345 | 0 | return fastEmitInst_rr(AArch64::ANDv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
10346 | 0 | } |
10347 | 0 | return 0; |
10348 | 0 | } |
10349 | | |
10350 | 0 | unsigned fastEmit_ISD_AND_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10351 | 0 | if (RetVT.SimpleTy != MVT::nxv16i8) |
10352 | 0 | return 0; |
10353 | 0 | if ((Subtarget->hasSVEorSME())) { |
10354 | 0 | return fastEmitInst_rr(AArch64::AND_ZZZ, &AArch64::ZPRRegClass, Op0, Op1); |
10355 | 0 | } |
10356 | 0 | return 0; |
10357 | 0 | } |
10358 | | |
10359 | 0 | unsigned fastEmit_ISD_AND_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10360 | 0 | if (RetVT.SimpleTy != MVT::nxv8i16) |
10361 | 0 | return 0; |
10362 | 0 | if ((Subtarget->hasSVEorSME())) { |
10363 | 0 | return fastEmitInst_rr(AArch64::AND_ZZZ, &AArch64::ZPRRegClass, Op0, Op1); |
10364 | 0 | } |
10365 | 0 | return 0; |
10366 | 0 | } |
10367 | | |
10368 | 0 | unsigned fastEmit_ISD_AND_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10369 | 0 | if (RetVT.SimpleTy != MVT::nxv4i32) |
10370 | 0 | return 0; |
10371 | 0 | if ((Subtarget->hasSVEorSME())) { |
10372 | 0 | return fastEmitInst_rr(AArch64::AND_ZZZ, &AArch64::ZPRRegClass, Op0, Op1); |
10373 | 0 | } |
10374 | 0 | return 0; |
10375 | 0 | } |
10376 | | |
10377 | 0 | unsigned fastEmit_ISD_AND_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10378 | 0 | if (RetVT.SimpleTy != MVT::nxv2i64) |
10379 | 0 | return 0; |
10380 | 0 | if ((Subtarget->hasSVEorSME())) { |
10381 | 0 | return fastEmitInst_rr(AArch64::AND_ZZZ, &AArch64::ZPRRegClass, Op0, Op1); |
10382 | 0 | } |
10383 | 0 | return 0; |
10384 | 0 | } |
10385 | | |
10386 | 0 | unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
10387 | 0 | switch (VT.SimpleTy) { |
10388 | 0 | case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op1); |
10389 | 0 | case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op1); |
10390 | 0 | case MVT::v8i8: return fastEmit_ISD_AND_MVT_v8i8_rr(RetVT, Op0, Op1); |
10391 | 0 | case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op1); |
10392 | 0 | case MVT::v4i16: return fastEmit_ISD_AND_MVT_v4i16_rr(RetVT, Op0, Op1); |
10393 | 0 | case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op1); |
10394 | 0 | case MVT::v2i32: return fastEmit_ISD_AND_MVT_v2i32_rr(RetVT, Op0, Op1); |
10395 | 0 | case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op1); |
10396 | 0 | case MVT::v1i64: return fastEmit_ISD_AND_MVT_v1i64_rr(RetVT, Op0, Op1); |
10397 | 0 | case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op1); |
10398 | 0 | case MVT::nxv16i8: return fastEmit_ISD_AND_MVT_nxv16i8_rr(RetVT, Op0, Op1); |
10399 | 0 | case MVT::nxv8i16: return fastEmit_ISD_AND_MVT_nxv8i16_rr(RetVT, Op0, Op1); |
10400 | 0 | case MVT::nxv4i32: return fastEmit_ISD_AND_MVT_nxv4i32_rr(RetVT, Op0, Op1); |
10401 | 0 | case MVT::nxv2i64: return fastEmit_ISD_AND_MVT_nxv2i64_rr(RetVT, Op0, Op1); |
10402 | 0 | default: return 0; |
10403 | 0 | } |
10404 | 0 | } |
10405 | | |
10406 | | // FastEmit functions for ISD::AVGCEILS. |
10407 | | |
10408 | 0 | unsigned fastEmit_ISD_AVGCEILS_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10409 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
10410 | 0 | return 0; |
10411 | 0 | if ((Subtarget->hasNEON())) { |
10412 | 0 | return fastEmitInst_rr(AArch64::SRHADDv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
10413 | 0 | } |
10414 | 0 | return 0; |
10415 | 0 | } |
10416 | | |
10417 | 0 | unsigned fastEmit_ISD_AVGCEILS_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10418 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
10419 | 0 | return 0; |
10420 | 0 | if ((Subtarget->hasNEON())) { |
10421 | 0 | return fastEmitInst_rr(AArch64::SRHADDv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
10422 | 0 | } |
10423 | 0 | return 0; |
10424 | 0 | } |
10425 | | |
10426 | 0 | unsigned fastEmit_ISD_AVGCEILS_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10427 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
10428 | 0 | return 0; |
10429 | 0 | if ((Subtarget->hasNEON())) { |
10430 | 0 | return fastEmitInst_rr(AArch64::SRHADDv4i16, &AArch64::FPR64RegClass, Op0, Op1); |
10431 | 0 | } |
10432 | 0 | return 0; |
10433 | 0 | } |
10434 | | |
10435 | 0 | unsigned fastEmit_ISD_AVGCEILS_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10436 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
10437 | 0 | return 0; |
10438 | 0 | if ((Subtarget->hasNEON())) { |
10439 | 0 | return fastEmitInst_rr(AArch64::SRHADDv8i16, &AArch64::FPR128RegClass, Op0, Op1); |
10440 | 0 | } |
10441 | 0 | return 0; |
10442 | 0 | } |
10443 | | |
10444 | 0 | unsigned fastEmit_ISD_AVGCEILS_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10445 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
10446 | 0 | return 0; |
10447 | 0 | if ((Subtarget->hasNEON())) { |
10448 | 0 | return fastEmitInst_rr(AArch64::SRHADDv2i32, &AArch64::FPR64RegClass, Op0, Op1); |
10449 | 0 | } |
10450 | 0 | return 0; |
10451 | 0 | } |
10452 | | |
10453 | 0 | unsigned fastEmit_ISD_AVGCEILS_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10454 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
10455 | 0 | return 0; |
10456 | 0 | if ((Subtarget->hasNEON())) { |
10457 | 0 | return fastEmitInst_rr(AArch64::SRHADDv4i32, &AArch64::FPR128RegClass, Op0, Op1); |
10458 | 0 | } |
10459 | 0 | return 0; |
10460 | 0 | } |
10461 | | |
10462 | 0 | unsigned fastEmit_ISD_AVGCEILS_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
10463 | 0 | switch (VT.SimpleTy) { |
10464 | 0 | case MVT::v8i8: return fastEmit_ISD_AVGCEILS_MVT_v8i8_rr(RetVT, Op0, Op1); |
10465 | 0 | case MVT::v16i8: return fastEmit_ISD_AVGCEILS_MVT_v16i8_rr(RetVT, Op0, Op1); |
10466 | 0 | case MVT::v4i16: return fastEmit_ISD_AVGCEILS_MVT_v4i16_rr(RetVT, Op0, Op1); |
10467 | 0 | case MVT::v8i16: return fastEmit_ISD_AVGCEILS_MVT_v8i16_rr(RetVT, Op0, Op1); |
10468 | 0 | case MVT::v2i32: return fastEmit_ISD_AVGCEILS_MVT_v2i32_rr(RetVT, Op0, Op1); |
10469 | 0 | case MVT::v4i32: return fastEmit_ISD_AVGCEILS_MVT_v4i32_rr(RetVT, Op0, Op1); |
10470 | 0 | default: return 0; |
10471 | 0 | } |
10472 | 0 | } |
10473 | | |
10474 | | // FastEmit functions for ISD::AVGCEILU. |
10475 | | |
10476 | 0 | unsigned fastEmit_ISD_AVGCEILU_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10477 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
10478 | 0 | return 0; |
10479 | 0 | if ((Subtarget->hasNEON())) { |
10480 | 0 | return fastEmitInst_rr(AArch64::URHADDv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
10481 | 0 | } |
10482 | 0 | return 0; |
10483 | 0 | } |
10484 | | |
10485 | 0 | unsigned fastEmit_ISD_AVGCEILU_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10486 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
10487 | 0 | return 0; |
10488 | 0 | if ((Subtarget->hasNEON())) { |
10489 | 0 | return fastEmitInst_rr(AArch64::URHADDv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
10490 | 0 | } |
10491 | 0 | return 0; |
10492 | 0 | } |
10493 | | |
10494 | 0 | unsigned fastEmit_ISD_AVGCEILU_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10495 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
10496 | 0 | return 0; |
10497 | 0 | if ((Subtarget->hasNEON())) { |
10498 | 0 | return fastEmitInst_rr(AArch64::URHADDv4i16, &AArch64::FPR64RegClass, Op0, Op1); |
10499 | 0 | } |
10500 | 0 | return 0; |
10501 | 0 | } |
10502 | | |
10503 | 0 | unsigned fastEmit_ISD_AVGCEILU_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10504 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
10505 | 0 | return 0; |
10506 | 0 | if ((Subtarget->hasNEON())) { |
10507 | 0 | return fastEmitInst_rr(AArch64::URHADDv8i16, &AArch64::FPR128RegClass, Op0, Op1); |
10508 | 0 | } |
10509 | 0 | return 0; |
10510 | 0 | } |
10511 | | |
10512 | 0 | unsigned fastEmit_ISD_AVGCEILU_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10513 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
10514 | 0 | return 0; |
10515 | 0 | if ((Subtarget->hasNEON())) { |
10516 | 0 | return fastEmitInst_rr(AArch64::URHADDv2i32, &AArch64::FPR64RegClass, Op0, Op1); |
10517 | 0 | } |
10518 | 0 | return 0; |
10519 | 0 | } |
10520 | | |
10521 | 0 | unsigned fastEmit_ISD_AVGCEILU_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10522 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
10523 | 0 | return 0; |
10524 | 0 | if ((Subtarget->hasNEON())) { |
10525 | 0 | return fastEmitInst_rr(AArch64::URHADDv4i32, &AArch64::FPR128RegClass, Op0, Op1); |
10526 | 0 | } |
10527 | 0 | return 0; |
10528 | 0 | } |
10529 | | |
10530 | 0 | unsigned fastEmit_ISD_AVGCEILU_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
10531 | 0 | switch (VT.SimpleTy) { |
10532 | 0 | case MVT::v8i8: return fastEmit_ISD_AVGCEILU_MVT_v8i8_rr(RetVT, Op0, Op1); |
10533 | 0 | case MVT::v16i8: return fastEmit_ISD_AVGCEILU_MVT_v16i8_rr(RetVT, Op0, Op1); |
10534 | 0 | case MVT::v4i16: return fastEmit_ISD_AVGCEILU_MVT_v4i16_rr(RetVT, Op0, Op1); |
10535 | 0 | case MVT::v8i16: return fastEmit_ISD_AVGCEILU_MVT_v8i16_rr(RetVT, Op0, Op1); |
10536 | 0 | case MVT::v2i32: return fastEmit_ISD_AVGCEILU_MVT_v2i32_rr(RetVT, Op0, Op1); |
10537 | 0 | case MVT::v4i32: return fastEmit_ISD_AVGCEILU_MVT_v4i32_rr(RetVT, Op0, Op1); |
10538 | 0 | default: return 0; |
10539 | 0 | } |
10540 | 0 | } |
10541 | | |
10542 | | // FastEmit functions for ISD::AVGFLOORS. |
10543 | | |
10544 | 0 | unsigned fastEmit_ISD_AVGFLOORS_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10545 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
10546 | 0 | return 0; |
10547 | 0 | if ((Subtarget->hasNEON())) { |
10548 | 0 | return fastEmitInst_rr(AArch64::SHADDv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
10549 | 0 | } |
10550 | 0 | return 0; |
10551 | 0 | } |
10552 | | |
10553 | 0 | unsigned fastEmit_ISD_AVGFLOORS_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10554 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
10555 | 0 | return 0; |
10556 | 0 | if ((Subtarget->hasNEON())) { |
10557 | 0 | return fastEmitInst_rr(AArch64::SHADDv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
10558 | 0 | } |
10559 | 0 | return 0; |
10560 | 0 | } |
10561 | | |
10562 | 0 | unsigned fastEmit_ISD_AVGFLOORS_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10563 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
10564 | 0 | return 0; |
10565 | 0 | if ((Subtarget->hasNEON())) { |
10566 | 0 | return fastEmitInst_rr(AArch64::SHADDv4i16, &AArch64::FPR64RegClass, Op0, Op1); |
10567 | 0 | } |
10568 | 0 | return 0; |
10569 | 0 | } |
10570 | | |
10571 | 0 | unsigned fastEmit_ISD_AVGFLOORS_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10572 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
10573 | 0 | return 0; |
10574 | 0 | if ((Subtarget->hasNEON())) { |
10575 | 0 | return fastEmitInst_rr(AArch64::SHADDv8i16, &AArch64::FPR128RegClass, Op0, Op1); |
10576 | 0 | } |
10577 | 0 | return 0; |
10578 | 0 | } |
10579 | | |
10580 | 0 | unsigned fastEmit_ISD_AVGFLOORS_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10581 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
10582 | 0 | return 0; |
10583 | 0 | if ((Subtarget->hasNEON())) { |
10584 | 0 | return fastEmitInst_rr(AArch64::SHADDv2i32, &AArch64::FPR64RegClass, Op0, Op1); |
10585 | 0 | } |
10586 | 0 | return 0; |
10587 | 0 | } |
10588 | | |
10589 | 0 | unsigned fastEmit_ISD_AVGFLOORS_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10590 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
10591 | 0 | return 0; |
10592 | 0 | if ((Subtarget->hasNEON())) { |
10593 | 0 | return fastEmitInst_rr(AArch64::SHADDv4i32, &AArch64::FPR128RegClass, Op0, Op1); |
10594 | 0 | } |
10595 | 0 | return 0; |
10596 | 0 | } |
10597 | | |
10598 | 0 | unsigned fastEmit_ISD_AVGFLOORS_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
10599 | 0 | switch (VT.SimpleTy) { |
10600 | 0 | case MVT::v8i8: return fastEmit_ISD_AVGFLOORS_MVT_v8i8_rr(RetVT, Op0, Op1); |
10601 | 0 | case MVT::v16i8: return fastEmit_ISD_AVGFLOORS_MVT_v16i8_rr(RetVT, Op0, Op1); |
10602 | 0 | case MVT::v4i16: return fastEmit_ISD_AVGFLOORS_MVT_v4i16_rr(RetVT, Op0, Op1); |
10603 | 0 | case MVT::v8i16: return fastEmit_ISD_AVGFLOORS_MVT_v8i16_rr(RetVT, Op0, Op1); |
10604 | 0 | case MVT::v2i32: return fastEmit_ISD_AVGFLOORS_MVT_v2i32_rr(RetVT, Op0, Op1); |
10605 | 0 | case MVT::v4i32: return fastEmit_ISD_AVGFLOORS_MVT_v4i32_rr(RetVT, Op0, Op1); |
10606 | 0 | default: return 0; |
10607 | 0 | } |
10608 | 0 | } |
10609 | | |
10610 | | // FastEmit functions for ISD::AVGFLOORU. |
10611 | | |
10612 | 0 | unsigned fastEmit_ISD_AVGFLOORU_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10613 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
10614 | 0 | return 0; |
10615 | 0 | if ((Subtarget->hasNEON())) { |
10616 | 0 | return fastEmitInst_rr(AArch64::UHADDv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
10617 | 0 | } |
10618 | 0 | return 0; |
10619 | 0 | } |
10620 | | |
10621 | 0 | unsigned fastEmit_ISD_AVGFLOORU_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10622 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
10623 | 0 | return 0; |
10624 | 0 | if ((Subtarget->hasNEON())) { |
10625 | 0 | return fastEmitInst_rr(AArch64::UHADDv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
10626 | 0 | } |
10627 | 0 | return 0; |
10628 | 0 | } |
10629 | | |
10630 | 0 | unsigned fastEmit_ISD_AVGFLOORU_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10631 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
10632 | 0 | return 0; |
10633 | 0 | if ((Subtarget->hasNEON())) { |
10634 | 0 | return fastEmitInst_rr(AArch64::UHADDv4i16, &AArch64::FPR64RegClass, Op0, Op1); |
10635 | 0 | } |
10636 | 0 | return 0; |
10637 | 0 | } |
10638 | | |
10639 | 0 | unsigned fastEmit_ISD_AVGFLOORU_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10640 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
10641 | 0 | return 0; |
10642 | 0 | if ((Subtarget->hasNEON())) { |
10643 | 0 | return fastEmitInst_rr(AArch64::UHADDv8i16, &AArch64::FPR128RegClass, Op0, Op1); |
10644 | 0 | } |
10645 | 0 | return 0; |
10646 | 0 | } |
10647 | | |
10648 | 0 | unsigned fastEmit_ISD_AVGFLOORU_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10649 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
10650 | 0 | return 0; |
10651 | 0 | if ((Subtarget->hasNEON())) { |
10652 | 0 | return fastEmitInst_rr(AArch64::UHADDv2i32, &AArch64::FPR64RegClass, Op0, Op1); |
10653 | 0 | } |
10654 | 0 | return 0; |
10655 | 0 | } |
10656 | | |
10657 | 0 | unsigned fastEmit_ISD_AVGFLOORU_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10658 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
10659 | 0 | return 0; |
10660 | 0 | if ((Subtarget->hasNEON())) { |
10661 | 0 | return fastEmitInst_rr(AArch64::UHADDv4i32, &AArch64::FPR128RegClass, Op0, Op1); |
10662 | 0 | } |
10663 | 0 | return 0; |
10664 | 0 | } |
10665 | | |
10666 | 0 | unsigned fastEmit_ISD_AVGFLOORU_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
10667 | 0 | switch (VT.SimpleTy) { |
10668 | 0 | case MVT::v8i8: return fastEmit_ISD_AVGFLOORU_MVT_v8i8_rr(RetVT, Op0, Op1); |
10669 | 0 | case MVT::v16i8: return fastEmit_ISD_AVGFLOORU_MVT_v16i8_rr(RetVT, Op0, Op1); |
10670 | 0 | case MVT::v4i16: return fastEmit_ISD_AVGFLOORU_MVT_v4i16_rr(RetVT, Op0, Op1); |
10671 | 0 | case MVT::v8i16: return fastEmit_ISD_AVGFLOORU_MVT_v8i16_rr(RetVT, Op0, Op1); |
10672 | 0 | case MVT::v2i32: return fastEmit_ISD_AVGFLOORU_MVT_v2i32_rr(RetVT, Op0, Op1); |
10673 | 0 | case MVT::v4i32: return fastEmit_ISD_AVGFLOORU_MVT_v4i32_rr(RetVT, Op0, Op1); |
10674 | 0 | default: return 0; |
10675 | 0 | } |
10676 | 0 | } |
10677 | | |
10678 | | // FastEmit functions for ISD::CONCAT_VECTORS. |
10679 | | |
10680 | 0 | unsigned fastEmit_ISD_CONCAT_VECTORS_MVT_nxv1i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10681 | 0 | if (RetVT.SimpleTy != MVT::nxv2i1) |
10682 | 0 | return 0; |
10683 | 0 | if ((Subtarget->hasSVEorSME())) { |
10684 | 0 | return fastEmitInst_rr(AArch64::UZP1_PPP_D, &AArch64::PPRRegClass, Op0, Op1); |
10685 | 0 | } |
10686 | 0 | return 0; |
10687 | 0 | } |
10688 | | |
10689 | 0 | unsigned fastEmit_ISD_CONCAT_VECTORS_MVT_nxv2i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10690 | 0 | if (RetVT.SimpleTy != MVT::nxv4i1) |
10691 | 0 | return 0; |
10692 | 0 | if ((Subtarget->hasSVEorSME())) { |
10693 | 0 | return fastEmitInst_rr(AArch64::UZP1_PPP_S, &AArch64::PPRRegClass, Op0, Op1); |
10694 | 0 | } |
10695 | 0 | return 0; |
10696 | 0 | } |
10697 | | |
10698 | 0 | unsigned fastEmit_ISD_CONCAT_VECTORS_MVT_nxv4i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10699 | 0 | if (RetVT.SimpleTy != MVT::nxv8i1) |
10700 | 0 | return 0; |
10701 | 0 | if ((Subtarget->hasSVEorSME())) { |
10702 | 0 | return fastEmitInst_rr(AArch64::UZP1_PPP_H, &AArch64::PPRRegClass, Op0, Op1); |
10703 | 0 | } |
10704 | 0 | return 0; |
10705 | 0 | } |
10706 | | |
10707 | 0 | unsigned fastEmit_ISD_CONCAT_VECTORS_MVT_nxv8i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10708 | 0 | if (RetVT.SimpleTy != MVT::nxv16i1) |
10709 | 0 | return 0; |
10710 | 0 | if ((Subtarget->hasSVEorSME())) { |
10711 | 0 | return fastEmitInst_rr(AArch64::UZP1_PPP_B, &AArch64::PPRRegClass, Op0, Op1); |
10712 | 0 | } |
10713 | 0 | return 0; |
10714 | 0 | } |
10715 | | |
10716 | 0 | unsigned fastEmit_ISD_CONCAT_VECTORS_MVT_nxv2f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10717 | 0 | if (RetVT.SimpleTy != MVT::nxv4f16) |
10718 | 0 | return 0; |
10719 | 0 | if ((Subtarget->hasSVEorSME())) { |
10720 | 0 | return fastEmitInst_rr(AArch64::UZP1_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
10721 | 0 | } |
10722 | 0 | return 0; |
10723 | 0 | } |
10724 | | |
10725 | 0 | unsigned fastEmit_ISD_CONCAT_VECTORS_MVT_nxv4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10726 | 0 | if (RetVT.SimpleTy != MVT::nxv8f16) |
10727 | 0 | return 0; |
10728 | 0 | if ((Subtarget->hasSVEorSME())) { |
10729 | 0 | return fastEmitInst_rr(AArch64::UZP1_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
10730 | 0 | } |
10731 | 0 | return 0; |
10732 | 0 | } |
10733 | | |
10734 | 0 | unsigned fastEmit_ISD_CONCAT_VECTORS_MVT_nxv2bf16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10735 | 0 | if (RetVT.SimpleTy != MVT::nxv4bf16) |
10736 | 0 | return 0; |
10737 | 0 | if ((Subtarget->hasSVEorSME())) { |
10738 | 0 | return fastEmitInst_rr(AArch64::UZP1_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
10739 | 0 | } |
10740 | 0 | return 0; |
10741 | 0 | } |
10742 | | |
10743 | 0 | unsigned fastEmit_ISD_CONCAT_VECTORS_MVT_nxv4bf16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10744 | 0 | if (RetVT.SimpleTy != MVT::nxv8bf16) |
10745 | 0 | return 0; |
10746 | 0 | if ((Subtarget->hasSVEorSME())) { |
10747 | 0 | return fastEmitInst_rr(AArch64::UZP1_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
10748 | 0 | } |
10749 | 0 | return 0; |
10750 | 0 | } |
10751 | | |
10752 | 0 | unsigned fastEmit_ISD_CONCAT_VECTORS_MVT_nxv2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10753 | 0 | if (RetVT.SimpleTy != MVT::nxv4f32) |
10754 | 0 | return 0; |
10755 | 0 | if ((Subtarget->hasSVEorSME())) { |
10756 | 0 | return fastEmitInst_rr(AArch64::UZP1_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
10757 | 0 | } |
10758 | 0 | return 0; |
10759 | 0 | } |
10760 | | |
10761 | 0 | unsigned fastEmit_ISD_CONCAT_VECTORS_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
10762 | 0 | switch (VT.SimpleTy) { |
10763 | 0 | case MVT::nxv1i1: return fastEmit_ISD_CONCAT_VECTORS_MVT_nxv1i1_rr(RetVT, Op0, Op1); |
10764 | 0 | case MVT::nxv2i1: return fastEmit_ISD_CONCAT_VECTORS_MVT_nxv2i1_rr(RetVT, Op0, Op1); |
10765 | 0 | case MVT::nxv4i1: return fastEmit_ISD_CONCAT_VECTORS_MVT_nxv4i1_rr(RetVT, Op0, Op1); |
10766 | 0 | case MVT::nxv8i1: return fastEmit_ISD_CONCAT_VECTORS_MVT_nxv8i1_rr(RetVT, Op0, Op1); |
10767 | 0 | case MVT::nxv2f16: return fastEmit_ISD_CONCAT_VECTORS_MVT_nxv2f16_rr(RetVT, Op0, Op1); |
10768 | 0 | case MVT::nxv4f16: return fastEmit_ISD_CONCAT_VECTORS_MVT_nxv4f16_rr(RetVT, Op0, Op1); |
10769 | 0 | case MVT::nxv2bf16: return fastEmit_ISD_CONCAT_VECTORS_MVT_nxv2bf16_rr(RetVT, Op0, Op1); |
10770 | 0 | case MVT::nxv4bf16: return fastEmit_ISD_CONCAT_VECTORS_MVT_nxv4bf16_rr(RetVT, Op0, Op1); |
10771 | 0 | case MVT::nxv2f32: return fastEmit_ISD_CONCAT_VECTORS_MVT_nxv2f32_rr(RetVT, Op0, Op1); |
10772 | 0 | default: return 0; |
10773 | 0 | } |
10774 | 0 | } |
10775 | | |
10776 | | // FastEmit functions for ISD::FADD. |
10777 | | |
10778 | 0 | unsigned fastEmit_ISD_FADD_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10779 | 0 | if (RetVT.SimpleTy != MVT::f16) |
10780 | 0 | return 0; |
10781 | 0 | if ((Subtarget->hasFullFP16())) { |
10782 | 0 | return fastEmitInst_rr(AArch64::FADDHrr, &AArch64::FPR16RegClass, Op0, Op1); |
10783 | 0 | } |
10784 | 0 | return 0; |
10785 | 0 | } |
10786 | | |
10787 | 0 | unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10788 | 0 | if (RetVT.SimpleTy != MVT::f32) |
10789 | 0 | return 0; |
10790 | 0 | if ((Subtarget->hasFPARMv8())) { |
10791 | 0 | return fastEmitInst_rr(AArch64::FADDSrr, &AArch64::FPR32RegClass, Op0, Op1); |
10792 | 0 | } |
10793 | 0 | return 0; |
10794 | 0 | } |
10795 | | |
10796 | 0 | unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10797 | 0 | if (RetVT.SimpleTy != MVT::f64) |
10798 | 0 | return 0; |
10799 | 0 | if ((Subtarget->hasFPARMv8())) { |
10800 | 0 | return fastEmitInst_rr(AArch64::FADDDrr, &AArch64::FPR64RegClass, Op0, Op1); |
10801 | 0 | } |
10802 | 0 | return 0; |
10803 | 0 | } |
10804 | | |
10805 | 0 | unsigned fastEmit_ISD_FADD_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10806 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
10807 | 0 | return 0; |
10808 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
10809 | 0 | return fastEmitInst_rr(AArch64::FADDv4f16, &AArch64::FPR64RegClass, Op0, Op1); |
10810 | 0 | } |
10811 | 0 | return 0; |
10812 | 0 | } |
10813 | | |
10814 | 0 | unsigned fastEmit_ISD_FADD_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10815 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
10816 | 0 | return 0; |
10817 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
10818 | 0 | return fastEmitInst_rr(AArch64::FADDv8f16, &AArch64::FPR128RegClass, Op0, Op1); |
10819 | 0 | } |
10820 | 0 | return 0; |
10821 | 0 | } |
10822 | | |
10823 | 0 | unsigned fastEmit_ISD_FADD_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10824 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
10825 | 0 | return 0; |
10826 | 0 | if ((Subtarget->hasNEON())) { |
10827 | 0 | return fastEmitInst_rr(AArch64::FADDv2f32, &AArch64::FPR64RegClass, Op0, Op1); |
10828 | 0 | } |
10829 | 0 | return 0; |
10830 | 0 | } |
10831 | | |
10832 | 0 | unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10833 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
10834 | 0 | return 0; |
10835 | 0 | if ((Subtarget->hasNEON())) { |
10836 | 0 | return fastEmitInst_rr(AArch64::FADDv4f32, &AArch64::FPR128RegClass, Op0, Op1); |
10837 | 0 | } |
10838 | 0 | return 0; |
10839 | 0 | } |
10840 | | |
10841 | 0 | unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10842 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
10843 | 0 | return 0; |
10844 | 0 | if ((Subtarget->hasNEON())) { |
10845 | 0 | return fastEmitInst_rr(AArch64::FADDv2f64, &AArch64::FPR128RegClass, Op0, Op1); |
10846 | 0 | } |
10847 | 0 | return 0; |
10848 | 0 | } |
10849 | | |
10850 | 0 | unsigned fastEmit_ISD_FADD_MVT_nxv8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10851 | 0 | if (RetVT.SimpleTy != MVT::nxv8f16) |
10852 | 0 | return 0; |
10853 | 0 | if ((Subtarget->hasSVEorSME())) { |
10854 | 0 | return fastEmitInst_rr(AArch64::FADD_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
10855 | 0 | } |
10856 | 0 | return 0; |
10857 | 0 | } |
10858 | | |
10859 | 0 | unsigned fastEmit_ISD_FADD_MVT_nxv8bf16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10860 | 0 | if (RetVT.SimpleTy != MVT::nxv8bf16) |
10861 | 0 | return 0; |
10862 | 0 | if ((Subtarget->hasB16B16()) && (Subtarget->hasSVE2() || Subtarget->hasSME2())) { |
10863 | 0 | return fastEmitInst_rr(AArch64::BFADD_ZZZ, &AArch64::ZPRRegClass, Op0, Op1); |
10864 | 0 | } |
10865 | 0 | return 0; |
10866 | 0 | } |
10867 | | |
10868 | 0 | unsigned fastEmit_ISD_FADD_MVT_nxv4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10869 | 0 | if (RetVT.SimpleTy != MVT::nxv4f32) |
10870 | 0 | return 0; |
10871 | 0 | if ((Subtarget->hasSVEorSME())) { |
10872 | 0 | return fastEmitInst_rr(AArch64::FADD_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
10873 | 0 | } |
10874 | 0 | return 0; |
10875 | 0 | } |
10876 | | |
10877 | 0 | unsigned fastEmit_ISD_FADD_MVT_nxv2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10878 | 0 | if (RetVT.SimpleTy != MVT::nxv2f64) |
10879 | 0 | return 0; |
10880 | 0 | if ((Subtarget->hasSVEorSME())) { |
10881 | 0 | return fastEmitInst_rr(AArch64::FADD_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
10882 | 0 | } |
10883 | 0 | return 0; |
10884 | 0 | } |
10885 | | |
10886 | 0 | unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
10887 | 0 | switch (VT.SimpleTy) { |
10888 | 0 | case MVT::f16: return fastEmit_ISD_FADD_MVT_f16_rr(RetVT, Op0, Op1); |
10889 | 0 | case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op1); |
10890 | 0 | case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op1); |
10891 | 0 | case MVT::v4f16: return fastEmit_ISD_FADD_MVT_v4f16_rr(RetVT, Op0, Op1); |
10892 | 0 | case MVT::v8f16: return fastEmit_ISD_FADD_MVT_v8f16_rr(RetVT, Op0, Op1); |
10893 | 0 | case MVT::v2f32: return fastEmit_ISD_FADD_MVT_v2f32_rr(RetVT, Op0, Op1); |
10894 | 0 | case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op1); |
10895 | 0 | case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op1); |
10896 | 0 | case MVT::nxv8f16: return fastEmit_ISD_FADD_MVT_nxv8f16_rr(RetVT, Op0, Op1); |
10897 | 0 | case MVT::nxv8bf16: return fastEmit_ISD_FADD_MVT_nxv8bf16_rr(RetVT, Op0, Op1); |
10898 | 0 | case MVT::nxv4f32: return fastEmit_ISD_FADD_MVT_nxv4f32_rr(RetVT, Op0, Op1); |
10899 | 0 | case MVT::nxv2f64: return fastEmit_ISD_FADD_MVT_nxv2f64_rr(RetVT, Op0, Op1); |
10900 | 0 | default: return 0; |
10901 | 0 | } |
10902 | 0 | } |
10903 | | |
10904 | | // FastEmit functions for ISD::FDIV. |
10905 | | |
10906 | 0 | unsigned fastEmit_ISD_FDIV_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10907 | 0 | if (RetVT.SimpleTy != MVT::f16) |
10908 | 0 | return 0; |
10909 | 0 | if ((Subtarget->hasFullFP16())) { |
10910 | 0 | return fastEmitInst_rr(AArch64::FDIVHrr, &AArch64::FPR16RegClass, Op0, Op1); |
10911 | 0 | } |
10912 | 0 | return 0; |
10913 | 0 | } |
10914 | | |
10915 | 0 | unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10916 | 0 | if (RetVT.SimpleTy != MVT::f32) |
10917 | 0 | return 0; |
10918 | 0 | if ((Subtarget->hasFPARMv8())) { |
10919 | 0 | return fastEmitInst_rr(AArch64::FDIVSrr, &AArch64::FPR32RegClass, Op0, Op1); |
10920 | 0 | } |
10921 | 0 | return 0; |
10922 | 0 | } |
10923 | | |
10924 | 0 | unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10925 | 0 | if (RetVT.SimpleTy != MVT::f64) |
10926 | 0 | return 0; |
10927 | 0 | if ((Subtarget->hasFPARMv8())) { |
10928 | 0 | return fastEmitInst_rr(AArch64::FDIVDrr, &AArch64::FPR64RegClass, Op0, Op1); |
10929 | 0 | } |
10930 | 0 | return 0; |
10931 | 0 | } |
10932 | | |
10933 | 0 | unsigned fastEmit_ISD_FDIV_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10934 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
10935 | 0 | return 0; |
10936 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
10937 | 0 | return fastEmitInst_rr(AArch64::FDIVv4f16, &AArch64::FPR64RegClass, Op0, Op1); |
10938 | 0 | } |
10939 | 0 | return 0; |
10940 | 0 | } |
10941 | | |
10942 | 0 | unsigned fastEmit_ISD_FDIV_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10943 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
10944 | 0 | return 0; |
10945 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
10946 | 0 | return fastEmitInst_rr(AArch64::FDIVv8f16, &AArch64::FPR128RegClass, Op0, Op1); |
10947 | 0 | } |
10948 | 0 | return 0; |
10949 | 0 | } |
10950 | | |
10951 | 0 | unsigned fastEmit_ISD_FDIV_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10952 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
10953 | 0 | return 0; |
10954 | 0 | if ((Subtarget->hasNEON())) { |
10955 | 0 | return fastEmitInst_rr(AArch64::FDIVv2f32, &AArch64::FPR64RegClass, Op0, Op1); |
10956 | 0 | } |
10957 | 0 | return 0; |
10958 | 0 | } |
10959 | | |
10960 | 0 | unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10961 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
10962 | 0 | return 0; |
10963 | 0 | if ((Subtarget->hasNEON())) { |
10964 | 0 | return fastEmitInst_rr(AArch64::FDIVv4f32, &AArch64::FPR128RegClass, Op0, Op1); |
10965 | 0 | } |
10966 | 0 | return 0; |
10967 | 0 | } |
10968 | | |
10969 | 0 | unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10970 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
10971 | 0 | return 0; |
10972 | 0 | if ((Subtarget->hasNEON())) { |
10973 | 0 | return fastEmitInst_rr(AArch64::FDIVv2f64, &AArch64::FPR128RegClass, Op0, Op1); |
10974 | 0 | } |
10975 | 0 | return 0; |
10976 | 0 | } |
10977 | | |
10978 | 0 | unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
10979 | 0 | switch (VT.SimpleTy) { |
10980 | 0 | case MVT::f16: return fastEmit_ISD_FDIV_MVT_f16_rr(RetVT, Op0, Op1); |
10981 | 0 | case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op1); |
10982 | 0 | case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op1); |
10983 | 0 | case MVT::v4f16: return fastEmit_ISD_FDIV_MVT_v4f16_rr(RetVT, Op0, Op1); |
10984 | 0 | case MVT::v8f16: return fastEmit_ISD_FDIV_MVT_v8f16_rr(RetVT, Op0, Op1); |
10985 | 0 | case MVT::v2f32: return fastEmit_ISD_FDIV_MVT_v2f32_rr(RetVT, Op0, Op1); |
10986 | 0 | case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1); |
10987 | 0 | case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1); |
10988 | 0 | default: return 0; |
10989 | 0 | } |
10990 | 0 | } |
10991 | | |
10992 | | // FastEmit functions for ISD::FMAXIMUM. |
10993 | | |
10994 | 0 | unsigned fastEmit_ISD_FMAXIMUM_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
10995 | 0 | if (RetVT.SimpleTy != MVT::f16) |
10996 | 0 | return 0; |
10997 | 0 | if ((Subtarget->hasFullFP16())) { |
10998 | 0 | return fastEmitInst_rr(AArch64::FMAXHrr, &AArch64::FPR16RegClass, Op0, Op1); |
10999 | 0 | } |
11000 | 0 | return 0; |
11001 | 0 | } |
11002 | | |
11003 | 0 | unsigned fastEmit_ISD_FMAXIMUM_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11004 | 0 | if (RetVT.SimpleTy != MVT::f32) |
11005 | 0 | return 0; |
11006 | 0 | if ((Subtarget->hasFPARMv8())) { |
11007 | 0 | return fastEmitInst_rr(AArch64::FMAXSrr, &AArch64::FPR32RegClass, Op0, Op1); |
11008 | 0 | } |
11009 | 0 | return 0; |
11010 | 0 | } |
11011 | | |
11012 | 0 | unsigned fastEmit_ISD_FMAXIMUM_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11013 | 0 | if (RetVT.SimpleTy != MVT::f64) |
11014 | 0 | return 0; |
11015 | 0 | if ((Subtarget->hasFPARMv8())) { |
11016 | 0 | return fastEmitInst_rr(AArch64::FMAXDrr, &AArch64::FPR64RegClass, Op0, Op1); |
11017 | 0 | } |
11018 | 0 | return 0; |
11019 | 0 | } |
11020 | | |
11021 | 0 | unsigned fastEmit_ISD_FMAXIMUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11022 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
11023 | 0 | return 0; |
11024 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
11025 | 0 | return fastEmitInst_rr(AArch64::FMAXv4f16, &AArch64::FPR64RegClass, Op0, Op1); |
11026 | 0 | } |
11027 | 0 | return 0; |
11028 | 0 | } |
11029 | | |
11030 | 0 | unsigned fastEmit_ISD_FMAXIMUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11031 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
11032 | 0 | return 0; |
11033 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
11034 | 0 | return fastEmitInst_rr(AArch64::FMAXv8f16, &AArch64::FPR128RegClass, Op0, Op1); |
11035 | 0 | } |
11036 | 0 | return 0; |
11037 | 0 | } |
11038 | | |
11039 | 0 | unsigned fastEmit_ISD_FMAXIMUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11040 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
11041 | 0 | return 0; |
11042 | 0 | if ((Subtarget->hasNEON())) { |
11043 | 0 | return fastEmitInst_rr(AArch64::FMAXv2f32, &AArch64::FPR64RegClass, Op0, Op1); |
11044 | 0 | } |
11045 | 0 | return 0; |
11046 | 0 | } |
11047 | | |
11048 | 0 | unsigned fastEmit_ISD_FMAXIMUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11049 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
11050 | 0 | return 0; |
11051 | 0 | if ((Subtarget->hasNEON())) { |
11052 | 0 | return fastEmitInst_rr(AArch64::FMAXv4f32, &AArch64::FPR128RegClass, Op0, Op1); |
11053 | 0 | } |
11054 | 0 | return 0; |
11055 | 0 | } |
11056 | | |
11057 | 0 | unsigned fastEmit_ISD_FMAXIMUM_MVT_v1f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11058 | 0 | if (RetVT.SimpleTy != MVT::v1f64) |
11059 | 0 | return 0; |
11060 | 0 | return fastEmitInst_rr(AArch64::FMAXDrr, &AArch64::FPR64RegClass, Op0, Op1); |
11061 | 0 | } |
11062 | | |
11063 | 0 | unsigned fastEmit_ISD_FMAXIMUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11064 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
11065 | 0 | return 0; |
11066 | 0 | if ((Subtarget->hasNEON())) { |
11067 | 0 | return fastEmitInst_rr(AArch64::FMAXv2f64, &AArch64::FPR128RegClass, Op0, Op1); |
11068 | 0 | } |
11069 | 0 | return 0; |
11070 | 0 | } |
11071 | | |
11072 | 0 | unsigned fastEmit_ISD_FMAXIMUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
11073 | 0 | switch (VT.SimpleTy) { |
11074 | 0 | case MVT::f16: return fastEmit_ISD_FMAXIMUM_MVT_f16_rr(RetVT, Op0, Op1); |
11075 | 0 | case MVT::f32: return fastEmit_ISD_FMAXIMUM_MVT_f32_rr(RetVT, Op0, Op1); |
11076 | 0 | case MVT::f64: return fastEmit_ISD_FMAXIMUM_MVT_f64_rr(RetVT, Op0, Op1); |
11077 | 0 | case MVT::v4f16: return fastEmit_ISD_FMAXIMUM_MVT_v4f16_rr(RetVT, Op0, Op1); |
11078 | 0 | case MVT::v8f16: return fastEmit_ISD_FMAXIMUM_MVT_v8f16_rr(RetVT, Op0, Op1); |
11079 | 0 | case MVT::v2f32: return fastEmit_ISD_FMAXIMUM_MVT_v2f32_rr(RetVT, Op0, Op1); |
11080 | 0 | case MVT::v4f32: return fastEmit_ISD_FMAXIMUM_MVT_v4f32_rr(RetVT, Op0, Op1); |
11081 | 0 | case MVT::v1f64: return fastEmit_ISD_FMAXIMUM_MVT_v1f64_rr(RetVT, Op0, Op1); |
11082 | 0 | case MVT::v2f64: return fastEmit_ISD_FMAXIMUM_MVT_v2f64_rr(RetVT, Op0, Op1); |
11083 | 0 | default: return 0; |
11084 | 0 | } |
11085 | 0 | } |
11086 | | |
11087 | | // FastEmit functions for ISD::FMAXNUM. |
11088 | | |
11089 | 0 | unsigned fastEmit_ISD_FMAXNUM_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11090 | 0 | if (RetVT.SimpleTy != MVT::f16) |
11091 | 0 | return 0; |
11092 | 0 | if ((Subtarget->hasFullFP16())) { |
11093 | 0 | return fastEmitInst_rr(AArch64::FMAXNMHrr, &AArch64::FPR16RegClass, Op0, Op1); |
11094 | 0 | } |
11095 | 0 | return 0; |
11096 | 0 | } |
11097 | | |
11098 | 0 | unsigned fastEmit_ISD_FMAXNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11099 | 0 | if (RetVT.SimpleTy != MVT::f32) |
11100 | 0 | return 0; |
11101 | 0 | if ((Subtarget->hasFPARMv8())) { |
11102 | 0 | return fastEmitInst_rr(AArch64::FMAXNMSrr, &AArch64::FPR32RegClass, Op0, Op1); |
11103 | 0 | } |
11104 | 0 | return 0; |
11105 | 0 | } |
11106 | | |
11107 | 0 | unsigned fastEmit_ISD_FMAXNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11108 | 0 | if (RetVT.SimpleTy != MVT::f64) |
11109 | 0 | return 0; |
11110 | 0 | if ((Subtarget->hasFPARMv8())) { |
11111 | 0 | return fastEmitInst_rr(AArch64::FMAXNMDrr, &AArch64::FPR64RegClass, Op0, Op1); |
11112 | 0 | } |
11113 | 0 | return 0; |
11114 | 0 | } |
11115 | | |
11116 | 0 | unsigned fastEmit_ISD_FMAXNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11117 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
11118 | 0 | return 0; |
11119 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
11120 | 0 | return fastEmitInst_rr(AArch64::FMAXNMv4f16, &AArch64::FPR64RegClass, Op0, Op1); |
11121 | 0 | } |
11122 | 0 | return 0; |
11123 | 0 | } |
11124 | | |
11125 | 0 | unsigned fastEmit_ISD_FMAXNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11126 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
11127 | 0 | return 0; |
11128 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
11129 | 0 | return fastEmitInst_rr(AArch64::FMAXNMv8f16, &AArch64::FPR128RegClass, Op0, Op1); |
11130 | 0 | } |
11131 | 0 | return 0; |
11132 | 0 | } |
11133 | | |
11134 | 0 | unsigned fastEmit_ISD_FMAXNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11135 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
11136 | 0 | return 0; |
11137 | 0 | if ((Subtarget->hasNEON())) { |
11138 | 0 | return fastEmitInst_rr(AArch64::FMAXNMv2f32, &AArch64::FPR64RegClass, Op0, Op1); |
11139 | 0 | } |
11140 | 0 | return 0; |
11141 | 0 | } |
11142 | | |
11143 | 0 | unsigned fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11144 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
11145 | 0 | return 0; |
11146 | 0 | if ((Subtarget->hasNEON())) { |
11147 | 0 | return fastEmitInst_rr(AArch64::FMAXNMv4f32, &AArch64::FPR128RegClass, Op0, Op1); |
11148 | 0 | } |
11149 | 0 | return 0; |
11150 | 0 | } |
11151 | | |
11152 | 0 | unsigned fastEmit_ISD_FMAXNUM_MVT_v1f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11153 | 0 | if (RetVT.SimpleTy != MVT::v1f64) |
11154 | 0 | return 0; |
11155 | 0 | return fastEmitInst_rr(AArch64::FMAXNMDrr, &AArch64::FPR64RegClass, Op0, Op1); |
11156 | 0 | } |
11157 | | |
11158 | 0 | unsigned fastEmit_ISD_FMAXNUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11159 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
11160 | 0 | return 0; |
11161 | 0 | if ((Subtarget->hasNEON())) { |
11162 | 0 | return fastEmitInst_rr(AArch64::FMAXNMv2f64, &AArch64::FPR128RegClass, Op0, Op1); |
11163 | 0 | } |
11164 | 0 | return 0; |
11165 | 0 | } |
11166 | | |
11167 | 0 | unsigned fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
11168 | 0 | switch (VT.SimpleTy) { |
11169 | 0 | case MVT::f16: return fastEmit_ISD_FMAXNUM_MVT_f16_rr(RetVT, Op0, Op1); |
11170 | 0 | case MVT::f32: return fastEmit_ISD_FMAXNUM_MVT_f32_rr(RetVT, Op0, Op1); |
11171 | 0 | case MVT::f64: return fastEmit_ISD_FMAXNUM_MVT_f64_rr(RetVT, Op0, Op1); |
11172 | 0 | case MVT::v4f16: return fastEmit_ISD_FMAXNUM_MVT_v4f16_rr(RetVT, Op0, Op1); |
11173 | 0 | case MVT::v8f16: return fastEmit_ISD_FMAXNUM_MVT_v8f16_rr(RetVT, Op0, Op1); |
11174 | 0 | case MVT::v2f32: return fastEmit_ISD_FMAXNUM_MVT_v2f32_rr(RetVT, Op0, Op1); |
11175 | 0 | case MVT::v4f32: return fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op1); |
11176 | 0 | case MVT::v1f64: return fastEmit_ISD_FMAXNUM_MVT_v1f64_rr(RetVT, Op0, Op1); |
11177 | 0 | case MVT::v2f64: return fastEmit_ISD_FMAXNUM_MVT_v2f64_rr(RetVT, Op0, Op1); |
11178 | 0 | default: return 0; |
11179 | 0 | } |
11180 | 0 | } |
11181 | | |
11182 | | // FastEmit functions for ISD::FMINIMUM. |
11183 | | |
11184 | 0 | unsigned fastEmit_ISD_FMINIMUM_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11185 | 0 | if (RetVT.SimpleTy != MVT::f16) |
11186 | 0 | return 0; |
11187 | 0 | if ((Subtarget->hasFullFP16())) { |
11188 | 0 | return fastEmitInst_rr(AArch64::FMINHrr, &AArch64::FPR16RegClass, Op0, Op1); |
11189 | 0 | } |
11190 | 0 | return 0; |
11191 | 0 | } |
11192 | | |
11193 | 0 | unsigned fastEmit_ISD_FMINIMUM_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11194 | 0 | if (RetVT.SimpleTy != MVT::f32) |
11195 | 0 | return 0; |
11196 | 0 | if ((Subtarget->hasFPARMv8())) { |
11197 | 0 | return fastEmitInst_rr(AArch64::FMINSrr, &AArch64::FPR32RegClass, Op0, Op1); |
11198 | 0 | } |
11199 | 0 | return 0; |
11200 | 0 | } |
11201 | | |
11202 | 0 | unsigned fastEmit_ISD_FMINIMUM_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11203 | 0 | if (RetVT.SimpleTy != MVT::f64) |
11204 | 0 | return 0; |
11205 | 0 | if ((Subtarget->hasFPARMv8())) { |
11206 | 0 | return fastEmitInst_rr(AArch64::FMINDrr, &AArch64::FPR64RegClass, Op0, Op1); |
11207 | 0 | } |
11208 | 0 | return 0; |
11209 | 0 | } |
11210 | | |
11211 | 0 | unsigned fastEmit_ISD_FMINIMUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11212 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
11213 | 0 | return 0; |
11214 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
11215 | 0 | return fastEmitInst_rr(AArch64::FMINv4f16, &AArch64::FPR64RegClass, Op0, Op1); |
11216 | 0 | } |
11217 | 0 | return 0; |
11218 | 0 | } |
11219 | | |
11220 | 0 | unsigned fastEmit_ISD_FMINIMUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11221 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
11222 | 0 | return 0; |
11223 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
11224 | 0 | return fastEmitInst_rr(AArch64::FMINv8f16, &AArch64::FPR128RegClass, Op0, Op1); |
11225 | 0 | } |
11226 | 0 | return 0; |
11227 | 0 | } |
11228 | | |
11229 | 0 | unsigned fastEmit_ISD_FMINIMUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11230 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
11231 | 0 | return 0; |
11232 | 0 | if ((Subtarget->hasNEON())) { |
11233 | 0 | return fastEmitInst_rr(AArch64::FMINv2f32, &AArch64::FPR64RegClass, Op0, Op1); |
11234 | 0 | } |
11235 | 0 | return 0; |
11236 | 0 | } |
11237 | | |
11238 | 0 | unsigned fastEmit_ISD_FMINIMUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11239 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
11240 | 0 | return 0; |
11241 | 0 | if ((Subtarget->hasNEON())) { |
11242 | 0 | return fastEmitInst_rr(AArch64::FMINv4f32, &AArch64::FPR128RegClass, Op0, Op1); |
11243 | 0 | } |
11244 | 0 | return 0; |
11245 | 0 | } |
11246 | | |
11247 | 0 | unsigned fastEmit_ISD_FMINIMUM_MVT_v1f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11248 | 0 | if (RetVT.SimpleTy != MVT::v1f64) |
11249 | 0 | return 0; |
11250 | 0 | return fastEmitInst_rr(AArch64::FMINDrr, &AArch64::FPR64RegClass, Op0, Op1); |
11251 | 0 | } |
11252 | | |
11253 | 0 | unsigned fastEmit_ISD_FMINIMUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11254 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
11255 | 0 | return 0; |
11256 | 0 | if ((Subtarget->hasNEON())) { |
11257 | 0 | return fastEmitInst_rr(AArch64::FMINv2f64, &AArch64::FPR128RegClass, Op0, Op1); |
11258 | 0 | } |
11259 | 0 | return 0; |
11260 | 0 | } |
11261 | | |
11262 | 0 | unsigned fastEmit_ISD_FMINIMUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
11263 | 0 | switch (VT.SimpleTy) { |
11264 | 0 | case MVT::f16: return fastEmit_ISD_FMINIMUM_MVT_f16_rr(RetVT, Op0, Op1); |
11265 | 0 | case MVT::f32: return fastEmit_ISD_FMINIMUM_MVT_f32_rr(RetVT, Op0, Op1); |
11266 | 0 | case MVT::f64: return fastEmit_ISD_FMINIMUM_MVT_f64_rr(RetVT, Op0, Op1); |
11267 | 0 | case MVT::v4f16: return fastEmit_ISD_FMINIMUM_MVT_v4f16_rr(RetVT, Op0, Op1); |
11268 | 0 | case MVT::v8f16: return fastEmit_ISD_FMINIMUM_MVT_v8f16_rr(RetVT, Op0, Op1); |
11269 | 0 | case MVT::v2f32: return fastEmit_ISD_FMINIMUM_MVT_v2f32_rr(RetVT, Op0, Op1); |
11270 | 0 | case MVT::v4f32: return fastEmit_ISD_FMINIMUM_MVT_v4f32_rr(RetVT, Op0, Op1); |
11271 | 0 | case MVT::v1f64: return fastEmit_ISD_FMINIMUM_MVT_v1f64_rr(RetVT, Op0, Op1); |
11272 | 0 | case MVT::v2f64: return fastEmit_ISD_FMINIMUM_MVT_v2f64_rr(RetVT, Op0, Op1); |
11273 | 0 | default: return 0; |
11274 | 0 | } |
11275 | 0 | } |
11276 | | |
11277 | | // FastEmit functions for ISD::FMINNUM. |
11278 | | |
11279 | 0 | unsigned fastEmit_ISD_FMINNUM_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11280 | 0 | if (RetVT.SimpleTy != MVT::f16) |
11281 | 0 | return 0; |
11282 | 0 | if ((Subtarget->hasFullFP16())) { |
11283 | 0 | return fastEmitInst_rr(AArch64::FMINNMHrr, &AArch64::FPR16RegClass, Op0, Op1); |
11284 | 0 | } |
11285 | 0 | return 0; |
11286 | 0 | } |
11287 | | |
11288 | 0 | unsigned fastEmit_ISD_FMINNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11289 | 0 | if (RetVT.SimpleTy != MVT::f32) |
11290 | 0 | return 0; |
11291 | 0 | if ((Subtarget->hasFPARMv8())) { |
11292 | 0 | return fastEmitInst_rr(AArch64::FMINNMSrr, &AArch64::FPR32RegClass, Op0, Op1); |
11293 | 0 | } |
11294 | 0 | return 0; |
11295 | 0 | } |
11296 | | |
11297 | 0 | unsigned fastEmit_ISD_FMINNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11298 | 0 | if (RetVT.SimpleTy != MVT::f64) |
11299 | 0 | return 0; |
11300 | 0 | if ((Subtarget->hasFPARMv8())) { |
11301 | 0 | return fastEmitInst_rr(AArch64::FMINNMDrr, &AArch64::FPR64RegClass, Op0, Op1); |
11302 | 0 | } |
11303 | 0 | return 0; |
11304 | 0 | } |
11305 | | |
11306 | 0 | unsigned fastEmit_ISD_FMINNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11307 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
11308 | 0 | return 0; |
11309 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
11310 | 0 | return fastEmitInst_rr(AArch64::FMINNMv4f16, &AArch64::FPR64RegClass, Op0, Op1); |
11311 | 0 | } |
11312 | 0 | return 0; |
11313 | 0 | } |
11314 | | |
11315 | 0 | unsigned fastEmit_ISD_FMINNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11316 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
11317 | 0 | return 0; |
11318 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
11319 | 0 | return fastEmitInst_rr(AArch64::FMINNMv8f16, &AArch64::FPR128RegClass, Op0, Op1); |
11320 | 0 | } |
11321 | 0 | return 0; |
11322 | 0 | } |
11323 | | |
11324 | 0 | unsigned fastEmit_ISD_FMINNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11325 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
11326 | 0 | return 0; |
11327 | 0 | if ((Subtarget->hasNEON())) { |
11328 | 0 | return fastEmitInst_rr(AArch64::FMINNMv2f32, &AArch64::FPR64RegClass, Op0, Op1); |
11329 | 0 | } |
11330 | 0 | return 0; |
11331 | 0 | } |
11332 | | |
11333 | 0 | unsigned fastEmit_ISD_FMINNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11334 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
11335 | 0 | return 0; |
11336 | 0 | if ((Subtarget->hasNEON())) { |
11337 | 0 | return fastEmitInst_rr(AArch64::FMINNMv4f32, &AArch64::FPR128RegClass, Op0, Op1); |
11338 | 0 | } |
11339 | 0 | return 0; |
11340 | 0 | } |
11341 | | |
11342 | 0 | unsigned fastEmit_ISD_FMINNUM_MVT_v1f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11343 | 0 | if (RetVT.SimpleTy != MVT::v1f64) |
11344 | 0 | return 0; |
11345 | 0 | return fastEmitInst_rr(AArch64::FMINNMDrr, &AArch64::FPR64RegClass, Op0, Op1); |
11346 | 0 | } |
11347 | | |
11348 | 0 | unsigned fastEmit_ISD_FMINNUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11349 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
11350 | 0 | return 0; |
11351 | 0 | if ((Subtarget->hasNEON())) { |
11352 | 0 | return fastEmitInst_rr(AArch64::FMINNMv2f64, &AArch64::FPR128RegClass, Op0, Op1); |
11353 | 0 | } |
11354 | 0 | return 0; |
11355 | 0 | } |
11356 | | |
11357 | 0 | unsigned fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
11358 | 0 | switch (VT.SimpleTy) { |
11359 | 0 | case MVT::f16: return fastEmit_ISD_FMINNUM_MVT_f16_rr(RetVT, Op0, Op1); |
11360 | 0 | case MVT::f32: return fastEmit_ISD_FMINNUM_MVT_f32_rr(RetVT, Op0, Op1); |
11361 | 0 | case MVT::f64: return fastEmit_ISD_FMINNUM_MVT_f64_rr(RetVT, Op0, Op1); |
11362 | 0 | case MVT::v4f16: return fastEmit_ISD_FMINNUM_MVT_v4f16_rr(RetVT, Op0, Op1); |
11363 | 0 | case MVT::v8f16: return fastEmit_ISD_FMINNUM_MVT_v8f16_rr(RetVT, Op0, Op1); |
11364 | 0 | case MVT::v2f32: return fastEmit_ISD_FMINNUM_MVT_v2f32_rr(RetVT, Op0, Op1); |
11365 | 0 | case MVT::v4f32: return fastEmit_ISD_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op1); |
11366 | 0 | case MVT::v1f64: return fastEmit_ISD_FMINNUM_MVT_v1f64_rr(RetVT, Op0, Op1); |
11367 | 0 | case MVT::v2f64: return fastEmit_ISD_FMINNUM_MVT_v2f64_rr(RetVT, Op0, Op1); |
11368 | 0 | default: return 0; |
11369 | 0 | } |
11370 | 0 | } |
11371 | | |
11372 | | // FastEmit functions for ISD::FMUL. |
11373 | | |
11374 | 0 | unsigned fastEmit_ISD_FMUL_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11375 | 0 | if (RetVT.SimpleTy != MVT::f16) |
11376 | 0 | return 0; |
11377 | 0 | if ((Subtarget->hasFullFP16())) { |
11378 | 0 | return fastEmitInst_rr(AArch64::FMULHrr, &AArch64::FPR16RegClass, Op0, Op1); |
11379 | 0 | } |
11380 | 0 | return 0; |
11381 | 0 | } |
11382 | | |
11383 | 0 | unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11384 | 0 | if (RetVT.SimpleTy != MVT::f32) |
11385 | 0 | return 0; |
11386 | 0 | if ((Subtarget->hasFPARMv8())) { |
11387 | 0 | return fastEmitInst_rr(AArch64::FMULSrr, &AArch64::FPR32RegClass, Op0, Op1); |
11388 | 0 | } |
11389 | 0 | return 0; |
11390 | 0 | } |
11391 | | |
11392 | 0 | unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11393 | 0 | if (RetVT.SimpleTy != MVT::f64) |
11394 | 0 | return 0; |
11395 | 0 | if ((Subtarget->hasFPARMv8())) { |
11396 | 0 | return fastEmitInst_rr(AArch64::FMULDrr, &AArch64::FPR64RegClass, Op0, Op1); |
11397 | 0 | } |
11398 | 0 | return 0; |
11399 | 0 | } |
11400 | | |
11401 | 0 | unsigned fastEmit_ISD_FMUL_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11402 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
11403 | 0 | return 0; |
11404 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
11405 | 0 | return fastEmitInst_rr(AArch64::FMULv4f16, &AArch64::FPR64RegClass, Op0, Op1); |
11406 | 0 | } |
11407 | 0 | return 0; |
11408 | 0 | } |
11409 | | |
11410 | 0 | unsigned fastEmit_ISD_FMUL_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11411 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
11412 | 0 | return 0; |
11413 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
11414 | 0 | return fastEmitInst_rr(AArch64::FMULv8f16, &AArch64::FPR128RegClass, Op0, Op1); |
11415 | 0 | } |
11416 | 0 | return 0; |
11417 | 0 | } |
11418 | | |
11419 | 0 | unsigned fastEmit_ISD_FMUL_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11420 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
11421 | 0 | return 0; |
11422 | 0 | if ((Subtarget->hasNEON())) { |
11423 | 0 | return fastEmitInst_rr(AArch64::FMULv2f32, &AArch64::FPR64RegClass, Op0, Op1); |
11424 | 0 | } |
11425 | 0 | return 0; |
11426 | 0 | } |
11427 | | |
11428 | 0 | unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11429 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
11430 | 0 | return 0; |
11431 | 0 | if ((Subtarget->hasNEON())) { |
11432 | 0 | return fastEmitInst_rr(AArch64::FMULv4f32, &AArch64::FPR128RegClass, Op0, Op1); |
11433 | 0 | } |
11434 | 0 | return 0; |
11435 | 0 | } |
11436 | | |
11437 | 0 | unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11438 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
11439 | 0 | return 0; |
11440 | 0 | if ((Subtarget->hasNEON())) { |
11441 | 0 | return fastEmitInst_rr(AArch64::FMULv2f64, &AArch64::FPR128RegClass, Op0, Op1); |
11442 | 0 | } |
11443 | 0 | return 0; |
11444 | 0 | } |
11445 | | |
11446 | 0 | unsigned fastEmit_ISD_FMUL_MVT_nxv8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11447 | 0 | if (RetVT.SimpleTy != MVT::nxv8f16) |
11448 | 0 | return 0; |
11449 | 0 | if ((Subtarget->hasSVEorSME())) { |
11450 | 0 | return fastEmitInst_rr(AArch64::FMUL_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
11451 | 0 | } |
11452 | 0 | return 0; |
11453 | 0 | } |
11454 | | |
11455 | 0 | unsigned fastEmit_ISD_FMUL_MVT_nxv8bf16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11456 | 0 | if (RetVT.SimpleTy != MVT::nxv8bf16) |
11457 | 0 | return 0; |
11458 | 0 | if ((Subtarget->hasB16B16()) && (Subtarget->hasSVE2() || Subtarget->hasSME2())) { |
11459 | 0 | return fastEmitInst_rr(AArch64::BFMUL_ZZZ, &AArch64::ZPRRegClass, Op0, Op1); |
11460 | 0 | } |
11461 | 0 | return 0; |
11462 | 0 | } |
11463 | | |
11464 | 0 | unsigned fastEmit_ISD_FMUL_MVT_nxv4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11465 | 0 | if (RetVT.SimpleTy != MVT::nxv4f32) |
11466 | 0 | return 0; |
11467 | 0 | if ((Subtarget->hasSVEorSME())) { |
11468 | 0 | return fastEmitInst_rr(AArch64::FMUL_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
11469 | 0 | } |
11470 | 0 | return 0; |
11471 | 0 | } |
11472 | | |
11473 | 0 | unsigned fastEmit_ISD_FMUL_MVT_nxv2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11474 | 0 | if (RetVT.SimpleTy != MVT::nxv2f64) |
11475 | 0 | return 0; |
11476 | 0 | if ((Subtarget->hasSVEorSME())) { |
11477 | 0 | return fastEmitInst_rr(AArch64::FMUL_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
11478 | 0 | } |
11479 | 0 | return 0; |
11480 | 0 | } |
11481 | | |
11482 | 0 | unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
11483 | 0 | switch (VT.SimpleTy) { |
11484 | 0 | case MVT::f16: return fastEmit_ISD_FMUL_MVT_f16_rr(RetVT, Op0, Op1); |
11485 | 0 | case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op1); |
11486 | 0 | case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op1); |
11487 | 0 | case MVT::v4f16: return fastEmit_ISD_FMUL_MVT_v4f16_rr(RetVT, Op0, Op1); |
11488 | 0 | case MVT::v8f16: return fastEmit_ISD_FMUL_MVT_v8f16_rr(RetVT, Op0, Op1); |
11489 | 0 | case MVT::v2f32: return fastEmit_ISD_FMUL_MVT_v2f32_rr(RetVT, Op0, Op1); |
11490 | 0 | case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1); |
11491 | 0 | case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1); |
11492 | 0 | case MVT::nxv8f16: return fastEmit_ISD_FMUL_MVT_nxv8f16_rr(RetVT, Op0, Op1); |
11493 | 0 | case MVT::nxv8bf16: return fastEmit_ISD_FMUL_MVT_nxv8bf16_rr(RetVT, Op0, Op1); |
11494 | 0 | case MVT::nxv4f32: return fastEmit_ISD_FMUL_MVT_nxv4f32_rr(RetVT, Op0, Op1); |
11495 | 0 | case MVT::nxv2f64: return fastEmit_ISD_FMUL_MVT_nxv2f64_rr(RetVT, Op0, Op1); |
11496 | 0 | default: return 0; |
11497 | 0 | } |
11498 | 0 | } |
11499 | | |
11500 | | // FastEmit functions for ISD::FSUB. |
11501 | | |
11502 | 0 | unsigned fastEmit_ISD_FSUB_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11503 | 0 | if (RetVT.SimpleTy != MVT::f16) |
11504 | 0 | return 0; |
11505 | 0 | if ((Subtarget->hasFullFP16())) { |
11506 | 0 | return fastEmitInst_rr(AArch64::FSUBHrr, &AArch64::FPR16RegClass, Op0, Op1); |
11507 | 0 | } |
11508 | 0 | return 0; |
11509 | 0 | } |
11510 | | |
11511 | 0 | unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11512 | 0 | if (RetVT.SimpleTy != MVT::f32) |
11513 | 0 | return 0; |
11514 | 0 | if ((Subtarget->hasFPARMv8())) { |
11515 | 0 | return fastEmitInst_rr(AArch64::FSUBSrr, &AArch64::FPR32RegClass, Op0, Op1); |
11516 | 0 | } |
11517 | 0 | return 0; |
11518 | 0 | } |
11519 | | |
11520 | 0 | unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11521 | 0 | if (RetVT.SimpleTy != MVT::f64) |
11522 | 0 | return 0; |
11523 | 0 | if ((Subtarget->hasFPARMv8())) { |
11524 | 0 | return fastEmitInst_rr(AArch64::FSUBDrr, &AArch64::FPR64RegClass, Op0, Op1); |
11525 | 0 | } |
11526 | 0 | return 0; |
11527 | 0 | } |
11528 | | |
11529 | 0 | unsigned fastEmit_ISD_FSUB_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11530 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
11531 | 0 | return 0; |
11532 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
11533 | 0 | return fastEmitInst_rr(AArch64::FSUBv4f16, &AArch64::FPR64RegClass, Op0, Op1); |
11534 | 0 | } |
11535 | 0 | return 0; |
11536 | 0 | } |
11537 | | |
11538 | 0 | unsigned fastEmit_ISD_FSUB_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11539 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
11540 | 0 | return 0; |
11541 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
11542 | 0 | return fastEmitInst_rr(AArch64::FSUBv8f16, &AArch64::FPR128RegClass, Op0, Op1); |
11543 | 0 | } |
11544 | 0 | return 0; |
11545 | 0 | } |
11546 | | |
11547 | 0 | unsigned fastEmit_ISD_FSUB_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11548 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
11549 | 0 | return 0; |
11550 | 0 | if ((Subtarget->hasNEON())) { |
11551 | 0 | return fastEmitInst_rr(AArch64::FSUBv2f32, &AArch64::FPR64RegClass, Op0, Op1); |
11552 | 0 | } |
11553 | 0 | return 0; |
11554 | 0 | } |
11555 | | |
11556 | 0 | unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11557 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
11558 | 0 | return 0; |
11559 | 0 | if ((Subtarget->hasNEON())) { |
11560 | 0 | return fastEmitInst_rr(AArch64::FSUBv4f32, &AArch64::FPR128RegClass, Op0, Op1); |
11561 | 0 | } |
11562 | 0 | return 0; |
11563 | 0 | } |
11564 | | |
11565 | 0 | unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11566 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
11567 | 0 | return 0; |
11568 | 0 | if ((Subtarget->hasNEON())) { |
11569 | 0 | return fastEmitInst_rr(AArch64::FSUBv2f64, &AArch64::FPR128RegClass, Op0, Op1); |
11570 | 0 | } |
11571 | 0 | return 0; |
11572 | 0 | } |
11573 | | |
11574 | 0 | unsigned fastEmit_ISD_FSUB_MVT_nxv8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11575 | 0 | if (RetVT.SimpleTy != MVT::nxv8f16) |
11576 | 0 | return 0; |
11577 | 0 | if ((Subtarget->hasSVEorSME())) { |
11578 | 0 | return fastEmitInst_rr(AArch64::FSUB_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
11579 | 0 | } |
11580 | 0 | return 0; |
11581 | 0 | } |
11582 | | |
11583 | 0 | unsigned fastEmit_ISD_FSUB_MVT_nxv8bf16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11584 | 0 | if (RetVT.SimpleTy != MVT::nxv8bf16) |
11585 | 0 | return 0; |
11586 | 0 | if ((Subtarget->hasB16B16()) && (Subtarget->hasSVE2() || Subtarget->hasSME2())) { |
11587 | 0 | return fastEmitInst_rr(AArch64::BFSUB_ZZZ, &AArch64::ZPRRegClass, Op0, Op1); |
11588 | 0 | } |
11589 | 0 | return 0; |
11590 | 0 | } |
11591 | | |
11592 | 0 | unsigned fastEmit_ISD_FSUB_MVT_nxv4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11593 | 0 | if (RetVT.SimpleTy != MVT::nxv4f32) |
11594 | 0 | return 0; |
11595 | 0 | if ((Subtarget->hasSVEorSME())) { |
11596 | 0 | return fastEmitInst_rr(AArch64::FSUB_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
11597 | 0 | } |
11598 | 0 | return 0; |
11599 | 0 | } |
11600 | | |
11601 | 0 | unsigned fastEmit_ISD_FSUB_MVT_nxv2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11602 | 0 | if (RetVT.SimpleTy != MVT::nxv2f64) |
11603 | 0 | return 0; |
11604 | 0 | if ((Subtarget->hasSVEorSME())) { |
11605 | 0 | return fastEmitInst_rr(AArch64::FSUB_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
11606 | 0 | } |
11607 | 0 | return 0; |
11608 | 0 | } |
11609 | | |
11610 | 0 | unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
11611 | 0 | switch (VT.SimpleTy) { |
11612 | 0 | case MVT::f16: return fastEmit_ISD_FSUB_MVT_f16_rr(RetVT, Op0, Op1); |
11613 | 0 | case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op1); |
11614 | 0 | case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op1); |
11615 | 0 | case MVT::v4f16: return fastEmit_ISD_FSUB_MVT_v4f16_rr(RetVT, Op0, Op1); |
11616 | 0 | case MVT::v8f16: return fastEmit_ISD_FSUB_MVT_v8f16_rr(RetVT, Op0, Op1); |
11617 | 0 | case MVT::v2f32: return fastEmit_ISD_FSUB_MVT_v2f32_rr(RetVT, Op0, Op1); |
11618 | 0 | case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1); |
11619 | 0 | case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1); |
11620 | 0 | case MVT::nxv8f16: return fastEmit_ISD_FSUB_MVT_nxv8f16_rr(RetVT, Op0, Op1); |
11621 | 0 | case MVT::nxv8bf16: return fastEmit_ISD_FSUB_MVT_nxv8bf16_rr(RetVT, Op0, Op1); |
11622 | 0 | case MVT::nxv4f32: return fastEmit_ISD_FSUB_MVT_nxv4f32_rr(RetVT, Op0, Op1); |
11623 | 0 | case MVT::nxv2f64: return fastEmit_ISD_FSUB_MVT_nxv2f64_rr(RetVT, Op0, Op1); |
11624 | 0 | default: return 0; |
11625 | 0 | } |
11626 | 0 | } |
11627 | | |
11628 | | // FastEmit functions for ISD::MUL. |
11629 | | |
11630 | 0 | unsigned fastEmit_ISD_MUL_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11631 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
11632 | 0 | return 0; |
11633 | 0 | if ((Subtarget->hasNEON())) { |
11634 | 0 | return fastEmitInst_rr(AArch64::MULv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
11635 | 0 | } |
11636 | 0 | return 0; |
11637 | 0 | } |
11638 | | |
11639 | 0 | unsigned fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11640 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
11641 | 0 | return 0; |
11642 | 0 | if ((Subtarget->hasNEON())) { |
11643 | 0 | return fastEmitInst_rr(AArch64::MULv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
11644 | 0 | } |
11645 | 0 | return 0; |
11646 | 0 | } |
11647 | | |
11648 | 0 | unsigned fastEmit_ISD_MUL_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11649 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
11650 | 0 | return 0; |
11651 | 0 | if ((Subtarget->hasNEON())) { |
11652 | 0 | return fastEmitInst_rr(AArch64::MULv4i16, &AArch64::FPR64RegClass, Op0, Op1); |
11653 | 0 | } |
11654 | 0 | return 0; |
11655 | 0 | } |
11656 | | |
11657 | 0 | unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11658 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
11659 | 0 | return 0; |
11660 | 0 | if ((Subtarget->hasNEON())) { |
11661 | 0 | return fastEmitInst_rr(AArch64::MULv8i16, &AArch64::FPR128RegClass, Op0, Op1); |
11662 | 0 | } |
11663 | 0 | return 0; |
11664 | 0 | } |
11665 | | |
11666 | 0 | unsigned fastEmit_ISD_MUL_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11667 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
11668 | 0 | return 0; |
11669 | 0 | if ((Subtarget->hasNEON())) { |
11670 | 0 | return fastEmitInst_rr(AArch64::MULv2i32, &AArch64::FPR64RegClass, Op0, Op1); |
11671 | 0 | } |
11672 | 0 | return 0; |
11673 | 0 | } |
11674 | | |
11675 | 0 | unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11676 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
11677 | 0 | return 0; |
11678 | 0 | if ((Subtarget->hasNEON())) { |
11679 | 0 | return fastEmitInst_rr(AArch64::MULv4i32, &AArch64::FPR128RegClass, Op0, Op1); |
11680 | 0 | } |
11681 | 0 | return 0; |
11682 | 0 | } |
11683 | | |
11684 | 0 | unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
11685 | 0 | switch (VT.SimpleTy) { |
11686 | 0 | case MVT::v8i8: return fastEmit_ISD_MUL_MVT_v8i8_rr(RetVT, Op0, Op1); |
11687 | 0 | case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op1); |
11688 | 0 | case MVT::v4i16: return fastEmit_ISD_MUL_MVT_v4i16_rr(RetVT, Op0, Op1); |
11689 | 0 | case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op1); |
11690 | 0 | case MVT::v2i32: return fastEmit_ISD_MUL_MVT_v2i32_rr(RetVT, Op0, Op1); |
11691 | 0 | case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op1); |
11692 | 0 | default: return 0; |
11693 | 0 | } |
11694 | 0 | } |
11695 | | |
11696 | | // FastEmit functions for ISD::MULHS. |
11697 | | |
11698 | 0 | unsigned fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11699 | 0 | if (RetVT.SimpleTy != MVT::i64) |
11700 | 0 | return 0; |
11701 | 0 | return fastEmitInst_rr(AArch64::SMULHrr, &AArch64::GPR64RegClass, Op0, Op1); |
11702 | 0 | } |
11703 | | |
11704 | 0 | unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
11705 | 0 | switch (VT.SimpleTy) { |
11706 | 0 | case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op1); |
11707 | 0 | default: return 0; |
11708 | 0 | } |
11709 | 0 | } |
11710 | | |
11711 | | // FastEmit functions for ISD::MULHU. |
11712 | | |
11713 | 0 | unsigned fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11714 | 0 | if (RetVT.SimpleTy != MVT::i64) |
11715 | 0 | return 0; |
11716 | 0 | return fastEmitInst_rr(AArch64::UMULHrr, &AArch64::GPR64RegClass, Op0, Op1); |
11717 | 0 | } |
11718 | | |
11719 | 0 | unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
11720 | 0 | switch (VT.SimpleTy) { |
11721 | 0 | case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op1); |
11722 | 0 | default: return 0; |
11723 | 0 | } |
11724 | 0 | } |
11725 | | |
11726 | | // FastEmit functions for ISD::OR. |
11727 | | |
11728 | 0 | unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11729 | 0 | if (RetVT.SimpleTy != MVT::i32) |
11730 | 0 | return 0; |
11731 | 0 | return fastEmitInst_rr(AArch64::ORRWrr, &AArch64::GPR32RegClass, Op0, Op1); |
11732 | 0 | } |
11733 | | |
11734 | 0 | unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11735 | 0 | if (RetVT.SimpleTy != MVT::i64) |
11736 | 0 | return 0; |
11737 | 0 | return fastEmitInst_rr(AArch64::ORRXrr, &AArch64::GPR64RegClass, Op0, Op1); |
11738 | 0 | } |
11739 | | |
11740 | 0 | unsigned fastEmit_ISD_OR_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11741 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
11742 | 0 | return 0; |
11743 | 0 | if ((Subtarget->hasNEON())) { |
11744 | 0 | return fastEmitInst_rr(AArch64::ORRv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
11745 | 0 | } |
11746 | 0 | return 0; |
11747 | 0 | } |
11748 | | |
11749 | 0 | unsigned fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11750 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
11751 | 0 | return 0; |
11752 | 0 | if ((Subtarget->hasNEON())) { |
11753 | 0 | return fastEmitInst_rr(AArch64::ORRv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
11754 | 0 | } |
11755 | 0 | return 0; |
11756 | 0 | } |
11757 | | |
11758 | 0 | unsigned fastEmit_ISD_OR_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11759 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
11760 | 0 | return 0; |
11761 | 0 | if ((Subtarget->hasNEON())) { |
11762 | 0 | return fastEmitInst_rr(AArch64::ORRv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
11763 | 0 | } |
11764 | 0 | return 0; |
11765 | 0 | } |
11766 | | |
11767 | 0 | unsigned fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11768 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
11769 | 0 | return 0; |
11770 | 0 | if ((Subtarget->hasNEON())) { |
11771 | 0 | return fastEmitInst_rr(AArch64::ORRv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
11772 | 0 | } |
11773 | 0 | return 0; |
11774 | 0 | } |
11775 | | |
11776 | 0 | unsigned fastEmit_ISD_OR_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11777 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
11778 | 0 | return 0; |
11779 | 0 | if ((Subtarget->hasNEON())) { |
11780 | 0 | return fastEmitInst_rr(AArch64::ORRv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
11781 | 0 | } |
11782 | 0 | return 0; |
11783 | 0 | } |
11784 | | |
11785 | 0 | unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11786 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
11787 | 0 | return 0; |
11788 | 0 | if ((Subtarget->hasNEON())) { |
11789 | 0 | return fastEmitInst_rr(AArch64::ORRv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
11790 | 0 | } |
11791 | 0 | return 0; |
11792 | 0 | } |
11793 | | |
11794 | 0 | unsigned fastEmit_ISD_OR_MVT_v1i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11795 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
11796 | 0 | return 0; |
11797 | 0 | if ((Subtarget->hasNEON())) { |
11798 | 0 | return fastEmitInst_rr(AArch64::ORRv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
11799 | 0 | } |
11800 | 0 | return 0; |
11801 | 0 | } |
11802 | | |
11803 | 0 | unsigned fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11804 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
11805 | 0 | return 0; |
11806 | 0 | if ((Subtarget->hasNEON())) { |
11807 | 0 | return fastEmitInst_rr(AArch64::ORRv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
11808 | 0 | } |
11809 | 0 | return 0; |
11810 | 0 | } |
11811 | | |
11812 | 0 | unsigned fastEmit_ISD_OR_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11813 | 0 | if (RetVT.SimpleTy != MVT::nxv16i8) |
11814 | 0 | return 0; |
11815 | 0 | if ((Subtarget->hasSVEorSME())) { |
11816 | 0 | return fastEmitInst_rr(AArch64::ORR_ZZZ, &AArch64::ZPRRegClass, Op0, Op1); |
11817 | 0 | } |
11818 | 0 | return 0; |
11819 | 0 | } |
11820 | | |
11821 | 0 | unsigned fastEmit_ISD_OR_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11822 | 0 | if (RetVT.SimpleTy != MVT::nxv8i16) |
11823 | 0 | return 0; |
11824 | 0 | if ((Subtarget->hasSVEorSME())) { |
11825 | 0 | return fastEmitInst_rr(AArch64::ORR_ZZZ, &AArch64::ZPRRegClass, Op0, Op1); |
11826 | 0 | } |
11827 | 0 | return 0; |
11828 | 0 | } |
11829 | | |
11830 | 0 | unsigned fastEmit_ISD_OR_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11831 | 0 | if (RetVT.SimpleTy != MVT::nxv4i32) |
11832 | 0 | return 0; |
11833 | 0 | if ((Subtarget->hasSVEorSME())) { |
11834 | 0 | return fastEmitInst_rr(AArch64::ORR_ZZZ, &AArch64::ZPRRegClass, Op0, Op1); |
11835 | 0 | } |
11836 | 0 | return 0; |
11837 | 0 | } |
11838 | | |
11839 | 0 | unsigned fastEmit_ISD_OR_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11840 | 0 | if (RetVT.SimpleTy != MVT::nxv2i64) |
11841 | 0 | return 0; |
11842 | 0 | if ((Subtarget->hasSVEorSME())) { |
11843 | 0 | return fastEmitInst_rr(AArch64::ORR_ZZZ, &AArch64::ZPRRegClass, Op0, Op1); |
11844 | 0 | } |
11845 | 0 | return 0; |
11846 | 0 | } |
11847 | | |
11848 | 0 | unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
11849 | 0 | switch (VT.SimpleTy) { |
11850 | 0 | case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op1); |
11851 | 0 | case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op1); |
11852 | 0 | case MVT::v8i8: return fastEmit_ISD_OR_MVT_v8i8_rr(RetVT, Op0, Op1); |
11853 | 0 | case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op1); |
11854 | 0 | case MVT::v4i16: return fastEmit_ISD_OR_MVT_v4i16_rr(RetVT, Op0, Op1); |
11855 | 0 | case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op1); |
11856 | 0 | case MVT::v2i32: return fastEmit_ISD_OR_MVT_v2i32_rr(RetVT, Op0, Op1); |
11857 | 0 | case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op1); |
11858 | 0 | case MVT::v1i64: return fastEmit_ISD_OR_MVT_v1i64_rr(RetVT, Op0, Op1); |
11859 | 0 | case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op1); |
11860 | 0 | case MVT::nxv16i8: return fastEmit_ISD_OR_MVT_nxv16i8_rr(RetVT, Op0, Op1); |
11861 | 0 | case MVT::nxv8i16: return fastEmit_ISD_OR_MVT_nxv8i16_rr(RetVT, Op0, Op1); |
11862 | 0 | case MVT::nxv4i32: return fastEmit_ISD_OR_MVT_nxv4i32_rr(RetVT, Op0, Op1); |
11863 | 0 | case MVT::nxv2i64: return fastEmit_ISD_OR_MVT_nxv2i64_rr(RetVT, Op0, Op1); |
11864 | 0 | default: return 0; |
11865 | 0 | } |
11866 | 0 | } |
11867 | | |
11868 | | // FastEmit functions for ISD::ROTR. |
11869 | | |
11870 | 0 | unsigned fastEmit_ISD_ROTR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11871 | 0 | if (RetVT.SimpleTy != MVT::i64) |
11872 | 0 | return 0; |
11873 | 0 | return fastEmitInst_rr(AArch64::RORVXr, &AArch64::GPR64RegClass, Op0, Op1); |
11874 | 0 | } |
11875 | | |
11876 | 0 | unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
11877 | 0 | switch (VT.SimpleTy) { |
11878 | 0 | case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_rr(RetVT, Op0, Op1); |
11879 | 0 | default: return 0; |
11880 | 0 | } |
11881 | 0 | } |
11882 | | |
11883 | | // FastEmit functions for ISD::SADDSAT. |
11884 | | |
11885 | 0 | unsigned fastEmit_ISD_SADDSAT_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11886 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
11887 | 0 | return 0; |
11888 | 0 | if ((Subtarget->hasNEON())) { |
11889 | 0 | return fastEmitInst_rr(AArch64::SQADDv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
11890 | 0 | } |
11891 | 0 | return 0; |
11892 | 0 | } |
11893 | | |
11894 | 0 | unsigned fastEmit_ISD_SADDSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11895 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
11896 | 0 | return 0; |
11897 | 0 | if ((Subtarget->hasNEON())) { |
11898 | 0 | return fastEmitInst_rr(AArch64::SQADDv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
11899 | 0 | } |
11900 | 0 | return 0; |
11901 | 0 | } |
11902 | | |
11903 | 0 | unsigned fastEmit_ISD_SADDSAT_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11904 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
11905 | 0 | return 0; |
11906 | 0 | if ((Subtarget->hasNEON())) { |
11907 | 0 | return fastEmitInst_rr(AArch64::SQADDv4i16, &AArch64::FPR64RegClass, Op0, Op1); |
11908 | 0 | } |
11909 | 0 | return 0; |
11910 | 0 | } |
11911 | | |
11912 | 0 | unsigned fastEmit_ISD_SADDSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11913 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
11914 | 0 | return 0; |
11915 | 0 | if ((Subtarget->hasNEON())) { |
11916 | 0 | return fastEmitInst_rr(AArch64::SQADDv8i16, &AArch64::FPR128RegClass, Op0, Op1); |
11917 | 0 | } |
11918 | 0 | return 0; |
11919 | 0 | } |
11920 | | |
11921 | 0 | unsigned fastEmit_ISD_SADDSAT_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11922 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
11923 | 0 | return 0; |
11924 | 0 | if ((Subtarget->hasNEON())) { |
11925 | 0 | return fastEmitInst_rr(AArch64::SQADDv2i32, &AArch64::FPR64RegClass, Op0, Op1); |
11926 | 0 | } |
11927 | 0 | return 0; |
11928 | 0 | } |
11929 | | |
11930 | 0 | unsigned fastEmit_ISD_SADDSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11931 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
11932 | 0 | return 0; |
11933 | 0 | if ((Subtarget->hasNEON())) { |
11934 | 0 | return fastEmitInst_rr(AArch64::SQADDv4i32, &AArch64::FPR128RegClass, Op0, Op1); |
11935 | 0 | } |
11936 | 0 | return 0; |
11937 | 0 | } |
11938 | | |
11939 | 0 | unsigned fastEmit_ISD_SADDSAT_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11940 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
11941 | 0 | return 0; |
11942 | 0 | if ((Subtarget->hasNEON())) { |
11943 | 0 | return fastEmitInst_rr(AArch64::SQADDv2i64, &AArch64::FPR128RegClass, Op0, Op1); |
11944 | 0 | } |
11945 | 0 | return 0; |
11946 | 0 | } |
11947 | | |
11948 | 0 | unsigned fastEmit_ISD_SADDSAT_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11949 | 0 | if (RetVT.SimpleTy != MVT::nxv16i8) |
11950 | 0 | return 0; |
11951 | 0 | if ((Subtarget->hasSVEorSME())) { |
11952 | 0 | return fastEmitInst_rr(AArch64::SQADD_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op1); |
11953 | 0 | } |
11954 | 0 | return 0; |
11955 | 0 | } |
11956 | | |
11957 | 0 | unsigned fastEmit_ISD_SADDSAT_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11958 | 0 | if (RetVT.SimpleTy != MVT::nxv8i16) |
11959 | 0 | return 0; |
11960 | 0 | if ((Subtarget->hasSVEorSME())) { |
11961 | 0 | return fastEmitInst_rr(AArch64::SQADD_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
11962 | 0 | } |
11963 | 0 | return 0; |
11964 | 0 | } |
11965 | | |
11966 | 0 | unsigned fastEmit_ISD_SADDSAT_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11967 | 0 | if (RetVT.SimpleTy != MVT::nxv4i32) |
11968 | 0 | return 0; |
11969 | 0 | if ((Subtarget->hasSVEorSME())) { |
11970 | 0 | return fastEmitInst_rr(AArch64::SQADD_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
11971 | 0 | } |
11972 | 0 | return 0; |
11973 | 0 | } |
11974 | | |
11975 | 0 | unsigned fastEmit_ISD_SADDSAT_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
11976 | 0 | if (RetVT.SimpleTy != MVT::nxv2i64) |
11977 | 0 | return 0; |
11978 | 0 | if ((Subtarget->hasSVEorSME())) { |
11979 | 0 | return fastEmitInst_rr(AArch64::SQADD_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
11980 | 0 | } |
11981 | 0 | return 0; |
11982 | 0 | } |
11983 | | |
11984 | 0 | unsigned fastEmit_ISD_SADDSAT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
11985 | 0 | switch (VT.SimpleTy) { |
11986 | 0 | case MVT::v8i8: return fastEmit_ISD_SADDSAT_MVT_v8i8_rr(RetVT, Op0, Op1); |
11987 | 0 | case MVT::v16i8: return fastEmit_ISD_SADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1); |
11988 | 0 | case MVT::v4i16: return fastEmit_ISD_SADDSAT_MVT_v4i16_rr(RetVT, Op0, Op1); |
11989 | 0 | case MVT::v8i16: return fastEmit_ISD_SADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1); |
11990 | 0 | case MVT::v2i32: return fastEmit_ISD_SADDSAT_MVT_v2i32_rr(RetVT, Op0, Op1); |
11991 | 0 | case MVT::v4i32: return fastEmit_ISD_SADDSAT_MVT_v4i32_rr(RetVT, Op0, Op1); |
11992 | 0 | case MVT::v2i64: return fastEmit_ISD_SADDSAT_MVT_v2i64_rr(RetVT, Op0, Op1); |
11993 | 0 | case MVT::nxv16i8: return fastEmit_ISD_SADDSAT_MVT_nxv16i8_rr(RetVT, Op0, Op1); |
11994 | 0 | case MVT::nxv8i16: return fastEmit_ISD_SADDSAT_MVT_nxv8i16_rr(RetVT, Op0, Op1); |
11995 | 0 | case MVT::nxv4i32: return fastEmit_ISD_SADDSAT_MVT_nxv4i32_rr(RetVT, Op0, Op1); |
11996 | 0 | case MVT::nxv2i64: return fastEmit_ISD_SADDSAT_MVT_nxv2i64_rr(RetVT, Op0, Op1); |
11997 | 0 | default: return 0; |
11998 | 0 | } |
11999 | 0 | } |
12000 | | |
12001 | | // FastEmit functions for ISD::SDIV. |
12002 | | |
12003 | 0 | unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12004 | 0 | if (RetVT.SimpleTy != MVT::i32) |
12005 | 0 | return 0; |
12006 | 0 | return fastEmitInst_rr(AArch64::SDIVWr, &AArch64::GPR32RegClass, Op0, Op1); |
12007 | 0 | } |
12008 | | |
12009 | 0 | unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12010 | 0 | if (RetVT.SimpleTy != MVT::i64) |
12011 | 0 | return 0; |
12012 | 0 | return fastEmitInst_rr(AArch64::SDIVXr, &AArch64::GPR64RegClass, Op0, Op1); |
12013 | 0 | } |
12014 | | |
12015 | 0 | unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
12016 | 0 | switch (VT.SimpleTy) { |
12017 | 0 | case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op1); |
12018 | 0 | case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op1); |
12019 | 0 | default: return 0; |
12020 | 0 | } |
12021 | 0 | } |
12022 | | |
12023 | | // FastEmit functions for ISD::SHL. |
12024 | | |
12025 | 0 | unsigned fastEmit_ISD_SHL_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12026 | 0 | if (RetVT.SimpleTy != MVT::i64) |
12027 | 0 | return 0; |
12028 | 0 | return fastEmitInst_rr(AArch64::LSLVXr, &AArch64::GPR64RegClass, Op0, Op1); |
12029 | 0 | } |
12030 | | |
12031 | 0 | unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
12032 | 0 | switch (VT.SimpleTy) { |
12033 | 0 | case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_rr(RetVT, Op0, Op1); |
12034 | 0 | default: return 0; |
12035 | 0 | } |
12036 | 0 | } |
12037 | | |
12038 | | // FastEmit functions for ISD::SMAX. |
12039 | | |
12040 | 0 | unsigned fastEmit_ISD_SMAX_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12041 | 0 | if (RetVT.SimpleTy != MVT::i32) |
12042 | 0 | return 0; |
12043 | 0 | if ((Subtarget->hasCSSC())) { |
12044 | 0 | return fastEmitInst_rr(AArch64::SMAXWrr, &AArch64::GPR32RegClass, Op0, Op1); |
12045 | 0 | } |
12046 | 0 | return 0; |
12047 | 0 | } |
12048 | | |
12049 | 0 | unsigned fastEmit_ISD_SMAX_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12050 | 0 | if (RetVT.SimpleTy != MVT::i64) |
12051 | 0 | return 0; |
12052 | 0 | if ((Subtarget->hasCSSC())) { |
12053 | 0 | return fastEmitInst_rr(AArch64::SMAXXrr, &AArch64::GPR64RegClass, Op0, Op1); |
12054 | 0 | } |
12055 | 0 | return 0; |
12056 | 0 | } |
12057 | | |
12058 | 0 | unsigned fastEmit_ISD_SMAX_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12059 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
12060 | 0 | return 0; |
12061 | 0 | if ((Subtarget->hasNEON())) { |
12062 | 0 | return fastEmitInst_rr(AArch64::SMAXv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
12063 | 0 | } |
12064 | 0 | return 0; |
12065 | 0 | } |
12066 | | |
12067 | 0 | unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12068 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
12069 | 0 | return 0; |
12070 | 0 | if ((Subtarget->hasNEON())) { |
12071 | 0 | return fastEmitInst_rr(AArch64::SMAXv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
12072 | 0 | } |
12073 | 0 | return 0; |
12074 | 0 | } |
12075 | | |
12076 | 0 | unsigned fastEmit_ISD_SMAX_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12077 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
12078 | 0 | return 0; |
12079 | 0 | if ((Subtarget->hasNEON())) { |
12080 | 0 | return fastEmitInst_rr(AArch64::SMAXv4i16, &AArch64::FPR64RegClass, Op0, Op1); |
12081 | 0 | } |
12082 | 0 | return 0; |
12083 | 0 | } |
12084 | | |
12085 | 0 | unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12086 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
12087 | 0 | return 0; |
12088 | 0 | if ((Subtarget->hasNEON())) { |
12089 | 0 | return fastEmitInst_rr(AArch64::SMAXv8i16, &AArch64::FPR128RegClass, Op0, Op1); |
12090 | 0 | } |
12091 | 0 | return 0; |
12092 | 0 | } |
12093 | | |
12094 | 0 | unsigned fastEmit_ISD_SMAX_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12095 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
12096 | 0 | return 0; |
12097 | 0 | if ((Subtarget->hasNEON())) { |
12098 | 0 | return fastEmitInst_rr(AArch64::SMAXv2i32, &AArch64::FPR64RegClass, Op0, Op1); |
12099 | 0 | } |
12100 | 0 | return 0; |
12101 | 0 | } |
12102 | | |
12103 | 0 | unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12104 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
12105 | 0 | return 0; |
12106 | 0 | if ((Subtarget->hasNEON())) { |
12107 | 0 | return fastEmitInst_rr(AArch64::SMAXv4i32, &AArch64::FPR128RegClass, Op0, Op1); |
12108 | 0 | } |
12109 | 0 | return 0; |
12110 | 0 | } |
12111 | | |
12112 | 0 | unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
12113 | 0 | switch (VT.SimpleTy) { |
12114 | 0 | case MVT::i32: return fastEmit_ISD_SMAX_MVT_i32_rr(RetVT, Op0, Op1); |
12115 | 0 | case MVT::i64: return fastEmit_ISD_SMAX_MVT_i64_rr(RetVT, Op0, Op1); |
12116 | 0 | case MVT::v8i8: return fastEmit_ISD_SMAX_MVT_v8i8_rr(RetVT, Op0, Op1); |
12117 | 0 | case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op1); |
12118 | 0 | case MVT::v4i16: return fastEmit_ISD_SMAX_MVT_v4i16_rr(RetVT, Op0, Op1); |
12119 | 0 | case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op1); |
12120 | 0 | case MVT::v2i32: return fastEmit_ISD_SMAX_MVT_v2i32_rr(RetVT, Op0, Op1); |
12121 | 0 | case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op1); |
12122 | 0 | default: return 0; |
12123 | 0 | } |
12124 | 0 | } |
12125 | | |
12126 | | // FastEmit functions for ISD::SMIN. |
12127 | | |
12128 | 0 | unsigned fastEmit_ISD_SMIN_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12129 | 0 | if (RetVT.SimpleTy != MVT::i32) |
12130 | 0 | return 0; |
12131 | 0 | if ((Subtarget->hasCSSC())) { |
12132 | 0 | return fastEmitInst_rr(AArch64::SMINWrr, &AArch64::GPR32RegClass, Op0, Op1); |
12133 | 0 | } |
12134 | 0 | return 0; |
12135 | 0 | } |
12136 | | |
12137 | 0 | unsigned fastEmit_ISD_SMIN_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12138 | 0 | if (RetVT.SimpleTy != MVT::i64) |
12139 | 0 | return 0; |
12140 | 0 | if ((Subtarget->hasCSSC())) { |
12141 | 0 | return fastEmitInst_rr(AArch64::SMINXrr, &AArch64::GPR64RegClass, Op0, Op1); |
12142 | 0 | } |
12143 | 0 | return 0; |
12144 | 0 | } |
12145 | | |
12146 | 0 | unsigned fastEmit_ISD_SMIN_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12147 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
12148 | 0 | return 0; |
12149 | 0 | if ((Subtarget->hasNEON())) { |
12150 | 0 | return fastEmitInst_rr(AArch64::SMINv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
12151 | 0 | } |
12152 | 0 | return 0; |
12153 | 0 | } |
12154 | | |
12155 | 0 | unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12156 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
12157 | 0 | return 0; |
12158 | 0 | if ((Subtarget->hasNEON())) { |
12159 | 0 | return fastEmitInst_rr(AArch64::SMINv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
12160 | 0 | } |
12161 | 0 | return 0; |
12162 | 0 | } |
12163 | | |
12164 | 0 | unsigned fastEmit_ISD_SMIN_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12165 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
12166 | 0 | return 0; |
12167 | 0 | if ((Subtarget->hasNEON())) { |
12168 | 0 | return fastEmitInst_rr(AArch64::SMINv4i16, &AArch64::FPR64RegClass, Op0, Op1); |
12169 | 0 | } |
12170 | 0 | return 0; |
12171 | 0 | } |
12172 | | |
12173 | 0 | unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12174 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
12175 | 0 | return 0; |
12176 | 0 | if ((Subtarget->hasNEON())) { |
12177 | 0 | return fastEmitInst_rr(AArch64::SMINv8i16, &AArch64::FPR128RegClass, Op0, Op1); |
12178 | 0 | } |
12179 | 0 | return 0; |
12180 | 0 | } |
12181 | | |
12182 | 0 | unsigned fastEmit_ISD_SMIN_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12183 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
12184 | 0 | return 0; |
12185 | 0 | if ((Subtarget->hasNEON())) { |
12186 | 0 | return fastEmitInst_rr(AArch64::SMINv2i32, &AArch64::FPR64RegClass, Op0, Op1); |
12187 | 0 | } |
12188 | 0 | return 0; |
12189 | 0 | } |
12190 | | |
12191 | 0 | unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12192 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
12193 | 0 | return 0; |
12194 | 0 | if ((Subtarget->hasNEON())) { |
12195 | 0 | return fastEmitInst_rr(AArch64::SMINv4i32, &AArch64::FPR128RegClass, Op0, Op1); |
12196 | 0 | } |
12197 | 0 | return 0; |
12198 | 0 | } |
12199 | | |
12200 | 0 | unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
12201 | 0 | switch (VT.SimpleTy) { |
12202 | 0 | case MVT::i32: return fastEmit_ISD_SMIN_MVT_i32_rr(RetVT, Op0, Op1); |
12203 | 0 | case MVT::i64: return fastEmit_ISD_SMIN_MVT_i64_rr(RetVT, Op0, Op1); |
12204 | 0 | case MVT::v8i8: return fastEmit_ISD_SMIN_MVT_v8i8_rr(RetVT, Op0, Op1); |
12205 | 0 | case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op1); |
12206 | 0 | case MVT::v4i16: return fastEmit_ISD_SMIN_MVT_v4i16_rr(RetVT, Op0, Op1); |
12207 | 0 | case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op1); |
12208 | 0 | case MVT::v2i32: return fastEmit_ISD_SMIN_MVT_v2i32_rr(RetVT, Op0, Op1); |
12209 | 0 | case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op1); |
12210 | 0 | default: return 0; |
12211 | 0 | } |
12212 | 0 | } |
12213 | | |
12214 | | // FastEmit functions for ISD::SRA. |
12215 | | |
12216 | 0 | unsigned fastEmit_ISD_SRA_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12217 | 0 | if (RetVT.SimpleTy != MVT::i64) |
12218 | 0 | return 0; |
12219 | 0 | return fastEmitInst_rr(AArch64::ASRVXr, &AArch64::GPR64RegClass, Op0, Op1); |
12220 | 0 | } |
12221 | | |
12222 | 0 | unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
12223 | 0 | switch (VT.SimpleTy) { |
12224 | 0 | case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_rr(RetVT, Op0, Op1); |
12225 | 0 | default: return 0; |
12226 | 0 | } |
12227 | 0 | } |
12228 | | |
12229 | | // FastEmit functions for ISD::SRL. |
12230 | | |
12231 | 0 | unsigned fastEmit_ISD_SRL_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12232 | 0 | if (RetVT.SimpleTy != MVT::i64) |
12233 | 0 | return 0; |
12234 | 0 | return fastEmitInst_rr(AArch64::LSRVXr, &AArch64::GPR64RegClass, Op0, Op1); |
12235 | 0 | } |
12236 | | |
12237 | 0 | unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
12238 | 0 | switch (VT.SimpleTy) { |
12239 | 0 | case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_rr(RetVT, Op0, Op1); |
12240 | 0 | default: return 0; |
12241 | 0 | } |
12242 | 0 | } |
12243 | | |
12244 | | // FastEmit functions for ISD::SSUBSAT. |
12245 | | |
12246 | 0 | unsigned fastEmit_ISD_SSUBSAT_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12247 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
12248 | 0 | return 0; |
12249 | 0 | if ((Subtarget->hasNEON())) { |
12250 | 0 | return fastEmitInst_rr(AArch64::SQSUBv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
12251 | 0 | } |
12252 | 0 | return 0; |
12253 | 0 | } |
12254 | | |
12255 | 0 | unsigned fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12256 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
12257 | 0 | return 0; |
12258 | 0 | if ((Subtarget->hasNEON())) { |
12259 | 0 | return fastEmitInst_rr(AArch64::SQSUBv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
12260 | 0 | } |
12261 | 0 | return 0; |
12262 | 0 | } |
12263 | | |
12264 | 0 | unsigned fastEmit_ISD_SSUBSAT_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12265 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
12266 | 0 | return 0; |
12267 | 0 | if ((Subtarget->hasNEON())) { |
12268 | 0 | return fastEmitInst_rr(AArch64::SQSUBv4i16, &AArch64::FPR64RegClass, Op0, Op1); |
12269 | 0 | } |
12270 | 0 | return 0; |
12271 | 0 | } |
12272 | | |
12273 | 0 | unsigned fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12274 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
12275 | 0 | return 0; |
12276 | 0 | if ((Subtarget->hasNEON())) { |
12277 | 0 | return fastEmitInst_rr(AArch64::SQSUBv8i16, &AArch64::FPR128RegClass, Op0, Op1); |
12278 | 0 | } |
12279 | 0 | return 0; |
12280 | 0 | } |
12281 | | |
12282 | 0 | unsigned fastEmit_ISD_SSUBSAT_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12283 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
12284 | 0 | return 0; |
12285 | 0 | if ((Subtarget->hasNEON())) { |
12286 | 0 | return fastEmitInst_rr(AArch64::SQSUBv2i32, &AArch64::FPR64RegClass, Op0, Op1); |
12287 | 0 | } |
12288 | 0 | return 0; |
12289 | 0 | } |
12290 | | |
12291 | 0 | unsigned fastEmit_ISD_SSUBSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12292 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
12293 | 0 | return 0; |
12294 | 0 | if ((Subtarget->hasNEON())) { |
12295 | 0 | return fastEmitInst_rr(AArch64::SQSUBv4i32, &AArch64::FPR128RegClass, Op0, Op1); |
12296 | 0 | } |
12297 | 0 | return 0; |
12298 | 0 | } |
12299 | | |
12300 | 0 | unsigned fastEmit_ISD_SSUBSAT_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12301 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
12302 | 0 | return 0; |
12303 | 0 | if ((Subtarget->hasNEON())) { |
12304 | 0 | return fastEmitInst_rr(AArch64::SQSUBv2i64, &AArch64::FPR128RegClass, Op0, Op1); |
12305 | 0 | } |
12306 | 0 | return 0; |
12307 | 0 | } |
12308 | | |
12309 | 0 | unsigned fastEmit_ISD_SSUBSAT_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12310 | 0 | if (RetVT.SimpleTy != MVT::nxv16i8) |
12311 | 0 | return 0; |
12312 | 0 | if ((Subtarget->hasSVEorSME())) { |
12313 | 0 | return fastEmitInst_rr(AArch64::SQSUB_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op1); |
12314 | 0 | } |
12315 | 0 | return 0; |
12316 | 0 | } |
12317 | | |
12318 | 0 | unsigned fastEmit_ISD_SSUBSAT_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12319 | 0 | if (RetVT.SimpleTy != MVT::nxv8i16) |
12320 | 0 | return 0; |
12321 | 0 | if ((Subtarget->hasSVEorSME())) { |
12322 | 0 | return fastEmitInst_rr(AArch64::SQSUB_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
12323 | 0 | } |
12324 | 0 | return 0; |
12325 | 0 | } |
12326 | | |
12327 | 0 | unsigned fastEmit_ISD_SSUBSAT_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12328 | 0 | if (RetVT.SimpleTy != MVT::nxv4i32) |
12329 | 0 | return 0; |
12330 | 0 | if ((Subtarget->hasSVEorSME())) { |
12331 | 0 | return fastEmitInst_rr(AArch64::SQSUB_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
12332 | 0 | } |
12333 | 0 | return 0; |
12334 | 0 | } |
12335 | | |
12336 | 0 | unsigned fastEmit_ISD_SSUBSAT_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12337 | 0 | if (RetVT.SimpleTy != MVT::nxv2i64) |
12338 | 0 | return 0; |
12339 | 0 | if ((Subtarget->hasSVEorSME())) { |
12340 | 0 | return fastEmitInst_rr(AArch64::SQSUB_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
12341 | 0 | } |
12342 | 0 | return 0; |
12343 | 0 | } |
12344 | | |
12345 | 0 | unsigned fastEmit_ISD_SSUBSAT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
12346 | 0 | switch (VT.SimpleTy) { |
12347 | 0 | case MVT::v8i8: return fastEmit_ISD_SSUBSAT_MVT_v8i8_rr(RetVT, Op0, Op1); |
12348 | 0 | case MVT::v16i8: return fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(RetVT, Op0, Op1); |
12349 | 0 | case MVT::v4i16: return fastEmit_ISD_SSUBSAT_MVT_v4i16_rr(RetVT, Op0, Op1); |
12350 | 0 | case MVT::v8i16: return fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(RetVT, Op0, Op1); |
12351 | 0 | case MVT::v2i32: return fastEmit_ISD_SSUBSAT_MVT_v2i32_rr(RetVT, Op0, Op1); |
12352 | 0 | case MVT::v4i32: return fastEmit_ISD_SSUBSAT_MVT_v4i32_rr(RetVT, Op0, Op1); |
12353 | 0 | case MVT::v2i64: return fastEmit_ISD_SSUBSAT_MVT_v2i64_rr(RetVT, Op0, Op1); |
12354 | 0 | case MVT::nxv16i8: return fastEmit_ISD_SSUBSAT_MVT_nxv16i8_rr(RetVT, Op0, Op1); |
12355 | 0 | case MVT::nxv8i16: return fastEmit_ISD_SSUBSAT_MVT_nxv8i16_rr(RetVT, Op0, Op1); |
12356 | 0 | case MVT::nxv4i32: return fastEmit_ISD_SSUBSAT_MVT_nxv4i32_rr(RetVT, Op0, Op1); |
12357 | 0 | case MVT::nxv2i64: return fastEmit_ISD_SSUBSAT_MVT_nxv2i64_rr(RetVT, Op0, Op1); |
12358 | 0 | default: return 0; |
12359 | 0 | } |
12360 | 0 | } |
12361 | | |
12362 | | // FastEmit functions for ISD::STRICT_FADD. |
12363 | | |
12364 | 0 | unsigned fastEmit_ISD_STRICT_FADD_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12365 | 0 | if (RetVT.SimpleTy != MVT::f16) |
12366 | 0 | return 0; |
12367 | 0 | if ((Subtarget->hasFullFP16())) { |
12368 | 0 | return fastEmitInst_rr(AArch64::FADDHrr, &AArch64::FPR16RegClass, Op0, Op1); |
12369 | 0 | } |
12370 | 0 | return 0; |
12371 | 0 | } |
12372 | | |
12373 | 0 | unsigned fastEmit_ISD_STRICT_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12374 | 0 | if (RetVT.SimpleTy != MVT::f32) |
12375 | 0 | return 0; |
12376 | 0 | if ((Subtarget->hasFPARMv8())) { |
12377 | 0 | return fastEmitInst_rr(AArch64::FADDSrr, &AArch64::FPR32RegClass, Op0, Op1); |
12378 | 0 | } |
12379 | 0 | return 0; |
12380 | 0 | } |
12381 | | |
12382 | 0 | unsigned fastEmit_ISD_STRICT_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12383 | 0 | if (RetVT.SimpleTy != MVT::f64) |
12384 | 0 | return 0; |
12385 | 0 | if ((Subtarget->hasFPARMv8())) { |
12386 | 0 | return fastEmitInst_rr(AArch64::FADDDrr, &AArch64::FPR64RegClass, Op0, Op1); |
12387 | 0 | } |
12388 | 0 | return 0; |
12389 | 0 | } |
12390 | | |
12391 | 0 | unsigned fastEmit_ISD_STRICT_FADD_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12392 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
12393 | 0 | return 0; |
12394 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
12395 | 0 | return fastEmitInst_rr(AArch64::FADDv4f16, &AArch64::FPR64RegClass, Op0, Op1); |
12396 | 0 | } |
12397 | 0 | return 0; |
12398 | 0 | } |
12399 | | |
12400 | 0 | unsigned fastEmit_ISD_STRICT_FADD_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12401 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
12402 | 0 | return 0; |
12403 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
12404 | 0 | return fastEmitInst_rr(AArch64::FADDv8f16, &AArch64::FPR128RegClass, Op0, Op1); |
12405 | 0 | } |
12406 | 0 | return 0; |
12407 | 0 | } |
12408 | | |
12409 | 0 | unsigned fastEmit_ISD_STRICT_FADD_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12410 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
12411 | 0 | return 0; |
12412 | 0 | if ((Subtarget->hasNEON())) { |
12413 | 0 | return fastEmitInst_rr(AArch64::FADDv2f32, &AArch64::FPR64RegClass, Op0, Op1); |
12414 | 0 | } |
12415 | 0 | return 0; |
12416 | 0 | } |
12417 | | |
12418 | 0 | unsigned fastEmit_ISD_STRICT_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12419 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
12420 | 0 | return 0; |
12421 | 0 | if ((Subtarget->hasNEON())) { |
12422 | 0 | return fastEmitInst_rr(AArch64::FADDv4f32, &AArch64::FPR128RegClass, Op0, Op1); |
12423 | 0 | } |
12424 | 0 | return 0; |
12425 | 0 | } |
12426 | | |
12427 | 0 | unsigned fastEmit_ISD_STRICT_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12428 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
12429 | 0 | return 0; |
12430 | 0 | if ((Subtarget->hasNEON())) { |
12431 | 0 | return fastEmitInst_rr(AArch64::FADDv2f64, &AArch64::FPR128RegClass, Op0, Op1); |
12432 | 0 | } |
12433 | 0 | return 0; |
12434 | 0 | } |
12435 | | |
12436 | 0 | unsigned fastEmit_ISD_STRICT_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
12437 | 0 | switch (VT.SimpleTy) { |
12438 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_FADD_MVT_f16_rr(RetVT, Op0, Op1); |
12439 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FADD_MVT_f32_rr(RetVT, Op0, Op1); |
12440 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FADD_MVT_f64_rr(RetVT, Op0, Op1); |
12441 | 0 | case MVT::v4f16: return fastEmit_ISD_STRICT_FADD_MVT_v4f16_rr(RetVT, Op0, Op1); |
12442 | 0 | case MVT::v8f16: return fastEmit_ISD_STRICT_FADD_MVT_v8f16_rr(RetVT, Op0, Op1); |
12443 | 0 | case MVT::v2f32: return fastEmit_ISD_STRICT_FADD_MVT_v2f32_rr(RetVT, Op0, Op1); |
12444 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FADD_MVT_v4f32_rr(RetVT, Op0, Op1); |
12445 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FADD_MVT_v2f64_rr(RetVT, Op0, Op1); |
12446 | 0 | default: return 0; |
12447 | 0 | } |
12448 | 0 | } |
12449 | | |
12450 | | // FastEmit functions for ISD::STRICT_FDIV. |
12451 | | |
12452 | 0 | unsigned fastEmit_ISD_STRICT_FDIV_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12453 | 0 | if (RetVT.SimpleTy != MVT::f16) |
12454 | 0 | return 0; |
12455 | 0 | if ((Subtarget->hasFullFP16())) { |
12456 | 0 | return fastEmitInst_rr(AArch64::FDIVHrr, &AArch64::FPR16RegClass, Op0, Op1); |
12457 | 0 | } |
12458 | 0 | return 0; |
12459 | 0 | } |
12460 | | |
12461 | 0 | unsigned fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12462 | 0 | if (RetVT.SimpleTy != MVT::f32) |
12463 | 0 | return 0; |
12464 | 0 | if ((Subtarget->hasFPARMv8())) { |
12465 | 0 | return fastEmitInst_rr(AArch64::FDIVSrr, &AArch64::FPR32RegClass, Op0, Op1); |
12466 | 0 | } |
12467 | 0 | return 0; |
12468 | 0 | } |
12469 | | |
12470 | 0 | unsigned fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12471 | 0 | if (RetVT.SimpleTy != MVT::f64) |
12472 | 0 | return 0; |
12473 | 0 | if ((Subtarget->hasFPARMv8())) { |
12474 | 0 | return fastEmitInst_rr(AArch64::FDIVDrr, &AArch64::FPR64RegClass, Op0, Op1); |
12475 | 0 | } |
12476 | 0 | return 0; |
12477 | 0 | } |
12478 | | |
12479 | 0 | unsigned fastEmit_ISD_STRICT_FDIV_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12480 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
12481 | 0 | return 0; |
12482 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
12483 | 0 | return fastEmitInst_rr(AArch64::FDIVv4f16, &AArch64::FPR64RegClass, Op0, Op1); |
12484 | 0 | } |
12485 | 0 | return 0; |
12486 | 0 | } |
12487 | | |
12488 | 0 | unsigned fastEmit_ISD_STRICT_FDIV_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12489 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
12490 | 0 | return 0; |
12491 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
12492 | 0 | return fastEmitInst_rr(AArch64::FDIVv8f16, &AArch64::FPR128RegClass, Op0, Op1); |
12493 | 0 | } |
12494 | 0 | return 0; |
12495 | 0 | } |
12496 | | |
12497 | 0 | unsigned fastEmit_ISD_STRICT_FDIV_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12498 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
12499 | 0 | return 0; |
12500 | 0 | if ((Subtarget->hasNEON())) { |
12501 | 0 | return fastEmitInst_rr(AArch64::FDIVv2f32, &AArch64::FPR64RegClass, Op0, Op1); |
12502 | 0 | } |
12503 | 0 | return 0; |
12504 | 0 | } |
12505 | | |
12506 | 0 | unsigned fastEmit_ISD_STRICT_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12507 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
12508 | 0 | return 0; |
12509 | 0 | if ((Subtarget->hasNEON())) { |
12510 | 0 | return fastEmitInst_rr(AArch64::FDIVv4f32, &AArch64::FPR128RegClass, Op0, Op1); |
12511 | 0 | } |
12512 | 0 | return 0; |
12513 | 0 | } |
12514 | | |
12515 | 0 | unsigned fastEmit_ISD_STRICT_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12516 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
12517 | 0 | return 0; |
12518 | 0 | if ((Subtarget->hasNEON())) { |
12519 | 0 | return fastEmitInst_rr(AArch64::FDIVv2f64, &AArch64::FPR128RegClass, Op0, Op1); |
12520 | 0 | } |
12521 | 0 | return 0; |
12522 | 0 | } |
12523 | | |
12524 | 0 | unsigned fastEmit_ISD_STRICT_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
12525 | 0 | switch (VT.SimpleTy) { |
12526 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_FDIV_MVT_f16_rr(RetVT, Op0, Op1); |
12527 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(RetVT, Op0, Op1); |
12528 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(RetVT, Op0, Op1); |
12529 | 0 | case MVT::v4f16: return fastEmit_ISD_STRICT_FDIV_MVT_v4f16_rr(RetVT, Op0, Op1); |
12530 | 0 | case MVT::v8f16: return fastEmit_ISD_STRICT_FDIV_MVT_v8f16_rr(RetVT, Op0, Op1); |
12531 | 0 | case MVT::v2f32: return fastEmit_ISD_STRICT_FDIV_MVT_v2f32_rr(RetVT, Op0, Op1); |
12532 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1); |
12533 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1); |
12534 | 0 | default: return 0; |
12535 | 0 | } |
12536 | 0 | } |
12537 | | |
12538 | | // FastEmit functions for ISD::STRICT_FMAXIMUM. |
12539 | | |
12540 | 0 | unsigned fastEmit_ISD_STRICT_FMAXIMUM_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12541 | 0 | if (RetVT.SimpleTy != MVT::f16) |
12542 | 0 | return 0; |
12543 | 0 | if ((Subtarget->hasFullFP16())) { |
12544 | 0 | return fastEmitInst_rr(AArch64::FMAXHrr, &AArch64::FPR16RegClass, Op0, Op1); |
12545 | 0 | } |
12546 | 0 | return 0; |
12547 | 0 | } |
12548 | | |
12549 | 0 | unsigned fastEmit_ISD_STRICT_FMAXIMUM_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12550 | 0 | if (RetVT.SimpleTy != MVT::f32) |
12551 | 0 | return 0; |
12552 | 0 | if ((Subtarget->hasFPARMv8())) { |
12553 | 0 | return fastEmitInst_rr(AArch64::FMAXSrr, &AArch64::FPR32RegClass, Op0, Op1); |
12554 | 0 | } |
12555 | 0 | return 0; |
12556 | 0 | } |
12557 | | |
12558 | 0 | unsigned fastEmit_ISD_STRICT_FMAXIMUM_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12559 | 0 | if (RetVT.SimpleTy != MVT::f64) |
12560 | 0 | return 0; |
12561 | 0 | if ((Subtarget->hasFPARMv8())) { |
12562 | 0 | return fastEmitInst_rr(AArch64::FMAXDrr, &AArch64::FPR64RegClass, Op0, Op1); |
12563 | 0 | } |
12564 | 0 | return 0; |
12565 | 0 | } |
12566 | | |
12567 | 0 | unsigned fastEmit_ISD_STRICT_FMAXIMUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12568 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
12569 | 0 | return 0; |
12570 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
12571 | 0 | return fastEmitInst_rr(AArch64::FMAXv4f16, &AArch64::FPR64RegClass, Op0, Op1); |
12572 | 0 | } |
12573 | 0 | return 0; |
12574 | 0 | } |
12575 | | |
12576 | 0 | unsigned fastEmit_ISD_STRICT_FMAXIMUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12577 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
12578 | 0 | return 0; |
12579 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
12580 | 0 | return fastEmitInst_rr(AArch64::FMAXv8f16, &AArch64::FPR128RegClass, Op0, Op1); |
12581 | 0 | } |
12582 | 0 | return 0; |
12583 | 0 | } |
12584 | | |
12585 | 0 | unsigned fastEmit_ISD_STRICT_FMAXIMUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12586 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
12587 | 0 | return 0; |
12588 | 0 | if ((Subtarget->hasNEON())) { |
12589 | 0 | return fastEmitInst_rr(AArch64::FMAXv2f32, &AArch64::FPR64RegClass, Op0, Op1); |
12590 | 0 | } |
12591 | 0 | return 0; |
12592 | 0 | } |
12593 | | |
12594 | 0 | unsigned fastEmit_ISD_STRICT_FMAXIMUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12595 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
12596 | 0 | return 0; |
12597 | 0 | if ((Subtarget->hasNEON())) { |
12598 | 0 | return fastEmitInst_rr(AArch64::FMAXv4f32, &AArch64::FPR128RegClass, Op0, Op1); |
12599 | 0 | } |
12600 | 0 | return 0; |
12601 | 0 | } |
12602 | | |
12603 | 0 | unsigned fastEmit_ISD_STRICT_FMAXIMUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12604 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
12605 | 0 | return 0; |
12606 | 0 | if ((Subtarget->hasNEON())) { |
12607 | 0 | return fastEmitInst_rr(AArch64::FMAXv2f64, &AArch64::FPR128RegClass, Op0, Op1); |
12608 | 0 | } |
12609 | 0 | return 0; |
12610 | 0 | } |
12611 | | |
12612 | 0 | unsigned fastEmit_ISD_STRICT_FMAXIMUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
12613 | 0 | switch (VT.SimpleTy) { |
12614 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_FMAXIMUM_MVT_f16_rr(RetVT, Op0, Op1); |
12615 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FMAXIMUM_MVT_f32_rr(RetVT, Op0, Op1); |
12616 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FMAXIMUM_MVT_f64_rr(RetVT, Op0, Op1); |
12617 | 0 | case MVT::v4f16: return fastEmit_ISD_STRICT_FMAXIMUM_MVT_v4f16_rr(RetVT, Op0, Op1); |
12618 | 0 | case MVT::v8f16: return fastEmit_ISD_STRICT_FMAXIMUM_MVT_v8f16_rr(RetVT, Op0, Op1); |
12619 | 0 | case MVT::v2f32: return fastEmit_ISD_STRICT_FMAXIMUM_MVT_v2f32_rr(RetVT, Op0, Op1); |
12620 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FMAXIMUM_MVT_v4f32_rr(RetVT, Op0, Op1); |
12621 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FMAXIMUM_MVT_v2f64_rr(RetVT, Op0, Op1); |
12622 | 0 | default: return 0; |
12623 | 0 | } |
12624 | 0 | } |
12625 | | |
12626 | | // FastEmit functions for ISD::STRICT_FMAXNUM. |
12627 | | |
12628 | 0 | unsigned fastEmit_ISD_STRICT_FMAXNUM_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12629 | 0 | if (RetVT.SimpleTy != MVT::f16) |
12630 | 0 | return 0; |
12631 | 0 | if ((Subtarget->hasFullFP16())) { |
12632 | 0 | return fastEmitInst_rr(AArch64::FMAXNMHrr, &AArch64::FPR16RegClass, Op0, Op1); |
12633 | 0 | } |
12634 | 0 | return 0; |
12635 | 0 | } |
12636 | | |
12637 | 0 | unsigned fastEmit_ISD_STRICT_FMAXNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12638 | 0 | if (RetVT.SimpleTy != MVT::f32) |
12639 | 0 | return 0; |
12640 | 0 | if ((Subtarget->hasFPARMv8())) { |
12641 | 0 | return fastEmitInst_rr(AArch64::FMAXNMSrr, &AArch64::FPR32RegClass, Op0, Op1); |
12642 | 0 | } |
12643 | 0 | return 0; |
12644 | 0 | } |
12645 | | |
12646 | 0 | unsigned fastEmit_ISD_STRICT_FMAXNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12647 | 0 | if (RetVT.SimpleTy != MVT::f64) |
12648 | 0 | return 0; |
12649 | 0 | if ((Subtarget->hasFPARMv8())) { |
12650 | 0 | return fastEmitInst_rr(AArch64::FMAXNMDrr, &AArch64::FPR64RegClass, Op0, Op1); |
12651 | 0 | } |
12652 | 0 | return 0; |
12653 | 0 | } |
12654 | | |
12655 | 0 | unsigned fastEmit_ISD_STRICT_FMAXNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12656 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
12657 | 0 | return 0; |
12658 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
12659 | 0 | return fastEmitInst_rr(AArch64::FMAXNMv4f16, &AArch64::FPR64RegClass, Op0, Op1); |
12660 | 0 | } |
12661 | 0 | return 0; |
12662 | 0 | } |
12663 | | |
12664 | 0 | unsigned fastEmit_ISD_STRICT_FMAXNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12665 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
12666 | 0 | return 0; |
12667 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
12668 | 0 | return fastEmitInst_rr(AArch64::FMAXNMv8f16, &AArch64::FPR128RegClass, Op0, Op1); |
12669 | 0 | } |
12670 | 0 | return 0; |
12671 | 0 | } |
12672 | | |
12673 | 0 | unsigned fastEmit_ISD_STRICT_FMAXNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12674 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
12675 | 0 | return 0; |
12676 | 0 | if ((Subtarget->hasNEON())) { |
12677 | 0 | return fastEmitInst_rr(AArch64::FMAXNMv2f32, &AArch64::FPR64RegClass, Op0, Op1); |
12678 | 0 | } |
12679 | 0 | return 0; |
12680 | 0 | } |
12681 | | |
12682 | 0 | unsigned fastEmit_ISD_STRICT_FMAXNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12683 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
12684 | 0 | return 0; |
12685 | 0 | if ((Subtarget->hasNEON())) { |
12686 | 0 | return fastEmitInst_rr(AArch64::FMAXNMv4f32, &AArch64::FPR128RegClass, Op0, Op1); |
12687 | 0 | } |
12688 | 0 | return 0; |
12689 | 0 | } |
12690 | | |
12691 | 0 | unsigned fastEmit_ISD_STRICT_FMAXNUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12692 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
12693 | 0 | return 0; |
12694 | 0 | if ((Subtarget->hasNEON())) { |
12695 | 0 | return fastEmitInst_rr(AArch64::FMAXNMv2f64, &AArch64::FPR128RegClass, Op0, Op1); |
12696 | 0 | } |
12697 | 0 | return 0; |
12698 | 0 | } |
12699 | | |
12700 | 0 | unsigned fastEmit_ISD_STRICT_FMAXNUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
12701 | 0 | switch (VT.SimpleTy) { |
12702 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_FMAXNUM_MVT_f16_rr(RetVT, Op0, Op1); |
12703 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FMAXNUM_MVT_f32_rr(RetVT, Op0, Op1); |
12704 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FMAXNUM_MVT_f64_rr(RetVT, Op0, Op1); |
12705 | 0 | case MVT::v4f16: return fastEmit_ISD_STRICT_FMAXNUM_MVT_v4f16_rr(RetVT, Op0, Op1); |
12706 | 0 | case MVT::v8f16: return fastEmit_ISD_STRICT_FMAXNUM_MVT_v8f16_rr(RetVT, Op0, Op1); |
12707 | 0 | case MVT::v2f32: return fastEmit_ISD_STRICT_FMAXNUM_MVT_v2f32_rr(RetVT, Op0, Op1); |
12708 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op1); |
12709 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FMAXNUM_MVT_v2f64_rr(RetVT, Op0, Op1); |
12710 | 0 | default: return 0; |
12711 | 0 | } |
12712 | 0 | } |
12713 | | |
12714 | | // FastEmit functions for ISD::STRICT_FMINIMUM. |
12715 | | |
12716 | 0 | unsigned fastEmit_ISD_STRICT_FMINIMUM_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12717 | 0 | if (RetVT.SimpleTy != MVT::f16) |
12718 | 0 | return 0; |
12719 | 0 | if ((Subtarget->hasFullFP16())) { |
12720 | 0 | return fastEmitInst_rr(AArch64::FMINHrr, &AArch64::FPR16RegClass, Op0, Op1); |
12721 | 0 | } |
12722 | 0 | return 0; |
12723 | 0 | } |
12724 | | |
12725 | 0 | unsigned fastEmit_ISD_STRICT_FMINIMUM_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12726 | 0 | if (RetVT.SimpleTy != MVT::f32) |
12727 | 0 | return 0; |
12728 | 0 | if ((Subtarget->hasFPARMv8())) { |
12729 | 0 | return fastEmitInst_rr(AArch64::FMINSrr, &AArch64::FPR32RegClass, Op0, Op1); |
12730 | 0 | } |
12731 | 0 | return 0; |
12732 | 0 | } |
12733 | | |
12734 | 0 | unsigned fastEmit_ISD_STRICT_FMINIMUM_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12735 | 0 | if (RetVT.SimpleTy != MVT::f64) |
12736 | 0 | return 0; |
12737 | 0 | if ((Subtarget->hasFPARMv8())) { |
12738 | 0 | return fastEmitInst_rr(AArch64::FMINDrr, &AArch64::FPR64RegClass, Op0, Op1); |
12739 | 0 | } |
12740 | 0 | return 0; |
12741 | 0 | } |
12742 | | |
12743 | 0 | unsigned fastEmit_ISD_STRICT_FMINIMUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12744 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
12745 | 0 | return 0; |
12746 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
12747 | 0 | return fastEmitInst_rr(AArch64::FMINv4f16, &AArch64::FPR64RegClass, Op0, Op1); |
12748 | 0 | } |
12749 | 0 | return 0; |
12750 | 0 | } |
12751 | | |
12752 | 0 | unsigned fastEmit_ISD_STRICT_FMINIMUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12753 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
12754 | 0 | return 0; |
12755 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
12756 | 0 | return fastEmitInst_rr(AArch64::FMINv8f16, &AArch64::FPR128RegClass, Op0, Op1); |
12757 | 0 | } |
12758 | 0 | return 0; |
12759 | 0 | } |
12760 | | |
12761 | 0 | unsigned fastEmit_ISD_STRICT_FMINIMUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12762 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
12763 | 0 | return 0; |
12764 | 0 | if ((Subtarget->hasNEON())) { |
12765 | 0 | return fastEmitInst_rr(AArch64::FMINv2f32, &AArch64::FPR64RegClass, Op0, Op1); |
12766 | 0 | } |
12767 | 0 | return 0; |
12768 | 0 | } |
12769 | | |
12770 | 0 | unsigned fastEmit_ISD_STRICT_FMINIMUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12771 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
12772 | 0 | return 0; |
12773 | 0 | if ((Subtarget->hasNEON())) { |
12774 | 0 | return fastEmitInst_rr(AArch64::FMINv4f32, &AArch64::FPR128RegClass, Op0, Op1); |
12775 | 0 | } |
12776 | 0 | return 0; |
12777 | 0 | } |
12778 | | |
12779 | 0 | unsigned fastEmit_ISD_STRICT_FMINIMUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12780 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
12781 | 0 | return 0; |
12782 | 0 | if ((Subtarget->hasNEON())) { |
12783 | 0 | return fastEmitInst_rr(AArch64::FMINv2f64, &AArch64::FPR128RegClass, Op0, Op1); |
12784 | 0 | } |
12785 | 0 | return 0; |
12786 | 0 | } |
12787 | | |
12788 | 0 | unsigned fastEmit_ISD_STRICT_FMINIMUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
12789 | 0 | switch (VT.SimpleTy) { |
12790 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_FMINIMUM_MVT_f16_rr(RetVT, Op0, Op1); |
12791 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FMINIMUM_MVT_f32_rr(RetVT, Op0, Op1); |
12792 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FMINIMUM_MVT_f64_rr(RetVT, Op0, Op1); |
12793 | 0 | case MVT::v4f16: return fastEmit_ISD_STRICT_FMINIMUM_MVT_v4f16_rr(RetVT, Op0, Op1); |
12794 | 0 | case MVT::v8f16: return fastEmit_ISD_STRICT_FMINIMUM_MVT_v8f16_rr(RetVT, Op0, Op1); |
12795 | 0 | case MVT::v2f32: return fastEmit_ISD_STRICT_FMINIMUM_MVT_v2f32_rr(RetVT, Op0, Op1); |
12796 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FMINIMUM_MVT_v4f32_rr(RetVT, Op0, Op1); |
12797 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FMINIMUM_MVT_v2f64_rr(RetVT, Op0, Op1); |
12798 | 0 | default: return 0; |
12799 | 0 | } |
12800 | 0 | } |
12801 | | |
12802 | | // FastEmit functions for ISD::STRICT_FMINNUM. |
12803 | | |
12804 | 0 | unsigned fastEmit_ISD_STRICT_FMINNUM_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12805 | 0 | if (RetVT.SimpleTy != MVT::f16) |
12806 | 0 | return 0; |
12807 | 0 | if ((Subtarget->hasFullFP16())) { |
12808 | 0 | return fastEmitInst_rr(AArch64::FMINNMHrr, &AArch64::FPR16RegClass, Op0, Op1); |
12809 | 0 | } |
12810 | 0 | return 0; |
12811 | 0 | } |
12812 | | |
12813 | 0 | unsigned fastEmit_ISD_STRICT_FMINNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12814 | 0 | if (RetVT.SimpleTy != MVT::f32) |
12815 | 0 | return 0; |
12816 | 0 | if ((Subtarget->hasFPARMv8())) { |
12817 | 0 | return fastEmitInst_rr(AArch64::FMINNMSrr, &AArch64::FPR32RegClass, Op0, Op1); |
12818 | 0 | } |
12819 | 0 | return 0; |
12820 | 0 | } |
12821 | | |
12822 | 0 | unsigned fastEmit_ISD_STRICT_FMINNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12823 | 0 | if (RetVT.SimpleTy != MVT::f64) |
12824 | 0 | return 0; |
12825 | 0 | if ((Subtarget->hasFPARMv8())) { |
12826 | 0 | return fastEmitInst_rr(AArch64::FMINNMDrr, &AArch64::FPR64RegClass, Op0, Op1); |
12827 | 0 | } |
12828 | 0 | return 0; |
12829 | 0 | } |
12830 | | |
12831 | 0 | unsigned fastEmit_ISD_STRICT_FMINNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12832 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
12833 | 0 | return 0; |
12834 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
12835 | 0 | return fastEmitInst_rr(AArch64::FMINNMv4f16, &AArch64::FPR64RegClass, Op0, Op1); |
12836 | 0 | } |
12837 | 0 | return 0; |
12838 | 0 | } |
12839 | | |
12840 | 0 | unsigned fastEmit_ISD_STRICT_FMINNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12841 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
12842 | 0 | return 0; |
12843 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
12844 | 0 | return fastEmitInst_rr(AArch64::FMINNMv8f16, &AArch64::FPR128RegClass, Op0, Op1); |
12845 | 0 | } |
12846 | 0 | return 0; |
12847 | 0 | } |
12848 | | |
12849 | 0 | unsigned fastEmit_ISD_STRICT_FMINNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12850 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
12851 | 0 | return 0; |
12852 | 0 | if ((Subtarget->hasNEON())) { |
12853 | 0 | return fastEmitInst_rr(AArch64::FMINNMv2f32, &AArch64::FPR64RegClass, Op0, Op1); |
12854 | 0 | } |
12855 | 0 | return 0; |
12856 | 0 | } |
12857 | | |
12858 | 0 | unsigned fastEmit_ISD_STRICT_FMINNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12859 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
12860 | 0 | return 0; |
12861 | 0 | if ((Subtarget->hasNEON())) { |
12862 | 0 | return fastEmitInst_rr(AArch64::FMINNMv4f32, &AArch64::FPR128RegClass, Op0, Op1); |
12863 | 0 | } |
12864 | 0 | return 0; |
12865 | 0 | } |
12866 | | |
12867 | 0 | unsigned fastEmit_ISD_STRICT_FMINNUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12868 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
12869 | 0 | return 0; |
12870 | 0 | if ((Subtarget->hasNEON())) { |
12871 | 0 | return fastEmitInst_rr(AArch64::FMINNMv2f64, &AArch64::FPR128RegClass, Op0, Op1); |
12872 | 0 | } |
12873 | 0 | return 0; |
12874 | 0 | } |
12875 | | |
12876 | 0 | unsigned fastEmit_ISD_STRICT_FMINNUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
12877 | 0 | switch (VT.SimpleTy) { |
12878 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_FMINNUM_MVT_f16_rr(RetVT, Op0, Op1); |
12879 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FMINNUM_MVT_f32_rr(RetVT, Op0, Op1); |
12880 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FMINNUM_MVT_f64_rr(RetVT, Op0, Op1); |
12881 | 0 | case MVT::v4f16: return fastEmit_ISD_STRICT_FMINNUM_MVT_v4f16_rr(RetVT, Op0, Op1); |
12882 | 0 | case MVT::v8f16: return fastEmit_ISD_STRICT_FMINNUM_MVT_v8f16_rr(RetVT, Op0, Op1); |
12883 | 0 | case MVT::v2f32: return fastEmit_ISD_STRICT_FMINNUM_MVT_v2f32_rr(RetVT, Op0, Op1); |
12884 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op1); |
12885 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FMINNUM_MVT_v2f64_rr(RetVT, Op0, Op1); |
12886 | 0 | default: return 0; |
12887 | 0 | } |
12888 | 0 | } |
12889 | | |
12890 | | // FastEmit functions for ISD::STRICT_FMUL. |
12891 | | |
12892 | 0 | unsigned fastEmit_ISD_STRICT_FMUL_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12893 | 0 | if (RetVT.SimpleTy != MVT::f16) |
12894 | 0 | return 0; |
12895 | 0 | if ((Subtarget->hasFullFP16())) { |
12896 | 0 | return fastEmitInst_rr(AArch64::FMULHrr, &AArch64::FPR16RegClass, Op0, Op1); |
12897 | 0 | } |
12898 | 0 | return 0; |
12899 | 0 | } |
12900 | | |
12901 | 0 | unsigned fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12902 | 0 | if (RetVT.SimpleTy != MVT::f32) |
12903 | 0 | return 0; |
12904 | 0 | if ((Subtarget->hasFPARMv8())) { |
12905 | 0 | return fastEmitInst_rr(AArch64::FMULSrr, &AArch64::FPR32RegClass, Op0, Op1); |
12906 | 0 | } |
12907 | 0 | return 0; |
12908 | 0 | } |
12909 | | |
12910 | 0 | unsigned fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12911 | 0 | if (RetVT.SimpleTy != MVT::f64) |
12912 | 0 | return 0; |
12913 | 0 | if ((Subtarget->hasFPARMv8())) { |
12914 | 0 | return fastEmitInst_rr(AArch64::FMULDrr, &AArch64::FPR64RegClass, Op0, Op1); |
12915 | 0 | } |
12916 | 0 | return 0; |
12917 | 0 | } |
12918 | | |
12919 | 0 | unsigned fastEmit_ISD_STRICT_FMUL_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12920 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
12921 | 0 | return 0; |
12922 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
12923 | 0 | return fastEmitInst_rr(AArch64::FMULv4f16, &AArch64::FPR64RegClass, Op0, Op1); |
12924 | 0 | } |
12925 | 0 | return 0; |
12926 | 0 | } |
12927 | | |
12928 | 0 | unsigned fastEmit_ISD_STRICT_FMUL_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12929 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
12930 | 0 | return 0; |
12931 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
12932 | 0 | return fastEmitInst_rr(AArch64::FMULv8f16, &AArch64::FPR128RegClass, Op0, Op1); |
12933 | 0 | } |
12934 | 0 | return 0; |
12935 | 0 | } |
12936 | | |
12937 | 0 | unsigned fastEmit_ISD_STRICT_FMUL_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12938 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
12939 | 0 | return 0; |
12940 | 0 | if ((Subtarget->hasNEON())) { |
12941 | 0 | return fastEmitInst_rr(AArch64::FMULv2f32, &AArch64::FPR64RegClass, Op0, Op1); |
12942 | 0 | } |
12943 | 0 | return 0; |
12944 | 0 | } |
12945 | | |
12946 | 0 | unsigned fastEmit_ISD_STRICT_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12947 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
12948 | 0 | return 0; |
12949 | 0 | if ((Subtarget->hasNEON())) { |
12950 | 0 | return fastEmitInst_rr(AArch64::FMULv4f32, &AArch64::FPR128RegClass, Op0, Op1); |
12951 | 0 | } |
12952 | 0 | return 0; |
12953 | 0 | } |
12954 | | |
12955 | 0 | unsigned fastEmit_ISD_STRICT_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12956 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
12957 | 0 | return 0; |
12958 | 0 | if ((Subtarget->hasNEON())) { |
12959 | 0 | return fastEmitInst_rr(AArch64::FMULv2f64, &AArch64::FPR128RegClass, Op0, Op1); |
12960 | 0 | } |
12961 | 0 | return 0; |
12962 | 0 | } |
12963 | | |
12964 | 0 | unsigned fastEmit_ISD_STRICT_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
12965 | 0 | switch (VT.SimpleTy) { |
12966 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_FMUL_MVT_f16_rr(RetVT, Op0, Op1); |
12967 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(RetVT, Op0, Op1); |
12968 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(RetVT, Op0, Op1); |
12969 | 0 | case MVT::v4f16: return fastEmit_ISD_STRICT_FMUL_MVT_v4f16_rr(RetVT, Op0, Op1); |
12970 | 0 | case MVT::v8f16: return fastEmit_ISD_STRICT_FMUL_MVT_v8f16_rr(RetVT, Op0, Op1); |
12971 | 0 | case MVT::v2f32: return fastEmit_ISD_STRICT_FMUL_MVT_v2f32_rr(RetVT, Op0, Op1); |
12972 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1); |
12973 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1); |
12974 | 0 | default: return 0; |
12975 | 0 | } |
12976 | 0 | } |
12977 | | |
12978 | | // FastEmit functions for ISD::STRICT_FSUB. |
12979 | | |
12980 | 0 | unsigned fastEmit_ISD_STRICT_FSUB_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12981 | 0 | if (RetVT.SimpleTy != MVT::f16) |
12982 | 0 | return 0; |
12983 | 0 | if ((Subtarget->hasFullFP16())) { |
12984 | 0 | return fastEmitInst_rr(AArch64::FSUBHrr, &AArch64::FPR16RegClass, Op0, Op1); |
12985 | 0 | } |
12986 | 0 | return 0; |
12987 | 0 | } |
12988 | | |
12989 | 0 | unsigned fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12990 | 0 | if (RetVT.SimpleTy != MVT::f32) |
12991 | 0 | return 0; |
12992 | 0 | if ((Subtarget->hasFPARMv8())) { |
12993 | 0 | return fastEmitInst_rr(AArch64::FSUBSrr, &AArch64::FPR32RegClass, Op0, Op1); |
12994 | 0 | } |
12995 | 0 | return 0; |
12996 | 0 | } |
12997 | | |
12998 | 0 | unsigned fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
12999 | 0 | if (RetVT.SimpleTy != MVT::f64) |
13000 | 0 | return 0; |
13001 | 0 | if ((Subtarget->hasFPARMv8())) { |
13002 | 0 | return fastEmitInst_rr(AArch64::FSUBDrr, &AArch64::FPR64RegClass, Op0, Op1); |
13003 | 0 | } |
13004 | 0 | return 0; |
13005 | 0 | } |
13006 | | |
13007 | 0 | unsigned fastEmit_ISD_STRICT_FSUB_MVT_v4f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13008 | 0 | if (RetVT.SimpleTy != MVT::v4f16) |
13009 | 0 | return 0; |
13010 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
13011 | 0 | return fastEmitInst_rr(AArch64::FSUBv4f16, &AArch64::FPR64RegClass, Op0, Op1); |
13012 | 0 | } |
13013 | 0 | return 0; |
13014 | 0 | } |
13015 | | |
13016 | 0 | unsigned fastEmit_ISD_STRICT_FSUB_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13017 | 0 | if (RetVT.SimpleTy != MVT::v8f16) |
13018 | 0 | return 0; |
13019 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
13020 | 0 | return fastEmitInst_rr(AArch64::FSUBv8f16, &AArch64::FPR128RegClass, Op0, Op1); |
13021 | 0 | } |
13022 | 0 | return 0; |
13023 | 0 | } |
13024 | | |
13025 | 0 | unsigned fastEmit_ISD_STRICT_FSUB_MVT_v2f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13026 | 0 | if (RetVT.SimpleTy != MVT::v2f32) |
13027 | 0 | return 0; |
13028 | 0 | if ((Subtarget->hasNEON())) { |
13029 | 0 | return fastEmitInst_rr(AArch64::FSUBv2f32, &AArch64::FPR64RegClass, Op0, Op1); |
13030 | 0 | } |
13031 | 0 | return 0; |
13032 | 0 | } |
13033 | | |
13034 | 0 | unsigned fastEmit_ISD_STRICT_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13035 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
13036 | 0 | return 0; |
13037 | 0 | if ((Subtarget->hasNEON())) { |
13038 | 0 | return fastEmitInst_rr(AArch64::FSUBv4f32, &AArch64::FPR128RegClass, Op0, Op1); |
13039 | 0 | } |
13040 | 0 | return 0; |
13041 | 0 | } |
13042 | | |
13043 | 0 | unsigned fastEmit_ISD_STRICT_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13044 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
13045 | 0 | return 0; |
13046 | 0 | if ((Subtarget->hasNEON())) { |
13047 | 0 | return fastEmitInst_rr(AArch64::FSUBv2f64, &AArch64::FPR128RegClass, Op0, Op1); |
13048 | 0 | } |
13049 | 0 | return 0; |
13050 | 0 | } |
13051 | | |
13052 | 0 | unsigned fastEmit_ISD_STRICT_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
13053 | 0 | switch (VT.SimpleTy) { |
13054 | 0 | case MVT::f16: return fastEmit_ISD_STRICT_FSUB_MVT_f16_rr(RetVT, Op0, Op1); |
13055 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(RetVT, Op0, Op1); |
13056 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(RetVT, Op0, Op1); |
13057 | 0 | case MVT::v4f16: return fastEmit_ISD_STRICT_FSUB_MVT_v4f16_rr(RetVT, Op0, Op1); |
13058 | 0 | case MVT::v8f16: return fastEmit_ISD_STRICT_FSUB_MVT_v8f16_rr(RetVT, Op0, Op1); |
13059 | 0 | case MVT::v2f32: return fastEmit_ISD_STRICT_FSUB_MVT_v2f32_rr(RetVT, Op0, Op1); |
13060 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1); |
13061 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1); |
13062 | 0 | default: return 0; |
13063 | 0 | } |
13064 | 0 | } |
13065 | | |
13066 | | // FastEmit functions for ISD::SUB. |
13067 | | |
13068 | 0 | unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13069 | 0 | if (RetVT.SimpleTy != MVT::i32) |
13070 | 0 | return 0; |
13071 | 0 | return fastEmitInst_rr(AArch64::SUBSWrr, &AArch64::GPR32RegClass, Op0, Op1); |
13072 | 0 | } |
13073 | | |
13074 | 0 | unsigned fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13075 | 0 | if (RetVT.SimpleTy != MVT::i64) |
13076 | 0 | return 0; |
13077 | 0 | return fastEmitInst_rr(AArch64::SUBSXrr, &AArch64::GPR64RegClass, Op0, Op1); |
13078 | 0 | } |
13079 | | |
13080 | 0 | unsigned fastEmit_ISD_SUB_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13081 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
13082 | 0 | return 0; |
13083 | 0 | if ((Subtarget->hasNEON())) { |
13084 | 0 | return fastEmitInst_rr(AArch64::SUBv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
13085 | 0 | } |
13086 | 0 | return 0; |
13087 | 0 | } |
13088 | | |
13089 | 0 | unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13090 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
13091 | 0 | return 0; |
13092 | 0 | if ((Subtarget->hasNEON())) { |
13093 | 0 | return fastEmitInst_rr(AArch64::SUBv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
13094 | 0 | } |
13095 | 0 | return 0; |
13096 | 0 | } |
13097 | | |
13098 | 0 | unsigned fastEmit_ISD_SUB_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13099 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
13100 | 0 | return 0; |
13101 | 0 | if ((Subtarget->hasNEON())) { |
13102 | 0 | return fastEmitInst_rr(AArch64::SUBv4i16, &AArch64::FPR64RegClass, Op0, Op1); |
13103 | 0 | } |
13104 | 0 | return 0; |
13105 | 0 | } |
13106 | | |
13107 | 0 | unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13108 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
13109 | 0 | return 0; |
13110 | 0 | if ((Subtarget->hasNEON())) { |
13111 | 0 | return fastEmitInst_rr(AArch64::SUBv8i16, &AArch64::FPR128RegClass, Op0, Op1); |
13112 | 0 | } |
13113 | 0 | return 0; |
13114 | 0 | } |
13115 | | |
13116 | 0 | unsigned fastEmit_ISD_SUB_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13117 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
13118 | 0 | return 0; |
13119 | 0 | if ((Subtarget->hasNEON())) { |
13120 | 0 | return fastEmitInst_rr(AArch64::SUBv2i32, &AArch64::FPR64RegClass, Op0, Op1); |
13121 | 0 | } |
13122 | 0 | return 0; |
13123 | 0 | } |
13124 | | |
13125 | 0 | unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13126 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
13127 | 0 | return 0; |
13128 | 0 | if ((Subtarget->hasNEON())) { |
13129 | 0 | return fastEmitInst_rr(AArch64::SUBv4i32, &AArch64::FPR128RegClass, Op0, Op1); |
13130 | 0 | } |
13131 | 0 | return 0; |
13132 | 0 | } |
13133 | | |
13134 | 0 | unsigned fastEmit_ISD_SUB_MVT_v1i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13135 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
13136 | 0 | return 0; |
13137 | 0 | if ((Subtarget->hasNEON())) { |
13138 | 0 | return fastEmitInst_rr(AArch64::SUBv1i64, &AArch64::FPR64RegClass, Op0, Op1); |
13139 | 0 | } |
13140 | 0 | return 0; |
13141 | 0 | } |
13142 | | |
13143 | 0 | unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13144 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
13145 | 0 | return 0; |
13146 | 0 | if ((Subtarget->hasNEON())) { |
13147 | 0 | return fastEmitInst_rr(AArch64::SUBv2i64, &AArch64::FPR128RegClass, Op0, Op1); |
13148 | 0 | } |
13149 | 0 | return 0; |
13150 | 0 | } |
13151 | | |
13152 | 0 | unsigned fastEmit_ISD_SUB_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13153 | 0 | if (RetVT.SimpleTy != MVT::nxv16i8) |
13154 | 0 | return 0; |
13155 | 0 | if ((Subtarget->hasSVEorSME())) { |
13156 | 0 | return fastEmitInst_rr(AArch64::SUB_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op1); |
13157 | 0 | } |
13158 | 0 | return 0; |
13159 | 0 | } |
13160 | | |
13161 | 0 | unsigned fastEmit_ISD_SUB_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13162 | 0 | if (RetVT.SimpleTy != MVT::nxv8i16) |
13163 | 0 | return 0; |
13164 | 0 | if ((Subtarget->hasSVEorSME())) { |
13165 | 0 | return fastEmitInst_rr(AArch64::SUB_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
13166 | 0 | } |
13167 | 0 | return 0; |
13168 | 0 | } |
13169 | | |
13170 | 0 | unsigned fastEmit_ISD_SUB_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13171 | 0 | if (RetVT.SimpleTy != MVT::nxv4i32) |
13172 | 0 | return 0; |
13173 | 0 | if ((Subtarget->hasSVEorSME())) { |
13174 | 0 | return fastEmitInst_rr(AArch64::SUB_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
13175 | 0 | } |
13176 | 0 | return 0; |
13177 | 0 | } |
13178 | | |
13179 | 0 | unsigned fastEmit_ISD_SUB_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13180 | 0 | if (RetVT.SimpleTy != MVT::nxv2i64) |
13181 | 0 | return 0; |
13182 | 0 | if ((Subtarget->hasSVEorSME())) { |
13183 | 0 | return fastEmitInst_rr(AArch64::SUB_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
13184 | 0 | } |
13185 | 0 | return 0; |
13186 | 0 | } |
13187 | | |
13188 | 0 | unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
13189 | 0 | switch (VT.SimpleTy) { |
13190 | 0 | case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op1); |
13191 | 0 | case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op1); |
13192 | 0 | case MVT::v8i8: return fastEmit_ISD_SUB_MVT_v8i8_rr(RetVT, Op0, Op1); |
13193 | 0 | case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op1); |
13194 | 0 | case MVT::v4i16: return fastEmit_ISD_SUB_MVT_v4i16_rr(RetVT, Op0, Op1); |
13195 | 0 | case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op1); |
13196 | 0 | case MVT::v2i32: return fastEmit_ISD_SUB_MVT_v2i32_rr(RetVT, Op0, Op1); |
13197 | 0 | case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op1); |
13198 | 0 | case MVT::v1i64: return fastEmit_ISD_SUB_MVT_v1i64_rr(RetVT, Op0, Op1); |
13199 | 0 | case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op1); |
13200 | 0 | case MVT::nxv16i8: return fastEmit_ISD_SUB_MVT_nxv16i8_rr(RetVT, Op0, Op1); |
13201 | 0 | case MVT::nxv8i16: return fastEmit_ISD_SUB_MVT_nxv8i16_rr(RetVT, Op0, Op1); |
13202 | 0 | case MVT::nxv4i32: return fastEmit_ISD_SUB_MVT_nxv4i32_rr(RetVT, Op0, Op1); |
13203 | 0 | case MVT::nxv2i64: return fastEmit_ISD_SUB_MVT_nxv2i64_rr(RetVT, Op0, Op1); |
13204 | 0 | default: return 0; |
13205 | 0 | } |
13206 | 0 | } |
13207 | | |
13208 | | // FastEmit functions for ISD::UADDSAT. |
13209 | | |
13210 | 0 | unsigned fastEmit_ISD_UADDSAT_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13211 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
13212 | 0 | return 0; |
13213 | 0 | if ((Subtarget->hasNEON())) { |
13214 | 0 | return fastEmitInst_rr(AArch64::UQADDv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
13215 | 0 | } |
13216 | 0 | return 0; |
13217 | 0 | } |
13218 | | |
13219 | 0 | unsigned fastEmit_ISD_UADDSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13220 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
13221 | 0 | return 0; |
13222 | 0 | if ((Subtarget->hasNEON())) { |
13223 | 0 | return fastEmitInst_rr(AArch64::UQADDv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
13224 | 0 | } |
13225 | 0 | return 0; |
13226 | 0 | } |
13227 | | |
13228 | 0 | unsigned fastEmit_ISD_UADDSAT_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13229 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
13230 | 0 | return 0; |
13231 | 0 | if ((Subtarget->hasNEON())) { |
13232 | 0 | return fastEmitInst_rr(AArch64::UQADDv4i16, &AArch64::FPR64RegClass, Op0, Op1); |
13233 | 0 | } |
13234 | 0 | return 0; |
13235 | 0 | } |
13236 | | |
13237 | 0 | unsigned fastEmit_ISD_UADDSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13238 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
13239 | 0 | return 0; |
13240 | 0 | if ((Subtarget->hasNEON())) { |
13241 | 0 | return fastEmitInst_rr(AArch64::UQADDv8i16, &AArch64::FPR128RegClass, Op0, Op1); |
13242 | 0 | } |
13243 | 0 | return 0; |
13244 | 0 | } |
13245 | | |
13246 | 0 | unsigned fastEmit_ISD_UADDSAT_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13247 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
13248 | 0 | return 0; |
13249 | 0 | if ((Subtarget->hasNEON())) { |
13250 | 0 | return fastEmitInst_rr(AArch64::UQADDv2i32, &AArch64::FPR64RegClass, Op0, Op1); |
13251 | 0 | } |
13252 | 0 | return 0; |
13253 | 0 | } |
13254 | | |
13255 | 0 | unsigned fastEmit_ISD_UADDSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13256 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
13257 | 0 | return 0; |
13258 | 0 | if ((Subtarget->hasNEON())) { |
13259 | 0 | return fastEmitInst_rr(AArch64::UQADDv4i32, &AArch64::FPR128RegClass, Op0, Op1); |
13260 | 0 | } |
13261 | 0 | return 0; |
13262 | 0 | } |
13263 | | |
13264 | 0 | unsigned fastEmit_ISD_UADDSAT_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13265 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
13266 | 0 | return 0; |
13267 | 0 | if ((Subtarget->hasNEON())) { |
13268 | 0 | return fastEmitInst_rr(AArch64::UQADDv2i64, &AArch64::FPR128RegClass, Op0, Op1); |
13269 | 0 | } |
13270 | 0 | return 0; |
13271 | 0 | } |
13272 | | |
13273 | 0 | unsigned fastEmit_ISD_UADDSAT_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13274 | 0 | if (RetVT.SimpleTy != MVT::nxv16i8) |
13275 | 0 | return 0; |
13276 | 0 | if ((Subtarget->hasSVEorSME())) { |
13277 | 0 | return fastEmitInst_rr(AArch64::UQADD_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op1); |
13278 | 0 | } |
13279 | 0 | return 0; |
13280 | 0 | } |
13281 | | |
13282 | 0 | unsigned fastEmit_ISD_UADDSAT_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13283 | 0 | if (RetVT.SimpleTy != MVT::nxv8i16) |
13284 | 0 | return 0; |
13285 | 0 | if ((Subtarget->hasSVEorSME())) { |
13286 | 0 | return fastEmitInst_rr(AArch64::UQADD_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
13287 | 0 | } |
13288 | 0 | return 0; |
13289 | 0 | } |
13290 | | |
13291 | 0 | unsigned fastEmit_ISD_UADDSAT_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13292 | 0 | if (RetVT.SimpleTy != MVT::nxv4i32) |
13293 | 0 | return 0; |
13294 | 0 | if ((Subtarget->hasSVEorSME())) { |
13295 | 0 | return fastEmitInst_rr(AArch64::UQADD_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
13296 | 0 | } |
13297 | 0 | return 0; |
13298 | 0 | } |
13299 | | |
13300 | 0 | unsigned fastEmit_ISD_UADDSAT_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13301 | 0 | if (RetVT.SimpleTy != MVT::nxv2i64) |
13302 | 0 | return 0; |
13303 | 0 | if ((Subtarget->hasSVEorSME())) { |
13304 | 0 | return fastEmitInst_rr(AArch64::UQADD_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
13305 | 0 | } |
13306 | 0 | return 0; |
13307 | 0 | } |
13308 | | |
13309 | 0 | unsigned fastEmit_ISD_UADDSAT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
13310 | 0 | switch (VT.SimpleTy) { |
13311 | 0 | case MVT::v8i8: return fastEmit_ISD_UADDSAT_MVT_v8i8_rr(RetVT, Op0, Op1); |
13312 | 0 | case MVT::v16i8: return fastEmit_ISD_UADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1); |
13313 | 0 | case MVT::v4i16: return fastEmit_ISD_UADDSAT_MVT_v4i16_rr(RetVT, Op0, Op1); |
13314 | 0 | case MVT::v8i16: return fastEmit_ISD_UADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1); |
13315 | 0 | case MVT::v2i32: return fastEmit_ISD_UADDSAT_MVT_v2i32_rr(RetVT, Op0, Op1); |
13316 | 0 | case MVT::v4i32: return fastEmit_ISD_UADDSAT_MVT_v4i32_rr(RetVT, Op0, Op1); |
13317 | 0 | case MVT::v2i64: return fastEmit_ISD_UADDSAT_MVT_v2i64_rr(RetVT, Op0, Op1); |
13318 | 0 | case MVT::nxv16i8: return fastEmit_ISD_UADDSAT_MVT_nxv16i8_rr(RetVT, Op0, Op1); |
13319 | 0 | case MVT::nxv8i16: return fastEmit_ISD_UADDSAT_MVT_nxv8i16_rr(RetVT, Op0, Op1); |
13320 | 0 | case MVT::nxv4i32: return fastEmit_ISD_UADDSAT_MVT_nxv4i32_rr(RetVT, Op0, Op1); |
13321 | 0 | case MVT::nxv2i64: return fastEmit_ISD_UADDSAT_MVT_nxv2i64_rr(RetVT, Op0, Op1); |
13322 | 0 | default: return 0; |
13323 | 0 | } |
13324 | 0 | } |
13325 | | |
13326 | | // FastEmit functions for ISD::UDIV. |
13327 | | |
13328 | 0 | unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13329 | 0 | if (RetVT.SimpleTy != MVT::i32) |
13330 | 0 | return 0; |
13331 | 0 | return fastEmitInst_rr(AArch64::UDIVWr, &AArch64::GPR32RegClass, Op0, Op1); |
13332 | 0 | } |
13333 | | |
13334 | 0 | unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13335 | 0 | if (RetVT.SimpleTy != MVT::i64) |
13336 | 0 | return 0; |
13337 | 0 | return fastEmitInst_rr(AArch64::UDIVXr, &AArch64::GPR64RegClass, Op0, Op1); |
13338 | 0 | } |
13339 | | |
13340 | 0 | unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
13341 | 0 | switch (VT.SimpleTy) { |
13342 | 0 | case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op1); |
13343 | 0 | case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op1); |
13344 | 0 | default: return 0; |
13345 | 0 | } |
13346 | 0 | } |
13347 | | |
13348 | | // FastEmit functions for ISD::UMAX. |
13349 | | |
13350 | 0 | unsigned fastEmit_ISD_UMAX_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13351 | 0 | if (RetVT.SimpleTy != MVT::i32) |
13352 | 0 | return 0; |
13353 | 0 | if ((Subtarget->hasCSSC())) { |
13354 | 0 | return fastEmitInst_rr(AArch64::UMAXWrr, &AArch64::GPR32RegClass, Op0, Op1); |
13355 | 0 | } |
13356 | 0 | return 0; |
13357 | 0 | } |
13358 | | |
13359 | 0 | unsigned fastEmit_ISD_UMAX_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13360 | 0 | if (RetVT.SimpleTy != MVT::i64) |
13361 | 0 | return 0; |
13362 | 0 | if ((Subtarget->hasCSSC())) { |
13363 | 0 | return fastEmitInst_rr(AArch64::UMAXXrr, &AArch64::GPR64RegClass, Op0, Op1); |
13364 | 0 | } |
13365 | 0 | return 0; |
13366 | 0 | } |
13367 | | |
13368 | 0 | unsigned fastEmit_ISD_UMAX_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13369 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
13370 | 0 | return 0; |
13371 | 0 | if ((Subtarget->hasNEON())) { |
13372 | 0 | return fastEmitInst_rr(AArch64::UMAXv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
13373 | 0 | } |
13374 | 0 | return 0; |
13375 | 0 | } |
13376 | | |
13377 | 0 | unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13378 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
13379 | 0 | return 0; |
13380 | 0 | if ((Subtarget->hasNEON())) { |
13381 | 0 | return fastEmitInst_rr(AArch64::UMAXv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
13382 | 0 | } |
13383 | 0 | return 0; |
13384 | 0 | } |
13385 | | |
13386 | 0 | unsigned fastEmit_ISD_UMAX_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13387 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
13388 | 0 | return 0; |
13389 | 0 | if ((Subtarget->hasNEON())) { |
13390 | 0 | return fastEmitInst_rr(AArch64::UMAXv4i16, &AArch64::FPR64RegClass, Op0, Op1); |
13391 | 0 | } |
13392 | 0 | return 0; |
13393 | 0 | } |
13394 | | |
13395 | 0 | unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13396 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
13397 | 0 | return 0; |
13398 | 0 | if ((Subtarget->hasNEON())) { |
13399 | 0 | return fastEmitInst_rr(AArch64::UMAXv8i16, &AArch64::FPR128RegClass, Op0, Op1); |
13400 | 0 | } |
13401 | 0 | return 0; |
13402 | 0 | } |
13403 | | |
13404 | 0 | unsigned fastEmit_ISD_UMAX_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13405 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
13406 | 0 | return 0; |
13407 | 0 | if ((Subtarget->hasNEON())) { |
13408 | 0 | return fastEmitInst_rr(AArch64::UMAXv2i32, &AArch64::FPR64RegClass, Op0, Op1); |
13409 | 0 | } |
13410 | 0 | return 0; |
13411 | 0 | } |
13412 | | |
13413 | 0 | unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13414 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
13415 | 0 | return 0; |
13416 | 0 | if ((Subtarget->hasNEON())) { |
13417 | 0 | return fastEmitInst_rr(AArch64::UMAXv4i32, &AArch64::FPR128RegClass, Op0, Op1); |
13418 | 0 | } |
13419 | 0 | return 0; |
13420 | 0 | } |
13421 | | |
13422 | 0 | unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
13423 | 0 | switch (VT.SimpleTy) { |
13424 | 0 | case MVT::i32: return fastEmit_ISD_UMAX_MVT_i32_rr(RetVT, Op0, Op1); |
13425 | 0 | case MVT::i64: return fastEmit_ISD_UMAX_MVT_i64_rr(RetVT, Op0, Op1); |
13426 | 0 | case MVT::v8i8: return fastEmit_ISD_UMAX_MVT_v8i8_rr(RetVT, Op0, Op1); |
13427 | 0 | case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op1); |
13428 | 0 | case MVT::v4i16: return fastEmit_ISD_UMAX_MVT_v4i16_rr(RetVT, Op0, Op1); |
13429 | 0 | case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op1); |
13430 | 0 | case MVT::v2i32: return fastEmit_ISD_UMAX_MVT_v2i32_rr(RetVT, Op0, Op1); |
13431 | 0 | case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op1); |
13432 | 0 | default: return 0; |
13433 | 0 | } |
13434 | 0 | } |
13435 | | |
13436 | | // FastEmit functions for ISD::UMIN. |
13437 | | |
13438 | 0 | unsigned fastEmit_ISD_UMIN_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13439 | 0 | if (RetVT.SimpleTy != MVT::i32) |
13440 | 0 | return 0; |
13441 | 0 | if ((Subtarget->hasCSSC())) { |
13442 | 0 | return fastEmitInst_rr(AArch64::UMINWrr, &AArch64::GPR32RegClass, Op0, Op1); |
13443 | 0 | } |
13444 | 0 | return 0; |
13445 | 0 | } |
13446 | | |
13447 | 0 | unsigned fastEmit_ISD_UMIN_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13448 | 0 | if (RetVT.SimpleTy != MVT::i64) |
13449 | 0 | return 0; |
13450 | 0 | if ((Subtarget->hasCSSC())) { |
13451 | 0 | return fastEmitInst_rr(AArch64::UMINXrr, &AArch64::GPR64RegClass, Op0, Op1); |
13452 | 0 | } |
13453 | 0 | return 0; |
13454 | 0 | } |
13455 | | |
13456 | 0 | unsigned fastEmit_ISD_UMIN_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13457 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
13458 | 0 | return 0; |
13459 | 0 | if ((Subtarget->hasNEON())) { |
13460 | 0 | return fastEmitInst_rr(AArch64::UMINv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
13461 | 0 | } |
13462 | 0 | return 0; |
13463 | 0 | } |
13464 | | |
13465 | 0 | unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13466 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
13467 | 0 | return 0; |
13468 | 0 | if ((Subtarget->hasNEON())) { |
13469 | 0 | return fastEmitInst_rr(AArch64::UMINv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
13470 | 0 | } |
13471 | 0 | return 0; |
13472 | 0 | } |
13473 | | |
13474 | 0 | unsigned fastEmit_ISD_UMIN_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13475 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
13476 | 0 | return 0; |
13477 | 0 | if ((Subtarget->hasNEON())) { |
13478 | 0 | return fastEmitInst_rr(AArch64::UMINv4i16, &AArch64::FPR64RegClass, Op0, Op1); |
13479 | 0 | } |
13480 | 0 | return 0; |
13481 | 0 | } |
13482 | | |
13483 | 0 | unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13484 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
13485 | 0 | return 0; |
13486 | 0 | if ((Subtarget->hasNEON())) { |
13487 | 0 | return fastEmitInst_rr(AArch64::UMINv8i16, &AArch64::FPR128RegClass, Op0, Op1); |
13488 | 0 | } |
13489 | 0 | return 0; |
13490 | 0 | } |
13491 | | |
13492 | 0 | unsigned fastEmit_ISD_UMIN_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13493 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
13494 | 0 | return 0; |
13495 | 0 | if ((Subtarget->hasNEON())) { |
13496 | 0 | return fastEmitInst_rr(AArch64::UMINv2i32, &AArch64::FPR64RegClass, Op0, Op1); |
13497 | 0 | } |
13498 | 0 | return 0; |
13499 | 0 | } |
13500 | | |
13501 | 0 | unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13502 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
13503 | 0 | return 0; |
13504 | 0 | if ((Subtarget->hasNEON())) { |
13505 | 0 | return fastEmitInst_rr(AArch64::UMINv4i32, &AArch64::FPR128RegClass, Op0, Op1); |
13506 | 0 | } |
13507 | 0 | return 0; |
13508 | 0 | } |
13509 | | |
13510 | 0 | unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
13511 | 0 | switch (VT.SimpleTy) { |
13512 | 0 | case MVT::i32: return fastEmit_ISD_UMIN_MVT_i32_rr(RetVT, Op0, Op1); |
13513 | 0 | case MVT::i64: return fastEmit_ISD_UMIN_MVT_i64_rr(RetVT, Op0, Op1); |
13514 | 0 | case MVT::v8i8: return fastEmit_ISD_UMIN_MVT_v8i8_rr(RetVT, Op0, Op1); |
13515 | 0 | case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op1); |
13516 | 0 | case MVT::v4i16: return fastEmit_ISD_UMIN_MVT_v4i16_rr(RetVT, Op0, Op1); |
13517 | 0 | case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op1); |
13518 | 0 | case MVT::v2i32: return fastEmit_ISD_UMIN_MVT_v2i32_rr(RetVT, Op0, Op1); |
13519 | 0 | case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op1); |
13520 | 0 | default: return 0; |
13521 | 0 | } |
13522 | 0 | } |
13523 | | |
13524 | | // FastEmit functions for ISD::USUBSAT. |
13525 | | |
13526 | 0 | unsigned fastEmit_ISD_USUBSAT_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13527 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
13528 | 0 | return 0; |
13529 | 0 | if ((Subtarget->hasNEON())) { |
13530 | 0 | return fastEmitInst_rr(AArch64::UQSUBv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
13531 | 0 | } |
13532 | 0 | return 0; |
13533 | 0 | } |
13534 | | |
13535 | 0 | unsigned fastEmit_ISD_USUBSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13536 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
13537 | 0 | return 0; |
13538 | 0 | if ((Subtarget->hasNEON())) { |
13539 | 0 | return fastEmitInst_rr(AArch64::UQSUBv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
13540 | 0 | } |
13541 | 0 | return 0; |
13542 | 0 | } |
13543 | | |
13544 | 0 | unsigned fastEmit_ISD_USUBSAT_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13545 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
13546 | 0 | return 0; |
13547 | 0 | if ((Subtarget->hasNEON())) { |
13548 | 0 | return fastEmitInst_rr(AArch64::UQSUBv4i16, &AArch64::FPR64RegClass, Op0, Op1); |
13549 | 0 | } |
13550 | 0 | return 0; |
13551 | 0 | } |
13552 | | |
13553 | 0 | unsigned fastEmit_ISD_USUBSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13554 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
13555 | 0 | return 0; |
13556 | 0 | if ((Subtarget->hasNEON())) { |
13557 | 0 | return fastEmitInst_rr(AArch64::UQSUBv8i16, &AArch64::FPR128RegClass, Op0, Op1); |
13558 | 0 | } |
13559 | 0 | return 0; |
13560 | 0 | } |
13561 | | |
13562 | 0 | unsigned fastEmit_ISD_USUBSAT_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13563 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
13564 | 0 | return 0; |
13565 | 0 | if ((Subtarget->hasNEON())) { |
13566 | 0 | return fastEmitInst_rr(AArch64::UQSUBv2i32, &AArch64::FPR64RegClass, Op0, Op1); |
13567 | 0 | } |
13568 | 0 | return 0; |
13569 | 0 | } |
13570 | | |
13571 | 0 | unsigned fastEmit_ISD_USUBSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13572 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
13573 | 0 | return 0; |
13574 | 0 | if ((Subtarget->hasNEON())) { |
13575 | 0 | return fastEmitInst_rr(AArch64::UQSUBv4i32, &AArch64::FPR128RegClass, Op0, Op1); |
13576 | 0 | } |
13577 | 0 | return 0; |
13578 | 0 | } |
13579 | | |
13580 | 0 | unsigned fastEmit_ISD_USUBSAT_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13581 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
13582 | 0 | return 0; |
13583 | 0 | if ((Subtarget->hasNEON())) { |
13584 | 0 | return fastEmitInst_rr(AArch64::UQSUBv2i64, &AArch64::FPR128RegClass, Op0, Op1); |
13585 | 0 | } |
13586 | 0 | return 0; |
13587 | 0 | } |
13588 | | |
13589 | 0 | unsigned fastEmit_ISD_USUBSAT_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13590 | 0 | if (RetVT.SimpleTy != MVT::nxv16i8) |
13591 | 0 | return 0; |
13592 | 0 | if ((Subtarget->hasSVEorSME())) { |
13593 | 0 | return fastEmitInst_rr(AArch64::UQSUB_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op1); |
13594 | 0 | } |
13595 | 0 | return 0; |
13596 | 0 | } |
13597 | | |
13598 | 0 | unsigned fastEmit_ISD_USUBSAT_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13599 | 0 | if (RetVT.SimpleTy != MVT::nxv8i16) |
13600 | 0 | return 0; |
13601 | 0 | if ((Subtarget->hasSVEorSME())) { |
13602 | 0 | return fastEmitInst_rr(AArch64::UQSUB_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op1); |
13603 | 0 | } |
13604 | 0 | return 0; |
13605 | 0 | } |
13606 | | |
13607 | 0 | unsigned fastEmit_ISD_USUBSAT_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13608 | 0 | if (RetVT.SimpleTy != MVT::nxv4i32) |
13609 | 0 | return 0; |
13610 | 0 | if ((Subtarget->hasSVEorSME())) { |
13611 | 0 | return fastEmitInst_rr(AArch64::UQSUB_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op1); |
13612 | 0 | } |
13613 | 0 | return 0; |
13614 | 0 | } |
13615 | | |
13616 | 0 | unsigned fastEmit_ISD_USUBSAT_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13617 | 0 | if (RetVT.SimpleTy != MVT::nxv2i64) |
13618 | 0 | return 0; |
13619 | 0 | if ((Subtarget->hasSVEorSME())) { |
13620 | 0 | return fastEmitInst_rr(AArch64::UQSUB_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op1); |
13621 | 0 | } |
13622 | 0 | return 0; |
13623 | 0 | } |
13624 | | |
13625 | 0 | unsigned fastEmit_ISD_USUBSAT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
13626 | 0 | switch (VT.SimpleTy) { |
13627 | 0 | case MVT::v8i8: return fastEmit_ISD_USUBSAT_MVT_v8i8_rr(RetVT, Op0, Op1); |
13628 | 0 | case MVT::v16i8: return fastEmit_ISD_USUBSAT_MVT_v16i8_rr(RetVT, Op0, Op1); |
13629 | 0 | case MVT::v4i16: return fastEmit_ISD_USUBSAT_MVT_v4i16_rr(RetVT, Op0, Op1); |
13630 | 0 | case MVT::v8i16: return fastEmit_ISD_USUBSAT_MVT_v8i16_rr(RetVT, Op0, Op1); |
13631 | 0 | case MVT::v2i32: return fastEmit_ISD_USUBSAT_MVT_v2i32_rr(RetVT, Op0, Op1); |
13632 | 0 | case MVT::v4i32: return fastEmit_ISD_USUBSAT_MVT_v4i32_rr(RetVT, Op0, Op1); |
13633 | 0 | case MVT::v2i64: return fastEmit_ISD_USUBSAT_MVT_v2i64_rr(RetVT, Op0, Op1); |
13634 | 0 | case MVT::nxv16i8: return fastEmit_ISD_USUBSAT_MVT_nxv16i8_rr(RetVT, Op0, Op1); |
13635 | 0 | case MVT::nxv8i16: return fastEmit_ISD_USUBSAT_MVT_nxv8i16_rr(RetVT, Op0, Op1); |
13636 | 0 | case MVT::nxv4i32: return fastEmit_ISD_USUBSAT_MVT_nxv4i32_rr(RetVT, Op0, Op1); |
13637 | 0 | case MVT::nxv2i64: return fastEmit_ISD_USUBSAT_MVT_nxv2i64_rr(RetVT, Op0, Op1); |
13638 | 0 | default: return 0; |
13639 | 0 | } |
13640 | 0 | } |
13641 | | |
13642 | | // FastEmit functions for ISD::XOR. |
13643 | | |
13644 | 0 | unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13645 | 0 | if (RetVT.SimpleTy != MVT::i32) |
13646 | 0 | return 0; |
13647 | 0 | return fastEmitInst_rr(AArch64::EORWrr, &AArch64::GPR32RegClass, Op0, Op1); |
13648 | 0 | } |
13649 | | |
13650 | 0 | unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13651 | 0 | if (RetVT.SimpleTy != MVT::i64) |
13652 | 0 | return 0; |
13653 | 0 | return fastEmitInst_rr(AArch64::EORXrr, &AArch64::GPR64RegClass, Op0, Op1); |
13654 | 0 | } |
13655 | | |
13656 | 0 | unsigned fastEmit_ISD_XOR_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13657 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
13658 | 0 | return 0; |
13659 | 0 | if ((Subtarget->hasNEON())) { |
13660 | 0 | return fastEmitInst_rr(AArch64::EORv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
13661 | 0 | } |
13662 | 0 | return 0; |
13663 | 0 | } |
13664 | | |
13665 | 0 | unsigned fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13666 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
13667 | 0 | return 0; |
13668 | 0 | if ((Subtarget->hasNEON())) { |
13669 | 0 | return fastEmitInst_rr(AArch64::EORv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
13670 | 0 | } |
13671 | 0 | return 0; |
13672 | 0 | } |
13673 | | |
13674 | 0 | unsigned fastEmit_ISD_XOR_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13675 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
13676 | 0 | return 0; |
13677 | 0 | if ((Subtarget->hasNEON())) { |
13678 | 0 | return fastEmitInst_rr(AArch64::EORv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
13679 | 0 | } |
13680 | 0 | return 0; |
13681 | 0 | } |
13682 | | |
13683 | 0 | unsigned fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13684 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
13685 | 0 | return 0; |
13686 | 0 | if ((Subtarget->hasNEON())) { |
13687 | 0 | return fastEmitInst_rr(AArch64::EORv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
13688 | 0 | } |
13689 | 0 | return 0; |
13690 | 0 | } |
13691 | | |
13692 | 0 | unsigned fastEmit_ISD_XOR_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13693 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
13694 | 0 | return 0; |
13695 | 0 | if ((Subtarget->hasNEON())) { |
13696 | 0 | return fastEmitInst_rr(AArch64::EORv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
13697 | 0 | } |
13698 | 0 | return 0; |
13699 | 0 | } |
13700 | | |
13701 | 0 | unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13702 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
13703 | 0 | return 0; |
13704 | 0 | if ((Subtarget->hasNEON())) { |
13705 | 0 | return fastEmitInst_rr(AArch64::EORv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
13706 | 0 | } |
13707 | 0 | return 0; |
13708 | 0 | } |
13709 | | |
13710 | 0 | unsigned fastEmit_ISD_XOR_MVT_v1i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13711 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
13712 | 0 | return 0; |
13713 | 0 | if ((Subtarget->hasNEON())) { |
13714 | 0 | return fastEmitInst_rr(AArch64::EORv8i8, &AArch64::FPR64RegClass, Op0, Op1); |
13715 | 0 | } |
13716 | 0 | return 0; |
13717 | 0 | } |
13718 | | |
13719 | 0 | unsigned fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13720 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
13721 | 0 | return 0; |
13722 | 0 | if ((Subtarget->hasNEON())) { |
13723 | 0 | return fastEmitInst_rr(AArch64::EORv16i8, &AArch64::FPR128RegClass, Op0, Op1); |
13724 | 0 | } |
13725 | 0 | return 0; |
13726 | 0 | } |
13727 | | |
13728 | 0 | unsigned fastEmit_ISD_XOR_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13729 | 0 | if (RetVT.SimpleTy != MVT::nxv16i8) |
13730 | 0 | return 0; |
13731 | 0 | if ((Subtarget->hasSVEorSME())) { |
13732 | 0 | return fastEmitInst_rr(AArch64::EOR_ZZZ, &AArch64::ZPRRegClass, Op0, Op1); |
13733 | 0 | } |
13734 | 0 | return 0; |
13735 | 0 | } |
13736 | | |
13737 | 0 | unsigned fastEmit_ISD_XOR_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13738 | 0 | if (RetVT.SimpleTy != MVT::nxv8i16) |
13739 | 0 | return 0; |
13740 | 0 | if ((Subtarget->hasSVEorSME())) { |
13741 | 0 | return fastEmitInst_rr(AArch64::EOR_ZZZ, &AArch64::ZPRRegClass, Op0, Op1); |
13742 | 0 | } |
13743 | 0 | return 0; |
13744 | 0 | } |
13745 | | |
13746 | 0 | unsigned fastEmit_ISD_XOR_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13747 | 0 | if (RetVT.SimpleTy != MVT::nxv4i32) |
13748 | 0 | return 0; |
13749 | 0 | if ((Subtarget->hasSVEorSME())) { |
13750 | 0 | return fastEmitInst_rr(AArch64::EOR_ZZZ, &AArch64::ZPRRegClass, Op0, Op1); |
13751 | 0 | } |
13752 | 0 | return 0; |
13753 | 0 | } |
13754 | | |
13755 | 0 | unsigned fastEmit_ISD_XOR_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
13756 | 0 | if (RetVT.SimpleTy != MVT::nxv2i64) |
13757 | 0 | return 0; |
13758 | 0 | if ((Subtarget->hasSVEorSME())) { |
13759 | 0 | return fastEmitInst_rr(AArch64::EOR_ZZZ, &AArch64::ZPRRegClass, Op0, Op1); |
13760 | 0 | } |
13761 | 0 | return 0; |
13762 | 0 | } |
13763 | | |
13764 | 0 | unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
13765 | 0 | switch (VT.SimpleTy) { |
13766 | 0 | case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op1); |
13767 | 0 | case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op1); |
13768 | 0 | case MVT::v8i8: return fastEmit_ISD_XOR_MVT_v8i8_rr(RetVT, Op0, Op1); |
13769 | 0 | case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op1); |
13770 | 0 | case MVT::v4i16: return fastEmit_ISD_XOR_MVT_v4i16_rr(RetVT, Op0, Op1); |
13771 | 0 | case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op1); |
13772 | 0 | case MVT::v2i32: return fastEmit_ISD_XOR_MVT_v2i32_rr(RetVT, Op0, Op1); |
13773 | 0 | case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op1); |
13774 | 0 | case MVT::v1i64: return fastEmit_ISD_XOR_MVT_v1i64_rr(RetVT, Op0, Op1); |
13775 | 0 | case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op1); |
13776 | 0 | case MVT::nxv16i8: return fastEmit_ISD_XOR_MVT_nxv16i8_rr(RetVT, Op0, Op1); |
13777 | 0 | case MVT::nxv8i16: return fastEmit_ISD_XOR_MVT_nxv8i16_rr(RetVT, Op0, Op1); |
13778 | 0 | case MVT::nxv4i32: return fastEmit_ISD_XOR_MVT_nxv4i32_rr(RetVT, Op0, Op1); |
13779 | 0 | case MVT::nxv2i64: return fastEmit_ISD_XOR_MVT_nxv2i64_rr(RetVT, Op0, Op1); |
13780 | 0 | default: return 0; |
13781 | 0 | } |
13782 | 0 | } |
13783 | | |
13784 | | // Top-level FastEmit function. |
13785 | | |
13786 | 0 | unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, unsigned Op1) override { |
13787 | 0 | switch (Opcode) { |
13788 | 0 | case AArch64ISD::ADDP: return fastEmit_AArch64ISD_ADDP_rr(VT, RetVT, Op0, Op1); |
13789 | 0 | case AArch64ISD::BIC: return fastEmit_AArch64ISD_BIC_rr(VT, RetVT, Op0, Op1); |
13790 | 0 | case AArch64ISD::CMEQ: return fastEmit_AArch64ISD_CMEQ_rr(VT, RetVT, Op0, Op1); |
13791 | 0 | case AArch64ISD::CMGE: return fastEmit_AArch64ISD_CMGE_rr(VT, RetVT, Op0, Op1); |
13792 | 0 | case AArch64ISD::CMGT: return fastEmit_AArch64ISD_CMGT_rr(VT, RetVT, Op0, Op1); |
13793 | 0 | case AArch64ISD::CMHI: return fastEmit_AArch64ISD_CMHI_rr(VT, RetVT, Op0, Op1); |
13794 | 0 | case AArch64ISD::CMHS: return fastEmit_AArch64ISD_CMHS_rr(VT, RetVT, Op0, Op1); |
13795 | 0 | case AArch64ISD::FCMEQ: return fastEmit_AArch64ISD_FCMEQ_rr(VT, RetVT, Op0, Op1); |
13796 | 0 | case AArch64ISD::FCMGE: return fastEmit_AArch64ISD_FCMGE_rr(VT, RetVT, Op0, Op1); |
13797 | 0 | case AArch64ISD::FCMGT: return fastEmit_AArch64ISD_FCMGT_rr(VT, RetVT, Op0, Op1); |
13798 | 0 | case AArch64ISD::FCMP: return fastEmit_AArch64ISD_FCMP_rr(VT, RetVT, Op0, Op1); |
13799 | 0 | case AArch64ISD::FRECPS: return fastEmit_AArch64ISD_FRECPS_rr(VT, RetVT, Op0, Op1); |
13800 | 0 | case AArch64ISD::FRSQRTS: return fastEmit_AArch64ISD_FRSQRTS_rr(VT, RetVT, Op0, Op1); |
13801 | 0 | case AArch64ISD::PMULL: return fastEmit_AArch64ISD_PMULL_rr(VT, RetVT, Op0, Op1); |
13802 | 0 | case AArch64ISD::PTEST: return fastEmit_AArch64ISD_PTEST_rr(VT, RetVT, Op0, Op1); |
13803 | 0 | case AArch64ISD::PTEST_ANY: return fastEmit_AArch64ISD_PTEST_ANY_rr(VT, RetVT, Op0, Op1); |
13804 | 0 | case AArch64ISD::SMULL: return fastEmit_AArch64ISD_SMULL_rr(VT, RetVT, Op0, Op1); |
13805 | 0 | case AArch64ISD::STRICT_FCMP: return fastEmit_AArch64ISD_STRICT_FCMP_rr(VT, RetVT, Op0, Op1); |
13806 | 0 | case AArch64ISD::STRICT_FCMPE: return fastEmit_AArch64ISD_STRICT_FCMPE_rr(VT, RetVT, Op0, Op1); |
13807 | 0 | case AArch64ISD::TBL: return fastEmit_AArch64ISD_TBL_rr(VT, RetVT, Op0, Op1); |
13808 | 0 | case AArch64ISD::TRN1: return fastEmit_AArch64ISD_TRN1_rr(VT, RetVT, Op0, Op1); |
13809 | 0 | case AArch64ISD::TRN2: return fastEmit_AArch64ISD_TRN2_rr(VT, RetVT, Op0, Op1); |
13810 | 0 | case AArch64ISD::UMULL: return fastEmit_AArch64ISD_UMULL_rr(VT, RetVT, Op0, Op1); |
13811 | 0 | case AArch64ISD::UZP1: return fastEmit_AArch64ISD_UZP1_rr(VT, RetVT, Op0, Op1); |
13812 | 0 | case AArch64ISD::UZP2: return fastEmit_AArch64ISD_UZP2_rr(VT, RetVT, Op0, Op1); |
13813 | 0 | case AArch64ISD::ZIP1: return fastEmit_AArch64ISD_ZIP1_rr(VT, RetVT, Op0, Op1); |
13814 | 0 | case AArch64ISD::ZIP2: return fastEmit_AArch64ISD_ZIP2_rr(VT, RetVT, Op0, Op1); |
13815 | 0 | case ISD::ABDS: return fastEmit_ISD_ABDS_rr(VT, RetVT, Op0, Op1); |
13816 | 0 | case ISD::ABDU: return fastEmit_ISD_ABDU_rr(VT, RetVT, Op0, Op1); |
13817 | 0 | case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op1); |
13818 | 0 | case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op1); |
13819 | 0 | case ISD::AVGCEILS: return fastEmit_ISD_AVGCEILS_rr(VT, RetVT, Op0, Op1); |
13820 | 0 | case ISD::AVGCEILU: return fastEmit_ISD_AVGCEILU_rr(VT, RetVT, Op0, Op1); |
13821 | 0 | case ISD::AVGFLOORS: return fastEmit_ISD_AVGFLOORS_rr(VT, RetVT, Op0, Op1); |
13822 | 0 | case ISD::AVGFLOORU: return fastEmit_ISD_AVGFLOORU_rr(VT, RetVT, Op0, Op1); |
13823 | 0 | case ISD::CONCAT_VECTORS: return fastEmit_ISD_CONCAT_VECTORS_rr(VT, RetVT, Op0, Op1); |
13824 | 0 | case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op1); |
13825 | 0 | case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op1); |
13826 | 0 | case ISD::FMAXIMUM: return fastEmit_ISD_FMAXIMUM_rr(VT, RetVT, Op0, Op1); |
13827 | 0 | case ISD::FMAXNUM: return fastEmit_ISD_FMAXNUM_rr(VT, RetVT, Op0, Op1); |
13828 | 0 | case ISD::FMINIMUM: return fastEmit_ISD_FMINIMUM_rr(VT, RetVT, Op0, Op1); |
13829 | 0 | case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op1); |
13830 | 0 | case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op1); |
13831 | 0 | case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op1); |
13832 | 0 | case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op1); |
13833 | 0 | case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op1); |
13834 | 0 | case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op1); |
13835 | 0 | case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op1); |
13836 | 0 | case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op1); |
13837 | 0 | case ISD::SADDSAT: return fastEmit_ISD_SADDSAT_rr(VT, RetVT, Op0, Op1); |
13838 | 0 | case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op1); |
13839 | 0 | case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op1); |
13840 | 0 | case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op1); |
13841 | 0 | case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op1); |
13842 | 0 | case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op1); |
13843 | 0 | case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op1); |
13844 | 0 | case ISD::SSUBSAT: return fastEmit_ISD_SSUBSAT_rr(VT, RetVT, Op0, Op1); |
13845 | 0 | case ISD::STRICT_FADD: return fastEmit_ISD_STRICT_FADD_rr(VT, RetVT, Op0, Op1); |
13846 | 0 | case ISD::STRICT_FDIV: return fastEmit_ISD_STRICT_FDIV_rr(VT, RetVT, Op0, Op1); |
13847 | 0 | case ISD::STRICT_FMAXIMUM: return fastEmit_ISD_STRICT_FMAXIMUM_rr(VT, RetVT, Op0, Op1); |
13848 | 0 | case ISD::STRICT_FMAXNUM: return fastEmit_ISD_STRICT_FMAXNUM_rr(VT, RetVT, Op0, Op1); |
13849 | 0 | case ISD::STRICT_FMINIMUM: return fastEmit_ISD_STRICT_FMINIMUM_rr(VT, RetVT, Op0, Op1); |
13850 | 0 | case ISD::STRICT_FMINNUM: return fastEmit_ISD_STRICT_FMINNUM_rr(VT, RetVT, Op0, Op1); |
13851 | 0 | case ISD::STRICT_FMUL: return fastEmit_ISD_STRICT_FMUL_rr(VT, RetVT, Op0, Op1); |
13852 | 0 | case ISD::STRICT_FSUB: return fastEmit_ISD_STRICT_FSUB_rr(VT, RetVT, Op0, Op1); |
13853 | 0 | case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op1); |
13854 | 0 | case ISD::UADDSAT: return fastEmit_ISD_UADDSAT_rr(VT, RetVT, Op0, Op1); |
13855 | 0 | case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op1); |
13856 | 0 | case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op1); |
13857 | 0 | case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op1); |
13858 | 0 | case ISD::USUBSAT: return fastEmit_ISD_USUBSAT_rr(VT, RetVT, Op0, Op1); |
13859 | 0 | case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op1); |
13860 | 0 | default: return 0; |
13861 | 0 | } |
13862 | 0 | } |
13863 | | |
13864 | | // FastEmit functions for AArch64ISD::DUPLANE64. |
13865 | | |
13866 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE64_MVT_v2i64_ri_Predicate_VectorIndexD(MVT RetVT, unsigned Op0, uint64_t imm1) { |
13867 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
13868 | 0 | return 0; |
13869 | 0 | if ((Subtarget->hasNEON())) { |
13870 | 0 | return fastEmitInst_ri(AArch64::DUPv2i64lane, &AArch64::FPR128RegClass, Op0, imm1); |
13871 | 0 | } |
13872 | 0 | return 0; |
13873 | 0 | } |
13874 | | |
13875 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE64_MVT_v2f64_ri_Predicate_VectorIndexD(MVT RetVT, unsigned Op0, uint64_t imm1) { |
13876 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
13877 | 0 | return 0; |
13878 | 0 | return fastEmitInst_ri(AArch64::DUPv2i64lane, &AArch64::FPR128RegClass, Op0, imm1); |
13879 | 0 | } |
13880 | | |
13881 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE64_ri_Predicate_VectorIndexD(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
13882 | 0 | switch (VT.SimpleTy) { |
13883 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_DUPLANE64_MVT_v2i64_ri_Predicate_VectorIndexD(RetVT, Op0, imm1); |
13884 | 0 | case MVT::v2f64: return fastEmit_AArch64ISD_DUPLANE64_MVT_v2f64_ri_Predicate_VectorIndexD(RetVT, Op0, imm1); |
13885 | 0 | default: return 0; |
13886 | 0 | } |
13887 | 0 | } |
13888 | | |
13889 | | // FastEmit functions for ISD::EXTRACT_VECTOR_ELT. |
13890 | | |
13891 | 0 | unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri_Predicate_VectorIndexD(MVT RetVT, unsigned Op0, uint64_t imm1) { |
13892 | 0 | if (RetVT.SimpleTy != MVT::i64) |
13893 | 0 | return 0; |
13894 | 0 | if ((Subtarget->hasNEON())) { |
13895 | 0 | return fastEmitInst_ri(AArch64::UMOVvi64, &AArch64::GPR64RegClass, Op0, imm1); |
13896 | 0 | } |
13897 | 0 | return 0; |
13898 | 0 | } |
13899 | | |
13900 | 0 | unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_VectorIndexD(MVT RetVT, unsigned Op0, uint64_t imm1) { |
13901 | 0 | if (RetVT.SimpleTy != MVT::f64) |
13902 | 0 | return 0; |
13903 | 0 | return fastEmitInst_ri(AArch64::DUPi64, &AArch64::FPR64RegClass, Op0, imm1); |
13904 | 0 | } |
13905 | | |
13906 | 0 | unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexD(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
13907 | 0 | switch (VT.SimpleTy) { |
13908 | 0 | case MVT::v2i64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri_Predicate_VectorIndexD(RetVT, Op0, imm1); |
13909 | 0 | case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_VectorIndexD(RetVT, Op0, imm1); |
13910 | 0 | default: return 0; |
13911 | 0 | } |
13912 | 0 | } |
13913 | | |
13914 | | // Top-level FastEmit function. |
13915 | | |
13916 | 0 | unsigned fastEmit_ri_Predicate_VectorIndexD(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) { |
13917 | 0 | switch (Opcode) { |
13918 | 0 | case AArch64ISD::DUPLANE64: return fastEmit_AArch64ISD_DUPLANE64_ri_Predicate_VectorIndexD(VT, RetVT, Op0, imm1); |
13919 | 0 | case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexD(VT, RetVT, Op0, imm1); |
13920 | 0 | default: return 0; |
13921 | 0 | } |
13922 | 0 | } |
13923 | | |
13924 | | // FastEmit functions for AArch64ISD::DUPLANE32. |
13925 | | |
13926 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE32_MVT_v4i32_MVT_v2i32_ri_Predicate_VectorIndexS(unsigned Op0, uint64_t imm1) { |
13927 | 0 | if ((Subtarget->hasNEON())) { |
13928 | 0 | return fastEmitInst_ri(AArch64::DUPv2i32lane, &AArch64::FPR64RegClass, Op0, imm1); |
13929 | 0 | } |
13930 | 0 | return 0; |
13931 | 0 | } |
13932 | | |
13933 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE32_MVT_v4i32_MVT_v4i32_ri_Predicate_VectorIndexS(unsigned Op0, uint64_t imm1) { |
13934 | 0 | if ((Subtarget->hasNEON())) { |
13935 | 0 | return fastEmitInst_ri(AArch64::DUPv4i32lane, &AArch64::FPR128RegClass, Op0, imm1); |
13936 | 0 | } |
13937 | 0 | return 0; |
13938 | 0 | } |
13939 | | |
13940 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE32_MVT_v4i32_ri_Predicate_VectorIndexS(MVT RetVT, unsigned Op0, uint64_t imm1) { |
13941 | 0 | switch (RetVT.SimpleTy) { |
13942 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_DUPLANE32_MVT_v4i32_MVT_v2i32_ri_Predicate_VectorIndexS(Op0, imm1); |
13943 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_DUPLANE32_MVT_v4i32_MVT_v4i32_ri_Predicate_VectorIndexS(Op0, imm1); |
13944 | 0 | default: return 0; |
13945 | 0 | } |
13946 | 0 | } |
13947 | | |
13948 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE32_MVT_v4f32_MVT_v2f32_ri_Predicate_VectorIndexS(unsigned Op0, uint64_t imm1) { |
13949 | 0 | return fastEmitInst_ri(AArch64::DUPv2i32lane, &AArch64::FPR64RegClass, Op0, imm1); |
13950 | 0 | } |
13951 | | |
13952 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE32_MVT_v4f32_MVT_v4f32_ri_Predicate_VectorIndexS(unsigned Op0, uint64_t imm1) { |
13953 | 0 | return fastEmitInst_ri(AArch64::DUPv4i32lane, &AArch64::FPR128RegClass, Op0, imm1); |
13954 | 0 | } |
13955 | | |
13956 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE32_MVT_v4f32_ri_Predicate_VectorIndexS(MVT RetVT, unsigned Op0, uint64_t imm1) { |
13957 | 0 | switch (RetVT.SimpleTy) { |
13958 | 0 | case MVT::v2f32: return fastEmit_AArch64ISD_DUPLANE32_MVT_v4f32_MVT_v2f32_ri_Predicate_VectorIndexS(Op0, imm1); |
13959 | 0 | case MVT::v4f32: return fastEmit_AArch64ISD_DUPLANE32_MVT_v4f32_MVT_v4f32_ri_Predicate_VectorIndexS(Op0, imm1); |
13960 | 0 | default: return 0; |
13961 | 0 | } |
13962 | 0 | } |
13963 | | |
13964 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE32_ri_Predicate_VectorIndexS(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
13965 | 0 | switch (VT.SimpleTy) { |
13966 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_DUPLANE32_MVT_v4i32_ri_Predicate_VectorIndexS(RetVT, Op0, imm1); |
13967 | 0 | case MVT::v4f32: return fastEmit_AArch64ISD_DUPLANE32_MVT_v4f32_ri_Predicate_VectorIndexS(RetVT, Op0, imm1); |
13968 | 0 | default: return 0; |
13969 | 0 | } |
13970 | 0 | } |
13971 | | |
13972 | | // FastEmit functions for ISD::EXTRACT_VECTOR_ELT. |
13973 | | |
13974 | 0 | unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_VectorIndexS(MVT RetVT, unsigned Op0, uint64_t imm1) { |
13975 | 0 | if (RetVT.SimpleTy != MVT::i32) |
13976 | 0 | return 0; |
13977 | 0 | if ((Subtarget->hasNEON())) { |
13978 | 0 | return fastEmitInst_ri(AArch64::UMOVvi32, &AArch64::GPR32RegClass, Op0, imm1); |
13979 | 0 | } |
13980 | 0 | return 0; |
13981 | 0 | } |
13982 | | |
13983 | 0 | unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_VectorIndexS(MVT RetVT, unsigned Op0, uint64_t imm1) { |
13984 | 0 | if (RetVT.SimpleTy != MVT::f32) |
13985 | 0 | return 0; |
13986 | 0 | return fastEmitInst_ri(AArch64::DUPi32, &AArch64::FPR32RegClass, Op0, imm1); |
13987 | 0 | } |
13988 | | |
13989 | 0 | unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexS(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
13990 | 0 | switch (VT.SimpleTy) { |
13991 | 0 | case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_VectorIndexS(RetVT, Op0, imm1); |
13992 | 0 | case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_VectorIndexS(RetVT, Op0, imm1); |
13993 | 0 | default: return 0; |
13994 | 0 | } |
13995 | 0 | } |
13996 | | |
13997 | | // Top-level FastEmit function. |
13998 | | |
13999 | 0 | unsigned fastEmit_ri_Predicate_VectorIndexS(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) { |
14000 | 0 | switch (Opcode) { |
14001 | 0 | case AArch64ISD::DUPLANE32: return fastEmit_AArch64ISD_DUPLANE32_ri_Predicate_VectorIndexS(VT, RetVT, Op0, imm1); |
14002 | 0 | case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexS(VT, RetVT, Op0, imm1); |
14003 | 0 | default: return 0; |
14004 | 0 | } |
14005 | 0 | } |
14006 | | |
14007 | | // FastEmit functions for AArch64ISD::DUPLANE16. |
14008 | | |
14009 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE16_MVT_v8i16_MVT_v4i16_ri_Predicate_VectorIndexH(unsigned Op0, uint64_t imm1) { |
14010 | 0 | if ((Subtarget->hasNEON())) { |
14011 | 0 | return fastEmitInst_ri(AArch64::DUPv4i16lane, &AArch64::FPR64RegClass, Op0, imm1); |
14012 | 0 | } |
14013 | 0 | return 0; |
14014 | 0 | } |
14015 | | |
14016 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE16_MVT_v8i16_MVT_v8i16_ri_Predicate_VectorIndexH(unsigned Op0, uint64_t imm1) { |
14017 | 0 | if ((Subtarget->hasNEON())) { |
14018 | 0 | return fastEmitInst_ri(AArch64::DUPv8i16lane, &AArch64::FPR128RegClass, Op0, imm1); |
14019 | 0 | } |
14020 | 0 | return 0; |
14021 | 0 | } |
14022 | | |
14023 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE16_MVT_v8i16_ri_Predicate_VectorIndexH(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14024 | 0 | switch (RetVT.SimpleTy) { |
14025 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_DUPLANE16_MVT_v8i16_MVT_v4i16_ri_Predicate_VectorIndexH(Op0, imm1); |
14026 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_DUPLANE16_MVT_v8i16_MVT_v8i16_ri_Predicate_VectorIndexH(Op0, imm1); |
14027 | 0 | default: return 0; |
14028 | 0 | } |
14029 | 0 | } |
14030 | | |
14031 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE16_MVT_v8f16_MVT_v4f16_ri_Predicate_VectorIndexH(unsigned Op0, uint64_t imm1) { |
14032 | 0 | return fastEmitInst_ri(AArch64::DUPv4i16lane, &AArch64::FPR64RegClass, Op0, imm1); |
14033 | 0 | } |
14034 | | |
14035 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE16_MVT_v8f16_MVT_v8f16_ri_Predicate_VectorIndexH(unsigned Op0, uint64_t imm1) { |
14036 | 0 | return fastEmitInst_ri(AArch64::DUPv8i16lane, &AArch64::FPR128RegClass, Op0, imm1); |
14037 | 0 | } |
14038 | | |
14039 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE16_MVT_v8f16_ri_Predicate_VectorIndexH(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14040 | 0 | switch (RetVT.SimpleTy) { |
14041 | 0 | case MVT::v4f16: return fastEmit_AArch64ISD_DUPLANE16_MVT_v8f16_MVT_v4f16_ri_Predicate_VectorIndexH(Op0, imm1); |
14042 | 0 | case MVT::v8f16: return fastEmit_AArch64ISD_DUPLANE16_MVT_v8f16_MVT_v8f16_ri_Predicate_VectorIndexH(Op0, imm1); |
14043 | 0 | default: return 0; |
14044 | 0 | } |
14045 | 0 | } |
14046 | | |
14047 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE16_MVT_v8bf16_MVT_v4bf16_ri_Predicate_VectorIndexH(unsigned Op0, uint64_t imm1) { |
14048 | 0 | return fastEmitInst_ri(AArch64::DUPv4i16lane, &AArch64::FPR64RegClass, Op0, imm1); |
14049 | 0 | } |
14050 | | |
14051 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE16_MVT_v8bf16_MVT_v8bf16_ri_Predicate_VectorIndexH(unsigned Op0, uint64_t imm1) { |
14052 | 0 | return fastEmitInst_ri(AArch64::DUPv8i16lane, &AArch64::FPR128RegClass, Op0, imm1); |
14053 | 0 | } |
14054 | | |
14055 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE16_MVT_v8bf16_ri_Predicate_VectorIndexH(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14056 | 0 | switch (RetVT.SimpleTy) { |
14057 | 0 | case MVT::v4bf16: return fastEmit_AArch64ISD_DUPLANE16_MVT_v8bf16_MVT_v4bf16_ri_Predicate_VectorIndexH(Op0, imm1); |
14058 | 0 | case MVT::v8bf16: return fastEmit_AArch64ISD_DUPLANE16_MVT_v8bf16_MVT_v8bf16_ri_Predicate_VectorIndexH(Op0, imm1); |
14059 | 0 | default: return 0; |
14060 | 0 | } |
14061 | 0 | } |
14062 | | |
14063 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE16_ri_Predicate_VectorIndexH(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14064 | 0 | switch (VT.SimpleTy) { |
14065 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_DUPLANE16_MVT_v8i16_ri_Predicate_VectorIndexH(RetVT, Op0, imm1); |
14066 | 0 | case MVT::v8f16: return fastEmit_AArch64ISD_DUPLANE16_MVT_v8f16_ri_Predicate_VectorIndexH(RetVT, Op0, imm1); |
14067 | 0 | case MVT::v8bf16: return fastEmit_AArch64ISD_DUPLANE16_MVT_v8bf16_ri_Predicate_VectorIndexH(RetVT, Op0, imm1); |
14068 | 0 | default: return 0; |
14069 | 0 | } |
14070 | 0 | } |
14071 | | |
14072 | | // FastEmit functions for ISD::EXTRACT_VECTOR_ELT. |
14073 | | |
14074 | 0 | unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8i16_ri_Predicate_VectorIndexH(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14075 | 0 | if (RetVT.SimpleTy != MVT::i32) |
14076 | 0 | return 0; |
14077 | 0 | if ((Subtarget->hasNEON())) { |
14078 | 0 | return fastEmitInst_ri(AArch64::UMOVvi16, &AArch64::GPR32RegClass, Op0, imm1); |
14079 | 0 | } |
14080 | 0 | return 0; |
14081 | 0 | } |
14082 | | |
14083 | 0 | unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8f16_ri_Predicate_VectorIndexH(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14084 | 0 | if (RetVT.SimpleTy != MVT::f16) |
14085 | 0 | return 0; |
14086 | 0 | return fastEmitInst_ri(AArch64::DUPi16, &AArch64::FPR16RegClass, Op0, imm1); |
14087 | 0 | } |
14088 | | |
14089 | 0 | unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8bf16_ri_Predicate_VectorIndexH(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14090 | 0 | if (RetVT.SimpleTy != MVT::bf16) |
14091 | 0 | return 0; |
14092 | 0 | return fastEmitInst_ri(AArch64::DUPi16, &AArch64::FPR16RegClass, Op0, imm1); |
14093 | 0 | } |
14094 | | |
14095 | 0 | unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexH(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14096 | 0 | switch (VT.SimpleTy) { |
14097 | 0 | case MVT::v8i16: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8i16_ri_Predicate_VectorIndexH(RetVT, Op0, imm1); |
14098 | 0 | case MVT::v8f16: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8f16_ri_Predicate_VectorIndexH(RetVT, Op0, imm1); |
14099 | 0 | case MVT::v8bf16: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8bf16_ri_Predicate_VectorIndexH(RetVT, Op0, imm1); |
14100 | 0 | default: return 0; |
14101 | 0 | } |
14102 | 0 | } |
14103 | | |
14104 | | // Top-level FastEmit function. |
14105 | | |
14106 | 0 | unsigned fastEmit_ri_Predicate_VectorIndexH(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) { |
14107 | 0 | switch (Opcode) { |
14108 | 0 | case AArch64ISD::DUPLANE16: return fastEmit_AArch64ISD_DUPLANE16_ri_Predicate_VectorIndexH(VT, RetVT, Op0, imm1); |
14109 | 0 | case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexH(VT, RetVT, Op0, imm1); |
14110 | 0 | default: return 0; |
14111 | 0 | } |
14112 | 0 | } |
14113 | | |
14114 | | // FastEmit functions for AArch64ISD::DUPLANE8. |
14115 | | |
14116 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE8_MVT_v16i8_MVT_v8i8_ri_Predicate_VectorIndexB(unsigned Op0, uint64_t imm1) { |
14117 | 0 | if ((Subtarget->hasNEON())) { |
14118 | 0 | return fastEmitInst_ri(AArch64::DUPv8i8lane, &AArch64::FPR64RegClass, Op0, imm1); |
14119 | 0 | } |
14120 | 0 | return 0; |
14121 | 0 | } |
14122 | | |
14123 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE8_MVT_v16i8_MVT_v16i8_ri_Predicate_VectorIndexB(unsigned Op0, uint64_t imm1) { |
14124 | 0 | if ((Subtarget->hasNEON())) { |
14125 | 0 | return fastEmitInst_ri(AArch64::DUPv16i8lane, &AArch64::FPR128RegClass, Op0, imm1); |
14126 | 0 | } |
14127 | 0 | return 0; |
14128 | 0 | } |
14129 | | |
14130 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE8_MVT_v16i8_ri_Predicate_VectorIndexB(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14131 | 0 | switch (RetVT.SimpleTy) { |
14132 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_DUPLANE8_MVT_v16i8_MVT_v8i8_ri_Predicate_VectorIndexB(Op0, imm1); |
14133 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_DUPLANE8_MVT_v16i8_MVT_v16i8_ri_Predicate_VectorIndexB(Op0, imm1); |
14134 | 0 | default: return 0; |
14135 | 0 | } |
14136 | 0 | } |
14137 | | |
14138 | 0 | unsigned fastEmit_AArch64ISD_DUPLANE8_ri_Predicate_VectorIndexB(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14139 | 0 | switch (VT.SimpleTy) { |
14140 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_DUPLANE8_MVT_v16i8_ri_Predicate_VectorIndexB(RetVT, Op0, imm1); |
14141 | 0 | default: return 0; |
14142 | 0 | } |
14143 | 0 | } |
14144 | | |
14145 | | // FastEmit functions for ISD::EXTRACT_VECTOR_ELT. |
14146 | | |
14147 | 0 | unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v16i8_ri_Predicate_VectorIndexB(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14148 | 0 | if (RetVT.SimpleTy != MVT::i32) |
14149 | 0 | return 0; |
14150 | 0 | if ((Subtarget->hasNEON())) { |
14151 | 0 | return fastEmitInst_ri(AArch64::UMOVvi8, &AArch64::GPR32RegClass, Op0, imm1); |
14152 | 0 | } |
14153 | 0 | return 0; |
14154 | 0 | } |
14155 | | |
14156 | 0 | unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexB(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14157 | 0 | switch (VT.SimpleTy) { |
14158 | 0 | case MVT::v16i8: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v16i8_ri_Predicate_VectorIndexB(RetVT, Op0, imm1); |
14159 | 0 | default: return 0; |
14160 | 0 | } |
14161 | 0 | } |
14162 | | |
14163 | | // Top-level FastEmit function. |
14164 | | |
14165 | 0 | unsigned fastEmit_ri_Predicate_VectorIndexB(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) { |
14166 | 0 | switch (Opcode) { |
14167 | 0 | case AArch64ISD::DUPLANE8: return fastEmit_AArch64ISD_DUPLANE8_ri_Predicate_VectorIndexB(VT, RetVT, Op0, imm1); |
14168 | 0 | case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexB(VT, RetVT, Op0, imm1); |
14169 | 0 | default: return 0; |
14170 | 0 | } |
14171 | 0 | } |
14172 | | |
14173 | | // FastEmit functions for ISD::EXTRACT_VECTOR_ELT. |
14174 | | |
14175 | 0 | unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v16i8_ri_Predicate_VectorIndex0(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14176 | 0 | if (RetVT.SimpleTy != MVT::i32) |
14177 | 0 | return 0; |
14178 | 0 | if ((Subtarget->hasNEON() || Subtarget->hasSME())) { |
14179 | 0 | return fastEmitInst_ri(AArch64::UMOVvi8_idx0, &AArch64::GPR32RegClass, Op0, imm1); |
14180 | 0 | } |
14181 | 0 | return 0; |
14182 | 0 | } |
14183 | | |
14184 | 0 | unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8i16_ri_Predicate_VectorIndex0(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14185 | 0 | if (RetVT.SimpleTy != MVT::i32) |
14186 | 0 | return 0; |
14187 | 0 | if ((Subtarget->hasNEON() || Subtarget->hasSME())) { |
14188 | 0 | return fastEmitInst_ri(AArch64::UMOVvi16_idx0, &AArch64::GPR32RegClass, Op0, imm1); |
14189 | 0 | } |
14190 | 0 | return 0; |
14191 | 0 | } |
14192 | | |
14193 | 0 | unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_VectorIndex0(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14194 | 0 | if (RetVT.SimpleTy != MVT::i32) |
14195 | 0 | return 0; |
14196 | 0 | if ((Subtarget->hasNEON() || Subtarget->hasSME())) { |
14197 | 0 | return fastEmitInst_ri(AArch64::UMOVvi32_idx0, &AArch64::GPR32RegClass, Op0, imm1); |
14198 | 0 | } |
14199 | 0 | return 0; |
14200 | 0 | } |
14201 | | |
14202 | 0 | unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri_Predicate_VectorIndex0(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14203 | 0 | if (RetVT.SimpleTy != MVT::i64) |
14204 | 0 | return 0; |
14205 | 0 | if ((Subtarget->hasNEON() || Subtarget->hasSME())) { |
14206 | 0 | return fastEmitInst_ri(AArch64::UMOVvi64_idx0, &AArch64::GPR64RegClass, Op0, imm1); |
14207 | 0 | } |
14208 | 0 | return 0; |
14209 | 0 | } |
14210 | | |
14211 | 0 | unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndex0(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14212 | 0 | switch (VT.SimpleTy) { |
14213 | 0 | case MVT::v16i8: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v16i8_ri_Predicate_VectorIndex0(RetVT, Op0, imm1); |
14214 | 0 | case MVT::v8i16: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8i16_ri_Predicate_VectorIndex0(RetVT, Op0, imm1); |
14215 | 0 | case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_VectorIndex0(RetVT, Op0, imm1); |
14216 | 0 | case MVT::v2i64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri_Predicate_VectorIndex0(RetVT, Op0, imm1); |
14217 | 0 | default: return 0; |
14218 | 0 | } |
14219 | 0 | } |
14220 | | |
14221 | | // Top-level FastEmit function. |
14222 | | |
14223 | 0 | unsigned fastEmit_ri_Predicate_VectorIndex0(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) { |
14224 | 0 | switch (Opcode) { |
14225 | 0 | case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndex0(VT, RetVT, Op0, imm1); |
14226 | 0 | default: return 0; |
14227 | 0 | } |
14228 | 0 | } |
14229 | | |
14230 | | // FastEmit functions for AArch64ISD::SQSHLU_I. |
14231 | | |
14232 | 0 | unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14233 | 0 | if (RetVT.SimpleTy != MVT::i64) |
14234 | 0 | return 0; |
14235 | 0 | if ((Subtarget->hasNEON())) { |
14236 | 0 | return fastEmitInst_ri(AArch64::SQSHLUd, &AArch64::FPR64RegClass, Op0, imm1); |
14237 | 0 | } |
14238 | 0 | return 0; |
14239 | 0 | } |
14240 | | |
14241 | 0 | unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v1i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14242 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
14243 | 0 | return 0; |
14244 | 0 | if ((Subtarget->hasNEON())) { |
14245 | 0 | return fastEmitInst_ri(AArch64::SQSHLUd, &AArch64::FPR64RegClass, Op0, imm1); |
14246 | 0 | } |
14247 | 0 | return 0; |
14248 | 0 | } |
14249 | | |
14250 | 0 | unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v2i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14251 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
14252 | 0 | return 0; |
14253 | 0 | if ((Subtarget->hasNEON())) { |
14254 | 0 | return fastEmitInst_ri(AArch64::SQSHLUv2i64_shift, &AArch64::FPR128RegClass, Op0, imm1); |
14255 | 0 | } |
14256 | 0 | return 0; |
14257 | 0 | } |
14258 | | |
14259 | 0 | unsigned fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL64(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14260 | 0 | switch (VT.SimpleTy) { |
14261 | 0 | case MVT::i64: return fastEmit_AArch64ISD_SQSHLU_I_MVT_i64_ri_Predicate_vecshiftL64(RetVT, Op0, imm1); |
14262 | 0 | case MVT::v1i64: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v1i64_ri_Predicate_vecshiftL64(RetVT, Op0, imm1); |
14263 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v2i64_ri_Predicate_vecshiftL64(RetVT, Op0, imm1); |
14264 | 0 | default: return 0; |
14265 | 0 | } |
14266 | 0 | } |
14267 | | |
14268 | | // FastEmit functions for AArch64ISD::SQSHL_I. |
14269 | | |
14270 | 0 | unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14271 | 0 | if (RetVT.SimpleTy != MVT::i64) |
14272 | 0 | return 0; |
14273 | 0 | if ((Subtarget->hasNEON())) { |
14274 | 0 | return fastEmitInst_ri(AArch64::SQSHLd, &AArch64::FPR64RegClass, Op0, imm1); |
14275 | 0 | } |
14276 | 0 | return 0; |
14277 | 0 | } |
14278 | | |
14279 | 0 | unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v1i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14280 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
14281 | 0 | return 0; |
14282 | 0 | if ((Subtarget->hasNEON())) { |
14283 | 0 | return fastEmitInst_ri(AArch64::SQSHLd, &AArch64::FPR64RegClass, Op0, imm1); |
14284 | 0 | } |
14285 | 0 | return 0; |
14286 | 0 | } |
14287 | | |
14288 | 0 | unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v2i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14289 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
14290 | 0 | return 0; |
14291 | 0 | if ((Subtarget->hasNEON())) { |
14292 | 0 | return fastEmitInst_ri(AArch64::SQSHLv2i64_shift, &AArch64::FPR128RegClass, Op0, imm1); |
14293 | 0 | } |
14294 | 0 | return 0; |
14295 | 0 | } |
14296 | | |
14297 | 0 | unsigned fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL64(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14298 | 0 | switch (VT.SimpleTy) { |
14299 | 0 | case MVT::i64: return fastEmit_AArch64ISD_SQSHL_I_MVT_i64_ri_Predicate_vecshiftL64(RetVT, Op0, imm1); |
14300 | 0 | case MVT::v1i64: return fastEmit_AArch64ISD_SQSHL_I_MVT_v1i64_ri_Predicate_vecshiftL64(RetVT, Op0, imm1); |
14301 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_SQSHL_I_MVT_v2i64_ri_Predicate_vecshiftL64(RetVT, Op0, imm1); |
14302 | 0 | default: return 0; |
14303 | 0 | } |
14304 | 0 | } |
14305 | | |
14306 | | // FastEmit functions for AArch64ISD::UQSHL_I. |
14307 | | |
14308 | 0 | unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14309 | 0 | if (RetVT.SimpleTy != MVT::i64) |
14310 | 0 | return 0; |
14311 | 0 | if ((Subtarget->hasNEON())) { |
14312 | 0 | return fastEmitInst_ri(AArch64::UQSHLd, &AArch64::FPR64RegClass, Op0, imm1); |
14313 | 0 | } |
14314 | 0 | return 0; |
14315 | 0 | } |
14316 | | |
14317 | 0 | unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v1i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14318 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
14319 | 0 | return 0; |
14320 | 0 | if ((Subtarget->hasNEON())) { |
14321 | 0 | return fastEmitInst_ri(AArch64::UQSHLd, &AArch64::FPR64RegClass, Op0, imm1); |
14322 | 0 | } |
14323 | 0 | return 0; |
14324 | 0 | } |
14325 | | |
14326 | 0 | unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v2i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14327 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
14328 | 0 | return 0; |
14329 | 0 | if ((Subtarget->hasNEON())) { |
14330 | 0 | return fastEmitInst_ri(AArch64::UQSHLv2i64_shift, &AArch64::FPR128RegClass, Op0, imm1); |
14331 | 0 | } |
14332 | 0 | return 0; |
14333 | 0 | } |
14334 | | |
14335 | 0 | unsigned fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL64(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14336 | 0 | switch (VT.SimpleTy) { |
14337 | 0 | case MVT::i64: return fastEmit_AArch64ISD_UQSHL_I_MVT_i64_ri_Predicate_vecshiftL64(RetVT, Op0, imm1); |
14338 | 0 | case MVT::v1i64: return fastEmit_AArch64ISD_UQSHL_I_MVT_v1i64_ri_Predicate_vecshiftL64(RetVT, Op0, imm1); |
14339 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_UQSHL_I_MVT_v2i64_ri_Predicate_vecshiftL64(RetVT, Op0, imm1); |
14340 | 0 | default: return 0; |
14341 | 0 | } |
14342 | 0 | } |
14343 | | |
14344 | | // FastEmit functions for AArch64ISD::VSHL. |
14345 | | |
14346 | 0 | unsigned fastEmit_AArch64ISD_VSHL_MVT_i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14347 | 0 | if (RetVT.SimpleTy != MVT::i64) |
14348 | 0 | return 0; |
14349 | 0 | if ((Subtarget->hasNEON())) { |
14350 | 0 | return fastEmitInst_ri(AArch64::SHLd, &AArch64::FPR64RegClass, Op0, imm1); |
14351 | 0 | } |
14352 | 0 | return 0; |
14353 | 0 | } |
14354 | | |
14355 | 0 | unsigned fastEmit_AArch64ISD_VSHL_MVT_v1i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14356 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
14357 | 0 | return 0; |
14358 | 0 | if ((Subtarget->hasNEON())) { |
14359 | 0 | return fastEmitInst_ri(AArch64::SHLd, &AArch64::FPR64RegClass, Op0, imm1); |
14360 | 0 | } |
14361 | 0 | return 0; |
14362 | 0 | } |
14363 | | |
14364 | 0 | unsigned fastEmit_AArch64ISD_VSHL_MVT_v2i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14365 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
14366 | 0 | return 0; |
14367 | 0 | if ((Subtarget->hasNEON())) { |
14368 | 0 | return fastEmitInst_ri(AArch64::SHLv2i64_shift, &AArch64::FPR128RegClass, Op0, imm1); |
14369 | 0 | } |
14370 | 0 | return 0; |
14371 | 0 | } |
14372 | | |
14373 | 0 | unsigned fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL64(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14374 | 0 | switch (VT.SimpleTy) { |
14375 | 0 | case MVT::i64: return fastEmit_AArch64ISD_VSHL_MVT_i64_ri_Predicate_vecshiftL64(RetVT, Op0, imm1); |
14376 | 0 | case MVT::v1i64: return fastEmit_AArch64ISD_VSHL_MVT_v1i64_ri_Predicate_vecshiftL64(RetVT, Op0, imm1); |
14377 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_VSHL_MVT_v2i64_ri_Predicate_vecshiftL64(RetVT, Op0, imm1); |
14378 | 0 | default: return 0; |
14379 | 0 | } |
14380 | 0 | } |
14381 | | |
14382 | | // Top-level FastEmit function. |
14383 | | |
14384 | 0 | unsigned fastEmit_ri_Predicate_vecshiftL64(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) { |
14385 | 0 | switch (Opcode) { |
14386 | 0 | case AArch64ISD::SQSHLU_I: return fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL64(VT, RetVT, Op0, imm1); |
14387 | 0 | case AArch64ISD::SQSHL_I: return fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL64(VT, RetVT, Op0, imm1); |
14388 | 0 | case AArch64ISD::UQSHL_I: return fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL64(VT, RetVT, Op0, imm1); |
14389 | 0 | case AArch64ISD::VSHL: return fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL64(VT, RetVT, Op0, imm1); |
14390 | 0 | default: return 0; |
14391 | 0 | } |
14392 | 0 | } |
14393 | | |
14394 | | // FastEmit functions for AArch64ISD::SQSHLU_I. |
14395 | | |
14396 | 0 | unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14397 | 0 | if (RetVT.SimpleTy != MVT::i32) |
14398 | 0 | return 0; |
14399 | 0 | if ((Subtarget->hasNEON())) { |
14400 | 0 | return fastEmitInst_ri(AArch64::SQSHLUs, &AArch64::FPR32RegClass, Op0, imm1); |
14401 | 0 | } |
14402 | 0 | return 0; |
14403 | 0 | } |
14404 | | |
14405 | 0 | unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v2i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14406 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
14407 | 0 | return 0; |
14408 | 0 | if ((Subtarget->hasNEON())) { |
14409 | 0 | return fastEmitInst_ri(AArch64::SQSHLUv2i32_shift, &AArch64::FPR64RegClass, Op0, imm1); |
14410 | 0 | } |
14411 | 0 | return 0; |
14412 | 0 | } |
14413 | | |
14414 | 0 | unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v4i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14415 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
14416 | 0 | return 0; |
14417 | 0 | if ((Subtarget->hasNEON())) { |
14418 | 0 | return fastEmitInst_ri(AArch64::SQSHLUv4i32_shift, &AArch64::FPR128RegClass, Op0, imm1); |
14419 | 0 | } |
14420 | 0 | return 0; |
14421 | 0 | } |
14422 | | |
14423 | 0 | unsigned fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL32(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14424 | 0 | switch (VT.SimpleTy) { |
14425 | 0 | case MVT::i32: return fastEmit_AArch64ISD_SQSHLU_I_MVT_i32_ri_Predicate_vecshiftL32(RetVT, Op0, imm1); |
14426 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v2i32_ri_Predicate_vecshiftL32(RetVT, Op0, imm1); |
14427 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v4i32_ri_Predicate_vecshiftL32(RetVT, Op0, imm1); |
14428 | 0 | default: return 0; |
14429 | 0 | } |
14430 | 0 | } |
14431 | | |
14432 | | // FastEmit functions for AArch64ISD::SQSHL_I. |
14433 | | |
14434 | 0 | unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14435 | 0 | if (RetVT.SimpleTy != MVT::i32) |
14436 | 0 | return 0; |
14437 | 0 | if ((Subtarget->hasNEON())) { |
14438 | 0 | return fastEmitInst_ri(AArch64::SQSHLs, &AArch64::FPR32RegClass, Op0, imm1); |
14439 | 0 | } |
14440 | 0 | return 0; |
14441 | 0 | } |
14442 | | |
14443 | 0 | unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v2i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14444 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
14445 | 0 | return 0; |
14446 | 0 | if ((Subtarget->hasNEON())) { |
14447 | 0 | return fastEmitInst_ri(AArch64::SQSHLv2i32_shift, &AArch64::FPR64RegClass, Op0, imm1); |
14448 | 0 | } |
14449 | 0 | return 0; |
14450 | 0 | } |
14451 | | |
14452 | 0 | unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v4i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14453 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
14454 | 0 | return 0; |
14455 | 0 | if ((Subtarget->hasNEON())) { |
14456 | 0 | return fastEmitInst_ri(AArch64::SQSHLv4i32_shift, &AArch64::FPR128RegClass, Op0, imm1); |
14457 | 0 | } |
14458 | 0 | return 0; |
14459 | 0 | } |
14460 | | |
14461 | 0 | unsigned fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL32(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14462 | 0 | switch (VT.SimpleTy) { |
14463 | 0 | case MVT::i32: return fastEmit_AArch64ISD_SQSHL_I_MVT_i32_ri_Predicate_vecshiftL32(RetVT, Op0, imm1); |
14464 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_SQSHL_I_MVT_v2i32_ri_Predicate_vecshiftL32(RetVT, Op0, imm1); |
14465 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_SQSHL_I_MVT_v4i32_ri_Predicate_vecshiftL32(RetVT, Op0, imm1); |
14466 | 0 | default: return 0; |
14467 | 0 | } |
14468 | 0 | } |
14469 | | |
14470 | | // FastEmit functions for AArch64ISD::UQSHL_I. |
14471 | | |
14472 | 0 | unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14473 | 0 | if (RetVT.SimpleTy != MVT::i32) |
14474 | 0 | return 0; |
14475 | 0 | if ((Subtarget->hasNEON())) { |
14476 | 0 | return fastEmitInst_ri(AArch64::UQSHLs, &AArch64::FPR32RegClass, Op0, imm1); |
14477 | 0 | } |
14478 | 0 | return 0; |
14479 | 0 | } |
14480 | | |
14481 | 0 | unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v2i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14482 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
14483 | 0 | return 0; |
14484 | 0 | if ((Subtarget->hasNEON())) { |
14485 | 0 | return fastEmitInst_ri(AArch64::UQSHLv2i32_shift, &AArch64::FPR64RegClass, Op0, imm1); |
14486 | 0 | } |
14487 | 0 | return 0; |
14488 | 0 | } |
14489 | | |
14490 | 0 | unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v4i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14491 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
14492 | 0 | return 0; |
14493 | 0 | if ((Subtarget->hasNEON())) { |
14494 | 0 | return fastEmitInst_ri(AArch64::UQSHLv4i32_shift, &AArch64::FPR128RegClass, Op0, imm1); |
14495 | 0 | } |
14496 | 0 | return 0; |
14497 | 0 | } |
14498 | | |
14499 | 0 | unsigned fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL32(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14500 | 0 | switch (VT.SimpleTy) { |
14501 | 0 | case MVT::i32: return fastEmit_AArch64ISD_UQSHL_I_MVT_i32_ri_Predicate_vecshiftL32(RetVT, Op0, imm1); |
14502 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_UQSHL_I_MVT_v2i32_ri_Predicate_vecshiftL32(RetVT, Op0, imm1); |
14503 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_UQSHL_I_MVT_v4i32_ri_Predicate_vecshiftL32(RetVT, Op0, imm1); |
14504 | 0 | default: return 0; |
14505 | 0 | } |
14506 | 0 | } |
14507 | | |
14508 | | // FastEmit functions for AArch64ISD::VSHL. |
14509 | | |
14510 | 0 | unsigned fastEmit_AArch64ISD_VSHL_MVT_v2i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14511 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
14512 | 0 | return 0; |
14513 | 0 | if ((Subtarget->hasNEON())) { |
14514 | 0 | return fastEmitInst_ri(AArch64::SHLv2i32_shift, &AArch64::FPR64RegClass, Op0, imm1); |
14515 | 0 | } |
14516 | 0 | return 0; |
14517 | 0 | } |
14518 | | |
14519 | 0 | unsigned fastEmit_AArch64ISD_VSHL_MVT_v4i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14520 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
14521 | 0 | return 0; |
14522 | 0 | if ((Subtarget->hasNEON())) { |
14523 | 0 | return fastEmitInst_ri(AArch64::SHLv4i32_shift, &AArch64::FPR128RegClass, Op0, imm1); |
14524 | 0 | } |
14525 | 0 | return 0; |
14526 | 0 | } |
14527 | | |
14528 | 0 | unsigned fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL32(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14529 | 0 | switch (VT.SimpleTy) { |
14530 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_VSHL_MVT_v2i32_ri_Predicate_vecshiftL32(RetVT, Op0, imm1); |
14531 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_VSHL_MVT_v4i32_ri_Predicate_vecshiftL32(RetVT, Op0, imm1); |
14532 | 0 | default: return 0; |
14533 | 0 | } |
14534 | 0 | } |
14535 | | |
14536 | | // Top-level FastEmit function. |
14537 | | |
14538 | 0 | unsigned fastEmit_ri_Predicate_vecshiftL32(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) { |
14539 | 0 | switch (Opcode) { |
14540 | 0 | case AArch64ISD::SQSHLU_I: return fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL32(VT, RetVT, Op0, imm1); |
14541 | 0 | case AArch64ISD::SQSHL_I: return fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL32(VT, RetVT, Op0, imm1); |
14542 | 0 | case AArch64ISD::UQSHL_I: return fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL32(VT, RetVT, Op0, imm1); |
14543 | 0 | case AArch64ISD::VSHL: return fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL32(VT, RetVT, Op0, imm1); |
14544 | 0 | default: return 0; |
14545 | 0 | } |
14546 | 0 | } |
14547 | | |
14548 | | // FastEmit functions for AArch64ISD::SRSHR_I. |
14549 | | |
14550 | 0 | unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14551 | 0 | if (RetVT.SimpleTy != MVT::i64) |
14552 | 0 | return 0; |
14553 | 0 | if ((Subtarget->hasNEON())) { |
14554 | 0 | return fastEmitInst_ri(AArch64::SRSHRd, &AArch64::FPR64RegClass, Op0, imm1); |
14555 | 0 | } |
14556 | 0 | return 0; |
14557 | 0 | } |
14558 | | |
14559 | 0 | unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v1i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14560 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
14561 | 0 | return 0; |
14562 | 0 | if ((Subtarget->hasNEON())) { |
14563 | 0 | return fastEmitInst_ri(AArch64::SRSHRd, &AArch64::FPR64RegClass, Op0, imm1); |
14564 | 0 | } |
14565 | 0 | return 0; |
14566 | 0 | } |
14567 | | |
14568 | 0 | unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v2i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14569 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
14570 | 0 | return 0; |
14571 | 0 | if ((Subtarget->hasNEON())) { |
14572 | 0 | return fastEmitInst_ri(AArch64::SRSHRv2i64_shift, &AArch64::FPR128RegClass, Op0, imm1); |
14573 | 0 | } |
14574 | 0 | return 0; |
14575 | 0 | } |
14576 | | |
14577 | 0 | unsigned fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR64(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14578 | 0 | switch (VT.SimpleTy) { |
14579 | 0 | case MVT::i64: return fastEmit_AArch64ISD_SRSHR_I_MVT_i64_ri_Predicate_vecshiftR64(RetVT, Op0, imm1); |
14580 | 0 | case MVT::v1i64: return fastEmit_AArch64ISD_SRSHR_I_MVT_v1i64_ri_Predicate_vecshiftR64(RetVT, Op0, imm1); |
14581 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_SRSHR_I_MVT_v2i64_ri_Predicate_vecshiftR64(RetVT, Op0, imm1); |
14582 | 0 | default: return 0; |
14583 | 0 | } |
14584 | 0 | } |
14585 | | |
14586 | | // FastEmit functions for AArch64ISD::URSHR_I. |
14587 | | |
14588 | 0 | unsigned fastEmit_AArch64ISD_URSHR_I_MVT_i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14589 | 0 | if (RetVT.SimpleTy != MVT::i64) |
14590 | 0 | return 0; |
14591 | 0 | if ((Subtarget->hasNEON())) { |
14592 | 0 | return fastEmitInst_ri(AArch64::URSHRd, &AArch64::FPR64RegClass, Op0, imm1); |
14593 | 0 | } |
14594 | 0 | return 0; |
14595 | 0 | } |
14596 | | |
14597 | 0 | unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v1i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14598 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
14599 | 0 | return 0; |
14600 | 0 | if ((Subtarget->hasNEON())) { |
14601 | 0 | return fastEmitInst_ri(AArch64::URSHRd, &AArch64::FPR64RegClass, Op0, imm1); |
14602 | 0 | } |
14603 | 0 | return 0; |
14604 | 0 | } |
14605 | | |
14606 | 0 | unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v2i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14607 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
14608 | 0 | return 0; |
14609 | 0 | if ((Subtarget->hasNEON())) { |
14610 | 0 | return fastEmitInst_ri(AArch64::URSHRv2i64_shift, &AArch64::FPR128RegClass, Op0, imm1); |
14611 | 0 | } |
14612 | 0 | return 0; |
14613 | 0 | } |
14614 | | |
14615 | 0 | unsigned fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR64(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14616 | 0 | switch (VT.SimpleTy) { |
14617 | 0 | case MVT::i64: return fastEmit_AArch64ISD_URSHR_I_MVT_i64_ri_Predicate_vecshiftR64(RetVT, Op0, imm1); |
14618 | 0 | case MVT::v1i64: return fastEmit_AArch64ISD_URSHR_I_MVT_v1i64_ri_Predicate_vecshiftR64(RetVT, Op0, imm1); |
14619 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_URSHR_I_MVT_v2i64_ri_Predicate_vecshiftR64(RetVT, Op0, imm1); |
14620 | 0 | default: return 0; |
14621 | 0 | } |
14622 | 0 | } |
14623 | | |
14624 | | // FastEmit functions for AArch64ISD::VASHR. |
14625 | | |
14626 | 0 | unsigned fastEmit_AArch64ISD_VASHR_MVT_i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14627 | 0 | if (RetVT.SimpleTy != MVT::i64) |
14628 | 0 | return 0; |
14629 | 0 | if ((Subtarget->hasNEON())) { |
14630 | 0 | return fastEmitInst_ri(AArch64::SSHRd, &AArch64::FPR64RegClass, Op0, imm1); |
14631 | 0 | } |
14632 | 0 | return 0; |
14633 | 0 | } |
14634 | | |
14635 | 0 | unsigned fastEmit_AArch64ISD_VASHR_MVT_v1i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14636 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
14637 | 0 | return 0; |
14638 | 0 | if ((Subtarget->hasNEON())) { |
14639 | 0 | return fastEmitInst_ri(AArch64::SSHRd, &AArch64::FPR64RegClass, Op0, imm1); |
14640 | 0 | } |
14641 | 0 | return 0; |
14642 | 0 | } |
14643 | | |
14644 | 0 | unsigned fastEmit_AArch64ISD_VASHR_MVT_v2i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14645 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
14646 | 0 | return 0; |
14647 | 0 | if ((Subtarget->hasNEON())) { |
14648 | 0 | return fastEmitInst_ri(AArch64::SSHRv2i64_shift, &AArch64::FPR128RegClass, Op0, imm1); |
14649 | 0 | } |
14650 | 0 | return 0; |
14651 | 0 | } |
14652 | | |
14653 | 0 | unsigned fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR64(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14654 | 0 | switch (VT.SimpleTy) { |
14655 | 0 | case MVT::i64: return fastEmit_AArch64ISD_VASHR_MVT_i64_ri_Predicate_vecshiftR64(RetVT, Op0, imm1); |
14656 | 0 | case MVT::v1i64: return fastEmit_AArch64ISD_VASHR_MVT_v1i64_ri_Predicate_vecshiftR64(RetVT, Op0, imm1); |
14657 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_VASHR_MVT_v2i64_ri_Predicate_vecshiftR64(RetVT, Op0, imm1); |
14658 | 0 | default: return 0; |
14659 | 0 | } |
14660 | 0 | } |
14661 | | |
14662 | | // FastEmit functions for AArch64ISD::VLSHR. |
14663 | | |
14664 | 0 | unsigned fastEmit_AArch64ISD_VLSHR_MVT_i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14665 | 0 | if (RetVT.SimpleTy != MVT::i64) |
14666 | 0 | return 0; |
14667 | 0 | if ((Subtarget->hasNEON())) { |
14668 | 0 | return fastEmitInst_ri(AArch64::USHRd, &AArch64::FPR64RegClass, Op0, imm1); |
14669 | 0 | } |
14670 | 0 | return 0; |
14671 | 0 | } |
14672 | | |
14673 | 0 | unsigned fastEmit_AArch64ISD_VLSHR_MVT_v1i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14674 | 0 | if (RetVT.SimpleTy != MVT::v1i64) |
14675 | 0 | return 0; |
14676 | 0 | if ((Subtarget->hasNEON())) { |
14677 | 0 | return fastEmitInst_ri(AArch64::USHRd, &AArch64::FPR64RegClass, Op0, imm1); |
14678 | 0 | } |
14679 | 0 | return 0; |
14680 | 0 | } |
14681 | | |
14682 | 0 | unsigned fastEmit_AArch64ISD_VLSHR_MVT_v2i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14683 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
14684 | 0 | return 0; |
14685 | 0 | if ((Subtarget->hasNEON())) { |
14686 | 0 | return fastEmitInst_ri(AArch64::USHRv2i64_shift, &AArch64::FPR128RegClass, Op0, imm1); |
14687 | 0 | } |
14688 | 0 | return 0; |
14689 | 0 | } |
14690 | | |
14691 | 0 | unsigned fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR64(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14692 | 0 | switch (VT.SimpleTy) { |
14693 | 0 | case MVT::i64: return fastEmit_AArch64ISD_VLSHR_MVT_i64_ri_Predicate_vecshiftR64(RetVT, Op0, imm1); |
14694 | 0 | case MVT::v1i64: return fastEmit_AArch64ISD_VLSHR_MVT_v1i64_ri_Predicate_vecshiftR64(RetVT, Op0, imm1); |
14695 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_VLSHR_MVT_v2i64_ri_Predicate_vecshiftR64(RetVT, Op0, imm1); |
14696 | 0 | default: return 0; |
14697 | 0 | } |
14698 | 0 | } |
14699 | | |
14700 | | // Top-level FastEmit function. |
14701 | | |
14702 | 0 | unsigned fastEmit_ri_Predicate_vecshiftR64(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) { |
14703 | 0 | switch (Opcode) { |
14704 | 0 | case AArch64ISD::SRSHR_I: return fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR64(VT, RetVT, Op0, imm1); |
14705 | 0 | case AArch64ISD::URSHR_I: return fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR64(VT, RetVT, Op0, imm1); |
14706 | 0 | case AArch64ISD::VASHR: return fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR64(VT, RetVT, Op0, imm1); |
14707 | 0 | case AArch64ISD::VLSHR: return fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR64(VT, RetVT, Op0, imm1); |
14708 | 0 | default: return 0; |
14709 | 0 | } |
14710 | 0 | } |
14711 | | |
14712 | | // FastEmit functions for AArch64ISD::SQSHLU_I. |
14713 | | |
14714 | 0 | unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v8i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14715 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
14716 | 0 | return 0; |
14717 | 0 | if ((Subtarget->hasNEON())) { |
14718 | 0 | return fastEmitInst_ri(AArch64::SQSHLUv8i8_shift, &AArch64::FPR64RegClass, Op0, imm1); |
14719 | 0 | } |
14720 | 0 | return 0; |
14721 | 0 | } |
14722 | | |
14723 | 0 | unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v16i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14724 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
14725 | 0 | return 0; |
14726 | 0 | if ((Subtarget->hasNEON())) { |
14727 | 0 | return fastEmitInst_ri(AArch64::SQSHLUv16i8_shift, &AArch64::FPR128RegClass, Op0, imm1); |
14728 | 0 | } |
14729 | 0 | return 0; |
14730 | 0 | } |
14731 | | |
14732 | 0 | unsigned fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL8(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14733 | 0 | switch (VT.SimpleTy) { |
14734 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v8i8_ri_Predicate_vecshiftL8(RetVT, Op0, imm1); |
14735 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v16i8_ri_Predicate_vecshiftL8(RetVT, Op0, imm1); |
14736 | 0 | default: return 0; |
14737 | 0 | } |
14738 | 0 | } |
14739 | | |
14740 | | // FastEmit functions for AArch64ISD::SQSHL_I. |
14741 | | |
14742 | 0 | unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v8i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14743 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
14744 | 0 | return 0; |
14745 | 0 | if ((Subtarget->hasNEON())) { |
14746 | 0 | return fastEmitInst_ri(AArch64::SQSHLv8i8_shift, &AArch64::FPR64RegClass, Op0, imm1); |
14747 | 0 | } |
14748 | 0 | return 0; |
14749 | 0 | } |
14750 | | |
14751 | 0 | unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v16i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14752 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
14753 | 0 | return 0; |
14754 | 0 | if ((Subtarget->hasNEON())) { |
14755 | 0 | return fastEmitInst_ri(AArch64::SQSHLv16i8_shift, &AArch64::FPR128RegClass, Op0, imm1); |
14756 | 0 | } |
14757 | 0 | return 0; |
14758 | 0 | } |
14759 | | |
14760 | 0 | unsigned fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL8(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14761 | 0 | switch (VT.SimpleTy) { |
14762 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_SQSHL_I_MVT_v8i8_ri_Predicate_vecshiftL8(RetVT, Op0, imm1); |
14763 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_SQSHL_I_MVT_v16i8_ri_Predicate_vecshiftL8(RetVT, Op0, imm1); |
14764 | 0 | default: return 0; |
14765 | 0 | } |
14766 | 0 | } |
14767 | | |
14768 | | // FastEmit functions for AArch64ISD::UQSHL_I. |
14769 | | |
14770 | 0 | unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v8i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14771 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
14772 | 0 | return 0; |
14773 | 0 | if ((Subtarget->hasNEON())) { |
14774 | 0 | return fastEmitInst_ri(AArch64::UQSHLv8i8_shift, &AArch64::FPR64RegClass, Op0, imm1); |
14775 | 0 | } |
14776 | 0 | return 0; |
14777 | 0 | } |
14778 | | |
14779 | 0 | unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v16i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14780 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
14781 | 0 | return 0; |
14782 | 0 | if ((Subtarget->hasNEON())) { |
14783 | 0 | return fastEmitInst_ri(AArch64::UQSHLv16i8_shift, &AArch64::FPR128RegClass, Op0, imm1); |
14784 | 0 | } |
14785 | 0 | return 0; |
14786 | 0 | } |
14787 | | |
14788 | 0 | unsigned fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL8(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14789 | 0 | switch (VT.SimpleTy) { |
14790 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_UQSHL_I_MVT_v8i8_ri_Predicate_vecshiftL8(RetVT, Op0, imm1); |
14791 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_UQSHL_I_MVT_v16i8_ri_Predicate_vecshiftL8(RetVT, Op0, imm1); |
14792 | 0 | default: return 0; |
14793 | 0 | } |
14794 | 0 | } |
14795 | | |
14796 | | // FastEmit functions for AArch64ISD::VSHL. |
14797 | | |
14798 | 0 | unsigned fastEmit_AArch64ISD_VSHL_MVT_v8i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14799 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
14800 | 0 | return 0; |
14801 | 0 | if ((Subtarget->hasNEON())) { |
14802 | 0 | return fastEmitInst_ri(AArch64::SHLv8i8_shift, &AArch64::FPR64RegClass, Op0, imm1); |
14803 | 0 | } |
14804 | 0 | return 0; |
14805 | 0 | } |
14806 | | |
14807 | 0 | unsigned fastEmit_AArch64ISD_VSHL_MVT_v16i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14808 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
14809 | 0 | return 0; |
14810 | 0 | if ((Subtarget->hasNEON())) { |
14811 | 0 | return fastEmitInst_ri(AArch64::SHLv16i8_shift, &AArch64::FPR128RegClass, Op0, imm1); |
14812 | 0 | } |
14813 | 0 | return 0; |
14814 | 0 | } |
14815 | | |
14816 | 0 | unsigned fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL8(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14817 | 0 | switch (VT.SimpleTy) { |
14818 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_VSHL_MVT_v8i8_ri_Predicate_vecshiftL8(RetVT, Op0, imm1); |
14819 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_VSHL_MVT_v16i8_ri_Predicate_vecshiftL8(RetVT, Op0, imm1); |
14820 | 0 | default: return 0; |
14821 | 0 | } |
14822 | 0 | } |
14823 | | |
14824 | | // Top-level FastEmit function. |
14825 | | |
14826 | 0 | unsigned fastEmit_ri_Predicate_vecshiftL8(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) { |
14827 | 0 | switch (Opcode) { |
14828 | 0 | case AArch64ISD::SQSHLU_I: return fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL8(VT, RetVT, Op0, imm1); |
14829 | 0 | case AArch64ISD::SQSHL_I: return fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL8(VT, RetVT, Op0, imm1); |
14830 | 0 | case AArch64ISD::UQSHL_I: return fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL8(VT, RetVT, Op0, imm1); |
14831 | 0 | case AArch64ISD::VSHL: return fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL8(VT, RetVT, Op0, imm1); |
14832 | 0 | default: return 0; |
14833 | 0 | } |
14834 | 0 | } |
14835 | | |
14836 | | // FastEmit functions for AArch64ISD::SQSHLU_I. |
14837 | | |
14838 | 0 | unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v4i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14839 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
14840 | 0 | return 0; |
14841 | 0 | if ((Subtarget->hasNEON())) { |
14842 | 0 | return fastEmitInst_ri(AArch64::SQSHLUv4i16_shift, &AArch64::FPR64RegClass, Op0, imm1); |
14843 | 0 | } |
14844 | 0 | return 0; |
14845 | 0 | } |
14846 | | |
14847 | 0 | unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v8i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14848 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
14849 | 0 | return 0; |
14850 | 0 | if ((Subtarget->hasNEON())) { |
14851 | 0 | return fastEmitInst_ri(AArch64::SQSHLUv8i16_shift, &AArch64::FPR128RegClass, Op0, imm1); |
14852 | 0 | } |
14853 | 0 | return 0; |
14854 | 0 | } |
14855 | | |
14856 | 0 | unsigned fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14857 | 0 | switch (VT.SimpleTy) { |
14858 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v4i16_ri_Predicate_vecshiftL16(RetVT, Op0, imm1); |
14859 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v8i16_ri_Predicate_vecshiftL16(RetVT, Op0, imm1); |
14860 | 0 | default: return 0; |
14861 | 0 | } |
14862 | 0 | } |
14863 | | |
14864 | | // FastEmit functions for AArch64ISD::SQSHL_I. |
14865 | | |
14866 | 0 | unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v4i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14867 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
14868 | 0 | return 0; |
14869 | 0 | if ((Subtarget->hasNEON())) { |
14870 | 0 | return fastEmitInst_ri(AArch64::SQSHLv4i16_shift, &AArch64::FPR64RegClass, Op0, imm1); |
14871 | 0 | } |
14872 | 0 | return 0; |
14873 | 0 | } |
14874 | | |
14875 | 0 | unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v8i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14876 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
14877 | 0 | return 0; |
14878 | 0 | if ((Subtarget->hasNEON())) { |
14879 | 0 | return fastEmitInst_ri(AArch64::SQSHLv8i16_shift, &AArch64::FPR128RegClass, Op0, imm1); |
14880 | 0 | } |
14881 | 0 | return 0; |
14882 | 0 | } |
14883 | | |
14884 | 0 | unsigned fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14885 | 0 | switch (VT.SimpleTy) { |
14886 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_SQSHL_I_MVT_v4i16_ri_Predicate_vecshiftL16(RetVT, Op0, imm1); |
14887 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_SQSHL_I_MVT_v8i16_ri_Predicate_vecshiftL16(RetVT, Op0, imm1); |
14888 | 0 | default: return 0; |
14889 | 0 | } |
14890 | 0 | } |
14891 | | |
14892 | | // FastEmit functions for AArch64ISD::UQSHL_I. |
14893 | | |
14894 | 0 | unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v4i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14895 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
14896 | 0 | return 0; |
14897 | 0 | if ((Subtarget->hasNEON())) { |
14898 | 0 | return fastEmitInst_ri(AArch64::UQSHLv4i16_shift, &AArch64::FPR64RegClass, Op0, imm1); |
14899 | 0 | } |
14900 | 0 | return 0; |
14901 | 0 | } |
14902 | | |
14903 | 0 | unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v8i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14904 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
14905 | 0 | return 0; |
14906 | 0 | if ((Subtarget->hasNEON())) { |
14907 | 0 | return fastEmitInst_ri(AArch64::UQSHLv8i16_shift, &AArch64::FPR128RegClass, Op0, imm1); |
14908 | 0 | } |
14909 | 0 | return 0; |
14910 | 0 | } |
14911 | | |
14912 | 0 | unsigned fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14913 | 0 | switch (VT.SimpleTy) { |
14914 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_UQSHL_I_MVT_v4i16_ri_Predicate_vecshiftL16(RetVT, Op0, imm1); |
14915 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_UQSHL_I_MVT_v8i16_ri_Predicate_vecshiftL16(RetVT, Op0, imm1); |
14916 | 0 | default: return 0; |
14917 | 0 | } |
14918 | 0 | } |
14919 | | |
14920 | | // FastEmit functions for AArch64ISD::VSHL. |
14921 | | |
14922 | 0 | unsigned fastEmit_AArch64ISD_VSHL_MVT_v4i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14923 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
14924 | 0 | return 0; |
14925 | 0 | if ((Subtarget->hasNEON())) { |
14926 | 0 | return fastEmitInst_ri(AArch64::SHLv4i16_shift, &AArch64::FPR64RegClass, Op0, imm1); |
14927 | 0 | } |
14928 | 0 | return 0; |
14929 | 0 | } |
14930 | | |
14931 | 0 | unsigned fastEmit_AArch64ISD_VSHL_MVT_v8i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14932 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
14933 | 0 | return 0; |
14934 | 0 | if ((Subtarget->hasNEON())) { |
14935 | 0 | return fastEmitInst_ri(AArch64::SHLv8i16_shift, &AArch64::FPR128RegClass, Op0, imm1); |
14936 | 0 | } |
14937 | 0 | return 0; |
14938 | 0 | } |
14939 | | |
14940 | 0 | unsigned fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14941 | 0 | switch (VT.SimpleTy) { |
14942 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_VSHL_MVT_v4i16_ri_Predicate_vecshiftL16(RetVT, Op0, imm1); |
14943 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_VSHL_MVT_v8i16_ri_Predicate_vecshiftL16(RetVT, Op0, imm1); |
14944 | 0 | default: return 0; |
14945 | 0 | } |
14946 | 0 | } |
14947 | | |
14948 | | // Top-level FastEmit function. |
14949 | | |
14950 | 0 | unsigned fastEmit_ri_Predicate_vecshiftL16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) { |
14951 | 0 | switch (Opcode) { |
14952 | 0 | case AArch64ISD::SQSHLU_I: return fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL16(VT, RetVT, Op0, imm1); |
14953 | 0 | case AArch64ISD::SQSHL_I: return fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL16(VT, RetVT, Op0, imm1); |
14954 | 0 | case AArch64ISD::UQSHL_I: return fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL16(VT, RetVT, Op0, imm1); |
14955 | 0 | case AArch64ISD::VSHL: return fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL16(VT, RetVT, Op0, imm1); |
14956 | 0 | default: return 0; |
14957 | 0 | } |
14958 | 0 | } |
14959 | | |
14960 | | // FastEmit functions for AArch64ISD::SRSHR_I. |
14961 | | |
14962 | 0 | unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v8i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14963 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
14964 | 0 | return 0; |
14965 | 0 | if ((Subtarget->hasNEON())) { |
14966 | 0 | return fastEmitInst_ri(AArch64::SRSHRv8i8_shift, &AArch64::FPR64RegClass, Op0, imm1); |
14967 | 0 | } |
14968 | 0 | return 0; |
14969 | 0 | } |
14970 | | |
14971 | 0 | unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v16i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14972 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
14973 | 0 | return 0; |
14974 | 0 | if ((Subtarget->hasNEON())) { |
14975 | 0 | return fastEmitInst_ri(AArch64::SRSHRv16i8_shift, &AArch64::FPR128RegClass, Op0, imm1); |
14976 | 0 | } |
14977 | 0 | return 0; |
14978 | 0 | } |
14979 | | |
14980 | 0 | unsigned fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR8(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
14981 | 0 | switch (VT.SimpleTy) { |
14982 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_SRSHR_I_MVT_v8i8_ri_Predicate_vecshiftR8(RetVT, Op0, imm1); |
14983 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_SRSHR_I_MVT_v16i8_ri_Predicate_vecshiftR8(RetVT, Op0, imm1); |
14984 | 0 | default: return 0; |
14985 | 0 | } |
14986 | 0 | } |
14987 | | |
14988 | | // FastEmit functions for AArch64ISD::URSHR_I. |
14989 | | |
14990 | 0 | unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v8i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, uint64_t imm1) { |
14991 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
14992 | 0 | return 0; |
14993 | 0 | if ((Subtarget->hasNEON())) { |
14994 | 0 | return fastEmitInst_ri(AArch64::URSHRv8i8_shift, &AArch64::FPR64RegClass, Op0, imm1); |
14995 | 0 | } |
14996 | 0 | return 0; |
14997 | 0 | } |
14998 | | |
14999 | 0 | unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v16i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15000 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
15001 | 0 | return 0; |
15002 | 0 | if ((Subtarget->hasNEON())) { |
15003 | 0 | return fastEmitInst_ri(AArch64::URSHRv16i8_shift, &AArch64::FPR128RegClass, Op0, imm1); |
15004 | 0 | } |
15005 | 0 | return 0; |
15006 | 0 | } |
15007 | | |
15008 | 0 | unsigned fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR8(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
15009 | 0 | switch (VT.SimpleTy) { |
15010 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_URSHR_I_MVT_v8i8_ri_Predicate_vecshiftR8(RetVT, Op0, imm1); |
15011 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_URSHR_I_MVT_v16i8_ri_Predicate_vecshiftR8(RetVT, Op0, imm1); |
15012 | 0 | default: return 0; |
15013 | 0 | } |
15014 | 0 | } |
15015 | | |
15016 | | // FastEmit functions for AArch64ISD::VASHR. |
15017 | | |
15018 | 0 | unsigned fastEmit_AArch64ISD_VASHR_MVT_v8i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15019 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
15020 | 0 | return 0; |
15021 | 0 | if ((Subtarget->hasNEON())) { |
15022 | 0 | return fastEmitInst_ri(AArch64::SSHRv8i8_shift, &AArch64::FPR64RegClass, Op0, imm1); |
15023 | 0 | } |
15024 | 0 | return 0; |
15025 | 0 | } |
15026 | | |
15027 | 0 | unsigned fastEmit_AArch64ISD_VASHR_MVT_v16i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15028 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
15029 | 0 | return 0; |
15030 | 0 | if ((Subtarget->hasNEON())) { |
15031 | 0 | return fastEmitInst_ri(AArch64::SSHRv16i8_shift, &AArch64::FPR128RegClass, Op0, imm1); |
15032 | 0 | } |
15033 | 0 | return 0; |
15034 | 0 | } |
15035 | | |
15036 | 0 | unsigned fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR8(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
15037 | 0 | switch (VT.SimpleTy) { |
15038 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_VASHR_MVT_v8i8_ri_Predicate_vecshiftR8(RetVT, Op0, imm1); |
15039 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_VASHR_MVT_v16i8_ri_Predicate_vecshiftR8(RetVT, Op0, imm1); |
15040 | 0 | default: return 0; |
15041 | 0 | } |
15042 | 0 | } |
15043 | | |
15044 | | // FastEmit functions for AArch64ISD::VLSHR. |
15045 | | |
15046 | 0 | unsigned fastEmit_AArch64ISD_VLSHR_MVT_v8i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15047 | 0 | if (RetVT.SimpleTy != MVT::v8i8) |
15048 | 0 | return 0; |
15049 | 0 | if ((Subtarget->hasNEON())) { |
15050 | 0 | return fastEmitInst_ri(AArch64::USHRv8i8_shift, &AArch64::FPR64RegClass, Op0, imm1); |
15051 | 0 | } |
15052 | 0 | return 0; |
15053 | 0 | } |
15054 | | |
15055 | 0 | unsigned fastEmit_AArch64ISD_VLSHR_MVT_v16i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15056 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
15057 | 0 | return 0; |
15058 | 0 | if ((Subtarget->hasNEON())) { |
15059 | 0 | return fastEmitInst_ri(AArch64::USHRv16i8_shift, &AArch64::FPR128RegClass, Op0, imm1); |
15060 | 0 | } |
15061 | 0 | return 0; |
15062 | 0 | } |
15063 | | |
15064 | 0 | unsigned fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR8(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
15065 | 0 | switch (VT.SimpleTy) { |
15066 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_VLSHR_MVT_v8i8_ri_Predicate_vecshiftR8(RetVT, Op0, imm1); |
15067 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_VLSHR_MVT_v16i8_ri_Predicate_vecshiftR8(RetVT, Op0, imm1); |
15068 | 0 | default: return 0; |
15069 | 0 | } |
15070 | 0 | } |
15071 | | |
15072 | | // Top-level FastEmit function. |
15073 | | |
15074 | 0 | unsigned fastEmit_ri_Predicate_vecshiftR8(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) { |
15075 | 0 | switch (Opcode) { |
15076 | 0 | case AArch64ISD::SRSHR_I: return fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR8(VT, RetVT, Op0, imm1); |
15077 | 0 | case AArch64ISD::URSHR_I: return fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR8(VT, RetVT, Op0, imm1); |
15078 | 0 | case AArch64ISD::VASHR: return fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR8(VT, RetVT, Op0, imm1); |
15079 | 0 | case AArch64ISD::VLSHR: return fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR8(VT, RetVT, Op0, imm1); |
15080 | 0 | default: return 0; |
15081 | 0 | } |
15082 | 0 | } |
15083 | | |
15084 | | // FastEmit functions for AArch64ISD::SRSHR_I. |
15085 | | |
15086 | 0 | unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v4i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15087 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
15088 | 0 | return 0; |
15089 | 0 | if ((Subtarget->hasNEON())) { |
15090 | 0 | return fastEmitInst_ri(AArch64::SRSHRv4i16_shift, &AArch64::FPR64RegClass, Op0, imm1); |
15091 | 0 | } |
15092 | 0 | return 0; |
15093 | 0 | } |
15094 | | |
15095 | 0 | unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v8i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15096 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
15097 | 0 | return 0; |
15098 | 0 | if ((Subtarget->hasNEON())) { |
15099 | 0 | return fastEmitInst_ri(AArch64::SRSHRv8i16_shift, &AArch64::FPR128RegClass, Op0, imm1); |
15100 | 0 | } |
15101 | 0 | return 0; |
15102 | 0 | } |
15103 | | |
15104 | 0 | unsigned fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
15105 | 0 | switch (VT.SimpleTy) { |
15106 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_SRSHR_I_MVT_v4i16_ri_Predicate_vecshiftR16(RetVT, Op0, imm1); |
15107 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_SRSHR_I_MVT_v8i16_ri_Predicate_vecshiftR16(RetVT, Op0, imm1); |
15108 | 0 | default: return 0; |
15109 | 0 | } |
15110 | 0 | } |
15111 | | |
15112 | | // FastEmit functions for AArch64ISD::URSHR_I. |
15113 | | |
15114 | 0 | unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v4i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15115 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
15116 | 0 | return 0; |
15117 | 0 | if ((Subtarget->hasNEON())) { |
15118 | 0 | return fastEmitInst_ri(AArch64::URSHRv4i16_shift, &AArch64::FPR64RegClass, Op0, imm1); |
15119 | 0 | } |
15120 | 0 | return 0; |
15121 | 0 | } |
15122 | | |
15123 | 0 | unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v8i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15124 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
15125 | 0 | return 0; |
15126 | 0 | if ((Subtarget->hasNEON())) { |
15127 | 0 | return fastEmitInst_ri(AArch64::URSHRv8i16_shift, &AArch64::FPR128RegClass, Op0, imm1); |
15128 | 0 | } |
15129 | 0 | return 0; |
15130 | 0 | } |
15131 | | |
15132 | 0 | unsigned fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
15133 | 0 | switch (VT.SimpleTy) { |
15134 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_URSHR_I_MVT_v4i16_ri_Predicate_vecshiftR16(RetVT, Op0, imm1); |
15135 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_URSHR_I_MVT_v8i16_ri_Predicate_vecshiftR16(RetVT, Op0, imm1); |
15136 | 0 | default: return 0; |
15137 | 0 | } |
15138 | 0 | } |
15139 | | |
15140 | | // FastEmit functions for AArch64ISD::VASHR. |
15141 | | |
15142 | 0 | unsigned fastEmit_AArch64ISD_VASHR_MVT_v4i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15143 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
15144 | 0 | return 0; |
15145 | 0 | if ((Subtarget->hasNEON())) { |
15146 | 0 | return fastEmitInst_ri(AArch64::SSHRv4i16_shift, &AArch64::FPR64RegClass, Op0, imm1); |
15147 | 0 | } |
15148 | 0 | return 0; |
15149 | 0 | } |
15150 | | |
15151 | 0 | unsigned fastEmit_AArch64ISD_VASHR_MVT_v8i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15152 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
15153 | 0 | return 0; |
15154 | 0 | if ((Subtarget->hasNEON())) { |
15155 | 0 | return fastEmitInst_ri(AArch64::SSHRv8i16_shift, &AArch64::FPR128RegClass, Op0, imm1); |
15156 | 0 | } |
15157 | 0 | return 0; |
15158 | 0 | } |
15159 | | |
15160 | 0 | unsigned fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
15161 | 0 | switch (VT.SimpleTy) { |
15162 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_VASHR_MVT_v4i16_ri_Predicate_vecshiftR16(RetVT, Op0, imm1); |
15163 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_VASHR_MVT_v8i16_ri_Predicate_vecshiftR16(RetVT, Op0, imm1); |
15164 | 0 | default: return 0; |
15165 | 0 | } |
15166 | 0 | } |
15167 | | |
15168 | | // FastEmit functions for AArch64ISD::VLSHR. |
15169 | | |
15170 | 0 | unsigned fastEmit_AArch64ISD_VLSHR_MVT_v4i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15171 | 0 | if (RetVT.SimpleTy != MVT::v4i16) |
15172 | 0 | return 0; |
15173 | 0 | if ((Subtarget->hasNEON())) { |
15174 | 0 | return fastEmitInst_ri(AArch64::USHRv4i16_shift, &AArch64::FPR64RegClass, Op0, imm1); |
15175 | 0 | } |
15176 | 0 | return 0; |
15177 | 0 | } |
15178 | | |
15179 | 0 | unsigned fastEmit_AArch64ISD_VLSHR_MVT_v8i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15180 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
15181 | 0 | return 0; |
15182 | 0 | if ((Subtarget->hasNEON())) { |
15183 | 0 | return fastEmitInst_ri(AArch64::USHRv8i16_shift, &AArch64::FPR128RegClass, Op0, imm1); |
15184 | 0 | } |
15185 | 0 | return 0; |
15186 | 0 | } |
15187 | | |
15188 | 0 | unsigned fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
15189 | 0 | switch (VT.SimpleTy) { |
15190 | 0 | case MVT::v4i16: return fastEmit_AArch64ISD_VLSHR_MVT_v4i16_ri_Predicate_vecshiftR16(RetVT, Op0, imm1); |
15191 | 0 | case MVT::v8i16: return fastEmit_AArch64ISD_VLSHR_MVT_v8i16_ri_Predicate_vecshiftR16(RetVT, Op0, imm1); |
15192 | 0 | default: return 0; |
15193 | 0 | } |
15194 | 0 | } |
15195 | | |
15196 | | // Top-level FastEmit function. |
15197 | | |
15198 | 0 | unsigned fastEmit_ri_Predicate_vecshiftR16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) { |
15199 | 0 | switch (Opcode) { |
15200 | 0 | case AArch64ISD::SRSHR_I: return fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR16(VT, RetVT, Op0, imm1); |
15201 | 0 | case AArch64ISD::URSHR_I: return fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR16(VT, RetVT, Op0, imm1); |
15202 | 0 | case AArch64ISD::VASHR: return fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR16(VT, RetVT, Op0, imm1); |
15203 | 0 | case AArch64ISD::VLSHR: return fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR16(VT, RetVT, Op0, imm1); |
15204 | 0 | default: return 0; |
15205 | 0 | } |
15206 | 0 | } |
15207 | | |
15208 | | // FastEmit functions for AArch64ISD::SRSHR_I. |
15209 | | |
15210 | 0 | unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v2i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15211 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
15212 | 0 | return 0; |
15213 | 0 | if ((Subtarget->hasNEON())) { |
15214 | 0 | return fastEmitInst_ri(AArch64::SRSHRv2i32_shift, &AArch64::FPR64RegClass, Op0, imm1); |
15215 | 0 | } |
15216 | 0 | return 0; |
15217 | 0 | } |
15218 | | |
15219 | 0 | unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v4i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15220 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
15221 | 0 | return 0; |
15222 | 0 | if ((Subtarget->hasNEON())) { |
15223 | 0 | return fastEmitInst_ri(AArch64::SRSHRv4i32_shift, &AArch64::FPR128RegClass, Op0, imm1); |
15224 | 0 | } |
15225 | 0 | return 0; |
15226 | 0 | } |
15227 | | |
15228 | 0 | unsigned fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR32(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
15229 | 0 | switch (VT.SimpleTy) { |
15230 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_SRSHR_I_MVT_v2i32_ri_Predicate_vecshiftR32(RetVT, Op0, imm1); |
15231 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_SRSHR_I_MVT_v4i32_ri_Predicate_vecshiftR32(RetVT, Op0, imm1); |
15232 | 0 | default: return 0; |
15233 | 0 | } |
15234 | 0 | } |
15235 | | |
15236 | | // FastEmit functions for AArch64ISD::URSHR_I. |
15237 | | |
15238 | 0 | unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v2i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15239 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
15240 | 0 | return 0; |
15241 | 0 | if ((Subtarget->hasNEON())) { |
15242 | 0 | return fastEmitInst_ri(AArch64::URSHRv2i32_shift, &AArch64::FPR64RegClass, Op0, imm1); |
15243 | 0 | } |
15244 | 0 | return 0; |
15245 | 0 | } |
15246 | | |
15247 | 0 | unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v4i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15248 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
15249 | 0 | return 0; |
15250 | 0 | if ((Subtarget->hasNEON())) { |
15251 | 0 | return fastEmitInst_ri(AArch64::URSHRv4i32_shift, &AArch64::FPR128RegClass, Op0, imm1); |
15252 | 0 | } |
15253 | 0 | return 0; |
15254 | 0 | } |
15255 | | |
15256 | 0 | unsigned fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR32(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
15257 | 0 | switch (VT.SimpleTy) { |
15258 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_URSHR_I_MVT_v2i32_ri_Predicate_vecshiftR32(RetVT, Op0, imm1); |
15259 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_URSHR_I_MVT_v4i32_ri_Predicate_vecshiftR32(RetVT, Op0, imm1); |
15260 | 0 | default: return 0; |
15261 | 0 | } |
15262 | 0 | } |
15263 | | |
15264 | | // FastEmit functions for AArch64ISD::VASHR. |
15265 | | |
15266 | 0 | unsigned fastEmit_AArch64ISD_VASHR_MVT_v2i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15267 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
15268 | 0 | return 0; |
15269 | 0 | if ((Subtarget->hasNEON())) { |
15270 | 0 | return fastEmitInst_ri(AArch64::SSHRv2i32_shift, &AArch64::FPR64RegClass, Op0, imm1); |
15271 | 0 | } |
15272 | 0 | return 0; |
15273 | 0 | } |
15274 | | |
15275 | 0 | unsigned fastEmit_AArch64ISD_VASHR_MVT_v4i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15276 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
15277 | 0 | return 0; |
15278 | 0 | if ((Subtarget->hasNEON())) { |
15279 | 0 | return fastEmitInst_ri(AArch64::SSHRv4i32_shift, &AArch64::FPR128RegClass, Op0, imm1); |
15280 | 0 | } |
15281 | 0 | return 0; |
15282 | 0 | } |
15283 | | |
15284 | 0 | unsigned fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR32(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
15285 | 0 | switch (VT.SimpleTy) { |
15286 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_VASHR_MVT_v2i32_ri_Predicate_vecshiftR32(RetVT, Op0, imm1); |
15287 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_VASHR_MVT_v4i32_ri_Predicate_vecshiftR32(RetVT, Op0, imm1); |
15288 | 0 | default: return 0; |
15289 | 0 | } |
15290 | 0 | } |
15291 | | |
15292 | | // FastEmit functions for AArch64ISD::VLSHR. |
15293 | | |
15294 | 0 | unsigned fastEmit_AArch64ISD_VLSHR_MVT_v2i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15295 | 0 | if (RetVT.SimpleTy != MVT::v2i32) |
15296 | 0 | return 0; |
15297 | 0 | if ((Subtarget->hasNEON())) { |
15298 | 0 | return fastEmitInst_ri(AArch64::USHRv2i32_shift, &AArch64::FPR64RegClass, Op0, imm1); |
15299 | 0 | } |
15300 | 0 | return 0; |
15301 | 0 | } |
15302 | | |
15303 | 0 | unsigned fastEmit_AArch64ISD_VLSHR_MVT_v4i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15304 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
15305 | 0 | return 0; |
15306 | 0 | if ((Subtarget->hasNEON())) { |
15307 | 0 | return fastEmitInst_ri(AArch64::USHRv4i32_shift, &AArch64::FPR128RegClass, Op0, imm1); |
15308 | 0 | } |
15309 | 0 | return 0; |
15310 | 0 | } |
15311 | | |
15312 | 0 | unsigned fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR32(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
15313 | 0 | switch (VT.SimpleTy) { |
15314 | 0 | case MVT::v2i32: return fastEmit_AArch64ISD_VLSHR_MVT_v2i32_ri_Predicate_vecshiftR32(RetVT, Op0, imm1); |
15315 | 0 | case MVT::v4i32: return fastEmit_AArch64ISD_VLSHR_MVT_v4i32_ri_Predicate_vecshiftR32(RetVT, Op0, imm1); |
15316 | 0 | default: return 0; |
15317 | 0 | } |
15318 | 0 | } |
15319 | | |
15320 | | // Top-level FastEmit function. |
15321 | | |
15322 | 0 | unsigned fastEmit_ri_Predicate_vecshiftR32(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) { |
15323 | 0 | switch (Opcode) { |
15324 | 0 | case AArch64ISD::SRSHR_I: return fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR32(VT, RetVT, Op0, imm1); |
15325 | 0 | case AArch64ISD::URSHR_I: return fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR32(VT, RetVT, Op0, imm1); |
15326 | 0 | case AArch64ISD::VASHR: return fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR32(VT, RetVT, Op0, imm1); |
15327 | 0 | case AArch64ISD::VLSHR: return fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR32(VT, RetVT, Op0, imm1); |
15328 | 0 | default: return 0; |
15329 | 0 | } |
15330 | 0 | } |
15331 | | |
15332 | | // FastEmit functions for ISD::SMAX. |
15333 | | |
15334 | 0 | unsigned fastEmit_ISD_SMAX_MVT_i32_ri_Predicate_simm8_32b(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15335 | 0 | if (RetVT.SimpleTy != MVT::i32) |
15336 | 0 | return 0; |
15337 | 0 | if ((Subtarget->hasCSSC())) { |
15338 | 0 | return fastEmitInst_ri(AArch64::SMAXWri, &AArch64::GPR32RegClass, Op0, imm1); |
15339 | 0 | } |
15340 | 0 | return 0; |
15341 | 0 | } |
15342 | | |
15343 | 0 | unsigned fastEmit_ISD_SMAX_ri_Predicate_simm8_32b(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
15344 | 0 | switch (VT.SimpleTy) { |
15345 | 0 | case MVT::i32: return fastEmit_ISD_SMAX_MVT_i32_ri_Predicate_simm8_32b(RetVT, Op0, imm1); |
15346 | 0 | default: return 0; |
15347 | 0 | } |
15348 | 0 | } |
15349 | | |
15350 | | // FastEmit functions for ISD::SMIN. |
15351 | | |
15352 | 0 | unsigned fastEmit_ISD_SMIN_MVT_i32_ri_Predicate_simm8_32b(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15353 | 0 | if (RetVT.SimpleTy != MVT::i32) |
15354 | 0 | return 0; |
15355 | 0 | if ((Subtarget->hasCSSC())) { |
15356 | 0 | return fastEmitInst_ri(AArch64::SMINWri, &AArch64::GPR32RegClass, Op0, imm1); |
15357 | 0 | } |
15358 | 0 | return 0; |
15359 | 0 | } |
15360 | | |
15361 | 0 | unsigned fastEmit_ISD_SMIN_ri_Predicate_simm8_32b(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
15362 | 0 | switch (VT.SimpleTy) { |
15363 | 0 | case MVT::i32: return fastEmit_ISD_SMIN_MVT_i32_ri_Predicate_simm8_32b(RetVT, Op0, imm1); |
15364 | 0 | default: return 0; |
15365 | 0 | } |
15366 | 0 | } |
15367 | | |
15368 | | // Top-level FastEmit function. |
15369 | | |
15370 | 0 | unsigned fastEmit_ri_Predicate_simm8_32b(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) { |
15371 | 0 | switch (Opcode) { |
15372 | 0 | case ISD::SMAX: return fastEmit_ISD_SMAX_ri_Predicate_simm8_32b(VT, RetVT, Op0, imm1); |
15373 | 0 | case ISD::SMIN: return fastEmit_ISD_SMIN_ri_Predicate_simm8_32b(VT, RetVT, Op0, imm1); |
15374 | 0 | default: return 0; |
15375 | 0 | } |
15376 | 0 | } |
15377 | | |
15378 | | // FastEmit functions for ISD::SMAX. |
15379 | | |
15380 | 0 | unsigned fastEmit_ISD_SMAX_MVT_i64_ri_Predicate_simm8_64b(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15381 | 0 | if (RetVT.SimpleTy != MVT::i64) |
15382 | 0 | return 0; |
15383 | 0 | if ((Subtarget->hasCSSC())) { |
15384 | 0 | return fastEmitInst_ri(AArch64::SMAXXri, &AArch64::GPR64RegClass, Op0, imm1); |
15385 | 0 | } |
15386 | 0 | return 0; |
15387 | 0 | } |
15388 | | |
15389 | 0 | unsigned fastEmit_ISD_SMAX_ri_Predicate_simm8_64b(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
15390 | 0 | switch (VT.SimpleTy) { |
15391 | 0 | case MVT::i64: return fastEmit_ISD_SMAX_MVT_i64_ri_Predicate_simm8_64b(RetVT, Op0, imm1); |
15392 | 0 | default: return 0; |
15393 | 0 | } |
15394 | 0 | } |
15395 | | |
15396 | | // FastEmit functions for ISD::SMIN. |
15397 | | |
15398 | 0 | unsigned fastEmit_ISD_SMIN_MVT_i64_ri_Predicate_simm8_64b(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15399 | 0 | if (RetVT.SimpleTy != MVT::i64) |
15400 | 0 | return 0; |
15401 | 0 | if ((Subtarget->hasCSSC())) { |
15402 | 0 | return fastEmitInst_ri(AArch64::SMINXri, &AArch64::GPR64RegClass, Op0, imm1); |
15403 | 0 | } |
15404 | 0 | return 0; |
15405 | 0 | } |
15406 | | |
15407 | 0 | unsigned fastEmit_ISD_SMIN_ri_Predicate_simm8_64b(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
15408 | 0 | switch (VT.SimpleTy) { |
15409 | 0 | case MVT::i64: return fastEmit_ISD_SMIN_MVT_i64_ri_Predicate_simm8_64b(RetVT, Op0, imm1); |
15410 | 0 | default: return 0; |
15411 | 0 | } |
15412 | 0 | } |
15413 | | |
15414 | | // Top-level FastEmit function. |
15415 | | |
15416 | 0 | unsigned fastEmit_ri_Predicate_simm8_64b(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) { |
15417 | 0 | switch (Opcode) { |
15418 | 0 | case ISD::SMAX: return fastEmit_ISD_SMAX_ri_Predicate_simm8_64b(VT, RetVT, Op0, imm1); |
15419 | 0 | case ISD::SMIN: return fastEmit_ISD_SMIN_ri_Predicate_simm8_64b(VT, RetVT, Op0, imm1); |
15420 | 0 | default: return 0; |
15421 | 0 | } |
15422 | 0 | } |
15423 | | |
15424 | | // FastEmit functions for ISD::UMAX. |
15425 | | |
15426 | 0 | unsigned fastEmit_ISD_UMAX_MVT_i32_ri_Predicate_uimm8_32b(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15427 | 0 | if (RetVT.SimpleTy != MVT::i32) |
15428 | 0 | return 0; |
15429 | 0 | if ((Subtarget->hasCSSC())) { |
15430 | 0 | return fastEmitInst_ri(AArch64::UMAXWri, &AArch64::GPR32RegClass, Op0, imm1); |
15431 | 0 | } |
15432 | 0 | return 0; |
15433 | 0 | } |
15434 | | |
15435 | 0 | unsigned fastEmit_ISD_UMAX_ri_Predicate_uimm8_32b(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
15436 | 0 | switch (VT.SimpleTy) { |
15437 | 0 | case MVT::i32: return fastEmit_ISD_UMAX_MVT_i32_ri_Predicate_uimm8_32b(RetVT, Op0, imm1); |
15438 | 0 | default: return 0; |
15439 | 0 | } |
15440 | 0 | } |
15441 | | |
15442 | | // FastEmit functions for ISD::UMIN. |
15443 | | |
15444 | 0 | unsigned fastEmit_ISD_UMIN_MVT_i32_ri_Predicate_uimm8_32b(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15445 | 0 | if (RetVT.SimpleTy != MVT::i32) |
15446 | 0 | return 0; |
15447 | 0 | if ((Subtarget->hasCSSC())) { |
15448 | 0 | return fastEmitInst_ri(AArch64::UMINWri, &AArch64::GPR32RegClass, Op0, imm1); |
15449 | 0 | } |
15450 | 0 | return 0; |
15451 | 0 | } |
15452 | | |
15453 | 0 | unsigned fastEmit_ISD_UMIN_ri_Predicate_uimm8_32b(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
15454 | 0 | switch (VT.SimpleTy) { |
15455 | 0 | case MVT::i32: return fastEmit_ISD_UMIN_MVT_i32_ri_Predicate_uimm8_32b(RetVT, Op0, imm1); |
15456 | 0 | default: return 0; |
15457 | 0 | } |
15458 | 0 | } |
15459 | | |
15460 | | // Top-level FastEmit function. |
15461 | | |
15462 | 0 | unsigned fastEmit_ri_Predicate_uimm8_32b(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) { |
15463 | 0 | switch (Opcode) { |
15464 | 0 | case ISD::UMAX: return fastEmit_ISD_UMAX_ri_Predicate_uimm8_32b(VT, RetVT, Op0, imm1); |
15465 | 0 | case ISD::UMIN: return fastEmit_ISD_UMIN_ri_Predicate_uimm8_32b(VT, RetVT, Op0, imm1); |
15466 | 0 | default: return 0; |
15467 | 0 | } |
15468 | 0 | } |
15469 | | |
15470 | | // FastEmit functions for ISD::UMAX. |
15471 | | |
15472 | 0 | unsigned fastEmit_ISD_UMAX_MVT_i64_ri_Predicate_uimm8_64b(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15473 | 0 | if (RetVT.SimpleTy != MVT::i64) |
15474 | 0 | return 0; |
15475 | 0 | if ((Subtarget->hasCSSC())) { |
15476 | 0 | return fastEmitInst_ri(AArch64::UMAXXri, &AArch64::GPR64RegClass, Op0, imm1); |
15477 | 0 | } |
15478 | 0 | return 0; |
15479 | 0 | } |
15480 | | |
15481 | 0 | unsigned fastEmit_ISD_UMAX_ri_Predicate_uimm8_64b(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
15482 | 0 | switch (VT.SimpleTy) { |
15483 | 0 | case MVT::i64: return fastEmit_ISD_UMAX_MVT_i64_ri_Predicate_uimm8_64b(RetVT, Op0, imm1); |
15484 | 0 | default: return 0; |
15485 | 0 | } |
15486 | 0 | } |
15487 | | |
15488 | | // FastEmit functions for ISD::UMIN. |
15489 | | |
15490 | 0 | unsigned fastEmit_ISD_UMIN_MVT_i64_ri_Predicate_uimm8_64b(MVT RetVT, unsigned Op0, uint64_t imm1) { |
15491 | 0 | if (RetVT.SimpleTy != MVT::i64) |
15492 | 0 | return 0; |
15493 | 0 | if ((Subtarget->hasCSSC())) { |
15494 | 0 | return fastEmitInst_ri(AArch64::UMINXri, &AArch64::GPR64RegClass, Op0, imm1); |
15495 | 0 | } |
15496 | 0 | return 0; |
15497 | 0 | } |
15498 | | |
15499 | 0 | unsigned fastEmit_ISD_UMIN_ri_Predicate_uimm8_64b(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
15500 | 0 | switch (VT.SimpleTy) { |
15501 | 0 | case MVT::i64: return fastEmit_ISD_UMIN_MVT_i64_ri_Predicate_uimm8_64b(RetVT, Op0, imm1); |
15502 | 0 | default: return 0; |
15503 | 0 | } |
15504 | 0 | } |
15505 | | |
15506 | | // Top-level FastEmit function. |
15507 | | |
15508 | 0 | unsigned fastEmit_ri_Predicate_uimm8_64b(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) { |
15509 | 0 | switch (Opcode) { |
15510 | 0 | case ISD::UMAX: return fastEmit_ISD_UMAX_ri_Predicate_uimm8_64b(VT, RetVT, Op0, imm1); |
15511 | 0 | case ISD::UMIN: return fastEmit_ISD_UMIN_ri_Predicate_uimm8_64b(VT, RetVT, Op0, imm1); |
15512 | 0 | default: return 0; |
15513 | 0 | } |
15514 | 0 | } |
15515 | | |
15516 | | // FastEmit functions for AArch64ISD::MRS. |
15517 | | |
15518 | 0 | unsigned fastEmit_AArch64ISD_MRS_MVT_i32_i(MVT RetVT, uint64_t imm0) { |
15519 | 0 | if (RetVT.SimpleTy != MVT::i64) |
15520 | 0 | return 0; |
15521 | 0 | return fastEmitInst_i(AArch64::MRS, &AArch64::GPR64RegClass, imm0); |
15522 | 0 | } |
15523 | | |
15524 | 0 | unsigned fastEmit_AArch64ISD_MRS_i(MVT VT, MVT RetVT, uint64_t imm0) { |
15525 | 0 | switch (VT.SimpleTy) { |
15526 | 0 | case MVT::i32: return fastEmit_AArch64ISD_MRS_MVT_i32_i(RetVT, imm0); |
15527 | 0 | default: return 0; |
15528 | 0 | } |
15529 | 0 | } |
15530 | | |
15531 | | // FastEmit functions for ISD::Constant. |
15532 | | |
15533 | 0 | unsigned fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) { |
15534 | 0 | if (RetVT.SimpleTy != MVT::i32) |
15535 | 0 | return 0; |
15536 | 0 | return fastEmitInst_i(AArch64::MOVi32imm, &AArch64::GPR32RegClass, imm0); |
15537 | 0 | } |
15538 | | |
15539 | 0 | unsigned fastEmit_ISD_Constant_MVT_i64_i(MVT RetVT, uint64_t imm0) { |
15540 | 0 | if (RetVT.SimpleTy != MVT::i64) |
15541 | 0 | return 0; |
15542 | 0 | return fastEmitInst_i(AArch64::MOVi64imm, &AArch64::GPR64RegClass, imm0); |
15543 | 0 | } |
15544 | | |
15545 | 0 | unsigned fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) { |
15546 | 0 | switch (VT.SimpleTy) { |
15547 | 0 | case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0); |
15548 | 0 | case MVT::i64: return fastEmit_ISD_Constant_MVT_i64_i(RetVT, imm0); |
15549 | 0 | default: return 0; |
15550 | 0 | } |
15551 | 0 | } |
15552 | | |
15553 | | // Top-level FastEmit function. |
15554 | | |
15555 | 0 | unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override { |
15556 | 0 | if (VT == MVT::i32 && Predicate_imm0_255(imm0)) |
15557 | 0 | if (unsigned Reg = fastEmit_i_Predicate_imm0_255(VT, RetVT, Opcode, imm0)) |
15558 | 0 | return Reg; |
15559 | | |
15560 | 0 | if (VT == MVT::i32 && Predicate_simm6_32b(imm0)) |
15561 | 0 | if (unsigned Reg = fastEmit_i_Predicate_simm6_32b(VT, RetVT, Opcode, imm0)) |
15562 | 0 | return Reg; |
15563 | | |
15564 | 0 | switch (Opcode) { |
15565 | 0 | case AArch64ISD::MRS: return fastEmit_AArch64ISD_MRS_i(VT, RetVT, imm0); |
15566 | 0 | case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0); |
15567 | 0 | default: return 0; |
15568 | 0 | } |
15569 | 0 | } |
15570 | | |
15571 | | // FastEmit functions for AArch64ISD::FMOV. |
15572 | | |
15573 | 0 | unsigned fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v4f16_i_Predicate_imm0_255(uint64_t imm0) { |
15574 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
15575 | 0 | return fastEmitInst_i(AArch64::FMOVv4f16_ns, &AArch64::FPR64RegClass, imm0); |
15576 | 0 | } |
15577 | 0 | return 0; |
15578 | 0 | } |
15579 | | |
15580 | 0 | unsigned fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v8f16_i_Predicate_imm0_255(uint64_t imm0) { |
15581 | 0 | if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { |
15582 | 0 | return fastEmitInst_i(AArch64::FMOVv8f16_ns, &AArch64::FPR128RegClass, imm0); |
15583 | 0 | } |
15584 | 0 | return 0; |
15585 | 0 | } |
15586 | | |
15587 | 0 | unsigned fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v2f32_i_Predicate_imm0_255(uint64_t imm0) { |
15588 | 0 | if ((Subtarget->hasNEON())) { |
15589 | 0 | return fastEmitInst_i(AArch64::FMOVv2f32_ns, &AArch64::FPR64RegClass, imm0); |
15590 | 0 | } |
15591 | 0 | return 0; |
15592 | 0 | } |
15593 | | |
15594 | 0 | unsigned fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v4f32_i_Predicate_imm0_255(uint64_t imm0) { |
15595 | 0 | if ((Subtarget->hasNEON())) { |
15596 | 0 | return fastEmitInst_i(AArch64::FMOVv4f32_ns, &AArch64::FPR128RegClass, imm0); |
15597 | 0 | } |
15598 | 0 | return 0; |
15599 | 0 | } |
15600 | | |
15601 | 0 | unsigned fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v2f64_i_Predicate_imm0_255(uint64_t imm0) { |
15602 | 0 | if ((Subtarget->hasNEON())) { |
15603 | 0 | return fastEmitInst_i(AArch64::FMOVv2f64_ns, &AArch64::FPR128RegClass, imm0); |
15604 | 0 | } |
15605 | 0 | return 0; |
15606 | 0 | } |
15607 | | |
15608 | 0 | unsigned fastEmit_AArch64ISD_FMOV_MVT_i32_i_Predicate_imm0_255(MVT RetVT, uint64_t imm0) { |
15609 | 0 | switch (RetVT.SimpleTy) { |
15610 | 0 | case MVT::v4f16: return fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v4f16_i_Predicate_imm0_255(imm0); |
15611 | 0 | case MVT::v8f16: return fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v8f16_i_Predicate_imm0_255(imm0); |
15612 | 0 | case MVT::v2f32: return fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v2f32_i_Predicate_imm0_255(imm0); |
15613 | 0 | case MVT::v4f32: return fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v4f32_i_Predicate_imm0_255(imm0); |
15614 | 0 | case MVT::v2f64: return fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v2f64_i_Predicate_imm0_255(imm0); |
15615 | 0 | default: return 0; |
15616 | 0 | } |
15617 | 0 | } |
15618 | | |
15619 | 0 | unsigned fastEmit_AArch64ISD_FMOV_i_Predicate_imm0_255(MVT VT, MVT RetVT, uint64_t imm0) { |
15620 | 0 | switch (VT.SimpleTy) { |
15621 | 0 | case MVT::i32: return fastEmit_AArch64ISD_FMOV_MVT_i32_i_Predicate_imm0_255(RetVT, imm0); |
15622 | 0 | default: return 0; |
15623 | 0 | } |
15624 | 0 | } |
15625 | | |
15626 | | // FastEmit functions for AArch64ISD::MOVI. |
15627 | | |
15628 | 0 | unsigned fastEmit_AArch64ISD_MOVI_MVT_i32_MVT_v8i8_i_Predicate_imm0_255(uint64_t imm0) { |
15629 | 0 | if ((Subtarget->hasNEON())) { |
15630 | 0 | return fastEmitInst_i(AArch64::MOVIv8b_ns, &AArch64::FPR64RegClass, imm0); |
15631 | 0 | } |
15632 | 0 | return 0; |
15633 | 0 | } |
15634 | | |
15635 | 0 | unsigned fastEmit_AArch64ISD_MOVI_MVT_i32_MVT_v16i8_i_Predicate_imm0_255(uint64_t imm0) { |
15636 | 0 | if ((Subtarget->hasNEON())) { |
15637 | 0 | return fastEmitInst_i(AArch64::MOVIv16b_ns, &AArch64::FPR128RegClass, imm0); |
15638 | 0 | } |
15639 | 0 | return 0; |
15640 | 0 | } |
15641 | | |
15642 | 0 | unsigned fastEmit_AArch64ISD_MOVI_MVT_i32_i_Predicate_imm0_255(MVT RetVT, uint64_t imm0) { |
15643 | 0 | switch (RetVT.SimpleTy) { |
15644 | 0 | case MVT::v8i8: return fastEmit_AArch64ISD_MOVI_MVT_i32_MVT_v8i8_i_Predicate_imm0_255(imm0); |
15645 | 0 | case MVT::v16i8: return fastEmit_AArch64ISD_MOVI_MVT_i32_MVT_v16i8_i_Predicate_imm0_255(imm0); |
15646 | 0 | default: return 0; |
15647 | 0 | } |
15648 | 0 | } |
15649 | | |
15650 | 0 | unsigned fastEmit_AArch64ISD_MOVI_i_Predicate_imm0_255(MVT VT, MVT RetVT, uint64_t imm0) { |
15651 | 0 | switch (VT.SimpleTy) { |
15652 | 0 | case MVT::i32: return fastEmit_AArch64ISD_MOVI_MVT_i32_i_Predicate_imm0_255(RetVT, imm0); |
15653 | 0 | default: return 0; |
15654 | 0 | } |
15655 | 0 | } |
15656 | | |
15657 | | // FastEmit functions for AArch64ISD::MOVIedit. |
15658 | | |
15659 | 0 | unsigned fastEmit_AArch64ISD_MOVIedit_MVT_i32_MVT_f64_i_Predicate_imm0_255(uint64_t imm0) { |
15660 | 0 | return fastEmitInst_i(AArch64::MOVID, &AArch64::FPR64RegClass, imm0); |
15661 | 0 | } |
15662 | | |
15663 | 0 | unsigned fastEmit_AArch64ISD_MOVIedit_MVT_i32_MVT_v2i64_i_Predicate_imm0_255(uint64_t imm0) { |
15664 | 0 | if ((Subtarget->hasNEON())) { |
15665 | 0 | return fastEmitInst_i(AArch64::MOVIv2d_ns, &AArch64::FPR128RegClass, imm0); |
15666 | 0 | } |
15667 | 0 | return 0; |
15668 | 0 | } |
15669 | | |
15670 | 0 | unsigned fastEmit_AArch64ISD_MOVIedit_MVT_i32_i_Predicate_imm0_255(MVT RetVT, uint64_t imm0) { |
15671 | 0 | switch (RetVT.SimpleTy) { |
15672 | 0 | case MVT::f64: return fastEmit_AArch64ISD_MOVIedit_MVT_i32_MVT_f64_i_Predicate_imm0_255(imm0); |
15673 | 0 | case MVT::v2i64: return fastEmit_AArch64ISD_MOVIedit_MVT_i32_MVT_v2i64_i_Predicate_imm0_255(imm0); |
15674 | 0 | default: return 0; |
15675 | 0 | } |
15676 | 0 | } |
15677 | | |
15678 | 0 | unsigned fastEmit_AArch64ISD_MOVIedit_i_Predicate_imm0_255(MVT VT, MVT RetVT, uint64_t imm0) { |
15679 | 0 | switch (VT.SimpleTy) { |
15680 | 0 | case MVT::i32: return fastEmit_AArch64ISD_MOVIedit_MVT_i32_i_Predicate_imm0_255(RetVT, imm0); |
15681 | 0 | default: return 0; |
15682 | 0 | } |
15683 | 0 | } |
15684 | | |
15685 | | // Top-level FastEmit function. |
15686 | | |
15687 | 0 | unsigned fastEmit_i_Predicate_imm0_255(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) { |
15688 | 0 | switch (Opcode) { |
15689 | 0 | case AArch64ISD::FMOV: return fastEmit_AArch64ISD_FMOV_i_Predicate_imm0_255(VT, RetVT, imm0); |
15690 | 0 | case AArch64ISD::MOVI: return fastEmit_AArch64ISD_MOVI_i_Predicate_imm0_255(VT, RetVT, imm0); |
15691 | 0 | case AArch64ISD::MOVIedit: return fastEmit_AArch64ISD_MOVIedit_i_Predicate_imm0_255(VT, RetVT, imm0); |
15692 | 0 | default: return 0; |
15693 | 0 | } |
15694 | 0 | } |
15695 | | |
15696 | | // FastEmit functions for AArch64ISD::RDSVL. |
15697 | | |
15698 | 0 | unsigned fastEmit_AArch64ISD_RDSVL_MVT_i32_i_Predicate_simm6_32b(MVT RetVT, uint64_t imm0) { |
15699 | 0 | if (RetVT.SimpleTy != MVT::i64) |
15700 | 0 | return 0; |
15701 | 0 | if ((Subtarget->hasSME())) { |
15702 | 0 | return fastEmitInst_i(AArch64::RDSVLI_XI, &AArch64::GPR64RegClass, imm0); |
15703 | 0 | } |
15704 | 0 | return 0; |
15705 | 0 | } |
15706 | | |
15707 | 0 | unsigned fastEmit_AArch64ISD_RDSVL_i_Predicate_simm6_32b(MVT VT, MVT RetVT, uint64_t imm0) { |
15708 | 0 | switch (VT.SimpleTy) { |
15709 | 0 | case MVT::i32: return fastEmit_AArch64ISD_RDSVL_MVT_i32_i_Predicate_simm6_32b(RetVT, imm0); |
15710 | 0 | default: return 0; |
15711 | 0 | } |
15712 | 0 | } |
15713 | | |
15714 | | // Top-level FastEmit function. |
15715 | | |
15716 | 0 | unsigned fastEmit_i_Predicate_simm6_32b(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) { |
15717 | 0 | switch (Opcode) { |
15718 | 0 | case AArch64ISD::RDSVL: return fastEmit_AArch64ISD_RDSVL_i_Predicate_simm6_32b(VT, RetVT, imm0); |
15719 | 0 | default: return 0; |
15720 | 0 | } |
15721 | 0 | } |
15722 | | |