Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Machine Code Emitter                                                       *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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uint64_t AArch64MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
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    SmallVectorImpl<MCFixup> &Fixups,
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0
    const MCSubtargetInfo &STI) const {
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0
  static const uint64_t InstBits[] = {
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1011
0
    UINT64_C(0),
1012
0
    UINT64_C(0),
1013
0
    UINT64_C(0),
1014
0
    UINT64_C(0),
1015
0
    UINT64_C(0),
1016
0
    UINT64_C(0),
1017
0
    UINT64_C(0),
1018
0
    UINT64_C(0),
1019
0
    UINT64_C(0),
1020
0
    UINT64_C(0),
1021
0
    UINT64_C(0),
1022
0
    UINT64_C(0),
1023
0
    UINT64_C(0),
1024
0
    UINT64_C(0),
1025
0
    UINT64_C(0),
1026
0
    UINT64_C(0),
1027
0
    UINT64_C(0),
1028
0
    UINT64_C(0),
1029
0
    UINT64_C(0),
1030
0
    UINT64_C(0),
1031
0
    UINT64_C(0),
1032
0
    UINT64_C(0),
1033
0
    UINT64_C(0),
1034
0
    UINT64_C(0),
1035
0
    UINT64_C(0),
1036
0
    UINT64_C(0),
1037
0
    UINT64_C(0),
1038
0
    UINT64_C(0),
1039
0
    UINT64_C(0),
1040
0
    UINT64_C(0),
1041
0
    UINT64_C(0),
1042
0
    UINT64_C(0),
1043
0
    UINT64_C(0),
1044
0
    UINT64_C(0),
1045
0
    UINT64_C(0),
1046
0
    UINT64_C(0),
1047
0
    UINT64_C(0),
1048
0
    UINT64_C(0),
1049
0
    UINT64_C(0),
1050
0
    UINT64_C(0),
1051
0
    UINT64_C(0),
1052
0
    UINT64_C(0),
1053
0
    UINT64_C(0),
1054
0
    UINT64_C(0),
1055
0
    UINT64_C(0),
1056
0
    UINT64_C(0),
1057
0
    UINT64_C(0),
1058
0
    UINT64_C(0),
1059
0
    UINT64_C(0),
1060
0
    UINT64_C(0),
1061
0
    UINT64_C(0),
1062
0
    UINT64_C(0),
1063
0
    UINT64_C(0),
1064
0
    UINT64_C(0),
1065
0
    UINT64_C(0),
1066
0
    UINT64_C(0),
1067
0
    UINT64_C(0),
1068
0
    UINT64_C(0),
1069
0
    UINT64_C(0),
1070
0
    UINT64_C(0),
1071
0
    UINT64_C(0),
1072
0
    UINT64_C(0),
1073
0
    UINT64_C(0),
1074
0
    UINT64_C(0),
1075
0
    UINT64_C(0),
1076
0
    UINT64_C(0),
1077
0
    UINT64_C(0),
1078
0
    UINT64_C(0),
1079
0
    UINT64_C(0),
1080
0
    UINT64_C(0),
1081
0
    UINT64_C(0),
1082
0
    UINT64_C(0),
1083
0
    UINT64_C(0),
1084
0
    UINT64_C(0),
1085
0
    UINT64_C(0),
1086
0
    UINT64_C(0),
1087
0
    UINT64_C(0),
1088
0
    UINT64_C(0),
1089
0
    UINT64_C(0),
1090
0
    UINT64_C(0),
1091
0
    UINT64_C(0),
1092
0
    UINT64_C(0),
1093
0
    UINT64_C(0),
1094
0
    UINT64_C(0),
1095
0
    UINT64_C(0),
1096
0
    UINT64_C(0),
1097
0
    UINT64_C(0),
1098
0
    UINT64_C(0),
1099
0
    UINT64_C(0),
1100
0
    UINT64_C(0),
1101
0
    UINT64_C(0),
1102
0
    UINT64_C(0),
1103
0
    UINT64_C(0),
1104
0
    UINT64_C(0),
1105
0
    UINT64_C(0),
1106
0
    UINT64_C(0),
1107
0
    UINT64_C(0),
1108
0
    UINT64_C(0),
1109
0
    UINT64_C(0),
1110
0
    UINT64_C(0),
1111
0
    UINT64_C(0),
1112
0
    UINT64_C(0),
1113
0
    UINT64_C(0),
1114
0
    UINT64_C(0),
1115
0
    UINT64_C(0),
1116
0
    UINT64_C(0),
1117
0
    UINT64_C(0),
1118
0
    UINT64_C(0),
1119
0
    UINT64_C(0),
1120
0
    UINT64_C(0),
1121
0
    UINT64_C(0),
1122
0
    UINT64_C(0),
1123
0
    UINT64_C(0),
1124
0
    UINT64_C(0),
1125
0
    UINT64_C(0),
1126
0
    UINT64_C(0),
1127
0
    UINT64_C(0),
1128
0
    UINT64_C(0),
1129
0
    UINT64_C(0),
1130
0
    UINT64_C(0),
1131
0
    UINT64_C(0),
1132
0
    UINT64_C(0),
1133
0
    UINT64_C(0),
1134
0
    UINT64_C(0),
1135
0
    UINT64_C(0),
1136
0
    UINT64_C(0),
1137
0
    UINT64_C(0),
1138
0
    UINT64_C(0),
1139
0
    UINT64_C(0),
1140
0
    UINT64_C(0),
1141
0
    UINT64_C(0),
1142
0
    UINT64_C(0),
1143
0
    UINT64_C(0),
1144
0
    UINT64_C(0),
1145
0
    UINT64_C(0),
1146
0
    UINT64_C(0),
1147
0
    UINT64_C(0),
1148
0
    UINT64_C(0),
1149
0
    UINT64_C(0),
1150
0
    UINT64_C(0),
1151
0
    UINT64_C(0),
1152
0
    UINT64_C(0),
1153
0
    UINT64_C(0),
1154
0
    UINT64_C(0),
1155
0
    UINT64_C(0),
1156
0
    UINT64_C(0),
1157
0
    UINT64_C(0),
1158
0
    UINT64_C(0),
1159
0
    UINT64_C(0),
1160
0
    UINT64_C(0),
1161
0
    UINT64_C(0),
1162
0
    UINT64_C(0),
1163
0
    UINT64_C(0),
1164
0
    UINT64_C(0),
1165
0
    UINT64_C(0),
1166
0
    UINT64_C(0),
1167
0
    UINT64_C(0),
1168
0
    UINT64_C(0),
1169
0
    UINT64_C(0),
1170
0
    UINT64_C(0),
1171
0
    UINT64_C(0),
1172
0
    UINT64_C(0),
1173
0
    UINT64_C(0),
1174
0
    UINT64_C(0),
1175
0
    UINT64_C(0),
1176
0
    UINT64_C(0),
1177
0
    UINT64_C(0),
1178
0
    UINT64_C(0),
1179
0
    UINT64_C(0),
1180
0
    UINT64_C(0),
1181
0
    UINT64_C(0),
1182
0
    UINT64_C(0),
1183
0
    UINT64_C(0),
1184
0
    UINT64_C(0),
1185
0
    UINT64_C(0),
1186
0
    UINT64_C(0),
1187
0
    UINT64_C(0),
1188
0
    UINT64_C(0),
1189
0
    UINT64_C(0),
1190
0
    UINT64_C(0),
1191
0
    UINT64_C(0),
1192
0
    UINT64_C(0),
1193
0
    UINT64_C(0),
1194
0
    UINT64_C(0),
1195
0
    UINT64_C(0),
1196
0
    UINT64_C(0),
1197
0
    UINT64_C(0),
1198
0
    UINT64_C(0),
1199
0
    UINT64_C(0),
1200
0
    UINT64_C(0),
1201
0
    UINT64_C(0),
1202
0
    UINT64_C(0),
1203
0
    UINT64_C(0),
1204
0
    UINT64_C(0),
1205
0
    UINT64_C(0),
1206
0
    UINT64_C(0),
1207
0
    UINT64_C(0),
1208
0
    UINT64_C(0),
1209
0
    UINT64_C(0),
1210
0
    UINT64_C(0),
1211
0
    UINT64_C(0),
1212
0
    UINT64_C(0),
1213
0
    UINT64_C(0),
1214
0
    UINT64_C(0),
1215
0
    UINT64_C(0),
1216
0
    UINT64_C(0),
1217
0
    UINT64_C(0),
1218
0
    UINT64_C(0),
1219
0
    UINT64_C(0),
1220
0
    UINT64_C(0),
1221
0
    UINT64_C(0),
1222
0
    UINT64_C(0),
1223
0
    UINT64_C(0),
1224
0
    UINT64_C(0),
1225
0
    UINT64_C(0),
1226
0
    UINT64_C(0),
1227
0
    UINT64_C(0),
1228
0
    UINT64_C(0),
1229
0
    UINT64_C(0),
1230
0
    UINT64_C(0),
1231
0
    UINT64_C(0),
1232
0
    UINT64_C(0),
1233
0
    UINT64_C(0),
1234
0
    UINT64_C(0),
1235
0
    UINT64_C(0),
1236
0
    UINT64_C(0),
1237
0
    UINT64_C(0),
1238
0
    UINT64_C(0),
1239
0
    UINT64_C(0),
1240
0
    UINT64_C(0),
1241
0
    UINT64_C(0),
1242
0
    UINT64_C(0),
1243
0
    UINT64_C(0),
1244
0
    UINT64_C(0),
1245
0
    UINT64_C(0),
1246
0
    UINT64_C(0),
1247
0
    UINT64_C(0),
1248
0
    UINT64_C(0),
1249
0
    UINT64_C(0),
1250
0
    UINT64_C(0),
1251
0
    UINT64_C(0),
1252
0
    UINT64_C(0),
1253
0
    UINT64_C(0),
1254
0
    UINT64_C(0),
1255
0
    UINT64_C(0),
1256
0
    UINT64_C(0),
1257
0
    UINT64_C(0),
1258
0
    UINT64_C(0),
1259
0
    UINT64_C(0),
1260
0
    UINT64_C(0),
1261
0
    UINT64_C(0),
1262
0
    UINT64_C(0),
1263
0
    UINT64_C(0),
1264
0
    UINT64_C(0),
1265
0
    UINT64_C(0),
1266
0
    UINT64_C(0),
1267
0
    UINT64_C(0),
1268
0
    UINT64_C(0),
1269
0
    UINT64_C(0),
1270
0
    UINT64_C(0),
1271
0
    UINT64_C(0),
1272
0
    UINT64_C(0),
1273
0
    UINT64_C(0),
1274
0
    UINT64_C(0),
1275
0
    UINT64_C(0),
1276
0
    UINT64_C(0),
1277
0
    UINT64_C(0),
1278
0
    UINT64_C(0),
1279
0
    UINT64_C(0),
1280
0
    UINT64_C(0),
1281
0
    UINT64_C(0),
1282
0
    UINT64_C(0),
1283
0
    UINT64_C(0),
1284
0
    UINT64_C(0),
1285
0
    UINT64_C(0),
1286
0
    UINT64_C(0),
1287
0
    UINT64_C(0),
1288
0
    UINT64_C(0),
1289
0
    UINT64_C(0),
1290
0
    UINT64_C(0),
1291
0
    UINT64_C(0),
1292
0
    UINT64_C(0),
1293
0
    UINT64_C(0),
1294
0
    UINT64_C(0),
1295
0
    UINT64_C(0),
1296
0
    UINT64_C(0),
1297
0
    UINT64_C(0),
1298
0
    UINT64_C(0),
1299
0
    UINT64_C(0),
1300
0
    UINT64_C(0),
1301
0
    UINT64_C(0),
1302
0
    UINT64_C(0),
1303
0
    UINT64_C(0),
1304
0
    UINT64_C(0),
1305
0
    UINT64_C(0),
1306
0
    UINT64_C(0),
1307
0
    UINT64_C(0),
1308
0
    UINT64_C(0),
1309
0
    UINT64_C(0),
1310
0
    UINT64_C(0),
1311
0
    UINT64_C(0),
1312
0
    UINT64_C(0),
1313
0
    UINT64_C(0),
1314
0
    UINT64_C(0),
1315
0
    UINT64_C(0),
1316
0
    UINT64_C(0),
1317
0
    UINT64_C(0),
1318
0
    UINT64_C(0),
1319
0
    UINT64_C(0),
1320
0
    UINT64_C(0),
1321
0
    UINT64_C(0),
1322
0
    UINT64_C(0),
1323
0
    UINT64_C(0),
1324
0
    UINT64_C(0),
1325
0
    UINT64_C(0),
1326
0
    UINT64_C(0),
1327
0
    UINT64_C(0),
1328
0
    UINT64_C(0),
1329
0
    UINT64_C(0),
1330
0
    UINT64_C(0),
1331
0
    UINT64_C(0),
1332
0
    UINT64_C(0),
1333
0
    UINT64_C(0),
1334
0
    UINT64_C(0),
1335
0
    UINT64_C(0),
1336
0
    UINT64_C(0),
1337
0
    UINT64_C(0),
1338
0
    UINT64_C(0),
1339
0
    UINT64_C(0),
1340
0
    UINT64_C(0),
1341
0
    UINT64_C(0),
1342
0
    UINT64_C(0),
1343
0
    UINT64_C(0),
1344
0
    UINT64_C(0),
1345
0
    UINT64_C(0),
1346
0
    UINT64_C(0),
1347
0
    UINT64_C(0),
1348
0
    UINT64_C(0),
1349
0
    UINT64_C(0),
1350
0
    UINT64_C(0),
1351
0
    UINT64_C(0),
1352
0
    UINT64_C(0),
1353
0
    UINT64_C(0),
1354
0
    UINT64_C(0),
1355
0
    UINT64_C(0),
1356
0
    UINT64_C(0),
1357
0
    UINT64_C(0),
1358
0
    UINT64_C(0),
1359
0
    UINT64_C(0),
1360
0
    UINT64_C(0),
1361
0
    UINT64_C(0),
1362
0
    UINT64_C(0),
1363
0
    UINT64_C(0),
1364
0
    UINT64_C(0),
1365
0
    UINT64_C(0),
1366
0
    UINT64_C(0),
1367
0
    UINT64_C(0),
1368
0
    UINT64_C(0),
1369
0
    UINT64_C(0),
1370
0
    UINT64_C(0),
1371
0
    UINT64_C(0),
1372
0
    UINT64_C(0),
1373
0
    UINT64_C(0),
1374
0
    UINT64_C(0),
1375
0
    UINT64_C(0),
1376
0
    UINT64_C(0),
1377
0
    UINT64_C(0),
1378
0
    UINT64_C(0),
1379
0
    UINT64_C(0),
1380
0
    UINT64_C(0),
1381
0
    UINT64_C(0),
1382
0
    UINT64_C(0),
1383
0
    UINT64_C(0),
1384
0
    UINT64_C(0),
1385
0
    UINT64_C(0),
1386
0
    UINT64_C(0),
1387
0
    UINT64_C(0),
1388
0
    UINT64_C(0),
1389
0
    UINT64_C(0),
1390
0
    UINT64_C(0),
1391
0
    UINT64_C(0),
1392
0
    UINT64_C(0),
1393
0
    UINT64_C(0),
1394
0
    UINT64_C(0),
1395
0
    UINT64_C(0),
1396
0
    UINT64_C(0),
1397
0
    UINT64_C(0),
1398
0
    UINT64_C(0),
1399
0
    UINT64_C(0),
1400
0
    UINT64_C(0),
1401
0
    UINT64_C(0),
1402
0
    UINT64_C(0),
1403
0
    UINT64_C(0),
1404
0
    UINT64_C(0),
1405
0
    UINT64_C(0),
1406
0
    UINT64_C(0),
1407
0
    UINT64_C(0),
1408
0
    UINT64_C(0),
1409
0
    UINT64_C(0),
1410
0
    UINT64_C(0),
1411
0
    UINT64_C(0),
1412
0
    UINT64_C(0),
1413
0
    UINT64_C(0),
1414
0
    UINT64_C(0),
1415
0
    UINT64_C(0),
1416
0
    UINT64_C(0),
1417
0
    UINT64_C(0),
1418
0
    UINT64_C(0),
1419
0
    UINT64_C(0),
1420
0
    UINT64_C(0),
1421
0
    UINT64_C(0),
1422
0
    UINT64_C(0),
1423
0
    UINT64_C(0),
1424
0
    UINT64_C(0),
1425
0
    UINT64_C(0),
1426
0
    UINT64_C(0),
1427
0
    UINT64_C(0),
1428
0
    UINT64_C(0),
1429
0
    UINT64_C(0),
1430
0
    UINT64_C(0),
1431
0
    UINT64_C(0),
1432
0
    UINT64_C(0),
1433
0
    UINT64_C(0),
1434
0
    UINT64_C(0),
1435
0
    UINT64_C(0),
1436
0
    UINT64_C(0),
1437
0
    UINT64_C(0),
1438
0
    UINT64_C(0),
1439
0
    UINT64_C(0),
1440
0
    UINT64_C(0),
1441
0
    UINT64_C(0),
1442
0
    UINT64_C(0),
1443
0
    UINT64_C(0),
1444
0
    UINT64_C(0),
1445
0
    UINT64_C(0),
1446
0
    UINT64_C(0),
1447
0
    UINT64_C(0),
1448
0
    UINT64_C(0),
1449
0
    UINT64_C(0),
1450
0
    UINT64_C(0),
1451
0
    UINT64_C(0),
1452
0
    UINT64_C(0),
1453
0
    UINT64_C(1522540544), // ABSWr
1454
0
    UINT64_C(3670024192), // ABSXr
1455
0
    UINT64_C(68591616), // ABS_ZPmZ_B
1456
0
    UINT64_C(81174528), // ABS_ZPmZ_D
1457
0
    UINT64_C(72785920), // ABS_ZPmZ_H
1458
0
    UINT64_C(76980224), // ABS_ZPmZ_S
1459
0
    UINT64_C(1310767104), // ABSv16i8
1460
0
    UINT64_C(1591785472), // ABSv1i64
1461
0
    UINT64_C(245413888),  // ABSv2i32
1462
0
    UINT64_C(1323350016), // ABSv2i64
1463
0
    UINT64_C(241219584),  // ABSv4i16
1464
0
    UINT64_C(1319155712), // ABSv4i32
1465
0
    UINT64_C(1314961408), // ABSv8i16
1466
0
    UINT64_C(237025280),  // ABSv8i8
1467
0
    UINT64_C(1161875456), // ADCLB_ZZZ_D
1468
0
    UINT64_C(1157681152), // ADCLB_ZZZ_S
1469
0
    UINT64_C(1161876480), // ADCLT_ZZZ_D
1470
0
    UINT64_C(1157682176), // ADCLT_ZZZ_S
1471
0
    UINT64_C(973078528),  // ADCSWr
1472
0
    UINT64_C(3120562176), // ADCSXr
1473
0
    UINT64_C(436207616),  // ADCWr
1474
0
    UINT64_C(2583691264), // ADCXr
1475
0
    UINT64_C(2441084928), // ADDG
1476
0
    UINT64_C(3234856960), // ADDHA_MPPZ_D
1477
0
    UINT64_C(3230662656), // ADDHA_MPPZ_S
1478
0
    UINT64_C(1163943936), // ADDHNB_ZZZ_B
1479
0
    UINT64_C(1168138240), // ADDHNB_ZZZ_H
1480
0
    UINT64_C(1172332544), // ADDHNB_ZZZ_S
1481
0
    UINT64_C(1163944960), // ADDHNT_ZZZ_B
1482
0
    UINT64_C(1168139264), // ADDHNT_ZZZ_H
1483
0
    UINT64_C(1172333568), // ADDHNT_ZZZ_S
1484
0
    UINT64_C(245383168),  // ADDHNv2i64_v2i32
1485
0
    UINT64_C(1319124992), // ADDHNv2i64_v4i32
1486
0
    UINT64_C(241188864),  // ADDHNv4i32_v4i16
1487
0
    UINT64_C(1314930688), // ADDHNv4i32_v8i16
1488
0
    UINT64_C(1310736384), // ADDHNv8i16_v16i8
1489
0
    UINT64_C(236994560),  // ADDHNv8i16_v8i8
1490
0
    UINT64_C(73420800), // ADDPL_XXI
1491
0
    UINT64_C(2583699456), // ADDPT_shift
1492
0
    UINT64_C(1142005760), // ADDP_ZPmZ_B
1493
0
    UINT64_C(1154588672), // ADDP_ZPmZ_D
1494
0
    UINT64_C(1146200064), // ADDP_ZPmZ_H
1495
0
    UINT64_C(1150394368), // ADDP_ZPmZ_S
1496
0
    UINT64_C(1310768128), // ADDPv16i8
1497
0
    UINT64_C(245414912),  // ADDPv2i32
1498
0
    UINT64_C(1323351040), // ADDPv2i64
1499
0
    UINT64_C(1592899584), // ADDPv2i64p
1500
0
    UINT64_C(241220608),  // ADDPv4i16
1501
0
    UINT64_C(1319156736), // ADDPv4i32
1502
0
    UINT64_C(1314962432), // ADDPv8i16
1503
0
    UINT64_C(237026304),  // ADDPv8i8
1504
0
    UINT64_C(67444736), // ADDQV_VPZ_B
1505
0
    UINT64_C(80027648), // ADDQV_VPZ_D
1506
0
    UINT64_C(71639040), // ADDQV_VPZ_H
1507
0
    UINT64_C(75833344), // ADDQV_VPZ_S
1508
0
    UINT64_C(73422848), // ADDSPL_XXI
1509
0
    UINT64_C(69228544), // ADDSVL_XXI
1510
0
    UINT64_C(822083584),  // ADDSWri
1511
0
    UINT64_C(721420288),  // ADDSWrs
1512
0
    UINT64_C(723517440),  // ADDSWrx
1513
0
    UINT64_C(2969567232), // ADDSXri
1514
0
    UINT64_C(2868903936), // ADDSXrs
1515
0
    UINT64_C(2871001088), // ADDSXrx
1516
0
    UINT64_C(2871025664), // ADDSXrx64
1517
0
    UINT64_C(3234922496), // ADDVA_MPPZ_D
1518
0
    UINT64_C(3230728192), // ADDVA_MPPZ_S
1519
0
    UINT64_C(69226496), // ADDVL_XXI
1520
0
    UINT64_C(1311881216), // ADDVv16i8v
1521
0
    UINT64_C(242333696),  // ADDVv4i16v
1522
0
    UINT64_C(1320269824), // ADDVv4i32v
1523
0
    UINT64_C(1316075520), // ADDVv8i16v
1524
0
    UINT64_C(238139392),  // ADDVv8i8v
1525
0
    UINT64_C(285212672),  // ADDWri
1526
0
    UINT64_C(184549376),  // ADDWrs
1527
0
    UINT64_C(186646528),  // ADDWrx
1528
0
    UINT64_C(2432696320), // ADDXri
1529
0
    UINT64_C(2332033024), // ADDXrs
1530
0
    UINT64_C(2334130176), // ADDXrx
1531
0
    UINT64_C(2334154752), // ADDXrx64
1532
0
    UINT64_C(3240141568), // ADD_VG2_2ZZ_B
1533
0
    UINT64_C(3252724480), // ADD_VG2_2ZZ_D
1534
0
    UINT64_C(3244335872), // ADD_VG2_2ZZ_H
1535
0
    UINT64_C(3248530176), // ADD_VG2_2ZZ_S
1536
0
    UINT64_C(3252688912), // ADD_VG2_M2Z2Z_D
1537
0
    UINT64_C(3248494608), // ADD_VG2_M2Z2Z_S
1538
0
    UINT64_C(3244300304), // ADD_VG2_M2ZZ_D
1539
0
    UINT64_C(3240106000), // ADD_VG2_M2ZZ_S
1540
0
    UINT64_C(3252689936), // ADD_VG2_M2Z_D
1541
0
    UINT64_C(3248495632), // ADD_VG2_M2Z_S
1542
0
    UINT64_C(3240143616), // ADD_VG4_4ZZ_B
1543
0
    UINT64_C(3252726528), // ADD_VG4_4ZZ_D
1544
0
    UINT64_C(3244337920), // ADD_VG4_4ZZ_H
1545
0
    UINT64_C(3248532224), // ADD_VG4_4ZZ_S
1546
0
    UINT64_C(3252754448), // ADD_VG4_M4Z4Z_D
1547
0
    UINT64_C(3248560144), // ADD_VG4_M4Z4Z_S
1548
0
    UINT64_C(3245348880), // ADD_VG4_M4ZZ_D
1549
0
    UINT64_C(3241154576), // ADD_VG4_M4ZZ_S
1550
0
    UINT64_C(3252755472), // ADD_VG4_M4Z_D
1551
0
    UINT64_C(3248561168), // ADD_VG4_M4Z_S
1552
0
    UINT64_C(622903296),  // ADD_ZI_B
1553
0
    UINT64_C(635486208),  // ADD_ZI_D
1554
0
    UINT64_C(627097600),  // ADD_ZI_H
1555
0
    UINT64_C(631291904),  // ADD_ZI_S
1556
0
    UINT64_C(67108864), // ADD_ZPmZ_B
1557
0
    UINT64_C(79953920), // ADD_ZPmZ_CPA
1558
0
    UINT64_C(79691776), // ADD_ZPmZ_D
1559
0
    UINT64_C(71303168), // ADD_ZPmZ_H
1560
0
    UINT64_C(75497472), // ADD_ZPmZ_S
1561
0
    UINT64_C(69206016), // ADD_ZZZ_B
1562
0
    UINT64_C(81790976), // ADD_ZZZ_CPA
1563
0
    UINT64_C(81788928), // ADD_ZZZ_D
1564
0
    UINT64_C(73400320), // ADD_ZZZ_H
1565
0
    UINT64_C(77594624), // ADD_ZZZ_S
1566
0
    UINT64_C(1310753792), // ADDv16i8
1567
0
    UINT64_C(1591772160), // ADDv1i64
1568
0
    UINT64_C(245400576),  // ADDv2i32
1569
0
    UINT64_C(1323336704), // ADDv2i64
1570
0
    UINT64_C(241206272),  // ADDv4i16
1571
0
    UINT64_C(1319142400), // ADDv4i32
1572
0
    UINT64_C(1314948096), // ADDv8i16
1573
0
    UINT64_C(237011968),  // ADDv8i8
1574
0
    UINT64_C(268435456),  // ADR
1575
0
    UINT64_C(2415919104), // ADRP
1576
0
    UINT64_C(81829888), // ADR_LSL_ZZZ_D_0
1577
0
    UINT64_C(81830912), // ADR_LSL_ZZZ_D_1
1578
0
    UINT64_C(81831936), // ADR_LSL_ZZZ_D_2
1579
0
    UINT64_C(81832960), // ADR_LSL_ZZZ_D_3
1580
0
    UINT64_C(77635584), // ADR_LSL_ZZZ_S_0
1581
0
    UINT64_C(77636608), // ADR_LSL_ZZZ_S_1
1582
0
    UINT64_C(77637632), // ADR_LSL_ZZZ_S_2
1583
0
    UINT64_C(77638656), // ADR_LSL_ZZZ_S_3
1584
0
    UINT64_C(69246976), // ADR_SXTW_ZZZ_D_0
1585
0
    UINT64_C(69248000), // ADR_SXTW_ZZZ_D_1
1586
0
    UINT64_C(69249024), // ADR_SXTW_ZZZ_D_2
1587
0
    UINT64_C(69250048), // ADR_SXTW_ZZZ_D_3
1588
0
    UINT64_C(73441280), // ADR_UXTW_ZZZ_D_0
1589
0
    UINT64_C(73442304), // ADR_UXTW_ZZZ_D_1
1590
0
    UINT64_C(73443328), // ADR_UXTW_ZZZ_D_2
1591
0
    UINT64_C(73444352), // ADR_UXTW_ZZZ_D_3
1592
0
    UINT64_C(1159914496), // AESD_ZZZ_B
1593
0
    UINT64_C(1311266816), // AESDrr
1594
0
    UINT64_C(1159913472), // AESE_ZZZ_B
1595
0
    UINT64_C(1311262720), // AESErr
1596
0
    UINT64_C(1159783424), // AESIMC_ZZ_B
1597
0
    UINT64_C(1311275008), // AESIMCrr
1598
0
    UINT64_C(1159782400), // AESMC_ZZ_B
1599
0
    UINT64_C(1311270912), // AESMCrr
1600
0
    UINT64_C(69083136), // ANDQV_VPZ_B
1601
0
    UINT64_C(81666048), // ANDQV_VPZ_D
1602
0
    UINT64_C(73277440), // ANDQV_VPZ_H
1603
0
    UINT64_C(77471744), // ANDQV_VPZ_S
1604
0
    UINT64_C(1912602624), // ANDSWri
1605
0
    UINT64_C(1778384896), // ANDSWrs
1606
0
    UINT64_C(4060086272), // ANDSXri
1607
0
    UINT64_C(3925868544), // ANDSXrs
1608
0
    UINT64_C(624967680),  // ANDS_PPzPP
1609
0
    UINT64_C(68820992), // ANDV_VPZ_B
1610
0
    UINT64_C(81403904), // ANDV_VPZ_D
1611
0
    UINT64_C(73015296), // ANDV_VPZ_H
1612
0
    UINT64_C(77209600), // ANDV_VPZ_S
1613
0
    UINT64_C(301989888),  // ANDWri
1614
0
    UINT64_C(167772160),  // ANDWrs
1615
0
    UINT64_C(2449473536), // ANDXri
1616
0
    UINT64_C(2315255808), // ANDXrs
1617
0
    UINT64_C(620773376),  // AND_PPzPP
1618
0
    UINT64_C(92274688), // AND_ZI
1619
0
    UINT64_C(68812800), // AND_ZPmZ_B
1620
0
    UINT64_C(81395712), // AND_ZPmZ_D
1621
0
    UINT64_C(73007104), // AND_ZPmZ_H
1622
0
    UINT64_C(77201408), // AND_ZPmZ_S
1623
0
    UINT64_C(69218304), // AND_ZZZ
1624
0
    UINT64_C(1310727168), // ANDv16i8
1625
0
    UINT64_C(236985344),  // ANDv8i8
1626
0
    UINT64_C(67404032), // ASRD_ZPmI_B
1627
0
    UINT64_C(75792384), // ASRD_ZPmI_D
1628
0
    UINT64_C(67404288), // ASRD_ZPmI_H
1629
0
    UINT64_C(71598080), // ASRD_ZPmI_S
1630
0
    UINT64_C(68452352), // ASRR_ZPmZ_B
1631
0
    UINT64_C(81035264), // ASRR_ZPmZ_D
1632
0
    UINT64_C(72646656), // ASRR_ZPmZ_H
1633
0
    UINT64_C(76840960), // ASRR_ZPmZ_S
1634
0
    UINT64_C(448800768),  // ASRVWr
1635
0
    UINT64_C(2596284416), // ASRVXr
1636
0
    UINT64_C(68714496), // ASR_WIDE_ZPmZ_B
1637
0
    UINT64_C(72908800), // ASR_WIDE_ZPmZ_H
1638
0
    UINT64_C(77103104), // ASR_WIDE_ZPmZ_S
1639
0
    UINT64_C(69238784), // ASR_WIDE_ZZZ_B
1640
0
    UINT64_C(73433088), // ASR_WIDE_ZZZ_H
1641
0
    UINT64_C(77627392), // ASR_WIDE_ZZZ_S
1642
0
    UINT64_C(67141888), // ASR_ZPmI_B
1643
0
    UINT64_C(75530240), // ASR_ZPmI_D
1644
0
    UINT64_C(67142144), // ASR_ZPmI_H
1645
0
    UINT64_C(71335936), // ASR_ZPmI_S
1646
0
    UINT64_C(68190208), // ASR_ZPmZ_B
1647
0
    UINT64_C(80773120), // ASR_ZPmZ_D
1648
0
    UINT64_C(72384512), // ASR_ZPmZ_H
1649
0
    UINT64_C(76578816), // ASR_ZPmZ_S
1650
0
    UINT64_C(69767168), // ASR_ZZI_B
1651
0
    UINT64_C(77631488), // ASR_ZZI_D
1652
0
    UINT64_C(70291456), // ASR_ZZI_H
1653
0
    UINT64_C(73437184), // ASR_ZZI_S
1654
0
    UINT64_C(3670087680), // AUTDA
1655
0
    UINT64_C(3670088704), // AUTDB
1656
0
    UINT64_C(3670096864), // AUTDZA
1657
0
    UINT64_C(3670097888), // AUTDZB
1658
0
    UINT64_C(3670085632), // AUTIA
1659
0
    UINT64_C(3573752223), // AUTIA1716
1660
0
    UINT64_C(3670129662), // AUTIA171615
1661
0
    UINT64_C(3573752767), // AUTIASP
1662
0
    UINT64_C(4085252127), // AUTIASPPCi
1663
0
    UINT64_C(3670118430), // AUTIASPPCr
1664
0
    UINT64_C(3573752735), // AUTIAZ
1665
0
    UINT64_C(3670086656), // AUTIB
1666
0
    UINT64_C(3573752287), // AUTIB1716
1667
0
    UINT64_C(3670130686), // AUTIB171615
1668
0
    UINT64_C(3573752831), // AUTIBSP
1669
0
    UINT64_C(4087349279), // AUTIBSPPCi
1670
0
    UINT64_C(3670119454), // AUTIBSPPCr
1671
0
    UINT64_C(3573752799), // AUTIBZ
1672
0
    UINT64_C(3670094816), // AUTIZA
1673
0
    UINT64_C(3670095840), // AUTIZB
1674
0
    UINT64_C(3573563487), // AXFLAG
1675
0
    UINT64_C(335544320),  // B
1676
0
    UINT64_C(3458203648), // BCAX
1677
0
    UINT64_C(73414656), // BCAX_ZZZZ
1678
0
    UINT64_C(1409286160), // BCcc
1679
0
    UINT64_C(1157673984), // BDEP_ZZZ_B
1680
0
    UINT64_C(1170256896), // BDEP_ZZZ_D
1681
0
    UINT64_C(1161868288), // BDEP_ZZZ_H
1682
0
    UINT64_C(1166062592), // BDEP_ZZZ_S
1683
0
    UINT64_C(1157672960), // BEXT_ZZZ_B
1684
0
    UINT64_C(1170255872), // BEXT_ZZZ_D
1685
0
    UINT64_C(1161867264), // BEXT_ZZZ_H
1686
0
    UINT64_C(1166061568), // BEXT_ZZZ_S
1687
0
    UINT64_C(255913984),  // BF16DOTlanev4bf16
1688
0
    UINT64_C(1329655808), // BF16DOTlanev8bf16
1689
0
    UINT64_C(1856075776), // BF1CVTL2v8f16
1690
0
    UINT64_C(1695102976), // BF1CVTLT_ZZ_BtoH
1691
0
    UINT64_C(3244744705), // BF1CVTL_2ZZ_BtoH_NAME
1692
0
    UINT64_C(782333952),  // BF1CVTLv8f16
1693
0
    UINT64_C(3244744704), // BF1CVT_2ZZ_BtoH_NAME
1694
0
    UINT64_C(1695037440), // BF1CVT_ZZ_BtoH
1695
0
    UINT64_C(1860270080), // BF2CVTL2v8f16
1696
0
    UINT64_C(1695104000), // BF2CVTLT_ZZ_BtoH
1697
0
    UINT64_C(3253133313), // BF2CVTL_2ZZ_BtoH_NAME
1698
0
    UINT64_C(786528256),  // BF2CVTLv8f16
1699
0
    UINT64_C(3253133312), // BF2CVT_2ZZ_BtoH_NAME
1700
0
    UINT64_C(1695038464), // BF2CVT_ZZ_BtoH
1701
0
    UINT64_C(3252952064), // BFADD_VG2_M2Z_H
1702
0
    UINT64_C(3253017600), // BFADD_VG4_M4Z_H
1703
0
    UINT64_C(1694531584), // BFADD_ZPmZZ
1704
0
    UINT64_C(1694498816), // BFADD_ZZZ
1705
0
    UINT64_C(3240148992), // BFCLAMP_VG2_2ZZZ_H
1706
0
    UINT64_C(3240151040), // BFCLAMP_VG4_4ZZZ_H
1707
0
    UINT64_C(1679827968), // BFCLAMP_ZZZ
1708
0
    UINT64_C(509820928),  // BFCVT
1709
0
    UINT64_C(245458944),  // BFCVTN
1710
0
    UINT64_C(1319200768), // BFCVTN2
1711
0
    UINT64_C(1686806528), // BFCVTNT_ZPmZ
1712
0
    UINT64_C(1695168512), // BFCVTN_Z2Z_HtoB
1713
0
    UINT64_C(3244351520), // BFCVTN_Z2Z_StoH
1714
0
    UINT64_C(3244613632), // BFCVT_Z2Z_HtoB
1715
0
    UINT64_C(3244351488), // BFCVT_Z2Z_StoH
1716
0
    UINT64_C(1703583744), // BFCVT_ZPmZ
1717
0
    UINT64_C(3248492560), // BFDOT_VG2_M2Z2Z_HtoS
1718
0
    UINT64_C(3243249688), // BFDOT_VG2_M2ZZI_HtoS
1719
0
    UINT64_C(3240103952), // BFDOT_VG2_M2ZZ_HtoS
1720
0
    UINT64_C(3248558096), // BFDOT_VG4_M4Z4Z_HtoS
1721
0
    UINT64_C(3243282456), // BFDOT_VG4_M4ZZI_HtoS
1722
0
    UINT64_C(3241152528), // BFDOT_VG4_M4ZZ_HtoS
1723
0
    UINT64_C(1684029440), // BFDOT_ZZI
1724
0
    UINT64_C(1684045824), // BFDOT_ZZZ
1725
0
    UINT64_C(776010752),  // BFDOTv4bf16
1726
0
    UINT64_C(1849752576), // BFDOTv8bf16
1727
0
    UINT64_C(3240145184), // BFMAXNM_VG2_2Z2Z_H
1728
0
    UINT64_C(3240141088), // BFMAXNM_VG2_2ZZ_H
1729
0
    UINT64_C(3240147232), // BFMAXNM_VG4_4Z2Z_H
1730
0
    UINT64_C(3240143136), // BFMAXNM_VG4_4ZZ_H
1731
0
    UINT64_C(1694793728), // BFMAXNM_ZPmZZ
1732
0
    UINT64_C(3240145152), // BFMAX_VG2_2Z2Z_H
1733
0
    UINT64_C(3240141056), // BFMAX_VG2_2ZZ_H
1734
0
    UINT64_C(3240147200), // BFMAX_VG4_4Z2Z_H
1735
0
    UINT64_C(3240143104), // BFMAX_VG4_4ZZ_H
1736
0
    UINT64_C(1694924800), // BFMAX_ZPmZZ
1737
0
    UINT64_C(3240145185), // BFMINNM_VG2_2Z2Z_H
1738
0
    UINT64_C(3240141089), // BFMINNM_VG2_2ZZ_H
1739
0
    UINT64_C(3240147233), // BFMINNM_VG4_4Z2Z_H
1740
0
    UINT64_C(3240143137), // BFMINNM_VG4_4ZZ_H
1741
0
    UINT64_C(1694859264), // BFMINNM_ZPmZZ
1742
0
    UINT64_C(3240145153), // BFMIN_VG2_2Z2Z_H
1743
0
    UINT64_C(3240141057), // BFMIN_VG2_2ZZ_H
1744
0
    UINT64_C(3240147201), // BFMIN_VG4_4Z2Z_H
1745
0
    UINT64_C(3240143105), // BFMIN_VG4_4ZZ_H
1746
0
    UINT64_C(1694990336), // BFMIN_ZPmZZ
1747
0
    UINT64_C(784399360),  // BFMLALB
1748
0
    UINT64_C(264302592),  // BFMLALBIdx
1749
0
    UINT64_C(1692434432), // BFMLALB_ZZZ
1750
0
    UINT64_C(1692418048), // BFMLALB_ZZZI
1751
0
    UINT64_C(1858141184), // BFMLALT
1752
0
    UINT64_C(1338044416), // BFMLALTIdx
1753
0
    UINT64_C(1692435456), // BFMLALT_ZZZ
1754
0
    UINT64_C(1692419072), // BFMLALT_ZZZI
1755
0
    UINT64_C(3246395408), // BFMLAL_MZZI_HtoS
1756
0
    UINT64_C(3240102928), // BFMLAL_MZZ_HtoS
1757
0
    UINT64_C(3248490512), // BFMLAL_VG2_M2Z2Z_HtoS
1758
0
    UINT64_C(3247443984), // BFMLAL_VG2_M2ZZI_HtoS
1759
0
    UINT64_C(3240101904), // BFMLAL_VG2_M2ZZ_HtoS
1760
0
    UINT64_C(3248556048), // BFMLAL_VG4_M4Z4Z_HtoS
1761
0
    UINT64_C(3247476752), // BFMLAL_VG4_M4ZZI_HtoS
1762
0
    UINT64_C(3241150480), // BFMLAL_VG4_M4ZZ_HtoS
1763
0
    UINT64_C(3252686856), // BFMLA_VG2_M2Z2Z
1764
0
    UINT64_C(3244301312), // BFMLA_VG2_M2ZZ
1765
0
    UINT64_C(3239055392), // BFMLA_VG2_M2ZZI
1766
0
    UINT64_C(3252752392), // BFMLA_VG4_M4Z4Z
1767
0
    UINT64_C(3245349888), // BFMLA_VG4_M4ZZ
1768
0
    UINT64_C(3239088160), // BFMLA_VG4_M4ZZI
1769
0
    UINT64_C(1696595968), // BFMLA_ZPmZZ
1770
0
    UINT64_C(1679820800), // BFMLA_ZZZI
1771
0
    UINT64_C(1692426240), // BFMLSLB_ZZZI_S
1772
0
    UINT64_C(1692442624), // BFMLSLB_ZZZ_S
1773
0
    UINT64_C(1692427264), // BFMLSLT_ZZZI_S
1774
0
    UINT64_C(1692443648), // BFMLSLT_ZZZ_S
1775
0
    UINT64_C(3246395416), // BFMLSL_MZZI_HtoS
1776
0
    UINT64_C(3240102936), // BFMLSL_MZZ_HtoS
1777
0
    UINT64_C(3248490520), // BFMLSL_VG2_M2Z2Z_HtoS
1778
0
    UINT64_C(3247443992), // BFMLSL_VG2_M2ZZI_HtoS
1779
0
    UINT64_C(3240101912), // BFMLSL_VG2_M2ZZ_HtoS
1780
0
    UINT64_C(3248556056), // BFMLSL_VG4_M4Z4Z_HtoS
1781
0
    UINT64_C(3247476760), // BFMLSL_VG4_M4ZZI_HtoS
1782
0
    UINT64_C(3241150488), // BFMLSL_VG4_M4ZZ_HtoS
1783
0
    UINT64_C(3252686872), // BFMLS_VG2_M2Z2Z
1784
0
    UINT64_C(3244301320), // BFMLS_VG2_M2ZZ
1785
0
    UINT64_C(3239055408), // BFMLS_VG2_M2ZZI
1786
0
    UINT64_C(3252752408), // BFMLS_VG4_M4Z4Z
1787
0
    UINT64_C(3245349896), // BFMLS_VG4_M4ZZ
1788
0
    UINT64_C(3239088176), // BFMLS_VG4_M4ZZI
1789
0
    UINT64_C(1696604160), // BFMLS_ZPmZZ
1790
0
    UINT64_C(1679821824), // BFMLS_ZZZI
1791
0
    UINT64_C(1849748480), // BFMMLA
1792
0
    UINT64_C(1684071424), // BFMMLA_ZZZ
1793
0
    UINT64_C(2172649472), // BFMOPA_MPPZZ
1794
0
    UINT64_C(2174746632), // BFMOPA_MPPZZ_H
1795
0
    UINT64_C(2172649488), // BFMOPS_MPPZZ
1796
0
    UINT64_C(2174746648), // BFMOPS_MPPZZ_H
1797
0
    UINT64_C(1694662656), // BFMUL_ZPmZZ
1798
0
    UINT64_C(1694500864), // BFMUL_ZZZ
1799
0
    UINT64_C(1679828992), // BFMUL_ZZZI
1800
0
    UINT64_C(855638016),  // BFMWri
1801
0
    UINT64_C(3007315968), // BFMXri
1802
0
    UINT64_C(3252952072), // BFSUB_VG2_M2Z_H
1803
0
    UINT64_C(3253017608), // BFSUB_VG4_M4Z_H
1804
0
    UINT64_C(1694597120), // BFSUB_ZPmZZ
1805
0
    UINT64_C(1694499840), // BFSUB_ZZZ
1806
0
    UINT64_C(3243245592), // BFVDOT_VG2_M2ZZI_HtoS
1807
0
    UINT64_C(1157675008), // BGRP_ZZZ_B
1808
0
    UINT64_C(1170257920), // BGRP_ZZZ_D
1809
0
    UINT64_C(1161869312), // BGRP_ZZZ_H
1810
0
    UINT64_C(1166063616), // BGRP_ZZZ_S
1811
0
    UINT64_C(1780482048), // BICSWrs
1812
0
    UINT64_C(3927965696), // BICSXrs
1813
0
    UINT64_C(624967696),  // BICS_PPzPP
1814
0
    UINT64_C(169869312),  // BICWrs
1815
0
    UINT64_C(2317352960), // BICXrs
1816
0
    UINT64_C(620773392),  // BIC_PPzPP
1817
0
    UINT64_C(68878336), // BIC_ZPmZ_B
1818
0
    UINT64_C(81461248), // BIC_ZPmZ_D
1819
0
    UINT64_C(73072640), // BIC_ZPmZ_H
1820
0
    UINT64_C(77266944), // BIC_ZPmZ_S
1821
0
    UINT64_C(81801216), // BIC_ZZZ
1822
0
    UINT64_C(1314921472), // BICv16i8
1823
0
    UINT64_C(788534272),  // BICv2i32
1824
0
    UINT64_C(788567040),  // BICv4i16
1825
0
    UINT64_C(1862276096), // BICv4i32
1826
0
    UINT64_C(1862308864), // BICv8i16
1827
0
    UINT64_C(241179648),  // BICv8i8
1828
0
    UINT64_C(1860180992), // BIFv16i8
1829
0
    UINT64_C(786439168),  // BIFv8i8
1830
0
    UINT64_C(1855986688), // BITv16i8
1831
0
    UINT64_C(782244864),  // BITv8i8
1832
0
    UINT64_C(2483027968), // BL
1833
0
    UINT64_C(3594452992), // BLR
1834
0
    UINT64_C(3611232256), // BLRAA
1835
0
    UINT64_C(3594455071), // BLRAAZ
1836
0
    UINT64_C(3611233280), // BLRAB
1837
0
    UINT64_C(3594456095), // BLRABZ
1838
0
    UINT64_C(2155872264), // BMOPA_MPPZZ_S
1839
0
    UINT64_C(2155872280), // BMOPS_MPPZZ_S
1840
0
    UINT64_C(3592355840), // BR
1841
0
    UINT64_C(3609135104), // BRAA
1842
0
    UINT64_C(3592357919), // BRAAZ
1843
0
    UINT64_C(3609136128), // BRAB
1844
0
    UINT64_C(3592358943), // BRABZ
1845
0
    UINT64_C(3574166175), // BRB_IALL
1846
0
    UINT64_C(3574166207), // BRB_INJ
1847
0
    UINT64_C(3558866944), // BRK
1848
0
    UINT64_C(626016256),  // BRKAS_PPzP
1849
0
    UINT64_C(621821968),  // BRKA_PPmP
1850
0
    UINT64_C(621821952),  // BRKA_PPzP
1851
0
    UINT64_C(634404864),  // BRKBS_PPzP
1852
0
    UINT64_C(630210576),  // BRKB_PPmP
1853
0
    UINT64_C(630210560),  // BRKB_PPzP
1854
0
    UINT64_C(626540544),  // BRKNS_PPzP
1855
0
    UINT64_C(622346240),  // BRKN_PPzP
1856
0
    UINT64_C(625000448),  // BRKPAS_PPzPP
1857
0
    UINT64_C(620806144),  // BRKPA_PPzPP
1858
0
    UINT64_C(625000464),  // BRKPBS_PPzPP
1859
0
    UINT64_C(620806160),  // BRKPB_PPzPP
1860
0
    UINT64_C(73415680), // BSL1N_ZZZZ
1861
0
    UINT64_C(77609984), // BSL2N_ZZZZ
1862
0
    UINT64_C(69221376), // BSL_ZZZZ
1863
0
    UINT64_C(1851792384), // BSLv16i8
1864
0
    UINT64_C(778050560),  // BSLv8i8
1865
0
    UINT64_C(1409286144), // Bcc
1866
0
    UINT64_C(1157683200), // CADD_ZZI_B
1867
0
    UINT64_C(1170266112), // CADD_ZZI_D
1868
0
    UINT64_C(1161877504), // CADD_ZZI_H
1869
0
    UINT64_C(1166071808), // CADD_ZZI_S
1870
0
    UINT64_C(148929536),  // CASAB
1871
0
    UINT64_C(1222671360), // CASAH
1872
0
    UINT64_C(148962304),  // CASALB
1873
0
    UINT64_C(1222704128), // CASALH
1874
0
    UINT64_C(2296445952), // CASALW
1875
0
    UINT64_C(3370187776), // CASALX
1876
0
    UINT64_C(2296413184), // CASAW
1877
0
    UINT64_C(3370155008), // CASAX
1878
0
    UINT64_C(144735232),  // CASB
1879
0
    UINT64_C(1218477056), // CASH
1880
0
    UINT64_C(144768000),  // CASLB
1881
0
    UINT64_C(1218509824), // CASLH
1882
0
    UINT64_C(2292251648), // CASLW
1883
0
    UINT64_C(3365993472), // CASLX
1884
0
    UINT64_C(140573696),  // CASPALW
1885
0
    UINT64_C(1214315520), // CASPALX
1886
0
    UINT64_C(140540928),  // CASPAW
1887
0
    UINT64_C(1214282752), // CASPAX
1888
0
    UINT64_C(136379392),  // CASPLW
1889
0
    UINT64_C(1210121216), // CASPLX
1890
0
    UINT64_C(136346624),  // CASPW
1891
0
    UINT64_C(1210088448), // CASPX
1892
0
    UINT64_C(2292218880), // CASW
1893
0
    UINT64_C(3365960704), // CASX
1894
0
    UINT64_C(889192448),  // CBNZW
1895
0
    UINT64_C(3036676096), // CBNZX
1896
0
    UINT64_C(872415232),  // CBZW
1897
0
    UINT64_C(3019898880), // CBZX
1898
0
    UINT64_C(977274880),  // CCMNWi
1899
0
    UINT64_C(977272832),  // CCMNWr
1900
0
    UINT64_C(3124758528), // CCMNXi
1901
0
    UINT64_C(3124756480), // CCMNXr
1902
0
    UINT64_C(2051016704), // CCMPWi
1903
0
    UINT64_C(2051014656), // CCMPWr
1904
0
    UINT64_C(4198500352), // CCMPXi
1905
0
    UINT64_C(4198498304), // CCMPXr
1906
0
    UINT64_C(1155547136), // CDOT_ZZZI_D
1907
0
    UINT64_C(1151352832), // CDOT_ZZZI_S
1908
0
    UINT64_C(1153437696), // CDOT_ZZZ_D
1909
0
    UINT64_C(1149243392), // CDOT_ZZZ_S
1910
0
    UINT64_C(3573563423), // CFINV
1911
0
    UINT64_C(3573753119), // CHKFEAT
1912
0
    UINT64_C(87072768), // CLASTA_RPZ_B
1913
0
    UINT64_C(99655680), // CLASTA_RPZ_D
1914
0
    UINT64_C(91267072), // CLASTA_RPZ_H
1915
0
    UINT64_C(95461376), // CLASTA_RPZ_S
1916
0
    UINT64_C(86671360), // CLASTA_VPZ_B
1917
0
    UINT64_C(99254272), // CLASTA_VPZ_D
1918
0
    UINT64_C(90865664), // CLASTA_VPZ_H
1919
0
    UINT64_C(95059968), // CLASTA_VPZ_S
1920
0
    UINT64_C(86540288), // CLASTA_ZPZ_B
1921
0
    UINT64_C(99123200), // CLASTA_ZPZ_D
1922
0
    UINT64_C(90734592), // CLASTA_ZPZ_H
1923
0
    UINT64_C(94928896), // CLASTA_ZPZ_S
1924
0
    UINT64_C(87138304), // CLASTB_RPZ_B
1925
0
    UINT64_C(99721216), // CLASTB_RPZ_D
1926
0
    UINT64_C(91332608), // CLASTB_RPZ_H
1927
0
    UINT64_C(95526912), // CLASTB_RPZ_S
1928
0
    UINT64_C(86736896), // CLASTB_VPZ_B
1929
0
    UINT64_C(99319808), // CLASTB_VPZ_D
1930
0
    UINT64_C(90931200), // CLASTB_VPZ_H
1931
0
    UINT64_C(95125504), // CLASTB_VPZ_S
1932
0
    UINT64_C(86605824), // CLASTB_ZPZ_B
1933
0
    UINT64_C(99188736), // CLASTB_ZPZ_D
1934
0
    UINT64_C(90800128), // CLASTB_ZPZ_H
1935
0
    UINT64_C(94994432), // CLASTB_ZPZ_S
1936
0
    UINT64_C(3573755999), // CLREX
1937
0
    UINT64_C(1522537472), // CLSWr
1938
0
    UINT64_C(3670021120), // CLSXr
1939
0
    UINT64_C(68722688), // CLS_ZPmZ_B
1940
0
    UINT64_C(81305600), // CLS_ZPmZ_D
1941
0
    UINT64_C(72916992), // CLS_ZPmZ_H
1942
0
    UINT64_C(77111296), // CLS_ZPmZ_S
1943
0
    UINT64_C(1310738432), // CLSv16i8
1944
0
    UINT64_C(245385216),  // CLSv2i32
1945
0
    UINT64_C(241190912),  // CLSv4i16
1946
0
    UINT64_C(1319127040), // CLSv4i32
1947
0
    UINT64_C(1314932736), // CLSv8i16
1948
0
    UINT64_C(236996608),  // CLSv8i8
1949
0
    UINT64_C(1522536448), // CLZWr
1950
0
    UINT64_C(3670020096), // CLZXr
1951
0
    UINT64_C(68788224), // CLZ_ZPmZ_B
1952
0
    UINT64_C(81371136), // CLZ_ZPmZ_D
1953
0
    UINT64_C(72982528), // CLZ_ZPmZ_H
1954
0
    UINT64_C(77176832), // CLZ_ZPmZ_S
1955
0
    UINT64_C(1847609344), // CLZv16i8
1956
0
    UINT64_C(782256128),  // CLZv2i32
1957
0
    UINT64_C(778061824),  // CLZv4i16
1958
0
    UINT64_C(1855997952), // CLZv4i32
1959
0
    UINT64_C(1851803648), // CLZv8i16
1960
0
    UINT64_C(773867520),  // CLZv8i8
1961
0
    UINT64_C(1847626752), // CMEQv16i8
1962
0
    UINT64_C(1310758912), // CMEQv16i8rz
1963
0
    UINT64_C(2128645120), // CMEQv1i64
1964
0
    UINT64_C(1591777280), // CMEQv1i64rz
1965
0
    UINT64_C(782273536),  // CMEQv2i32
1966
0
    UINT64_C(245405696),  // CMEQv2i32rz
1967
0
    UINT64_C(1860209664), // CMEQv2i64
1968
0
    UINT64_C(1323341824), // CMEQv2i64rz
1969
0
    UINT64_C(778079232),  // CMEQv4i16
1970
0
    UINT64_C(241211392),  // CMEQv4i16rz
1971
0
    UINT64_C(1856015360), // CMEQv4i32
1972
0
    UINT64_C(1319147520), // CMEQv4i32rz
1973
0
    UINT64_C(1851821056), // CMEQv8i16
1974
0
    UINT64_C(1314953216), // CMEQv8i16rz
1975
0
    UINT64_C(773884928),  // CMEQv8i8
1976
0
    UINT64_C(237017088),  // CMEQv8i8rz
1977
0
    UINT64_C(1310735360), // CMGEv16i8
1978
0
    UINT64_C(1847625728), // CMGEv16i8rz
1979
0
    UINT64_C(1591753728), // CMGEv1i64
1980
0
    UINT64_C(2128644096), // CMGEv1i64rz
1981
0
    UINT64_C(245382144),  // CMGEv2i32
1982
0
    UINT64_C(782272512),  // CMGEv2i32rz
1983
0
    UINT64_C(1323318272), // CMGEv2i64
1984
0
    UINT64_C(1860208640), // CMGEv2i64rz
1985
0
    UINT64_C(241187840),  // CMGEv4i16
1986
0
    UINT64_C(778078208),  // CMGEv4i16rz
1987
0
    UINT64_C(1319123968), // CMGEv4i32
1988
0
    UINT64_C(1856014336), // CMGEv4i32rz
1989
0
    UINT64_C(1314929664), // CMGEv8i16
1990
0
    UINT64_C(1851820032), // CMGEv8i16rz
1991
0
    UINT64_C(236993536),  // CMGEv8i8
1992
0
    UINT64_C(773883904),  // CMGEv8i8rz
1993
0
    UINT64_C(1310733312), // CMGTv16i8
1994
0
    UINT64_C(1310754816), // CMGTv16i8rz
1995
0
    UINT64_C(1591751680), // CMGTv1i64
1996
0
    UINT64_C(1591773184), // CMGTv1i64rz
1997
0
    UINT64_C(245380096),  // CMGTv2i32
1998
0
    UINT64_C(245401600),  // CMGTv2i32rz
1999
0
    UINT64_C(1323316224), // CMGTv2i64
2000
0
    UINT64_C(1323337728), // CMGTv2i64rz
2001
0
    UINT64_C(241185792),  // CMGTv4i16
2002
0
    UINT64_C(241207296),  // CMGTv4i16rz
2003
0
    UINT64_C(1319121920), // CMGTv4i32
2004
0
    UINT64_C(1319143424), // CMGTv4i32rz
2005
0
    UINT64_C(1314927616), // CMGTv8i16
2006
0
    UINT64_C(1314949120), // CMGTv8i16rz
2007
0
    UINT64_C(236991488),  // CMGTv8i8
2008
0
    UINT64_C(237012992),  // CMGTv8i8rz
2009
0
    UINT64_C(1847604224), // CMHIv16i8
2010
0
    UINT64_C(2128622592), // CMHIv1i64
2011
0
    UINT64_C(782251008),  // CMHIv2i32
2012
0
    UINT64_C(1860187136), // CMHIv2i64
2013
0
    UINT64_C(778056704),  // CMHIv4i16
2014
0
    UINT64_C(1855992832), // CMHIv4i32
2015
0
    UINT64_C(1851798528), // CMHIv8i16
2016
0
    UINT64_C(773862400),  // CMHIv8i8
2017
0
    UINT64_C(1847606272), // CMHSv16i8
2018
0
    UINT64_C(2128624640), // CMHSv1i64
2019
0
    UINT64_C(782253056),  // CMHSv2i32
2020
0
    UINT64_C(1860189184), // CMHSv2i64
2021
0
    UINT64_C(778058752),  // CMHSv4i16
2022
0
    UINT64_C(1855994880), // CMHSv4i32
2023
0
    UINT64_C(1851800576), // CMHSv8i16
2024
0
    UINT64_C(773864448),  // CMHSv8i8
2025
0
    UINT64_C(1151361024), // CMLA_ZZZI_H
2026
0
    UINT64_C(1155555328), // CMLA_ZZZI_S
2027
0
    UINT64_C(1140858880), // CMLA_ZZZ_B
2028
0
    UINT64_C(1153441792), // CMLA_ZZZ_D
2029
0
    UINT64_C(1145053184), // CMLA_ZZZ_H
2030
0
    UINT64_C(1149247488), // CMLA_ZZZ_S
2031
0
    UINT64_C(1847629824), // CMLEv16i8rz
2032
0
    UINT64_C(2128648192), // CMLEv1i64rz
2033
0
    UINT64_C(782276608),  // CMLEv2i32rz
2034
0
    UINT64_C(1860212736), // CMLEv2i64rz
2035
0
    UINT64_C(778082304),  // CMLEv4i16rz
2036
0
    UINT64_C(1856018432), // CMLEv4i32rz
2037
0
    UINT64_C(1851824128), // CMLEv8i16rz
2038
0
    UINT64_C(773888000),  // CMLEv8i8rz
2039
0
    UINT64_C(1310763008), // CMLTv16i8rz
2040
0
    UINT64_C(1591781376), // CMLTv1i64rz
2041
0
    UINT64_C(245409792),  // CMLTv2i32rz
2042
0
    UINT64_C(1323345920), // CMLTv2i64rz
2043
0
    UINT64_C(241215488),  // CMLTv4i16rz
2044
0
    UINT64_C(1319151616), // CMLTv4i32rz
2045
0
    UINT64_C(1314957312), // CMLTv8i16rz
2046
0
    UINT64_C(237021184),  // CMLTv8i8rz
2047
0
    UINT64_C(620789760),  // CMPEQ_PPzZI_B
2048
0
    UINT64_C(633372672),  // CMPEQ_PPzZI_D
2049
0
    UINT64_C(624984064),  // CMPEQ_PPzZI_H
2050
0
    UINT64_C(629178368),  // CMPEQ_PPzZI_S
2051
0
    UINT64_C(604020736),  // CMPEQ_PPzZZ_B
2052
0
    UINT64_C(616603648),  // CMPEQ_PPzZZ_D
2053
0
    UINT64_C(608215040),  // CMPEQ_PPzZZ_H
2054
0
    UINT64_C(612409344),  // CMPEQ_PPzZZ_S
2055
0
    UINT64_C(603987968),  // CMPEQ_WIDE_PPzZZ_B
2056
0
    UINT64_C(608182272),  // CMPEQ_WIDE_PPzZZ_H
2057
0
    UINT64_C(612376576),  // CMPEQ_WIDE_PPzZZ_S
2058
0
    UINT64_C(620756992),  // CMPGE_PPzZI_B
2059
0
    UINT64_C(633339904),  // CMPGE_PPzZI_D
2060
0
    UINT64_C(624951296),  // CMPGE_PPzZI_H
2061
0
    UINT64_C(629145600),  // CMPGE_PPzZI_S
2062
0
    UINT64_C(604012544),  // CMPGE_PPzZZ_B
2063
0
    UINT64_C(616595456),  // CMPGE_PPzZZ_D
2064
0
    UINT64_C(608206848),  // CMPGE_PPzZZ_H
2065
0
    UINT64_C(612401152),  // CMPGE_PPzZZ_S
2066
0
    UINT64_C(603996160),  // CMPGE_WIDE_PPzZZ_B
2067
0
    UINT64_C(608190464),  // CMPGE_WIDE_PPzZZ_H
2068
0
    UINT64_C(612384768),  // CMPGE_WIDE_PPzZZ_S
2069
0
    UINT64_C(620757008),  // CMPGT_PPzZI_B
2070
0
    UINT64_C(633339920),  // CMPGT_PPzZI_D
2071
0
    UINT64_C(624951312),  // CMPGT_PPzZI_H
2072
0
    UINT64_C(629145616),  // CMPGT_PPzZI_S
2073
0
    UINT64_C(604012560),  // CMPGT_PPzZZ_B
2074
0
    UINT64_C(616595472),  // CMPGT_PPzZZ_D
2075
0
    UINT64_C(608206864),  // CMPGT_PPzZZ_H
2076
0
    UINT64_C(612401168),  // CMPGT_PPzZZ_S
2077
0
    UINT64_C(603996176),  // CMPGT_WIDE_PPzZZ_B
2078
0
    UINT64_C(608190480),  // CMPGT_WIDE_PPzZZ_H
2079
0
    UINT64_C(612384784),  // CMPGT_WIDE_PPzZZ_S
2080
0
    UINT64_C(606076944),  // CMPHI_PPzZI_B
2081
0
    UINT64_C(618659856),  // CMPHI_PPzZI_D
2082
0
    UINT64_C(610271248),  // CMPHI_PPzZI_H
2083
0
    UINT64_C(614465552),  // CMPHI_PPzZI_S
2084
0
    UINT64_C(603979792),  // CMPHI_PPzZZ_B
2085
0
    UINT64_C(616562704),  // CMPHI_PPzZZ_D
2086
0
    UINT64_C(608174096),  // CMPHI_PPzZZ_H
2087
0
    UINT64_C(612368400),  // CMPHI_PPzZZ_S
2088
0
    UINT64_C(604028944),  // CMPHI_WIDE_PPzZZ_B
2089
0
    UINT64_C(608223248),  // CMPHI_WIDE_PPzZZ_H
2090
0
    UINT64_C(612417552),  // CMPHI_WIDE_PPzZZ_S
2091
0
    UINT64_C(606076928),  // CMPHS_PPzZI_B
2092
0
    UINT64_C(618659840),  // CMPHS_PPzZI_D
2093
0
    UINT64_C(610271232),  // CMPHS_PPzZI_H
2094
0
    UINT64_C(614465536),  // CMPHS_PPzZI_S
2095
0
    UINT64_C(603979776),  // CMPHS_PPzZZ_B
2096
0
    UINT64_C(616562688),  // CMPHS_PPzZZ_D
2097
0
    UINT64_C(608174080),  // CMPHS_PPzZZ_H
2098
0
    UINT64_C(612368384),  // CMPHS_PPzZZ_S
2099
0
    UINT64_C(604028928),  // CMPHS_WIDE_PPzZZ_B
2100
0
    UINT64_C(608223232),  // CMPHS_WIDE_PPzZZ_H
2101
0
    UINT64_C(612417536),  // CMPHS_WIDE_PPzZZ_S
2102
0
    UINT64_C(620765200),  // CMPLE_PPzZI_B
2103
0
    UINT64_C(633348112),  // CMPLE_PPzZI_D
2104
0
    UINT64_C(624959504),  // CMPLE_PPzZI_H
2105
0
    UINT64_C(629153808),  // CMPLE_PPzZI_S
2106
0
    UINT64_C(604004368),  // CMPLE_WIDE_PPzZZ_B
2107
0
    UINT64_C(608198672),  // CMPLE_WIDE_PPzZZ_H
2108
0
    UINT64_C(612392976),  // CMPLE_WIDE_PPzZZ_S
2109
0
    UINT64_C(606085120),  // CMPLO_PPzZI_B
2110
0
    UINT64_C(618668032),  // CMPLO_PPzZI_D
2111
0
    UINT64_C(610279424),  // CMPLO_PPzZI_H
2112
0
    UINT64_C(614473728),  // CMPLO_PPzZI_S
2113
0
    UINT64_C(604037120),  // CMPLO_WIDE_PPzZZ_B
2114
0
    UINT64_C(608231424),  // CMPLO_WIDE_PPzZZ_H
2115
0
    UINT64_C(612425728),  // CMPLO_WIDE_PPzZZ_S
2116
0
    UINT64_C(606085136),  // CMPLS_PPzZI_B
2117
0
    UINT64_C(618668048),  // CMPLS_PPzZI_D
2118
0
    UINT64_C(610279440),  // CMPLS_PPzZI_H
2119
0
    UINT64_C(614473744),  // CMPLS_PPzZI_S
2120
0
    UINT64_C(604037136),  // CMPLS_WIDE_PPzZZ_B
2121
0
    UINT64_C(608231440),  // CMPLS_WIDE_PPzZZ_H
2122
0
    UINT64_C(612425744),  // CMPLS_WIDE_PPzZZ_S
2123
0
    UINT64_C(620765184),  // CMPLT_PPzZI_B
2124
0
    UINT64_C(633348096),  // CMPLT_PPzZI_D
2125
0
    UINT64_C(624959488),  // CMPLT_PPzZI_H
2126
0
    UINT64_C(629153792),  // CMPLT_PPzZI_S
2127
0
    UINT64_C(604004352),  // CMPLT_WIDE_PPzZZ_B
2128
0
    UINT64_C(608198656),  // CMPLT_WIDE_PPzZZ_H
2129
0
    UINT64_C(612392960),  // CMPLT_WIDE_PPzZZ_S
2130
0
    UINT64_C(620789776),  // CMPNE_PPzZI_B
2131
0
    UINT64_C(633372688),  // CMPNE_PPzZI_D
2132
0
    UINT64_C(624984080),  // CMPNE_PPzZI_H
2133
0
    UINT64_C(629178384),  // CMPNE_PPzZI_S
2134
0
    UINT64_C(604020752),  // CMPNE_PPzZZ_B
2135
0
    UINT64_C(616603664),  // CMPNE_PPzZZ_D
2136
0
    UINT64_C(608215056),  // CMPNE_PPzZZ_H
2137
0
    UINT64_C(612409360),  // CMPNE_PPzZZ_S
2138
0
    UINT64_C(603987984),  // CMPNE_WIDE_PPzZZ_B
2139
0
    UINT64_C(608182288),  // CMPNE_WIDE_PPzZZ_H
2140
0
    UINT64_C(612376592),  // CMPNE_WIDE_PPzZZ_S
2141
0
    UINT64_C(1310755840), // CMTSTv16i8
2142
0
    UINT64_C(1591774208), // CMTSTv1i64
2143
0
    UINT64_C(245402624),  // CMTSTv2i32
2144
0
    UINT64_C(1323338752), // CMTSTv2i64
2145
0
    UINT64_C(241208320),  // CMTSTv4i16
2146
0
    UINT64_C(1319144448), // CMTSTv4i32
2147
0
    UINT64_C(1314950144), // CMTSTv8i16
2148
0
    UINT64_C(237014016),  // CMTSTv8i8
2149
0
    UINT64_C(68919296), // CNOT_ZPmZ_B
2150
0
    UINT64_C(81502208), // CNOT_ZPmZ_D
2151
0
    UINT64_C(73113600), // CNOT_ZPmZ_H
2152
0
    UINT64_C(77307904), // CNOT_ZPmZ_S
2153
0
    UINT64_C(69263360), // CNTB_XPiI
2154
0
    UINT64_C(81846272), // CNTD_XPiI
2155
0
    UINT64_C(73457664), // CNTH_XPiI
2156
0
    UINT64_C(622887424),  // CNTP_XCI_B
2157
0
    UINT64_C(635470336),  // CNTP_XCI_D
2158
0
    UINT64_C(627081728),  // CNTP_XCI_H
2159
0
    UINT64_C(631276032),  // CNTP_XCI_S
2160
0
    UINT64_C(622886912),  // CNTP_XPP_B
2161
0
    UINT64_C(635469824),  // CNTP_XPP_D
2162
0
    UINT64_C(627081216),  // CNTP_XPP_H
2163
0
    UINT64_C(631275520),  // CNTP_XPP_S
2164
0
    UINT64_C(77651968), // CNTW_XPiI
2165
0
    UINT64_C(1522539520), // CNTWr
2166
0
    UINT64_C(3670023168), // CNTXr
2167
0
    UINT64_C(68853760), // CNT_ZPmZ_B
2168
0
    UINT64_C(81436672), // CNT_ZPmZ_D
2169
0
    UINT64_C(73048064), // CNT_ZPmZ_H
2170
0
    UINT64_C(77242368), // CNT_ZPmZ_S
2171
0
    UINT64_C(1310742528), // CNTv16i8
2172
0
    UINT64_C(237000704),  // CNTv8i8
2173
0
    UINT64_C(98664448), // COMPACT_ZPZ_D
2174
0
    UINT64_C(94470144), // COMPACT_ZPZ_S
2175
0
    UINT64_C(494928896),  // CPYE
2176
0
    UINT64_C(494978048),  // CPYEN
2177
0
    UINT64_C(494961664),  // CPYERN
2178
0
    UINT64_C(494937088),  // CPYERT
2179
0
    UINT64_C(494986240),  // CPYERTN
2180
0
    UINT64_C(494969856),  // CPYERTRN
2181
0
    UINT64_C(494953472),  // CPYERTWN
2182
0
    UINT64_C(494941184),  // CPYET
2183
0
    UINT64_C(494990336),  // CPYETN
2184
0
    UINT64_C(494973952),  // CPYETRN
2185
0
    UINT64_C(494957568),  // CPYETWN
2186
0
    UINT64_C(494945280),  // CPYEWN
2187
0
    UINT64_C(494932992),  // CPYEWT
2188
0
    UINT64_C(494982144),  // CPYEWTN
2189
0
    UINT64_C(494965760),  // CPYEWTRN
2190
0
    UINT64_C(494949376),  // CPYEWTWN
2191
0
    UINT64_C(427820032),  // CPYFE
2192
0
    UINT64_C(427869184),  // CPYFEN
2193
0
    UINT64_C(427852800),  // CPYFERN
2194
0
    UINT64_C(427828224),  // CPYFERT
2195
0
    UINT64_C(427877376),  // CPYFERTN
2196
0
    UINT64_C(427860992),  // CPYFERTRN
2197
0
    UINT64_C(427844608),  // CPYFERTWN
2198
0
    UINT64_C(427832320),  // CPYFET
2199
0
    UINT64_C(427881472),  // CPYFETN
2200
0
    UINT64_C(427865088),  // CPYFETRN
2201
0
    UINT64_C(427848704),  // CPYFETWN
2202
0
    UINT64_C(427836416),  // CPYFEWN
2203
0
    UINT64_C(427824128),  // CPYFEWT
2204
0
    UINT64_C(427873280),  // CPYFEWTN
2205
0
    UINT64_C(427856896),  // CPYFEWTRN
2206
0
    UINT64_C(427840512),  // CPYFEWTWN
2207
0
    UINT64_C(423625728),  // CPYFM
2208
0
    UINT64_C(423674880),  // CPYFMN
2209
0
    UINT64_C(423658496),  // CPYFMRN
2210
0
    UINT64_C(423633920),  // CPYFMRT
2211
0
    UINT64_C(423683072),  // CPYFMRTN
2212
0
    UINT64_C(423666688),  // CPYFMRTRN
2213
0
    UINT64_C(423650304),  // CPYFMRTWN
2214
0
    UINT64_C(423638016),  // CPYFMT
2215
0
    UINT64_C(423687168),  // CPYFMTN
2216
0
    UINT64_C(423670784),  // CPYFMTRN
2217
0
    UINT64_C(423654400),  // CPYFMTWN
2218
0
    UINT64_C(423642112),  // CPYFMWN
2219
0
    UINT64_C(423629824),  // CPYFMWT
2220
0
    UINT64_C(423678976),  // CPYFMWTN
2221
0
    UINT64_C(423662592),  // CPYFMWTRN
2222
0
    UINT64_C(423646208),  // CPYFMWTWN
2223
0
    UINT64_C(419431424),  // CPYFP
2224
0
    UINT64_C(419480576),  // CPYFPN
2225
0
    UINT64_C(419464192),  // CPYFPRN
2226
0
    UINT64_C(419439616),  // CPYFPRT
2227
0
    UINT64_C(419488768),  // CPYFPRTN
2228
0
    UINT64_C(419472384),  // CPYFPRTRN
2229
0
    UINT64_C(419456000),  // CPYFPRTWN
2230
0
    UINT64_C(419443712),  // CPYFPT
2231
0
    UINT64_C(419492864),  // CPYFPTN
2232
0
    UINT64_C(419476480),  // CPYFPTRN
2233
0
    UINT64_C(419460096),  // CPYFPTWN
2234
0
    UINT64_C(419447808),  // CPYFPWN
2235
0
    UINT64_C(419435520),  // CPYFPWT
2236
0
    UINT64_C(419484672),  // CPYFPWTN
2237
0
    UINT64_C(419468288),  // CPYFPWTRN
2238
0
    UINT64_C(419451904),  // CPYFPWTWN
2239
0
    UINT64_C(490734592),  // CPYM
2240
0
    UINT64_C(490783744),  // CPYMN
2241
0
    UINT64_C(490767360),  // CPYMRN
2242
0
    UINT64_C(490742784),  // CPYMRT
2243
0
    UINT64_C(490791936),  // CPYMRTN
2244
0
    UINT64_C(490775552),  // CPYMRTRN
2245
0
    UINT64_C(490759168),  // CPYMRTWN
2246
0
    UINT64_C(490746880),  // CPYMT
2247
0
    UINT64_C(490796032),  // CPYMTN
2248
0
    UINT64_C(490779648),  // CPYMTRN
2249
0
    UINT64_C(490763264),  // CPYMTWN
2250
0
    UINT64_C(490750976),  // CPYMWN
2251
0
    UINT64_C(490738688),  // CPYMWT
2252
0
    UINT64_C(490787840),  // CPYMWTN
2253
0
    UINT64_C(490771456),  // CPYMWTRN
2254
0
    UINT64_C(490755072),  // CPYMWTWN
2255
0
    UINT64_C(486540288),  // CPYP
2256
0
    UINT64_C(486589440),  // CPYPN
2257
0
    UINT64_C(486573056),  // CPYPRN
2258
0
    UINT64_C(486548480),  // CPYPRT
2259
0
    UINT64_C(486597632),  // CPYPRTN
2260
0
    UINT64_C(486581248),  // CPYPRTRN
2261
0
    UINT64_C(486564864),  // CPYPRTWN
2262
0
    UINT64_C(486552576),  // CPYPT
2263
0
    UINT64_C(486601728),  // CPYPTN
2264
0
    UINT64_C(486585344),  // CPYPTRN
2265
0
    UINT64_C(486568960),  // CPYPTWN
2266
0
    UINT64_C(486556672),  // CPYPWN
2267
0
    UINT64_C(486544384),  // CPYPWT
2268
0
    UINT64_C(486593536),  // CPYPWTN
2269
0
    UINT64_C(486577152),  // CPYPWTRN
2270
0
    UINT64_C(486560768),  // CPYPWTWN
2271
0
    UINT64_C(84951040), // CPY_ZPmI_B
2272
0
    UINT64_C(97533952), // CPY_ZPmI_D
2273
0
    UINT64_C(89145344), // CPY_ZPmI_H
2274
0
    UINT64_C(93339648), // CPY_ZPmI_S
2275
0
    UINT64_C(86548480), // CPY_ZPmR_B
2276
0
    UINT64_C(99131392), // CPY_ZPmR_D
2277
0
    UINT64_C(90742784), // CPY_ZPmR_H
2278
0
    UINT64_C(94937088), // CPY_ZPmR_S
2279
0
    UINT64_C(86016000), // CPY_ZPmV_B
2280
0
    UINT64_C(98598912), // CPY_ZPmV_D
2281
0
    UINT64_C(90210304), // CPY_ZPmV_H
2282
0
    UINT64_C(94404608), // CPY_ZPmV_S
2283
0
    UINT64_C(84934656), // CPY_ZPzI_B
2284
0
    UINT64_C(97517568), // CPY_ZPzI_D
2285
0
    UINT64_C(89128960), // CPY_ZPzI_H
2286
0
    UINT64_C(93323264), // CPY_ZPzI_S
2287
0
    UINT64_C(448806912),  // CRC32Brr
2288
0
    UINT64_C(448811008),  // CRC32CBrr
2289
0
    UINT64_C(448812032),  // CRC32CHrr
2290
0
    UINT64_C(448813056),  // CRC32CWrr
2291
0
    UINT64_C(2596297728), // CRC32CXrr
2292
0
    UINT64_C(448807936),  // CRC32Hrr
2293
0
    UINT64_C(448808960),  // CRC32Wrr
2294
0
    UINT64_C(2596293632), // CRC32Xrr
2295
0
    UINT64_C(444596224),  // CSELWr
2296
0
    UINT64_C(2592079872), // CSELXr
2297
0
    UINT64_C(444597248),  // CSINCWr
2298
0
    UINT64_C(2592080896), // CSINCXr
2299
0
    UINT64_C(1518338048), // CSINVWr
2300
0
    UINT64_C(3665821696), // CSINVXr
2301
0
    UINT64_C(1518339072), // CSNEGWr
2302
0
    UINT64_C(3665822720), // CSNEGXr
2303
0
    UINT64_C(631250944),  // CTERMEQ_WW
2304
0
    UINT64_C(635445248),  // CTERMEQ_XX
2305
0
    UINT64_C(631250960),  // CTERMNE_WW
2306
0
    UINT64_C(635445264),  // CTERMNE_XX
2307
0
    UINT64_C(1522538496), // CTZWr
2308
0
    UINT64_C(3670022144), // CTZXr
2309
0
    UINT64_C(3567255553), // DCPS1
2310
0
    UINT64_C(3567255554), // DCPS2
2311
0
    UINT64_C(3567255555), // DCPS3
2312
0
    UINT64_C(70312960), // DECB_XPiI
2313
0
    UINT64_C(82895872), // DECD_XPiI
2314
0
    UINT64_C(82887680), // DECD_ZPiI
2315
0
    UINT64_C(74507264), // DECH_XPiI
2316
0
    UINT64_C(74499072), // DECH_ZPiI
2317
0
    UINT64_C(623740928),  // DECP_XP_B
2318
0
    UINT64_C(636323840),  // DECP_XP_D
2319
0
    UINT64_C(627935232),  // DECP_XP_H
2320
0
    UINT64_C(632129536),  // DECP_XP_S
2321
0
    UINT64_C(636321792),  // DECP_ZP_D
2322
0
    UINT64_C(627933184),  // DECP_ZP_H
2323
0
    UINT64_C(632127488),  // DECP_ZP_S
2324
0
    UINT64_C(78701568), // DECW_XPiI
2325
0
    UINT64_C(78693376), // DECW_ZPiI
2326
0
    UINT64_C(3573756095), // DMB
2327
0
    UINT64_C(3602842592), // DRPS
2328
0
    UINT64_C(3573756063), // DSB
2329
0
    UINT64_C(3573756479), // DSBnXS
2330
0
    UINT64_C(96468992), // DUPM_ZI
2331
0
    UINT64_C(86057984), // DUPQ_ZZI_B
2332
0
    UINT64_C(86516736), // DUPQ_ZZI_D
2333
0
    UINT64_C(86123520), // DUPQ_ZZI_H
2334
0
    UINT64_C(86254592), // DUPQ_ZZI_S
2335
0
    UINT64_C(624476160),  // DUP_ZI_B
2336
0
    UINT64_C(637059072),  // DUP_ZI_D
2337
0
    UINT64_C(628670464),  // DUP_ZI_H
2338
0
    UINT64_C(632864768),  // DUP_ZI_S
2339
0
    UINT64_C(85997568), // DUP_ZR_B
2340
0
    UINT64_C(98580480), // DUP_ZR_D
2341
0
    UINT64_C(90191872), // DUP_ZR_H
2342
0
    UINT64_C(94386176), // DUP_ZR_S
2343
0
    UINT64_C(86056960), // DUP_ZZI_B
2344
0
    UINT64_C(86515712), // DUP_ZZI_D
2345
0
    UINT64_C(86122496), // DUP_ZZI_H
2346
0
    UINT64_C(87040000), // DUP_ZZI_Q
2347
0
    UINT64_C(86253568), // DUP_ZZI_S
2348
0
    UINT64_C(1577190400), // DUPi16
2349
0
    UINT64_C(1577321472), // DUPi32
2350
0
    UINT64_C(1577583616), // DUPi64
2351
0
    UINT64_C(1577124864), // DUPi8
2352
0
    UINT64_C(1308691456), // DUPv16i8gpr
2353
0
    UINT64_C(1308689408), // DUPv16i8lane
2354
0
    UINT64_C(235146240),  // DUPv2i32gpr
2355
0
    UINT64_C(235144192),  // DUPv2i32lane
2356
0
    UINT64_C(1309150208), // DUPv2i64gpr
2357
0
    UINT64_C(1309148160), // DUPv2i64lane
2358
0
    UINT64_C(235015168),  // DUPv4i16gpr
2359
0
    UINT64_C(235013120),  // DUPv4i16lane
2360
0
    UINT64_C(1308888064), // DUPv4i32gpr
2361
0
    UINT64_C(1308886016), // DUPv4i32lane
2362
0
    UINT64_C(1308756992), // DUPv8i16gpr
2363
0
    UINT64_C(1308754944), // DUPv8i16lane
2364
0
    UINT64_C(234949632),  // DUPv8i8gpr
2365
0
    UINT64_C(234947584),  // DUPv8i8lane
2366
0
    UINT64_C(1243611136), // EONWrs
2367
0
    UINT64_C(3391094784), // EONXrs
2368
0
    UINT64_C(3456106496), // EOR3
2369
0
    UINT64_C(69220352), // EOR3_ZZZZ
2370
0
    UINT64_C(1157664768), // EORBT_ZZZ_B
2371
0
    UINT64_C(1170247680), // EORBT_ZZZ_D
2372
0
    UINT64_C(1161859072), // EORBT_ZZZ_H
2373
0
    UINT64_C(1166053376), // EORBT_ZZZ_S
2374
0
    UINT64_C(69017600), // EORQV_VPZ_B
2375
0
    UINT64_C(81600512), // EORQV_VPZ_D
2376
0
    UINT64_C(73211904), // EORQV_VPZ_H
2377
0
    UINT64_C(77406208), // EORQV_VPZ_S
2378
0
    UINT64_C(624968192),  // EORS_PPzPP
2379
0
    UINT64_C(1157665792), // EORTB_ZZZ_B
2380
0
    UINT64_C(1170248704), // EORTB_ZZZ_D
2381
0
    UINT64_C(1161860096), // EORTB_ZZZ_H
2382
0
    UINT64_C(1166054400), // EORTB_ZZZ_S
2383
0
    UINT64_C(68755456), // EORV_VPZ_B
2384
0
    UINT64_C(81338368), // EORV_VPZ_D
2385
0
    UINT64_C(72949760), // EORV_VPZ_H
2386
0
    UINT64_C(77144064), // EORV_VPZ_S
2387
0
    UINT64_C(1375731712), // EORWri
2388
0
    UINT64_C(1241513984), // EORWrs
2389
0
    UINT64_C(3523215360), // EORXri
2390
0
    UINT64_C(3388997632), // EORXrs
2391
0
    UINT64_C(620773888),  // EOR_PPzPP
2392
0
    UINT64_C(88080384), // EOR_ZI
2393
0
    UINT64_C(68747264), // EOR_ZPmZ_B
2394
0
    UINT64_C(81330176), // EOR_ZPmZ_D
2395
0
    UINT64_C(72941568), // EOR_ZPmZ_H
2396
0
    UINT64_C(77135872), // EOR_ZPmZ_S
2397
0
    UINT64_C(77606912), // EOR_ZZZ
2398
0
    UINT64_C(1847598080), // EORv16i8
2399
0
    UINT64_C(773856256),  // EORv8i8
2400
0
    UINT64_C(3600745440), // ERET
2401
0
    UINT64_C(3600747519), // ERETAA
2402
0
    UINT64_C(3600748543), // ERETAB
2403
0
    UINT64_C(90186752), // EXTQ_ZZI
2404
0
    UINT64_C(3221356544), // EXTRACT_ZPMXI_H_B
2405
0
    UINT64_C(3233939456), // EXTRACT_ZPMXI_H_D
2406
0
    UINT64_C(3225550848), // EXTRACT_ZPMXI_H_H
2407
0
    UINT64_C(3234004992), // EXTRACT_ZPMXI_H_Q
2408
0
    UINT64_C(3229745152), // EXTRACT_ZPMXI_H_S
2409
0
    UINT64_C(3221389312), // EXTRACT_ZPMXI_V_B
2410
0
    UINT64_C(3233972224), // EXTRACT_ZPMXI_V_D
2411
0
    UINT64_C(3225583616), // EXTRACT_ZPMXI_V_H
2412
0
    UINT64_C(3234037760), // EXTRACT_ZPMXI_V_Q
2413
0
    UINT64_C(3229777920), // EXTRACT_ZPMXI_V_S
2414
0
    UINT64_C(327155712),  // EXTRWrri
2415
0
    UINT64_C(2478833664), // EXTRXrri
2416
0
    UINT64_C(85983232), // EXT_ZZI
2417
0
    UINT64_C(90177536), // EXT_ZZI_B
2418
0
    UINT64_C(1845493760), // EXTv16i8
2419
0
    UINT64_C(771751936),  // EXTv8i8
2420
0
    UINT64_C(1847687168), // F1CVTL2v8f16
2421
0
    UINT64_C(1695100928), // F1CVTLT_ZZ_BtoH
2422
0
    UINT64_C(3240550401), // F1CVTL_2ZZ_BtoH_NAME
2423
0
    UINT64_C(773945344),  // F1CVTLv8f16
2424
0
    UINT64_C(3240550400), // F1CVT_2ZZ_BtoH_NAME
2425
0
    UINT64_C(1695035392), // F1CVT_ZZ_BtoH
2426
0
    UINT64_C(1851881472), // F2CVTL2v8f16
2427
0
    UINT64_C(1695101952), // F2CVTLT_ZZ_BtoH
2428
0
    UINT64_C(3248939009), // F2CVTL_2ZZ_BtoH_NAME
2429
0
    UINT64_C(778139648),  // F2CVTLv8f16
2430
0
    UINT64_C(3248939008), // F2CVT_2ZZ_BtoH_NAME
2431
0
    UINT64_C(1695036416), // F2CVT_ZZ_BtoH
2432
0
    UINT64_C(2126517248), // FABD16
2433
0
    UINT64_C(2124469248), // FABD32
2434
0
    UINT64_C(2128663552), // FABD64
2435
0
    UINT64_C(1707638784), // FABD_ZPmZ_D
2436
0
    UINT64_C(1699250176), // FABD_ZPmZ_H
2437
0
    UINT64_C(1703444480), // FABD_ZPmZ_S
2438
0
    UINT64_C(782291968),  // FABDv2f32
2439
0
    UINT64_C(1860228096), // FABDv2f64
2440
0
    UINT64_C(784339968),  // FABDv4f16
2441
0
    UINT64_C(1856033792), // FABDv4f32
2442
0
    UINT64_C(1858081792), // FABDv8f16
2443
0
    UINT64_C(509657088),  // FABSDr
2444
0
    UINT64_C(518045696),  // FABSHr
2445
0
    UINT64_C(505462784),  // FABSSr
2446
0
    UINT64_C(81567744), // FABS_ZPmZ_D
2447
0
    UINT64_C(73179136), // FABS_ZPmZ_H
2448
0
    UINT64_C(77373440), // FABS_ZPmZ_S
2449
0
    UINT64_C(245430272),  // FABSv2f32
2450
0
    UINT64_C(1323366400), // FABSv2f64
2451
0
    UINT64_C(251197440),  // FABSv4f16
2452
0
    UINT64_C(1319172096), // FABSv4f32
2453
0
    UINT64_C(1324939264), // FABSv8f16
2454
0
    UINT64_C(2118134784), // FACGE16
2455
0
    UINT64_C(2116086784), // FACGE32
2456
0
    UINT64_C(2120281088), // FACGE64
2457
0
    UINT64_C(1707130896), // FACGE_PPzZZ_D
2458
0
    UINT64_C(1698742288), // FACGE_PPzZZ_H
2459
0
    UINT64_C(1702936592), // FACGE_PPzZZ_S
2460
0
    UINT64_C(773909504),  // FACGEv2f32
2461
0
    UINT64_C(1851845632), // FACGEv2f64
2462
0
    UINT64_C(775957504),  // FACGEv4f16
2463
0
    UINT64_C(1847651328), // FACGEv4f32
2464
0
    UINT64_C(1849699328), // FACGEv8f16
2465
0
    UINT64_C(2126523392), // FACGT16
2466
0
    UINT64_C(2124475392), // FACGT32
2467
0
    UINT64_C(2128669696), // FACGT64
2468
0
    UINT64_C(1707139088), // FACGT_PPzZZ_D
2469
0
    UINT64_C(1698750480), // FACGT_PPzZZ_H
2470
0
    UINT64_C(1702944784), // FACGT_PPzZZ_S
2471
0
    UINT64_C(782298112),  // FACGTv2f32
2472
0
    UINT64_C(1860234240), // FACGTv2f64
2473
0
    UINT64_C(784346112),  // FACGTv4f16
2474
0
    UINT64_C(1856039936), // FACGTv4f32
2475
0
    UINT64_C(1858087936), // FACGTv8f16
2476
0
    UINT64_C(1708662784), // FADDA_VPZ_D
2477
0
    UINT64_C(1700274176), // FADDA_VPZ_H
2478
0
    UINT64_C(1704468480), // FADDA_VPZ_S
2479
0
    UINT64_C(509618176),  // FADDDrr
2480
0
    UINT64_C(518006784),  // FADDHrr
2481
0
    UINT64_C(1691385856), // FADDP_ZPmZZ_D
2482
0
    UINT64_C(1682997248), // FADDP_ZPmZZ_H
2483
0
    UINT64_C(1687191552), // FADDP_ZPmZZ_S
2484
0
    UINT64_C(773903360),  // FADDPv2f32
2485
0
    UINT64_C(1851839488), // FADDPv2f64
2486
0
    UINT64_C(1580259328), // FADDPv2i16p
2487
0
    UINT64_C(2117130240), // FADDPv2i32p
2488
0
    UINT64_C(2121324544), // FADDPv2i64p
2489
0
    UINT64_C(775951360),  // FADDPv4f16
2490
0
    UINT64_C(1847645184), // FADDPv4f32
2491
0
    UINT64_C(1849693184), // FADDPv8f16
2492
0
    UINT64_C(1691394048), // FADDQV_D
2493
0
    UINT64_C(1683005440), // FADDQV_H
2494
0
    UINT64_C(1687199744), // FADDQV_S
2495
0
    UINT64_C(505423872),  // FADDSrr
2496
0
    UINT64_C(1707089920), // FADDV_VPZ_D
2497
0
    UINT64_C(1698701312), // FADDV_VPZ_H
2498
0
    UINT64_C(1702895616), // FADDV_VPZ_S
2499
0
    UINT64_C(3252689920), // FADD_VG2_M2Z_D
2500
0
    UINT64_C(3248757760), // FADD_VG2_M2Z_H
2501
0
    UINT64_C(3248495616), // FADD_VG2_M2Z_S
2502
0
    UINT64_C(3252755456), // FADD_VG4_M4Z_D
2503
0
    UINT64_C(3248823296), // FADD_VG4_M4Z_H
2504
0
    UINT64_C(3248561152), // FADD_VG4_M4Z_S
2505
0
    UINT64_C(1708687360), // FADD_ZPmI_D
2506
0
    UINT64_C(1700298752), // FADD_ZPmI_H
2507
0
    UINT64_C(1704493056), // FADD_ZPmI_S
2508
0
    UINT64_C(1707114496), // FADD_ZPmZ_D
2509
0
    UINT64_C(1698725888), // FADD_ZPmZ_H
2510
0
    UINT64_C(1702920192), // FADD_ZPmZ_S
2511
0
    UINT64_C(1707081728), // FADD_ZZZ_D
2512
0
    UINT64_C(1698693120), // FADD_ZZZ_H
2513
0
    UINT64_C(1702887424), // FADD_ZZZ_S
2514
0
    UINT64_C(237032448),  // FADDv2f32
2515
0
    UINT64_C(1314968576), // FADDv2f64
2516
0
    UINT64_C(239080448),  // FADDv4f16
2517
0
    UINT64_C(1310774272), // FADDv4f32
2518
0
    UINT64_C(1312822272), // FADDv8f16
2519
0
    UINT64_C(3252728128), // FAMAX_2Z2Z_D
2520
0
    UINT64_C(3244339520), // FAMAX_2Z2Z_H
2521
0
    UINT64_C(3248533824), // FAMAX_2Z2Z_S
2522
0
    UINT64_C(3252730176), // FAMAX_4Z4Z_D
2523
0
    UINT64_C(3244341568), // FAMAX_4Z4Z_H
2524
0
    UINT64_C(3248535872), // FAMAX_4Z4Z_S
2525
0
    UINT64_C(1708032000), // FAMAX_ZPmZ_D
2526
0
    UINT64_C(1699643392), // FAMAX_ZPmZ_H
2527
0
    UINT64_C(1703837696), // FAMAX_ZPmZ_S
2528
0
    UINT64_C(245423104),  // FAMAXv2f32
2529
0
    UINT64_C(1323359232), // FAMAXv2f64
2530
0
    UINT64_C(247471104),  // FAMAXv4f16
2531
0
    UINT64_C(1319164928), // FAMAXv4f32
2532
0
    UINT64_C(1321212928), // FAMAXv8f16
2533
0
    UINT64_C(3252728129), // FAMIN_2Z2Z_D
2534
0
    UINT64_C(3244339521), // FAMIN_2Z2Z_H
2535
0
    UINT64_C(3248533825), // FAMIN_2Z2Z_S
2536
0
    UINT64_C(3252730177), // FAMIN_4Z4Z_D
2537
0
    UINT64_C(3244341569), // FAMIN_4Z4Z_H
2538
0
    UINT64_C(3248535873), // FAMIN_4Z4Z_S
2539
0
    UINT64_C(1708097536), // FAMIN_ZPmZ_D
2540
0
    UINT64_C(1699708928), // FAMIN_ZPmZ_H
2541
0
    UINT64_C(1703903232), // FAMIN_ZPmZ_S
2542
0
    UINT64_C(782294016),  // FAMINv2f32
2543
0
    UINT64_C(1860230144), // FAMINv2f64
2544
0
    UINT64_C(784342016),  // FAMINv4f16
2545
0
    UINT64_C(1856035840), // FAMINv4f32
2546
0
    UINT64_C(1858083840), // FAMINv8f16
2547
0
    UINT64_C(1690337280), // FCADD_ZPmZ_D
2548
0
    UINT64_C(1681948672), // FCADD_ZPmZ_H
2549
0
    UINT64_C(1686142976), // FCADD_ZPmZ_S
2550
0
    UINT64_C(780198912),  // FCADDv2f32
2551
0
    UINT64_C(1858135040), // FCADDv2f64
2552
0
    UINT64_C(776004608),  // FCADDv4f16
2553
0
    UINT64_C(1853940736), // FCADDv4f32
2554
0
    UINT64_C(1849746432), // FCADDv8f16
2555
0
    UINT64_C(509608960),  // FCCMPDrr
2556
0
    UINT64_C(509608976),  // FCCMPEDrr
2557
0
    UINT64_C(517997584),  // FCCMPEHrr
2558
0
    UINT64_C(505414672),  // FCCMPESrr
2559
0
    UINT64_C(517997568),  // FCCMPHrr
2560
0
    UINT64_C(505414656),  // FCCMPSrr
2561
0
    UINT64_C(3252731904), // FCLAMP_VG2_2Z2Z_D
2562
0
    UINT64_C(3244343296), // FCLAMP_VG2_2Z2Z_H
2563
0
    UINT64_C(3248537600), // FCLAMP_VG2_2Z2Z_S
2564
0
    UINT64_C(3252733952), // FCLAMP_VG4_4Z4Z_D
2565
0
    UINT64_C(3244345344), // FCLAMP_VG4_4Z4Z_H
2566
0
    UINT64_C(3248539648), // FCLAMP_VG4_4Z4Z_S
2567
0
    UINT64_C(1692410880), // FCLAMP_ZZZ_D
2568
0
    UINT64_C(1684022272), // FCLAMP_ZZZ_H
2569
0
    UINT64_C(1688216576), // FCLAMP_ZZZ_S
2570
0
    UINT64_C(1581261824), // FCMEQ16
2571
0
    UINT64_C(1579213824), // FCMEQ32
2572
0
    UINT64_C(1583408128), // FCMEQ64
2573
0
    UINT64_C(1708269568), // FCMEQ_PPzZ0_D
2574
0
    UINT64_C(1699880960), // FCMEQ_PPzZ0_H
2575
0
    UINT64_C(1704075264), // FCMEQ_PPzZ0_S
2576
0
    UINT64_C(1707106304), // FCMEQ_PPzZZ_D
2577
0
    UINT64_C(1698717696), // FCMEQ_PPzZZ_H
2578
0
    UINT64_C(1702912000), // FCMEQ_PPzZZ_S
2579
0
    UINT64_C(1593366528), // FCMEQv1i16rz
2580
0
    UINT64_C(1587599360), // FCMEQv1i32rz
2581
0
    UINT64_C(1591793664), // FCMEQv1i64rz
2582
0
    UINT64_C(237036544),  // FCMEQv2f32
2583
0
    UINT64_C(1314972672), // FCMEQv2f64
2584
0
    UINT64_C(245422080),  // FCMEQv2i32rz
2585
0
    UINT64_C(1323358208), // FCMEQv2i64rz
2586
0
    UINT64_C(239084544),  // FCMEQv4f16
2587
0
    UINT64_C(1310778368), // FCMEQv4f32
2588
0
    UINT64_C(251189248),  // FCMEQv4i16rz
2589
0
    UINT64_C(1319163904), // FCMEQv4i32rz
2590
0
    UINT64_C(1312826368), // FCMEQv8f16
2591
0
    UINT64_C(1324931072), // FCMEQv8i16rz
2592
0
    UINT64_C(2118132736), // FCMGE16
2593
0
    UINT64_C(2116084736), // FCMGE32
2594
0
    UINT64_C(2120279040), // FCMGE64
2595
0
    UINT64_C(1708138496), // FCMGE_PPzZ0_D
2596
0
    UINT64_C(1699749888), // FCMGE_PPzZ0_H
2597
0
    UINT64_C(1703944192), // FCMGE_PPzZ0_S
2598
0
    UINT64_C(1707098112), // FCMGE_PPzZZ_D
2599
0
    UINT64_C(1698709504), // FCMGE_PPzZZ_H
2600
0
    UINT64_C(1702903808), // FCMGE_PPzZZ_S
2601
0
    UINT64_C(2130233344), // FCMGEv1i16rz
2602
0
    UINT64_C(2124466176), // FCMGEv1i32rz
2603
0
    UINT64_C(2128660480), // FCMGEv1i64rz
2604
0
    UINT64_C(773907456),  // FCMGEv2f32
2605
0
    UINT64_C(1851843584), // FCMGEv2f64
2606
0
    UINT64_C(782288896),  // FCMGEv2i32rz
2607
0
    UINT64_C(1860225024), // FCMGEv2i64rz
2608
0
    UINT64_C(775955456),  // FCMGEv4f16
2609
0
    UINT64_C(1847649280), // FCMGEv4f32
2610
0
    UINT64_C(788056064),  // FCMGEv4i16rz
2611
0
    UINT64_C(1856030720), // FCMGEv4i32rz
2612
0
    UINT64_C(1849697280), // FCMGEv8f16
2613
0
    UINT64_C(1861797888), // FCMGEv8i16rz
2614
0
    UINT64_C(2126521344), // FCMGT16
2615
0
    UINT64_C(2124473344), // FCMGT32
2616
0
    UINT64_C(2128667648), // FCMGT64
2617
0
    UINT64_C(1708138512), // FCMGT_PPzZ0_D
2618
0
    UINT64_C(1699749904), // FCMGT_PPzZ0_H
2619
0
    UINT64_C(1703944208), // FCMGT_PPzZ0_S
2620
0
    UINT64_C(1707098128), // FCMGT_PPzZZ_D
2621
0
    UINT64_C(1698709520), // FCMGT_PPzZZ_H
2622
0
    UINT64_C(1702903824), // FCMGT_PPzZZ_S
2623
0
    UINT64_C(1593362432), // FCMGTv1i16rz
2624
0
    UINT64_C(1587595264), // FCMGTv1i32rz
2625
0
    UINT64_C(1591789568), // FCMGTv1i64rz
2626
0
    UINT64_C(782296064),  // FCMGTv2f32
2627
0
    UINT64_C(1860232192), // FCMGTv2f64
2628
0
    UINT64_C(245417984),  // FCMGTv2i32rz
2629
0
    UINT64_C(1323354112), // FCMGTv2i64rz
2630
0
    UINT64_C(784344064),  // FCMGTv4f16
2631
0
    UINT64_C(1856037888), // FCMGTv4f32
2632
0
    UINT64_C(251185152),  // FCMGTv4i16rz
2633
0
    UINT64_C(1319159808), // FCMGTv4i32rz
2634
0
    UINT64_C(1858085888), // FCMGTv8f16
2635
0
    UINT64_C(1324926976), // FCMGTv8i16rz
2636
0
    UINT64_C(1690304512), // FCMLA_ZPmZZ_D
2637
0
    UINT64_C(1681915904), // FCMLA_ZPmZZ_H
2638
0
    UINT64_C(1686110208), // FCMLA_ZPmZZ_S
2639
0
    UINT64_C(1688211456), // FCMLA_ZZZI_H
2640
0
    UINT64_C(1692405760), // FCMLA_ZZZI_S
2641
0
    UINT64_C(780190720),  // FCMLAv2f32
2642
0
    UINT64_C(1858126848), // FCMLAv2f64
2643
0
    UINT64_C(775996416),  // FCMLAv4f16
2644
0
    UINT64_C(792727552),  // FCMLAv4f16_indexed
2645
0
    UINT64_C(1853932544), // FCMLAv4f32
2646
0
    UINT64_C(1870663680), // FCMLAv4f32_indexed
2647
0
    UINT64_C(1849738240), // FCMLAv8f16
2648
0
    UINT64_C(1866469376), // FCMLAv8f16_indexed
2649
0
    UINT64_C(1708204048), // FCMLE_PPzZ0_D
2650
0
    UINT64_C(1699815440), // FCMLE_PPzZ0_H
2651
0
    UINT64_C(1704009744), // FCMLE_PPzZ0_S
2652
0
    UINT64_C(2130237440), // FCMLEv1i16rz
2653
0
    UINT64_C(2124470272), // FCMLEv1i32rz
2654
0
    UINT64_C(2128664576), // FCMLEv1i64rz
2655
0
    UINT64_C(782292992),  // FCMLEv2i32rz
2656
0
    UINT64_C(1860229120), // FCMLEv2i64rz
2657
0
    UINT64_C(788060160),  // FCMLEv4i16rz
2658
0
    UINT64_C(1856034816), // FCMLEv4i32rz
2659
0
    UINT64_C(1861801984), // FCMLEv8i16rz
2660
0
    UINT64_C(1708204032), // FCMLT_PPzZ0_D
2661
0
    UINT64_C(1699815424), // FCMLT_PPzZ0_H
2662
0
    UINT64_C(1704009728), // FCMLT_PPzZ0_S
2663
0
    UINT64_C(1593370624), // FCMLTv1i16rz
2664
0
    UINT64_C(1587603456), // FCMLTv1i32rz
2665
0
    UINT64_C(1591797760), // FCMLTv1i64rz
2666
0
    UINT64_C(245426176),  // FCMLTv2i32rz
2667
0
    UINT64_C(1323362304), // FCMLTv2i64rz
2668
0
    UINT64_C(251193344),  // FCMLTv4i16rz
2669
0
    UINT64_C(1319168000), // FCMLTv4i32rz
2670
0
    UINT64_C(1324935168), // FCMLTv8i16rz
2671
0
    UINT64_C(1708335104), // FCMNE_PPzZ0_D
2672
0
    UINT64_C(1699946496), // FCMNE_PPzZ0_H
2673
0
    UINT64_C(1704140800), // FCMNE_PPzZ0_S
2674
0
    UINT64_C(1707106320), // FCMNE_PPzZZ_D
2675
0
    UINT64_C(1698717712), // FCMNE_PPzZZ_H
2676
0
    UINT64_C(1702912016), // FCMNE_PPzZZ_S
2677
0
    UINT64_C(509616136),  // FCMPDri
2678
0
    UINT64_C(509616128),  // FCMPDrr
2679
0
    UINT64_C(509616152),  // FCMPEDri
2680
0
    UINT64_C(509616144),  // FCMPEDrr
2681
0
    UINT64_C(518004760),  // FCMPEHri
2682
0
    UINT64_C(518004752),  // FCMPEHrr
2683
0
    UINT64_C(505421848),  // FCMPESri
2684
0
    UINT64_C(505421840),  // FCMPESrr
2685
0
    UINT64_C(518004744),  // FCMPHri
2686
0
    UINT64_C(518004736),  // FCMPHrr
2687
0
    UINT64_C(505421832),  // FCMPSri
2688
0
    UINT64_C(505421824),  // FCMPSrr
2689
0
    UINT64_C(1707130880), // FCMUO_PPzZZ_D
2690
0
    UINT64_C(1698742272), // FCMUO_PPzZZ_H
2691
0
    UINT64_C(1702936576), // FCMUO_PPzZZ_S
2692
0
    UINT64_C(97566720), // FCPY_ZPmI_D
2693
0
    UINT64_C(89178112), // FCPY_ZPmI_H
2694
0
    UINT64_C(93372416), // FCPY_ZPmI_S
2695
0
    UINT64_C(509611008),  // FCSELDrrr
2696
0
    UINT64_C(517999616),  // FCSELHrrr
2697
0
    UINT64_C(505416704),  // FCSELSrrr
2698
0
    UINT64_C(509870080),  // FCVTASUWDr
2699
0
    UINT64_C(518258688),  // FCVTASUWHr
2700
0
    UINT64_C(505675776),  // FCVTASUWSr
2701
0
    UINT64_C(2657353728), // FCVTASUXDr
2702
0
    UINT64_C(2665742336), // FCVTASUXHr
2703
0
    UINT64_C(2653159424), // FCVTASUXSr
2704
0
    UINT64_C(1585039360), // FCVTASv1f16
2705
0
    UINT64_C(1579272192), // FCVTASv1i32
2706
0
    UINT64_C(1583466496), // FCVTASv1i64
2707
0
    UINT64_C(237094912),  // FCVTASv2f32
2708
0
    UINT64_C(1315031040), // FCVTASv2f64
2709
0
    UINT64_C(242862080),  // FCVTASv4f16
2710
0
    UINT64_C(1310836736), // FCVTASv4f32
2711
0
    UINT64_C(1316603904), // FCVTASv8f16
2712
0
    UINT64_C(509935616),  // FCVTAUUWDr
2713
0
    UINT64_C(518324224),  // FCVTAUUWHr
2714
0
    UINT64_C(505741312),  // FCVTAUUWSr
2715
0
    UINT64_C(2657419264), // FCVTAUUXDr
2716
0
    UINT64_C(2665807872), // FCVTAUUXHr
2717
0
    UINT64_C(2653224960), // FCVTAUUXSr
2718
0
    UINT64_C(2121910272), // FCVTAUv1f16
2719
0
    UINT64_C(2116143104), // FCVTAUv1i32
2720
0
    UINT64_C(2120337408), // FCVTAUv1i64
2721
0
    UINT64_C(773965824),  // FCVTAUv2f32
2722
0
    UINT64_C(1851901952), // FCVTAUv2f64
2723
0
    UINT64_C(779732992),  // FCVTAUv4f16
2724
0
    UINT64_C(1847707648), // FCVTAUv4f32
2725
0
    UINT64_C(1853474816), // FCVTAUv8f16
2726
0
    UINT64_C(518176768),  // FCVTDHr
2727
0
    UINT64_C(505593856),  // FCVTDSr
2728
0
    UINT64_C(509853696),  // FCVTHDr
2729
0
    UINT64_C(505659392),  // FCVTHSr
2730
0
    UINT64_C(1686740992), // FCVTLT_ZPmZ_HtoS
2731
0
    UINT64_C(1691066368), // FCVTLT_ZPmZ_StoD
2732
0
    UINT64_C(3248545793), // FCVTL_2ZZ_H_S
2733
0
    UINT64_C(241268736),  // FCVTLv2i32
2734
0
    UINT64_C(237074432),  // FCVTLv4i16
2735
0
    UINT64_C(1315010560), // FCVTLv4i32
2736
0
    UINT64_C(1310816256), // FCVTLv8i16
2737
0
    UINT64_C(510656512),  // FCVTMSUWDr
2738
0
    UINT64_C(519045120),  // FCVTMSUWHr
2739
0
    UINT64_C(506462208),  // FCVTMSUWSr
2740
0
    UINT64_C(2658140160), // FCVTMSUXDr
2741
0
    UINT64_C(2666528768), // FCVTMSUXHr
2742
0
    UINT64_C(2653945856), // FCVTMSUXSr
2743
0
    UINT64_C(1585035264), // FCVTMSv1f16
2744
0
    UINT64_C(1579268096), // FCVTMSv1i32
2745
0
    UINT64_C(1583462400), // FCVTMSv1i64
2746
0
    UINT64_C(237090816),  // FCVTMSv2f32
2747
0
    UINT64_C(1315026944), // FCVTMSv2f64
2748
0
    UINT64_C(242857984),  // FCVTMSv4f16
2749
0
    UINT64_C(1310832640), // FCVTMSv4f32
2750
0
    UINT64_C(1316599808), // FCVTMSv8f16
2751
0
    UINT64_C(510722048),  // FCVTMUUWDr
2752
0
    UINT64_C(519110656),  // FCVTMUUWHr
2753
0
    UINT64_C(506527744),  // FCVTMUUWSr
2754
0
    UINT64_C(2658205696), // FCVTMUUXDr
2755
0
    UINT64_C(2666594304), // FCVTMUUXHr
2756
0
    UINT64_C(2654011392), // FCVTMUUXSr
2757
0
    UINT64_C(2121906176), // FCVTMUv1f16
2758
0
    UINT64_C(2116139008), // FCVTMUv1i32
2759
0
    UINT64_C(2120333312), // FCVTMUv1i64
2760
0
    UINT64_C(773961728),  // FCVTMUv2f32
2761
0
    UINT64_C(1851897856), // FCVTMUv2f64
2762
0
    UINT64_C(779728896),  // FCVTMUv4f16
2763
0
    UINT64_C(1847703552), // FCVTMUv4f32
2764
0
    UINT64_C(1853470720), // FCVTMUv8f16
2765
0
    UINT64_C(1695167488), // FCVTNB_Z2Z_StoB
2766
0
    UINT64_C(509607936),  // FCVTNSUWDr
2767
0
    UINT64_C(517996544),  // FCVTNSUWHr
2768
0
    UINT64_C(505413632),  // FCVTNSUWSr
2769
0
    UINT64_C(2657091584), // FCVTNSUXDr
2770
0
    UINT64_C(2665480192), // FCVTNSUXHr
2771
0
    UINT64_C(2652897280), // FCVTNSUXSr
2772
0
    UINT64_C(1585031168), // FCVTNSv1f16
2773
0
    UINT64_C(1579264000), // FCVTNSv1i32
2774
0
    UINT64_C(1583458304), // FCVTNSv1i64
2775
0
    UINT64_C(237086720),  // FCVTNSv2f32
2776
0
    UINT64_C(1315022848), // FCVTNSv2f64
2777
0
    UINT64_C(242853888),  // FCVTNSv4f16
2778
0
    UINT64_C(1310828544), // FCVTNSv4f32
2779
0
    UINT64_C(1316595712), // FCVTNSv8f16
2780
0
    UINT64_C(1695169536), // FCVTNT_Z2Z_StoB
2781
0
    UINT64_C(1691000832), // FCVTNT_ZPmZ_DtoS
2782
0
    UINT64_C(1686675456), // FCVTNT_ZPmZ_StoH
2783
0
    UINT64_C(509673472),  // FCVTNUUWDr
2784
0
    UINT64_C(518062080),  // FCVTNUUWHr
2785
0
    UINT64_C(505479168),  // FCVTNUUWSr
2786
0
    UINT64_C(2657157120), // FCVTNUUXDr
2787
0
    UINT64_C(2665545728), // FCVTNUUXHr
2788
0
    UINT64_C(2652962816), // FCVTNUUXSr
2789
0
    UINT64_C(2121902080), // FCVTNUv1f16
2790
0
    UINT64_C(2116134912), // FCVTNUv1i32
2791
0
    UINT64_C(2120329216), // FCVTNUv1i64
2792
0
    UINT64_C(773957632),  // FCVTNUv2f32
2793
0
    UINT64_C(1851893760), // FCVTNUv2f64
2794
0
    UINT64_C(779724800),  // FCVTNUv4f16
2795
0
    UINT64_C(1847699456), // FCVTNUv4f32
2796
0
    UINT64_C(1853466624), // FCVTNUv8f16
2797
0
    UINT64_C(1312879616), // FCVTN_F16_F8v16f8
2798
0
    UINT64_C(239137792),  // FCVTN_F16_F8v8f8
2799
0
    UINT64_C(1308685312), // FCVTN_F32_F82v16f8
2800
0
    UINT64_C(234943488),  // FCVTN_F32_F8v8f8
2801
0
    UINT64_C(1695166464), // FCVTN_Z2Z_HtoB
2802
0
    UINT64_C(3240157216), // FCVTN_Z2Z_StoH
2803
0
    UINT64_C(3241467936), // FCVTN_Z4Z_StoB_NAME
2804
0
    UINT64_C(241264640),  // FCVTNv2i32
2805
0
    UINT64_C(237070336),  // FCVTNv4i16
2806
0
    UINT64_C(1315006464), // FCVTNv4i32
2807
0
    UINT64_C(1310812160), // FCVTNv8i16
2808
0
    UINT64_C(510132224),  // FCVTPSUWDr
2809
0
    UINT64_C(518520832),  // FCVTPSUWHr
2810
0
    UINT64_C(505937920),  // FCVTPSUWSr
2811
0
    UINT64_C(2657615872), // FCVTPSUXDr
2812
0
    UINT64_C(2666004480), // FCVTPSUXHr
2813
0
    UINT64_C(2653421568), // FCVTPSUXSr
2814
0
    UINT64_C(1593419776), // FCVTPSv1f16
2815
0
    UINT64_C(1587652608), // FCVTPSv1i32
2816
0
    UINT64_C(1591846912), // FCVTPSv1i64
2817
0
    UINT64_C(245475328),  // FCVTPSv2f32
2818
0
    UINT64_C(1323411456), // FCVTPSv2f64
2819
0
    UINT64_C(251242496),  // FCVTPSv4f16
2820
0
    UINT64_C(1319217152), // FCVTPSv4f32
2821
0
    UINT64_C(1324984320), // FCVTPSv8f16
2822
0
    UINT64_C(510197760),  // FCVTPUUWDr
2823
0
    UINT64_C(518586368),  // FCVTPUUWHr
2824
0
    UINT64_C(506003456),  // FCVTPUUWSr
2825
0
    UINT64_C(2657681408), // FCVTPUUXDr
2826
0
    UINT64_C(2666070016), // FCVTPUUXHr
2827
0
    UINT64_C(2653487104), // FCVTPUUXSr
2828
0
    UINT64_C(2130290688), // FCVTPUv1f16
2829
0
    UINT64_C(2124523520), // FCVTPUv1i32
2830
0
    UINT64_C(2128717824), // FCVTPUv1i64
2831
0
    UINT64_C(782346240),  // FCVTPUv2f32
2832
0
    UINT64_C(1860282368), // FCVTPUv2f64
2833
0
    UINT64_C(788113408),  // FCVTPUv4f16
2834
0
    UINT64_C(1856088064), // FCVTPUv4f32
2835
0
    UINT64_C(1861855232), // FCVTPUv8f16
2836
0
    UINT64_C(509755392),  // FCVTSDr
2837
0
    UINT64_C(518144000),  // FCVTSHr
2838
0
    UINT64_C(1678417920), // FCVTXNT_ZPmZ_DtoS
2839
0
    UINT64_C(2120312832), // FCVTXNv1i64
2840
0
    UINT64_C(778135552),  // FCVTXNv2f32
2841
0
    UINT64_C(1851877376), // FCVTXNv4f32
2842
0
    UINT64_C(1695195136), // FCVTX_ZPmZ_DtoS
2843
0
    UINT64_C(509116416),  // FCVTZSSWDri
2844
0
    UINT64_C(517505024),  // FCVTZSSWHri
2845
0
    UINT64_C(504922112),  // FCVTZSSWSri
2846
0
    UINT64_C(2656567296), // FCVTZSSXDri
2847
0
    UINT64_C(2664955904), // FCVTZSSXHri
2848
0
    UINT64_C(2652372992), // FCVTZSSXSri
2849
0
    UINT64_C(511180800),  // FCVTZSUWDr
2850
0
    UINT64_C(519569408),  // FCVTZSUWHr
2851
0
    UINT64_C(506986496),  // FCVTZSUWSr
2852
0
    UINT64_C(2658664448), // FCVTZSUXDr
2853
0
    UINT64_C(2667053056), // FCVTZSUXHr
2854
0
    UINT64_C(2654470144), // FCVTZSUXSr
2855
0
    UINT64_C(3240222720), // FCVTZS_2Z2Z_StoS
2856
0
    UINT64_C(3241271296), // FCVTZS_4Z4Z_StoS
2857
0
    UINT64_C(1709088768), // FCVTZS_ZPmZ_DtoD
2858
0
    UINT64_C(1708695552), // FCVTZS_ZPmZ_DtoS
2859
0
    UINT64_C(1700700160), // FCVTZS_ZPmZ_HtoD
2860
0
    UINT64_C(1700438016), // FCVTZS_ZPmZ_HtoH
2861
0
    UINT64_C(1700569088), // FCVTZS_ZPmZ_HtoS
2862
0
    UINT64_C(1708957696), // FCVTZS_ZPmZ_StoD
2863
0
    UINT64_C(1704763392), // FCVTZS_ZPmZ_StoS
2864
0
    UINT64_C(1598094336), // FCVTZSd
2865
0
    UINT64_C(1594948608), // FCVTZSh
2866
0
    UINT64_C(1595997184), // FCVTZSs
2867
0
    UINT64_C(1593423872), // FCVTZSv1f16
2868
0
    UINT64_C(1587656704), // FCVTZSv1i32
2869
0
    UINT64_C(1591851008), // FCVTZSv1i64
2870
0
    UINT64_C(245479424),  // FCVTZSv2f32
2871
0
    UINT64_C(1323415552), // FCVTZSv2f64
2872
0
    UINT64_C(253819904),  // FCVTZSv2i32_shift
2873
0
    UINT64_C(1329658880), // FCVTZSv2i64_shift
2874
0
    UINT64_C(251246592),  // FCVTZSv4f16
2875
0
    UINT64_C(1319221248), // FCVTZSv4f32
2876
0
    UINT64_C(252771328),  // FCVTZSv4i16_shift
2877
0
    UINT64_C(1327561728), // FCVTZSv4i32_shift
2878
0
    UINT64_C(1324988416), // FCVTZSv8f16
2879
0
    UINT64_C(1326513152), // FCVTZSv8i16_shift
2880
0
    UINT64_C(509181952),  // FCVTZUSWDri
2881
0
    UINT64_C(517570560),  // FCVTZUSWHri
2882
0
    UINT64_C(504987648),  // FCVTZUSWSri
2883
0
    UINT64_C(2656632832), // FCVTZUSXDri
2884
0
    UINT64_C(2665021440), // FCVTZUSXHri
2885
0
    UINT64_C(2652438528), // FCVTZUSXSri
2886
0
    UINT64_C(511246336),  // FCVTZUUWDr
2887
0
    UINT64_C(519634944),  // FCVTZUUWHr
2888
0
    UINT64_C(507052032),  // FCVTZUUWSr
2889
0
    UINT64_C(2658729984), // FCVTZUUXDr
2890
0
    UINT64_C(2667118592), // FCVTZUUXHr
2891
0
    UINT64_C(2654535680), // FCVTZUUXSr
2892
0
    UINT64_C(3240222752), // FCVTZU_2Z2Z_StoS
2893
0
    UINT64_C(3241271328), // FCVTZU_4Z4Z_StoS
2894
0
    UINT64_C(1709154304), // FCVTZU_ZPmZ_DtoD
2895
0
    UINT64_C(1708761088), // FCVTZU_ZPmZ_DtoS
2896
0
    UINT64_C(1700765696), // FCVTZU_ZPmZ_HtoD
2897
0
    UINT64_C(1700503552), // FCVTZU_ZPmZ_HtoH
2898
0
    UINT64_C(1700634624), // FCVTZU_ZPmZ_HtoS
2899
0
    UINT64_C(1709023232), // FCVTZU_ZPmZ_StoD
2900
0
    UINT64_C(1704828928), // FCVTZU_ZPmZ_StoS
2901
0
    UINT64_C(2134965248), // FCVTZUd
2902
0
    UINT64_C(2131819520), // FCVTZUh
2903
0
    UINT64_C(2132868096), // FCVTZUs
2904
0
    UINT64_C(2130294784), // FCVTZUv1f16
2905
0
    UINT64_C(2124527616), // FCVTZUv1i32
2906
0
    UINT64_C(2128721920), // FCVTZUv1i64
2907
0
    UINT64_C(782350336),  // FCVTZUv2f32
2908
0
    UINT64_C(1860286464), // FCVTZUv2f64
2909
0
    UINT64_C(790690816),  // FCVTZUv2i32_shift
2910
0
    UINT64_C(1866529792), // FCVTZUv2i64_shift
2911
0
    UINT64_C(788117504),  // FCVTZUv4f16
2912
0
    UINT64_C(1856092160), // FCVTZUv4f32
2913
0
    UINT64_C(789642240),  // FCVTZUv4i16_shift
2914
0
    UINT64_C(1864432640), // FCVTZUv4i32_shift
2915
0
    UINT64_C(1861859328), // FCVTZUv8f16
2916
0
    UINT64_C(1863384064), // FCVTZUv8i16_shift
2917
0
    UINT64_C(3248545792), // FCVT_2ZZ_H_S
2918
0
    UINT64_C(3240419328), // FCVT_Z2Z_HtoB
2919
0
    UINT64_C(3240157184), // FCVT_Z2Z_StoH
2920
0
    UINT64_C(3241467904), // FCVT_Z4Z_StoB_NAME
2921
0
    UINT64_C(1707646976), // FCVT_ZPmZ_DtoH
2922
0
    UINT64_C(1707778048), // FCVT_ZPmZ_DtoS
2923
0
    UINT64_C(1707712512), // FCVT_ZPmZ_HtoD
2924
0
    UINT64_C(1703518208), // FCVT_ZPmZ_HtoS
2925
0
    UINT64_C(1707843584), // FCVT_ZPmZ_StoD
2926
0
    UINT64_C(1703452672), // FCVT_ZPmZ_StoH
2927
0
    UINT64_C(509614080),  // FDIVDrr
2928
0
    UINT64_C(518002688),  // FDIVHrr
2929
0
    UINT64_C(1707900928), // FDIVR_ZPmZ_D
2930
0
    UINT64_C(1699512320), // FDIVR_ZPmZ_H
2931
0
    UINT64_C(1703706624), // FDIVR_ZPmZ_S
2932
0
    UINT64_C(505419776),  // FDIVSrr
2933
0
    UINT64_C(1707966464), // FDIV_ZPmZ_D
2934
0
    UINT64_C(1699577856), // FDIV_ZPmZ_H
2935
0
    UINT64_C(1703772160), // FDIV_ZPmZ_S
2936
0
    UINT64_C(773913600),  // FDIVv2f32
2937
0
    UINT64_C(1851849728), // FDIVv2f64
2938
0
    UINT64_C(775961600),  // FDIVv4f16
2939
0
    UINT64_C(1847655424), // FDIVv4f32
2940
0
    UINT64_C(1849703424), // FDIVv8f16
2941
0
    UINT64_C(3248492576), // FDOT_VG2_M2Z2Z_BtoH
2942
0
    UINT64_C(3248492592), // FDOT_VG2_M2Z2Z_BtoS
2943
0
    UINT64_C(3248492544), // FDOT_VG2_M2Z2Z_HtoS
2944
0
    UINT64_C(3251634208), // FDOT_VG2_M2ZZI_BtoH
2945
0
    UINT64_C(3243245624), // FDOT_VG2_M2ZZI_BtoS
2946
0
    UINT64_C(3243249672), // FDOT_VG2_M2ZZI_HtoS
2947
0
    UINT64_C(3240103944), // FDOT_VG2_M2ZZ_BtoH
2948
0
    UINT64_C(3240103960), // FDOT_VG2_M2ZZ_BtoS
2949
0
    UINT64_C(3240103936), // FDOT_VG2_M2ZZ_HtoS
2950
0
    UINT64_C(3248558112), // FDOT_VG4_M4Z4Z_BtoH
2951
0
    UINT64_C(3248558128), // FDOT_VG4_M4Z4Z_BtoS
2952
0
    UINT64_C(3248558080), // FDOT_VG4_M4Z4Z_HtoS
2953
0
    UINT64_C(3239088192), // FDOT_VG4_M4ZZI_BtoH
2954
0
    UINT64_C(3243278344), // FDOT_VG4_M4ZZI_BtoS
2955
0
    UINT64_C(3243282440), // FDOT_VG4_M4ZZI_HtoS
2956
0
    UINT64_C(3241152520), // FDOT_VG4_M4ZZ_BtoH
2957
0
    UINT64_C(3241152536), // FDOT_VG4_M4ZZ_BtoS
2958
0
    UINT64_C(3241152512), // FDOT_VG4_M4ZZ_HtoS
2959
0
    UINT64_C(1679836160), // FDOT_ZZZI_BtoH
2960
0
    UINT64_C(1684030464), // FDOT_ZZZI_BtoS
2961
0
    UINT64_C(1679835136), // FDOT_ZZZI_S
2962
0
    UINT64_C(1679852544), // FDOT_ZZZ_BtoH
2963
0
    UINT64_C(1684046848), // FDOT_ZZZ_BtoS
2964
0
    UINT64_C(1679851520), // FDOT_ZZZ_S
2965
0
    UINT64_C(1325400064), // FDOTlanev16f8
2966
0
    UINT64_C(255852544),  // FDOTlanev4f16
2967
0
    UINT64_C(1329594368), // FDOTlanev8f16
2968
0
    UINT64_C(251658240),  // FDOTlanev8f8
2969
0
    UINT64_C(234945536),  // FDOTv2f32
2970
0
    UINT64_C(239139840),  // FDOTv4f16
2971
0
    UINT64_C(1308687360), // FDOTv4f32
2972
0
    UINT64_C(1312881664), // FDOTv8f16
2973
0
    UINT64_C(637124608),  // FDUP_ZI_D
2974
0
    UINT64_C(628736000),  // FDUP_ZI_H
2975
0
    UINT64_C(632930304),  // FDUP_ZI_S
2976
0
    UINT64_C(81836032), // FEXPA_ZZ_D
2977
0
    UINT64_C(73447424), // FEXPA_ZZ_H
2978
0
    UINT64_C(77641728), // FEXPA_ZZ_S
2979
0
    UINT64_C(511574016),  // FJCVTZS
2980
0
    UINT64_C(1696505856), // FLOGB_ZPmZ_D
2981
0
    UINT64_C(1696243712), // FLOGB_ZPmZ_H
2982
0
    UINT64_C(1696374784), // FLOGB_ZPmZ_S
2983
0
    UINT64_C(524288000),  // FMADDDrrr
2984
0
    UINT64_C(532676608),  // FMADDHrrr
2985
0
    UINT64_C(520093696),  // FMADDSrrr
2986
0
    UINT64_C(1709211648), // FMAD_ZPmZZ_D
2987
0
    UINT64_C(1700823040), // FMAD_ZPmZZ_H
2988
0
    UINT64_C(1705017344), // FMAD_ZPmZZ_S
2989
0
    UINT64_C(509626368),  // FMAXDrr
2990
0
    UINT64_C(518014976),  // FMAXHrr
2991
0
    UINT64_C(509634560),  // FMAXNMDrr
2992
0
    UINT64_C(518023168),  // FMAXNMHrr
2993
0
    UINT64_C(1691648000), // FMAXNMP_ZPmZZ_D
2994
0
    UINT64_C(1683259392), // FMAXNMP_ZPmZZ_H
2995
0
    UINT64_C(1687453696), // FMAXNMP_ZPmZZ_S
2996
0
    UINT64_C(773899264),  // FMAXNMPv2f32
2997
0
    UINT64_C(1851835392), // FMAXNMPv2f64
2998
0
    UINT64_C(1580255232), // FMAXNMPv2i16p
2999
0
    UINT64_C(2117126144), // FMAXNMPv2i32p
3000
0
    UINT64_C(2121320448), // FMAXNMPv2i64p
3001
0
    UINT64_C(775947264),  // FMAXNMPv4f16
3002
0
    UINT64_C(1847641088), // FMAXNMPv4f32
3003
0
    UINT64_C(1849689088), // FMAXNMPv8f16
3004
0
    UINT64_C(1691656192), // FMAXNMQV_D
3005
0
    UINT64_C(1683267584), // FMAXNMQV_H
3006
0
    UINT64_C(1687461888), // FMAXNMQV_S
3007
0
    UINT64_C(505440256),  // FMAXNMSrr
3008
0
    UINT64_C(1707352064), // FMAXNMV_VPZ_D
3009
0
    UINT64_C(1698963456), // FMAXNMV_VPZ_H
3010
0
    UINT64_C(1703157760), // FMAXNMV_VPZ_S
3011
0
    UINT64_C(238077952),  // FMAXNMVv4i16v
3012
0
    UINT64_C(1848690688), // FMAXNMVv4i32v
3013
0
    UINT64_C(1311819776), // FMAXNMVv8i16v
3014
0
    UINT64_C(3252728096), // FMAXNM_VG2_2Z2Z_D
3015
0
    UINT64_C(3244339488), // FMAXNM_VG2_2Z2Z_H
3016
0
    UINT64_C(3248533792), // FMAXNM_VG2_2Z2Z_S
3017
0
    UINT64_C(3252724000), // FMAXNM_VG2_2ZZ_D
3018
0
    UINT64_C(3244335392), // FMAXNM_VG2_2ZZ_H
3019
0
    UINT64_C(3248529696), // FMAXNM_VG2_2ZZ_S
3020
0
    UINT64_C(3252730144), // FMAXNM_VG4_4Z4Z_D
3021
0
    UINT64_C(3244341536), // FMAXNM_VG4_4Z4Z_H
3022
0
    UINT64_C(3248535840), // FMAXNM_VG4_4Z4Z_S
3023
0
    UINT64_C(3252726048), // FMAXNM_VG4_4ZZ_D
3024
0
    UINT64_C(3244337440), // FMAXNM_VG4_4ZZ_H
3025
0
    UINT64_C(3248531744), // FMAXNM_VG4_4ZZ_S
3026
0
    UINT64_C(1708949504), // FMAXNM_ZPmI_D
3027
0
    UINT64_C(1700560896), // FMAXNM_ZPmI_H
3028
0
    UINT64_C(1704755200), // FMAXNM_ZPmI_S
3029
0
    UINT64_C(1707376640), // FMAXNM_ZPmZ_D
3030
0
    UINT64_C(1698988032), // FMAXNM_ZPmZ_H
3031
0
    UINT64_C(1703182336), // FMAXNM_ZPmZ_S
3032
0
    UINT64_C(237028352),  // FMAXNMv2f32
3033
0
    UINT64_C(1314964480), // FMAXNMv2f64
3034
0
    UINT64_C(239076352),  // FMAXNMv4f16
3035
0
    UINT64_C(1310770176), // FMAXNMv4f32
3036
0
    UINT64_C(1312818176), // FMAXNMv8f16
3037
0
    UINT64_C(1691779072), // FMAXP_ZPmZZ_D
3038
0
    UINT64_C(1683390464), // FMAXP_ZPmZZ_H
3039
0
    UINT64_C(1687584768), // FMAXP_ZPmZZ_S
3040
0
    UINT64_C(773911552),  // FMAXPv2f32
3041
0
    UINT64_C(1851847680), // FMAXPv2f64
3042
0
    UINT64_C(1580267520), // FMAXPv2i16p
3043
0
    UINT64_C(2117138432), // FMAXPv2i32p
3044
0
    UINT64_C(2121332736), // FMAXPv2i64p
3045
0
    UINT64_C(775959552),  // FMAXPv4f16
3046
0
    UINT64_C(1847653376), // FMAXPv4f32
3047
0
    UINT64_C(1849701376), // FMAXPv8f16
3048
0
    UINT64_C(1691787264), // FMAXQV_D
3049
0
    UINT64_C(1683398656), // FMAXQV_H
3050
0
    UINT64_C(1687592960), // FMAXQV_S
3051
0
    UINT64_C(505432064),  // FMAXSrr
3052
0
    UINT64_C(1707483136), // FMAXV_VPZ_D
3053
0
    UINT64_C(1699094528), // FMAXV_VPZ_H
3054
0
    UINT64_C(1703288832), // FMAXV_VPZ_S
3055
0
    UINT64_C(238090240),  // FMAXVv4i16v
3056
0
    UINT64_C(1848702976), // FMAXVv4i32v
3057
0
    UINT64_C(1311832064), // FMAXVv8i16v
3058
0
    UINT64_C(3252728064), // FMAX_VG2_2Z2Z_D
3059
0
    UINT64_C(3244339456), // FMAX_VG2_2Z2Z_H
3060
0
    UINT64_C(3248533760), // FMAX_VG2_2Z2Z_S
3061
0
    UINT64_C(3252723968), // FMAX_VG2_2ZZ_D
3062
0
    UINT64_C(3244335360), // FMAX_VG2_2ZZ_H
3063
0
    UINT64_C(3248529664), // FMAX_VG2_2ZZ_S
3064
0
    UINT64_C(3252730112), // FMAX_VG4_4Z4Z_D
3065
0
    UINT64_C(3244341504), // FMAX_VG4_4Z4Z_H
3066
0
    UINT64_C(3248535808), // FMAX_VG4_4Z4Z_S
3067
0
    UINT64_C(3252726016), // FMAX_VG4_4ZZ_D
3068
0
    UINT64_C(3244337408), // FMAX_VG4_4ZZ_H
3069
0
    UINT64_C(3248531712), // FMAX_VG4_4ZZ_S
3070
0
    UINT64_C(1709080576), // FMAX_ZPmI_D
3071
0
    UINT64_C(1700691968), // FMAX_ZPmI_H
3072
0
    UINT64_C(1704886272), // FMAX_ZPmI_S
3073
0
    UINT64_C(1707507712), // FMAX_ZPmZ_D
3074
0
    UINT64_C(1699119104), // FMAX_ZPmZ_H
3075
0
    UINT64_C(1703313408), // FMAX_ZPmZ_S
3076
0
    UINT64_C(237040640),  // FMAXv2f32
3077
0
    UINT64_C(1314976768), // FMAXv2f64
3078
0
    UINT64_C(239088640),  // FMAXv4f16
3079
0
    UINT64_C(1310782464), // FMAXv4f32
3080
0
    UINT64_C(1312830464), // FMAXv8f16
3081
0
    UINT64_C(509630464),  // FMINDrr
3082
0
    UINT64_C(518019072),  // FMINHrr
3083
0
    UINT64_C(509638656),  // FMINNMDrr
3084
0
    UINT64_C(518027264),  // FMINNMHrr
3085
0
    UINT64_C(1691713536), // FMINNMP_ZPmZZ_D
3086
0
    UINT64_C(1683324928), // FMINNMP_ZPmZZ_H
3087
0
    UINT64_C(1687519232), // FMINNMP_ZPmZZ_S
3088
0
    UINT64_C(782287872),  // FMINNMPv2f32
3089
0
    UINT64_C(1860224000), // FMINNMPv2f64
3090
0
    UINT64_C(1588643840), // FMINNMPv2i16p
3091
0
    UINT64_C(2125514752), // FMINNMPv2i32p
3092
0
    UINT64_C(2129709056), // FMINNMPv2i64p
3093
0
    UINT64_C(784335872),  // FMINNMPv4f16
3094
0
    UINT64_C(1856029696), // FMINNMPv4f32
3095
0
    UINT64_C(1858077696), // FMINNMPv8f16
3096
0
    UINT64_C(1691721728), // FMINNMQV_D
3097
0
    UINT64_C(1683333120), // FMINNMQV_H
3098
0
    UINT64_C(1687527424), // FMINNMQV_S
3099
0
    UINT64_C(505444352),  // FMINNMSrr
3100
0
    UINT64_C(1707417600), // FMINNMV_VPZ_D
3101
0
    UINT64_C(1699028992), // FMINNMV_VPZ_H
3102
0
    UINT64_C(1703223296), // FMINNMV_VPZ_S
3103
0
    UINT64_C(246466560),  // FMINNMVv4i16v
3104
0
    UINT64_C(1857079296), // FMINNMVv4i32v
3105
0
    UINT64_C(1320208384), // FMINNMVv8i16v
3106
0
    UINT64_C(3252728097), // FMINNM_VG2_2Z2Z_D
3107
0
    UINT64_C(3244339489), // FMINNM_VG2_2Z2Z_H
3108
0
    UINT64_C(3248533793), // FMINNM_VG2_2Z2Z_S
3109
0
    UINT64_C(3252724001), // FMINNM_VG2_2ZZ_D
3110
0
    UINT64_C(3244335393), // FMINNM_VG2_2ZZ_H
3111
0
    UINT64_C(3248529697), // FMINNM_VG2_2ZZ_S
3112
0
    UINT64_C(3252730145), // FMINNM_VG4_4Z4Z_D
3113
0
    UINT64_C(3244341537), // FMINNM_VG4_4Z4Z_H
3114
0
    UINT64_C(3248535841), // FMINNM_VG4_4Z4Z_S
3115
0
    UINT64_C(3252726049), // FMINNM_VG4_4ZZ_D
3116
0
    UINT64_C(3244337441), // FMINNM_VG4_4ZZ_H
3117
0
    UINT64_C(3248531745), // FMINNM_VG4_4ZZ_S
3118
0
    UINT64_C(1709015040), // FMINNM_ZPmI_D
3119
0
    UINT64_C(1700626432), // FMINNM_ZPmI_H
3120
0
    UINT64_C(1704820736), // FMINNM_ZPmI_S
3121
0
    UINT64_C(1707442176), // FMINNM_ZPmZ_D
3122
0
    UINT64_C(1699053568), // FMINNM_ZPmZ_H
3123
0
    UINT64_C(1703247872), // FMINNM_ZPmZ_S
3124
0
    UINT64_C(245416960),  // FMINNMv2f32
3125
0
    UINT64_C(1323353088), // FMINNMv2f64
3126
0
    UINT64_C(247464960),  // FMINNMv4f16
3127
0
    UINT64_C(1319158784), // FMINNMv4f32
3128
0
    UINT64_C(1321206784), // FMINNMv8f16
3129
0
    UINT64_C(1691844608), // FMINP_ZPmZZ_D
3130
0
    UINT64_C(1683456000), // FMINP_ZPmZZ_H
3131
0
    UINT64_C(1687650304), // FMINP_ZPmZZ_S
3132
0
    UINT64_C(782300160),  // FMINPv2f32
3133
0
    UINT64_C(1860236288), // FMINPv2f64
3134
0
    UINT64_C(1588656128), // FMINPv2i16p
3135
0
    UINT64_C(2125527040), // FMINPv2i32p
3136
0
    UINT64_C(2129721344), // FMINPv2i64p
3137
0
    UINT64_C(784348160),  // FMINPv4f16
3138
0
    UINT64_C(1856041984), // FMINPv4f32
3139
0
    UINT64_C(1858089984), // FMINPv8f16
3140
0
    UINT64_C(1691852800), // FMINQV_D
3141
0
    UINT64_C(1683464192), // FMINQV_H
3142
0
    UINT64_C(1687658496), // FMINQV_S
3143
0
    UINT64_C(505436160),  // FMINSrr
3144
0
    UINT64_C(1707548672), // FMINV_VPZ_D
3145
0
    UINT64_C(1699160064), // FMINV_VPZ_H
3146
0
    UINT64_C(1703354368), // FMINV_VPZ_S
3147
0
    UINT64_C(246478848),  // FMINVv4i16v
3148
0
    UINT64_C(1857091584), // FMINVv4i32v
3149
0
    UINT64_C(1320220672), // FMINVv8i16v
3150
0
    UINT64_C(3252728065), // FMIN_VG2_2Z2Z_D
3151
0
    UINT64_C(3244339457), // FMIN_VG2_2Z2Z_H
3152
0
    UINT64_C(3248533761), // FMIN_VG2_2Z2Z_S
3153
0
    UINT64_C(3252723969), // FMIN_VG2_2ZZ_D
3154
0
    UINT64_C(3244335361), // FMIN_VG2_2ZZ_H
3155
0
    UINT64_C(3248529665), // FMIN_VG2_2ZZ_S
3156
0
    UINT64_C(3252730113), // FMIN_VG4_4Z4Z_D
3157
0
    UINT64_C(3244341505), // FMIN_VG4_4Z4Z_H
3158
0
    UINT64_C(3248535809), // FMIN_VG4_4Z4Z_S
3159
0
    UINT64_C(3252726017), // FMIN_VG4_4ZZ_D
3160
0
    UINT64_C(3244337409), // FMIN_VG4_4ZZ_H
3161
0
    UINT64_C(3248531713), // FMIN_VG4_4ZZ_S
3162
0
    UINT64_C(1709146112), // FMIN_ZPmI_D
3163
0
    UINT64_C(1700757504), // FMIN_ZPmI_H
3164
0
    UINT64_C(1704951808), // FMIN_ZPmI_S
3165
0
    UINT64_C(1707573248), // FMIN_ZPmZ_D
3166
0
    UINT64_C(1699184640), // FMIN_ZPmZ_H
3167
0
    UINT64_C(1703378944), // FMIN_ZPmZ_S
3168
0
    UINT64_C(245429248),  // FMINv2f32
3169
0
    UINT64_C(1323365376), // FMINv2f64
3170
0
    UINT64_C(247477248),  // FMINv4f16
3171
0
    UINT64_C(1319171072), // FMINv4f32
3172
0
    UINT64_C(1321219072), // FMINv8f16
3173
0
    UINT64_C(796950528),  // FMLAL2lanev4f16
3174
0
    UINT64_C(1870692352), // FMLAL2lanev8f16
3175
0
    UINT64_C(773901312),  // FMLAL2v4f16
3176
0
    UINT64_C(1847643136), // FMLAL2v8f16
3177
0
    UINT64_C(1688242176), // FMLALB_ZZZ
3178
0
    UINT64_C(1679839232), // FMLALB_ZZZI
3179
0
    UINT64_C(1688223744), // FMLALB_ZZZI_SHH
3180
0
    UINT64_C(1688240128), // FMLALB_ZZZ_SHH
3181
0
    UINT64_C(264241152),  // FMLALBlanev8f16
3182
0
    UINT64_C(247528448),  // FMLALBv8f16
3183
0
    UINT64_C(1679853568), // FMLALLBB_ZZZ
3184
0
    UINT64_C(1679867904), // FMLALLBB_ZZZI
3185
0
    UINT64_C(788561920),  // FMLALLBBlanev4f32
3186
0
    UINT64_C(234931200),  // FMLALLBBv4f32
3187
0
    UINT64_C(1679857664), // FMLALLBT_ZZZ
3188
0
    UINT64_C(1684062208), // FMLALLBT_ZZZI
3189
0
    UINT64_C(792756224),  // FMLALLBTlanev4f32
3190
0
    UINT64_C(239125504),  // FMLALLBTv4f32
3191
0
    UINT64_C(1679861760), // FMLALLTB_ZZZ
3192
0
    UINT64_C(1688256512), // FMLALLTB_ZZZI
3193
0
    UINT64_C(1862303744), // FMLALLTBlanev4f32
3194
0
    UINT64_C(1308673024), // FMLALLTBv4f32
3195
0
    UINT64_C(1679865856), // FMLALLTT_ZZZ
3196
0
    UINT64_C(1692450816), // FMLALLTT_ZZZI
3197
0
    UINT64_C(1866498048), // FMLALLTTlanev4f32
3198
0
    UINT64_C(1312867328), // FMLALLTTv4f32
3199
0
    UINT64_C(3242196992), // FMLALL_MZZI_BtoS
3200
0
    UINT64_C(3241149440), // FMLALL_MZZ_BtoS
3201
0
    UINT64_C(3248488480), // FMLALL_VG2_M2Z2Z_BtoS
3202
0
    UINT64_C(3247439904), // FMLALL_VG2_M2ZZI_BtoS
3203
0
    UINT64_C(3240099842), // FMLALL_VG2_M2ZZ_BtoS
3204
0
    UINT64_C(3248554016), // FMLALL_VG4_M4Z4Z_BtoS
3205
0
    UINT64_C(3239084096), // FMLALL_VG4_M4ZZI_BtoS
3206
0
    UINT64_C(3241148418), // FMLALL_VG4_M4ZZ_BtoS
3207
0
    UINT64_C(1688246272), // FMLALT_ZZZ
3208
0
    UINT64_C(1688227840), // FMLALT_ZZZI
3209
0
    UINT64_C(1688224768), // FMLALT_ZZZI_SHH
3210
0
    UINT64_C(1688241152), // FMLALT_ZZZ_SHH
3211
0
    UINT64_C(1337982976), // FMLALTlanev8f16
3212
0
    UINT64_C(1321270272), // FMLALTv8f16
3213
0
    UINT64_C(3250585600), // FMLAL_MZZI_BtoH
3214
0
    UINT64_C(3246395392), // FMLAL_MZZI_HtoS
3215
0
    UINT64_C(3240102912), // FMLAL_MZZ_HtoS
3216
0
    UINT64_C(3248490528), // FMLAL_VG2_M2Z2Z_BtoH
3217
0
    UINT64_C(3248490496), // FMLAL_VG2_M2Z2Z_HtoS
3218
0
    UINT64_C(3247444016), // FMLAL_VG2_M2ZZI_BtoH
3219
0
    UINT64_C(3247443968), // FMLAL_VG2_M2ZZI_HtoS
3220
0
    UINT64_C(3240101892), // FMLAL_VG2_M2ZZ_BtoH
3221
0
    UINT64_C(3240101888), // FMLAL_VG2_M2ZZ_HtoS
3222
0
    UINT64_C(3241151488), // FMLAL_VG2_MZZ_BtoH
3223
0
    UINT64_C(3248556064), // FMLAL_VG4_M4Z4Z_BtoH
3224
0
    UINT64_C(3248556032), // FMLAL_VG4_M4Z4Z_HtoS
3225
0
    UINT64_C(3247476768), // FMLAL_VG4_M4ZZI_BtoH
3226
0
    UINT64_C(3247476736), // FMLAL_VG4_M4ZZI_HtoS
3227
0
    UINT64_C(3241150468), // FMLAL_VG4_M4ZZ_BtoH
3228
0
    UINT64_C(3241150464), // FMLAL_VG4_M4ZZ_HtoS
3229
0
    UINT64_C(260046848),  // FMLALlanev4f16
3230
0
    UINT64_C(1333788672), // FMLALlanev8f16
3231
0
    UINT64_C(237038592),  // FMLALv4f16
3232
0
    UINT64_C(1310780416), // FMLALv8f16
3233
0
    UINT64_C(3252688896), // FMLA_VG2_M2Z2Z_D
3234
0
    UINT64_C(3248494592), // FMLA_VG2_M2Z2Z_S
3235
0
    UINT64_C(3248492552), // FMLA_VG2_M2Z4Z_H
3236
0
    UINT64_C(3251634176), // FMLA_VG2_M2ZZI_D
3237
0
    UINT64_C(3239055360), // FMLA_VG2_M2ZZI_H
3238
0
    UINT64_C(3243245568), // FMLA_VG2_M2ZZI_S
3239
0
    UINT64_C(3244300288), // FMLA_VG2_M2ZZ_D
3240
0
    UINT64_C(3240107008), // FMLA_VG2_M2ZZ_H
3241
0
    UINT64_C(3240105984), // FMLA_VG2_M2ZZ_S
3242
0
    UINT64_C(3252754432), // FMLA_VG4_M4Z4Z_D
3243
0
    UINT64_C(3248558088), // FMLA_VG4_M4Z4Z_H
3244
0
    UINT64_C(3248560128), // FMLA_VG4_M4Z4Z_S
3245
0
    UINT64_C(3251666944), // FMLA_VG4_M4ZZI_D
3246
0
    UINT64_C(3239088128), // FMLA_VG4_M4ZZI_H
3247
0
    UINT64_C(3243278336), // FMLA_VG4_M4ZZI_S
3248
0
    UINT64_C(3245348864), // FMLA_VG4_M4ZZ_D
3249
0
    UINT64_C(3241155584), // FMLA_VG4_M4ZZ_H
3250
0
    UINT64_C(3241154560), // FMLA_VG4_M4ZZ_S
3251
0
    UINT64_C(1709178880), // FMLA_ZPmZZ_D
3252
0
    UINT64_C(1700790272), // FMLA_ZPmZZ_H
3253
0
    UINT64_C(1704984576), // FMLA_ZPmZZ_S
3254
0
    UINT64_C(1692401664), // FMLA_ZZZI_D
3255
0
    UINT64_C(1679818752), // FMLA_ZZZI_H
3256
0
    UINT64_C(1688207360), // FMLA_ZZZI_S
3257
0
    UINT64_C(1593839616), // FMLAv1i16_indexed
3258
0
    UINT64_C(1602228224), // FMLAv1i32_indexed
3259
0
    UINT64_C(1606422528), // FMLAv1i64_indexed
3260
0
    UINT64_C(237030400),  // FMLAv2f32
3261
0
    UINT64_C(1314966528), // FMLAv2f64
3262
0
    UINT64_C(260050944),  // FMLAv2i32_indexed
3263
0
    UINT64_C(1337987072), // FMLAv2i64_indexed
3264
0
    UINT64_C(239078400),  // FMLAv4f16
3265
0
    UINT64_C(1310772224), // FMLAv4f32
3266
0
    UINT64_C(251662336),  // FMLAv4i16_indexed
3267
0
    UINT64_C(1333792768), // FMLAv4i32_indexed
3268
0
    UINT64_C(1312820224), // FMLAv8f16
3269
0
    UINT64_C(1325404160), // FMLAv8i16_indexed
3270
0
    UINT64_C(796966912),  // FMLSL2lanev4f16
3271
0
    UINT64_C(1870708736), // FMLSL2lanev8f16
3272
0
    UINT64_C(782289920),  // FMLSL2v4f16
3273
0
    UINT64_C(1856031744), // FMLSL2v8f16
3274
0
    UINT64_C(1688231936), // FMLSLB_ZZZI_SHH
3275
0
    UINT64_C(1688248320), // FMLSLB_ZZZ_SHH
3276
0
    UINT64_C(1688232960), // FMLSLT_ZZZI_SHH
3277
0
    UINT64_C(1688249344), // FMLSLT_ZZZ_SHH
3278
0
    UINT64_C(3246395400), // FMLSL_MZZI_HtoS
3279
0
    UINT64_C(3240102920), // FMLSL_MZZ_HtoS
3280
0
    UINT64_C(3248490504), // FMLSL_VG2_M2Z2Z_HtoS
3281
0
    UINT64_C(3247443976), // FMLSL_VG2_M2ZZI_HtoS
3282
0
    UINT64_C(3240101896), // FMLSL_VG2_M2ZZ_HtoS
3283
0
    UINT64_C(3248556040), // FMLSL_VG4_M4Z4Z_HtoS
3284
0
    UINT64_C(3247476744), // FMLSL_VG4_M4ZZI_HtoS
3285
0
    UINT64_C(3241150472), // FMLSL_VG4_M4ZZ_HtoS
3286
0
    UINT64_C(260063232),  // FMLSLlanev4f16
3287
0
    UINT64_C(1333805056), // FMLSLlanev8f16
3288
0
    UINT64_C(245427200),  // FMLSLv4f16
3289
0
    UINT64_C(1319169024), // FMLSLv8f16
3290
0
    UINT64_C(3252688904), // FMLS_VG2_M2Z2Z_D
3291
0
    UINT64_C(3248492568), // FMLS_VG2_M2Z2Z_H
3292
0
    UINT64_C(3248494600), // FMLS_VG2_M2Z2Z_S
3293
0
    UINT64_C(3251634192), // FMLS_VG2_M2ZZI_D
3294
0
    UINT64_C(3239055376), // FMLS_VG2_M2ZZI_H
3295
0
    UINT64_C(3243245584), // FMLS_VG2_M2ZZI_S
3296
0
    UINT64_C(3244300296), // FMLS_VG2_M2ZZ_D
3297
0
    UINT64_C(3240107016), // FMLS_VG2_M2ZZ_H
3298
0
    UINT64_C(3240105992), // FMLS_VG2_M2ZZ_S
3299
0
    UINT64_C(3248558104), // FMLS_VG4_M4Z2Z_H
3300
0
    UINT64_C(3252754440), // FMLS_VG4_M4Z4Z_D
3301
0
    UINT64_C(3248560136), // FMLS_VG4_M4Z4Z_S
3302
0
    UINT64_C(3251666960), // FMLS_VG4_M4ZZI_D
3303
0
    UINT64_C(3239088144), // FMLS_VG4_M4ZZI_H
3304
0
    UINT64_C(3243278352), // FMLS_VG4_M4ZZI_S
3305
0
    UINT64_C(3245348872), // FMLS_VG4_M4ZZ_D
3306
0
    UINT64_C(3241155592), // FMLS_VG4_M4ZZ_H
3307
0
    UINT64_C(3241154568), // FMLS_VG4_M4ZZ_S
3308
0
    UINT64_C(1709187072), // FMLS_ZPmZZ_D
3309
0
    UINT64_C(1700798464), // FMLS_ZPmZZ_H
3310
0
    UINT64_C(1704992768), // FMLS_ZPmZZ_S
3311
0
    UINT64_C(1692402688), // FMLS_ZZZI_D
3312
0
    UINT64_C(1679819776), // FMLS_ZZZI_H
3313
0
    UINT64_C(1688208384), // FMLS_ZZZI_S
3314
0
    UINT64_C(1593856000), // FMLSv1i16_indexed
3315
0
    UINT64_C(1602244608), // FMLSv1i32_indexed
3316
0
    UINT64_C(1606438912), // FMLSv1i64_indexed
3317
0
    UINT64_C(245419008),  // FMLSv2f32
3318
0
    UINT64_C(1323355136), // FMLSv2f64
3319
0
    UINT64_C(260067328),  // FMLSv2i32_indexed
3320
0
    UINT64_C(1338003456), // FMLSv2i64_indexed
3321
0
    UINT64_C(247467008),  // FMLSv4f16
3322
0
    UINT64_C(1319160832), // FMLSv4f32
3323
0
    UINT64_C(251678720),  // FMLSv4i16_indexed
3324
0
    UINT64_C(1333809152), // FMLSv4i32_indexed
3325
0
    UINT64_C(1321208832), // FMLSv8f16
3326
0
    UINT64_C(1325420544), // FMLSv8i16_indexed
3327
0
    UINT64_C(1692460032), // FMMLA_ZZZ_D
3328
0
    UINT64_C(1688265728), // FMMLA_ZZZ_S
3329
0
    UINT64_C(2174746624), // FMOPAL_MPPZZ
3330
0
    UINT64_C(2157969416), // FMOPA_MPPZZ_BtoH
3331
0
    UINT64_C(2157969408), // FMOPA_MPPZZ_BtoS
3332
0
    UINT64_C(2160066560), // FMOPA_MPPZZ_D
3333
0
    UINT64_C(2172649480), // FMOPA_MPPZZ_H
3334
0
    UINT64_C(2155872256), // FMOPA_MPPZZ_S
3335
0
    UINT64_C(2174746640), // FMOPSL_MPPZZ
3336
0
    UINT64_C(2160066576), // FMOPS_MPPZZ_D
3337
0
    UINT64_C(2172649496), // FMOPS_MPPZZ_H
3338
0
    UINT64_C(2155872272), // FMOPS_MPPZZ_S
3339
0
    UINT64_C(2662203392), // FMOVDXHighr
3340
0
    UINT64_C(2657484800), // FMOVDXr
3341
0
    UINT64_C(509612032),  // FMOVDi
3342
0
    UINT64_C(509624320),  // FMOVDr
3343
0
    UINT64_C(518389760),  // FMOVHWr
3344
0
    UINT64_C(2665873408), // FMOVHXr
3345
0
    UINT64_C(518000640),  // FMOVHi
3346
0
    UINT64_C(518012928),  // FMOVHr
3347
0
    UINT64_C(505806848),  // FMOVSWr
3348
0
    UINT64_C(505417728),  // FMOVSi
3349
0
    UINT64_C(505430016),  // FMOVSr
3350
0
    UINT64_C(518455296),  // FMOVWHr
3351
0
    UINT64_C(505872384),  // FMOVWSr
3352
0
    UINT64_C(2662268928), // FMOVXDHighr
3353
0
    UINT64_C(2657550336), // FMOVXDr
3354
0
    UINT64_C(2665938944), // FMOVXHr
3355
0
    UINT64_C(251720704),  // FMOVv2f32_ns
3356
0
    UINT64_C(1862333440), // FMOVv2f64_ns
3357
0
    UINT64_C(251722752),  // FMOVv4f16_ns
3358
0
    UINT64_C(1325462528), // FMOVv4f32_ns
3359
0
    UINT64_C(1325464576), // FMOVv8f16_ns
3360
0
    UINT64_C(1709219840), // FMSB_ZPmZZ_D
3361
0
    UINT64_C(1700831232), // FMSB_ZPmZZ_H
3362
0
    UINT64_C(1705025536), // FMSB_ZPmZZ_S
3363
0
    UINT64_C(524320768),  // FMSUBDrrr
3364
0
    UINT64_C(532709376),  // FMSUBHrrr
3365
0
    UINT64_C(520126464),  // FMSUBSrrr
3366
0
    UINT64_C(509609984),  // FMULDrr
3367
0
    UINT64_C(517998592),  // FMULHrr
3368
0
    UINT64_C(505415680),  // FMULSrr
3369
0
    UINT64_C(1581259776), // FMULX16
3370
0
    UINT64_C(1579211776), // FMULX32
3371
0
    UINT64_C(1583406080), // FMULX64
3372
0
    UINT64_C(1707769856), // FMULX_ZPmZ_D
3373
0
    UINT64_C(1699381248), // FMULX_ZPmZ_H
3374
0
    UINT64_C(1703575552), // FMULX_ZPmZ_S
3375
0
    UINT64_C(2130743296), // FMULXv1i16_indexed
3376
0
    UINT64_C(2139131904), // FMULXv1i32_indexed
3377
0
    UINT64_C(2143326208), // FMULXv1i64_indexed
3378
0
    UINT64_C(237034496),  // FMULXv2f32
3379
0
    UINT64_C(1314970624), // FMULXv2f64
3380
0
    UINT64_C(796954624),  // FMULXv2i32_indexed
3381
0
    UINT64_C(1874890752), // FMULXv2i64_indexed
3382
0
    UINT64_C(239082496),  // FMULXv4f16
3383
0
    UINT64_C(1310776320), // FMULXv4f32
3384
0
    UINT64_C(788566016),  // FMULXv4i16_indexed
3385
0
    UINT64_C(1870696448), // FMULXv4i32_indexed
3386
0
    UINT64_C(1312824320), // FMULXv8f16
3387
0
    UINT64_C(1862307840), // FMULXv8i16_indexed
3388
0
    UINT64_C(1708818432), // FMUL_ZPmI_D
3389
0
    UINT64_C(1700429824), // FMUL_ZPmI_H
3390
0
    UINT64_C(1704624128), // FMUL_ZPmI_S
3391
0
    UINT64_C(1707245568), // FMUL_ZPmZ_D
3392
0
    UINT64_C(1698856960), // FMUL_ZPmZ_H
3393
0
    UINT64_C(1703051264), // FMUL_ZPmZ_S
3394
0
    UINT64_C(1692409856), // FMUL_ZZZI_D
3395
0
    UINT64_C(1679826944), // FMUL_ZZZI_H
3396
0
    UINT64_C(1688215552), // FMUL_ZZZI_S
3397
0
    UINT64_C(1707083776), // FMUL_ZZZ_D
3398
0
    UINT64_C(1698695168), // FMUL_ZZZ_H
3399
0
    UINT64_C(1702889472), // FMUL_ZZZ_S
3400
0
    UINT64_C(1593872384), // FMULv1i16_indexed
3401
0
    UINT64_C(1602260992), // FMULv1i32_indexed
3402
0
    UINT64_C(1606455296), // FMULv1i64_indexed
3403
0
    UINT64_C(773905408),  // FMULv2f32
3404
0
    UINT64_C(1851841536), // FMULv2f64
3405
0
    UINT64_C(260083712),  // FMULv2i32_indexed
3406
0
    UINT64_C(1338019840), // FMULv2i64_indexed
3407
0
    UINT64_C(775953408),  // FMULv4f16
3408
0
    UINT64_C(1847647232), // FMULv4f32
3409
0
    UINT64_C(251695104),  // FMULv4i16_indexed
3410
0
    UINT64_C(1333825536), // FMULv4i32_indexed
3411
0
    UINT64_C(1849695232), // FMULv8f16
3412
0
    UINT64_C(1325436928), // FMULv8i16_indexed
3413
0
    UINT64_C(509689856),  // FNEGDr
3414
0
    UINT64_C(518078464),  // FNEGHr
3415
0
    UINT64_C(505495552),  // FNEGSr
3416
0
    UINT64_C(81633280), // FNEG_ZPmZ_D
3417
0
    UINT64_C(73244672), // FNEG_ZPmZ_H
3418
0
    UINT64_C(77438976), // FNEG_ZPmZ_S
3419
0
    UINT64_C(782301184),  // FNEGv2f32
3420
0
    UINT64_C(1860237312), // FNEGv2f64
3421
0
    UINT64_C(788068352),  // FNEGv4f16
3422
0
    UINT64_C(1856043008), // FNEGv4f32
3423
0
    UINT64_C(1861810176), // FNEGv8f16
3424
0
    UINT64_C(526385152),  // FNMADDDrrr
3425
0
    UINT64_C(534773760),  // FNMADDHrrr
3426
0
    UINT64_C(522190848),  // FNMADDSrrr
3427
0
    UINT64_C(1709228032), // FNMAD_ZPmZZ_D
3428
0
    UINT64_C(1700839424), // FNMAD_ZPmZZ_H
3429
0
    UINT64_C(1705033728), // FNMAD_ZPmZZ_S
3430
0
    UINT64_C(1709195264), // FNMLA_ZPmZZ_D
3431
0
    UINT64_C(1700806656), // FNMLA_ZPmZZ_H
3432
0
    UINT64_C(1705000960), // FNMLA_ZPmZZ_S
3433
0
    UINT64_C(1709203456), // FNMLS_ZPmZZ_D
3434
0
    UINT64_C(1700814848), // FNMLS_ZPmZZ_H
3435
0
    UINT64_C(1705009152), // FNMLS_ZPmZZ_S
3436
0
    UINT64_C(1709236224), // FNMSB_ZPmZZ_D
3437
0
    UINT64_C(1700847616), // FNMSB_ZPmZZ_H
3438
0
    UINT64_C(1705041920), // FNMSB_ZPmZZ_S
3439
0
    UINT64_C(526417920),  // FNMSUBDrrr
3440
0
    UINT64_C(534806528),  // FNMSUBHrrr
3441
0
    UINT64_C(522223616),  // FNMSUBSrrr
3442
0
    UINT64_C(509642752),  // FNMULDrr
3443
0
    UINT64_C(518031360),  // FNMULHrr
3444
0
    UINT64_C(505448448),  // FNMULSrr
3445
0
    UINT64_C(1708011520), // FRECPE_ZZ_D
3446
0
    UINT64_C(1699622912), // FRECPE_ZZ_H
3447
0
    UINT64_C(1703817216), // FRECPE_ZZ_S
3448
0
    UINT64_C(1593432064), // FRECPEv1f16
3449
0
    UINT64_C(1587664896), // FRECPEv1i32
3450
0
    UINT64_C(1591859200), // FRECPEv1i64
3451
0
    UINT64_C(245487616),  // FRECPEv2f32
3452
0
    UINT64_C(1323423744), // FRECPEv2f64
3453
0
    UINT64_C(251254784),  // FRECPEv4f16
3454
0
    UINT64_C(1319229440), // FRECPEv4f32
3455
0
    UINT64_C(1324996608), // FRECPEv8f16
3456
0
    UINT64_C(1581267968), // FRECPS16
3457
0
    UINT64_C(1579219968), // FRECPS32
3458
0
    UINT64_C(1583414272), // FRECPS64
3459
0
    UINT64_C(1707087872), // FRECPS_ZZZ_D
3460
0
    UINT64_C(1698699264), // FRECPS_ZZZ_H
3461
0
    UINT64_C(1702893568), // FRECPS_ZZZ_S
3462
0
    UINT64_C(237042688),  // FRECPSv2f32
3463
0
    UINT64_C(1314978816), // FRECPSv2f64
3464
0
    UINT64_C(239090688),  // FRECPSv4f16
3465
0
    UINT64_C(1310784512), // FRECPSv4f32
3466
0
    UINT64_C(1312832512), // FRECPSv8f16
3467
0
    UINT64_C(1707909120), // FRECPX_ZPmZ_D
3468
0
    UINT64_C(1699520512), // FRECPX_ZPmZ_H
3469
0
    UINT64_C(1703714816), // FRECPX_ZPmZ_S
3470
0
    UINT64_C(1593440256), // FRECPXv1f16
3471
0
    UINT64_C(1587673088), // FRECPXv1i32
3472
0
    UINT64_C(1591867392), // FRECPXv1i64
3473
0
    UINT64_C(510181376),  // FRINT32XDr
3474
0
    UINT64_C(505987072),  // FRINT32XSr
3475
0
    UINT64_C(773974016),  // FRINT32Xv2f32
3476
0
    UINT64_C(1851910144), // FRINT32Xv2f64
3477
0
    UINT64_C(1847715840), // FRINT32Xv4f32
3478
0
    UINT64_C(510148608),  // FRINT32ZDr
3479
0
    UINT64_C(505954304),  // FRINT32ZSr
3480
0
    UINT64_C(237103104),  // FRINT32Zv2f32
3481
0
    UINT64_C(1315039232), // FRINT32Zv2f64
3482
0
    UINT64_C(1310844928), // FRINT32Zv4f32
3483
0
    UINT64_C(510246912),  // FRINT64XDr
3484
0
    UINT64_C(506052608),  // FRINT64XSr
3485
0
    UINT64_C(773978112),  // FRINT64Xv2f32
3486
0
    UINT64_C(1851914240), // FRINT64Xv2f64
3487
0
    UINT64_C(1847719936), // FRINT64Xv4f32
3488
0
    UINT64_C(510214144),  // FRINT64ZDr
3489
0
    UINT64_C(506019840),  // FRINT64ZSr
3490
0
    UINT64_C(237107200),  // FRINT64Zv2f32
3491
0
    UINT64_C(1315043328), // FRINT64Zv2f64
3492
0
    UINT64_C(1310849024), // FRINT64Zv4f32
3493
0
    UINT64_C(510017536),  // FRINTADr
3494
0
    UINT64_C(518406144),  // FRINTAHr
3495
0
    UINT64_C(505823232),  // FRINTASr
3496
0
    UINT64_C(3249332224), // FRINTA_2Z2Z_S
3497
0
    UINT64_C(3250380800), // FRINTA_4Z4Z_S
3498
0
    UINT64_C(1707384832), // FRINTA_ZPmZ_D
3499
0
    UINT64_C(1698996224), // FRINTA_ZPmZ_H
3500
0
    UINT64_C(1703190528), // FRINTA_ZPmZ_S
3501
0
    UINT64_C(773949440),  // FRINTAv2f32
3502
0
    UINT64_C(1851885568), // FRINTAv2f64
3503
0
    UINT64_C(779716608),  // FRINTAv4f16
3504
0
    UINT64_C(1847691264), // FRINTAv4f32
3505
0
    UINT64_C(1853458432), // FRINTAv8f16
3506
0
    UINT64_C(510115840),  // FRINTIDr
3507
0
    UINT64_C(518504448),  // FRINTIHr
3508
0
    UINT64_C(505921536),  // FRINTISr
3509
0
    UINT64_C(1707581440), // FRINTI_ZPmZ_D
3510
0
    UINT64_C(1699192832), // FRINTI_ZPmZ_H
3511
0
    UINT64_C(1703387136), // FRINTI_ZPmZ_S
3512
0
    UINT64_C(782342144),  // FRINTIv2f32
3513
0
    UINT64_C(1860278272), // FRINTIv2f64
3514
0
    UINT64_C(788109312),  // FRINTIv4f16
3515
0
    UINT64_C(1856083968), // FRINTIv4f32
3516
0
    UINT64_C(1861851136), // FRINTIv8f16
3517
0
    UINT64_C(509952000),  // FRINTMDr
3518
0
    UINT64_C(518340608),  // FRINTMHr
3519
0
    UINT64_C(505757696),  // FRINTMSr
3520
0
    UINT64_C(3249201152), // FRINTM_2Z2Z_S
3521
0
    UINT64_C(3250249728), // FRINTM_4Z4Z_S
3522
0
    UINT64_C(1707253760), // FRINTM_ZPmZ_D
3523
0
    UINT64_C(1698865152), // FRINTM_ZPmZ_H
3524
0
    UINT64_C(1703059456), // FRINTM_ZPmZ_S
3525
0
    UINT64_C(237082624),  // FRINTMv2f32
3526
0
    UINT64_C(1315018752), // FRINTMv2f64
3527
0
    UINT64_C(242849792),  // FRINTMv4f16
3528
0
    UINT64_C(1310824448), // FRINTMv4f32
3529
0
    UINT64_C(1316591616), // FRINTMv8f16
3530
0
    UINT64_C(509886464),  // FRINTNDr
3531
0
    UINT64_C(518275072),  // FRINTNHr
3532
0
    UINT64_C(505692160),  // FRINTNSr
3533
0
    UINT64_C(3249070080), // FRINTN_2Z2Z_S
3534
0
    UINT64_C(3250118656), // FRINTN_4Z4Z_S
3535
0
    UINT64_C(1707122688), // FRINTN_ZPmZ_D
3536
0
    UINT64_C(1698734080), // FRINTN_ZPmZ_H
3537
0
    UINT64_C(1702928384), // FRINTN_ZPmZ_S
3538
0
    UINT64_C(237078528),  // FRINTNv2f32
3539
0
    UINT64_C(1315014656), // FRINTNv2f64
3540
0
    UINT64_C(242845696),  // FRINTNv4f16
3541
0
    UINT64_C(1310820352), // FRINTNv4f32
3542
0
    UINT64_C(1316587520), // FRINTNv8f16
3543
0
    UINT64_C(509919232),  // FRINTPDr
3544
0
    UINT64_C(518307840),  // FRINTPHr
3545
0
    UINT64_C(505724928),  // FRINTPSr
3546
0
    UINT64_C(3249135616), // FRINTP_2Z2Z_S
3547
0
    UINT64_C(3250184192), // FRINTP_4Z4Z_S
3548
0
    UINT64_C(1707188224), // FRINTP_ZPmZ_D
3549
0
    UINT64_C(1698799616), // FRINTP_ZPmZ_H
3550
0
    UINT64_C(1702993920), // FRINTP_ZPmZ_S
3551
0
    UINT64_C(245467136),  // FRINTPv2f32
3552
0
    UINT64_C(1323403264), // FRINTPv2f64
3553
0
    UINT64_C(251234304),  // FRINTPv4f16
3554
0
    UINT64_C(1319208960), // FRINTPv4f32
3555
0
    UINT64_C(1324976128), // FRINTPv8f16
3556
0
    UINT64_C(510083072),  // FRINTXDr
3557
0
    UINT64_C(518471680),  // FRINTXHr
3558
0
    UINT64_C(505888768),  // FRINTXSr
3559
0
    UINT64_C(1707515904), // FRINTX_ZPmZ_D
3560
0
    UINT64_C(1699127296), // FRINTX_ZPmZ_H
3561
0
    UINT64_C(1703321600), // FRINTX_ZPmZ_S
3562
0
    UINT64_C(773953536),  // FRINTXv2f32
3563
0
    UINT64_C(1851889664), // FRINTXv2f64
3564
0
    UINT64_C(779720704),  // FRINTXv4f16
3565
0
    UINT64_C(1847695360), // FRINTXv4f32
3566
0
    UINT64_C(1853462528), // FRINTXv8f16
3567
0
    UINT64_C(509984768),  // FRINTZDr
3568
0
    UINT64_C(518373376),  // FRINTZHr
3569
0
    UINT64_C(505790464),  // FRINTZSr
3570
0
    UINT64_C(1707319296), // FRINTZ_ZPmZ_D
3571
0
    UINT64_C(1698930688), // FRINTZ_ZPmZ_H
3572
0
    UINT64_C(1703124992), // FRINTZ_ZPmZ_S
3573
0
    UINT64_C(245471232),  // FRINTZv2f32
3574
0
    UINT64_C(1323407360), // FRINTZv2f64
3575
0
    UINT64_C(251238400),  // FRINTZv4f16
3576
0
    UINT64_C(1319213056), // FRINTZv4f32
3577
0
    UINT64_C(1324980224), // FRINTZv8f16
3578
0
    UINT64_C(1708077056), // FRSQRTE_ZZ_D
3579
0
    UINT64_C(1699688448), // FRSQRTE_ZZ_H
3580
0
    UINT64_C(1703882752), // FRSQRTE_ZZ_S
3581
0
    UINT64_C(2130302976), // FRSQRTEv1f16
3582
0
    UINT64_C(2124535808), // FRSQRTEv1i32
3583
0
    UINT64_C(2128730112), // FRSQRTEv1i64
3584
0
    UINT64_C(782358528),  // FRSQRTEv2f32
3585
0
    UINT64_C(1860294656), // FRSQRTEv2f64
3586
0
    UINT64_C(788125696),  // FRSQRTEv4f16
3587
0
    UINT64_C(1856100352), // FRSQRTEv4f32
3588
0
    UINT64_C(1861867520), // FRSQRTEv8f16
3589
0
    UINT64_C(1589656576), // FRSQRTS16
3590
0
    UINT64_C(1587608576), // FRSQRTS32
3591
0
    UINT64_C(1591802880), // FRSQRTS64
3592
0
    UINT64_C(1707088896), // FRSQRTS_ZZZ_D
3593
0
    UINT64_C(1698700288), // FRSQRTS_ZZZ_H
3594
0
    UINT64_C(1702894592), // FRSQRTS_ZZZ_S
3595
0
    UINT64_C(245431296),  // FRSQRTSv2f32
3596
0
    UINT64_C(1323367424), // FRSQRTSv2f64
3597
0
    UINT64_C(247479296),  // FRSQRTSv4f16
3598
0
    UINT64_C(1319173120), // FRSQRTSv4f32
3599
0
    UINT64_C(1321221120), // FRSQRTSv8f16
3600
0
    UINT64_C(3252728192), // FSCALE_2Z2Z_D
3601
0
    UINT64_C(3244339584), // FSCALE_2Z2Z_H
3602
0
    UINT64_C(3248533888), // FSCALE_2Z2Z_S
3603
0
    UINT64_C(3252724096), // FSCALE_2ZZ_D
3604
0
    UINT64_C(3244335488), // FSCALE_2ZZ_H
3605
0
    UINT64_C(3248529792), // FSCALE_2ZZ_S
3606
0
    UINT64_C(3252730240), // FSCALE_4Z4Z_D
3607
0
    UINT64_C(3244341632), // FSCALE_4Z4Z_H
3608
0
    UINT64_C(3248535936), // FSCALE_4Z4Z_S
3609
0
    UINT64_C(3252726144), // FSCALE_4ZZ_D
3610
0
    UINT64_C(3244337536), // FSCALE_4ZZ_H
3611
0
    UINT64_C(3248531840), // FSCALE_4ZZ_S
3612
0
    UINT64_C(1707704320), // FSCALE_ZPmZ_D
3613
0
    UINT64_C(1699315712), // FSCALE_ZPmZ_H
3614
0
    UINT64_C(1703510016), // FSCALE_ZPmZ_S
3615
0
    UINT64_C(782302208),  // FSCALEv2f32
3616
0
    UINT64_C(1860238336), // FSCALEv2f64
3617
0
    UINT64_C(784350208),  // FSCALEv4f16
3618
0
    UINT64_C(1856044032), // FSCALEv4f32
3619
0
    UINT64_C(1858092032), // FSCALEv8f16
3620
0
    UINT64_C(509722624),  // FSQRTDr
3621
0
    UINT64_C(518111232),  // FSQRTHr
3622
0
    UINT64_C(505528320),  // FSQRTSr
3623
0
    UINT64_C(1707974656), // FSQRT_ZPmZ_D
3624
0
    UINT64_C(1699586048), // FSQRT_ZPmZ_H
3625
0
    UINT64_C(1703780352), // FSQRT_ZPmZ_S
3626
0
    UINT64_C(782366720),  // FSQRTv2f32
3627
0
    UINT64_C(1860302848), // FSQRTv2f64
3628
0
    UINT64_C(788133888),  // FSQRTv4f16
3629
0
    UINT64_C(1856108544), // FSQRTv4f32
3630
0
    UINT64_C(1861875712), // FSQRTv8f16
3631
0
    UINT64_C(509622272),  // FSUBDrr
3632
0
    UINT64_C(518010880),  // FSUBHrr
3633
0
    UINT64_C(1708883968), // FSUBR_ZPmI_D
3634
0
    UINT64_C(1700495360), // FSUBR_ZPmI_H
3635
0
    UINT64_C(1704689664), // FSUBR_ZPmI_S
3636
0
    UINT64_C(1707311104), // FSUBR_ZPmZ_D
3637
0
    UINT64_C(1698922496), // FSUBR_ZPmZ_H
3638
0
    UINT64_C(1703116800), // FSUBR_ZPmZ_S
3639
0
    UINT64_C(505427968),  // FSUBSrr
3640
0
    UINT64_C(3252689928), // FSUB_VG2_M2Z_D
3641
0
    UINT64_C(3248757768), // FSUB_VG2_M2Z_H
3642
0
    UINT64_C(3248495624), // FSUB_VG2_M2Z_S
3643
0
    UINT64_C(3252755464), // FSUB_VG4_M4Z_D
3644
0
    UINT64_C(3248823304), // FSUB_VG4_M4Z_H
3645
0
    UINT64_C(3248561160), // FSUB_VG4_M4Z_S
3646
0
    UINT64_C(1708752896), // FSUB_ZPmI_D
3647
0
    UINT64_C(1700364288), // FSUB_ZPmI_H
3648
0
    UINT64_C(1704558592), // FSUB_ZPmI_S
3649
0
    UINT64_C(1707180032), // FSUB_ZPmZ_D
3650
0
    UINT64_C(1698791424), // FSUB_ZPmZ_H
3651
0
    UINT64_C(1702985728), // FSUB_ZPmZ_S
3652
0
    UINT64_C(1707082752), // FSUB_ZZZ_D
3653
0
    UINT64_C(1698694144), // FSUB_ZZZ_H
3654
0
    UINT64_C(1702888448), // FSUB_ZZZ_S
3655
0
    UINT64_C(245421056),  // FSUBv2f32
3656
0
    UINT64_C(1323357184), // FSUBv2f64
3657
0
    UINT64_C(247469056),  // FSUBv4f16
3658
0
    UINT64_C(1319162880), // FSUBv4f32
3659
0
    UINT64_C(1321210880), // FSUBv8f16
3660
0
    UINT64_C(1708163072), // FTMAD_ZZI_D
3661
0
    UINT64_C(1699774464), // FTMAD_ZZI_H
3662
0
    UINT64_C(1703968768), // FTMAD_ZZI_S
3663
0
    UINT64_C(1707084800), // FTSMUL_ZZZ_D
3664
0
    UINT64_C(1698696192), // FTSMUL_ZZZ_H
3665
0
    UINT64_C(1702890496), // FTSMUL_ZZZ_S
3666
0
    UINT64_C(81833984), // FTSSEL_ZZZ_D
3667
0
    UINT64_C(73445376), // FTSSEL_ZZZ_H
3668
0
    UINT64_C(77639680), // FTSSEL_ZZZ_S
3669
0
    UINT64_C(3251636224), // FVDOTB_VG4_M2ZZI_BtoS
3670
0
    UINT64_C(3251636240), // FVDOTT_VG4_M2ZZI_BtoS
3671
0
    UINT64_C(3251638304), // FVDOT_VG2_M2ZZI_BtoH
3672
0
    UINT64_C(3243245576), // FVDOT_VG2_M2ZZI_HtoS
3673
0
    UINT64_C(3574101951), // GCSPOPCX
3674
0
    UINT64_C(3576395552), // GCSPOPM
3675
0
    UINT64_C(3574101983), // GCSPOPX
3676
0
    UINT64_C(3574298368), // GCSPUSHM
3677
0
    UINT64_C(3574101919), // GCSPUSHX
3678
0
    UINT64_C(3574298432), // GCSSS1
3679
0
    UINT64_C(3576395616), // GCSSS2
3680
0
    UINT64_C(3642690560), // GCSSTR
3681
0
    UINT64_C(3642694656), // GCSSTTR
3682
0
    UINT64_C(3290480640), // GLD1B_D_IMM_REAL
3683
0
    UINT64_C(3292577792), // GLD1B_D_REAL
3684
0
    UINT64_C(3292545024), // GLD1B_D_SXTW_REAL
3685
0
    UINT64_C(3288350720), // GLD1B_D_UXTW_REAL
3686
0
    UINT64_C(2216738816), // GLD1B_S_IMM_REAL
3687
0
    UINT64_C(2218803200), // GLD1B_S_SXTW_REAL
3688
0
    UINT64_C(2214608896), // GLD1B_S_UXTW_REAL
3689
0
    UINT64_C(3315646464), // GLD1D_IMM_REAL
3690
0
    UINT64_C(3317743616), // GLD1D_REAL
3691
0
    UINT64_C(3319840768), // GLD1D_SCALED_REAL
3692
0
    UINT64_C(3317710848), // GLD1D_SXTW_REAL
3693
0
    UINT64_C(3319808000), // GLD1D_SXTW_SCALED_REAL
3694
0
    UINT64_C(3313516544), // GLD1D_UXTW_REAL
3695
0
    UINT64_C(3315613696), // GLD1D_UXTW_SCALED_REAL
3696
0
    UINT64_C(3298869248), // GLD1H_D_IMM_REAL
3697
0
    UINT64_C(3300966400), // GLD1H_D_REAL
3698
0
    UINT64_C(3303063552), // GLD1H_D_SCALED_REAL
3699
0
    UINT64_C(3300933632), // GLD1H_D_SXTW_REAL
3700
0
    UINT64_C(3303030784), // GLD1H_D_SXTW_SCALED_REAL
3701
0
    UINT64_C(3296739328), // GLD1H_D_UXTW_REAL
3702
0
    UINT64_C(3298836480), // GLD1H_D_UXTW_SCALED_REAL
3703
0
    UINT64_C(2225127424), // GLD1H_S_IMM_REAL
3704
0
    UINT64_C(2227191808), // GLD1H_S_SXTW_REAL
3705
0
    UINT64_C(2229288960), // GLD1H_S_SXTW_SCALED_REAL
3706
0
    UINT64_C(2222997504), // GLD1H_S_UXTW_REAL
3707
0
    UINT64_C(2225094656), // GLD1H_S_UXTW_SCALED_REAL
3708
0
    UINT64_C(3288375296), // GLD1Q
3709
0
    UINT64_C(3290464256), // GLD1SB_D_IMM_REAL
3710
0
    UINT64_C(3292561408), // GLD1SB_D_REAL
3711
0
    UINT64_C(3292528640), // GLD1SB_D_SXTW_REAL
3712
0
    UINT64_C(3288334336), // GLD1SB_D_UXTW_REAL
3713
0
    UINT64_C(2216722432), // GLD1SB_S_IMM_REAL
3714
0
    UINT64_C(2218786816), // GLD1SB_S_SXTW_REAL
3715
0
    UINT64_C(2214592512), // GLD1SB_S_UXTW_REAL
3716
0
    UINT64_C(3298852864), // GLD1SH_D_IMM_REAL
3717
0
    UINT64_C(3300950016), // GLD1SH_D_REAL
3718
0
    UINT64_C(3303047168), // GLD1SH_D_SCALED_REAL
3719
0
    UINT64_C(3300917248), // GLD1SH_D_SXTW_REAL
3720
0
    UINT64_C(3303014400), // GLD1SH_D_SXTW_SCALED_REAL
3721
0
    UINT64_C(3296722944), // GLD1SH_D_UXTW_REAL
3722
0
    UINT64_C(3298820096), // GLD1SH_D_UXTW_SCALED_REAL
3723
0
    UINT64_C(2225111040), // GLD1SH_S_IMM_REAL
3724
0
    UINT64_C(2227175424), // GLD1SH_S_SXTW_REAL
3725
0
    UINT64_C(2229272576), // GLD1SH_S_SXTW_SCALED_REAL
3726
0
    UINT64_C(2222981120), // GLD1SH_S_UXTW_REAL
3727
0
    UINT64_C(2225078272), // GLD1SH_S_UXTW_SCALED_REAL
3728
0
    UINT64_C(3307241472), // GLD1SW_D_IMM_REAL
3729
0
    UINT64_C(3309338624), // GLD1SW_D_REAL
3730
0
    UINT64_C(3311435776), // GLD1SW_D_SCALED_REAL
3731
0
    UINT64_C(3309305856), // GLD1SW_D_SXTW_REAL
3732
0
    UINT64_C(3311403008), // GLD1SW_D_SXTW_SCALED_REAL
3733
0
    UINT64_C(3305111552), // GLD1SW_D_UXTW_REAL
3734
0
    UINT64_C(3307208704), // GLD1SW_D_UXTW_SCALED_REAL
3735
0
    UINT64_C(3307257856), // GLD1W_D_IMM_REAL
3736
0
    UINT64_C(3309355008), // GLD1W_D_REAL
3737
0
    UINT64_C(3311452160), // GLD1W_D_SCALED_REAL
3738
0
    UINT64_C(3309322240), // GLD1W_D_SXTW_REAL
3739
0
    UINT64_C(3311419392), // GLD1W_D_SXTW_SCALED_REAL
3740
0
    UINT64_C(3305127936), // GLD1W_D_UXTW_REAL
3741
0
    UINT64_C(3307225088), // GLD1W_D_UXTW_SCALED_REAL
3742
0
    UINT64_C(2233516032), // GLD1W_IMM_REAL
3743
0
    UINT64_C(2235580416), // GLD1W_SXTW_REAL
3744
0
    UINT64_C(2237677568), // GLD1W_SXTW_SCALED_REAL
3745
0
    UINT64_C(2231386112), // GLD1W_UXTW_REAL
3746
0
    UINT64_C(2233483264), // GLD1W_UXTW_SCALED_REAL
3747
0
    UINT64_C(3290488832), // GLDFF1B_D_IMM_REAL
3748
0
    UINT64_C(3292585984), // GLDFF1B_D_REAL
3749
0
    UINT64_C(3292553216), // GLDFF1B_D_SXTW_REAL
3750
0
    UINT64_C(3288358912), // GLDFF1B_D_UXTW_REAL
3751
0
    UINT64_C(2216747008), // GLDFF1B_S_IMM_REAL
3752
0
    UINT64_C(2218811392), // GLDFF1B_S_SXTW_REAL
3753
0
    UINT64_C(2214617088), // GLDFF1B_S_UXTW_REAL
3754
0
    UINT64_C(3315654656), // GLDFF1D_IMM_REAL
3755
0
    UINT64_C(3317751808), // GLDFF1D_REAL
3756
0
    UINT64_C(3319848960), // GLDFF1D_SCALED_REAL
3757
0
    UINT64_C(3317719040), // GLDFF1D_SXTW_REAL
3758
0
    UINT64_C(3319816192), // GLDFF1D_SXTW_SCALED_REAL
3759
0
    UINT64_C(3313524736), // GLDFF1D_UXTW_REAL
3760
0
    UINT64_C(3315621888), // GLDFF1D_UXTW_SCALED_REAL
3761
0
    UINT64_C(3298877440), // GLDFF1H_D_IMM_REAL
3762
0
    UINT64_C(3300974592), // GLDFF1H_D_REAL
3763
0
    UINT64_C(3303071744), // GLDFF1H_D_SCALED_REAL
3764
0
    UINT64_C(3300941824), // GLDFF1H_D_SXTW_REAL
3765
0
    UINT64_C(3303038976), // GLDFF1H_D_SXTW_SCALED_REAL
3766
0
    UINT64_C(3296747520), // GLDFF1H_D_UXTW_REAL
3767
0
    UINT64_C(3298844672), // GLDFF1H_D_UXTW_SCALED_REAL
3768
0
    UINT64_C(2225135616), // GLDFF1H_S_IMM_REAL
3769
0
    UINT64_C(2227200000), // GLDFF1H_S_SXTW_REAL
3770
0
    UINT64_C(2229297152), // GLDFF1H_S_SXTW_SCALED_REAL
3771
0
    UINT64_C(2223005696), // GLDFF1H_S_UXTW_REAL
3772
0
    UINT64_C(2225102848), // GLDFF1H_S_UXTW_SCALED_REAL
3773
0
    UINT64_C(3290472448), // GLDFF1SB_D_IMM_REAL
3774
0
    UINT64_C(3292569600), // GLDFF1SB_D_REAL
3775
0
    UINT64_C(3292536832), // GLDFF1SB_D_SXTW_REAL
3776
0
    UINT64_C(3288342528), // GLDFF1SB_D_UXTW_REAL
3777
0
    UINT64_C(2216730624), // GLDFF1SB_S_IMM_REAL
3778
0
    UINT64_C(2218795008), // GLDFF1SB_S_SXTW_REAL
3779
0
    UINT64_C(2214600704), // GLDFF1SB_S_UXTW_REAL
3780
0
    UINT64_C(3298861056), // GLDFF1SH_D_IMM_REAL
3781
0
    UINT64_C(3300958208), // GLDFF1SH_D_REAL
3782
0
    UINT64_C(3303055360), // GLDFF1SH_D_SCALED_REAL
3783
0
    UINT64_C(3300925440), // GLDFF1SH_D_SXTW_REAL
3784
0
    UINT64_C(3303022592), // GLDFF1SH_D_SXTW_SCALED_REAL
3785
0
    UINT64_C(3296731136), // GLDFF1SH_D_UXTW_REAL
3786
0
    UINT64_C(3298828288), // GLDFF1SH_D_UXTW_SCALED_REAL
3787
0
    UINT64_C(2225119232), // GLDFF1SH_S_IMM_REAL
3788
0
    UINT64_C(2227183616), // GLDFF1SH_S_SXTW_REAL
3789
0
    UINT64_C(2229280768), // GLDFF1SH_S_SXTW_SCALED_REAL
3790
0
    UINT64_C(2222989312), // GLDFF1SH_S_UXTW_REAL
3791
0
    UINT64_C(2225086464), // GLDFF1SH_S_UXTW_SCALED_REAL
3792
0
    UINT64_C(3307249664), // GLDFF1SW_D_IMM_REAL
3793
0
    UINT64_C(3309346816), // GLDFF1SW_D_REAL
3794
0
    UINT64_C(3311443968), // GLDFF1SW_D_SCALED_REAL
3795
0
    UINT64_C(3309314048), // GLDFF1SW_D_SXTW_REAL
3796
0
    UINT64_C(3311411200), // GLDFF1SW_D_SXTW_SCALED_REAL
3797
0
    UINT64_C(3305119744), // GLDFF1SW_D_UXTW_REAL
3798
0
    UINT64_C(3307216896), // GLDFF1SW_D_UXTW_SCALED_REAL
3799
0
    UINT64_C(3307266048), // GLDFF1W_D_IMM_REAL
3800
0
    UINT64_C(3309363200), // GLDFF1W_D_REAL
3801
0
    UINT64_C(3311460352), // GLDFF1W_D_SCALED_REAL
3802
0
    UINT64_C(3309330432), // GLDFF1W_D_SXTW_REAL
3803
0
    UINT64_C(3311427584), // GLDFF1W_D_SXTW_SCALED_REAL
3804
0
    UINT64_C(3305136128), // GLDFF1W_D_UXTW_REAL
3805
0
    UINT64_C(3307233280), // GLDFF1W_D_UXTW_SCALED_REAL
3806
0
    UINT64_C(2233524224), // GLDFF1W_IMM_REAL
3807
0
    UINT64_C(2235588608), // GLDFF1W_SXTW_REAL
3808
0
    UINT64_C(2237685760), // GLDFF1W_SXTW_SCALED_REAL
3809
0
    UINT64_C(2231394304), // GLDFF1W_UXTW_REAL
3810
0
    UINT64_C(2233491456), // GLDFF1W_UXTW_SCALED_REAL
3811
0
    UINT64_C(2596279296), // GMI
3812
0
    UINT64_C(3573751839), // HINT
3813
0
    UINT64_C(1172357120), // HISTCNT_ZPzZZ_D
3814
0
    UINT64_C(1168162816), // HISTCNT_ZPzZZ_S
3815
0
    UINT64_C(1159766016), // HISTSEG_ZZZ
3816
0
    UINT64_C(3560964096), // HLT
3817
0
    UINT64_C(3556769794), // HVC
3818
0
    UINT64_C(70311936), // INCB_XPiI
3819
0
    UINT64_C(82894848), // INCD_XPiI
3820
0
    UINT64_C(82886656), // INCD_ZPiI
3821
0
    UINT64_C(74506240), // INCH_XPiI
3822
0
    UINT64_C(74498048), // INCH_ZPiI
3823
0
    UINT64_C(623675392),  // INCP_XP_B
3824
0
    UINT64_C(636258304),  // INCP_XP_D
3825
0
    UINT64_C(627869696),  // INCP_XP_H
3826
0
    UINT64_C(632064000),  // INCP_XP_S
3827
0
    UINT64_C(636256256),  // INCP_ZP_D
3828
0
    UINT64_C(627867648),  // INCP_ZP_H
3829
0
    UINT64_C(632061952),  // INCP_ZP_S
3830
0
    UINT64_C(78700544), // INCW_XPiI
3831
0
    UINT64_C(78692352), // INCW_ZPiI
3832
0
    UINT64_C(69222400), // INDEX_II_B
3833
0
    UINT64_C(81805312), // INDEX_II_D
3834
0
    UINT64_C(73416704), // INDEX_II_H
3835
0
    UINT64_C(77611008), // INDEX_II_S
3836
0
    UINT64_C(69224448), // INDEX_IR_B
3837
0
    UINT64_C(81807360), // INDEX_IR_D
3838
0
    UINT64_C(73418752), // INDEX_IR_H
3839
0
    UINT64_C(77613056), // INDEX_IR_S
3840
0
    UINT64_C(69223424), // INDEX_RI_B
3841
0
    UINT64_C(81806336), // INDEX_RI_D
3842
0
    UINT64_C(73417728), // INDEX_RI_H
3843
0
    UINT64_C(77612032), // INDEX_RI_S
3844
0
    UINT64_C(69225472), // INDEX_RR_B
3845
0
    UINT64_C(81808384), // INDEX_RR_D
3846
0
    UINT64_C(73419776), // INDEX_RR_H
3847
0
    UINT64_C(77614080), // INDEX_RR_S
3848
0
    UINT64_C(3221225472), // INSERT_MXIPZ_H_B
3849
0
    UINT64_C(3233808384), // INSERT_MXIPZ_H_D
3850
0
    UINT64_C(3225419776), // INSERT_MXIPZ_H_H
3851
0
    UINT64_C(3233873920), // INSERT_MXIPZ_H_Q
3852
0
    UINT64_C(3229614080), // INSERT_MXIPZ_H_S
3853
0
    UINT64_C(3221258240), // INSERT_MXIPZ_V_B
3854
0
    UINT64_C(3233841152), // INSERT_MXIPZ_V_D
3855
0
    UINT64_C(3225452544), // INSERT_MXIPZ_V_H
3856
0
    UINT64_C(3233906688), // INSERT_MXIPZ_V_Q
3857
0
    UINT64_C(3229646848), // INSERT_MXIPZ_V_S
3858
0
    UINT64_C(86259712), // INSR_ZR_B
3859
0
    UINT64_C(98842624), // INSR_ZR_D
3860
0
    UINT64_C(90454016), // INSR_ZR_H
3861
0
    UINT64_C(94648320), // INSR_ZR_S
3862
0
    UINT64_C(87308288), // INSR_ZV_B
3863
0
    UINT64_C(99891200), // INSR_ZV_D
3864
0
    UINT64_C(91502592), // INSR_ZV_H
3865
0
    UINT64_C(95696896), // INSR_ZV_S
3866
0
    UINT64_C(1308761088), // INSvi16gpr
3867
0
    UINT64_C(1845625856), // INSvi16lane
3868
0
    UINT64_C(1308892160), // INSvi32gpr
3869
0
    UINT64_C(1845756928), // INSvi32lane
3870
0
    UINT64_C(1309154304), // INSvi64gpr
3871
0
    UINT64_C(1846019072), // INSvi64lane
3872
0
    UINT64_C(1308695552), // INSvi8gpr
3873
0
    UINT64_C(1845560320), // INSvi8lane
3874
0
    UINT64_C(2596278272), // IRG
3875
0
    UINT64_C(3573756127), // ISB
3876
0
    UINT64_C(86024192), // LASTA_RPZ_B
3877
0
    UINT64_C(98607104), // LASTA_RPZ_D
3878
0
    UINT64_C(90218496), // LASTA_RPZ_H
3879
0
    UINT64_C(94412800), // LASTA_RPZ_S
3880
0
    UINT64_C(86147072), // LASTA_VPZ_B
3881
0
    UINT64_C(98729984), // LASTA_VPZ_D
3882
0
    UINT64_C(90341376), // LASTA_VPZ_H
3883
0
    UINT64_C(94535680), // LASTA_VPZ_S
3884
0
    UINT64_C(86089728), // LASTB_RPZ_B
3885
0
    UINT64_C(98672640), // LASTB_RPZ_D
3886
0
    UINT64_C(90284032), // LASTB_RPZ_H
3887
0
    UINT64_C(94478336), // LASTB_RPZ_S
3888
0
    UINT64_C(86212608), // LASTB_VPZ_B
3889
0
    UINT64_C(98795520), // LASTB_VPZ_D
3890
0
    UINT64_C(90406912), // LASTB_VPZ_H
3891
0
    UINT64_C(94601216), // LASTB_VPZ_S
3892
0
    UINT64_C(2751479808), // LD1B
3893
0
    UINT64_C(2684354560), // LD1B_2Z
3894
0
    UINT64_C(2688548864), // LD1B_2Z_IMM
3895
0
    UINT64_C(2701131776), // LD1B_2Z_STRIDED
3896
0
    UINT64_C(2705326080), // LD1B_2Z_STRIDED_IMM
3897
0
    UINT64_C(2684387328), // LD1B_4Z
3898
0
    UINT64_C(2688581632), // LD1B_4Z_IMM
3899
0
    UINT64_C(2701164544), // LD1B_4Z_STRIDED
3900
0
    UINT64_C(2705358848), // LD1B_4Z_STRIDED_IMM
3901
0
    UINT64_C(2757771264), // LD1B_D
3902
0
    UINT64_C(2757795840), // LD1B_D_IMM
3903
0
    UINT64_C(2753576960), // LD1B_H
3904
0
    UINT64_C(2753601536), // LD1B_H_IMM
3905
0
    UINT64_C(2751504384), // LD1B_IMM
3906
0
    UINT64_C(2755674112), // LD1B_S
3907
0
    UINT64_C(2755698688), // LD1B_S_IMM
3908
0
    UINT64_C(2782937088), // LD1D
3909
0
    UINT64_C(2684379136), // LD1D_2Z
3910
0
    UINT64_C(2688573440), // LD1D_2Z_IMM
3911
0
    UINT64_C(2701156352), // LD1D_2Z_STRIDED
3912
0
    UINT64_C(2705350656), // LD1D_2Z_STRIDED_IMM
3913
0
    UINT64_C(2684411904), // LD1D_4Z
3914
0
    UINT64_C(2688606208), // LD1D_4Z_IMM
3915
0
    UINT64_C(2701189120), // LD1D_4Z_STRIDED
3916
0
    UINT64_C(2705383424), // LD1D_4Z_STRIDED_IMM
3917
0
    UINT64_C(2782961664), // LD1D_IMM
3918
0
    UINT64_C(2776662016), // LD1D_Q
3919
0
    UINT64_C(2777686016), // LD1D_Q_IMM
3920
0
    UINT64_C(1279270912), // LD1Fourv16b
3921
0
    UINT64_C(1287659520), // LD1Fourv16b_POST
3922
0
    UINT64_C(205532160),  // LD1Fourv1d
3923
0
    UINT64_C(213920768),  // LD1Fourv1d_POST
3924
0
    UINT64_C(1279273984), // LD1Fourv2d
3925
0
    UINT64_C(1287662592), // LD1Fourv2d_POST
3926
0
    UINT64_C(205531136),  // LD1Fourv2s
3927
0
    UINT64_C(213919744),  // LD1Fourv2s_POST
3928
0
    UINT64_C(205530112),  // LD1Fourv4h
3929
0
    UINT64_C(213918720),  // LD1Fourv4h_POST
3930
0
    UINT64_C(1279272960), // LD1Fourv4s
3931
0
    UINT64_C(1287661568), // LD1Fourv4s_POST
3932
0
    UINT64_C(205529088),  // LD1Fourv8b
3933
0
    UINT64_C(213917696),  // LD1Fourv8b_POST
3934
0
    UINT64_C(1279271936), // LD1Fourv8h
3935
0
    UINT64_C(1287660544), // LD1Fourv8h_POST
3936
0
    UINT64_C(2761965568), // LD1H
3937
0
    UINT64_C(2684362752), // LD1H_2Z
3938
0
    UINT64_C(2688557056), // LD1H_2Z_IMM
3939
0
    UINT64_C(2701139968), // LD1H_2Z_STRIDED
3940
0
    UINT64_C(2705334272), // LD1H_2Z_STRIDED_IMM
3941
0
    UINT64_C(2684395520), // LD1H_4Z
3942
0
    UINT64_C(2688589824), // LD1H_4Z_IMM
3943
0
    UINT64_C(2701172736), // LD1H_4Z_STRIDED
3944
0
    UINT64_C(2705367040), // LD1H_4Z_STRIDED_IMM
3945
0
    UINT64_C(2766159872), // LD1H_D
3946
0
    UINT64_C(2766184448), // LD1H_D_IMM
3947
0
    UINT64_C(2761990144), // LD1H_IMM
3948
0
    UINT64_C(2764062720), // LD1H_S
3949
0
    UINT64_C(2764087296), // LD1H_S_IMM
3950
0
    UINT64_C(1279291392), // LD1Onev16b
3951
0
    UINT64_C(1287680000), // LD1Onev16b_POST
3952
0
    UINT64_C(205552640),  // LD1Onev1d
3953
0
    UINT64_C(213941248),  // LD1Onev1d_POST
3954
0
    UINT64_C(1279294464), // LD1Onev2d
3955
0
    UINT64_C(1287683072), // LD1Onev2d_POST
3956
0
    UINT64_C(205551616),  // LD1Onev2s
3957
0
    UINT64_C(213940224),  // LD1Onev2s_POST
3958
0
    UINT64_C(205550592),  // LD1Onev4h
3959
0
    UINT64_C(213939200),  // LD1Onev4h_POST
3960
0
    UINT64_C(1279293440), // LD1Onev4s
3961
0
    UINT64_C(1287682048), // LD1Onev4s_POST
3962
0
    UINT64_C(205549568),  // LD1Onev8b
3963
0
    UINT64_C(213938176),  // LD1Onev8b_POST
3964
0
    UINT64_C(1279292416), // LD1Onev8h
3965
0
    UINT64_C(1287681024), // LD1Onev8h_POST
3966
0
    UINT64_C(2218844160), // LD1RB_D_IMM
3967
0
    UINT64_C(2218827776), // LD1RB_H_IMM
3968
0
    UINT64_C(2218819584), // LD1RB_IMM
3969
0
    UINT64_C(2218835968), // LD1RB_S_IMM
3970
0
    UINT64_C(2244009984), // LD1RD_IMM
3971
0
    UINT64_C(2227232768), // LD1RH_D_IMM
3972
0
    UINT64_C(2227216384), // LD1RH_IMM
3973
0
    UINT64_C(2227224576), // LD1RH_S_IMM
3974
0
    UINT64_C(2753560576), // LD1RO_B
3975
0
    UINT64_C(2753568768), // LD1RO_B_IMM
3976
0
    UINT64_C(2778726400), // LD1RO_D
3977
0
    UINT64_C(2778734592), // LD1RO_D_IMM
3978
0
    UINT64_C(2761949184), // LD1RO_H
3979
0
    UINT64_C(2761957376), // LD1RO_H_IMM
3980
0
    UINT64_C(2770337792), // LD1RO_W
3981
0
    UINT64_C(2770345984), // LD1RO_W_IMM
3982
0
    UINT64_C(2751463424), // LD1RQ_B
3983
0
    UINT64_C(2751471616), // LD1RQ_B_IMM
3984
0
    UINT64_C(2776629248), // LD1RQ_D
3985
0
    UINT64_C(2776637440), // LD1RQ_D_IMM
3986
0
    UINT64_C(2759852032), // LD1RQ_H
3987
0
    UINT64_C(2759860224), // LD1RQ_H_IMM
3988
0
    UINT64_C(2768240640), // LD1RQ_W
3989
0
    UINT64_C(2768248832), // LD1RQ_W_IMM
3990
0
    UINT64_C(2243985408), // LD1RSB_D_IMM
3991
0
    UINT64_C(2244001792), // LD1RSB_H_IMM
3992
0
    UINT64_C(2243993600), // LD1RSB_S_IMM
3993
0
    UINT64_C(2235596800), // LD1RSH_D_IMM
3994
0
    UINT64_C(2235604992), // LD1RSH_S_IMM
3995
0
    UINT64_C(2227208192), // LD1RSW_IMM
3996
0
    UINT64_C(2235621376), // LD1RW_D_IMM
3997
0
    UINT64_C(2235613184), // LD1RW_IMM
3998
0
    UINT64_C(1296089088), // LD1Rv16b
3999
0
    UINT64_C(1304477696), // LD1Rv16b_POST
4000
0
    UINT64_C(222350336),  // LD1Rv1d
4001
0
    UINT64_C(230738944),  // LD1Rv1d_POST
4002
0
    UINT64_C(1296092160), // LD1Rv2d
4003
0
    UINT64_C(1304480768), // LD1Rv2d_POST
4004
0
    UINT64_C(222349312),  // LD1Rv2s
4005
0
    UINT64_C(230737920),  // LD1Rv2s_POST
4006
0
    UINT64_C(222348288),  // LD1Rv4h
4007
0
    UINT64_C(230736896),  // LD1Rv4h_POST
4008
0
    UINT64_C(1296091136), // LD1Rv4s
4009
0
    UINT64_C(1304479744), // LD1Rv4s_POST
4010
0
    UINT64_C(222347264),  // LD1Rv8b
4011
0
    UINT64_C(230735872),  // LD1Rv8b_POST
4012
0
    UINT64_C(1296090112), // LD1Rv8h
4013
0
    UINT64_C(1304478720), // LD1Rv8h_POST
4014
0
    UINT64_C(2776645632), // LD1SB_D
4015
0
    UINT64_C(2776670208), // LD1SB_D_IMM
4016
0
    UINT64_C(2780839936), // LD1SB_H
4017
0
    UINT64_C(2780864512), // LD1SB_H_IMM
4018
0
    UINT64_C(2778742784), // LD1SB_S
4019
0
    UINT64_C(2778767360), // LD1SB_S_IMM
4020
0
    UINT64_C(2768257024), // LD1SH_D
4021
0
    UINT64_C(2768281600), // LD1SH_D_IMM
4022
0
    UINT64_C(2770354176), // LD1SH_S
4023
0
    UINT64_C(2770378752), // LD1SH_S_IMM
4024
0
    UINT64_C(2759868416), // LD1SW_D
4025
0
    UINT64_C(2759892992), // LD1SW_D_IMM
4026
0
    UINT64_C(1279287296), // LD1Threev16b
4027
0
    UINT64_C(1287675904), // LD1Threev16b_POST
4028
0
    UINT64_C(205548544),  // LD1Threev1d
4029
0
    UINT64_C(213937152),  // LD1Threev1d_POST
4030
0
    UINT64_C(1279290368), // LD1Threev2d
4031
0
    UINT64_C(1287678976), // LD1Threev2d_POST
4032
0
    UINT64_C(205547520),  // LD1Threev2s
4033
0
    UINT64_C(213936128),  // LD1Threev2s_POST
4034
0
    UINT64_C(205546496),  // LD1Threev4h
4035
0
    UINT64_C(213935104),  // LD1Threev4h_POST
4036
0
    UINT64_C(1279289344), // LD1Threev4s
4037
0
    UINT64_C(1287677952), // LD1Threev4s_POST
4038
0
    UINT64_C(205545472),  // LD1Threev8b
4039
0
    UINT64_C(213934080),  // LD1Threev8b_POST
4040
0
    UINT64_C(1279288320), // LD1Threev8h
4041
0
    UINT64_C(1287676928), // LD1Threev8h_POST
4042
0
    UINT64_C(1279303680), // LD1Twov16b
4043
0
    UINT64_C(1287692288), // LD1Twov16b_POST
4044
0
    UINT64_C(205564928),  // LD1Twov1d
4045
0
    UINT64_C(213953536),  // LD1Twov1d_POST
4046
0
    UINT64_C(1279306752), // LD1Twov2d
4047
0
    UINT64_C(1287695360), // LD1Twov2d_POST
4048
0
    UINT64_C(205563904),  // LD1Twov2s
4049
0
    UINT64_C(213952512),  // LD1Twov2s_POST
4050
0
    UINT64_C(205562880),  // LD1Twov4h
4051
0
    UINT64_C(213951488),  // LD1Twov4h_POST
4052
0
    UINT64_C(1279305728), // LD1Twov4s
4053
0
    UINT64_C(1287694336), // LD1Twov4s_POST
4054
0
    UINT64_C(205561856),  // LD1Twov8b
4055
0
    UINT64_C(213950464),  // LD1Twov8b_POST
4056
0
    UINT64_C(1279304704), // LD1Twov8h
4057
0
    UINT64_C(1287693312), // LD1Twov8h_POST
4058
0
    UINT64_C(2772451328), // LD1W
4059
0
    UINT64_C(2684370944), // LD1W_2Z
4060
0
    UINT64_C(2688565248), // LD1W_2Z_IMM
4061
0
    UINT64_C(2701148160), // LD1W_2Z_STRIDED
4062
0
    UINT64_C(2705342464), // LD1W_2Z_STRIDED_IMM
4063
0
    UINT64_C(2684403712), // LD1W_4Z
4064
0
    UINT64_C(2688598016), // LD1W_4Z_IMM
4065
0
    UINT64_C(2701180928), // LD1W_4Z_STRIDED
4066
0
    UINT64_C(2705375232), // LD1W_4Z_STRIDED_IMM
4067
0
    UINT64_C(2774548480), // LD1W_D
4068
0
    UINT64_C(2774573056), // LD1W_D_IMM
4069
0
    UINT64_C(2772475904), // LD1W_IMM
4070
0
    UINT64_C(2768273408), // LD1W_Q
4071
0
    UINT64_C(2769297408), // LD1W_Q_IMM
4072
0
    UINT64_C(3758096384), // LD1_MXIPXX_H_B
4073
0
    UINT64_C(3770679296), // LD1_MXIPXX_H_D
4074
0
    UINT64_C(3762290688), // LD1_MXIPXX_H_H
4075
0
    UINT64_C(3787456512), // LD1_MXIPXX_H_Q
4076
0
    UINT64_C(3766484992), // LD1_MXIPXX_H_S
4077
0
    UINT64_C(3758129152), // LD1_MXIPXX_V_B
4078
0
    UINT64_C(3770712064), // LD1_MXIPXX_V_D
4079
0
    UINT64_C(3762323456), // LD1_MXIPXX_V_H
4080
0
    UINT64_C(3787489280), // LD1_MXIPXX_V_Q
4081
0
    UINT64_C(3766517760), // LD1_MXIPXX_V_S
4082
0
    UINT64_C(222314496),  // LD1i16
4083
0
    UINT64_C(230703104),  // LD1i16_POST
4084
0
    UINT64_C(222330880),  // LD1i32
4085
0
    UINT64_C(230719488),  // LD1i32_POST
4086
0
    UINT64_C(222331904),  // LD1i64
4087
0
    UINT64_C(230720512),  // LD1i64_POST
4088
0
    UINT64_C(222298112),  // LD1i8
4089
0
    UINT64_C(230686720),  // LD1i8_POST
4090
0
    UINT64_C(2753609728), // LD2B
4091
0
    UINT64_C(2753617920), // LD2B_IMM
4092
0
    UINT64_C(2778775552), // LD2D
4093
0
    UINT64_C(2778783744), // LD2D_IMM
4094
0
    UINT64_C(2761998336), // LD2H
4095
0
    UINT64_C(2762006528), // LD2H_IMM
4096
0
    UINT64_C(2761981952), // LD2Q
4097
0
    UINT64_C(2760957952), // LD2Q_IMM
4098
0
    UINT64_C(1298186240), // LD2Rv16b
4099
0
    UINT64_C(1306574848), // LD2Rv16b_POST
4100
0
    UINT64_C(224447488),  // LD2Rv1d
4101
0
    UINT64_C(232836096),  // LD2Rv1d_POST
4102
0
    UINT64_C(1298189312), // LD2Rv2d
4103
0
    UINT64_C(1306577920), // LD2Rv2d_POST
4104
0
    UINT64_C(224446464),  // LD2Rv2s
4105
0
    UINT64_C(232835072),  // LD2Rv2s_POST
4106
0
    UINT64_C(224445440),  // LD2Rv4h
4107
0
    UINT64_C(232834048),  // LD2Rv4h_POST
4108
0
    UINT64_C(1298188288), // LD2Rv4s
4109
0
    UINT64_C(1306576896), // LD2Rv4s_POST
4110
0
    UINT64_C(224444416),  // LD2Rv8b
4111
0
    UINT64_C(232833024),  // LD2Rv8b_POST
4112
0
    UINT64_C(1298187264), // LD2Rv8h
4113
0
    UINT64_C(1306575872), // LD2Rv8h_POST
4114
0
    UINT64_C(1279295488), // LD2Twov16b
4115
0
    UINT64_C(1287684096), // LD2Twov16b_POST
4116
0
    UINT64_C(1279298560), // LD2Twov2d
4117
0
    UINT64_C(1287687168), // LD2Twov2d_POST
4118
0
    UINT64_C(205555712),  // LD2Twov2s
4119
0
    UINT64_C(213944320),  // LD2Twov2s_POST
4120
0
    UINT64_C(205554688),  // LD2Twov4h
4121
0
    UINT64_C(213943296),  // LD2Twov4h_POST
4122
0
    UINT64_C(1279297536), // LD2Twov4s
4123
0
    UINT64_C(1287686144), // LD2Twov4s_POST
4124
0
    UINT64_C(205553664),  // LD2Twov8b
4125
0
    UINT64_C(213942272),  // LD2Twov8b_POST
4126
0
    UINT64_C(1279296512), // LD2Twov8h
4127
0
    UINT64_C(1287685120), // LD2Twov8h_POST
4128
0
    UINT64_C(2770386944), // LD2W
4129
0
    UINT64_C(2770395136), // LD2W_IMM
4130
0
    UINT64_C(224411648),  // LD2i16
4131
0
    UINT64_C(232800256),  // LD2i16_POST
4132
0
    UINT64_C(224428032),  // LD2i32
4133
0
    UINT64_C(232816640),  // LD2i32_POST
4134
0
    UINT64_C(224429056),  // LD2i64
4135
0
    UINT64_C(232817664),  // LD2i64_POST
4136
0
    UINT64_C(224395264),  // LD2i8
4137
0
    UINT64_C(232783872),  // LD2i8_POST
4138
0
    UINT64_C(2755706880), // LD3B
4139
0
    UINT64_C(2755715072), // LD3B_IMM
4140
0
    UINT64_C(2780872704), // LD3D
4141
0
    UINT64_C(2780880896), // LD3D_IMM
4142
0
    UINT64_C(2764095488), // LD3H
4143
0
    UINT64_C(2764103680), // LD3H_IMM
4144
0
    UINT64_C(2770370560), // LD3Q
4145
0
    UINT64_C(2769346560), // LD3Q_IMM
4146
0
    UINT64_C(1296097280), // LD3Rv16b
4147
0
    UINT64_C(1304485888), // LD3Rv16b_POST
4148
0
    UINT64_C(222358528),  // LD3Rv1d
4149
0
    UINT64_C(230747136),  // LD3Rv1d_POST
4150
0
    UINT64_C(1296100352), // LD3Rv2d
4151
0
    UINT64_C(1304488960), // LD3Rv2d_POST
4152
0
    UINT64_C(222357504),  // LD3Rv2s
4153
0
    UINT64_C(230746112),  // LD3Rv2s_POST
4154
0
    UINT64_C(222356480),  // LD3Rv4h
4155
0
    UINT64_C(230745088),  // LD3Rv4h_POST
4156
0
    UINT64_C(1296099328), // LD3Rv4s
4157
0
    UINT64_C(1304487936), // LD3Rv4s_POST
4158
0
    UINT64_C(222355456),  // LD3Rv8b
4159
0
    UINT64_C(230744064),  // LD3Rv8b_POST
4160
0
    UINT64_C(1296098304), // LD3Rv8h
4161
0
    UINT64_C(1304486912), // LD3Rv8h_POST
4162
0
    UINT64_C(1279279104), // LD3Threev16b
4163
0
    UINT64_C(1287667712), // LD3Threev16b_POST
4164
0
    UINT64_C(1279282176), // LD3Threev2d
4165
0
    UINT64_C(1287670784), // LD3Threev2d_POST
4166
0
    UINT64_C(205539328),  // LD3Threev2s
4167
0
    UINT64_C(213927936),  // LD3Threev2s_POST
4168
0
    UINT64_C(205538304),  // LD3Threev4h
4169
0
    UINT64_C(213926912),  // LD3Threev4h_POST
4170
0
    UINT64_C(1279281152), // LD3Threev4s
4171
0
    UINT64_C(1287669760), // LD3Threev4s_POST
4172
0
    UINT64_C(205537280),  // LD3Threev8b
4173
0
    UINT64_C(213925888),  // LD3Threev8b_POST
4174
0
    UINT64_C(1279280128), // LD3Threev8h
4175
0
    UINT64_C(1287668736), // LD3Threev8h_POST
4176
0
    UINT64_C(2772484096), // LD3W
4177
0
    UINT64_C(2772492288), // LD3W_IMM
4178
0
    UINT64_C(222322688),  // LD3i16
4179
0
    UINT64_C(230711296),  // LD3i16_POST
4180
0
    UINT64_C(222339072),  // LD3i32
4181
0
    UINT64_C(230727680),  // LD3i32_POST
4182
0
    UINT64_C(222340096),  // LD3i64
4183
0
    UINT64_C(230728704),  // LD3i64_POST
4184
0
    UINT64_C(222306304),  // LD3i8
4185
0
    UINT64_C(230694912),  // LD3i8_POST
4186
0
    UINT64_C(2757804032), // LD4B
4187
0
    UINT64_C(2757812224), // LD4B_IMM
4188
0
    UINT64_C(2782969856), // LD4D
4189
0
    UINT64_C(2782978048), // LD4D_IMM
4190
0
    UINT64_C(1279262720), // LD4Fourv16b
4191
0
    UINT64_C(1287651328), // LD4Fourv16b_POST
4192
0
    UINT64_C(1279265792), // LD4Fourv2d
4193
0
    UINT64_C(1287654400), // LD4Fourv2d_POST
4194
0
    UINT64_C(205522944),  // LD4Fourv2s
4195
0
    UINT64_C(213911552),  // LD4Fourv2s_POST
4196
0
    UINT64_C(205521920),  // LD4Fourv4h
4197
0
    UINT64_C(213910528),  // LD4Fourv4h_POST
4198
0
    UINT64_C(1279264768), // LD4Fourv4s
4199
0
    UINT64_C(1287653376), // LD4Fourv4s_POST
4200
0
    UINT64_C(205520896),  // LD4Fourv8b
4201
0
    UINT64_C(213909504),  // LD4Fourv8b_POST
4202
0
    UINT64_C(1279263744), // LD4Fourv8h
4203
0
    UINT64_C(1287652352), // LD4Fourv8h_POST
4204
0
    UINT64_C(2766192640), // LD4H
4205
0
    UINT64_C(2766200832), // LD4H_IMM
4206
0
    UINT64_C(2778759168), // LD4Q
4207
0
    UINT64_C(2777735168), // LD4Q_IMM
4208
0
    UINT64_C(1298194432), // LD4Rv16b
4209
0
    UINT64_C(1306583040), // LD4Rv16b_POST
4210
0
    UINT64_C(224455680),  // LD4Rv1d
4211
0
    UINT64_C(232844288),  // LD4Rv1d_POST
4212
0
    UINT64_C(1298197504), // LD4Rv2d
4213
0
    UINT64_C(1306586112), // LD4Rv2d_POST
4214
0
    UINT64_C(224454656),  // LD4Rv2s
4215
0
    UINT64_C(232843264),  // LD4Rv2s_POST
4216
0
    UINT64_C(224453632),  // LD4Rv4h
4217
0
    UINT64_C(232842240),  // LD4Rv4h_POST
4218
0
    UINT64_C(1298196480), // LD4Rv4s
4219
0
    UINT64_C(1306585088), // LD4Rv4s_POST
4220
0
    UINT64_C(224452608),  // LD4Rv8b
4221
0
    UINT64_C(232841216),  // LD4Rv8b_POST
4222
0
    UINT64_C(1298195456), // LD4Rv8h
4223
0
    UINT64_C(1306584064), // LD4Rv8h_POST
4224
0
    UINT64_C(2774581248), // LD4W
4225
0
    UINT64_C(2774589440), // LD4W_IMM
4226
0
    UINT64_C(224419840),  // LD4i16
4227
0
    UINT64_C(232808448),  // LD4i16_POST
4228
0
    UINT64_C(224436224),  // LD4i32
4229
0
    UINT64_C(232824832),  // LD4i32_POST
4230
0
    UINT64_C(224437248),  // LD4i64
4231
0
    UINT64_C(232825856),  // LD4i64_POST
4232
0
    UINT64_C(224403456),  // LD4i8
4233
0
    UINT64_C(232792064),  // LD4i8_POST
4234
0
    UINT64_C(4164931584), // LD64B
4235
0
    UINT64_C(950009856),  // LDADDAB
4236
0
    UINT64_C(2023751680), // LDADDAH
4237
0
    UINT64_C(954204160),  // LDADDALB
4238
0
    UINT64_C(2027945984), // LDADDALH
4239
0
    UINT64_C(3101687808), // LDADDALW
4240
0
    UINT64_C(4175429632), // LDADDALX
4241
0
    UINT64_C(3097493504), // LDADDAW
4242
0
    UINT64_C(4171235328), // LDADDAX
4243
0
    UINT64_C(941621248),  // LDADDB
4244
0
    UINT64_C(2015363072), // LDADDH
4245
0
    UINT64_C(945815552),  // LDADDLB
4246
0
    UINT64_C(2019557376), // LDADDLH
4247
0
    UINT64_C(3093299200), // LDADDLW
4248
0
    UINT64_C(4167041024), // LDADDLX
4249
0
    UINT64_C(3089104896), // LDADDW
4250
0
    UINT64_C(4162846720), // LDADDX
4251
0
    UINT64_C(222397440),  // LDAP1
4252
0
    UINT64_C(952090624),  // LDAPRB
4253
0
    UINT64_C(2025832448), // LDAPRH
4254
0
    UINT64_C(3099574272), // LDAPRW
4255
0
    UINT64_C(2579499008), // LDAPRWpre
4256
0
    UINT64_C(4173316096), // LDAPRX
4257
0
    UINT64_C(3653240832), // LDAPRXpre
4258
0
    UINT64_C(423624704),  // LDAPURBi
4259
0
    UINT64_C(1497366528), // LDAPURHi
4260
0
    UINT64_C(432013312),  // LDAPURSBWi
4261
0
    UINT64_C(427819008),  // LDAPURSBXi
4262
0
    UINT64_C(1505755136), // LDAPURSHWi
4263
0
    UINT64_C(1501560832), // LDAPURSHXi
4264
0
    UINT64_C(2575302656), // LDAPURSWi
4265
0
    UINT64_C(3644850176), // LDAPURXi
4266
0
    UINT64_C(490735616),  // LDAPURbi
4267
0
    UINT64_C(3711961088), // LDAPURdi
4268
0
    UINT64_C(1564477440), // LDAPURhi
4269
0
    UINT64_C(2571108352), // LDAPURi
4270
0
    UINT64_C(499124224),  // LDAPURqi
4271
0
    UINT64_C(2638219264), // LDAPURsi
4272
0
    UINT64_C(148896768),  // LDARB
4273
0
    UINT64_C(1222638592), // LDARH
4274
0
    UINT64_C(2296380416), // LDARW
4275
0
    UINT64_C(3370122240), // LDARX
4276
0
    UINT64_C(2288025600), // LDAXPW
4277
0
    UINT64_C(3361767424), // LDAXPX
4278
0
    UINT64_C(140508160),  // LDAXRB
4279
0
    UINT64_C(1214249984), // LDAXRH
4280
0
    UINT64_C(2287991808), // LDAXRW
4281
0
    UINT64_C(3361733632), // LDAXRX
4282
0
    UINT64_C(950013952),  // LDCLRAB
4283
0
    UINT64_C(2023755776), // LDCLRAH
4284
0
    UINT64_C(954208256),  // LDCLRALB
4285
0
    UINT64_C(2027950080), // LDCLRALH
4286
0
    UINT64_C(3101691904), // LDCLRALW
4287
0
    UINT64_C(4175433728), // LDCLRALX
4288
0
    UINT64_C(3097497600), // LDCLRAW
4289
0
    UINT64_C(4171239424), // LDCLRAX
4290
0
    UINT64_C(941625344),  // LDCLRB
4291
0
    UINT64_C(2015367168), // LDCLRH
4292
0
    UINT64_C(945819648),  // LDCLRLB
4293
0
    UINT64_C(2019561472), // LDCLRLH
4294
0
    UINT64_C(3093303296), // LDCLRLW
4295
0
    UINT64_C(4167045120), // LDCLRLX
4296
0
    UINT64_C(421531648),  // LDCLRP
4297
0
    UINT64_C(429920256),  // LDCLRPA
4298
0
    UINT64_C(434114560),  // LDCLRPAL
4299
0
    UINT64_C(425725952),  // LDCLRPL
4300
0
    UINT64_C(3089108992), // LDCLRW
4301
0
    UINT64_C(4162850816), // LDCLRX
4302
0
    UINT64_C(950018048),  // LDEORAB
4303
0
    UINT64_C(2023759872), // LDEORAH
4304
0
    UINT64_C(954212352),  // LDEORALB
4305
0
    UINT64_C(2027954176), // LDEORALH
4306
0
    UINT64_C(3101696000), // LDEORALW
4307
0
    UINT64_C(4175437824), // LDEORALX
4308
0
    UINT64_C(3097501696), // LDEORAW
4309
0
    UINT64_C(4171243520), // LDEORAX
4310
0
    UINT64_C(941629440),  // LDEORB
4311
0
    UINT64_C(2015371264), // LDEORH
4312
0
    UINT64_C(945823744),  // LDEORLB
4313
0
    UINT64_C(2019565568), // LDEORLH
4314
0
    UINT64_C(3093307392), // LDEORLW
4315
0
    UINT64_C(4167049216), // LDEORLX
4316
0
    UINT64_C(3089113088), // LDEORW
4317
0
    UINT64_C(4162854912), // LDEORX
4318
0
    UINT64_C(2757779456), // LDFF1B_D_REAL
4319
0
    UINT64_C(2753585152), // LDFF1B_H_REAL
4320
0
    UINT64_C(2751488000), // LDFF1B_REAL
4321
0
    UINT64_C(2755682304), // LDFF1B_S_REAL
4322
0
    UINT64_C(2782945280), // LDFF1D_REAL
4323
0
    UINT64_C(2766168064), // LDFF1H_D_REAL
4324
0
    UINT64_C(2761973760), // LDFF1H_REAL
4325
0
    UINT64_C(2764070912), // LDFF1H_S_REAL
4326
0
    UINT64_C(2776653824), // LDFF1SB_D_REAL
4327
0
    UINT64_C(2780848128), // LDFF1SB_H_REAL
4328
0
    UINT64_C(2778750976), // LDFF1SB_S_REAL
4329
0
    UINT64_C(2768265216), // LDFF1SH_D_REAL
4330
0
    UINT64_C(2770362368), // LDFF1SH_S_REAL
4331
0
    UINT64_C(2759876608), // LDFF1SW_D_REAL
4332
0
    UINT64_C(2774556672), // LDFF1W_D_REAL
4333
0
    UINT64_C(2772459520), // LDFF1W_REAL
4334
0
    UINT64_C(3646947328), // LDG
4335
0
    UINT64_C(3655335936), // LDGM
4336
0
    UINT64_C(2571114496), // LDIAPPW
4337
0
    UINT64_C(2571110400), // LDIAPPWpre
4338
0
    UINT64_C(3644856320), // LDIAPPX
4339
0
    UINT64_C(3644852224), // LDIAPPXpre
4340
0
    UINT64_C(148864000),  // LDLARB
4341
0
    UINT64_C(1222605824), // LDLARH
4342
0
    UINT64_C(2296347648), // LDLARW
4343
0
    UINT64_C(3370089472), // LDLARX
4344
0
    UINT64_C(2758844416), // LDNF1B_D_IMM_REAL
4345
0
    UINT64_C(2754650112), // LDNF1B_H_IMM_REAL
4346
0
    UINT64_C(2752552960), // LDNF1B_IMM_REAL
4347
0
    UINT64_C(2756747264), // LDNF1B_S_IMM_REAL
4348
0
    UINT64_C(2784010240), // LDNF1D_IMM_REAL
4349
0
    UINT64_C(2767233024), // LDNF1H_D_IMM_REAL
4350
0
    UINT64_C(2763038720), // LDNF1H_IMM_REAL
4351
0
    UINT64_C(2765135872), // LDNF1H_S_IMM_REAL
4352
0
    UINT64_C(2777718784), // LDNF1SB_D_IMM_REAL
4353
0
    UINT64_C(2781913088), // LDNF1SB_H_IMM_REAL
4354
0
    UINT64_C(2779815936), // LDNF1SB_S_IMM_REAL
4355
0
    UINT64_C(2769330176), // LDNF1SH_D_IMM_REAL
4356
0
    UINT64_C(2771427328), // LDNF1SH_S_IMM_REAL
4357
0
    UINT64_C(2760941568), // LDNF1SW_D_IMM_REAL
4358
0
    UINT64_C(2775621632), // LDNF1W_D_IMM_REAL
4359
0
    UINT64_C(2773524480), // LDNF1W_IMM_REAL
4360
0
    UINT64_C(1816133632), // LDNPDi
4361
0
    UINT64_C(2889875456), // LDNPQi
4362
0
    UINT64_C(742391808),  // LDNPSi
4363
0
    UINT64_C(675282944),  // LDNPWi
4364
0
    UINT64_C(2822766592), // LDNPXi
4365
0
    UINT64_C(2684354561), // LDNT1B_2Z
4366
0
    UINT64_C(2688548865), // LDNT1B_2Z_IMM
4367
0
    UINT64_C(2701131784), // LDNT1B_2Z_STRIDED
4368
0
    UINT64_C(2705326088), // LDNT1B_2Z_STRIDED_IMM
4369
0
    UINT64_C(2684387329), // LDNT1B_4Z
4370
0
    UINT64_C(2688581633), // LDNT1B_4Z_IMM
4371
0
    UINT64_C(2701164552), // LDNT1B_4Z_STRIDED
4372
0
    UINT64_C(2705358856), // LDNT1B_4Z_STRIDED_IMM
4373
0
    UINT64_C(2751520768), // LDNT1B_ZRI
4374
0
    UINT64_C(2751512576), // LDNT1B_ZRR
4375
0
    UINT64_C(3288383488), // LDNT1B_ZZR_D_REAL
4376
0
    UINT64_C(2214633472), // LDNT1B_ZZR_S_REAL
4377
0
    UINT64_C(2684379137), // LDNT1D_2Z
4378
0
    UINT64_C(2688573441), // LDNT1D_2Z_IMM
4379
0
    UINT64_C(2701156360), // LDNT1D_2Z_STRIDED
4380
0
    UINT64_C(2705350664), // LDNT1D_2Z_STRIDED_IMM
4381
0
    UINT64_C(2684411905), // LDNT1D_4Z
4382
0
    UINT64_C(2688606209), // LDNT1D_4Z_IMM
4383
0
    UINT64_C(2701189128), // LDNT1D_4Z_STRIDED
4384
0
    UINT64_C(2705383432), // LDNT1D_4Z_STRIDED_IMM
4385
0
    UINT64_C(2776686592), // LDNT1D_ZRI
4386
0
    UINT64_C(2776678400), // LDNT1D_ZRR
4387
0
    UINT64_C(3313549312), // LDNT1D_ZZR_D_REAL
4388
0
    UINT64_C(2684362753), // LDNT1H_2Z
4389
0
    UINT64_C(2688557057), // LDNT1H_2Z_IMM
4390
0
    UINT64_C(2701139976), // LDNT1H_2Z_STRIDED
4391
0
    UINT64_C(2705334280), // LDNT1H_2Z_STRIDED_IMM
4392
0
    UINT64_C(2684395521), // LDNT1H_4Z
4393
0
    UINT64_C(2688589825), // LDNT1H_4Z_IMM
4394
0
    UINT64_C(2701172744), // LDNT1H_4Z_STRIDED
4395
0
    UINT64_C(2705367048), // LDNT1H_4Z_STRIDED_IMM
4396
0
    UINT64_C(2759909376), // LDNT1H_ZRI
4397
0
    UINT64_C(2759901184), // LDNT1H_ZRR
4398
0
    UINT64_C(3296772096), // LDNT1H_ZZR_D_REAL
4399
0
    UINT64_C(2223022080), // LDNT1H_ZZR_S_REAL
4400
0
    UINT64_C(3288367104), // LDNT1SB_ZZR_D_REAL
4401
0
    UINT64_C(2214625280), // LDNT1SB_ZZR_S_REAL
4402
0
    UINT64_C(3296755712), // LDNT1SH_ZZR_D_REAL
4403
0
    UINT64_C(2223013888), // LDNT1SH_ZZR_S_REAL
4404
0
    UINT64_C(3305144320), // LDNT1SW_ZZR_D_REAL
4405
0
    UINT64_C(2684370945), // LDNT1W_2Z
4406
0
    UINT64_C(2688565249), // LDNT1W_2Z_IMM
4407
0
    UINT64_C(2701148168), // LDNT1W_2Z_STRIDED
4408
0
    UINT64_C(2705342472), // LDNT1W_2Z_STRIDED_IMM
4409
0
    UINT64_C(2684403713), // LDNT1W_4Z
4410
0
    UINT64_C(2688598017), // LDNT1W_4Z_IMM
4411
0
    UINT64_C(2701180936), // LDNT1W_4Z_STRIDED
4412
0
    UINT64_C(2705375240), // LDNT1W_4Z_STRIDED_IMM
4413
0
    UINT64_C(2768297984), // LDNT1W_ZRI
4414
0
    UINT64_C(2768289792), // LDNT1W_ZRR
4415
0
    UINT64_C(3305160704), // LDNT1W_ZZR_D_REAL
4416
0
    UINT64_C(2231410688), // LDNT1W_ZZR_S_REAL
4417
0
    UINT64_C(1832910848), // LDPDi
4418
0
    UINT64_C(1824522240), // LDPDpost
4419
0
    UINT64_C(1841299456), // LDPDpre
4420
0
    UINT64_C(2906652672), // LDPQi
4421
0
    UINT64_C(2898264064), // LDPQpost
4422
0
    UINT64_C(2915041280), // LDPQpre
4423
0
    UINT64_C(1765801984), // LDPSWi
4424
0
    UINT64_C(1757413376), // LDPSWpost
4425
0
    UINT64_C(1774190592), // LDPSWpre
4426
0
    UINT64_C(759169024),  // LDPSi
4427
0
    UINT64_C(750780416),  // LDPSpost
4428
0
    UINT64_C(767557632),  // LDPSpre
4429
0
    UINT64_C(692060160),  // LDPWi
4430
0
    UINT64_C(683671552),  // LDPWpost
4431
0
    UINT64_C(700448768),  // LDPWpre
4432
0
    UINT64_C(2839543808), // LDPXi
4433
0
    UINT64_C(2831155200), // LDPXpost
4434
0
    UINT64_C(2847932416), // LDPXpre
4435
0
    UINT64_C(4162847744), // LDRAAindexed
4436
0
    UINT64_C(4162849792), // LDRAAwriteback
4437
0
    UINT64_C(4171236352), // LDRABindexed
4438
0
    UINT64_C(4171238400), // LDRABwriteback
4439
0
    UINT64_C(943719424),  // LDRBBpost
4440
0
    UINT64_C(943721472),  // LDRBBpre
4441
0
    UINT64_C(945833984),  // LDRBBroW
4442
0
    UINT64_C(945842176),  // LDRBBroX
4443
0
    UINT64_C(960495616),  // LDRBBui
4444
0
    UINT64_C(1010828288), // LDRBpost
4445
0
    UINT64_C(1010830336), // LDRBpre
4446
0
    UINT64_C(1012942848), // LDRBroW
4447
0
    UINT64_C(1012951040), // LDRBroX
4448
0
    UINT64_C(1027604480), // LDRBui
4449
0
    UINT64_C(1543503872), // LDRDl
4450
0
    UINT64_C(4232053760), // LDRDpost
4451
0
    UINT64_C(4232055808), // LDRDpre
4452
0
    UINT64_C(4234168320), // LDRDroW
4453
0
    UINT64_C(4234176512), // LDRDroX
4454
0
    UINT64_C(4248829952), // LDRDui
4455
0
    UINT64_C(2017461248), // LDRHHpost
4456
0
    UINT64_C(2017463296), // LDRHHpre
4457
0
    UINT64_C(2019575808), // LDRHHroW
4458
0
    UINT64_C(2019584000), // LDRHHroX
4459
0
    UINT64_C(2034237440), // LDRHHui
4460
0
    UINT64_C(2084570112), // LDRHpost
4461
0
    UINT64_C(2084572160), // LDRHpre
4462
0
    UINT64_C(2086684672), // LDRHroW
4463
0
    UINT64_C(2086692864), // LDRHroX
4464
0
    UINT64_C(2101346304), // LDRHui
4465
0
    UINT64_C(2617245696), // LDRQl
4466
0
    UINT64_C(1019216896), // LDRQpost
4467
0
    UINT64_C(1019218944), // LDRQpre
4468
0
    UINT64_C(1021331456), // LDRQroW
4469
0
    UINT64_C(1021339648), // LDRQroX
4470
0
    UINT64_C(1035993088), // LDRQui
4471
0
    UINT64_C(952108032),  // LDRSBWpost
4472
0
    UINT64_C(952110080),  // LDRSBWpre
4473
0
    UINT64_C(954222592),  // LDRSBWroW
4474
0
    UINT64_C(954230784),  // LDRSBWroX
4475
0
    UINT64_C(968884224),  // LDRSBWui
4476
0
    UINT64_C(947913728),  // LDRSBXpost
4477
0
    UINT64_C(947915776),  // LDRSBXpre
4478
0
    UINT64_C(950028288),  // LDRSBXroW
4479
0
    UINT64_C(950036480),  // LDRSBXroX
4480
0
    UINT64_C(964689920),  // LDRSBXui
4481
0
    UINT64_C(2025849856), // LDRSHWpost
4482
0
    UINT64_C(2025851904), // LDRSHWpre
4483
0
    UINT64_C(2027964416), // LDRSHWroW
4484
0
    UINT64_C(2027972608), // LDRSHWroX
4485
0
    UINT64_C(2042626048), // LDRSHWui
4486
0
    UINT64_C(2021655552), // LDRSHXpost
4487
0
    UINT64_C(2021657600), // LDRSHXpre
4488
0
    UINT64_C(2023770112), // LDRSHXroW
4489
0
    UINT64_C(2023778304), // LDRSHXroX
4490
0
    UINT64_C(2038431744), // LDRSHXui
4491
0
    UINT64_C(2550136832), // LDRSWl
4492
0
    UINT64_C(3095397376), // LDRSWpost
4493
0
    UINT64_C(3095399424), // LDRSWpre
4494
0
    UINT64_C(3097511936), // LDRSWroW
4495
0
    UINT64_C(3097520128), // LDRSWroX
4496
0
    UINT64_C(3112173568), // LDRSWui
4497
0
    UINT64_C(469762048),  // LDRSl
4498
0
    UINT64_C(3158311936), // LDRSpost
4499
0
    UINT64_C(3158313984), // LDRSpre
4500
0
    UINT64_C(3160426496), // LDRSroW
4501
0
    UINT64_C(3160434688), // LDRSroX
4502
0
    UINT64_C(3175088128), // LDRSui
4503
0
    UINT64_C(402653184),  // LDRWl
4504
0
    UINT64_C(3091203072), // LDRWpost
4505
0
    UINT64_C(3091205120), // LDRWpre
4506
0
    UINT64_C(3093317632), // LDRWroW
4507
0
    UINT64_C(3093325824), // LDRWroX
4508
0
    UINT64_C(3107979264), // LDRWui
4509
0
    UINT64_C(1476395008), // LDRXl
4510
0
    UINT64_C(4164944896), // LDRXpost
4511
0
    UINT64_C(4164946944), // LDRXpre
4512
0
    UINT64_C(4167059456), // LDRXroW
4513
0
    UINT64_C(4167067648), // LDRXroX
4514
0
    UINT64_C(4181721088), // LDRXui
4515
0
    UINT64_C(2239758336), // LDR_PXI
4516
0
    UINT64_C(3776937984), // LDR_TX
4517
0
    UINT64_C(3774873600), // LDR_ZA
4518
0
    UINT64_C(2239774720), // LDR_ZXI
4519
0
    UINT64_C(950022144),  // LDSETAB
4520
0
    UINT64_C(2023763968), // LDSETAH
4521
0
    UINT64_C(954216448),  // LDSETALB
4522
0
    UINT64_C(2027958272), // LDSETALH
4523
0
    UINT64_C(3101700096), // LDSETALW
4524
0
    UINT64_C(4175441920), // LDSETALX
4525
0
    UINT64_C(3097505792), // LDSETAW
4526
0
    UINT64_C(4171247616), // LDSETAX
4527
0
    UINT64_C(941633536),  // LDSETB
4528
0
    UINT64_C(2015375360), // LDSETH
4529
0
    UINT64_C(945827840),  // LDSETLB
4530
0
    UINT64_C(2019569664), // LDSETLH
4531
0
    UINT64_C(3093311488), // LDSETLW
4532
0
    UINT64_C(4167053312), // LDSETLX
4533
0
    UINT64_C(421539840),  // LDSETP
4534
0
    UINT64_C(429928448),  // LDSETPA
4535
0
    UINT64_C(434122752),  // LDSETPAL
4536
0
    UINT64_C(425734144),  // LDSETPL
4537
0
    UINT64_C(3089117184), // LDSETW
4538
0
    UINT64_C(4162859008), // LDSETX
4539
0
    UINT64_C(950026240),  // LDSMAXAB
4540
0
    UINT64_C(2023768064), // LDSMAXAH
4541
0
    UINT64_C(954220544),  // LDSMAXALB
4542
0
    UINT64_C(2027962368), // LDSMAXALH
4543
0
    UINT64_C(3101704192), // LDSMAXALW
4544
0
    UINT64_C(4175446016), // LDSMAXALX
4545
0
    UINT64_C(3097509888), // LDSMAXAW
4546
0
    UINT64_C(4171251712), // LDSMAXAX
4547
0
    UINT64_C(941637632),  // LDSMAXB
4548
0
    UINT64_C(2015379456), // LDSMAXH
4549
0
    UINT64_C(945831936),  // LDSMAXLB
4550
0
    UINT64_C(2019573760), // LDSMAXLH
4551
0
    UINT64_C(3093315584), // LDSMAXLW
4552
0
    UINT64_C(4167057408), // LDSMAXLX
4553
0
    UINT64_C(3089121280), // LDSMAXW
4554
0
    UINT64_C(4162863104), // LDSMAXX
4555
0
    UINT64_C(950030336),  // LDSMINAB
4556
0
    UINT64_C(2023772160), // LDSMINAH
4557
0
    UINT64_C(954224640),  // LDSMINALB
4558
0
    UINT64_C(2027966464), // LDSMINALH
4559
0
    UINT64_C(3101708288), // LDSMINALW
4560
0
    UINT64_C(4175450112), // LDSMINALX
4561
0
    UINT64_C(3097513984), // LDSMINAW
4562
0
    UINT64_C(4171255808), // LDSMINAX
4563
0
    UINT64_C(941641728),  // LDSMINB
4564
0
    UINT64_C(2015383552), // LDSMINH
4565
0
    UINT64_C(945836032),  // LDSMINLB
4566
0
    UINT64_C(2019577856), // LDSMINLH
4567
0
    UINT64_C(3093319680), // LDSMINLW
4568
0
    UINT64_C(4167061504), // LDSMINLX
4569
0
    UINT64_C(3089125376), // LDSMINW
4570
0
    UINT64_C(4162867200), // LDSMINX
4571
0
    UINT64_C(943720448),  // LDTRBi
4572
0
    UINT64_C(2017462272), // LDTRHi
4573
0
    UINT64_C(952109056),  // LDTRSBWi
4574
0
    UINT64_C(947914752),  // LDTRSBXi
4575
0
    UINT64_C(2025850880), // LDTRSHWi
4576
0
    UINT64_C(2021656576), // LDTRSHXi
4577
0
    UINT64_C(3095398400), // LDTRSWi
4578
0
    UINT64_C(3091204096), // LDTRWi
4579
0
    UINT64_C(4164945920), // LDTRXi
4580
0
    UINT64_C(950034432),  // LDUMAXAB
4581
0
    UINT64_C(2023776256), // LDUMAXAH
4582
0
    UINT64_C(954228736),  // LDUMAXALB
4583
0
    UINT64_C(2027970560), // LDUMAXALH
4584
0
    UINT64_C(3101712384), // LDUMAXALW
4585
0
    UINT64_C(4175454208), // LDUMAXALX
4586
0
    UINT64_C(3097518080), // LDUMAXAW
4587
0
    UINT64_C(4171259904), // LDUMAXAX
4588
0
    UINT64_C(941645824),  // LDUMAXB
4589
0
    UINT64_C(2015387648), // LDUMAXH
4590
0
    UINT64_C(945840128),  // LDUMAXLB
4591
0
    UINT64_C(2019581952), // LDUMAXLH
4592
0
    UINT64_C(3093323776), // LDUMAXLW
4593
0
    UINT64_C(4167065600), // LDUMAXLX
4594
0
    UINT64_C(3089129472), // LDUMAXW
4595
0
    UINT64_C(4162871296), // LDUMAXX
4596
0
    UINT64_C(950038528),  // LDUMINAB
4597
0
    UINT64_C(2023780352), // LDUMINAH
4598
0
    UINT64_C(954232832),  // LDUMINALB
4599
0
    UINT64_C(2027974656), // LDUMINALH
4600
0
    UINT64_C(3101716480), // LDUMINALW
4601
0
    UINT64_C(4175458304), // LDUMINALX
4602
0
    UINT64_C(3097522176), // LDUMINAW
4603
0
    UINT64_C(4171264000), // LDUMINAX
4604
0
    UINT64_C(941649920),  // LDUMINB
4605
0
    UINT64_C(2015391744), // LDUMINH
4606
0
    UINT64_C(945844224),  // LDUMINLB
4607
0
    UINT64_C(2019586048), // LDUMINLH
4608
0
    UINT64_C(3093327872), // LDUMINLW
4609
0
    UINT64_C(4167069696), // LDUMINLX
4610
0
    UINT64_C(3089133568), // LDUMINW
4611
0
    UINT64_C(4162875392), // LDUMINX
4612
0
    UINT64_C(943718400),  // LDURBBi
4613
0
    UINT64_C(1010827264), // LDURBi
4614
0
    UINT64_C(4232052736), // LDURDi
4615
0
    UINT64_C(2017460224), // LDURHHi
4616
0
    UINT64_C(2084569088), // LDURHi
4617
0
    UINT64_C(1019215872), // LDURQi
4618
0
    UINT64_C(952107008),  // LDURSBWi
4619
0
    UINT64_C(947912704),  // LDURSBXi
4620
0
    UINT64_C(2025848832), // LDURSHWi
4621
0
    UINT64_C(2021654528), // LDURSHXi
4622
0
    UINT64_C(3095396352), // LDURSWi
4623
0
    UINT64_C(3158310912), // LDURSi
4624
0
    UINT64_C(3091202048), // LDURWi
4625
0
    UINT64_C(4164943872), // LDURXi
4626
0
    UINT64_C(2287992832), // LDXPW
4627
0
    UINT64_C(3361734656), // LDXPX
4628
0
    UINT64_C(140475392),  // LDXRB
4629
0
    UINT64_C(1214217216), // LDXRH
4630
0
    UINT64_C(2287959040), // LDXRW
4631
0
    UINT64_C(3361700864), // LDXRX
4632
0
    UINT64_C(68648960), // LSLR_ZPmZ_B
4633
0
    UINT64_C(81231872), // LSLR_ZPmZ_D
4634
0
    UINT64_C(72843264), // LSLR_ZPmZ_H
4635
0
    UINT64_C(77037568), // LSLR_ZPmZ_S
4636
0
    UINT64_C(448798720),  // LSLVWr
4637
0
    UINT64_C(2596282368), // LSLVXr
4638
0
    UINT64_C(68911104), // LSL_WIDE_ZPmZ_B
4639
0
    UINT64_C(73105408), // LSL_WIDE_ZPmZ_H
4640
0
    UINT64_C(77299712), // LSL_WIDE_ZPmZ_S
4641
0
    UINT64_C(69241856), // LSL_WIDE_ZZZ_B
4642
0
    UINT64_C(73436160), // LSL_WIDE_ZZZ_H
4643
0
    UINT64_C(77630464), // LSL_WIDE_ZZZ_S
4644
0
    UINT64_C(67338496), // LSL_ZPmI_B
4645
0
    UINT64_C(75726848), // LSL_ZPmI_D
4646
0
    UINT64_C(67338752), // LSL_ZPmI_H
4647
0
    UINT64_C(71532544), // LSL_ZPmI_S
4648
0
    UINT64_C(68386816), // LSL_ZPmZ_B
4649
0
    UINT64_C(80969728), // LSL_ZPmZ_D
4650
0
    UINT64_C(72581120), // LSL_ZPmZ_H
4651
0
    UINT64_C(76775424), // LSL_ZPmZ_S
4652
0
    UINT64_C(69770240), // LSL_ZZI_B
4653
0
    UINT64_C(77634560), // LSL_ZZI_D
4654
0
    UINT64_C(70294528), // LSL_ZZI_H
4655
0
    UINT64_C(73440256), // LSL_ZZI_S
4656
0
    UINT64_C(68517888), // LSRR_ZPmZ_B
4657
0
    UINT64_C(81100800), // LSRR_ZPmZ_D
4658
0
    UINT64_C(72712192), // LSRR_ZPmZ_H
4659
0
    UINT64_C(76906496), // LSRR_ZPmZ_S
4660
0
    UINT64_C(448799744),  // LSRVWr
4661
0
    UINT64_C(2596283392), // LSRVXr
4662
0
    UINT64_C(68780032), // LSR_WIDE_ZPmZ_B
4663
0
    UINT64_C(72974336), // LSR_WIDE_ZPmZ_H
4664
0
    UINT64_C(77168640), // LSR_WIDE_ZPmZ_S
4665
0
    UINT64_C(69239808), // LSR_WIDE_ZZZ_B
4666
0
    UINT64_C(73434112), // LSR_WIDE_ZZZ_H
4667
0
    UINT64_C(77628416), // LSR_WIDE_ZZZ_S
4668
0
    UINT64_C(67207424), // LSR_ZPmI_B
4669
0
    UINT64_C(75595776), // LSR_ZPmI_D
4670
0
    UINT64_C(67207680), // LSR_ZPmI_H
4671
0
    UINT64_C(71401472), // LSR_ZPmI_S
4672
0
    UINT64_C(68255744), // LSR_ZPmZ_B
4673
0
    UINT64_C(80838656), // LSR_ZPmZ_D
4674
0
    UINT64_C(72450048), // LSR_ZPmZ_H
4675
0
    UINT64_C(76644352), // LSR_ZPmZ_S
4676
0
    UINT64_C(69768192), // LSR_ZZI_B
4677
0
    UINT64_C(77632512), // LSR_ZZI_D
4678
0
    UINT64_C(70292480), // LSR_ZZI_H
4679
0
    UINT64_C(73438208), // LSR_ZZI_S
4680
0
    UINT64_C(1317015552), // LUT2v16f8
4681
0
    UINT64_C(1321205760), // LUT2v8f16
4682
0
    UINT64_C(1312825344), // LUT4v16f8
4683
0
    UINT64_C(1312821248), // LUT4v8f16
4684
0
    UINT64_C(3230416896), // LUTI2_2ZTZI_B
4685
0
    UINT64_C(3230420992), // LUTI2_2ZTZI_H
4686
0
    UINT64_C(3230425088), // LUTI2_2ZTZI_S
4687
0
    UINT64_C(3230433280), // LUTI2_4ZTZI_B
4688
0
    UINT64_C(3230437376), // LUTI2_4ZTZI_H
4689
0
    UINT64_C(3230441472), // LUTI2_4ZTZI_S
4690
0
    UINT64_C(3231465472), // LUTI2_S_2ZTZI_B
4691
0
    UINT64_C(3231469568), // LUTI2_S_2ZTZI_H
4692
0
    UINT64_C(3231481856), // LUTI2_S_4ZTZI_B
4693
0
    UINT64_C(3231485952), // LUTI2_S_4ZTZI_H
4694
0
    UINT64_C(3234594816), // LUTI2_ZTZI_B
4695
0
    UINT64_C(3234598912), // LUTI2_ZTZI_H
4696
0
    UINT64_C(3234603008), // LUTI2_ZTZI_S
4697
0
    UINT64_C(1159770112), // LUTI2_ZZZI_B
4698
0
    UINT64_C(1159768064), // LUTI2_ZZZI_H
4699
0
    UINT64_C(3230285824), // LUTI4_2ZTZI_B
4700
0
    UINT64_C(3230289920), // LUTI4_2ZTZI_H
4701
0
    UINT64_C(3230294016), // LUTI4_2ZTZI_S
4702
0
    UINT64_C(3230306304), // LUTI4_4ZTZI_H
4703
0
    UINT64_C(3230310400), // LUTI4_4ZTZI_S
4704
0
    UINT64_C(3230334976), // LUTI4_4ZZT2Z
4705
0
    UINT64_C(3231334400), // LUTI4_S_2ZTZI_B
4706
0
    UINT64_C(3231338496), // LUTI4_S_2ZTZI_H
4707
0
    UINT64_C(3231354880), // LUTI4_S_4ZTZI_H
4708
0
    UINT64_C(3231383552), // LUTI4_S_4ZZT2Z
4709
0
    UINT64_C(1159771136), // LUTI4_Z2ZZI_H
4710
0
    UINT64_C(3234463744), // LUTI4_ZTZI_B
4711
0
    UINT64_C(3234467840), // LUTI4_ZTZI_H
4712
0
    UINT64_C(3234471936), // LUTI4_ZTZI_S
4713
0
    UINT64_C(1163961344), // LUTI4_ZZZI_B
4714
0
    UINT64_C(1159773184), // LUTI4_ZZZI_H
4715
0
    UINT64_C(2606759936), // MADDPT
4716
0
    UINT64_C(452984832),  // MADDWrrr
4717
0
    UINT64_C(2600468480), // MADDXrrr
4718
0
    UINT64_C(1153488896), // MAD_CPA
4719
0
    UINT64_C(67158016), // MAD_ZPmZZ_B
4720
0
    UINT64_C(79740928), // MAD_ZPmZZ_D
4721
0
    UINT64_C(71352320), // MAD_ZPmZZ_H
4722
0
    UINT64_C(75546624), // MAD_ZPmZZ_S
4723
0
    UINT64_C(1159757824), // MATCH_PPzZZ_B
4724
0
    UINT64_C(1163952128), // MATCH_PPzZZ_H
4725
0
    UINT64_C(1153486848), // MLA_CPA
4726
0
    UINT64_C(67125248), // MLA_ZPmZZ_B
4727
0
    UINT64_C(79708160), // MLA_ZPmZZ_D
4728
0
    UINT64_C(71319552), // MLA_ZPmZZ_H
4729
0
    UINT64_C(75513856), // MLA_ZPmZZ_S
4730
0
    UINT64_C(1155532800), // MLA_ZZZI_D
4731
0
    UINT64_C(1142949888), // MLA_ZZZI_H
4732
0
    UINT64_C(1151338496), // MLA_ZZZI_S
4733
0
    UINT64_C(1310757888), // MLAv16i8
4734
0
    UINT64_C(245404672),  // MLAv2i32
4735
0
    UINT64_C(796917760),  // MLAv2i32_indexed
4736
0
    UINT64_C(241210368),  // MLAv4i16
4737
0
    UINT64_C(792723456),  // MLAv4i16_indexed
4738
0
    UINT64_C(1319146496), // MLAv4i32
4739
0
    UINT64_C(1870659584), // MLAv4i32_indexed
4740
0
    UINT64_C(1314952192), // MLAv8i16
4741
0
    UINT64_C(1866465280), // MLAv8i16_indexed
4742
0
    UINT64_C(237016064),  // MLAv8i8
4743
0
    UINT64_C(67133440), // MLS_ZPmZZ_B
4744
0
    UINT64_C(79716352), // MLS_ZPmZZ_D
4745
0
    UINT64_C(71327744), // MLS_ZPmZZ_H
4746
0
    UINT64_C(75522048), // MLS_ZPmZZ_S
4747
0
    UINT64_C(1155533824), // MLS_ZZZI_D
4748
0
    UINT64_C(1142950912), // MLS_ZZZI_H
4749
0
    UINT64_C(1151339520), // MLS_ZZZI_S
4750
0
    UINT64_C(1847628800), // MLSv16i8
4751
0
    UINT64_C(782275584),  // MLSv2i32
4752
0
    UINT64_C(796934144),  // MLSv2i32_indexed
4753
0
    UINT64_C(778081280),  // MLSv4i16
4754
0
    UINT64_C(792739840),  // MLSv4i16_indexed
4755
0
    UINT64_C(1856017408), // MLSv4i32
4756
0
    UINT64_C(1870675968), // MLSv4i32_indexed
4757
0
    UINT64_C(1851823104), // MLSv8i16
4758
0
    UINT64_C(1866481664), // MLSv8i16_indexed
4759
0
    UINT64_C(773886976),  // MLSv8i8
4760
0
    UINT64_C(499155968),  // MOPSSETGE
4761
0
    UINT64_C(499164160),  // MOPSSETGEN
4762
0
    UINT64_C(499160064),  // MOPSSETGET
4763
0
    UINT64_C(499168256),  // MOPSSETGETN
4764
0
    UINT64_C(3221619200), // MOVAZ_2ZMI_H_B
4765
0
    UINT64_C(3234202112), // MOVAZ_2ZMI_H_D
4766
0
    UINT64_C(3225813504), // MOVAZ_2ZMI_H_H
4767
0
    UINT64_C(3230007808), // MOVAZ_2ZMI_H_S
4768
0
    UINT64_C(3221651968), // MOVAZ_2ZMI_V_B
4769
0
    UINT64_C(3234234880), // MOVAZ_2ZMI_V_D
4770
0
    UINT64_C(3225846272), // MOVAZ_2ZMI_V_H
4771
0
    UINT64_C(3230040576), // MOVAZ_2ZMI_V_S
4772
0
    UINT64_C(3221620224), // MOVAZ_4ZMI_H_B
4773
0
    UINT64_C(3234203136), // MOVAZ_4ZMI_H_D
4774
0
    UINT64_C(3225814528), // MOVAZ_4ZMI_H_H
4775
0
    UINT64_C(3230008832), // MOVAZ_4ZMI_H_S
4776
0
    UINT64_C(3221652992), // MOVAZ_4ZMI_V_B
4777
0
    UINT64_C(3234235904), // MOVAZ_4ZMI_V_D
4778
0
    UINT64_C(3225847296), // MOVAZ_4ZMI_V_H
4779
0
    UINT64_C(3230041600), // MOVAZ_4ZMI_V_S
4780
0
    UINT64_C(3221621248), // MOVAZ_VG2_2ZM
4781
0
    UINT64_C(3221622272), // MOVAZ_VG4_4ZM
4782
0
    UINT64_C(3221357056), // MOVAZ_ZMI_H_B
4783
0
    UINT64_C(3233939968), // MOVAZ_ZMI_H_D
4784
0
    UINT64_C(3225551360), // MOVAZ_ZMI_H_H
4785
0
    UINT64_C(3234005504), // MOVAZ_ZMI_H_Q
4786
0
    UINT64_C(3229745664), // MOVAZ_ZMI_H_S
4787
0
    UINT64_C(3221389824), // MOVAZ_ZMI_V_B
4788
0
    UINT64_C(3233972736), // MOVAZ_ZMI_V_D
4789
0
    UINT64_C(3225584128), // MOVAZ_ZMI_V_H
4790
0
    UINT64_C(3234038272), // MOVAZ_ZMI_V_Q
4791
0
    UINT64_C(3229778432), // MOVAZ_ZMI_V_S
4792
0
    UINT64_C(3221618688), // MOVA_2ZMXI_H_B
4793
0
    UINT64_C(3234201600), // MOVA_2ZMXI_H_D
4794
0
    UINT64_C(3225812992), // MOVA_2ZMXI_H_H
4795
0
    UINT64_C(3230007296), // MOVA_2ZMXI_H_S
4796
0
    UINT64_C(3221651456), // MOVA_2ZMXI_V_B
4797
0
    UINT64_C(3234234368), // MOVA_2ZMXI_V_D
4798
0
    UINT64_C(3225845760), // MOVA_2ZMXI_V_H
4799
0
    UINT64_C(3230040064), // MOVA_2ZMXI_V_S
4800
0
    UINT64_C(3221619712), // MOVA_4ZMXI_H_B
4801
0
    UINT64_C(3234202624), // MOVA_4ZMXI_H_D
4802
0
    UINT64_C(3225814016), // MOVA_4ZMXI_H_H
4803
0
    UINT64_C(3230008320), // MOVA_4ZMXI_H_S
4804
0
    UINT64_C(3221652480), // MOVA_4ZMXI_V_B
4805
0
    UINT64_C(3234235392), // MOVA_4ZMXI_V_D
4806
0
    UINT64_C(3225846784), // MOVA_4ZMXI_V_H
4807
0
    UINT64_C(3230041088), // MOVA_4ZMXI_V_S
4808
0
    UINT64_C(3221487616), // MOVA_MXI2Z_H_B
4809
0
    UINT64_C(3234070528), // MOVA_MXI2Z_H_D
4810
0
    UINT64_C(3225681920), // MOVA_MXI2Z_H_H
4811
0
    UINT64_C(3229876224), // MOVA_MXI2Z_H_S
4812
0
    UINT64_C(3221520384), // MOVA_MXI2Z_V_B
4813
0
    UINT64_C(3234103296), // MOVA_MXI2Z_V_D
4814
0
    UINT64_C(3225714688), // MOVA_MXI2Z_V_H
4815
0
    UINT64_C(3229908992), // MOVA_MXI2Z_V_S
4816
0
    UINT64_C(3221488640), // MOVA_MXI4Z_H_B
4817
0
    UINT64_C(3234071552), // MOVA_MXI4Z_H_D
4818
0
    UINT64_C(3225682944), // MOVA_MXI4Z_H_H
4819
0
    UINT64_C(3229877248), // MOVA_MXI4Z_H_S
4820
0
    UINT64_C(3221521408), // MOVA_MXI4Z_V_B
4821
0
    UINT64_C(3234104320), // MOVA_MXI4Z_V_D
4822
0
    UINT64_C(3225715712), // MOVA_MXI4Z_V_H
4823
0
    UINT64_C(3229910016), // MOVA_MXI4Z_V_S
4824
0
    UINT64_C(3221620736), // MOVA_VG2_2ZMXI
4825
0
    UINT64_C(3221489664), // MOVA_VG2_MXI2Z
4826
0
    UINT64_C(3221621760), // MOVA_VG4_4ZMXI
4827
0
    UINT64_C(3221490688), // MOVA_VG4_MXI4Z
4828
0
    UINT64_C(788587520),  // MOVID
4829
0
    UINT64_C(1325458432), // MOVIv16b_ns
4830
0
    UINT64_C(1862329344), // MOVIv2d_ns
4831
0
    UINT64_C(251659264),  // MOVIv2i32
4832
0
    UINT64_C(251708416),  // MOVIv2s_msl
4833
0
    UINT64_C(251692032),  // MOVIv4i16
4834
0
    UINT64_C(1325401088), // MOVIv4i32
4835
0
    UINT64_C(1325450240), // MOVIv4s_msl
4836
0
    UINT64_C(251716608),  // MOVIv8b_ns
4837
0
    UINT64_C(1325433856), // MOVIv8i16
4838
0
    UINT64_C(1920991232), // MOVKWi
4839
0
    UINT64_C(4068474880), // MOVKXi
4840
0
    UINT64_C(310378496),  // MOVNWi
4841
0
    UINT64_C(2457862144), // MOVNXi
4842
0
    UINT64_C(68231168), // MOVPRFX_ZPmZ_B
4843
0
    UINT64_C(80814080), // MOVPRFX_ZPmZ_D
4844
0
    UINT64_C(72425472), // MOVPRFX_ZPmZ_H
4845
0
    UINT64_C(76619776), // MOVPRFX_ZPmZ_S
4846
0
    UINT64_C(68165632), // MOVPRFX_ZPzZ_B
4847
0
    UINT64_C(80748544), // MOVPRFX_ZPzZ_D
4848
0
    UINT64_C(72359936), // MOVPRFX_ZPzZ_H
4849
0
    UINT64_C(76554240), // MOVPRFX_ZPzZ_S
4850
0
    UINT64_C(69254144), // MOVPRFX_ZZ
4851
0
    UINT64_C(3226403808), // MOVT
4852
0
    UINT64_C(3226338272), // MOVT_TIX
4853
0
    UINT64_C(3226207200), // MOVT_XTI
4854
0
    UINT64_C(1384120320), // MOVZWi
4855
0
    UINT64_C(3531603968), // MOVZXi
4856
0
    UINT64_C(3579838464), // MRRS
4857
0
    UINT64_C(3575644160), // MRS
4858
0
    UINT64_C(67166208), // MSB_ZPmZZ_B
4859
0
    UINT64_C(79749120), // MSB_ZPmZZ_D
4860
0
    UINT64_C(71360512), // MSB_ZPmZZ_H
4861
0
    UINT64_C(75554816), // MSB_ZPmZZ_S
4862
0
    UINT64_C(3573547008), // MSR
4863
0
    UINT64_C(3577741312), // MSRR
4864
0
    UINT64_C(3573563423), // MSRpstateImm1
4865
0
    UINT64_C(3573563423), // MSRpstateImm4
4866
0
    UINT64_C(3573760127), // MSRpstatesvcrImm1
4867
0
    UINT64_C(2606792704), // MSUBPT
4868
0
    UINT64_C(453017600),  // MSUBWrrr
4869
0
    UINT64_C(2600501248), // MSUBXrrr
4870
0
    UINT64_C(623951872),  // MUL_ZI_B
4871
0
    UINT64_C(636534784),  // MUL_ZI_D
4872
0
    UINT64_C(628146176),  // MUL_ZI_H
4873
0
    UINT64_C(632340480),  // MUL_ZI_S
4874
0
    UINT64_C(68157440), // MUL_ZPmZ_B
4875
0
    UINT64_C(80740352), // MUL_ZPmZ_D
4876
0
    UINT64_C(72351744), // MUL_ZPmZ_H
4877
0
    UINT64_C(76546048), // MUL_ZPmZ_S
4878
0
    UINT64_C(1155594240), // MUL_ZZZI_D
4879
0
    UINT64_C(1143011328), // MUL_ZZZI_H
4880
0
    UINT64_C(1151399936), // MUL_ZZZI_S
4881
0
    UINT64_C(69230592), // MUL_ZZZ_B
4882
0
    UINT64_C(81813504), // MUL_ZZZ_D
4883
0
    UINT64_C(73424896), // MUL_ZZZ_H
4884
0
    UINT64_C(77619200), // MUL_ZZZ_S
4885
0
    UINT64_C(1310759936), // MULv16i8
4886
0
    UINT64_C(245406720),  // MULv2i32
4887
0
    UINT64_C(260079616),  // MULv2i32_indexed
4888
0
    UINT64_C(241212416),  // MULv4i16
4889
0
    UINT64_C(255885312),  // MULv4i16_indexed
4890
0
    UINT64_C(1319148544), // MULv4i32
4891
0
    UINT64_C(1333821440), // MULv4i32_indexed
4892
0
    UINT64_C(1314954240), // MULv8i16
4893
0
    UINT64_C(1329627136), // MULv8i16_indexed
4894
0
    UINT64_C(237018112),  // MULv8i8
4895
0
    UINT64_C(788530176),  // MVNIv2i32
4896
0
    UINT64_C(788579328),  // MVNIv2s_msl
4897
0
    UINT64_C(788562944),  // MVNIv4i16
4898
0
    UINT64_C(1862272000), // MVNIv4i32
4899
0
    UINT64_C(1862321152), // MVNIv4s_msl
4900
0
    UINT64_C(1862304768), // MVNIv8i16
4901
0
    UINT64_C(633356816),  // NANDS_PPzPP
4902
0
    UINT64_C(629162512),  // NAND_PPzPP
4903
0
    UINT64_C(81804288), // NBSL_ZZZZ
4904
0
    UINT64_C(68657152), // NEG_ZPmZ_B
4905
0
    UINT64_C(81240064), // NEG_ZPmZ_D
4906
0
    UINT64_C(72851456), // NEG_ZPmZ_H
4907
0
    UINT64_C(77045760), // NEG_ZPmZ_S
4908
0
    UINT64_C(1847638016), // NEGv16i8
4909
0
    UINT64_C(2128656384), // NEGv1i64
4910
0
    UINT64_C(782284800),  // NEGv2i32
4911
0
    UINT64_C(1860220928), // NEGv2i64
4912
0
    UINT64_C(778090496),  // NEGv4i16
4913
0
    UINT64_C(1856026624), // NEGv4i32
4914
0
    UINT64_C(1851832320), // NEGv8i16
4915
0
    UINT64_C(773896192),  // NEGv8i8
4916
0
    UINT64_C(1159757840), // NMATCH_PPzZZ_B
4917
0
    UINT64_C(1163952144), // NMATCH_PPzZZ_H
4918
0
    UINT64_C(633356800),  // NORS_PPzPP
4919
0
    UINT64_C(629162496),  // NOR_PPzPP
4920
0
    UINT64_C(69115904), // NOT_ZPmZ_B
4921
0
    UINT64_C(81698816), // NOT_ZPmZ_D
4922
0
    UINT64_C(73310208), // NOT_ZPmZ_H
4923
0
    UINT64_C(77504512), // NOT_ZPmZ_S
4924
0
    UINT64_C(1847613440), // NOTv16i8
4925
0
    UINT64_C(773871616),  // NOTv8i8
4926
0
    UINT64_C(633356304),  // ORNS_PPzPP
4927
0
    UINT64_C(706740224),  // ORNWrs
4928
0
    UINT64_C(2854223872), // ORNXrs
4929
0
    UINT64_C(629162000),  // ORN_PPzPP
4930
0
    UINT64_C(1323310080), // ORNv16i8
4931
0
    UINT64_C(249568256),  // ORNv8i8
4932
0
    UINT64_C(68952064), // ORQV_VPZ_B
4933
0
    UINT64_C(81534976), // ORQV_VPZ_D
4934
0
    UINT64_C(73146368), // ORQV_VPZ_H
4935
0
    UINT64_C(77340672), // ORQV_VPZ_S
4936
0
    UINT64_C(633356288),  // ORRS_PPzPP
4937
0
    UINT64_C(838860800),  // ORRWri
4938
0
    UINT64_C(704643072),  // ORRWrs
4939
0
    UINT64_C(2986344448), // ORRXri
4940
0
    UINT64_C(2852126720), // ORRXrs
4941
0
    UINT64_C(629161984),  // ORR_PPzPP
4942
0
    UINT64_C(83886080), // ORR_ZI
4943
0
    UINT64_C(68681728), // ORR_ZPmZ_B
4944
0
    UINT64_C(81264640), // ORR_ZPmZ_D
4945
0
    UINT64_C(72876032), // ORR_ZPmZ_H
4946
0
    UINT64_C(77070336), // ORR_ZPmZ_S
4947
0
    UINT64_C(73412608), // ORR_ZZZ
4948
0
    UINT64_C(1319115776), // ORRv16i8
4949
0
    UINT64_C(251663360),  // ORRv2i32
4950
0
    UINT64_C(251696128),  // ORRv4i16
4951
0
    UINT64_C(1325405184), // ORRv4i32
4952
0
    UINT64_C(1325437952), // ORRv8i16
4953
0
    UINT64_C(245373952),  // ORRv8i8
4954
0
    UINT64_C(68689920), // ORV_VPZ_B
4955
0
    UINT64_C(81272832), // ORV_VPZ_D
4956
0
    UINT64_C(72884224), // ORV_VPZ_H
4957
0
    UINT64_C(77078528), // ORV_VPZ_S
4958
0
    UINT64_C(3670083584), // PACDA
4959
0
    UINT64_C(3670084608), // PACDB
4960
0
    UINT64_C(3670092768), // PACDZA
4961
0
    UINT64_C(3670093792), // PACDZB
4962
0
    UINT64_C(2596286464), // PACGA
4963
0
    UINT64_C(3670081536), // PACIA
4964
0
    UINT64_C(3573752095), // PACIA1716
4965
0
    UINT64_C(3670117374), // PACIA171615
4966
0
    UINT64_C(3573752639), // PACIASP
4967
0
    UINT64_C(3670123518), // PACIASPPC
4968
0
    UINT64_C(3573752607), // PACIAZ
4969
0
    UINT64_C(3670082560), // PACIB
4970
0
    UINT64_C(3573752159), // PACIB1716
4971
0
    UINT64_C(3670118398), // PACIB171615
4972
0
    UINT64_C(3573752703), // PACIBSP
4973
0
    UINT64_C(3670124542), // PACIBSPPC
4974
0
    UINT64_C(3573752671), // PACIBZ
4975
0
    UINT64_C(3670090720), // PACIZA
4976
0
    UINT64_C(3670091744), // PACIZB
4977
0
    UINT64_C(3573753087), // PACM
4978
0
    UINT64_C(3670115326), // PACNBIASPPC
4979
0
    UINT64_C(3670116350), // PACNBIBSPPC
4980
0
    UINT64_C(622883856),  // PEXT_2PCI_B
4981
0
    UINT64_C(635466768),  // PEXT_2PCI_D
4982
0
    UINT64_C(627078160),  // PEXT_2PCI_H
4983
0
    UINT64_C(631272464),  // PEXT_2PCI_S
4984
0
    UINT64_C(622882832),  // PEXT_PCI_B
4985
0
    UINT64_C(635465744),  // PEXT_PCI_D
4986
0
    UINT64_C(627077136),  // PEXT_PCI_H
4987
0
    UINT64_C(631271440),  // PEXT_PCI_S
4988
0
    UINT64_C(622388224),  // PFALSE
4989
0
    UINT64_C(626573312),  // PFIRST_B
4990
0
    UINT64_C(86652928), // PMOV_PZI_B
4991
0
    UINT64_C(94910464), // PMOV_PZI_D
4992
0
    UINT64_C(86784000), // PMOV_PZI_H
4993
0
    UINT64_C(90716160), // PMOV_PZI_S
4994
0
    UINT64_C(86718464), // PMOV_ZIP_B
4995
0
    UINT64_C(94976000), // PMOV_ZIP_D
4996
0
    UINT64_C(86849536), // PMOV_ZIP_H
4997
0
    UINT64_C(90781696), // PMOV_ZIP_S
4998
0
    UINT64_C(1170237440), // PMULLB_ZZZ_D
4999
0
    UINT64_C(1161848832), // PMULLB_ZZZ_H
5000
0
    UINT64_C(1157654528), // PMULLB_ZZZ_Q
5001
0
    UINT64_C(1170238464), // PMULLT_ZZZ_D
5002
0
    UINT64_C(1161849856), // PMULLT_ZZZ_H
5003
0
    UINT64_C(1157655552), // PMULLT_ZZZ_Q
5004
0
    UINT64_C(1310777344), // PMULLv16i8
5005
0
    UINT64_C(249618432),  // PMULLv1i64
5006
0
    UINT64_C(1323360256), // PMULLv2i64
5007
0
    UINT64_C(237035520),  // PMULLv8i8
5008
0
    UINT64_C(69231616), // PMUL_ZZZ_B
5009
0
    UINT64_C(1847630848), // PMULv16i8
5010
0
    UINT64_C(773889024),  // PMULv8i8
5011
0
    UINT64_C(622445568),  // PNEXT_B
5012
0
    UINT64_C(635028480),  // PNEXT_D
5013
0
    UINT64_C(626639872),  // PNEXT_H
5014
0
    UINT64_C(630834176),  // PNEXT_S
5015
0
    UINT64_C(3288391680), // PRFB_D_PZI
5016
0
    UINT64_C(3294658560), // PRFB_D_SCALED
5017
0
    UINT64_C(3294625792), // PRFB_D_SXTW_SCALED
5018
0
    UINT64_C(3290431488), // PRFB_D_UXTW_SCALED
5019
0
    UINT64_C(2243952640), // PRFB_PRI
5020
0
    UINT64_C(2214641664), // PRFB_PRR
5021
0
    UINT64_C(2214649856), // PRFB_S_PZI
5022
0
    UINT64_C(2220883968), // PRFB_S_SXTW_SCALED
5023
0
    UINT64_C(2216689664), // PRFB_S_UXTW_SCALED
5024
0
    UINT64_C(3313557504), // PRFD_D_PZI
5025
0
    UINT64_C(3294683136), // PRFD_D_SCALED
5026
0
    UINT64_C(3294650368), // PRFD_D_SXTW_SCALED
5027
0
    UINT64_C(3290456064), // PRFD_D_UXTW_SCALED
5028
0
    UINT64_C(2243977216), // PRFD_PRI
5029
0
    UINT64_C(2239807488), // PRFD_PRR
5030
0
    UINT64_C(2239815680), // PRFD_S_PZI
5031
0
    UINT64_C(2220908544), // PRFD_S_SXTW_SCALED
5032
0
    UINT64_C(2216714240), // PRFD_S_UXTW_SCALED
5033
0
    UINT64_C(3296780288), // PRFH_D_PZI
5034
0
    UINT64_C(3294666752), // PRFH_D_SCALED
5035
0
    UINT64_C(3294633984), // PRFH_D_SXTW_SCALED
5036
0
    UINT64_C(3290439680), // PRFH_D_UXTW_SCALED
5037
0
    UINT64_C(2243960832), // PRFH_PRI
5038
0
    UINT64_C(2223030272), // PRFH_PRR
5039
0
    UINT64_C(2223038464), // PRFH_S_PZI
5040
0
    UINT64_C(2220892160), // PRFH_S_SXTW_SCALED
5041
0
    UINT64_C(2216697856), // PRFH_S_UXTW_SCALED
5042
0
    UINT64_C(3623878656), // PRFMl
5043
0
    UINT64_C(4171253760), // PRFMroW
5044
0
    UINT64_C(4171261952), // PRFMroX
5045
0
    UINT64_C(4185915392), // PRFMui
5046
0
    UINT64_C(4169138176), // PRFUMi
5047
0
    UINT64_C(3305168896), // PRFW_D_PZI
5048
0
    UINT64_C(3294674944), // PRFW_D_SCALED
5049
0
    UINT64_C(3294642176), // PRFW_D_SXTW_SCALED
5050
0
    UINT64_C(3290447872), // PRFW_D_UXTW_SCALED
5051
0
    UINT64_C(2243969024), // PRFW_PRI
5052
0
    UINT64_C(2231418880), // PRFW_PRR
5053
0
    UINT64_C(2231427072), // PRFW_S_PZI
5054
0
    UINT64_C(2220900352), // PRFW_S_SXTW_SCALED
5055
0
    UINT64_C(2216706048), // PRFW_S_UXTW_SCALED
5056
0
    UINT64_C(623132672),  // PSEL_PPPRI_B
5057
0
    UINT64_C(627064832),  // PSEL_PPPRI_D
5058
0
    UINT64_C(623394816),  // PSEL_PPPRI_H
5059
0
    UINT64_C(623919104),  // PSEL_PPPRI_S
5060
0
    UINT64_C(626049024),  // PTEST_PP
5061
0
    UINT64_C(622452736),  // PTRUES_B
5062
0
    UINT64_C(635035648),  // PTRUES_D
5063
0
    UINT64_C(626647040),  // PTRUES_H
5064
0
    UINT64_C(630841344),  // PTRUES_S
5065
0
    UINT64_C(622387200),  // PTRUE_B
5066
0
    UINT64_C(622884880),  // PTRUE_C_B
5067
0
    UINT64_C(635467792),  // PTRUE_C_D
5068
0
    UINT64_C(627079184),  // PTRUE_C_H
5069
0
    UINT64_C(631273488),  // PTRUE_C_S
5070
0
    UINT64_C(634970112),  // PTRUE_D
5071
0
    UINT64_C(626581504),  // PTRUE_H
5072
0
    UINT64_C(630775808),  // PTRUE_S
5073
0
    UINT64_C(87113728), // PUNPKHI_PP
5074
0
    UINT64_C(87048192), // PUNPKLO_PP
5075
0
    UINT64_C(1163945984), // RADDHNB_ZZZ_B
5076
0
    UINT64_C(1168140288), // RADDHNB_ZZZ_H
5077
0
    UINT64_C(1172334592), // RADDHNB_ZZZ_S
5078
0
    UINT64_C(1163947008), // RADDHNT_ZZZ_B
5079
0
    UINT64_C(1168141312), // RADDHNT_ZZZ_H
5080
0
    UINT64_C(1172335616), // RADDHNT_ZZZ_S
5081
0
    UINT64_C(782254080),  // RADDHNv2i64_v2i32
5082
0
    UINT64_C(1855995904), // RADDHNv2i64_v4i32
5083
0
    UINT64_C(778059776),  // RADDHNv4i32_v4i16
5084
0
    UINT64_C(1851801600), // RADDHNv4i32_v8i16
5085
0
    UINT64_C(1847607296), // RADDHNv8i16_v16i8
5086
0
    UINT64_C(773865472),  // RADDHNv8i16_v8i8
5087
0
    UINT64_C(3462433792), // RAX1
5088
0
    UINT64_C(1159787520), // RAX1_ZZZ_D
5089
0
    UINT64_C(1522532352), // RBITWr
5090
0
    UINT64_C(3670016000), // RBITXr
5091
0
    UINT64_C(86474752), // RBIT_ZPmZ_B
5092
0
    UINT64_C(99057664), // RBIT_ZPmZ_D
5093
0
    UINT64_C(90669056), // RBIT_ZPmZ_H
5094
0
    UINT64_C(94863360), // RBIT_ZPmZ_S
5095
0
    UINT64_C(1851807744), // RBITv16i8
5096
0
    UINT64_C(778065920),  // RBITv8i8
5097
0
    UINT64_C(421529600),  // RCWCAS
5098
0
    UINT64_C(429918208),  // RCWCASA
5099
0
    UINT64_C(434112512),  // RCWCASAL
5100
0
    UINT64_C(425723904),  // RCWCASL
5101
0
    UINT64_C(421530624),  // RCWCASP
5102
0
    UINT64_C(429919232),  // RCWCASPA
5103
0
    UINT64_C(434113536),  // RCWCASPAL
5104
0
    UINT64_C(425724928),  // RCWCASPL
5105
0
    UINT64_C(941658112),  // RCWCLR
5106
0
    UINT64_C(950046720),  // RCWCLRA
5107
0
    UINT64_C(954241024),  // RCWCLRAL
5108
0
    UINT64_C(945852416),  // RCWCLRL
5109
0
    UINT64_C(421564416),  // RCWCLRP
5110
0
    UINT64_C(429953024),  // RCWCLRPA
5111
0
    UINT64_C(434147328),  // RCWCLRPAL
5112
0
    UINT64_C(425758720),  // RCWCLRPL
5113
0
    UINT64_C(2015399936), // RCWCLRS
5114
0
    UINT64_C(2023788544), // RCWCLRSA
5115
0
    UINT64_C(2027982848), // RCWCLRSAL
5116
0
    UINT64_C(2019594240), // RCWCLRSL
5117
0
    UINT64_C(1495306240), // RCWCLRSP
5118
0
    UINT64_C(1503694848), // RCWCLRSPA
5119
0
    UINT64_C(1507889152), // RCWCLRSPAL
5120
0
    UINT64_C(1499500544), // RCWCLRSPL
5121
0
    UINT64_C(1495271424), // RCWSCAS
5122
0
    UINT64_C(1503660032), // RCWSCASA
5123
0
    UINT64_C(1507854336), // RCWSCASAL
5124
0
    UINT64_C(1499465728), // RCWSCASL
5125
0
    UINT64_C(1495272448), // RCWSCASP
5126
0
    UINT64_C(1503661056), // RCWSCASPA
5127
0
    UINT64_C(1507855360), // RCWSCASPAL
5128
0
    UINT64_C(1499466752), // RCWSCASPL
5129
0
    UINT64_C(941666304),  // RCWSET
5130
0
    UINT64_C(950054912),  // RCWSETA
5131
0
    UINT64_C(954249216),  // RCWSETAL
5132
0
    UINT64_C(945860608),  // RCWSETL
5133
0
    UINT64_C(421572608),  // RCWSETP
5134
0
    UINT64_C(429961216),  // RCWSETPA
5135
0
    UINT64_C(434155520),  // RCWSETPAL
5136
0
    UINT64_C(425766912),  // RCWSETPL
5137
0
    UINT64_C(2015408128), // RCWSETS
5138
0
    UINT64_C(2023796736), // RCWSETSA
5139
0
    UINT64_C(2027991040), // RCWSETSAL
5140
0
    UINT64_C(2019602432), // RCWSETSL
5141
0
    UINT64_C(1495314432), // RCWSETSP
5142
0
    UINT64_C(1503703040), // RCWSETSPA
5143
0
    UINT64_C(1507897344), // RCWSETSPAL
5144
0
    UINT64_C(1499508736), // RCWSETSPL
5145
0
    UINT64_C(941662208),  // RCWSWP
5146
0
    UINT64_C(950050816),  // RCWSWPA
5147
0
    UINT64_C(954245120),  // RCWSWPAL
5148
0
    UINT64_C(945856512),  // RCWSWPL
5149
0
    UINT64_C(421568512),  // RCWSWPP
5150
0
    UINT64_C(429957120),  // RCWSWPPA
5151
0
    UINT64_C(434151424),  // RCWSWPPAL
5152
0
    UINT64_C(425762816),  // RCWSWPPL
5153
0
    UINT64_C(2015404032), // RCWSWPS
5154
0
    UINT64_C(2023792640), // RCWSWPSA
5155
0
    UINT64_C(2027986944), // RCWSWPSAL
5156
0
    UINT64_C(2019598336), // RCWSWPSL
5157
0
    UINT64_C(1495310336), // RCWSWPSP
5158
0
    UINT64_C(1503698944), // RCWSWPSPA
5159
0
    UINT64_C(1507893248), // RCWSWPSPAL
5160
0
    UINT64_C(1499504640), // RCWSWPSPL
5161
0
    UINT64_C(626585600),  // RDFFRS_PPz
5162
0
    UINT64_C(622391296),  // RDFFR_PPz_REAL
5163
0
    UINT64_C(622456832),  // RDFFR_P_REAL
5164
0
    UINT64_C(79648768), // RDSVLI_XI
5165
0
    UINT64_C(79646720), // RDVLI_XI
5166
0
    UINT64_C(3596550144), // RET
5167
0
    UINT64_C(3596553215), // RETAA
5168
0
    UINT64_C(1426063391), // RETAASPPCi
5169
0
    UINT64_C(3596553184), // RETAASPPCr
5170
0
    UINT64_C(3596554239), // RETAB
5171
0
    UINT64_C(1428160543), // RETABSPPCi
5172
0
    UINT64_C(3596554208), // RETABSPPCr
5173
0
    UINT64_C(1522533376), // REV16Wr
5174
0
    UINT64_C(3670017024), // REV16Xr
5175
0
    UINT64_C(1310726144), // REV16v16i8
5176
0
    UINT64_C(236984320),  // REV16v8i8
5177
0
    UINT64_C(3670018048), // REV32Xr
5178
0
    UINT64_C(1847592960), // REV32v16i8
5179
0
    UINT64_C(778045440),  // REV32v4i16
5180
0
    UINT64_C(1851787264), // REV32v8i16
5181
0
    UINT64_C(773851136),  // REV32v8i8
5182
0
    UINT64_C(1310722048), // REV64v16i8
5183
0
    UINT64_C(245368832),  // REV64v2i32
5184
0
    UINT64_C(241174528),  // REV64v4i16
5185
0
    UINT64_C(1319110656), // REV64v4i32
5186
0
    UINT64_C(1314916352), // REV64v8i16
5187
0
    UINT64_C(236980224),  // REV64v8i8
5188
0
    UINT64_C(98861056), // REVB_ZPmZ_D
5189
0
    UINT64_C(90472448), // REVB_ZPmZ_H
5190
0
    UINT64_C(94666752), // REVB_ZPmZ_S
5191
0
    UINT64_C(86933504), // REVD_ZPmZ
5192
0
    UINT64_C(98926592), // REVH_ZPmZ_D
5193
0
    UINT64_C(94732288), // REVH_ZPmZ_S
5194
0
    UINT64_C(98992128), // REVW_ZPmZ_D
5195
0
    UINT64_C(1522534400), // REVWr
5196
0
    UINT64_C(3670019072), // REVXr
5197
0
    UINT64_C(87310336), // REV_PP_B
5198
0
    UINT64_C(99893248), // REV_PP_D
5199
0
    UINT64_C(91504640), // REV_PP_H
5200
0
    UINT64_C(95698944), // REV_PP_S
5201
0
    UINT64_C(87570432), // REV_ZZ_B
5202
0
    UINT64_C(100153344),  // REV_ZZ_D
5203
0
    UINT64_C(91764736), // REV_ZZ_H
5204
0
    UINT64_C(95959040), // REV_ZZ_S
5205
0
    UINT64_C(3120563200), // RMIF
5206
0
    UINT64_C(448801792),  // RORVWr
5207
0
    UINT64_C(2596285440), // RORVXr
5208
0
    UINT64_C(4171253784), // RPRFM
5209
0
    UINT64_C(1160255488), // RSHRNB_ZZI_B
5210
0
    UINT64_C(1160779776), // RSHRNB_ZZI_H
5211
0
    UINT64_C(1163925504), // RSHRNB_ZZI_S
5212
0
    UINT64_C(1160256512), // RSHRNT_ZZI_B
5213
0
    UINT64_C(1160780800), // RSHRNT_ZZI_H
5214
0
    UINT64_C(1163926528), // RSHRNT_ZZI_S
5215
0
    UINT64_C(1325960192), // RSHRNv16i8_shift
5216
0
    UINT64_C(253791232),  // RSHRNv2i32_shift
5217
0
    UINT64_C(252742656),  // RSHRNv4i16_shift
5218
0
    UINT64_C(1327533056), // RSHRNv4i32_shift
5219
0
    UINT64_C(1326484480), // RSHRNv8i16_shift
5220
0
    UINT64_C(252218368),  // RSHRNv8i8_shift
5221
0
    UINT64_C(1163950080), // RSUBHNB_ZZZ_B
5222
0
    UINT64_C(1168144384), // RSUBHNB_ZZZ_H
5223
0
    UINT64_C(1172338688), // RSUBHNB_ZZZ_S
5224
0
    UINT64_C(1163951104), // RSUBHNT_ZZZ_B
5225
0
    UINT64_C(1168145408), // RSUBHNT_ZZZ_H
5226
0
    UINT64_C(1172339712), // RSUBHNT_ZZZ_S
5227
0
    UINT64_C(782262272),  // RSUBHNv2i64_v2i32
5228
0
    UINT64_C(1856004096), // RSUBHNv2i64_v4i32
5229
0
    UINT64_C(778067968),  // RSUBHNv4i32_v4i16
5230
0
    UINT64_C(1851809792), // RSUBHNv4i32_v8i16
5231
0
    UINT64_C(1847615488), // RSUBHNv8i16_v16i8
5232
0
    UINT64_C(773873664),  // RSUBHNv8i16_v8i8
5233
0
    UINT64_C(1170259968), // SABALB_ZZZ_D
5234
0
    UINT64_C(1161871360), // SABALB_ZZZ_H
5235
0
    UINT64_C(1166065664), // SABALB_ZZZ_S
5236
0
    UINT64_C(1170260992), // SABALT_ZZZ_D
5237
0
    UINT64_C(1161872384), // SABALT_ZZZ_H
5238
0
    UINT64_C(1166066688), // SABALT_ZZZ_S
5239
0
    UINT64_C(1310740480), // SABALv16i8_v8i16
5240
0
    UINT64_C(245387264),  // SABALv2i32_v2i64
5241
0
    UINT64_C(241192960),  // SABALv4i16_v4i32
5242
0
    UINT64_C(1319129088), // SABALv4i32_v2i64
5243
0
    UINT64_C(1314934784), // SABALv8i16_v4i32
5244
0
    UINT64_C(236998656),  // SABALv8i8_v8i16
5245
0
    UINT64_C(1157691392), // SABA_ZZZ_B
5246
0
    UINT64_C(1170274304), // SABA_ZZZ_D
5247
0
    UINT64_C(1161885696), // SABA_ZZZ_H
5248
0
    UINT64_C(1166080000), // SABA_ZZZ_S
5249
0
    UINT64_C(1310751744), // SABAv16i8
5250
0
    UINT64_C(245398528),  // SABAv2i32
5251
0
    UINT64_C(241204224),  // SABAv4i16
5252
0
    UINT64_C(1319140352), // SABAv4i32
5253
0
    UINT64_C(1314946048), // SABAv8i16
5254
0
    UINT64_C(237009920),  // SABAv8i8
5255
0
    UINT64_C(1170223104), // SABDLB_ZZZ_D
5256
0
    UINT64_C(1161834496), // SABDLB_ZZZ_H
5257
0
    UINT64_C(1166028800), // SABDLB_ZZZ_S
5258
0
    UINT64_C(1170224128), // SABDLT_ZZZ_D
5259
0
    UINT64_C(1161835520), // SABDLT_ZZZ_H
5260
0
    UINT64_C(1166029824), // SABDLT_ZZZ_S
5261
0
    UINT64_C(1310748672), // SABDLv16i8_v8i16
5262
0
    UINT64_C(245395456),  // SABDLv2i32_v2i64
5263
0
    UINT64_C(241201152),  // SABDLv4i16_v4i32
5264
0
    UINT64_C(1319137280), // SABDLv4i32_v2i64
5265
0
    UINT64_C(1314942976), // SABDLv8i16_v4i32
5266
0
    UINT64_C(237006848),  // SABDLv8i8_v8i16
5267
0
    UINT64_C(67895296), // SABD_ZPmZ_B
5268
0
    UINT64_C(80478208), // SABD_ZPmZ_D
5269
0
    UINT64_C(72089600), // SABD_ZPmZ_H
5270
0
    UINT64_C(76283904), // SABD_ZPmZ_S
5271
0
    UINT64_C(1310749696), // SABDv16i8
5272
0
    UINT64_C(245396480),  // SABDv2i32
5273
0
    UINT64_C(241202176),  // SABDv4i16
5274
0
    UINT64_C(1319138304), // SABDv4i32
5275
0
    UINT64_C(1314944000), // SABDv8i16
5276
0
    UINT64_C(237007872),  // SABDv8i8
5277
0
    UINT64_C(1153736704), // SADALP_ZPmZ_D
5278
0
    UINT64_C(1145348096), // SADALP_ZPmZ_H
5279
0
    UINT64_C(1149542400), // SADALP_ZPmZ_S
5280
0
    UINT64_C(1310746624), // SADALPv16i8_v8i16
5281
0
    UINT64_C(245393408),  // SADALPv2i32_v1i64
5282
0
    UINT64_C(241199104),  // SADALPv4i16_v2i32
5283
0
    UINT64_C(1319135232), // SADALPv4i32_v2i64
5284
0
    UINT64_C(1314940928), // SADALPv8i16_v4i32
5285
0
    UINT64_C(237004800),  // SADALPv8i8_v4i16
5286
0
    UINT64_C(1170243584), // SADDLBT_ZZZ_D
5287
0
    UINT64_C(1161854976), // SADDLBT_ZZZ_H
5288
0
    UINT64_C(1166049280), // SADDLBT_ZZZ_S
5289
0
    UINT64_C(1170210816), // SADDLB_ZZZ_D
5290
0
    UINT64_C(1161822208), // SADDLB_ZZZ_H
5291
0
    UINT64_C(1166016512), // SADDLB_ZZZ_S
5292
0
    UINT64_C(1310730240), // SADDLPv16i8_v8i16
5293
0
    UINT64_C(245377024),  // SADDLPv2i32_v1i64
5294
0
    UINT64_C(241182720),  // SADDLPv4i16_v2i32
5295
0
    UINT64_C(1319118848), // SADDLPv4i32_v2i64
5296
0
    UINT64_C(1314924544), // SADDLPv8i16_v4i32
5297
0
    UINT64_C(236988416),  // SADDLPv8i8_v4i16
5298
0
    UINT64_C(1170211840), // SADDLT_ZZZ_D
5299
0
    UINT64_C(1161823232), // SADDLT_ZZZ_H
5300
0
    UINT64_C(1166017536), // SADDLT_ZZZ_S
5301
0
    UINT64_C(1311782912), // SADDLVv16i8v
5302
0
    UINT64_C(242235392),  // SADDLVv4i16v
5303
0
    UINT64_C(1320171520), // SADDLVv4i32v
5304
0
    UINT64_C(1315977216), // SADDLVv8i16v
5305
0
    UINT64_C(238041088),  // SADDLVv8i8v
5306
0
    UINT64_C(1310720000), // SADDLv16i8_v8i16
5307
0
    UINT64_C(245366784),  // SADDLv2i32_v2i64
5308
0
    UINT64_C(241172480),  // SADDLv4i16_v4i32
5309
0
    UINT64_C(1319108608), // SADDLv4i32_v2i64
5310
0
    UINT64_C(1314914304), // SADDLv8i16_v4i32
5311
0
    UINT64_C(236978176),  // SADDLv8i8_v8i16
5312
0
    UINT64_C(67117056), // SADDV_VPZ_B
5313
0
    UINT64_C(71311360), // SADDV_VPZ_H
5314
0
    UINT64_C(75505664), // SADDV_VPZ_S
5315
0
    UINT64_C(1170227200), // SADDWB_ZZZ_D
5316
0
    UINT64_C(1161838592), // SADDWB_ZZZ_H
5317
0
    UINT64_C(1166032896), // SADDWB_ZZZ_S
5318
0
    UINT64_C(1170228224), // SADDWT_ZZZ_D
5319
0
    UINT64_C(1161839616), // SADDWT_ZZZ_H
5320
0
    UINT64_C(1166033920), // SADDWT_ZZZ_S
5321
0
    UINT64_C(1310724096), // SADDWv16i8_v8i16
5322
0
    UINT64_C(245370880),  // SADDWv2i32_v2i64
5323
0
    UINT64_C(241176576),  // SADDWv4i16_v4i32
5324
0
    UINT64_C(1319112704), // SADDWv4i32_v2i64
5325
0
    UINT64_C(1314918400), // SADDWv8i16_v4i32
5326
0
    UINT64_C(236982272),  // SADDWv8i8_v8i16
5327
0
    UINT64_C(3573756159), // SB
5328
0
    UINT64_C(1170264064), // SBCLB_ZZZ_D
5329
0
    UINT64_C(1166069760), // SBCLB_ZZZ_S
5330
0
    UINT64_C(1170265088), // SBCLT_ZZZ_D
5331
0
    UINT64_C(1166070784), // SBCLT_ZZZ_S
5332
0
    UINT64_C(2046820352), // SBCSWr
5333
0
    UINT64_C(4194304000), // SBCSXr
5334
0
    UINT64_C(1509949440), // SBCWr
5335
0
    UINT64_C(3657433088), // SBCXr
5336
0
    UINT64_C(318767104),  // SBFMWri
5337
0
    UINT64_C(2470445056), // SBFMXri
5338
0
    UINT64_C(3240150016), // SCLAMP_VG2_2Z2Z_B
5339
0
    UINT64_C(3252732928), // SCLAMP_VG2_2Z2Z_D
5340
0
    UINT64_C(3244344320), // SCLAMP_VG2_2Z2Z_H
5341
0
    UINT64_C(3248538624), // SCLAMP_VG2_2Z2Z_S
5342
0
    UINT64_C(3240152064), // SCLAMP_VG4_4Z4Z_B
5343
0
    UINT64_C(3252734976), // SCLAMP_VG4_4Z4Z_D
5344
0
    UINT64_C(3244346368), // SCLAMP_VG4_4Z4Z_H
5345
0
    UINT64_C(3248540672), // SCLAMP_VG4_4Z4Z_S
5346
0
    UINT64_C(1140899840), // SCLAMP_ZZZ_B
5347
0
    UINT64_C(1153482752), // SCLAMP_ZZZ_D
5348
0
    UINT64_C(1145094144), // SCLAMP_ZZZ_H
5349
0
    UINT64_C(1149288448), // SCLAMP_ZZZ_S
5350
0
    UINT64_C(507674624),  // SCVTFSWDri
5351
0
    UINT64_C(516063232),  // SCVTFSWHri
5352
0
    UINT64_C(503480320),  // SCVTFSWSri
5353
0
    UINT64_C(2655125504), // SCVTFSXDri
5354
0
    UINT64_C(2663514112), // SCVTFSXHri
5355
0
    UINT64_C(2650931200), // SCVTFSXSri
5356
0
    UINT64_C(509739008),  // SCVTFUWDri
5357
0
    UINT64_C(518127616),  // SCVTFUWHri
5358
0
    UINT64_C(505544704),  // SCVTFUWSri
5359
0
    UINT64_C(2657222656), // SCVTFUXDri
5360
0
    UINT64_C(2665611264), // SCVTFUXHri
5361
0
    UINT64_C(2653028352), // SCVTFUXSri
5362
0
    UINT64_C(3240288256), // SCVTF_2Z2Z_StoS
5363
0
    UINT64_C(3241336832), // SCVTF_4Z4Z_StoS
5364
0
    UINT64_C(1708564480), // SCVTF_ZPmZ_DtoD
5365
0
    UINT64_C(1700175872), // SCVTF_ZPmZ_DtoH
5366
0
    UINT64_C(1708433408), // SCVTF_ZPmZ_DtoS
5367
0
    UINT64_C(1699913728), // SCVTF_ZPmZ_HtoH
5368
0
    UINT64_C(1708171264), // SCVTF_ZPmZ_StoD
5369
0
    UINT64_C(1700044800), // SCVTF_ZPmZ_StoH
5370
0
    UINT64_C(1704239104), // SCVTF_ZPmZ_StoS
5371
0
    UINT64_C(1598088192), // SCVTFd
5372
0
    UINT64_C(1594942464), // SCVTFh
5373
0
    UINT64_C(1595991040), // SCVTFs
5374
0
    UINT64_C(1585043456), // SCVTFv1i16
5375
0
    UINT64_C(1579276288), // SCVTFv1i32
5376
0
    UINT64_C(1583470592), // SCVTFv1i64
5377
0
    UINT64_C(237099008),  // SCVTFv2f32
5378
0
    UINT64_C(1315035136), // SCVTFv2f64
5379
0
    UINT64_C(253813760),  // SCVTFv2i32_shift
5380
0
    UINT64_C(1329652736), // SCVTFv2i64_shift
5381
0
    UINT64_C(242866176),  // SCVTFv4f16
5382
0
    UINT64_C(1310840832), // SCVTFv4f32
5383
0
    UINT64_C(252765184),  // SCVTFv4i16_shift
5384
0
    UINT64_C(1327555584), // SCVTFv4i32_shift
5385
0
    UINT64_C(1316608000), // SCVTFv8f16
5386
0
    UINT64_C(1326507008), // SCVTFv8i16_shift
5387
0
    UINT64_C(81133568), // SDIVR_ZPmZ_D
5388
0
    UINT64_C(76939264), // SDIVR_ZPmZ_S
5389
0
    UINT64_C(448793600),  // SDIVWr
5390
0
    UINT64_C(2596277248), // SDIVXr
5391
0
    UINT64_C(81002496), // SDIV_ZPmZ_D
5392
0
    UINT64_C(76808192), // SDIV_ZPmZ_S
5393
0
    UINT64_C(3248493568), // SDOT_VG2_M2Z2Z_BtoS
5394
0
    UINT64_C(3252687872), // SDOT_VG2_M2Z2Z_HtoD
5395
0
    UINT64_C(3252687880), // SDOT_VG2_M2Z2Z_HtoS
5396
0
    UINT64_C(3243249696), // SDOT_VG2_M2ZZI_BToS
5397
0
    UINT64_C(3243249664), // SDOT_VG2_M2ZZI_HToS
5398
0
    UINT64_C(3251634184), // SDOT_VG2_M2ZZI_HtoD
5399
0
    UINT64_C(3240104960), // SDOT_VG2_M2ZZ_BtoS
5400
0
    UINT64_C(3244299264), // SDOT_VG2_M2ZZ_HtoD
5401
0
    UINT64_C(3244299272), // SDOT_VG2_M2ZZ_HtoS
5402
0
    UINT64_C(3248559104), // SDOT_VG4_M4Z4Z_BtoS
5403
0
    UINT64_C(3252753408), // SDOT_VG4_M4Z4Z_HtoD
5404
0
    UINT64_C(3252753416), // SDOT_VG4_M4Z4Z_HtoS
5405
0
    UINT64_C(3243282464), // SDOT_VG4_M4ZZI_BToS
5406
0
    UINT64_C(3243282432), // SDOT_VG4_M4ZZI_HToS
5407
0
    UINT64_C(3251666952), // SDOT_VG4_M4ZZI_HtoD
5408
0
    UINT64_C(3241153536), // SDOT_VG4_M4ZZ_BtoS
5409
0
    UINT64_C(3245347840), // SDOT_VG4_M4ZZ_HtoD
5410
0
    UINT64_C(3245347848), // SDOT_VG4_M4ZZ_HtoS
5411
0
    UINT64_C(1155530752), // SDOT_ZZZI_D
5412
0
    UINT64_C(1149290496), // SDOT_ZZZI_HtoS
5413
0
    UINT64_C(1151336448), // SDOT_ZZZI_S
5414
0
    UINT64_C(1153433600), // SDOT_ZZZ_D
5415
0
    UINT64_C(1140901888), // SDOT_ZZZ_HtoS
5416
0
    UINT64_C(1149239296), // SDOT_ZZZ_S
5417
0
    UINT64_C(1333846016), // SDOTlanev16i8
5418
0
    UINT64_C(260104192),  // SDOTlanev8i8
5419
0
    UINT64_C(1317049344), // SDOTv16i8
5420
0
    UINT64_C(243307520),  // SDOTv8i8
5421
0
    UINT64_C(620773904),  // SEL_PPPP
5422
0
    UINT64_C(3240132608), // SEL_VG2_2ZC2Z2Z_B
5423
0
    UINT64_C(3252715520), // SEL_VG2_2ZC2Z2Z_D
5424
0
    UINT64_C(3244326912), // SEL_VG2_2ZC2Z2Z_H
5425
0
    UINT64_C(3248521216), // SEL_VG2_2ZC2Z2Z_S
5426
0
    UINT64_C(3240198144), // SEL_VG4_4ZC4Z4Z_B
5427
0
    UINT64_C(3252781056), // SEL_VG4_4ZC4Z4Z_D
5428
0
    UINT64_C(3244392448), // SEL_VG4_4ZC4Z4Z_H
5429
0
    UINT64_C(3248586752), // SEL_VG4_4ZC4Z4Z_S
5430
0
    UINT64_C(86032384), // SEL_ZPZZ_B
5431
0
    UINT64_C(98615296), // SEL_ZPZZ_D
5432
0
    UINT64_C(90226688), // SEL_ZPZZ_H
5433
0
    UINT64_C(94420992), // SEL_ZPZZ_S
5434
0
    UINT64_C(432047104),  // SETE
5435
0
    UINT64_C(432055296),  // SETEN
5436
0
    UINT64_C(432051200),  // SETET
5437
0
    UINT64_C(432059392),  // SETETN
5438
0
    UINT64_C(973096973),  // SETF16
5439
0
    UINT64_C(973080589),  // SETF8
5440
0
    UINT64_C(623677440),  // SETFFR
5441
0
    UINT64_C(499139584),  // SETGM
5442
0
    UINT64_C(499147776),  // SETGMN
5443
0
    UINT64_C(499143680),  // SETGMT
5444
0
    UINT64_C(499151872),  // SETGMTN
5445
0
    UINT64_C(499123200),  // SETGP
5446
0
    UINT64_C(499131392),  // SETGPN
5447
0
    UINT64_C(499127296),  // SETGPT
5448
0
    UINT64_C(499135488),  // SETGPTN
5449
0
    UINT64_C(432030720),  // SETM
5450
0
    UINT64_C(432038912),  // SETMN
5451
0
    UINT64_C(432034816),  // SETMT
5452
0
    UINT64_C(432043008),  // SETMTN
5453
0
    UINT64_C(432014336),  // SETP
5454
0
    UINT64_C(432022528),  // SETPN
5455
0
    UINT64_C(432018432),  // SETPT
5456
0
    UINT64_C(432026624),  // SETPTN
5457
0
    UINT64_C(1577058304), // SHA1Crrr
5458
0
    UINT64_C(1579681792), // SHA1Hrr
5459
0
    UINT64_C(1577066496), // SHA1Mrrr
5460
0
    UINT64_C(1577062400), // SHA1Prrr
5461
0
    UINT64_C(1577070592), // SHA1SU0rrr
5462
0
    UINT64_C(1579685888), // SHA1SU1rr
5463
0
    UINT64_C(1577078784), // SHA256H2rrr
5464
0
    UINT64_C(1577074688), // SHA256Hrrr
5465
0
    UINT64_C(1579689984), // SHA256SU0rr
5466
0
    UINT64_C(1577082880), // SHA256SU1rrr
5467
0
    UINT64_C(3462430720), // SHA512H
5468
0
    UINT64_C(3462431744), // SHA512H2
5469
0
    UINT64_C(3468722176), // SHA512SU0
5470
0
    UINT64_C(3462432768), // SHA512SU1
5471
0
    UINT64_C(1141932032), // SHADD_ZPmZ_B
5472
0
    UINT64_C(1154514944), // SHADD_ZPmZ_D
5473
0
    UINT64_C(1146126336), // SHADD_ZPmZ_H
5474
0
    UINT64_C(1150320640), // SHADD_ZPmZ_S
5475
0
    UINT64_C(1310721024), // SHADDv16i8
5476
0
    UINT64_C(245367808),  // SHADDv2i32
5477
0
    UINT64_C(241173504),  // SHADDv4i16
5478
0
    UINT64_C(1319109632), // SHADDv4i32
5479
0
    UINT64_C(1314915328), // SHADDv8i16
5480
0
    UINT64_C(236979200),  // SHADDv8i8
5481
0
    UINT64_C(1847670784), // SHLLv16i8
5482
0
    UINT64_C(782317568),  // SHLLv2i32
5483
0
    UINT64_C(778123264),  // SHLLv4i16
5484
0
    UINT64_C(1856059392), // SHLLv4i32
5485
0
    UINT64_C(1851865088), // SHLLv8i16
5486
0
    UINT64_C(773928960),  // SHLLv8i8
5487
0
    UINT64_C(1598051328), // SHLd
5488
0
    UINT64_C(1325945856), // SHLv16i8_shift
5489
0
    UINT64_C(253776896),  // SHLv2i32_shift
5490
0
    UINT64_C(1329615872), // SHLv2i64_shift
5491
0
    UINT64_C(252728320),  // SHLv4i16_shift
5492
0
    UINT64_C(1327518720), // SHLv4i32_shift
5493
0
    UINT64_C(1326470144), // SHLv8i16_shift
5494
0
    UINT64_C(252204032),  // SHLv8i8_shift
5495
0
    UINT64_C(1160253440), // SHRNB_ZZI_B
5496
0
    UINT64_C(1160777728), // SHRNB_ZZI_H
5497
0
    UINT64_C(1163923456), // SHRNB_ZZI_S
5498
0
    UINT64_C(1160254464), // SHRNT_ZZI_B
5499
0
    UINT64_C(1160778752), // SHRNT_ZZI_H
5500
0
    UINT64_C(1163924480), // SHRNT_ZZI_S
5501
0
    UINT64_C(1325958144), // SHRNv16i8_shift
5502
0
    UINT64_C(253789184),  // SHRNv2i32_shift
5503
0
    UINT64_C(252740608),  // SHRNv4i16_shift
5504
0
    UINT64_C(1327531008), // SHRNv4i32_shift
5505
0
    UINT64_C(1326482432), // SHRNv8i16_shift
5506
0
    UINT64_C(252216320),  // SHRNv8i8_shift
5507
0
    UINT64_C(1142325248), // SHSUBR_ZPmZ_B
5508
0
    UINT64_C(1154908160), // SHSUBR_ZPmZ_D
5509
0
    UINT64_C(1146519552), // SHSUBR_ZPmZ_H
5510
0
    UINT64_C(1150713856), // SHSUBR_ZPmZ_S
5511
0
    UINT64_C(1142063104), // SHSUB_ZPmZ_B
5512
0
    UINT64_C(1154646016), // SHSUB_ZPmZ_D
5513
0
    UINT64_C(1146257408), // SHSUB_ZPmZ_H
5514
0
    UINT64_C(1150451712), // SHSUB_ZPmZ_S
5515
0
    UINT64_C(1310729216), // SHSUBv16i8
5516
0
    UINT64_C(245376000),  // SHSUBv2i32
5517
0
    UINT64_C(241181696),  // SHSUBv4i16
5518
0
    UINT64_C(1319117824), // SHSUBv4i32
5519
0
    UINT64_C(1314923520), // SHSUBv8i16
5520
0
    UINT64_C(236987392),  // SHSUBv8i8
5521
0
    UINT64_C(1158214656), // SLI_ZZI_B
5522
0
    UINT64_C(1166078976), // SLI_ZZI_D
5523
0
    UINT64_C(1158738944), // SLI_ZZI_H
5524
0
    UINT64_C(1161884672), // SLI_ZZI_S
5525
0
    UINT64_C(2134922240), // SLId
5526
0
    UINT64_C(1862816768), // SLIv16i8_shift
5527
0
    UINT64_C(790647808),  // SLIv2i32_shift
5528
0
    UINT64_C(1866486784), // SLIv2i64_shift
5529
0
    UINT64_C(789599232),  // SLIv4i16_shift
5530
0
    UINT64_C(1864389632), // SLIv4i32_shift
5531
0
    UINT64_C(1863341056), // SLIv8i16_shift
5532
0
    UINT64_C(789074944),  // SLIv8i8_shift
5533
0
    UINT64_C(3462447104), // SM3PARTW1
5534
0
    UINT64_C(3462448128), // SM3PARTW2
5535
0
    UINT64_C(3460300800), // SM3SS1
5536
0
    UINT64_C(3460333568), // SM3TT1A
5537
0
    UINT64_C(3460334592), // SM3TT1B
5538
0
    UINT64_C(3460335616), // SM3TT2A
5539
0
    UINT64_C(3460336640), // SM3TT2B
5540
0
    UINT64_C(3468723200), // SM4E
5541
0
    UINT64_C(1159786496), // SM4EKEY_ZZZ_S
5542
0
    UINT64_C(3462449152), // SM4ENCKEY
5543
0
    UINT64_C(1159979008), // SM4E_ZZZ_S
5544
0
    UINT64_C(2602565632), // SMADDLrrr
5545
0
    UINT64_C(1142202368), // SMAXP_ZPmZ_B
5546
0
    UINT64_C(1154785280), // SMAXP_ZPmZ_D
5547
0
    UINT64_C(1146396672), // SMAXP_ZPmZ_H
5548
0
    UINT64_C(1150590976), // SMAXP_ZPmZ_S
5549
0
    UINT64_C(1310761984), // SMAXPv16i8
5550
0
    UINT64_C(245408768),  // SMAXPv2i32
5551
0
    UINT64_C(241214464),  // SMAXPv4i16
5552
0
    UINT64_C(1319150592), // SMAXPv4i32
5553
0
    UINT64_C(1314956288), // SMAXPv8i16
5554
0
    UINT64_C(237020160),  // SMAXPv8i8
5555
0
    UINT64_C(67903488), // SMAXQV_VPZ_B
5556
0
    UINT64_C(80486400), // SMAXQV_VPZ_D
5557
0
    UINT64_C(72097792), // SMAXQV_VPZ_H
5558
0
    UINT64_C(76292096), // SMAXQV_VPZ_S
5559
0
    UINT64_C(67641344), // SMAXV_VPZ_B
5560
0
    UINT64_C(80224256), // SMAXV_VPZ_D
5561
0
    UINT64_C(71835648), // SMAXV_VPZ_H
5562
0
    UINT64_C(76029952), // SMAXV_VPZ_S
5563
0
    UINT64_C(1311811584), // SMAXVv16i8v
5564
0
    UINT64_C(242264064),  // SMAXVv4i16v
5565
0
    UINT64_C(1320200192), // SMAXVv4i32v
5566
0
    UINT64_C(1316005888), // SMAXVv8i16v
5567
0
    UINT64_C(238069760),  // SMAXVv8i8v
5568
0
    UINT64_C(297795584),  // SMAXWri
5569
0
    UINT64_C(448815104),  // SMAXWrr
5570
0
    UINT64_C(2445279232), // SMAXXri
5571
0
    UINT64_C(2596298752), // SMAXXrr
5572
0
    UINT64_C(3240144896), // SMAX_VG2_2Z2Z_B
5573
0
    UINT64_C(3252727808), // SMAX_VG2_2Z2Z_D
5574
0
    UINT64_C(3244339200), // SMAX_VG2_2Z2Z_H
5575
0
    UINT64_C(3248533504), // SMAX_VG2_2Z2Z_S
5576
0
    UINT64_C(3240140800), // SMAX_VG2_2ZZ_B
5577
0
    UINT64_C(3252723712), // SMAX_VG2_2ZZ_D
5578
0
    UINT64_C(3244335104), // SMAX_VG2_2ZZ_H
5579
0
    UINT64_C(3248529408), // SMAX_VG2_2ZZ_S
5580
0
    UINT64_C(3240146944), // SMAX_VG4_4Z4Z_B
5581
0
    UINT64_C(3252729856), // SMAX_VG4_4Z4Z_D
5582
0
    UINT64_C(3244341248), // SMAX_VG4_4Z4Z_H
5583
0
    UINT64_C(3248535552), // SMAX_VG4_4Z4Z_S
5584
0
    UINT64_C(3240142848), // SMAX_VG4_4ZZ_B
5585
0
    UINT64_C(3252725760), // SMAX_VG4_4ZZ_D
5586
0
    UINT64_C(3244337152), // SMAX_VG4_4ZZ_H
5587
0
    UINT64_C(3248531456), // SMAX_VG4_4ZZ_S
5588
0
    UINT64_C(623427584),  // SMAX_ZI_B
5589
0
    UINT64_C(636010496),  // SMAX_ZI_D
5590
0
    UINT64_C(627621888),  // SMAX_ZI_H
5591
0
    UINT64_C(631816192),  // SMAX_ZI_S
5592
0
    UINT64_C(67633152), // SMAX_ZPmZ_B
5593
0
    UINT64_C(80216064), // SMAX_ZPmZ_D
5594
0
    UINT64_C(71827456), // SMAX_ZPmZ_H
5595
0
    UINT64_C(76021760), // SMAX_ZPmZ_S
5596
0
    UINT64_C(1310745600), // SMAXv16i8
5597
0
    UINT64_C(245392384),  // SMAXv2i32
5598
0
    UINT64_C(241198080),  // SMAXv4i16
5599
0
    UINT64_C(1319134208), // SMAXv4i32
5600
0
    UINT64_C(1314939904), // SMAXv8i16
5601
0
    UINT64_C(237003776),  // SMAXv8i8
5602
0
    UINT64_C(3556769795), // SMC
5603
0
    UINT64_C(1142333440), // SMINP_ZPmZ_B
5604
0
    UINT64_C(1154916352), // SMINP_ZPmZ_D
5605
0
    UINT64_C(1146527744), // SMINP_ZPmZ_H
5606
0
    UINT64_C(1150722048), // SMINP_ZPmZ_S
5607
0
    UINT64_C(1310764032), // SMINPv16i8
5608
0
    UINT64_C(245410816),  // SMINPv2i32
5609
0
    UINT64_C(241216512),  // SMINPv4i16
5610
0
    UINT64_C(1319152640), // SMINPv4i32
5611
0
    UINT64_C(1314958336), // SMINPv8i16
5612
0
    UINT64_C(237022208),  // SMINPv8i8
5613
0
    UINT64_C(68034560), // SMINQV_VPZ_B
5614
0
    UINT64_C(80617472), // SMINQV_VPZ_D
5615
0
    UINT64_C(72228864), // SMINQV_VPZ_H
5616
0
    UINT64_C(76423168), // SMINQV_VPZ_S
5617
0
    UINT64_C(67772416), // SMINV_VPZ_B
5618
0
    UINT64_C(80355328), // SMINV_VPZ_D
5619
0
    UINT64_C(71966720), // SMINV_VPZ_H
5620
0
    UINT64_C(76161024), // SMINV_VPZ_S
5621
0
    UINT64_C(1311877120), // SMINVv16i8v
5622
0
    UINT64_C(242329600),  // SMINVv4i16v
5623
0
    UINT64_C(1320265728), // SMINVv4i32v
5624
0
    UINT64_C(1316071424), // SMINVv8i16v
5625
0
    UINT64_C(238135296),  // SMINVv8i8v
5626
0
    UINT64_C(298319872),  // SMINWri
5627
0
    UINT64_C(448817152),  // SMINWrr
5628
0
    UINT64_C(2445803520), // SMINXri
5629
0
    UINT64_C(2596300800), // SMINXrr
5630
0
    UINT64_C(3240144928), // SMIN_VG2_2Z2Z_B
5631
0
    UINT64_C(3252727840), // SMIN_VG2_2Z2Z_D
5632
0
    UINT64_C(3244339232), // SMIN_VG2_2Z2Z_H
5633
0
    UINT64_C(3248533536), // SMIN_VG2_2Z2Z_S
5634
0
    UINT64_C(3240140832), // SMIN_VG2_2ZZ_B
5635
0
    UINT64_C(3252723744), // SMIN_VG2_2ZZ_D
5636
0
    UINT64_C(3244335136), // SMIN_VG2_2ZZ_H
5637
0
    UINT64_C(3248529440), // SMIN_VG2_2ZZ_S
5638
0
    UINT64_C(3240146976), // SMIN_VG4_4Z4Z_B
5639
0
    UINT64_C(3252729888), // SMIN_VG4_4Z4Z_D
5640
0
    UINT64_C(3244341280), // SMIN_VG4_4Z4Z_H
5641
0
    UINT64_C(3248535584), // SMIN_VG4_4Z4Z_S
5642
0
    UINT64_C(3240142880), // SMIN_VG4_4ZZ_B
5643
0
    UINT64_C(3252725792), // SMIN_VG4_4ZZ_D
5644
0
    UINT64_C(3244337184), // SMIN_VG4_4ZZ_H
5645
0
    UINT64_C(3248531488), // SMIN_VG4_4ZZ_S
5646
0
    UINT64_C(623558656),  // SMIN_ZI_B
5647
0
    UINT64_C(636141568),  // SMIN_ZI_D
5648
0
    UINT64_C(627752960),  // SMIN_ZI_H
5649
0
    UINT64_C(631947264),  // SMIN_ZI_S
5650
0
    UINT64_C(67764224), // SMIN_ZPmZ_B
5651
0
    UINT64_C(80347136), // SMIN_ZPmZ_D
5652
0
    UINT64_C(71958528), // SMIN_ZPmZ_H
5653
0
    UINT64_C(76152832), // SMIN_ZPmZ_S
5654
0
    UINT64_C(1310747648), // SMINv16i8
5655
0
    UINT64_C(245394432),  // SMINv2i32
5656
0
    UINT64_C(241200128),  // SMINv4i16
5657
0
    UINT64_C(1319136256), // SMINv4i32
5658
0
    UINT64_C(1314941952), // SMINv8i16
5659
0
    UINT64_C(237005824),  // SMINv8i8
5660
0
    UINT64_C(1155563520), // SMLALB_ZZZI_D
5661
0
    UINT64_C(1151369216), // SMLALB_ZZZI_S
5662
0
    UINT64_C(1153449984), // SMLALB_ZZZ_D
5663
0
    UINT64_C(1145061376), // SMLALB_ZZZ_H
5664
0
    UINT64_C(1149255680), // SMLALB_ZZZ_S
5665
0
    UINT64_C(3238002688), // SMLALL_MZZI_BtoS
5666
0
    UINT64_C(3246391296), // SMLALL_MZZI_HtoD
5667
0
    UINT64_C(3240100864), // SMLALL_MZZ_BtoS
5668
0
    UINT64_C(3244295168), // SMLALL_MZZ_HtoD
5669
0
    UINT64_C(3248488448), // SMLALL_VG2_M2Z2Z_BtoS
5670
0
    UINT64_C(3252682752), // SMLALL_VG2_M2Z2Z_HtoD
5671
0
    UINT64_C(3239051264), // SMLALL_VG2_M2ZZI_BtoS
5672
0
    UINT64_C(3247439872), // SMLALL_VG2_M2ZZI_HtoD
5673
0
    UINT64_C(3240099840), // SMLALL_VG2_M2ZZ_BtoS
5674
0
    UINT64_C(3244294144), // SMLALL_VG2_M2ZZ_HtoD
5675
0
    UINT64_C(3248553984), // SMLALL_VG4_M4Z4Z_BtoS
5676
0
    UINT64_C(3252748288), // SMLALL_VG4_M4Z4Z_HtoD
5677
0
    UINT64_C(3239084032), // SMLALL_VG4_M4ZZI_BtoS
5678
0
    UINT64_C(3247472640), // SMLALL_VG4_M4ZZI_HtoD
5679
0
    UINT64_C(3241148416), // SMLALL_VG4_M4ZZ_BtoS
5680
0
    UINT64_C(3245342720), // SMLALL_VG4_M4ZZ_HtoD
5681
0
    UINT64_C(1155564544), // SMLALT_ZZZI_D
5682
0
    UINT64_C(1151370240), // SMLALT_ZZZI_S
5683
0
    UINT64_C(1153451008), // SMLALT_ZZZ_D
5684
0
    UINT64_C(1145062400), // SMLALT_ZZZ_H
5685
0
    UINT64_C(1149256704), // SMLALT_ZZZ_S
5686
0
    UINT64_C(3250589696), // SMLAL_MZZI_HtoS
5687
0
    UINT64_C(3244297216), // SMLAL_MZZ_HtoS
5688
0
    UINT64_C(3252684800), // SMLAL_VG2_M2Z2Z_HtoS
5689
0
    UINT64_C(3251638272), // SMLAL_VG2_M2ZZI_S
5690
0
    UINT64_C(3244296192), // SMLAL_VG2_M2ZZ_HtoS
5691
0
    UINT64_C(3252750336), // SMLAL_VG4_M4Z4Z_HtoS
5692
0
    UINT64_C(3251671040), // SMLAL_VG4_M4ZZI_HtoS
5693
0
    UINT64_C(3245344768), // SMLAL_VG4_M4ZZ_HtoS
5694
0
    UINT64_C(1310752768), // SMLALv16i8_v8i16
5695
0
    UINT64_C(260055040),  // SMLALv2i32_indexed
5696
0
    UINT64_C(245399552),  // SMLALv2i32_v2i64
5697
0
    UINT64_C(255860736),  // SMLALv4i16_indexed
5698
0
    UINT64_C(241205248),  // SMLALv4i16_v4i32
5699
0
    UINT64_C(1333796864), // SMLALv4i32_indexed
5700
0
    UINT64_C(1319141376), // SMLALv4i32_v2i64
5701
0
    UINT64_C(1329602560), // SMLALv8i16_indexed
5702
0
    UINT64_C(1314947072), // SMLALv8i16_v4i32
5703
0
    UINT64_C(237010944),  // SMLALv8i8_v8i16
5704
0
    UINT64_C(1155571712), // SMLSLB_ZZZI_D
5705
0
    UINT64_C(1151377408), // SMLSLB_ZZZI_S
5706
0
    UINT64_C(1153454080), // SMLSLB_ZZZ_D
5707
0
    UINT64_C(1145065472), // SMLSLB_ZZZ_H
5708
0
    UINT64_C(1149259776), // SMLSLB_ZZZ_S
5709
0
    UINT64_C(3238002696), // SMLSLL_MZZI_BtoS
5710
0
    UINT64_C(3246391304), // SMLSLL_MZZI_HtoD
5711
0
    UINT64_C(3240100872), // SMLSLL_MZZ_BtoS
5712
0
    UINT64_C(3244295176), // SMLSLL_MZZ_HtoD
5713
0
    UINT64_C(3248488456), // SMLSLL_VG2_M2Z2Z_BtoS
5714
0
    UINT64_C(3252682760), // SMLSLL_VG2_M2Z2Z_HtoD
5715
0
    UINT64_C(3239051272), // SMLSLL_VG2_M2ZZI_BtoS
5716
0
    UINT64_C(3247439880), // SMLSLL_VG2_M2ZZI_HtoD
5717
0
    UINT64_C(3240099848), // SMLSLL_VG2_M2ZZ_BtoS
5718
0
    UINT64_C(3244294152), // SMLSLL_VG2_M2ZZ_HtoD
5719
0
    UINT64_C(3248553992), // SMLSLL_VG4_M4Z4Z_BtoS
5720
0
    UINT64_C(3252748296), // SMLSLL_VG4_M4Z4Z_HtoD
5721
0
    UINT64_C(3239084040), // SMLSLL_VG4_M4ZZI_BtoS
5722
0
    UINT64_C(3247472648), // SMLSLL_VG4_M4ZZI_HtoD
5723
0
    UINT64_C(3241148424), // SMLSLL_VG4_M4ZZ_BtoS
5724
0
    UINT64_C(3245342728), // SMLSLL_VG4_M4ZZ_HtoD
5725
0
    UINT64_C(1155572736), // SMLSLT_ZZZI_D
5726
0
    UINT64_C(1151378432), // SMLSLT_ZZZI_S
5727
0
    UINT64_C(1153455104), // SMLSLT_ZZZ_D
5728
0
    UINT64_C(1145066496), // SMLSLT_ZZZ_H
5729
0
    UINT64_C(1149260800), // SMLSLT_ZZZ_S
5730
0
    UINT64_C(3250589704), // SMLSL_MZZI_HtoS
5731
0
    UINT64_C(3244297224), // SMLSL_MZZ_HtoS
5732
0
    UINT64_C(3252684808), // SMLSL_VG2_M2Z2Z_HtoS
5733
0
    UINT64_C(3251638280), // SMLSL_VG2_M2ZZI_S
5734
0
    UINT64_C(3244296200), // SMLSL_VG2_M2ZZ_HtoS
5735
0
    UINT64_C(3252750344), // SMLSL_VG4_M4Z4Z_HtoS
5736
0
    UINT64_C(3251671048), // SMLSL_VG4_M4ZZI_HtoS
5737
0
    UINT64_C(3245344776), // SMLSL_VG4_M4ZZ_HtoS
5738
0
    UINT64_C(1310760960), // SMLSLv16i8_v8i16
5739
0
    UINT64_C(260071424),  // SMLSLv2i32_indexed
5740
0
    UINT64_C(245407744),  // SMLSLv2i32_v2i64
5741
0
    UINT64_C(255877120),  // SMLSLv4i16_indexed
5742
0
    UINT64_C(241213440),  // SMLSLv4i16_v4i32
5743
0
    UINT64_C(1333813248), // SMLSLv4i32_indexed
5744
0
    UINT64_C(1319149568), // SMLSLv4i32_v2i64
5745
0
    UINT64_C(1329618944), // SMLSLv8i16_indexed
5746
0
    UINT64_C(1314955264), // SMLSLv8i16_v4i32
5747
0
    UINT64_C(237019136),  // SMLSLv8i8_v8i16
5748
0
    UINT64_C(1317053440), // SMMLA
5749
0
    UINT64_C(1157666816), // SMMLA_ZZZ
5750
0
    UINT64_C(2696937472), // SMOPA_MPPZZ_D
5751
0
    UINT64_C(2692743176), // SMOPA_MPPZZ_HtoS
5752
0
    UINT64_C(2692743168), // SMOPA_MPPZZ_S
5753
0
    UINT64_C(2696937488), // SMOPS_MPPZZ_D
5754
0
    UINT64_C(2692743192), // SMOPS_MPPZZ_HtoS
5755
0
    UINT64_C(2692743184), // SMOPS_MPPZZ_S
5756
0
    UINT64_C(235023360),  // SMOVvi16to32
5757
0
    UINT64_C(235023360),  // SMOVvi16to32_idx0
5758
0
    UINT64_C(1308765184), // SMOVvi16to64
5759
0
    UINT64_C(1308765184), // SMOVvi16to64_idx0
5760
0
    UINT64_C(1308896256), // SMOVvi32to64
5761
0
    UINT64_C(1308896256), // SMOVvi32to64_idx0
5762
0
    UINT64_C(234957824),  // SMOVvi8to32
5763
0
    UINT64_C(234957824),  // SMOVvi8to32_idx0
5764
0
    UINT64_C(1308699648), // SMOVvi8to64
5765
0
    UINT64_C(1308699648), // SMOVvi8to64_idx0
5766
0
    UINT64_C(2602598400), // SMSUBLrrr
5767
0
    UINT64_C(68288512), // SMULH_ZPmZ_B
5768
0
    UINT64_C(80871424), // SMULH_ZPmZ_D
5769
0
    UINT64_C(72482816), // SMULH_ZPmZ_H
5770
0
    UINT64_C(76677120), // SMULH_ZPmZ_S
5771
0
    UINT64_C(69232640), // SMULH_ZZZ_B
5772
0
    UINT64_C(81815552), // SMULH_ZZZ_D
5773
0
    UINT64_C(73426944), // SMULH_ZZZ_H
5774
0
    UINT64_C(77621248), // SMULH_ZZZ_S
5775
0
    UINT64_C(2604662784), // SMULHrr
5776
0
    UINT64_C(1155579904), // SMULLB_ZZZI_D
5777
0
    UINT64_C(1151385600), // SMULLB_ZZZI_S
5778
0
    UINT64_C(1170239488), // SMULLB_ZZZ_D
5779
0
    UINT64_C(1161850880), // SMULLB_ZZZ_H
5780
0
    UINT64_C(1166045184), // SMULLB_ZZZ_S
5781
0
    UINT64_C(1155580928), // SMULLT_ZZZI_D
5782
0
    UINT64_C(1151386624), // SMULLT_ZZZI_S
5783
0
    UINT64_C(1170240512), // SMULLT_ZZZ_D
5784
0
    UINT64_C(1161851904), // SMULLT_ZZZ_H
5785
0
    UINT64_C(1166046208), // SMULLT_ZZZ_S
5786
0
    UINT64_C(1310769152), // SMULLv16i8_v8i16
5787
0
    UINT64_C(260087808),  // SMULLv2i32_indexed
5788
0
    UINT64_C(245415936),  // SMULLv2i32_v2i64
5789
0
    UINT64_C(255893504),  // SMULLv4i16_indexed
5790
0
    UINT64_C(241221632),  // SMULLv4i16_v4i32
5791
0
    UINT64_C(1333829632), // SMULLv4i32_indexed
5792
0
    UINT64_C(1319157760), // SMULLv4i32_v2i64
5793
0
    UINT64_C(1329635328), // SMULLv8i16_indexed
5794
0
    UINT64_C(1314963456), // SMULLv8i16_v4i32
5795
0
    UINT64_C(237027328),  // SMULLv8i8_v8i16
5796
0
    UINT64_C(86867968), // SPLICE_ZPZZ_B
5797
0
    UINT64_C(99450880), // SPLICE_ZPZZ_D
5798
0
    UINT64_C(91062272), // SPLICE_ZPZZ_H
5799
0
    UINT64_C(95256576), // SPLICE_ZPZZ_S
5800
0
    UINT64_C(86802432), // SPLICE_ZPZ_B
5801
0
    UINT64_C(99385344), // SPLICE_ZPZ_D
5802
0
    UINT64_C(90996736), // SPLICE_ZPZ_H
5803
0
    UINT64_C(95191040), // SPLICE_ZPZ_S
5804
0
    UINT64_C(1141415936), // SQABS_ZPmZ_B
5805
0
    UINT64_C(1153998848), // SQABS_ZPmZ_D
5806
0
    UINT64_C(1145610240), // SQABS_ZPmZ_H
5807
0
    UINT64_C(1149804544), // SQABS_ZPmZ_S
5808
0
    UINT64_C(1310750720), // SQABSv16i8
5809
0
    UINT64_C(1583380480), // SQABSv1i16
5810
0
    UINT64_C(1587574784), // SQABSv1i32
5811
0
    UINT64_C(1591769088), // SQABSv1i64
5812
0
    UINT64_C(1579186176), // SQABSv1i8
5813
0
    UINT64_C(245397504),  // SQABSv2i32
5814
0
    UINT64_C(1323333632), // SQABSv2i64
5815
0
    UINT64_C(241203200),  // SQABSv4i16
5816
0
    UINT64_C(1319139328), // SQABSv4i32
5817
0
    UINT64_C(1314945024), // SQABSv8i16
5818
0
    UINT64_C(237008896),  // SQABSv8i8
5819
0
    UINT64_C(623165440),  // SQADD_ZI_B
5820
0
    UINT64_C(635748352),  // SQADD_ZI_D
5821
0
    UINT64_C(627359744),  // SQADD_ZI_H
5822
0
    UINT64_C(631554048),  // SQADD_ZI_S
5823
0
    UINT64_C(1142456320), // SQADD_ZPmZ_B
5824
0
    UINT64_C(1155039232), // SQADD_ZPmZ_D
5825
0
    UINT64_C(1146650624), // SQADD_ZPmZ_H
5826
0
    UINT64_C(1150844928), // SQADD_ZPmZ_S
5827
0
    UINT64_C(69210112), // SQADD_ZZZ_B
5828
0
    UINT64_C(81793024), // SQADD_ZZZ_D
5829
0
    UINT64_C(73404416), // SQADD_ZZZ_H
5830
0
    UINT64_C(77598720), // SQADD_ZZZ_S
5831
0
    UINT64_C(1310723072), // SQADDv16i8
5832
0
    UINT64_C(1583352832), // SQADDv1i16
5833
0
    UINT64_C(1587547136), // SQADDv1i32
5834
0
    UINT64_C(1591741440), // SQADDv1i64
5835
0
    UINT64_C(1579158528), // SQADDv1i8
5836
0
    UINT64_C(245369856),  // SQADDv2i32
5837
0
    UINT64_C(1323305984), // SQADDv2i64
5838
0
    UINT64_C(241175552),  // SQADDv4i16
5839
0
    UINT64_C(1319111680), // SQADDv4i32
5840
0
    UINT64_C(1314917376), // SQADDv8i16
5841
0
    UINT64_C(236981248),  // SQADDv8i8
5842
0
    UINT64_C(1157748736), // SQCADD_ZZI_B
5843
0
    UINT64_C(1170331648), // SQCADD_ZZI_D
5844
0
    UINT64_C(1161943040), // SQCADD_ZZI_H
5845
0
    UINT64_C(1166137344), // SQCADD_ZZI_S
5846
0
    UINT64_C(1160855552), // SQCVTN_Z2Z_StoH
5847
0
    UINT64_C(3249791040), // SQCVTN_Z4Z_DtoH
5848
0
    UINT64_C(3241402432), // SQCVTN_Z4Z_StoB
5849
0
    UINT64_C(1160859648), // SQCVTUN_Z2Z_StoH
5850
0
    UINT64_C(3253985344), // SQCVTUN_Z4Z_DtoH
5851
0
    UINT64_C(3245596736), // SQCVTUN_Z4Z_StoB
5852
0
    UINT64_C(3244548096), // SQCVTU_Z2Z_StoH
5853
0
    UINT64_C(3253985280), // SQCVTU_Z4Z_DtoH
5854
0
    UINT64_C(3245596672), // SQCVTU_Z4Z_StoB
5855
0
    UINT64_C(3240353792), // SQCVT_Z2Z_StoH
5856
0
    UINT64_C(3249790976), // SQCVT_Z4Z_DtoH
5857
0
    UINT64_C(3241402368), // SQCVT_Z4Z_StoB
5858
0
    UINT64_C(70318080), // SQDECB_XPiI
5859
0
    UINT64_C(69269504), // SQDECB_XPiWdI
5860
0
    UINT64_C(82900992), // SQDECD_XPiI
5861
0
    UINT64_C(81852416), // SQDECD_XPiWdI
5862
0
    UINT64_C(81840128), // SQDECD_ZPiI
5863
0
    UINT64_C(74512384), // SQDECH_XPiI
5864
0
    UINT64_C(73463808), // SQDECH_XPiWdI
5865
0
    UINT64_C(73451520), // SQDECH_ZPiI
5866
0
    UINT64_C(623544320),  // SQDECP_XPWd_B
5867
0
    UINT64_C(636127232),  // SQDECP_XPWd_D
5868
0
    UINT64_C(627738624),  // SQDECP_XPWd_H
5869
0
    UINT64_C(631932928),  // SQDECP_XPWd_S
5870
0
    UINT64_C(623545344),  // SQDECP_XP_B
5871
0
    UINT64_C(636128256),  // SQDECP_XP_D
5872
0
    UINT64_C(627739648),  // SQDECP_XP_H
5873
0
    UINT64_C(631933952),  // SQDECP_XP_S
5874
0
    UINT64_C(636125184),  // SQDECP_ZP_D
5875
0
    UINT64_C(627736576),  // SQDECP_ZP_H
5876
0
    UINT64_C(631930880),  // SQDECP_ZP_S
5877
0
    UINT64_C(78706688), // SQDECW_XPiI
5878
0
    UINT64_C(77658112), // SQDECW_XPiWdI
5879
0
    UINT64_C(77645824), // SQDECW_ZPiI
5880
0
    UINT64_C(1153435648), // SQDMLALBT_ZZZ_D
5881
0
    UINT64_C(1145047040), // SQDMLALBT_ZZZ_H
5882
0
    UINT64_C(1149241344), // SQDMLALBT_ZZZ_S
5883
0
    UINT64_C(1155538944), // SQDMLALB_ZZZI_D
5884
0
    UINT64_C(1151344640), // SQDMLALB_ZZZI_S
5885
0
    UINT64_C(1153458176), // SQDMLALB_ZZZ_D
5886
0
    UINT64_C(1145069568), // SQDMLALB_ZZZ_H
5887
0
    UINT64_C(1149263872), // SQDMLALB_ZZZ_S
5888
0
    UINT64_C(1155539968), // SQDMLALT_ZZZI_D
5889
0
    UINT64_C(1151345664), // SQDMLALT_ZZZI_S
5890
0
    UINT64_C(1153459200), // SQDMLALT_ZZZ_D
5891
0
    UINT64_C(1145070592), // SQDMLALT_ZZZ_H
5892
0
    UINT64_C(1149264896), // SQDMLALT_ZZZ_S
5893
0
    UINT64_C(1583386624), // SQDMLALi16
5894
0
    UINT64_C(1587580928), // SQDMLALi32
5895
0
    UINT64_C(1598042112), // SQDMLALv1i32_indexed
5896
0
    UINT64_C(1602236416), // SQDMLALv1i64_indexed
5897
0
    UINT64_C(260059136),  // SQDMLALv2i32_indexed
5898
0
    UINT64_C(245403648),  // SQDMLALv2i32_v2i64
5899
0
    UINT64_C(255864832),  // SQDMLALv4i16_indexed
5900
0
    UINT64_C(241209344),  // SQDMLALv4i16_v4i32
5901
0
    UINT64_C(1333800960), // SQDMLALv4i32_indexed
5902
0
    UINT64_C(1319145472), // SQDMLALv4i32_v2i64
5903
0
    UINT64_C(1329606656), // SQDMLALv8i16_indexed
5904
0
    UINT64_C(1314951168), // SQDMLALv8i16_v4i32
5905
0
    UINT64_C(1153436672), // SQDMLSLBT_ZZZ_D
5906
0
    UINT64_C(1145048064), // SQDMLSLBT_ZZZ_H
5907
0
    UINT64_C(1149242368), // SQDMLSLBT_ZZZ_S
5908
0
    UINT64_C(1155543040), // SQDMLSLB_ZZZI_D
5909
0
    UINT64_C(1151348736), // SQDMLSLB_ZZZI_S
5910
0
    UINT64_C(1153460224), // SQDMLSLB_ZZZ_D
5911
0
    UINT64_C(1145071616), // SQDMLSLB_ZZZ_H
5912
0
    UINT64_C(1149265920), // SQDMLSLB_ZZZ_S
5913
0
    UINT64_C(1155544064), // SQDMLSLT_ZZZI_D
5914
0
    UINT64_C(1151349760), // SQDMLSLT_ZZZI_S
5915
0
    UINT64_C(1153461248), // SQDMLSLT_ZZZ_D
5916
0
    UINT64_C(1145072640), // SQDMLSLT_ZZZ_H
5917
0
    UINT64_C(1149266944), // SQDMLSLT_ZZZ_S
5918
0
    UINT64_C(1583394816), // SQDMLSLi16
5919
0
    UINT64_C(1587589120), // SQDMLSLi32
5920
0
    UINT64_C(1598058496), // SQDMLSLv1i32_indexed
5921
0
    UINT64_C(1602252800), // SQDMLSLv1i64_indexed
5922
0
    UINT64_C(260075520),  // SQDMLSLv2i32_indexed
5923
0
    UINT64_C(245411840),  // SQDMLSLv2i32_v2i64
5924
0
    UINT64_C(255881216),  // SQDMLSLv4i16_indexed
5925
0
    UINT64_C(241217536),  // SQDMLSLv4i16_v4i32
5926
0
    UINT64_C(1333817344), // SQDMLSLv4i32_indexed
5927
0
    UINT64_C(1319153664), // SQDMLSLv4i32_v2i64
5928
0
    UINT64_C(1329623040), // SQDMLSLv8i16_indexed
5929
0
    UINT64_C(1314959360), // SQDMLSLv8i16_v4i32
5930
0
    UINT64_C(3240145920), // SQDMULH_VG2_2Z2Z_B
5931
0
    UINT64_C(3252728832), // SQDMULH_VG2_2Z2Z_D
5932
0
    UINT64_C(3244340224), // SQDMULH_VG2_2Z2Z_H
5933
0
    UINT64_C(3248534528), // SQDMULH_VG2_2Z2Z_S
5934
0
    UINT64_C(3240141824), // SQDMULH_VG2_2ZZ_B
5935
0
    UINT64_C(3252724736), // SQDMULH_VG2_2ZZ_D
5936
0
    UINT64_C(3244336128), // SQDMULH_VG2_2ZZ_H
5937
0
    UINT64_C(3248530432), // SQDMULH_VG2_2ZZ_S
5938
0
    UINT64_C(3240147968), // SQDMULH_VG4_4Z4Z_B
5939
0
    UINT64_C(3252730880), // SQDMULH_VG4_4Z4Z_D
5940
0
    UINT64_C(3244342272), // SQDMULH_VG4_4Z4Z_H
5941
0
    UINT64_C(3248536576), // SQDMULH_VG4_4Z4Z_S
5942
0
    UINT64_C(3240143872), // SQDMULH_VG4_4ZZ_B
5943
0
    UINT64_C(3252726784), // SQDMULH_VG4_4ZZ_D
5944
0
    UINT64_C(3244338176), // SQDMULH_VG4_4ZZ_H
5945
0
    UINT64_C(3248532480), // SQDMULH_VG4_4ZZ_S
5946
0
    UINT64_C(1155592192), // SQDMULH_ZZZI_D
5947
0
    UINT64_C(1143009280), // SQDMULH_ZZZI_H
5948
0
    UINT64_C(1151397888), // SQDMULH_ZZZI_S
5949
0
    UINT64_C(69234688), // SQDMULH_ZZZ_B
5950
0
    UINT64_C(81817600), // SQDMULH_ZZZ_D
5951
0
    UINT64_C(73428992), // SQDMULH_ZZZ_H
5952
0
    UINT64_C(77623296), // SQDMULH_ZZZ_S
5953
0
    UINT64_C(1583395840), // SQDMULHv1i16
5954
0
    UINT64_C(1598078976), // SQDMULHv1i16_indexed
5955
0
    UINT64_C(1587590144), // SQDMULHv1i32
5956
0
    UINT64_C(1602273280), // SQDMULHv1i32_indexed
5957
0
    UINT64_C(245412864),  // SQDMULHv2i32
5958
0
    UINT64_C(260096000),  // SQDMULHv2i32_indexed
5959
0
    UINT64_C(241218560),  // SQDMULHv4i16
5960
0
    UINT64_C(255901696),  // SQDMULHv4i16_indexed
5961
0
    UINT64_C(1319154688), // SQDMULHv4i32
5962
0
    UINT64_C(1333837824), // SQDMULHv4i32_indexed
5963
0
    UINT64_C(1314960384), // SQDMULHv8i16
5964
0
    UINT64_C(1329643520), // SQDMULHv8i16_indexed
5965
0
    UINT64_C(1155588096), // SQDMULLB_ZZZI_D
5966
0
    UINT64_C(1151393792), // SQDMULLB_ZZZI_S
5967
0
    UINT64_C(1170235392), // SQDMULLB_ZZZ_D
5968
0
    UINT64_C(1161846784), // SQDMULLB_ZZZ_H
5969
0
    UINT64_C(1166041088), // SQDMULLB_ZZZ_S
5970
0
    UINT64_C(1155589120), // SQDMULLT_ZZZI_D
5971
0
    UINT64_C(1151394816), // SQDMULLT_ZZZI_S
5972
0
    UINT64_C(1170236416), // SQDMULLT_ZZZ_D
5973
0
    UINT64_C(1161847808), // SQDMULLT_ZZZ_H
5974
0
    UINT64_C(1166042112), // SQDMULLT_ZZZ_S
5975
0
    UINT64_C(1583403008), // SQDMULLi16
5976
0
    UINT64_C(1587597312), // SQDMULLi32
5977
0
    UINT64_C(1598074880), // SQDMULLv1i32_indexed
5978
0
    UINT64_C(1602269184), // SQDMULLv1i64_indexed
5979
0
    UINT64_C(260091904),  // SQDMULLv2i32_indexed
5980
0
    UINT64_C(245420032),  // SQDMULLv2i32_v2i64
5981
0
    UINT64_C(255897600),  // SQDMULLv4i16_indexed
5982
0
    UINT64_C(241225728),  // SQDMULLv4i16_v4i32
5983
0
    UINT64_C(1333833728), // SQDMULLv4i32_indexed
5984
0
    UINT64_C(1319161856), // SQDMULLv4i32_v2i64
5985
0
    UINT64_C(1329639424), // SQDMULLv8i16_indexed
5986
0
    UINT64_C(1314967552), // SQDMULLv8i16_v4i32
5987
0
    UINT64_C(70316032), // SQINCB_XPiI
5988
0
    UINT64_C(69267456), // SQINCB_XPiWdI
5989
0
    UINT64_C(82898944), // SQINCD_XPiI
5990
0
    UINT64_C(81850368), // SQINCD_XPiWdI
5991
0
    UINT64_C(81838080), // SQINCD_ZPiI
5992
0
    UINT64_C(74510336), // SQINCH_XPiI
5993
0
    UINT64_C(73461760), // SQINCH_XPiWdI
5994
0
    UINT64_C(73449472), // SQINCH_ZPiI
5995
0
    UINT64_C(623413248),  // SQINCP_XPWd_B
5996
0
    UINT64_C(635996160),  // SQINCP_XPWd_D
5997
0
    UINT64_C(627607552),  // SQINCP_XPWd_H
5998
0
    UINT64_C(631801856),  // SQINCP_XPWd_S
5999
0
    UINT64_C(623414272),  // SQINCP_XP_B
6000
0
    UINT64_C(635997184),  // SQINCP_XP_D
6001
0
    UINT64_C(627608576),  // SQINCP_XP_H
6002
0
    UINT64_C(631802880),  // SQINCP_XP_S
6003
0
    UINT64_C(635994112),  // SQINCP_ZP_D
6004
0
    UINT64_C(627605504),  // SQINCP_ZP_H
6005
0
    UINT64_C(631799808),  // SQINCP_ZP_S
6006
0
    UINT64_C(78704640), // SQINCW_XPiI
6007
0
    UINT64_C(77656064), // SQINCW_XPiWdI
6008
0
    UINT64_C(77643776), // SQINCW_ZPiI
6009
0
    UINT64_C(1141481472), // SQNEG_ZPmZ_B
6010
0
    UINT64_C(1154064384), // SQNEG_ZPmZ_D
6011
0
    UINT64_C(1145675776), // SQNEG_ZPmZ_H
6012
0
    UINT64_C(1149870080), // SQNEG_ZPmZ_S
6013
0
    UINT64_C(1847621632), // SQNEGv16i8
6014
0
    UINT64_C(2120251392), // SQNEGv1i16
6015
0
    UINT64_C(2124445696), // SQNEGv1i32
6016
0
    UINT64_C(2128640000), // SQNEGv1i64
6017
0
    UINT64_C(2116057088), // SQNEGv1i8
6018
0
    UINT64_C(782268416),  // SQNEGv2i32
6019
0
    UINT64_C(1860204544), // SQNEGv2i64
6020
0
    UINT64_C(778074112),  // SQNEGv4i16
6021
0
    UINT64_C(1856010240), // SQNEGv4i32
6022
0
    UINT64_C(1851815936), // SQNEGv8i16
6023
0
    UINT64_C(773879808),  // SQNEGv8i8
6024
0
    UINT64_C(1151365120), // SQRDCMLAH_ZZZI_H
6025
0
    UINT64_C(1155559424), // SQRDCMLAH_ZZZI_S
6026
0
    UINT64_C(1140862976), // SQRDCMLAH_ZZZ_B
6027
0
    UINT64_C(1153445888), // SQRDCMLAH_ZZZ_D
6028
0
    UINT64_C(1145057280), // SQRDCMLAH_ZZZ_H
6029
0
    UINT64_C(1149251584), // SQRDCMLAH_ZZZ_S
6030
0
    UINT64_C(1155534848), // SQRDMLAH_ZZZI_D
6031
0
    UINT64_C(1142951936), // SQRDMLAH_ZZZI_H
6032
0
    UINT64_C(1151340544), // SQRDMLAH_ZZZI_S
6033
0
    UINT64_C(1140879360), // SQRDMLAH_ZZZ_B
6034
0
    UINT64_C(1153462272), // SQRDMLAH_ZZZ_D
6035
0
    UINT64_C(1145073664), // SQRDMLAH_ZZZ_H
6036
0
    UINT64_C(1149267968), // SQRDMLAH_ZZZ_S
6037
0
    UINT64_C(2118157312), // SQRDMLAHv1i16
6038
0
    UINT64_C(2134953984), // SQRDMLAHv1i16_indexed
6039
0
    UINT64_C(2122351616), // SQRDMLAHv1i32
6040
0
    UINT64_C(2139148288), // SQRDMLAHv1i32_indexed
6041
0
    UINT64_C(780174336),  // SQRDMLAHv2i32
6042
0
    UINT64_C(796971008),  // SQRDMLAHv2i32_indexed
6043
0
    UINT64_C(775980032),  // SQRDMLAHv4i16
6044
0
    UINT64_C(792776704),  // SQRDMLAHv4i16_indexed
6045
0
    UINT64_C(1853916160), // SQRDMLAHv4i32
6046
0
    UINT64_C(1870712832), // SQRDMLAHv4i32_indexed
6047
0
    UINT64_C(1849721856), // SQRDMLAHv8i16
6048
0
    UINT64_C(1866518528), // SQRDMLAHv8i16_indexed
6049
0
    UINT64_C(1155535872), // SQRDMLSH_ZZZI_D
6050
0
    UINT64_C(1142952960), // SQRDMLSH_ZZZI_H
6051
0
    UINT64_C(1151341568), // SQRDMLSH_ZZZI_S
6052
0
    UINT64_C(1140880384), // SQRDMLSH_ZZZ_B
6053
0
    UINT64_C(1153463296), // SQRDMLSH_ZZZ_D
6054
0
    UINT64_C(1145074688), // SQRDMLSH_ZZZ_H
6055
0
    UINT64_C(1149268992), // SQRDMLSH_ZZZ_S
6056
0
    UINT64_C(2118159360), // SQRDMLSHv1i16
6057
0
    UINT64_C(2134962176), // SQRDMLSHv1i16_indexed
6058
0
    UINT64_C(2122353664), // SQRDMLSHv1i32
6059
0
    UINT64_C(2139156480), // SQRDMLSHv1i32_indexed
6060
0
    UINT64_C(780176384),  // SQRDMLSHv2i32
6061
0
    UINT64_C(796979200),  // SQRDMLSHv2i32_indexed
6062
0
    UINT64_C(775982080),  // SQRDMLSHv4i16
6063
0
    UINT64_C(792784896),  // SQRDMLSHv4i16_indexed
6064
0
    UINT64_C(1853918208), // SQRDMLSHv4i32
6065
0
    UINT64_C(1870721024), // SQRDMLSHv4i32_indexed
6066
0
    UINT64_C(1849723904), // SQRDMLSHv8i16
6067
0
    UINT64_C(1866526720), // SQRDMLSHv8i16_indexed
6068
0
    UINT64_C(1155593216), // SQRDMULH_ZZZI_D
6069
0
    UINT64_C(1143010304), // SQRDMULH_ZZZI_H
6070
0
    UINT64_C(1151398912), // SQRDMULH_ZZZI_S
6071
0
    UINT64_C(69235712), // SQRDMULH_ZZZ_B
6072
0
    UINT64_C(81818624), // SQRDMULH_ZZZ_D
6073
0
    UINT64_C(73430016), // SQRDMULH_ZZZ_H
6074
0
    UINT64_C(77624320), // SQRDMULH_ZZZ_S
6075
0
    UINT64_C(2120266752), // SQRDMULHv1i16
6076
0
    UINT64_C(1598083072), // SQRDMULHv1i16_indexed
6077
0
    UINT64_C(2124461056), // SQRDMULHv1i32
6078
0
    UINT64_C(1602277376), // SQRDMULHv1i32_indexed
6079
0
    UINT64_C(782283776),  // SQRDMULHv2i32
6080
0
    UINT64_C(260100096),  // SQRDMULHv2i32_indexed
6081
0
    UINT64_C(778089472),  // SQRDMULHv4i16
6082
0
    UINT64_C(255905792),  // SQRDMULHv4i16_indexed
6083
0
    UINT64_C(1856025600), // SQRDMULHv4i32
6084
0
    UINT64_C(1333841920), // SQRDMULHv4i32_indexed
6085
0
    UINT64_C(1851831296), // SQRDMULHv8i16
6086
0
    UINT64_C(1329647616), // SQRDMULHv8i16_indexed
6087
0
    UINT64_C(1141800960), // SQRSHLR_ZPmZ_B
6088
0
    UINT64_C(1154383872), // SQRSHLR_ZPmZ_D
6089
0
    UINT64_C(1145995264), // SQRSHLR_ZPmZ_H
6090
0
    UINT64_C(1150189568), // SQRSHLR_ZPmZ_S
6091
0
    UINT64_C(1141538816), // SQRSHL_ZPmZ_B
6092
0
    UINT64_C(1154121728), // SQRSHL_ZPmZ_D
6093
0
    UINT64_C(1145733120), // SQRSHL_ZPmZ_H
6094
0
    UINT64_C(1149927424), // SQRSHL_ZPmZ_S
6095
0
    UINT64_C(1310743552), // SQRSHLv16i8
6096
0
    UINT64_C(1583373312), // SQRSHLv1i16
6097
0
    UINT64_C(1587567616), // SQRSHLv1i32
6098
0
    UINT64_C(1591761920), // SQRSHLv1i64
6099
0
    UINT64_C(1579179008), // SQRSHLv1i8
6100
0
    UINT64_C(245390336),  // SQRSHLv2i32
6101
0
    UINT64_C(1323326464), // SQRSHLv2i64
6102
0
    UINT64_C(241196032),  // SQRSHLv4i16
6103
0
    UINT64_C(1319132160), // SQRSHLv4i32
6104
0
    UINT64_C(1314937856), // SQRSHLv8i16
6105
0
    UINT64_C(237001728),  // SQRSHLv8i8
6106
0
    UINT64_C(1160259584), // SQRSHRNB_ZZI_B
6107
0
    UINT64_C(1160783872), // SQRSHRNB_ZZI_H
6108
0
    UINT64_C(1163929600), // SQRSHRNB_ZZI_S
6109
0
    UINT64_C(1160260608), // SQRSHRNT_ZZI_B
6110
0
    UINT64_C(1160784896), // SQRSHRNT_ZZI_H
6111
0
    UINT64_C(1163930624), // SQRSHRNT_ZZI_S
6112
0
    UINT64_C(3244350464), // SQRSHRN_VG4_Z4ZI_B
6113
0
    UINT64_C(3248544768), // SQRSHRN_VG4_Z4ZI_H
6114
0
    UINT64_C(1169172480), // SQRSHRN_Z2ZI_StoH
6115
0
    UINT64_C(1594399744), // SQRSHRNb
6116
0
    UINT64_C(1594924032), // SQRSHRNh
6117
0
    UINT64_C(1595972608), // SQRSHRNs
6118
0
    UINT64_C(1325964288), // SQRSHRNv16i8_shift
6119
0
    UINT64_C(253795328),  // SQRSHRNv2i32_shift
6120
0
    UINT64_C(252746752),  // SQRSHRNv4i16_shift
6121
0
    UINT64_C(1327537152), // SQRSHRNv4i32_shift
6122
0
    UINT64_C(1326488576), // SQRSHRNv8i16_shift
6123
0
    UINT64_C(252222464),  // SQRSHRNv8i8_shift
6124
0
    UINT64_C(1160251392), // SQRSHRUNB_ZZI_B
6125
0
    UINT64_C(1160775680), // SQRSHRUNB_ZZI_H
6126
0
    UINT64_C(1163921408), // SQRSHRUNB_ZZI_S
6127
0
    UINT64_C(1160252416), // SQRSHRUNT_ZZI_B
6128
0
    UINT64_C(1160776704), // SQRSHRUNT_ZZI_H
6129
0
    UINT64_C(1163922432), // SQRSHRUNT_ZZI_S
6130
0
    UINT64_C(3244350528), // SQRSHRUN_VG4_Z4ZI_B
6131
0
    UINT64_C(3248544832), // SQRSHRUN_VG4_Z4ZI_H
6132
0
    UINT64_C(1169164288), // SQRSHRUN_Z2ZI_StoH
6133
0
    UINT64_C(2131266560), // SQRSHRUNb
6134
0
    UINT64_C(2131790848), // SQRSHRUNh
6135
0
    UINT64_C(2132839424), // SQRSHRUNs
6136
0
    UINT64_C(1862831104), // SQRSHRUNv16i8_shift
6137
0
    UINT64_C(790662144),  // SQRSHRUNv2i32_shift
6138
0
    UINT64_C(789613568),  // SQRSHRUNv4i16_shift
6139
0
    UINT64_C(1864403968), // SQRSHRUNv4i32_shift
6140
0
    UINT64_C(1863355392), // SQRSHRUNv8i16_shift
6141
0
    UINT64_C(789089280),  // SQRSHRUNv8i8_shift
6142
0
    UINT64_C(3253785600), // SQRSHRU_VG2_Z2ZI_H
6143
0
    UINT64_C(3244349504), // SQRSHRU_VG4_Z4ZI_B
6144
0
    UINT64_C(3248543808), // SQRSHRU_VG4_Z4ZI_H
6145
0
    UINT64_C(3252737024), // SQRSHR_VG2_Z2ZI_H
6146
0
    UINT64_C(3244349440), // SQRSHR_VG4_Z4ZI_B
6147
0
    UINT64_C(3248543744), // SQRSHR_VG4_Z4ZI_H
6148
0
    UINT64_C(1141669888), // SQSHLR_ZPmZ_B
6149
0
    UINT64_C(1154252800), // SQSHLR_ZPmZ_D
6150
0
    UINT64_C(1145864192), // SQSHLR_ZPmZ_H
6151
0
    UINT64_C(1150058496), // SQSHLR_ZPmZ_S
6152
0
    UINT64_C(68124928), // SQSHLU_ZPmI_B
6153
0
    UINT64_C(76513280), // SQSHLU_ZPmI_D
6154
0
    UINT64_C(68125184), // SQSHLU_ZPmI_H
6155
0
    UINT64_C(72318976), // SQSHLU_ZPmI_S
6156
0
    UINT64_C(2131256320), // SQSHLUb
6157
0
    UINT64_C(2134926336), // SQSHLUd
6158
0
    UINT64_C(2131780608), // SQSHLUh
6159
0
    UINT64_C(2132829184), // SQSHLUs
6160
0
    UINT64_C(1862820864), // SQSHLUv16i8_shift
6161
0
    UINT64_C(790651904),  // SQSHLUv2i32_shift
6162
0
    UINT64_C(1866490880), // SQSHLUv2i64_shift
6163
0
    UINT64_C(789603328),  // SQSHLUv4i16_shift
6164
0
    UINT64_C(1864393728), // SQSHLUv4i32_shift
6165
0
    UINT64_C(1863345152), // SQSHLUv8i16_shift
6166
0
    UINT64_C(789079040),  // SQSHLUv8i8_shift
6167
0
    UINT64_C(67535104), // SQSHL_ZPmI_B
6168
0
    UINT64_C(75923456), // SQSHL_ZPmI_D
6169
0
    UINT64_C(67535360), // SQSHL_ZPmI_H
6170
0
    UINT64_C(71729152), // SQSHL_ZPmI_S
6171
0
    UINT64_C(1141407744), // SQSHL_ZPmZ_B
6172
0
    UINT64_C(1153990656), // SQSHL_ZPmZ_D
6173
0
    UINT64_C(1145602048), // SQSHL_ZPmZ_H
6174
0
    UINT64_C(1149796352), // SQSHL_ZPmZ_S
6175
0
    UINT64_C(1594389504), // SQSHLb
6176
0
    UINT64_C(1598059520), // SQSHLd
6177
0
    UINT64_C(1594913792), // SQSHLh
6178
0
    UINT64_C(1595962368), // SQSHLs
6179
0
    UINT64_C(1310739456), // SQSHLv16i8
6180
0
    UINT64_C(1325954048), // SQSHLv16i8_shift
6181
0
    UINT64_C(1583369216), // SQSHLv1i16
6182
0
    UINT64_C(1587563520), // SQSHLv1i32
6183
0
    UINT64_C(1591757824), // SQSHLv1i64
6184
0
    UINT64_C(1579174912), // SQSHLv1i8
6185
0
    UINT64_C(245386240),  // SQSHLv2i32
6186
0
    UINT64_C(253785088),  // SQSHLv2i32_shift
6187
0
    UINT64_C(1323322368), // SQSHLv2i64
6188
0
    UINT64_C(1329624064), // SQSHLv2i64_shift
6189
0
    UINT64_C(241191936),  // SQSHLv4i16
6190
0
    UINT64_C(252736512),  // SQSHLv4i16_shift
6191
0
    UINT64_C(1319128064), // SQSHLv4i32
6192
0
    UINT64_C(1327526912), // SQSHLv4i32_shift
6193
0
    UINT64_C(1314933760), // SQSHLv8i16
6194
0
    UINT64_C(1326478336), // SQSHLv8i16_shift
6195
0
    UINT64_C(236997632),  // SQSHLv8i8
6196
0
    UINT64_C(252212224),  // SQSHLv8i8_shift
6197
0
    UINT64_C(1160257536), // SQSHRNB_ZZI_B
6198
0
    UINT64_C(1160781824), // SQSHRNB_ZZI_H
6199
0
    UINT64_C(1163927552), // SQSHRNB_ZZI_S
6200
0
    UINT64_C(1160258560), // SQSHRNT_ZZI_B
6201
0
    UINT64_C(1160782848), // SQSHRNT_ZZI_H
6202
0
    UINT64_C(1163928576), // SQSHRNT_ZZI_S
6203
0
    UINT64_C(1594397696), // SQSHRNb
6204
0
    UINT64_C(1594921984), // SQSHRNh
6205
0
    UINT64_C(1595970560), // SQSHRNs
6206
0
    UINT64_C(1325962240), // SQSHRNv16i8_shift
6207
0
    UINT64_C(253793280),  // SQSHRNv2i32_shift
6208
0
    UINT64_C(252744704),  // SQSHRNv4i16_shift
6209
0
    UINT64_C(1327535104), // SQSHRNv4i32_shift
6210
0
    UINT64_C(1326486528), // SQSHRNv8i16_shift
6211
0
    UINT64_C(252220416),  // SQSHRNv8i8_shift
6212
0
    UINT64_C(1160249344), // SQSHRUNB_ZZI_B
6213
0
    UINT64_C(1160773632), // SQSHRUNB_ZZI_H
6214
0
    UINT64_C(1163919360), // SQSHRUNB_ZZI_S
6215
0
    UINT64_C(1160250368), // SQSHRUNT_ZZI_B
6216
0
    UINT64_C(1160774656), // SQSHRUNT_ZZI_H
6217
0
    UINT64_C(1163920384), // SQSHRUNT_ZZI_S
6218
0
    UINT64_C(2131264512), // SQSHRUNb
6219
0
    UINT64_C(2131788800), // SQSHRUNh
6220
0
    UINT64_C(2132837376), // SQSHRUNs
6221
0
    UINT64_C(1862829056), // SQSHRUNv16i8_shift
6222
0
    UINT64_C(790660096),  // SQSHRUNv2i32_shift
6223
0
    UINT64_C(789611520),  // SQSHRUNv4i16_shift
6224
0
    UINT64_C(1864401920), // SQSHRUNv4i32_shift
6225
0
    UINT64_C(1863353344), // SQSHRUNv8i16_shift
6226
0
    UINT64_C(789087232),  // SQSHRUNv8i8_shift
6227
0
    UINT64_C(1142849536), // SQSUBR_ZPmZ_B
6228
0
    UINT64_C(1155432448), // SQSUBR_ZPmZ_D
6229
0
    UINT64_C(1147043840), // SQSUBR_ZPmZ_H
6230
0
    UINT64_C(1151238144), // SQSUBR_ZPmZ_S
6231
0
    UINT64_C(623296512),  // SQSUB_ZI_B
6232
0
    UINT64_C(635879424),  // SQSUB_ZI_D
6233
0
    UINT64_C(627490816),  // SQSUB_ZI_H
6234
0
    UINT64_C(631685120),  // SQSUB_ZI_S
6235
0
    UINT64_C(1142587392), // SQSUB_ZPmZ_B
6236
0
    UINT64_C(1155170304), // SQSUB_ZPmZ_D
6237
0
    UINT64_C(1146781696), // SQSUB_ZPmZ_H
6238
0
    UINT64_C(1150976000), // SQSUB_ZPmZ_S
6239
0
    UINT64_C(69212160), // SQSUB_ZZZ_B
6240
0
    UINT64_C(81795072), // SQSUB_ZZZ_D
6241
0
    UINT64_C(73406464), // SQSUB_ZZZ_H
6242
0
    UINT64_C(77600768), // SQSUB_ZZZ_S
6243
0
    UINT64_C(1310731264), // SQSUBv16i8
6244
0
    UINT64_C(1583361024), // SQSUBv1i16
6245
0
    UINT64_C(1587555328), // SQSUBv1i32
6246
0
    UINT64_C(1591749632), // SQSUBv1i64
6247
0
    UINT64_C(1579166720), // SQSUBv1i8
6248
0
    UINT64_C(245378048),  // SQSUBv2i32
6249
0
    UINT64_C(1323314176), // SQSUBv2i64
6250
0
    UINT64_C(241183744),  // SQSUBv4i16
6251
0
    UINT64_C(1319119872), // SQSUBv4i32
6252
0
    UINT64_C(1314925568), // SQSUBv8i16
6253
0
    UINT64_C(236989440),  // SQSUBv8i8
6254
0
    UINT64_C(1160265728), // SQXTNB_ZZ_B
6255
0
    UINT64_C(1160790016), // SQXTNB_ZZ_H
6256
0
    UINT64_C(1163935744), // SQXTNB_ZZ_S
6257
0
    UINT64_C(1160266752), // SQXTNT_ZZ_B
6258
0
    UINT64_C(1160791040), // SQXTNT_ZZ_H
6259
0
    UINT64_C(1163936768), // SQXTNT_ZZ_S
6260
0
    UINT64_C(1310803968), // SQXTNv16i8
6261
0
    UINT64_C(1583433728), // SQXTNv1i16
6262
0
    UINT64_C(1587628032), // SQXTNv1i32
6263
0
    UINT64_C(1579239424), // SQXTNv1i8
6264
0
    UINT64_C(245450752),  // SQXTNv2i32
6265
0
    UINT64_C(241256448),  // SQXTNv4i16
6266
0
    UINT64_C(1319192576), // SQXTNv4i32
6267
0
    UINT64_C(1314998272), // SQXTNv8i16
6268
0
    UINT64_C(237062144),  // SQXTNv8i8
6269
0
    UINT64_C(1160269824), // SQXTUNB_ZZ_B
6270
0
    UINT64_C(1160794112), // SQXTUNB_ZZ_H
6271
0
    UINT64_C(1163939840), // SQXTUNB_ZZ_S
6272
0
    UINT64_C(1160270848), // SQXTUNT_ZZ_B
6273
0
    UINT64_C(1160795136), // SQXTUNT_ZZ_H
6274
0
    UINT64_C(1163940864), // SQXTUNT_ZZ_S
6275
0
    UINT64_C(1847666688), // SQXTUNv16i8
6276
0
    UINT64_C(2120296448), // SQXTUNv1i16
6277
0
    UINT64_C(2124490752), // SQXTUNv1i32
6278
0
    UINT64_C(2116102144), // SQXTUNv1i8
6279
0
    UINT64_C(782313472),  // SQXTUNv2i32
6280
0
    UINT64_C(778119168),  // SQXTUNv4i16
6281
0
    UINT64_C(1856055296), // SQXTUNv4i32
6282
0
    UINT64_C(1851860992), // SQXTUNv8i16
6283
0
    UINT64_C(773924864),  // SQXTUNv8i8
6284
0
    UINT64_C(1142194176), // SRHADD_ZPmZ_B
6285
0
    UINT64_C(1154777088), // SRHADD_ZPmZ_D
6286
0
    UINT64_C(1146388480), // SRHADD_ZPmZ_H
6287
0
    UINT64_C(1150582784), // SRHADD_ZPmZ_S
6288
0
    UINT64_C(1310725120), // SRHADDv16i8
6289
0
    UINT64_C(245371904),  // SRHADDv2i32
6290
0
    UINT64_C(241177600),  // SRHADDv4i16
6291
0
    UINT64_C(1319113728), // SRHADDv4i32
6292
0
    UINT64_C(1314919424), // SRHADDv8i16
6293
0
    UINT64_C(236983296),  // SRHADDv8i8
6294
0
    UINT64_C(1158213632), // SRI_ZZI_B
6295
0
    UINT64_C(1166077952), // SRI_ZZI_D
6296
0
    UINT64_C(1158737920), // SRI_ZZI_H
6297
0
    UINT64_C(1161883648), // SRI_ZZI_S
6298
0
    UINT64_C(2134918144), // SRId
6299
0
    UINT64_C(1862812672), // SRIv16i8_shift
6300
0
    UINT64_C(790643712),  // SRIv2i32_shift
6301
0
    UINT64_C(1866482688), // SRIv2i64_shift
6302
0
    UINT64_C(789595136),  // SRIv4i16_shift
6303
0
    UINT64_C(1864385536), // SRIv4i32_shift
6304
0
    UINT64_C(1863336960), // SRIv8i16_shift
6305
0
    UINT64_C(789070848),  // SRIv8i8_shift
6306
0
    UINT64_C(1141276672), // SRSHLR_ZPmZ_B
6307
0
    UINT64_C(1153859584), // SRSHLR_ZPmZ_D
6308
0
    UINT64_C(1145470976), // SRSHLR_ZPmZ_H
6309
0
    UINT64_C(1149665280), // SRSHLR_ZPmZ_S
6310
0
    UINT64_C(3240145440), // SRSHL_VG2_2Z2Z_B
6311
0
    UINT64_C(3252728352), // SRSHL_VG2_2Z2Z_D
6312
0
    UINT64_C(3244339744), // SRSHL_VG2_2Z2Z_H
6313
0
    UINT64_C(3248534048), // SRSHL_VG2_2Z2Z_S
6314
0
    UINT64_C(3240141344), // SRSHL_VG2_2ZZ_B
6315
0
    UINT64_C(3252724256), // SRSHL_VG2_2ZZ_D
6316
0
    UINT64_C(3244335648), // SRSHL_VG2_2ZZ_H
6317
0
    UINT64_C(3248529952), // SRSHL_VG2_2ZZ_S
6318
0
    UINT64_C(3240147488), // SRSHL_VG4_4Z4Z_B
6319
0
    UINT64_C(3252730400), // SRSHL_VG4_4Z4Z_D
6320
0
    UINT64_C(3244341792), // SRSHL_VG4_4Z4Z_H
6321
0
    UINT64_C(3248536096), // SRSHL_VG4_4Z4Z_S
6322
0
    UINT64_C(3240143392), // SRSHL_VG4_4ZZ_B
6323
0
    UINT64_C(3252726304), // SRSHL_VG4_4ZZ_D
6324
0
    UINT64_C(3244337696), // SRSHL_VG4_4ZZ_H
6325
0
    UINT64_C(3248532000), // SRSHL_VG4_4ZZ_S
6326
0
    UINT64_C(1141014528), // SRSHL_ZPmZ_B
6327
0
    UINT64_C(1153597440), // SRSHL_ZPmZ_D
6328
0
    UINT64_C(1145208832), // SRSHL_ZPmZ_H
6329
0
    UINT64_C(1149403136), // SRSHL_ZPmZ_S
6330
0
    UINT64_C(1310741504), // SRSHLv16i8
6331
0
    UINT64_C(1591759872), // SRSHLv1i64
6332
0
    UINT64_C(245388288),  // SRSHLv2i32
6333
0
    UINT64_C(1323324416), // SRSHLv2i64
6334
0
    UINT64_C(241193984),  // SRSHLv4i16
6335
0
    UINT64_C(1319130112), // SRSHLv4i32
6336
0
    UINT64_C(1314935808), // SRSHLv8i16
6337
0
    UINT64_C(236999680),  // SRSHLv8i8
6338
0
    UINT64_C(67928320), // SRSHR_ZPmI_B
6339
0
    UINT64_C(76316672), // SRSHR_ZPmI_D
6340
0
    UINT64_C(67928576), // SRSHR_ZPmI_H
6341
0
    UINT64_C(72122368), // SRSHR_ZPmI_S
6342
0
    UINT64_C(1598039040), // SRSHRd
6343
0
    UINT64_C(1325933568), // SRSHRv16i8_shift
6344
0
    UINT64_C(253764608),  // SRSHRv2i32_shift
6345
0
    UINT64_C(1329603584), // SRSHRv2i64_shift
6346
0
    UINT64_C(252716032),  // SRSHRv4i16_shift
6347
0
    UINT64_C(1327506432), // SRSHRv4i32_shift
6348
0
    UINT64_C(1326457856), // SRSHRv8i16_shift
6349
0
    UINT64_C(252191744),  // SRSHRv8i8_shift
6350
0
    UINT64_C(1158211584), // SRSRA_ZZI_B
6351
0
    UINT64_C(1166075904), // SRSRA_ZZI_D
6352
0
    UINT64_C(1158735872), // SRSRA_ZZI_H
6353
0
    UINT64_C(1161881600), // SRSRA_ZZI_S
6354
0
    UINT64_C(1598043136), // SRSRAd
6355
0
    UINT64_C(1325937664), // SRSRAv16i8_shift
6356
0
    UINT64_C(253768704),  // SRSRAv2i32_shift
6357
0
    UINT64_C(1329607680), // SRSRAv2i64_shift
6358
0
    UINT64_C(252720128),  // SRSRAv4i16_shift
6359
0
    UINT64_C(1327510528), // SRSRAv4i32_shift
6360
0
    UINT64_C(1326461952), // SRSRAv8i16_shift
6361
0
    UINT64_C(252195840),  // SRSRAv8i8_shift
6362
0
    UINT64_C(1161863168), // SSHLLB_ZZI_D
6363
0
    UINT64_C(1158193152), // SSHLLB_ZZI_H
6364
0
    UINT64_C(1158717440), // SSHLLB_ZZI_S
6365
0
    UINT64_C(1161864192), // SSHLLT_ZZI_D
6366
0
    UINT64_C(1158194176), // SSHLLT_ZZI_H
6367
0
    UINT64_C(1158718464), // SSHLLT_ZZI_S
6368
0
    UINT64_C(1325966336), // SSHLLv16i8_shift
6369
0
    UINT64_C(253797376),  // SSHLLv2i32_shift
6370
0
    UINT64_C(252748800),  // SSHLLv4i16_shift
6371
0
    UINT64_C(1327539200), // SSHLLv4i32_shift
6372
0
    UINT64_C(1326490624), // SSHLLv8i16_shift
6373
0
    UINT64_C(252224512),  // SSHLLv8i8_shift
6374
0
    UINT64_C(1310737408), // SSHLv16i8
6375
0
    UINT64_C(1591755776), // SSHLv1i64
6376
0
    UINT64_C(245384192),  // SSHLv2i32
6377
0
    UINT64_C(1323320320), // SSHLv2i64
6378
0
    UINT64_C(241189888),  // SSHLv4i16
6379
0
    UINT64_C(1319126016), // SSHLv4i32
6380
0
    UINT64_C(1314931712), // SSHLv8i16
6381
0
    UINT64_C(236995584),  // SSHLv8i8
6382
0
    UINT64_C(1598030848), // SSHRd
6383
0
    UINT64_C(1325925376), // SSHRv16i8_shift
6384
0
    UINT64_C(253756416),  // SSHRv2i32_shift
6385
0
    UINT64_C(1329595392), // SSHRv2i64_shift
6386
0
    UINT64_C(252707840),  // SSHRv4i16_shift
6387
0
    UINT64_C(1327498240), // SSHRv4i32_shift
6388
0
    UINT64_C(1326449664), // SSHRv8i16_shift
6389
0
    UINT64_C(252183552),  // SSHRv8i8_shift
6390
0
    UINT64_C(1158209536), // SSRA_ZZI_B
6391
0
    UINT64_C(1166073856), // SSRA_ZZI_D
6392
0
    UINT64_C(1158733824), // SSRA_ZZI_H
6393
0
    UINT64_C(1161879552), // SSRA_ZZI_S
6394
0
    UINT64_C(1598034944), // SSRAd
6395
0
    UINT64_C(1325929472), // SSRAv16i8_shift
6396
0
    UINT64_C(253760512),  // SSRAv2i32_shift
6397
0
    UINT64_C(1329599488), // SSRAv2i64_shift
6398
0
    UINT64_C(252711936),  // SSRAv4i16_shift
6399
0
    UINT64_C(1327502336), // SSRAv4i32_shift
6400
0
    UINT64_C(1326453760), // SSRAv8i16_shift
6401
0
    UINT64_C(252187648),  // SSRAv8i8_shift
6402
0
    UINT64_C(3825246208), // SST1B_D
6403
0
    UINT64_C(3829440512), // SST1B_D_IMM
6404
0
    UINT64_C(3825254400), // SST1B_D_SXTW
6405
0
    UINT64_C(3825238016), // SST1B_D_UXTW
6406
0
    UINT64_C(3831537664), // SST1B_S_IMM
6407
0
    UINT64_C(3829448704), // SST1B_S_SXTW
6408
0
    UINT64_C(3829432320), // SST1B_S_UXTW
6409
0
    UINT64_C(3850412032), // SST1D
6410
0
    UINT64_C(3854606336), // SST1D_IMM
6411
0
    UINT64_C(3852509184), // SST1D_SCALED
6412
0
    UINT64_C(3850420224), // SST1D_SXTW
6413
0
    UINT64_C(3852517376), // SST1D_SXTW_SCALED
6414
0
    UINT64_C(3850403840), // SST1D_UXTW
6415
0
    UINT64_C(3852500992), // SST1D_UXTW_SCALED
6416
0
    UINT64_C(3833634816), // SST1H_D
6417
0
    UINT64_C(3837829120), // SST1H_D_IMM
6418
0
    UINT64_C(3835731968), // SST1H_D_SCALED
6419
0
    UINT64_C(3833643008), // SST1H_D_SXTW
6420
0
    UINT64_C(3835740160), // SST1H_D_SXTW_SCALED
6421
0
    UINT64_C(3833626624), // SST1H_D_UXTW
6422
0
    UINT64_C(3835723776), // SST1H_D_UXTW_SCALED
6423
0
    UINT64_C(3839926272), // SST1H_S_IMM
6424
0
    UINT64_C(3837837312), // SST1H_S_SXTW
6425
0
    UINT64_C(3839934464), // SST1H_S_SXTW_SCALED
6426
0
    UINT64_C(3837820928), // SST1H_S_UXTW
6427
0
    UINT64_C(3839918080), // SST1H_S_UXTW_SCALED
6428
0
    UINT64_C(3827310592), // SST1Q
6429
0
    UINT64_C(3842023424), // SST1W_D
6430
0
    UINT64_C(3846217728), // SST1W_D_IMM
6431
0
    UINT64_C(3844120576), // SST1W_D_SCALED
6432
0
    UINT64_C(3842031616), // SST1W_D_SXTW
6433
0
    UINT64_C(3844128768), // SST1W_D_SXTW_SCALED
6434
0
    UINT64_C(3842015232), // SST1W_D_UXTW
6435
0
    UINT64_C(3844112384), // SST1W_D_UXTW_SCALED
6436
0
    UINT64_C(3848314880), // SST1W_IMM
6437
0
    UINT64_C(3846225920), // SST1W_SXTW
6438
0
    UINT64_C(3848323072), // SST1W_SXTW_SCALED
6439
0
    UINT64_C(3846209536), // SST1W_UXTW
6440
0
    UINT64_C(3848306688), // SST1W_UXTW_SCALED
6441
0
    UINT64_C(1170245632), // SSUBLBT_ZZZ_D
6442
0
    UINT64_C(1161857024), // SSUBLBT_ZZZ_H
6443
0
    UINT64_C(1166051328), // SSUBLBT_ZZZ_S
6444
0
    UINT64_C(1170214912), // SSUBLB_ZZZ_D
6445
0
    UINT64_C(1161826304), // SSUBLB_ZZZ_H
6446
0
    UINT64_C(1166020608), // SSUBLB_ZZZ_S
6447
0
    UINT64_C(1170246656), // SSUBLTB_ZZZ_D
6448
0
    UINT64_C(1161858048), // SSUBLTB_ZZZ_H
6449
0
    UINT64_C(1166052352), // SSUBLTB_ZZZ_S
6450
0
    UINT64_C(1170215936), // SSUBLT_ZZZ_D
6451
0
    UINT64_C(1161827328), // SSUBLT_ZZZ_H
6452
0
    UINT64_C(1166021632), // SSUBLT_ZZZ_S
6453
0
    UINT64_C(1310728192), // SSUBLv16i8_v8i16
6454
0
    UINT64_C(245374976),  // SSUBLv2i32_v2i64
6455
0
    UINT64_C(241180672),  // SSUBLv4i16_v4i32
6456
0
    UINT64_C(1319116800), // SSUBLv4i32_v2i64
6457
0
    UINT64_C(1314922496), // SSUBLv8i16_v4i32
6458
0
    UINT64_C(236986368),  // SSUBLv8i8_v8i16
6459
0
    UINT64_C(1170231296), // SSUBWB_ZZZ_D
6460
0
    UINT64_C(1161842688), // SSUBWB_ZZZ_H
6461
0
    UINT64_C(1166036992), // SSUBWB_ZZZ_S
6462
0
    UINT64_C(1170232320), // SSUBWT_ZZZ_D
6463
0
    UINT64_C(1161843712), // SSUBWT_ZZZ_H
6464
0
    UINT64_C(1166038016), // SSUBWT_ZZZ_S
6465
0
    UINT64_C(1310732288), // SSUBWv16i8_v8i16
6466
0
    UINT64_C(245379072),  // SSUBWv2i32_v2i64
6467
0
    UINT64_C(241184768),  // SSUBWv4i16_v4i32
6468
0
    UINT64_C(1319120896), // SSUBWv4i32_v2i64
6469
0
    UINT64_C(1314926592), // SSUBWv8i16_v4i32
6470
0
    UINT64_C(236990464),  // SSUBWv8i8_v8i16
6471
0
    UINT64_C(3825221632), // ST1B
6472
0
    UINT64_C(2686451712), // ST1B_2Z
6473
0
    UINT64_C(2690646016), // ST1B_2Z_IMM
6474
0
    UINT64_C(2703228928), // ST1B_2Z_STRIDED
6475
0
    UINT64_C(2707423232), // ST1B_2Z_STRIDED_IMM
6476
0
    UINT64_C(2686484480), // ST1B_4Z
6477
0
    UINT64_C(2690678784), // ST1B_4Z_IMM
6478
0
    UINT64_C(2703261696), // ST1B_4Z_STRIDED
6479
0
    UINT64_C(2707456000), // ST1B_4Z_STRIDED_IMM
6480
0
    UINT64_C(3831513088), // ST1B_D
6481
0
    UINT64_C(3831554048), // ST1B_D_IMM
6482
0
    UINT64_C(3827318784), // ST1B_H
6483
0
    UINT64_C(3827359744), // ST1B_H_IMM
6484
0
    UINT64_C(3825262592), // ST1B_IMM
6485
0
    UINT64_C(3829415936), // ST1B_S
6486
0
    UINT64_C(3829456896), // ST1B_S_IMM
6487
0
    UINT64_C(3856678912), // ST1D
6488
0
    UINT64_C(2686476288), // ST1D_2Z
6489
0
    UINT64_C(2690670592), // ST1D_2Z_IMM
6490
0
    UINT64_C(2703253504), // ST1D_2Z_STRIDED
6491
0
    UINT64_C(2707447808), // ST1D_2Z_STRIDED_IMM
6492
0
    UINT64_C(2686509056), // ST1D_4Z
6493
0
    UINT64_C(2690703360), // ST1D_4Z_IMM
6494
0
    UINT64_C(2703286272), // ST1D_4Z_STRIDED
6495
0
    UINT64_C(2707480576), // ST1D_4Z_STRIDED_IMM
6496
0
    UINT64_C(3856719872), // ST1D_IMM
6497
0
    UINT64_C(3854581760), // ST1D_Q
6498
0
    UINT64_C(3854622720), // ST1D_Q_IMM
6499
0
    UINT64_C(1275076608), // ST1Fourv16b
6500
0
    UINT64_C(1283465216), // ST1Fourv16b_POST
6501
0
    UINT64_C(201337856),  // ST1Fourv1d
6502
0
    UINT64_C(209726464),  // ST1Fourv1d_POST
6503
0
    UINT64_C(1275079680), // ST1Fourv2d
6504
0
    UINT64_C(1283468288), // ST1Fourv2d_POST
6505
0
    UINT64_C(201336832),  // ST1Fourv2s
6506
0
    UINT64_C(209725440),  // ST1Fourv2s_POST
6507
0
    UINT64_C(201335808),  // ST1Fourv4h
6508
0
    UINT64_C(209724416),  // ST1Fourv4h_POST
6509
0
    UINT64_C(1275078656), // ST1Fourv4s
6510
0
    UINT64_C(1283467264), // ST1Fourv4s_POST
6511
0
    UINT64_C(201334784),  // ST1Fourv8b
6512
0
    UINT64_C(209723392),  // ST1Fourv8b_POST
6513
0
    UINT64_C(1275077632), // ST1Fourv8h
6514
0
    UINT64_C(1283466240), // ST1Fourv8h_POST
6515
0
    UINT64_C(3835707392), // ST1H
6516
0
    UINT64_C(2686459904), // ST1H_2Z
6517
0
    UINT64_C(2690654208), // ST1H_2Z_IMM
6518
0
    UINT64_C(2703237120), // ST1H_2Z_STRIDED
6519
0
    UINT64_C(2707431424), // ST1H_2Z_STRIDED_IMM
6520
0
    UINT64_C(2686492672), // ST1H_4Z
6521
0
    UINT64_C(2690686976), // ST1H_4Z_IMM
6522
0
    UINT64_C(2703269888), // ST1H_4Z_STRIDED
6523
0
    UINT64_C(2707464192), // ST1H_4Z_STRIDED_IMM
6524
0
    UINT64_C(3839901696), // ST1H_D
6525
0
    UINT64_C(3839942656), // ST1H_D_IMM
6526
0
    UINT64_C(3835748352), // ST1H_IMM
6527
0
    UINT64_C(3837804544), // ST1H_S
6528
0
    UINT64_C(3837845504), // ST1H_S_IMM
6529
0
    UINT64_C(1275097088), // ST1Onev16b
6530
0
    UINT64_C(1283485696), // ST1Onev16b_POST
6531
0
    UINT64_C(201358336),  // ST1Onev1d
6532
0
    UINT64_C(209746944),  // ST1Onev1d_POST
6533
0
    UINT64_C(1275100160), // ST1Onev2d
6534
0
    UINT64_C(1283488768), // ST1Onev2d_POST
6535
0
    UINT64_C(201357312),  // ST1Onev2s
6536
0
    UINT64_C(209745920),  // ST1Onev2s_POST
6537
0
    UINT64_C(201356288),  // ST1Onev4h
6538
0
    UINT64_C(209744896),  // ST1Onev4h_POST
6539
0
    UINT64_C(1275099136), // ST1Onev4s
6540
0
    UINT64_C(1283487744), // ST1Onev4s_POST
6541
0
    UINT64_C(201355264),  // ST1Onev8b
6542
0
    UINT64_C(209743872),  // ST1Onev8b_POST
6543
0
    UINT64_C(1275098112), // ST1Onev8h
6544
0
    UINT64_C(1283486720), // ST1Onev8h_POST
6545
0
    UINT64_C(1275092992), // ST1Threev16b
6546
0
    UINT64_C(1283481600), // ST1Threev16b_POST
6547
0
    UINT64_C(201354240),  // ST1Threev1d
6548
0
    UINT64_C(209742848),  // ST1Threev1d_POST
6549
0
    UINT64_C(1275096064), // ST1Threev2d
6550
0
    UINT64_C(1283484672), // ST1Threev2d_POST
6551
0
    UINT64_C(201353216),  // ST1Threev2s
6552
0
    UINT64_C(209741824),  // ST1Threev2s_POST
6553
0
    UINT64_C(201352192),  // ST1Threev4h
6554
0
    UINT64_C(209740800),  // ST1Threev4h_POST
6555
0
    UINT64_C(1275095040), // ST1Threev4s
6556
0
    UINT64_C(1283483648), // ST1Threev4s_POST
6557
0
    UINT64_C(201351168),  // ST1Threev8b
6558
0
    UINT64_C(209739776),  // ST1Threev8b_POST
6559
0
    UINT64_C(1275094016), // ST1Threev8h
6560
0
    UINT64_C(1283482624), // ST1Threev8h_POST
6561
0
    UINT64_C(1275109376), // ST1Twov16b
6562
0
    UINT64_C(1283497984), // ST1Twov16b_POST
6563
0
    UINT64_C(201370624),  // ST1Twov1d
6564
0
    UINT64_C(209759232),  // ST1Twov1d_POST
6565
0
    UINT64_C(1275112448), // ST1Twov2d
6566
0
    UINT64_C(1283501056), // ST1Twov2d_POST
6567
0
    UINT64_C(201369600),  // ST1Twov2s
6568
0
    UINT64_C(209758208),  // ST1Twov2s_POST
6569
0
    UINT64_C(201368576),  // ST1Twov4h
6570
0
    UINT64_C(209757184),  // ST1Twov4h_POST
6571
0
    UINT64_C(1275111424), // ST1Twov4s
6572
0
    UINT64_C(1283500032), // ST1Twov4s_POST
6573
0
    UINT64_C(201367552),  // ST1Twov8b
6574
0
    UINT64_C(209756160),  // ST1Twov8b_POST
6575
0
    UINT64_C(1275110400), // ST1Twov8h
6576
0
    UINT64_C(1283499008), // ST1Twov8h_POST
6577
0
    UINT64_C(3846193152), // ST1W
6578
0
    UINT64_C(2686468096), // ST1W_2Z
6579
0
    UINT64_C(2690662400), // ST1W_2Z_IMM
6580
0
    UINT64_C(2703245312), // ST1W_2Z_STRIDED
6581
0
    UINT64_C(2707439616), // ST1W_2Z_STRIDED_IMM
6582
0
    UINT64_C(2686500864), // ST1W_4Z
6583
0
    UINT64_C(2690695168), // ST1W_4Z_IMM
6584
0
    UINT64_C(2703278080), // ST1W_4Z_STRIDED
6585
0
    UINT64_C(2707472384), // ST1W_4Z_STRIDED_IMM
6586
0
    UINT64_C(3848290304), // ST1W_D
6587
0
    UINT64_C(3848331264), // ST1W_D_IMM
6588
0
    UINT64_C(3846234112), // ST1W_IMM
6589
0
    UINT64_C(3841998848), // ST1W_Q
6590
0
    UINT64_C(3842039808), // ST1W_Q_IMM
6591
0
    UINT64_C(3760193536), // ST1_MXIPXX_H_B
6592
0
    UINT64_C(3772776448), // ST1_MXIPXX_H_D
6593
0
    UINT64_C(3764387840), // ST1_MXIPXX_H_H
6594
0
    UINT64_C(3789553664), // ST1_MXIPXX_H_Q
6595
0
    UINT64_C(3768582144), // ST1_MXIPXX_H_S
6596
0
    UINT64_C(3760226304), // ST1_MXIPXX_V_B
6597
0
    UINT64_C(3772809216), // ST1_MXIPXX_V_D
6598
0
    UINT64_C(3764420608), // ST1_MXIPXX_V_H
6599
0
    UINT64_C(3789586432), // ST1_MXIPXX_V_Q
6600
0
    UINT64_C(3768614912), // ST1_MXIPXX_V_S
6601
0
    UINT64_C(218120192),  // ST1i16
6602
0
    UINT64_C(226508800),  // ST1i16_POST
6603
0
    UINT64_C(218136576),  // ST1i32
6604
0
    UINT64_C(226525184),  // ST1i32_POST
6605
0
    UINT64_C(218137600),  // ST1i64
6606
0
    UINT64_C(226526208),  // ST1i64_POST
6607
0
    UINT64_C(218103808),  // ST1i8
6608
0
    UINT64_C(226492416),  // ST1i8_POST
6609
0
    UINT64_C(3827326976), // ST2B
6610
0
    UINT64_C(3828408320), // ST2B_IMM
6611
0
    UINT64_C(3852492800), // ST2D
6612
0
    UINT64_C(3853574144), // ST2D_IMM
6613
0
    UINT64_C(3651142656), // ST2GPostIndex
6614
0
    UINT64_C(3651144704), // ST2GPreIndex
6615
0
    UINT64_C(3651143680), // ST2Gi
6616
0
    UINT64_C(3835715584), // ST2H
6617
0
    UINT64_C(3836796928), // ST2H_IMM
6618
0
    UINT64_C(3831496704), // ST2Q
6619
0
    UINT64_C(3829399552), // ST2Q_IMM
6620
0
    UINT64_C(1275101184), // ST2Twov16b
6621
0
    UINT64_C(1283489792), // ST2Twov16b_POST
6622
0
    UINT64_C(1275104256), // ST2Twov2d
6623
0
    UINT64_C(1283492864), // ST2Twov2d_POST
6624
0
    UINT64_C(201361408),  // ST2Twov2s
6625
0
    UINT64_C(209750016),  // ST2Twov2s_POST
6626
0
    UINT64_C(201360384),  // ST2Twov4h
6627
0
    UINT64_C(209748992),  // ST2Twov4h_POST
6628
0
    UINT64_C(1275103232), // ST2Twov4s
6629
0
    UINT64_C(1283491840), // ST2Twov4s_POST
6630
0
    UINT64_C(201359360),  // ST2Twov8b
6631
0
    UINT64_C(209747968),  // ST2Twov8b_POST
6632
0
    UINT64_C(1275102208), // ST2Twov8h
6633
0
    UINT64_C(1283490816), // ST2Twov8h_POST
6634
0
    UINT64_C(3844104192), // ST2W
6635
0
    UINT64_C(3845185536), // ST2W_IMM
6636
0
    UINT64_C(220217344),  // ST2i16
6637
0
    UINT64_C(228605952),  // ST2i16_POST
6638
0
    UINT64_C(220233728),  // ST2i32
6639
0
    UINT64_C(228622336),  // ST2i32_POST
6640
0
    UINT64_C(220234752),  // ST2i64
6641
0
    UINT64_C(228623360),  // ST2i64_POST
6642
0
    UINT64_C(220200960),  // ST2i8
6643
0
    UINT64_C(228589568),  // ST2i8_POST
6644
0
    UINT64_C(3829424128), // ST3B
6645
0
    UINT64_C(3830505472), // ST3B_IMM
6646
0
    UINT64_C(3854589952), // ST3D
6647
0
    UINT64_C(3855671296), // ST3D_IMM
6648
0
    UINT64_C(3837812736), // ST3H
6649
0
    UINT64_C(3838894080), // ST3H_IMM
6650
0
    UINT64_C(3835691008), // ST3Q
6651
0
    UINT64_C(3833593856), // ST3Q_IMM
6652
0
    UINT64_C(1275084800), // ST3Threev16b
6653
0
    UINT64_C(1283473408), // ST3Threev16b_POST
6654
0
    UINT64_C(1275087872), // ST3Threev2d
6655
0
    UINT64_C(1283476480), // ST3Threev2d_POST
6656
0
    UINT64_C(201345024),  // ST3Threev2s
6657
0
    UINT64_C(209733632),  // ST3Threev2s_POST
6658
0
    UINT64_C(201344000),  // ST3Threev4h
6659
0
    UINT64_C(209732608),  // ST3Threev4h_POST
6660
0
    UINT64_C(1275086848), // ST3Threev4s
6661
0
    UINT64_C(1283475456), // ST3Threev4s_POST
6662
0
    UINT64_C(201342976),  // ST3Threev8b
6663
0
    UINT64_C(209731584),  // ST3Threev8b_POST
6664
0
    UINT64_C(1275085824), // ST3Threev8h
6665
0
    UINT64_C(1283474432), // ST3Threev8h_POST
6666
0
    UINT64_C(3846201344), // ST3W
6667
0
    UINT64_C(3847282688), // ST3W_IMM
6668
0
    UINT64_C(218128384),  // ST3i16
6669
0
    UINT64_C(226516992),  // ST3i16_POST
6670
0
    UINT64_C(218144768),  // ST3i32
6671
0
    UINT64_C(226533376),  // ST3i32_POST
6672
0
    UINT64_C(218145792),  // ST3i64
6673
0
    UINT64_C(226534400),  // ST3i64_POST
6674
0
    UINT64_C(218112000),  // ST3i8
6675
0
    UINT64_C(226500608),  // ST3i8_POST
6676
0
    UINT64_C(3831521280), // ST4B
6677
0
    UINT64_C(3832602624), // ST4B_IMM
6678
0
    UINT64_C(3856687104), // ST4D
6679
0
    UINT64_C(3857768448), // ST4D_IMM
6680
0
    UINT64_C(1275068416), // ST4Fourv16b
6681
0
    UINT64_C(1283457024), // ST4Fourv16b_POST
6682
0
    UINT64_C(1275071488), // ST4Fourv2d
6683
0
    UINT64_C(1283460096), // ST4Fourv2d_POST
6684
0
    UINT64_C(201328640),  // ST4Fourv2s
6685
0
    UINT64_C(209717248),  // ST4Fourv2s_POST
6686
0
    UINT64_C(201327616),  // ST4Fourv4h
6687
0
    UINT64_C(209716224),  // ST4Fourv4h_POST
6688
0
    UINT64_C(1275070464), // ST4Fourv4s
6689
0
    UINT64_C(1283459072), // ST4Fourv4s_POST
6690
0
    UINT64_C(201326592),  // ST4Fourv8b
6691
0
    UINT64_C(209715200),  // ST4Fourv8b_POST
6692
0
    UINT64_C(1275069440), // ST4Fourv8h
6693
0
    UINT64_C(1283458048), // ST4Fourv8h_POST
6694
0
    UINT64_C(3839909888), // ST4H
6695
0
    UINT64_C(3840991232), // ST4H_IMM
6696
0
    UINT64_C(3839885312), // ST4Q
6697
0
    UINT64_C(3837788160), // ST4Q_IMM
6698
0
    UINT64_C(3848298496), // ST4W
6699
0
    UINT64_C(3849379840), // ST4W_IMM
6700
0
    UINT64_C(220225536),  // ST4i16
6701
0
    UINT64_C(228614144),  // ST4i16_POST
6702
0
    UINT64_C(220241920),  // ST4i32
6703
0
    UINT64_C(228630528),  // ST4i32_POST
6704
0
    UINT64_C(220242944),  // ST4i64
6705
0
    UINT64_C(228631552),  // ST4i64_POST
6706
0
    UINT64_C(220209152),  // ST4i8
6707
0
    UINT64_C(228597760),  // ST4i8_POST
6708
0
    UINT64_C(4164915200), // ST64B
6709
0
    UINT64_C(4162891776), // ST64BV
6710
0
    UINT64_C(4162887680), // ST64BV0
6711
0
    UINT64_C(3651141632), // STGM
6712
0
    UINT64_C(1761607680), // STGPi
6713
0
    UINT64_C(3642754048), // STGPostIndex
6714
0
    UINT64_C(1753219072), // STGPpost
6715
0
    UINT64_C(1769996288), // STGPpre
6716
0
    UINT64_C(3642756096), // STGPreIndex
6717
0
    UINT64_C(3642755072), // STGi
6718
0
    UINT64_C(2566920192), // STILPW
6719
0
    UINT64_C(2566916096), // STILPWpre
6720
0
    UINT64_C(3640662016), // STILPX
6721
0
    UINT64_C(3640657920), // STILPXpre
6722
0
    UINT64_C(218203136),  // STL1
6723
0
    UINT64_C(144669696),  // STLLRB
6724
0
    UINT64_C(1218411520), // STLLRH
6725
0
    UINT64_C(2292153344), // STLLRW
6726
0
    UINT64_C(3365895168), // STLLRX
6727
0
    UINT64_C(144702464),  // STLRB
6728
0
    UINT64_C(1218444288), // STLRH
6729
0
    UINT64_C(2292186112), // STLRW
6730
0
    UINT64_C(2575304704), // STLRWpre
6731
0
    UINT64_C(3365927936), // STLRX
6732
0
    UINT64_C(3649046528), // STLRXpre
6733
0
    UINT64_C(419430400),  // STLURBi
6734
0
    UINT64_C(1493172224), // STLURHi
6735
0
    UINT64_C(2566914048), // STLURWi
6736
0
    UINT64_C(3640655872), // STLURXi
6737
0
    UINT64_C(486541312),  // STLURbi
6738
0
    UINT64_C(3707766784), // STLURdi
6739
0
    UINT64_C(1560283136), // STLURhi
6740
0
    UINT64_C(494929920),  // STLURqi
6741
0
    UINT64_C(2634024960), // STLURsi
6742
0
    UINT64_C(2283831296), // STLXPW
6743
0
    UINT64_C(3357573120), // STLXPX
6744
0
    UINT64_C(134250496),  // STLXRB
6745
0
    UINT64_C(1207992320), // STLXRH
6746
0
    UINT64_C(2281734144), // STLXRW
6747
0
    UINT64_C(3355475968), // STLXRX
6748
0
    UINT64_C(1811939328), // STNPDi
6749
0
    UINT64_C(2885681152), // STNPQi
6750
0
    UINT64_C(738197504),  // STNPSi
6751
0
    UINT64_C(671088640),  // STNPWi
6752
0
    UINT64_C(2818572288), // STNPXi
6753
0
    UINT64_C(2686451713), // STNT1B_2Z
6754
0
    UINT64_C(2690646017), // STNT1B_2Z_IMM
6755
0
    UINT64_C(2703228936), // STNT1B_2Z_STRIDED
6756
0
    UINT64_C(2707423240), // STNT1B_2Z_STRIDED_IMM
6757
0
    UINT64_C(2686484481), // STNT1B_4Z
6758
0
    UINT64_C(2690678785), // STNT1B_4Z_IMM
6759
0
    UINT64_C(2703261704), // STNT1B_4Z_STRIDED
6760
0
    UINT64_C(2707456008), // STNT1B_4Z_STRIDED_IMM
6761
0
    UINT64_C(3826311168), // STNT1B_ZRI
6762
0
    UINT64_C(3825229824), // STNT1B_ZRR
6763
0
    UINT64_C(3825213440), // STNT1B_ZZR_D_REAL
6764
0
    UINT64_C(3829407744), // STNT1B_ZZR_S_REAL
6765
0
    UINT64_C(2686476289), // STNT1D_2Z
6766
0
    UINT64_C(2690670593), // STNT1D_2Z_IMM
6767
0
    UINT64_C(2703253512), // STNT1D_2Z_STRIDED
6768
0
    UINT64_C(2707447816), // STNT1D_2Z_STRIDED_IMM
6769
0
    UINT64_C(2686509057), // STNT1D_4Z
6770
0
    UINT64_C(2690703361), // STNT1D_4Z_IMM
6771
0
    UINT64_C(2703286280), // STNT1D_4Z_STRIDED
6772
0
    UINT64_C(2707480584), // STNT1D_4Z_STRIDED_IMM
6773
0
    UINT64_C(3851476992), // STNT1D_ZRI
6774
0
    UINT64_C(3850395648), // STNT1D_ZRR
6775
0
    UINT64_C(3850379264), // STNT1D_ZZR_D_REAL
6776
0
    UINT64_C(2686459905), // STNT1H_2Z
6777
0
    UINT64_C(2690654209), // STNT1H_2Z_IMM
6778
0
    UINT64_C(2703237128), // STNT1H_2Z_STRIDED
6779
0
    UINT64_C(2707431432), // STNT1H_2Z_STRIDED_IMM
6780
0
    UINT64_C(2686492673), // STNT1H_4Z
6781
0
    UINT64_C(2690686977), // STNT1H_4Z_IMM
6782
0
    UINT64_C(2703269896), // STNT1H_4Z_STRIDED
6783
0
    UINT64_C(2707464200), // STNT1H_4Z_STRIDED_IMM
6784
0
    UINT64_C(3834699776), // STNT1H_ZRI
6785
0
    UINT64_C(3833618432), // STNT1H_ZRR
6786
0
    UINT64_C(3833602048), // STNT1H_ZZR_D_REAL
6787
0
    UINT64_C(3837796352), // STNT1H_ZZR_S_REAL
6788
0
    UINT64_C(2686468097), // STNT1W_2Z
6789
0
    UINT64_C(2690662401), // STNT1W_2Z_IMM
6790
0
    UINT64_C(2703245320), // STNT1W_2Z_STRIDED
6791
0
    UINT64_C(2707439624), // STNT1W_2Z_STRIDED_IMM
6792
0
    UINT64_C(2686500865), // STNT1W_4Z
6793
0
    UINT64_C(2690695169), // STNT1W_4Z_IMM
6794
0
    UINT64_C(2703278088), // STNT1W_4Z_STRIDED
6795
0
    UINT64_C(2707472392), // STNT1W_4Z_STRIDED_IMM
6796
0
    UINT64_C(3843088384), // STNT1W_ZRI
6797
0
    UINT64_C(3842007040), // STNT1W_ZRR
6798
0
    UINT64_C(3841990656), // STNT1W_ZZR_D_REAL
6799
0
    UINT64_C(3846184960), // STNT1W_ZZR_S_REAL
6800
0
    UINT64_C(1828716544), // STPDi
6801
0
    UINT64_C(1820327936), // STPDpost
6802
0
    UINT64_C(1837105152), // STPDpre
6803
0
    UINT64_C(2902458368), // STPQi
6804
0
    UINT64_C(2894069760), // STPQpost
6805
0
    UINT64_C(2910846976), // STPQpre
6806
0
    UINT64_C(754974720),  // STPSi
6807
0
    UINT64_C(746586112),  // STPSpost
6808
0
    UINT64_C(763363328),  // STPSpre
6809
0
    UINT64_C(687865856),  // STPWi
6810
0
    UINT64_C(679477248),  // STPWpost
6811
0
    UINT64_C(696254464),  // STPWpre
6812
0
    UINT64_C(2835349504), // STPXi
6813
0
    UINT64_C(2826960896), // STPXpost
6814
0
    UINT64_C(2843738112), // STPXpre
6815
0
    UINT64_C(939525120),  // STRBBpost
6816
0
    UINT64_C(939527168),  // STRBBpre
6817
0
    UINT64_C(941639680),  // STRBBroW
6818
0
    UINT64_C(941647872),  // STRBBroX
6819
0
    UINT64_C(956301312),  // STRBBui
6820
0
    UINT64_C(1006633984), // STRBpost
6821
0
    UINT64_C(1006636032), // STRBpre
6822
0
    UINT64_C(1008748544), // STRBroW
6823
0
    UINT64_C(1008756736), // STRBroX
6824
0
    UINT64_C(1023410176), // STRBui
6825
0
    UINT64_C(4227859456), // STRDpost
6826
0
    UINT64_C(4227861504), // STRDpre
6827
0
    UINT64_C(4229974016), // STRDroW
6828
0
    UINT64_C(4229982208), // STRDroX
6829
0
    UINT64_C(4244635648), // STRDui
6830
0
    UINT64_C(2013266944), // STRHHpost
6831
0
    UINT64_C(2013268992), // STRHHpre
6832
0
    UINT64_C(2015381504), // STRHHroW
6833
0
    UINT64_C(2015389696), // STRHHroX
6834
0
    UINT64_C(2030043136), // STRHHui
6835
0
    UINT64_C(2080375808), // STRHpost
6836
0
    UINT64_C(2080377856), // STRHpre
6837
0
    UINT64_C(2082490368), // STRHroW
6838
0
    UINT64_C(2082498560), // STRHroX
6839
0
    UINT64_C(2097152000), // STRHui
6840
0
    UINT64_C(1015022592), // STRQpost
6841
0
    UINT64_C(1015024640), // STRQpre
6842
0
    UINT64_C(1017137152), // STRQroW
6843
0
    UINT64_C(1017145344), // STRQroX
6844
0
    UINT64_C(1031798784), // STRQui
6845
0
    UINT64_C(3154117632), // STRSpost
6846
0
    UINT64_C(3154119680), // STRSpre
6847
0
    UINT64_C(3156232192), // STRSroW
6848
0
    UINT64_C(3156240384), // STRSroX
6849
0
    UINT64_C(3170893824), // STRSui
6850
0
    UINT64_C(3087008768), // STRWpost
6851
0
    UINT64_C(3087010816), // STRWpre
6852
0
    UINT64_C(3089123328), // STRWroW
6853
0
    UINT64_C(3089131520), // STRWroX
6854
0
    UINT64_C(3103784960), // STRWui
6855
0
    UINT64_C(4160750592), // STRXpost
6856
0
    UINT64_C(4160752640), // STRXpre
6857
0
    UINT64_C(4162865152), // STRXroW
6858
0
    UINT64_C(4162873344), // STRXroX
6859
0
    UINT64_C(4177526784), // STRXui
6860
0
    UINT64_C(3850371072), // STR_PXI
6861
0
    UINT64_C(3779035136), // STR_TX
6862
0
    UINT64_C(3776970752), // STR_ZA
6863
0
    UINT64_C(3850387456), // STR_ZXI
6864
0
    UINT64_C(939526144),  // STTRBi
6865
0
    UINT64_C(2013267968), // STTRHi
6866
0
    UINT64_C(3087009792), // STTRWi
6867
0
    UINT64_C(4160751616), // STTRXi
6868
0
    UINT64_C(939524096),  // STURBBi
6869
0
    UINT64_C(1006632960), // STURBi
6870
0
    UINT64_C(4227858432), // STURDi
6871
0
    UINT64_C(2013265920), // STURHHi
6872
0
    UINT64_C(2080374784), // STURHi
6873
0
    UINT64_C(1015021568), // STURQi
6874
0
    UINT64_C(3154116608), // STURSi
6875
0
    UINT64_C(3087007744), // STURWi
6876
0
    UINT64_C(4160749568), // STURXi
6877
0
    UINT64_C(2283798528), // STXPW
6878
0
    UINT64_C(3357540352), // STXPX
6879
0
    UINT64_C(134217728),  // STXRB
6880
0
    UINT64_C(1207959552), // STXRH
6881
0
    UINT64_C(2281701376), // STXRW
6882
0
    UINT64_C(3355443200), // STXRX
6883
0
    UINT64_C(3655336960), // STZ2GPostIndex
6884
0
    UINT64_C(3655339008), // STZ2GPreIndex
6885
0
    UINT64_C(3655337984), // STZ2Gi
6886
0
    UINT64_C(3642753024), // STZGM
6887
0
    UINT64_C(3646948352), // STZGPostIndex
6888
0
    UINT64_C(3646950400), // STZGPreIndex
6889
0
    UINT64_C(3646949376), // STZGi
6890
0
    UINT64_C(3514826752), // SUBG
6891
0
    UINT64_C(1163948032), // SUBHNB_ZZZ_B
6892
0
    UINT64_C(1168142336), // SUBHNB_ZZZ_H
6893
0
    UINT64_C(1172336640), // SUBHNB_ZZZ_S
6894
0
    UINT64_C(1163949056), // SUBHNT_ZZZ_B
6895
0
    UINT64_C(1168143360), // SUBHNT_ZZZ_H
6896
0
    UINT64_C(1172337664), // SUBHNT_ZZZ_S
6897
0
    UINT64_C(245391360),  // SUBHNv2i64_v2i32
6898
0
    UINT64_C(1319133184), // SUBHNv2i64_v4i32
6899
0
    UINT64_C(241197056),  // SUBHNv4i32_v4i16
6900
0
    UINT64_C(1314938880), // SUBHNv4i32_v8i16
6901
0
    UINT64_C(1310744576), // SUBHNv8i16_v16i8
6902
0
    UINT64_C(237002752),  // SUBHNv8i16_v8i8
6903
0
    UINT64_C(2596274176), // SUBP
6904
0
    UINT64_C(3133145088), // SUBPS
6905
0
    UINT64_C(3657441280), // SUBPT_shift
6906
0
    UINT64_C(623099904),  // SUBR_ZI_B
6907
0
    UINT64_C(635682816),  // SUBR_ZI_D
6908
0
    UINT64_C(627294208),  // SUBR_ZI_H
6909
0
    UINT64_C(631488512),  // SUBR_ZI_S
6910
0
    UINT64_C(67305472), // SUBR_ZPmZ_B
6911
0
    UINT64_C(79888384), // SUBR_ZPmZ_D
6912
0
    UINT64_C(71499776), // SUBR_ZPmZ_H
6913
0
    UINT64_C(75694080), // SUBR_ZPmZ_S
6914
0
    UINT64_C(1895825408), // SUBSWri
6915
0
    UINT64_C(1795162112), // SUBSWrs
6916
0
    UINT64_C(1797259264), // SUBSWrx
6917
0
    UINT64_C(4043309056), // SUBSXri
6918
0
    UINT64_C(3942645760), // SUBSXrs
6919
0
    UINT64_C(3944742912), // SUBSXrx
6920
0
    UINT64_C(3944767488), // SUBSXrx64
6921
0
    UINT64_C(1358954496), // SUBWri
6922
0
    UINT64_C(1258291200), // SUBWrs
6923
0
    UINT64_C(1260388352), // SUBWrx
6924
0
    UINT64_C(3506438144), // SUBXri
6925
0
    UINT64_C(3405774848), // SUBXrs
6926
0
    UINT64_C(3407872000), // SUBXrx
6927
0
    UINT64_C(3407896576), // SUBXrx64
6928
0
    UINT64_C(3252688920), // SUB_VG2_M2Z2Z_D
6929
0
    UINT64_C(3248494616), // SUB_VG2_M2Z2Z_S
6930
0
    UINT64_C(3244300312), // SUB_VG2_M2ZZ_D
6931
0
    UINT64_C(3240106008), // SUB_VG2_M2ZZ_S
6932
0
    UINT64_C(3252689944), // SUB_VG2_M2Z_D
6933
0
    UINT64_C(3248495640), // SUB_VG2_M2Z_S
6934
0
    UINT64_C(3252754456), // SUB_VG4_M4Z4Z_D
6935
0
    UINT64_C(3248560152), // SUB_VG4_M4Z4Z_S
6936
0
    UINT64_C(3245348888), // SUB_VG4_M4ZZ_D
6937
0
    UINT64_C(3241154584), // SUB_VG4_M4ZZ_S
6938
0
    UINT64_C(3252755480), // SUB_VG4_M4Z_D
6939
0
    UINT64_C(3248561176), // SUB_VG4_M4Z_S
6940
0
    UINT64_C(622968832),  // SUB_ZI_B
6941
0
    UINT64_C(635551744),  // SUB_ZI_D
6942
0
    UINT64_C(627163136),  // SUB_ZI_H
6943
0
    UINT64_C(631357440),  // SUB_ZI_S
6944
0
    UINT64_C(67174400), // SUB_ZPmZ_B
6945
0
    UINT64_C(80019456), // SUB_ZPmZ_CPA
6946
0
    UINT64_C(79757312), // SUB_ZPmZ_D
6947
0
    UINT64_C(71368704), // SUB_ZPmZ_H
6948
0
    UINT64_C(75563008), // SUB_ZPmZ_S
6949
0
    UINT64_C(69207040), // SUB_ZZZ_B
6950
0
    UINT64_C(81792000), // SUB_ZZZ_CPA
6951
0
    UINT64_C(81789952), // SUB_ZZZ_D
6952
0
    UINT64_C(73401344), // SUB_ZZZ_H
6953
0
    UINT64_C(77595648), // SUB_ZZZ_S
6954
0
    UINT64_C(1847624704), // SUBv16i8
6955
0
    UINT64_C(2128643072), // SUBv1i64
6956
0
    UINT64_C(782271488),  // SUBv2i32
6957
0
    UINT64_C(1860207616), // SUBv2i64
6958
0
    UINT64_C(778077184),  // SUBv4i16
6959
0
    UINT64_C(1856013312), // SUBv4i32
6960
0
    UINT64_C(1851819008), // SUBv8i16
6961
0
    UINT64_C(773882880),  // SUBv8i8
6962
0
    UINT64_C(3243249720), // SUDOT_VG2_M2ZZI_BToS
6963
0
    UINT64_C(3240104984), // SUDOT_VG2_M2ZZ_BToS
6964
0
    UINT64_C(3243282488), // SUDOT_VG4_M4ZZI_BToS
6965
0
    UINT64_C(3241153560), // SUDOT_VG4_M4ZZ_BToS
6966
0
    UINT64_C(1151343616), // SUDOT_ZZZI
6967
0
    UINT64_C(1325461504), // SUDOTlanev16i8
6968
0
    UINT64_C(251719680),  // SUDOTlanev8i8
6969
0
    UINT64_C(3238002708), // SUMLALL_MZZI_BtoS
6970
0
    UINT64_C(3239051312), // SUMLALL_VG2_M2ZZI_BtoS
6971
0
    UINT64_C(3240099860), // SUMLALL_VG2_M2ZZ_BtoS
6972
0
    UINT64_C(3239084080), // SUMLALL_VG4_M4ZZI_BtoS
6973
0
    UINT64_C(3241148436), // SUMLALL_VG4_M4ZZ_BtoS
6974
0
    UINT64_C(2699034624), // SUMOPA_MPPZZ_D
6975
0
    UINT64_C(2694840320), // SUMOPA_MPPZZ_S
6976
0
    UINT64_C(2699034640), // SUMOPS_MPPZZ_D
6977
0
    UINT64_C(2694840336), // SUMOPS_MPPZZ_S
6978
0
    UINT64_C(99694592), // SUNPKHI_ZZ_D
6979
0
    UINT64_C(91305984), // SUNPKHI_ZZ_H
6980
0
    UINT64_C(95500288), // SUNPKHI_ZZ_S
6981
0
    UINT64_C(99629056), // SUNPKLO_ZZ_D
6982
0
    UINT64_C(91240448), // SUNPKLO_ZZ_H
6983
0
    UINT64_C(95434752), // SUNPKLO_ZZ_S
6984
0
    UINT64_C(3253067776), // SUNPK_VG2_2ZZ_D
6985
0
    UINT64_C(3244679168), // SUNPK_VG2_2ZZ_H
6986
0
    UINT64_C(3248873472), // SUNPK_VG2_2ZZ_S
6987
0
    UINT64_C(3254116352), // SUNPK_VG4_4Z2Z_D
6988
0
    UINT64_C(3245727744), // SUNPK_VG4_4Z2Z_H
6989
0
    UINT64_C(3249922048), // SUNPK_VG4_4Z2Z_S
6990
0
    UINT64_C(1142718464), // SUQADD_ZPmZ_B
6991
0
    UINT64_C(1155301376), // SUQADD_ZPmZ_D
6992
0
    UINT64_C(1146912768), // SUQADD_ZPmZ_H
6993
0
    UINT64_C(1151107072), // SUQADD_ZPmZ_S
6994
0
    UINT64_C(1310734336), // SUQADDv16i8
6995
0
    UINT64_C(1583364096), // SUQADDv1i16
6996
0
    UINT64_C(1587558400), // SUQADDv1i32
6997
0
    UINT64_C(1591752704), // SUQADDv1i64
6998
0
    UINT64_C(1579169792), // SUQADDv1i8
6999
0
    UINT64_C(245381120),  // SUQADDv2i32
7000
0
    UINT64_C(1323317248), // SUQADDv2i64
7001
0
    UINT64_C(241186816),  // SUQADDv4i16
7002
0
    UINT64_C(1319122944), // SUQADDv4i32
7003
0
    UINT64_C(1314928640), // SUQADDv8i16
7004
0
    UINT64_C(236992512),  // SUQADDv8i8
7005
0
    UINT64_C(3243278392), // SUVDOT_VG4_M4ZZI_BToS
7006
0
    UINT64_C(3556769793), // SVC
7007
0
    UINT64_C(3243245600), // SVDOT_VG2_M2ZZI_HtoS
7008
0
    UINT64_C(3243278368), // SVDOT_VG4_M4ZZI_BtoS
7009
0
    UINT64_C(3251669000), // SVDOT_VG4_M4ZZI_HtoD
7010
0
    UINT64_C(950042624),  // SWPAB
7011
0
    UINT64_C(2023784448), // SWPAH
7012
0
    UINT64_C(954236928),  // SWPALB
7013
0
    UINT64_C(2027978752), // SWPALH
7014
0
    UINT64_C(3101720576), // SWPALW
7015
0
    UINT64_C(4175462400), // SWPALX
7016
0
    UINT64_C(3097526272), // SWPAW
7017
0
    UINT64_C(4171268096), // SWPAX
7018
0
    UINT64_C(941654016),  // SWPB
7019
0
    UINT64_C(2015395840), // SWPH
7020
0
    UINT64_C(945848320),  // SWPLB
7021
0
    UINT64_C(2019590144), // SWPLH
7022
0
    UINT64_C(3093331968), // SWPLW
7023
0
    UINT64_C(4167073792), // SWPLX
7024
0
    UINT64_C(421560320),  // SWPP
7025
0
    UINT64_C(429948928),  // SWPPA
7026
0
    UINT64_C(434143232),  // SWPPAL
7027
0
    UINT64_C(425754624),  // SWPPL
7028
0
    UINT64_C(3089137664), // SWPW
7029
0
    UINT64_C(4162879488), // SWPX
7030
0
    UINT64_C(80781312), // SXTB_ZPmZ_D
7031
0
    UINT64_C(72392704), // SXTB_ZPmZ_H
7032
0
    UINT64_C(76587008), // SXTB_ZPmZ_S
7033
0
    UINT64_C(80912384), // SXTH_ZPmZ_D
7034
0
    UINT64_C(76718080), // SXTH_ZPmZ_S
7035
0
    UINT64_C(81043456), // SXTW_ZPmZ_D
7036
0
    UINT64_C(3576168448), // SYSLxt
7037
0
    UINT64_C(3578265600), // SYSPxt
7038
0
    UINT64_C(3578265631), // SYSPxt_XZR
7039
0
    UINT64_C(3574071296), // SYSxt
7040
0
    UINT64_C(1140914176), // TBLQ_ZZZ_B
7041
0
    UINT64_C(1153497088), // TBLQ_ZZZ_D
7042
0
    UINT64_C(1145108480), // TBLQ_ZZZ_H
7043
0
    UINT64_C(1149302784), // TBLQ_ZZZ_S
7044
0
    UINT64_C(85993472), // TBL_ZZZZ_B
7045
0
    UINT64_C(98576384), // TBL_ZZZZ_D
7046
0
    UINT64_C(90187776), // TBL_ZZZZ_H
7047
0
    UINT64_C(94382080), // TBL_ZZZZ_S
7048
0
    UINT64_C(85995520), // TBL_ZZZ_B
7049
0
    UINT64_C(98578432), // TBL_ZZZ_D
7050
0
    UINT64_C(90189824), // TBL_ZZZ_H
7051
0
    UINT64_C(94384128), // TBL_ZZZ_S
7052
0
    UINT64_C(1308647424), // TBLv16i8Four
7053
0
    UINT64_C(1308622848), // TBLv16i8One
7054
0
    UINT64_C(1308639232), // TBLv16i8Three
7055
0
    UINT64_C(1308631040), // TBLv16i8Two
7056
0
    UINT64_C(234905600),  // TBLv8i8Four
7057
0
    UINT64_C(234881024),  // TBLv8i8One
7058
0
    UINT64_C(234897408),  // TBLv8i8Three
7059
0
    UINT64_C(234889216),  // TBLv8i8Two
7060
0
    UINT64_C(922746880),  // TBNZW
7061
0
    UINT64_C(3070230528), // TBNZX
7062
0
    UINT64_C(85996544), // TBXQ_ZZZ_B
7063
0
    UINT64_C(98579456), // TBXQ_ZZZ_D
7064
0
    UINT64_C(90190848), // TBXQ_ZZZ_H
7065
0
    UINT64_C(94385152), // TBXQ_ZZZ_S
7066
0
    UINT64_C(85994496), // TBX_ZZZ_B
7067
0
    UINT64_C(98577408), // TBX_ZZZ_D
7068
0
    UINT64_C(90188800), // TBX_ZZZ_H
7069
0
    UINT64_C(94383104), // TBX_ZZZ_S
7070
0
    UINT64_C(1308651520), // TBXv16i8Four
7071
0
    UINT64_C(1308626944), // TBXv16i8One
7072
0
    UINT64_C(1308643328), // TBXv16i8Three
7073
0
    UINT64_C(1308635136), // TBXv16i8Two
7074
0
    UINT64_C(234909696),  // TBXv8i8Four
7075
0
    UINT64_C(234885120),  // TBXv8i8One
7076
0
    UINT64_C(234901504),  // TBXv8i8Three
7077
0
    UINT64_C(234893312),  // TBXv8i8Two
7078
0
    UINT64_C(905969664),  // TBZW
7079
0
    UINT64_C(3053453312), // TBZX
7080
0
    UINT64_C(3563061248), // TCANCEL
7081
0
    UINT64_C(3573756031), // TCOMMIT
7082
0
    UINT64_C(3574297312), // TRCIT
7083
0
    UINT64_C(86003712), // TRN1_PPP_B
7084
0
    UINT64_C(98586624), // TRN1_PPP_D
7085
0
    UINT64_C(90198016), // TRN1_PPP_H
7086
0
    UINT64_C(94392320), // TRN1_PPP_S
7087
0
    UINT64_C(86011904), // TRN1_ZZZ_B
7088
0
    UINT64_C(98594816), // TRN1_ZZZ_D
7089
0
    UINT64_C(90206208), // TRN1_ZZZ_H
7090
0
    UINT64_C(94377984), // TRN1_ZZZ_Q
7091
0
    UINT64_C(94400512), // TRN1_ZZZ_S
7092
0
    UINT64_C(1308633088), // TRN1v16i8
7093
0
    UINT64_C(243279872),  // TRN1v2i32
7094
0
    UINT64_C(1321216000), // TRN1v2i64
7095
0
    UINT64_C(239085568),  // TRN1v4i16
7096
0
    UINT64_C(1317021696), // TRN1v4i32
7097
0
    UINT64_C(1312827392), // TRN1v8i16
7098
0
    UINT64_C(234891264),  // TRN1v8i8
7099
0
    UINT64_C(86004736), // TRN2_PPP_B
7100
0
    UINT64_C(98587648), // TRN2_PPP_D
7101
0
    UINT64_C(90199040), // TRN2_PPP_H
7102
0
    UINT64_C(94393344), // TRN2_PPP_S
7103
0
    UINT64_C(86012928), // TRN2_ZZZ_B
7104
0
    UINT64_C(98595840), // TRN2_ZZZ_D
7105
0
    UINT64_C(90207232), // TRN2_ZZZ_H
7106
0
    UINT64_C(94379008), // TRN2_ZZZ_Q
7107
0
    UINT64_C(94401536), // TRN2_ZZZ_S
7108
0
    UINT64_C(1308649472), // TRN2v16i8
7109
0
    UINT64_C(243296256),  // TRN2v2i32
7110
0
    UINT64_C(1321232384), // TRN2v2i64
7111
0
    UINT64_C(239101952),  // TRN2v4i16
7112
0
    UINT64_C(1317038080), // TRN2v4i32
7113
0
    UINT64_C(1312843776), // TRN2v8i16
7114
0
    UINT64_C(234907648),  // TRN2v8i8
7115
0
    UINT64_C(3573752415), // TSB
7116
0
    UINT64_C(3575853152), // TSTART
7117
0
    UINT64_C(3575853408), // TTEST
7118
0
    UINT64_C(1170262016), // UABALB_ZZZ_D
7119
0
    UINT64_C(1161873408), // UABALB_ZZZ_H
7120
0
    UINT64_C(1166067712), // UABALB_ZZZ_S
7121
0
    UINT64_C(1170263040), // UABALT_ZZZ_D
7122
0
    UINT64_C(1161874432), // UABALT_ZZZ_H
7123
0
    UINT64_C(1166068736), // UABALT_ZZZ_S
7124
0
    UINT64_C(1847611392), // UABALv16i8_v8i16
7125
0
    UINT64_C(782258176),  // UABALv2i32_v2i64
7126
0
    UINT64_C(778063872),  // UABALv4i16_v4i32
7127
0
    UINT64_C(1856000000), // UABALv4i32_v2i64
7128
0
    UINT64_C(1851805696), // UABALv8i16_v4i32
7129
0
    UINT64_C(773869568),  // UABALv8i8_v8i16
7130
0
    UINT64_C(1157692416), // UABA_ZZZ_B
7131
0
    UINT64_C(1170275328), // UABA_ZZZ_D
7132
0
    UINT64_C(1161886720), // UABA_ZZZ_H
7133
0
    UINT64_C(1166081024), // UABA_ZZZ_S
7134
0
    UINT64_C(1847622656), // UABAv16i8
7135
0
    UINT64_C(782269440),  // UABAv2i32
7136
0
    UINT64_C(778075136),  // UABAv4i16
7137
0
    UINT64_C(1856011264), // UABAv4i32
7138
0
    UINT64_C(1851816960), // UABAv8i16
7139
0
    UINT64_C(773880832),  // UABAv8i8
7140
0
    UINT64_C(1170225152), // UABDLB_ZZZ_D
7141
0
    UINT64_C(1161836544), // UABDLB_ZZZ_H
7142
0
    UINT64_C(1166030848), // UABDLB_ZZZ_S
7143
0
    UINT64_C(1170226176), // UABDLT_ZZZ_D
7144
0
    UINT64_C(1161837568), // UABDLT_ZZZ_H
7145
0
    UINT64_C(1166031872), // UABDLT_ZZZ_S
7146
0
    UINT64_C(1847619584), // UABDLv16i8_v8i16
7147
0
    UINT64_C(782266368),  // UABDLv2i32_v2i64
7148
0
    UINT64_C(778072064),  // UABDLv4i16_v4i32
7149
0
    UINT64_C(1856008192), // UABDLv4i32_v2i64
7150
0
    UINT64_C(1851813888), // UABDLv8i16_v4i32
7151
0
    UINT64_C(773877760),  // UABDLv8i8_v8i16
7152
0
    UINT64_C(67960832), // UABD_ZPmZ_B
7153
0
    UINT64_C(80543744), // UABD_ZPmZ_D
7154
0
    UINT64_C(72155136), // UABD_ZPmZ_H
7155
0
    UINT64_C(76349440), // UABD_ZPmZ_S
7156
0
    UINT64_C(1847620608), // UABDv16i8
7157
0
    UINT64_C(782267392),  // UABDv2i32
7158
0
    UINT64_C(778073088),  // UABDv4i16
7159
0
    UINT64_C(1856009216), // UABDv4i32
7160
0
    UINT64_C(1851814912), // UABDv8i16
7161
0
    UINT64_C(773878784),  // UABDv8i8
7162
0
    UINT64_C(1153802240), // UADALP_ZPmZ_D
7163
0
    UINT64_C(1145413632), // UADALP_ZPmZ_H
7164
0
    UINT64_C(1149607936), // UADALP_ZPmZ_S
7165
0
    UINT64_C(1847617536), // UADALPv16i8_v8i16
7166
0
    UINT64_C(782264320),  // UADALPv2i32_v1i64
7167
0
    UINT64_C(778070016),  // UADALPv4i16_v2i32
7168
0
    UINT64_C(1856006144), // UADALPv4i32_v2i64
7169
0
    UINT64_C(1851811840), // UADALPv8i16_v4i32
7170
0
    UINT64_C(773875712),  // UADALPv8i8_v4i16
7171
0
    UINT64_C(1170212864), // UADDLB_ZZZ_D
7172
0
    UINT64_C(1161824256), // UADDLB_ZZZ_H
7173
0
    UINT64_C(1166018560), // UADDLB_ZZZ_S
7174
0
    UINT64_C(1847601152), // UADDLPv16i8_v8i16
7175
0
    UINT64_C(782247936),  // UADDLPv2i32_v1i64
7176
0
    UINT64_C(778053632),  // UADDLPv4i16_v2i32
7177
0
    UINT64_C(1855989760), // UADDLPv4i32_v2i64
7178
0
    UINT64_C(1851795456), // UADDLPv8i16_v4i32
7179
0
    UINT64_C(773859328),  // UADDLPv8i8_v4i16
7180
0
    UINT64_C(1170213888), // UADDLT_ZZZ_D
7181
0
    UINT64_C(1161825280), // UADDLT_ZZZ_H
7182
0
    UINT64_C(1166019584), // UADDLT_ZZZ_S
7183
0
    UINT64_C(1848653824), // UADDLVv16i8v
7184
0
    UINT64_C(779106304),  // UADDLVv4i16v
7185
0
    UINT64_C(1857042432), // UADDLVv4i32v
7186
0
    UINT64_C(1852848128), // UADDLVv8i16v
7187
0
    UINT64_C(774912000),  // UADDLVv8i8v
7188
0
    UINT64_C(1847590912), // UADDLv16i8_v8i16
7189
0
    UINT64_C(782237696),  // UADDLv2i32_v2i64
7190
0
    UINT64_C(778043392),  // UADDLv4i16_v4i32
7191
0
    UINT64_C(1855979520), // UADDLv4i32_v2i64
7192
0
    UINT64_C(1851785216), // UADDLv8i16_v4i32
7193
0
    UINT64_C(773849088),  // UADDLv8i8_v8i16
7194
0
    UINT64_C(67182592), // UADDV_VPZ_B
7195
0
    UINT64_C(79765504), // UADDV_VPZ_D
7196
0
    UINT64_C(71376896), // UADDV_VPZ_H
7197
0
    UINT64_C(75571200), // UADDV_VPZ_S
7198
0
    UINT64_C(1170229248), // UADDWB_ZZZ_D
7199
0
    UINT64_C(1161840640), // UADDWB_ZZZ_H
7200
0
    UINT64_C(1166034944), // UADDWB_ZZZ_S
7201
0
    UINT64_C(1170230272), // UADDWT_ZZZ_D
7202
0
    UINT64_C(1161841664), // UADDWT_ZZZ_H
7203
0
    UINT64_C(1166035968), // UADDWT_ZZZ_S
7204
0
    UINT64_C(1847595008), // UADDWv16i8_v8i16
7205
0
    UINT64_C(782241792),  // UADDWv2i32_v2i64
7206
0
    UINT64_C(778047488),  // UADDWv4i16_v4i32
7207
0
    UINT64_C(1855983616), // UADDWv4i32_v2i64
7208
0
    UINT64_C(1851789312), // UADDWv8i16_v4i32
7209
0
    UINT64_C(773853184),  // UADDWv8i8_v8i16
7210
0
    UINT64_C(1392508928), // UBFMWri
7211
0
    UINT64_C(3544186880), // UBFMXri
7212
0
    UINT64_C(3240150017), // UCLAMP_VG2_2Z2Z_B
7213
0
    UINT64_C(3252732929), // UCLAMP_VG2_2Z2Z_D
7214
0
    UINT64_C(3244344321), // UCLAMP_VG2_2Z2Z_H
7215
0
    UINT64_C(3248538625), // UCLAMP_VG2_2Z2Z_S
7216
0
    UINT64_C(3240152065), // UCLAMP_VG4_4Z4Z_B
7217
0
    UINT64_C(3252734977), // UCLAMP_VG4_4Z4Z_D
7218
0
    UINT64_C(3244346369), // UCLAMP_VG4_4Z4Z_H
7219
0
    UINT64_C(3248540673), // UCLAMP_VG4_4Z4Z_S
7220
0
    UINT64_C(1140900864), // UCLAMP_ZZZ_B
7221
0
    UINT64_C(1153483776), // UCLAMP_ZZZ_D
7222
0
    UINT64_C(1145095168), // UCLAMP_ZZZ_H
7223
0
    UINT64_C(1149289472), // UCLAMP_ZZZ_S
7224
0
    UINT64_C(507740160),  // UCVTFSWDri
7225
0
    UINT64_C(516128768),  // UCVTFSWHri
7226
0
    UINT64_C(503545856),  // UCVTFSWSri
7227
0
    UINT64_C(2655191040), // UCVTFSXDri
7228
0
    UINT64_C(2663579648), // UCVTFSXHri
7229
0
    UINT64_C(2650996736), // UCVTFSXSri
7230
0
    UINT64_C(509804544),  // UCVTFUWDri
7231
0
    UINT64_C(518193152),  // UCVTFUWHri
7232
0
    UINT64_C(505610240),  // UCVTFUWSri
7233
0
    UINT64_C(2657288192), // UCVTFUXDri
7234
0
    UINT64_C(2665676800), // UCVTFUXHri
7235
0
    UINT64_C(2653093888), // UCVTFUXSri
7236
0
    UINT64_C(3240288288), // UCVTF_2Z2Z_StoS
7237
0
    UINT64_C(3241336864), // UCVTF_4Z4Z_StoS
7238
0
    UINT64_C(1708630016), // UCVTF_ZPmZ_DtoD
7239
0
    UINT64_C(1700241408), // UCVTF_ZPmZ_DtoH
7240
0
    UINT64_C(1708498944), // UCVTF_ZPmZ_DtoS
7241
0
    UINT64_C(1699979264), // UCVTF_ZPmZ_HtoH
7242
0
    UINT64_C(1708236800), // UCVTF_ZPmZ_StoD
7243
0
    UINT64_C(1700110336), // UCVTF_ZPmZ_StoH
7244
0
    UINT64_C(1704304640), // UCVTF_ZPmZ_StoS
7245
0
    UINT64_C(2134959104), // UCVTFd
7246
0
    UINT64_C(2131813376), // UCVTFh
7247
0
    UINT64_C(2132861952), // UCVTFs
7248
0
    UINT64_C(2121914368), // UCVTFv1i16
7249
0
    UINT64_C(2116147200), // UCVTFv1i32
7250
0
    UINT64_C(2120341504), // UCVTFv1i64
7251
0
    UINT64_C(773969920),  // UCVTFv2f32
7252
0
    UINT64_C(1851906048), // UCVTFv2f64
7253
0
    UINT64_C(790684672),  // UCVTFv2i32_shift
7254
0
    UINT64_C(1866523648), // UCVTFv2i64_shift
7255
0
    UINT64_C(779737088),  // UCVTFv4f16
7256
0
    UINT64_C(1847711744), // UCVTFv4f32
7257
0
    UINT64_C(789636096),  // UCVTFv4i16_shift
7258
0
    UINT64_C(1864426496), // UCVTFv4i32_shift
7259
0
    UINT64_C(1853478912), // UCVTFv8f16
7260
0
    UINT64_C(1863377920), // UCVTFv8i16_shift
7261
0
    UINT64_C(0),  // UDF
7262
0
    UINT64_C(81199104), // UDIVR_ZPmZ_D
7263
0
    UINT64_C(77004800), // UDIVR_ZPmZ_S
7264
0
    UINT64_C(448792576),  // UDIVWr
7265
0
    UINT64_C(2596276224), // UDIVXr
7266
0
    UINT64_C(81068032), // UDIV_ZPmZ_D
7267
0
    UINT64_C(76873728), // UDIV_ZPmZ_S
7268
0
    UINT64_C(3248493584), // UDOT_VG2_M2Z2Z_BtoS
7269
0
    UINT64_C(3252687888), // UDOT_VG2_M2Z2Z_HtoD
7270
0
    UINT64_C(3252687896), // UDOT_VG2_M2Z2Z_HtoS
7271
0
    UINT64_C(3243249712), // UDOT_VG2_M2ZZI_BToS
7272
0
    UINT64_C(3243249680), // UDOT_VG2_M2ZZI_HToS
7273
0
    UINT64_C(3251634200), // UDOT_VG2_M2ZZI_HtoD
7274
0
    UINT64_C(3240104976), // UDOT_VG2_M2ZZ_BtoS
7275
0
    UINT64_C(3244299280), // UDOT_VG2_M2ZZ_HtoD
7276
0
    UINT64_C(3244299288), // UDOT_VG2_M2ZZ_HtoS
7277
0
    UINT64_C(3248559120), // UDOT_VG4_M4Z4Z_BtoS
7278
0
    UINT64_C(3252753424), // UDOT_VG4_M4Z4Z_HtoD
7279
0
    UINT64_C(3252753432), // UDOT_VG4_M4Z4Z_HtoS
7280
0
    UINT64_C(3243282480), // UDOT_VG4_M4ZZI_BtoS
7281
0
    UINT64_C(3243282448), // UDOT_VG4_M4ZZI_HToS
7282
0
    UINT64_C(3251666968), // UDOT_VG4_M4ZZI_HtoD
7283
0
    UINT64_C(3241153552), // UDOT_VG4_M4ZZ_BtoS
7284
0
    UINT64_C(3245347856), // UDOT_VG4_M4ZZ_HtoD
7285
0
    UINT64_C(3245347864), // UDOT_VG4_M4ZZ_HtoS
7286
0
    UINT64_C(1155531776), // UDOT_ZZZI_D
7287
0
    UINT64_C(1149291520), // UDOT_ZZZI_HtoS
7288
0
    UINT64_C(1151337472), // UDOT_ZZZI_S
7289
0
    UINT64_C(1153434624), // UDOT_ZZZ_D
7290
0
    UINT64_C(1140902912), // UDOT_ZZZ_HtoS
7291
0
    UINT64_C(1149240320), // UDOT_ZZZ_S
7292
0
    UINT64_C(1870716928), // UDOTlanev16i8
7293
0
    UINT64_C(796975104),  // UDOTlanev8i8
7294
0
    UINT64_C(1853920256), // UDOTv16i8
7295
0
    UINT64_C(780178432),  // UDOTv8i8
7296
0
    UINT64_C(1141997568), // UHADD_ZPmZ_B
7297
0
    UINT64_C(1154580480), // UHADD_ZPmZ_D
7298
0
    UINT64_C(1146191872), // UHADD_ZPmZ_H
7299
0
    UINT64_C(1150386176), // UHADD_ZPmZ_S
7300
0
    UINT64_C(1847591936), // UHADDv16i8
7301
0
    UINT64_C(782238720),  // UHADDv2i32
7302
0
    UINT64_C(778044416),  // UHADDv4i16
7303
0
    UINT64_C(1855980544), // UHADDv4i32
7304
0
    UINT64_C(1851786240), // UHADDv8i16
7305
0
    UINT64_C(773850112),  // UHADDv8i8
7306
0
    UINT64_C(1142390784), // UHSUBR_ZPmZ_B
7307
0
    UINT64_C(1154973696), // UHSUBR_ZPmZ_D
7308
0
    UINT64_C(1146585088), // UHSUBR_ZPmZ_H
7309
0
    UINT64_C(1150779392), // UHSUBR_ZPmZ_S
7310
0
    UINT64_C(1142128640), // UHSUB_ZPmZ_B
7311
0
    UINT64_C(1154711552), // UHSUB_ZPmZ_D
7312
0
    UINT64_C(1146322944), // UHSUB_ZPmZ_H
7313
0
    UINT64_C(1150517248), // UHSUB_ZPmZ_S
7314
0
    UINT64_C(1847600128), // UHSUBv16i8
7315
0
    UINT64_C(782246912),  // UHSUBv2i32
7316
0
    UINT64_C(778052608),  // UHSUBv4i16
7317
0
    UINT64_C(1855988736), // UHSUBv4i32
7318
0
    UINT64_C(1851794432), // UHSUBv8i16
7319
0
    UINT64_C(773858304),  // UHSUBv8i8
7320
0
    UINT64_C(2610954240), // UMADDLrrr
7321
0
    UINT64_C(1142267904), // UMAXP_ZPmZ_B
7322
0
    UINT64_C(1154850816), // UMAXP_ZPmZ_D
7323
0
    UINT64_C(1146462208), // UMAXP_ZPmZ_H
7324
0
    UINT64_C(1150656512), // UMAXP_ZPmZ_S
7325
0
    UINT64_C(1847632896), // UMAXPv16i8
7326
0
    UINT64_C(782279680),  // UMAXPv2i32
7327
0
    UINT64_C(778085376),  // UMAXPv4i16
7328
0
    UINT64_C(1856021504), // UMAXPv4i32
7329
0
    UINT64_C(1851827200), // UMAXPv8i16
7330
0
    UINT64_C(773891072),  // UMAXPv8i8
7331
0
    UINT64_C(67969024), // UMAXQV_VPZ_B
7332
0
    UINT64_C(80551936), // UMAXQV_VPZ_D
7333
0
    UINT64_C(72163328), // UMAXQV_VPZ_H
7334
0
    UINT64_C(76357632), // UMAXQV_VPZ_S
7335
0
    UINT64_C(67706880), // UMAXV_VPZ_B
7336
0
    UINT64_C(80289792), // UMAXV_VPZ_D
7337
0
    UINT64_C(71901184), // UMAXV_VPZ_H
7338
0
    UINT64_C(76095488), // UMAXV_VPZ_S
7339
0
    UINT64_C(1848682496), // UMAXVv16i8v
7340
0
    UINT64_C(779134976),  // UMAXVv4i16v
7341
0
    UINT64_C(1857071104), // UMAXVv4i32v
7342
0
    UINT64_C(1852876800), // UMAXVv8i16v
7343
0
    UINT64_C(774940672),  // UMAXVv8i8v
7344
0
    UINT64_C(298057728),  // UMAXWri
7345
0
    UINT64_C(448816128),  // UMAXWrr
7346
0
    UINT64_C(2445541376), // UMAXXri
7347
0
    UINT64_C(2596299776), // UMAXXrr
7348
0
    UINT64_C(3240144897), // UMAX_VG2_2Z2Z_B
7349
0
    UINT64_C(3252727809), // UMAX_VG2_2Z2Z_D
7350
0
    UINT64_C(3244339201), // UMAX_VG2_2Z2Z_H
7351
0
    UINT64_C(3248533505), // UMAX_VG2_2Z2Z_S
7352
0
    UINT64_C(3240140801), // UMAX_VG2_2ZZ_B
7353
0
    UINT64_C(3252723713), // UMAX_VG2_2ZZ_D
7354
0
    UINT64_C(3244335105), // UMAX_VG2_2ZZ_H
7355
0
    UINT64_C(3248529409), // UMAX_VG2_2ZZ_S
7356
0
    UINT64_C(3240146945), // UMAX_VG4_4Z4Z_B
7357
0
    UINT64_C(3252729857), // UMAX_VG4_4Z4Z_D
7358
0
    UINT64_C(3244341249), // UMAX_VG4_4Z4Z_H
7359
0
    UINT64_C(3248535553), // UMAX_VG4_4Z4Z_S
7360
0
    UINT64_C(3240142849), // UMAX_VG4_4ZZ_B
7361
0
    UINT64_C(3252725761), // UMAX_VG4_4ZZ_D
7362
0
    UINT64_C(3244337153), // UMAX_VG4_4ZZ_H
7363
0
    UINT64_C(3248531457), // UMAX_VG4_4ZZ_S
7364
0
    UINT64_C(623493120),  // UMAX_ZI_B
7365
0
    UINT64_C(636076032),  // UMAX_ZI_D
7366
0
    UINT64_C(627687424),  // UMAX_ZI_H
7367
0
    UINT64_C(631881728),  // UMAX_ZI_S
7368
0
    UINT64_C(67698688), // UMAX_ZPmZ_B
7369
0
    UINT64_C(80281600), // UMAX_ZPmZ_D
7370
0
    UINT64_C(71892992), // UMAX_ZPmZ_H
7371
0
    UINT64_C(76087296), // UMAX_ZPmZ_S
7372
0
    UINT64_C(1847616512), // UMAXv16i8
7373
0
    UINT64_C(782263296),  // UMAXv2i32
7374
0
    UINT64_C(778068992),  // UMAXv4i16
7375
0
    UINT64_C(1856005120), // UMAXv4i32
7376
0
    UINT64_C(1851810816), // UMAXv8i16
7377
0
    UINT64_C(773874688),  // UMAXv8i8
7378
0
    UINT64_C(1142398976), // UMINP_ZPmZ_B
7379
0
    UINT64_C(1154981888), // UMINP_ZPmZ_D
7380
0
    UINT64_C(1146593280), // UMINP_ZPmZ_H
7381
0
    UINT64_C(1150787584), // UMINP_ZPmZ_S
7382
0
    UINT64_C(1847634944), // UMINPv16i8
7383
0
    UINT64_C(782281728),  // UMINPv2i32
7384
0
    UINT64_C(778087424),  // UMINPv4i16
7385
0
    UINT64_C(1856023552), // UMINPv4i32
7386
0
    UINT64_C(1851829248), // UMINPv8i16
7387
0
    UINT64_C(773893120),  // UMINPv8i8
7388
0
    UINT64_C(68100096), // UMINQV_VPZ_B
7389
0
    UINT64_C(80683008), // UMINQV_VPZ_D
7390
0
    UINT64_C(72294400), // UMINQV_VPZ_H
7391
0
    UINT64_C(76488704), // UMINQV_VPZ_S
7392
0
    UINT64_C(67837952), // UMINV_VPZ_B
7393
0
    UINT64_C(80420864), // UMINV_VPZ_D
7394
0
    UINT64_C(72032256), // UMINV_VPZ_H
7395
0
    UINT64_C(76226560), // UMINV_VPZ_S
7396
0
    UINT64_C(1848748032), // UMINVv16i8v
7397
0
    UINT64_C(779200512),  // UMINVv4i16v
7398
0
    UINT64_C(1857136640), // UMINVv4i32v
7399
0
    UINT64_C(1852942336), // UMINVv8i16v
7400
0
    UINT64_C(775006208),  // UMINVv8i8v
7401
0
    UINT64_C(298582016),  // UMINWri
7402
0
    UINT64_C(448818176),  // UMINWrr
7403
0
    UINT64_C(2446065664), // UMINXri
7404
0
    UINT64_C(2596301824), // UMINXrr
7405
0
    UINT64_C(3240144929), // UMIN_VG2_2Z2Z_B
7406
0
    UINT64_C(3252727841), // UMIN_VG2_2Z2Z_D
7407
0
    UINT64_C(3244339233), // UMIN_VG2_2Z2Z_H
7408
0
    UINT64_C(3248533537), // UMIN_VG2_2Z2Z_S
7409
0
    UINT64_C(3240140833), // UMIN_VG2_2ZZ_B
7410
0
    UINT64_C(3252723745), // UMIN_VG2_2ZZ_D
7411
0
    UINT64_C(3244335137), // UMIN_VG2_2ZZ_H
7412
0
    UINT64_C(3248529441), // UMIN_VG2_2ZZ_S
7413
0
    UINT64_C(3240146977), // UMIN_VG4_4Z4Z_B
7414
0
    UINT64_C(3252729889), // UMIN_VG4_4Z4Z_D
7415
0
    UINT64_C(3244341281), // UMIN_VG4_4Z4Z_H
7416
0
    UINT64_C(3248535585), // UMIN_VG4_4Z4Z_S
7417
0
    UINT64_C(3240142881), // UMIN_VG4_4ZZ_B
7418
0
    UINT64_C(3252725793), // UMIN_VG4_4ZZ_D
7419
0
    UINT64_C(3244337185), // UMIN_VG4_4ZZ_H
7420
0
    UINT64_C(3248531489), // UMIN_VG4_4ZZ_S
7421
0
    UINT64_C(623624192),  // UMIN_ZI_B
7422
0
    UINT64_C(636207104),  // UMIN_ZI_D
7423
0
    UINT64_C(627818496),  // UMIN_ZI_H
7424
0
    UINT64_C(632012800),  // UMIN_ZI_S
7425
0
    UINT64_C(67829760), // UMIN_ZPmZ_B
7426
0
    UINT64_C(80412672), // UMIN_ZPmZ_D
7427
0
    UINT64_C(72024064), // UMIN_ZPmZ_H
7428
0
    UINT64_C(76218368), // UMIN_ZPmZ_S
7429
0
    UINT64_C(1847618560), // UMINv16i8
7430
0
    UINT64_C(782265344),  // UMINv2i32
7431
0
    UINT64_C(778071040),  // UMINv4i16
7432
0
    UINT64_C(1856007168), // UMINv4i32
7433
0
    UINT64_C(1851812864), // UMINv8i16
7434
0
    UINT64_C(773876736),  // UMINv8i8
7435
0
    UINT64_C(1155567616), // UMLALB_ZZZI_D
7436
0
    UINT64_C(1151373312), // UMLALB_ZZZI_S
7437
0
    UINT64_C(1153452032), // UMLALB_ZZZ_D
7438
0
    UINT64_C(1145063424), // UMLALB_ZZZ_H
7439
0
    UINT64_C(1149257728), // UMLALB_ZZZ_S
7440
0
    UINT64_C(3238002704), // UMLALL_MZZI_BtoS
7441
0
    UINT64_C(3246391312), // UMLALL_MZZI_HtoD
7442
0
    UINT64_C(3240100880), // UMLALL_MZZ_BtoS
7443
0
    UINT64_C(3244295184), // UMLALL_MZZ_HtoD
7444
0
    UINT64_C(3248488464), // UMLALL_VG2_M2Z2Z_BtoS
7445
0
    UINT64_C(3252682768), // UMLALL_VG2_M2Z2Z_HtoD
7446
0
    UINT64_C(3239051280), // UMLALL_VG2_M2ZZI_BtoS
7447
0
    UINT64_C(3247439888), // UMLALL_VG2_M2ZZI_HtoD
7448
0
    UINT64_C(3240099856), // UMLALL_VG2_M2ZZ_BtoS
7449
0
    UINT64_C(3244294160), // UMLALL_VG2_M2ZZ_HtoD
7450
0
    UINT64_C(3248554000), // UMLALL_VG4_M4Z4Z_BtoS
7451
0
    UINT64_C(3252748304), // UMLALL_VG4_M4Z4Z_HtoD
7452
0
    UINT64_C(3239084048), // UMLALL_VG4_M4ZZI_BtoS
7453
0
    UINT64_C(3247472656), // UMLALL_VG4_M4ZZI_HtoD
7454
0
    UINT64_C(3241148432), // UMLALL_VG4_M4ZZ_BtoS
7455
0
    UINT64_C(3245342736), // UMLALL_VG4_M4ZZ_HtoD
7456
0
    UINT64_C(1155568640), // UMLALT_ZZZI_D
7457
0
    UINT64_C(1151374336), // UMLALT_ZZZI_S
7458
0
    UINT64_C(1153453056), // UMLALT_ZZZ_D
7459
0
    UINT64_C(1145064448), // UMLALT_ZZZ_H
7460
0
    UINT64_C(1149258752), // UMLALT_ZZZ_S
7461
0
    UINT64_C(3250589712), // UMLAL_MZZI_HtoS
7462
0
    UINT64_C(3244297232), // UMLAL_MZZ_HtoS
7463
0
    UINT64_C(3252684816), // UMLAL_VG2_M2Z2Z_HtoS
7464
0
    UINT64_C(3251638288), // UMLAL_VG2_M2ZZI_S
7465
0
    UINT64_C(3244296208), // UMLAL_VG2_M2ZZ_HtoS
7466
0
    UINT64_C(3252750352), // UMLAL_VG4_M4Z4Z_HtoS
7467
0
    UINT64_C(3251671056), // UMLAL_VG4_M4ZZI_HtoS
7468
0
    UINT64_C(3245344784), // UMLAL_VG4_M4ZZ_HtoS
7469
0
    UINT64_C(1847623680), // UMLALv16i8_v8i16
7470
0
    UINT64_C(796925952),  // UMLALv2i32_indexed
7471
0
    UINT64_C(782270464),  // UMLALv2i32_v2i64
7472
0
    UINT64_C(792731648),  // UMLALv4i16_indexed
7473
0
    UINT64_C(778076160),  // UMLALv4i16_v4i32
7474
0
    UINT64_C(1870667776), // UMLALv4i32_indexed
7475
0
    UINT64_C(1856012288), // UMLALv4i32_v2i64
7476
0
    UINT64_C(1866473472), // UMLALv8i16_indexed
7477
0
    UINT64_C(1851817984), // UMLALv8i16_v4i32
7478
0
    UINT64_C(773881856),  // UMLALv8i8_v8i16
7479
0
    UINT64_C(1155575808), // UMLSLB_ZZZI_D
7480
0
    UINT64_C(1151381504), // UMLSLB_ZZZI_S
7481
0
    UINT64_C(1153456128), // UMLSLB_ZZZ_D
7482
0
    UINT64_C(1145067520), // UMLSLB_ZZZ_H
7483
0
    UINT64_C(1149261824), // UMLSLB_ZZZ_S
7484
0
    UINT64_C(3238002712), // UMLSLL_MZZI_BtoS
7485
0
    UINT64_C(3246391320), // UMLSLL_MZZI_HtoD
7486
0
    UINT64_C(3240100888), // UMLSLL_MZZ_BtoS
7487
0
    UINT64_C(3244295192), // UMLSLL_MZZ_HtoD
7488
0
    UINT64_C(3248488472), // UMLSLL_VG2_M2Z2Z_BtoS
7489
0
    UINT64_C(3252682776), // UMLSLL_VG2_M2Z2Z_HtoD
7490
0
    UINT64_C(3239051288), // UMLSLL_VG2_M2ZZI_BtoS
7491
0
    UINT64_C(3247439896), // UMLSLL_VG2_M2ZZI_HtoD
7492
0
    UINT64_C(3240099864), // UMLSLL_VG2_M2ZZ_BtoS
7493
0
    UINT64_C(3244294168), // UMLSLL_VG2_M2ZZ_HtoD
7494
0
    UINT64_C(3248554008), // UMLSLL_VG4_M4Z4Z_BtoS
7495
0
    UINT64_C(3252748312), // UMLSLL_VG4_M4Z4Z_HtoD
7496
0
    UINT64_C(3239084056), // UMLSLL_VG4_M4ZZI_BtoS
7497
0
    UINT64_C(3247472664), // UMLSLL_VG4_M4ZZI_HtoD
7498
0
    UINT64_C(3241148440), // UMLSLL_VG4_M4ZZ_BtoS
7499
0
    UINT64_C(3245342744), // UMLSLL_VG4_M4ZZ_HtoD
7500
0
    UINT64_C(1155576832), // UMLSLT_ZZZI_D
7501
0
    UINT64_C(1151382528), // UMLSLT_ZZZI_S
7502
0
    UINT64_C(1153457152), // UMLSLT_ZZZ_D
7503
0
    UINT64_C(1145068544), // UMLSLT_ZZZ_H
7504
0
    UINT64_C(1149262848), // UMLSLT_ZZZ_S
7505
0
    UINT64_C(3250589720), // UMLSL_MZZI_HtoS
7506
0
    UINT64_C(3244297240), // UMLSL_MZZ_HtoS
7507
0
    UINT64_C(3252684824), // UMLSL_VG2_M2Z2Z_HtoS
7508
0
    UINT64_C(3251638296), // UMLSL_VG2_M2ZZI_S
7509
0
    UINT64_C(3244296216), // UMLSL_VG2_M2ZZ_HtoS
7510
0
    UINT64_C(3252750360), // UMLSL_VG4_M4Z4Z_HtoS
7511
0
    UINT64_C(3251671064), // UMLSL_VG4_M4ZZI_HtoS
7512
0
    UINT64_C(3245344792), // UMLSL_VG4_M4ZZ_HtoS
7513
0
    UINT64_C(1847631872), // UMLSLv16i8_v8i16
7514
0
    UINT64_C(796942336),  // UMLSLv2i32_indexed
7515
0
    UINT64_C(782278656),  // UMLSLv2i32_v2i64
7516
0
    UINT64_C(792748032),  // UMLSLv4i16_indexed
7517
0
    UINT64_C(778084352),  // UMLSLv4i16_v4i32
7518
0
    UINT64_C(1870684160), // UMLSLv4i32_indexed
7519
0
    UINT64_C(1856020480), // UMLSLv4i32_v2i64
7520
0
    UINT64_C(1866489856), // UMLSLv8i16_indexed
7521
0
    UINT64_C(1851826176), // UMLSLv8i16_v4i32
7522
0
    UINT64_C(773890048),  // UMLSLv8i8_v8i16
7523
0
    UINT64_C(1853924352), // UMMLA
7524
0
    UINT64_C(1170249728), // UMMLA_ZZZ
7525
0
    UINT64_C(2715811840), // UMOPA_MPPZZ_D
7526
0
    UINT64_C(2709520392), // UMOPA_MPPZZ_HtoS
7527
0
    UINT64_C(2711617536), // UMOPA_MPPZZ_S
7528
0
    UINT64_C(2715811856), // UMOPS_MPPZZ_D
7529
0
    UINT64_C(2709520408), // UMOPS_MPPZZ_HtoS
7530
0
    UINT64_C(2711617552), // UMOPS_MPPZZ_S
7531
0
    UINT64_C(235027456),  // UMOVvi16
7532
0
    UINT64_C(235027456),  // UMOVvi16_idx0
7533
0
    UINT64_C(235158528),  // UMOVvi32
7534
0
    UINT64_C(235158528),  // UMOVvi32_idx0
7535
0
    UINT64_C(1309162496), // UMOVvi64
7536
0
    UINT64_C(1309162496), // UMOVvi64_idx0
7537
0
    UINT64_C(234961920),  // UMOVvi8
7538
0
    UINT64_C(234961920),  // UMOVvi8_idx0
7539
0
    UINT64_C(2610987008), // UMSUBLrrr
7540
0
    UINT64_C(68354048), // UMULH_ZPmZ_B
7541
0
    UINT64_C(80936960), // UMULH_ZPmZ_D
7542
0
    UINT64_C(72548352), // UMULH_ZPmZ_H
7543
0
    UINT64_C(76742656), // UMULH_ZPmZ_S
7544
0
    UINT64_C(69233664), // UMULH_ZZZ_B
7545
0
    UINT64_C(81816576), // UMULH_ZZZ_D
7546
0
    UINT64_C(73427968), // UMULH_ZZZ_H
7547
0
    UINT64_C(77622272), // UMULH_ZZZ_S
7548
0
    UINT64_C(2613051392), // UMULHrr
7549
0
    UINT64_C(1155584000), // UMULLB_ZZZI_D
7550
0
    UINT64_C(1151389696), // UMULLB_ZZZI_S
7551
0
    UINT64_C(1170241536), // UMULLB_ZZZ_D
7552
0
    UINT64_C(1161852928), // UMULLB_ZZZ_H
7553
0
    UINT64_C(1166047232), // UMULLB_ZZZ_S
7554
0
    UINT64_C(1155585024), // UMULLT_ZZZI_D
7555
0
    UINT64_C(1151390720), // UMULLT_ZZZI_S
7556
0
    UINT64_C(1170242560), // UMULLT_ZZZ_D
7557
0
    UINT64_C(1161853952), // UMULLT_ZZZ_H
7558
0
    UINT64_C(1166048256), // UMULLT_ZZZ_S
7559
0
    UINT64_C(1847640064), // UMULLv16i8_v8i16
7560
0
    UINT64_C(796958720),  // UMULLv2i32_indexed
7561
0
    UINT64_C(782286848),  // UMULLv2i32_v2i64
7562
0
    UINT64_C(792764416),  // UMULLv4i16_indexed
7563
0
    UINT64_C(778092544),  // UMULLv4i16_v4i32
7564
0
    UINT64_C(1870700544), // UMULLv4i32_indexed
7565
0
    UINT64_C(1856028672), // UMULLv4i32_v2i64
7566
0
    UINT64_C(1866506240), // UMULLv8i16_indexed
7567
0
    UINT64_C(1851834368), // UMULLv8i16_v4i32
7568
0
    UINT64_C(773898240),  // UMULLv8i8_v8i16
7569
0
    UINT64_C(623230976),  // UQADD_ZI_B
7570
0
    UINT64_C(635813888),  // UQADD_ZI_D
7571
0
    UINT64_C(627425280),  // UQADD_ZI_H
7572
0
    UINT64_C(631619584),  // UQADD_ZI_S
7573
0
    UINT64_C(1142521856), // UQADD_ZPmZ_B
7574
0
    UINT64_C(1155104768), // UQADD_ZPmZ_D
7575
0
    UINT64_C(1146716160), // UQADD_ZPmZ_H
7576
0
    UINT64_C(1150910464), // UQADD_ZPmZ_S
7577
0
    UINT64_C(69211136), // UQADD_ZZZ_B
7578
0
    UINT64_C(81794048), // UQADD_ZZZ_D
7579
0
    UINT64_C(73405440), // UQADD_ZZZ_H
7580
0
    UINT64_C(77599744), // UQADD_ZZZ_S
7581
0
    UINT64_C(1847593984), // UQADDv16i8
7582
0
    UINT64_C(2120223744), // UQADDv1i16
7583
0
    UINT64_C(2124418048), // UQADDv1i32
7584
0
    UINT64_C(2128612352), // UQADDv1i64
7585
0
    UINT64_C(2116029440), // UQADDv1i8
7586
0
    UINT64_C(782240768),  // UQADDv2i32
7587
0
    UINT64_C(1860176896), // UQADDv2i64
7588
0
    UINT64_C(778046464),  // UQADDv4i16
7589
0
    UINT64_C(1855982592), // UQADDv4i32
7590
0
    UINT64_C(1851788288), // UQADDv8i16
7591
0
    UINT64_C(773852160),  // UQADDv8i8
7592
0
    UINT64_C(1160857600), // UQCVTN_Z2Z_StoH
7593
0
    UINT64_C(3249791072), // UQCVTN_Z4Z_DtoH
7594
0
    UINT64_C(3241402464), // UQCVTN_Z4Z_StoB
7595
0
    UINT64_C(3240353824), // UQCVT_Z2Z_StoH
7596
0
    UINT64_C(3249791008), // UQCVT_Z4Z_DtoH
7597
0
    UINT64_C(3241402400), // UQCVT_Z4Z_StoB
7598
0
    UINT64_C(69270528), // UQDECB_WPiI
7599
0
    UINT64_C(70319104), // UQDECB_XPiI
7600
0
    UINT64_C(81853440), // UQDECD_WPiI
7601
0
    UINT64_C(82902016), // UQDECD_XPiI
7602
0
    UINT64_C(81841152), // UQDECD_ZPiI
7603
0
    UINT64_C(73464832), // UQDECH_WPiI
7604
0
    UINT64_C(74513408), // UQDECH_XPiI
7605
0
    UINT64_C(73452544), // UQDECH_ZPiI
7606
0
    UINT64_C(623609856),  // UQDECP_WP_B
7607
0
    UINT64_C(636192768),  // UQDECP_WP_D
7608
0
    UINT64_C(627804160),  // UQDECP_WP_H
7609
0
    UINT64_C(631998464),  // UQDECP_WP_S
7610
0
    UINT64_C(623610880),  // UQDECP_XP_B
7611
0
    UINT64_C(636193792),  // UQDECP_XP_D
7612
0
    UINT64_C(627805184),  // UQDECP_XP_H
7613
0
    UINT64_C(631999488),  // UQDECP_XP_S
7614
0
    UINT64_C(636190720),  // UQDECP_ZP_D
7615
0
    UINT64_C(627802112),  // UQDECP_ZP_H
7616
0
    UINT64_C(631996416),  // UQDECP_ZP_S
7617
0
    UINT64_C(77659136), // UQDECW_WPiI
7618
0
    UINT64_C(78707712), // UQDECW_XPiI
7619
0
    UINT64_C(77646848), // UQDECW_ZPiI
7620
0
    UINT64_C(69268480), // UQINCB_WPiI
7621
0
    UINT64_C(70317056), // UQINCB_XPiI
7622
0
    UINT64_C(81851392), // UQINCD_WPiI
7623
0
    UINT64_C(82899968), // UQINCD_XPiI
7624
0
    UINT64_C(81839104), // UQINCD_ZPiI
7625
0
    UINT64_C(73462784), // UQINCH_WPiI
7626
0
    UINT64_C(74511360), // UQINCH_XPiI
7627
0
    UINT64_C(73450496), // UQINCH_ZPiI
7628
0
    UINT64_C(623478784),  // UQINCP_WP_B
7629
0
    UINT64_C(636061696),  // UQINCP_WP_D
7630
0
    UINT64_C(627673088),  // UQINCP_WP_H
7631
0
    UINT64_C(631867392),  // UQINCP_WP_S
7632
0
    UINT64_C(623479808),  // UQINCP_XP_B
7633
0
    UINT64_C(636062720),  // UQINCP_XP_D
7634
0
    UINT64_C(627674112),  // UQINCP_XP_H
7635
0
    UINT64_C(631868416),  // UQINCP_XP_S
7636
0
    UINT64_C(636059648),  // UQINCP_ZP_D
7637
0
    UINT64_C(627671040),  // UQINCP_ZP_H
7638
0
    UINT64_C(631865344),  // UQINCP_ZP_S
7639
0
    UINT64_C(77657088), // UQINCW_WPiI
7640
0
    UINT64_C(78705664), // UQINCW_XPiI
7641
0
    UINT64_C(77644800), // UQINCW_ZPiI
7642
0
    UINT64_C(1141866496), // UQRSHLR_ZPmZ_B
7643
0
    UINT64_C(1154449408), // UQRSHLR_ZPmZ_D
7644
0
    UINT64_C(1146060800), // UQRSHLR_ZPmZ_H
7645
0
    UINT64_C(1150255104), // UQRSHLR_ZPmZ_S
7646
0
    UINT64_C(1141604352), // UQRSHL_ZPmZ_B
7647
0
    UINT64_C(1154187264), // UQRSHL_ZPmZ_D
7648
0
    UINT64_C(1145798656), // UQRSHL_ZPmZ_H
7649
0
    UINT64_C(1149992960), // UQRSHL_ZPmZ_S
7650
0
    UINT64_C(1847614464), // UQRSHLv16i8
7651
0
    UINT64_C(2120244224), // UQRSHLv1i16
7652
0
    UINT64_C(2124438528), // UQRSHLv1i32
7653
0
    UINT64_C(2128632832), // UQRSHLv1i64
7654
0
    UINT64_C(2116049920), // UQRSHLv1i8
7655
0
    UINT64_C(782261248),  // UQRSHLv2i32
7656
0
    UINT64_C(1860197376), // UQRSHLv2i64
7657
0
    UINT64_C(778066944),  // UQRSHLv4i16
7658
0
    UINT64_C(1856003072), // UQRSHLv4i32
7659
0
    UINT64_C(1851808768), // UQRSHLv8i16
7660
0
    UINT64_C(773872640),  // UQRSHLv8i8
7661
0
    UINT64_C(1160263680), // UQRSHRNB_ZZI_B
7662
0
    UINT64_C(1160787968), // UQRSHRNB_ZZI_H
7663
0
    UINT64_C(1163933696), // UQRSHRNB_ZZI_S
7664
0
    UINT64_C(1160264704), // UQRSHRNT_ZZI_B
7665
0
    UINT64_C(1160788992), // UQRSHRNT_ZZI_H
7666
0
    UINT64_C(1163934720), // UQRSHRNT_ZZI_S
7667
0
    UINT64_C(3244350496), // UQRSHRN_VG4_Z4ZI_B
7668
0
    UINT64_C(3248544800), // UQRSHRN_VG4_Z4ZI_H
7669
0
    UINT64_C(1169176576), // UQRSHRN_Z2ZI_StoH
7670
0
    UINT64_C(2131270656), // UQRSHRNb
7671
0
    UINT64_C(2131794944), // UQRSHRNh
7672
0
    UINT64_C(2132843520), // UQRSHRNs
7673
0
    UINT64_C(1862835200), // UQRSHRNv16i8_shift
7674
0
    UINT64_C(790666240),  // UQRSHRNv2i32_shift
7675
0
    UINT64_C(789617664),  // UQRSHRNv4i16_shift
7676
0
    UINT64_C(1864408064), // UQRSHRNv4i32_shift
7677
0
    UINT64_C(1863359488), // UQRSHRNv8i16_shift
7678
0
    UINT64_C(789093376),  // UQRSHRNv8i8_shift
7679
0
    UINT64_C(3252737056), // UQRSHR_VG2_Z2ZI_H
7680
0
    UINT64_C(3244349472), // UQRSHR_VG4_Z4ZI_B
7681
0
    UINT64_C(3248543776), // UQRSHR_VG4_Z4ZI_H
7682
0
    UINT64_C(1141735424), // UQSHLR_ZPmZ_B
7683
0
    UINT64_C(1154318336), // UQSHLR_ZPmZ_D
7684
0
    UINT64_C(1145929728), // UQSHLR_ZPmZ_H
7685
0
    UINT64_C(1150124032), // UQSHLR_ZPmZ_S
7686
0
    UINT64_C(67600640), // UQSHL_ZPmI_B
7687
0
    UINT64_C(75988992), // UQSHL_ZPmI_D
7688
0
    UINT64_C(67600896), // UQSHL_ZPmI_H
7689
0
    UINT64_C(71794688), // UQSHL_ZPmI_S
7690
0
    UINT64_C(1141473280), // UQSHL_ZPmZ_B
7691
0
    UINT64_C(1154056192), // UQSHL_ZPmZ_D
7692
0
    UINT64_C(1145667584), // UQSHL_ZPmZ_H
7693
0
    UINT64_C(1149861888), // UQSHL_ZPmZ_S
7694
0
    UINT64_C(2131260416), // UQSHLb
7695
0
    UINT64_C(2134930432), // UQSHLd
7696
0
    UINT64_C(2131784704), // UQSHLh
7697
0
    UINT64_C(2132833280), // UQSHLs
7698
0
    UINT64_C(1847610368), // UQSHLv16i8
7699
0
    UINT64_C(1862824960), // UQSHLv16i8_shift
7700
0
    UINT64_C(2120240128), // UQSHLv1i16
7701
0
    UINT64_C(2124434432), // UQSHLv1i32
7702
0
    UINT64_C(2128628736), // UQSHLv1i64
7703
0
    UINT64_C(2116045824), // UQSHLv1i8
7704
0
    UINT64_C(782257152),  // UQSHLv2i32
7705
0
    UINT64_C(790656000),  // UQSHLv2i32_shift
7706
0
    UINT64_C(1860193280), // UQSHLv2i64
7707
0
    UINT64_C(1866494976), // UQSHLv2i64_shift
7708
0
    UINT64_C(778062848),  // UQSHLv4i16
7709
0
    UINT64_C(789607424),  // UQSHLv4i16_shift
7710
0
    UINT64_C(1855998976), // UQSHLv4i32
7711
0
    UINT64_C(1864397824), // UQSHLv4i32_shift
7712
0
    UINT64_C(1851804672), // UQSHLv8i16
7713
0
    UINT64_C(1863349248), // UQSHLv8i16_shift
7714
0
    UINT64_C(773868544),  // UQSHLv8i8
7715
0
    UINT64_C(789083136),  // UQSHLv8i8_shift
7716
0
    UINT64_C(1160261632), // UQSHRNB_ZZI_B
7717
0
    UINT64_C(1160785920), // UQSHRNB_ZZI_H
7718
0
    UINT64_C(1163931648), // UQSHRNB_ZZI_S
7719
0
    UINT64_C(1160262656), // UQSHRNT_ZZI_B
7720
0
    UINT64_C(1160786944), // UQSHRNT_ZZI_H
7721
0
    UINT64_C(1163932672), // UQSHRNT_ZZI_S
7722
0
    UINT64_C(2131268608), // UQSHRNb
7723
0
    UINT64_C(2131792896), // UQSHRNh
7724
0
    UINT64_C(2132841472), // UQSHRNs
7725
0
    UINT64_C(1862833152), // UQSHRNv16i8_shift
7726
0
    UINT64_C(790664192),  // UQSHRNv2i32_shift
7727
0
    UINT64_C(789615616),  // UQSHRNv4i16_shift
7728
0
    UINT64_C(1864406016), // UQSHRNv4i32_shift
7729
0
    UINT64_C(1863357440), // UQSHRNv8i16_shift
7730
0
    UINT64_C(789091328),  // UQSHRNv8i8_shift
7731
0
    UINT64_C(1142915072), // UQSUBR_ZPmZ_B
7732
0
    UINT64_C(1155497984), // UQSUBR_ZPmZ_D
7733
0
    UINT64_C(1147109376), // UQSUBR_ZPmZ_H
7734
0
    UINT64_C(1151303680), // UQSUBR_ZPmZ_S
7735
0
    UINT64_C(623362048),  // UQSUB_ZI_B
7736
0
    UINT64_C(635944960),  // UQSUB_ZI_D
7737
0
    UINT64_C(627556352),  // UQSUB_ZI_H
7738
0
    UINT64_C(631750656),  // UQSUB_ZI_S
7739
0
    UINT64_C(1142652928), // UQSUB_ZPmZ_B
7740
0
    UINT64_C(1155235840), // UQSUB_ZPmZ_D
7741
0
    UINT64_C(1146847232), // UQSUB_ZPmZ_H
7742
0
    UINT64_C(1151041536), // UQSUB_ZPmZ_S
7743
0
    UINT64_C(69213184), // UQSUB_ZZZ_B
7744
0
    UINT64_C(81796096), // UQSUB_ZZZ_D
7745
0
    UINT64_C(73407488), // UQSUB_ZZZ_H
7746
0
    UINT64_C(77601792), // UQSUB_ZZZ_S
7747
0
    UINT64_C(1847602176), // UQSUBv16i8
7748
0
    UINT64_C(2120231936), // UQSUBv1i16
7749
0
    UINT64_C(2124426240), // UQSUBv1i32
7750
0
    UINT64_C(2128620544), // UQSUBv1i64
7751
0
    UINT64_C(2116037632), // UQSUBv1i8
7752
0
    UINT64_C(782248960),  // UQSUBv2i32
7753
0
    UINT64_C(1860185088), // UQSUBv2i64
7754
0
    UINT64_C(778054656),  // UQSUBv4i16
7755
0
    UINT64_C(1855990784), // UQSUBv4i32
7756
0
    UINT64_C(1851796480), // UQSUBv8i16
7757
0
    UINT64_C(773860352),  // UQSUBv8i8
7758
0
    UINT64_C(1160267776), // UQXTNB_ZZ_B
7759
0
    UINT64_C(1160792064), // UQXTNB_ZZ_H
7760
0
    UINT64_C(1163937792), // UQXTNB_ZZ_S
7761
0
    UINT64_C(1160268800), // UQXTNT_ZZ_B
7762
0
    UINT64_C(1160793088), // UQXTNT_ZZ_H
7763
0
    UINT64_C(1163938816), // UQXTNT_ZZ_S
7764
0
    UINT64_C(1847674880), // UQXTNv16i8
7765
0
    UINT64_C(2120304640), // UQXTNv1i16
7766
0
    UINT64_C(2124498944), // UQXTNv1i32
7767
0
    UINT64_C(2116110336), // UQXTNv1i8
7768
0
    UINT64_C(782321664),  // UQXTNv2i32
7769
0
    UINT64_C(778127360),  // UQXTNv4i16
7770
0
    UINT64_C(1856063488), // UQXTNv4i32
7771
0
    UINT64_C(1851869184), // UQXTNv8i16
7772
0
    UINT64_C(773933056),  // UQXTNv8i8
7773
0
    UINT64_C(1149280256), // URECPE_ZPmZ_S
7774
0
    UINT64_C(245483520),  // URECPEv2i32
7775
0
    UINT64_C(1319225344), // URECPEv4i32
7776
0
    UINT64_C(1142259712), // URHADD_ZPmZ_B
7777
0
    UINT64_C(1154842624), // URHADD_ZPmZ_D
7778
0
    UINT64_C(1146454016), // URHADD_ZPmZ_H
7779
0
    UINT64_C(1150648320), // URHADD_ZPmZ_S
7780
0
    UINT64_C(1847596032), // URHADDv16i8
7781
0
    UINT64_C(782242816),  // URHADDv2i32
7782
0
    UINT64_C(778048512),  // URHADDv4i16
7783
0
    UINT64_C(1855984640), // URHADDv4i32
7784
0
    UINT64_C(1851790336), // URHADDv8i16
7785
0
    UINT64_C(773854208),  // URHADDv8i8
7786
0
    UINT64_C(1141342208), // URSHLR_ZPmZ_B
7787
0
    UINT64_C(1153925120), // URSHLR_ZPmZ_D
7788
0
    UINT64_C(1145536512), // URSHLR_ZPmZ_H
7789
0
    UINT64_C(1149730816), // URSHLR_ZPmZ_S
7790
0
    UINT64_C(3240145441), // URSHL_VG2_2Z2Z_B
7791
0
    UINT64_C(3252728353), // URSHL_VG2_2Z2Z_D
7792
0
    UINT64_C(3244339745), // URSHL_VG2_2Z2Z_H
7793
0
    UINT64_C(3248534049), // URSHL_VG2_2Z2Z_S
7794
0
    UINT64_C(3240141345), // URSHL_VG2_2ZZ_B
7795
0
    UINT64_C(3252724257), // URSHL_VG2_2ZZ_D
7796
0
    UINT64_C(3244335649), // URSHL_VG2_2ZZ_H
7797
0
    UINT64_C(3248529953), // URSHL_VG2_2ZZ_S
7798
0
    UINT64_C(3240147489), // URSHL_VG4_4Z4Z_B
7799
0
    UINT64_C(3252730401), // URSHL_VG4_4Z4Z_D
7800
0
    UINT64_C(3244341793), // URSHL_VG4_4Z4Z_H
7801
0
    UINT64_C(3248536097), // URSHL_VG4_4Z4Z_S
7802
0
    UINT64_C(3240143393), // URSHL_VG4_4ZZ_B
7803
0
    UINT64_C(3252726305), // URSHL_VG4_4ZZ_D
7804
0
    UINT64_C(3244337697), // URSHL_VG4_4ZZ_H
7805
0
    UINT64_C(3248532001), // URSHL_VG4_4ZZ_S
7806
0
    UINT64_C(1141080064), // URSHL_ZPmZ_B
7807
0
    UINT64_C(1153662976), // URSHL_ZPmZ_D
7808
0
    UINT64_C(1145274368), // URSHL_ZPmZ_H
7809
0
    UINT64_C(1149468672), // URSHL_ZPmZ_S
7810
0
    UINT64_C(1847612416), // URSHLv16i8
7811
0
    UINT64_C(2128630784), // URSHLv1i64
7812
0
    UINT64_C(782259200),  // URSHLv2i32
7813
0
    UINT64_C(1860195328), // URSHLv2i64
7814
0
    UINT64_C(778064896),  // URSHLv4i16
7815
0
    UINT64_C(1856001024), // URSHLv4i32
7816
0
    UINT64_C(1851806720), // URSHLv8i16
7817
0
    UINT64_C(773870592),  // URSHLv8i8
7818
0
    UINT64_C(67993856), // URSHR_ZPmI_B
7819
0
    UINT64_C(76382208), // URSHR_ZPmI_D
7820
0
    UINT64_C(67994112), // URSHR_ZPmI_H
7821
0
    UINT64_C(72187904), // URSHR_ZPmI_S
7822
0
    UINT64_C(2134909952), // URSHRd
7823
0
    UINT64_C(1862804480), // URSHRv16i8_shift
7824
0
    UINT64_C(790635520),  // URSHRv2i32_shift
7825
0
    UINT64_C(1866474496), // URSHRv2i64_shift
7826
0
    UINT64_C(789586944),  // URSHRv4i16_shift
7827
0
    UINT64_C(1864377344), // URSHRv4i32_shift
7828
0
    UINT64_C(1863328768), // URSHRv8i16_shift
7829
0
    UINT64_C(789062656),  // URSHRv8i8_shift
7830
0
    UINT64_C(1149345792), // URSQRTE_ZPmZ_S
7831
0
    UINT64_C(782354432),  // URSQRTEv2i32
7832
0
    UINT64_C(1856096256), // URSQRTEv4i32
7833
0
    UINT64_C(1158212608), // URSRA_ZZI_B
7834
0
    UINT64_C(1166076928), // URSRA_ZZI_D
7835
0
    UINT64_C(1158736896), // URSRA_ZZI_H
7836
0
    UINT64_C(1161882624), // URSRA_ZZI_S
7837
0
    UINT64_C(2134914048), // URSRAd
7838
0
    UINT64_C(1862808576), // URSRAv16i8_shift
7839
0
    UINT64_C(790639616),  // URSRAv2i32_shift
7840
0
    UINT64_C(1866478592), // URSRAv2i64_shift
7841
0
    UINT64_C(789591040),  // URSRAv4i16_shift
7842
0
    UINT64_C(1864381440), // URSRAv4i32_shift
7843
0
    UINT64_C(1863332864), // URSRAv8i16_shift
7844
0
    UINT64_C(789066752),  // URSRAv8i8_shift
7845
0
    UINT64_C(3248493576), // USDOT_VG2_M2Z2Z_BToS
7846
0
    UINT64_C(3243249704), // USDOT_VG2_M2ZZI_BToS
7847
0
    UINT64_C(3240104968), // USDOT_VG2_M2ZZ_BToS
7848
0
    UINT64_C(3248559112), // USDOT_VG4_M4Z4Z_BToS
7849
0
    UINT64_C(3243282472), // USDOT_VG4_M4ZZI_BToS
7850
0
    UINT64_C(3241153544), // USDOT_VG4_M4ZZ_BToS
7851
0
    UINT64_C(1149270016), // USDOT_ZZZ
7852
0
    UINT64_C(1151342592), // USDOT_ZZZI
7853
0
    UINT64_C(1333850112), // USDOTlanev16i8
7854
0
    UINT64_C(260108288),  // USDOTlanev8i8
7855
0
    UINT64_C(1317051392), // USDOTv16i8
7856
0
    UINT64_C(243309568),  // USDOTv8i8
7857
0
    UINT64_C(1161865216), // USHLLB_ZZI_D
7858
0
    UINT64_C(1158195200), // USHLLB_ZZI_H
7859
0
    UINT64_C(1158719488), // USHLLB_ZZI_S
7860
0
    UINT64_C(1161866240), // USHLLT_ZZI_D
7861
0
    UINT64_C(1158196224), // USHLLT_ZZI_H
7862
0
    UINT64_C(1158720512), // USHLLT_ZZI_S
7863
0
    UINT64_C(1862837248), // USHLLv16i8_shift
7864
0
    UINT64_C(790668288),  // USHLLv2i32_shift
7865
0
    UINT64_C(789619712),  // USHLLv4i16_shift
7866
0
    UINT64_C(1864410112), // USHLLv4i32_shift
7867
0
    UINT64_C(1863361536), // USHLLv8i16_shift
7868
0
    UINT64_C(789095424),  // USHLLv8i8_shift
7869
0
    UINT64_C(1847608320), // USHLv16i8
7870
0
    UINT64_C(2128626688), // USHLv1i64
7871
0
    UINT64_C(782255104),  // USHLv2i32
7872
0
    UINT64_C(1860191232), // USHLv2i64
7873
0
    UINT64_C(778060800),  // USHLv4i16
7874
0
    UINT64_C(1855996928), // USHLv4i32
7875
0
    UINT64_C(1851802624), // USHLv8i16
7876
0
    UINT64_C(773866496),  // USHLv8i8
7877
0
    UINT64_C(2134901760), // USHRd
7878
0
    UINT64_C(1862796288), // USHRv16i8_shift
7879
0
    UINT64_C(790627328),  // USHRv2i32_shift
7880
0
    UINT64_C(1866466304), // USHRv2i64_shift
7881
0
    UINT64_C(789578752),  // USHRv4i16_shift
7882
0
    UINT64_C(1864369152), // USHRv4i32_shift
7883
0
    UINT64_C(1863320576), // USHRv8i16_shift
7884
0
    UINT64_C(789054464),  // USHRv8i8_shift
7885
0
    UINT64_C(3238002692), // USMLALL_MZZI_BtoS
7886
0
    UINT64_C(3240100868), // USMLALL_MZZ_BtoS
7887
0
    UINT64_C(3248488452), // USMLALL_VG2_M2Z2Z_BtoS
7888
0
    UINT64_C(3239051296), // USMLALL_VG2_M2ZZI_BtoS
7889
0
    UINT64_C(3240099844), // USMLALL_VG2_M2ZZ_BtoS
7890
0
    UINT64_C(3248553988), // USMLALL_VG4_M4Z4Z_BtoS
7891
0
    UINT64_C(3239084064), // USMLALL_VG4_M4ZZI_BtoS
7892
0
    UINT64_C(3241148420), // USMLALL_VG4_M4ZZ_BtoS
7893
0
    UINT64_C(1317055488), // USMMLA
7894
0
    UINT64_C(1166055424), // USMMLA_ZZZ
7895
0
    UINT64_C(2713714688), // USMOPA_MPPZZ_D
7896
0
    UINT64_C(2709520384), // USMOPA_MPPZZ_S
7897
0
    UINT64_C(2713714704), // USMOPS_MPPZZ_D
7898
0
    UINT64_C(2709520400), // USMOPS_MPPZZ_S
7899
0
    UINT64_C(1142784000), // USQADD_ZPmZ_B
7900
0
    UINT64_C(1155366912), // USQADD_ZPmZ_D
7901
0
    UINT64_C(1146978304), // USQADD_ZPmZ_H
7902
0
    UINT64_C(1151172608), // USQADD_ZPmZ_S
7903
0
    UINT64_C(1847605248), // USQADDv16i8
7904
0
    UINT64_C(2120235008), // USQADDv1i16
7905
0
    UINT64_C(2124429312), // USQADDv1i32
7906
0
    UINT64_C(2128623616), // USQADDv1i64
7907
0
    UINT64_C(2116040704), // USQADDv1i8
7908
0
    UINT64_C(782252032),  // USQADDv2i32
7909
0
    UINT64_C(1860188160), // USQADDv2i64
7910
0
    UINT64_C(778057728),  // USQADDv4i16
7911
0
    UINT64_C(1855993856), // USQADDv4i32
7912
0
    UINT64_C(1851799552), // USQADDv8i16
7913
0
    UINT64_C(773863424),  // USQADDv8i8
7914
0
    UINT64_C(1158210560), // USRA_ZZI_B
7915
0
    UINT64_C(1166074880), // USRA_ZZI_D
7916
0
    UINT64_C(1158734848), // USRA_ZZI_H
7917
0
    UINT64_C(1161880576), // USRA_ZZI_S
7918
0
    UINT64_C(2134905856), // USRAd
7919
0
    UINT64_C(1862800384), // USRAv16i8_shift
7920
0
    UINT64_C(790631424),  // USRAv2i32_shift
7921
0
    UINT64_C(1866470400), // USRAv2i64_shift
7922
0
    UINT64_C(789582848),  // USRAv4i16_shift
7923
0
    UINT64_C(1864373248), // USRAv4i32_shift
7924
0
    UINT64_C(1863324672), // USRAv8i16_shift
7925
0
    UINT64_C(789058560),  // USRAv8i8_shift
7926
0
    UINT64_C(1170216960), // USUBLB_ZZZ_D
7927
0
    UINT64_C(1161828352), // USUBLB_ZZZ_H
7928
0
    UINT64_C(1166022656), // USUBLB_ZZZ_S
7929
0
    UINT64_C(1170217984), // USUBLT_ZZZ_D
7930
0
    UINT64_C(1161829376), // USUBLT_ZZZ_H
7931
0
    UINT64_C(1166023680), // USUBLT_ZZZ_S
7932
0
    UINT64_C(1847599104), // USUBLv16i8_v8i16
7933
0
    UINT64_C(782245888),  // USUBLv2i32_v2i64
7934
0
    UINT64_C(778051584),  // USUBLv4i16_v4i32
7935
0
    UINT64_C(1855987712), // USUBLv4i32_v2i64
7936
0
    UINT64_C(1851793408), // USUBLv8i16_v4i32
7937
0
    UINT64_C(773857280),  // USUBLv8i8_v8i16
7938
0
    UINT64_C(1170233344), // USUBWB_ZZZ_D
7939
0
    UINT64_C(1161844736), // USUBWB_ZZZ_H
7940
0
    UINT64_C(1166039040), // USUBWB_ZZZ_S
7941
0
    UINT64_C(1170234368), // USUBWT_ZZZ_D
7942
0
    UINT64_C(1161845760), // USUBWT_ZZZ_H
7943
0
    UINT64_C(1166040064), // USUBWT_ZZZ_S
7944
0
    UINT64_C(1847603200), // USUBWv16i8_v8i16
7945
0
    UINT64_C(782249984),  // USUBWv2i32_v2i64
7946
0
    UINT64_C(778055680),  // USUBWv4i16_v4i32
7947
0
    UINT64_C(1855991808), // USUBWv4i32_v2i64
7948
0
    UINT64_C(1851797504), // USUBWv8i16_v4i32
7949
0
    UINT64_C(773861376),  // USUBWv8i8_v8i16
7950
0
    UINT64_C(3243278376), // USVDOT_VG4_M4ZZI_BToS
7951
0
    UINT64_C(99825664), // UUNPKHI_ZZ_D
7952
0
    UINT64_C(91437056), // UUNPKHI_ZZ_H
7953
0
    UINT64_C(95631360), // UUNPKHI_ZZ_S
7954
0
    UINT64_C(99760128), // UUNPKLO_ZZ_D
7955
0
    UINT64_C(91371520), // UUNPKLO_ZZ_H
7956
0
    UINT64_C(95565824), // UUNPKLO_ZZ_S
7957
0
    UINT64_C(3253067777), // UUNPK_VG2_2ZZ_D
7958
0
    UINT64_C(3244679169), // UUNPK_VG2_2ZZ_H
7959
0
    UINT64_C(3248873473), // UUNPK_VG2_2ZZ_S
7960
0
    UINT64_C(3254116353), // UUNPK_VG4_4Z2Z_D
7961
0
    UINT64_C(3245727745), // UUNPK_VG4_4Z2Z_H
7962
0
    UINT64_C(3249922049), // UUNPK_VG4_4Z2Z_S
7963
0
    UINT64_C(3243245616), // UVDOT_VG2_M2ZZI_HtoS
7964
0
    UINT64_C(3243278384), // UVDOT_VG4_M4ZZI_BtoS
7965
0
    UINT64_C(3251669016), // UVDOT_VG4_M4ZZI_HtoD
7966
0
    UINT64_C(80846848), // UXTB_ZPmZ_D
7967
0
    UINT64_C(72458240), // UXTB_ZPmZ_H
7968
0
    UINT64_C(76652544), // UXTB_ZPmZ_S
7969
0
    UINT64_C(80977920), // UXTH_ZPmZ_D
7970
0
    UINT64_C(76783616), // UXTH_ZPmZ_S
7971
0
    UINT64_C(81108992), // UXTW_ZPmZ_D
7972
0
    UINT64_C(86001664), // UZP1_PPP_B
7973
0
    UINT64_C(98584576), // UZP1_PPP_D
7974
0
    UINT64_C(90195968), // UZP1_PPP_H
7975
0
    UINT64_C(94390272), // UZP1_PPP_S
7976
0
    UINT64_C(86009856), // UZP1_ZZZ_B
7977
0
    UINT64_C(98592768), // UZP1_ZZZ_D
7978
0
    UINT64_C(90204160), // UZP1_ZZZ_H
7979
0
    UINT64_C(94373888), // UZP1_ZZZ_Q
7980
0
    UINT64_C(94398464), // UZP1_ZZZ_S
7981
0
    UINT64_C(1308628992), // UZP1v16i8
7982
0
    UINT64_C(243275776),  // UZP1v2i32
7983
0
    UINT64_C(1321211904), // UZP1v2i64
7984
0
    UINT64_C(239081472),  // UZP1v4i16
7985
0
    UINT64_C(1317017600), // UZP1v4i32
7986
0
    UINT64_C(1312823296), // UZP1v8i16
7987
0
    UINT64_C(234887168),  // UZP1v8i8
7988
0
    UINT64_C(86002688), // UZP2_PPP_B
7989
0
    UINT64_C(98585600), // UZP2_PPP_D
7990
0
    UINT64_C(90196992), // UZP2_PPP_H
7991
0
    UINT64_C(94391296), // UZP2_PPP_S
7992
0
    UINT64_C(86010880), // UZP2_ZZZ_B
7993
0
    UINT64_C(98593792), // UZP2_ZZZ_D
7994
0
    UINT64_C(90205184), // UZP2_ZZZ_H
7995
0
    UINT64_C(94374912), // UZP2_ZZZ_Q
7996
0
    UINT64_C(94399488), // UZP2_ZZZ_S
7997
0
    UINT64_C(1308645376), // UZP2v16i8
7998
0
    UINT64_C(243292160),  // UZP2v2i32
7999
0
    UINT64_C(1321228288), // UZP2v2i64
8000
0
    UINT64_C(239097856),  // UZP2v4i16
8001
0
    UINT64_C(1317033984), // UZP2v4i32
8002
0
    UINT64_C(1312839680), // UZP2v8i16
8003
0
    UINT64_C(234903552),  // UZP2v8i8
8004
0
    UINT64_C(1140910080), // UZPQ1_ZZZ_B
8005
0
    UINT64_C(1153492992), // UZPQ1_ZZZ_D
8006
0
    UINT64_C(1145104384), // UZPQ1_ZZZ_H
8007
0
    UINT64_C(1149298688), // UZPQ1_ZZZ_S
8008
0
    UINT64_C(1140911104), // UZPQ2_ZZZ_B
8009
0
    UINT64_C(1153494016), // UZPQ2_ZZZ_D
8010
0
    UINT64_C(1145105408), // UZPQ2_ZZZ_H
8011
0
    UINT64_C(1149299712), // UZPQ2_ZZZ_S
8012
0
    UINT64_C(3240153089), // UZP_VG2_2ZZZ_B
8013
0
    UINT64_C(3252736001), // UZP_VG2_2ZZZ_D
8014
0
    UINT64_C(3244347393), // UZP_VG2_2ZZZ_H
8015
0
    UINT64_C(3240154113), // UZP_VG2_2ZZZ_Q
8016
0
    UINT64_C(3248541697), // UZP_VG2_2ZZZ_S
8017
0
    UINT64_C(3241598978), // UZP_VG4_4Z4Z_B
8018
0
    UINT64_C(3254181890), // UZP_VG4_4Z4Z_D
8019
0
    UINT64_C(3245793282), // UZP_VG4_4Z4Z_H
8020
0
    UINT64_C(3241664514), // UZP_VG4_4Z4Z_Q
8021
0
    UINT64_C(3249987586), // UZP_VG4_4Z4Z_S
8022
0
    UINT64_C(3573747712), // WFET
8023
0
    UINT64_C(3573747744), // WFIT
8024
0
    UINT64_C(622874640),  // WHILEGE_2PXX_B
8025
0
    UINT64_C(635457552),  // WHILEGE_2PXX_D
8026
0
    UINT64_C(627068944),  // WHILEGE_2PXX_H
8027
0
    UINT64_C(631263248),  // WHILEGE_2PXX_S
8028
0
    UINT64_C(622870544),  // WHILEGE_CXX_B
8029
0
    UINT64_C(635453456),  // WHILEGE_CXX_D
8030
0
    UINT64_C(627064848),  // WHILEGE_CXX_H
8031
0
    UINT64_C(631259152),  // WHILEGE_CXX_S
8032
0
    UINT64_C(622854144),  // WHILEGE_PWW_B
8033
0
    UINT64_C(635437056),  // WHILEGE_PWW_D
8034
0
    UINT64_C(627048448),  // WHILEGE_PWW_H
8035
0
    UINT64_C(631242752),  // WHILEGE_PWW_S
8036
0
    UINT64_C(622858240),  // WHILEGE_PXX_B
8037
0
    UINT64_C(635441152),  // WHILEGE_PXX_D
8038
0
    UINT64_C(627052544),  // WHILEGE_PXX_H
8039
0
    UINT64_C(631246848),  // WHILEGE_PXX_S
8040
0
    UINT64_C(622874641),  // WHILEGT_2PXX_B
8041
0
    UINT64_C(635457553),  // WHILEGT_2PXX_D
8042
0
    UINT64_C(627068945),  // WHILEGT_2PXX_H
8043
0
    UINT64_C(631263249),  // WHILEGT_2PXX_S
8044
0
    UINT64_C(622870552),  // WHILEGT_CXX_B
8045
0
    UINT64_C(635453464),  // WHILEGT_CXX_D
8046
0
    UINT64_C(627064856),  // WHILEGT_CXX_H
8047
0
    UINT64_C(631259160),  // WHILEGT_CXX_S
8048
0
    UINT64_C(622854160),  // WHILEGT_PWW_B
8049
0
    UINT64_C(635437072),  // WHILEGT_PWW_D
8050
0
    UINT64_C(627048464),  // WHILEGT_PWW_H
8051
0
    UINT64_C(631242768),  // WHILEGT_PWW_S
8052
0
    UINT64_C(622858256),  // WHILEGT_PXX_B
8053
0
    UINT64_C(635441168),  // WHILEGT_PXX_D
8054
0
    UINT64_C(627052560),  // WHILEGT_PXX_H
8055
0
    UINT64_C(631246864),  // WHILEGT_PXX_S
8056
0
    UINT64_C(622876689),  // WHILEHI_2PXX_B
8057
0
    UINT64_C(635459601),  // WHILEHI_2PXX_D
8058
0
    UINT64_C(627070993),  // WHILEHI_2PXX_H
8059
0
    UINT64_C(631265297),  // WHILEHI_2PXX_S
8060
0
    UINT64_C(622872600),  // WHILEHI_CXX_B
8061
0
    UINT64_C(635455512),  // WHILEHI_CXX_D
8062
0
    UINT64_C(627066904),  // WHILEHI_CXX_H
8063
0
    UINT64_C(631261208),  // WHILEHI_CXX_S
8064
0
    UINT64_C(622856208),  // WHILEHI_PWW_B
8065
0
    UINT64_C(635439120),  // WHILEHI_PWW_D
8066
0
    UINT64_C(627050512),  // WHILEHI_PWW_H
8067
0
    UINT64_C(631244816),  // WHILEHI_PWW_S
8068
0
    UINT64_C(622860304),  // WHILEHI_PXX_B
8069
0
    UINT64_C(635443216),  // WHILEHI_PXX_D
8070
0
    UINT64_C(627054608),  // WHILEHI_PXX_H
8071
0
    UINT64_C(631248912),  // WHILEHI_PXX_S
8072
0
    UINT64_C(622876688),  // WHILEHS_2PXX_B
8073
0
    UINT64_C(635459600),  // WHILEHS_2PXX_D
8074
0
    UINT64_C(627070992),  // WHILEHS_2PXX_H
8075
0
    UINT64_C(631265296),  // WHILEHS_2PXX_S
8076
0
    UINT64_C(622872592),  // WHILEHS_CXX_B
8077
0
    UINT64_C(635455504),  // WHILEHS_CXX_D
8078
0
    UINT64_C(627066896),  // WHILEHS_CXX_H
8079
0
    UINT64_C(631261200),  // WHILEHS_CXX_S
8080
0
    UINT64_C(622856192),  // WHILEHS_PWW_B
8081
0
    UINT64_C(635439104),  // WHILEHS_PWW_D
8082
0
    UINT64_C(627050496),  // WHILEHS_PWW_H
8083
0
    UINT64_C(631244800),  // WHILEHS_PWW_S
8084
0
    UINT64_C(622860288),  // WHILEHS_PXX_B
8085
0
    UINT64_C(635443200),  // WHILEHS_PXX_D
8086
0
    UINT64_C(627054592),  // WHILEHS_PXX_H
8087
0
    UINT64_C(631248896),  // WHILEHS_PXX_S
8088
0
    UINT64_C(622875665),  // WHILELE_2PXX_B
8089
0
    UINT64_C(635458577),  // WHILELE_2PXX_D
8090
0
    UINT64_C(627069969),  // WHILELE_2PXX_H
8091
0
    UINT64_C(631264273),  // WHILELE_2PXX_S
8092
0
    UINT64_C(622871576),  // WHILELE_CXX_B
8093
0
    UINT64_C(635454488),  // WHILELE_CXX_D
8094
0
    UINT64_C(627065880),  // WHILELE_CXX_H
8095
0
    UINT64_C(631260184),  // WHILELE_CXX_S
8096
0
    UINT64_C(622855184),  // WHILELE_PWW_B
8097
0
    UINT64_C(635438096),  // WHILELE_PWW_D
8098
0
    UINT64_C(627049488),  // WHILELE_PWW_H
8099
0
    UINT64_C(631243792),  // WHILELE_PWW_S
8100
0
    UINT64_C(622859280),  // WHILELE_PXX_B
8101
0
    UINT64_C(635442192),  // WHILELE_PXX_D
8102
0
    UINT64_C(627053584),  // WHILELE_PXX_H
8103
0
    UINT64_C(631247888),  // WHILELE_PXX_S
8104
0
    UINT64_C(622877712),  // WHILELO_2PXX_B
8105
0
    UINT64_C(635460624),  // WHILELO_2PXX_D
8106
0
    UINT64_C(627072016),  // WHILELO_2PXX_H
8107
0
    UINT64_C(631266320),  // WHILELO_2PXX_S
8108
0
    UINT64_C(622873616),  // WHILELO_CXX_B
8109
0
    UINT64_C(635456528),  // WHILELO_CXX_D
8110
0
    UINT64_C(627067920),  // WHILELO_CXX_H
8111
0
    UINT64_C(631262224),  // WHILELO_CXX_S
8112
0
    UINT64_C(622857216),  // WHILELO_PWW_B
8113
0
    UINT64_C(635440128),  // WHILELO_PWW_D
8114
0
    UINT64_C(627051520),  // WHILELO_PWW_H
8115
0
    UINT64_C(631245824),  // WHILELO_PWW_S
8116
0
    UINT64_C(622861312),  // WHILELO_PXX_B
8117
0
    UINT64_C(635444224),  // WHILELO_PXX_D
8118
0
    UINT64_C(627055616),  // WHILELO_PXX_H
8119
0
    UINT64_C(631249920),  // WHILELO_PXX_S
8120
0
    UINT64_C(622877713),  // WHILELS_2PXX_B
8121
0
    UINT64_C(635460625),  // WHILELS_2PXX_D
8122
0
    UINT64_C(627072017),  // WHILELS_2PXX_H
8123
0
    UINT64_C(631266321),  // WHILELS_2PXX_S
8124
0
    UINT64_C(622873624),  // WHILELS_CXX_B
8125
0
    UINT64_C(635456536),  // WHILELS_CXX_D
8126
0
    UINT64_C(627067928),  // WHILELS_CXX_H
8127
0
    UINT64_C(631262232),  // WHILELS_CXX_S
8128
0
    UINT64_C(622857232),  // WHILELS_PWW_B
8129
0
    UINT64_C(635440144),  // WHILELS_PWW_D
8130
0
    UINT64_C(627051536),  // WHILELS_PWW_H
8131
0
    UINT64_C(631245840),  // WHILELS_PWW_S
8132
0
    UINT64_C(622861328),  // WHILELS_PXX_B
8133
0
    UINT64_C(635444240),  // WHILELS_PXX_D
8134
0
    UINT64_C(627055632),  // WHILELS_PXX_H
8135
0
    UINT64_C(631249936),  // WHILELS_PXX_S
8136
0
    UINT64_C(622875664),  // WHILELT_2PXX_B
8137
0
    UINT64_C(635458576),  // WHILELT_2PXX_D
8138
0
    UINT64_C(627069968),  // WHILELT_2PXX_H
8139
0
    UINT64_C(631264272),  // WHILELT_2PXX_S
8140
0
    UINT64_C(622871568),  // WHILELT_CXX_B
8141
0
    UINT64_C(635454480),  // WHILELT_CXX_D
8142
0
    UINT64_C(627065872),  // WHILELT_CXX_H
8143
0
    UINT64_C(631260176),  // WHILELT_CXX_S
8144
0
    UINT64_C(622855168),  // WHILELT_PWW_B
8145
0
    UINT64_C(635438080),  // WHILELT_PWW_D
8146
0
    UINT64_C(627049472),  // WHILELT_PWW_H
8147
0
    UINT64_C(631243776),  // WHILELT_PWW_S
8148
0
    UINT64_C(622859264),  // WHILELT_PXX_B
8149
0
    UINT64_C(635442176),  // WHILELT_PXX_D
8150
0
    UINT64_C(627053568),  // WHILELT_PXX_H
8151
0
    UINT64_C(631247872),  // WHILELT_PXX_S
8152
0
    UINT64_C(622866448),  // WHILERW_PXX_B
8153
0
    UINT64_C(635449360),  // WHILERW_PXX_D
8154
0
    UINT64_C(627060752),  // WHILERW_PXX_H
8155
0
    UINT64_C(631255056),  // WHILERW_PXX_S
8156
0
    UINT64_C(622866432),  // WHILEWR_PXX_B
8157
0
    UINT64_C(635449344),  // WHILEWR_PXX_D
8158
0
    UINT64_C(627060736),  // WHILEWR_PXX_H
8159
0
    UINT64_C(631255040),  // WHILEWR_PXX_S
8160
0
    UINT64_C(623415296),  // WRFFR
8161
0
    UINT64_C(3573563455), // XAFLAG
8162
0
    UINT64_C(3464495104), // XAR
8163
0
    UINT64_C(69743616), // XAR_ZZZI_B
8164
0
    UINT64_C(77607936), // XAR_ZZZI_D
8165
0
    UINT64_C(70267904), // XAR_ZZZI_H
8166
0
    UINT64_C(73413632), // XAR_ZZZI_S
8167
0
    UINT64_C(3670099936), // XPACD
8168
0
    UINT64_C(3670098912), // XPACI
8169
0
    UINT64_C(3573752063), // XPACLRI
8170
0
    UINT64_C(1310795776), // XTNv16i8
8171
0
    UINT64_C(245442560),  // XTNv2i32
8172
0
    UINT64_C(241248256),  // XTNv4i16
8173
0
    UINT64_C(1319184384), // XTNv4i32
8174
0
    UINT64_C(1314990080), // XTNv8i16
8175
0
    UINT64_C(237053952),  // XTNv8i8
8176
0
    UINT64_C(3221749760), // ZERO_M
8177
0
    UINT64_C(3222044672), // ZERO_MXI_2Z
8178
0
    UINT64_C(3222175744), // ZERO_MXI_4Z
8179
0
    UINT64_C(3222077440), // ZERO_MXI_VG2_2Z
8180
0
    UINT64_C(3222208512), // ZERO_MXI_VG2_4Z
8181
0
    UINT64_C(3222011904), // ZERO_MXI_VG2_Z
8182
0
    UINT64_C(3222110208), // ZERO_MXI_VG4_2Z
8183
0
    UINT64_C(3222241280), // ZERO_MXI_VG4_4Z
8184
0
    UINT64_C(3222142976), // ZERO_MXI_VG4_Z
8185
0
    UINT64_C(3225944065), // ZERO_T
8186
0
    UINT64_C(85999616), // ZIP1_PPP_B
8187
0
    UINT64_C(98582528), // ZIP1_PPP_D
8188
0
    UINT64_C(90193920), // ZIP1_PPP_H
8189
0
    UINT64_C(94388224), // ZIP1_PPP_S
8190
0
    UINT64_C(86007808), // ZIP1_ZZZ_B
8191
0
    UINT64_C(98590720), // ZIP1_ZZZ_D
8192
0
    UINT64_C(90202112), // ZIP1_ZZZ_H
8193
0
    UINT64_C(94371840), // ZIP1_ZZZ_Q
8194
0
    UINT64_C(94396416), // ZIP1_ZZZ_S
8195
0
    UINT64_C(1308637184), // ZIP1v16i8
8196
0
    UINT64_C(243283968),  // ZIP1v2i32
8197
0
    UINT64_C(1321220096), // ZIP1v2i64
8198
0
    UINT64_C(239089664),  // ZIP1v4i16
8199
0
    UINT64_C(1317025792), // ZIP1v4i32
8200
0
    UINT64_C(1312831488), // ZIP1v8i16
8201
0
    UINT64_C(234895360),  // ZIP1v8i8
8202
0
    UINT64_C(86000640), // ZIP2_PPP_B
8203
0
    UINT64_C(98583552), // ZIP2_PPP_D
8204
0
    UINT64_C(90194944), // ZIP2_PPP_H
8205
0
    UINT64_C(94389248), // ZIP2_PPP_S
8206
0
    UINT64_C(86008832), // ZIP2_ZZZ_B
8207
0
    UINT64_C(98591744), // ZIP2_ZZZ_D
8208
0
    UINT64_C(90203136), // ZIP2_ZZZ_H
8209
0
    UINT64_C(94372864), // ZIP2_ZZZ_Q
8210
0
    UINT64_C(94397440), // ZIP2_ZZZ_S
8211
0
    UINT64_C(1308653568), // ZIP2v16i8
8212
0
    UINT64_C(243300352),  // ZIP2v2i32
8213
0
    UINT64_C(1321236480), // ZIP2v2i64
8214
0
    UINT64_C(239106048),  // ZIP2v4i16
8215
0
    UINT64_C(1317042176), // ZIP2v4i32
8216
0
    UINT64_C(1312847872), // ZIP2v8i16
8217
0
    UINT64_C(234911744),  // ZIP2v8i8
8218
0
    UINT64_C(1140908032), // ZIPQ1_ZZZ_B
8219
0
    UINT64_C(1153490944), // ZIPQ1_ZZZ_D
8220
0
    UINT64_C(1145102336), // ZIPQ1_ZZZ_H
8221
0
    UINT64_C(1149296640), // ZIPQ1_ZZZ_S
8222
0
    UINT64_C(1140909056), // ZIPQ2_ZZZ_B
8223
0
    UINT64_C(1153491968), // ZIPQ2_ZZZ_D
8224
0
    UINT64_C(1145103360), // ZIPQ2_ZZZ_H
8225
0
    UINT64_C(1149297664), // ZIPQ2_ZZZ_S
8226
0
    UINT64_C(3240153088), // ZIP_VG2_2ZZZ_B
8227
0
    UINT64_C(3252736000), // ZIP_VG2_2ZZZ_D
8228
0
    UINT64_C(3244347392), // ZIP_VG2_2ZZZ_H
8229
0
    UINT64_C(3240154112), // ZIP_VG2_2ZZZ_Q
8230
0
    UINT64_C(3248541696), // ZIP_VG2_2ZZZ_S
8231
0
    UINT64_C(3241598976), // ZIP_VG4_4Z4Z_B
8232
0
    UINT64_C(3254181888), // ZIP_VG4_4Z4Z_D
8233
0
    UINT64_C(3245793280), // ZIP_VG4_4Z4Z_H
8234
0
    UINT64_C(3241664512), // ZIP_VG4_4Z4Z_Q
8235
0
    UINT64_C(3249987584), // ZIP_VG4_4Z4Z_S
8236
0
    UINT64_C(0)
8237
0
  };
8238
0
  const unsigned opcode = MI.getOpcode();
8239
0
  uint64_t Value = InstBits[opcode];
8240
0
  uint64_t op = 0;
8241
0
  (void)op;  // suppress warning
8242
0
  switch (opcode) {
8243
0
    case AArch64::AUTIA1716:
8244
0
    case AArch64::AUTIA171615:
8245
0
    case AArch64::AUTIASP:
8246
0
    case AArch64::AUTIAZ:
8247
0
    case AArch64::AUTIB1716:
8248
0
    case AArch64::AUTIB171615:
8249
0
    case AArch64::AUTIBSP:
8250
0
    case AArch64::AUTIBZ:
8251
0
    case AArch64::AXFLAG:
8252
0
    case AArch64::BRB_IALL:
8253
0
    case AArch64::BRB_INJ:
8254
0
    case AArch64::CFINV:
8255
0
    case AArch64::CHKFEAT:
8256
0
    case AArch64::DRPS:
8257
0
    case AArch64::ERET:
8258
0
    case AArch64::ERETAA:
8259
0
    case AArch64::ERETAB:
8260
0
    case AArch64::GCSPOPCX:
8261
0
    case AArch64::GCSPOPX:
8262
0
    case AArch64::GCSPUSHX:
8263
0
    case AArch64::PACIA1716:
8264
0
    case AArch64::PACIA171615:
8265
0
    case AArch64::PACIASP:
8266
0
    case AArch64::PACIASPPC:
8267
0
    case AArch64::PACIAZ:
8268
0
    case AArch64::PACIB1716:
8269
0
    case AArch64::PACIB171615:
8270
0
    case AArch64::PACIBSP:
8271
0
    case AArch64::PACIBSPPC:
8272
0
    case AArch64::PACIBZ:
8273
0
    case AArch64::PACM:
8274
0
    case AArch64::PACNBIASPPC:
8275
0
    case AArch64::PACNBIBSPPC:
8276
0
    case AArch64::RETAA:
8277
0
    case AArch64::RETAB:
8278
0
    case AArch64::SB:
8279
0
    case AArch64::SETFFR:
8280
0
    case AArch64::TCOMMIT:
8281
0
    case AArch64::TSB:
8282
0
    case AArch64::XAFLAG:
8283
0
    case AArch64::XPACLRI:
8284
0
    case AArch64::ZERO_T: {
8285
0
      break;
8286
0
    }
8287
0
    case AArch64::DSBnXS: {
8288
      // op: CRm
8289
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8290
0
      op &= UINT64_C(12);
8291
0
      op <<= 8;
8292
0
      Value |= op;
8293
0
      break;
8294
0
    }
8295
0
    case AArch64::CLREX:
8296
0
    case AArch64::DMB:
8297
0
    case AArch64::DSB:
8298
0
    case AArch64::ISB: {
8299
      // op: CRm
8300
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8301
0
      op &= UINT64_C(15);
8302
0
      op <<= 8;
8303
0
      Value |= op;
8304
0
      break;
8305
0
    }
8306
0
    case AArch64::PTRUE_C_B:
8307
0
    case AArch64::PTRUE_C_D:
8308
0
    case AArch64::PTRUE_C_H:
8309
0
    case AArch64::PTRUE_C_S: {
8310
      // op: PNd
8311
0
      op = EncodePNR_p8to15(MI, 0, Fixups, STI);
8312
0
      op &= UINT64_C(7);
8313
0
      Value |= op;
8314
0
      break;
8315
0
    }
8316
0
    case AArch64::WHILEGE_CXX_B:
8317
0
    case AArch64::WHILEGE_CXX_D:
8318
0
    case AArch64::WHILEGE_CXX_H:
8319
0
    case AArch64::WHILEGE_CXX_S:
8320
0
    case AArch64::WHILEGT_CXX_B:
8321
0
    case AArch64::WHILEGT_CXX_D:
8322
0
    case AArch64::WHILEGT_CXX_H:
8323
0
    case AArch64::WHILEGT_CXX_S:
8324
0
    case AArch64::WHILEHI_CXX_B:
8325
0
    case AArch64::WHILEHI_CXX_D:
8326
0
    case AArch64::WHILEHI_CXX_H:
8327
0
    case AArch64::WHILEHI_CXX_S:
8328
0
    case AArch64::WHILEHS_CXX_B:
8329
0
    case AArch64::WHILEHS_CXX_D:
8330
0
    case AArch64::WHILEHS_CXX_H:
8331
0
    case AArch64::WHILEHS_CXX_S:
8332
0
    case AArch64::WHILELE_CXX_B:
8333
0
    case AArch64::WHILELE_CXX_D:
8334
0
    case AArch64::WHILELE_CXX_H:
8335
0
    case AArch64::WHILELE_CXX_S:
8336
0
    case AArch64::WHILELO_CXX_B:
8337
0
    case AArch64::WHILELO_CXX_D:
8338
0
    case AArch64::WHILELO_CXX_H:
8339
0
    case AArch64::WHILELO_CXX_S:
8340
0
    case AArch64::WHILELS_CXX_B:
8341
0
    case AArch64::WHILELS_CXX_D:
8342
0
    case AArch64::WHILELS_CXX_H:
8343
0
    case AArch64::WHILELS_CXX_S:
8344
0
    case AArch64::WHILELT_CXX_B:
8345
0
    case AArch64::WHILELT_CXX_D:
8346
0
    case AArch64::WHILELT_CXX_H:
8347
0
    case AArch64::WHILELT_CXX_S: {
8348
      // op: PNd
8349
0
      op = EncodePNR_p8to15(MI, 0, Fixups, STI);
8350
0
      op &= UINT64_C(7);
8351
0
      Value |= op;
8352
      // op: Rn
8353
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8354
0
      op &= UINT64_C(31);
8355
0
      op <<= 5;
8356
0
      Value |= op;
8357
      // op: vl
8358
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8359
0
      op &= UINT64_C(1);
8360
0
      op <<= 13;
8361
0
      Value |= op;
8362
      // op: Rm
8363
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8364
0
      op &= UINT64_C(31);
8365
0
      op <<= 16;
8366
0
      Value |= op;
8367
0
      break;
8368
0
    }
8369
0
    case AArch64::SEL_VG2_2ZC2Z2Z_B:
8370
0
    case AArch64::SEL_VG2_2ZC2Z2Z_D:
8371
0
    case AArch64::SEL_VG2_2ZC2Z2Z_H:
8372
0
    case AArch64::SEL_VG2_2ZC2Z2Z_S: {
8373
      // op: PNg
8374
0
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
8375
0
      op &= UINT64_C(7);
8376
0
      op <<= 10;
8377
0
      Value |= op;
8378
      // op: Zm
8379
0
      op = EncodeRegAsMultipleOf<2>(MI, 3, Fixups, STI);
8380
0
      op &= UINT64_C(15);
8381
0
      op <<= 17;
8382
0
      Value |= op;
8383
      // op: Zn
8384
0
      op = EncodeRegAsMultipleOf<2>(MI, 2, Fixups, STI);
8385
0
      op &= UINT64_C(15);
8386
0
      op <<= 6;
8387
0
      Value |= op;
8388
      // op: Zd
8389
0
      op = EncodeRegAsMultipleOf<2>(MI, 0, Fixups, STI);
8390
0
      op &= UINT64_C(15);
8391
0
      op <<= 1;
8392
0
      Value |= op;
8393
0
      break;
8394
0
    }
8395
0
    case AArch64::SEL_VG4_4ZC4Z4Z_B:
8396
0
    case AArch64::SEL_VG4_4ZC4Z4Z_D:
8397
0
    case AArch64::SEL_VG4_4ZC4Z4Z_H:
8398
0
    case AArch64::SEL_VG4_4ZC4Z4Z_S: {
8399
      // op: PNg
8400
0
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
8401
0
      op &= UINT64_C(7);
8402
0
      op <<= 10;
8403
0
      Value |= op;
8404
      // op: Zm
8405
0
      op = EncodeRegAsMultipleOf<4>(MI, 3, Fixups, STI);
8406
0
      op &= UINT64_C(7);
8407
0
      op <<= 18;
8408
0
      Value |= op;
8409
      // op: Zn
8410
0
      op = EncodeRegAsMultipleOf<4>(MI, 2, Fixups, STI);
8411
0
      op &= UINT64_C(7);
8412
0
      op <<= 7;
8413
0
      Value |= op;
8414
      // op: Zd
8415
0
      op = EncodeRegAsMultipleOf<4>(MI, 0, Fixups, STI);
8416
0
      op &= UINT64_C(7);
8417
0
      op <<= 2;
8418
0
      Value |= op;
8419
0
      break;
8420
0
    }
8421
0
    case AArch64::WHILEGE_2PXX_B:
8422
0
    case AArch64::WHILEGE_2PXX_D:
8423
0
    case AArch64::WHILEGE_2PXX_H:
8424
0
    case AArch64::WHILEGE_2PXX_S:
8425
0
    case AArch64::WHILEGT_2PXX_B:
8426
0
    case AArch64::WHILEGT_2PXX_D:
8427
0
    case AArch64::WHILEGT_2PXX_H:
8428
0
    case AArch64::WHILEGT_2PXX_S:
8429
0
    case AArch64::WHILEHI_2PXX_B:
8430
0
    case AArch64::WHILEHI_2PXX_D:
8431
0
    case AArch64::WHILEHI_2PXX_H:
8432
0
    case AArch64::WHILEHI_2PXX_S:
8433
0
    case AArch64::WHILEHS_2PXX_B:
8434
0
    case AArch64::WHILEHS_2PXX_D:
8435
0
    case AArch64::WHILEHS_2PXX_H:
8436
0
    case AArch64::WHILEHS_2PXX_S:
8437
0
    case AArch64::WHILELE_2PXX_B:
8438
0
    case AArch64::WHILELE_2PXX_D:
8439
0
    case AArch64::WHILELE_2PXX_H:
8440
0
    case AArch64::WHILELE_2PXX_S:
8441
0
    case AArch64::WHILELO_2PXX_B:
8442
0
    case AArch64::WHILELO_2PXX_D:
8443
0
    case AArch64::WHILELO_2PXX_H:
8444
0
    case AArch64::WHILELO_2PXX_S:
8445
0
    case AArch64::WHILELS_2PXX_B:
8446
0
    case AArch64::WHILELS_2PXX_D:
8447
0
    case AArch64::WHILELS_2PXX_H:
8448
0
    case AArch64::WHILELS_2PXX_S:
8449
0
    case AArch64::WHILELT_2PXX_B:
8450
0
    case AArch64::WHILELT_2PXX_D:
8451
0
    case AArch64::WHILELT_2PXX_H:
8452
0
    case AArch64::WHILELT_2PXX_S: {
8453
      // op: Pd
8454
0
      op = EncodeRegAsMultipleOf<2>(MI, 0, Fixups, STI);
8455
0
      op &= UINT64_C(7);
8456
0
      op <<= 1;
8457
0
      Value |= op;
8458
      // op: Rn
8459
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8460
0
      op &= UINT64_C(31);
8461
0
      op <<= 5;
8462
0
      Value |= op;
8463
      // op: Rm
8464
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8465
0
      op &= UINT64_C(31);
8466
0
      op <<= 16;
8467
0
      Value |= op;
8468
0
      break;
8469
0
    }
8470
0
    case AArch64::PFALSE:
8471
0
    case AArch64::RDFFR_P_REAL: {
8472
      // op: Pd
8473
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8474
0
      op &= UINT64_C(15);
8475
0
      Value |= op;
8476
0
      break;
8477
0
    }
8478
0
    case AArch64::PEXT_2PCI_B:
8479
0
    case AArch64::PEXT_2PCI_D:
8480
0
    case AArch64::PEXT_2PCI_H:
8481
0
    case AArch64::PEXT_2PCI_S: {
8482
      // op: Pd
8483
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8484
0
      op &= UINT64_C(15);
8485
0
      Value |= op;
8486
      // op: PNn
8487
0
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
8488
0
      op &= UINT64_C(7);
8489
0
      op <<= 5;
8490
0
      Value |= op;
8491
      // op: index
8492
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8493
0
      op &= UINT64_C(1);
8494
0
      op <<= 8;
8495
0
      Value |= op;
8496
0
      break;
8497
0
    }
8498
0
    case AArch64::PEXT_PCI_B:
8499
0
    case AArch64::PEXT_PCI_D:
8500
0
    case AArch64::PEXT_PCI_H:
8501
0
    case AArch64::PEXT_PCI_S: {
8502
      // op: Pd
8503
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8504
0
      op &= UINT64_C(15);
8505
0
      Value |= op;
8506
      // op: PNn
8507
0
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
8508
0
      op &= UINT64_C(7);
8509
0
      op <<= 5;
8510
0
      Value |= op;
8511
      // op: index
8512
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8513
0
      op &= UINT64_C(3);
8514
0
      op <<= 8;
8515
0
      Value |= op;
8516
0
      break;
8517
0
    }
8518
0
    case AArch64::ANDS_PPzPP:
8519
0
    case AArch64::AND_PPzPP:
8520
0
    case AArch64::BICS_PPzPP:
8521
0
    case AArch64::BIC_PPzPP:
8522
0
    case AArch64::BRKPAS_PPzPP:
8523
0
    case AArch64::BRKPA_PPzPP:
8524
0
    case AArch64::BRKPBS_PPzPP:
8525
0
    case AArch64::BRKPB_PPzPP:
8526
0
    case AArch64::EORS_PPzPP:
8527
0
    case AArch64::EOR_PPzPP:
8528
0
    case AArch64::NANDS_PPzPP:
8529
0
    case AArch64::NAND_PPzPP:
8530
0
    case AArch64::NORS_PPzPP:
8531
0
    case AArch64::NOR_PPzPP:
8532
0
    case AArch64::ORNS_PPzPP:
8533
0
    case AArch64::ORN_PPzPP:
8534
0
    case AArch64::ORRS_PPzPP:
8535
0
    case AArch64::ORR_PPzPP:
8536
0
    case AArch64::SEL_PPPP: {
8537
      // op: Pd
8538
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8539
0
      op &= UINT64_C(15);
8540
0
      Value |= op;
8541
      // op: Pg
8542
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8543
0
      op &= UINT64_C(15);
8544
0
      op <<= 10;
8545
0
      Value |= op;
8546
      // op: Pm
8547
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8548
0
      op &= UINT64_C(15);
8549
0
      op <<= 16;
8550
0
      Value |= op;
8551
      // op: Pn
8552
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8553
0
      op &= UINT64_C(15);
8554
0
      op <<= 5;
8555
0
      Value |= op;
8556
0
      break;
8557
0
    }
8558
0
    case AArch64::BRKAS_PPzP:
8559
0
    case AArch64::BRKA_PPzP:
8560
0
    case AArch64::BRKBS_PPzP:
8561
0
    case AArch64::BRKB_PPzP: {
8562
      // op: Pd
8563
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8564
0
      op &= UINT64_C(15);
8565
0
      Value |= op;
8566
      // op: Pg
8567
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8568
0
      op &= UINT64_C(15);
8569
0
      op <<= 10;
8570
0
      Value |= op;
8571
      // op: Pn
8572
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8573
0
      op &= UINT64_C(15);
8574
0
      op <<= 5;
8575
0
      Value |= op;
8576
0
      break;
8577
0
    }
8578
0
    case AArch64::RDFFRS_PPz:
8579
0
    case AArch64::RDFFR_PPz_REAL: {
8580
      // op: Pd
8581
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8582
0
      op &= UINT64_C(15);
8583
0
      Value |= op;
8584
      // op: Pg
8585
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8586
0
      op &= UINT64_C(15);
8587
0
      op <<= 5;
8588
0
      Value |= op;
8589
0
      break;
8590
0
    }
8591
0
    case AArch64::CMPEQ_PPzZZ_B:
8592
0
    case AArch64::CMPEQ_PPzZZ_D:
8593
0
    case AArch64::CMPEQ_PPzZZ_H:
8594
0
    case AArch64::CMPEQ_PPzZZ_S:
8595
0
    case AArch64::CMPEQ_WIDE_PPzZZ_B:
8596
0
    case AArch64::CMPEQ_WIDE_PPzZZ_H:
8597
0
    case AArch64::CMPEQ_WIDE_PPzZZ_S:
8598
0
    case AArch64::CMPGE_PPzZZ_B:
8599
0
    case AArch64::CMPGE_PPzZZ_D:
8600
0
    case AArch64::CMPGE_PPzZZ_H:
8601
0
    case AArch64::CMPGE_PPzZZ_S:
8602
0
    case AArch64::CMPGE_WIDE_PPzZZ_B:
8603
0
    case AArch64::CMPGE_WIDE_PPzZZ_H:
8604
0
    case AArch64::CMPGE_WIDE_PPzZZ_S:
8605
0
    case AArch64::CMPGT_PPzZZ_B:
8606
0
    case AArch64::CMPGT_PPzZZ_D:
8607
0
    case AArch64::CMPGT_PPzZZ_H:
8608
0
    case AArch64::CMPGT_PPzZZ_S:
8609
0
    case AArch64::CMPGT_WIDE_PPzZZ_B:
8610
0
    case AArch64::CMPGT_WIDE_PPzZZ_H:
8611
0
    case AArch64::CMPGT_WIDE_PPzZZ_S:
8612
0
    case AArch64::CMPHI_PPzZZ_B:
8613
0
    case AArch64::CMPHI_PPzZZ_D:
8614
0
    case AArch64::CMPHI_PPzZZ_H:
8615
0
    case AArch64::CMPHI_PPzZZ_S:
8616
0
    case AArch64::CMPHI_WIDE_PPzZZ_B:
8617
0
    case AArch64::CMPHI_WIDE_PPzZZ_H:
8618
0
    case AArch64::CMPHI_WIDE_PPzZZ_S:
8619
0
    case AArch64::CMPHS_PPzZZ_B:
8620
0
    case AArch64::CMPHS_PPzZZ_D:
8621
0
    case AArch64::CMPHS_PPzZZ_H:
8622
0
    case AArch64::CMPHS_PPzZZ_S:
8623
0
    case AArch64::CMPHS_WIDE_PPzZZ_B:
8624
0
    case AArch64::CMPHS_WIDE_PPzZZ_H:
8625
0
    case AArch64::CMPHS_WIDE_PPzZZ_S:
8626
0
    case AArch64::CMPLE_WIDE_PPzZZ_B:
8627
0
    case AArch64::CMPLE_WIDE_PPzZZ_H:
8628
0
    case AArch64::CMPLE_WIDE_PPzZZ_S:
8629
0
    case AArch64::CMPLO_WIDE_PPzZZ_B:
8630
0
    case AArch64::CMPLO_WIDE_PPzZZ_H:
8631
0
    case AArch64::CMPLO_WIDE_PPzZZ_S:
8632
0
    case AArch64::CMPLS_WIDE_PPzZZ_B:
8633
0
    case AArch64::CMPLS_WIDE_PPzZZ_H:
8634
0
    case AArch64::CMPLS_WIDE_PPzZZ_S:
8635
0
    case AArch64::CMPLT_WIDE_PPzZZ_B:
8636
0
    case AArch64::CMPLT_WIDE_PPzZZ_H:
8637
0
    case AArch64::CMPLT_WIDE_PPzZZ_S:
8638
0
    case AArch64::CMPNE_PPzZZ_B:
8639
0
    case AArch64::CMPNE_PPzZZ_D:
8640
0
    case AArch64::CMPNE_PPzZZ_H:
8641
0
    case AArch64::CMPNE_PPzZZ_S:
8642
0
    case AArch64::CMPNE_WIDE_PPzZZ_B:
8643
0
    case AArch64::CMPNE_WIDE_PPzZZ_H:
8644
0
    case AArch64::CMPNE_WIDE_PPzZZ_S:
8645
0
    case AArch64::FACGE_PPzZZ_D:
8646
0
    case AArch64::FACGE_PPzZZ_H:
8647
0
    case AArch64::FACGE_PPzZZ_S:
8648
0
    case AArch64::FACGT_PPzZZ_D:
8649
0
    case AArch64::FACGT_PPzZZ_H:
8650
0
    case AArch64::FACGT_PPzZZ_S:
8651
0
    case AArch64::FCMEQ_PPzZZ_D:
8652
0
    case AArch64::FCMEQ_PPzZZ_H:
8653
0
    case AArch64::FCMEQ_PPzZZ_S:
8654
0
    case AArch64::FCMGE_PPzZZ_D:
8655
0
    case AArch64::FCMGE_PPzZZ_H:
8656
0
    case AArch64::FCMGE_PPzZZ_S:
8657
0
    case AArch64::FCMGT_PPzZZ_D:
8658
0
    case AArch64::FCMGT_PPzZZ_H:
8659
0
    case AArch64::FCMGT_PPzZZ_S:
8660
0
    case AArch64::FCMNE_PPzZZ_D:
8661
0
    case AArch64::FCMNE_PPzZZ_H:
8662
0
    case AArch64::FCMNE_PPzZZ_S:
8663
0
    case AArch64::FCMUO_PPzZZ_D:
8664
0
    case AArch64::FCMUO_PPzZZ_H:
8665
0
    case AArch64::FCMUO_PPzZZ_S:
8666
0
    case AArch64::MATCH_PPzZZ_B:
8667
0
    case AArch64::MATCH_PPzZZ_H:
8668
0
    case AArch64::NMATCH_PPzZZ_B:
8669
0
    case AArch64::NMATCH_PPzZZ_H: {
8670
      // op: Pd
8671
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8672
0
      op &= UINT64_C(15);
8673
0
      Value |= op;
8674
      // op: Pg
8675
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8676
0
      op &= UINT64_C(7);
8677
0
      op <<= 10;
8678
0
      Value |= op;
8679
      // op: Zm
8680
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8681
0
      op &= UINT64_C(31);
8682
0
      op <<= 16;
8683
0
      Value |= op;
8684
      // op: Zn
8685
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8686
0
      op &= UINT64_C(31);
8687
0
      op <<= 5;
8688
0
      Value |= op;
8689
0
      break;
8690
0
    }
8691
0
    case AArch64::FCMEQ_PPzZ0_D:
8692
0
    case AArch64::FCMEQ_PPzZ0_H:
8693
0
    case AArch64::FCMEQ_PPzZ0_S:
8694
0
    case AArch64::FCMGE_PPzZ0_D:
8695
0
    case AArch64::FCMGE_PPzZ0_H:
8696
0
    case AArch64::FCMGE_PPzZ0_S:
8697
0
    case AArch64::FCMGT_PPzZ0_D:
8698
0
    case AArch64::FCMGT_PPzZ0_H:
8699
0
    case AArch64::FCMGT_PPzZ0_S:
8700
0
    case AArch64::FCMLE_PPzZ0_D:
8701
0
    case AArch64::FCMLE_PPzZ0_H:
8702
0
    case AArch64::FCMLE_PPzZ0_S:
8703
0
    case AArch64::FCMLT_PPzZ0_D:
8704
0
    case AArch64::FCMLT_PPzZ0_H:
8705
0
    case AArch64::FCMLT_PPzZ0_S:
8706
0
    case AArch64::FCMNE_PPzZ0_D:
8707
0
    case AArch64::FCMNE_PPzZ0_H:
8708
0
    case AArch64::FCMNE_PPzZ0_S: {
8709
      // op: Pd
8710
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8711
0
      op &= UINT64_C(15);
8712
0
      Value |= op;
8713
      // op: Pg
8714
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8715
0
      op &= UINT64_C(7);
8716
0
      op <<= 10;
8717
0
      Value |= op;
8718
      // op: Zn
8719
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8720
0
      op &= UINT64_C(31);
8721
0
      op <<= 5;
8722
0
      Value |= op;
8723
0
      break;
8724
0
    }
8725
0
    case AArch64::CMPEQ_PPzZI_B:
8726
0
    case AArch64::CMPEQ_PPzZI_D:
8727
0
    case AArch64::CMPEQ_PPzZI_H:
8728
0
    case AArch64::CMPEQ_PPzZI_S:
8729
0
    case AArch64::CMPGE_PPzZI_B:
8730
0
    case AArch64::CMPGE_PPzZI_D:
8731
0
    case AArch64::CMPGE_PPzZI_H:
8732
0
    case AArch64::CMPGE_PPzZI_S:
8733
0
    case AArch64::CMPGT_PPzZI_B:
8734
0
    case AArch64::CMPGT_PPzZI_D:
8735
0
    case AArch64::CMPGT_PPzZI_H:
8736
0
    case AArch64::CMPGT_PPzZI_S:
8737
0
    case AArch64::CMPLE_PPzZI_B:
8738
0
    case AArch64::CMPLE_PPzZI_D:
8739
0
    case AArch64::CMPLE_PPzZI_H:
8740
0
    case AArch64::CMPLE_PPzZI_S:
8741
0
    case AArch64::CMPLT_PPzZI_B:
8742
0
    case AArch64::CMPLT_PPzZI_D:
8743
0
    case AArch64::CMPLT_PPzZI_H:
8744
0
    case AArch64::CMPLT_PPzZI_S:
8745
0
    case AArch64::CMPNE_PPzZI_B:
8746
0
    case AArch64::CMPNE_PPzZI_D:
8747
0
    case AArch64::CMPNE_PPzZI_H:
8748
0
    case AArch64::CMPNE_PPzZI_S: {
8749
      // op: Pd
8750
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8751
0
      op &= UINT64_C(15);
8752
0
      Value |= op;
8753
      // op: Pg
8754
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8755
0
      op &= UINT64_C(7);
8756
0
      op <<= 10;
8757
0
      Value |= op;
8758
      // op: Zn
8759
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8760
0
      op &= UINT64_C(31);
8761
0
      op <<= 5;
8762
0
      Value |= op;
8763
      // op: imm5
8764
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8765
0
      op &= UINT64_C(31);
8766
0
      op <<= 16;
8767
0
      Value |= op;
8768
0
      break;
8769
0
    }
8770
0
    case AArch64::CMPHI_PPzZI_B:
8771
0
    case AArch64::CMPHI_PPzZI_D:
8772
0
    case AArch64::CMPHI_PPzZI_H:
8773
0
    case AArch64::CMPHI_PPzZI_S:
8774
0
    case AArch64::CMPHS_PPzZI_B:
8775
0
    case AArch64::CMPHS_PPzZI_D:
8776
0
    case AArch64::CMPHS_PPzZI_H:
8777
0
    case AArch64::CMPHS_PPzZI_S:
8778
0
    case AArch64::CMPLO_PPzZI_B:
8779
0
    case AArch64::CMPLO_PPzZI_D:
8780
0
    case AArch64::CMPLO_PPzZI_H:
8781
0
    case AArch64::CMPLO_PPzZI_S:
8782
0
    case AArch64::CMPLS_PPzZI_B:
8783
0
    case AArch64::CMPLS_PPzZI_D:
8784
0
    case AArch64::CMPLS_PPzZI_H:
8785
0
    case AArch64::CMPLS_PPzZI_S: {
8786
      // op: Pd
8787
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8788
0
      op &= UINT64_C(15);
8789
0
      Value |= op;
8790
      // op: Pg
8791
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8792
0
      op &= UINT64_C(7);
8793
0
      op <<= 10;
8794
0
      Value |= op;
8795
      // op: Zn
8796
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8797
0
      op &= UINT64_C(31);
8798
0
      op <<= 5;
8799
0
      Value |= op;
8800
      // op: imm7
8801
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8802
0
      op &= UINT64_C(127);
8803
0
      op <<= 14;
8804
0
      Value |= op;
8805
0
      break;
8806
0
    }
8807
0
    case AArch64::BRKA_PPmP:
8808
0
    case AArch64::BRKB_PPmP: {
8809
      // op: Pd
8810
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8811
0
      op &= UINT64_C(15);
8812
0
      Value |= op;
8813
      // op: Pg
8814
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8815
0
      op &= UINT64_C(15);
8816
0
      op <<= 10;
8817
0
      Value |= op;
8818
      // op: Pn
8819
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8820
0
      op &= UINT64_C(15);
8821
0
      op <<= 5;
8822
0
      Value |= op;
8823
0
      break;
8824
0
    }
8825
0
    case AArch64::TRN1_PPP_B:
8826
0
    case AArch64::TRN1_PPP_D:
8827
0
    case AArch64::TRN1_PPP_H:
8828
0
    case AArch64::TRN1_PPP_S:
8829
0
    case AArch64::TRN2_PPP_B:
8830
0
    case AArch64::TRN2_PPP_D:
8831
0
    case AArch64::TRN2_PPP_H:
8832
0
    case AArch64::TRN2_PPP_S:
8833
0
    case AArch64::UZP1_PPP_B:
8834
0
    case AArch64::UZP1_PPP_D:
8835
0
    case AArch64::UZP1_PPP_H:
8836
0
    case AArch64::UZP1_PPP_S:
8837
0
    case AArch64::UZP2_PPP_B:
8838
0
    case AArch64::UZP2_PPP_D:
8839
0
    case AArch64::UZP2_PPP_H:
8840
0
    case AArch64::UZP2_PPP_S:
8841
0
    case AArch64::ZIP1_PPP_B:
8842
0
    case AArch64::ZIP1_PPP_D:
8843
0
    case AArch64::ZIP1_PPP_H:
8844
0
    case AArch64::ZIP1_PPP_S:
8845
0
    case AArch64::ZIP2_PPP_B:
8846
0
    case AArch64::ZIP2_PPP_D:
8847
0
    case AArch64::ZIP2_PPP_H:
8848
0
    case AArch64::ZIP2_PPP_S: {
8849
      // op: Pd
8850
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8851
0
      op &= UINT64_C(15);
8852
0
      Value |= op;
8853
      // op: Pm
8854
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8855
0
      op &= UINT64_C(15);
8856
0
      op <<= 16;
8857
0
      Value |= op;
8858
      // op: Pn
8859
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8860
0
      op &= UINT64_C(15);
8861
0
      op <<= 5;
8862
0
      Value |= op;
8863
0
      break;
8864
0
    }
8865
0
    case AArch64::PUNPKHI_PP:
8866
0
    case AArch64::PUNPKLO_PP:
8867
0
    case AArch64::REV_PP_B:
8868
0
    case AArch64::REV_PP_D:
8869
0
    case AArch64::REV_PP_H:
8870
0
    case AArch64::REV_PP_S: {
8871
      // op: Pd
8872
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8873
0
      op &= UINT64_C(15);
8874
0
      Value |= op;
8875
      // op: Pn
8876
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8877
0
      op &= UINT64_C(15);
8878
0
      op <<= 5;
8879
0
      Value |= op;
8880
0
      break;
8881
0
    }
8882
0
    case AArch64::WHILEGE_PWW_B:
8883
0
    case AArch64::WHILEGE_PWW_D:
8884
0
    case AArch64::WHILEGE_PWW_H:
8885
0
    case AArch64::WHILEGE_PWW_S:
8886
0
    case AArch64::WHILEGE_PXX_B:
8887
0
    case AArch64::WHILEGE_PXX_D:
8888
0
    case AArch64::WHILEGE_PXX_H:
8889
0
    case AArch64::WHILEGE_PXX_S:
8890
0
    case AArch64::WHILEGT_PWW_B:
8891
0
    case AArch64::WHILEGT_PWW_D:
8892
0
    case AArch64::WHILEGT_PWW_H:
8893
0
    case AArch64::WHILEGT_PWW_S:
8894
0
    case AArch64::WHILEGT_PXX_B:
8895
0
    case AArch64::WHILEGT_PXX_D:
8896
0
    case AArch64::WHILEGT_PXX_H:
8897
0
    case AArch64::WHILEGT_PXX_S:
8898
0
    case AArch64::WHILEHI_PWW_B:
8899
0
    case AArch64::WHILEHI_PWW_D:
8900
0
    case AArch64::WHILEHI_PWW_H:
8901
0
    case AArch64::WHILEHI_PWW_S:
8902
0
    case AArch64::WHILEHI_PXX_B:
8903
0
    case AArch64::WHILEHI_PXX_D:
8904
0
    case AArch64::WHILEHI_PXX_H:
8905
0
    case AArch64::WHILEHI_PXX_S:
8906
0
    case AArch64::WHILEHS_PWW_B:
8907
0
    case AArch64::WHILEHS_PWW_D:
8908
0
    case AArch64::WHILEHS_PWW_H:
8909
0
    case AArch64::WHILEHS_PWW_S:
8910
0
    case AArch64::WHILEHS_PXX_B:
8911
0
    case AArch64::WHILEHS_PXX_D:
8912
0
    case AArch64::WHILEHS_PXX_H:
8913
0
    case AArch64::WHILEHS_PXX_S:
8914
0
    case AArch64::WHILELE_PWW_B:
8915
0
    case AArch64::WHILELE_PWW_D:
8916
0
    case AArch64::WHILELE_PWW_H:
8917
0
    case AArch64::WHILELE_PWW_S:
8918
0
    case AArch64::WHILELE_PXX_B:
8919
0
    case AArch64::WHILELE_PXX_D:
8920
0
    case AArch64::WHILELE_PXX_H:
8921
0
    case AArch64::WHILELE_PXX_S:
8922
0
    case AArch64::WHILELO_PWW_B:
8923
0
    case AArch64::WHILELO_PWW_D:
8924
0
    case AArch64::WHILELO_PWW_H:
8925
0
    case AArch64::WHILELO_PWW_S:
8926
0
    case AArch64::WHILELO_PXX_B:
8927
0
    case AArch64::WHILELO_PXX_D:
8928
0
    case AArch64::WHILELO_PXX_H:
8929
0
    case AArch64::WHILELO_PXX_S:
8930
0
    case AArch64::WHILELS_PWW_B:
8931
0
    case AArch64::WHILELS_PWW_D:
8932
0
    case AArch64::WHILELS_PWW_H:
8933
0
    case AArch64::WHILELS_PWW_S:
8934
0
    case AArch64::WHILELS_PXX_B:
8935
0
    case AArch64::WHILELS_PXX_D:
8936
0
    case AArch64::WHILELS_PXX_H:
8937
0
    case AArch64::WHILELS_PXX_S:
8938
0
    case AArch64::WHILELT_PWW_B:
8939
0
    case AArch64::WHILELT_PWW_D:
8940
0
    case AArch64::WHILELT_PWW_H:
8941
0
    case AArch64::WHILELT_PWW_S:
8942
0
    case AArch64::WHILELT_PXX_B:
8943
0
    case AArch64::WHILELT_PXX_D:
8944
0
    case AArch64::WHILELT_PXX_H:
8945
0
    case AArch64::WHILELT_PXX_S:
8946
0
    case AArch64::WHILERW_PXX_B:
8947
0
    case AArch64::WHILERW_PXX_D:
8948
0
    case AArch64::WHILERW_PXX_H:
8949
0
    case AArch64::WHILERW_PXX_S:
8950
0
    case AArch64::WHILEWR_PXX_B:
8951
0
    case AArch64::WHILEWR_PXX_D:
8952
0
    case AArch64::WHILEWR_PXX_H:
8953
0
    case AArch64::WHILEWR_PXX_S: {
8954
      // op: Pd
8955
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8956
0
      op &= UINT64_C(15);
8957
0
      Value |= op;
8958
      // op: Rm
8959
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8960
0
      op &= UINT64_C(31);
8961
0
      op <<= 16;
8962
0
      Value |= op;
8963
      // op: Rn
8964
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8965
0
      op &= UINT64_C(31);
8966
0
      op <<= 5;
8967
0
      Value |= op;
8968
0
      break;
8969
0
    }
8970
0
    case AArch64::PMOV_PZI_B: {
8971
      // op: Pd
8972
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8973
0
      op &= UINT64_C(15);
8974
0
      Value |= op;
8975
      // op: Zn
8976
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8977
0
      op &= UINT64_C(31);
8978
0
      op <<= 5;
8979
0
      Value |= op;
8980
0
      break;
8981
0
    }
8982
0
    case AArch64::PMOV_PZI_D: {
8983
      // op: Pd
8984
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8985
0
      op &= UINT64_C(15);
8986
0
      Value |= op;
8987
      // op: Zn
8988
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8989
0
      op &= UINT64_C(31);
8990
0
      op <<= 5;
8991
0
      Value |= op;
8992
      // op: index
8993
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8994
0
      Value |= (op & UINT64_C(4)) << 20;
8995
0
      Value |= (op & UINT64_C(3)) << 17;
8996
0
      break;
8997
0
    }
8998
0
    case AArch64::PMOV_PZI_H: {
8999
      // op: Pd
9000
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9001
0
      op &= UINT64_C(15);
9002
0
      Value |= op;
9003
      // op: Zn
9004
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9005
0
      op &= UINT64_C(31);
9006
0
      op <<= 5;
9007
0
      Value |= op;
9008
      // op: index
9009
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9010
0
      op &= UINT64_C(1);
9011
0
      op <<= 17;
9012
0
      Value |= op;
9013
0
      break;
9014
0
    }
9015
0
    case AArch64::PMOV_PZI_S: {
9016
      // op: Pd
9017
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9018
0
      op &= UINT64_C(15);
9019
0
      Value |= op;
9020
      // op: Zn
9021
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9022
0
      op &= UINT64_C(31);
9023
0
      op <<= 5;
9024
0
      Value |= op;
9025
      // op: index
9026
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9027
0
      op &= UINT64_C(3);
9028
0
      op <<= 17;
9029
0
      Value |= op;
9030
0
      break;
9031
0
    }
9032
0
    case AArch64::PTRUES_B:
9033
0
    case AArch64::PTRUES_D:
9034
0
    case AArch64::PTRUES_H:
9035
0
    case AArch64::PTRUES_S:
9036
0
    case AArch64::PTRUE_B:
9037
0
    case AArch64::PTRUE_D:
9038
0
    case AArch64::PTRUE_H:
9039
0
    case AArch64::PTRUE_S: {
9040
      // op: Pd
9041
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9042
0
      op &= UINT64_C(15);
9043
0
      Value |= op;
9044
      // op: pattern
9045
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9046
0
      op &= UINT64_C(31);
9047
0
      op <<= 5;
9048
0
      Value |= op;
9049
0
      break;
9050
0
    }
9051
0
    case AArch64::BRKNS_PPzP:
9052
0
    case AArch64::BRKN_PPzP: {
9053
      // op: Pdm
9054
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9055
0
      op &= UINT64_C(15);
9056
0
      Value |= op;
9057
      // op: Pg
9058
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9059
0
      op &= UINT64_C(15);
9060
0
      op <<= 10;
9061
0
      Value |= op;
9062
      // op: Pn
9063
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9064
0
      op &= UINT64_C(15);
9065
0
      op <<= 5;
9066
0
      Value |= op;
9067
0
      break;
9068
0
    }
9069
0
    case AArch64::PFIRST_B:
9070
0
    case AArch64::PNEXT_B:
9071
0
    case AArch64::PNEXT_D:
9072
0
    case AArch64::PNEXT_H:
9073
0
    case AArch64::PNEXT_S: {
9074
      // op: Pdn
9075
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9076
0
      op &= UINT64_C(15);
9077
0
      Value |= op;
9078
      // op: Pg
9079
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9080
0
      op &= UINT64_C(15);
9081
0
      op <<= 5;
9082
0
      Value |= op;
9083
0
      break;
9084
0
    }
9085
0
    case AArch64::PTEST_PP: {
9086
      // op: Pg
9087
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9088
0
      op &= UINT64_C(15);
9089
0
      op <<= 10;
9090
0
      Value |= op;
9091
      // op: Pn
9092
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9093
0
      op &= UINT64_C(15);
9094
0
      op <<= 5;
9095
0
      Value |= op;
9096
0
      break;
9097
0
    }
9098
0
    case AArch64::CNTP_XPP_B:
9099
0
    case AArch64::CNTP_XPP_D:
9100
0
    case AArch64::CNTP_XPP_H:
9101
0
    case AArch64::CNTP_XPP_S: {
9102
      // op: Pg
9103
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9104
0
      op &= UINT64_C(15);
9105
0
      op <<= 10;
9106
0
      Value |= op;
9107
      // op: Pn
9108
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9109
0
      op &= UINT64_C(15);
9110
0
      op <<= 5;
9111
0
      Value |= op;
9112
      // op: Rd
9113
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9114
0
      op &= UINT64_C(31);
9115
0
      Value |= op;
9116
0
      break;
9117
0
    }
9118
0
    case AArch64::SEL_ZPZZ_B:
9119
0
    case AArch64::SEL_ZPZZ_D:
9120
0
    case AArch64::SEL_ZPZZ_H:
9121
0
    case AArch64::SEL_ZPZZ_S: {
9122
      // op: Pg
9123
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9124
0
      op &= UINT64_C(15);
9125
0
      op <<= 10;
9126
0
      Value |= op;
9127
      // op: Zd
9128
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9129
0
      op &= UINT64_C(31);
9130
0
      Value |= op;
9131
      // op: Zm
9132
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9133
0
      op &= UINT64_C(31);
9134
0
      op <<= 16;
9135
0
      Value |= op;
9136
      // op: Zn
9137
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9138
0
      op &= UINT64_C(31);
9139
0
      op <<= 5;
9140
0
      Value |= op;
9141
0
      break;
9142
0
    }
9143
0
    case AArch64::LASTA_RPZ_B:
9144
0
    case AArch64::LASTA_RPZ_D:
9145
0
    case AArch64::LASTA_RPZ_H:
9146
0
    case AArch64::LASTA_RPZ_S:
9147
0
    case AArch64::LASTB_RPZ_B:
9148
0
    case AArch64::LASTB_RPZ_D:
9149
0
    case AArch64::LASTB_RPZ_H:
9150
0
    case AArch64::LASTB_RPZ_S: {
9151
      // op: Pg
9152
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9153
0
      op &= UINT64_C(7);
9154
0
      op <<= 10;
9155
0
      Value |= op;
9156
      // op: Rd
9157
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9158
0
      op &= UINT64_C(31);
9159
0
      Value |= op;
9160
      // op: Zn
9161
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9162
0
      op &= UINT64_C(31);
9163
0
      op <<= 5;
9164
0
      Value |= op;
9165
0
      break;
9166
0
    }
9167
0
    case AArch64::CLASTA_RPZ_B:
9168
0
    case AArch64::CLASTA_RPZ_D:
9169
0
    case AArch64::CLASTA_RPZ_H:
9170
0
    case AArch64::CLASTA_RPZ_S:
9171
0
    case AArch64::CLASTB_RPZ_B:
9172
0
    case AArch64::CLASTB_RPZ_D:
9173
0
    case AArch64::CLASTB_RPZ_H:
9174
0
    case AArch64::CLASTB_RPZ_S: {
9175
      // op: Pg
9176
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9177
0
      op &= UINT64_C(7);
9178
0
      op <<= 10;
9179
0
      Value |= op;
9180
      // op: Rdn
9181
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9182
0
      op &= UINT64_C(31);
9183
0
      Value |= op;
9184
      // op: Zm
9185
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9186
0
      op &= UINT64_C(31);
9187
0
      op <<= 5;
9188
0
      Value |= op;
9189
0
      break;
9190
0
    }
9191
0
    case AArch64::LD2B:
9192
0
    case AArch64::LD2D:
9193
0
    case AArch64::LD2H:
9194
0
    case AArch64::LD2Q:
9195
0
    case AArch64::LD2W:
9196
0
    case AArch64::LD3B:
9197
0
    case AArch64::LD3D:
9198
0
    case AArch64::LD3H:
9199
0
    case AArch64::LD3Q:
9200
0
    case AArch64::LD3W:
9201
0
    case AArch64::LD4B:
9202
0
    case AArch64::LD4D:
9203
0
    case AArch64::LD4H:
9204
0
    case AArch64::LD4Q:
9205
0
    case AArch64::LD4W:
9206
0
    case AArch64::LDNT1B_ZRR:
9207
0
    case AArch64::LDNT1D_ZRR:
9208
0
    case AArch64::LDNT1H_ZRR:
9209
0
    case AArch64::LDNT1W_ZRR:
9210
0
    case AArch64::ST1B:
9211
0
    case AArch64::ST1B_D:
9212
0
    case AArch64::ST1B_H:
9213
0
    case AArch64::ST1B_S:
9214
0
    case AArch64::ST1D:
9215
0
    case AArch64::ST1D_Q:
9216
0
    case AArch64::ST1H:
9217
0
    case AArch64::ST1H_D:
9218
0
    case AArch64::ST1H_S:
9219
0
    case AArch64::ST1W:
9220
0
    case AArch64::ST1W_D:
9221
0
    case AArch64::ST1W_Q:
9222
0
    case AArch64::ST2B:
9223
0
    case AArch64::ST2D:
9224
0
    case AArch64::ST2H:
9225
0
    case AArch64::ST2W:
9226
0
    case AArch64::ST3B:
9227
0
    case AArch64::ST3D:
9228
0
    case AArch64::ST3H:
9229
0
    case AArch64::ST3W:
9230
0
    case AArch64::ST4B:
9231
0
    case AArch64::ST4D:
9232
0
    case AArch64::ST4H:
9233
0
    case AArch64::ST4W:
9234
0
    case AArch64::STNT1B_ZRR:
9235
0
    case AArch64::STNT1D_ZRR:
9236
0
    case AArch64::STNT1H_ZRR:
9237
0
    case AArch64::STNT1W_ZRR: {
9238
      // op: Pg
9239
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9240
0
      op &= UINT64_C(7);
9241
0
      op <<= 10;
9242
0
      Value |= op;
9243
      // op: Rm
9244
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9245
0
      op &= UINT64_C(31);
9246
0
      op <<= 16;
9247
0
      Value |= op;
9248
      // op: Rn
9249
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9250
0
      op &= UINT64_C(31);
9251
0
      op <<= 5;
9252
0
      Value |= op;
9253
      // op: Zt
9254
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9255
0
      op &= UINT64_C(31);
9256
0
      Value |= op;
9257
0
      break;
9258
0
    }
9259
0
    case AArch64::LDNT1B_ZZR_D_REAL:
9260
0
    case AArch64::LDNT1B_ZZR_S_REAL:
9261
0
    case AArch64::LDNT1D_ZZR_D_REAL:
9262
0
    case AArch64::LDNT1H_ZZR_D_REAL:
9263
0
    case AArch64::LDNT1H_ZZR_S_REAL:
9264
0
    case AArch64::LDNT1SB_ZZR_D_REAL:
9265
0
    case AArch64::LDNT1SB_ZZR_S_REAL:
9266
0
    case AArch64::LDNT1SH_ZZR_D_REAL:
9267
0
    case AArch64::LDNT1SH_ZZR_S_REAL:
9268
0
    case AArch64::LDNT1SW_ZZR_D_REAL:
9269
0
    case AArch64::LDNT1W_ZZR_D_REAL:
9270
0
    case AArch64::LDNT1W_ZZR_S_REAL:
9271
0
    case AArch64::STNT1B_ZZR_D_REAL:
9272
0
    case AArch64::STNT1B_ZZR_S_REAL:
9273
0
    case AArch64::STNT1D_ZZR_D_REAL:
9274
0
    case AArch64::STNT1H_ZZR_D_REAL:
9275
0
    case AArch64::STNT1H_ZZR_S_REAL:
9276
0
    case AArch64::STNT1W_ZZR_D_REAL:
9277
0
    case AArch64::STNT1W_ZZR_S_REAL: {
9278
      // op: Pg
9279
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9280
0
      op &= UINT64_C(7);
9281
0
      op <<= 10;
9282
0
      Value |= op;
9283
      // op: Rm
9284
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9285
0
      op &= UINT64_C(31);
9286
0
      op <<= 16;
9287
0
      Value |= op;
9288
      // op: Zn
9289
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9290
0
      op &= UINT64_C(31);
9291
0
      op <<= 5;
9292
0
      Value |= op;
9293
      // op: Zt
9294
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9295
0
      op &= UINT64_C(31);
9296
0
      Value |= op;
9297
0
      break;
9298
0
    }
9299
0
    case AArch64::GLD1B_D_REAL:
9300
0
    case AArch64::GLD1B_D_SXTW_REAL:
9301
0
    case AArch64::GLD1B_D_UXTW_REAL:
9302
0
    case AArch64::GLD1B_S_SXTW_REAL:
9303
0
    case AArch64::GLD1B_S_UXTW_REAL:
9304
0
    case AArch64::GLD1D_REAL:
9305
0
    case AArch64::GLD1D_SCALED_REAL:
9306
0
    case AArch64::GLD1D_SXTW_REAL:
9307
0
    case AArch64::GLD1D_SXTW_SCALED_REAL:
9308
0
    case AArch64::GLD1D_UXTW_REAL:
9309
0
    case AArch64::GLD1D_UXTW_SCALED_REAL:
9310
0
    case AArch64::GLD1H_D_REAL:
9311
0
    case AArch64::GLD1H_D_SCALED_REAL:
9312
0
    case AArch64::GLD1H_D_SXTW_REAL:
9313
0
    case AArch64::GLD1H_D_SXTW_SCALED_REAL:
9314
0
    case AArch64::GLD1H_D_UXTW_REAL:
9315
0
    case AArch64::GLD1H_D_UXTW_SCALED_REAL:
9316
0
    case AArch64::GLD1H_S_SXTW_REAL:
9317
0
    case AArch64::GLD1H_S_SXTW_SCALED_REAL:
9318
0
    case AArch64::GLD1H_S_UXTW_REAL:
9319
0
    case AArch64::GLD1H_S_UXTW_SCALED_REAL:
9320
0
    case AArch64::GLD1SB_D_REAL:
9321
0
    case AArch64::GLD1SB_D_SXTW_REAL:
9322
0
    case AArch64::GLD1SB_D_UXTW_REAL:
9323
0
    case AArch64::GLD1SB_S_SXTW_REAL:
9324
0
    case AArch64::GLD1SB_S_UXTW_REAL:
9325
0
    case AArch64::GLD1SH_D_REAL:
9326
0
    case AArch64::GLD1SH_D_SCALED_REAL:
9327
0
    case AArch64::GLD1SH_D_SXTW_REAL:
9328
0
    case AArch64::GLD1SH_D_SXTW_SCALED_REAL:
9329
0
    case AArch64::GLD1SH_D_UXTW_REAL:
9330
0
    case AArch64::GLD1SH_D_UXTW_SCALED_REAL:
9331
0
    case AArch64::GLD1SH_S_SXTW_REAL:
9332
0
    case AArch64::GLD1SH_S_SXTW_SCALED_REAL:
9333
0
    case AArch64::GLD1SH_S_UXTW_REAL:
9334
0
    case AArch64::GLD1SH_S_UXTW_SCALED_REAL:
9335
0
    case AArch64::GLD1SW_D_REAL:
9336
0
    case AArch64::GLD1SW_D_SCALED_REAL:
9337
0
    case AArch64::GLD1SW_D_SXTW_REAL:
9338
0
    case AArch64::GLD1SW_D_SXTW_SCALED_REAL:
9339
0
    case AArch64::GLD1SW_D_UXTW_REAL:
9340
0
    case AArch64::GLD1SW_D_UXTW_SCALED_REAL:
9341
0
    case AArch64::GLD1W_D_REAL:
9342
0
    case AArch64::GLD1W_D_SCALED_REAL:
9343
0
    case AArch64::GLD1W_D_SXTW_REAL:
9344
0
    case AArch64::GLD1W_D_SXTW_SCALED_REAL:
9345
0
    case AArch64::GLD1W_D_UXTW_REAL:
9346
0
    case AArch64::GLD1W_D_UXTW_SCALED_REAL:
9347
0
    case AArch64::GLD1W_SXTW_REAL:
9348
0
    case AArch64::GLD1W_SXTW_SCALED_REAL:
9349
0
    case AArch64::GLD1W_UXTW_REAL:
9350
0
    case AArch64::GLD1W_UXTW_SCALED_REAL:
9351
0
    case AArch64::GLDFF1B_D_REAL:
9352
0
    case AArch64::GLDFF1B_D_SXTW_REAL:
9353
0
    case AArch64::GLDFF1B_D_UXTW_REAL:
9354
0
    case AArch64::GLDFF1B_S_SXTW_REAL:
9355
0
    case AArch64::GLDFF1B_S_UXTW_REAL:
9356
0
    case AArch64::GLDFF1D_REAL:
9357
0
    case AArch64::GLDFF1D_SCALED_REAL:
9358
0
    case AArch64::GLDFF1D_SXTW_REAL:
9359
0
    case AArch64::GLDFF1D_SXTW_SCALED_REAL:
9360
0
    case AArch64::GLDFF1D_UXTW_REAL:
9361
0
    case AArch64::GLDFF1D_UXTW_SCALED_REAL:
9362
0
    case AArch64::GLDFF1H_D_REAL:
9363
0
    case AArch64::GLDFF1H_D_SCALED_REAL:
9364
0
    case AArch64::GLDFF1H_D_SXTW_REAL:
9365
0
    case AArch64::GLDFF1H_D_SXTW_SCALED_REAL:
9366
0
    case AArch64::GLDFF1H_D_UXTW_REAL:
9367
0
    case AArch64::GLDFF1H_D_UXTW_SCALED_REAL:
9368
0
    case AArch64::GLDFF1H_S_SXTW_REAL:
9369
0
    case AArch64::GLDFF1H_S_SXTW_SCALED_REAL:
9370
0
    case AArch64::GLDFF1H_S_UXTW_REAL:
9371
0
    case AArch64::GLDFF1H_S_UXTW_SCALED_REAL:
9372
0
    case AArch64::GLDFF1SB_D_REAL:
9373
0
    case AArch64::GLDFF1SB_D_SXTW_REAL:
9374
0
    case AArch64::GLDFF1SB_D_UXTW_REAL:
9375
0
    case AArch64::GLDFF1SB_S_SXTW_REAL:
9376
0
    case AArch64::GLDFF1SB_S_UXTW_REAL:
9377
0
    case AArch64::GLDFF1SH_D_REAL:
9378
0
    case AArch64::GLDFF1SH_D_SCALED_REAL:
9379
0
    case AArch64::GLDFF1SH_D_SXTW_REAL:
9380
0
    case AArch64::GLDFF1SH_D_SXTW_SCALED_REAL:
9381
0
    case AArch64::GLDFF1SH_D_UXTW_REAL:
9382
0
    case AArch64::GLDFF1SH_D_UXTW_SCALED_REAL:
9383
0
    case AArch64::GLDFF1SH_S_SXTW_REAL:
9384
0
    case AArch64::GLDFF1SH_S_SXTW_SCALED_REAL:
9385
0
    case AArch64::GLDFF1SH_S_UXTW_REAL:
9386
0
    case AArch64::GLDFF1SH_S_UXTW_SCALED_REAL:
9387
0
    case AArch64::GLDFF1SW_D_REAL:
9388
0
    case AArch64::GLDFF1SW_D_SCALED_REAL:
9389
0
    case AArch64::GLDFF1SW_D_SXTW_REAL:
9390
0
    case AArch64::GLDFF1SW_D_SXTW_SCALED_REAL:
9391
0
    case AArch64::GLDFF1SW_D_UXTW_REAL:
9392
0
    case AArch64::GLDFF1SW_D_UXTW_SCALED_REAL:
9393
0
    case AArch64::GLDFF1W_D_REAL:
9394
0
    case AArch64::GLDFF1W_D_SCALED_REAL:
9395
0
    case AArch64::GLDFF1W_D_SXTW_REAL:
9396
0
    case AArch64::GLDFF1W_D_SXTW_SCALED_REAL:
9397
0
    case AArch64::GLDFF1W_D_UXTW_REAL:
9398
0
    case AArch64::GLDFF1W_D_UXTW_SCALED_REAL:
9399
0
    case AArch64::GLDFF1W_SXTW_REAL:
9400
0
    case AArch64::GLDFF1W_SXTW_SCALED_REAL:
9401
0
    case AArch64::GLDFF1W_UXTW_REAL:
9402
0
    case AArch64::GLDFF1W_UXTW_SCALED_REAL:
9403
0
    case AArch64::SST1B_D:
9404
0
    case AArch64::SST1B_D_SXTW:
9405
0
    case AArch64::SST1B_D_UXTW:
9406
0
    case AArch64::SST1B_S_SXTW:
9407
0
    case AArch64::SST1B_S_UXTW:
9408
0
    case AArch64::SST1D:
9409
0
    case AArch64::SST1D_SCALED:
9410
0
    case AArch64::SST1D_SXTW:
9411
0
    case AArch64::SST1D_SXTW_SCALED:
9412
0
    case AArch64::SST1D_UXTW:
9413
0
    case AArch64::SST1D_UXTW_SCALED:
9414
0
    case AArch64::SST1H_D:
9415
0
    case AArch64::SST1H_D_SCALED:
9416
0
    case AArch64::SST1H_D_SXTW:
9417
0
    case AArch64::SST1H_D_SXTW_SCALED:
9418
0
    case AArch64::SST1H_D_UXTW:
9419
0
    case AArch64::SST1H_D_UXTW_SCALED:
9420
0
    case AArch64::SST1H_S_SXTW:
9421
0
    case AArch64::SST1H_S_SXTW_SCALED:
9422
0
    case AArch64::SST1H_S_UXTW:
9423
0
    case AArch64::SST1H_S_UXTW_SCALED:
9424
0
    case AArch64::SST1W_D:
9425
0
    case AArch64::SST1W_D_SCALED:
9426
0
    case AArch64::SST1W_D_SXTW:
9427
0
    case AArch64::SST1W_D_SXTW_SCALED:
9428
0
    case AArch64::SST1W_D_UXTW:
9429
0
    case AArch64::SST1W_D_UXTW_SCALED:
9430
0
    case AArch64::SST1W_SXTW:
9431
0
    case AArch64::SST1W_SXTW_SCALED:
9432
0
    case AArch64::SST1W_UXTW:
9433
0
    case AArch64::SST1W_UXTW_SCALED: {
9434
      // op: Pg
9435
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9436
0
      op &= UINT64_C(7);
9437
0
      op <<= 10;
9438
0
      Value |= op;
9439
      // op: Rn
9440
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9441
0
      op &= UINT64_C(31);
9442
0
      op <<= 5;
9443
0
      Value |= op;
9444
      // op: Zm
9445
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9446
0
      op &= UINT64_C(31);
9447
0
      op <<= 16;
9448
0
      Value |= op;
9449
      // op: Zt
9450
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9451
0
      op &= UINT64_C(31);
9452
0
      Value |= op;
9453
0
      break;
9454
0
    }
9455
0
    case AArch64::PRFB_D_SCALED:
9456
0
    case AArch64::PRFB_D_SXTW_SCALED:
9457
0
    case AArch64::PRFB_D_UXTW_SCALED:
9458
0
    case AArch64::PRFB_S_SXTW_SCALED:
9459
0
    case AArch64::PRFB_S_UXTW_SCALED:
9460
0
    case AArch64::PRFD_D_SCALED:
9461
0
    case AArch64::PRFD_D_SXTW_SCALED:
9462
0
    case AArch64::PRFD_D_UXTW_SCALED:
9463
0
    case AArch64::PRFD_S_SXTW_SCALED:
9464
0
    case AArch64::PRFD_S_UXTW_SCALED:
9465
0
    case AArch64::PRFH_D_SCALED:
9466
0
    case AArch64::PRFH_D_SXTW_SCALED:
9467
0
    case AArch64::PRFH_D_UXTW_SCALED:
9468
0
    case AArch64::PRFH_S_SXTW_SCALED:
9469
0
    case AArch64::PRFH_S_UXTW_SCALED:
9470
0
    case AArch64::PRFW_D_SCALED:
9471
0
    case AArch64::PRFW_D_SXTW_SCALED:
9472
0
    case AArch64::PRFW_D_UXTW_SCALED:
9473
0
    case AArch64::PRFW_S_SXTW_SCALED:
9474
0
    case AArch64::PRFW_S_UXTW_SCALED: {
9475
      // op: Pg
9476
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9477
0
      op &= UINT64_C(7);
9478
0
      op <<= 10;
9479
0
      Value |= op;
9480
      // op: Rn
9481
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9482
0
      op &= UINT64_C(31);
9483
0
      op <<= 5;
9484
0
      Value |= op;
9485
      // op: Zm
9486
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9487
0
      op &= UINT64_C(31);
9488
0
      op <<= 16;
9489
0
      Value |= op;
9490
      // op: prfop
9491
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9492
0
      op &= UINT64_C(15);
9493
0
      Value |= op;
9494
0
      break;
9495
0
    }
9496
0
    case AArch64::LD1B_D_IMM:
9497
0
    case AArch64::LD1B_H_IMM:
9498
0
    case AArch64::LD1B_IMM:
9499
0
    case AArch64::LD1B_S_IMM:
9500
0
    case AArch64::LD1D_IMM:
9501
0
    case AArch64::LD1H_D_IMM:
9502
0
    case AArch64::LD1H_IMM:
9503
0
    case AArch64::LD1H_S_IMM:
9504
0
    case AArch64::LD1SB_D_IMM:
9505
0
    case AArch64::LD1SB_H_IMM:
9506
0
    case AArch64::LD1SB_S_IMM:
9507
0
    case AArch64::LD1SH_D_IMM:
9508
0
    case AArch64::LD1SH_S_IMM:
9509
0
    case AArch64::LD1SW_D_IMM:
9510
0
    case AArch64::LD1W_D_IMM:
9511
0
    case AArch64::LD1W_IMM:
9512
0
    case AArch64::LDNF1B_D_IMM_REAL:
9513
0
    case AArch64::LDNF1B_H_IMM_REAL:
9514
0
    case AArch64::LDNF1B_IMM_REAL:
9515
0
    case AArch64::LDNF1B_S_IMM_REAL:
9516
0
    case AArch64::LDNF1D_IMM_REAL:
9517
0
    case AArch64::LDNF1H_D_IMM_REAL:
9518
0
    case AArch64::LDNF1H_IMM_REAL:
9519
0
    case AArch64::LDNF1H_S_IMM_REAL:
9520
0
    case AArch64::LDNF1SB_D_IMM_REAL:
9521
0
    case AArch64::LDNF1SB_H_IMM_REAL:
9522
0
    case AArch64::LDNF1SB_S_IMM_REAL:
9523
0
    case AArch64::LDNF1SH_D_IMM_REAL:
9524
0
    case AArch64::LDNF1SH_S_IMM_REAL:
9525
0
    case AArch64::LDNF1SW_D_IMM_REAL:
9526
0
    case AArch64::LDNF1W_D_IMM_REAL:
9527
0
    case AArch64::LDNF1W_IMM_REAL:
9528
0
    case AArch64::ST1B_D_IMM:
9529
0
    case AArch64::ST1B_H_IMM:
9530
0
    case AArch64::ST1B_IMM:
9531
0
    case AArch64::ST1B_S_IMM:
9532
0
    case AArch64::ST1D_IMM:
9533
0
    case AArch64::ST1D_Q_IMM:
9534
0
    case AArch64::ST1H_D_IMM:
9535
0
    case AArch64::ST1H_IMM:
9536
0
    case AArch64::ST1H_S_IMM:
9537
0
    case AArch64::ST1W_D_IMM:
9538
0
    case AArch64::ST1W_IMM:
9539
0
    case AArch64::ST1W_Q_IMM:
9540
0
    case AArch64::ST2B_IMM:
9541
0
    case AArch64::ST2D_IMM:
9542
0
    case AArch64::ST2H_IMM:
9543
0
    case AArch64::ST2W_IMM:
9544
0
    case AArch64::ST3B_IMM:
9545
0
    case AArch64::ST3D_IMM:
9546
0
    case AArch64::ST3H_IMM:
9547
0
    case AArch64::ST3W_IMM:
9548
0
    case AArch64::ST4B_IMM:
9549
0
    case AArch64::ST4D_IMM:
9550
0
    case AArch64::ST4H_IMM:
9551
0
    case AArch64::ST4W_IMM:
9552
0
    case AArch64::STNT1B_ZRI:
9553
0
    case AArch64::STNT1D_ZRI:
9554
0
    case AArch64::STNT1H_ZRI:
9555
0
    case AArch64::STNT1W_ZRI: {
9556
      // op: Pg
9557
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9558
0
      op &= UINT64_C(7);
9559
0
      op <<= 10;
9560
0
      Value |= op;
9561
      // op: Rn
9562
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9563
0
      op &= UINT64_C(31);
9564
0
      op <<= 5;
9565
0
      Value |= op;
9566
      // op: Zt
9567
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9568
0
      op &= UINT64_C(31);
9569
0
      Value |= op;
9570
      // op: imm4
9571
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9572
0
      op &= UINT64_C(15);
9573
0
      op <<= 16;
9574
0
      Value |= op;
9575
0
      break;
9576
0
    }
9577
0
    case AArch64::LD1RB_D_IMM:
9578
0
    case AArch64::LD1RB_H_IMM:
9579
0
    case AArch64::LD1RB_IMM:
9580
0
    case AArch64::LD1RB_S_IMM:
9581
0
    case AArch64::LD1RD_IMM:
9582
0
    case AArch64::LD1RH_D_IMM:
9583
0
    case AArch64::LD1RH_IMM:
9584
0
    case AArch64::LD1RH_S_IMM:
9585
0
    case AArch64::LD1RSB_D_IMM:
9586
0
    case AArch64::LD1RSB_H_IMM:
9587
0
    case AArch64::LD1RSB_S_IMM:
9588
0
    case AArch64::LD1RSH_D_IMM:
9589
0
    case AArch64::LD1RSH_S_IMM:
9590
0
    case AArch64::LD1RSW_IMM:
9591
0
    case AArch64::LD1RW_D_IMM:
9592
0
    case AArch64::LD1RW_IMM: {
9593
      // op: Pg
9594
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9595
0
      op &= UINT64_C(7);
9596
0
      op <<= 10;
9597
0
      Value |= op;
9598
      // op: Rn
9599
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9600
0
      op &= UINT64_C(31);
9601
0
      op <<= 5;
9602
0
      Value |= op;
9603
      // op: Zt
9604
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9605
0
      op &= UINT64_C(31);
9606
0
      Value |= op;
9607
      // op: imm6
9608
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9609
0
      op &= UINT64_C(63);
9610
0
      op <<= 16;
9611
0
      Value |= op;
9612
0
      break;
9613
0
    }
9614
0
    case AArch64::ANDV_VPZ_B:
9615
0
    case AArch64::ANDV_VPZ_D:
9616
0
    case AArch64::ANDV_VPZ_H:
9617
0
    case AArch64::ANDV_VPZ_S:
9618
0
    case AArch64::EORV_VPZ_B:
9619
0
    case AArch64::EORV_VPZ_D:
9620
0
    case AArch64::EORV_VPZ_H:
9621
0
    case AArch64::EORV_VPZ_S:
9622
0
    case AArch64::LASTA_VPZ_B:
9623
0
    case AArch64::LASTA_VPZ_D:
9624
0
    case AArch64::LASTA_VPZ_H:
9625
0
    case AArch64::LASTA_VPZ_S:
9626
0
    case AArch64::LASTB_VPZ_B:
9627
0
    case AArch64::LASTB_VPZ_D:
9628
0
    case AArch64::LASTB_VPZ_H:
9629
0
    case AArch64::LASTB_VPZ_S:
9630
0
    case AArch64::ORV_VPZ_B:
9631
0
    case AArch64::ORV_VPZ_D:
9632
0
    case AArch64::ORV_VPZ_H:
9633
0
    case AArch64::ORV_VPZ_S:
9634
0
    case AArch64::SADDV_VPZ_B:
9635
0
    case AArch64::SADDV_VPZ_H:
9636
0
    case AArch64::SADDV_VPZ_S:
9637
0
    case AArch64::SMAXV_VPZ_B:
9638
0
    case AArch64::SMAXV_VPZ_D:
9639
0
    case AArch64::SMAXV_VPZ_H:
9640
0
    case AArch64::SMAXV_VPZ_S:
9641
0
    case AArch64::SMINV_VPZ_B:
9642
0
    case AArch64::SMINV_VPZ_D:
9643
0
    case AArch64::SMINV_VPZ_H:
9644
0
    case AArch64::SMINV_VPZ_S:
9645
0
    case AArch64::UADDV_VPZ_B:
9646
0
    case AArch64::UADDV_VPZ_D:
9647
0
    case AArch64::UADDV_VPZ_H:
9648
0
    case AArch64::UADDV_VPZ_S:
9649
0
    case AArch64::UMAXV_VPZ_B:
9650
0
    case AArch64::UMAXV_VPZ_D:
9651
0
    case AArch64::UMAXV_VPZ_H:
9652
0
    case AArch64::UMAXV_VPZ_S:
9653
0
    case AArch64::UMINV_VPZ_B:
9654
0
    case AArch64::UMINV_VPZ_D:
9655
0
    case AArch64::UMINV_VPZ_H:
9656
0
    case AArch64::UMINV_VPZ_S: {
9657
      // op: Pg
9658
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9659
0
      op &= UINT64_C(7);
9660
0
      op <<= 10;
9661
0
      Value |= op;
9662
      // op: Vd
9663
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9664
0
      op &= UINT64_C(31);
9665
0
      Value |= op;
9666
      // op: Zn
9667
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9668
0
      op &= UINT64_C(31);
9669
0
      op <<= 5;
9670
0
      Value |= op;
9671
0
      break;
9672
0
    }
9673
0
    case AArch64::CLASTA_VPZ_B:
9674
0
    case AArch64::CLASTA_VPZ_D:
9675
0
    case AArch64::CLASTA_VPZ_H:
9676
0
    case AArch64::CLASTA_VPZ_S:
9677
0
    case AArch64::CLASTB_VPZ_B:
9678
0
    case AArch64::CLASTB_VPZ_D:
9679
0
    case AArch64::CLASTB_VPZ_H:
9680
0
    case AArch64::CLASTB_VPZ_S:
9681
0
    case AArch64::FADDA_VPZ_D:
9682
0
    case AArch64::FADDA_VPZ_H:
9683
0
    case AArch64::FADDA_VPZ_S: {
9684
      // op: Pg
9685
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9686
0
      op &= UINT64_C(7);
9687
0
      op <<= 10;
9688
0
      Value |= op;
9689
      // op: Vdn
9690
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9691
0
      op &= UINT64_C(31);
9692
0
      Value |= op;
9693
      // op: Zm
9694
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9695
0
      op &= UINT64_C(31);
9696
0
      op <<= 5;
9697
0
      Value |= op;
9698
0
      break;
9699
0
    }
9700
0
    case AArch64::FMAD_ZPmZZ_D:
9701
0
    case AArch64::FMAD_ZPmZZ_H:
9702
0
    case AArch64::FMAD_ZPmZZ_S:
9703
0
    case AArch64::FMSB_ZPmZZ_D:
9704
0
    case AArch64::FMSB_ZPmZZ_H:
9705
0
    case AArch64::FMSB_ZPmZZ_S:
9706
0
    case AArch64::FNMAD_ZPmZZ_D:
9707
0
    case AArch64::FNMAD_ZPmZZ_H:
9708
0
    case AArch64::FNMAD_ZPmZZ_S:
9709
0
    case AArch64::FNMSB_ZPmZZ_D:
9710
0
    case AArch64::FNMSB_ZPmZZ_H:
9711
0
    case AArch64::FNMSB_ZPmZZ_S: {
9712
      // op: Pg
9713
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9714
0
      op &= UINT64_C(7);
9715
0
      op <<= 10;
9716
0
      Value |= op;
9717
      // op: Za
9718
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
9719
0
      op &= UINT64_C(31);
9720
0
      op <<= 16;
9721
0
      Value |= op;
9722
      // op: Zdn
9723
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9724
0
      op &= UINT64_C(31);
9725
0
      Value |= op;
9726
      // op: Zm
9727
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9728
0
      op &= UINT64_C(31);
9729
0
      op <<= 5;
9730
0
      Value |= op;
9731
0
      break;
9732
0
    }
9733
0
    case AArch64::COMPACT_ZPZ_D:
9734
0
    case AArch64::COMPACT_ZPZ_S:
9735
0
    case AArch64::MOVPRFX_ZPzZ_B:
9736
0
    case AArch64::MOVPRFX_ZPzZ_D:
9737
0
    case AArch64::MOVPRFX_ZPzZ_H:
9738
0
    case AArch64::MOVPRFX_ZPzZ_S: {
9739
      // op: Pg
9740
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9741
0
      op &= UINT64_C(7);
9742
0
      op <<= 10;
9743
0
      Value |= op;
9744
      // op: Zd
9745
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9746
0
      op &= UINT64_C(31);
9747
0
      Value |= op;
9748
      // op: Zn
9749
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9750
0
      op &= UINT64_C(31);
9751
0
      op <<= 5;
9752
0
      Value |= op;
9753
0
      break;
9754
0
    }
9755
0
    case AArch64::BFMLA_ZPmZZ:
9756
0
    case AArch64::BFMLS_ZPmZZ:
9757
0
    case AArch64::FMLA_ZPmZZ_D:
9758
0
    case AArch64::FMLA_ZPmZZ_H:
9759
0
    case AArch64::FMLA_ZPmZZ_S:
9760
0
    case AArch64::FMLS_ZPmZZ_D:
9761
0
    case AArch64::FMLS_ZPmZZ_H:
9762
0
    case AArch64::FMLS_ZPmZZ_S:
9763
0
    case AArch64::FNMLA_ZPmZZ_D:
9764
0
    case AArch64::FNMLA_ZPmZZ_H:
9765
0
    case AArch64::FNMLA_ZPmZZ_S:
9766
0
    case AArch64::FNMLS_ZPmZZ_D:
9767
0
    case AArch64::FNMLS_ZPmZZ_H:
9768
0
    case AArch64::FNMLS_ZPmZZ_S:
9769
0
    case AArch64::MLA_ZPmZZ_B:
9770
0
    case AArch64::MLA_ZPmZZ_D:
9771
0
    case AArch64::MLA_ZPmZZ_H:
9772
0
    case AArch64::MLA_ZPmZZ_S:
9773
0
    case AArch64::MLS_ZPmZZ_B:
9774
0
    case AArch64::MLS_ZPmZZ_D:
9775
0
    case AArch64::MLS_ZPmZZ_H:
9776
0
    case AArch64::MLS_ZPmZZ_S: {
9777
      // op: Pg
9778
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9779
0
      op &= UINT64_C(7);
9780
0
      op <<= 10;
9781
0
      Value |= op;
9782
      // op: Zda
9783
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9784
0
      op &= UINT64_C(31);
9785
0
      Value |= op;
9786
      // op: Zm
9787
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
9788
0
      op &= UINT64_C(31);
9789
0
      op <<= 16;
9790
0
      Value |= op;
9791
      // op: Zn
9792
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9793
0
      op &= UINT64_C(31);
9794
0
      op <<= 5;
9795
0
      Value |= op;
9796
0
      break;
9797
0
    }
9798
0
    case AArch64::MAD_ZPmZZ_B:
9799
0
    case AArch64::MAD_ZPmZZ_D:
9800
0
    case AArch64::MAD_ZPmZZ_H:
9801
0
    case AArch64::MAD_ZPmZZ_S:
9802
0
    case AArch64::MSB_ZPmZZ_B:
9803
0
    case AArch64::MSB_ZPmZZ_D:
9804
0
    case AArch64::MSB_ZPmZZ_H:
9805
0
    case AArch64::MSB_ZPmZZ_S: {
9806
      // op: Pg
9807
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9808
0
      op &= UINT64_C(7);
9809
0
      op <<= 10;
9810
0
      Value |= op;
9811
      // op: Zdn
9812
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9813
0
      op &= UINT64_C(31);
9814
0
      Value |= op;
9815
      // op: Za
9816
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
9817
0
      op &= UINT64_C(31);
9818
0
      op <<= 5;
9819
0
      Value |= op;
9820
      // op: Zm
9821
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9822
0
      op &= UINT64_C(31);
9823
0
      op <<= 16;
9824
0
      Value |= op;
9825
0
      break;
9826
0
    }
9827
0
    case AArch64::ADD_ZPmZ_B:
9828
0
    case AArch64::ADD_ZPmZ_CPA:
9829
0
    case AArch64::ADD_ZPmZ_D:
9830
0
    case AArch64::ADD_ZPmZ_H:
9831
0
    case AArch64::ADD_ZPmZ_S:
9832
0
    case AArch64::AND_ZPmZ_B:
9833
0
    case AArch64::AND_ZPmZ_D:
9834
0
    case AArch64::AND_ZPmZ_H:
9835
0
    case AArch64::AND_ZPmZ_S:
9836
0
    case AArch64::ASRR_ZPmZ_B:
9837
0
    case AArch64::ASRR_ZPmZ_D:
9838
0
    case AArch64::ASRR_ZPmZ_H:
9839
0
    case AArch64::ASRR_ZPmZ_S:
9840
0
    case AArch64::ASR_WIDE_ZPmZ_B:
9841
0
    case AArch64::ASR_WIDE_ZPmZ_H:
9842
0
    case AArch64::ASR_WIDE_ZPmZ_S:
9843
0
    case AArch64::ASR_ZPmZ_B:
9844
0
    case AArch64::ASR_ZPmZ_D:
9845
0
    case AArch64::ASR_ZPmZ_H:
9846
0
    case AArch64::ASR_ZPmZ_S:
9847
0
    case AArch64::BFADD_ZPmZZ:
9848
0
    case AArch64::BFMAXNM_ZPmZZ:
9849
0
    case AArch64::BFMAX_ZPmZZ:
9850
0
    case AArch64::BFMINNM_ZPmZZ:
9851
0
    case AArch64::BFMIN_ZPmZZ:
9852
0
    case AArch64::BFMUL_ZPmZZ:
9853
0
    case AArch64::BFSUB_ZPmZZ:
9854
0
    case AArch64::BIC_ZPmZ_B:
9855
0
    case AArch64::BIC_ZPmZ_D:
9856
0
    case AArch64::BIC_ZPmZ_H:
9857
0
    case AArch64::BIC_ZPmZ_S:
9858
0
    case AArch64::CLASTA_ZPZ_B:
9859
0
    case AArch64::CLASTA_ZPZ_D:
9860
0
    case AArch64::CLASTA_ZPZ_H:
9861
0
    case AArch64::CLASTA_ZPZ_S:
9862
0
    case AArch64::CLASTB_ZPZ_B:
9863
0
    case AArch64::CLASTB_ZPZ_D:
9864
0
    case AArch64::CLASTB_ZPZ_H:
9865
0
    case AArch64::CLASTB_ZPZ_S:
9866
0
    case AArch64::EOR_ZPmZ_B:
9867
0
    case AArch64::EOR_ZPmZ_D:
9868
0
    case AArch64::EOR_ZPmZ_H:
9869
0
    case AArch64::EOR_ZPmZ_S:
9870
0
    case AArch64::FABD_ZPmZ_D:
9871
0
    case AArch64::FABD_ZPmZ_H:
9872
0
    case AArch64::FABD_ZPmZ_S:
9873
0
    case AArch64::FADD_ZPmZ_D:
9874
0
    case AArch64::FADD_ZPmZ_H:
9875
0
    case AArch64::FADD_ZPmZ_S:
9876
0
    case AArch64::FAMAX_ZPmZ_D:
9877
0
    case AArch64::FAMAX_ZPmZ_H:
9878
0
    case AArch64::FAMAX_ZPmZ_S:
9879
0
    case AArch64::FAMIN_ZPmZ_D:
9880
0
    case AArch64::FAMIN_ZPmZ_H:
9881
0
    case AArch64::FAMIN_ZPmZ_S:
9882
0
    case AArch64::FDIVR_ZPmZ_D:
9883
0
    case AArch64::FDIVR_ZPmZ_H:
9884
0
    case AArch64::FDIVR_ZPmZ_S:
9885
0
    case AArch64::FDIV_ZPmZ_D:
9886
0
    case AArch64::FDIV_ZPmZ_H:
9887
0
    case AArch64::FDIV_ZPmZ_S:
9888
0
    case AArch64::FMAXNM_ZPmZ_D:
9889
0
    case AArch64::FMAXNM_ZPmZ_H:
9890
0
    case AArch64::FMAXNM_ZPmZ_S:
9891
0
    case AArch64::FMAX_ZPmZ_D:
9892
0
    case AArch64::FMAX_ZPmZ_H:
9893
0
    case AArch64::FMAX_ZPmZ_S:
9894
0
    case AArch64::FMINNM_ZPmZ_D:
9895
0
    case AArch64::FMINNM_ZPmZ_H:
9896
0
    case AArch64::FMINNM_ZPmZ_S:
9897
0
    case AArch64::FMIN_ZPmZ_D:
9898
0
    case AArch64::FMIN_ZPmZ_H:
9899
0
    case AArch64::FMIN_ZPmZ_S:
9900
0
    case AArch64::FMULX_ZPmZ_D:
9901
0
    case AArch64::FMULX_ZPmZ_H:
9902
0
    case AArch64::FMULX_ZPmZ_S:
9903
0
    case AArch64::FMUL_ZPmZ_D:
9904
0
    case AArch64::FMUL_ZPmZ_H:
9905
0
    case AArch64::FMUL_ZPmZ_S:
9906
0
    case AArch64::FSCALE_ZPmZ_D:
9907
0
    case AArch64::FSCALE_ZPmZ_H:
9908
0
    case AArch64::FSCALE_ZPmZ_S:
9909
0
    case AArch64::FSUBR_ZPmZ_D:
9910
0
    case AArch64::FSUBR_ZPmZ_H:
9911
0
    case AArch64::FSUBR_ZPmZ_S:
9912
0
    case AArch64::FSUB_ZPmZ_D:
9913
0
    case AArch64::FSUB_ZPmZ_H:
9914
0
    case AArch64::FSUB_ZPmZ_S:
9915
0
    case AArch64::LSLR_ZPmZ_B:
9916
0
    case AArch64::LSLR_ZPmZ_D:
9917
0
    case AArch64::LSLR_ZPmZ_H:
9918
0
    case AArch64::LSLR_ZPmZ_S:
9919
0
    case AArch64::LSL_WIDE_ZPmZ_B:
9920
0
    case AArch64::LSL_WIDE_ZPmZ_H:
9921
0
    case AArch64::LSL_WIDE_ZPmZ_S:
9922
0
    case AArch64::LSL_ZPmZ_B:
9923
0
    case AArch64::LSL_ZPmZ_D:
9924
0
    case AArch64::LSL_ZPmZ_H:
9925
0
    case AArch64::LSL_ZPmZ_S:
9926
0
    case AArch64::LSRR_ZPmZ_B:
9927
0
    case AArch64::LSRR_ZPmZ_D:
9928
0
    case AArch64::LSRR_ZPmZ_H:
9929
0
    case AArch64::LSRR_ZPmZ_S:
9930
0
    case AArch64::LSR_WIDE_ZPmZ_B:
9931
0
    case AArch64::LSR_WIDE_ZPmZ_H:
9932
0
    case AArch64::LSR_WIDE_ZPmZ_S:
9933
0
    case AArch64::LSR_ZPmZ_B:
9934
0
    case AArch64::LSR_ZPmZ_D:
9935
0
    case AArch64::LSR_ZPmZ_H:
9936
0
    case AArch64::LSR_ZPmZ_S:
9937
0
    case AArch64::MUL_ZPmZ_B:
9938
0
    case AArch64::MUL_ZPmZ_D:
9939
0
    case AArch64::MUL_ZPmZ_H:
9940
0
    case AArch64::MUL_ZPmZ_S:
9941
0
    case AArch64::ORR_ZPmZ_B:
9942
0
    case AArch64::ORR_ZPmZ_D:
9943
0
    case AArch64::ORR_ZPmZ_H:
9944
0
    case AArch64::ORR_ZPmZ_S:
9945
0
    case AArch64::SABD_ZPmZ_B:
9946
0
    case AArch64::SABD_ZPmZ_D:
9947
0
    case AArch64::SABD_ZPmZ_H:
9948
0
    case AArch64::SABD_ZPmZ_S:
9949
0
    case AArch64::SDIVR_ZPmZ_D:
9950
0
    case AArch64::SDIVR_ZPmZ_S:
9951
0
    case AArch64::SDIV_ZPmZ_D:
9952
0
    case AArch64::SDIV_ZPmZ_S:
9953
0
    case AArch64::SMAX_ZPmZ_B:
9954
0
    case AArch64::SMAX_ZPmZ_D:
9955
0
    case AArch64::SMAX_ZPmZ_H:
9956
0
    case AArch64::SMAX_ZPmZ_S:
9957
0
    case AArch64::SMIN_ZPmZ_B:
9958
0
    case AArch64::SMIN_ZPmZ_D:
9959
0
    case AArch64::SMIN_ZPmZ_H:
9960
0
    case AArch64::SMIN_ZPmZ_S:
9961
0
    case AArch64::SMULH_ZPmZ_B:
9962
0
    case AArch64::SMULH_ZPmZ_D:
9963
0
    case AArch64::SMULH_ZPmZ_H:
9964
0
    case AArch64::SMULH_ZPmZ_S:
9965
0
    case AArch64::SPLICE_ZPZ_B:
9966
0
    case AArch64::SPLICE_ZPZ_D:
9967
0
    case AArch64::SPLICE_ZPZ_H:
9968
0
    case AArch64::SPLICE_ZPZ_S:
9969
0
    case AArch64::SUBR_ZPmZ_B:
9970
0
    case AArch64::SUBR_ZPmZ_D:
9971
0
    case AArch64::SUBR_ZPmZ_H:
9972
0
    case AArch64::SUBR_ZPmZ_S:
9973
0
    case AArch64::SUB_ZPmZ_B:
9974
0
    case AArch64::SUB_ZPmZ_CPA:
9975
0
    case AArch64::SUB_ZPmZ_D:
9976
0
    case AArch64::SUB_ZPmZ_H:
9977
0
    case AArch64::SUB_ZPmZ_S:
9978
0
    case AArch64::UABD_ZPmZ_B:
9979
0
    case AArch64::UABD_ZPmZ_D:
9980
0
    case AArch64::UABD_ZPmZ_H:
9981
0
    case AArch64::UABD_ZPmZ_S:
9982
0
    case AArch64::UDIVR_ZPmZ_D:
9983
0
    case AArch64::UDIVR_ZPmZ_S:
9984
0
    case AArch64::UDIV_ZPmZ_D:
9985
0
    case AArch64::UDIV_ZPmZ_S:
9986
0
    case AArch64::UMAX_ZPmZ_B:
9987
0
    case AArch64::UMAX_ZPmZ_D:
9988
0
    case AArch64::UMAX_ZPmZ_H:
9989
0
    case AArch64::UMAX_ZPmZ_S:
9990
0
    case AArch64::UMIN_ZPmZ_B:
9991
0
    case AArch64::UMIN_ZPmZ_D:
9992
0
    case AArch64::UMIN_ZPmZ_H:
9993
0
    case AArch64::UMIN_ZPmZ_S:
9994
0
    case AArch64::UMULH_ZPmZ_B:
9995
0
    case AArch64::UMULH_ZPmZ_D:
9996
0
    case AArch64::UMULH_ZPmZ_H:
9997
0
    case AArch64::UMULH_ZPmZ_S: {
9998
      // op: Pg
9999
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10000
0
      op &= UINT64_C(7);
10001
0
      op <<= 10;
10002
0
      Value |= op;
10003
      // op: Zdn
10004
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10005
0
      op &= UINT64_C(31);
10006
0
      Value |= op;
10007
      // op: Zm
10008
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10009
0
      op &= UINT64_C(31);
10010
0
      op <<= 5;
10011
0
      Value |= op;
10012
0
      break;
10013
0
    }
10014
0
    case AArch64::FADD_ZPmI_D:
10015
0
    case AArch64::FADD_ZPmI_H:
10016
0
    case AArch64::FADD_ZPmI_S:
10017
0
    case AArch64::FMAXNM_ZPmI_D:
10018
0
    case AArch64::FMAXNM_ZPmI_H:
10019
0
    case AArch64::FMAXNM_ZPmI_S:
10020
0
    case AArch64::FMAX_ZPmI_D:
10021
0
    case AArch64::FMAX_ZPmI_H:
10022
0
    case AArch64::FMAX_ZPmI_S:
10023
0
    case AArch64::FMINNM_ZPmI_D:
10024
0
    case AArch64::FMINNM_ZPmI_H:
10025
0
    case AArch64::FMINNM_ZPmI_S:
10026
0
    case AArch64::FMIN_ZPmI_D:
10027
0
    case AArch64::FMIN_ZPmI_H:
10028
0
    case AArch64::FMIN_ZPmI_S:
10029
0
    case AArch64::FMUL_ZPmI_D:
10030
0
    case AArch64::FMUL_ZPmI_H:
10031
0
    case AArch64::FMUL_ZPmI_S:
10032
0
    case AArch64::FSUBR_ZPmI_D:
10033
0
    case AArch64::FSUBR_ZPmI_H:
10034
0
    case AArch64::FSUBR_ZPmI_S:
10035
0
    case AArch64::FSUB_ZPmI_D:
10036
0
    case AArch64::FSUB_ZPmI_H:
10037
0
    case AArch64::FSUB_ZPmI_S: {
10038
      // op: Pg
10039
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10040
0
      op &= UINT64_C(7);
10041
0
      op <<= 10;
10042
0
      Value |= op;
10043
      // op: Zdn
10044
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10045
0
      op &= UINT64_C(31);
10046
0
      Value |= op;
10047
      // op: i1
10048
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10049
0
      op &= UINT64_C(1);
10050
0
      op <<= 5;
10051
0
      Value |= op;
10052
0
      break;
10053
0
    }
10054
0
    case AArch64::LSL_ZPmI_H:
10055
0
    case AArch64::SQSHLU_ZPmI_H:
10056
0
    case AArch64::SQSHL_ZPmI_H:
10057
0
    case AArch64::UQSHL_ZPmI_H: {
10058
      // op: Pg
10059
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10060
0
      op &= UINT64_C(7);
10061
0
      op <<= 10;
10062
0
      Value |= op;
10063
      // op: Zdn
10064
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10065
0
      op &= UINT64_C(31);
10066
0
      Value |= op;
10067
      // op: imm
10068
0
      op = getVecShiftL16OpValue(MI, 3, Fixups, STI);
10069
0
      op &= UINT64_C(15);
10070
0
      op <<= 5;
10071
0
      Value |= op;
10072
0
      break;
10073
0
    }
10074
0
    case AArch64::LSL_ZPmI_S:
10075
0
    case AArch64::SQSHLU_ZPmI_S:
10076
0
    case AArch64::SQSHL_ZPmI_S:
10077
0
    case AArch64::UQSHL_ZPmI_S: {
10078
      // op: Pg
10079
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10080
0
      op &= UINT64_C(7);
10081
0
      op <<= 10;
10082
0
      Value |= op;
10083
      // op: Zdn
10084
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10085
0
      op &= UINT64_C(31);
10086
0
      Value |= op;
10087
      // op: imm
10088
0
      op = getVecShiftL32OpValue(MI, 3, Fixups, STI);
10089
0
      op &= UINT64_C(31);
10090
0
      op <<= 5;
10091
0
      Value |= op;
10092
0
      break;
10093
0
    }
10094
0
    case AArch64::LSL_ZPmI_D:
10095
0
    case AArch64::SQSHLU_ZPmI_D:
10096
0
    case AArch64::SQSHL_ZPmI_D:
10097
0
    case AArch64::UQSHL_ZPmI_D: {
10098
      // op: Pg
10099
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10100
0
      op &= UINT64_C(7);
10101
0
      op <<= 10;
10102
0
      Value |= op;
10103
      // op: Zdn
10104
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10105
0
      op &= UINT64_C(31);
10106
0
      Value |= op;
10107
      // op: imm
10108
0
      op = getVecShiftL64OpValue(MI, 3, Fixups, STI);
10109
0
      Value |= (op & UINT64_C(32)) << 17;
10110
0
      Value |= (op & UINT64_C(31)) << 5;
10111
0
      break;
10112
0
    }
10113
0
    case AArch64::LSL_ZPmI_B:
10114
0
    case AArch64::SQSHLU_ZPmI_B:
10115
0
    case AArch64::SQSHL_ZPmI_B:
10116
0
    case AArch64::UQSHL_ZPmI_B: {
10117
      // op: Pg
10118
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10119
0
      op &= UINT64_C(7);
10120
0
      op <<= 10;
10121
0
      Value |= op;
10122
      // op: Zdn
10123
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10124
0
      op &= UINT64_C(31);
10125
0
      Value |= op;
10126
      // op: imm
10127
0
      op = getVecShiftL8OpValue(MI, 3, Fixups, STI);
10128
0
      op &= UINT64_C(7);
10129
0
      op <<= 5;
10130
0
      Value |= op;
10131
0
      break;
10132
0
    }
10133
0
    case AArch64::ASRD_ZPmI_H:
10134
0
    case AArch64::ASR_ZPmI_H:
10135
0
    case AArch64::LSR_ZPmI_H:
10136
0
    case AArch64::SRSHR_ZPmI_H:
10137
0
    case AArch64::URSHR_ZPmI_H: {
10138
      // op: Pg
10139
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10140
0
      op &= UINT64_C(7);
10141
0
      op <<= 10;
10142
0
      Value |= op;
10143
      // op: Zdn
10144
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10145
0
      op &= UINT64_C(31);
10146
0
      Value |= op;
10147
      // op: imm
10148
0
      op = getVecShiftR16OpValue(MI, 3, Fixups, STI);
10149
0
      op &= UINT64_C(15);
10150
0
      op <<= 5;
10151
0
      Value |= op;
10152
0
      break;
10153
0
    }
10154
0
    case AArch64::ASRD_ZPmI_S:
10155
0
    case AArch64::ASR_ZPmI_S:
10156
0
    case AArch64::LSR_ZPmI_S:
10157
0
    case AArch64::SRSHR_ZPmI_S:
10158
0
    case AArch64::URSHR_ZPmI_S: {
10159
      // op: Pg
10160
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10161
0
      op &= UINT64_C(7);
10162
0
      op <<= 10;
10163
0
      Value |= op;
10164
      // op: Zdn
10165
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10166
0
      op &= UINT64_C(31);
10167
0
      Value |= op;
10168
      // op: imm
10169
0
      op = getVecShiftR32OpValue(MI, 3, Fixups, STI);
10170
0
      op &= UINT64_C(31);
10171
0
      op <<= 5;
10172
0
      Value |= op;
10173
0
      break;
10174
0
    }
10175
0
    case AArch64::ASRD_ZPmI_D:
10176
0
    case AArch64::ASR_ZPmI_D:
10177
0
    case AArch64::LSR_ZPmI_D:
10178
0
    case AArch64::SRSHR_ZPmI_D:
10179
0
    case AArch64::URSHR_ZPmI_D: {
10180
      // op: Pg
10181
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10182
0
      op &= UINT64_C(7);
10183
0
      op <<= 10;
10184
0
      Value |= op;
10185
      // op: Zdn
10186
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10187
0
      op &= UINT64_C(31);
10188
0
      Value |= op;
10189
      // op: imm
10190
0
      op = getVecShiftR64OpValue(MI, 3, Fixups, STI);
10191
0
      Value |= (op & UINT64_C(32)) << 17;
10192
0
      Value |= (op & UINT64_C(31)) << 5;
10193
0
      break;
10194
0
    }
10195
0
    case AArch64::ASRD_ZPmI_B:
10196
0
    case AArch64::ASR_ZPmI_B:
10197
0
    case AArch64::LSR_ZPmI_B:
10198
0
    case AArch64::SRSHR_ZPmI_B:
10199
0
    case AArch64::URSHR_ZPmI_B: {
10200
      // op: Pg
10201
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10202
0
      op &= UINT64_C(7);
10203
0
      op <<= 10;
10204
0
      Value |= op;
10205
      // op: Zdn
10206
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10207
0
      op &= UINT64_C(31);
10208
0
      Value |= op;
10209
      // op: imm
10210
0
      op = getVecShiftR8OpValue(MI, 3, Fixups, STI);
10211
0
      op &= UINT64_C(7);
10212
0
      op <<= 5;
10213
0
      Value |= op;
10214
0
      break;
10215
0
    }
10216
0
    case AArch64::ADDP_ZPmZ_B:
10217
0
    case AArch64::ADDP_ZPmZ_D:
10218
0
    case AArch64::ADDP_ZPmZ_H:
10219
0
    case AArch64::ADDP_ZPmZ_S:
10220
0
    case AArch64::FADDP_ZPmZZ_D:
10221
0
    case AArch64::FADDP_ZPmZZ_H:
10222
0
    case AArch64::FADDP_ZPmZZ_S:
10223
0
    case AArch64::FMAXNMP_ZPmZZ_D:
10224
0
    case AArch64::FMAXNMP_ZPmZZ_H:
10225
0
    case AArch64::FMAXNMP_ZPmZZ_S:
10226
0
    case AArch64::FMAXP_ZPmZZ_D:
10227
0
    case AArch64::FMAXP_ZPmZZ_H:
10228
0
    case AArch64::FMAXP_ZPmZZ_S:
10229
0
    case AArch64::FMINNMP_ZPmZZ_D:
10230
0
    case AArch64::FMINNMP_ZPmZZ_H:
10231
0
    case AArch64::FMINNMP_ZPmZZ_S:
10232
0
    case AArch64::FMINP_ZPmZZ_D:
10233
0
    case AArch64::FMINP_ZPmZZ_H:
10234
0
    case AArch64::FMINP_ZPmZZ_S:
10235
0
    case AArch64::SHADD_ZPmZ_B:
10236
0
    case AArch64::SHADD_ZPmZ_D:
10237
0
    case AArch64::SHADD_ZPmZ_H:
10238
0
    case AArch64::SHADD_ZPmZ_S:
10239
0
    case AArch64::SHSUBR_ZPmZ_B:
10240
0
    case AArch64::SHSUBR_ZPmZ_D:
10241
0
    case AArch64::SHSUBR_ZPmZ_H:
10242
0
    case AArch64::SHSUBR_ZPmZ_S:
10243
0
    case AArch64::SHSUB_ZPmZ_B:
10244
0
    case AArch64::SHSUB_ZPmZ_D:
10245
0
    case AArch64::SHSUB_ZPmZ_H:
10246
0
    case AArch64::SHSUB_ZPmZ_S:
10247
0
    case AArch64::SMAXP_ZPmZ_B:
10248
0
    case AArch64::SMAXP_ZPmZ_D:
10249
0
    case AArch64::SMAXP_ZPmZ_H:
10250
0
    case AArch64::SMAXP_ZPmZ_S:
10251
0
    case AArch64::SMINP_ZPmZ_B:
10252
0
    case AArch64::SMINP_ZPmZ_D:
10253
0
    case AArch64::SMINP_ZPmZ_H:
10254
0
    case AArch64::SMINP_ZPmZ_S:
10255
0
    case AArch64::SQADD_ZPmZ_B:
10256
0
    case AArch64::SQADD_ZPmZ_D:
10257
0
    case AArch64::SQADD_ZPmZ_H:
10258
0
    case AArch64::SQADD_ZPmZ_S:
10259
0
    case AArch64::SQRSHLR_ZPmZ_B:
10260
0
    case AArch64::SQRSHLR_ZPmZ_D:
10261
0
    case AArch64::SQRSHLR_ZPmZ_H:
10262
0
    case AArch64::SQRSHLR_ZPmZ_S:
10263
0
    case AArch64::SQRSHL_ZPmZ_B:
10264
0
    case AArch64::SQRSHL_ZPmZ_D:
10265
0
    case AArch64::SQRSHL_ZPmZ_H:
10266
0
    case AArch64::SQRSHL_ZPmZ_S:
10267
0
    case AArch64::SQSHLR_ZPmZ_B:
10268
0
    case AArch64::SQSHLR_ZPmZ_D:
10269
0
    case AArch64::SQSHLR_ZPmZ_H:
10270
0
    case AArch64::SQSHLR_ZPmZ_S:
10271
0
    case AArch64::SQSHL_ZPmZ_B:
10272
0
    case AArch64::SQSHL_ZPmZ_D:
10273
0
    case AArch64::SQSHL_ZPmZ_H:
10274
0
    case AArch64::SQSHL_ZPmZ_S:
10275
0
    case AArch64::SQSUBR_ZPmZ_B:
10276
0
    case AArch64::SQSUBR_ZPmZ_D:
10277
0
    case AArch64::SQSUBR_ZPmZ_H:
10278
0
    case AArch64::SQSUBR_ZPmZ_S:
10279
0
    case AArch64::SQSUB_ZPmZ_B:
10280
0
    case AArch64::SQSUB_ZPmZ_D:
10281
0
    case AArch64::SQSUB_ZPmZ_H:
10282
0
    case AArch64::SQSUB_ZPmZ_S:
10283
0
    case AArch64::SRHADD_ZPmZ_B:
10284
0
    case AArch64::SRHADD_ZPmZ_D:
10285
0
    case AArch64::SRHADD_ZPmZ_H:
10286
0
    case AArch64::SRHADD_ZPmZ_S:
10287
0
    case AArch64::SRSHLR_ZPmZ_B:
10288
0
    case AArch64::SRSHLR_ZPmZ_D:
10289
0
    case AArch64::SRSHLR_ZPmZ_H:
10290
0
    case AArch64::SRSHLR_ZPmZ_S:
10291
0
    case AArch64::SRSHL_ZPmZ_B:
10292
0
    case AArch64::SRSHL_ZPmZ_D:
10293
0
    case AArch64::SRSHL_ZPmZ_H:
10294
0
    case AArch64::SRSHL_ZPmZ_S:
10295
0
    case AArch64::SUQADD_ZPmZ_B:
10296
0
    case AArch64::SUQADD_ZPmZ_D:
10297
0
    case AArch64::SUQADD_ZPmZ_H:
10298
0
    case AArch64::SUQADD_ZPmZ_S:
10299
0
    case AArch64::UHADD_ZPmZ_B:
10300
0
    case AArch64::UHADD_ZPmZ_D:
10301
0
    case AArch64::UHADD_ZPmZ_H:
10302
0
    case AArch64::UHADD_ZPmZ_S:
10303
0
    case AArch64::UHSUBR_ZPmZ_B:
10304
0
    case AArch64::UHSUBR_ZPmZ_D:
10305
0
    case AArch64::UHSUBR_ZPmZ_H:
10306
0
    case AArch64::UHSUBR_ZPmZ_S:
10307
0
    case AArch64::UHSUB_ZPmZ_B:
10308
0
    case AArch64::UHSUB_ZPmZ_D:
10309
0
    case AArch64::UHSUB_ZPmZ_H:
10310
0
    case AArch64::UHSUB_ZPmZ_S:
10311
0
    case AArch64::UMAXP_ZPmZ_B:
10312
0
    case AArch64::UMAXP_ZPmZ_D:
10313
0
    case AArch64::UMAXP_ZPmZ_H:
10314
0
    case AArch64::UMAXP_ZPmZ_S:
10315
0
    case AArch64::UMINP_ZPmZ_B:
10316
0
    case AArch64::UMINP_ZPmZ_D:
10317
0
    case AArch64::UMINP_ZPmZ_H:
10318
0
    case AArch64::UMINP_ZPmZ_S:
10319
0
    case AArch64::UQADD_ZPmZ_B:
10320
0
    case AArch64::UQADD_ZPmZ_D:
10321
0
    case AArch64::UQADD_ZPmZ_H:
10322
0
    case AArch64::UQADD_ZPmZ_S:
10323
0
    case AArch64::UQRSHLR_ZPmZ_B:
10324
0
    case AArch64::UQRSHLR_ZPmZ_D:
10325
0
    case AArch64::UQRSHLR_ZPmZ_H:
10326
0
    case AArch64::UQRSHLR_ZPmZ_S:
10327
0
    case AArch64::UQRSHL_ZPmZ_B:
10328
0
    case AArch64::UQRSHL_ZPmZ_D:
10329
0
    case AArch64::UQRSHL_ZPmZ_H:
10330
0
    case AArch64::UQRSHL_ZPmZ_S:
10331
0
    case AArch64::UQSHLR_ZPmZ_B:
10332
0
    case AArch64::UQSHLR_ZPmZ_D:
10333
0
    case AArch64::UQSHLR_ZPmZ_H:
10334
0
    case AArch64::UQSHLR_ZPmZ_S:
10335
0
    case AArch64::UQSHL_ZPmZ_B:
10336
0
    case AArch64::UQSHL_ZPmZ_D:
10337
0
    case AArch64::UQSHL_ZPmZ_H:
10338
0
    case AArch64::UQSHL_ZPmZ_S:
10339
0
    case AArch64::UQSUBR_ZPmZ_B:
10340
0
    case AArch64::UQSUBR_ZPmZ_D:
10341
0
    case AArch64::UQSUBR_ZPmZ_H:
10342
0
    case AArch64::UQSUBR_ZPmZ_S:
10343
0
    case AArch64::UQSUB_ZPmZ_B:
10344
0
    case AArch64::UQSUB_ZPmZ_D:
10345
0
    case AArch64::UQSUB_ZPmZ_H:
10346
0
    case AArch64::UQSUB_ZPmZ_S:
10347
0
    case AArch64::URHADD_ZPmZ_B:
10348
0
    case AArch64::URHADD_ZPmZ_D:
10349
0
    case AArch64::URHADD_ZPmZ_H:
10350
0
    case AArch64::URHADD_ZPmZ_S:
10351
0
    case AArch64::URSHLR_ZPmZ_B:
10352
0
    case AArch64::URSHLR_ZPmZ_D:
10353
0
    case AArch64::URSHLR_ZPmZ_H:
10354
0
    case AArch64::URSHLR_ZPmZ_S:
10355
0
    case AArch64::URSHL_ZPmZ_B:
10356
0
    case AArch64::URSHL_ZPmZ_D:
10357
0
    case AArch64::URSHL_ZPmZ_H:
10358
0
    case AArch64::URSHL_ZPmZ_S:
10359
0
    case AArch64::USQADD_ZPmZ_B:
10360
0
    case AArch64::USQADD_ZPmZ_D:
10361
0
    case AArch64::USQADD_ZPmZ_H:
10362
0
    case AArch64::USQADD_ZPmZ_S: {
10363
      // op: Pg
10364
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10365
0
      op &= UINT64_C(7);
10366
0
      op <<= 10;
10367
0
      Value |= op;
10368
      // op: Zm
10369
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10370
0
      op &= UINT64_C(31);
10371
0
      op <<= 5;
10372
0
      Value |= op;
10373
      // op: Zdn
10374
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10375
0
      op &= UINT64_C(31);
10376
0
      Value |= op;
10377
0
      break;
10378
0
    }
10379
0
    case AArch64::SPLICE_ZPZZ_B:
10380
0
    case AArch64::SPLICE_ZPZZ_D:
10381
0
    case AArch64::SPLICE_ZPZZ_H:
10382
0
    case AArch64::SPLICE_ZPZZ_S: {
10383
      // op: Pg
10384
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10385
0
      op &= UINT64_C(7);
10386
0
      op <<= 10;
10387
0
      Value |= op;
10388
      // op: Zn
10389
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10390
0
      op &= UINT64_C(31);
10391
0
      op <<= 5;
10392
0
      Value |= op;
10393
      // op: Zd
10394
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10395
0
      op &= UINT64_C(31);
10396
0
      Value |= op;
10397
0
      break;
10398
0
    }
10399
0
    case AArch64::GLD1B_D_IMM_REAL:
10400
0
    case AArch64::GLD1B_S_IMM_REAL:
10401
0
    case AArch64::GLD1D_IMM_REAL:
10402
0
    case AArch64::GLD1H_D_IMM_REAL:
10403
0
    case AArch64::GLD1H_S_IMM_REAL:
10404
0
    case AArch64::GLD1SB_D_IMM_REAL:
10405
0
    case AArch64::GLD1SB_S_IMM_REAL:
10406
0
    case AArch64::GLD1SH_D_IMM_REAL:
10407
0
    case AArch64::GLD1SH_S_IMM_REAL:
10408
0
    case AArch64::GLD1SW_D_IMM_REAL:
10409
0
    case AArch64::GLD1W_D_IMM_REAL:
10410
0
    case AArch64::GLD1W_IMM_REAL:
10411
0
    case AArch64::GLDFF1B_D_IMM_REAL:
10412
0
    case AArch64::GLDFF1B_S_IMM_REAL:
10413
0
    case AArch64::GLDFF1D_IMM_REAL:
10414
0
    case AArch64::GLDFF1H_D_IMM_REAL:
10415
0
    case AArch64::GLDFF1H_S_IMM_REAL:
10416
0
    case AArch64::GLDFF1SB_D_IMM_REAL:
10417
0
    case AArch64::GLDFF1SB_S_IMM_REAL:
10418
0
    case AArch64::GLDFF1SH_D_IMM_REAL:
10419
0
    case AArch64::GLDFF1SH_S_IMM_REAL:
10420
0
    case AArch64::GLDFF1SW_D_IMM_REAL:
10421
0
    case AArch64::GLDFF1W_D_IMM_REAL:
10422
0
    case AArch64::GLDFF1W_IMM_REAL: {
10423
      // op: Pg
10424
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10425
0
      op &= UINT64_C(7);
10426
0
      op <<= 10;
10427
0
      Value |= op;
10428
      // op: Zn
10429
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10430
0
      op &= UINT64_C(31);
10431
0
      op <<= 5;
10432
0
      Value |= op;
10433
      // op: Zt
10434
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10435
0
      op &= UINT64_C(31);
10436
0
      Value |= op;
10437
      // op: imm5
10438
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10439
0
      op &= UINT64_C(31);
10440
0
      op <<= 16;
10441
0
      Value |= op;
10442
0
      break;
10443
0
    }
10444
0
    case AArch64::PRFB_D_PZI:
10445
0
    case AArch64::PRFB_S_PZI:
10446
0
    case AArch64::PRFD_D_PZI:
10447
0
    case AArch64::PRFD_S_PZI:
10448
0
    case AArch64::PRFH_D_PZI:
10449
0
    case AArch64::PRFH_S_PZI:
10450
0
    case AArch64::PRFW_D_PZI:
10451
0
    case AArch64::PRFW_S_PZI: {
10452
      // op: Pg
10453
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10454
0
      op &= UINT64_C(7);
10455
0
      op <<= 10;
10456
0
      Value |= op;
10457
      // op: Zn
10458
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10459
0
      op &= UINT64_C(31);
10460
0
      op <<= 5;
10461
0
      Value |= op;
10462
      // op: imm5
10463
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10464
0
      op &= UINT64_C(31);
10465
0
      op <<= 16;
10466
0
      Value |= op;
10467
      // op: prfop
10468
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10469
0
      op &= UINT64_C(15);
10470
0
      Value |= op;
10471
0
      break;
10472
0
    }
10473
0
    case AArch64::SADALP_ZPmZ_D:
10474
0
    case AArch64::SADALP_ZPmZ_H:
10475
0
    case AArch64::SADALP_ZPmZ_S:
10476
0
    case AArch64::UADALP_ZPmZ_D:
10477
0
    case AArch64::UADALP_ZPmZ_H:
10478
0
    case AArch64::UADALP_ZPmZ_S: {
10479
      // op: Pg
10480
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10481
0
      op &= UINT64_C(7);
10482
0
      op <<= 10;
10483
0
      Value |= op;
10484
      // op: Zn
10485
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10486
0
      op &= UINT64_C(31);
10487
0
      op <<= 5;
10488
0
      Value |= op;
10489
      // op: Zda
10490
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10491
0
      op &= UINT64_C(31);
10492
0
      Value |= op;
10493
0
      break;
10494
0
    }
10495
0
    case AArch64::SST1B_D_IMM:
10496
0
    case AArch64::SST1B_S_IMM:
10497
0
    case AArch64::SST1D_IMM:
10498
0
    case AArch64::SST1H_D_IMM:
10499
0
    case AArch64::SST1H_S_IMM:
10500
0
    case AArch64::SST1W_D_IMM:
10501
0
    case AArch64::SST1W_IMM: {
10502
      // op: Pg
10503
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10504
0
      op &= UINT64_C(7);
10505
0
      op <<= 10;
10506
0
      Value |= op;
10507
      // op: imm5
10508
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10509
0
      op &= UINT64_C(31);
10510
0
      op <<= 16;
10511
0
      Value |= op;
10512
      // op: Zn
10513
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10514
0
      op &= UINT64_C(31);
10515
0
      op <<= 5;
10516
0
      Value |= op;
10517
      // op: Zt
10518
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10519
0
      op &= UINT64_C(31);
10520
0
      Value |= op;
10521
0
      break;
10522
0
    }
10523
0
    case AArch64::FCPY_ZPmI_D:
10524
0
    case AArch64::FCPY_ZPmI_H:
10525
0
    case AArch64::FCPY_ZPmI_S: {
10526
      // op: Pg
10527
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10528
0
      op &= UINT64_C(15);
10529
0
      op <<= 16;
10530
0
      Value |= op;
10531
      // op: Zd
10532
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10533
0
      op &= UINT64_C(31);
10534
0
      Value |= op;
10535
      // op: imm8
10536
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10537
0
      op &= UINT64_C(255);
10538
0
      op <<= 5;
10539
0
      Value |= op;
10540
0
      break;
10541
0
    }
10542
0
    case AArch64::CPY_ZPmR_B:
10543
0
    case AArch64::CPY_ZPmR_D:
10544
0
    case AArch64::CPY_ZPmR_H:
10545
0
    case AArch64::CPY_ZPmR_S: {
10546
      // op: Pg
10547
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10548
0
      op &= UINT64_C(7);
10549
0
      op <<= 10;
10550
0
      Value |= op;
10551
      // op: Rn
10552
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10553
0
      op &= UINT64_C(31);
10554
0
      op <<= 5;
10555
0
      Value |= op;
10556
      // op: Zd
10557
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10558
0
      op &= UINT64_C(31);
10559
0
      Value |= op;
10560
0
      break;
10561
0
    }
10562
0
    case AArch64::CPY_ZPmV_B:
10563
0
    case AArch64::CPY_ZPmV_D:
10564
0
    case AArch64::CPY_ZPmV_H:
10565
0
    case AArch64::CPY_ZPmV_S: {
10566
      // op: Pg
10567
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10568
0
      op &= UINT64_C(7);
10569
0
      op <<= 10;
10570
0
      Value |= op;
10571
      // op: Vn
10572
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10573
0
      op &= UINT64_C(31);
10574
0
      op <<= 5;
10575
0
      Value |= op;
10576
      // op: Zd
10577
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10578
0
      op &= UINT64_C(31);
10579
0
      Value |= op;
10580
0
      break;
10581
0
    }
10582
0
    case AArch64::ABS_ZPmZ_B:
10583
0
    case AArch64::ABS_ZPmZ_D:
10584
0
    case AArch64::ABS_ZPmZ_H:
10585
0
    case AArch64::ABS_ZPmZ_S:
10586
0
    case AArch64::CLS_ZPmZ_B:
10587
0
    case AArch64::CLS_ZPmZ_D:
10588
0
    case AArch64::CLS_ZPmZ_H:
10589
0
    case AArch64::CLS_ZPmZ_S:
10590
0
    case AArch64::CLZ_ZPmZ_B:
10591
0
    case AArch64::CLZ_ZPmZ_D:
10592
0
    case AArch64::CLZ_ZPmZ_H:
10593
0
    case AArch64::CLZ_ZPmZ_S:
10594
0
    case AArch64::CNOT_ZPmZ_B:
10595
0
    case AArch64::CNOT_ZPmZ_D:
10596
0
    case AArch64::CNOT_ZPmZ_H:
10597
0
    case AArch64::CNOT_ZPmZ_S:
10598
0
    case AArch64::CNT_ZPmZ_B:
10599
0
    case AArch64::CNT_ZPmZ_D:
10600
0
    case AArch64::CNT_ZPmZ_H:
10601
0
    case AArch64::CNT_ZPmZ_S:
10602
0
    case AArch64::FABS_ZPmZ_D:
10603
0
    case AArch64::FABS_ZPmZ_H:
10604
0
    case AArch64::FABS_ZPmZ_S:
10605
0
    case AArch64::FCVTX_ZPmZ_DtoS:
10606
0
    case AArch64::FCVTZS_ZPmZ_DtoD:
10607
0
    case AArch64::FCVTZS_ZPmZ_DtoS:
10608
0
    case AArch64::FCVTZS_ZPmZ_HtoD:
10609
0
    case AArch64::FCVTZS_ZPmZ_HtoH:
10610
0
    case AArch64::FCVTZS_ZPmZ_HtoS:
10611
0
    case AArch64::FCVTZS_ZPmZ_StoD:
10612
0
    case AArch64::FCVTZS_ZPmZ_StoS:
10613
0
    case AArch64::FCVTZU_ZPmZ_DtoD:
10614
0
    case AArch64::FCVTZU_ZPmZ_DtoS:
10615
0
    case AArch64::FCVTZU_ZPmZ_HtoD:
10616
0
    case AArch64::FCVTZU_ZPmZ_HtoH:
10617
0
    case AArch64::FCVTZU_ZPmZ_HtoS:
10618
0
    case AArch64::FCVTZU_ZPmZ_StoD:
10619
0
    case AArch64::FCVTZU_ZPmZ_StoS:
10620
0
    case AArch64::FCVT_ZPmZ_DtoH:
10621
0
    case AArch64::FCVT_ZPmZ_DtoS:
10622
0
    case AArch64::FCVT_ZPmZ_HtoD:
10623
0
    case AArch64::FCVT_ZPmZ_HtoS:
10624
0
    case AArch64::FCVT_ZPmZ_StoD:
10625
0
    case AArch64::FCVT_ZPmZ_StoH:
10626
0
    case AArch64::FLOGB_ZPmZ_D:
10627
0
    case AArch64::FLOGB_ZPmZ_H:
10628
0
    case AArch64::FLOGB_ZPmZ_S:
10629
0
    case AArch64::FNEG_ZPmZ_D:
10630
0
    case AArch64::FNEG_ZPmZ_H:
10631
0
    case AArch64::FNEG_ZPmZ_S:
10632
0
    case AArch64::FRECPX_ZPmZ_D:
10633
0
    case AArch64::FRECPX_ZPmZ_H:
10634
0
    case AArch64::FRECPX_ZPmZ_S:
10635
0
    case AArch64::FRINTA_ZPmZ_D:
10636
0
    case AArch64::FRINTA_ZPmZ_H:
10637
0
    case AArch64::FRINTA_ZPmZ_S:
10638
0
    case AArch64::FRINTI_ZPmZ_D:
10639
0
    case AArch64::FRINTI_ZPmZ_H:
10640
0
    case AArch64::FRINTI_ZPmZ_S:
10641
0
    case AArch64::FRINTM_ZPmZ_D:
10642
0
    case AArch64::FRINTM_ZPmZ_H:
10643
0
    case AArch64::FRINTM_ZPmZ_S:
10644
0
    case AArch64::FRINTN_ZPmZ_D:
10645
0
    case AArch64::FRINTN_ZPmZ_H:
10646
0
    case AArch64::FRINTN_ZPmZ_S:
10647
0
    case AArch64::FRINTP_ZPmZ_D:
10648
0
    case AArch64::FRINTP_ZPmZ_H:
10649
0
    case AArch64::FRINTP_ZPmZ_S:
10650
0
    case AArch64::FRINTX_ZPmZ_D:
10651
0
    case AArch64::FRINTX_ZPmZ_H:
10652
0
    case AArch64::FRINTX_ZPmZ_S:
10653
0
    case AArch64::FRINTZ_ZPmZ_D:
10654
0
    case AArch64::FRINTZ_ZPmZ_H:
10655
0
    case AArch64::FRINTZ_ZPmZ_S:
10656
0
    case AArch64::FSQRT_ZPmZ_D:
10657
0
    case AArch64::FSQRT_ZPmZ_H:
10658
0
    case AArch64::FSQRT_ZPmZ_S:
10659
0
    case AArch64::MOVPRFX_ZPmZ_B:
10660
0
    case AArch64::MOVPRFX_ZPmZ_D:
10661
0
    case AArch64::MOVPRFX_ZPmZ_H:
10662
0
    case AArch64::MOVPRFX_ZPmZ_S:
10663
0
    case AArch64::NEG_ZPmZ_B:
10664
0
    case AArch64::NEG_ZPmZ_D:
10665
0
    case AArch64::NEG_ZPmZ_H:
10666
0
    case AArch64::NEG_ZPmZ_S:
10667
0
    case AArch64::NOT_ZPmZ_B:
10668
0
    case AArch64::NOT_ZPmZ_D:
10669
0
    case AArch64::NOT_ZPmZ_H:
10670
0
    case AArch64::NOT_ZPmZ_S:
10671
0
    case AArch64::SCVTF_ZPmZ_DtoD:
10672
0
    case AArch64::SCVTF_ZPmZ_DtoH:
10673
0
    case AArch64::SCVTF_ZPmZ_DtoS:
10674
0
    case AArch64::SCVTF_ZPmZ_HtoH:
10675
0
    case AArch64::SCVTF_ZPmZ_StoD:
10676
0
    case AArch64::SCVTF_ZPmZ_StoH:
10677
0
    case AArch64::SCVTF_ZPmZ_StoS:
10678
0
    case AArch64::SQABS_ZPmZ_B:
10679
0
    case AArch64::SQABS_ZPmZ_D:
10680
0
    case AArch64::SQABS_ZPmZ_H:
10681
0
    case AArch64::SQABS_ZPmZ_S:
10682
0
    case AArch64::SQNEG_ZPmZ_B:
10683
0
    case AArch64::SQNEG_ZPmZ_D:
10684
0
    case AArch64::SQNEG_ZPmZ_H:
10685
0
    case AArch64::SQNEG_ZPmZ_S:
10686
0
    case AArch64::SXTB_ZPmZ_D:
10687
0
    case AArch64::SXTB_ZPmZ_H:
10688
0
    case AArch64::SXTB_ZPmZ_S:
10689
0
    case AArch64::SXTH_ZPmZ_D:
10690
0
    case AArch64::SXTH_ZPmZ_S:
10691
0
    case AArch64::SXTW_ZPmZ_D:
10692
0
    case AArch64::UCVTF_ZPmZ_DtoD:
10693
0
    case AArch64::UCVTF_ZPmZ_DtoH:
10694
0
    case AArch64::UCVTF_ZPmZ_DtoS:
10695
0
    case AArch64::UCVTF_ZPmZ_HtoH:
10696
0
    case AArch64::UCVTF_ZPmZ_StoD:
10697
0
    case AArch64::UCVTF_ZPmZ_StoH:
10698
0
    case AArch64::UCVTF_ZPmZ_StoS:
10699
0
    case AArch64::URECPE_ZPmZ_S:
10700
0
    case AArch64::URSQRTE_ZPmZ_S:
10701
0
    case AArch64::UXTB_ZPmZ_D:
10702
0
    case AArch64::UXTB_ZPmZ_H:
10703
0
    case AArch64::UXTB_ZPmZ_S:
10704
0
    case AArch64::UXTH_ZPmZ_D:
10705
0
    case AArch64::UXTH_ZPmZ_S:
10706
0
    case AArch64::UXTW_ZPmZ_D: {
10707
      // op: Pg
10708
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10709
0
      op &= UINT64_C(7);
10710
0
      op <<= 10;
10711
0
      Value |= op;
10712
      // op: Zd
10713
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10714
0
      op &= UINT64_C(31);
10715
0
      Value |= op;
10716
      // op: Zn
10717
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10718
0
      op &= UINT64_C(31);
10719
0
      op <<= 5;
10720
0
      Value |= op;
10721
0
      break;
10722
0
    }
10723
0
    case AArch64::DECP_ZP_D:
10724
0
    case AArch64::DECP_ZP_H:
10725
0
    case AArch64::DECP_ZP_S:
10726
0
    case AArch64::INCP_ZP_D:
10727
0
    case AArch64::INCP_ZP_H:
10728
0
    case AArch64::INCP_ZP_S:
10729
0
    case AArch64::SQDECP_ZP_D:
10730
0
    case AArch64::SQDECP_ZP_H:
10731
0
    case AArch64::SQDECP_ZP_S:
10732
0
    case AArch64::SQINCP_ZP_D:
10733
0
    case AArch64::SQINCP_ZP_H:
10734
0
    case AArch64::SQINCP_ZP_S:
10735
0
    case AArch64::UQDECP_ZP_D:
10736
0
    case AArch64::UQDECP_ZP_H:
10737
0
    case AArch64::UQDECP_ZP_S:
10738
0
    case AArch64::UQINCP_ZP_D:
10739
0
    case AArch64::UQINCP_ZP_H:
10740
0
    case AArch64::UQINCP_ZP_S: {
10741
      // op: Pm
10742
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10743
0
      op &= UINT64_C(15);
10744
0
      op <<= 5;
10745
0
      Value |= op;
10746
      // op: Zdn
10747
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10748
0
      op &= UINT64_C(31);
10749
0
      Value |= op;
10750
0
      break;
10751
0
    }
10752
0
    case AArch64::ADDHA_MPPZ_S:
10753
0
    case AArch64::ADDVA_MPPZ_S: {
10754
      // op: Pm
10755
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10756
0
      op &= UINT64_C(7);
10757
0
      op <<= 13;
10758
0
      Value |= op;
10759
      // op: Pn
10760
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10761
0
      op &= UINT64_C(7);
10762
0
      op <<= 10;
10763
0
      Value |= op;
10764
      // op: Zn
10765
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
10766
0
      op &= UINT64_C(31);
10767
0
      op <<= 5;
10768
0
      Value |= op;
10769
      // op: ZAda
10770
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10771
0
      op &= UINT64_C(3);
10772
0
      Value |= op;
10773
0
      break;
10774
0
    }
10775
0
    case AArch64::ADDHA_MPPZ_D:
10776
0
    case AArch64::ADDVA_MPPZ_D: {
10777
      // op: Pm
10778
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10779
0
      op &= UINT64_C(7);
10780
0
      op <<= 13;
10781
0
      Value |= op;
10782
      // op: Pn
10783
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10784
0
      op &= UINT64_C(7);
10785
0
      op <<= 10;
10786
0
      Value |= op;
10787
      // op: Zn
10788
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
10789
0
      op &= UINT64_C(31);
10790
0
      op <<= 5;
10791
0
      Value |= op;
10792
      // op: ZAda
10793
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10794
0
      op &= UINT64_C(7);
10795
0
      Value |= op;
10796
0
      break;
10797
0
    }
10798
0
    case AArch64::WRFFR: {
10799
      // op: Pn
10800
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10801
0
      op &= UINT64_C(15);
10802
0
      op <<= 5;
10803
0
      Value |= op;
10804
0
      break;
10805
0
    }
10806
0
    case AArch64::LDR_PXI:
10807
0
    case AArch64::STR_PXI: {
10808
      // op: Pt
10809
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10810
0
      op &= UINT64_C(15);
10811
0
      Value |= op;
10812
      // op: Rn
10813
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10814
0
      op &= UINT64_C(31);
10815
0
      op <<= 5;
10816
0
      Value |= op;
10817
      // op: imm9
10818
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10819
0
      Value |= (op & UINT64_C(504)) << 13;
10820
0
      Value |= (op & UINT64_C(7)) << 10;
10821
0
      break;
10822
0
    }
10823
0
    case AArch64::XPACD:
10824
0
    case AArch64::XPACI: {
10825
      // op: Rd
10826
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10827
0
      op &= UINT64_C(31);
10828
0
      Value |= op;
10829
0
      break;
10830
0
    }
10831
0
    case AArch64::CNTP_XCI_B:
10832
0
    case AArch64::CNTP_XCI_D:
10833
0
    case AArch64::CNTP_XCI_H:
10834
0
    case AArch64::CNTP_XCI_S: {
10835
      // op: Rd
10836
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10837
0
      op &= UINT64_C(31);
10838
0
      Value |= op;
10839
      // op: PNn
10840
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10841
0
      op &= UINT64_C(15);
10842
0
      op <<= 5;
10843
0
      Value |= op;
10844
      // op: vl
10845
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10846
0
      op &= UINT64_C(1);
10847
0
      op <<= 10;
10848
0
      Value |= op;
10849
0
      break;
10850
0
    }
10851
0
    case AArch64::ADDPL_XXI:
10852
0
    case AArch64::ADDSPL_XXI:
10853
0
    case AArch64::ADDSVL_XXI:
10854
0
    case AArch64::ADDVL_XXI: {
10855
      // op: Rd
10856
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10857
0
      op &= UINT64_C(31);
10858
0
      Value |= op;
10859
      // op: Rn
10860
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10861
0
      op &= UINT64_C(31);
10862
0
      op <<= 16;
10863
0
      Value |= op;
10864
      // op: imm6
10865
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10866
0
      op &= UINT64_C(63);
10867
0
      op <<= 5;
10868
0
      Value |= op;
10869
0
      break;
10870
0
    }
10871
0
    case AArch64::ABSWr:
10872
0
    case AArch64::ABSXr:
10873
0
    case AArch64::ABSv1i64:
10874
0
    case AArch64::ABSv2i32:
10875
0
    case AArch64::ABSv2i64:
10876
0
    case AArch64::ABSv4i16:
10877
0
    case AArch64::ABSv4i32:
10878
0
    case AArch64::ABSv8i8:
10879
0
    case AArch64::ABSv8i16:
10880
0
    case AArch64::ABSv16i8:
10881
0
    case AArch64::ADDPv2i64p:
10882
0
    case AArch64::ADDVv4i16v:
10883
0
    case AArch64::ADDVv4i32v:
10884
0
    case AArch64::ADDVv8i8v:
10885
0
    case AArch64::ADDVv8i16v:
10886
0
    case AArch64::ADDVv16i8v:
10887
0
    case AArch64::AESIMCrr:
10888
0
    case AArch64::AESMCrr:
10889
0
    case AArch64::BF1CVTL2v8f16:
10890
0
    case AArch64::BF1CVTLv8f16:
10891
0
    case AArch64::BF2CVTL2v8f16:
10892
0
    case AArch64::BF2CVTLv8f16:
10893
0
    case AArch64::BFCVT:
10894
0
    case AArch64::BFCVTN:
10895
0
    case AArch64::CLSWr:
10896
0
    case AArch64::CLSXr:
10897
0
    case AArch64::CLSv2i32:
10898
0
    case AArch64::CLSv4i16:
10899
0
    case AArch64::CLSv4i32:
10900
0
    case AArch64::CLSv8i8:
10901
0
    case AArch64::CLSv8i16:
10902
0
    case AArch64::CLSv16i8:
10903
0
    case AArch64::CLZWr:
10904
0
    case AArch64::CLZXr:
10905
0
    case AArch64::CLZv2i32:
10906
0
    case AArch64::CLZv4i16:
10907
0
    case AArch64::CLZv4i32:
10908
0
    case AArch64::CLZv8i8:
10909
0
    case AArch64::CLZv8i16:
10910
0
    case AArch64::CLZv16i8:
10911
0
    case AArch64::CMEQv1i64rz:
10912
0
    case AArch64::CMEQv2i32rz:
10913
0
    case AArch64::CMEQv2i64rz:
10914
0
    case AArch64::CMEQv4i16rz:
10915
0
    case AArch64::CMEQv4i32rz:
10916
0
    case AArch64::CMEQv8i8rz:
10917
0
    case AArch64::CMEQv8i16rz:
10918
0
    case AArch64::CMEQv16i8rz:
10919
0
    case AArch64::CMGEv1i64rz:
10920
0
    case AArch64::CMGEv2i32rz:
10921
0
    case AArch64::CMGEv2i64rz:
10922
0
    case AArch64::CMGEv4i16rz:
10923
0
    case AArch64::CMGEv4i32rz:
10924
0
    case AArch64::CMGEv8i8rz:
10925
0
    case AArch64::CMGEv8i16rz:
10926
0
    case AArch64::CMGEv16i8rz:
10927
0
    case AArch64::CMGTv1i64rz:
10928
0
    case AArch64::CMGTv2i32rz:
10929
0
    case AArch64::CMGTv2i64rz:
10930
0
    case AArch64::CMGTv4i16rz:
10931
0
    case AArch64::CMGTv4i32rz:
10932
0
    case AArch64::CMGTv8i8rz:
10933
0
    case AArch64::CMGTv8i16rz:
10934
0
    case AArch64::CMGTv16i8rz:
10935
0
    case AArch64::CMLEv1i64rz:
10936
0
    case AArch64::CMLEv2i32rz:
10937
0
    case AArch64::CMLEv2i64rz:
10938
0
    case AArch64::CMLEv4i16rz:
10939
0
    case AArch64::CMLEv4i32rz:
10940
0
    case AArch64::CMLEv8i8rz:
10941
0
    case AArch64::CMLEv8i16rz:
10942
0
    case AArch64::CMLEv16i8rz:
10943
0
    case AArch64::CMLTv1i64rz:
10944
0
    case AArch64::CMLTv2i32rz:
10945
0
    case AArch64::CMLTv2i64rz:
10946
0
    case AArch64::CMLTv4i16rz:
10947
0
    case AArch64::CMLTv4i32rz:
10948
0
    case AArch64::CMLTv8i8rz:
10949
0
    case AArch64::CMLTv8i16rz:
10950
0
    case AArch64::CMLTv16i8rz:
10951
0
    case AArch64::CNTWr:
10952
0
    case AArch64::CNTXr:
10953
0
    case AArch64::CNTv8i8:
10954
0
    case AArch64::CNTv16i8:
10955
0
    case AArch64::CTZWr:
10956
0
    case AArch64::CTZXr:
10957
0
    case AArch64::DUPv2i32gpr:
10958
0
    case AArch64::DUPv2i64gpr:
10959
0
    case AArch64::DUPv4i16gpr:
10960
0
    case AArch64::DUPv4i32gpr:
10961
0
    case AArch64::DUPv8i8gpr:
10962
0
    case AArch64::DUPv8i16gpr:
10963
0
    case AArch64::DUPv16i8gpr:
10964
0
    case AArch64::F1CVTL2v8f16:
10965
0
    case AArch64::F1CVTLv8f16:
10966
0
    case AArch64::F2CVTL2v8f16:
10967
0
    case AArch64::F2CVTLv8f16:
10968
0
    case AArch64::FABSDr:
10969
0
    case AArch64::FABSHr:
10970
0
    case AArch64::FABSSr:
10971
0
    case AArch64::FABSv2f32:
10972
0
    case AArch64::FABSv2f64:
10973
0
    case AArch64::FABSv4f16:
10974
0
    case AArch64::FABSv4f32:
10975
0
    case AArch64::FABSv8f16:
10976
0
    case AArch64::FADDPv2i16p:
10977
0
    case AArch64::FADDPv2i32p:
10978
0
    case AArch64::FADDPv2i64p:
10979
0
    case AArch64::FCMEQv1i16rz:
10980
0
    case AArch64::FCMEQv1i32rz:
10981
0
    case AArch64::FCMEQv1i64rz:
10982
0
    case AArch64::FCMEQv2i32rz:
10983
0
    case AArch64::FCMEQv2i64rz:
10984
0
    case AArch64::FCMEQv4i16rz:
10985
0
    case AArch64::FCMEQv4i32rz:
10986
0
    case AArch64::FCMEQv8i16rz:
10987
0
    case AArch64::FCMGEv1i16rz:
10988
0
    case AArch64::FCMGEv1i32rz:
10989
0
    case AArch64::FCMGEv1i64rz:
10990
0
    case AArch64::FCMGEv2i32rz:
10991
0
    case AArch64::FCMGEv2i64rz:
10992
0
    case AArch64::FCMGEv4i16rz:
10993
0
    case AArch64::FCMGEv4i32rz:
10994
0
    case AArch64::FCMGEv8i16rz:
10995
0
    case AArch64::FCMGTv1i16rz:
10996
0
    case AArch64::FCMGTv1i32rz:
10997
0
    case AArch64::FCMGTv1i64rz:
10998
0
    case AArch64::FCMGTv2i32rz:
10999
0
    case AArch64::FCMGTv2i64rz:
11000
0
    case AArch64::FCMGTv4i16rz:
11001
0
    case AArch64::FCMGTv4i32rz:
11002
0
    case AArch64::FCMGTv8i16rz:
11003
0
    case AArch64::FCMLEv1i16rz:
11004
0
    case AArch64::FCMLEv1i32rz:
11005
0
    case AArch64::FCMLEv1i64rz:
11006
0
    case AArch64::FCMLEv2i32rz:
11007
0
    case AArch64::FCMLEv2i64rz:
11008
0
    case AArch64::FCMLEv4i16rz:
11009
0
    case AArch64::FCMLEv4i32rz:
11010
0
    case AArch64::FCMLEv8i16rz:
11011
0
    case AArch64::FCMLTv1i16rz:
11012
0
    case AArch64::FCMLTv1i32rz:
11013
0
    case AArch64::FCMLTv1i64rz:
11014
0
    case AArch64::FCMLTv2i32rz:
11015
0
    case AArch64::FCMLTv2i64rz:
11016
0
    case AArch64::FCMLTv4i16rz:
11017
0
    case AArch64::FCMLTv4i32rz:
11018
0
    case AArch64::FCMLTv8i16rz:
11019
0
    case AArch64::FCVTASUWDr:
11020
0
    case AArch64::FCVTASUWHr:
11021
0
    case AArch64::FCVTASUWSr:
11022
0
    case AArch64::FCVTASUXDr:
11023
0
    case AArch64::FCVTASUXHr:
11024
0
    case AArch64::FCVTASUXSr:
11025
0
    case AArch64::FCVTASv1f16:
11026
0
    case AArch64::FCVTASv1i32:
11027
0
    case AArch64::FCVTASv1i64:
11028
0
    case AArch64::FCVTASv2f32:
11029
0
    case AArch64::FCVTASv2f64:
11030
0
    case AArch64::FCVTASv4f16:
11031
0
    case AArch64::FCVTASv4f32:
11032
0
    case AArch64::FCVTASv8f16:
11033
0
    case AArch64::FCVTAUUWDr:
11034
0
    case AArch64::FCVTAUUWHr:
11035
0
    case AArch64::FCVTAUUWSr:
11036
0
    case AArch64::FCVTAUUXDr:
11037
0
    case AArch64::FCVTAUUXHr:
11038
0
    case AArch64::FCVTAUUXSr:
11039
0
    case AArch64::FCVTAUv1f16:
11040
0
    case AArch64::FCVTAUv1i32:
11041
0
    case AArch64::FCVTAUv1i64:
11042
0
    case AArch64::FCVTAUv2f32:
11043
0
    case AArch64::FCVTAUv2f64:
11044
0
    case AArch64::FCVTAUv4f16:
11045
0
    case AArch64::FCVTAUv4f32:
11046
0
    case AArch64::FCVTAUv8f16:
11047
0
    case AArch64::FCVTDHr:
11048
0
    case AArch64::FCVTDSr:
11049
0
    case AArch64::FCVTHDr:
11050
0
    case AArch64::FCVTHSr:
11051
0
    case AArch64::FCVTLv2i32:
11052
0
    case AArch64::FCVTLv4i16:
11053
0
    case AArch64::FCVTLv4i32:
11054
0
    case AArch64::FCVTLv8i16:
11055
0
    case AArch64::FCVTMSUWDr:
11056
0
    case AArch64::FCVTMSUWHr:
11057
0
    case AArch64::FCVTMSUWSr:
11058
0
    case AArch64::FCVTMSUXDr:
11059
0
    case AArch64::FCVTMSUXHr:
11060
0
    case AArch64::FCVTMSUXSr:
11061
0
    case AArch64::FCVTMSv1f16:
11062
0
    case AArch64::FCVTMSv1i32:
11063
0
    case AArch64::FCVTMSv1i64:
11064
0
    case AArch64::FCVTMSv2f32:
11065
0
    case AArch64::FCVTMSv2f64:
11066
0
    case AArch64::FCVTMSv4f16:
11067
0
    case AArch64::FCVTMSv4f32:
11068
0
    case AArch64::FCVTMSv8f16:
11069
0
    case AArch64::FCVTMUUWDr:
11070
0
    case AArch64::FCVTMUUWHr:
11071
0
    case AArch64::FCVTMUUWSr:
11072
0
    case AArch64::FCVTMUUXDr:
11073
0
    case AArch64::FCVTMUUXHr:
11074
0
    case AArch64::FCVTMUUXSr:
11075
0
    case AArch64::FCVTMUv1f16:
11076
0
    case AArch64::FCVTMUv1i32:
11077
0
    case AArch64::FCVTMUv1i64:
11078
0
    case AArch64::FCVTMUv2f32:
11079
0
    case AArch64::FCVTMUv2f64:
11080
0
    case AArch64::FCVTMUv4f16:
11081
0
    case AArch64::FCVTMUv4f32:
11082
0
    case AArch64::FCVTMUv8f16:
11083
0
    case AArch64::FCVTNSUWDr:
11084
0
    case AArch64::FCVTNSUWHr:
11085
0
    case AArch64::FCVTNSUWSr:
11086
0
    case AArch64::FCVTNSUXDr:
11087
0
    case AArch64::FCVTNSUXHr:
11088
0
    case AArch64::FCVTNSUXSr:
11089
0
    case AArch64::FCVTNSv1f16:
11090
0
    case AArch64::FCVTNSv1i32:
11091
0
    case AArch64::FCVTNSv1i64:
11092
0
    case AArch64::FCVTNSv2f32:
11093
0
    case AArch64::FCVTNSv2f64:
11094
0
    case AArch64::FCVTNSv4f16:
11095
0
    case AArch64::FCVTNSv4f32:
11096
0
    case AArch64::FCVTNSv8f16:
11097
0
    case AArch64::FCVTNUUWDr:
11098
0
    case AArch64::FCVTNUUWHr:
11099
0
    case AArch64::FCVTNUUWSr:
11100
0
    case AArch64::FCVTNUUXDr:
11101
0
    case AArch64::FCVTNUUXHr:
11102
0
    case AArch64::FCVTNUUXSr:
11103
0
    case AArch64::FCVTNUv1f16:
11104
0
    case AArch64::FCVTNUv1i32:
11105
0
    case AArch64::FCVTNUv1i64:
11106
0
    case AArch64::FCVTNUv2f32:
11107
0
    case AArch64::FCVTNUv2f64:
11108
0
    case AArch64::FCVTNUv4f16:
11109
0
    case AArch64::FCVTNUv4f32:
11110
0
    case AArch64::FCVTNUv8f16:
11111
0
    case AArch64::FCVTNv2i32:
11112
0
    case AArch64::FCVTNv4i16:
11113
0
    case AArch64::FCVTPSUWDr:
11114
0
    case AArch64::FCVTPSUWHr:
11115
0
    case AArch64::FCVTPSUWSr:
11116
0
    case AArch64::FCVTPSUXDr:
11117
0
    case AArch64::FCVTPSUXHr:
11118
0
    case AArch64::FCVTPSUXSr:
11119
0
    case AArch64::FCVTPSv1f16:
11120
0
    case AArch64::FCVTPSv1i32:
11121
0
    case AArch64::FCVTPSv1i64:
11122
0
    case AArch64::FCVTPSv2f32:
11123
0
    case AArch64::FCVTPSv2f64:
11124
0
    case AArch64::FCVTPSv4f16:
11125
0
    case AArch64::FCVTPSv4f32:
11126
0
    case AArch64::FCVTPSv8f16:
11127
0
    case AArch64::FCVTPUUWDr:
11128
0
    case AArch64::FCVTPUUWHr:
11129
0
    case AArch64::FCVTPUUWSr:
11130
0
    case AArch64::FCVTPUUXDr:
11131
0
    case AArch64::FCVTPUUXHr:
11132
0
    case AArch64::FCVTPUUXSr:
11133
0
    case AArch64::FCVTPUv1f16:
11134
0
    case AArch64::FCVTPUv1i32:
11135
0
    case AArch64::FCVTPUv1i64:
11136
0
    case AArch64::FCVTPUv2f32:
11137
0
    case AArch64::FCVTPUv2f64:
11138
0
    case AArch64::FCVTPUv4f16:
11139
0
    case AArch64::FCVTPUv4f32:
11140
0
    case AArch64::FCVTPUv8f16:
11141
0
    case AArch64::FCVTSDr:
11142
0
    case AArch64::FCVTSHr:
11143
0
    case AArch64::FCVTXNv1i64:
11144
0
    case AArch64::FCVTXNv2f32:
11145
0
    case AArch64::FCVTZSUWDr:
11146
0
    case AArch64::FCVTZSUWHr:
11147
0
    case AArch64::FCVTZSUWSr:
11148
0
    case AArch64::FCVTZSUXDr:
11149
0
    case AArch64::FCVTZSUXHr:
11150
0
    case AArch64::FCVTZSUXSr:
11151
0
    case AArch64::FCVTZSv1f16:
11152
0
    case AArch64::FCVTZSv1i32:
11153
0
    case AArch64::FCVTZSv1i64:
11154
0
    case AArch64::FCVTZSv2f32:
11155
0
    case AArch64::FCVTZSv2f64:
11156
0
    case AArch64::FCVTZSv4f16:
11157
0
    case AArch64::FCVTZSv4f32:
11158
0
    case AArch64::FCVTZSv8f16:
11159
0
    case AArch64::FCVTZUUWDr:
11160
0
    case AArch64::FCVTZUUWHr:
11161
0
    case AArch64::FCVTZUUWSr:
11162
0
    case AArch64::FCVTZUUXDr:
11163
0
    case AArch64::FCVTZUUXHr:
11164
0
    case AArch64::FCVTZUUXSr:
11165
0
    case AArch64::FCVTZUv1f16:
11166
0
    case AArch64::FCVTZUv1i32:
11167
0
    case AArch64::FCVTZUv1i64:
11168
0
    case AArch64::FCVTZUv2f32:
11169
0
    case AArch64::FCVTZUv2f64:
11170
0
    case AArch64::FCVTZUv4f16:
11171
0
    case AArch64::FCVTZUv4f32:
11172
0
    case AArch64::FCVTZUv8f16:
11173
0
    case AArch64::FJCVTZS:
11174
0
    case AArch64::FMAXNMPv2i16p:
11175
0
    case AArch64::FMAXNMPv2i32p:
11176
0
    case AArch64::FMAXNMPv2i64p:
11177
0
    case AArch64::FMAXNMVv4i16v:
11178
0
    case AArch64::FMAXNMVv4i32v:
11179
0
    case AArch64::FMAXNMVv8i16v:
11180
0
    case AArch64::FMAXPv2i16p:
11181
0
    case AArch64::FMAXPv2i32p:
11182
0
    case AArch64::FMAXPv2i64p:
11183
0
    case AArch64::FMAXVv4i16v:
11184
0
    case AArch64::FMAXVv4i32v:
11185
0
    case AArch64::FMAXVv8i16v:
11186
0
    case AArch64::FMINNMPv2i16p:
11187
0
    case AArch64::FMINNMPv2i32p:
11188
0
    case AArch64::FMINNMPv2i64p:
11189
0
    case AArch64::FMINNMVv4i16v:
11190
0
    case AArch64::FMINNMVv4i32v:
11191
0
    case AArch64::FMINNMVv8i16v:
11192
0
    case AArch64::FMINPv2i16p:
11193
0
    case AArch64::FMINPv2i32p:
11194
0
    case AArch64::FMINPv2i64p:
11195
0
    case AArch64::FMINVv4i16v:
11196
0
    case AArch64::FMINVv4i32v:
11197
0
    case AArch64::FMINVv8i16v:
11198
0
    case AArch64::FMOVDXHighr:
11199
0
    case AArch64::FMOVDXr:
11200
0
    case AArch64::FMOVDr:
11201
0
    case AArch64::FMOVHWr:
11202
0
    case AArch64::FMOVHXr:
11203
0
    case AArch64::FMOVHr:
11204
0
    case AArch64::FMOVSWr:
11205
0
    case AArch64::FMOVSr:
11206
0
    case AArch64::FMOVWHr:
11207
0
    case AArch64::FMOVWSr:
11208
0
    case AArch64::FMOVXDHighr:
11209
0
    case AArch64::FMOVXDr:
11210
0
    case AArch64::FMOVXHr:
11211
0
    case AArch64::FNEGDr:
11212
0
    case AArch64::FNEGHr:
11213
0
    case AArch64::FNEGSr:
11214
0
    case AArch64::FNEGv2f32:
11215
0
    case AArch64::FNEGv2f64:
11216
0
    case AArch64::FNEGv4f16:
11217
0
    case AArch64::FNEGv4f32:
11218
0
    case AArch64::FNEGv8f16:
11219
0
    case AArch64::FRECPEv1f16:
11220
0
    case AArch64::FRECPEv1i32:
11221
0
    case AArch64::FRECPEv1i64:
11222
0
    case AArch64::FRECPEv2f32:
11223
0
    case AArch64::FRECPEv2f64:
11224
0
    case AArch64::FRECPEv4f16:
11225
0
    case AArch64::FRECPEv4f32:
11226
0
    case AArch64::FRECPEv8f16:
11227
0
    case AArch64::FRECPXv1f16:
11228
0
    case AArch64::FRECPXv1i32:
11229
0
    case AArch64::FRECPXv1i64:
11230
0
    case AArch64::FRINT32XDr:
11231
0
    case AArch64::FRINT32XSr:
11232
0
    case AArch64::FRINT32Xv2f32:
11233
0
    case AArch64::FRINT32Xv2f64:
11234
0
    case AArch64::FRINT32Xv4f32:
11235
0
    case AArch64::FRINT32ZDr:
11236
0
    case AArch64::FRINT32ZSr:
11237
0
    case AArch64::FRINT32Zv2f32:
11238
0
    case AArch64::FRINT32Zv2f64:
11239
0
    case AArch64::FRINT32Zv4f32:
11240
0
    case AArch64::FRINT64XDr:
11241
0
    case AArch64::FRINT64XSr:
11242
0
    case AArch64::FRINT64Xv2f32:
11243
0
    case AArch64::FRINT64Xv2f64:
11244
0
    case AArch64::FRINT64Xv4f32:
11245
0
    case AArch64::FRINT64ZDr:
11246
0
    case AArch64::FRINT64ZSr:
11247
0
    case AArch64::FRINT64Zv2f32:
11248
0
    case AArch64::FRINT64Zv2f64:
11249
0
    case AArch64::FRINT64Zv4f32:
11250
0
    case AArch64::FRINTADr:
11251
0
    case AArch64::FRINTAHr:
11252
0
    case AArch64::FRINTASr:
11253
0
    case AArch64::FRINTAv2f32:
11254
0
    case AArch64::FRINTAv2f64:
11255
0
    case AArch64::FRINTAv4f16:
11256
0
    case AArch64::FRINTAv4f32:
11257
0
    case AArch64::FRINTAv8f16:
11258
0
    case AArch64::FRINTIDr:
11259
0
    case AArch64::FRINTIHr:
11260
0
    case AArch64::FRINTISr:
11261
0
    case AArch64::FRINTIv2f32:
11262
0
    case AArch64::FRINTIv2f64:
11263
0
    case AArch64::FRINTIv4f16:
11264
0
    case AArch64::FRINTIv4f32:
11265
0
    case AArch64::FRINTIv8f16:
11266
0
    case AArch64::FRINTMDr:
11267
0
    case AArch64::FRINTMHr:
11268
0
    case AArch64::FRINTMSr:
11269
0
    case AArch64::FRINTMv2f32:
11270
0
    case AArch64::FRINTMv2f64:
11271
0
    case AArch64::FRINTMv4f16:
11272
0
    case AArch64::FRINTMv4f32:
11273
0
    case AArch64::FRINTMv8f16:
11274
0
    case AArch64::FRINTNDr:
11275
0
    case AArch64::FRINTNHr:
11276
0
    case AArch64::FRINTNSr:
11277
0
    case AArch64::FRINTNv2f32:
11278
0
    case AArch64::FRINTNv2f64:
11279
0
    case AArch64::FRINTNv4f16:
11280
0
    case AArch64::FRINTNv4f32:
11281
0
    case AArch64::FRINTNv8f16:
11282
0
    case AArch64::FRINTPDr:
11283
0
    case AArch64::FRINTPHr:
11284
0
    case AArch64::FRINTPSr:
11285
0
    case AArch64::FRINTPv2f32:
11286
0
    case AArch64::FRINTPv2f64:
11287
0
    case AArch64::FRINTPv4f16:
11288
0
    case AArch64::FRINTPv4f32:
11289
0
    case AArch64::FRINTPv8f16:
11290
0
    case AArch64::FRINTXDr:
11291
0
    case AArch64::FRINTXHr:
11292
0
    case AArch64::FRINTXSr:
11293
0
    case AArch64::FRINTXv2f32:
11294
0
    case AArch64::FRINTXv2f64:
11295
0
    case AArch64::FRINTXv4f16:
11296
0
    case AArch64::FRINTXv4f32:
11297
0
    case AArch64::FRINTXv8f16:
11298
0
    case AArch64::FRINTZDr:
11299
0
    case AArch64::FRINTZHr:
11300
0
    case AArch64::FRINTZSr:
11301
0
    case AArch64::FRINTZv2f32:
11302
0
    case AArch64::FRINTZv2f64:
11303
0
    case AArch64::FRINTZv4f16:
11304
0
    case AArch64::FRINTZv4f32:
11305
0
    case AArch64::FRINTZv8f16:
11306
0
    case AArch64::FRSQRTEv1f16:
11307
0
    case AArch64::FRSQRTEv1i32:
11308
0
    case AArch64::FRSQRTEv1i64:
11309
0
    case AArch64::FRSQRTEv2f32:
11310
0
    case AArch64::FRSQRTEv2f64:
11311
0
    case AArch64::FRSQRTEv4f16:
11312
0
    case AArch64::FRSQRTEv4f32:
11313
0
    case AArch64::FRSQRTEv8f16:
11314
0
    case AArch64::FSQRTDr:
11315
0
    case AArch64::FSQRTHr:
11316
0
    case AArch64::FSQRTSr:
11317
0
    case AArch64::FSQRTv2f32:
11318
0
    case AArch64::FSQRTv2f64:
11319
0
    case AArch64::FSQRTv4f16:
11320
0
    case AArch64::FSQRTv4f32:
11321
0
    case AArch64::FSQRTv8f16:
11322
0
    case AArch64::NEGv1i64:
11323
0
    case AArch64::NEGv2i32:
11324
0
    case AArch64::NEGv2i64:
11325
0
    case AArch64::NEGv4i16:
11326
0
    case AArch64::NEGv4i32:
11327
0
    case AArch64::NEGv8i8:
11328
0
    case AArch64::NEGv8i16:
11329
0
    case AArch64::NEGv16i8:
11330
0
    case AArch64::NOTv8i8:
11331
0
    case AArch64::NOTv16i8:
11332
0
    case AArch64::RBITWr:
11333
0
    case AArch64::RBITXr:
11334
0
    case AArch64::RBITv8i8:
11335
0
    case AArch64::RBITv16i8:
11336
0
    case AArch64::REV16Wr:
11337
0
    case AArch64::REV16Xr:
11338
0
    case AArch64::REV16v8i8:
11339
0
    case AArch64::REV16v16i8:
11340
0
    case AArch64::REV32Xr:
11341
0
    case AArch64::REV32v4i16:
11342
0
    case AArch64::REV32v8i8:
11343
0
    case AArch64::REV32v8i16:
11344
0
    case AArch64::REV32v16i8:
11345
0
    case AArch64::REV64v2i32:
11346
0
    case AArch64::REV64v4i16:
11347
0
    case AArch64::REV64v4i32:
11348
0
    case AArch64::REV64v8i8:
11349
0
    case AArch64::REV64v8i16:
11350
0
    case AArch64::REV64v16i8:
11351
0
    case AArch64::REVWr:
11352
0
    case AArch64::REVXr:
11353
0
    case AArch64::SADDLPv2i32_v1i64:
11354
0
    case AArch64::SADDLPv4i16_v2i32:
11355
0
    case AArch64::SADDLPv4i32_v2i64:
11356
0
    case AArch64::SADDLPv8i8_v4i16:
11357
0
    case AArch64::SADDLPv8i16_v4i32:
11358
0
    case AArch64::SADDLPv16i8_v8i16:
11359
0
    case AArch64::SADDLVv4i16v:
11360
0
    case AArch64::SADDLVv4i32v:
11361
0
    case AArch64::SADDLVv8i8v:
11362
0
    case AArch64::SADDLVv8i16v:
11363
0
    case AArch64::SADDLVv16i8v:
11364
0
    case AArch64::SCVTFUWDri:
11365
0
    case AArch64::SCVTFUWHri:
11366
0
    case AArch64::SCVTFUWSri:
11367
0
    case AArch64::SCVTFUXDri:
11368
0
    case AArch64::SCVTFUXHri:
11369
0
    case AArch64::SCVTFUXSri:
11370
0
    case AArch64::SCVTFv1i16:
11371
0
    case AArch64::SCVTFv1i32:
11372
0
    case AArch64::SCVTFv1i64:
11373
0
    case AArch64::SCVTFv2f32:
11374
0
    case AArch64::SCVTFv2f64:
11375
0
    case AArch64::SCVTFv4f16:
11376
0
    case AArch64::SCVTFv4f32:
11377
0
    case AArch64::SCVTFv8f16:
11378
0
    case AArch64::SHA1Hrr:
11379
0
    case AArch64::SHLLv2i32:
11380
0
    case AArch64::SHLLv4i16:
11381
0
    case AArch64::SHLLv4i32:
11382
0
    case AArch64::SHLLv8i8:
11383
0
    case AArch64::SHLLv8i16:
11384
0
    case AArch64::SHLLv16i8:
11385
0
    case AArch64::SMAXVv4i16v:
11386
0
    case AArch64::SMAXVv4i32v:
11387
0
    case AArch64::SMAXVv8i8v:
11388
0
    case AArch64::SMAXVv8i16v:
11389
0
    case AArch64::SMAXVv16i8v:
11390
0
    case AArch64::SMINVv4i16v:
11391
0
    case AArch64::SMINVv4i32v:
11392
0
    case AArch64::SMINVv8i8v:
11393
0
    case AArch64::SMINVv8i16v:
11394
0
    case AArch64::SMINVv16i8v:
11395
0
    case AArch64::SMOVvi8to32_idx0:
11396
0
    case AArch64::SMOVvi8to64_idx0:
11397
0
    case AArch64::SMOVvi16to32_idx0:
11398
0
    case AArch64::SMOVvi16to64_idx0:
11399
0
    case AArch64::SMOVvi32to64_idx0:
11400
0
    case AArch64::SQABSv1i8:
11401
0
    case AArch64::SQABSv1i16:
11402
0
    case AArch64::SQABSv1i32:
11403
0
    case AArch64::SQABSv1i64:
11404
0
    case AArch64::SQABSv2i32:
11405
0
    case AArch64::SQABSv2i64:
11406
0
    case AArch64::SQABSv4i16:
11407
0
    case AArch64::SQABSv4i32:
11408
0
    case AArch64::SQABSv8i8:
11409
0
    case AArch64::SQABSv8i16:
11410
0
    case AArch64::SQABSv16i8:
11411
0
    case AArch64::SQNEGv1i8:
11412
0
    case AArch64::SQNEGv1i16:
11413
0
    case AArch64::SQNEGv1i32:
11414
0
    case AArch64::SQNEGv1i64:
11415
0
    case AArch64::SQNEGv2i32:
11416
0
    case AArch64::SQNEGv2i64:
11417
0
    case AArch64::SQNEGv4i16:
11418
0
    case AArch64::SQNEGv4i32:
11419
0
    case AArch64::SQNEGv8i8:
11420
0
    case AArch64::SQNEGv8i16:
11421
0
    case AArch64::SQNEGv16i8:
11422
0
    case AArch64::SQXTNv1i8:
11423
0
    case AArch64::SQXTNv1i16:
11424
0
    case AArch64::SQXTNv1i32:
11425
0
    case AArch64::SQXTNv2i32:
11426
0
    case AArch64::SQXTNv4i16:
11427
0
    case AArch64::SQXTNv8i8:
11428
0
    case AArch64::SQXTUNv1i8:
11429
0
    case AArch64::SQXTUNv1i16:
11430
0
    case AArch64::SQXTUNv1i32:
11431
0
    case AArch64::SQXTUNv2i32:
11432
0
    case AArch64::SQXTUNv4i16:
11433
0
    case AArch64::SQXTUNv8i8:
11434
0
    case AArch64::UADDLPv2i32_v1i64:
11435
0
    case AArch64::UADDLPv4i16_v2i32:
11436
0
    case AArch64::UADDLPv4i32_v2i64:
11437
0
    case AArch64::UADDLPv8i8_v4i16:
11438
0
    case AArch64::UADDLPv8i16_v4i32:
11439
0
    case AArch64::UADDLPv16i8_v8i16:
11440
0
    case AArch64::UADDLVv4i16v:
11441
0
    case AArch64::UADDLVv4i32v:
11442
0
    case AArch64::UADDLVv8i8v:
11443
0
    case AArch64::UADDLVv8i16v:
11444
0
    case AArch64::UADDLVv16i8v:
11445
0
    case AArch64::UCVTFUWDri:
11446
0
    case AArch64::UCVTFUWHri:
11447
0
    case AArch64::UCVTFUWSri:
11448
0
    case AArch64::UCVTFUXDri:
11449
0
    case AArch64::UCVTFUXHri:
11450
0
    case AArch64::UCVTFUXSri:
11451
0
    case AArch64::UCVTFv1i16:
11452
0
    case AArch64::UCVTFv1i32:
11453
0
    case AArch64::UCVTFv1i64:
11454
0
    case AArch64::UCVTFv2f32:
11455
0
    case AArch64::UCVTFv2f64:
11456
0
    case AArch64::UCVTFv4f16:
11457
0
    case AArch64::UCVTFv4f32:
11458
0
    case AArch64::UCVTFv8f16:
11459
0
    case AArch64::UMAXVv4i16v:
11460
0
    case AArch64::UMAXVv4i32v:
11461
0
    case AArch64::UMAXVv8i8v:
11462
0
    case AArch64::UMAXVv8i16v:
11463
0
    case AArch64::UMAXVv16i8v:
11464
0
    case AArch64::UMINVv4i16v:
11465
0
    case AArch64::UMINVv4i32v:
11466
0
    case AArch64::UMINVv8i8v:
11467
0
    case AArch64::UMINVv8i16v:
11468
0
    case AArch64::UMINVv16i8v:
11469
0
    case AArch64::UMOVvi8_idx0:
11470
0
    case AArch64::UMOVvi16_idx0:
11471
0
    case AArch64::UMOVvi32_idx0:
11472
0
    case AArch64::UMOVvi64_idx0:
11473
0
    case AArch64::UQXTNv1i8:
11474
0
    case AArch64::UQXTNv1i16:
11475
0
    case AArch64::UQXTNv1i32:
11476
0
    case AArch64::UQXTNv2i32:
11477
0
    case AArch64::UQXTNv4i16:
11478
0
    case AArch64::UQXTNv8i8:
11479
0
    case AArch64::URECPEv2i32:
11480
0
    case AArch64::URECPEv4i32:
11481
0
    case AArch64::URSQRTEv2i32:
11482
0
    case AArch64::URSQRTEv4i32:
11483
0
    case AArch64::XTNv2i32:
11484
0
    case AArch64::XTNv4i16:
11485
0
    case AArch64::XTNv8i8: {
11486
      // op: Rd
11487
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11488
0
      op &= UINT64_C(31);
11489
0
      Value |= op;
11490
      // op: Rn
11491
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11492
0
      op &= UINT64_C(31);
11493
0
      op <<= 5;
11494
0
      Value |= op;
11495
0
      break;
11496
0
    }
11497
0
    case AArch64::FMULXv1i16_indexed:
11498
0
    case AArch64::FMULXv4i16_indexed:
11499
0
    case AArch64::FMULXv8i16_indexed:
11500
0
    case AArch64::FMULv1i16_indexed:
11501
0
    case AArch64::FMULv4i16_indexed:
11502
0
    case AArch64::FMULv8i16_indexed:
11503
0
    case AArch64::MULv4i16_indexed:
11504
0
    case AArch64::MULv8i16_indexed:
11505
0
    case AArch64::SMULLv4i16_indexed:
11506
0
    case AArch64::SMULLv8i16_indexed:
11507
0
    case AArch64::SQDMULHv1i16_indexed:
11508
0
    case AArch64::SQDMULHv4i16_indexed:
11509
0
    case AArch64::SQDMULHv8i16_indexed:
11510
0
    case AArch64::SQDMULLv1i32_indexed:
11511
0
    case AArch64::SQDMULLv4i16_indexed:
11512
0
    case AArch64::SQDMULLv8i16_indexed:
11513
0
    case AArch64::SQRDMULHv1i16_indexed:
11514
0
    case AArch64::SQRDMULHv4i16_indexed:
11515
0
    case AArch64::SQRDMULHv8i16_indexed:
11516
0
    case AArch64::UMULLv4i16_indexed:
11517
0
    case AArch64::UMULLv8i16_indexed: {
11518
      // op: Rd
11519
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11520
0
      op &= UINT64_C(31);
11521
0
      Value |= op;
11522
      // op: Rn
11523
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11524
0
      op &= UINT64_C(31);
11525
0
      op <<= 5;
11526
0
      Value |= op;
11527
      // op: Rm
11528
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11529
0
      op &= UINT64_C(15);
11530
0
      op <<= 16;
11531
0
      Value |= op;
11532
      // op: idx
11533
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11534
0
      Value |= (op & UINT64_C(3)) << 20;
11535
0
      Value |= (op & UINT64_C(4)) << 9;
11536
0
      break;
11537
0
    }
11538
0
    case AArch64::ADCSWr:
11539
0
    case AArch64::ADCSXr:
11540
0
    case AArch64::ADCWr:
11541
0
    case AArch64::ADCXr:
11542
0
    case AArch64::ADDHNv2i64_v2i32:
11543
0
    case AArch64::ADDHNv4i32_v4i16:
11544
0
    case AArch64::ADDHNv8i16_v8i8:
11545
0
    case AArch64::ADDPv2i32:
11546
0
    case AArch64::ADDPv2i64:
11547
0
    case AArch64::ADDPv4i16:
11548
0
    case AArch64::ADDPv4i32:
11549
0
    case AArch64::ADDPv8i8:
11550
0
    case AArch64::ADDPv8i16:
11551
0
    case AArch64::ADDPv16i8:
11552
0
    case AArch64::ADDv1i64:
11553
0
    case AArch64::ADDv2i32:
11554
0
    case AArch64::ADDv2i64:
11555
0
    case AArch64::ADDv4i16:
11556
0
    case AArch64::ADDv4i32:
11557
0
    case AArch64::ADDv8i8:
11558
0
    case AArch64::ADDv8i16:
11559
0
    case AArch64::ADDv16i8:
11560
0
    case AArch64::ANDv8i8:
11561
0
    case AArch64::ANDv16i8:
11562
0
    case AArch64::ASRVWr:
11563
0
    case AArch64::ASRVXr:
11564
0
    case AArch64::BICv8i8:
11565
0
    case AArch64::BICv16i8:
11566
0
    case AArch64::CMEQv1i64:
11567
0
    case AArch64::CMEQv2i32:
11568
0
    case AArch64::CMEQv2i64:
11569
0
    case AArch64::CMEQv4i16:
11570
0
    case AArch64::CMEQv4i32:
11571
0
    case AArch64::CMEQv8i8:
11572
0
    case AArch64::CMEQv8i16:
11573
0
    case AArch64::CMEQv16i8:
11574
0
    case AArch64::CMGEv1i64:
11575
0
    case AArch64::CMGEv2i32:
11576
0
    case AArch64::CMGEv2i64:
11577
0
    case AArch64::CMGEv4i16:
11578
0
    case AArch64::CMGEv4i32:
11579
0
    case AArch64::CMGEv8i8:
11580
0
    case AArch64::CMGEv8i16:
11581
0
    case AArch64::CMGEv16i8:
11582
0
    case AArch64::CMGTv1i64:
11583
0
    case AArch64::CMGTv2i32:
11584
0
    case AArch64::CMGTv2i64:
11585
0
    case AArch64::CMGTv4i16:
11586
0
    case AArch64::CMGTv4i32:
11587
0
    case AArch64::CMGTv8i8:
11588
0
    case AArch64::CMGTv8i16:
11589
0
    case AArch64::CMGTv16i8:
11590
0
    case AArch64::CMHIv1i64:
11591
0
    case AArch64::CMHIv2i32:
11592
0
    case AArch64::CMHIv2i64:
11593
0
    case AArch64::CMHIv4i16:
11594
0
    case AArch64::CMHIv4i32:
11595
0
    case AArch64::CMHIv8i8:
11596
0
    case AArch64::CMHIv8i16:
11597
0
    case AArch64::CMHIv16i8:
11598
0
    case AArch64::CMHSv1i64:
11599
0
    case AArch64::CMHSv2i32:
11600
0
    case AArch64::CMHSv2i64:
11601
0
    case AArch64::CMHSv4i16:
11602
0
    case AArch64::CMHSv4i32:
11603
0
    case AArch64::CMHSv8i8:
11604
0
    case AArch64::CMHSv8i16:
11605
0
    case AArch64::CMHSv16i8:
11606
0
    case AArch64::CMTSTv1i64:
11607
0
    case AArch64::CMTSTv2i32:
11608
0
    case AArch64::CMTSTv2i64:
11609
0
    case AArch64::CMTSTv4i16:
11610
0
    case AArch64::CMTSTv4i32:
11611
0
    case AArch64::CMTSTv8i8:
11612
0
    case AArch64::CMTSTv8i16:
11613
0
    case AArch64::CMTSTv16i8:
11614
0
    case AArch64::CRC32Brr:
11615
0
    case AArch64::CRC32CBrr:
11616
0
    case AArch64::CRC32CHrr:
11617
0
    case AArch64::CRC32CWrr:
11618
0
    case AArch64::CRC32CXrr:
11619
0
    case AArch64::CRC32Hrr:
11620
0
    case AArch64::CRC32Wrr:
11621
0
    case AArch64::CRC32Xrr:
11622
0
    case AArch64::EORv8i8:
11623
0
    case AArch64::EORv16i8:
11624
0
    case AArch64::FABD16:
11625
0
    case AArch64::FABD32:
11626
0
    case AArch64::FABD64:
11627
0
    case AArch64::FABDv2f32:
11628
0
    case AArch64::FABDv2f64:
11629
0
    case AArch64::FABDv4f16:
11630
0
    case AArch64::FABDv4f32:
11631
0
    case AArch64::FABDv8f16:
11632
0
    case AArch64::FACGE16:
11633
0
    case AArch64::FACGE32:
11634
0
    case AArch64::FACGE64:
11635
0
    case AArch64::FACGEv2f32:
11636
0
    case AArch64::FACGEv2f64:
11637
0
    case AArch64::FACGEv4f16:
11638
0
    case AArch64::FACGEv4f32:
11639
0
    case AArch64::FACGEv8f16:
11640
0
    case AArch64::FACGT16:
11641
0
    case AArch64::FACGT32:
11642
0
    case AArch64::FACGT64:
11643
0
    case AArch64::FACGTv2f32:
11644
0
    case AArch64::FACGTv2f64:
11645
0
    case AArch64::FACGTv4f16:
11646
0
    case AArch64::FACGTv4f32:
11647
0
    case AArch64::FACGTv8f16:
11648
0
    case AArch64::FADDDrr:
11649
0
    case AArch64::FADDHrr:
11650
0
    case AArch64::FADDPv2f32:
11651
0
    case AArch64::FADDPv2f64:
11652
0
    case AArch64::FADDPv4f16:
11653
0
    case AArch64::FADDPv4f32:
11654
0
    case AArch64::FADDPv8f16:
11655
0
    case AArch64::FADDSrr:
11656
0
    case AArch64::FADDv2f32:
11657
0
    case AArch64::FADDv2f64:
11658
0
    case AArch64::FADDv4f16:
11659
0
    case AArch64::FADDv4f32:
11660
0
    case AArch64::FADDv8f16:
11661
0
    case AArch64::FAMAXv2f32:
11662
0
    case AArch64::FAMAXv2f64:
11663
0
    case AArch64::FAMAXv4f16:
11664
0
    case AArch64::FAMAXv4f32:
11665
0
    case AArch64::FAMAXv8f16:
11666
0
    case AArch64::FAMINv2f32:
11667
0
    case AArch64::FAMINv2f64:
11668
0
    case AArch64::FAMINv4f16:
11669
0
    case AArch64::FAMINv4f32:
11670
0
    case AArch64::FAMINv8f16:
11671
0
    case AArch64::FCMEQ16:
11672
0
    case AArch64::FCMEQ32:
11673
0
    case AArch64::FCMEQ64:
11674
0
    case AArch64::FCMEQv2f32:
11675
0
    case AArch64::FCMEQv2f64:
11676
0
    case AArch64::FCMEQv4f16:
11677
0
    case AArch64::FCMEQv4f32:
11678
0
    case AArch64::FCMEQv8f16:
11679
0
    case AArch64::FCMGE16:
11680
0
    case AArch64::FCMGE32:
11681
0
    case AArch64::FCMGE64:
11682
0
    case AArch64::FCMGEv2f32:
11683
0
    case AArch64::FCMGEv2f64:
11684
0
    case AArch64::FCMGEv4f16:
11685
0
    case AArch64::FCMGEv4f32:
11686
0
    case AArch64::FCMGEv8f16:
11687
0
    case AArch64::FCMGT16:
11688
0
    case AArch64::FCMGT32:
11689
0
    case AArch64::FCMGT64:
11690
0
    case AArch64::FCMGTv2f32:
11691
0
    case AArch64::FCMGTv2f64:
11692
0
    case AArch64::FCMGTv4f16:
11693
0
    case AArch64::FCMGTv4f32:
11694
0
    case AArch64::FCMGTv8f16:
11695
0
    case AArch64::FCVTN_F16_F8v8f8:
11696
0
    case AArch64::FCVTN_F16_F8v16f8:
11697
0
    case AArch64::FCVTN_F32_F8v8f8:
11698
0
    case AArch64::FDIVDrr:
11699
0
    case AArch64::FDIVHrr:
11700
0
    case AArch64::FDIVSrr:
11701
0
    case AArch64::FDIVv2f32:
11702
0
    case AArch64::FDIVv2f64:
11703
0
    case AArch64::FDIVv4f16:
11704
0
    case AArch64::FDIVv4f32:
11705
0
    case AArch64::FDIVv8f16:
11706
0
    case AArch64::FMAXDrr:
11707
0
    case AArch64::FMAXHrr:
11708
0
    case AArch64::FMAXNMDrr:
11709
0
    case AArch64::FMAXNMHrr:
11710
0
    case AArch64::FMAXNMPv2f32:
11711
0
    case AArch64::FMAXNMPv2f64:
11712
0
    case AArch64::FMAXNMPv4f16:
11713
0
    case AArch64::FMAXNMPv4f32:
11714
0
    case AArch64::FMAXNMPv8f16:
11715
0
    case AArch64::FMAXNMSrr:
11716
0
    case AArch64::FMAXNMv2f32:
11717
0
    case AArch64::FMAXNMv2f64:
11718
0
    case AArch64::FMAXNMv4f16:
11719
0
    case AArch64::FMAXNMv4f32:
11720
0
    case AArch64::FMAXNMv8f16:
11721
0
    case AArch64::FMAXPv2f32:
11722
0
    case AArch64::FMAXPv2f64:
11723
0
    case AArch64::FMAXPv4f16:
11724
0
    case AArch64::FMAXPv4f32:
11725
0
    case AArch64::FMAXPv8f16:
11726
0
    case AArch64::FMAXSrr:
11727
0
    case AArch64::FMAXv2f32:
11728
0
    case AArch64::FMAXv2f64:
11729
0
    case AArch64::FMAXv4f16:
11730
0
    case AArch64::FMAXv4f32:
11731
0
    case AArch64::FMAXv8f16:
11732
0
    case AArch64::FMINDrr:
11733
0
    case AArch64::FMINHrr:
11734
0
    case AArch64::FMINNMDrr:
11735
0
    case AArch64::FMINNMHrr:
11736
0
    case AArch64::FMINNMPv2f32:
11737
0
    case AArch64::FMINNMPv2f64:
11738
0
    case AArch64::FMINNMPv4f16:
11739
0
    case AArch64::FMINNMPv4f32:
11740
0
    case AArch64::FMINNMPv8f16:
11741
0
    case AArch64::FMINNMSrr:
11742
0
    case AArch64::FMINNMv2f32:
11743
0
    case AArch64::FMINNMv2f64:
11744
0
    case AArch64::FMINNMv4f16:
11745
0
    case AArch64::FMINNMv4f32:
11746
0
    case AArch64::FMINNMv8f16:
11747
0
    case AArch64::FMINPv2f32:
11748
0
    case AArch64::FMINPv2f64:
11749
0
    case AArch64::FMINPv4f16:
11750
0
    case AArch64::FMINPv4f32:
11751
0
    case AArch64::FMINPv8f16:
11752
0
    case AArch64::FMINSrr:
11753
0
    case AArch64::FMINv2f32:
11754
0
    case AArch64::FMINv2f64:
11755
0
    case AArch64::FMINv4f16:
11756
0
    case AArch64::FMINv4f32:
11757
0
    case AArch64::FMINv8f16:
11758
0
    case AArch64::FMULDrr:
11759
0
    case AArch64::FMULHrr:
11760
0
    case AArch64::FMULSrr:
11761
0
    case AArch64::FMULX16:
11762
0
    case AArch64::FMULX32:
11763
0
    case AArch64::FMULX64:
11764
0
    case AArch64::FMULXv2f32:
11765
0
    case AArch64::FMULXv2f64:
11766
0
    case AArch64::FMULXv4f16:
11767
0
    case AArch64::FMULXv4f32:
11768
0
    case AArch64::FMULXv8f16:
11769
0
    case AArch64::FMULv2f32:
11770
0
    case AArch64::FMULv2f64:
11771
0
    case AArch64::FMULv4f16:
11772
0
    case AArch64::FMULv4f32:
11773
0
    case AArch64::FMULv8f16:
11774
0
    case AArch64::FNMULDrr:
11775
0
    case AArch64::FNMULHrr:
11776
0
    case AArch64::FNMULSrr:
11777
0
    case AArch64::FRECPS16:
11778
0
    case AArch64::FRECPS32:
11779
0
    case AArch64::FRECPS64:
11780
0
    case AArch64::FRECPSv2f32:
11781
0
    case AArch64::FRECPSv2f64:
11782
0
    case AArch64::FRECPSv4f16:
11783
0
    case AArch64::FRECPSv4f32:
11784
0
    case AArch64::FRECPSv8f16:
11785
0
    case AArch64::FRSQRTS16:
11786
0
    case AArch64::FRSQRTS32:
11787
0
    case AArch64::FRSQRTS64:
11788
0
    case AArch64::FRSQRTSv2f32:
11789
0
    case AArch64::FRSQRTSv2f64:
11790
0
    case AArch64::FRSQRTSv4f16:
11791
0
    case AArch64::FRSQRTSv4f32:
11792
0
    case AArch64::FRSQRTSv8f16:
11793
0
    case AArch64::FSCALEv2f32:
11794
0
    case AArch64::FSCALEv2f64:
11795
0
    case AArch64::FSCALEv4f16:
11796
0
    case AArch64::FSCALEv4f32:
11797
0
    case AArch64::FSCALEv8f16:
11798
0
    case AArch64::FSUBDrr:
11799
0
    case AArch64::FSUBHrr:
11800
0
    case AArch64::FSUBSrr:
11801
0
    case AArch64::FSUBv2f32:
11802
0
    case AArch64::FSUBv2f64:
11803
0
    case AArch64::FSUBv4f16:
11804
0
    case AArch64::FSUBv4f32:
11805
0
    case AArch64::FSUBv8f16:
11806
0
    case AArch64::GMI:
11807
0
    case AArch64::IRG:
11808
0
    case AArch64::LSLVWr:
11809
0
    case AArch64::LSLVXr:
11810
0
    case AArch64::LSRVWr:
11811
0
    case AArch64::LSRVXr:
11812
0
    case AArch64::MULv2i32:
11813
0
    case AArch64::MULv4i16:
11814
0
    case AArch64::MULv4i32:
11815
0
    case AArch64::MULv8i8:
11816
0
    case AArch64::MULv8i16:
11817
0
    case AArch64::MULv16i8:
11818
0
    case AArch64::ORNv8i8:
11819
0
    case AArch64::ORNv16i8:
11820
0
    case AArch64::ORRv8i8:
11821
0
    case AArch64::ORRv16i8:
11822
0
    case AArch64::PACGA:
11823
0
    case AArch64::PMULLv1i64:
11824
0
    case AArch64::PMULLv2i64:
11825
0
    case AArch64::PMULLv8i8:
11826
0
    case AArch64::PMULLv16i8:
11827
0
    case AArch64::PMULv8i8:
11828
0
    case AArch64::PMULv16i8:
11829
0
    case AArch64::RADDHNv2i64_v2i32:
11830
0
    case AArch64::RADDHNv4i32_v4i16:
11831
0
    case AArch64::RADDHNv8i16_v8i8:
11832
0
    case AArch64::RORVWr:
11833
0
    case AArch64::RORVXr:
11834
0
    case AArch64::RSUBHNv2i64_v2i32:
11835
0
    case AArch64::RSUBHNv4i32_v4i16:
11836
0
    case AArch64::RSUBHNv8i16_v8i8:
11837
0
    case AArch64::SABDLv2i32_v2i64:
11838
0
    case AArch64::SABDLv4i16_v4i32:
11839
0
    case AArch64::SABDLv4i32_v2i64:
11840
0
    case AArch64::SABDLv8i8_v8i16:
11841
0
    case AArch64::SABDLv8i16_v4i32:
11842
0
    case AArch64::SABDLv16i8_v8i16:
11843
0
    case AArch64::SABDv2i32:
11844
0
    case AArch64::SABDv4i16:
11845
0
    case AArch64::SABDv4i32:
11846
0
    case AArch64::SABDv8i8:
11847
0
    case AArch64::SABDv8i16:
11848
0
    case AArch64::SABDv16i8:
11849
0
    case AArch64::SADDLv2i32_v2i64:
11850
0
    case AArch64::SADDLv4i16_v4i32:
11851
0
    case AArch64::SADDLv4i32_v2i64:
11852
0
    case AArch64::SADDLv8i8_v8i16:
11853
0
    case AArch64::SADDLv8i16_v4i32:
11854
0
    case AArch64::SADDLv16i8_v8i16:
11855
0
    case AArch64::SADDWv2i32_v2i64:
11856
0
    case AArch64::SADDWv4i16_v4i32:
11857
0
    case AArch64::SADDWv4i32_v2i64:
11858
0
    case AArch64::SADDWv8i8_v8i16:
11859
0
    case AArch64::SADDWv8i16_v4i32:
11860
0
    case AArch64::SADDWv16i8_v8i16:
11861
0
    case AArch64::SBCSWr:
11862
0
    case AArch64::SBCSXr:
11863
0
    case AArch64::SBCWr:
11864
0
    case AArch64::SBCXr:
11865
0
    case AArch64::SDIVWr:
11866
0
    case AArch64::SDIVXr:
11867
0
    case AArch64::SHADDv2i32:
11868
0
    case AArch64::SHADDv4i16:
11869
0
    case AArch64::SHADDv4i32:
11870
0
    case AArch64::SHADDv8i8:
11871
0
    case AArch64::SHADDv8i16:
11872
0
    case AArch64::SHADDv16i8:
11873
0
    case AArch64::SHSUBv2i32:
11874
0
    case AArch64::SHSUBv4i16:
11875
0
    case AArch64::SHSUBv4i32:
11876
0
    case AArch64::SHSUBv8i8:
11877
0
    case AArch64::SHSUBv8i16:
11878
0
    case AArch64::SHSUBv16i8:
11879
0
    case AArch64::SMAXPv2i32:
11880
0
    case AArch64::SMAXPv4i16:
11881
0
    case AArch64::SMAXPv4i32:
11882
0
    case AArch64::SMAXPv8i8:
11883
0
    case AArch64::SMAXPv8i16:
11884
0
    case AArch64::SMAXPv16i8:
11885
0
    case AArch64::SMAXWrr:
11886
0
    case AArch64::SMAXXrr:
11887
0
    case AArch64::SMAXv2i32:
11888
0
    case AArch64::SMAXv4i16:
11889
0
    case AArch64::SMAXv4i32:
11890
0
    case AArch64::SMAXv8i8:
11891
0
    case AArch64::SMAXv8i16:
11892
0
    case AArch64::SMAXv16i8:
11893
0
    case AArch64::SMINPv2i32:
11894
0
    case AArch64::SMINPv4i16:
11895
0
    case AArch64::SMINPv4i32:
11896
0
    case AArch64::SMINPv8i8:
11897
0
    case AArch64::SMINPv8i16:
11898
0
    case AArch64::SMINPv16i8:
11899
0
    case AArch64::SMINWrr:
11900
0
    case AArch64::SMINXrr:
11901
0
    case AArch64::SMINv2i32:
11902
0
    case AArch64::SMINv4i16:
11903
0
    case AArch64::SMINv4i32:
11904
0
    case AArch64::SMINv8i8:
11905
0
    case AArch64::SMINv8i16:
11906
0
    case AArch64::SMINv16i8:
11907
0
    case AArch64::SMULLv2i32_v2i64:
11908
0
    case AArch64::SMULLv4i16_v4i32:
11909
0
    case AArch64::SMULLv4i32_v2i64:
11910
0
    case AArch64::SMULLv8i8_v8i16:
11911
0
    case AArch64::SMULLv8i16_v4i32:
11912
0
    case AArch64::SMULLv16i8_v8i16:
11913
0
    case AArch64::SQADDv1i8:
11914
0
    case AArch64::SQADDv1i16:
11915
0
    case AArch64::SQADDv1i32:
11916
0
    case AArch64::SQADDv1i64:
11917
0
    case AArch64::SQADDv2i32:
11918
0
    case AArch64::SQADDv2i64:
11919
0
    case AArch64::SQADDv4i16:
11920
0
    case AArch64::SQADDv4i32:
11921
0
    case AArch64::SQADDv8i8:
11922
0
    case AArch64::SQADDv8i16:
11923
0
    case AArch64::SQADDv16i8:
11924
0
    case AArch64::SQDMULHv1i16:
11925
0
    case AArch64::SQDMULHv1i32:
11926
0
    case AArch64::SQDMULHv2i32:
11927
0
    case AArch64::SQDMULHv4i16:
11928
0
    case AArch64::SQDMULHv4i32:
11929
0
    case AArch64::SQDMULHv8i16:
11930
0
    case AArch64::SQDMULLi16:
11931
0
    case AArch64::SQDMULLi32:
11932
0
    case AArch64::SQDMULLv2i32_v2i64:
11933
0
    case AArch64::SQDMULLv4i16_v4i32:
11934
0
    case AArch64::SQDMULLv4i32_v2i64:
11935
0
    case AArch64::SQDMULLv8i16_v4i32:
11936
0
    case AArch64::SQRDMULHv1i16:
11937
0
    case AArch64::SQRDMULHv1i32:
11938
0
    case AArch64::SQRDMULHv2i32:
11939
0
    case AArch64::SQRDMULHv4i16:
11940
0
    case AArch64::SQRDMULHv4i32:
11941
0
    case AArch64::SQRDMULHv8i16:
11942
0
    case AArch64::SQRSHLv1i8:
11943
0
    case AArch64::SQRSHLv1i16:
11944
0
    case AArch64::SQRSHLv1i32:
11945
0
    case AArch64::SQRSHLv1i64:
11946
0
    case AArch64::SQRSHLv2i32:
11947
0
    case AArch64::SQRSHLv2i64:
11948
0
    case AArch64::SQRSHLv4i16:
11949
0
    case AArch64::SQRSHLv4i32:
11950
0
    case AArch64::SQRSHLv8i8:
11951
0
    case AArch64::SQRSHLv8i16:
11952
0
    case AArch64::SQRSHLv16i8:
11953
0
    case AArch64::SQSHLv1i8:
11954
0
    case AArch64::SQSHLv1i16:
11955
0
    case AArch64::SQSHLv1i32:
11956
0
    case AArch64::SQSHLv1i64:
11957
0
    case AArch64::SQSHLv2i32:
11958
0
    case AArch64::SQSHLv2i64:
11959
0
    case AArch64::SQSHLv4i16:
11960
0
    case AArch64::SQSHLv4i32:
11961
0
    case AArch64::SQSHLv8i8:
11962
0
    case AArch64::SQSHLv8i16:
11963
0
    case AArch64::SQSHLv16i8:
11964
0
    case AArch64::SQSUBv1i8:
11965
0
    case AArch64::SQSUBv1i16:
11966
0
    case AArch64::SQSUBv1i32:
11967
0
    case AArch64::SQSUBv1i64:
11968
0
    case AArch64::SQSUBv2i32:
11969
0
    case AArch64::SQSUBv2i64:
11970
0
    case AArch64::SQSUBv4i16:
11971
0
    case AArch64::SQSUBv4i32:
11972
0
    case AArch64::SQSUBv8i8:
11973
0
    case AArch64::SQSUBv8i16:
11974
0
    case AArch64::SQSUBv16i8:
11975
0
    case AArch64::SRHADDv2i32:
11976
0
    case AArch64::SRHADDv4i16:
11977
0
    case AArch64::SRHADDv4i32:
11978
0
    case AArch64::SRHADDv8i8:
11979
0
    case AArch64::SRHADDv8i16:
11980
0
    case AArch64::SRHADDv16i8:
11981
0
    case AArch64::SRSHLv1i64:
11982
0
    case AArch64::SRSHLv2i32:
11983
0
    case AArch64::SRSHLv2i64:
11984
0
    case AArch64::SRSHLv4i16:
11985
0
    case AArch64::SRSHLv4i32:
11986
0
    case AArch64::SRSHLv8i8:
11987
0
    case AArch64::SRSHLv8i16:
11988
0
    case AArch64::SRSHLv16i8:
11989
0
    case AArch64::SSHLv1i64:
11990
0
    case AArch64::SSHLv2i32:
11991
0
    case AArch64::SSHLv2i64:
11992
0
    case AArch64::SSHLv4i16:
11993
0
    case AArch64::SSHLv4i32:
11994
0
    case AArch64::SSHLv8i8:
11995
0
    case AArch64::SSHLv8i16:
11996
0
    case AArch64::SSHLv16i8:
11997
0
    case AArch64::SSUBLv2i32_v2i64:
11998
0
    case AArch64::SSUBLv4i16_v4i32:
11999
0
    case AArch64::SSUBLv4i32_v2i64:
12000
0
    case AArch64::SSUBLv8i8_v8i16:
12001
0
    case AArch64::SSUBLv8i16_v4i32:
12002
0
    case AArch64::SSUBLv16i8_v8i16:
12003
0
    case AArch64::SSUBWv2i32_v2i64:
12004
0
    case AArch64::SSUBWv4i16_v4i32:
12005
0
    case AArch64::SSUBWv4i32_v2i64:
12006
0
    case AArch64::SSUBWv8i8_v8i16:
12007
0
    case AArch64::SSUBWv8i16_v4i32:
12008
0
    case AArch64::SSUBWv16i8_v8i16:
12009
0
    case AArch64::SUBHNv2i64_v2i32:
12010
0
    case AArch64::SUBHNv4i32_v4i16:
12011
0
    case AArch64::SUBHNv8i16_v8i8:
12012
0
    case AArch64::SUBP:
12013
0
    case AArch64::SUBPS:
12014
0
    case AArch64::SUBv1i64:
12015
0
    case AArch64::SUBv2i32:
12016
0
    case AArch64::SUBv2i64:
12017
0
    case AArch64::SUBv4i16:
12018
0
    case AArch64::SUBv4i32:
12019
0
    case AArch64::SUBv8i8:
12020
0
    case AArch64::SUBv8i16:
12021
0
    case AArch64::SUBv16i8:
12022
0
    case AArch64::TRN1v2i32:
12023
0
    case AArch64::TRN1v2i64:
12024
0
    case AArch64::TRN1v4i16:
12025
0
    case AArch64::TRN1v4i32:
12026
0
    case AArch64::TRN1v8i8:
12027
0
    case AArch64::TRN1v8i16:
12028
0
    case AArch64::TRN1v16i8:
12029
0
    case AArch64::TRN2v2i32:
12030
0
    case AArch64::TRN2v2i64:
12031
0
    case AArch64::TRN2v4i16:
12032
0
    case AArch64::TRN2v4i32:
12033
0
    case AArch64::TRN2v8i8:
12034
0
    case AArch64::TRN2v8i16:
12035
0
    case AArch64::TRN2v16i8:
12036
0
    case AArch64::UABDLv2i32_v2i64:
12037
0
    case AArch64::UABDLv4i16_v4i32:
12038
0
    case AArch64::UABDLv4i32_v2i64:
12039
0
    case AArch64::UABDLv8i8_v8i16:
12040
0
    case AArch64::UABDLv8i16_v4i32:
12041
0
    case AArch64::UABDLv16i8_v8i16:
12042
0
    case AArch64::UABDv2i32:
12043
0
    case AArch64::UABDv4i16:
12044
0
    case AArch64::UABDv4i32:
12045
0
    case AArch64::UABDv8i8:
12046
0
    case AArch64::UABDv8i16:
12047
0
    case AArch64::UABDv16i8:
12048
0
    case AArch64::UADDLv2i32_v2i64:
12049
0
    case AArch64::UADDLv4i16_v4i32:
12050
0
    case AArch64::UADDLv4i32_v2i64:
12051
0
    case AArch64::UADDLv8i8_v8i16:
12052
0
    case AArch64::UADDLv8i16_v4i32:
12053
0
    case AArch64::UADDLv16i8_v8i16:
12054
0
    case AArch64::UADDWv2i32_v2i64:
12055
0
    case AArch64::UADDWv4i16_v4i32:
12056
0
    case AArch64::UADDWv4i32_v2i64:
12057
0
    case AArch64::UADDWv8i8_v8i16:
12058
0
    case AArch64::UADDWv8i16_v4i32:
12059
0
    case AArch64::UADDWv16i8_v8i16:
12060
0
    case AArch64::UDIVWr:
12061
0
    case AArch64::UDIVXr:
12062
0
    case AArch64::UHADDv2i32:
12063
0
    case AArch64::UHADDv4i16:
12064
0
    case AArch64::UHADDv4i32:
12065
0
    case AArch64::UHADDv8i8:
12066
0
    case AArch64::UHADDv8i16:
12067
0
    case AArch64::UHADDv16i8:
12068
0
    case AArch64::UHSUBv2i32:
12069
0
    case AArch64::UHSUBv4i16:
12070
0
    case AArch64::UHSUBv4i32:
12071
0
    case AArch64::UHSUBv8i8:
12072
0
    case AArch64::UHSUBv8i16:
12073
0
    case AArch64::UHSUBv16i8:
12074
0
    case AArch64::UMAXPv2i32:
12075
0
    case AArch64::UMAXPv4i16:
12076
0
    case AArch64::UMAXPv4i32:
12077
0
    case AArch64::UMAXPv8i8:
12078
0
    case AArch64::UMAXPv8i16:
12079
0
    case AArch64::UMAXPv16i8:
12080
0
    case AArch64::UMAXWrr:
12081
0
    case AArch64::UMAXXrr:
12082
0
    case AArch64::UMAXv2i32:
12083
0
    case AArch64::UMAXv4i16:
12084
0
    case AArch64::UMAXv4i32:
12085
0
    case AArch64::UMAXv8i8:
12086
0
    case AArch64::UMAXv8i16:
12087
0
    case AArch64::UMAXv16i8:
12088
0
    case AArch64::UMINPv2i32:
12089
0
    case AArch64::UMINPv4i16:
12090
0
    case AArch64::UMINPv4i32:
12091
0
    case AArch64::UMINPv8i8:
12092
0
    case AArch64::UMINPv8i16:
12093
0
    case AArch64::UMINPv16i8:
12094
0
    case AArch64::UMINWrr:
12095
0
    case AArch64::UMINXrr:
12096
0
    case AArch64::UMINv2i32:
12097
0
    case AArch64::UMINv4i16:
12098
0
    case AArch64::UMINv4i32:
12099
0
    case AArch64::UMINv8i8:
12100
0
    case AArch64::UMINv8i16:
12101
0
    case AArch64::UMINv16i8:
12102
0
    case AArch64::UMULLv2i32_v2i64:
12103
0
    case AArch64::UMULLv4i16_v4i32:
12104
0
    case AArch64::UMULLv4i32_v2i64:
12105
0
    case AArch64::UMULLv8i8_v8i16:
12106
0
    case AArch64::UMULLv8i16_v4i32:
12107
0
    case AArch64::UMULLv16i8_v8i16:
12108
0
    case AArch64::UQADDv1i8:
12109
0
    case AArch64::UQADDv1i16:
12110
0
    case AArch64::UQADDv1i32:
12111
0
    case AArch64::UQADDv1i64:
12112
0
    case AArch64::UQADDv2i32:
12113
0
    case AArch64::UQADDv2i64:
12114
0
    case AArch64::UQADDv4i16:
12115
0
    case AArch64::UQADDv4i32:
12116
0
    case AArch64::UQADDv8i8:
12117
0
    case AArch64::UQADDv8i16:
12118
0
    case AArch64::UQADDv16i8:
12119
0
    case AArch64::UQRSHLv1i8:
12120
0
    case AArch64::UQRSHLv1i16:
12121
0
    case AArch64::UQRSHLv1i32:
12122
0
    case AArch64::UQRSHLv1i64:
12123
0
    case AArch64::UQRSHLv2i32:
12124
0
    case AArch64::UQRSHLv2i64:
12125
0
    case AArch64::UQRSHLv4i16:
12126
0
    case AArch64::UQRSHLv4i32:
12127
0
    case AArch64::UQRSHLv8i8:
12128
0
    case AArch64::UQRSHLv8i16:
12129
0
    case AArch64::UQRSHLv16i8:
12130
0
    case AArch64::UQSHLv1i8:
12131
0
    case AArch64::UQSHLv1i16:
12132
0
    case AArch64::UQSHLv1i32:
12133
0
    case AArch64::UQSHLv1i64:
12134
0
    case AArch64::UQSHLv2i32:
12135
0
    case AArch64::UQSHLv2i64:
12136
0
    case AArch64::UQSHLv4i16:
12137
0
    case AArch64::UQSHLv4i32:
12138
0
    case AArch64::UQSHLv8i8:
12139
0
    case AArch64::UQSHLv8i16:
12140
0
    case AArch64::UQSHLv16i8:
12141
0
    case AArch64::UQSUBv1i8:
12142
0
    case AArch64::UQSUBv1i16:
12143
0
    case AArch64::UQSUBv1i32:
12144
0
    case AArch64::UQSUBv1i64:
12145
0
    case AArch64::UQSUBv2i32:
12146
0
    case AArch64::UQSUBv2i64:
12147
0
    case AArch64::UQSUBv4i16:
12148
0
    case AArch64::UQSUBv4i32:
12149
0
    case AArch64::UQSUBv8i8:
12150
0
    case AArch64::UQSUBv8i16:
12151
0
    case AArch64::UQSUBv16i8:
12152
0
    case AArch64::URHADDv2i32:
12153
0
    case AArch64::URHADDv4i16:
12154
0
    case AArch64::URHADDv4i32:
12155
0
    case AArch64::URHADDv8i8:
12156
0
    case AArch64::URHADDv8i16:
12157
0
    case AArch64::URHADDv16i8:
12158
0
    case AArch64::URSHLv1i64:
12159
0
    case AArch64::URSHLv2i32:
12160
0
    case AArch64::URSHLv2i64:
12161
0
    case AArch64::URSHLv4i16:
12162
0
    case AArch64::URSHLv4i32:
12163
0
    case AArch64::URSHLv8i8:
12164
0
    case AArch64::URSHLv8i16:
12165
0
    case AArch64::URSHLv16i8:
12166
0
    case AArch64::USHLv1i64:
12167
0
    case AArch64::USHLv2i32:
12168
0
    case AArch64::USHLv2i64:
12169
0
    case AArch64::USHLv4i16:
12170
0
    case AArch64::USHLv4i32:
12171
0
    case AArch64::USHLv8i8:
12172
0
    case AArch64::USHLv8i16:
12173
0
    case AArch64::USHLv16i8:
12174
0
    case AArch64::USUBLv2i32_v2i64:
12175
0
    case AArch64::USUBLv4i16_v4i32:
12176
0
    case AArch64::USUBLv4i32_v2i64:
12177
0
    case AArch64::USUBLv8i8_v8i16:
12178
0
    case AArch64::USUBLv8i16_v4i32:
12179
0
    case AArch64::USUBLv16i8_v8i16:
12180
0
    case AArch64::USUBWv2i32_v2i64:
12181
0
    case AArch64::USUBWv4i16_v4i32:
12182
0
    case AArch64::USUBWv4i32_v2i64:
12183
0
    case AArch64::USUBWv8i8_v8i16:
12184
0
    case AArch64::USUBWv8i16_v4i32:
12185
0
    case AArch64::USUBWv16i8_v8i16:
12186
0
    case AArch64::UZP1v2i32:
12187
0
    case AArch64::UZP1v2i64:
12188
0
    case AArch64::UZP1v4i16:
12189
0
    case AArch64::UZP1v4i32:
12190
0
    case AArch64::UZP1v8i8:
12191
0
    case AArch64::UZP1v8i16:
12192
0
    case AArch64::UZP1v16i8:
12193
0
    case AArch64::UZP2v2i32:
12194
0
    case AArch64::UZP2v2i64:
12195
0
    case AArch64::UZP2v4i16:
12196
0
    case AArch64::UZP2v4i32:
12197
0
    case AArch64::UZP2v8i8:
12198
0
    case AArch64::UZP2v8i16:
12199
0
    case AArch64::UZP2v16i8:
12200
0
    case AArch64::ZIP1v2i32:
12201
0
    case AArch64::ZIP1v2i64:
12202
0
    case AArch64::ZIP1v4i16:
12203
0
    case AArch64::ZIP1v4i32:
12204
0
    case AArch64::ZIP1v8i8:
12205
0
    case AArch64::ZIP1v8i16:
12206
0
    case AArch64::ZIP1v16i8:
12207
0
    case AArch64::ZIP2v2i32:
12208
0
    case AArch64::ZIP2v2i64:
12209
0
    case AArch64::ZIP2v4i16:
12210
0
    case AArch64::ZIP2v4i32:
12211
0
    case AArch64::ZIP2v8i8:
12212
0
    case AArch64::ZIP2v8i16:
12213
0
    case AArch64::ZIP2v16i8: {
12214
      // op: Rd
12215
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12216
0
      op &= UINT64_C(31);
12217
0
      Value |= op;
12218
      // op: Rn
12219
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12220
0
      op &= UINT64_C(31);
12221
0
      op <<= 5;
12222
0
      Value |= op;
12223
      // op: Rm
12224
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12225
0
      op &= UINT64_C(31);
12226
0
      op <<= 16;
12227
0
      Value |= op;
12228
0
      break;
12229
0
    }
12230
0
    case AArch64::FMADDDrrr:
12231
0
    case AArch64::FMADDHrrr:
12232
0
    case AArch64::FMADDSrrr:
12233
0
    case AArch64::FMSUBDrrr:
12234
0
    case AArch64::FMSUBHrrr:
12235
0
    case AArch64::FMSUBSrrr:
12236
0
    case AArch64::FNMADDDrrr:
12237
0
    case AArch64::FNMADDHrrr:
12238
0
    case AArch64::FNMADDSrrr:
12239
0
    case AArch64::FNMSUBDrrr:
12240
0
    case AArch64::FNMSUBHrrr:
12241
0
    case AArch64::FNMSUBSrrr:
12242
0
    case AArch64::MADDPT:
12243
0
    case AArch64::MADDWrrr:
12244
0
    case AArch64::MADDXrrr:
12245
0
    case AArch64::MSUBPT:
12246
0
    case AArch64::MSUBWrrr:
12247
0
    case AArch64::MSUBXrrr:
12248
0
    case AArch64::SMADDLrrr:
12249
0
    case AArch64::SMSUBLrrr:
12250
0
    case AArch64::UMADDLrrr:
12251
0
    case AArch64::UMSUBLrrr: {
12252
      // op: Rd
12253
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12254
0
      op &= UINT64_C(31);
12255
0
      Value |= op;
12256
      // op: Rn
12257
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12258
0
      op &= UINT64_C(31);
12259
0
      op <<= 5;
12260
0
      Value |= op;
12261
      // op: Rm
12262
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12263
0
      op &= UINT64_C(31);
12264
0
      op <<= 16;
12265
0
      Value |= op;
12266
      // op: Ra
12267
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12268
0
      op &= UINT64_C(31);
12269
0
      op <<= 10;
12270
0
      Value |= op;
12271
0
      break;
12272
0
    }
12273
0
    case AArch64::CSELWr:
12274
0
    case AArch64::CSELXr:
12275
0
    case AArch64::CSINCWr:
12276
0
    case AArch64::CSINCXr:
12277
0
    case AArch64::CSINVWr:
12278
0
    case AArch64::CSINVXr:
12279
0
    case AArch64::CSNEGWr:
12280
0
    case AArch64::CSNEGXr:
12281
0
    case AArch64::FCSELDrrr:
12282
0
    case AArch64::FCSELHrrr:
12283
0
    case AArch64::FCSELSrrr: {
12284
      // op: Rd
12285
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12286
0
      op &= UINT64_C(31);
12287
0
      Value |= op;
12288
      // op: Rn
12289
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12290
0
      op &= UINT64_C(31);
12291
0
      op <<= 5;
12292
0
      Value |= op;
12293
      // op: Rm
12294
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12295
0
      op &= UINT64_C(31);
12296
0
      op <<= 16;
12297
0
      Value |= op;
12298
      // op: cond
12299
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12300
0
      op &= UINT64_C(15);
12301
0
      op <<= 12;
12302
0
      Value |= op;
12303
0
      break;
12304
0
    }
12305
0
    case AArch64::ADDSXrx64:
12306
0
    case AArch64::ADDXrx64:
12307
0
    case AArch64::SUBSXrx64:
12308
0
    case AArch64::SUBXrx64: {
12309
      // op: Rd
12310
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12311
0
      op &= UINT64_C(31);
12312
0
      Value |= op;
12313
      // op: Rn
12314
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12315
0
      op &= UINT64_C(31);
12316
0
      op <<= 5;
12317
0
      Value |= op;
12318
      // op: Rm
12319
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12320
0
      op &= UINT64_C(31);
12321
0
      op <<= 16;
12322
0
      Value |= op;
12323
      // op: ext
12324
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12325
0
      Value |= (op & UINT64_C(32)) << 10;
12326
0
      Value |= (op & UINT64_C(7)) << 10;
12327
0
      break;
12328
0
    }
12329
0
    case AArch64::ADDSWrx:
12330
0
    case AArch64::ADDSXrx:
12331
0
    case AArch64::ADDWrx:
12332
0
    case AArch64::ADDXrx:
12333
0
    case AArch64::SUBSWrx:
12334
0
    case AArch64::SUBSXrx:
12335
0
    case AArch64::SUBWrx:
12336
0
    case AArch64::SUBXrx: {
12337
      // op: Rd
12338
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12339
0
      op &= UINT64_C(31);
12340
0
      Value |= op;
12341
      // op: Rn
12342
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12343
0
      op &= UINT64_C(31);
12344
0
      op <<= 5;
12345
0
      Value |= op;
12346
      // op: Rm
12347
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12348
0
      op &= UINT64_C(31);
12349
0
      op <<= 16;
12350
0
      Value |= op;
12351
      // op: extend
12352
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12353
0
      op &= UINT64_C(63);
12354
0
      op <<= 10;
12355
0
      Value |= op;
12356
0
      break;
12357
0
    }
12358
0
    case AArch64::FMULXv1i32_indexed:
12359
0
    case AArch64::FMULXv2i32_indexed:
12360
0
    case AArch64::FMULXv4i32_indexed:
12361
0
    case AArch64::FMULv1i32_indexed:
12362
0
    case AArch64::FMULv2i32_indexed:
12363
0
    case AArch64::FMULv4i32_indexed:
12364
0
    case AArch64::MULv2i32_indexed:
12365
0
    case AArch64::MULv4i32_indexed:
12366
0
    case AArch64::SMULLv2i32_indexed:
12367
0
    case AArch64::SMULLv4i32_indexed:
12368
0
    case AArch64::SQDMULHv1i32_indexed:
12369
0
    case AArch64::SQDMULHv2i32_indexed:
12370
0
    case AArch64::SQDMULHv4i32_indexed:
12371
0
    case AArch64::SQDMULLv1i64_indexed:
12372
0
    case AArch64::SQDMULLv2i32_indexed:
12373
0
    case AArch64::SQDMULLv4i32_indexed:
12374
0
    case AArch64::SQRDMULHv1i32_indexed:
12375
0
    case AArch64::SQRDMULHv2i32_indexed:
12376
0
    case AArch64::SQRDMULHv4i32_indexed:
12377
0
    case AArch64::UMULLv2i32_indexed:
12378
0
    case AArch64::UMULLv4i32_indexed: {
12379
      // op: Rd
12380
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12381
0
      op &= UINT64_C(31);
12382
0
      Value |= op;
12383
      // op: Rn
12384
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12385
0
      op &= UINT64_C(31);
12386
0
      op <<= 5;
12387
0
      Value |= op;
12388
      // op: Rm
12389
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12390
0
      op &= UINT64_C(31);
12391
0
      op <<= 16;
12392
0
      Value |= op;
12393
      // op: idx
12394
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12395
0
      Value |= (op & UINT64_C(1)) << 21;
12396
0
      Value |= (op & UINT64_C(2)) << 10;
12397
0
      break;
12398
0
    }
12399
0
    case AArch64::FMULXv1i64_indexed:
12400
0
    case AArch64::FMULXv2i64_indexed:
12401
0
    case AArch64::FMULv1i64_indexed:
12402
0
    case AArch64::FMULv2i64_indexed: {
12403
      // op: Rd
12404
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12405
0
      op &= UINT64_C(31);
12406
0
      Value |= op;
12407
      // op: Rn
12408
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12409
0
      op &= UINT64_C(31);
12410
0
      op <<= 5;
12411
0
      Value |= op;
12412
      // op: Rm
12413
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12414
0
      op &= UINT64_C(31);
12415
0
      op <<= 16;
12416
0
      Value |= op;
12417
      // op: idx
12418
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12419
0
      op &= UINT64_C(1);
12420
0
      op <<= 11;
12421
0
      Value |= op;
12422
0
      break;
12423
0
    }
12424
0
    case AArch64::LUT4v16f8: {
12425
      // op: Rd
12426
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12427
0
      op &= UINT64_C(31);
12428
0
      Value |= op;
12429
      // op: Rn
12430
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12431
0
      op &= UINT64_C(31);
12432
0
      op <<= 5;
12433
0
      Value |= op;
12434
      // op: Rm
12435
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12436
0
      op &= UINT64_C(31);
12437
0
      op <<= 16;
12438
0
      Value |= op;
12439
      // op: idx
12440
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12441
0
      op &= UINT64_C(1);
12442
0
      op <<= 14;
12443
0
      Value |= op;
12444
0
      break;
12445
0
    }
12446
0
    case AArch64::LUT2v16f8:
12447
0
    case AArch64::LUT4v8f16: {
12448
      // op: Rd
12449
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12450
0
      op &= UINT64_C(31);
12451
0
      Value |= op;
12452
      // op: Rn
12453
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12454
0
      op &= UINT64_C(31);
12455
0
      op <<= 5;
12456
0
      Value |= op;
12457
      // op: Rm
12458
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12459
0
      op &= UINT64_C(31);
12460
0
      op <<= 16;
12461
0
      Value |= op;
12462
      // op: idx
12463
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12464
0
      op &= UINT64_C(3);
12465
0
      op <<= 13;
12466
0
      Value |= op;
12467
0
      break;
12468
0
    }
12469
0
    case AArch64::LUT2v8f16: {
12470
      // op: Rd
12471
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12472
0
      op &= UINT64_C(31);
12473
0
      Value |= op;
12474
      // op: Rn
12475
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12476
0
      op &= UINT64_C(31);
12477
0
      op <<= 5;
12478
0
      Value |= op;
12479
      // op: Rm
12480
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12481
0
      op &= UINT64_C(31);
12482
0
      op <<= 16;
12483
0
      Value |= op;
12484
      // op: idx
12485
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12486
0
      op &= UINT64_C(7);
12487
0
      op <<= 12;
12488
0
      Value |= op;
12489
0
      break;
12490
0
    }
12491
0
    case AArch64::EXTv16i8: {
12492
      // op: Rd
12493
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12494
0
      op &= UINT64_C(31);
12495
0
      Value |= op;
12496
      // op: Rn
12497
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12498
0
      op &= UINT64_C(31);
12499
0
      op <<= 5;
12500
0
      Value |= op;
12501
      // op: Rm
12502
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12503
0
      op &= UINT64_C(31);
12504
0
      op <<= 16;
12505
0
      Value |= op;
12506
      // op: imm
12507
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12508
0
      op &= UINT64_C(15);
12509
0
      op <<= 11;
12510
0
      Value |= op;
12511
0
      break;
12512
0
    }
12513
0
    case AArch64::EXTRWrri: {
12514
      // op: Rd
12515
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12516
0
      op &= UINT64_C(31);
12517
0
      Value |= op;
12518
      // op: Rn
12519
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12520
0
      op &= UINT64_C(31);
12521
0
      op <<= 5;
12522
0
      Value |= op;
12523
      // op: Rm
12524
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12525
0
      op &= UINT64_C(31);
12526
0
      op <<= 16;
12527
0
      Value |= op;
12528
      // op: imm
12529
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12530
0
      op &= UINT64_C(31);
12531
0
      op <<= 10;
12532
0
      Value |= op;
12533
0
      break;
12534
0
    }
12535
0
    case AArch64::EXTRXrri: {
12536
      // op: Rd
12537
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12538
0
      op &= UINT64_C(31);
12539
0
      Value |= op;
12540
      // op: Rn
12541
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12542
0
      op &= UINT64_C(31);
12543
0
      op <<= 5;
12544
0
      Value |= op;
12545
      // op: Rm
12546
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12547
0
      op &= UINT64_C(31);
12548
0
      op <<= 16;
12549
0
      Value |= op;
12550
      // op: imm
12551
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12552
0
      op &= UINT64_C(63);
12553
0
      op <<= 10;
12554
0
      Value |= op;
12555
0
      break;
12556
0
    }
12557
0
    case AArch64::EXTv8i8: {
12558
      // op: Rd
12559
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12560
0
      op &= UINT64_C(31);
12561
0
      Value |= op;
12562
      // op: Rn
12563
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12564
0
      op &= UINT64_C(31);
12565
0
      op <<= 5;
12566
0
      Value |= op;
12567
      // op: Rm
12568
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12569
0
      op &= UINT64_C(31);
12570
0
      op <<= 16;
12571
0
      Value |= op;
12572
      // op: imm
12573
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12574
0
      op &= UINT64_C(7);
12575
0
      op <<= 11;
12576
0
      Value |= op;
12577
0
      break;
12578
0
    }
12579
0
    case AArch64::FCADDv2f32:
12580
0
    case AArch64::FCADDv2f64:
12581
0
    case AArch64::FCADDv4f16:
12582
0
    case AArch64::FCADDv4f32:
12583
0
    case AArch64::FCADDv8f16: {
12584
      // op: Rd
12585
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12586
0
      op &= UINT64_C(31);
12587
0
      Value |= op;
12588
      // op: Rn
12589
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12590
0
      op &= UINT64_C(31);
12591
0
      op <<= 5;
12592
0
      Value |= op;
12593
      // op: Rm
12594
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12595
0
      op &= UINT64_C(31);
12596
0
      op <<= 16;
12597
0
      Value |= op;
12598
      // op: rot
12599
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12600
0
      op &= UINT64_C(1);
12601
0
      op <<= 12;
12602
0
      Value |= op;
12603
0
      break;
12604
0
    }
12605
0
    case AArch64::ADDSWrs:
12606
0
    case AArch64::ADDSXrs:
12607
0
    case AArch64::ADDWrs:
12608
0
    case AArch64::ADDXrs:
12609
0
    case AArch64::ANDSWrs:
12610
0
    case AArch64::ANDSXrs:
12611
0
    case AArch64::ANDWrs:
12612
0
    case AArch64::ANDXrs:
12613
0
    case AArch64::BICSWrs:
12614
0
    case AArch64::BICSXrs:
12615
0
    case AArch64::BICWrs:
12616
0
    case AArch64::BICXrs:
12617
0
    case AArch64::EONWrs:
12618
0
    case AArch64::EONXrs:
12619
0
    case AArch64::EORWrs:
12620
0
    case AArch64::EORXrs:
12621
0
    case AArch64::ORNWrs:
12622
0
    case AArch64::ORNXrs:
12623
0
    case AArch64::ORRWrs:
12624
0
    case AArch64::ORRXrs:
12625
0
    case AArch64::SUBSWrs:
12626
0
    case AArch64::SUBSXrs:
12627
0
    case AArch64::SUBWrs:
12628
0
    case AArch64::SUBXrs: {
12629
      // op: Rd
12630
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12631
0
      op &= UINT64_C(31);
12632
0
      Value |= op;
12633
      // op: Rn
12634
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12635
0
      op &= UINT64_C(31);
12636
0
      op <<= 5;
12637
0
      Value |= op;
12638
      // op: Rm
12639
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12640
0
      op &= UINT64_C(31);
12641
0
      op <<= 16;
12642
0
      Value |= op;
12643
      // op: shift
12644
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12645
0
      Value |= (op & UINT64_C(192)) << 16;
12646
0
      Value |= (op & UINT64_C(63)) << 10;
12647
0
      break;
12648
0
    }
12649
0
    case AArch64::ADDPT_shift:
12650
0
    case AArch64::SUBPT_shift: {
12651
      // op: Rd
12652
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12653
0
      op &= UINT64_C(31);
12654
0
      Value |= op;
12655
      // op: Rn
12656
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12657
0
      op &= UINT64_C(31);
12658
0
      op <<= 5;
12659
0
      Value |= op;
12660
      // op: Rm
12661
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12662
0
      op &= UINT64_C(31);
12663
0
      op <<= 16;
12664
0
      Value |= op;
12665
      // op: shift_imm
12666
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12667
0
      op &= UINT64_C(7);
12668
0
      op <<= 10;
12669
0
      Value |= op;
12670
0
      break;
12671
0
    }
12672
0
    case AArch64::SMULHrr:
12673
0
    case AArch64::UMULHrr: {
12674
      // op: Rd
12675
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12676
0
      op &= UINT64_C(31);
12677
0
      Value |= op;
12678
      // op: Rn
12679
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12680
0
      op &= UINT64_C(31);
12681
0
      op <<= 5;
12682
0
      Value |= op;
12683
      // op: Rm
12684
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12685
0
      op &= UINT64_C(31);
12686
0
      op <<= 16;
12687
0
      Value |= op;
12688
0
      Value = fixMulHigh(MI, Value, STI);
12689
0
      break;
12690
0
    }
12691
0
    case AArch64::DUPv2i64lane:
12692
0
    case AArch64::UMOVvi64: {
12693
      // op: Rd
12694
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12695
0
      op &= UINT64_C(31);
12696
0
      Value |= op;
12697
      // op: Rn
12698
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12699
0
      op &= UINT64_C(31);
12700
0
      op <<= 5;
12701
0
      Value |= op;
12702
      // op: idx
12703
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12704
0
      op &= UINT64_C(1);
12705
0
      op <<= 20;
12706
0
      Value |= op;
12707
0
      break;
12708
0
    }
12709
0
    case AArch64::DUPv8i8lane:
12710
0
    case AArch64::DUPv16i8lane:
12711
0
    case AArch64::SMOVvi8to32:
12712
0
    case AArch64::SMOVvi8to64:
12713
0
    case AArch64::UMOVvi8: {
12714
      // op: Rd
12715
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12716
0
      op &= UINT64_C(31);
12717
0
      Value |= op;
12718
      // op: Rn
12719
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12720
0
      op &= UINT64_C(31);
12721
0
      op <<= 5;
12722
0
      Value |= op;
12723
      // op: idx
12724
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12725
0
      op &= UINT64_C(15);
12726
0
      op <<= 17;
12727
0
      Value |= op;
12728
0
      break;
12729
0
    }
12730
0
    case AArch64::DUPv2i32lane:
12731
0
    case AArch64::DUPv4i32lane:
12732
0
    case AArch64::SMOVvi32to64:
12733
0
    case AArch64::UMOVvi32: {
12734
      // op: Rd
12735
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12736
0
      op &= UINT64_C(31);
12737
0
      Value |= op;
12738
      // op: Rn
12739
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12740
0
      op &= UINT64_C(31);
12741
0
      op <<= 5;
12742
0
      Value |= op;
12743
      // op: idx
12744
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12745
0
      op &= UINT64_C(3);
12746
0
      op <<= 19;
12747
0
      Value |= op;
12748
0
      break;
12749
0
    }
12750
0
    case AArch64::DUPv4i16lane:
12751
0
    case AArch64::DUPv8i16lane:
12752
0
    case AArch64::SMOVvi16to32:
12753
0
    case AArch64::SMOVvi16to64:
12754
0
    case AArch64::UMOVvi16: {
12755
      // op: Rd
12756
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12757
0
      op &= UINT64_C(31);
12758
0
      Value |= op;
12759
      // op: Rn
12760
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12761
0
      op &= UINT64_C(31);
12762
0
      op <<= 5;
12763
0
      Value |= op;
12764
      // op: idx
12765
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12766
0
      op &= UINT64_C(7);
12767
0
      op <<= 18;
12768
0
      Value |= op;
12769
0
      break;
12770
0
    }
12771
0
    case AArch64::ADDSWri:
12772
0
    case AArch64::ADDSXri:
12773
0
    case AArch64::ADDWri:
12774
0
    case AArch64::ADDXri:
12775
0
    case AArch64::SUBSWri:
12776
0
    case AArch64::SUBSXri:
12777
0
    case AArch64::SUBWri:
12778
0
    case AArch64::SUBXri: {
12779
      // op: Rd
12780
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12781
0
      op &= UINT64_C(31);
12782
0
      Value |= op;
12783
      // op: Rn
12784
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12785
0
      op &= UINT64_C(31);
12786
0
      op <<= 5;
12787
0
      Value |= op;
12788
      // op: imm
12789
0
      op = getAddSubImmOpValue(MI, 2, Fixups, STI);
12790
0
      op &= UINT64_C(16383);
12791
0
      op <<= 10;
12792
0
      Value |= op;
12793
0
      break;
12794
0
    }
12795
0
    case AArch64::SMAXWri:
12796
0
    case AArch64::SMAXXri:
12797
0
    case AArch64::SMINWri:
12798
0
    case AArch64::SMINXri:
12799
0
    case AArch64::UMAXWri:
12800
0
    case AArch64::UMAXXri:
12801
0
    case AArch64::UMINWri:
12802
0
    case AArch64::UMINXri: {
12803
      // op: Rd
12804
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12805
0
      op &= UINT64_C(31);
12806
0
      Value |= op;
12807
      // op: Rn
12808
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12809
0
      op &= UINT64_C(31);
12810
0
      op <<= 5;
12811
0
      Value |= op;
12812
      // op: imm
12813
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12814
0
      op &= UINT64_C(255);
12815
0
      op <<= 10;
12816
0
      Value |= op;
12817
0
      break;
12818
0
    }
12819
0
    case AArch64::ANDSWri:
12820
0
    case AArch64::ANDWri:
12821
0
    case AArch64::EORWri:
12822
0
    case AArch64::ORRWri: {
12823
      // op: Rd
12824
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12825
0
      op &= UINT64_C(31);
12826
0
      Value |= op;
12827
      // op: Rn
12828
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12829
0
      op &= UINT64_C(31);
12830
0
      op <<= 5;
12831
0
      Value |= op;
12832
      // op: imm
12833
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12834
0
      op &= UINT64_C(4095);
12835
0
      op <<= 10;
12836
0
      Value |= op;
12837
0
      break;
12838
0
    }
12839
0
    case AArch64::ANDSXri:
12840
0
    case AArch64::ANDXri:
12841
0
    case AArch64::EORXri:
12842
0
    case AArch64::ORRXri: {
12843
      // op: Rd
12844
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12845
0
      op &= UINT64_C(31);
12846
0
      Value |= op;
12847
      // op: Rn
12848
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12849
0
      op &= UINT64_C(31);
12850
0
      op <<= 5;
12851
0
      Value |= op;
12852
      // op: imm
12853
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12854
0
      op &= UINT64_C(8191);
12855
0
      op <<= 10;
12856
0
      Value |= op;
12857
0
      break;
12858
0
    }
12859
0
    case AArch64::SHLv4i16_shift:
12860
0
    case AArch64::SHLv8i16_shift:
12861
0
    case AArch64::SQSHLUh:
12862
0
    case AArch64::SQSHLUv4i16_shift:
12863
0
    case AArch64::SQSHLUv8i16_shift:
12864
0
    case AArch64::SQSHLh:
12865
0
    case AArch64::SQSHLv4i16_shift:
12866
0
    case AArch64::SQSHLv8i16_shift:
12867
0
    case AArch64::SSHLLv4i16_shift:
12868
0
    case AArch64::SSHLLv8i16_shift:
12869
0
    case AArch64::UQSHLh:
12870
0
    case AArch64::UQSHLv4i16_shift:
12871
0
    case AArch64::UQSHLv8i16_shift:
12872
0
    case AArch64::USHLLv4i16_shift:
12873
0
    case AArch64::USHLLv8i16_shift: {
12874
      // op: Rd
12875
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12876
0
      op &= UINT64_C(31);
12877
0
      Value |= op;
12878
      // op: Rn
12879
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12880
0
      op &= UINT64_C(31);
12881
0
      op <<= 5;
12882
0
      Value |= op;
12883
      // op: imm
12884
0
      op = getVecShiftL16OpValue(MI, 2, Fixups, STI);
12885
0
      op &= UINT64_C(15);
12886
0
      op <<= 16;
12887
0
      Value |= op;
12888
0
      break;
12889
0
    }
12890
0
    case AArch64::SHLv2i32_shift:
12891
0
    case AArch64::SHLv4i32_shift:
12892
0
    case AArch64::SQSHLUs:
12893
0
    case AArch64::SQSHLUv2i32_shift:
12894
0
    case AArch64::SQSHLUv4i32_shift:
12895
0
    case AArch64::SQSHLs:
12896
0
    case AArch64::SQSHLv2i32_shift:
12897
0
    case AArch64::SQSHLv4i32_shift:
12898
0
    case AArch64::SSHLLv2i32_shift:
12899
0
    case AArch64::SSHLLv4i32_shift:
12900
0
    case AArch64::UQSHLs:
12901
0
    case AArch64::UQSHLv2i32_shift:
12902
0
    case AArch64::UQSHLv4i32_shift:
12903
0
    case AArch64::USHLLv2i32_shift:
12904
0
    case AArch64::USHLLv4i32_shift: {
12905
      // op: Rd
12906
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12907
0
      op &= UINT64_C(31);
12908
0
      Value |= op;
12909
      // op: Rn
12910
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12911
0
      op &= UINT64_C(31);
12912
0
      op <<= 5;
12913
0
      Value |= op;
12914
      // op: imm
12915
0
      op = getVecShiftL32OpValue(MI, 2, Fixups, STI);
12916
0
      op &= UINT64_C(31);
12917
0
      op <<= 16;
12918
0
      Value |= op;
12919
0
      break;
12920
0
    }
12921
0
    case AArch64::SHLd:
12922
0
    case AArch64::SHLv2i64_shift:
12923
0
    case AArch64::SQSHLUd:
12924
0
    case AArch64::SQSHLUv2i64_shift:
12925
0
    case AArch64::SQSHLd:
12926
0
    case AArch64::SQSHLv2i64_shift:
12927
0
    case AArch64::UQSHLd:
12928
0
    case AArch64::UQSHLv2i64_shift: {
12929
      // op: Rd
12930
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12931
0
      op &= UINT64_C(31);
12932
0
      Value |= op;
12933
      // op: Rn
12934
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12935
0
      op &= UINT64_C(31);
12936
0
      op <<= 5;
12937
0
      Value |= op;
12938
      // op: imm
12939
0
      op = getVecShiftL64OpValue(MI, 2, Fixups, STI);
12940
0
      op &= UINT64_C(63);
12941
0
      op <<= 16;
12942
0
      Value |= op;
12943
0
      break;
12944
0
    }
12945
0
    case AArch64::SHLv8i8_shift:
12946
0
    case AArch64::SHLv16i8_shift:
12947
0
    case AArch64::SQSHLUb:
12948
0
    case AArch64::SQSHLUv8i8_shift:
12949
0
    case AArch64::SQSHLUv16i8_shift:
12950
0
    case AArch64::SQSHLb:
12951
0
    case AArch64::SQSHLv8i8_shift:
12952
0
    case AArch64::SQSHLv16i8_shift:
12953
0
    case AArch64::SSHLLv8i8_shift:
12954
0
    case AArch64::SSHLLv16i8_shift:
12955
0
    case AArch64::UQSHLb:
12956
0
    case AArch64::UQSHLv8i8_shift:
12957
0
    case AArch64::UQSHLv16i8_shift:
12958
0
    case AArch64::USHLLv8i8_shift:
12959
0
    case AArch64::USHLLv16i8_shift: {
12960
      // op: Rd
12961
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12962
0
      op &= UINT64_C(31);
12963
0
      Value |= op;
12964
      // op: Rn
12965
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12966
0
      op &= UINT64_C(31);
12967
0
      op <<= 5;
12968
0
      Value |= op;
12969
      // op: imm
12970
0
      op = getVecShiftL8OpValue(MI, 2, Fixups, STI);
12971
0
      op &= UINT64_C(7);
12972
0
      op <<= 16;
12973
0
      Value |= op;
12974
0
      break;
12975
0
    }
12976
0
    case AArch64::FCVTZSh:
12977
0
    case AArch64::FCVTZSv4i16_shift:
12978
0
    case AArch64::FCVTZSv8i16_shift:
12979
0
    case AArch64::FCVTZUh:
12980
0
    case AArch64::FCVTZUv4i16_shift:
12981
0
    case AArch64::FCVTZUv8i16_shift:
12982
0
    case AArch64::SCVTFh:
12983
0
    case AArch64::SCVTFv4i16_shift:
12984
0
    case AArch64::SCVTFv8i16_shift:
12985
0
    case AArch64::SQRSHRNh:
12986
0
    case AArch64::SQRSHRUNh:
12987
0
    case AArch64::SQSHRNh:
12988
0
    case AArch64::SQSHRUNh:
12989
0
    case AArch64::SRSHRv4i16_shift:
12990
0
    case AArch64::SRSHRv8i16_shift:
12991
0
    case AArch64::SSHRv4i16_shift:
12992
0
    case AArch64::SSHRv8i16_shift:
12993
0
    case AArch64::UCVTFh:
12994
0
    case AArch64::UCVTFv4i16_shift:
12995
0
    case AArch64::UCVTFv8i16_shift:
12996
0
    case AArch64::UQRSHRNh:
12997
0
    case AArch64::UQSHRNh:
12998
0
    case AArch64::URSHRv4i16_shift:
12999
0
    case AArch64::URSHRv8i16_shift:
13000
0
    case AArch64::USHRv4i16_shift:
13001
0
    case AArch64::USHRv8i16_shift: {
13002
      // op: Rd
13003
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13004
0
      op &= UINT64_C(31);
13005
0
      Value |= op;
13006
      // op: Rn
13007
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13008
0
      op &= UINT64_C(31);
13009
0
      op <<= 5;
13010
0
      Value |= op;
13011
      // op: imm
13012
0
      op = getVecShiftR16OpValue(MI, 2, Fixups, STI);
13013
0
      op &= UINT64_C(15);
13014
0
      op <<= 16;
13015
0
      Value |= op;
13016
0
      break;
13017
0
    }
13018
0
    case AArch64::RSHRNv8i8_shift:
13019
0
    case AArch64::SHRNv8i8_shift:
13020
0
    case AArch64::SQRSHRNv8i8_shift:
13021
0
    case AArch64::SQRSHRUNv8i8_shift:
13022
0
    case AArch64::SQSHRNv8i8_shift:
13023
0
    case AArch64::SQSHRUNv8i8_shift:
13024
0
    case AArch64::UQRSHRNv8i8_shift:
13025
0
    case AArch64::UQSHRNv8i8_shift: {
13026
      // op: Rd
13027
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13028
0
      op &= UINT64_C(31);
13029
0
      Value |= op;
13030
      // op: Rn
13031
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13032
0
      op &= UINT64_C(31);
13033
0
      op <<= 5;
13034
0
      Value |= op;
13035
      // op: imm
13036
0
      op = getVecShiftR16OpValue(MI, 2, Fixups, STI);
13037
0
      op &= UINT64_C(7);
13038
0
      op <<= 16;
13039
0
      Value |= op;
13040
0
      break;
13041
0
    }
13042
0
    case AArch64::RSHRNv4i16_shift:
13043
0
    case AArch64::SHRNv4i16_shift:
13044
0
    case AArch64::SQRSHRNv4i16_shift:
13045
0
    case AArch64::SQRSHRUNv4i16_shift:
13046
0
    case AArch64::SQSHRNv4i16_shift:
13047
0
    case AArch64::SQSHRUNv4i16_shift:
13048
0
    case AArch64::UQRSHRNv4i16_shift:
13049
0
    case AArch64::UQSHRNv4i16_shift: {
13050
      // op: Rd
13051
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13052
0
      op &= UINT64_C(31);
13053
0
      Value |= op;
13054
      // op: Rn
13055
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13056
0
      op &= UINT64_C(31);
13057
0
      op <<= 5;
13058
0
      Value |= op;
13059
      // op: imm
13060
0
      op = getVecShiftR32OpValue(MI, 2, Fixups, STI);
13061
0
      op &= UINT64_C(15);
13062
0
      op <<= 16;
13063
0
      Value |= op;
13064
0
      break;
13065
0
    }
13066
0
    case AArch64::FCVTZSs:
13067
0
    case AArch64::FCVTZSv2i32_shift:
13068
0
    case AArch64::FCVTZSv4i32_shift:
13069
0
    case AArch64::FCVTZUs:
13070
0
    case AArch64::FCVTZUv2i32_shift:
13071
0
    case AArch64::FCVTZUv4i32_shift:
13072
0
    case AArch64::SCVTFs:
13073
0
    case AArch64::SCVTFv2i32_shift:
13074
0
    case AArch64::SCVTFv4i32_shift:
13075
0
    case AArch64::SQRSHRNs:
13076
0
    case AArch64::SQRSHRUNs:
13077
0
    case AArch64::SQSHRNs:
13078
0
    case AArch64::SQSHRUNs:
13079
0
    case AArch64::SRSHRv2i32_shift:
13080
0
    case AArch64::SRSHRv4i32_shift:
13081
0
    case AArch64::SSHRv2i32_shift:
13082
0
    case AArch64::SSHRv4i32_shift:
13083
0
    case AArch64::UCVTFs:
13084
0
    case AArch64::UCVTFv2i32_shift:
13085
0
    case AArch64::UCVTFv4i32_shift:
13086
0
    case AArch64::UQRSHRNs:
13087
0
    case AArch64::UQSHRNs:
13088
0
    case AArch64::URSHRv2i32_shift:
13089
0
    case AArch64::URSHRv4i32_shift:
13090
0
    case AArch64::USHRv2i32_shift:
13091
0
    case AArch64::USHRv4i32_shift: {
13092
      // op: Rd
13093
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13094
0
      op &= UINT64_C(31);
13095
0
      Value |= op;
13096
      // op: Rn
13097
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13098
0
      op &= UINT64_C(31);
13099
0
      op <<= 5;
13100
0
      Value |= op;
13101
      // op: imm
13102
0
      op = getVecShiftR32OpValue(MI, 2, Fixups, STI);
13103
0
      op &= UINT64_C(31);
13104
0
      op <<= 16;
13105
0
      Value |= op;
13106
0
      break;
13107
0
    }
13108
0
    case AArch64::RSHRNv2i32_shift:
13109
0
    case AArch64::SHRNv2i32_shift:
13110
0
    case AArch64::SQRSHRNv2i32_shift:
13111
0
    case AArch64::SQRSHRUNv2i32_shift:
13112
0
    case AArch64::SQSHRNv2i32_shift:
13113
0
    case AArch64::SQSHRUNv2i32_shift:
13114
0
    case AArch64::UQRSHRNv2i32_shift:
13115
0
    case AArch64::UQSHRNv2i32_shift: {
13116
      // op: Rd
13117
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13118
0
      op &= UINT64_C(31);
13119
0
      Value |= op;
13120
      // op: Rn
13121
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13122
0
      op &= UINT64_C(31);
13123
0
      op <<= 5;
13124
0
      Value |= op;
13125
      // op: imm
13126
0
      op = getVecShiftR64OpValue(MI, 2, Fixups, STI);
13127
0
      op &= UINT64_C(31);
13128
0
      op <<= 16;
13129
0
      Value |= op;
13130
0
      break;
13131
0
    }
13132
0
    case AArch64::FCVTZSd:
13133
0
    case AArch64::FCVTZSv2i64_shift:
13134
0
    case AArch64::FCVTZUd:
13135
0
    case AArch64::FCVTZUv2i64_shift:
13136
0
    case AArch64::SCVTFd:
13137
0
    case AArch64::SCVTFv2i64_shift:
13138
0
    case AArch64::SRSHRd:
13139
0
    case AArch64::SRSHRv2i64_shift:
13140
0
    case AArch64::SSHRd:
13141
0
    case AArch64::SSHRv2i64_shift:
13142
0
    case AArch64::UCVTFd:
13143
0
    case AArch64::UCVTFv2i64_shift:
13144
0
    case AArch64::URSHRd:
13145
0
    case AArch64::URSHRv2i64_shift:
13146
0
    case AArch64::USHRd:
13147
0
    case AArch64::USHRv2i64_shift: {
13148
      // op: Rd
13149
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13150
0
      op &= UINT64_C(31);
13151
0
      Value |= op;
13152
      // op: Rn
13153
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13154
0
      op &= UINT64_C(31);
13155
0
      op <<= 5;
13156
0
      Value |= op;
13157
      // op: imm
13158
0
      op = getVecShiftR64OpValue(MI, 2, Fixups, STI);
13159
0
      op &= UINT64_C(63);
13160
0
      op <<= 16;
13161
0
      Value |= op;
13162
0
      break;
13163
0
    }
13164
0
    case AArch64::SQRSHRNb:
13165
0
    case AArch64::SQRSHRUNb:
13166
0
    case AArch64::SQSHRNb:
13167
0
    case AArch64::SQSHRUNb:
13168
0
    case AArch64::SRSHRv8i8_shift:
13169
0
    case AArch64::SRSHRv16i8_shift:
13170
0
    case AArch64::SSHRv8i8_shift:
13171
0
    case AArch64::SSHRv16i8_shift:
13172
0
    case AArch64::UQRSHRNb:
13173
0
    case AArch64::UQSHRNb:
13174
0
    case AArch64::URSHRv8i8_shift:
13175
0
    case AArch64::URSHRv16i8_shift:
13176
0
    case AArch64::USHRv8i8_shift:
13177
0
    case AArch64::USHRv16i8_shift: {
13178
      // op: Rd
13179
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13180
0
      op &= UINT64_C(31);
13181
0
      Value |= op;
13182
      // op: Rn
13183
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13184
0
      op &= UINT64_C(31);
13185
0
      op <<= 5;
13186
0
      Value |= op;
13187
      // op: imm
13188
0
      op = getVecShiftR8OpValue(MI, 2, Fixups, STI);
13189
0
      op &= UINT64_C(7);
13190
0
      op <<= 16;
13191
0
      Value |= op;
13192
0
      break;
13193
0
    }
13194
0
    case AArch64::ADDG:
13195
0
    case AArch64::SUBG: {
13196
      // op: Rd
13197
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13198
0
      op &= UINT64_C(31);
13199
0
      Value |= op;
13200
      // op: Rn
13201
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13202
0
      op &= UINT64_C(31);
13203
0
      op <<= 5;
13204
0
      Value |= op;
13205
      // op: imm6
13206
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13207
0
      op &= UINT64_C(63);
13208
0
      op <<= 16;
13209
0
      Value |= op;
13210
      // op: imm4
13211
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
13212
0
      op &= UINT64_C(15);
13213
0
      op <<= 10;
13214
0
      Value |= op;
13215
0
      break;
13216
0
    }
13217
0
    case AArch64::SBFMWri:
13218
0
    case AArch64::UBFMWri: {
13219
      // op: Rd
13220
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13221
0
      op &= UINT64_C(31);
13222
0
      Value |= op;
13223
      // op: Rn
13224
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13225
0
      op &= UINT64_C(31);
13226
0
      op <<= 5;
13227
0
      Value |= op;
13228
      // op: immr
13229
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13230
0
      op &= UINT64_C(31);
13231
0
      op <<= 16;
13232
0
      Value |= op;
13233
      // op: imms
13234
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
13235
0
      op &= UINT64_C(31);
13236
0
      op <<= 10;
13237
0
      Value |= op;
13238
0
      break;
13239
0
    }
13240
0
    case AArch64::SBFMXri:
13241
0
    case AArch64::UBFMXri: {
13242
      // op: Rd
13243
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13244
0
      op &= UINT64_C(31);
13245
0
      Value |= op;
13246
      // op: Rn
13247
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13248
0
      op &= UINT64_C(31);
13249
0
      op <<= 5;
13250
0
      Value |= op;
13251
      // op: immr
13252
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13253
0
      op &= UINT64_C(63);
13254
0
      op <<= 16;
13255
0
      Value |= op;
13256
      // op: imms
13257
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
13258
0
      op &= UINT64_C(63);
13259
0
      op <<= 10;
13260
0
      Value |= op;
13261
0
      break;
13262
0
    }
13263
0
    case AArch64::FCVTZSSWDri:
13264
0
    case AArch64::FCVTZSSWHri:
13265
0
    case AArch64::FCVTZSSWSri:
13266
0
    case AArch64::FCVTZUSWDri:
13267
0
    case AArch64::FCVTZUSWHri:
13268
0
    case AArch64::FCVTZUSWSri:
13269
0
    case AArch64::SCVTFSWDri:
13270
0
    case AArch64::SCVTFSWHri:
13271
0
    case AArch64::SCVTFSWSri:
13272
0
    case AArch64::UCVTFSWDri:
13273
0
    case AArch64::UCVTFSWHri:
13274
0
    case AArch64::UCVTFSWSri: {
13275
      // op: Rd
13276
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13277
0
      op &= UINT64_C(31);
13278
0
      Value |= op;
13279
      // op: Rn
13280
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13281
0
      op &= UINT64_C(31);
13282
0
      op <<= 5;
13283
0
      Value |= op;
13284
      // op: scale
13285
0
      op = getFixedPointScaleOpValue(MI, 2, Fixups, STI);
13286
0
      op &= UINT64_C(31);
13287
0
      op <<= 10;
13288
0
      Value |= op;
13289
0
      break;
13290
0
    }
13291
0
    case AArch64::FCVTZSSXDri:
13292
0
    case AArch64::FCVTZSSXHri:
13293
0
    case AArch64::FCVTZSSXSri:
13294
0
    case AArch64::FCVTZUSXDri:
13295
0
    case AArch64::FCVTZUSXHri:
13296
0
    case AArch64::FCVTZUSXSri:
13297
0
    case AArch64::SCVTFSXDri:
13298
0
    case AArch64::SCVTFSXHri:
13299
0
    case AArch64::SCVTFSXSri:
13300
0
    case AArch64::UCVTFSXDri:
13301
0
    case AArch64::UCVTFSXHri:
13302
0
    case AArch64::UCVTFSXSri: {
13303
      // op: Rd
13304
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13305
0
      op &= UINT64_C(31);
13306
0
      Value |= op;
13307
      // op: Rn
13308
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13309
0
      op &= UINT64_C(31);
13310
0
      op <<= 5;
13311
0
      Value |= op;
13312
      // op: scale
13313
0
      op = getFixedPointScaleOpValue(MI, 2, Fixups, STI);
13314
0
      op &= UINT64_C(63);
13315
0
      op <<= 10;
13316
0
      Value |= op;
13317
0
      break;
13318
0
    }
13319
0
    case AArch64::BFMWri: {
13320
      // op: Rd
13321
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13322
0
      op &= UINT64_C(31);
13323
0
      Value |= op;
13324
      // op: Rn
13325
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13326
0
      op &= UINT64_C(31);
13327
0
      op <<= 5;
13328
0
      Value |= op;
13329
      // op: immr
13330
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
13331
0
      op &= UINT64_C(31);
13332
0
      op <<= 16;
13333
0
      Value |= op;
13334
      // op: imms
13335
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
13336
0
      op &= UINT64_C(31);
13337
0
      op <<= 10;
13338
0
      Value |= op;
13339
0
      break;
13340
0
    }
13341
0
    case AArch64::BFMXri: {
13342
      // op: Rd
13343
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13344
0
      op &= UINT64_C(31);
13345
0
      Value |= op;
13346
      // op: Rn
13347
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13348
0
      op &= UINT64_C(31);
13349
0
      op <<= 5;
13350
0
      Value |= op;
13351
      // op: immr
13352
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
13353
0
      op &= UINT64_C(63);
13354
0
      op <<= 16;
13355
0
      Value |= op;
13356
      // op: imms
13357
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
13358
0
      op &= UINT64_C(63);
13359
0
      op <<= 10;
13360
0
      Value |= op;
13361
0
      break;
13362
0
    }
13363
0
    case AArch64::FMOVDi:
13364
0
    case AArch64::FMOVHi:
13365
0
    case AArch64::FMOVSi: {
13366
      // op: Rd
13367
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13368
0
      op &= UINT64_C(31);
13369
0
      Value |= op;
13370
      // op: imm
13371
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13372
0
      op &= UINT64_C(255);
13373
0
      op <<= 13;
13374
0
      Value |= op;
13375
0
      break;
13376
0
    }
13377
0
    case AArch64::MOVNWi:
13378
0
    case AArch64::MOVNXi: {
13379
      // op: Rd
13380
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13381
0
      op &= UINT64_C(31);
13382
0
      Value |= op;
13383
      // op: imm
13384
0
      op = getMoveWideImmOpValue(MI, 1, Fixups, STI);
13385
0
      op &= UINT64_C(65535);
13386
0
      op <<= 5;
13387
0
      Value |= op;
13388
      // op: shift
13389
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13390
0
      op &= UINT64_C(48);
13391
0
      op <<= 17;
13392
0
      Value |= op;
13393
0
      break;
13394
0
    }
13395
0
    case AArch64::MOVZWi:
13396
0
    case AArch64::MOVZXi: {
13397
      // op: Rd
13398
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13399
0
      op &= UINT64_C(31);
13400
0
      Value |= op;
13401
      // op: imm
13402
0
      op = getMoveWideImmOpValue(MI, 1, Fixups, STI);
13403
0
      op &= UINT64_C(65535);
13404
0
      op <<= 5;
13405
0
      Value |= op;
13406
      // op: shift
13407
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13408
0
      op &= UINT64_C(48);
13409
0
      op <<= 17;
13410
0
      Value |= op;
13411
0
      Value = fixMOVZ(MI, Value, STI);
13412
0
      break;
13413
0
    }
13414
0
    case AArch64::MOVKWi:
13415
0
    case AArch64::MOVKXi: {
13416
      // op: Rd
13417
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13418
0
      op &= UINT64_C(31);
13419
0
      Value |= op;
13420
      // op: imm
13421
0
      op = getMoveWideImmOpValue(MI, 2, Fixups, STI);
13422
0
      op &= UINT64_C(65535);
13423
0
      op <<= 5;
13424
0
      Value |= op;
13425
      // op: shift
13426
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
13427
0
      op &= UINT64_C(48);
13428
0
      op <<= 17;
13429
0
      Value |= op;
13430
0
      break;
13431
0
    }
13432
0
    case AArch64::CNTB_XPiI:
13433
0
    case AArch64::CNTD_XPiI:
13434
0
    case AArch64::CNTH_XPiI:
13435
0
    case AArch64::CNTW_XPiI: {
13436
      // op: Rd
13437
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13438
0
      op &= UINT64_C(31);
13439
0
      Value |= op;
13440
      // op: imm4
13441
0
      op = getSVEIncDecImm(MI, 2, Fixups, STI);
13442
0
      op &= UINT64_C(15);
13443
0
      op <<= 16;
13444
0
      Value |= op;
13445
      // op: pattern
13446
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13447
0
      op &= UINT64_C(31);
13448
0
      op <<= 5;
13449
0
      Value |= op;
13450
0
      break;
13451
0
    }
13452
0
    case AArch64::RDSVLI_XI:
13453
0
    case AArch64::RDVLI_XI: {
13454
      // op: Rd
13455
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13456
0
      op &= UINT64_C(31);
13457
0
      Value |= op;
13458
      // op: imm6
13459
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13460
0
      op &= UINT64_C(63);
13461
0
      op <<= 5;
13462
0
      Value |= op;
13463
0
      break;
13464
0
    }
13465
0
    case AArch64::FMOVv2f32_ns:
13466
0
    case AArch64::FMOVv2f64_ns:
13467
0
    case AArch64::FMOVv4f16_ns:
13468
0
    case AArch64::FMOVv4f32_ns:
13469
0
    case AArch64::FMOVv8f16_ns:
13470
0
    case AArch64::MOVID:
13471
0
    case AArch64::MOVIv2d_ns:
13472
0
    case AArch64::MOVIv8b_ns:
13473
0
    case AArch64::MOVIv16b_ns: {
13474
      // op: Rd
13475
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13476
0
      op &= UINT64_C(31);
13477
0
      Value |= op;
13478
      // op: imm8
13479
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13480
0
      Value |= (op & UINT64_C(224)) << 11;
13481
0
      Value |= (op & UINT64_C(31)) << 5;
13482
0
      break;
13483
0
    }
13484
0
    case AArch64::MOVIv2s_msl:
13485
0
    case AArch64::MOVIv4s_msl:
13486
0
    case AArch64::MVNIv2s_msl:
13487
0
    case AArch64::MVNIv4s_msl: {
13488
      // op: Rd
13489
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13490
0
      op &= UINT64_C(31);
13491
0
      Value |= op;
13492
      // op: imm8
13493
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13494
0
      Value |= (op & UINT64_C(224)) << 11;
13495
0
      Value |= (op & UINT64_C(31)) << 5;
13496
      // op: shift
13497
0
      op = getMoveVecShifterOpValue(MI, 2, Fixups, STI);
13498
0
      op &= UINT64_C(1);
13499
0
      op <<= 12;
13500
0
      Value |= op;
13501
0
      break;
13502
0
    }
13503
0
    case AArch64::MOVIv4i16:
13504
0
    case AArch64::MOVIv8i16:
13505
0
    case AArch64::MVNIv4i16:
13506
0
    case AArch64::MVNIv8i16: {
13507
      // op: Rd
13508
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13509
0
      op &= UINT64_C(31);
13510
0
      Value |= op;
13511
      // op: imm8
13512
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13513
0
      Value |= (op & UINT64_C(224)) << 11;
13514
0
      Value |= (op & UINT64_C(31)) << 5;
13515
      // op: shift
13516
0
      op = getVecShifterOpValue(MI, 2, Fixups, STI);
13517
0
      op &= UINT64_C(1);
13518
0
      op <<= 13;
13519
0
      Value |= op;
13520
0
      break;
13521
0
    }
13522
0
    case AArch64::MOVIv2i32:
13523
0
    case AArch64::MOVIv4i32:
13524
0
    case AArch64::MVNIv2i32:
13525
0
    case AArch64::MVNIv4i32: {
13526
      // op: Rd
13527
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13528
0
      op &= UINT64_C(31);
13529
0
      Value |= op;
13530
      // op: imm8
13531
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13532
0
      Value |= (op & UINT64_C(224)) << 11;
13533
0
      Value |= (op & UINT64_C(31)) << 5;
13534
      // op: shift
13535
0
      op = getVecShifterOpValue(MI, 2, Fixups, STI);
13536
0
      op &= UINT64_C(3);
13537
0
      op <<= 13;
13538
0
      Value |= op;
13539
0
      break;
13540
0
    }
13541
0
    case AArch64::AUTDZA:
13542
0
    case AArch64::AUTDZB:
13543
0
    case AArch64::AUTIZA:
13544
0
    case AArch64::AUTIZB:
13545
0
    case AArch64::PACDZA:
13546
0
    case AArch64::PACDZB:
13547
0
    case AArch64::PACIZA:
13548
0
    case AArch64::PACIZB: {
13549
      // op: Rd
13550
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13551
0
      op &= UINT64_C(31);
13552
0
      Value |= op;
13553
0
      break;
13554
0
    }
13555
0
    case AArch64::AESDrr:
13556
0
    case AArch64::AESErr:
13557
0
    case AArch64::AUTDA:
13558
0
    case AArch64::AUTDB:
13559
0
    case AArch64::AUTIA:
13560
0
    case AArch64::AUTIB:
13561
0
    case AArch64::BFCVTN2:
13562
0
    case AArch64::FCVTNv4i32:
13563
0
    case AArch64::FCVTNv8i16:
13564
0
    case AArch64::FCVTXNv4f32:
13565
0
    case AArch64::PACDA:
13566
0
    case AArch64::PACDB:
13567
0
    case AArch64::PACIA:
13568
0
    case AArch64::PACIB:
13569
0
    case AArch64::SADALPv2i32_v1i64:
13570
0
    case AArch64::SADALPv4i16_v2i32:
13571
0
    case AArch64::SADALPv4i32_v2i64:
13572
0
    case AArch64::SADALPv8i8_v4i16:
13573
0
    case AArch64::SADALPv8i16_v4i32:
13574
0
    case AArch64::SADALPv16i8_v8i16:
13575
0
    case AArch64::SHA1SU1rr:
13576
0
    case AArch64::SHA256SU0rr:
13577
0
    case AArch64::SQXTNv4i32:
13578
0
    case AArch64::SQXTNv8i16:
13579
0
    case AArch64::SQXTNv16i8:
13580
0
    case AArch64::SQXTUNv4i32:
13581
0
    case AArch64::SQXTUNv8i16:
13582
0
    case AArch64::SQXTUNv16i8:
13583
0
    case AArch64::SUQADDv1i8:
13584
0
    case AArch64::SUQADDv1i16:
13585
0
    case AArch64::SUQADDv1i32:
13586
0
    case AArch64::SUQADDv1i64:
13587
0
    case AArch64::SUQADDv2i32:
13588
0
    case AArch64::SUQADDv2i64:
13589
0
    case AArch64::SUQADDv4i16:
13590
0
    case AArch64::SUQADDv4i32:
13591
0
    case AArch64::SUQADDv8i8:
13592
0
    case AArch64::SUQADDv8i16:
13593
0
    case AArch64::SUQADDv16i8:
13594
0
    case AArch64::UADALPv2i32_v1i64:
13595
0
    case AArch64::UADALPv4i16_v2i32:
13596
0
    case AArch64::UADALPv4i32_v2i64:
13597
0
    case AArch64::UADALPv8i8_v4i16:
13598
0
    case AArch64::UADALPv8i16_v4i32:
13599
0
    case AArch64::UADALPv16i8_v8i16:
13600
0
    case AArch64::UQXTNv4i32:
13601
0
    case AArch64::UQXTNv8i16:
13602
0
    case AArch64::UQXTNv16i8:
13603
0
    case AArch64::USQADDv1i8:
13604
0
    case AArch64::USQADDv1i16:
13605
0
    case AArch64::USQADDv1i32:
13606
0
    case AArch64::USQADDv1i64:
13607
0
    case AArch64::USQADDv2i32:
13608
0
    case AArch64::USQADDv2i64:
13609
0
    case AArch64::USQADDv4i16:
13610
0
    case AArch64::USQADDv4i32:
13611
0
    case AArch64::USQADDv8i8:
13612
0
    case AArch64::USQADDv8i16:
13613
0
    case AArch64::USQADDv16i8:
13614
0
    case AArch64::XTNv4i32:
13615
0
    case AArch64::XTNv8i16:
13616
0
    case AArch64::XTNv16i8: {
13617
      // op: Rd
13618
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13619
0
      op &= UINT64_C(31);
13620
0
      Value |= op;
13621
      // op: Rn
13622
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13623
0
      op &= UINT64_C(31);
13624
0
      op <<= 5;
13625
0
      Value |= op;
13626
0
      break;
13627
0
    }
13628
0
    case AArch64::BFMLALBIdx:
13629
0
    case AArch64::BFMLALTIdx:
13630
0
    case AArch64::FDOTlanev4f16:
13631
0
    case AArch64::FDOTlanev8f16:
13632
0
    case AArch64::FMLAL2lanev4f16:
13633
0
    case AArch64::FMLAL2lanev8f16:
13634
0
    case AArch64::FMLALlanev4f16:
13635
0
    case AArch64::FMLALlanev8f16:
13636
0
    case AArch64::FMLAv1i16_indexed:
13637
0
    case AArch64::FMLAv4i16_indexed:
13638
0
    case AArch64::FMLAv8i16_indexed:
13639
0
    case AArch64::FMLSL2lanev4f16:
13640
0
    case AArch64::FMLSL2lanev8f16:
13641
0
    case AArch64::FMLSLlanev4f16:
13642
0
    case AArch64::FMLSLlanev8f16:
13643
0
    case AArch64::FMLSv1i16_indexed:
13644
0
    case AArch64::FMLSv4i16_indexed:
13645
0
    case AArch64::FMLSv8i16_indexed:
13646
0
    case AArch64::MLAv4i16_indexed:
13647
0
    case AArch64::MLAv8i16_indexed:
13648
0
    case AArch64::MLSv4i16_indexed:
13649
0
    case AArch64::MLSv8i16_indexed:
13650
0
    case AArch64::SMLALv4i16_indexed:
13651
0
    case AArch64::SMLALv8i16_indexed:
13652
0
    case AArch64::SMLSLv4i16_indexed:
13653
0
    case AArch64::SMLSLv8i16_indexed:
13654
0
    case AArch64::SQDMLALv1i32_indexed:
13655
0
    case AArch64::SQDMLALv4i16_indexed:
13656
0
    case AArch64::SQDMLALv8i16_indexed:
13657
0
    case AArch64::SQDMLSLv1i32_indexed:
13658
0
    case AArch64::SQDMLSLv4i16_indexed:
13659
0
    case AArch64::SQDMLSLv8i16_indexed:
13660
0
    case AArch64::SQRDMLAHv1i16_indexed:
13661
0
    case AArch64::SQRDMLAHv4i16_indexed:
13662
0
    case AArch64::SQRDMLAHv8i16_indexed:
13663
0
    case AArch64::SQRDMLSHv1i16_indexed:
13664
0
    case AArch64::SQRDMLSHv4i16_indexed:
13665
0
    case AArch64::SQRDMLSHv8i16_indexed:
13666
0
    case AArch64::UMLALv4i16_indexed:
13667
0
    case AArch64::UMLALv8i16_indexed:
13668
0
    case AArch64::UMLSLv4i16_indexed:
13669
0
    case AArch64::UMLSLv8i16_indexed: {
13670
      // op: Rd
13671
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13672
0
      op &= UINT64_C(31);
13673
0
      Value |= op;
13674
      // op: Rn
13675
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13676
0
      op &= UINT64_C(31);
13677
0
      op <<= 5;
13678
0
      Value |= op;
13679
      // op: Rm
13680
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
13681
0
      op &= UINT64_C(15);
13682
0
      op <<= 16;
13683
0
      Value |= op;
13684
      // op: idx
13685
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
13686
0
      Value |= (op & UINT64_C(3)) << 20;
13687
0
      Value |= (op & UINT64_C(4)) << 9;
13688
0
      break;
13689
0
    }
13690
0
    case AArch64::ADDHNv2i64_v4i32:
13691
0
    case AArch64::ADDHNv4i32_v8i16:
13692
0
    case AArch64::ADDHNv8i16_v16i8:
13693
0
    case AArch64::BFDOTv4bf16:
13694
0
    case AArch64::BFDOTv8bf16:
13695
0
    case AArch64::BFMLALB:
13696
0
    case AArch64::BFMLALT:
13697
0
    case AArch64::BFMMLA:
13698
0
    case AArch64::BIFv8i8:
13699
0
    case AArch64::BIFv16i8:
13700
0
    case AArch64::BITv8i8:
13701
0
    case AArch64::BITv16i8:
13702
0
    case AArch64::BSLv8i8:
13703
0
    case AArch64::BSLv16i8:
13704
0
    case AArch64::FCVTN_F32_F82v16f8:
13705
0
    case AArch64::FDOTv2f32:
13706
0
    case AArch64::FDOTv4f16:
13707
0
    case AArch64::FDOTv4f32:
13708
0
    case AArch64::FDOTv8f16:
13709
0
    case AArch64::FMLAL2v4f16:
13710
0
    case AArch64::FMLAL2v8f16:
13711
0
    case AArch64::FMLALBv8f16:
13712
0
    case AArch64::FMLALLBBv4f32:
13713
0
    case AArch64::FMLALLBTv4f32:
13714
0
    case AArch64::FMLALLTBv4f32:
13715
0
    case AArch64::FMLALLTTv4f32:
13716
0
    case AArch64::FMLALTv8f16:
13717
0
    case AArch64::FMLALv4f16:
13718
0
    case AArch64::FMLALv8f16:
13719
0
    case AArch64::FMLAv2f32:
13720
0
    case AArch64::FMLAv2f64:
13721
0
    case AArch64::FMLAv4f16:
13722
0
    case AArch64::FMLAv4f32:
13723
0
    case AArch64::FMLAv8f16:
13724
0
    case AArch64::FMLSL2v4f16:
13725
0
    case AArch64::FMLSL2v8f16:
13726
0
    case AArch64::FMLSLv4f16:
13727
0
    case AArch64::FMLSLv8f16:
13728
0
    case AArch64::FMLSv2f32:
13729
0
    case AArch64::FMLSv2f64:
13730
0
    case AArch64::FMLSv4f16:
13731
0
    case AArch64::FMLSv4f32:
13732
0
    case AArch64::FMLSv8f16:
13733
0
    case AArch64::MLAv2i32:
13734
0
    case AArch64::MLAv4i16:
13735
0
    case AArch64::MLAv4i32:
13736
0
    case AArch64::MLAv8i8:
13737
0
    case AArch64::MLAv8i16:
13738
0
    case AArch64::MLAv16i8:
13739
0
    case AArch64::MLSv2i32:
13740
0
    case AArch64::MLSv4i16:
13741
0
    case AArch64::MLSv4i32:
13742
0
    case AArch64::MLSv8i8:
13743
0
    case AArch64::MLSv8i16:
13744
0
    case AArch64::MLSv16i8:
13745
0
    case AArch64::RADDHNv2i64_v4i32:
13746
0
    case AArch64::RADDHNv4i32_v8i16:
13747
0
    case AArch64::RADDHNv8i16_v16i8:
13748
0
    case AArch64::RSUBHNv2i64_v4i32:
13749
0
    case AArch64::RSUBHNv4i32_v8i16:
13750
0
    case AArch64::RSUBHNv8i16_v16i8:
13751
0
    case AArch64::SABALv2i32_v2i64:
13752
0
    case AArch64::SABALv4i16_v4i32:
13753
0
    case AArch64::SABALv4i32_v2i64:
13754
0
    case AArch64::SABALv8i8_v8i16:
13755
0
    case AArch64::SABALv8i16_v4i32:
13756
0
    case AArch64::SABALv16i8_v8i16:
13757
0
    case AArch64::SABAv2i32:
13758
0
    case AArch64::SABAv4i16:
13759
0
    case AArch64::SABAv4i32:
13760
0
    case AArch64::SABAv8i8:
13761
0
    case AArch64::SABAv8i16:
13762
0
    case AArch64::SABAv16i8:
13763
0
    case AArch64::SDOTv8i8:
13764
0
    case AArch64::SDOTv16i8:
13765
0
    case AArch64::SHA1Crrr:
13766
0
    case AArch64::SHA1Mrrr:
13767
0
    case AArch64::SHA1Prrr:
13768
0
    case AArch64::SHA1SU0rrr:
13769
0
    case AArch64::SHA256H2rrr:
13770
0
    case AArch64::SHA256Hrrr:
13771
0
    case AArch64::SHA256SU1rrr:
13772
0
    case AArch64::SMLALv2i32_v2i64:
13773
0
    case AArch64::SMLALv4i16_v4i32:
13774
0
    case AArch64::SMLALv4i32_v2i64:
13775
0
    case AArch64::SMLALv8i8_v8i16:
13776
0
    case AArch64::SMLALv8i16_v4i32:
13777
0
    case AArch64::SMLALv16i8_v8i16:
13778
0
    case AArch64::SMLSLv2i32_v2i64:
13779
0
    case AArch64::SMLSLv4i16_v4i32:
13780
0
    case AArch64::SMLSLv4i32_v2i64:
13781
0
    case AArch64::SMLSLv8i8_v8i16:
13782
0
    case AArch64::SMLSLv8i16_v4i32:
13783
0
    case AArch64::SMLSLv16i8_v8i16:
13784
0
    case AArch64::SMMLA:
13785
0
    case AArch64::SQDMLALi16:
13786
0
    case AArch64::SQDMLALi32:
13787
0
    case AArch64::SQDMLALv2i32_v2i64:
13788
0
    case AArch64::SQDMLALv4i16_v4i32:
13789
0
    case AArch64::SQDMLALv4i32_v2i64:
13790
0
    case AArch64::SQDMLALv8i16_v4i32:
13791
0
    case AArch64::SQDMLSLi16:
13792
0
    case AArch64::SQDMLSLi32:
13793
0
    case AArch64::SQDMLSLv2i32_v2i64:
13794
0
    case AArch64::SQDMLSLv4i16_v4i32:
13795
0
    case AArch64::SQDMLSLv4i32_v2i64:
13796
0
    case AArch64::SQDMLSLv8i16_v4i32:
13797
0
    case AArch64::SQRDMLAHv1i16:
13798
0
    case AArch64::SQRDMLAHv1i32:
13799
0
    case AArch64::SQRDMLAHv2i32:
13800
0
    case AArch64::SQRDMLAHv4i16:
13801
0
    case AArch64::SQRDMLAHv4i32:
13802
0
    case AArch64::SQRDMLAHv8i16:
13803
0
    case AArch64::SQRDMLSHv1i16:
13804
0
    case AArch64::SQRDMLSHv1i32:
13805
0
    case AArch64::SQRDMLSHv2i32:
13806
0
    case AArch64::SQRDMLSHv4i16:
13807
0
    case AArch64::SQRDMLSHv4i32:
13808
0
    case AArch64::SQRDMLSHv8i16:
13809
0
    case AArch64::SUBHNv2i64_v4i32:
13810
0
    case AArch64::SUBHNv4i32_v8i16:
13811
0
    case AArch64::SUBHNv8i16_v16i8:
13812
0
    case AArch64::UABALv2i32_v2i64:
13813
0
    case AArch64::UABALv4i16_v4i32:
13814
0
    case AArch64::UABALv4i32_v2i64:
13815
0
    case AArch64::UABALv8i8_v8i16:
13816
0
    case AArch64::UABALv8i16_v4i32:
13817
0
    case AArch64::UABALv16i8_v8i16:
13818
0
    case AArch64::UABAv2i32:
13819
0
    case AArch64::UABAv4i16:
13820
0
    case AArch64::UABAv4i32:
13821
0
    case AArch64::UABAv8i8:
13822
0
    case AArch64::UABAv8i16:
13823
0
    case AArch64::UABAv16i8:
13824
0
    case AArch64::UDOTv8i8:
13825
0
    case AArch64::UDOTv16i8:
13826
0
    case AArch64::UMLALv2i32_v2i64:
13827
0
    case AArch64::UMLALv4i16_v4i32:
13828
0
    case AArch64::UMLALv4i32_v2i64:
13829
0
    case AArch64::UMLALv8i8_v8i16:
13830
0
    case AArch64::UMLALv8i16_v4i32:
13831
0
    case AArch64::UMLALv16i8_v8i16:
13832
0
    case AArch64::UMLSLv2i32_v2i64:
13833
0
    case AArch64::UMLSLv4i16_v4i32:
13834
0
    case AArch64::UMLSLv4i32_v2i64:
13835
0
    case AArch64::UMLSLv8i8_v8i16:
13836
0
    case AArch64::UMLSLv8i16_v4i32:
13837
0
    case AArch64::UMLSLv16i8_v8i16:
13838
0
    case AArch64::UMMLA:
13839
0
    case AArch64::USDOTv8i8:
13840
0
    case AArch64::USDOTv16i8:
13841
0
    case AArch64::USMMLA: {
13842
      // op: Rd
13843
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13844
0
      op &= UINT64_C(31);
13845
0
      Value |= op;
13846
      // op: Rn
13847
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13848
0
      op &= UINT64_C(31);
13849
0
      op <<= 5;
13850
0
      Value |= op;
13851
      // op: Rm
13852
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
13853
0
      op &= UINT64_C(31);
13854
0
      op <<= 16;
13855
0
      Value |= op;
13856
0
      break;
13857
0
    }
13858
0
    case AArch64::BF16DOTlanev4bf16:
13859
0
    case AArch64::BF16DOTlanev8bf16:
13860
0
    case AArch64::FDOTlanev8f8:
13861
0
    case AArch64::FDOTlanev16f8:
13862
0
    case AArch64::FMLAv1i32_indexed:
13863
0
    case AArch64::FMLAv2i32_indexed:
13864
0
    case AArch64::FMLAv4i32_indexed:
13865
0
    case AArch64::FMLSv1i32_indexed:
13866
0
    case AArch64::FMLSv2i32_indexed:
13867
0
    case AArch64::FMLSv4i32_indexed:
13868
0
    case AArch64::MLAv2i32_indexed:
13869
0
    case AArch64::MLAv4i32_indexed:
13870
0
    case AArch64::MLSv2i32_indexed:
13871
0
    case AArch64::MLSv4i32_indexed:
13872
0
    case AArch64::SDOTlanev8i8:
13873
0
    case AArch64::SDOTlanev16i8:
13874
0
    case AArch64::SMLALv2i32_indexed:
13875
0
    case AArch64::SMLALv4i32_indexed:
13876
0
    case AArch64::SMLSLv2i32_indexed:
13877
0
    case AArch64::SMLSLv4i32_indexed:
13878
0
    case AArch64::SQDMLALv1i64_indexed:
13879
0
    case AArch64::SQDMLALv2i32_indexed:
13880
0
    case AArch64::SQDMLALv4i32_indexed:
13881
0
    case AArch64::SQDMLSLv1i64_indexed:
13882
0
    case AArch64::SQDMLSLv2i32_indexed:
13883
0
    case AArch64::SQDMLSLv4i32_indexed:
13884
0
    case AArch64::SQRDMLAHv1i32_indexed:
13885
0
    case AArch64::SQRDMLAHv2i32_indexed:
13886
0
    case AArch64::SQRDMLAHv4i32_indexed:
13887
0
    case AArch64::SQRDMLSHv1i32_indexed:
13888
0
    case AArch64::SQRDMLSHv2i32_indexed:
13889
0
    case AArch64::SQRDMLSHv4i32_indexed:
13890
0
    case AArch64::SUDOTlanev8i8:
13891
0
    case AArch64::SUDOTlanev16i8:
13892
0
    case AArch64::UDOTlanev8i8:
13893
0
    case AArch64::UDOTlanev16i8:
13894
0
    case AArch64::UMLALv2i32_indexed:
13895
0
    case AArch64::UMLALv4i32_indexed:
13896
0
    case AArch64::UMLSLv2i32_indexed:
13897
0
    case AArch64::UMLSLv4i32_indexed:
13898
0
    case AArch64::USDOTlanev8i8:
13899
0
    case AArch64::USDOTlanev16i8: {
13900
      // op: Rd
13901
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13902
0
      op &= UINT64_C(31);
13903
0
      Value |= op;
13904
      // op: Rn
13905
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13906
0
      op &= UINT64_C(31);
13907
0
      op <<= 5;
13908
0
      Value |= op;
13909
      // op: Rm
13910
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
13911
0
      op &= UINT64_C(31);
13912
0
      op <<= 16;
13913
0
      Value |= op;
13914
      // op: idx
13915
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
13916
0
      Value |= (op & UINT64_C(1)) << 21;
13917
0
      Value |= (op & UINT64_C(2)) << 10;
13918
0
      break;
13919
0
    }
13920
0
    case AArch64::FMLAv1i64_indexed:
13921
0
    case AArch64::FMLAv2i64_indexed:
13922
0
    case AArch64::FMLSv1i64_indexed:
13923
0
    case AArch64::FMLSv2i64_indexed: {
13924
      // op: Rd
13925
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13926
0
      op &= UINT64_C(31);
13927
0
      Value |= op;
13928
      // op: Rn
13929
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13930
0
      op &= UINT64_C(31);
13931
0
      op <<= 5;
13932
0
      Value |= op;
13933
      // op: Rm
13934
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
13935
0
      op &= UINT64_C(31);
13936
0
      op <<= 16;
13937
0
      Value |= op;
13938
      // op: idx
13939
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
13940
0
      op &= UINT64_C(1);
13941
0
      op <<= 11;
13942
0
      Value |= op;
13943
0
      break;
13944
0
    }
13945
0
    case AArch64::FCMLAv2f32:
13946
0
    case AArch64::FCMLAv2f64:
13947
0
    case AArch64::FCMLAv4f16:
13948
0
    case AArch64::FCMLAv4f32:
13949
0
    case AArch64::FCMLAv8f16: {
13950
      // op: Rd
13951
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13952
0
      op &= UINT64_C(31);
13953
0
      Value |= op;
13954
      // op: Rn
13955
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13956
0
      op &= UINT64_C(31);
13957
0
      op <<= 5;
13958
0
      Value |= op;
13959
      // op: Rm
13960
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
13961
0
      op &= UINT64_C(31);
13962
0
      op <<= 16;
13963
0
      Value |= op;
13964
      // op: rot
13965
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
13966
0
      op &= UINT64_C(3);
13967
0
      op <<= 11;
13968
0
      Value |= op;
13969
0
      break;
13970
0
    }
13971
0
    case AArch64::FCMLAv8f16_indexed: {
13972
      // op: Rd
13973
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13974
0
      op &= UINT64_C(31);
13975
0
      Value |= op;
13976
      // op: Rn
13977
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13978
0
      op &= UINT64_C(31);
13979
0
      op <<= 5;
13980
0
      Value |= op;
13981
      // op: Rm
13982
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
13983
0
      op &= UINT64_C(31);
13984
0
      op <<= 16;
13985
0
      Value |= op;
13986
      // op: rot
13987
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
13988
0
      op &= UINT64_C(3);
13989
0
      op <<= 13;
13990
0
      Value |= op;
13991
      // op: idx
13992
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
13993
0
      Value |= (op & UINT64_C(1)) << 21;
13994
0
      Value |= (op & UINT64_C(2)) << 10;
13995
0
      break;
13996
0
    }
13997
0
    case AArch64::FCMLAv4f32_indexed: {
13998
      // op: Rd
13999
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14000
0
      op &= UINT64_C(31);
14001
0
      Value |= op;
14002
      // op: Rn
14003
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14004
0
      op &= UINT64_C(31);
14005
0
      op <<= 5;
14006
0
      Value |= op;
14007
      // op: Rm
14008
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14009
0
      op &= UINT64_C(31);
14010
0
      op <<= 16;
14011
0
      Value |= op;
14012
      // op: rot
14013
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
14014
0
      op &= UINT64_C(3);
14015
0
      op <<= 13;
14016
0
      Value |= op;
14017
      // op: idx
14018
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
14019
0
      op &= UINT64_C(1);
14020
0
      op <<= 11;
14021
0
      Value |= op;
14022
0
      break;
14023
0
    }
14024
0
    case AArch64::FCMLAv4f16_indexed: {
14025
      // op: Rd
14026
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14027
0
      op &= UINT64_C(31);
14028
0
      Value |= op;
14029
      // op: Rn
14030
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14031
0
      op &= UINT64_C(31);
14032
0
      op <<= 5;
14033
0
      Value |= op;
14034
      // op: Rm
14035
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14036
0
      op &= UINT64_C(31);
14037
0
      op <<= 16;
14038
0
      Value |= op;
14039
      // op: rot
14040
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
14041
0
      op &= UINT64_C(3);
14042
0
      op <<= 13;
14043
0
      Value |= op;
14044
      // op: idx
14045
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
14046
0
      op &= UINT64_C(1);
14047
0
      op <<= 21;
14048
0
      Value |= op;
14049
0
      break;
14050
0
    }
14051
0
    case AArch64::FMLALBlanev8f16:
14052
0
    case AArch64::FMLALLBBlanev4f32:
14053
0
    case AArch64::FMLALLBTlanev4f32:
14054
0
    case AArch64::FMLALLTBlanev4f32:
14055
0
    case AArch64::FMLALLTTlanev4f32:
14056
0
    case AArch64::FMLALTlanev8f16: {
14057
      // op: Rd
14058
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14059
0
      op &= UINT64_C(31);
14060
0
      Value |= op;
14061
      // op: Rn
14062
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14063
0
      op &= UINT64_C(31);
14064
0
      op <<= 5;
14065
0
      Value |= op;
14066
      // op: Rm
14067
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14068
0
      op &= UINT64_C(7);
14069
0
      op <<= 16;
14070
0
      Value |= op;
14071
      // op: idx
14072
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
14073
0
      Value |= (op & UINT64_C(7)) << 19;
14074
0
      Value |= (op & UINT64_C(8)) << 8;
14075
0
      break;
14076
0
    }
14077
0
    case AArch64::SLIv4i16_shift:
14078
0
    case AArch64::SLIv8i16_shift: {
14079
      // op: Rd
14080
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14081
0
      op &= UINT64_C(31);
14082
0
      Value |= op;
14083
      // op: Rn
14084
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14085
0
      op &= UINT64_C(31);
14086
0
      op <<= 5;
14087
0
      Value |= op;
14088
      // op: imm
14089
0
      op = getVecShiftL16OpValue(MI, 3, Fixups, STI);
14090
0
      op &= UINT64_C(15);
14091
0
      op <<= 16;
14092
0
      Value |= op;
14093
0
      break;
14094
0
    }
14095
0
    case AArch64::SLIv2i32_shift:
14096
0
    case AArch64::SLIv4i32_shift: {
14097
      // op: Rd
14098
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14099
0
      op &= UINT64_C(31);
14100
0
      Value |= op;
14101
      // op: Rn
14102
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14103
0
      op &= UINT64_C(31);
14104
0
      op <<= 5;
14105
0
      Value |= op;
14106
      // op: imm
14107
0
      op = getVecShiftL32OpValue(MI, 3, Fixups, STI);
14108
0
      op &= UINT64_C(31);
14109
0
      op <<= 16;
14110
0
      Value |= op;
14111
0
      break;
14112
0
    }
14113
0
    case AArch64::SLId:
14114
0
    case AArch64::SLIv2i64_shift: {
14115
      // op: Rd
14116
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14117
0
      op &= UINT64_C(31);
14118
0
      Value |= op;
14119
      // op: Rn
14120
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14121
0
      op &= UINT64_C(31);
14122
0
      op <<= 5;
14123
0
      Value |= op;
14124
      // op: imm
14125
0
      op = getVecShiftL64OpValue(MI, 3, Fixups, STI);
14126
0
      op &= UINT64_C(63);
14127
0
      op <<= 16;
14128
0
      Value |= op;
14129
0
      break;
14130
0
    }
14131
0
    case AArch64::SLIv8i8_shift:
14132
0
    case AArch64::SLIv16i8_shift: {
14133
      // op: Rd
14134
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14135
0
      op &= UINT64_C(31);
14136
0
      Value |= op;
14137
      // op: Rn
14138
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14139
0
      op &= UINT64_C(31);
14140
0
      op <<= 5;
14141
0
      Value |= op;
14142
      // op: imm
14143
0
      op = getVecShiftL8OpValue(MI, 3, Fixups, STI);
14144
0
      op &= UINT64_C(7);
14145
0
      op <<= 16;
14146
0
      Value |= op;
14147
0
      break;
14148
0
    }
14149
0
    case AArch64::SRIv4i16_shift:
14150
0
    case AArch64::SRIv8i16_shift:
14151
0
    case AArch64::SRSRAv4i16_shift:
14152
0
    case AArch64::SRSRAv8i16_shift:
14153
0
    case AArch64::SSRAv4i16_shift:
14154
0
    case AArch64::SSRAv8i16_shift:
14155
0
    case AArch64::URSRAv4i16_shift:
14156
0
    case AArch64::URSRAv8i16_shift:
14157
0
    case AArch64::USRAv4i16_shift:
14158
0
    case AArch64::USRAv8i16_shift: {
14159
      // op: Rd
14160
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14161
0
      op &= UINT64_C(31);
14162
0
      Value |= op;
14163
      // op: Rn
14164
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14165
0
      op &= UINT64_C(31);
14166
0
      op <<= 5;
14167
0
      Value |= op;
14168
      // op: imm
14169
0
      op = getVecShiftR16OpValue(MI, 3, Fixups, STI);
14170
0
      op &= UINT64_C(15);
14171
0
      op <<= 16;
14172
0
      Value |= op;
14173
0
      break;
14174
0
    }
14175
0
    case AArch64::RSHRNv16i8_shift:
14176
0
    case AArch64::SHRNv16i8_shift:
14177
0
    case AArch64::SQRSHRNv16i8_shift:
14178
0
    case AArch64::SQRSHRUNv16i8_shift:
14179
0
    case AArch64::SQSHRNv16i8_shift:
14180
0
    case AArch64::SQSHRUNv16i8_shift:
14181
0
    case AArch64::UQRSHRNv16i8_shift:
14182
0
    case AArch64::UQSHRNv16i8_shift: {
14183
      // op: Rd
14184
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14185
0
      op &= UINT64_C(31);
14186
0
      Value |= op;
14187
      // op: Rn
14188
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14189
0
      op &= UINT64_C(31);
14190
0
      op <<= 5;
14191
0
      Value |= op;
14192
      // op: imm
14193
0
      op = getVecShiftR16OpValue(MI, 3, Fixups, STI);
14194
0
      op &= UINT64_C(7);
14195
0
      op <<= 16;
14196
0
      Value |= op;
14197
0
      break;
14198
0
    }
14199
0
    case AArch64::RSHRNv8i16_shift:
14200
0
    case AArch64::SHRNv8i16_shift:
14201
0
    case AArch64::SQRSHRNv8i16_shift:
14202
0
    case AArch64::SQRSHRUNv8i16_shift:
14203
0
    case AArch64::SQSHRNv8i16_shift:
14204
0
    case AArch64::SQSHRUNv8i16_shift:
14205
0
    case AArch64::UQRSHRNv8i16_shift:
14206
0
    case AArch64::UQSHRNv8i16_shift: {
14207
      // op: Rd
14208
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14209
0
      op &= UINT64_C(31);
14210
0
      Value |= op;
14211
      // op: Rn
14212
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14213
0
      op &= UINT64_C(31);
14214
0
      op <<= 5;
14215
0
      Value |= op;
14216
      // op: imm
14217
0
      op = getVecShiftR32OpValue(MI, 3, Fixups, STI);
14218
0
      op &= UINT64_C(15);
14219
0
      op <<= 16;
14220
0
      Value |= op;
14221
0
      break;
14222
0
    }
14223
0
    case AArch64::SRIv2i32_shift:
14224
0
    case AArch64::SRIv4i32_shift:
14225
0
    case AArch64::SRSRAv2i32_shift:
14226
0
    case AArch64::SRSRAv4i32_shift:
14227
0
    case AArch64::SSRAv2i32_shift:
14228
0
    case AArch64::SSRAv4i32_shift:
14229
0
    case AArch64::URSRAv2i32_shift:
14230
0
    case AArch64::URSRAv4i32_shift:
14231
0
    case AArch64::USRAv2i32_shift:
14232
0
    case AArch64::USRAv4i32_shift: {
14233
      // op: Rd
14234
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14235
0
      op &= UINT64_C(31);
14236
0
      Value |= op;
14237
      // op: Rn
14238
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14239
0
      op &= UINT64_C(31);
14240
0
      op <<= 5;
14241
0
      Value |= op;
14242
      // op: imm
14243
0
      op = getVecShiftR32OpValue(MI, 3, Fixups, STI);
14244
0
      op &= UINT64_C(31);
14245
0
      op <<= 16;
14246
0
      Value |= op;
14247
0
      break;
14248
0
    }
14249
0
    case AArch64::RSHRNv4i32_shift:
14250
0
    case AArch64::SHRNv4i32_shift:
14251
0
    case AArch64::SQRSHRNv4i32_shift:
14252
0
    case AArch64::SQRSHRUNv4i32_shift:
14253
0
    case AArch64::SQSHRNv4i32_shift:
14254
0
    case AArch64::SQSHRUNv4i32_shift:
14255
0
    case AArch64::UQRSHRNv4i32_shift:
14256
0
    case AArch64::UQSHRNv4i32_shift: {
14257
      // op: Rd
14258
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14259
0
      op &= UINT64_C(31);
14260
0
      Value |= op;
14261
      // op: Rn
14262
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14263
0
      op &= UINT64_C(31);
14264
0
      op <<= 5;
14265
0
      Value |= op;
14266
      // op: imm
14267
0
      op = getVecShiftR64OpValue(MI, 3, Fixups, STI);
14268
0
      op &= UINT64_C(31);
14269
0
      op <<= 16;
14270
0
      Value |= op;
14271
0
      break;
14272
0
    }
14273
0
    case AArch64::SRId:
14274
0
    case AArch64::SRIv2i64_shift:
14275
0
    case AArch64::SRSRAd:
14276
0
    case AArch64::SRSRAv2i64_shift:
14277
0
    case AArch64::SSRAd:
14278
0
    case AArch64::SSRAv2i64_shift:
14279
0
    case AArch64::URSRAd:
14280
0
    case AArch64::URSRAv2i64_shift:
14281
0
    case AArch64::USRAd:
14282
0
    case AArch64::USRAv2i64_shift: {
14283
      // op: Rd
14284
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14285
0
      op &= UINT64_C(31);
14286
0
      Value |= op;
14287
      // op: Rn
14288
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14289
0
      op &= UINT64_C(31);
14290
0
      op <<= 5;
14291
0
      Value |= op;
14292
      // op: imm
14293
0
      op = getVecShiftR64OpValue(MI, 3, Fixups, STI);
14294
0
      op &= UINT64_C(63);
14295
0
      op <<= 16;
14296
0
      Value |= op;
14297
0
      break;
14298
0
    }
14299
0
    case AArch64::SRIv8i8_shift:
14300
0
    case AArch64::SRIv16i8_shift:
14301
0
    case AArch64::SRSRAv8i8_shift:
14302
0
    case AArch64::SRSRAv16i8_shift:
14303
0
    case AArch64::SSRAv8i8_shift:
14304
0
    case AArch64::SSRAv16i8_shift:
14305
0
    case AArch64::URSRAv8i8_shift:
14306
0
    case AArch64::URSRAv16i8_shift:
14307
0
    case AArch64::USRAv8i8_shift:
14308
0
    case AArch64::USRAv16i8_shift: {
14309
      // op: Rd
14310
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14311
0
      op &= UINT64_C(31);
14312
0
      Value |= op;
14313
      // op: Rn
14314
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14315
0
      op &= UINT64_C(31);
14316
0
      op <<= 5;
14317
0
      Value |= op;
14318
      // op: imm
14319
0
      op = getVecShiftR8OpValue(MI, 3, Fixups, STI);
14320
0
      op &= UINT64_C(7);
14321
0
      op <<= 16;
14322
0
      Value |= op;
14323
0
      break;
14324
0
    }
14325
0
    case AArch64::INSvi64gpr: {
14326
      // op: Rd
14327
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14328
0
      op &= UINT64_C(31);
14329
0
      Value |= op;
14330
      // op: Rn
14331
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14332
0
      op &= UINT64_C(31);
14333
0
      op <<= 5;
14334
0
      Value |= op;
14335
      // op: idx
14336
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14337
0
      op &= UINT64_C(1);
14338
0
      op <<= 20;
14339
0
      Value |= op;
14340
0
      break;
14341
0
    }
14342
0
    case AArch64::INSvi64lane: {
14343
      // op: Rd
14344
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14345
0
      op &= UINT64_C(31);
14346
0
      Value |= op;
14347
      // op: Rn
14348
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14349
0
      op &= UINT64_C(31);
14350
0
      op <<= 5;
14351
0
      Value |= op;
14352
      // op: idx
14353
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14354
0
      op &= UINT64_C(1);
14355
0
      op <<= 20;
14356
0
      Value |= op;
14357
      // op: idx2
14358
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
14359
0
      op &= UINT64_C(1);
14360
0
      op <<= 14;
14361
0
      Value |= op;
14362
0
      break;
14363
0
    }
14364
0
    case AArch64::INSvi8gpr: {
14365
      // op: Rd
14366
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14367
0
      op &= UINT64_C(31);
14368
0
      Value |= op;
14369
      // op: Rn
14370
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14371
0
      op &= UINT64_C(31);
14372
0
      op <<= 5;
14373
0
      Value |= op;
14374
      // op: idx
14375
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14376
0
      op &= UINT64_C(15);
14377
0
      op <<= 17;
14378
0
      Value |= op;
14379
0
      break;
14380
0
    }
14381
0
    case AArch64::INSvi8lane: {
14382
      // op: Rd
14383
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14384
0
      op &= UINT64_C(31);
14385
0
      Value |= op;
14386
      // op: Rn
14387
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14388
0
      op &= UINT64_C(31);
14389
0
      op <<= 5;
14390
0
      Value |= op;
14391
      // op: idx
14392
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14393
0
      op &= UINT64_C(15);
14394
0
      op <<= 17;
14395
0
      Value |= op;
14396
      // op: idx2
14397
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
14398
0
      op &= UINT64_C(15);
14399
0
      op <<= 11;
14400
0
      Value |= op;
14401
0
      break;
14402
0
    }
14403
0
    case AArch64::INSvi32gpr: {
14404
      // op: Rd
14405
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14406
0
      op &= UINT64_C(31);
14407
0
      Value |= op;
14408
      // op: Rn
14409
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14410
0
      op &= UINT64_C(31);
14411
0
      op <<= 5;
14412
0
      Value |= op;
14413
      // op: idx
14414
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14415
0
      op &= UINT64_C(3);
14416
0
      op <<= 19;
14417
0
      Value |= op;
14418
0
      break;
14419
0
    }
14420
0
    case AArch64::INSvi32lane: {
14421
      // op: Rd
14422
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14423
0
      op &= UINT64_C(31);
14424
0
      Value |= op;
14425
      // op: Rn
14426
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14427
0
      op &= UINT64_C(31);
14428
0
      op <<= 5;
14429
0
      Value |= op;
14430
      // op: idx
14431
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14432
0
      op &= UINT64_C(3);
14433
0
      op <<= 19;
14434
0
      Value |= op;
14435
      // op: idx2
14436
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
14437
0
      op &= UINT64_C(3);
14438
0
      op <<= 13;
14439
0
      Value |= op;
14440
0
      break;
14441
0
    }
14442
0
    case AArch64::INSvi16gpr: {
14443
      // op: Rd
14444
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14445
0
      op &= UINT64_C(31);
14446
0
      Value |= op;
14447
      // op: Rn
14448
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14449
0
      op &= UINT64_C(31);
14450
0
      op <<= 5;
14451
0
      Value |= op;
14452
      // op: idx
14453
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14454
0
      op &= UINT64_C(7);
14455
0
      op <<= 18;
14456
0
      Value |= op;
14457
0
      break;
14458
0
    }
14459
0
    case AArch64::INSvi16lane: {
14460
      // op: Rd
14461
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14462
0
      op &= UINT64_C(31);
14463
0
      Value |= op;
14464
      // op: Rn
14465
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14466
0
      op &= UINT64_C(31);
14467
0
      op <<= 5;
14468
0
      Value |= op;
14469
      // op: idx
14470
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14471
0
      op &= UINT64_C(7);
14472
0
      op <<= 18;
14473
0
      Value |= op;
14474
      // op: idx2
14475
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
14476
0
      op &= UINT64_C(7);
14477
0
      op <<= 12;
14478
0
      Value |= op;
14479
0
      break;
14480
0
    }
14481
0
    case AArch64::BICv4i16:
14482
0
    case AArch64::BICv8i16:
14483
0
    case AArch64::ORRv4i16:
14484
0
    case AArch64::ORRv8i16: {
14485
      // op: Rd
14486
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14487
0
      op &= UINT64_C(31);
14488
0
      Value |= op;
14489
      // op: imm8
14490
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14491
0
      Value |= (op & UINT64_C(224)) << 11;
14492
0
      Value |= (op & UINT64_C(31)) << 5;
14493
      // op: shift
14494
0
      op = getVecShifterOpValue(MI, 3, Fixups, STI);
14495
0
      op &= UINT64_C(1);
14496
0
      op <<= 13;
14497
0
      Value |= op;
14498
0
      break;
14499
0
    }
14500
0
    case AArch64::BICv2i32:
14501
0
    case AArch64::BICv4i32:
14502
0
    case AArch64::ORRv2i32:
14503
0
    case AArch64::ORRv4i32: {
14504
      // op: Rd
14505
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14506
0
      op &= UINT64_C(31);
14507
0
      Value |= op;
14508
      // op: imm8
14509
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14510
0
      Value |= (op & UINT64_C(224)) << 11;
14511
0
      Value |= (op & UINT64_C(31)) << 5;
14512
      // op: shift
14513
0
      op = getVecShifterOpValue(MI, 3, Fixups, STI);
14514
0
      op &= UINT64_C(3);
14515
0
      op <<= 13;
14516
0
      Value |= op;
14517
0
      break;
14518
0
    }
14519
0
    case AArch64::MOPSSETGE:
14520
0
    case AArch64::MOPSSETGEN:
14521
0
    case AArch64::MOPSSETGET:
14522
0
    case AArch64::MOPSSETGETN:
14523
0
    case AArch64::SETE:
14524
0
    case AArch64::SETEN:
14525
0
    case AArch64::SETET:
14526
0
    case AArch64::SETETN:
14527
0
    case AArch64::SETGM:
14528
0
    case AArch64::SETGMN:
14529
0
    case AArch64::SETGMT:
14530
0
    case AArch64::SETGMTN:
14531
0
    case AArch64::SETGP:
14532
0
    case AArch64::SETGPN:
14533
0
    case AArch64::SETGPT:
14534
0
    case AArch64::SETGPTN:
14535
0
    case AArch64::SETM:
14536
0
    case AArch64::SETMN:
14537
0
    case AArch64::SETMT:
14538
0
    case AArch64::SETMTN:
14539
0
    case AArch64::SETP:
14540
0
    case AArch64::SETPN:
14541
0
    case AArch64::SETPT:
14542
0
    case AArch64::SETPTN: {
14543
      // op: Rd
14544
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14545
0
      op &= UINT64_C(31);
14546
0
      Value |= op;
14547
      // op: Rn
14548
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14549
0
      op &= UINT64_C(31);
14550
0
      op <<= 5;
14551
0
      Value |= op;
14552
      // op: Rm
14553
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
14554
0
      op &= UINT64_C(31);
14555
0
      op <<= 16;
14556
0
      Value |= op;
14557
0
      break;
14558
0
    }
14559
0
    case AArch64::CPYE:
14560
0
    case AArch64::CPYEN:
14561
0
    case AArch64::CPYERN:
14562
0
    case AArch64::CPYERT:
14563
0
    case AArch64::CPYERTN:
14564
0
    case AArch64::CPYERTRN:
14565
0
    case AArch64::CPYERTWN:
14566
0
    case AArch64::CPYET:
14567
0
    case AArch64::CPYETN:
14568
0
    case AArch64::CPYETRN:
14569
0
    case AArch64::CPYETWN:
14570
0
    case AArch64::CPYEWN:
14571
0
    case AArch64::CPYEWT:
14572
0
    case AArch64::CPYEWTN:
14573
0
    case AArch64::CPYEWTRN:
14574
0
    case AArch64::CPYEWTWN:
14575
0
    case AArch64::CPYFE:
14576
0
    case AArch64::CPYFEN:
14577
0
    case AArch64::CPYFERN:
14578
0
    case AArch64::CPYFERT:
14579
0
    case AArch64::CPYFERTN:
14580
0
    case AArch64::CPYFERTRN:
14581
0
    case AArch64::CPYFERTWN:
14582
0
    case AArch64::CPYFET:
14583
0
    case AArch64::CPYFETN:
14584
0
    case AArch64::CPYFETRN:
14585
0
    case AArch64::CPYFETWN:
14586
0
    case AArch64::CPYFEWN:
14587
0
    case AArch64::CPYFEWT:
14588
0
    case AArch64::CPYFEWTN:
14589
0
    case AArch64::CPYFEWTRN:
14590
0
    case AArch64::CPYFEWTWN:
14591
0
    case AArch64::CPYFM:
14592
0
    case AArch64::CPYFMN:
14593
0
    case AArch64::CPYFMRN:
14594
0
    case AArch64::CPYFMRT:
14595
0
    case AArch64::CPYFMRTN:
14596
0
    case AArch64::CPYFMRTRN:
14597
0
    case AArch64::CPYFMRTWN:
14598
0
    case AArch64::CPYFMT:
14599
0
    case AArch64::CPYFMTN:
14600
0
    case AArch64::CPYFMTRN:
14601
0
    case AArch64::CPYFMTWN:
14602
0
    case AArch64::CPYFMWN:
14603
0
    case AArch64::CPYFMWT:
14604
0
    case AArch64::CPYFMWTN:
14605
0
    case AArch64::CPYFMWTRN:
14606
0
    case AArch64::CPYFMWTWN:
14607
0
    case AArch64::CPYFP:
14608
0
    case AArch64::CPYFPN:
14609
0
    case AArch64::CPYFPRN:
14610
0
    case AArch64::CPYFPRT:
14611
0
    case AArch64::CPYFPRTN:
14612
0
    case AArch64::CPYFPRTRN:
14613
0
    case AArch64::CPYFPRTWN:
14614
0
    case AArch64::CPYFPT:
14615
0
    case AArch64::CPYFPTN:
14616
0
    case AArch64::CPYFPTRN:
14617
0
    case AArch64::CPYFPTWN:
14618
0
    case AArch64::CPYFPWN:
14619
0
    case AArch64::CPYFPWT:
14620
0
    case AArch64::CPYFPWTN:
14621
0
    case AArch64::CPYFPWTRN:
14622
0
    case AArch64::CPYFPWTWN:
14623
0
    case AArch64::CPYM:
14624
0
    case AArch64::CPYMN:
14625
0
    case AArch64::CPYMRN:
14626
0
    case AArch64::CPYMRT:
14627
0
    case AArch64::CPYMRTN:
14628
0
    case AArch64::CPYMRTRN:
14629
0
    case AArch64::CPYMRTWN:
14630
0
    case AArch64::CPYMT:
14631
0
    case AArch64::CPYMTN:
14632
0
    case AArch64::CPYMTRN:
14633
0
    case AArch64::CPYMTWN:
14634
0
    case AArch64::CPYMWN:
14635
0
    case AArch64::CPYMWT:
14636
0
    case AArch64::CPYMWTN:
14637
0
    case AArch64::CPYMWTRN:
14638
0
    case AArch64::CPYMWTWN:
14639
0
    case AArch64::CPYP:
14640
0
    case AArch64::CPYPN:
14641
0
    case AArch64::CPYPRN:
14642
0
    case AArch64::CPYPRT:
14643
0
    case AArch64::CPYPRTN:
14644
0
    case AArch64::CPYPRTRN:
14645
0
    case AArch64::CPYPRTWN:
14646
0
    case AArch64::CPYPT:
14647
0
    case AArch64::CPYPTN:
14648
0
    case AArch64::CPYPTRN:
14649
0
    case AArch64::CPYPTWN:
14650
0
    case AArch64::CPYPWN:
14651
0
    case AArch64::CPYPWT:
14652
0
    case AArch64::CPYPWTN:
14653
0
    case AArch64::CPYPWTRN:
14654
0
    case AArch64::CPYPWTWN: {
14655
      // op: Rd
14656
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14657
0
      op &= UINT64_C(31);
14658
0
      Value |= op;
14659
      // op: Rs
14660
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
14661
0
      op &= UINT64_C(31);
14662
0
      op <<= 16;
14663
0
      Value |= op;
14664
      // op: Rn
14665
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
14666
0
      op &= UINT64_C(31);
14667
0
      op <<= 5;
14668
0
      Value |= op;
14669
0
      break;
14670
0
    }
14671
0
    case AArch64::DECP_XP_B:
14672
0
    case AArch64::DECP_XP_D:
14673
0
    case AArch64::DECP_XP_H:
14674
0
    case AArch64::DECP_XP_S:
14675
0
    case AArch64::INCP_XP_B:
14676
0
    case AArch64::INCP_XP_D:
14677
0
    case AArch64::INCP_XP_H:
14678
0
    case AArch64::INCP_XP_S:
14679
0
    case AArch64::SQDECP_XPWd_B:
14680
0
    case AArch64::SQDECP_XPWd_D:
14681
0
    case AArch64::SQDECP_XPWd_H:
14682
0
    case AArch64::SQDECP_XPWd_S:
14683
0
    case AArch64::SQDECP_XP_B:
14684
0
    case AArch64::SQDECP_XP_D:
14685
0
    case AArch64::SQDECP_XP_H:
14686
0
    case AArch64::SQDECP_XP_S:
14687
0
    case AArch64::SQINCP_XPWd_B:
14688
0
    case AArch64::SQINCP_XPWd_D:
14689
0
    case AArch64::SQINCP_XPWd_H:
14690
0
    case AArch64::SQINCP_XPWd_S:
14691
0
    case AArch64::SQINCP_XP_B:
14692
0
    case AArch64::SQINCP_XP_D:
14693
0
    case AArch64::SQINCP_XP_H:
14694
0
    case AArch64::SQINCP_XP_S:
14695
0
    case AArch64::UQDECP_WP_B:
14696
0
    case AArch64::UQDECP_WP_D:
14697
0
    case AArch64::UQDECP_WP_H:
14698
0
    case AArch64::UQDECP_WP_S:
14699
0
    case AArch64::UQDECP_XP_B:
14700
0
    case AArch64::UQDECP_XP_D:
14701
0
    case AArch64::UQDECP_XP_H:
14702
0
    case AArch64::UQDECP_XP_S:
14703
0
    case AArch64::UQINCP_WP_B:
14704
0
    case AArch64::UQINCP_WP_D:
14705
0
    case AArch64::UQINCP_WP_H:
14706
0
    case AArch64::UQINCP_WP_S:
14707
0
    case AArch64::UQINCP_XP_B:
14708
0
    case AArch64::UQINCP_XP_D:
14709
0
    case AArch64::UQINCP_XP_H:
14710
0
    case AArch64::UQINCP_XP_S: {
14711
      // op: Rdn
14712
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14713
0
      op &= UINT64_C(31);
14714
0
      Value |= op;
14715
      // op: Pg
14716
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14717
0
      op &= UINT64_C(15);
14718
0
      op <<= 5;
14719
0
      Value |= op;
14720
0
      break;
14721
0
    }
14722
0
    case AArch64::DECB_XPiI:
14723
0
    case AArch64::DECD_XPiI:
14724
0
    case AArch64::DECH_XPiI:
14725
0
    case AArch64::DECW_XPiI:
14726
0
    case AArch64::INCB_XPiI:
14727
0
    case AArch64::INCD_XPiI:
14728
0
    case AArch64::INCH_XPiI:
14729
0
    case AArch64::INCW_XPiI:
14730
0
    case AArch64::SQDECB_XPiI:
14731
0
    case AArch64::SQDECB_XPiWdI:
14732
0
    case AArch64::SQDECD_XPiI:
14733
0
    case AArch64::SQDECD_XPiWdI:
14734
0
    case AArch64::SQDECH_XPiI:
14735
0
    case AArch64::SQDECH_XPiWdI:
14736
0
    case AArch64::SQDECW_XPiI:
14737
0
    case AArch64::SQDECW_XPiWdI:
14738
0
    case AArch64::SQINCB_XPiI:
14739
0
    case AArch64::SQINCB_XPiWdI:
14740
0
    case AArch64::SQINCD_XPiI:
14741
0
    case AArch64::SQINCD_XPiWdI:
14742
0
    case AArch64::SQINCH_XPiI:
14743
0
    case AArch64::SQINCH_XPiWdI:
14744
0
    case AArch64::SQINCW_XPiI:
14745
0
    case AArch64::SQINCW_XPiWdI:
14746
0
    case AArch64::UQDECB_WPiI:
14747
0
    case AArch64::UQDECB_XPiI:
14748
0
    case AArch64::UQDECD_WPiI:
14749
0
    case AArch64::UQDECD_XPiI:
14750
0
    case AArch64::UQDECH_WPiI:
14751
0
    case AArch64::UQDECH_XPiI:
14752
0
    case AArch64::UQDECW_WPiI:
14753
0
    case AArch64::UQDECW_XPiI:
14754
0
    case AArch64::UQINCB_WPiI:
14755
0
    case AArch64::UQINCB_XPiI:
14756
0
    case AArch64::UQINCD_WPiI:
14757
0
    case AArch64::UQINCD_XPiI:
14758
0
    case AArch64::UQINCH_WPiI:
14759
0
    case AArch64::UQINCH_XPiI:
14760
0
    case AArch64::UQINCW_WPiI:
14761
0
    case AArch64::UQINCW_XPiI: {
14762
      // op: Rdn
14763
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14764
0
      op &= UINT64_C(31);
14765
0
      Value |= op;
14766
      // op: pattern
14767
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14768
0
      op &= UINT64_C(31);
14769
0
      op <<= 5;
14770
0
      Value |= op;
14771
      // op: imm4
14772
0
      op = getSVEIncDecImm(MI, 3, Fixups, STI);
14773
0
      op &= UINT64_C(15);
14774
0
      op <<= 16;
14775
0
      Value |= op;
14776
0
      break;
14777
0
    }
14778
0
    case AArch64::RETAASPPCr:
14779
0
    case AArch64::RETABSPPCr: {
14780
      // op: Rm
14781
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14782
0
      op &= UINT64_C(31);
14783
0
      Value |= op;
14784
0
      break;
14785
0
    }
14786
0
    case AArch64::CTERMEQ_WW:
14787
0
    case AArch64::CTERMEQ_XX:
14788
0
    case AArch64::CTERMNE_WW:
14789
0
    case AArch64::CTERMNE_XX:
14790
0
    case AArch64::FCMPDrr:
14791
0
    case AArch64::FCMPEDrr:
14792
0
    case AArch64::FCMPEHrr:
14793
0
    case AArch64::FCMPESrr:
14794
0
    case AArch64::FCMPHrr:
14795
0
    case AArch64::FCMPSrr: {
14796
      // op: Rm
14797
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14798
0
      op &= UINT64_C(31);
14799
0
      op <<= 16;
14800
0
      Value |= op;
14801
      // op: Rn
14802
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14803
0
      op &= UINT64_C(31);
14804
0
      op <<= 5;
14805
0
      Value |= op;
14806
0
      break;
14807
0
    }
14808
0
    case AArch64::INDEX_IR_B:
14809
0
    case AArch64::INDEX_IR_D:
14810
0
    case AArch64::INDEX_IR_H:
14811
0
    case AArch64::INDEX_IR_S: {
14812
      // op: Rm
14813
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14814
0
      op &= UINT64_C(31);
14815
0
      op <<= 16;
14816
0
      Value |= op;
14817
      // op: Zd
14818
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14819
0
      op &= UINT64_C(31);
14820
0
      Value |= op;
14821
      // op: imm5
14822
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14823
0
      op &= UINT64_C(31);
14824
0
      op <<= 5;
14825
0
      Value |= op;
14826
0
      break;
14827
0
    }
14828
0
    case AArch64::INSR_ZR_B:
14829
0
    case AArch64::INSR_ZR_D:
14830
0
    case AArch64::INSR_ZR_H:
14831
0
    case AArch64::INSR_ZR_S: {
14832
      // op: Rm
14833
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14834
0
      op &= UINT64_C(31);
14835
0
      op <<= 5;
14836
0
      Value |= op;
14837
      // op: Zdn
14838
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14839
0
      op &= UINT64_C(31);
14840
0
      Value |= op;
14841
0
      break;
14842
0
    }
14843
0
    case AArch64::LD1B_2Z_STRIDED:
14844
0
    case AArch64::LD1D_2Z_STRIDED:
14845
0
    case AArch64::LD1H_2Z_STRIDED:
14846
0
    case AArch64::LD1W_2Z_STRIDED:
14847
0
    case AArch64::LDNT1B_2Z_STRIDED:
14848
0
    case AArch64::LDNT1D_2Z_STRIDED:
14849
0
    case AArch64::LDNT1H_2Z_STRIDED:
14850
0
    case AArch64::LDNT1W_2Z_STRIDED:
14851
0
    case AArch64::ST1B_2Z_STRIDED:
14852
0
    case AArch64::ST1D_2Z_STRIDED:
14853
0
    case AArch64::ST1H_2Z_STRIDED:
14854
0
    case AArch64::ST1W_2Z_STRIDED:
14855
0
    case AArch64::STNT1B_2Z_STRIDED:
14856
0
    case AArch64::STNT1D_2Z_STRIDED:
14857
0
    case AArch64::STNT1H_2Z_STRIDED:
14858
0
    case AArch64::STNT1W_2Z_STRIDED: {
14859
      // op: Rm
14860
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14861
0
      op &= UINT64_C(31);
14862
0
      op <<= 16;
14863
0
      Value |= op;
14864
      // op: PNg
14865
0
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
14866
0
      op &= UINT64_C(7);
14867
0
      op <<= 10;
14868
0
      Value |= op;
14869
      // op: Rn
14870
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14871
0
      op &= UINT64_C(31);
14872
0
      op <<= 5;
14873
0
      Value |= op;
14874
      // op: Zt
14875
0
      op = EncodeZPR2StridedRegisterClass(MI, 0, Fixups, STI);
14876
0
      Value |= (op & UINT64_C(8)) << 1;
14877
0
      Value |= (op & UINT64_C(7));
14878
0
      break;
14879
0
    }
14880
0
    case AArch64::LD1B_4Z_STRIDED:
14881
0
    case AArch64::LD1D_4Z_STRIDED:
14882
0
    case AArch64::LD1H_4Z_STRIDED:
14883
0
    case AArch64::LD1W_4Z_STRIDED:
14884
0
    case AArch64::LDNT1B_4Z_STRIDED:
14885
0
    case AArch64::LDNT1D_4Z_STRIDED:
14886
0
    case AArch64::LDNT1H_4Z_STRIDED:
14887
0
    case AArch64::LDNT1W_4Z_STRIDED:
14888
0
    case AArch64::ST1B_4Z_STRIDED:
14889
0
    case AArch64::ST1D_4Z_STRIDED:
14890
0
    case AArch64::ST1H_4Z_STRIDED:
14891
0
    case AArch64::ST1W_4Z_STRIDED:
14892
0
    case AArch64::STNT1B_4Z_STRIDED:
14893
0
    case AArch64::STNT1D_4Z_STRIDED:
14894
0
    case AArch64::STNT1H_4Z_STRIDED:
14895
0
    case AArch64::STNT1W_4Z_STRIDED: {
14896
      // op: Rm
14897
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14898
0
      op &= UINT64_C(31);
14899
0
      op <<= 16;
14900
0
      Value |= op;
14901
      // op: PNg
14902
0
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
14903
0
      op &= UINT64_C(7);
14904
0
      op <<= 10;
14905
0
      Value |= op;
14906
      // op: Rn
14907
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14908
0
      op &= UINT64_C(31);
14909
0
      op <<= 5;
14910
0
      Value |= op;
14911
      // op: Zt
14912
0
      op = EncodeZPR4StridedRegisterClass(MI, 0, Fixups, STI);
14913
0
      Value |= (op & UINT64_C(4)) << 2;
14914
0
      Value |= (op & UINT64_C(3));
14915
0
      break;
14916
0
    }
14917
0
    case AArch64::PRFB_PRR:
14918
0
    case AArch64::PRFD_PRR:
14919
0
    case AArch64::PRFH_PRR:
14920
0
    case AArch64::PRFW_PRR: {
14921
      // op: Rm
14922
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14923
0
      op &= UINT64_C(31);
14924
0
      op <<= 16;
14925
0
      Value |= op;
14926
      // op: Rn
14927
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14928
0
      op &= UINT64_C(31);
14929
0
      op <<= 5;
14930
0
      Value |= op;
14931
      // op: Pg
14932
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14933
0
      op &= UINT64_C(7);
14934
0
      op <<= 10;
14935
0
      Value |= op;
14936
      // op: prfop
14937
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14938
0
      op &= UINT64_C(15);
14939
0
      Value |= op;
14940
0
      break;
14941
0
    }
14942
0
    case AArch64::LD1_MXIPXX_H_H:
14943
0
    case AArch64::LD1_MXIPXX_V_H:
14944
0
    case AArch64::ST1_MXIPXX_H_H:
14945
0
    case AArch64::ST1_MXIPXX_V_H: {
14946
      // op: Rm
14947
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
14948
0
      op &= UINT64_C(31);
14949
0
      op <<= 16;
14950
0
      Value |= op;
14951
      // op: Rv
14952
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 1, Fixups, STI);
14953
0
      op &= UINT64_C(3);
14954
0
      op <<= 13;
14955
0
      Value |= op;
14956
      // op: Pg
14957
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14958
0
      op &= UINT64_C(7);
14959
0
      op <<= 10;
14960
0
      Value |= op;
14961
      // op: Rn
14962
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
14963
0
      op &= UINT64_C(31);
14964
0
      op <<= 5;
14965
0
      Value |= op;
14966
      // op: ZAt
14967
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14968
0
      op &= UINT64_C(1);
14969
0
      op <<= 3;
14970
0
      Value |= op;
14971
      // op: imm
14972
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14973
0
      op &= UINT64_C(7);
14974
0
      Value |= op;
14975
0
      break;
14976
0
    }
14977
0
    case AArch64::LD1_MXIPXX_H_Q:
14978
0
    case AArch64::LD1_MXIPXX_V_Q:
14979
0
    case AArch64::ST1_MXIPXX_H_Q:
14980
0
    case AArch64::ST1_MXIPXX_V_Q: {
14981
      // op: Rm
14982
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
14983
0
      op &= UINT64_C(31);
14984
0
      op <<= 16;
14985
0
      Value |= op;
14986
      // op: Rv
14987
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 1, Fixups, STI);
14988
0
      op &= UINT64_C(3);
14989
0
      op <<= 13;
14990
0
      Value |= op;
14991
      // op: Pg
14992
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14993
0
      op &= UINT64_C(7);
14994
0
      op <<= 10;
14995
0
      Value |= op;
14996
      // op: Rn
14997
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
14998
0
      op &= UINT64_C(31);
14999
0
      op <<= 5;
15000
0
      Value |= op;
15001
      // op: ZAt
15002
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15003
0
      op &= UINT64_C(15);
15004
0
      Value |= op;
15005
0
      break;
15006
0
    }
15007
0
    case AArch64::LD1_MXIPXX_H_S:
15008
0
    case AArch64::LD1_MXIPXX_V_S:
15009
0
    case AArch64::ST1_MXIPXX_H_S:
15010
0
    case AArch64::ST1_MXIPXX_V_S: {
15011
      // op: Rm
15012
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
15013
0
      op &= UINT64_C(31);
15014
0
      op <<= 16;
15015
0
      Value |= op;
15016
      // op: Rv
15017
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 1, Fixups, STI);
15018
0
      op &= UINT64_C(3);
15019
0
      op <<= 13;
15020
0
      Value |= op;
15021
      // op: Pg
15022
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15023
0
      op &= UINT64_C(7);
15024
0
      op <<= 10;
15025
0
      Value |= op;
15026
      // op: Rn
15027
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15028
0
      op &= UINT64_C(31);
15029
0
      op <<= 5;
15030
0
      Value |= op;
15031
      // op: ZAt
15032
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15033
0
      op &= UINT64_C(3);
15034
0
      op <<= 2;
15035
0
      Value |= op;
15036
      // op: imm
15037
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15038
0
      op &= UINT64_C(3);
15039
0
      Value |= op;
15040
0
      break;
15041
0
    }
15042
0
    case AArch64::LD1_MXIPXX_H_D:
15043
0
    case AArch64::LD1_MXIPXX_V_D:
15044
0
    case AArch64::ST1_MXIPXX_H_D:
15045
0
    case AArch64::ST1_MXIPXX_V_D: {
15046
      // op: Rm
15047
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
15048
0
      op &= UINT64_C(31);
15049
0
      op <<= 16;
15050
0
      Value |= op;
15051
      // op: Rv
15052
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 1, Fixups, STI);
15053
0
      op &= UINT64_C(3);
15054
0
      op <<= 13;
15055
0
      Value |= op;
15056
      // op: Pg
15057
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15058
0
      op &= UINT64_C(7);
15059
0
      op <<= 10;
15060
0
      Value |= op;
15061
      // op: Rn
15062
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15063
0
      op &= UINT64_C(31);
15064
0
      op <<= 5;
15065
0
      Value |= op;
15066
      // op: ZAt
15067
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15068
0
      op &= UINT64_C(7);
15069
0
      op <<= 1;
15070
0
      Value |= op;
15071
      // op: imm
15072
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15073
0
      op &= UINT64_C(1);
15074
0
      Value |= op;
15075
0
      break;
15076
0
    }
15077
0
    case AArch64::LD1_MXIPXX_H_B:
15078
0
    case AArch64::LD1_MXIPXX_V_B:
15079
0
    case AArch64::ST1_MXIPXX_H_B:
15080
0
    case AArch64::ST1_MXIPXX_V_B: {
15081
      // op: Rm
15082
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
15083
0
      op &= UINT64_C(31);
15084
0
      op <<= 16;
15085
0
      Value |= op;
15086
      // op: Rv
15087
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 1, Fixups, STI);
15088
0
      op &= UINT64_C(3);
15089
0
      op <<= 13;
15090
0
      Value |= op;
15091
      // op: Pg
15092
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15093
0
      op &= UINT64_C(7);
15094
0
      op <<= 10;
15095
0
      Value |= op;
15096
      // op: Rn
15097
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15098
0
      op &= UINT64_C(31);
15099
0
      op <<= 5;
15100
0
      Value |= op;
15101
      // op: imm
15102
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15103
0
      op &= UINT64_C(15);
15104
0
      Value |= op;
15105
0
      break;
15106
0
    }
15107
0
    case AArch64::AUTIASPPCr:
15108
0
    case AArch64::AUTIBSPPCr:
15109
0
    case AArch64::BLR:
15110
0
    case AArch64::BLRAAZ:
15111
0
    case AArch64::BLRABZ:
15112
0
    case AArch64::BR:
15113
0
    case AArch64::BRAAZ:
15114
0
    case AArch64::BRABZ:
15115
0
    case AArch64::RET:
15116
0
    case AArch64::SETF8:
15117
0
    case AArch64::SETF16: {
15118
      // op: Rn
15119
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15120
0
      op &= UINT64_C(31);
15121
0
      op <<= 5;
15122
0
      Value |= op;
15123
0
      break;
15124
0
    }
15125
0
    case AArch64::BLRAA:
15126
0
    case AArch64::BLRAB:
15127
0
    case AArch64::BRAA:
15128
0
    case AArch64::BRAB: {
15129
      // op: Rn
15130
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15131
0
      op &= UINT64_C(31);
15132
0
      op <<= 5;
15133
0
      Value |= op;
15134
      // op: Rm
15135
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15136
0
      op &= UINT64_C(31);
15137
0
      Value |= op;
15138
0
      break;
15139
0
    }
15140
0
    case AArch64::CCMNWr:
15141
0
    case AArch64::CCMNXr:
15142
0
    case AArch64::CCMPWr:
15143
0
    case AArch64::CCMPXr:
15144
0
    case AArch64::FCCMPDrr:
15145
0
    case AArch64::FCCMPEDrr:
15146
0
    case AArch64::FCCMPEHrr:
15147
0
    case AArch64::FCCMPESrr:
15148
0
    case AArch64::FCCMPHrr:
15149
0
    case AArch64::FCCMPSrr: {
15150
      // op: Rn
15151
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15152
0
      op &= UINT64_C(31);
15153
0
      op <<= 5;
15154
0
      Value |= op;
15155
      // op: Rm
15156
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15157
0
      op &= UINT64_C(31);
15158
0
      op <<= 16;
15159
0
      Value |= op;
15160
      // op: nzcv
15161
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15162
0
      op &= UINT64_C(15);
15163
0
      Value |= op;
15164
      // op: cond
15165
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15166
0
      op &= UINT64_C(15);
15167
0
      op <<= 12;
15168
0
      Value |= op;
15169
0
      break;
15170
0
    }
15171
0
    case AArch64::CCMNWi:
15172
0
    case AArch64::CCMNXi:
15173
0
    case AArch64::CCMPWi:
15174
0
    case AArch64::CCMPXi: {
15175
      // op: Rn
15176
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15177
0
      op &= UINT64_C(31);
15178
0
      op <<= 5;
15179
0
      Value |= op;
15180
      // op: imm
15181
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15182
0
      op &= UINT64_C(31);
15183
0
      op <<= 16;
15184
0
      Value |= op;
15185
      // op: nzcv
15186
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15187
0
      op &= UINT64_C(15);
15188
0
      Value |= op;
15189
      // op: cond
15190
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15191
0
      op &= UINT64_C(15);
15192
0
      op <<= 12;
15193
0
      Value |= op;
15194
0
      break;
15195
0
    }
15196
0
    case AArch64::RMIF: {
15197
      // op: Rn
15198
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15199
0
      op &= UINT64_C(31);
15200
0
      op <<= 5;
15201
0
      Value |= op;
15202
      // op: imm
15203
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15204
0
      op &= UINT64_C(63);
15205
0
      op <<= 15;
15206
0
      Value |= op;
15207
      // op: mask
15208
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15209
0
      op &= UINT64_C(15);
15210
0
      Value |= op;
15211
0
      break;
15212
0
    }
15213
0
    case AArch64::FCMPDri:
15214
0
    case AArch64::FCMPEDri:
15215
0
    case AArch64::FCMPEHri:
15216
0
    case AArch64::FCMPESri:
15217
0
    case AArch64::FCMPHri:
15218
0
    case AArch64::FCMPSri: {
15219
      // op: Rn
15220
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15221
0
      op &= UINT64_C(31);
15222
0
      op <<= 5;
15223
0
      Value |= op;
15224
0
      Value = fixOneOperandFPComparison(MI, Value, STI);
15225
0
      break;
15226
0
    }
15227
0
    case AArch64::LDR_TX:
15228
0
    case AArch64::STR_TX: {
15229
      // op: Rn
15230
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15231
0
      op &= UINT64_C(31);
15232
0
      op <<= 5;
15233
0
      Value |= op;
15234
0
      break;
15235
0
    }
15236
0
    case AArch64::LDAPRB:
15237
0
    case AArch64::LDAPRH:
15238
0
    case AArch64::LDAPRW:
15239
0
    case AArch64::LDAPRX:
15240
0
    case AArch64::LDGM:
15241
0
    case AArch64::STGM:
15242
0
    case AArch64::STZGM: {
15243
      // op: Rn
15244
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15245
0
      op &= UINT64_C(31);
15246
0
      op <<= 5;
15247
0
      Value |= op;
15248
      // op: Rt
15249
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15250
0
      op &= UINT64_C(31);
15251
0
      Value |= op;
15252
0
      break;
15253
0
    }
15254
0
    case AArch64::ST2Gi:
15255
0
    case AArch64::STGi:
15256
0
    case AArch64::STZ2Gi:
15257
0
    case AArch64::STZGi: {
15258
      // op: Rn
15259
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15260
0
      op &= UINT64_C(31);
15261
0
      op <<= 5;
15262
0
      Value |= op;
15263
      // op: Rt
15264
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15265
0
      op &= UINT64_C(31);
15266
0
      Value |= op;
15267
      // op: offset
15268
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15269
0
      op &= UINT64_C(511);
15270
0
      op <<= 12;
15271
0
      Value |= op;
15272
0
      break;
15273
0
    }
15274
0
    case AArch64::DUP_ZR_B:
15275
0
    case AArch64::DUP_ZR_D:
15276
0
    case AArch64::DUP_ZR_H:
15277
0
    case AArch64::DUP_ZR_S: {
15278
      // op: Rn
15279
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15280
0
      op &= UINT64_C(31);
15281
0
      op <<= 5;
15282
0
      Value |= op;
15283
      // op: Zd
15284
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15285
0
      op &= UINT64_C(31);
15286
0
      Value |= op;
15287
0
      break;
15288
0
    }
15289
0
    case AArch64::INDEX_RI_B:
15290
0
    case AArch64::INDEX_RI_D:
15291
0
    case AArch64::INDEX_RI_H:
15292
0
    case AArch64::INDEX_RI_S: {
15293
      // op: Rn
15294
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15295
0
      op &= UINT64_C(31);
15296
0
      op <<= 5;
15297
0
      Value |= op;
15298
      // op: Zd
15299
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15300
0
      op &= UINT64_C(31);
15301
0
      Value |= op;
15302
      // op: imm5
15303
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15304
0
      op &= UINT64_C(31);
15305
0
      op <<= 16;
15306
0
      Value |= op;
15307
0
      break;
15308
0
    }
15309
0
    case AArch64::LDR_ZXI:
15310
0
    case AArch64::STR_ZXI: {
15311
      // op: Rn
15312
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15313
0
      op &= UINT64_C(31);
15314
0
      op <<= 5;
15315
0
      Value |= op;
15316
      // op: Zt
15317
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15318
0
      op &= UINT64_C(31);
15319
0
      Value |= op;
15320
      // op: imm9
15321
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15322
0
      Value |= (op & UINT64_C(504)) << 13;
15323
0
      Value |= (op & UINT64_C(7)) << 10;
15324
0
      break;
15325
0
    }
15326
0
    case AArch64::PRFB_PRI:
15327
0
    case AArch64::PRFD_PRI:
15328
0
    case AArch64::PRFH_PRI:
15329
0
    case AArch64::PRFW_PRI: {
15330
      // op: Rn
15331
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15332
0
      op &= UINT64_C(31);
15333
0
      op <<= 5;
15334
0
      Value |= op;
15335
      // op: Pg
15336
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15337
0
      op &= UINT64_C(7);
15338
0
      op <<= 10;
15339
0
      Value |= op;
15340
      // op: imm6
15341
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15342
0
      op &= UINT64_C(63);
15343
0
      op <<= 16;
15344
0
      Value |= op;
15345
      // op: prfop
15346
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15347
0
      op &= UINT64_C(15);
15348
0
      Value |= op;
15349
0
      break;
15350
0
    }
15351
0
    case AArch64::LDG:
15352
0
    case AArch64::ST2GPostIndex:
15353
0
    case AArch64::ST2GPreIndex:
15354
0
    case AArch64::STGPostIndex:
15355
0
    case AArch64::STGPreIndex:
15356
0
    case AArch64::STZ2GPostIndex:
15357
0
    case AArch64::STZ2GPreIndex:
15358
0
    case AArch64::STZGPostIndex:
15359
0
    case AArch64::STZGPreIndex: {
15360
      // op: Rn
15361
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15362
0
      op &= UINT64_C(31);
15363
0
      op <<= 5;
15364
0
      Value |= op;
15365
      // op: Rt
15366
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15367
0
      op &= UINT64_C(31);
15368
0
      Value |= op;
15369
      // op: offset
15370
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15371
0
      op &= UINT64_C(511);
15372
0
      op <<= 12;
15373
0
      Value |= op;
15374
0
      break;
15375
0
    }
15376
0
    case AArch64::MOVA_MXI2Z_H_H:
15377
0
    case AArch64::MOVA_MXI2Z_V_H: {
15378
      // op: Rs
15379
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
15380
0
      op &= UINT64_C(3);
15381
0
      op <<= 13;
15382
0
      Value |= op;
15383
      // op: Zn
15384
0
      op = EncodeRegAsMultipleOf<2>(MI, 4, Fixups, STI);
15385
0
      op &= UINT64_C(15);
15386
0
      op <<= 6;
15387
0
      Value |= op;
15388
      // op: ZAd
15389
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15390
0
      op &= UINT64_C(1);
15391
0
      op <<= 2;
15392
0
      Value |= op;
15393
      // op: imm
15394
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15395
0
      op &= UINT64_C(3);
15396
0
      Value |= op;
15397
0
      break;
15398
0
    }
15399
0
    case AArch64::MOVA_MXI2Z_H_S:
15400
0
    case AArch64::MOVA_MXI2Z_V_S: {
15401
      // op: Rs
15402
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
15403
0
      op &= UINT64_C(3);
15404
0
      op <<= 13;
15405
0
      Value |= op;
15406
      // op: Zn
15407
0
      op = EncodeRegAsMultipleOf<2>(MI, 4, Fixups, STI);
15408
0
      op &= UINT64_C(15);
15409
0
      op <<= 6;
15410
0
      Value |= op;
15411
      // op: ZAd
15412
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15413
0
      op &= UINT64_C(3);
15414
0
      op <<= 1;
15415
0
      Value |= op;
15416
      // op: imm
15417
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15418
0
      op &= UINT64_C(1);
15419
0
      Value |= op;
15420
0
      break;
15421
0
    }
15422
0
    case AArch64::MOVA_MXI2Z_H_D:
15423
0
    case AArch64::MOVA_MXI2Z_V_D: {
15424
      // op: Rs
15425
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
15426
0
      op &= UINT64_C(3);
15427
0
      op <<= 13;
15428
0
      Value |= op;
15429
      // op: Zn
15430
0
      op = EncodeRegAsMultipleOf<2>(MI, 4, Fixups, STI);
15431
0
      op &= UINT64_C(15);
15432
0
      op <<= 6;
15433
0
      Value |= op;
15434
      // op: ZAd
15435
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15436
0
      op &= UINT64_C(7);
15437
0
      Value |= op;
15438
0
      break;
15439
0
    }
15440
0
    case AArch64::MOVA_MXI2Z_H_B:
15441
0
    case AArch64::MOVA_MXI2Z_V_B: {
15442
      // op: Rs
15443
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
15444
0
      op &= UINT64_C(3);
15445
0
      op <<= 13;
15446
0
      Value |= op;
15447
      // op: Zn
15448
0
      op = EncodeRegAsMultipleOf<2>(MI, 4, Fixups, STI);
15449
0
      op &= UINT64_C(15);
15450
0
      op <<= 6;
15451
0
      Value |= op;
15452
      // op: imm
15453
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15454
0
      op &= UINT64_C(7);
15455
0
      Value |= op;
15456
0
      break;
15457
0
    }
15458
0
    case AArch64::MOVA_MXI4Z_H_H:
15459
0
    case AArch64::MOVA_MXI4Z_V_H: {
15460
      // op: Rs
15461
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
15462
0
      op &= UINT64_C(3);
15463
0
      op <<= 13;
15464
0
      Value |= op;
15465
      // op: Zn
15466
0
      op = EncodeRegAsMultipleOf<4>(MI, 4, Fixups, STI);
15467
0
      op &= UINT64_C(7);
15468
0
      op <<= 7;
15469
0
      Value |= op;
15470
      // op: ZAd
15471
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15472
0
      op &= UINT64_C(1);
15473
0
      op <<= 1;
15474
0
      Value |= op;
15475
      // op: imm
15476
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15477
0
      op &= UINT64_C(1);
15478
0
      Value |= op;
15479
0
      break;
15480
0
    }
15481
0
    case AArch64::MOVA_MXI4Z_H_S:
15482
0
    case AArch64::MOVA_MXI4Z_V_S: {
15483
      // op: Rs
15484
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
15485
0
      op &= UINT64_C(3);
15486
0
      op <<= 13;
15487
0
      Value |= op;
15488
      // op: Zn
15489
0
      op = EncodeRegAsMultipleOf<4>(MI, 4, Fixups, STI);
15490
0
      op &= UINT64_C(7);
15491
0
      op <<= 7;
15492
0
      Value |= op;
15493
      // op: ZAd
15494
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15495
0
      op &= UINT64_C(3);
15496
0
      Value |= op;
15497
0
      break;
15498
0
    }
15499
0
    case AArch64::MOVA_MXI4Z_H_D:
15500
0
    case AArch64::MOVA_MXI4Z_V_D: {
15501
      // op: Rs
15502
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
15503
0
      op &= UINT64_C(3);
15504
0
      op <<= 13;
15505
0
      Value |= op;
15506
      // op: Zn
15507
0
      op = EncodeRegAsMultipleOf<4>(MI, 4, Fixups, STI);
15508
0
      op &= UINT64_C(7);
15509
0
      op <<= 7;
15510
0
      Value |= op;
15511
      // op: ZAd
15512
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15513
0
      op &= UINT64_C(7);
15514
0
      Value |= op;
15515
0
      break;
15516
0
    }
15517
0
    case AArch64::MOVA_MXI4Z_H_B:
15518
0
    case AArch64::MOVA_MXI4Z_V_B: {
15519
      // op: Rs
15520
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
15521
0
      op &= UINT64_C(3);
15522
0
      op <<= 13;
15523
0
      Value |= op;
15524
      // op: Zn
15525
0
      op = EncodeRegAsMultipleOf<4>(MI, 4, Fixups, STI);
15526
0
      op &= UINT64_C(7);
15527
0
      op <<= 7;
15528
0
      Value |= op;
15529
      // op: imm
15530
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15531
0
      op &= UINT64_C(3);
15532
0
      Value |= op;
15533
0
      break;
15534
0
    }
15535
0
    case AArch64::MOVAZ_ZMI_H_H:
15536
0
    case AArch64::MOVAZ_ZMI_V_H: {
15537
      // op: Rs
15538
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
15539
0
      op &= UINT64_C(3);
15540
0
      op <<= 13;
15541
0
      Value |= op;
15542
      // op: Zd
15543
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15544
0
      op &= UINT64_C(31);
15545
0
      Value |= op;
15546
      // op: ZAn
15547
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15548
0
      op &= UINT64_C(1);
15549
0
      op <<= 8;
15550
0
      Value |= op;
15551
      // op: imm
15552
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15553
0
      op &= UINT64_C(7);
15554
0
      op <<= 5;
15555
0
      Value |= op;
15556
0
      break;
15557
0
    }
15558
0
    case AArch64::MOVAZ_ZMI_H_Q:
15559
0
    case AArch64::MOVAZ_ZMI_V_Q: {
15560
      // op: Rs
15561
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
15562
0
      op &= UINT64_C(3);
15563
0
      op <<= 13;
15564
0
      Value |= op;
15565
      // op: Zd
15566
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15567
0
      op &= UINT64_C(31);
15568
0
      Value |= op;
15569
      // op: ZAn
15570
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15571
0
      op &= UINT64_C(15);
15572
0
      op <<= 5;
15573
0
      Value |= op;
15574
0
      break;
15575
0
    }
15576
0
    case AArch64::MOVAZ_ZMI_H_S:
15577
0
    case AArch64::MOVAZ_ZMI_V_S: {
15578
      // op: Rs
15579
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
15580
0
      op &= UINT64_C(3);
15581
0
      op <<= 13;
15582
0
      Value |= op;
15583
      // op: Zd
15584
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15585
0
      op &= UINT64_C(31);
15586
0
      Value |= op;
15587
      // op: ZAn
15588
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15589
0
      op &= UINT64_C(3);
15590
0
      op <<= 7;
15591
0
      Value |= op;
15592
      // op: imm
15593
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15594
0
      op &= UINT64_C(3);
15595
0
      op <<= 5;
15596
0
      Value |= op;
15597
0
      break;
15598
0
    }
15599
0
    case AArch64::MOVAZ_ZMI_H_D:
15600
0
    case AArch64::MOVAZ_ZMI_V_D: {
15601
      // op: Rs
15602
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
15603
0
      op &= UINT64_C(3);
15604
0
      op <<= 13;
15605
0
      Value |= op;
15606
      // op: Zd
15607
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15608
0
      op &= UINT64_C(31);
15609
0
      Value |= op;
15610
      // op: ZAn
15611
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15612
0
      op &= UINT64_C(7);
15613
0
      op <<= 6;
15614
0
      Value |= op;
15615
      // op: imm
15616
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15617
0
      op &= UINT64_C(1);
15618
0
      op <<= 5;
15619
0
      Value |= op;
15620
0
      break;
15621
0
    }
15622
0
    case AArch64::MOVAZ_ZMI_H_B:
15623
0
    case AArch64::MOVAZ_ZMI_V_B: {
15624
      // op: Rs
15625
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
15626
0
      op &= UINT64_C(3);
15627
0
      op <<= 13;
15628
0
      Value |= op;
15629
      // op: Zd
15630
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15631
0
      op &= UINT64_C(31);
15632
0
      Value |= op;
15633
      // op: imm
15634
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15635
0
      op &= UINT64_C(15);
15636
0
      op <<= 5;
15637
0
      Value |= op;
15638
0
      break;
15639
0
    }
15640
0
    case AArch64::MOVA_VG2_MXI2Z: {
15641
      // op: Rs
15642
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
15643
0
      op &= UINT64_C(3);
15644
0
      op <<= 13;
15645
0
      Value |= op;
15646
      // op: imm
15647
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15648
0
      op &= UINT64_C(7);
15649
0
      Value |= op;
15650
      // op: Zn
15651
0
      op = EncodeRegAsMultipleOf<2>(MI, 4, Fixups, STI);
15652
0
      op &= UINT64_C(15);
15653
0
      op <<= 6;
15654
0
      Value |= op;
15655
0
      break;
15656
0
    }
15657
0
    case AArch64::MOVA_VG4_MXI4Z: {
15658
      // op: Rs
15659
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
15660
0
      op &= UINT64_C(3);
15661
0
      op <<= 13;
15662
0
      Value |= op;
15663
      // op: imm
15664
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15665
0
      op &= UINT64_C(7);
15666
0
      Value |= op;
15667
      // op: Zn
15668
0
      op = EncodeRegAsMultipleOf<4>(MI, 4, Fixups, STI);
15669
0
      op &= UINT64_C(7);
15670
0
      op <<= 7;
15671
0
      Value |= op;
15672
0
      break;
15673
0
    }
15674
0
    case AArch64::MOVA_VG2_2ZMXI: {
15675
      // op: Rs
15676
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
15677
0
      op &= UINT64_C(3);
15678
0
      op <<= 13;
15679
0
      Value |= op;
15680
      // op: imm
15681
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15682
0
      op &= UINT64_C(7);
15683
0
      op <<= 5;
15684
0
      Value |= op;
15685
      // op: Zd
15686
0
      op = EncodeRegAsMultipleOf<2>(MI, 0, Fixups, STI);
15687
0
      op &= UINT64_C(15);
15688
0
      op <<= 1;
15689
0
      Value |= op;
15690
0
      break;
15691
0
    }
15692
0
    case AArch64::MOVA_VG4_4ZMXI: {
15693
      // op: Rs
15694
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
15695
0
      op &= UINT64_C(3);
15696
0
      op <<= 13;
15697
0
      Value |= op;
15698
      // op: imm
15699
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15700
0
      op &= UINT64_C(7);
15701
0
      op <<= 5;
15702
0
      Value |= op;
15703
      // op: Zd
15704
0
      op = EncodeRegAsMultipleOf<4>(MI, 0, Fixups, STI);
15705
0
      op &= UINT64_C(7);
15706
0
      op <<= 2;
15707
0
      Value |= op;
15708
0
      break;
15709
0
    }
15710
0
    case AArch64::MOVAZ_VG2_2ZM: {
15711
      // op: Rs
15712
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 3, Fixups, STI);
15713
0
      op &= UINT64_C(3);
15714
0
      op <<= 13;
15715
0
      Value |= op;
15716
      // op: imm
15717
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15718
0
      op &= UINT64_C(7);
15719
0
      op <<= 5;
15720
0
      Value |= op;
15721
      // op: Zd
15722
0
      op = EncodeRegAsMultipleOf<2>(MI, 0, Fixups, STI);
15723
0
      op &= UINT64_C(15);
15724
0
      op <<= 1;
15725
0
      Value |= op;
15726
0
      break;
15727
0
    }
15728
0
    case AArch64::MOVAZ_VG4_4ZM: {
15729
      // op: Rs
15730
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 3, Fixups, STI);
15731
0
      op &= UINT64_C(3);
15732
0
      op <<= 13;
15733
0
      Value |= op;
15734
      // op: imm
15735
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15736
0
      op &= UINT64_C(7);
15737
0
      op <<= 5;
15738
0
      Value |= op;
15739
      // op: Zd
15740
0
      op = EncodeRegAsMultipleOf<4>(MI, 0, Fixups, STI);
15741
0
      op &= UINT64_C(7);
15742
0
      op <<= 2;
15743
0
      Value |= op;
15744
0
      break;
15745
0
    }
15746
0
    case AArch64::LDADDAB:
15747
0
    case AArch64::LDADDAH:
15748
0
    case AArch64::LDADDALB:
15749
0
    case AArch64::LDADDALH:
15750
0
    case AArch64::LDADDALW:
15751
0
    case AArch64::LDADDALX:
15752
0
    case AArch64::LDADDAW:
15753
0
    case AArch64::LDADDAX:
15754
0
    case AArch64::LDADDB:
15755
0
    case AArch64::LDADDH:
15756
0
    case AArch64::LDADDLB:
15757
0
    case AArch64::LDADDLH:
15758
0
    case AArch64::LDADDLW:
15759
0
    case AArch64::LDADDLX:
15760
0
    case AArch64::LDADDW:
15761
0
    case AArch64::LDADDX:
15762
0
    case AArch64::LDCLRAB:
15763
0
    case AArch64::LDCLRAH:
15764
0
    case AArch64::LDCLRALB:
15765
0
    case AArch64::LDCLRALH:
15766
0
    case AArch64::LDCLRALW:
15767
0
    case AArch64::LDCLRALX:
15768
0
    case AArch64::LDCLRAW:
15769
0
    case AArch64::LDCLRAX:
15770
0
    case AArch64::LDCLRB:
15771
0
    case AArch64::LDCLRH:
15772
0
    case AArch64::LDCLRLB:
15773
0
    case AArch64::LDCLRLH:
15774
0
    case AArch64::LDCLRLW:
15775
0
    case AArch64::LDCLRLX:
15776
0
    case AArch64::LDCLRW:
15777
0
    case AArch64::LDCLRX:
15778
0
    case AArch64::LDEORAB:
15779
0
    case AArch64::LDEORAH:
15780
0
    case AArch64::LDEORALB:
15781
0
    case AArch64::LDEORALH:
15782
0
    case AArch64::LDEORALW:
15783
0
    case AArch64::LDEORALX:
15784
0
    case AArch64::LDEORAW:
15785
0
    case AArch64::LDEORAX:
15786
0
    case AArch64::LDEORB:
15787
0
    case AArch64::LDEORH:
15788
0
    case AArch64::LDEORLB:
15789
0
    case AArch64::LDEORLH:
15790
0
    case AArch64::LDEORLW:
15791
0
    case AArch64::LDEORLX:
15792
0
    case AArch64::LDEORW:
15793
0
    case AArch64::LDEORX:
15794
0
    case AArch64::LDSETAB:
15795
0
    case AArch64::LDSETAH:
15796
0
    case AArch64::LDSETALB:
15797
0
    case AArch64::LDSETALH:
15798
0
    case AArch64::LDSETALW:
15799
0
    case AArch64::LDSETALX:
15800
0
    case AArch64::LDSETAW:
15801
0
    case AArch64::LDSETAX:
15802
0
    case AArch64::LDSETB:
15803
0
    case AArch64::LDSETH:
15804
0
    case AArch64::LDSETLB:
15805
0
    case AArch64::LDSETLH:
15806
0
    case AArch64::LDSETLW:
15807
0
    case AArch64::LDSETLX:
15808
0
    case AArch64::LDSETW:
15809
0
    case AArch64::LDSETX:
15810
0
    case AArch64::LDSMAXAB:
15811
0
    case AArch64::LDSMAXAH:
15812
0
    case AArch64::LDSMAXALB:
15813
0
    case AArch64::LDSMAXALH:
15814
0
    case AArch64::LDSMAXALW:
15815
0
    case AArch64::LDSMAXALX:
15816
0
    case AArch64::LDSMAXAW:
15817
0
    case AArch64::LDSMAXAX:
15818
0
    case AArch64::LDSMAXB:
15819
0
    case AArch64::LDSMAXH:
15820
0
    case AArch64::LDSMAXLB:
15821
0
    case AArch64::LDSMAXLH:
15822
0
    case AArch64::LDSMAXLW:
15823
0
    case AArch64::LDSMAXLX:
15824
0
    case AArch64::LDSMAXW:
15825
0
    case AArch64::LDSMAXX:
15826
0
    case AArch64::LDSMINAB:
15827
0
    case AArch64::LDSMINAH:
15828
0
    case AArch64::LDSMINALB:
15829
0
    case AArch64::LDSMINALH:
15830
0
    case AArch64::LDSMINALW:
15831
0
    case AArch64::LDSMINALX:
15832
0
    case AArch64::LDSMINAW:
15833
0
    case AArch64::LDSMINAX:
15834
0
    case AArch64::LDSMINB:
15835
0
    case AArch64::LDSMINH:
15836
0
    case AArch64::LDSMINLB:
15837
0
    case AArch64::LDSMINLH:
15838
0
    case AArch64::LDSMINLW:
15839
0
    case AArch64::LDSMINLX:
15840
0
    case AArch64::LDSMINW:
15841
0
    case AArch64::LDSMINX:
15842
0
    case AArch64::LDUMAXAB:
15843
0
    case AArch64::LDUMAXAH:
15844
0
    case AArch64::LDUMAXALB:
15845
0
    case AArch64::LDUMAXALH:
15846
0
    case AArch64::LDUMAXALW:
15847
0
    case AArch64::LDUMAXALX:
15848
0
    case AArch64::LDUMAXAW:
15849
0
    case AArch64::LDUMAXAX:
15850
0
    case AArch64::LDUMAXB:
15851
0
    case AArch64::LDUMAXH:
15852
0
    case AArch64::LDUMAXLB:
15853
0
    case AArch64::LDUMAXLH:
15854
0
    case AArch64::LDUMAXLW:
15855
0
    case AArch64::LDUMAXLX:
15856
0
    case AArch64::LDUMAXW:
15857
0
    case AArch64::LDUMAXX:
15858
0
    case AArch64::LDUMINAB:
15859
0
    case AArch64::LDUMINAH:
15860
0
    case AArch64::LDUMINALB:
15861
0
    case AArch64::LDUMINALH:
15862
0
    case AArch64::LDUMINALW:
15863
0
    case AArch64::LDUMINALX:
15864
0
    case AArch64::LDUMINAW:
15865
0
    case AArch64::LDUMINAX:
15866
0
    case AArch64::LDUMINB:
15867
0
    case AArch64::LDUMINH:
15868
0
    case AArch64::LDUMINLB:
15869
0
    case AArch64::LDUMINLH:
15870
0
    case AArch64::LDUMINLW:
15871
0
    case AArch64::LDUMINLX:
15872
0
    case AArch64::LDUMINW:
15873
0
    case AArch64::LDUMINX:
15874
0
    case AArch64::RCWCLR:
15875
0
    case AArch64::RCWCLRA:
15876
0
    case AArch64::RCWCLRAL:
15877
0
    case AArch64::RCWCLRL:
15878
0
    case AArch64::RCWCLRS:
15879
0
    case AArch64::RCWCLRSA:
15880
0
    case AArch64::RCWCLRSAL:
15881
0
    case AArch64::RCWCLRSL:
15882
0
    case AArch64::RCWSET:
15883
0
    case AArch64::RCWSETA:
15884
0
    case AArch64::RCWSETAL:
15885
0
    case AArch64::RCWSETL:
15886
0
    case AArch64::RCWSETS:
15887
0
    case AArch64::RCWSETSA:
15888
0
    case AArch64::RCWSETSAL:
15889
0
    case AArch64::RCWSETSL:
15890
0
    case AArch64::RCWSWP:
15891
0
    case AArch64::RCWSWPA:
15892
0
    case AArch64::RCWSWPAL:
15893
0
    case AArch64::RCWSWPL:
15894
0
    case AArch64::RCWSWPS:
15895
0
    case AArch64::RCWSWPSA:
15896
0
    case AArch64::RCWSWPSAL:
15897
0
    case AArch64::RCWSWPSL:
15898
0
    case AArch64::SWPAB:
15899
0
    case AArch64::SWPAH:
15900
0
    case AArch64::SWPALB:
15901
0
    case AArch64::SWPALH:
15902
0
    case AArch64::SWPALW:
15903
0
    case AArch64::SWPALX:
15904
0
    case AArch64::SWPAW:
15905
0
    case AArch64::SWPAX:
15906
0
    case AArch64::SWPB:
15907
0
    case AArch64::SWPH:
15908
0
    case AArch64::SWPLB:
15909
0
    case AArch64::SWPLH:
15910
0
    case AArch64::SWPLW:
15911
0
    case AArch64::SWPLX:
15912
0
    case AArch64::SWPW:
15913
0
    case AArch64::SWPX: {
15914
      // op: Rs
15915
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15916
0
      op &= UINT64_C(31);
15917
0
      op <<= 16;
15918
0
      Value |= op;
15919
      // op: Rn
15920
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15921
0
      op &= UINT64_C(31);
15922
0
      op <<= 5;
15923
0
      Value |= op;
15924
      // op: Rt
15925
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15926
0
      op &= UINT64_C(31);
15927
0
      Value |= op;
15928
0
      break;
15929
0
    }
15930
0
    case AArch64::CASAB:
15931
0
    case AArch64::CASAH:
15932
0
    case AArch64::CASALB:
15933
0
    case AArch64::CASALH:
15934
0
    case AArch64::CASALW:
15935
0
    case AArch64::CASALX:
15936
0
    case AArch64::CASAW:
15937
0
    case AArch64::CASAX:
15938
0
    case AArch64::CASB:
15939
0
    case AArch64::CASH:
15940
0
    case AArch64::CASLB:
15941
0
    case AArch64::CASLH:
15942
0
    case AArch64::CASLW:
15943
0
    case AArch64::CASLX:
15944
0
    case AArch64::CASPALW:
15945
0
    case AArch64::CASPALX:
15946
0
    case AArch64::CASPAW:
15947
0
    case AArch64::CASPAX:
15948
0
    case AArch64::CASPLW:
15949
0
    case AArch64::CASPLX:
15950
0
    case AArch64::CASPW:
15951
0
    case AArch64::CASPX:
15952
0
    case AArch64::CASW:
15953
0
    case AArch64::CASX:
15954
0
    case AArch64::RCWCAS:
15955
0
    case AArch64::RCWCASA:
15956
0
    case AArch64::RCWCASAL:
15957
0
    case AArch64::RCWCASL:
15958
0
    case AArch64::RCWCASP:
15959
0
    case AArch64::RCWCASPA:
15960
0
    case AArch64::RCWCASPAL:
15961
0
    case AArch64::RCWCASPL:
15962
0
    case AArch64::RCWSCAS:
15963
0
    case AArch64::RCWSCASA:
15964
0
    case AArch64::RCWSCASAL:
15965
0
    case AArch64::RCWSCASL:
15966
0
    case AArch64::RCWSCASP:
15967
0
    case AArch64::RCWSCASPA:
15968
0
    case AArch64::RCWSCASPAL:
15969
0
    case AArch64::RCWSCASPL: {
15970
      // op: Rs
15971
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15972
0
      op &= UINT64_C(31);
15973
0
      op <<= 16;
15974
0
      Value |= op;
15975
      // op: Rn
15976
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15977
0
      op &= UINT64_C(31);
15978
0
      op <<= 5;
15979
0
      Value |= op;
15980
      // op: Rt
15981
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15982
0
      op &= UINT64_C(31);
15983
0
      Value |= op;
15984
0
      break;
15985
0
    }
15986
0
    case AArch64::RPRFM: {
15987
      // op: Rt
15988
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15989
0
      Value |= (op & UINT64_C(32)) << 10;
15990
0
      Value |= (op & UINT64_C(24)) << 9;
15991
0
      Value |= (op & UINT64_C(7));
15992
      // op: Rn
15993
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15994
0
      op &= UINT64_C(31);
15995
0
      op <<= 5;
15996
0
      Value |= op;
15997
      // op: Rm
15998
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15999
0
      op &= UINT64_C(31);
16000
0
      op <<= 16;
16001
0
      Value |= op;
16002
0
      break;
16003
0
    }
16004
0
    case AArch64::GCSPOPM:
16005
0
    case AArch64::GCSPUSHM:
16006
0
    case AArch64::GCSSS1:
16007
0
    case AArch64::GCSSS2:
16008
0
    case AArch64::TRCIT:
16009
0
    case AArch64::TSTART:
16010
0
    case AArch64::TTEST:
16011
0
    case AArch64::WFET:
16012
0
    case AArch64::WFIT: {
16013
      // op: Rt
16014
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16015
0
      op &= UINT64_C(31);
16016
0
      Value |= op;
16017
0
      break;
16018
0
    }
16019
0
    case AArch64::GCSSTR:
16020
0
    case AArch64::GCSSTTR:
16021
0
    case AArch64::LD64B:
16022
0
    case AArch64::ST64B: {
16023
      // op: Rt
16024
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16025
0
      op &= UINT64_C(31);
16026
0
      Value |= op;
16027
      // op: Rn
16028
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16029
0
      op &= UINT64_C(31);
16030
0
      op <<= 5;
16031
0
      Value |= op;
16032
0
      break;
16033
0
    }
16034
0
    case AArch64::LDRBBroW:
16035
0
    case AArch64::LDRBBroX:
16036
0
    case AArch64::LDRBroW:
16037
0
    case AArch64::LDRBroX:
16038
0
    case AArch64::LDRDroW:
16039
0
    case AArch64::LDRDroX:
16040
0
    case AArch64::LDRHHroW:
16041
0
    case AArch64::LDRHHroX:
16042
0
    case AArch64::LDRHroW:
16043
0
    case AArch64::LDRHroX:
16044
0
    case AArch64::LDRQroW:
16045
0
    case AArch64::LDRQroX:
16046
0
    case AArch64::LDRSBWroW:
16047
0
    case AArch64::LDRSBWroX:
16048
0
    case AArch64::LDRSBXroW:
16049
0
    case AArch64::LDRSBXroX:
16050
0
    case AArch64::LDRSHWroW:
16051
0
    case AArch64::LDRSHWroX:
16052
0
    case AArch64::LDRSHXroW:
16053
0
    case AArch64::LDRSHXroX:
16054
0
    case AArch64::LDRSWroW:
16055
0
    case AArch64::LDRSWroX:
16056
0
    case AArch64::LDRSroW:
16057
0
    case AArch64::LDRSroX:
16058
0
    case AArch64::LDRWroW:
16059
0
    case AArch64::LDRWroX:
16060
0
    case AArch64::LDRXroW:
16061
0
    case AArch64::LDRXroX:
16062
0
    case AArch64::PRFMroW:
16063
0
    case AArch64::PRFMroX:
16064
0
    case AArch64::STRBBroW:
16065
0
    case AArch64::STRBBroX:
16066
0
    case AArch64::STRBroW:
16067
0
    case AArch64::STRBroX:
16068
0
    case AArch64::STRDroW:
16069
0
    case AArch64::STRDroX:
16070
0
    case AArch64::STRHHroW:
16071
0
    case AArch64::STRHHroX:
16072
0
    case AArch64::STRHroW:
16073
0
    case AArch64::STRHroX:
16074
0
    case AArch64::STRQroW:
16075
0
    case AArch64::STRQroX:
16076
0
    case AArch64::STRSroW:
16077
0
    case AArch64::STRSroX:
16078
0
    case AArch64::STRWroW:
16079
0
    case AArch64::STRWroX:
16080
0
    case AArch64::STRXroW:
16081
0
    case AArch64::STRXroX: {
16082
      // op: Rt
16083
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16084
0
      op &= UINT64_C(31);
16085
0
      Value |= op;
16086
      // op: Rn
16087
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16088
0
      op &= UINT64_C(31);
16089
0
      op <<= 5;
16090
0
      Value |= op;
16091
      // op: Rm
16092
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16093
0
      op &= UINT64_C(31);
16094
0
      op <<= 16;
16095
0
      Value |= op;
16096
      // op: extend
16097
0
      op = getMemExtendOpValue(MI, 3, Fixups, STI);
16098
0
      Value |= (op & UINT64_C(2)) << 14;
16099
0
      Value |= (op & UINT64_C(1)) << 12;
16100
0
      break;
16101
0
    }
16102
0
    case AArch64::LDRQui:
16103
0
    case AArch64::STRQui: {
16104
      // op: Rt
16105
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16106
0
      op &= UINT64_C(31);
16107
0
      Value |= op;
16108
      // op: Rn
16109
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16110
0
      op &= UINT64_C(31);
16111
0
      op <<= 5;
16112
0
      Value |= op;
16113
      // op: offset
16114
0
      op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale16>(MI, 2, Fixups, STI);
16115
0
      op &= UINT64_C(4095);
16116
0
      op <<= 10;
16117
0
      Value |= op;
16118
0
      break;
16119
0
    }
16120
0
    case AArch64::LDRBBui:
16121
0
    case AArch64::LDRBui:
16122
0
    case AArch64::LDRSBWui:
16123
0
    case AArch64::LDRSBXui:
16124
0
    case AArch64::STRBBui:
16125
0
    case AArch64::STRBui: {
16126
      // op: Rt
16127
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16128
0
      op &= UINT64_C(31);
16129
0
      Value |= op;
16130
      // op: Rn
16131
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16132
0
      op &= UINT64_C(31);
16133
0
      op <<= 5;
16134
0
      Value |= op;
16135
      // op: offset
16136
0
      op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale1>(MI, 2, Fixups, STI);
16137
0
      op &= UINT64_C(4095);
16138
0
      op <<= 10;
16139
0
      Value |= op;
16140
0
      break;
16141
0
    }
16142
0
    case AArch64::LDRHHui:
16143
0
    case AArch64::LDRHui:
16144
0
    case AArch64::LDRSHWui:
16145
0
    case AArch64::LDRSHXui:
16146
0
    case AArch64::STRHHui:
16147
0
    case AArch64::STRHui: {
16148
      // op: Rt
16149
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16150
0
      op &= UINT64_C(31);
16151
0
      Value |= op;
16152
      // op: Rn
16153
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16154
0
      op &= UINT64_C(31);
16155
0
      op <<= 5;
16156
0
      Value |= op;
16157
      // op: offset
16158
0
      op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale2>(MI, 2, Fixups, STI);
16159
0
      op &= UINT64_C(4095);
16160
0
      op <<= 10;
16161
0
      Value |= op;
16162
0
      break;
16163
0
    }
16164
0
    case AArch64::LDRSWui:
16165
0
    case AArch64::LDRSui:
16166
0
    case AArch64::LDRWui:
16167
0
    case AArch64::STRSui:
16168
0
    case AArch64::STRWui: {
16169
      // op: Rt
16170
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16171
0
      op &= UINT64_C(31);
16172
0
      Value |= op;
16173
      // op: Rn
16174
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16175
0
      op &= UINT64_C(31);
16176
0
      op <<= 5;
16177
0
      Value |= op;
16178
      // op: offset
16179
0
      op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale4>(MI, 2, Fixups, STI);
16180
0
      op &= UINT64_C(4095);
16181
0
      op <<= 10;
16182
0
      Value |= op;
16183
0
      break;
16184
0
    }
16185
0
    case AArch64::LDRDui:
16186
0
    case AArch64::LDRXui:
16187
0
    case AArch64::PRFMui:
16188
0
    case AArch64::STRDui:
16189
0
    case AArch64::STRXui: {
16190
      // op: Rt
16191
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16192
0
      op &= UINT64_C(31);
16193
0
      Value |= op;
16194
      // op: Rn
16195
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16196
0
      op &= UINT64_C(31);
16197
0
      op <<= 5;
16198
0
      Value |= op;
16199
      // op: offset
16200
0
      op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale8>(MI, 2, Fixups, STI);
16201
0
      op &= UINT64_C(4095);
16202
0
      op <<= 10;
16203
0
      Value |= op;
16204
0
      break;
16205
0
    }
16206
0
    case AArch64::LDAPURBi:
16207
0
    case AArch64::LDAPURHi:
16208
0
    case AArch64::LDAPURSBWi:
16209
0
    case AArch64::LDAPURSBXi:
16210
0
    case AArch64::LDAPURSHWi:
16211
0
    case AArch64::LDAPURSHXi:
16212
0
    case AArch64::LDAPURSWi:
16213
0
    case AArch64::LDAPURXi:
16214
0
    case AArch64::LDAPURi:
16215
0
    case AArch64::LDTRBi:
16216
0
    case AArch64::LDTRHi:
16217
0
    case AArch64::LDTRSBWi:
16218
0
    case AArch64::LDTRSBXi:
16219
0
    case AArch64::LDTRSHWi:
16220
0
    case AArch64::LDTRSHXi:
16221
0
    case AArch64::LDTRSWi:
16222
0
    case AArch64::LDTRWi:
16223
0
    case AArch64::LDTRXi:
16224
0
    case AArch64::LDURBBi:
16225
0
    case AArch64::LDURBi:
16226
0
    case AArch64::LDURDi:
16227
0
    case AArch64::LDURHHi:
16228
0
    case AArch64::LDURHi:
16229
0
    case AArch64::LDURQi:
16230
0
    case AArch64::LDURSBWi:
16231
0
    case AArch64::LDURSBXi:
16232
0
    case AArch64::LDURSHWi:
16233
0
    case AArch64::LDURSHXi:
16234
0
    case AArch64::LDURSWi:
16235
0
    case AArch64::LDURSi:
16236
0
    case AArch64::LDURWi:
16237
0
    case AArch64::LDURXi:
16238
0
    case AArch64::PRFUMi:
16239
0
    case AArch64::STLURBi:
16240
0
    case AArch64::STLURHi:
16241
0
    case AArch64::STLURWi:
16242
0
    case AArch64::STLURXi:
16243
0
    case AArch64::STTRBi:
16244
0
    case AArch64::STTRHi:
16245
0
    case AArch64::STTRWi:
16246
0
    case AArch64::STTRXi:
16247
0
    case AArch64::STURBBi:
16248
0
    case AArch64::STURBi:
16249
0
    case AArch64::STURDi:
16250
0
    case AArch64::STURHHi:
16251
0
    case AArch64::STURHi:
16252
0
    case AArch64::STURQi:
16253
0
    case AArch64::STURSi:
16254
0
    case AArch64::STURWi:
16255
0
    case AArch64::STURXi: {
16256
      // op: Rt
16257
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16258
0
      op &= UINT64_C(31);
16259
0
      Value |= op;
16260
      // op: Rn
16261
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16262
0
      op &= UINT64_C(31);
16263
0
      op <<= 5;
16264
0
      Value |= op;
16265
      // op: offset
16266
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16267
0
      op &= UINT64_C(511);
16268
0
      op <<= 12;
16269
0
      Value |= op;
16270
0
      break;
16271
0
    }
16272
0
    case AArch64::LDAPURbi:
16273
0
    case AArch64::LDAPURdi:
16274
0
    case AArch64::LDAPURhi:
16275
0
    case AArch64::LDAPURqi:
16276
0
    case AArch64::LDAPURsi:
16277
0
    case AArch64::STLURbi:
16278
0
    case AArch64::STLURdi:
16279
0
    case AArch64::STLURhi:
16280
0
    case AArch64::STLURqi:
16281
0
    case AArch64::STLURsi: {
16282
      // op: Rt
16283
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16284
0
      op &= UINT64_C(31);
16285
0
      Value |= op;
16286
      // op: Rn
16287
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16288
0
      op &= UINT64_C(31);
16289
0
      op <<= 5;
16290
0
      Value |= op;
16291
      // op: simm
16292
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16293
0
      op &= UINT64_C(511);
16294
0
      op <<= 12;
16295
0
      Value |= op;
16296
0
      break;
16297
0
    }
16298
0
    case AArch64::LDARB:
16299
0
    case AArch64::LDARH:
16300
0
    case AArch64::LDARW:
16301
0
    case AArch64::LDARX:
16302
0
    case AArch64::LDAXRB:
16303
0
    case AArch64::LDAXRH:
16304
0
    case AArch64::LDAXRW:
16305
0
    case AArch64::LDAXRX:
16306
0
    case AArch64::LDLARB:
16307
0
    case AArch64::LDLARH:
16308
0
    case AArch64::LDLARW:
16309
0
    case AArch64::LDLARX:
16310
0
    case AArch64::LDXRB:
16311
0
    case AArch64::LDXRH:
16312
0
    case AArch64::LDXRW:
16313
0
    case AArch64::LDXRX:
16314
0
    case AArch64::STLLRB:
16315
0
    case AArch64::STLLRH:
16316
0
    case AArch64::STLLRW:
16317
0
    case AArch64::STLLRX:
16318
0
    case AArch64::STLRB:
16319
0
    case AArch64::STLRH:
16320
0
    case AArch64::STLRW:
16321
0
    case AArch64::STLRX: {
16322
      // op: Rt
16323
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16324
0
      op &= UINT64_C(31);
16325
0
      Value |= op;
16326
      // op: Rn
16327
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16328
0
      op &= UINT64_C(31);
16329
0
      op <<= 5;
16330
0
      Value |= op;
16331
0
      Value = fixLoadStoreExclusive<0,0>(MI, Value, STI);
16332
0
      break;
16333
0
    }
16334
0
    case AArch64::LDIAPPW:
16335
0
    case AArch64::LDIAPPX:
16336
0
    case AArch64::STILPW:
16337
0
    case AArch64::STILPX: {
16338
      // op: Rt
16339
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16340
0
      op &= UINT64_C(31);
16341
0
      Value |= op;
16342
      // op: Rn
16343
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16344
0
      op &= UINT64_C(31);
16345
0
      op <<= 5;
16346
0
      Value |= op;
16347
      // op: Rt2
16348
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16349
0
      op &= UINT64_C(31);
16350
0
      op <<= 16;
16351
0
      Value |= op;
16352
0
      break;
16353
0
    }
16354
0
    case AArch64::LDNPDi:
16355
0
    case AArch64::LDNPQi:
16356
0
    case AArch64::LDNPSi:
16357
0
    case AArch64::LDNPWi:
16358
0
    case AArch64::LDNPXi:
16359
0
    case AArch64::LDPDi:
16360
0
    case AArch64::LDPQi:
16361
0
    case AArch64::LDPSWi:
16362
0
    case AArch64::LDPSi:
16363
0
    case AArch64::LDPWi:
16364
0
    case AArch64::LDPXi:
16365
0
    case AArch64::STGPi:
16366
0
    case AArch64::STNPDi:
16367
0
    case AArch64::STNPQi:
16368
0
    case AArch64::STNPSi:
16369
0
    case AArch64::STNPWi:
16370
0
    case AArch64::STNPXi:
16371
0
    case AArch64::STPDi:
16372
0
    case AArch64::STPQi:
16373
0
    case AArch64::STPSi:
16374
0
    case AArch64::STPWi:
16375
0
    case AArch64::STPXi: {
16376
      // op: Rt
16377
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16378
0
      op &= UINT64_C(31);
16379
0
      Value |= op;
16380
      // op: Rt2
16381
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16382
0
      op &= UINT64_C(31);
16383
0
      op <<= 10;
16384
0
      Value |= op;
16385
      // op: Rn
16386
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16387
0
      op &= UINT64_C(31);
16388
0
      op <<= 5;
16389
0
      Value |= op;
16390
      // op: offset
16391
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16392
0
      op &= UINT64_C(127);
16393
0
      op <<= 15;
16394
0
      Value |= op;
16395
0
      break;
16396
0
    }
16397
0
    case AArch64::LDAXPW:
16398
0
    case AArch64::LDAXPX:
16399
0
    case AArch64::LDXPW:
16400
0
    case AArch64::LDXPX: {
16401
      // op: Rt
16402
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16403
0
      op &= UINT64_C(31);
16404
0
      Value |= op;
16405
      // op: Rt2
16406
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16407
0
      op &= UINT64_C(31);
16408
0
      op <<= 10;
16409
0
      Value |= op;
16410
      // op: Rn
16411
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16412
0
      op &= UINT64_C(31);
16413
0
      op <<= 5;
16414
0
      Value |= op;
16415
0
      Value = fixLoadStoreExclusive<0,1>(MI, Value, STI);
16416
0
      break;
16417
0
    }
16418
0
    case AArch64::TBNZW:
16419
0
    case AArch64::TBNZX:
16420
0
    case AArch64::TBZW:
16421
0
    case AArch64::TBZX: {
16422
      // op: Rt
16423
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16424
0
      op &= UINT64_C(31);
16425
0
      Value |= op;
16426
      // op: bit_off
16427
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16428
0
      op &= UINT64_C(31);
16429
0
      op <<= 19;
16430
0
      Value |= op;
16431
      // op: target
16432
0
      op = getTestBranchTargetOpValue(MI, 2, Fixups, STI);
16433
0
      op &= UINT64_C(16383);
16434
0
      op <<= 5;
16435
0
      Value |= op;
16436
0
      break;
16437
0
    }
16438
0
    case AArch64::LDRDl:
16439
0
    case AArch64::LDRQl:
16440
0
    case AArch64::LDRSWl:
16441
0
    case AArch64::LDRSl:
16442
0
    case AArch64::LDRWl:
16443
0
    case AArch64::LDRXl:
16444
0
    case AArch64::PRFMl: {
16445
      // op: Rt
16446
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16447
0
      op &= UINT64_C(31);
16448
0
      Value |= op;
16449
      // op: label
16450
0
      op = getLoadLiteralOpValue(MI, 1, Fixups, STI);
16451
0
      op &= UINT64_C(524287);
16452
0
      op <<= 5;
16453
0
      Value |= op;
16454
0
      break;
16455
0
    }
16456
0
    case AArch64::SYSLxt: {
16457
      // op: Rt
16458
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16459
0
      op &= UINT64_C(31);
16460
0
      Value |= op;
16461
      // op: op1
16462
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16463
0
      op &= UINT64_C(7);
16464
0
      op <<= 16;
16465
0
      Value |= op;
16466
      // op: Cn
16467
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16468
0
      op &= UINT64_C(15);
16469
0
      op <<= 12;
16470
0
      Value |= op;
16471
      // op: Cm
16472
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16473
0
      op &= UINT64_C(15);
16474
0
      op <<= 8;
16475
0
      Value |= op;
16476
      // op: op2
16477
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
16478
0
      op &= UINT64_C(7);
16479
0
      op <<= 5;
16480
0
      Value |= op;
16481
0
      break;
16482
0
    }
16483
0
    case AArch64::MRRS:
16484
0
    case AArch64::MRS: {
16485
      // op: Rt
16486
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16487
0
      op &= UINT64_C(31);
16488
0
      Value |= op;
16489
      // op: systemreg
16490
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16491
0
      op &= UINT64_C(65535);
16492
0
      op <<= 5;
16493
0
      Value |= op;
16494
0
      break;
16495
0
    }
16496
0
    case AArch64::CBNZW:
16497
0
    case AArch64::CBNZX:
16498
0
    case AArch64::CBZW:
16499
0
    case AArch64::CBZX: {
16500
      // op: Rt
16501
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16502
0
      op &= UINT64_C(31);
16503
0
      Value |= op;
16504
      // op: target
16505
0
      op = getCondBranchTargetOpValue(MI, 1, Fixups, STI);
16506
0
      op &= UINT64_C(524287);
16507
0
      op <<= 5;
16508
0
      Value |= op;
16509
0
      break;
16510
0
    }
16511
0
    case AArch64::LDAPRWpre:
16512
0
    case AArch64::LDAPRXpre:
16513
0
    case AArch64::STLRWpre:
16514
0
    case AArch64::STLRXpre: {
16515
      // op: Rt
16516
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16517
0
      op &= UINT64_C(31);
16518
0
      Value |= op;
16519
      // op: Rn
16520
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16521
0
      op &= UINT64_C(31);
16522
0
      op <<= 5;
16523
0
      Value |= op;
16524
0
      break;
16525
0
    }
16526
0
    case AArch64::ST64BV:
16527
0
    case AArch64::ST64BV0: {
16528
      // op: Rt
16529
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16530
0
      op &= UINT64_C(31);
16531
0
      Value |= op;
16532
      // op: Rn
16533
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16534
0
      op &= UINT64_C(31);
16535
0
      op <<= 5;
16536
0
      Value |= op;
16537
      // op: Rs
16538
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16539
0
      op &= UINT64_C(31);
16540
0
      op <<= 16;
16541
0
      Value |= op;
16542
0
      break;
16543
0
    }
16544
0
    case AArch64::LDRBBpost:
16545
0
    case AArch64::LDRBBpre:
16546
0
    case AArch64::LDRBpost:
16547
0
    case AArch64::LDRBpre:
16548
0
    case AArch64::LDRDpost:
16549
0
    case AArch64::LDRDpre:
16550
0
    case AArch64::LDRHHpost:
16551
0
    case AArch64::LDRHHpre:
16552
0
    case AArch64::LDRHpost:
16553
0
    case AArch64::LDRHpre:
16554
0
    case AArch64::LDRQpost:
16555
0
    case AArch64::LDRQpre:
16556
0
    case AArch64::LDRSBWpost:
16557
0
    case AArch64::LDRSBWpre:
16558
0
    case AArch64::LDRSBXpost:
16559
0
    case AArch64::LDRSBXpre:
16560
0
    case AArch64::LDRSHWpost:
16561
0
    case AArch64::LDRSHWpre:
16562
0
    case AArch64::LDRSHXpost:
16563
0
    case AArch64::LDRSHXpre:
16564
0
    case AArch64::LDRSWpost:
16565
0
    case AArch64::LDRSWpre:
16566
0
    case AArch64::LDRSpost:
16567
0
    case AArch64::LDRSpre:
16568
0
    case AArch64::LDRWpost:
16569
0
    case AArch64::LDRWpre:
16570
0
    case AArch64::LDRXpost:
16571
0
    case AArch64::LDRXpre:
16572
0
    case AArch64::STRBBpost:
16573
0
    case AArch64::STRBBpre:
16574
0
    case AArch64::STRBpost:
16575
0
    case AArch64::STRBpre:
16576
0
    case AArch64::STRDpost:
16577
0
    case AArch64::STRDpre:
16578
0
    case AArch64::STRHHpost:
16579
0
    case AArch64::STRHHpre:
16580
0
    case AArch64::STRHpost:
16581
0
    case AArch64::STRHpre:
16582
0
    case AArch64::STRQpost:
16583
0
    case AArch64::STRQpre:
16584
0
    case AArch64::STRSpost:
16585
0
    case AArch64::STRSpre:
16586
0
    case AArch64::STRWpost:
16587
0
    case AArch64::STRWpre:
16588
0
    case AArch64::STRXpost:
16589
0
    case AArch64::STRXpre: {
16590
      // op: Rt
16591
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16592
0
      op &= UINT64_C(31);
16593
0
      Value |= op;
16594
      // op: Rn
16595
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16596
0
      op &= UINT64_C(31);
16597
0
      op <<= 5;
16598
0
      Value |= op;
16599
      // op: offset
16600
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16601
0
      op &= UINT64_C(511);
16602
0
      op <<= 12;
16603
0
      Value |= op;
16604
0
      break;
16605
0
    }
16606
0
    case AArch64::LDIAPPWpre:
16607
0
    case AArch64::LDIAPPXpre:
16608
0
    case AArch64::STILPWpre:
16609
0
    case AArch64::STILPXpre: {
16610
      // op: Rt
16611
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16612
0
      op &= UINT64_C(31);
16613
0
      Value |= op;
16614
      // op: Rn
16615
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16616
0
      op &= UINT64_C(31);
16617
0
      op <<= 5;
16618
0
      Value |= op;
16619
      // op: Rt2
16620
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16621
0
      op &= UINT64_C(31);
16622
0
      op <<= 16;
16623
0
      Value |= op;
16624
0
      break;
16625
0
    }
16626
0
    case AArch64::LDPDpost:
16627
0
    case AArch64::LDPDpre:
16628
0
    case AArch64::LDPQpost:
16629
0
    case AArch64::LDPQpre:
16630
0
    case AArch64::LDPSWpost:
16631
0
    case AArch64::LDPSWpre:
16632
0
    case AArch64::LDPSpost:
16633
0
    case AArch64::LDPSpre:
16634
0
    case AArch64::LDPWpost:
16635
0
    case AArch64::LDPWpre:
16636
0
    case AArch64::LDPXpost:
16637
0
    case AArch64::LDPXpre:
16638
0
    case AArch64::STGPpost:
16639
0
    case AArch64::STGPpre:
16640
0
    case AArch64::STPDpost:
16641
0
    case AArch64::STPDpre:
16642
0
    case AArch64::STPQpost:
16643
0
    case AArch64::STPQpre:
16644
0
    case AArch64::STPSpost:
16645
0
    case AArch64::STPSpre:
16646
0
    case AArch64::STPWpost:
16647
0
    case AArch64::STPWpre:
16648
0
    case AArch64::STPXpost:
16649
0
    case AArch64::STPXpre: {
16650
      // op: Rt
16651
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16652
0
      op &= UINT64_C(31);
16653
0
      Value |= op;
16654
      // op: Rt2
16655
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16656
0
      op &= UINT64_C(31);
16657
0
      op <<= 10;
16658
0
      Value |= op;
16659
      // op: Rn
16660
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16661
0
      op &= UINT64_C(31);
16662
0
      op <<= 5;
16663
0
      Value |= op;
16664
      // op: offset
16665
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
16666
0
      op &= UINT64_C(127);
16667
0
      op <<= 15;
16668
0
      Value |= op;
16669
0
      break;
16670
0
    }
16671
0
    case AArch64::MSR:
16672
0
    case AArch64::MSRR: {
16673
      // op: Rt
16674
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16675
0
      op &= UINT64_C(31);
16676
0
      Value |= op;
16677
      // op: systemreg
16678
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16679
0
      op &= UINT64_C(65535);
16680
0
      op <<= 5;
16681
0
      Value |= op;
16682
0
      break;
16683
0
    }
16684
0
    case AArch64::LDCLRP:
16685
0
    case AArch64::LDCLRPA:
16686
0
    case AArch64::LDCLRPAL:
16687
0
    case AArch64::LDCLRPL:
16688
0
    case AArch64::LDSETP:
16689
0
    case AArch64::LDSETPA:
16690
0
    case AArch64::LDSETPAL:
16691
0
    case AArch64::LDSETPL:
16692
0
    case AArch64::SWPP:
16693
0
    case AArch64::SWPPA:
16694
0
    case AArch64::SWPPAL:
16695
0
    case AArch64::SWPPL: {
16696
      // op: Rt
16697
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16698
0
      op &= UINT64_C(31);
16699
0
      Value |= op;
16700
      // op: Rt2
16701
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16702
0
      op &= UINT64_C(31);
16703
0
      op <<= 16;
16704
0
      Value |= op;
16705
      // op: Rn
16706
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
16707
0
      op &= UINT64_C(31);
16708
0
      op <<= 5;
16709
0
      Value |= op;
16710
0
      break;
16711
0
    }
16712
0
    case AArch64::SYSPxt:
16713
0
    case AArch64::SYSxt: {
16714
      // op: Rt
16715
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
16716
0
      op &= UINT64_C(31);
16717
0
      Value |= op;
16718
      // op: op1
16719
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16720
0
      op &= UINT64_C(7);
16721
0
      op <<= 16;
16722
0
      Value |= op;
16723
      // op: Cn
16724
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16725
0
      op &= UINT64_C(15);
16726
0
      op <<= 12;
16727
0
      Value |= op;
16728
      // op: Cm
16729
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16730
0
      op &= UINT64_C(15);
16731
0
      op <<= 8;
16732
0
      Value |= op;
16733
      // op: op2
16734
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16735
0
      op &= UINT64_C(7);
16736
0
      op <<= 5;
16737
0
      Value |= op;
16738
0
      break;
16739
0
    }
16740
0
    case AArch64::RCWCLRP:
16741
0
    case AArch64::RCWCLRPA:
16742
0
    case AArch64::RCWCLRPAL:
16743
0
    case AArch64::RCWCLRPL:
16744
0
    case AArch64::RCWCLRSP:
16745
0
    case AArch64::RCWCLRSPA:
16746
0
    case AArch64::RCWCLRSPAL:
16747
0
    case AArch64::RCWCLRSPL:
16748
0
    case AArch64::RCWSETP:
16749
0
    case AArch64::RCWSETPA:
16750
0
    case AArch64::RCWSETPAL:
16751
0
    case AArch64::RCWSETPL:
16752
0
    case AArch64::RCWSETSP:
16753
0
    case AArch64::RCWSETSPA:
16754
0
    case AArch64::RCWSETSPAL:
16755
0
    case AArch64::RCWSETSPL:
16756
0
    case AArch64::RCWSWPP:
16757
0
    case AArch64::RCWSWPPA:
16758
0
    case AArch64::RCWSWPPAL:
16759
0
    case AArch64::RCWSWPPL:
16760
0
    case AArch64::RCWSWPSP:
16761
0
    case AArch64::RCWSWPSPA:
16762
0
    case AArch64::RCWSWPSPAL:
16763
0
    case AArch64::RCWSWPSPL: {
16764
      // op: Rt2
16765
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16766
0
      op &= UINT64_C(31);
16767
0
      op <<= 16;
16768
0
      Value |= op;
16769
      // op: Rn
16770
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
16771
0
      op &= UINT64_C(31);
16772
0
      op <<= 5;
16773
0
      Value |= op;
16774
      // op: Rt
16775
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16776
0
      op &= UINT64_C(31);
16777
0
      Value |= op;
16778
0
      break;
16779
0
    }
16780
0
    case AArch64::LDR_ZA:
16781
0
    case AArch64::STR_ZA: {
16782
      // op: Rv
16783
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 1, Fixups, STI);
16784
0
      op &= UINT64_C(3);
16785
0
      op <<= 13;
16786
0
      Value |= op;
16787
      // op: Rn
16788
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16789
0
      op &= UINT64_C(31);
16790
0
      op <<= 5;
16791
0
      Value |= op;
16792
      // op: imm4
16793
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16794
0
      op &= UINT64_C(15);
16795
0
      Value |= op;
16796
0
      break;
16797
0
    }
16798
0
    case AArch64::INSERT_MXIPZ_H_H:
16799
0
    case AArch64::INSERT_MXIPZ_V_H: {
16800
      // op: Rv
16801
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
16802
0
      op &= UINT64_C(3);
16803
0
      op <<= 13;
16804
0
      Value |= op;
16805
      // op: Pg
16806
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
16807
0
      op &= UINT64_C(7);
16808
0
      op <<= 10;
16809
0
      Value |= op;
16810
      // op: Zn
16811
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16812
0
      op &= UINT64_C(31);
16813
0
      op <<= 5;
16814
0
      Value |= op;
16815
      // op: ZAd
16816
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16817
0
      op &= UINT64_C(1);
16818
0
      op <<= 3;
16819
0
      Value |= op;
16820
      // op: imm
16821
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16822
0
      op &= UINT64_C(7);
16823
0
      Value |= op;
16824
0
      break;
16825
0
    }
16826
0
    case AArch64::INSERT_MXIPZ_H_Q:
16827
0
    case AArch64::INSERT_MXIPZ_V_Q: {
16828
      // op: Rv
16829
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
16830
0
      op &= UINT64_C(3);
16831
0
      op <<= 13;
16832
0
      Value |= op;
16833
      // op: Pg
16834
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
16835
0
      op &= UINT64_C(7);
16836
0
      op <<= 10;
16837
0
      Value |= op;
16838
      // op: Zn
16839
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16840
0
      op &= UINT64_C(31);
16841
0
      op <<= 5;
16842
0
      Value |= op;
16843
      // op: ZAd
16844
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16845
0
      op &= UINT64_C(15);
16846
0
      Value |= op;
16847
0
      break;
16848
0
    }
16849
0
    case AArch64::INSERT_MXIPZ_H_S:
16850
0
    case AArch64::INSERT_MXIPZ_V_S: {
16851
      // op: Rv
16852
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
16853
0
      op &= UINT64_C(3);
16854
0
      op <<= 13;
16855
0
      Value |= op;
16856
      // op: Pg
16857
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
16858
0
      op &= UINT64_C(7);
16859
0
      op <<= 10;
16860
0
      Value |= op;
16861
      // op: Zn
16862
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16863
0
      op &= UINT64_C(31);
16864
0
      op <<= 5;
16865
0
      Value |= op;
16866
      // op: ZAd
16867
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16868
0
      op &= UINT64_C(3);
16869
0
      op <<= 2;
16870
0
      Value |= op;
16871
      // op: imm
16872
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16873
0
      op &= UINT64_C(3);
16874
0
      Value |= op;
16875
0
      break;
16876
0
    }
16877
0
    case AArch64::INSERT_MXIPZ_H_D:
16878
0
    case AArch64::INSERT_MXIPZ_V_D: {
16879
      // op: Rv
16880
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
16881
0
      op &= UINT64_C(3);
16882
0
      op <<= 13;
16883
0
      Value |= op;
16884
      // op: Pg
16885
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
16886
0
      op &= UINT64_C(7);
16887
0
      op <<= 10;
16888
0
      Value |= op;
16889
      // op: Zn
16890
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16891
0
      op &= UINT64_C(31);
16892
0
      op <<= 5;
16893
0
      Value |= op;
16894
      // op: ZAd
16895
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16896
0
      op &= UINT64_C(7);
16897
0
      op <<= 1;
16898
0
      Value |= op;
16899
      // op: imm
16900
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16901
0
      op &= UINT64_C(1);
16902
0
      Value |= op;
16903
0
      break;
16904
0
    }
16905
0
    case AArch64::INSERT_MXIPZ_H_B:
16906
0
    case AArch64::INSERT_MXIPZ_V_B: {
16907
      // op: Rv
16908
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
16909
0
      op &= UINT64_C(3);
16910
0
      op <<= 13;
16911
0
      Value |= op;
16912
      // op: Pg
16913
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
16914
0
      op &= UINT64_C(7);
16915
0
      op <<= 10;
16916
0
      Value |= op;
16917
      // op: Zn
16918
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16919
0
      op &= UINT64_C(31);
16920
0
      op <<= 5;
16921
0
      Value |= op;
16922
      // op: imm
16923
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16924
0
      op &= UINT64_C(15);
16925
0
      Value |= op;
16926
0
      break;
16927
0
    }
16928
0
    case AArch64::PSEL_PPPRI_B: {
16929
      // op: Rv
16930
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
16931
0
      op &= UINT64_C(3);
16932
0
      op <<= 16;
16933
0
      Value |= op;
16934
      // op: Pn
16935
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16936
0
      op &= UINT64_C(15);
16937
0
      op <<= 10;
16938
0
      Value |= op;
16939
      // op: Pm
16940
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16941
0
      op &= UINT64_C(15);
16942
0
      op <<= 5;
16943
0
      Value |= op;
16944
      // op: Pd
16945
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16946
0
      op &= UINT64_C(15);
16947
0
      Value |= op;
16948
      // op: imm
16949
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
16950
0
      Value |= (op & UINT64_C(12)) << 20;
16951
0
      Value |= (op & UINT64_C(3)) << 19;
16952
0
      break;
16953
0
    }
16954
0
    case AArch64::PSEL_PPPRI_H: {
16955
      // op: Rv
16956
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
16957
0
      op &= UINT64_C(3);
16958
0
      op <<= 16;
16959
0
      Value |= op;
16960
      // op: Pn
16961
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16962
0
      op &= UINT64_C(15);
16963
0
      op <<= 10;
16964
0
      Value |= op;
16965
      // op: Pm
16966
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16967
0
      op &= UINT64_C(15);
16968
0
      op <<= 5;
16969
0
      Value |= op;
16970
      // op: Pd
16971
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16972
0
      op &= UINT64_C(15);
16973
0
      Value |= op;
16974
      // op: imm
16975
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
16976
0
      Value |= (op & UINT64_C(6)) << 21;
16977
0
      Value |= (op & UINT64_C(1)) << 20;
16978
0
      break;
16979
0
    }
16980
0
    case AArch64::PSEL_PPPRI_D: {
16981
      // op: Rv
16982
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
16983
0
      op &= UINT64_C(3);
16984
0
      op <<= 16;
16985
0
      Value |= op;
16986
      // op: Pn
16987
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16988
0
      op &= UINT64_C(15);
16989
0
      op <<= 10;
16990
0
      Value |= op;
16991
      // op: Pm
16992
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16993
0
      op &= UINT64_C(15);
16994
0
      op <<= 5;
16995
0
      Value |= op;
16996
      // op: Pd
16997
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16998
0
      op &= UINT64_C(15);
16999
0
      Value |= op;
17000
      // op: imm
17001
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
17002
0
      op &= UINT64_C(1);
17003
0
      op <<= 23;
17004
0
      Value |= op;
17005
0
      break;
17006
0
    }
17007
0
    case AArch64::PSEL_PPPRI_S: {
17008
      // op: Rv
17009
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
17010
0
      op &= UINT64_C(3);
17011
0
      op <<= 16;
17012
0
      Value |= op;
17013
      // op: Pn
17014
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
17015
0
      op &= UINT64_C(15);
17016
0
      op <<= 10;
17017
0
      Value |= op;
17018
      // op: Pm
17019
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
17020
0
      op &= UINT64_C(15);
17021
0
      op <<= 5;
17022
0
      Value |= op;
17023
      // op: Pd
17024
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
17025
0
      op &= UINT64_C(15);
17026
0
      Value |= op;
17027
      // op: imm
17028
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
17029
0
      op &= UINT64_C(3);
17030
0
      op <<= 22;
17031
0
      Value |= op;
17032
0
      break;
17033
0
    }
17034
0
    case AArch64::EXTRACT_ZPMXI_H_H:
17035
0
    case AArch64::EXTRACT_ZPMXI_V_H: {
17036
      // op: Rv
17037
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 4, Fixups, STI);
17038
0
      op &= UINT64_C(3);
17039
0
      op <<= 13;
17040
0
      Value |= op;
17041
      // op: Pg
17042
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
17043
0
      op &= UINT64_C(7);
17044
0
      op <<= 10;
17045
0
      Value |= op;
17046
      // op: Zd
17047
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
17048
0
      op &= UINT64_C(31);
17049
0
      Value |= op;
17050
      // op: ZAn
17051
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
17052
0
      op &= UINT64_C(1);
17053
0
      op <<= 8;
17054
0
      Value |= op;
17055
      // op: imm
17056
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
17057
0
      op &= UINT64_C(7);
17058
0
      op <<= 5;
17059
0
      Value |= op;
17060
0
      break;
17061
0
    }
17062
0
    case AArch64::EXTRACT_ZPMXI_H_Q:
17063
0
    case AArch64::EXTRACT_ZPMXI_V_Q: {
17064
      // op: Rv
17065
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 4, Fixups, STI);
17066
0
      op &= UINT64_C(3);
17067
0
      op <<= 13;
17068
0
      Value |= op;
17069
      // op: Pg
17070
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
17071
0
      op &= UINT64_C(7);
17072
0
      op <<= 10;
17073
0
      Value |= op;
17074
      // op: Zd
17075
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
17076
0
      op &= UINT64_C(31);
17077
0
      Value |= op;
17078
      // op: ZAn
17079
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
17080
0
      op &= UINT64_C(15);
17081
0
      op <<= 5;
17082
0
      Value |= op;
17083
0
      break;
17084
0
    }
17085
0
    case AArch64::EXTRACT_ZPMXI_H_S:
17086
0
    case AArch64::EXTRACT_ZPMXI_V_S: {
17087
      // op: Rv
17088
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 4, Fixups, STI);
17089
0
      op &= UINT64_C(3);
17090
0
      op <<= 13;
17091
0
      Value |= op;
17092
      // op: Pg
17093
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
17094
0
      op &= UINT64_C(7);
17095
0
      op <<= 10;
17096
0
      Value |= op;
17097
      // op: Zd
17098
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
17099
0
      op &= UINT64_C(31);
17100
0
      Value |= op;
17101
      // op: ZAn
17102
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
17103
0
      op &= UINT64_C(3);
17104
0
      op <<= 7;
17105
0
      Value |= op;
17106
      // op: imm
17107
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
17108
0
      op &= UINT64_C(3);
17109
0
      op <<= 5;
17110
0
      Value |= op;
17111
0
      break;
17112
0
    }
17113
0
    case AArch64::EXTRACT_ZPMXI_H_D:
17114
0
    case AArch64::EXTRACT_ZPMXI_V_D: {
17115
      // op: Rv
17116
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 4, Fixups, STI);
17117
0
      op &= UINT64_C(3);
17118
0
      op <<= 13;
17119
0
      Value |= op;
17120
      // op: Pg
17121
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
17122
0
      op &= UINT64_C(7);
17123
0
      op <<= 10;
17124
0
      Value |= op;
17125
      // op: Zd
17126
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
17127
0
      op &= UINT64_C(31);
17128
0
      Value |= op;
17129
      // op: ZAn
17130
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
17131
0
      op &= UINT64_C(7);
17132
0
      op <<= 6;
17133
0
      Value |= op;
17134
      // op: imm
17135
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
17136
0
      op &= UINT64_C(1);
17137
0
      op <<= 5;
17138
0
      Value |= op;
17139
0
      break;
17140
0
    }
17141
0
    case AArch64::EXTRACT_ZPMXI_H_B:
17142
0
    case AArch64::EXTRACT_ZPMXI_V_B: {
17143
      // op: Rv
17144
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 4, Fixups, STI);
17145
0
      op &= UINT64_C(3);
17146
0
      op <<= 13;
17147
0
      Value |= op;
17148
      // op: Pg
17149
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
17150
0
      op &= UINT64_C(7);
17151
0
      op <<= 10;
17152
0
      Value |= op;
17153
      // op: Zd
17154
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
17155
0
      op &= UINT64_C(31);
17156
0
      Value |= op;
17157
      // op: imm
17158
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
17159
0
      op &= UINT64_C(15);
17160
0
      op <<= 5;
17161
0
      Value |= op;
17162
0
      break;
17163
0
    }
17164
0
    case AArch64::BFMLAL_VG2_M2Z2Z_HtoS:
17165
0
    case AArch64::BFMLSL_VG2_M2Z2Z_HtoS:
17166
0
    case AArch64::FMLAL_VG2_M2Z2Z_BtoH:
17167
0
    case AArch64::FMLAL_VG2_M2Z2Z_HtoS:
17168
0
    case AArch64::FMLSL_VG2_M2Z2Z_HtoS:
17169
0
    case AArch64::SMLAL_VG2_M2Z2Z_HtoS:
17170
0
    case AArch64::SMLSL_VG2_M2Z2Z_HtoS:
17171
0
    case AArch64::UMLAL_VG2_M2Z2Z_HtoS:
17172
0
    case AArch64::UMLSL_VG2_M2Z2Z_HtoS: {
17173
      // op: Rv
17174
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
17175
0
      op &= UINT64_C(3);
17176
0
      op <<= 13;
17177
0
      Value |= op;
17178
      // op: Zm
17179
0
      op = EncodeRegAsMultipleOf<2>(MI, 5, Fixups, STI);
17180
0
      op &= UINT64_C(15);
17181
0
      op <<= 17;
17182
0
      Value |= op;
17183
      // op: Zn
17184
0
      op = EncodeRegAsMultipleOf<2>(MI, 4, Fixups, STI);
17185
0
      op &= UINT64_C(15);
17186
0
      op <<= 6;
17187
0
      Value |= op;
17188
      // op: imm
17189
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
17190
0
      op &= UINT64_C(3);
17191
0
      Value |= op;
17192
0
      break;
17193
0
    }
17194
0
    case AArch64::BFMLAL_VG4_M4Z4Z_HtoS:
17195
0
    case AArch64::BFMLSL_VG4_M4Z4Z_HtoS:
17196
0
    case AArch64::FMLAL_VG4_M4Z4Z_BtoH:
17197
0
    case AArch64::FMLAL_VG4_M4Z4Z_HtoS:
17198
0
    case AArch64::FMLSL_VG4_M4Z4Z_HtoS:
17199
0
    case AArch64::SMLAL_VG4_M4Z4Z_HtoS:
17200
0
    case AArch64::SMLSL_VG4_M4Z4Z_HtoS:
17201
0
    case AArch64::UMLAL_VG4_M4Z4Z_HtoS:
17202
0
    case AArch64::UMLSL_VG4_M4Z4Z_HtoS: {
17203
      // op: Rv
17204
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
17205
0
      op &= UINT64_C(3);
17206
0
      op <<= 13;
17207
0
      Value |= op;
17208
      // op: Zm
17209
0
      op = EncodeRegAsMultipleOf<4>(MI, 5, Fixups, STI);
17210
0
      op &= UINT64_C(7);
17211
0
      op <<= 18;
17212
0
      Value |= op;
17213
      // op: Zn
17214
0
      op = EncodeRegAsMultipleOf<4>(MI, 4, Fixups, STI);
17215
0
      op &= UINT64_C(7);
17216
0
      op <<= 7;
17217
0
      Value |= op;
17218
      // op: imm
17219
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
17220
0
      op &= UINT64_C(3);
17221
0
      Value |= op;
17222
0
      break;
17223
0
    }
17224
0
    case AArch64::BFMLAL_VG2_M2ZZ_HtoS:
17225
0
    case AArch64::BFMLAL_VG4_M4ZZ_HtoS:
17226
0
    case AArch64::BFMLSL_VG2_M2ZZ_HtoS:
17227
0
    case AArch64::BFMLSL_VG4_M4ZZ_HtoS:
17228
0
    case AArch64::FMLAL_VG2_M2ZZ_BtoH:
17229
0
    case AArch64::FMLAL_VG2_M2ZZ_HtoS:
17230
0
    case AArch64::FMLAL_VG4_M4ZZ_BtoH:
17231
0
    case AArch64::FMLAL_VG4_M4ZZ_HtoS:
17232
0
    case AArch64::FMLSL_VG2_M2ZZ_HtoS:
17233
0
    case AArch64::FMLSL_VG4_M4ZZ_HtoS:
17234
0
    case AArch64::SMLAL_VG2_M2ZZ_HtoS:
17235
0
    case AArch64::SMLAL_VG4_M4ZZ_HtoS:
17236
0
    case AArch64::SMLSL_VG2_M2ZZ_HtoS:
17237
0
    case AArch64::SMLSL_VG4_M4ZZ_HtoS:
17238
0
    case AArch64::UMLAL_VG2_M2ZZ_HtoS:
17239
0
    case AArch64::UMLAL_VG4_M4ZZ_HtoS:
17240
0
    case AArch64::UMLSL_VG2_M2ZZ_HtoS:
17241
0
    case AArch64::UMLSL_VG4_M4ZZ_HtoS: {
17242
      // op: Rv
17243
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
17244
0
      op &= UINT64_C(3);
17245
0
      op <<= 13;
17246
0
      Value |= op;
17247
      // op: Zm
17248
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
17249
0
      op &= UINT64_C(15);
17250
0
      op <<= 16;
17251
0
      Value |= op;
17252
      // op: Zn
17253
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
17254
0
      op &= UINT64_C(31);
17255
0
      op <<= 5;
17256
0
      Value |= op;
17257
      // op: imm
17258
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
17259
0
      op &= UINT64_C(3);
17260
0
      Value |= op;
17261
0
      break;
17262
0
    }
17263
0
    case AArch64::BFMLAL_MZZ_HtoS:
17264
0
    case AArch64::BFMLSL_MZZ_HtoS:
17265
0
    case AArch64::FMLAL_MZZ_HtoS:
17266
0
    case AArch64::FMLAL_VG2_MZZ_BtoH:
17267
0
    case AArch64::FMLSL_MZZ_HtoS:
17268
0
    case AArch64::SMLAL_MZZ_HtoS:
17269
0
    case AArch64::SMLSL_MZZ_HtoS:
17270
0
    case AArch64::UMLAL_MZZ_HtoS:
17271
0
    case AArch64::UMLSL_MZZ_HtoS: {
17272
      // op: Rv
17273
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
17274
0
      op &= UINT64_C(3);
17275
0
      op <<= 13;
17276
0
      Value |= op;
17277
      // op: Zm
17278
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
17279
0
      op &= UINT64_C(15);
17280
0
      op <<= 16;
17281
0
      Value |= op;
17282
      // op: Zn
17283
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
17284
0
      op &= UINT64_C(31);
17285
0
      op <<= 5;
17286
0
      Value |= op;
17287
      // op: imm
17288
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
17289
0
      op &= UINT64_C(7);
17290
0
      Value |= op;
17291
0
      break;
17292
0
    }
17293
0
    case AArch64::ZERO_MXI_VG2_4Z:
17294
0
    case AArch64::ZERO_MXI_VG4_4Z: {
17295
      // op: Rv
17296
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
17297
0
      op &= UINT64_C(3);
17298
0
      op <<= 13;
17299
0
      Value |= op;
17300
      // op: imm
17301
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
17302
0
      op &= UINT64_C(1);
17303
0
      Value |= op;
17304
0
      break;
17305
0
    }
17306
0
    case AArch64::ZERO_MXI_4Z:
17307
0
    case AArch64::ZERO_MXI_VG2_2Z:
17308
0
    case AArch64::ZERO_MXI_VG4_2Z: {
17309
      // op: Rv
17310
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
17311
0
      op &= UINT64_C(3);
17312
0
      op <<= 13;
17313
0
      Value |= op;
17314
      // op: imm
17315
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
17316
0
      op &= UINT64_C(3);
17317
0
      Value |= op;
17318
0
      break;
17319
0
    }
17320
0
    case AArch64::ZERO_MXI_2Z:
17321
0
    case AArch64::ZERO_MXI_VG2_Z:
17322
0
    case AArch64::ZERO_MXI_VG4_Z: {
17323
      // op: Rv
17324
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
17325
0
      op &= UINT64_C(3);
17326
0
      op <<= 13;
17327
0
      Value |= op;
17328
      // op: imm
17329
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
17330
0
      op &= UINT64_C(7);
17331
0
      Value |= op;
17332
0
      break;
17333
0
    }
17334
0
    case AArch64::ADD_VG2_M2Z_D:
17335
0
    case AArch64::ADD_VG2_M2Z_S:
17336
0
    case AArch64::BFADD_VG2_M2Z_H:
17337
0
    case AArch64::BFSUB_VG2_M2Z_H:
17338
0
    case AArch64::FADD_VG2_M2Z_D:
17339
0
    case AArch64::FADD_VG2_M2Z_H:
17340
0
    case AArch64::FADD_VG2_M2Z_S:
17341
0
    case AArch64::FSUB_VG2_M2Z_D:
17342
0
    case AArch64::FSUB_VG2_M2Z_H:
17343
0
    case AArch64::FSUB_VG2_M2Z_S:
17344
0
    case AArch64::SUB_VG2_M2Z_D:
17345
0
    case AArch64::SUB_VG2_M2Z_S: {
17346
      // op: Rv
17347
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
17348
0
      op &= UINT64_C(3);
17349
0
      op <<= 13;
17350
0
      Value |= op;
17351
      // op: imm3
17352
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
17353
0
      op &= UINT64_C(7);
17354
0
      Value |= op;
17355
      // op: Zm
17356
0
      op = EncodeRegAsMultipleOf<2>(MI, 4, Fixups, STI);
17357
0
      op &= UINT64_C(15);
17358
0
      op <<= 6;
17359
0
      Value |= op;
17360
0
      break;
17361
0
    }
17362
0
    case AArch64::ADD_VG4_M4Z_D:
17363
0
    case AArch64::ADD_VG4_M4Z_S:
17364
0
    case AArch64::BFADD_VG4_M4Z_H:
17365
0
    case AArch64::BFSUB_VG4_M4Z_H:
17366
0
    case AArch64::FADD_VG4_M4Z_D:
17367
0
    case AArch64::FADD_VG4_M4Z_H:
17368
0
    case AArch64::FADD_VG4_M4Z_S:
17369
0
    case AArch64::FSUB_VG4_M4Z_D:
17370
0
    case AArch64::FSUB_VG4_M4Z_H:
17371
0
    case AArch64::FSUB_VG4_M4Z_S:
17372
0
    case AArch64::SUB_VG4_M4Z_D:
17373
0
    case AArch64::SUB_VG4_M4Z_S: {
17374
      // op: Rv
17375
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
17376
0
      op &= UINT64_C(3);
17377
0
      op <<= 13;
17378
0
      Value |= op;
17379
      // op: imm3
17380
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
17381
0
      op &= UINT64_C(7);
17382
0
      Value |= op;
17383
      // op: Zm
17384
0
      op = EncodeRegAsMultipleOf<4>(MI, 4, Fixups, STI);
17385
0
      op &= UINT64_C(7);
17386
0
      op <<= 7;
17387
0
      Value |= op;
17388
0
      break;
17389
0
    }
17390
0
    case AArch64::RAX1:
17391
0
    case AArch64::SM4ENCKEY:
17392
0
    case AArch64::TBLv8i8Four:
17393
0
    case AArch64::TBLv8i8One:
17394
0
    case AArch64::TBLv8i8Three:
17395
0
    case AArch64::TBLv8i8Two:
17396
0
    case AArch64::TBLv16i8Four:
17397
0
    case AArch64::TBLv16i8One:
17398
0
    case AArch64::TBLv16i8Three:
17399
0
    case AArch64::TBLv16i8Two: {
17400
      // op: Vd
17401
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
17402
0
      op &= UINT64_C(31);
17403
0
      Value |= op;
17404
      // op: Vn
17405
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
17406
0
      op &= UINT64_C(31);
17407
0
      op <<= 5;
17408
0
      Value |= op;
17409
      // op: Vm
17410
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
17411
0
      op &= UINT64_C(31);
17412
0
      op <<= 16;
17413
0
      Value |= op;
17414
0
      break;
17415
0
    }
17416
0
    case AArch64::BCAX:
17417
0
    case AArch64::EOR3:
17418
0
    case AArch64::SM3SS1: {
17419
      // op: Vd
17420
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
17421
0
      op &= UINT64_C(31);
17422
0
      Value |= op;
17423
      // op: Vn
17424
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
17425
0
      op &= UINT64_C(31);
17426
0
      op <<= 5;
17427
0
      Value |= op;
17428
      // op: Vm
17429
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
17430
0
      op &= UINT64_C(31);
17431
0
      op <<= 16;
17432
0
      Value |= op;
17433
      // op: Va
17434
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
17435
0
      op &= UINT64_C(31);
17436
0
      op <<= 10;
17437
0
      Value |= op;
17438
0
      break;
17439
0
    }
17440
0
    case AArch64::XAR: {
17441
      // op: Vd
17442
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
17443
0
      op &= UINT64_C(31);
17444
0
      Value |= op;
17445
      // op: Vn
17446
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
17447
0
      op &= UINT64_C(31);
17448
0
      op <<= 5;
17449
0
      Value |= op;
17450
      // op: imm
17451
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
17452
0
      op &= UINT64_C(63);
17453
0
      op <<= 10;
17454
0
      Value |= op;
17455
      // op: Vm
17456
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
17457
0
      op &= UINT64_C(31);
17458
0
      op <<= 16;
17459
0
      Value |= op;
17460
0
      break;
17461
0
    }
17462
0
    case AArch64::ADDQV_VPZ_B:
17463
0
    case AArch64::ADDQV_VPZ_D:
17464
0
    case AArch64::ADDQV_VPZ_H:
17465
0
    case AArch64::ADDQV_VPZ_S:
17466
0
    case AArch64::ANDQV_VPZ_B:
17467
0
    case AArch64::ANDQV_VPZ_D:
17468
0
    case AArch64::ANDQV_VPZ_H:
17469
0
    case AArch64::ANDQV_VPZ_S:
17470
0
    case AArch64::EORQV_VPZ_B:
17471
0
    case AArch64::EORQV_VPZ_D:
17472
0
    case AArch64::EORQV_VPZ_H:
17473
0
    case AArch64::EORQV_VPZ_S:
17474
0
    case AArch64::FADDQV_D:
17475
0
    case AArch64::FADDQV_H:
17476
0
    case AArch64::FADDQV_S:
17477
0
    case AArch64::FMAXNMQV_D:
17478
0
    case AArch64::FMAXNMQV_H:
17479
0
    case AArch64::FMAXNMQV_S:
17480
0
    case AArch64::FMAXQV_D:
17481
0
    case AArch64::FMAXQV_H:
17482
0
    case AArch64::FMAXQV_S:
17483
0
    case AArch64::FMINNMQV_D:
17484
0
    case AArch64::FMINNMQV_H:
17485
0
    case AArch64::FMINNMQV_S:
17486
0
    case AArch64::FMINQV_D:
17487
0
    case AArch64::FMINQV_H:
17488
0
    case AArch64::FMINQV_S:
17489
0
    case AArch64::ORQV_VPZ_B:
17490
0
    case AArch64::ORQV_VPZ_D:
17491
0
    case AArch64::ORQV_VPZ_H:
17492
0
    case AArch64::ORQV_VPZ_S:
17493
0
    case AArch64::SMAXQV_VPZ_B:
17494
0
    case AArch64::SMAXQV_VPZ_D:
17495
0
    case AArch64::SMAXQV_VPZ_H:
17496
0
    case AArch64::SMAXQV_VPZ_S:
17497
0
    case AArch64::SMINQV_VPZ_B:
17498
0
    case AArch64::SMINQV_VPZ_D:
17499
0
    case AArch64::SMINQV_VPZ_H:
17500
0
    case AArch64::SMINQV_VPZ_S:
17501
0
    case AArch64::UMAXQV_VPZ_B:
17502
0
    case AArch64::UMAXQV_VPZ_D:
17503
0
    case AArch64::UMAXQV_VPZ_H:
17504
0
    case AArch64::UMAXQV_VPZ_S:
17505
0
    case AArch64::UMINQV_VPZ_B:
17506
0
    case AArch64::UMINQV_VPZ_D:
17507
0
    case AArch64::UMINQV_VPZ_H:
17508
0
    case AArch64::UMINQV_VPZ_S: {
17509
      // op: Vd
17510
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
17511
0
      op &= UINT64_C(31);
17512
0
      Value |= op;
17513
      // op: Zn
17514
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
17515
0
      op &= UINT64_C(31);
17516
0
      op <<= 5;
17517
0
      Value |= op;
17518
      // op: Pg
17519
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
17520
0
      op &= UINT64_C(7);
17521
0
      op <<= 10;
17522
0
      Value |= op;
17523
0
      break;
17524
0
    }
17525
0
    case AArch64::SHA512SU0:
17526
0
    case AArch64::SM4E: {
17527
      // op: Vd
17528
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
17529
0
      op &= UINT64_C(31);
17530
0
      Value |= op;
17531
      // op: Vn
17532
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
17533
0
      op &= UINT64_C(31);
17534
0
      op <<= 5;
17535
0
      Value |= op;
17536
0
      break;
17537
0
    }
17538
0
    case AArch64::SHA512H:
17539
0
    case AArch64::SHA512H2:
17540
0
    case AArch64::SHA512SU1:
17541
0
    case AArch64::SM3PARTW1:
17542
0
    case AArch64::SM3PARTW2:
17543
0
    case AArch64::TBXv8i8Four:
17544
0
    case AArch64::TBXv8i8One:
17545
0
    case AArch64::TBXv8i8Three:
17546
0
    case AArch64::TBXv8i8Two:
17547
0
    case AArch64::TBXv16i8Four:
17548
0
    case AArch64::TBXv16i8One:
17549
0
    case AArch64::TBXv16i8Three:
17550
0
    case AArch64::TBXv16i8Two: {
17551
      // op: Vd
17552
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
17553
0
      op &= UINT64_C(31);
17554
0
      Value |= op;
17555
      // op: Vn
17556
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
17557
0
      op &= UINT64_C(31);
17558
0
      op <<= 5;
17559
0
      Value |= op;
17560
      // op: Vm
17561
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
17562
0
      op &= UINT64_C(31);
17563
0
      op <<= 16;
17564
0
      Value |= op;
17565
0
      break;
17566
0
    }
17567
0
    case AArch64::SM3TT1A:
17568
0
    case AArch64::SM3TT1B:
17569
0
    case AArch64::SM3TT2A:
17570
0
    case AArch64::SM3TT2B: {
17571
      // op: Vd
17572
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
17573
0
      op &= UINT64_C(31);
17574
0
      Value |= op;
17575
      // op: Vn
17576
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
17577
0
      op &= UINT64_C(31);
17578
0
      op <<= 5;
17579
0
      Value |= op;
17580
      // op: imm
17581
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
17582
0
      op &= UINT64_C(3);
17583
0
      op <<= 12;
17584
0
      Value |= op;
17585
      // op: Vm
17586
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
17587
0
      op &= UINT64_C(31);
17588
0
      op <<= 16;
17589
0
      Value |= op;
17590
0
      break;
17591
0
    }
17592
0
    case AArch64::INSR_ZV_B:
17593
0
    case AArch64::INSR_ZV_D:
17594
0
    case AArch64::INSR_ZV_H:
17595
0
    case AArch64::INSR_ZV_S: {
17596
      // op: Vm
17597
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
17598
0
      op &= UINT64_C(31);
17599
0
      op <<= 5;
17600
0
      Value |= op;
17601
      // op: Zdn
17602
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
17603
0
      op &= UINT64_C(31);
17604
0
      Value |= op;
17605
0
      break;
17606
0
    }
17607
0
    case AArch64::LD1Fourv1d:
17608
0
    case AArch64::LD1Fourv2d:
17609
0
    case AArch64::LD1Fourv2s:
17610
0
    case AArch64::LD1Fourv4h:
17611
0
    case AArch64::LD1Fourv4s:
17612
0
    case AArch64::LD1Fourv8b:
17613
0
    case AArch64::LD1Fourv8h:
17614
0
    case AArch64::LD1Fourv16b:
17615
0
    case AArch64::LD1Onev1d:
17616
0
    case AArch64::LD1Onev2d:
17617
0
    case AArch64::LD1Onev2s:
17618
0
    case AArch64::LD1Onev4h:
17619
0
    case AArch64::LD1Onev4s:
17620
0
    case AArch64::LD1Onev8b:
17621
0
    case AArch64::LD1Onev8h:
17622
0
    case AArch64::LD1Onev16b:
17623
0
    case AArch64::LD1Rv1d:
17624
0
    case AArch64::LD1Rv2d:
17625
0
    case AArch64::LD1Rv2s:
17626
0
    case AArch64::LD1Rv4h:
17627
0
    case AArch64::LD1Rv4s:
17628
0
    case AArch64::LD1Rv8b:
17629
0
    case AArch64::LD1Rv8h:
17630
0
    case AArch64::LD1Rv16b:
17631
0
    case AArch64::LD1Threev1d:
17632
0
    case AArch64::LD1Threev2d:
17633
0
    case AArch64::LD1Threev2s:
17634
0
    case AArch64::LD1Threev4h:
17635
0
    case AArch64::LD1Threev4s:
17636
0
    case AArch64::LD1Threev8b:
17637
0
    case AArch64::LD1Threev8h:
17638
0
    case AArch64::LD1Threev16b:
17639
0
    case AArch64::LD1Twov1d:
17640
0
    case AArch64::LD1Twov2d:
17641
0
    case AArch64::LD1Twov2s:
17642
0
    case AArch64::LD1Twov4h:
17643
0
    case AArch64::LD1Twov4s:
17644
0
    case AArch64::LD1Twov8b:
17645
0
    case AArch64::LD1Twov8h:
17646
0
    case AArch64::LD1Twov16b:
17647
0
    case AArch64::LD2Rv1d:
17648
0
    case AArch64::LD2Rv2d:
17649
0
    case AArch64::LD2Rv2s:
17650
0
    case AArch64::LD2Rv4h:
17651
0
    case AArch64::LD2Rv4s:
17652
0
    case AArch64::LD2Rv8b:
17653
0
    case AArch64::LD2Rv8h:
17654
0
    case AArch64::LD2Rv16b:
17655
0
    case AArch64::LD2Twov2d:
17656
0
    case AArch64::LD2Twov2s:
17657
0
    case AArch64::LD2Twov4h:
17658
0
    case AArch64::LD2Twov4s:
17659
0
    case AArch64::LD2Twov8b:
17660
0
    case AArch64::LD2Twov8h:
17661
0
    case AArch64::LD2Twov16b:
17662
0
    case AArch64::LD3Rv1d:
17663
0
    case AArch64::LD3Rv2d:
17664
0
    case AArch64::LD3Rv2s:
17665
0
    case AArch64::LD3Rv4h:
17666
0
    case AArch64::LD3Rv4s:
17667
0
    case AArch64::LD3Rv8b:
17668
0
    case AArch64::LD3Rv8h:
17669
0
    case AArch64::LD3Rv16b:
17670
0
    case AArch64::LD3Threev2d:
17671
0
    case AArch64::LD3Threev2s:
17672
0
    case AArch64::LD3Threev4h:
17673
0
    case AArch64::LD3Threev4s:
17674
0
    case AArch64::LD3Threev8b:
17675
0
    case AArch64::LD3Threev8h:
17676
0
    case AArch64::LD3Threev16b:
17677
0
    case AArch64::LD4Fourv2d:
17678
0
    case AArch64::LD4Fourv2s:
17679
0
    case AArch64::LD4Fourv4h:
17680
0
    case AArch64::LD4Fourv4s:
17681
0
    case AArch64::LD4Fourv8b:
17682
0
    case AArch64::LD4Fourv8h:
17683
0
    case AArch64::LD4Fourv16b:
17684
0
    case AArch64::LD4Rv1d:
17685
0
    case AArch64::LD4Rv2d:
17686
0
    case AArch64::LD4Rv2s:
17687
0
    case AArch64::LD4Rv4h:
17688
0
    case AArch64::LD4Rv4s:
17689
0
    case AArch64::LD4Rv8b:
17690
0
    case AArch64::LD4Rv8h:
17691
0
    case AArch64::LD4Rv16b:
17692
0
    case AArch64::ST1Fourv1d:
17693
0
    case AArch64::ST1Fourv2d:
17694
0
    case AArch64::ST1Fourv2s:
17695
0
    case AArch64::ST1Fourv4h:
17696
0
    case AArch64::ST1Fourv4s:
17697
0
    case AArch64::ST1Fourv8b:
17698
0
    case AArch64::ST1Fourv8h:
17699
0
    case AArch64::ST1Fourv16b:
17700
0
    case AArch64::ST1Onev1d:
17701
0
    case AArch64::ST1Onev2d:
17702
0
    case AArch64::ST1Onev2s:
17703
0
    case AArch64::ST1Onev4h:
17704
0
    case AArch64::ST1Onev4s:
17705
0
    case AArch64::ST1Onev8b:
17706
0
    case AArch64::ST1Onev8h:
17707
0
    case AArch64::ST1Onev16b:
17708
0
    case AArch64::ST1Threev1d:
17709
0
    case AArch64::ST1Threev2d:
17710
0
    case AArch64::ST1Threev2s:
17711
0
    case AArch64::ST1Threev4h:
17712
0
    case AArch64::ST1Threev4s:
17713
0
    case AArch64::ST1Threev8b:
17714
0
    case AArch64::ST1Threev8h:
17715
0
    case AArch64::ST1Threev16b:
17716
0
    case AArch64::ST1Twov1d:
17717
0
    case AArch64::ST1Twov2d:
17718
0
    case AArch64::ST1Twov2s:
17719
0
    case AArch64::ST1Twov4h:
17720
0
    case AArch64::ST1Twov4s:
17721
0
    case AArch64::ST1Twov8b:
17722
0
    case AArch64::ST1Twov8h:
17723
0
    case AArch64::ST1Twov16b:
17724
0
    case AArch64::ST2Twov2d:
17725
0
    case AArch64::ST2Twov2s:
17726
0
    case AArch64::ST2Twov4h:
17727
0
    case AArch64::ST2Twov4s:
17728
0
    case AArch64::ST2Twov8b:
17729
0
    case AArch64::ST2Twov8h:
17730
0
    case AArch64::ST2Twov16b:
17731
0
    case AArch64::ST3Threev2d:
17732
0
    case AArch64::ST3Threev2s:
17733
0
    case AArch64::ST3Threev4h:
17734
0
    case AArch64::ST3Threev4s:
17735
0
    case AArch64::ST3Threev8b:
17736
0
    case AArch64::ST3Threev8h:
17737
0
    case AArch64::ST3Threev16b:
17738
0
    case AArch64::ST4Fourv2d:
17739
0
    case AArch64::ST4Fourv2s:
17740
0
    case AArch64::ST4Fourv4h:
17741
0
    case AArch64::ST4Fourv4s:
17742
0
    case AArch64::ST4Fourv8b:
17743
0
    case AArch64::ST4Fourv8h:
17744
0
    case AArch64::ST4Fourv16b: {
17745
      // op: Vt
17746
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
17747
0
      op &= UINT64_C(31);
17748
0
      Value |= op;
17749
      // op: Rn
17750
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
17751
0
      op &= UINT64_C(31);
17752
0
      op <<= 5;
17753
0
      Value |= op;
17754
0
      break;
17755
0
    }
17756
0
    case AArch64::STL1: {
17757
      // op: Vt
17758
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
17759
0
      op &= UINT64_C(31);
17760
0
      Value |= op;
17761
      // op: Rn
17762
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
17763
0
      op &= UINT64_C(31);
17764
0
      op <<= 5;
17765
0
      Value |= op;
17766
      // op: Q
17767
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
17768
0
      op &= UINT64_C(1);
17769
0
      op <<= 30;
17770
0
      Value |= op;
17771
0
      break;
17772
0
    }
17773
0
    case AArch64::ST1i32:
17774
0
    case AArch64::ST2i32:
17775
0
    case AArch64::ST3i32:
17776
0
    case AArch64::ST4i32: {
17777
      // op: Vt
17778
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
17779
0
      op &= UINT64_C(31);
17780
0
      Value |= op;
17781
      // op: Rn
17782
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
17783
0
      op &= UINT64_C(31);
17784
0
      op <<= 5;
17785
0
      Value |= op;
17786
      // op: idx
17787
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
17788
0
      Value |= (op & UINT64_C(2)) << 29;
17789
0
      Value |= (op & UINT64_C(1)) << 12;
17790
0
      break;
17791
0
    }
17792
0
    case AArch64::ST1i16:
17793
0
    case AArch64::ST2i16:
17794
0
    case AArch64::ST3i16:
17795
0
    case AArch64::ST4i16: {
17796
      // op: Vt
17797
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
17798
0
      op &= UINT64_C(31);
17799
0
      Value |= op;
17800
      // op: Rn
17801
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
17802
0
      op &= UINT64_C(31);
17803
0
      op <<= 5;
17804
0
      Value |= op;
17805
      // op: idx
17806
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
17807
0
      Value |= (op & UINT64_C(4)) << 28;
17808
0
      Value |= (op & UINT64_C(3)) << 11;
17809
0
      break;
17810
0
    }
17811
0
    case AArch64::ST1i8:
17812
0
    case AArch64::ST2i8:
17813
0
    case AArch64::ST3i8:
17814
0
    case AArch64::ST4i8: {
17815
      // op: Vt
17816
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
17817
0
      op &= UINT64_C(31);
17818
0
      Value |= op;
17819
      // op: Rn
17820
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
17821
0
      op &= UINT64_C(31);
17822
0
      op <<= 5;
17823
0
      Value |= op;
17824
      // op: idx
17825
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
17826
0
      Value |= (op & UINT64_C(8)) << 27;
17827
0
      Value |= (op & UINT64_C(7)) << 10;
17828
0
      break;
17829
0
    }
17830
0
    case AArch64::ST1i64:
17831
0
    case AArch64::ST2i64:
17832
0
    case AArch64::ST3i64:
17833
0
    case AArch64::ST4i64: {
17834
      // op: Vt
17835
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
17836
0
      op &= UINT64_C(31);
17837
0
      Value |= op;
17838
      // op: Rn
17839
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
17840
0
      op &= UINT64_C(31);
17841
0
      op <<= 5;
17842
0
      Value |= op;
17843
      // op: idx
17844
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
17845
0
      op &= UINT64_C(1);
17846
0
      op <<= 30;
17847
0
      Value |= op;
17848
0
      break;
17849
0
    }
17850
0
    case AArch64::LD1Fourv1d_POST:
17851
0
    case AArch64::LD1Fourv2d_POST:
17852
0
    case AArch64::LD1Fourv2s_POST:
17853
0
    case AArch64::LD1Fourv4h_POST:
17854
0
    case AArch64::LD1Fourv4s_POST:
17855
0
    case AArch64::LD1Fourv8b_POST:
17856
0
    case AArch64::LD1Fourv8h_POST:
17857
0
    case AArch64::LD1Fourv16b_POST:
17858
0
    case AArch64::LD1Onev1d_POST:
17859
0
    case AArch64::LD1Onev2d_POST:
17860
0
    case AArch64::LD1Onev2s_POST:
17861
0
    case AArch64::LD1Onev4h_POST:
17862
0
    case AArch64::LD1Onev4s_POST:
17863
0
    case AArch64::LD1Onev8b_POST:
17864
0
    case AArch64::LD1Onev8h_POST:
17865
0
    case AArch64::LD1Onev16b_POST:
17866
0
    case AArch64::LD1Rv1d_POST:
17867
0
    case AArch64::LD1Rv2d_POST:
17868
0
    case AArch64::LD1Rv2s_POST:
17869
0
    case AArch64::LD1Rv4h_POST:
17870
0
    case AArch64::LD1Rv4s_POST:
17871
0
    case AArch64::LD1Rv8b_POST:
17872
0
    case AArch64::LD1Rv8h_POST:
17873
0
    case AArch64::LD1Rv16b_POST:
17874
0
    case AArch64::LD1Threev1d_POST:
17875
0
    case AArch64::LD1Threev2d_POST:
17876
0
    case AArch64::LD1Threev2s_POST:
17877
0
    case AArch64::LD1Threev4h_POST:
17878
0
    case AArch64::LD1Threev4s_POST:
17879
0
    case AArch64::LD1Threev8b_POST:
17880
0
    case AArch64::LD1Threev8h_POST:
17881
0
    case AArch64::LD1Threev16b_POST:
17882
0
    case AArch64::LD1Twov1d_POST:
17883
0
    case AArch64::LD1Twov2d_POST:
17884
0
    case AArch64::LD1Twov2s_POST:
17885
0
    case AArch64::LD1Twov4h_POST:
17886
0
    case AArch64::LD1Twov4s_POST:
17887
0
    case AArch64::LD1Twov8b_POST:
17888
0
    case AArch64::LD1Twov8h_POST:
17889
0
    case AArch64::LD1Twov16b_POST:
17890
0
    case AArch64::LD2Rv1d_POST:
17891
0
    case AArch64::LD2Rv2d_POST:
17892
0
    case AArch64::LD2Rv2s_POST:
17893
0
    case AArch64::LD2Rv4h_POST:
17894
0
    case AArch64::LD2Rv4s_POST:
17895
0
    case AArch64::LD2Rv8b_POST:
17896
0
    case AArch64::LD2Rv8h_POST:
17897
0
    case AArch64::LD2Rv16b_POST:
17898
0
    case AArch64::LD2Twov2d_POST:
17899
0
    case AArch64::LD2Twov2s_POST:
17900
0
    case AArch64::LD2Twov4h_POST:
17901
0
    case AArch64::LD2Twov4s_POST:
17902
0
    case AArch64::LD2Twov8b_POST:
17903
0
    case AArch64::LD2Twov8h_POST:
17904
0
    case AArch64::LD2Twov16b_POST:
17905
0
    case AArch64::LD3Rv1d_POST:
17906
0
    case AArch64::LD3Rv2d_POST:
17907
0
    case AArch64::LD3Rv2s_POST:
17908
0
    case AArch64::LD3Rv4h_POST:
17909
0
    case AArch64::LD3Rv4s_POST:
17910
0
    case AArch64::LD3Rv8b_POST:
17911
0
    case AArch64::LD3Rv8h_POST:
17912
0
    case AArch64::LD3Rv16b_POST:
17913
0
    case AArch64::LD3Threev2d_POST:
17914
0
    case AArch64::LD3Threev2s_POST:
17915
0
    case AArch64::LD3Threev4h_POST:
17916
0
    case AArch64::LD3Threev4s_POST:
17917
0
    case AArch64::LD3Threev8b_POST:
17918
0
    case AArch64::LD3Threev8h_POST:
17919
0
    case AArch64::LD3Threev16b_POST:
17920
0
    case AArch64::LD4Fourv2d_POST:
17921
0
    case AArch64::LD4Fourv2s_POST:
17922
0
    case AArch64::LD4Fourv4h_POST:
17923
0
    case AArch64::LD4Fourv4s_POST:
17924
0
    case AArch64::LD4Fourv8b_POST:
17925
0
    case AArch64::LD4Fourv8h_POST:
17926
0
    case AArch64::LD4Fourv16b_POST:
17927
0
    case AArch64::LD4Rv1d_POST:
17928
0
    case AArch64::LD4Rv2d_POST:
17929
0
    case AArch64::LD4Rv2s_POST:
17930
0
    case AArch64::LD4Rv4h_POST:
17931
0
    case AArch64::LD4Rv4s_POST:
17932
0
    case AArch64::LD4Rv8b_POST:
17933
0
    case AArch64::LD4Rv8h_POST:
17934
0
    case AArch64::LD4Rv16b_POST:
17935
0
    case AArch64::ST1Fourv1d_POST:
17936
0
    case AArch64::ST1Fourv2d_POST:
17937
0
    case AArch64::ST1Fourv2s_POST:
17938
0
    case AArch64::ST1Fourv4h_POST:
17939
0
    case AArch64::ST1Fourv4s_POST:
17940
0
    case AArch64::ST1Fourv8b_POST:
17941
0
    case AArch64::ST1Fourv8h_POST:
17942
0
    case AArch64::ST1Fourv16b_POST:
17943
0
    case AArch64::ST1Onev1d_POST:
17944
0
    case AArch64::ST1Onev2d_POST:
17945
0
    case AArch64::ST1Onev2s_POST:
17946
0
    case AArch64::ST1Onev4h_POST:
17947
0
    case AArch64::ST1Onev4s_POST:
17948
0
    case AArch64::ST1Onev8b_POST:
17949
0
    case AArch64::ST1Onev8h_POST:
17950
0
    case AArch64::ST1Onev16b_POST:
17951
0
    case AArch64::ST1Threev1d_POST:
17952
0
    case AArch64::ST1Threev2d_POST:
17953
0
    case AArch64::ST1Threev2s_POST:
17954
0
    case AArch64::ST1Threev4h_POST:
17955
0
    case AArch64::ST1Threev4s_POST:
17956
0
    case AArch64::ST1Threev8b_POST:
17957
0
    case AArch64::ST1Threev8h_POST:
17958
0
    case AArch64::ST1Threev16b_POST:
17959
0
    case AArch64::ST1Twov1d_POST:
17960
0
    case AArch64::ST1Twov2d_POST:
17961
0
    case AArch64::ST1Twov2s_POST:
17962
0
    case AArch64::ST1Twov4h_POST:
17963
0
    case AArch64::ST1Twov4s_POST:
17964
0
    case AArch64::ST1Twov8b_POST:
17965
0
    case AArch64::ST1Twov8h_POST:
17966
0
    case AArch64::ST1Twov16b_POST:
17967
0
    case AArch64::ST2Twov2d_POST:
17968
0
    case AArch64::ST2Twov2s_POST:
17969
0
    case AArch64::ST2Twov4h_POST:
17970
0
    case AArch64::ST2Twov4s_POST:
17971
0
    case AArch64::ST2Twov8b_POST:
17972
0
    case AArch64::ST2Twov8h_POST:
17973
0
    case AArch64::ST2Twov16b_POST:
17974
0
    case AArch64::ST3Threev2d_POST:
17975
0
    case AArch64::ST3Threev2s_POST:
17976
0
    case AArch64::ST3Threev4h_POST:
17977
0
    case AArch64::ST3Threev4s_POST:
17978
0
    case AArch64::ST3Threev8b_POST:
17979
0
    case AArch64::ST3Threev8h_POST:
17980
0
    case AArch64::ST3Threev16b_POST:
17981
0
    case AArch64::ST4Fourv2d_POST:
17982
0
    case AArch64::ST4Fourv2s_POST:
17983
0
    case AArch64::ST4Fourv4h_POST:
17984
0
    case AArch64::ST4Fourv4s_POST:
17985
0
    case AArch64::ST4Fourv8b_POST:
17986
0
    case AArch64::ST4Fourv8h_POST:
17987
0
    case AArch64::ST4Fourv16b_POST: {
17988
      // op: Vt
17989
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
17990
0
      op &= UINT64_C(31);
17991
0
      Value |= op;
17992
      // op: Rn
17993
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
17994
0
      op &= UINT64_C(31);
17995
0
      op <<= 5;
17996
0
      Value |= op;
17997
      // op: Xm
17998
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
17999
0
      op &= UINT64_C(31);
18000
0
      op <<= 16;
18001
0
      Value |= op;
18002
0
      break;
18003
0
    }
18004
0
    case AArch64::LDAP1: {
18005
      // op: Vt
18006
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
18007
0
      op &= UINT64_C(31);
18008
0
      Value |= op;
18009
      // op: Rn
18010
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18011
0
      op &= UINT64_C(31);
18012
0
      op <<= 5;
18013
0
      Value |= op;
18014
      // op: Q
18015
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18016
0
      op &= UINT64_C(1);
18017
0
      op <<= 30;
18018
0
      Value |= op;
18019
0
      break;
18020
0
    }
18021
0
    case AArch64::LD1i32:
18022
0
    case AArch64::LD2i32:
18023
0
    case AArch64::LD3i32:
18024
0
    case AArch64::LD4i32: {
18025
      // op: Vt
18026
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
18027
0
      op &= UINT64_C(31);
18028
0
      Value |= op;
18029
      // op: Rn
18030
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18031
0
      op &= UINT64_C(31);
18032
0
      op <<= 5;
18033
0
      Value |= op;
18034
      // op: idx
18035
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18036
0
      Value |= (op & UINT64_C(2)) << 29;
18037
0
      Value |= (op & UINT64_C(1)) << 12;
18038
0
      break;
18039
0
    }
18040
0
    case AArch64::ST1i32_POST:
18041
0
    case AArch64::ST2i32_POST:
18042
0
    case AArch64::ST3i32_POST:
18043
0
    case AArch64::ST4i32_POST: {
18044
      // op: Vt
18045
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
18046
0
      op &= UINT64_C(31);
18047
0
      Value |= op;
18048
      // op: Rn
18049
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18050
0
      op &= UINT64_C(31);
18051
0
      op <<= 5;
18052
0
      Value |= op;
18053
      // op: idx
18054
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18055
0
      Value |= (op & UINT64_C(2)) << 29;
18056
0
      Value |= (op & UINT64_C(1)) << 12;
18057
      // op: Xm
18058
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
18059
0
      op &= UINT64_C(31);
18060
0
      op <<= 16;
18061
0
      Value |= op;
18062
0
      break;
18063
0
    }
18064
0
    case AArch64::LD1i16:
18065
0
    case AArch64::LD2i16:
18066
0
    case AArch64::LD3i16:
18067
0
    case AArch64::LD4i16: {
18068
      // op: Vt
18069
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
18070
0
      op &= UINT64_C(31);
18071
0
      Value |= op;
18072
      // op: Rn
18073
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18074
0
      op &= UINT64_C(31);
18075
0
      op <<= 5;
18076
0
      Value |= op;
18077
      // op: idx
18078
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18079
0
      Value |= (op & UINT64_C(4)) << 28;
18080
0
      Value |= (op & UINT64_C(3)) << 11;
18081
0
      break;
18082
0
    }
18083
0
    case AArch64::ST1i16_POST:
18084
0
    case AArch64::ST2i16_POST:
18085
0
    case AArch64::ST3i16_POST:
18086
0
    case AArch64::ST4i16_POST: {
18087
      // op: Vt
18088
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
18089
0
      op &= UINT64_C(31);
18090
0
      Value |= op;
18091
      // op: Rn
18092
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18093
0
      op &= UINT64_C(31);
18094
0
      op <<= 5;
18095
0
      Value |= op;
18096
      // op: idx
18097
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18098
0
      Value |= (op & UINT64_C(4)) << 28;
18099
0
      Value |= (op & UINT64_C(3)) << 11;
18100
      // op: Xm
18101
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
18102
0
      op &= UINT64_C(31);
18103
0
      op <<= 16;
18104
0
      Value |= op;
18105
0
      break;
18106
0
    }
18107
0
    case AArch64::LD1i8:
18108
0
    case AArch64::LD2i8:
18109
0
    case AArch64::LD3i8:
18110
0
    case AArch64::LD4i8: {
18111
      // op: Vt
18112
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
18113
0
      op &= UINT64_C(31);
18114
0
      Value |= op;
18115
      // op: Rn
18116
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18117
0
      op &= UINT64_C(31);
18118
0
      op <<= 5;
18119
0
      Value |= op;
18120
      // op: idx
18121
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18122
0
      Value |= (op & UINT64_C(8)) << 27;
18123
0
      Value |= (op & UINT64_C(7)) << 10;
18124
0
      break;
18125
0
    }
18126
0
    case AArch64::ST1i8_POST:
18127
0
    case AArch64::ST2i8_POST:
18128
0
    case AArch64::ST3i8_POST:
18129
0
    case AArch64::ST4i8_POST: {
18130
      // op: Vt
18131
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
18132
0
      op &= UINT64_C(31);
18133
0
      Value |= op;
18134
      // op: Rn
18135
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18136
0
      op &= UINT64_C(31);
18137
0
      op <<= 5;
18138
0
      Value |= op;
18139
      // op: idx
18140
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18141
0
      Value |= (op & UINT64_C(8)) << 27;
18142
0
      Value |= (op & UINT64_C(7)) << 10;
18143
      // op: Xm
18144
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
18145
0
      op &= UINT64_C(31);
18146
0
      op <<= 16;
18147
0
      Value |= op;
18148
0
      break;
18149
0
    }
18150
0
    case AArch64::LD1i64:
18151
0
    case AArch64::LD2i64:
18152
0
    case AArch64::LD3i64:
18153
0
    case AArch64::LD4i64: {
18154
      // op: Vt
18155
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
18156
0
      op &= UINT64_C(31);
18157
0
      Value |= op;
18158
      // op: Rn
18159
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18160
0
      op &= UINT64_C(31);
18161
0
      op <<= 5;
18162
0
      Value |= op;
18163
      // op: idx
18164
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18165
0
      op &= UINT64_C(1);
18166
0
      op <<= 30;
18167
0
      Value |= op;
18168
0
      break;
18169
0
    }
18170
0
    case AArch64::ST1i64_POST:
18171
0
    case AArch64::ST2i64_POST:
18172
0
    case AArch64::ST3i64_POST:
18173
0
    case AArch64::ST4i64_POST: {
18174
      // op: Vt
18175
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
18176
0
      op &= UINT64_C(31);
18177
0
      Value |= op;
18178
      // op: Rn
18179
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18180
0
      op &= UINT64_C(31);
18181
0
      op <<= 5;
18182
0
      Value |= op;
18183
      // op: idx
18184
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18185
0
      op &= UINT64_C(1);
18186
0
      op <<= 30;
18187
0
      Value |= op;
18188
      // op: Xm
18189
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
18190
0
      op &= UINT64_C(31);
18191
0
      op <<= 16;
18192
0
      Value |= op;
18193
0
      break;
18194
0
    }
18195
0
    case AArch64::LD1i32_POST:
18196
0
    case AArch64::LD2i32_POST:
18197
0
    case AArch64::LD3i32_POST:
18198
0
    case AArch64::LD4i32_POST: {
18199
      // op: Vt
18200
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18201
0
      op &= UINT64_C(31);
18202
0
      Value |= op;
18203
      // op: Rn
18204
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
18205
0
      op &= UINT64_C(31);
18206
0
      op <<= 5;
18207
0
      Value |= op;
18208
      // op: idx
18209
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18210
0
      Value |= (op & UINT64_C(2)) << 29;
18211
0
      Value |= (op & UINT64_C(1)) << 12;
18212
      // op: Xm
18213
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
18214
0
      op &= UINT64_C(31);
18215
0
      op <<= 16;
18216
0
      Value |= op;
18217
0
      break;
18218
0
    }
18219
0
    case AArch64::LD1i16_POST:
18220
0
    case AArch64::LD2i16_POST:
18221
0
    case AArch64::LD3i16_POST:
18222
0
    case AArch64::LD4i16_POST: {
18223
      // op: Vt
18224
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18225
0
      op &= UINT64_C(31);
18226
0
      Value |= op;
18227
      // op: Rn
18228
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
18229
0
      op &= UINT64_C(31);
18230
0
      op <<= 5;
18231
0
      Value |= op;
18232
      // op: idx
18233
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18234
0
      Value |= (op & UINT64_C(4)) << 28;
18235
0
      Value |= (op & UINT64_C(3)) << 11;
18236
      // op: Xm
18237
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
18238
0
      op &= UINT64_C(31);
18239
0
      op <<= 16;
18240
0
      Value |= op;
18241
0
      break;
18242
0
    }
18243
0
    case AArch64::LD1i8_POST:
18244
0
    case AArch64::LD2i8_POST:
18245
0
    case AArch64::LD3i8_POST:
18246
0
    case AArch64::LD4i8_POST: {
18247
      // op: Vt
18248
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18249
0
      op &= UINT64_C(31);
18250
0
      Value |= op;
18251
      // op: Rn
18252
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
18253
0
      op &= UINT64_C(31);
18254
0
      op <<= 5;
18255
0
      Value |= op;
18256
      // op: idx
18257
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18258
0
      Value |= (op & UINT64_C(8)) << 27;
18259
0
      Value |= (op & UINT64_C(7)) << 10;
18260
      // op: Xm
18261
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
18262
0
      op &= UINT64_C(31);
18263
0
      op <<= 16;
18264
0
      Value |= op;
18265
0
      break;
18266
0
    }
18267
0
    case AArch64::LD1i64_POST:
18268
0
    case AArch64::LD2i64_POST:
18269
0
    case AArch64::LD3i64_POST:
18270
0
    case AArch64::LD4i64_POST: {
18271
      // op: Vt
18272
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18273
0
      op &= UINT64_C(31);
18274
0
      Value |= op;
18275
      // op: Rn
18276
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
18277
0
      op &= UINT64_C(31);
18278
0
      op <<= 5;
18279
0
      Value |= op;
18280
      // op: idx
18281
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18282
0
      op &= UINT64_C(1);
18283
0
      op <<= 30;
18284
0
      Value |= op;
18285
      // op: Xm
18286
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
18287
0
      op &= UINT64_C(31);
18288
0
      op <<= 16;
18289
0
      Value |= op;
18290
0
      break;
18291
0
    }
18292
0
    case AArch64::STLXRB:
18293
0
    case AArch64::STLXRH:
18294
0
    case AArch64::STLXRW:
18295
0
    case AArch64::STLXRX:
18296
0
    case AArch64::STXRB:
18297
0
    case AArch64::STXRH:
18298
0
    case AArch64::STXRW:
18299
0
    case AArch64::STXRX: {
18300
      // op: Ws
18301
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
18302
0
      op &= UINT64_C(31);
18303
0
      op <<= 16;
18304
0
      Value |= op;
18305
      // op: Rt
18306
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
18307
0
      op &= UINT64_C(31);
18308
0
      Value |= op;
18309
      // op: Rn
18310
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18311
0
      op &= UINT64_C(31);
18312
0
      op <<= 5;
18313
0
      Value |= op;
18314
0
      Value = fixLoadStoreExclusive<1,0>(MI, Value, STI);
18315
0
      break;
18316
0
    }
18317
0
    case AArch64::STLXPW:
18318
0
    case AArch64::STLXPX:
18319
0
    case AArch64::STXPW:
18320
0
    case AArch64::STXPX: {
18321
      // op: Ws
18322
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
18323
0
      op &= UINT64_C(31);
18324
0
      op <<= 16;
18325
0
      Value |= op;
18326
      // op: Rt
18327
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
18328
0
      op &= UINT64_C(31);
18329
0
      Value |= op;
18330
      // op: Rt2
18331
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18332
0
      op &= UINT64_C(31);
18333
0
      op <<= 10;
18334
0
      Value |= op;
18335
      // op: Rn
18336
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18337
0
      op &= UINT64_C(31);
18338
0
      op <<= 5;
18339
0
      Value |= op;
18340
0
      break;
18341
0
    }
18342
0
    case AArch64::ADR:
18343
0
    case AArch64::ADRP: {
18344
      // op: Xd
18345
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
18346
0
      op &= UINT64_C(31);
18347
0
      Value |= op;
18348
      // op: label
18349
0
      op = getAdrLabelOpValue(MI, 1, Fixups, STI);
18350
0
      Value |= (op & UINT64_C(3)) << 29;
18351
0
      Value |= (op & UINT64_C(2097148)) << 3;
18352
0
      break;
18353
0
    }
18354
0
    case AArch64::MOVA_2ZMXI_H_H:
18355
0
    case AArch64::MOVA_2ZMXI_V_H: {
18356
      // op: Zd
18357
0
      op = EncodeRegAsMultipleOf<2>(MI, 0, Fixups, STI);
18358
0
      op &= UINT64_C(15);
18359
0
      op <<= 1;
18360
0
      Value |= op;
18361
      // op: Rs
18362
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
18363
0
      op &= UINT64_C(3);
18364
0
      op <<= 13;
18365
0
      Value |= op;
18366
      // op: ZAn
18367
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
18368
0
      op &= UINT64_C(1);
18369
0
      op <<= 7;
18370
0
      Value |= op;
18371
      // op: imm
18372
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18373
0
      op &= UINT64_C(3);
18374
0
      op <<= 5;
18375
0
      Value |= op;
18376
0
      break;
18377
0
    }
18378
0
    case AArch64::MOVA_2ZMXI_H_S:
18379
0
    case AArch64::MOVA_2ZMXI_V_S: {
18380
      // op: Zd
18381
0
      op = EncodeRegAsMultipleOf<2>(MI, 0, Fixups, STI);
18382
0
      op &= UINT64_C(15);
18383
0
      op <<= 1;
18384
0
      Value |= op;
18385
      // op: Rs
18386
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
18387
0
      op &= UINT64_C(3);
18388
0
      op <<= 13;
18389
0
      Value |= op;
18390
      // op: ZAn
18391
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
18392
0
      op &= UINT64_C(3);
18393
0
      op <<= 6;
18394
0
      Value |= op;
18395
      // op: imm
18396
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18397
0
      op &= UINT64_C(1);
18398
0
      op <<= 5;
18399
0
      Value |= op;
18400
0
      break;
18401
0
    }
18402
0
    case AArch64::MOVA_2ZMXI_H_D:
18403
0
    case AArch64::MOVA_2ZMXI_V_D: {
18404
      // op: Zd
18405
0
      op = EncodeRegAsMultipleOf<2>(MI, 0, Fixups, STI);
18406
0
      op &= UINT64_C(15);
18407
0
      op <<= 1;
18408
0
      Value |= op;
18409
      // op: Rs
18410
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
18411
0
      op &= UINT64_C(3);
18412
0
      op <<= 13;
18413
0
      Value |= op;
18414
      // op: ZAn
18415
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
18416
0
      op &= UINT64_C(7);
18417
0
      op <<= 5;
18418
0
      Value |= op;
18419
0
      break;
18420
0
    }
18421
0
    case AArch64::MOVA_2ZMXI_H_B:
18422
0
    case AArch64::MOVA_2ZMXI_V_B: {
18423
      // op: Zd
18424
0
      op = EncodeRegAsMultipleOf<2>(MI, 0, Fixups, STI);
18425
0
      op &= UINT64_C(15);
18426
0
      op <<= 1;
18427
0
      Value |= op;
18428
      // op: Rs
18429
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
18430
0
      op &= UINT64_C(3);
18431
0
      op <<= 13;
18432
0
      Value |= op;
18433
      // op: imm
18434
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18435
0
      op &= UINT64_C(7);
18436
0
      op <<= 5;
18437
0
      Value |= op;
18438
0
      break;
18439
0
    }
18440
0
    case AArch64::MOVAZ_2ZMI_H_H:
18441
0
    case AArch64::MOVAZ_2ZMI_V_H: {
18442
      // op: Zd
18443
0
      op = EncodeRegAsMultipleOf<2>(MI, 0, Fixups, STI);
18444
0
      op &= UINT64_C(15);
18445
0
      op <<= 1;
18446
0
      Value |= op;
18447
      // op: Rs
18448
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
18449
0
      op &= UINT64_C(3);
18450
0
      op <<= 13;
18451
0
      Value |= op;
18452
      // op: ZAn
18453
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18454
0
      op &= UINT64_C(1);
18455
0
      op <<= 7;
18456
0
      Value |= op;
18457
      // op: imm
18458
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
18459
0
      op &= UINT64_C(3);
18460
0
      op <<= 5;
18461
0
      Value |= op;
18462
0
      break;
18463
0
    }
18464
0
    case AArch64::MOVAZ_2ZMI_H_S:
18465
0
    case AArch64::MOVAZ_2ZMI_V_S: {
18466
      // op: Zd
18467
0
      op = EncodeRegAsMultipleOf<2>(MI, 0, Fixups, STI);
18468
0
      op &= UINT64_C(15);
18469
0
      op <<= 1;
18470
0
      Value |= op;
18471
      // op: Rs
18472
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
18473
0
      op &= UINT64_C(3);
18474
0
      op <<= 13;
18475
0
      Value |= op;
18476
      // op: ZAn
18477
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18478
0
      op &= UINT64_C(3);
18479
0
      op <<= 6;
18480
0
      Value |= op;
18481
      // op: imm
18482
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
18483
0
      op &= UINT64_C(1);
18484
0
      op <<= 5;
18485
0
      Value |= op;
18486
0
      break;
18487
0
    }
18488
0
    case AArch64::MOVAZ_2ZMI_H_D:
18489
0
    case AArch64::MOVAZ_2ZMI_V_D: {
18490
      // op: Zd
18491
0
      op = EncodeRegAsMultipleOf<2>(MI, 0, Fixups, STI);
18492
0
      op &= UINT64_C(15);
18493
0
      op <<= 1;
18494
0
      Value |= op;
18495
      // op: Rs
18496
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
18497
0
      op &= UINT64_C(3);
18498
0
      op <<= 13;
18499
0
      Value |= op;
18500
      // op: ZAn
18501
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18502
0
      op &= UINT64_C(7);
18503
0
      op <<= 5;
18504
0
      Value |= op;
18505
0
      break;
18506
0
    }
18507
0
    case AArch64::MOVAZ_2ZMI_H_B:
18508
0
    case AArch64::MOVAZ_2ZMI_V_B: {
18509
      // op: Zd
18510
0
      op = EncodeRegAsMultipleOf<2>(MI, 0, Fixups, STI);
18511
0
      op &= UINT64_C(15);
18512
0
      op <<= 1;
18513
0
      Value |= op;
18514
      // op: Rs
18515
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
18516
0
      op &= UINT64_C(3);
18517
0
      op <<= 13;
18518
0
      Value |= op;
18519
      // op: imm
18520
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
18521
0
      op &= UINT64_C(7);
18522
0
      op <<= 5;
18523
0
      Value |= op;
18524
0
      break;
18525
0
    }
18526
0
    case AArch64::UZP_VG2_2ZZZ_B:
18527
0
    case AArch64::UZP_VG2_2ZZZ_D:
18528
0
    case AArch64::UZP_VG2_2ZZZ_H:
18529
0
    case AArch64::UZP_VG2_2ZZZ_Q:
18530
0
    case AArch64::UZP_VG2_2ZZZ_S:
18531
0
    case AArch64::ZIP_VG2_2ZZZ_B:
18532
0
    case AArch64::ZIP_VG2_2ZZZ_D:
18533
0
    case AArch64::ZIP_VG2_2ZZZ_H:
18534
0
    case AArch64::ZIP_VG2_2ZZZ_Q:
18535
0
    case AArch64::ZIP_VG2_2ZZZ_S: {
18536
      // op: Zd
18537
0
      op = EncodeRegAsMultipleOf<2>(MI, 0, Fixups, STI);
18538
0
      op &= UINT64_C(15);
18539
0
      op <<= 1;
18540
0
      Value |= op;
18541
      // op: Zm
18542
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18543
0
      op &= UINT64_C(31);
18544
0
      op <<= 16;
18545
0
      Value |= op;
18546
      // op: Zn
18547
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
18548
0
      op &= UINT64_C(31);
18549
0
      op <<= 5;
18550
0
      Value |= op;
18551
0
      break;
18552
0
    }
18553
0
    case AArch64::MOVA_4ZMXI_H_H:
18554
0
    case AArch64::MOVA_4ZMXI_V_H: {
18555
      // op: Zd
18556
0
      op = EncodeRegAsMultipleOf<4>(MI, 0, Fixups, STI);
18557
0
      op &= UINT64_C(7);
18558
0
      op <<= 2;
18559
0
      Value |= op;
18560
      // op: Rs
18561
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
18562
0
      op &= UINT64_C(3);
18563
0
      op <<= 13;
18564
0
      Value |= op;
18565
      // op: ZAn
18566
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
18567
0
      op &= UINT64_C(1);
18568
0
      op <<= 6;
18569
0
      Value |= op;
18570
      // op: imm
18571
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18572
0
      op &= UINT64_C(1);
18573
0
      op <<= 5;
18574
0
      Value |= op;
18575
0
      break;
18576
0
    }
18577
0
    case AArch64::MOVA_4ZMXI_H_S:
18578
0
    case AArch64::MOVA_4ZMXI_V_S: {
18579
      // op: Zd
18580
0
      op = EncodeRegAsMultipleOf<4>(MI, 0, Fixups, STI);
18581
0
      op &= UINT64_C(7);
18582
0
      op <<= 2;
18583
0
      Value |= op;
18584
      // op: Rs
18585
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
18586
0
      op &= UINT64_C(3);
18587
0
      op <<= 13;
18588
0
      Value |= op;
18589
      // op: ZAn
18590
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
18591
0
      op &= UINT64_C(3);
18592
0
      op <<= 5;
18593
0
      Value |= op;
18594
0
      break;
18595
0
    }
18596
0
    case AArch64::MOVA_4ZMXI_H_D:
18597
0
    case AArch64::MOVA_4ZMXI_V_D: {
18598
      // op: Zd
18599
0
      op = EncodeRegAsMultipleOf<4>(MI, 0, Fixups, STI);
18600
0
      op &= UINT64_C(7);
18601
0
      op <<= 2;
18602
0
      Value |= op;
18603
      // op: Rs
18604
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
18605
0
      op &= UINT64_C(3);
18606
0
      op <<= 13;
18607
0
      Value |= op;
18608
      // op: ZAn
18609
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
18610
0
      op &= UINT64_C(7);
18611
0
      op <<= 5;
18612
0
      Value |= op;
18613
0
      break;
18614
0
    }
18615
0
    case AArch64::MOVA_4ZMXI_H_B:
18616
0
    case AArch64::MOVA_4ZMXI_V_B: {
18617
      // op: Zd
18618
0
      op = EncodeRegAsMultipleOf<4>(MI, 0, Fixups, STI);
18619
0
      op &= UINT64_C(7);
18620
0
      op <<= 2;
18621
0
      Value |= op;
18622
      // op: Rs
18623
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
18624
0
      op &= UINT64_C(3);
18625
0
      op <<= 13;
18626
0
      Value |= op;
18627
      // op: imm
18628
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18629
0
      op &= UINT64_C(3);
18630
0
      op <<= 5;
18631
0
      Value |= op;
18632
0
      break;
18633
0
    }
18634
0
    case AArch64::MOVAZ_4ZMI_H_H:
18635
0
    case AArch64::MOVAZ_4ZMI_V_H: {
18636
      // op: Zd
18637
0
      op = EncodeRegAsMultipleOf<4>(MI, 0, Fixups, STI);
18638
0
      op &= UINT64_C(7);
18639
0
      op <<= 2;
18640
0
      Value |= op;
18641
      // op: Rs
18642
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
18643
0
      op &= UINT64_C(3);
18644
0
      op <<= 13;
18645
0
      Value |= op;
18646
      // op: ZAn
18647
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18648
0
      op &= UINT64_C(1);
18649
0
      op <<= 6;
18650
0
      Value |= op;
18651
      // op: imm
18652
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
18653
0
      op &= UINT64_C(1);
18654
0
      op <<= 5;
18655
0
      Value |= op;
18656
0
      break;
18657
0
    }
18658
0
    case AArch64::MOVAZ_4ZMI_H_S:
18659
0
    case AArch64::MOVAZ_4ZMI_V_S: {
18660
      // op: Zd
18661
0
      op = EncodeRegAsMultipleOf<4>(MI, 0, Fixups, STI);
18662
0
      op &= UINT64_C(7);
18663
0
      op <<= 2;
18664
0
      Value |= op;
18665
      // op: Rs
18666
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
18667
0
      op &= UINT64_C(3);
18668
0
      op <<= 13;
18669
0
      Value |= op;
18670
      // op: ZAn
18671
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18672
0
      op &= UINT64_C(3);
18673
0
      op <<= 5;
18674
0
      Value |= op;
18675
0
      break;
18676
0
    }
18677
0
    case AArch64::MOVAZ_4ZMI_H_D:
18678
0
    case AArch64::MOVAZ_4ZMI_V_D: {
18679
      // op: Zd
18680
0
      op = EncodeRegAsMultipleOf<4>(MI, 0, Fixups, STI);
18681
0
      op &= UINT64_C(7);
18682
0
      op <<= 2;
18683
0
      Value |= op;
18684
      // op: Rs
18685
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
18686
0
      op &= UINT64_C(3);
18687
0
      op <<= 13;
18688
0
      Value |= op;
18689
      // op: ZAn
18690
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18691
0
      op &= UINT64_C(7);
18692
0
      op <<= 5;
18693
0
      Value |= op;
18694
0
      break;
18695
0
    }
18696
0
    case AArch64::MOVAZ_4ZMI_H_B:
18697
0
    case AArch64::MOVAZ_4ZMI_V_B: {
18698
      // op: Zd
18699
0
      op = EncodeRegAsMultipleOf<4>(MI, 0, Fixups, STI);
18700
0
      op &= UINT64_C(7);
18701
0
      op <<= 2;
18702
0
      Value |= op;
18703
      // op: Rs
18704
0
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
18705
0
      op &= UINT64_C(3);
18706
0
      op <<= 13;
18707
0
      Value |= op;
18708
      // op: imm
18709
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
18710
0
      op &= UINT64_C(3);
18711
0
      op <<= 5;
18712
0
      Value |= op;
18713
0
      break;
18714
0
    }
18715
0
    case AArch64::CPY_ZPzI_B:
18716
0
    case AArch64::CPY_ZPzI_D:
18717
0
    case AArch64::CPY_ZPzI_H:
18718
0
    case AArch64::CPY_ZPzI_S: {
18719
      // op: Zd
18720
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
18721
0
      op &= UINT64_C(31);
18722
0
      Value |= op;
18723
      // op: Pg
18724
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
18725
0
      op &= UINT64_C(15);
18726
0
      op <<= 16;
18727
0
      Value |= op;
18728
      // op: imm
18729
0
      op = getImm8OptLsl(MI, 2, Fixups, STI);
18730
0
      op &= UINT64_C(511);
18731
0
      op <<= 5;
18732
0
      Value |= op;
18733
0
      break;
18734
0
    }
18735
0
    case AArch64::CPY_ZPmI_B:
18736
0
    case AArch64::CPY_ZPmI_D:
18737
0
    case AArch64::CPY_ZPmI_H:
18738
0
    case AArch64::CPY_ZPmI_S: {
18739
      // op: Zd
18740
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
18741
0
      op &= UINT64_C(31);
18742
0
      Value |= op;
18743
      // op: Pg
18744
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18745
0
      op &= UINT64_C(15);
18746
0
      op <<= 16;
18747
0
      Value |= op;
18748
      // op: imm
18749
0
      op = getImm8OptLsl(MI, 3, Fixups, STI);
18750
0
      op &= UINT64_C(511);
18751
0
      op <<= 5;
18752
0
      Value |= op;
18753
0
      break;
18754
0
    }
18755
0
    case AArch64::BFCVTNT_ZPmZ:
18756
0
    case AArch64::BFCVT_ZPmZ:
18757
0
    case AArch64::RBIT_ZPmZ_B:
18758
0
    case AArch64::RBIT_ZPmZ_D:
18759
0
    case AArch64::RBIT_ZPmZ_H:
18760
0
    case AArch64::RBIT_ZPmZ_S:
18761
0
    case AArch64::REVB_ZPmZ_D:
18762
0
    case AArch64::REVB_ZPmZ_H:
18763
0
    case AArch64::REVB_ZPmZ_S:
18764
0
    case AArch64::REVD_ZPmZ:
18765
0
    case AArch64::REVH_ZPmZ_D:
18766
0
    case AArch64::REVH_ZPmZ_S:
18767
0
    case AArch64::REVW_ZPmZ_D: {
18768
      // op: Zd
18769
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
18770
0
      op &= UINT64_C(31);
18771
0
      Value |= op;
18772
      // op: Pg
18773
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18774
0
      op &= UINT64_C(7);
18775
0
      op <<= 10;
18776
0
      Value |= op;
18777
      // op: Zn
18778
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18779
0
      op &= UINT64_C(31);
18780
0
      op <<= 5;
18781
0
      Value |= op;
18782
0
      break;
18783
0
    }
18784
0
    case AArch64::PMOV_ZIP_B: {
18785
      // op: Zd
18786
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
18787
0
      op &= UINT64_C(31);
18788
0
      Value |= op;
18789
      // op: Pn
18790
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18791
0
      op &= UINT64_C(15);
18792
0
      op <<= 5;
18793
0
      Value |= op;
18794
0
      break;
18795
0
    }
18796
0
    case AArch64::PMOV_ZIP_D: {
18797
      // op: Zd
18798
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
18799
0
      op &= UINT64_C(31);
18800
0
      Value |= op;
18801
      // op: Pn
18802
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18803
0
      op &= UINT64_C(15);
18804
0
      op <<= 5;
18805
0
      Value |= op;
18806
      // op: index
18807
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18808
0
      Value |= (op & UINT64_C(4)) << 20;
18809
0
      Value |= (op & UINT64_C(3)) << 17;
18810
0
      break;
18811
0
    }
18812
0
    case AArch64::PMOV_ZIP_H: {
18813
      // op: Zd
18814
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
18815
0
      op &= UINT64_C(31);
18816
0
      Value |= op;
18817
      // op: Pn
18818
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18819
0
      op &= UINT64_C(15);
18820
0
      op <<= 5;
18821
0
      Value |= op;
18822
      // op: index
18823
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18824
0
      op &= UINT64_C(1);
18825
0
      op <<= 17;
18826
0
      Value |= op;
18827
0
      break;
18828
0
    }
18829
0
    case AArch64::PMOV_ZIP_S: {
18830
      // op: Zd
18831
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
18832
0
      op &= UINT64_C(31);
18833
0
      Value |= op;
18834
      // op: Pn
18835
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
18836
0
      op &= UINT64_C(15);
18837
0
      op <<= 5;
18838
0
      Value |= op;
18839
      // op: index
18840
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18841
0
      op &= UINT64_C(3);
18842
0
      op <<= 17;
18843
0
      Value |= op;
18844
0
      break;
18845
0
    }
18846
0
    case AArch64::INDEX_RR_B:
18847
0
    case AArch64::INDEX_RR_D:
18848
0
    case AArch64::INDEX_RR_H:
18849
0
    case AArch64::INDEX_RR_S: {
18850
      // op: Zd
18851
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
18852
0
      op &= UINT64_C(31);
18853
0
      Value |= op;
18854
      // op: Rm
18855
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18856
0
      op &= UINT64_C(31);
18857
0
      op <<= 16;
18858
0
      Value |= op;
18859
      // op: Rn
18860
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
18861
0
      op &= UINT64_C(31);
18862
0
      op <<= 5;
18863
0
      Value |= op;
18864
0
      break;
18865
0
    }
18866
0
    case AArch64::ADD_ZZZ_B:
18867
0
    case AArch64::ADD_ZZZ_CPA:
18868
0
    case AArch64::ADD_ZZZ_D:
18869
0
    case AArch64::ADD_ZZZ_H:
18870
0
    case AArch64::ADD_ZZZ_S:
18871
0
    case AArch64::AND_ZZZ:
18872
0
    case AArch64::ASR_WIDE_ZZZ_B:
18873
0
    case AArch64::ASR_WIDE_ZZZ_H:
18874
0
    case AArch64::ASR_WIDE_ZZZ_S:
18875
0
    case AArch64::BFADD_ZZZ:
18876
0
    case AArch64::BFMUL_ZZZ:
18877
0
    case AArch64::BFSUB_ZZZ:
18878
0
    case AArch64::BIC_ZZZ:
18879
0
    case AArch64::EOR_ZZZ:
18880
0
    case AArch64::FADD_ZZZ_D:
18881
0
    case AArch64::FADD_ZZZ_H:
18882
0
    case AArch64::FADD_ZZZ_S:
18883
0
    case AArch64::FMUL_ZZZ_D:
18884
0
    case AArch64::FMUL_ZZZ_H:
18885
0
    case AArch64::FMUL_ZZZ_S:
18886
0
    case AArch64::FRECPS_ZZZ_D:
18887
0
    case AArch64::FRECPS_ZZZ_H:
18888
0
    case AArch64::FRECPS_ZZZ_S:
18889
0
    case AArch64::FRSQRTS_ZZZ_D:
18890
0
    case AArch64::FRSQRTS_ZZZ_H:
18891
0
    case AArch64::FRSQRTS_ZZZ_S:
18892
0
    case AArch64::FSUB_ZZZ_D:
18893
0
    case AArch64::FSUB_ZZZ_H:
18894
0
    case AArch64::FSUB_ZZZ_S:
18895
0
    case AArch64::FTSMUL_ZZZ_D:
18896
0
    case AArch64::FTSMUL_ZZZ_H:
18897
0
    case AArch64::FTSMUL_ZZZ_S:
18898
0
    case AArch64::FTSSEL_ZZZ_D:
18899
0
    case AArch64::FTSSEL_ZZZ_H:
18900
0
    case AArch64::FTSSEL_ZZZ_S:
18901
0
    case AArch64::LSL_WIDE_ZZZ_B:
18902
0
    case AArch64::LSL_WIDE_ZZZ_H:
18903
0
    case AArch64::LSL_WIDE_ZZZ_S:
18904
0
    case AArch64::LSR_WIDE_ZZZ_B:
18905
0
    case AArch64::LSR_WIDE_ZZZ_H:
18906
0
    case AArch64::LSR_WIDE_ZZZ_S:
18907
0
    case AArch64::MUL_ZZZ_B:
18908
0
    case AArch64::MUL_ZZZ_D:
18909
0
    case AArch64::MUL_ZZZ_H:
18910
0
    case AArch64::MUL_ZZZ_S:
18911
0
    case AArch64::ORR_ZZZ:
18912
0
    case AArch64::PMUL_ZZZ_B:
18913
0
    case AArch64::SMULH_ZZZ_B:
18914
0
    case AArch64::SMULH_ZZZ_D:
18915
0
    case AArch64::SMULH_ZZZ_H:
18916
0
    case AArch64::SMULH_ZZZ_S:
18917
0
    case AArch64::SQADD_ZZZ_B:
18918
0
    case AArch64::SQADD_ZZZ_D:
18919
0
    case AArch64::SQADD_ZZZ_H:
18920
0
    case AArch64::SQADD_ZZZ_S:
18921
0
    case AArch64::SQDMULH_ZZZ_B:
18922
0
    case AArch64::SQDMULH_ZZZ_D:
18923
0
    case AArch64::SQDMULH_ZZZ_H:
18924
0
    case AArch64::SQDMULH_ZZZ_S:
18925
0
    case AArch64::SQRDMULH_ZZZ_B:
18926
0
    case AArch64::SQRDMULH_ZZZ_D:
18927
0
    case AArch64::SQRDMULH_ZZZ_H:
18928
0
    case AArch64::SQRDMULH_ZZZ_S:
18929
0
    case AArch64::SQSUB_ZZZ_B:
18930
0
    case AArch64::SQSUB_ZZZ_D:
18931
0
    case AArch64::SQSUB_ZZZ_H:
18932
0
    case AArch64::SQSUB_ZZZ_S:
18933
0
    case AArch64::SUB_ZZZ_B:
18934
0
    case AArch64::SUB_ZZZ_CPA:
18935
0
    case AArch64::SUB_ZZZ_D:
18936
0
    case AArch64::SUB_ZZZ_H:
18937
0
    case AArch64::SUB_ZZZ_S:
18938
0
    case AArch64::TBL_ZZZZ_B:
18939
0
    case AArch64::TBL_ZZZZ_D:
18940
0
    case AArch64::TBL_ZZZZ_H:
18941
0
    case AArch64::TBL_ZZZZ_S:
18942
0
    case AArch64::TBL_ZZZ_B:
18943
0
    case AArch64::TBL_ZZZ_D:
18944
0
    case AArch64::TBL_ZZZ_H:
18945
0
    case AArch64::TBL_ZZZ_S:
18946
0
    case AArch64::TRN1_ZZZ_B:
18947
0
    case AArch64::TRN1_ZZZ_D:
18948
0
    case AArch64::TRN1_ZZZ_H:
18949
0
    case AArch64::TRN1_ZZZ_Q:
18950
0
    case AArch64::TRN1_ZZZ_S:
18951
0
    case AArch64::TRN2_ZZZ_B:
18952
0
    case AArch64::TRN2_ZZZ_D:
18953
0
    case AArch64::TRN2_ZZZ_H:
18954
0
    case AArch64::TRN2_ZZZ_Q:
18955
0
    case AArch64::TRN2_ZZZ_S:
18956
0
    case AArch64::UMULH_ZZZ_B:
18957
0
    case AArch64::UMULH_ZZZ_D:
18958
0
    case AArch64::UMULH_ZZZ_H:
18959
0
    case AArch64::UMULH_ZZZ_S:
18960
0
    case AArch64::UQADD_ZZZ_B:
18961
0
    case AArch64::UQADD_ZZZ_D:
18962
0
    case AArch64::UQADD_ZZZ_H:
18963
0
    case AArch64::UQADD_ZZZ_S:
18964
0
    case AArch64::UQSUB_ZZZ_B:
18965
0
    case AArch64::UQSUB_ZZZ_D:
18966
0
    case AArch64::UQSUB_ZZZ_H:
18967
0
    case AArch64::UQSUB_ZZZ_S:
18968
0
    case AArch64::UZP1_ZZZ_B:
18969
0
    case AArch64::UZP1_ZZZ_D:
18970
0
    case AArch64::UZP1_ZZZ_H:
18971
0
    case AArch64::UZP1_ZZZ_Q:
18972
0
    case AArch64::UZP1_ZZZ_S:
18973
0
    case AArch64::UZP2_ZZZ_B:
18974
0
    case AArch64::UZP2_ZZZ_D:
18975
0
    case AArch64::UZP2_ZZZ_H:
18976
0
    case AArch64::UZP2_ZZZ_Q:
18977
0
    case AArch64::UZP2_ZZZ_S:
18978
0
    case AArch64::ZIP1_ZZZ_B:
18979
0
    case AArch64::ZIP1_ZZZ_D:
18980
0
    case AArch64::ZIP1_ZZZ_H:
18981
0
    case AArch64::ZIP1_ZZZ_Q:
18982
0
    case AArch64::ZIP1_ZZZ_S:
18983
0
    case AArch64::ZIP2_ZZZ_B:
18984
0
    case AArch64::ZIP2_ZZZ_D:
18985
0
    case AArch64::ZIP2_ZZZ_H:
18986
0
    case AArch64::ZIP2_ZZZ_Q:
18987
0
    case AArch64::ZIP2_ZZZ_S: {
18988
      // op: Zd
18989
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
18990
0
      op &= UINT64_C(31);
18991
0
      Value |= op;
18992
      // op: Zm
18993
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
18994
0
      op &= UINT64_C(31);
18995
0
      op <<= 16;
18996
0
      Value |= op;
18997
      // op: Zn
18998
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
18999
0
      op &= UINT64_C(31);
19000
0
      op <<= 5;
19001
0
      Value |= op;
19002
0
      break;
19003
0
    }
19004
0
    case AArch64::TBXQ_ZZZ_B:
19005
0
    case AArch64::TBXQ_ZZZ_D:
19006
0
    case AArch64::TBXQ_ZZZ_H:
19007
0
    case AArch64::TBXQ_ZZZ_S:
19008
0
    case AArch64::TBX_ZZZ_B:
19009
0
    case AArch64::TBX_ZZZ_D:
19010
0
    case AArch64::TBX_ZZZ_H:
19011
0
    case AArch64::TBX_ZZZ_S: {
19012
      // op: Zd
19013
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19014
0
      op &= UINT64_C(31);
19015
0
      Value |= op;
19016
      // op: Zm
19017
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
19018
0
      op &= UINT64_C(31);
19019
0
      op <<= 16;
19020
0
      Value |= op;
19021
      // op: Zn
19022
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19023
0
      op &= UINT64_C(31);
19024
0
      op <<= 5;
19025
0
      Value |= op;
19026
0
      break;
19027
0
    }
19028
0
    case AArch64::BFCVTN_Z2Z_HtoB:
19029
0
    case AArch64::FCVTNB_Z2Z_StoB:
19030
0
    case AArch64::FCVTNT_Z2Z_StoB:
19031
0
    case AArch64::FCVTN_Z2Z_HtoB:
19032
0
    case AArch64::SQCVTN_Z2Z_StoH:
19033
0
    case AArch64::SQCVTUN_Z2Z_StoH:
19034
0
    case AArch64::UQCVTN_Z2Z_StoH: {
19035
      // op: Zd
19036
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19037
0
      op &= UINT64_C(31);
19038
0
      Value |= op;
19039
      // op: Zn
19040
0
      op = EncodeRegAsMultipleOf<2>(MI, 1, Fixups, STI);
19041
0
      op &= UINT64_C(15);
19042
0
      op <<= 6;
19043
0
      Value |= op;
19044
0
      break;
19045
0
    }
19046
0
    case AArch64::SQRSHRN_Z2ZI_StoH:
19047
0
    case AArch64::SQRSHRUN_Z2ZI_StoH:
19048
0
    case AArch64::UQRSHRN_Z2ZI_StoH: {
19049
      // op: Zd
19050
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19051
0
      op &= UINT64_C(31);
19052
0
      Value |= op;
19053
      // op: Zn
19054
0
      op = EncodeRegAsMultipleOf<2>(MI, 1, Fixups, STI);
19055
0
      op &= UINT64_C(15);
19056
0
      op <<= 6;
19057
0
      Value |= op;
19058
      // op: imm4
19059
0
      op = getVecShiftR16OpValue(MI, 2, Fixups, STI);
19060
0
      op &= UINT64_C(15);
19061
0
      op <<= 16;
19062
0
      Value |= op;
19063
0
      break;
19064
0
    }
19065
0
    case AArch64::BF1CVTLT_ZZ_BtoH:
19066
0
    case AArch64::BF1CVT_ZZ_BtoH:
19067
0
    case AArch64::BF2CVTLT_ZZ_BtoH:
19068
0
    case AArch64::BF2CVT_ZZ_BtoH:
19069
0
    case AArch64::F1CVTLT_ZZ_BtoH:
19070
0
    case AArch64::F1CVT_ZZ_BtoH:
19071
0
    case AArch64::F2CVTLT_ZZ_BtoH:
19072
0
    case AArch64::F2CVT_ZZ_BtoH:
19073
0
    case AArch64::FEXPA_ZZ_D:
19074
0
    case AArch64::FEXPA_ZZ_H:
19075
0
    case AArch64::FEXPA_ZZ_S:
19076
0
    case AArch64::FRECPE_ZZ_D:
19077
0
    case AArch64::FRECPE_ZZ_H:
19078
0
    case AArch64::FRECPE_ZZ_S:
19079
0
    case AArch64::FRSQRTE_ZZ_D:
19080
0
    case AArch64::FRSQRTE_ZZ_H:
19081
0
    case AArch64::FRSQRTE_ZZ_S:
19082
0
    case AArch64::MOVPRFX_ZZ:
19083
0
    case AArch64::REV_ZZ_B:
19084
0
    case AArch64::REV_ZZ_D:
19085
0
    case AArch64::REV_ZZ_H:
19086
0
    case AArch64::REV_ZZ_S:
19087
0
    case AArch64::SQXTNB_ZZ_B:
19088
0
    case AArch64::SQXTNB_ZZ_H:
19089
0
    case AArch64::SQXTNB_ZZ_S:
19090
0
    case AArch64::SQXTUNB_ZZ_B:
19091
0
    case AArch64::SQXTUNB_ZZ_H:
19092
0
    case AArch64::SQXTUNB_ZZ_S:
19093
0
    case AArch64::SUNPKHI_ZZ_D:
19094
0
    case AArch64::SUNPKHI_ZZ_H:
19095
0
    case AArch64::SUNPKHI_ZZ_S:
19096
0
    case AArch64::SUNPKLO_ZZ_D:
19097
0
    case AArch64::SUNPKLO_ZZ_H:
19098
0
    case AArch64::SUNPKLO_ZZ_S:
19099
0
    case AArch64::UQXTNB_ZZ_B:
19100
0
    case AArch64::UQXTNB_ZZ_H:
19101
0
    case AArch64::UQXTNB_ZZ_S:
19102
0
    case AArch64::UUNPKHI_ZZ_D:
19103
0
    case AArch64::UUNPKHI_ZZ_H:
19104
0
    case AArch64::UUNPKHI_ZZ_S:
19105
0
    case AArch64::UUNPKLO_ZZ_D:
19106
0
    case AArch64::UUNPKLO_ZZ_H:
19107
0
    case AArch64::UUNPKLO_ZZ_S: {
19108
      // op: Zd
19109
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19110
0
      op &= UINT64_C(31);
19111
0
      Value |= op;
19112
      // op: Zn
19113
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19114
0
      op &= UINT64_C(31);
19115
0
      op <<= 5;
19116
0
      Value |= op;
19117
0
      break;
19118
0
    }
19119
0
    case AArch64::SMULLB_ZZZI_D:
19120
0
    case AArch64::SMULLT_ZZZI_D:
19121
0
    case AArch64::SQDMULLB_ZZZI_D:
19122
0
    case AArch64::SQDMULLT_ZZZI_D:
19123
0
    case AArch64::UMULLB_ZZZI_D:
19124
0
    case AArch64::UMULLT_ZZZI_D: {
19125
      // op: Zd
19126
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19127
0
      op &= UINT64_C(31);
19128
0
      Value |= op;
19129
      // op: Zn
19130
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19131
0
      op &= UINT64_C(31);
19132
0
      op <<= 5;
19133
0
      Value |= op;
19134
      // op: Zm
19135
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19136
0
      op &= UINT64_C(15);
19137
0
      op <<= 16;
19138
0
      Value |= op;
19139
      // op: iop
19140
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
19141
0
      Value |= (op & UINT64_C(2)) << 19;
19142
0
      Value |= (op & UINT64_C(1)) << 11;
19143
0
      break;
19144
0
    }
19145
0
    case AArch64::FMUL_ZZZI_D:
19146
0
    case AArch64::MUL_ZZZI_D:
19147
0
    case AArch64::SQDMULH_ZZZI_D:
19148
0
    case AArch64::SQRDMULH_ZZZI_D: {
19149
      // op: Zd
19150
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19151
0
      op &= UINT64_C(31);
19152
0
      Value |= op;
19153
      // op: Zn
19154
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19155
0
      op &= UINT64_C(31);
19156
0
      op <<= 5;
19157
0
      Value |= op;
19158
      // op: Zm
19159
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19160
0
      op &= UINT64_C(15);
19161
0
      op <<= 16;
19162
0
      Value |= op;
19163
      // op: iop
19164
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
19165
0
      op &= UINT64_C(1);
19166
0
      op <<= 20;
19167
0
      Value |= op;
19168
0
      break;
19169
0
    }
19170
0
    case AArch64::ADDHNB_ZZZ_B:
19171
0
    case AArch64::ADDHNB_ZZZ_H:
19172
0
    case AArch64::ADDHNB_ZZZ_S:
19173
0
    case AArch64::ADR_LSL_ZZZ_D_0:
19174
0
    case AArch64::ADR_LSL_ZZZ_D_1:
19175
0
    case AArch64::ADR_LSL_ZZZ_D_2:
19176
0
    case AArch64::ADR_LSL_ZZZ_D_3:
19177
0
    case AArch64::ADR_LSL_ZZZ_S_0:
19178
0
    case AArch64::ADR_LSL_ZZZ_S_1:
19179
0
    case AArch64::ADR_LSL_ZZZ_S_2:
19180
0
    case AArch64::ADR_LSL_ZZZ_S_3:
19181
0
    case AArch64::ADR_SXTW_ZZZ_D_0:
19182
0
    case AArch64::ADR_SXTW_ZZZ_D_1:
19183
0
    case AArch64::ADR_SXTW_ZZZ_D_2:
19184
0
    case AArch64::ADR_SXTW_ZZZ_D_3:
19185
0
    case AArch64::ADR_UXTW_ZZZ_D_0:
19186
0
    case AArch64::ADR_UXTW_ZZZ_D_1:
19187
0
    case AArch64::ADR_UXTW_ZZZ_D_2:
19188
0
    case AArch64::ADR_UXTW_ZZZ_D_3:
19189
0
    case AArch64::BDEP_ZZZ_B:
19190
0
    case AArch64::BDEP_ZZZ_D:
19191
0
    case AArch64::BDEP_ZZZ_H:
19192
0
    case AArch64::BDEP_ZZZ_S:
19193
0
    case AArch64::BEXT_ZZZ_B:
19194
0
    case AArch64::BEXT_ZZZ_D:
19195
0
    case AArch64::BEXT_ZZZ_H:
19196
0
    case AArch64::BEXT_ZZZ_S:
19197
0
    case AArch64::BGRP_ZZZ_B:
19198
0
    case AArch64::BGRP_ZZZ_D:
19199
0
    case AArch64::BGRP_ZZZ_H:
19200
0
    case AArch64::BGRP_ZZZ_S:
19201
0
    case AArch64::HISTSEG_ZZZ:
19202
0
    case AArch64::PMULLB_ZZZ_D:
19203
0
    case AArch64::PMULLB_ZZZ_H:
19204
0
    case AArch64::PMULLB_ZZZ_Q:
19205
0
    case AArch64::PMULLT_ZZZ_D:
19206
0
    case AArch64::PMULLT_ZZZ_H:
19207
0
    case AArch64::PMULLT_ZZZ_Q:
19208
0
    case AArch64::RADDHNB_ZZZ_B:
19209
0
    case AArch64::RADDHNB_ZZZ_H:
19210
0
    case AArch64::RADDHNB_ZZZ_S:
19211
0
    case AArch64::RAX1_ZZZ_D:
19212
0
    case AArch64::RSUBHNB_ZZZ_B:
19213
0
    case AArch64::RSUBHNB_ZZZ_H:
19214
0
    case AArch64::RSUBHNB_ZZZ_S:
19215
0
    case AArch64::SABDLB_ZZZ_D:
19216
0
    case AArch64::SABDLB_ZZZ_H:
19217
0
    case AArch64::SABDLB_ZZZ_S:
19218
0
    case AArch64::SABDLT_ZZZ_D:
19219
0
    case AArch64::SABDLT_ZZZ_H:
19220
0
    case AArch64::SABDLT_ZZZ_S:
19221
0
    case AArch64::SADDLBT_ZZZ_D:
19222
0
    case AArch64::SADDLBT_ZZZ_H:
19223
0
    case AArch64::SADDLBT_ZZZ_S:
19224
0
    case AArch64::SADDLB_ZZZ_D:
19225
0
    case AArch64::SADDLB_ZZZ_H:
19226
0
    case AArch64::SADDLB_ZZZ_S:
19227
0
    case AArch64::SADDLT_ZZZ_D:
19228
0
    case AArch64::SADDLT_ZZZ_H:
19229
0
    case AArch64::SADDLT_ZZZ_S:
19230
0
    case AArch64::SADDWB_ZZZ_D:
19231
0
    case AArch64::SADDWB_ZZZ_H:
19232
0
    case AArch64::SADDWB_ZZZ_S:
19233
0
    case AArch64::SADDWT_ZZZ_D:
19234
0
    case AArch64::SADDWT_ZZZ_H:
19235
0
    case AArch64::SADDWT_ZZZ_S:
19236
0
    case AArch64::SM4EKEY_ZZZ_S:
19237
0
    case AArch64::SMULLB_ZZZ_D:
19238
0
    case AArch64::SMULLB_ZZZ_H:
19239
0
    case AArch64::SMULLB_ZZZ_S:
19240
0
    case AArch64::SMULLT_ZZZ_D:
19241
0
    case AArch64::SMULLT_ZZZ_H:
19242
0
    case AArch64::SMULLT_ZZZ_S:
19243
0
    case AArch64::SQDMULLB_ZZZ_D:
19244
0
    case AArch64::SQDMULLB_ZZZ_H:
19245
0
    case AArch64::SQDMULLB_ZZZ_S:
19246
0
    case AArch64::SQDMULLT_ZZZ_D:
19247
0
    case AArch64::SQDMULLT_ZZZ_H:
19248
0
    case AArch64::SQDMULLT_ZZZ_S:
19249
0
    case AArch64::SSUBLBT_ZZZ_D:
19250
0
    case AArch64::SSUBLBT_ZZZ_H:
19251
0
    case AArch64::SSUBLBT_ZZZ_S:
19252
0
    case AArch64::SSUBLB_ZZZ_D:
19253
0
    case AArch64::SSUBLB_ZZZ_H:
19254
0
    case AArch64::SSUBLB_ZZZ_S:
19255
0
    case AArch64::SSUBLTB_ZZZ_D:
19256
0
    case AArch64::SSUBLTB_ZZZ_H:
19257
0
    case AArch64::SSUBLTB_ZZZ_S:
19258
0
    case AArch64::SSUBLT_ZZZ_D:
19259
0
    case AArch64::SSUBLT_ZZZ_H:
19260
0
    case AArch64::SSUBLT_ZZZ_S:
19261
0
    case AArch64::SSUBWB_ZZZ_D:
19262
0
    case AArch64::SSUBWB_ZZZ_H:
19263
0
    case AArch64::SSUBWB_ZZZ_S:
19264
0
    case AArch64::SSUBWT_ZZZ_D:
19265
0
    case AArch64::SSUBWT_ZZZ_H:
19266
0
    case AArch64::SSUBWT_ZZZ_S:
19267
0
    case AArch64::SUBHNB_ZZZ_B:
19268
0
    case AArch64::SUBHNB_ZZZ_H:
19269
0
    case AArch64::SUBHNB_ZZZ_S:
19270
0
    case AArch64::TBLQ_ZZZ_B:
19271
0
    case AArch64::TBLQ_ZZZ_D:
19272
0
    case AArch64::TBLQ_ZZZ_H:
19273
0
    case AArch64::TBLQ_ZZZ_S:
19274
0
    case AArch64::UABDLB_ZZZ_D:
19275
0
    case AArch64::UABDLB_ZZZ_H:
19276
0
    case AArch64::UABDLB_ZZZ_S:
19277
0
    case AArch64::UABDLT_ZZZ_D:
19278
0
    case AArch64::UABDLT_ZZZ_H:
19279
0
    case AArch64::UABDLT_ZZZ_S:
19280
0
    case AArch64::UADDLB_ZZZ_D:
19281
0
    case AArch64::UADDLB_ZZZ_H:
19282
0
    case AArch64::UADDLB_ZZZ_S:
19283
0
    case AArch64::UADDLT_ZZZ_D:
19284
0
    case AArch64::UADDLT_ZZZ_H:
19285
0
    case AArch64::UADDLT_ZZZ_S:
19286
0
    case AArch64::UADDWB_ZZZ_D:
19287
0
    case AArch64::UADDWB_ZZZ_H:
19288
0
    case AArch64::UADDWB_ZZZ_S:
19289
0
    case AArch64::UADDWT_ZZZ_D:
19290
0
    case AArch64::UADDWT_ZZZ_H:
19291
0
    case AArch64::UADDWT_ZZZ_S:
19292
0
    case AArch64::UMULLB_ZZZ_D:
19293
0
    case AArch64::UMULLB_ZZZ_H:
19294
0
    case AArch64::UMULLB_ZZZ_S:
19295
0
    case AArch64::UMULLT_ZZZ_D:
19296
0
    case AArch64::UMULLT_ZZZ_H:
19297
0
    case AArch64::UMULLT_ZZZ_S:
19298
0
    case AArch64::USUBLB_ZZZ_D:
19299
0
    case AArch64::USUBLB_ZZZ_H:
19300
0
    case AArch64::USUBLB_ZZZ_S:
19301
0
    case AArch64::USUBLT_ZZZ_D:
19302
0
    case AArch64::USUBLT_ZZZ_H:
19303
0
    case AArch64::USUBLT_ZZZ_S:
19304
0
    case AArch64::USUBWB_ZZZ_D:
19305
0
    case AArch64::USUBWB_ZZZ_H:
19306
0
    case AArch64::USUBWB_ZZZ_S:
19307
0
    case AArch64::USUBWT_ZZZ_D:
19308
0
    case AArch64::USUBWT_ZZZ_H:
19309
0
    case AArch64::USUBWT_ZZZ_S:
19310
0
    case AArch64::UZPQ1_ZZZ_B:
19311
0
    case AArch64::UZPQ1_ZZZ_D:
19312
0
    case AArch64::UZPQ1_ZZZ_H:
19313
0
    case AArch64::UZPQ1_ZZZ_S:
19314
0
    case AArch64::UZPQ2_ZZZ_B:
19315
0
    case AArch64::UZPQ2_ZZZ_D:
19316
0
    case AArch64::UZPQ2_ZZZ_H:
19317
0
    case AArch64::UZPQ2_ZZZ_S:
19318
0
    case AArch64::ZIPQ1_ZZZ_B:
19319
0
    case AArch64::ZIPQ1_ZZZ_D:
19320
0
    case AArch64::ZIPQ1_ZZZ_H:
19321
0
    case AArch64::ZIPQ1_ZZZ_S:
19322
0
    case AArch64::ZIPQ2_ZZZ_B:
19323
0
    case AArch64::ZIPQ2_ZZZ_D:
19324
0
    case AArch64::ZIPQ2_ZZZ_H:
19325
0
    case AArch64::ZIPQ2_ZZZ_S: {
19326
      // op: Zd
19327
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19328
0
      op &= UINT64_C(31);
19329
0
      Value |= op;
19330
      // op: Zn
19331
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19332
0
      op &= UINT64_C(31);
19333
0
      op <<= 5;
19334
0
      Value |= op;
19335
      // op: Zm
19336
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19337
0
      op &= UINT64_C(31);
19338
0
      op <<= 16;
19339
0
      Value |= op;
19340
0
      break;
19341
0
    }
19342
0
    case AArch64::LUTI2_ZZZI_H: {
19343
      // op: Zd
19344
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19345
0
      op &= UINT64_C(31);
19346
0
      Value |= op;
19347
      // op: Zn
19348
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19349
0
      op &= UINT64_C(31);
19350
0
      op <<= 5;
19351
0
      Value |= op;
19352
      // op: Zm
19353
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19354
0
      op &= UINT64_C(31);
19355
0
      op <<= 16;
19356
0
      Value |= op;
19357
      // op: idx
19358
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
19359
0
      Value |= (op & UINT64_C(6)) << 21;
19360
0
      Value |= (op & UINT64_C(1)) << 12;
19361
0
      break;
19362
0
    }
19363
0
    case AArch64::LUTI4_ZZZI_B: {
19364
      // op: Zd
19365
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19366
0
      op &= UINT64_C(31);
19367
0
      Value |= op;
19368
      // op: Zn
19369
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19370
0
      op &= UINT64_C(31);
19371
0
      op <<= 5;
19372
0
      Value |= op;
19373
      // op: Zm
19374
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19375
0
      op &= UINT64_C(31);
19376
0
      op <<= 16;
19377
0
      Value |= op;
19378
      // op: idx
19379
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
19380
0
      op &= UINT64_C(1);
19381
0
      op <<= 23;
19382
0
      Value |= op;
19383
0
      break;
19384
0
    }
19385
0
    case AArch64::LUTI2_ZZZI_B:
19386
0
    case AArch64::LUTI4_Z2ZZI_H:
19387
0
    case AArch64::LUTI4_ZZZI_H: {
19388
      // op: Zd
19389
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19390
0
      op &= UINT64_C(31);
19391
0
      Value |= op;
19392
      // op: Zn
19393
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19394
0
      op &= UINT64_C(31);
19395
0
      op <<= 5;
19396
0
      Value |= op;
19397
      // op: Zm
19398
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19399
0
      op &= UINT64_C(31);
19400
0
      op <<= 16;
19401
0
      Value |= op;
19402
      // op: idx
19403
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
19404
0
      op &= UINT64_C(3);
19405
0
      op <<= 22;
19406
0
      Value |= op;
19407
0
      break;
19408
0
    }
19409
0
    case AArch64::BFMUL_ZZZI:
19410
0
    case AArch64::FMUL_ZZZI_H:
19411
0
    case AArch64::MUL_ZZZI_H:
19412
0
    case AArch64::SQDMULH_ZZZI_H:
19413
0
    case AArch64::SQRDMULH_ZZZI_H: {
19414
      // op: Zd
19415
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19416
0
      op &= UINT64_C(31);
19417
0
      Value |= op;
19418
      // op: Zn
19419
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19420
0
      op &= UINT64_C(31);
19421
0
      op <<= 5;
19422
0
      Value |= op;
19423
      // op: Zm
19424
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19425
0
      op &= UINT64_C(7);
19426
0
      op <<= 16;
19427
0
      Value |= op;
19428
      // op: iop
19429
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
19430
0
      Value |= (op & UINT64_C(4)) << 20;
19431
0
      Value |= (op & UINT64_C(3)) << 19;
19432
0
      break;
19433
0
    }
19434
0
    case AArch64::SMULLB_ZZZI_S:
19435
0
    case AArch64::SMULLT_ZZZI_S:
19436
0
    case AArch64::SQDMULLB_ZZZI_S:
19437
0
    case AArch64::SQDMULLT_ZZZI_S:
19438
0
    case AArch64::UMULLB_ZZZI_S:
19439
0
    case AArch64::UMULLT_ZZZI_S: {
19440
      // op: Zd
19441
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19442
0
      op &= UINT64_C(31);
19443
0
      Value |= op;
19444
      // op: Zn
19445
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19446
0
      op &= UINT64_C(31);
19447
0
      op <<= 5;
19448
0
      Value |= op;
19449
      // op: Zm
19450
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19451
0
      op &= UINT64_C(7);
19452
0
      op <<= 16;
19453
0
      Value |= op;
19454
      // op: iop
19455
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
19456
0
      Value |= (op & UINT64_C(6)) << 18;
19457
0
      Value |= (op & UINT64_C(1)) << 11;
19458
0
      break;
19459
0
    }
19460
0
    case AArch64::FMUL_ZZZI_S:
19461
0
    case AArch64::MUL_ZZZI_S:
19462
0
    case AArch64::SQDMULH_ZZZI_S:
19463
0
    case AArch64::SQRDMULH_ZZZI_S: {
19464
      // op: Zd
19465
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19466
0
      op &= UINT64_C(31);
19467
0
      Value |= op;
19468
      // op: Zn
19469
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19470
0
      op &= UINT64_C(31);
19471
0
      op <<= 5;
19472
0
      Value |= op;
19473
      // op: Zm
19474
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19475
0
      op &= UINT64_C(7);
19476
0
      op <<= 16;
19477
0
      Value |= op;
19478
      // op: iop
19479
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
19480
0
      op &= UINT64_C(3);
19481
0
      op <<= 19;
19482
0
      Value |= op;
19483
0
      break;
19484
0
    }
19485
0
    case AArch64::DUP_ZZI_S: {
19486
      // op: Zd
19487
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19488
0
      op &= UINT64_C(31);
19489
0
      Value |= op;
19490
      // op: Zn
19491
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19492
0
      op &= UINT64_C(31);
19493
0
      op <<= 5;
19494
0
      Value |= op;
19495
      // op: idx
19496
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19497
0
      Value |= (op & UINT64_C(12)) << 20;
19498
0
      Value |= (op & UINT64_C(3)) << 19;
19499
0
      break;
19500
0
    }
19501
0
    case AArch64::DUP_ZZI_H: {
19502
      // op: Zd
19503
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19504
0
      op &= UINT64_C(31);
19505
0
      Value |= op;
19506
      // op: Zn
19507
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19508
0
      op &= UINT64_C(31);
19509
0
      op <<= 5;
19510
0
      Value |= op;
19511
      // op: idx
19512
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19513
0
      Value |= (op & UINT64_C(24)) << 19;
19514
0
      Value |= (op & UINT64_C(7)) << 18;
19515
0
      break;
19516
0
    }
19517
0
    case AArch64::DUP_ZZI_B: {
19518
      // op: Zd
19519
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19520
0
      op &= UINT64_C(31);
19521
0
      Value |= op;
19522
      // op: Zn
19523
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19524
0
      op &= UINT64_C(31);
19525
0
      op <<= 5;
19526
0
      Value |= op;
19527
      // op: idx
19528
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19529
0
      Value |= (op & UINT64_C(48)) << 18;
19530
0
      Value |= (op & UINT64_C(15)) << 17;
19531
0
      break;
19532
0
    }
19533
0
    case AArch64::DUP_ZZI_D: {
19534
      // op: Zd
19535
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19536
0
      op &= UINT64_C(31);
19537
0
      Value |= op;
19538
      // op: Zn
19539
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19540
0
      op &= UINT64_C(31);
19541
0
      op <<= 5;
19542
0
      Value |= op;
19543
      // op: idx
19544
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19545
0
      Value |= (op & UINT64_C(6)) << 21;
19546
0
      Value |= (op & UINT64_C(1)) << 20;
19547
0
      break;
19548
0
    }
19549
0
    case AArch64::DUP_ZZI_Q: {
19550
      // op: Zd
19551
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19552
0
      op &= UINT64_C(31);
19553
0
      Value |= op;
19554
      // op: Zn
19555
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19556
0
      op &= UINT64_C(31);
19557
0
      op <<= 5;
19558
0
      Value |= op;
19559
      // op: idx
19560
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19561
0
      op &= UINT64_C(3);
19562
0
      op <<= 22;
19563
0
      Value |= op;
19564
0
      break;
19565
0
    }
19566
0
    case AArch64::LSL_ZZI_H:
19567
0
    case AArch64::SSHLLB_ZZI_S:
19568
0
    case AArch64::SSHLLT_ZZI_S:
19569
0
    case AArch64::USHLLB_ZZI_S:
19570
0
    case AArch64::USHLLT_ZZI_S: {
19571
      // op: Zd
19572
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19573
0
      op &= UINT64_C(31);
19574
0
      Value |= op;
19575
      // op: Zn
19576
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19577
0
      op &= UINT64_C(31);
19578
0
      op <<= 5;
19579
0
      Value |= op;
19580
      // op: imm
19581
0
      op = getVecShiftL16OpValue(MI, 2, Fixups, STI);
19582
0
      op &= UINT64_C(15);
19583
0
      op <<= 16;
19584
0
      Value |= op;
19585
0
      break;
19586
0
    }
19587
0
    case AArch64::LSL_ZZI_S:
19588
0
    case AArch64::SSHLLB_ZZI_D:
19589
0
    case AArch64::SSHLLT_ZZI_D:
19590
0
    case AArch64::USHLLB_ZZI_D:
19591
0
    case AArch64::USHLLT_ZZI_D: {
19592
      // op: Zd
19593
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19594
0
      op &= UINT64_C(31);
19595
0
      Value |= op;
19596
      // op: Zn
19597
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19598
0
      op &= UINT64_C(31);
19599
0
      op <<= 5;
19600
0
      Value |= op;
19601
      // op: imm
19602
0
      op = getVecShiftL32OpValue(MI, 2, Fixups, STI);
19603
0
      op &= UINT64_C(31);
19604
0
      op <<= 16;
19605
0
      Value |= op;
19606
0
      break;
19607
0
    }
19608
0
    case AArch64::LSL_ZZI_D: {
19609
      // op: Zd
19610
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19611
0
      op &= UINT64_C(31);
19612
0
      Value |= op;
19613
      // op: Zn
19614
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19615
0
      op &= UINT64_C(31);
19616
0
      op <<= 5;
19617
0
      Value |= op;
19618
      // op: imm
19619
0
      op = getVecShiftL64OpValue(MI, 2, Fixups, STI);
19620
0
      Value |= (op & UINT64_C(32)) << 17;
19621
0
      Value |= (op & UINT64_C(31)) << 16;
19622
0
      break;
19623
0
    }
19624
0
    case AArch64::LSL_ZZI_B:
19625
0
    case AArch64::SSHLLB_ZZI_H:
19626
0
    case AArch64::SSHLLT_ZZI_H:
19627
0
    case AArch64::USHLLB_ZZI_H:
19628
0
    case AArch64::USHLLT_ZZI_H: {
19629
      // op: Zd
19630
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19631
0
      op &= UINT64_C(31);
19632
0
      Value |= op;
19633
      // op: Zn
19634
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19635
0
      op &= UINT64_C(31);
19636
0
      op <<= 5;
19637
0
      Value |= op;
19638
      // op: imm
19639
0
      op = getVecShiftL8OpValue(MI, 2, Fixups, STI);
19640
0
      op &= UINT64_C(7);
19641
0
      op <<= 16;
19642
0
      Value |= op;
19643
0
      break;
19644
0
    }
19645
0
    case AArch64::ASR_ZZI_H:
19646
0
    case AArch64::LSR_ZZI_H:
19647
0
    case AArch64::RSHRNB_ZZI_H:
19648
0
    case AArch64::SHRNB_ZZI_H:
19649
0
    case AArch64::SQRSHRNB_ZZI_H:
19650
0
    case AArch64::SQRSHRUNB_ZZI_H:
19651
0
    case AArch64::SQSHRNB_ZZI_H:
19652
0
    case AArch64::SQSHRUNB_ZZI_H:
19653
0
    case AArch64::UQRSHRNB_ZZI_H:
19654
0
    case AArch64::UQSHRNB_ZZI_H: {
19655
      // op: Zd
19656
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19657
0
      op &= UINT64_C(31);
19658
0
      Value |= op;
19659
      // op: Zn
19660
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19661
0
      op &= UINT64_C(31);
19662
0
      op <<= 5;
19663
0
      Value |= op;
19664
      // op: imm
19665
0
      op = getVecShiftR16OpValue(MI, 2, Fixups, STI);
19666
0
      op &= UINT64_C(15);
19667
0
      op <<= 16;
19668
0
      Value |= op;
19669
0
      break;
19670
0
    }
19671
0
    case AArch64::ASR_ZZI_S:
19672
0
    case AArch64::LSR_ZZI_S:
19673
0
    case AArch64::RSHRNB_ZZI_S:
19674
0
    case AArch64::SHRNB_ZZI_S:
19675
0
    case AArch64::SQRSHRNB_ZZI_S:
19676
0
    case AArch64::SQRSHRUNB_ZZI_S:
19677
0
    case AArch64::SQSHRNB_ZZI_S:
19678
0
    case AArch64::SQSHRUNB_ZZI_S:
19679
0
    case AArch64::UQRSHRNB_ZZI_S:
19680
0
    case AArch64::UQSHRNB_ZZI_S: {
19681
      // op: Zd
19682
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19683
0
      op &= UINT64_C(31);
19684
0
      Value |= op;
19685
      // op: Zn
19686
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19687
0
      op &= UINT64_C(31);
19688
0
      op <<= 5;
19689
0
      Value |= op;
19690
      // op: imm
19691
0
      op = getVecShiftR32OpValue(MI, 2, Fixups, STI);
19692
0
      op &= UINT64_C(31);
19693
0
      op <<= 16;
19694
0
      Value |= op;
19695
0
      break;
19696
0
    }
19697
0
    case AArch64::ASR_ZZI_D:
19698
0
    case AArch64::LSR_ZZI_D: {
19699
      // op: Zd
19700
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19701
0
      op &= UINT64_C(31);
19702
0
      Value |= op;
19703
      // op: Zn
19704
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19705
0
      op &= UINT64_C(31);
19706
0
      op <<= 5;
19707
0
      Value |= op;
19708
      // op: imm
19709
0
      op = getVecShiftR64OpValue(MI, 2, Fixups, STI);
19710
0
      Value |= (op & UINT64_C(32)) << 17;
19711
0
      Value |= (op & UINT64_C(31)) << 16;
19712
0
      break;
19713
0
    }
19714
0
    case AArch64::ASR_ZZI_B:
19715
0
    case AArch64::LSR_ZZI_B:
19716
0
    case AArch64::RSHRNB_ZZI_B:
19717
0
    case AArch64::SHRNB_ZZI_B:
19718
0
    case AArch64::SQRSHRNB_ZZI_B:
19719
0
    case AArch64::SQRSHRUNB_ZZI_B:
19720
0
    case AArch64::SQSHRNB_ZZI_B:
19721
0
    case AArch64::SQSHRUNB_ZZI_B:
19722
0
    case AArch64::UQRSHRNB_ZZI_B:
19723
0
    case AArch64::UQSHRNB_ZZI_B: {
19724
      // op: Zd
19725
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19726
0
      op &= UINT64_C(31);
19727
0
      Value |= op;
19728
      // op: Zn
19729
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19730
0
      op &= UINT64_C(31);
19731
0
      op <<= 5;
19732
0
      Value |= op;
19733
      // op: imm
19734
0
      op = getVecShiftR8OpValue(MI, 2, Fixups, STI);
19735
0
      op &= UINT64_C(7);
19736
0
      op <<= 16;
19737
0
      Value |= op;
19738
0
      break;
19739
0
    }
19740
0
    case AArch64::EXT_ZZI_B: {
19741
      // op: Zd
19742
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19743
0
      op &= UINT64_C(31);
19744
0
      Value |= op;
19745
      // op: Zn
19746
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19747
0
      op &= UINT64_C(31);
19748
0
      op <<= 5;
19749
0
      Value |= op;
19750
      // op: imm8
19751
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19752
0
      Value |= (op & UINT64_C(248)) << 13;
19753
0
      Value |= (op & UINT64_C(7)) << 10;
19754
0
      break;
19755
0
    }
19756
0
    case AArch64::DUPQ_ZZI_D: {
19757
      // op: Zd
19758
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19759
0
      op &= UINT64_C(31);
19760
0
      Value |= op;
19761
      // op: Zn
19762
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19763
0
      op &= UINT64_C(31);
19764
0
      op <<= 5;
19765
0
      Value |= op;
19766
      // op: index
19767
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19768
0
      op &= UINT64_C(1);
19769
0
      op <<= 20;
19770
0
      Value |= op;
19771
0
      break;
19772
0
    }
19773
0
    case AArch64::DUPQ_ZZI_B: {
19774
      // op: Zd
19775
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19776
0
      op &= UINT64_C(31);
19777
0
      Value |= op;
19778
      // op: Zn
19779
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19780
0
      op &= UINT64_C(31);
19781
0
      op <<= 5;
19782
0
      Value |= op;
19783
      // op: index
19784
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19785
0
      op &= UINT64_C(15);
19786
0
      op <<= 17;
19787
0
      Value |= op;
19788
0
      break;
19789
0
    }
19790
0
    case AArch64::DUPQ_ZZI_S: {
19791
      // op: Zd
19792
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19793
0
      op &= UINT64_C(31);
19794
0
      Value |= op;
19795
      // op: Zn
19796
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19797
0
      op &= UINT64_C(31);
19798
0
      op <<= 5;
19799
0
      Value |= op;
19800
      // op: index
19801
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19802
0
      op &= UINT64_C(3);
19803
0
      op <<= 19;
19804
0
      Value |= op;
19805
0
      break;
19806
0
    }
19807
0
    case AArch64::DUPQ_ZZI_H: {
19808
      // op: Zd
19809
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19810
0
      op &= UINT64_C(31);
19811
0
      Value |= op;
19812
      // op: Zn
19813
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19814
0
      op &= UINT64_C(31);
19815
0
      op <<= 5;
19816
0
      Value |= op;
19817
      // op: index
19818
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19819
0
      op &= UINT64_C(7);
19820
0
      op <<= 18;
19821
0
      Value |= op;
19822
0
      break;
19823
0
    }
19824
0
    case AArch64::SQXTNT_ZZ_B:
19825
0
    case AArch64::SQXTNT_ZZ_H:
19826
0
    case AArch64::SQXTNT_ZZ_S:
19827
0
    case AArch64::SQXTUNT_ZZ_B:
19828
0
    case AArch64::SQXTUNT_ZZ_H:
19829
0
    case AArch64::SQXTUNT_ZZ_S:
19830
0
    case AArch64::UQXTNT_ZZ_B:
19831
0
    case AArch64::UQXTNT_ZZ_H:
19832
0
    case AArch64::UQXTNT_ZZ_S: {
19833
      // op: Zd
19834
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19835
0
      op &= UINT64_C(31);
19836
0
      Value |= op;
19837
      // op: Zn
19838
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19839
0
      op &= UINT64_C(31);
19840
0
      op <<= 5;
19841
0
      Value |= op;
19842
0
      break;
19843
0
    }
19844
0
    case AArch64::HISTCNT_ZPzZZ_D:
19845
0
    case AArch64::HISTCNT_ZPzZZ_S: {
19846
      // op: Zd
19847
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19848
0
      op &= UINT64_C(31);
19849
0
      Value |= op;
19850
      // op: Zn
19851
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19852
0
      op &= UINT64_C(31);
19853
0
      op <<= 5;
19854
0
      Value |= op;
19855
      // op: Pg
19856
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
19857
0
      op &= UINT64_C(7);
19858
0
      op <<= 10;
19859
0
      Value |= op;
19860
      // op: Zm
19861
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
19862
0
      op &= UINT64_C(31);
19863
0
      op <<= 16;
19864
0
      Value |= op;
19865
0
      break;
19866
0
    }
19867
0
    case AArch64::ADDHNT_ZZZ_B:
19868
0
    case AArch64::ADDHNT_ZZZ_H:
19869
0
    case AArch64::ADDHNT_ZZZ_S:
19870
0
    case AArch64::EORBT_ZZZ_B:
19871
0
    case AArch64::EORBT_ZZZ_D:
19872
0
    case AArch64::EORBT_ZZZ_H:
19873
0
    case AArch64::EORBT_ZZZ_S:
19874
0
    case AArch64::EORTB_ZZZ_B:
19875
0
    case AArch64::EORTB_ZZZ_D:
19876
0
    case AArch64::EORTB_ZZZ_H:
19877
0
    case AArch64::EORTB_ZZZ_S:
19878
0
    case AArch64::RADDHNT_ZZZ_B:
19879
0
    case AArch64::RADDHNT_ZZZ_H:
19880
0
    case AArch64::RADDHNT_ZZZ_S:
19881
0
    case AArch64::RSUBHNT_ZZZ_B:
19882
0
    case AArch64::RSUBHNT_ZZZ_H:
19883
0
    case AArch64::RSUBHNT_ZZZ_S:
19884
0
    case AArch64::SUBHNT_ZZZ_B:
19885
0
    case AArch64::SUBHNT_ZZZ_H:
19886
0
    case AArch64::SUBHNT_ZZZ_S: {
19887
      // op: Zd
19888
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19889
0
      op &= UINT64_C(31);
19890
0
      Value |= op;
19891
      // op: Zn
19892
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19893
0
      op &= UINT64_C(31);
19894
0
      op <<= 5;
19895
0
      Value |= op;
19896
      // op: Zm
19897
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
19898
0
      op &= UINT64_C(31);
19899
0
      op <<= 16;
19900
0
      Value |= op;
19901
0
      break;
19902
0
    }
19903
0
    case AArch64::SLI_ZZI_H: {
19904
      // op: Zd
19905
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19906
0
      op &= UINT64_C(31);
19907
0
      Value |= op;
19908
      // op: Zn
19909
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19910
0
      op &= UINT64_C(31);
19911
0
      op <<= 5;
19912
0
      Value |= op;
19913
      // op: imm
19914
0
      op = getVecShiftL16OpValue(MI, 3, Fixups, STI);
19915
0
      op &= UINT64_C(15);
19916
0
      op <<= 16;
19917
0
      Value |= op;
19918
0
      break;
19919
0
    }
19920
0
    case AArch64::SLI_ZZI_S: {
19921
      // op: Zd
19922
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19923
0
      op &= UINT64_C(31);
19924
0
      Value |= op;
19925
      // op: Zn
19926
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19927
0
      op &= UINT64_C(31);
19928
0
      op <<= 5;
19929
0
      Value |= op;
19930
      // op: imm
19931
0
      op = getVecShiftL32OpValue(MI, 3, Fixups, STI);
19932
0
      op &= UINT64_C(31);
19933
0
      op <<= 16;
19934
0
      Value |= op;
19935
0
      break;
19936
0
    }
19937
0
    case AArch64::SLI_ZZI_D: {
19938
      // op: Zd
19939
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19940
0
      op &= UINT64_C(31);
19941
0
      Value |= op;
19942
      // op: Zn
19943
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19944
0
      op &= UINT64_C(31);
19945
0
      op <<= 5;
19946
0
      Value |= op;
19947
      // op: imm
19948
0
      op = getVecShiftL64OpValue(MI, 3, Fixups, STI);
19949
0
      Value |= (op & UINT64_C(32)) << 17;
19950
0
      Value |= (op & UINT64_C(31)) << 16;
19951
0
      break;
19952
0
    }
19953
0
    case AArch64::SLI_ZZI_B: {
19954
      // op: Zd
19955
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19956
0
      op &= UINT64_C(31);
19957
0
      Value |= op;
19958
      // op: Zn
19959
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19960
0
      op &= UINT64_C(31);
19961
0
      op <<= 5;
19962
0
      Value |= op;
19963
      // op: imm
19964
0
      op = getVecShiftL8OpValue(MI, 3, Fixups, STI);
19965
0
      op &= UINT64_C(7);
19966
0
      op <<= 16;
19967
0
      Value |= op;
19968
0
      break;
19969
0
    }
19970
0
    case AArch64::RSHRNT_ZZI_H:
19971
0
    case AArch64::SHRNT_ZZI_H:
19972
0
    case AArch64::SQRSHRNT_ZZI_H:
19973
0
    case AArch64::SQRSHRUNT_ZZI_H:
19974
0
    case AArch64::SQSHRNT_ZZI_H:
19975
0
    case AArch64::SQSHRUNT_ZZI_H:
19976
0
    case AArch64::SRI_ZZI_H:
19977
0
    case AArch64::UQRSHRNT_ZZI_H:
19978
0
    case AArch64::UQSHRNT_ZZI_H: {
19979
      // op: Zd
19980
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
19981
0
      op &= UINT64_C(31);
19982
0
      Value |= op;
19983
      // op: Zn
19984
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
19985
0
      op &= UINT64_C(31);
19986
0
      op <<= 5;
19987
0
      Value |= op;
19988
      // op: imm
19989
0
      op = getVecShiftR16OpValue(MI, 3, Fixups, STI);
19990
0
      op &= UINT64_C(15);
19991
0
      op <<= 16;
19992
0
      Value |= op;
19993
0
      break;
19994
0
    }
19995
0
    case AArch64::RSHRNT_ZZI_S:
19996
0
    case AArch64::SHRNT_ZZI_S:
19997
0
    case AArch64::SQRSHRNT_ZZI_S:
19998
0
    case AArch64::SQRSHRUNT_ZZI_S:
19999
0
    case AArch64::SQSHRNT_ZZI_S:
20000
0
    case AArch64::SQSHRUNT_ZZI_S:
20001
0
    case AArch64::SRI_ZZI_S:
20002
0
    case AArch64::UQRSHRNT_ZZI_S:
20003
0
    case AArch64::UQSHRNT_ZZI_S: {
20004
      // op: Zd
20005
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20006
0
      op &= UINT64_C(31);
20007
0
      Value |= op;
20008
      // op: Zn
20009
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20010
0
      op &= UINT64_C(31);
20011
0
      op <<= 5;
20012
0
      Value |= op;
20013
      // op: imm
20014
0
      op = getVecShiftR32OpValue(MI, 3, Fixups, STI);
20015
0
      op &= UINT64_C(31);
20016
0
      op <<= 16;
20017
0
      Value |= op;
20018
0
      break;
20019
0
    }
20020
0
    case AArch64::SRI_ZZI_D: {
20021
      // op: Zd
20022
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20023
0
      op &= UINT64_C(31);
20024
0
      Value |= op;
20025
      // op: Zn
20026
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20027
0
      op &= UINT64_C(31);
20028
0
      op <<= 5;
20029
0
      Value |= op;
20030
      // op: imm
20031
0
      op = getVecShiftR64OpValue(MI, 3, Fixups, STI);
20032
0
      Value |= (op & UINT64_C(32)) << 17;
20033
0
      Value |= (op & UINT64_C(31)) << 16;
20034
0
      break;
20035
0
    }
20036
0
    case AArch64::RSHRNT_ZZI_B:
20037
0
    case AArch64::SHRNT_ZZI_B:
20038
0
    case AArch64::SQRSHRNT_ZZI_B:
20039
0
    case AArch64::SQRSHRUNT_ZZI_B:
20040
0
    case AArch64::SQSHRNT_ZZI_B:
20041
0
    case AArch64::SQSHRUNT_ZZI_B:
20042
0
    case AArch64::SRI_ZZI_B:
20043
0
    case AArch64::UQRSHRNT_ZZI_B:
20044
0
    case AArch64::UQSHRNT_ZZI_B: {
20045
      // op: Zd
20046
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20047
0
      op &= UINT64_C(31);
20048
0
      Value |= op;
20049
      // op: Zn
20050
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20051
0
      op &= UINT64_C(31);
20052
0
      op <<= 5;
20053
0
      Value |= op;
20054
      // op: imm
20055
0
      op = getVecShiftR8OpValue(MI, 3, Fixups, STI);
20056
0
      op &= UINT64_C(7);
20057
0
      op <<= 16;
20058
0
      Value |= op;
20059
0
      break;
20060
0
    }
20061
0
    case AArch64::FCVTLT_ZPmZ_HtoS:
20062
0
    case AArch64::FCVTLT_ZPmZ_StoD:
20063
0
    case AArch64::FCVTNT_ZPmZ_DtoS:
20064
0
    case AArch64::FCVTNT_ZPmZ_StoH:
20065
0
    case AArch64::FCVTXNT_ZPmZ_DtoS: {
20066
      // op: Zd
20067
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20068
0
      op &= UINT64_C(31);
20069
0
      Value |= op;
20070
      // op: Zn
20071
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20072
0
      op &= UINT64_C(31);
20073
0
      op <<= 5;
20074
0
      Value |= op;
20075
      // op: Pg
20076
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20077
0
      op &= UINT64_C(7);
20078
0
      op <<= 10;
20079
0
      Value |= op;
20080
0
      break;
20081
0
    }
20082
0
    case AArch64::DUP_ZI_B:
20083
0
    case AArch64::DUP_ZI_D:
20084
0
    case AArch64::DUP_ZI_H:
20085
0
    case AArch64::DUP_ZI_S: {
20086
      // op: Zd
20087
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20088
0
      op &= UINT64_C(31);
20089
0
      Value |= op;
20090
      // op: imm
20091
0
      op = getImm8OptLsl(MI, 1, Fixups, STI);
20092
0
      op &= UINT64_C(511);
20093
0
      op <<= 5;
20094
0
      Value |= op;
20095
0
      break;
20096
0
    }
20097
0
    case AArch64::INDEX_II_B:
20098
0
    case AArch64::INDEX_II_D:
20099
0
    case AArch64::INDEX_II_H:
20100
0
    case AArch64::INDEX_II_S: {
20101
      // op: Zd
20102
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20103
0
      op &= UINT64_C(31);
20104
0
      Value |= op;
20105
      // op: imm5
20106
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
20107
0
      op &= UINT64_C(31);
20108
0
      op <<= 5;
20109
0
      Value |= op;
20110
      // op: imm5b
20111
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20112
0
      op &= UINT64_C(31);
20113
0
      op <<= 16;
20114
0
      Value |= op;
20115
0
      break;
20116
0
    }
20117
0
    case AArch64::FDUP_ZI_D:
20118
0
    case AArch64::FDUP_ZI_H:
20119
0
    case AArch64::FDUP_ZI_S: {
20120
      // op: Zd
20121
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20122
0
      op &= UINT64_C(31);
20123
0
      Value |= op;
20124
      // op: imm8
20125
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
20126
0
      op &= UINT64_C(255);
20127
0
      op <<= 5;
20128
0
      Value |= op;
20129
0
      break;
20130
0
    }
20131
0
    case AArch64::DUPM_ZI: {
20132
      // op: Zd
20133
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20134
0
      op &= UINT64_C(31);
20135
0
      Value |= op;
20136
      // op: imms
20137
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
20138
0
      op &= UINT64_C(8191);
20139
0
      op <<= 5;
20140
0
      Value |= op;
20141
0
      break;
20142
0
    }
20143
0
    case AArch64::FCMLA_ZPmZZ_D:
20144
0
    case AArch64::FCMLA_ZPmZZ_H:
20145
0
    case AArch64::FCMLA_ZPmZZ_S: {
20146
      // op: Zda
20147
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20148
0
      op &= UINT64_C(31);
20149
0
      Value |= op;
20150
      // op: Pg
20151
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
20152
0
      op &= UINT64_C(7);
20153
0
      op <<= 10;
20154
0
      Value |= op;
20155
      // op: Zn
20156
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20157
0
      op &= UINT64_C(31);
20158
0
      op <<= 5;
20159
0
      Value |= op;
20160
      // op: Zm
20161
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
20162
0
      op &= UINT64_C(31);
20163
0
      op <<= 16;
20164
0
      Value |= op;
20165
      // op: imm
20166
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
20167
0
      op &= UINT64_C(3);
20168
0
      op <<= 13;
20169
0
      Value |= op;
20170
0
      break;
20171
0
    }
20172
0
    case AArch64::SMLALB_ZZZI_D:
20173
0
    case AArch64::SMLALT_ZZZI_D:
20174
0
    case AArch64::SMLSLB_ZZZI_D:
20175
0
    case AArch64::SMLSLT_ZZZI_D:
20176
0
    case AArch64::SQDMLALB_ZZZI_D:
20177
0
    case AArch64::SQDMLALT_ZZZI_D:
20178
0
    case AArch64::SQDMLSLB_ZZZI_D:
20179
0
    case AArch64::SQDMLSLT_ZZZI_D:
20180
0
    case AArch64::UMLALB_ZZZI_D:
20181
0
    case AArch64::UMLALT_ZZZI_D:
20182
0
    case AArch64::UMLSLB_ZZZI_D:
20183
0
    case AArch64::UMLSLT_ZZZI_D: {
20184
      // op: Zda
20185
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20186
0
      op &= UINT64_C(31);
20187
0
      Value |= op;
20188
      // op: Zn
20189
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20190
0
      op &= UINT64_C(31);
20191
0
      op <<= 5;
20192
0
      Value |= op;
20193
      // op: Zm
20194
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20195
0
      op &= UINT64_C(15);
20196
0
      op <<= 16;
20197
0
      Value |= op;
20198
      // op: iop
20199
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
20200
0
      Value |= (op & UINT64_C(2)) << 19;
20201
0
      Value |= (op & UINT64_C(1)) << 11;
20202
0
      break;
20203
0
    }
20204
0
    case AArch64::FMLA_ZZZI_D:
20205
0
    case AArch64::FMLS_ZZZI_D:
20206
0
    case AArch64::MLA_ZZZI_D:
20207
0
    case AArch64::MLS_ZZZI_D:
20208
0
    case AArch64::SQRDMLAH_ZZZI_D:
20209
0
    case AArch64::SQRDMLSH_ZZZI_D: {
20210
      // op: Zda
20211
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20212
0
      op &= UINT64_C(31);
20213
0
      Value |= op;
20214
      // op: Zn
20215
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20216
0
      op &= UINT64_C(31);
20217
0
      op <<= 5;
20218
0
      Value |= op;
20219
      // op: Zm
20220
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20221
0
      op &= UINT64_C(15);
20222
0
      op <<= 16;
20223
0
      Value |= op;
20224
      // op: iop
20225
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
20226
0
      op &= UINT64_C(1);
20227
0
      op <<= 20;
20228
0
      Value |= op;
20229
0
      break;
20230
0
    }
20231
0
    case AArch64::ADCLB_ZZZ_D:
20232
0
    case AArch64::ADCLB_ZZZ_S:
20233
0
    case AArch64::ADCLT_ZZZ_D:
20234
0
    case AArch64::ADCLT_ZZZ_S:
20235
0
    case AArch64::BFDOT_ZZZ:
20236
0
    case AArch64::BFMLALB_ZZZ:
20237
0
    case AArch64::BFMLALT_ZZZ:
20238
0
    case AArch64::BFMLSLB_ZZZ_S:
20239
0
    case AArch64::BFMLSLT_ZZZ_S:
20240
0
    case AArch64::FDOT_ZZZ_BtoH:
20241
0
    case AArch64::FDOT_ZZZ_BtoS:
20242
0
    case AArch64::FDOT_ZZZ_S:
20243
0
    case AArch64::FMLALB_ZZZ:
20244
0
    case AArch64::FMLALB_ZZZ_SHH:
20245
0
    case AArch64::FMLALLBB_ZZZ:
20246
0
    case AArch64::FMLALLBT_ZZZ:
20247
0
    case AArch64::FMLALLTB_ZZZ:
20248
0
    case AArch64::FMLALLTT_ZZZ:
20249
0
    case AArch64::FMLALT_ZZZ:
20250
0
    case AArch64::FMLALT_ZZZ_SHH:
20251
0
    case AArch64::FMLSLB_ZZZ_SHH:
20252
0
    case AArch64::FMLSLT_ZZZ_SHH:
20253
0
    case AArch64::FMMLA_ZZZ_D:
20254
0
    case AArch64::FMMLA_ZZZ_S:
20255
0
    case AArch64::MLA_CPA:
20256
0
    case AArch64::SABALB_ZZZ_D:
20257
0
    case AArch64::SABALB_ZZZ_H:
20258
0
    case AArch64::SABALB_ZZZ_S:
20259
0
    case AArch64::SABALT_ZZZ_D:
20260
0
    case AArch64::SABALT_ZZZ_H:
20261
0
    case AArch64::SABALT_ZZZ_S:
20262
0
    case AArch64::SABA_ZZZ_B:
20263
0
    case AArch64::SABA_ZZZ_D:
20264
0
    case AArch64::SABA_ZZZ_H:
20265
0
    case AArch64::SABA_ZZZ_S:
20266
0
    case AArch64::SBCLB_ZZZ_D:
20267
0
    case AArch64::SBCLB_ZZZ_S:
20268
0
    case AArch64::SBCLT_ZZZ_D:
20269
0
    case AArch64::SBCLT_ZZZ_S:
20270
0
    case AArch64::SDOT_ZZZ_D:
20271
0
    case AArch64::SDOT_ZZZ_HtoS:
20272
0
    case AArch64::SDOT_ZZZ_S:
20273
0
    case AArch64::SMLALB_ZZZ_D:
20274
0
    case AArch64::SMLALB_ZZZ_H:
20275
0
    case AArch64::SMLALB_ZZZ_S:
20276
0
    case AArch64::SMLALT_ZZZ_D:
20277
0
    case AArch64::SMLALT_ZZZ_H:
20278
0
    case AArch64::SMLALT_ZZZ_S:
20279
0
    case AArch64::SMLSLB_ZZZ_D:
20280
0
    case AArch64::SMLSLB_ZZZ_H:
20281
0
    case AArch64::SMLSLB_ZZZ_S:
20282
0
    case AArch64::SMLSLT_ZZZ_D:
20283
0
    case AArch64::SMLSLT_ZZZ_H:
20284
0
    case AArch64::SMLSLT_ZZZ_S:
20285
0
    case AArch64::SMMLA_ZZZ:
20286
0
    case AArch64::SQDMLALBT_ZZZ_D:
20287
0
    case AArch64::SQDMLALBT_ZZZ_H:
20288
0
    case AArch64::SQDMLALBT_ZZZ_S:
20289
0
    case AArch64::SQDMLALB_ZZZ_D:
20290
0
    case AArch64::SQDMLALB_ZZZ_H:
20291
0
    case AArch64::SQDMLALB_ZZZ_S:
20292
0
    case AArch64::SQDMLALT_ZZZ_D:
20293
0
    case AArch64::SQDMLALT_ZZZ_H:
20294
0
    case AArch64::SQDMLALT_ZZZ_S:
20295
0
    case AArch64::SQDMLSLBT_ZZZ_D:
20296
0
    case AArch64::SQDMLSLBT_ZZZ_H:
20297
0
    case AArch64::SQDMLSLBT_ZZZ_S:
20298
0
    case AArch64::SQDMLSLB_ZZZ_D:
20299
0
    case AArch64::SQDMLSLB_ZZZ_H:
20300
0
    case AArch64::SQDMLSLB_ZZZ_S:
20301
0
    case AArch64::SQDMLSLT_ZZZ_D:
20302
0
    case AArch64::SQDMLSLT_ZZZ_H:
20303
0
    case AArch64::SQDMLSLT_ZZZ_S:
20304
0
    case AArch64::SQRDMLAH_ZZZ_B:
20305
0
    case AArch64::SQRDMLAH_ZZZ_D:
20306
0
    case AArch64::SQRDMLAH_ZZZ_H:
20307
0
    case AArch64::SQRDMLAH_ZZZ_S:
20308
0
    case AArch64::SQRDMLSH_ZZZ_B:
20309
0
    case AArch64::SQRDMLSH_ZZZ_D:
20310
0
    case AArch64::SQRDMLSH_ZZZ_H:
20311
0
    case AArch64::SQRDMLSH_ZZZ_S:
20312
0
    case AArch64::UABALB_ZZZ_D:
20313
0
    case AArch64::UABALB_ZZZ_H:
20314
0
    case AArch64::UABALB_ZZZ_S:
20315
0
    case AArch64::UABALT_ZZZ_D:
20316
0
    case AArch64::UABALT_ZZZ_H:
20317
0
    case AArch64::UABALT_ZZZ_S:
20318
0
    case AArch64::UABA_ZZZ_B:
20319
0
    case AArch64::UABA_ZZZ_D:
20320
0
    case AArch64::UABA_ZZZ_H:
20321
0
    case AArch64::UABA_ZZZ_S:
20322
0
    case AArch64::UDOT_ZZZ_D:
20323
0
    case AArch64::UDOT_ZZZ_HtoS:
20324
0
    case AArch64::UDOT_ZZZ_S:
20325
0
    case AArch64::UMLALB_ZZZ_D:
20326
0
    case AArch64::UMLALB_ZZZ_H:
20327
0
    case AArch64::UMLALB_ZZZ_S:
20328
0
    case AArch64::UMLALT_ZZZ_D:
20329
0
    case AArch64::UMLALT_ZZZ_H:
20330
0
    case AArch64::UMLALT_ZZZ_S:
20331
0
    case AArch64::UMLSLB_ZZZ_D:
20332
0
    case AArch64::UMLSLB_ZZZ_H:
20333
0
    case AArch64::UMLSLB_ZZZ_S:
20334
0
    case AArch64::UMLSLT_ZZZ_D:
20335
0
    case AArch64::UMLSLT_ZZZ_H:
20336
0
    case AArch64::UMLSLT_ZZZ_S:
20337
0
    case AArch64::UMMLA_ZZZ:
20338
0
    case AArch64::USDOT_ZZZ:
20339
0
    case AArch64::USMMLA_ZZZ: {
20340
      // op: Zda
20341
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20342
0
      op &= UINT64_C(31);
20343
0
      Value |= op;
20344
      // op: Zn
20345
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20346
0
      op &= UINT64_C(31);
20347
0
      op <<= 5;
20348
0
      Value |= op;
20349
      // op: Zm
20350
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20351
0
      op &= UINT64_C(31);
20352
0
      op <<= 16;
20353
0
      Value |= op;
20354
0
      break;
20355
0
    }
20356
0
    case AArch64::CDOT_ZZZ_D:
20357
0
    case AArch64::CDOT_ZZZ_S:
20358
0
    case AArch64::CMLA_ZZZ_B:
20359
0
    case AArch64::CMLA_ZZZ_D:
20360
0
    case AArch64::CMLA_ZZZ_H:
20361
0
    case AArch64::CMLA_ZZZ_S:
20362
0
    case AArch64::SQRDCMLAH_ZZZ_B:
20363
0
    case AArch64::SQRDCMLAH_ZZZ_D:
20364
0
    case AArch64::SQRDCMLAH_ZZZ_H:
20365
0
    case AArch64::SQRDCMLAH_ZZZ_S: {
20366
      // op: Zda
20367
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20368
0
      op &= UINT64_C(31);
20369
0
      Value |= op;
20370
      // op: Zn
20371
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20372
0
      op &= UINT64_C(31);
20373
0
      op <<= 5;
20374
0
      Value |= op;
20375
      // op: Zm
20376
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20377
0
      op &= UINT64_C(31);
20378
0
      op <<= 16;
20379
0
      Value |= op;
20380
      // op: rot
20381
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
20382
0
      op &= UINT64_C(3);
20383
0
      op <<= 10;
20384
0
      Value |= op;
20385
0
      break;
20386
0
    }
20387
0
    case AArch64::SDOT_ZZZI_HtoS:
20388
0
    case AArch64::UDOT_ZZZI_HtoS: {
20389
      // op: Zda
20390
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20391
0
      op &= UINT64_C(31);
20392
0
      Value |= op;
20393
      // op: Zn
20394
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20395
0
      op &= UINT64_C(31);
20396
0
      op <<= 5;
20397
0
      Value |= op;
20398
      // op: Zm
20399
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20400
0
      op &= UINT64_C(7);
20401
0
      op <<= 16;
20402
0
      Value |= op;
20403
      // op: i2
20404
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
20405
0
      op &= UINT64_C(3);
20406
0
      op <<= 19;
20407
0
      Value |= op;
20408
0
      break;
20409
0
    }
20410
0
    case AArch64::SUDOT_ZZZI:
20411
0
    case AArch64::USDOT_ZZZI: {
20412
      // op: Zda
20413
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20414
0
      op &= UINT64_C(31);
20415
0
      Value |= op;
20416
      // op: Zn
20417
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20418
0
      op &= UINT64_C(31);
20419
0
      op <<= 5;
20420
0
      Value |= op;
20421
      // op: Zm
20422
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20423
0
      op &= UINT64_C(7);
20424
0
      op <<= 16;
20425
0
      Value |= op;
20426
      // op: idx
20427
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
20428
0
      op &= UINT64_C(3);
20429
0
      op <<= 19;
20430
0
      Value |= op;
20431
0
      break;
20432
0
    }
20433
0
    case AArch64::FMLALB_ZZZI:
20434
0
    case AArch64::FMLALLBB_ZZZI:
20435
0
    case AArch64::FMLALLBT_ZZZI:
20436
0
    case AArch64::FMLALLTB_ZZZI:
20437
0
    case AArch64::FMLALLTT_ZZZI:
20438
0
    case AArch64::FMLALT_ZZZI: {
20439
      // op: Zda
20440
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20441
0
      op &= UINT64_C(31);
20442
0
      Value |= op;
20443
      // op: Zn
20444
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20445
0
      op &= UINT64_C(31);
20446
0
      op <<= 5;
20447
0
      Value |= op;
20448
      // op: Zm
20449
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20450
0
      op &= UINT64_C(7);
20451
0
      op <<= 16;
20452
0
      Value |= op;
20453
      // op: imm4
20454
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
20455
0
      Value |= (op & UINT64_C(12)) << 17;
20456
0
      Value |= (op & UINT64_C(3)) << 10;
20457
0
      break;
20458
0
    }
20459
0
    case AArch64::BFMLA_ZZZI:
20460
0
    case AArch64::BFMLS_ZZZI:
20461
0
    case AArch64::FMLA_ZZZI_H:
20462
0
    case AArch64::FMLS_ZZZI_H:
20463
0
    case AArch64::MLA_ZZZI_H:
20464
0
    case AArch64::MLS_ZZZI_H:
20465
0
    case AArch64::SQRDMLAH_ZZZI_H:
20466
0
    case AArch64::SQRDMLSH_ZZZI_H: {
20467
      // op: Zda
20468
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20469
0
      op &= UINT64_C(31);
20470
0
      Value |= op;
20471
      // op: Zn
20472
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20473
0
      op &= UINT64_C(31);
20474
0
      op <<= 5;
20475
0
      Value |= op;
20476
      // op: Zm
20477
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20478
0
      op &= UINT64_C(7);
20479
0
      op <<= 16;
20480
0
      Value |= op;
20481
      // op: iop
20482
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
20483
0
      Value |= (op & UINT64_C(4)) << 20;
20484
0
      Value |= (op & UINT64_C(3)) << 19;
20485
0
      break;
20486
0
    }
20487
0
    case AArch64::BFMLALB_ZZZI:
20488
0
    case AArch64::BFMLALT_ZZZI:
20489
0
    case AArch64::BFMLSLB_ZZZI_S:
20490
0
    case AArch64::BFMLSLT_ZZZI_S:
20491
0
    case AArch64::FDOT_ZZZI_BtoH:
20492
0
    case AArch64::FMLALB_ZZZI_SHH:
20493
0
    case AArch64::FMLALT_ZZZI_SHH:
20494
0
    case AArch64::FMLSLB_ZZZI_SHH:
20495
0
    case AArch64::FMLSLT_ZZZI_SHH:
20496
0
    case AArch64::SMLALB_ZZZI_S:
20497
0
    case AArch64::SMLALT_ZZZI_S:
20498
0
    case AArch64::SMLSLB_ZZZI_S:
20499
0
    case AArch64::SMLSLT_ZZZI_S:
20500
0
    case AArch64::SQDMLALB_ZZZI_S:
20501
0
    case AArch64::SQDMLALT_ZZZI_S:
20502
0
    case AArch64::SQDMLSLB_ZZZI_S:
20503
0
    case AArch64::SQDMLSLT_ZZZI_S:
20504
0
    case AArch64::UMLALB_ZZZI_S:
20505
0
    case AArch64::UMLALT_ZZZI_S:
20506
0
    case AArch64::UMLSLB_ZZZI_S:
20507
0
    case AArch64::UMLSLT_ZZZI_S: {
20508
      // op: Zda
20509
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20510
0
      op &= UINT64_C(31);
20511
0
      Value |= op;
20512
      // op: Zn
20513
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20514
0
      op &= UINT64_C(31);
20515
0
      op <<= 5;
20516
0
      Value |= op;
20517
      // op: Zm
20518
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20519
0
      op &= UINT64_C(7);
20520
0
      op <<= 16;
20521
0
      Value |= op;
20522
      // op: iop
20523
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
20524
0
      Value |= (op & UINT64_C(6)) << 18;
20525
0
      Value |= (op & UINT64_C(1)) << 11;
20526
0
      break;
20527
0
    }
20528
0
    case AArch64::BFDOT_ZZI:
20529
0
    case AArch64::FDOT_ZZZI_BtoS:
20530
0
    case AArch64::FDOT_ZZZI_S:
20531
0
    case AArch64::FMLA_ZZZI_S:
20532
0
    case AArch64::FMLS_ZZZI_S:
20533
0
    case AArch64::MLA_ZZZI_S:
20534
0
    case AArch64::MLS_ZZZI_S:
20535
0
    case AArch64::SQRDMLAH_ZZZI_S:
20536
0
    case AArch64::SQRDMLSH_ZZZI_S: {
20537
      // op: Zda
20538
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20539
0
      op &= UINT64_C(31);
20540
0
      Value |= op;
20541
      // op: Zn
20542
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20543
0
      op &= UINT64_C(31);
20544
0
      op <<= 5;
20545
0
      Value |= op;
20546
      // op: Zm
20547
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20548
0
      op &= UINT64_C(7);
20549
0
      op <<= 16;
20550
0
      Value |= op;
20551
      // op: iop
20552
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
20553
0
      op &= UINT64_C(3);
20554
0
      op <<= 19;
20555
0
      Value |= op;
20556
0
      break;
20557
0
    }
20558
0
    case AArch64::FCMLA_ZZZI_S: {
20559
      // op: Zda
20560
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20561
0
      op &= UINT64_C(31);
20562
0
      Value |= op;
20563
      // op: Zn
20564
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20565
0
      op &= UINT64_C(31);
20566
0
      op <<= 5;
20567
0
      Value |= op;
20568
      // op: imm
20569
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
20570
0
      op &= UINT64_C(3);
20571
0
      op <<= 10;
20572
0
      Value |= op;
20573
      // op: Zm
20574
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20575
0
      op &= UINT64_C(15);
20576
0
      op <<= 16;
20577
0
      Value |= op;
20578
      // op: iop
20579
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
20580
0
      op &= UINT64_C(1);
20581
0
      op <<= 20;
20582
0
      Value |= op;
20583
0
      break;
20584
0
    }
20585
0
    case AArch64::FCMLA_ZZZI_H: {
20586
      // op: Zda
20587
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20588
0
      op &= UINT64_C(31);
20589
0
      Value |= op;
20590
      // op: Zn
20591
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20592
0
      op &= UINT64_C(31);
20593
0
      op <<= 5;
20594
0
      Value |= op;
20595
      // op: imm
20596
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
20597
0
      op &= UINT64_C(3);
20598
0
      op <<= 10;
20599
0
      Value |= op;
20600
      // op: Zm
20601
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20602
0
      op &= UINT64_C(7);
20603
0
      op <<= 16;
20604
0
      Value |= op;
20605
      // op: iop
20606
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
20607
0
      op &= UINT64_C(3);
20608
0
      op <<= 19;
20609
0
      Value |= op;
20610
0
      break;
20611
0
    }
20612
0
    case AArch64::SRSRA_ZZI_H:
20613
0
    case AArch64::SSRA_ZZI_H:
20614
0
    case AArch64::URSRA_ZZI_H:
20615
0
    case AArch64::USRA_ZZI_H: {
20616
      // op: Zda
20617
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20618
0
      op &= UINT64_C(31);
20619
0
      Value |= op;
20620
      // op: Zn
20621
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20622
0
      op &= UINT64_C(31);
20623
0
      op <<= 5;
20624
0
      Value |= op;
20625
      // op: imm
20626
0
      op = getVecShiftR16OpValue(MI, 3, Fixups, STI);
20627
0
      op &= UINT64_C(15);
20628
0
      op <<= 16;
20629
0
      Value |= op;
20630
0
      break;
20631
0
    }
20632
0
    case AArch64::SRSRA_ZZI_S:
20633
0
    case AArch64::SSRA_ZZI_S:
20634
0
    case AArch64::URSRA_ZZI_S:
20635
0
    case AArch64::USRA_ZZI_S: {
20636
      // op: Zda
20637
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20638
0
      op &= UINT64_C(31);
20639
0
      Value |= op;
20640
      // op: Zn
20641
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20642
0
      op &= UINT64_C(31);
20643
0
      op <<= 5;
20644
0
      Value |= op;
20645
      // op: imm
20646
0
      op = getVecShiftR32OpValue(MI, 3, Fixups, STI);
20647
0
      op &= UINT64_C(31);
20648
0
      op <<= 16;
20649
0
      Value |= op;
20650
0
      break;
20651
0
    }
20652
0
    case AArch64::SRSRA_ZZI_D:
20653
0
    case AArch64::SSRA_ZZI_D:
20654
0
    case AArch64::URSRA_ZZI_D:
20655
0
    case AArch64::USRA_ZZI_D: {
20656
      // op: Zda
20657
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20658
0
      op &= UINT64_C(31);
20659
0
      Value |= op;
20660
      // op: Zn
20661
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20662
0
      op &= UINT64_C(31);
20663
0
      op <<= 5;
20664
0
      Value |= op;
20665
      // op: imm
20666
0
      op = getVecShiftR64OpValue(MI, 3, Fixups, STI);
20667
0
      Value |= (op & UINT64_C(32)) << 17;
20668
0
      Value |= (op & UINT64_C(31)) << 16;
20669
0
      break;
20670
0
    }
20671
0
    case AArch64::SRSRA_ZZI_B:
20672
0
    case AArch64::SSRA_ZZI_B:
20673
0
    case AArch64::URSRA_ZZI_B:
20674
0
    case AArch64::USRA_ZZI_B: {
20675
      // op: Zda
20676
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20677
0
      op &= UINT64_C(31);
20678
0
      Value |= op;
20679
      // op: Zn
20680
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20681
0
      op &= UINT64_C(31);
20682
0
      op <<= 5;
20683
0
      Value |= op;
20684
      // op: imm
20685
0
      op = getVecShiftR8OpValue(MI, 3, Fixups, STI);
20686
0
      op &= UINT64_C(7);
20687
0
      op <<= 16;
20688
0
      Value |= op;
20689
0
      break;
20690
0
    }
20691
0
    case AArch64::SDOT_ZZZI_D:
20692
0
    case AArch64::UDOT_ZZZI_D: {
20693
      // op: Zda
20694
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20695
0
      op &= UINT64_C(31);
20696
0
      Value |= op;
20697
      // op: Zn
20698
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20699
0
      op &= UINT64_C(31);
20700
0
      op <<= 5;
20701
0
      Value |= op;
20702
      // op: iop
20703
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
20704
0
      op &= UINT64_C(1);
20705
0
      op <<= 20;
20706
0
      Value |= op;
20707
      // op: Zm
20708
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20709
0
      op &= UINT64_C(15);
20710
0
      op <<= 16;
20711
0
      Value |= op;
20712
0
      break;
20713
0
    }
20714
0
    case AArch64::SDOT_ZZZI_S:
20715
0
    case AArch64::UDOT_ZZZI_S: {
20716
      // op: Zda
20717
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20718
0
      op &= UINT64_C(31);
20719
0
      Value |= op;
20720
      // op: Zn
20721
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20722
0
      op &= UINT64_C(31);
20723
0
      op <<= 5;
20724
0
      Value |= op;
20725
      // op: iop
20726
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
20727
0
      op &= UINT64_C(3);
20728
0
      op <<= 19;
20729
0
      Value |= op;
20730
      // op: Zm
20731
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20732
0
      op &= UINT64_C(7);
20733
0
      op <<= 16;
20734
0
      Value |= op;
20735
0
      break;
20736
0
    }
20737
0
    case AArch64::CDOT_ZZZI_D:
20738
0
    case AArch64::CMLA_ZZZI_S:
20739
0
    case AArch64::SQRDCMLAH_ZZZI_S: {
20740
      // op: Zda
20741
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20742
0
      op &= UINT64_C(31);
20743
0
      Value |= op;
20744
      // op: Zn
20745
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20746
0
      op &= UINT64_C(31);
20747
0
      op <<= 5;
20748
0
      Value |= op;
20749
      // op: rot
20750
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
20751
0
      op &= UINT64_C(3);
20752
0
      op <<= 10;
20753
0
      Value |= op;
20754
      // op: iop
20755
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
20756
0
      op &= UINT64_C(1);
20757
0
      op <<= 20;
20758
0
      Value |= op;
20759
      // op: Zm
20760
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20761
0
      op &= UINT64_C(15);
20762
0
      op <<= 16;
20763
0
      Value |= op;
20764
0
      break;
20765
0
    }
20766
0
    case AArch64::CDOT_ZZZI_S:
20767
0
    case AArch64::CMLA_ZZZI_H:
20768
0
    case AArch64::SQRDCMLAH_ZZZI_H: {
20769
      // op: Zda
20770
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20771
0
      op &= UINT64_C(31);
20772
0
      Value |= op;
20773
      // op: Zn
20774
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20775
0
      op &= UINT64_C(31);
20776
0
      op <<= 5;
20777
0
      Value |= op;
20778
      // op: rot
20779
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
20780
0
      op &= UINT64_C(3);
20781
0
      op <<= 10;
20782
0
      Value |= op;
20783
      // op: iop
20784
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
20785
0
      op &= UINT64_C(3);
20786
0
      op <<= 19;
20787
0
      Value |= op;
20788
      // op: Zm
20789
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20790
0
      op &= UINT64_C(7);
20791
0
      op <<= 16;
20792
0
      Value |= op;
20793
0
      break;
20794
0
    }
20795
0
    case AArch64::AESIMC_ZZ_B:
20796
0
    case AArch64::AESMC_ZZ_B: {
20797
      // op: Zdn
20798
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20799
0
      op &= UINT64_C(31);
20800
0
      Value |= op;
20801
0
      break;
20802
0
    }
20803
0
    case AArch64::BCAX_ZZZZ:
20804
0
    case AArch64::BSL1N_ZZZZ:
20805
0
    case AArch64::BSL2N_ZZZZ:
20806
0
    case AArch64::BSL_ZZZZ:
20807
0
    case AArch64::EOR3_ZZZZ:
20808
0
    case AArch64::NBSL_ZZZZ: {
20809
      // op: Zdn
20810
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20811
0
      op &= UINT64_C(31);
20812
0
      Value |= op;
20813
      // op: Zk
20814
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20815
0
      op &= UINT64_C(31);
20816
0
      op <<= 5;
20817
0
      Value |= op;
20818
      // op: Zm
20819
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20820
0
      op &= UINT64_C(31);
20821
0
      op <<= 16;
20822
0
      Value |= op;
20823
0
      break;
20824
0
    }
20825
0
    case AArch64::MAD_CPA: {
20826
      // op: Zdn
20827
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20828
0
      op &= UINT64_C(31);
20829
0
      Value |= op;
20830
      // op: Zm
20831
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20832
0
      op &= UINT64_C(31);
20833
0
      op <<= 16;
20834
0
      Value |= op;
20835
      // op: Za
20836
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20837
0
      op &= UINT64_C(31);
20838
0
      op <<= 5;
20839
0
      Value |= op;
20840
0
      break;
20841
0
    }
20842
0
    case AArch64::AESD_ZZZ_B:
20843
0
    case AArch64::AESE_ZZZ_B:
20844
0
    case AArch64::SM4E_ZZZ_S: {
20845
      // op: Zdn
20846
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20847
0
      op &= UINT64_C(31);
20848
0
      Value |= op;
20849
      // op: Zm
20850
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20851
0
      op &= UINT64_C(31);
20852
0
      op <<= 5;
20853
0
      Value |= op;
20854
0
      break;
20855
0
    }
20856
0
    case AArch64::XAR_ZZZI_H: {
20857
      // op: Zdn
20858
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20859
0
      op &= UINT64_C(31);
20860
0
      Value |= op;
20861
      // op: Zm
20862
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20863
0
      op &= UINT64_C(31);
20864
0
      op <<= 5;
20865
0
      Value |= op;
20866
      // op: imm
20867
0
      op = getVecShiftR16OpValue(MI, 3, Fixups, STI);
20868
0
      op &= UINT64_C(15);
20869
0
      op <<= 16;
20870
0
      Value |= op;
20871
0
      break;
20872
0
    }
20873
0
    case AArch64::XAR_ZZZI_S: {
20874
      // op: Zdn
20875
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20876
0
      op &= UINT64_C(31);
20877
0
      Value |= op;
20878
      // op: Zm
20879
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20880
0
      op &= UINT64_C(31);
20881
0
      op <<= 5;
20882
0
      Value |= op;
20883
      // op: imm
20884
0
      op = getVecShiftR32OpValue(MI, 3, Fixups, STI);
20885
0
      op &= UINT64_C(31);
20886
0
      op <<= 16;
20887
0
      Value |= op;
20888
0
      break;
20889
0
    }
20890
0
    case AArch64::XAR_ZZZI_D: {
20891
      // op: Zdn
20892
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20893
0
      op &= UINT64_C(31);
20894
0
      Value |= op;
20895
      // op: Zm
20896
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20897
0
      op &= UINT64_C(31);
20898
0
      op <<= 5;
20899
0
      Value |= op;
20900
      // op: imm
20901
0
      op = getVecShiftR64OpValue(MI, 3, Fixups, STI);
20902
0
      Value |= (op & UINT64_C(32)) << 17;
20903
0
      Value |= (op & UINT64_C(31)) << 16;
20904
0
      break;
20905
0
    }
20906
0
    case AArch64::XAR_ZZZI_B: {
20907
      // op: Zdn
20908
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20909
0
      op &= UINT64_C(31);
20910
0
      Value |= op;
20911
      // op: Zm
20912
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20913
0
      op &= UINT64_C(31);
20914
0
      op <<= 5;
20915
0
      Value |= op;
20916
      // op: imm
20917
0
      op = getVecShiftR8OpValue(MI, 3, Fixups, STI);
20918
0
      op &= UINT64_C(7);
20919
0
      op <<= 16;
20920
0
      Value |= op;
20921
0
      break;
20922
0
    }
20923
0
    case AArch64::FTMAD_ZZI_D:
20924
0
    case AArch64::FTMAD_ZZI_H:
20925
0
    case AArch64::FTMAD_ZZI_S: {
20926
      // op: Zdn
20927
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20928
0
      op &= UINT64_C(31);
20929
0
      Value |= op;
20930
      // op: Zm
20931
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20932
0
      op &= UINT64_C(31);
20933
0
      op <<= 5;
20934
0
      Value |= op;
20935
      // op: imm3
20936
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20937
0
      op &= UINT64_C(7);
20938
0
      op <<= 16;
20939
0
      Value |= op;
20940
0
      break;
20941
0
    }
20942
0
    case AArch64::EXTQ_ZZI: {
20943
      // op: Zdn
20944
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20945
0
      op &= UINT64_C(31);
20946
0
      Value |= op;
20947
      // op: Zm
20948
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20949
0
      op &= UINT64_C(31);
20950
0
      op <<= 5;
20951
0
      Value |= op;
20952
      // op: imm4
20953
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20954
0
      op &= UINT64_C(15);
20955
0
      op <<= 16;
20956
0
      Value |= op;
20957
0
      break;
20958
0
    }
20959
0
    case AArch64::EXT_ZZI: {
20960
      // op: Zdn
20961
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20962
0
      op &= UINT64_C(31);
20963
0
      Value |= op;
20964
      // op: Zm
20965
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20966
0
      op &= UINT64_C(31);
20967
0
      op <<= 5;
20968
0
      Value |= op;
20969
      // op: imm8
20970
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20971
0
      Value |= (op & UINT64_C(248)) << 13;
20972
0
      Value |= (op & UINT64_C(7)) << 10;
20973
0
      break;
20974
0
    }
20975
0
    case AArch64::CADD_ZZI_B:
20976
0
    case AArch64::CADD_ZZI_D:
20977
0
    case AArch64::CADD_ZZI_H:
20978
0
    case AArch64::CADD_ZZI_S:
20979
0
    case AArch64::SQCADD_ZZI_B:
20980
0
    case AArch64::SQCADD_ZZI_D:
20981
0
    case AArch64::SQCADD_ZZI_H:
20982
0
    case AArch64::SQCADD_ZZI_S: {
20983
      // op: Zdn
20984
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
20985
0
      op &= UINT64_C(31);
20986
0
      Value |= op;
20987
      // op: Zm
20988
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
20989
0
      op &= UINT64_C(31);
20990
0
      op <<= 5;
20991
0
      Value |= op;
20992
      // op: rot
20993
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
20994
0
      op &= UINT64_C(1);
20995
0
      op <<= 10;
20996
0
      Value |= op;
20997
0
      break;
20998
0
    }
20999
0
    case AArch64::FCADD_ZPmZ_D:
21000
0
    case AArch64::FCADD_ZPmZ_H:
21001
0
    case AArch64::FCADD_ZPmZ_S: {
21002
      // op: Zdn
21003
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
21004
0
      op &= UINT64_C(31);
21005
0
      Value |= op;
21006
      // op: Zm
21007
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
21008
0
      op &= UINT64_C(31);
21009
0
      op <<= 5;
21010
0
      Value |= op;
21011
      // op: Pg
21012
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
21013
0
      op &= UINT64_C(7);
21014
0
      op <<= 10;
21015
0
      Value |= op;
21016
      // op: imm
21017
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
21018
0
      op &= UINT64_C(1);
21019
0
      op <<= 16;
21020
0
      Value |= op;
21021
0
      break;
21022
0
    }
21023
0
    case AArch64::ADD_ZI_B:
21024
0
    case AArch64::ADD_ZI_D:
21025
0
    case AArch64::ADD_ZI_H:
21026
0
    case AArch64::ADD_ZI_S:
21027
0
    case AArch64::SQADD_ZI_B:
21028
0
    case AArch64::SQADD_ZI_D:
21029
0
    case AArch64::SQADD_ZI_H:
21030
0
    case AArch64::SQADD_ZI_S:
21031
0
    case AArch64::SQSUB_ZI_B:
21032
0
    case AArch64::SQSUB_ZI_D:
21033
0
    case AArch64::SQSUB_ZI_H:
21034
0
    case AArch64::SQSUB_ZI_S:
21035
0
    case AArch64::SUBR_ZI_B:
21036
0
    case AArch64::SUBR_ZI_D:
21037
0
    case AArch64::SUBR_ZI_H:
21038
0
    case AArch64::SUBR_ZI_S:
21039
0
    case AArch64::SUB_ZI_B:
21040
0
    case AArch64::SUB_ZI_D:
21041
0
    case AArch64::SUB_ZI_H:
21042
0
    case AArch64::SUB_ZI_S:
21043
0
    case AArch64::UQADD_ZI_B:
21044
0
    case AArch64::UQADD_ZI_D:
21045
0
    case AArch64::UQADD_ZI_H:
21046
0
    case AArch64::UQADD_ZI_S:
21047
0
    case AArch64::UQSUB_ZI_B:
21048
0
    case AArch64::UQSUB_ZI_D:
21049
0
    case AArch64::UQSUB_ZI_H:
21050
0
    case AArch64::UQSUB_ZI_S: {
21051
      // op: Zdn
21052
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
21053
0
      op &= UINT64_C(31);
21054
0
      Value |= op;
21055
      // op: imm
21056
0
      op = getImm8OptLsl(MI, 2, Fixups, STI);
21057
0
      op &= UINT64_C(511);
21058
0
      op <<= 5;
21059
0
      Value |= op;
21060
0
      break;
21061
0
    }
21062
0
    case AArch64::MUL_ZI_B:
21063
0
    case AArch64::MUL_ZI_D:
21064
0
    case AArch64::MUL_ZI_H:
21065
0
    case AArch64::MUL_ZI_S:
21066
0
    case AArch64::SMAX_ZI_B:
21067
0
    case AArch64::SMAX_ZI_D:
21068
0
    case AArch64::SMAX_ZI_H:
21069
0
    case AArch64::SMAX_ZI_S:
21070
0
    case AArch64::SMIN_ZI_B:
21071
0
    case AArch64::SMIN_ZI_D:
21072
0
    case AArch64::SMIN_ZI_H:
21073
0
    case AArch64::SMIN_ZI_S:
21074
0
    case AArch64::UMAX_ZI_B:
21075
0
    case AArch64::UMAX_ZI_D:
21076
0
    case AArch64::UMAX_ZI_H:
21077
0
    case AArch64::UMAX_ZI_S:
21078
0
    case AArch64::UMIN_ZI_B:
21079
0
    case AArch64::UMIN_ZI_D:
21080
0
    case AArch64::UMIN_ZI_H:
21081
0
    case AArch64::UMIN_ZI_S: {
21082
      // op: Zdn
21083
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
21084
0
      op &= UINT64_C(31);
21085
0
      Value |= op;
21086
      // op: imm
21087
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
21088
0
      op &= UINT64_C(255);
21089
0
      op <<= 5;
21090
0
      Value |= op;
21091
0
      break;
21092
0
    }
21093
0
    case AArch64::AND_ZI:
21094
0
    case AArch64::EOR_ZI:
21095
0
    case AArch64::ORR_ZI: {
21096
      // op: Zdn
21097
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
21098
0
      op &= UINT64_C(31);
21099
0
      Value |= op;
21100
      // op: imms13
21101
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
21102
0
      op &= UINT64_C(8191);
21103
0
      op <<= 5;
21104
0
      Value |= op;
21105
0
      break;
21106
0
    }
21107
0
    case AArch64::DECD_ZPiI:
21108
0
    case AArch64::DECH_ZPiI:
21109
0
    case AArch64::DECW_ZPiI:
21110
0
    case AArch64::INCD_ZPiI:
21111
0
    case AArch64::INCH_ZPiI:
21112
0
    case AArch64::INCW_ZPiI:
21113
0
    case AArch64::SQDECD_ZPiI:
21114
0
    case AArch64::SQDECH_ZPiI:
21115
0
    case AArch64::SQDECW_ZPiI:
21116
0
    case AArch64::SQINCD_ZPiI:
21117
0
    case AArch64::SQINCH_ZPiI:
21118
0
    case AArch64::SQINCW_ZPiI:
21119
0
    case AArch64::UQDECD_ZPiI:
21120
0
    case AArch64::UQDECH_ZPiI:
21121
0
    case AArch64::UQDECW_ZPiI:
21122
0
    case AArch64::UQINCD_ZPiI:
21123
0
    case AArch64::UQINCH_ZPiI:
21124
0
    case AArch64::UQINCW_ZPiI: {
21125
      // op: Zdn
21126
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
21127
0
      op &= UINT64_C(31);
21128
0
      Value |= op;
21129
      // op: pattern
21130
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
21131
0
      op &= UINT64_C(31);
21132
0
      op <<= 5;
21133
0
      Value |= op;
21134
      // op: imm4
21135
0
      op = getSVEIncDecImm(MI, 3, Fixups, STI);
21136
0
      op &= UINT64_C(15);
21137
0
      op <<= 16;
21138
0
      Value |= op;
21139
0
      break;
21140
0
    }
21141
0
    case AArch64::BFMAXNM_VG2_2Z2Z_H:
21142
0
    case AArch64::BFMAX_VG2_2Z2Z_H:
21143
0
    case AArch64::BFMINNM_VG2_2Z2Z_H:
21144
0
    case AArch64::BFMIN_VG2_2Z2Z_H:
21145
0
    case AArch64::FAMAX_2Z2Z_D:
21146
0
    case AArch64::FAMAX_2Z2Z_H:
21147
0
    case AArch64::FAMAX_2Z2Z_S:
21148
0
    case AArch64::FAMIN_2Z2Z_D:
21149
0
    case AArch64::FAMIN_2Z2Z_H:
21150
0
    case AArch64::FAMIN_2Z2Z_S:
21151
0
    case AArch64::FMAXNM_VG2_2Z2Z_D:
21152
0
    case AArch64::FMAXNM_VG2_2Z2Z_H:
21153
0
    case AArch64::FMAXNM_VG2_2Z2Z_S:
21154
0
    case AArch64::FMAX_VG2_2Z2Z_D:
21155
0
    case AArch64::FMAX_VG2_2Z2Z_H:
21156
0
    case AArch64::FMAX_VG2_2Z2Z_S:
21157
0
    case AArch64::FMINNM_VG2_2Z2Z_D:
21158
0
    case AArch64::FMINNM_VG2_2Z2Z_H:
21159
0
    case AArch64::FMINNM_VG2_2Z2Z_S:
21160
0
    case AArch64::FMIN_VG2_2Z2Z_D:
21161
0
    case AArch64::FMIN_VG2_2Z2Z_H:
21162
0
    case AArch64::FMIN_VG2_2Z2Z_S:
21163
0
    case AArch64::FSCALE_2Z2Z_D:
21164
0
    case AArch64::FSCALE_2Z2Z_H:
21165
0
    case AArch64::FSCALE_2Z2Z_S:
21166
0
    case AArch64::SMAX_VG2_2Z2Z_B:
21167
0
    case AArch64::SMAX_VG2_2Z2Z_D:
21168
0
    case AArch64::SMAX_VG2_2Z2Z_H:
21169
0
    case AArch64::SMAX_VG2_2Z2Z_S:
21170
0
    case AArch64::SMIN_VG2_2Z2Z_B:
21171
0
    case AArch64::SMIN_VG2_2Z2Z_D:
21172
0
    case AArch64::SMIN_VG2_2Z2Z_H:
21173
0
    case AArch64::SMIN_VG2_2Z2Z_S:
21174
0
    case AArch64::SQDMULH_VG2_2Z2Z_B:
21175
0
    case AArch64::SQDMULH_VG2_2Z2Z_D:
21176
0
    case AArch64::SQDMULH_VG2_2Z2Z_H:
21177
0
    case AArch64::SQDMULH_VG2_2Z2Z_S:
21178
0
    case AArch64::SRSHL_VG2_2Z2Z_B:
21179
0
    case AArch64::SRSHL_VG2_2Z2Z_D:
21180
0
    case AArch64::SRSHL_VG2_2Z2Z_H:
21181
0
    case AArch64::SRSHL_VG2_2Z2Z_S:
21182
0
    case AArch64::UMAX_VG2_2Z2Z_B:
21183
0
    case AArch64::UMAX_VG2_2Z2Z_D:
21184
0
    case AArch64::UMAX_VG2_2Z2Z_H:
21185
0
    case AArch64::UMAX_VG2_2Z2Z_S:
21186
0
    case AArch64::UMIN_VG2_2Z2Z_B:
21187
0
    case AArch64::UMIN_VG2_2Z2Z_D:
21188
0
    case AArch64::UMIN_VG2_2Z2Z_H:
21189
0
    case AArch64::UMIN_VG2_2Z2Z_S:
21190
0
    case AArch64::URSHL_VG2_2Z2Z_B:
21191
0
    case AArch64::URSHL_VG2_2Z2Z_D:
21192
0
    case AArch64::URSHL_VG2_2Z2Z_H:
21193
0
    case AArch64::URSHL_VG2_2Z2Z_S: {
21194
      // op: Zm
21195
0
      op = EncodeRegAsMultipleOf<2>(MI, 2, Fixups, STI);
21196
0
      op &= UINT64_C(15);
21197
0
      op <<= 17;
21198
0
      Value |= op;
21199
      // op: Zdn
21200
0
      op = EncodeRegAsMultipleOf<2>(MI, 0, Fixups, STI);
21201
0
      op &= UINT64_C(15);
21202
0
      op <<= 1;
21203
0
      Value |= op;
21204
0
      break;
21205
0
    }
21206
0
    case AArch64::FMLALL_VG2_M2Z2Z_BtoS:
21207
0
    case AArch64::SMLALL_VG2_M2Z2Z_BtoS:
21208
0
    case AArch64::SMLALL_VG2_M2Z2Z_HtoD:
21209
0
    case AArch64::SMLSLL_VG2_M2Z2Z_BtoS:
21210
0
    case AArch64::SMLSLL_VG2_M2Z2Z_HtoD:
21211
0
    case AArch64::UMLALL_VG2_M2Z2Z_BtoS:
21212
0
    case AArch64::UMLALL_VG2_M2Z2Z_HtoD:
21213
0
    case AArch64::UMLSLL_VG2_M2Z2Z_BtoS:
21214
0
    case AArch64::UMLSLL_VG2_M2Z2Z_HtoD:
21215
0
    case AArch64::USMLALL_VG2_M2Z2Z_BtoS: {
21216
      // op: Zm
21217
0
      op = EncodeRegAsMultipleOf<2>(MI, 5, Fixups, STI);
21218
0
      op &= UINT64_C(15);
21219
0
      op <<= 17;
21220
0
      Value |= op;
21221
      // op: Rv
21222
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
21223
0
      op &= UINT64_C(3);
21224
0
      op <<= 13;
21225
0
      Value |= op;
21226
      // op: Zn
21227
0
      op = EncodeRegAsMultipleOf<2>(MI, 4, Fixups, STI);
21228
0
      op &= UINT64_C(15);
21229
0
      op <<= 6;
21230
0
      Value |= op;
21231
      // op: imm
21232
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
21233
0
      op &= UINT64_C(1);
21234
0
      Value |= op;
21235
0
      break;
21236
0
    }
21237
0
    case AArch64::ADD_VG2_M2Z2Z_D:
21238
0
    case AArch64::ADD_VG2_M2Z2Z_S:
21239
0
    case AArch64::BFDOT_VG2_M2Z2Z_HtoS:
21240
0
    case AArch64::BFMLA_VG2_M2Z2Z:
21241
0
    case AArch64::BFMLS_VG2_M2Z2Z:
21242
0
    case AArch64::FDOT_VG2_M2Z2Z_BtoH:
21243
0
    case AArch64::FDOT_VG2_M2Z2Z_BtoS:
21244
0
    case AArch64::FDOT_VG2_M2Z2Z_HtoS:
21245
0
    case AArch64::FMLA_VG2_M2Z2Z_D:
21246
0
    case AArch64::FMLA_VG2_M2Z2Z_S:
21247
0
    case AArch64::FMLA_VG2_M2Z4Z_H:
21248
0
    case AArch64::FMLS_VG2_M2Z2Z_D:
21249
0
    case AArch64::FMLS_VG2_M2Z2Z_H:
21250
0
    case AArch64::FMLS_VG2_M2Z2Z_S:
21251
0
    case AArch64::SDOT_VG2_M2Z2Z_BtoS:
21252
0
    case AArch64::SDOT_VG2_M2Z2Z_HtoD:
21253
0
    case AArch64::SDOT_VG2_M2Z2Z_HtoS:
21254
0
    case AArch64::SUB_VG2_M2Z2Z_D:
21255
0
    case AArch64::SUB_VG2_M2Z2Z_S:
21256
0
    case AArch64::UDOT_VG2_M2Z2Z_BtoS:
21257
0
    case AArch64::UDOT_VG2_M2Z2Z_HtoD:
21258
0
    case AArch64::UDOT_VG2_M2Z2Z_HtoS:
21259
0
    case AArch64::USDOT_VG2_M2Z2Z_BToS: {
21260
      // op: Zm
21261
0
      op = EncodeRegAsMultipleOf<2>(MI, 5, Fixups, STI);
21262
0
      op &= UINT64_C(15);
21263
0
      op <<= 17;
21264
0
      Value |= op;
21265
      // op: Zn
21266
0
      op = EncodeRegAsMultipleOf<2>(MI, 4, Fixups, STI);
21267
0
      op &= UINT64_C(15);
21268
0
      op <<= 6;
21269
0
      Value |= op;
21270
      // op: Rv
21271
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
21272
0
      op &= UINT64_C(3);
21273
0
      op <<= 13;
21274
0
      Value |= op;
21275
      // op: imm3
21276
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
21277
0
      op &= UINT64_C(7);
21278
0
      Value |= op;
21279
0
      break;
21280
0
    }
21281
0
    case AArch64::BFMAXNM_VG4_4Z2Z_H:
21282
0
    case AArch64::BFMAX_VG4_4Z2Z_H:
21283
0
    case AArch64::BFMINNM_VG4_4Z2Z_H:
21284
0
    case AArch64::BFMIN_VG4_4Z2Z_H:
21285
0
    case AArch64::FAMAX_4Z4Z_D:
21286
0
    case AArch64::FAMAX_4Z4Z_H:
21287
0
    case AArch64::FAMAX_4Z4Z_S:
21288
0
    case AArch64::FAMIN_4Z4Z_D:
21289
0
    case AArch64::FAMIN_4Z4Z_H:
21290
0
    case AArch64::FAMIN_4Z4Z_S:
21291
0
    case AArch64::FMAXNM_VG4_4Z4Z_D:
21292
0
    case AArch64::FMAXNM_VG4_4Z4Z_H:
21293
0
    case AArch64::FMAXNM_VG4_4Z4Z_S:
21294
0
    case AArch64::FMAX_VG4_4Z4Z_D:
21295
0
    case AArch64::FMAX_VG4_4Z4Z_H:
21296
0
    case AArch64::FMAX_VG4_4Z4Z_S:
21297
0
    case AArch64::FMINNM_VG4_4Z4Z_D:
21298
0
    case AArch64::FMINNM_VG4_4Z4Z_H:
21299
0
    case AArch64::FMINNM_VG4_4Z4Z_S:
21300
0
    case AArch64::FMIN_VG4_4Z4Z_D:
21301
0
    case AArch64::FMIN_VG4_4Z4Z_H:
21302
0
    case AArch64::FMIN_VG4_4Z4Z_S:
21303
0
    case AArch64::FSCALE_4Z4Z_D:
21304
0
    case AArch64::FSCALE_4Z4Z_H:
21305
0
    case AArch64::FSCALE_4Z4Z_S:
21306
0
    case AArch64::SMAX_VG4_4Z4Z_B:
21307
0
    case AArch64::SMAX_VG4_4Z4Z_D:
21308
0
    case AArch64::SMAX_VG4_4Z4Z_H:
21309
0
    case AArch64::SMAX_VG4_4Z4Z_S:
21310
0
    case AArch64::SMIN_VG4_4Z4Z_B:
21311
0
    case AArch64::SMIN_VG4_4Z4Z_D:
21312
0
    case AArch64::SMIN_VG4_4Z4Z_H:
21313
0
    case AArch64::SMIN_VG4_4Z4Z_S:
21314
0
    case AArch64::SQDMULH_VG4_4Z4Z_B:
21315
0
    case AArch64::SQDMULH_VG4_4Z4Z_D:
21316
0
    case AArch64::SQDMULH_VG4_4Z4Z_H:
21317
0
    case AArch64::SQDMULH_VG4_4Z4Z_S:
21318
0
    case AArch64::SRSHL_VG4_4Z4Z_B:
21319
0
    case AArch64::SRSHL_VG4_4Z4Z_D:
21320
0
    case AArch64::SRSHL_VG4_4Z4Z_H:
21321
0
    case AArch64::SRSHL_VG4_4Z4Z_S:
21322
0
    case AArch64::UMAX_VG4_4Z4Z_B:
21323
0
    case AArch64::UMAX_VG4_4Z4Z_D:
21324
0
    case AArch64::UMAX_VG4_4Z4Z_H:
21325
0
    case AArch64::UMAX_VG4_4Z4Z_S:
21326
0
    case AArch64::UMIN_VG4_4Z4Z_B:
21327
0
    case AArch64::UMIN_VG4_4Z4Z_D:
21328
0
    case AArch64::UMIN_VG4_4Z4Z_H:
21329
0
    case AArch64::UMIN_VG4_4Z4Z_S:
21330
0
    case AArch64::URSHL_VG4_4Z4Z_B:
21331
0
    case AArch64::URSHL_VG4_4Z4Z_D:
21332
0
    case AArch64::URSHL_VG4_4Z4Z_H:
21333
0
    case AArch64::URSHL_VG4_4Z4Z_S: {
21334
      // op: Zm
21335
0
      op = EncodeRegAsMultipleOf<4>(MI, 2, Fixups, STI);
21336
0
      op &= UINT64_C(7);
21337
0
      op <<= 18;
21338
0
      Value |= op;
21339
      // op: Zdn
21340
0
      op = EncodeRegAsMultipleOf<4>(MI, 0, Fixups, STI);
21341
0
      op &= UINT64_C(7);
21342
0
      op <<= 2;
21343
0
      Value |= op;
21344
0
      break;
21345
0
    }
21346
0
    case AArch64::FMLALL_VG4_M4Z4Z_BtoS:
21347
0
    case AArch64::SMLALL_VG4_M4Z4Z_BtoS:
21348
0
    case AArch64::SMLALL_VG4_M4Z4Z_HtoD:
21349
0
    case AArch64::SMLSLL_VG4_M4Z4Z_BtoS:
21350
0
    case AArch64::SMLSLL_VG4_M4Z4Z_HtoD:
21351
0
    case AArch64::UMLALL_VG4_M4Z4Z_BtoS:
21352
0
    case AArch64::UMLALL_VG4_M4Z4Z_HtoD:
21353
0
    case AArch64::UMLSLL_VG4_M4Z4Z_BtoS:
21354
0
    case AArch64::UMLSLL_VG4_M4Z4Z_HtoD:
21355
0
    case AArch64::USMLALL_VG4_M4Z4Z_BtoS: {
21356
      // op: Zm
21357
0
      op = EncodeRegAsMultipleOf<4>(MI, 5, Fixups, STI);
21358
0
      op &= UINT64_C(7);
21359
0
      op <<= 18;
21360
0
      Value |= op;
21361
      // op: Rv
21362
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
21363
0
      op &= UINT64_C(3);
21364
0
      op <<= 13;
21365
0
      Value |= op;
21366
      // op: Zn
21367
0
      op = EncodeRegAsMultipleOf<4>(MI, 4, Fixups, STI);
21368
0
      op &= UINT64_C(7);
21369
0
      op <<= 7;
21370
0
      Value |= op;
21371
      // op: imm
21372
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
21373
0
      op &= UINT64_C(1);
21374
0
      Value |= op;
21375
0
      break;
21376
0
    }
21377
0
    case AArch64::ADD_VG4_M4Z4Z_D:
21378
0
    case AArch64::ADD_VG4_M4Z4Z_S:
21379
0
    case AArch64::BFDOT_VG4_M4Z4Z_HtoS:
21380
0
    case AArch64::BFMLA_VG4_M4Z4Z:
21381
0
    case AArch64::BFMLS_VG4_M4Z4Z:
21382
0
    case AArch64::FDOT_VG4_M4Z4Z_BtoH:
21383
0
    case AArch64::FDOT_VG4_M4Z4Z_BtoS:
21384
0
    case AArch64::FDOT_VG4_M4Z4Z_HtoS:
21385
0
    case AArch64::FMLA_VG4_M4Z4Z_D:
21386
0
    case AArch64::FMLA_VG4_M4Z4Z_H:
21387
0
    case AArch64::FMLA_VG4_M4Z4Z_S:
21388
0
    case AArch64::FMLS_VG4_M4Z2Z_H:
21389
0
    case AArch64::FMLS_VG4_M4Z4Z_D:
21390
0
    case AArch64::FMLS_VG4_M4Z4Z_S:
21391
0
    case AArch64::SDOT_VG4_M4Z4Z_BtoS:
21392
0
    case AArch64::SDOT_VG4_M4Z4Z_HtoD:
21393
0
    case AArch64::SDOT_VG4_M4Z4Z_HtoS:
21394
0
    case AArch64::SUB_VG4_M4Z4Z_D:
21395
0
    case AArch64::SUB_VG4_M4Z4Z_S:
21396
0
    case AArch64::UDOT_VG4_M4Z4Z_BtoS:
21397
0
    case AArch64::UDOT_VG4_M4Z4Z_HtoD:
21398
0
    case AArch64::UDOT_VG4_M4Z4Z_HtoS:
21399
0
    case AArch64::USDOT_VG4_M4Z4Z_BToS: {
21400
      // op: Zm
21401
0
      op = EncodeRegAsMultipleOf<4>(MI, 5, Fixups, STI);
21402
0
      op &= UINT64_C(7);
21403
0
      op <<= 18;
21404
0
      Value |= op;
21405
      // op: Zn
21406
0
      op = EncodeRegAsMultipleOf<4>(MI, 4, Fixups, STI);
21407
0
      op &= UINT64_C(7);
21408
0
      op <<= 7;
21409
0
      Value |= op;
21410
      // op: Rv
21411
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
21412
0
      op &= UINT64_C(3);
21413
0
      op <<= 13;
21414
0
      Value |= op;
21415
      // op: imm3
21416
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
21417
0
      op &= UINT64_C(7);
21418
0
      Value |= op;
21419
0
      break;
21420
0
    }
21421
0
    case AArch64::ADD_VG2_2ZZ_B:
21422
0
    case AArch64::ADD_VG2_2ZZ_D:
21423
0
    case AArch64::ADD_VG2_2ZZ_H:
21424
0
    case AArch64::ADD_VG2_2ZZ_S:
21425
0
    case AArch64::BFMAXNM_VG2_2ZZ_H:
21426
0
    case AArch64::BFMAX_VG2_2ZZ_H:
21427
0
    case AArch64::BFMINNM_VG2_2ZZ_H:
21428
0
    case AArch64::BFMIN_VG2_2ZZ_H:
21429
0
    case AArch64::FMAXNM_VG2_2ZZ_D:
21430
0
    case AArch64::FMAXNM_VG2_2ZZ_H:
21431
0
    case AArch64::FMAXNM_VG2_2ZZ_S:
21432
0
    case AArch64::FMAX_VG2_2ZZ_D:
21433
0
    case AArch64::FMAX_VG2_2ZZ_H:
21434
0
    case AArch64::FMAX_VG2_2ZZ_S:
21435
0
    case AArch64::FMINNM_VG2_2ZZ_D:
21436
0
    case AArch64::FMINNM_VG2_2ZZ_H:
21437
0
    case AArch64::FMINNM_VG2_2ZZ_S:
21438
0
    case AArch64::FMIN_VG2_2ZZ_D:
21439
0
    case AArch64::FMIN_VG2_2ZZ_H:
21440
0
    case AArch64::FMIN_VG2_2ZZ_S:
21441
0
    case AArch64::FSCALE_2ZZ_D:
21442
0
    case AArch64::FSCALE_2ZZ_H:
21443
0
    case AArch64::FSCALE_2ZZ_S:
21444
0
    case AArch64::SMAX_VG2_2ZZ_B:
21445
0
    case AArch64::SMAX_VG2_2ZZ_D:
21446
0
    case AArch64::SMAX_VG2_2ZZ_H:
21447
0
    case AArch64::SMAX_VG2_2ZZ_S:
21448
0
    case AArch64::SMIN_VG2_2ZZ_B:
21449
0
    case AArch64::SMIN_VG2_2ZZ_D:
21450
0
    case AArch64::SMIN_VG2_2ZZ_H:
21451
0
    case AArch64::SMIN_VG2_2ZZ_S:
21452
0
    case AArch64::SQDMULH_VG2_2ZZ_B:
21453
0
    case AArch64::SQDMULH_VG2_2ZZ_D:
21454
0
    case AArch64::SQDMULH_VG2_2ZZ_H:
21455
0
    case AArch64::SQDMULH_VG2_2ZZ_S:
21456
0
    case AArch64::SRSHL_VG2_2ZZ_B:
21457
0
    case AArch64::SRSHL_VG2_2ZZ_D:
21458
0
    case AArch64::SRSHL_VG2_2ZZ_H:
21459
0
    case AArch64::SRSHL_VG2_2ZZ_S:
21460
0
    case AArch64::UMAX_VG2_2ZZ_B:
21461
0
    case AArch64::UMAX_VG2_2ZZ_D:
21462
0
    case AArch64::UMAX_VG2_2ZZ_H:
21463
0
    case AArch64::UMAX_VG2_2ZZ_S:
21464
0
    case AArch64::UMIN_VG2_2ZZ_B:
21465
0
    case AArch64::UMIN_VG2_2ZZ_D:
21466
0
    case AArch64::UMIN_VG2_2ZZ_H:
21467
0
    case AArch64::UMIN_VG2_2ZZ_S:
21468
0
    case AArch64::URSHL_VG2_2ZZ_B:
21469
0
    case AArch64::URSHL_VG2_2ZZ_D:
21470
0
    case AArch64::URSHL_VG2_2ZZ_H:
21471
0
    case AArch64::URSHL_VG2_2ZZ_S: {
21472
      // op: Zm
21473
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
21474
0
      op &= UINT64_C(15);
21475
0
      op <<= 16;
21476
0
      Value |= op;
21477
      // op: Zdn
21478
0
      op = EncodeRegAsMultipleOf<2>(MI, 0, Fixups, STI);
21479
0
      op &= UINT64_C(15);
21480
0
      op <<= 1;
21481
0
      Value |= op;
21482
0
      break;
21483
0
    }
21484
0
    case AArch64::ADD_VG4_4ZZ_B:
21485
0
    case AArch64::ADD_VG4_4ZZ_D:
21486
0
    case AArch64::ADD_VG4_4ZZ_H:
21487
0
    case AArch64::ADD_VG4_4ZZ_S:
21488
0
    case AArch64::BFMAXNM_VG4_4ZZ_H:
21489
0
    case AArch64::BFMAX_VG4_4ZZ_H:
21490
0
    case AArch64::BFMINNM_VG4_4ZZ_H:
21491
0
    case AArch64::BFMIN_VG4_4ZZ_H:
21492
0
    case AArch64::FMAXNM_VG4_4ZZ_D:
21493
0
    case AArch64::FMAXNM_VG4_4ZZ_H:
21494
0
    case AArch64::FMAXNM_VG4_4ZZ_S:
21495
0
    case AArch64::FMAX_VG4_4ZZ_D:
21496
0
    case AArch64::FMAX_VG4_4ZZ_H:
21497
0
    case AArch64::FMAX_VG4_4ZZ_S:
21498
0
    case AArch64::FMINNM_VG4_4ZZ_D:
21499
0
    case AArch64::FMINNM_VG4_4ZZ_H:
21500
0
    case AArch64::FMINNM_VG4_4ZZ_S:
21501
0
    case AArch64::FMIN_VG4_4ZZ_D:
21502
0
    case AArch64::FMIN_VG4_4ZZ_H:
21503
0
    case AArch64::FMIN_VG4_4ZZ_S:
21504
0
    case AArch64::FSCALE_4ZZ_D:
21505
0
    case AArch64::FSCALE_4ZZ_H:
21506
0
    case AArch64::FSCALE_4ZZ_S:
21507
0
    case AArch64::SMAX_VG4_4ZZ_B:
21508
0
    case AArch64::SMAX_VG4_4ZZ_D:
21509
0
    case AArch64::SMAX_VG4_4ZZ_H:
21510
0
    case AArch64::SMAX_VG4_4ZZ_S:
21511
0
    case AArch64::SMIN_VG4_4ZZ_B:
21512
0
    case AArch64::SMIN_VG4_4ZZ_D:
21513
0
    case AArch64::SMIN_VG4_4ZZ_H:
21514
0
    case AArch64::SMIN_VG4_4ZZ_S:
21515
0
    case AArch64::SQDMULH_VG4_4ZZ_B:
21516
0
    case AArch64::SQDMULH_VG4_4ZZ_D:
21517
0
    case AArch64::SQDMULH_VG4_4ZZ_H:
21518
0
    case AArch64::SQDMULH_VG4_4ZZ_S:
21519
0
    case AArch64::SRSHL_VG4_4ZZ_B:
21520
0
    case AArch64::SRSHL_VG4_4ZZ_D:
21521
0
    case AArch64::SRSHL_VG4_4ZZ_H:
21522
0
    case AArch64::SRSHL_VG4_4ZZ_S:
21523
0
    case AArch64::UMAX_VG4_4ZZ_B:
21524
0
    case AArch64::UMAX_VG4_4ZZ_D:
21525
0
    case AArch64::UMAX_VG4_4ZZ_H:
21526
0
    case AArch64::UMAX_VG4_4ZZ_S:
21527
0
    case AArch64::UMIN_VG4_4ZZ_B:
21528
0
    case AArch64::UMIN_VG4_4ZZ_D:
21529
0
    case AArch64::UMIN_VG4_4ZZ_H:
21530
0
    case AArch64::UMIN_VG4_4ZZ_S:
21531
0
    case AArch64::URSHL_VG4_4ZZ_B:
21532
0
    case AArch64::URSHL_VG4_4ZZ_D:
21533
0
    case AArch64::URSHL_VG4_4ZZ_H:
21534
0
    case AArch64::URSHL_VG4_4ZZ_S: {
21535
      // op: Zm
21536
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
21537
0
      op &= UINT64_C(15);
21538
0
      op <<= 16;
21539
0
      Value |= op;
21540
      // op: Zdn
21541
0
      op = EncodeRegAsMultipleOf<4>(MI, 0, Fixups, STI);
21542
0
      op &= UINT64_C(7);
21543
0
      op <<= 2;
21544
0
      Value |= op;
21545
0
      break;
21546
0
    }
21547
0
    case AArch64::BFMMLA_ZZZ: {
21548
      // op: Zm
21549
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
21550
0
      op &= UINT64_C(31);
21551
0
      op <<= 16;
21552
0
      Value |= op;
21553
      // op: Zda
21554
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
21555
0
      op &= UINT64_C(31);
21556
0
      Value |= op;
21557
      // op: Zn
21558
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
21559
0
      op &= UINT64_C(31);
21560
0
      op <<= 5;
21561
0
      Value |= op;
21562
0
      break;
21563
0
    }
21564
0
    case AArch64::BFCLAMP_VG2_2ZZZ_H:
21565
0
    case AArch64::FCLAMP_VG2_2Z2Z_D:
21566
0
    case AArch64::FCLAMP_VG2_2Z2Z_H:
21567
0
    case AArch64::FCLAMP_VG2_2Z2Z_S:
21568
0
    case AArch64::SCLAMP_VG2_2Z2Z_B:
21569
0
    case AArch64::SCLAMP_VG2_2Z2Z_D:
21570
0
    case AArch64::SCLAMP_VG2_2Z2Z_H:
21571
0
    case AArch64::SCLAMP_VG2_2Z2Z_S:
21572
0
    case AArch64::UCLAMP_VG2_2Z2Z_B:
21573
0
    case AArch64::UCLAMP_VG2_2Z2Z_D:
21574
0
    case AArch64::UCLAMP_VG2_2Z2Z_H:
21575
0
    case AArch64::UCLAMP_VG2_2Z2Z_S: {
21576
      // op: Zm
21577
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
21578
0
      op &= UINT64_C(31);
21579
0
      op <<= 16;
21580
0
      Value |= op;
21581
      // op: Zn
21582
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
21583
0
      op &= UINT64_C(31);
21584
0
      op <<= 5;
21585
0
      Value |= op;
21586
      // op: Zd
21587
0
      op = EncodeRegAsMultipleOf<2>(MI, 0, Fixups, STI);
21588
0
      op &= UINT64_C(15);
21589
0
      op <<= 1;
21590
0
      Value |= op;
21591
0
      break;
21592
0
    }
21593
0
    case AArch64::BFCLAMP_VG4_4ZZZ_H:
21594
0
    case AArch64::FCLAMP_VG4_4Z4Z_D:
21595
0
    case AArch64::FCLAMP_VG4_4Z4Z_H:
21596
0
    case AArch64::FCLAMP_VG4_4Z4Z_S:
21597
0
    case AArch64::SCLAMP_VG4_4Z4Z_B:
21598
0
    case AArch64::SCLAMP_VG4_4Z4Z_D:
21599
0
    case AArch64::SCLAMP_VG4_4Z4Z_H:
21600
0
    case AArch64::SCLAMP_VG4_4Z4Z_S:
21601
0
    case AArch64::UCLAMP_VG4_4Z4Z_B:
21602
0
    case AArch64::UCLAMP_VG4_4Z4Z_D:
21603
0
    case AArch64::UCLAMP_VG4_4Z4Z_H:
21604
0
    case AArch64::UCLAMP_VG4_4Z4Z_S: {
21605
      // op: Zm
21606
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
21607
0
      op &= UINT64_C(31);
21608
0
      op <<= 16;
21609
0
      Value |= op;
21610
      // op: Zn
21611
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
21612
0
      op &= UINT64_C(31);
21613
0
      op <<= 5;
21614
0
      Value |= op;
21615
      // op: Zd
21616
0
      op = EncodeRegAsMultipleOf<4>(MI, 0, Fixups, STI);
21617
0
      op &= UINT64_C(7);
21618
0
      op <<= 2;
21619
0
      Value |= op;
21620
0
      break;
21621
0
    }
21622
0
    case AArch64::BFCLAMP_ZZZ:
21623
0
    case AArch64::FCLAMP_ZZZ_D:
21624
0
    case AArch64::FCLAMP_ZZZ_H:
21625
0
    case AArch64::FCLAMP_ZZZ_S:
21626
0
    case AArch64::SCLAMP_ZZZ_B:
21627
0
    case AArch64::SCLAMP_ZZZ_D:
21628
0
    case AArch64::SCLAMP_ZZZ_H:
21629
0
    case AArch64::SCLAMP_ZZZ_S:
21630
0
    case AArch64::UCLAMP_ZZZ_B:
21631
0
    case AArch64::UCLAMP_ZZZ_D:
21632
0
    case AArch64::UCLAMP_ZZZ_H:
21633
0
    case AArch64::UCLAMP_ZZZ_S: {
21634
      // op: Zm
21635
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
21636
0
      op &= UINT64_C(31);
21637
0
      op <<= 16;
21638
0
      Value |= op;
21639
      // op: Zn
21640
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
21641
0
      op &= UINT64_C(31);
21642
0
      op <<= 5;
21643
0
      Value |= op;
21644
      // op: Zd
21645
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
21646
0
      op &= UINT64_C(31);
21647
0
      Value |= op;
21648
0
      break;
21649
0
    }
21650
0
    case AArch64::FVDOTB_VG4_M2ZZI_BtoS:
21651
0
    case AArch64::FVDOTT_VG4_M2ZZI_BtoS: {
21652
      // op: Zm
21653
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
21654
0
      op &= UINT64_C(15);
21655
0
      op <<= 16;
21656
0
      Value |= op;
21657
      // op: Rv
21658
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
21659
0
      op &= UINT64_C(3);
21660
0
      op <<= 13;
21661
0
      Value |= op;
21662
      // op: Zn
21663
0
      op = EncodeRegAsMultipleOf<2>(MI, 4, Fixups, STI);
21664
0
      op &= UINT64_C(15);
21665
0
      op <<= 6;
21666
0
      Value |= op;
21667
      // op: imm3
21668
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
21669
0
      op &= UINT64_C(7);
21670
0
      Value |= op;
21671
      // op: i
21672
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
21673
0
      Value |= (op & UINT64_C(2)) << 9;
21674
0
      Value |= (op & UINT64_C(1)) << 3;
21675
0
      break;
21676
0
    }
21677
0
    case AArch64::BFMLA_VG2_M2ZZI:
21678
0
    case AArch64::BFMLS_VG2_M2ZZI:
21679
0
    case AArch64::FDOT_VG2_M2ZZI_BtoH:
21680
0
    case AArch64::FMLA_VG2_M2ZZI_H:
21681
0
    case AArch64::FMLS_VG2_M2ZZI_H:
21682
0
    case AArch64::FVDOT_VG2_M2ZZI_BtoH: {
21683
      // op: Zm
21684
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
21685
0
      op &= UINT64_C(15);
21686
0
      op <<= 16;
21687
0
      Value |= op;
21688
      // op: Rv
21689
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
21690
0
      op &= UINT64_C(3);
21691
0
      op <<= 13;
21692
0
      Value |= op;
21693
      // op: Zn
21694
0
      op = EncodeRegAsMultipleOf<2>(MI, 4, Fixups, STI);
21695
0
      op &= UINT64_C(15);
21696
0
      op <<= 6;
21697
0
      Value |= op;
21698
      // op: imm3
21699
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
21700
0
      op &= UINT64_C(7);
21701
0
      Value |= op;
21702
      // op: i
21703
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
21704
0
      Value |= (op & UINT64_C(6)) << 9;
21705
0
      Value |= (op & UINT64_C(1)) << 3;
21706
0
      break;
21707
0
    }
21708
0
    case AArch64::BFDOT_VG2_M2ZZI_HtoS:
21709
0
    case AArch64::BFVDOT_VG2_M2ZZI_HtoS:
21710
0
    case AArch64::FDOT_VG2_M2ZZI_BtoS:
21711
0
    case AArch64::FDOT_VG2_M2ZZI_HtoS:
21712
0
    case AArch64::FMLA_VG2_M2ZZI_S:
21713
0
    case AArch64::FMLS_VG2_M2ZZI_S:
21714
0
    case AArch64::FVDOT_VG2_M2ZZI_HtoS:
21715
0
    case AArch64::SDOT_VG2_M2ZZI_BToS:
21716
0
    case AArch64::SDOT_VG2_M2ZZI_HToS:
21717
0
    case AArch64::SUDOT_VG2_M2ZZI_BToS:
21718
0
    case AArch64::SVDOT_VG2_M2ZZI_HtoS:
21719
0
    case AArch64::UDOT_VG2_M2ZZI_BToS:
21720
0
    case AArch64::UDOT_VG2_M2ZZI_HToS:
21721
0
    case AArch64::USDOT_VG2_M2ZZI_BToS:
21722
0
    case AArch64::UVDOT_VG2_M2ZZI_HtoS: {
21723
      // op: Zm
21724
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
21725
0
      op &= UINT64_C(15);
21726
0
      op <<= 16;
21727
0
      Value |= op;
21728
      // op: Rv
21729
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
21730
0
      op &= UINT64_C(3);
21731
0
      op <<= 13;
21732
0
      Value |= op;
21733
      // op: Zn
21734
0
      op = EncodeRegAsMultipleOf<2>(MI, 4, Fixups, STI);
21735
0
      op &= UINT64_C(15);
21736
0
      op <<= 6;
21737
0
      Value |= op;
21738
      // op: imm3
21739
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
21740
0
      op &= UINT64_C(7);
21741
0
      Value |= op;
21742
      // op: i
21743
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
21744
0
      op &= UINT64_C(3);
21745
0
      op <<= 10;
21746
0
      Value |= op;
21747
0
      break;
21748
0
    }
21749
0
    case AArch64::BFMLA_VG4_M4ZZI:
21750
0
    case AArch64::BFMLS_VG4_M4ZZI:
21751
0
    case AArch64::FDOT_VG4_M4ZZI_BtoH:
21752
0
    case AArch64::FMLA_VG4_M4ZZI_H:
21753
0
    case AArch64::FMLS_VG4_M4ZZI_H: {
21754
      // op: Zm
21755
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
21756
0
      op &= UINT64_C(15);
21757
0
      op <<= 16;
21758
0
      Value |= op;
21759
      // op: Rv
21760
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
21761
0
      op &= UINT64_C(3);
21762
0
      op <<= 13;
21763
0
      Value |= op;
21764
      // op: Zn
21765
0
      op = EncodeRegAsMultipleOf<4>(MI, 4, Fixups, STI);
21766
0
      op &= UINT64_C(7);
21767
0
      op <<= 7;
21768
0
      Value |= op;
21769
      // op: imm3
21770
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
21771
0
      op &= UINT64_C(7);
21772
0
      Value |= op;
21773
      // op: i
21774
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
21775
0
      Value |= (op & UINT64_C(6)) << 9;
21776
0
      Value |= (op & UINT64_C(1)) << 3;
21777
0
      break;
21778
0
    }
21779
0
    case AArch64::BFDOT_VG4_M4ZZI_HtoS:
21780
0
    case AArch64::FDOT_VG4_M4ZZI_BtoS:
21781
0
    case AArch64::FDOT_VG4_M4ZZI_HtoS:
21782
0
    case AArch64::FMLA_VG4_M4ZZI_S:
21783
0
    case AArch64::FMLS_VG4_M4ZZI_S:
21784
0
    case AArch64::SDOT_VG4_M4ZZI_BToS:
21785
0
    case AArch64::SDOT_VG4_M4ZZI_HToS:
21786
0
    case AArch64::SUDOT_VG4_M4ZZI_BToS:
21787
0
    case AArch64::SUVDOT_VG4_M4ZZI_BToS:
21788
0
    case AArch64::SVDOT_VG4_M4ZZI_BtoS:
21789
0
    case AArch64::UDOT_VG4_M4ZZI_BtoS:
21790
0
    case AArch64::UDOT_VG4_M4ZZI_HToS:
21791
0
    case AArch64::USDOT_VG4_M4ZZI_BToS:
21792
0
    case AArch64::USVDOT_VG4_M4ZZI_BToS:
21793
0
    case AArch64::UVDOT_VG4_M4ZZI_BtoS: {
21794
      // op: Zm
21795
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
21796
0
      op &= UINT64_C(15);
21797
0
      op <<= 16;
21798
0
      Value |= op;
21799
      // op: Rv
21800
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
21801
0
      op &= UINT64_C(3);
21802
0
      op <<= 13;
21803
0
      Value |= op;
21804
      // op: Zn
21805
0
      op = EncodeRegAsMultipleOf<4>(MI, 4, Fixups, STI);
21806
0
      op &= UINT64_C(7);
21807
0
      op <<= 7;
21808
0
      Value |= op;
21809
      // op: imm3
21810
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
21811
0
      op &= UINT64_C(7);
21812
0
      Value |= op;
21813
      // op: i
21814
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
21815
0
      op &= UINT64_C(3);
21816
0
      op <<= 10;
21817
0
      Value |= op;
21818
0
      break;
21819
0
    }
21820
0
    case AArch64::FMLALL_VG2_M2ZZ_BtoS:
21821
0
    case AArch64::FMLALL_VG4_M4ZZ_BtoS:
21822
0
    case AArch64::SMLALL_VG2_M2ZZ_BtoS:
21823
0
    case AArch64::SMLALL_VG2_M2ZZ_HtoD:
21824
0
    case AArch64::SMLALL_VG4_M4ZZ_BtoS:
21825
0
    case AArch64::SMLALL_VG4_M4ZZ_HtoD:
21826
0
    case AArch64::SMLSLL_VG2_M2ZZ_BtoS:
21827
0
    case AArch64::SMLSLL_VG2_M2ZZ_HtoD:
21828
0
    case AArch64::SMLSLL_VG4_M4ZZ_BtoS:
21829
0
    case AArch64::SMLSLL_VG4_M4ZZ_HtoD:
21830
0
    case AArch64::SUMLALL_VG2_M2ZZ_BtoS:
21831
0
    case AArch64::SUMLALL_VG4_M4ZZ_BtoS:
21832
0
    case AArch64::UMLALL_VG2_M2ZZ_BtoS:
21833
0
    case AArch64::UMLALL_VG2_M2ZZ_HtoD:
21834
0
    case AArch64::UMLALL_VG4_M4ZZ_BtoS:
21835
0
    case AArch64::UMLALL_VG4_M4ZZ_HtoD:
21836
0
    case AArch64::UMLSLL_VG2_M2ZZ_BtoS:
21837
0
    case AArch64::UMLSLL_VG2_M2ZZ_HtoD:
21838
0
    case AArch64::UMLSLL_VG4_M4ZZ_BtoS:
21839
0
    case AArch64::UMLSLL_VG4_M4ZZ_HtoD:
21840
0
    case AArch64::USMLALL_VG2_M2ZZ_BtoS:
21841
0
    case AArch64::USMLALL_VG4_M4ZZ_BtoS: {
21842
      // op: Zm
21843
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
21844
0
      op &= UINT64_C(15);
21845
0
      op <<= 16;
21846
0
      Value |= op;
21847
      // op: Rv
21848
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
21849
0
      op &= UINT64_C(3);
21850
0
      op <<= 13;
21851
0
      Value |= op;
21852
      // op: Zn
21853
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
21854
0
      op &= UINT64_C(31);
21855
0
      op <<= 5;
21856
0
      Value |= op;
21857
      // op: imm
21858
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
21859
0
      op &= UINT64_C(1);
21860
0
      Value |= op;
21861
0
      break;
21862
0
    }
21863
0
    case AArch64::FMLALL_MZZ_BtoS:
21864
0
    case AArch64::SMLALL_MZZ_BtoS:
21865
0
    case AArch64::SMLALL_MZZ_HtoD:
21866
0
    case AArch64::SMLSLL_MZZ_BtoS:
21867
0
    case AArch64::SMLSLL_MZZ_HtoD:
21868
0
    case AArch64::UMLALL_MZZ_BtoS:
21869
0
    case AArch64::UMLALL_MZZ_HtoD:
21870
0
    case AArch64::UMLSLL_MZZ_BtoS:
21871
0
    case AArch64::UMLSLL_MZZ_HtoD:
21872
0
    case AArch64::USMLALL_MZZ_BtoS: {
21873
      // op: Zm
21874
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
21875
0
      op &= UINT64_C(15);
21876
0
      op <<= 16;
21877
0
      Value |= op;
21878
      // op: Rv
21879
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
21880
0
      op &= UINT64_C(3);
21881
0
      op <<= 13;
21882
0
      Value |= op;
21883
      // op: Zn
21884
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
21885
0
      op &= UINT64_C(31);
21886
0
      op <<= 5;
21887
0
      Value |= op;
21888
      // op: imm
21889
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
21890
0
      op &= UINT64_C(3);
21891
0
      Value |= op;
21892
0
      break;
21893
0
    }
21894
0
    case AArch64::FMLALL_VG2_M2ZZI_BtoS:
21895
0
    case AArch64::SMLALL_VG2_M2ZZI_BtoS:
21896
0
    case AArch64::SMLSLL_VG2_M2ZZI_BtoS:
21897
0
    case AArch64::SUMLALL_VG2_M2ZZI_BtoS:
21898
0
    case AArch64::UMLALL_VG2_M2ZZI_BtoS:
21899
0
    case AArch64::UMLSLL_VG2_M2ZZI_BtoS:
21900
0
    case AArch64::USMLALL_VG2_M2ZZI_BtoS: {
21901
      // op: Zm
21902
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
21903
0
      op &= UINT64_C(15);
21904
0
      op <<= 16;
21905
0
      Value |= op;
21906
      // op: Rv
21907
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
21908
0
      op &= UINT64_C(3);
21909
0
      op <<= 13;
21910
0
      Value |= op;
21911
      // op: i
21912
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
21913
0
      Value |= (op & UINT64_C(12)) << 8;
21914
0
      Value |= (op & UINT64_C(3)) << 1;
21915
      // op: imm
21916
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
21917
0
      op &= UINT64_C(1);
21918
0
      Value |= op;
21919
      // op: Zn
21920
0
      op = EncodeRegAsMultipleOf<2>(MI, 4, Fixups, STI);
21921
0
      op &= UINT64_C(15);
21922
0
      op <<= 6;
21923
0
      Value |= op;
21924
0
      break;
21925
0
    }
21926
0
    case AArch64::FMLALL_VG4_M4ZZI_BtoS:
21927
0
    case AArch64::SMLALL_VG4_M4ZZI_BtoS:
21928
0
    case AArch64::SMLSLL_VG4_M4ZZI_BtoS:
21929
0
    case AArch64::SUMLALL_VG4_M4ZZI_BtoS:
21930
0
    case AArch64::UMLALL_VG4_M4ZZI_BtoS:
21931
0
    case AArch64::UMLSLL_VG4_M4ZZI_BtoS:
21932
0
    case AArch64::USMLALL_VG4_M4ZZI_BtoS: {
21933
      // op: Zm
21934
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
21935
0
      op &= UINT64_C(15);
21936
0
      op <<= 16;
21937
0
      Value |= op;
21938
      // op: Rv
21939
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
21940
0
      op &= UINT64_C(3);
21941
0
      op <<= 13;
21942
0
      Value |= op;
21943
      // op: i
21944
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
21945
0
      Value |= (op & UINT64_C(12)) << 8;
21946
0
      Value |= (op & UINT64_C(3)) << 1;
21947
      // op: imm
21948
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
21949
0
      op &= UINT64_C(1);
21950
0
      Value |= op;
21951
      // op: Zn
21952
0
      op = EncodeRegAsMultipleOf<4>(MI, 4, Fixups, STI);
21953
0
      op &= UINT64_C(7);
21954
0
      op <<= 7;
21955
0
      Value |= op;
21956
0
      break;
21957
0
    }
21958
0
    case AArch64::FMLAL_VG2_M2ZZI_BtoH: {
21959
      // op: Zm
21960
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
21961
0
      op &= UINT64_C(15);
21962
0
      op <<= 16;
21963
0
      Value |= op;
21964
      // op: Rv
21965
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
21966
0
      op &= UINT64_C(3);
21967
0
      op <<= 13;
21968
0
      Value |= op;
21969
      // op: i
21970
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
21971
0
      Value |= (op & UINT64_C(12)) << 8;
21972
0
      Value |= (op & UINT64_C(3)) << 2;
21973
      // op: imm2
21974
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
21975
0
      op &= UINT64_C(3);
21976
0
      Value |= op;
21977
      // op: Zn
21978
0
      op = EncodeRegAsMultipleOf<2>(MI, 4, Fixups, STI);
21979
0
      op &= UINT64_C(15);
21980
0
      op <<= 6;
21981
0
      Value |= op;
21982
0
      break;
21983
0
    }
21984
0
    case AArch64::FMLAL_VG4_M4ZZI_BtoH: {
21985
      // op: Zm
21986
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
21987
0
      op &= UINT64_C(15);
21988
0
      op <<= 16;
21989
0
      Value |= op;
21990
      // op: Rv
21991
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
21992
0
      op &= UINT64_C(3);
21993
0
      op <<= 13;
21994
0
      Value |= op;
21995
      // op: i
21996
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
21997
0
      Value |= (op & UINT64_C(12)) << 8;
21998
0
      Value |= (op & UINT64_C(3)) << 2;
21999
      // op: imm2
22000
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22001
0
      op &= UINT64_C(3);
22002
0
      Value |= op;
22003
      // op: Zn
22004
0
      op = EncodeRegAsMultipleOf<4>(MI, 4, Fixups, STI);
22005
0
      op &= UINT64_C(7);
22006
0
      op <<= 7;
22007
0
      Value |= op;
22008
0
      break;
22009
0
    }
22010
0
    case AArch64::SMLALL_MZZI_HtoD:
22011
0
    case AArch64::SMLSLL_MZZI_HtoD:
22012
0
    case AArch64::UMLALL_MZZI_HtoD:
22013
0
    case AArch64::UMLSLL_MZZI_HtoD: {
22014
      // op: Zm
22015
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
22016
0
      op &= UINT64_C(15);
22017
0
      op <<= 16;
22018
0
      Value |= op;
22019
      // op: Rv
22020
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
22021
0
      op &= UINT64_C(3);
22022
0
      op <<= 13;
22023
0
      Value |= op;
22024
      // op: i
22025
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
22026
0
      Value |= (op & UINT64_C(4)) << 13;
22027
0
      Value |= (op & UINT64_C(3)) << 10;
22028
      // op: Zn
22029
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
22030
0
      op &= UINT64_C(31);
22031
0
      op <<= 5;
22032
0
      Value |= op;
22033
      // op: imm2
22034
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22035
0
      op &= UINT64_C(3);
22036
0
      Value |= op;
22037
0
      break;
22038
0
    }
22039
0
    case AArch64::SMLALL_VG2_M2ZZI_HtoD:
22040
0
    case AArch64::SMLSLL_VG2_M2ZZI_HtoD:
22041
0
    case AArch64::UMLALL_VG2_M2ZZI_HtoD:
22042
0
    case AArch64::UMLSLL_VG2_M2ZZI_HtoD: {
22043
      // op: Zm
22044
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
22045
0
      op &= UINT64_C(15);
22046
0
      op <<= 16;
22047
0
      Value |= op;
22048
      // op: Rv
22049
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
22050
0
      op &= UINT64_C(3);
22051
0
      op <<= 13;
22052
0
      Value |= op;
22053
      // op: i
22054
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
22055
0
      Value |= (op & UINT64_C(4)) << 8;
22056
0
      Value |= (op & UINT64_C(3)) << 1;
22057
      // op: imm
22058
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22059
0
      op &= UINT64_C(1);
22060
0
      Value |= op;
22061
      // op: Zn
22062
0
      op = EncodeRegAsMultipleOf<2>(MI, 4, Fixups, STI);
22063
0
      op &= UINT64_C(15);
22064
0
      op <<= 6;
22065
0
      Value |= op;
22066
0
      break;
22067
0
    }
22068
0
    case AArch64::SMLALL_VG4_M4ZZI_HtoD:
22069
0
    case AArch64::SMLSLL_VG4_M4ZZI_HtoD:
22070
0
    case AArch64::UMLALL_VG4_M4ZZI_HtoD:
22071
0
    case AArch64::UMLSLL_VG4_M4ZZI_HtoD: {
22072
      // op: Zm
22073
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
22074
0
      op &= UINT64_C(15);
22075
0
      op <<= 16;
22076
0
      Value |= op;
22077
      // op: Rv
22078
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
22079
0
      op &= UINT64_C(3);
22080
0
      op <<= 13;
22081
0
      Value |= op;
22082
      // op: i
22083
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
22084
0
      Value |= (op & UINT64_C(4)) << 8;
22085
0
      Value |= (op & UINT64_C(3)) << 1;
22086
      // op: imm
22087
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22088
0
      op &= UINT64_C(1);
22089
0
      Value |= op;
22090
      // op: Zn
22091
0
      op = EncodeRegAsMultipleOf<4>(MI, 4, Fixups, STI);
22092
0
      op &= UINT64_C(7);
22093
0
      op <<= 7;
22094
0
      Value |= op;
22095
0
      break;
22096
0
    }
22097
0
    case AArch64::FMLAL_MZZI_BtoH: {
22098
      // op: Zm
22099
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
22100
0
      op &= UINT64_C(15);
22101
0
      op <<= 16;
22102
0
      Value |= op;
22103
      // op: Rv
22104
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
22105
0
      op &= UINT64_C(3);
22106
0
      op <<= 13;
22107
0
      Value |= op;
22108
      // op: i
22109
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
22110
0
      Value |= (op & UINT64_C(8)) << 12;
22111
0
      Value |= (op & UINT64_C(6)) << 9;
22112
0
      Value |= (op & UINT64_C(1)) << 3;
22113
      // op: Zn
22114
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
22115
0
      op &= UINT64_C(31);
22116
0
      op <<= 5;
22117
0
      Value |= op;
22118
      // op: imm3
22119
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22120
0
      op &= UINT64_C(7);
22121
0
      Value |= op;
22122
0
      break;
22123
0
    }
22124
0
    case AArch64::FMLALL_MZZI_BtoS:
22125
0
    case AArch64::SMLALL_MZZI_BtoS:
22126
0
    case AArch64::SMLSLL_MZZI_BtoS:
22127
0
    case AArch64::SUMLALL_MZZI_BtoS:
22128
0
    case AArch64::UMLALL_MZZI_BtoS:
22129
0
    case AArch64::UMLSLL_MZZI_BtoS:
22130
0
    case AArch64::USMLALL_MZZI_BtoS: {
22131
      // op: Zm
22132
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
22133
0
      op &= UINT64_C(15);
22134
0
      op <<= 16;
22135
0
      Value |= op;
22136
      // op: Rv
22137
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
22138
0
      op &= UINT64_C(3);
22139
0
      op <<= 13;
22140
0
      Value |= op;
22141
      // op: i
22142
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
22143
0
      Value |= (op & UINT64_C(8)) << 12;
22144
0
      Value |= (op & UINT64_C(7)) << 10;
22145
      // op: Zn
22146
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
22147
0
      op &= UINT64_C(31);
22148
0
      op <<= 5;
22149
0
      Value |= op;
22150
      // op: imm2
22151
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22152
0
      op &= UINT64_C(3);
22153
0
      Value |= op;
22154
0
      break;
22155
0
    }
22156
0
    case AArch64::FMLA_VG2_M2ZZI_D:
22157
0
    case AArch64::FMLS_VG2_M2ZZI_D:
22158
0
    case AArch64::SDOT_VG2_M2ZZI_HtoD:
22159
0
    case AArch64::UDOT_VG2_M2ZZI_HtoD: {
22160
      // op: Zm
22161
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
22162
0
      op &= UINT64_C(15);
22163
0
      op <<= 16;
22164
0
      Value |= op;
22165
      // op: Rv
22166
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
22167
0
      op &= UINT64_C(3);
22168
0
      op <<= 13;
22169
0
      Value |= op;
22170
      // op: i1
22171
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
22172
0
      op &= UINT64_C(1);
22173
0
      op <<= 10;
22174
0
      Value |= op;
22175
      // op: Zn
22176
0
      op = EncodeRegAsMultipleOf<2>(MI, 4, Fixups, STI);
22177
0
      op &= UINT64_C(15);
22178
0
      op <<= 6;
22179
0
      Value |= op;
22180
      // op: imm3
22181
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22182
0
      op &= UINT64_C(7);
22183
0
      Value |= op;
22184
0
      break;
22185
0
    }
22186
0
    case AArch64::FMLA_VG4_M4ZZI_D:
22187
0
    case AArch64::FMLS_VG4_M4ZZI_D:
22188
0
    case AArch64::SDOT_VG4_M4ZZI_HtoD:
22189
0
    case AArch64::SVDOT_VG4_M4ZZI_HtoD:
22190
0
    case AArch64::UDOT_VG4_M4ZZI_HtoD:
22191
0
    case AArch64::UVDOT_VG4_M4ZZI_HtoD: {
22192
      // op: Zm
22193
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
22194
0
      op &= UINT64_C(15);
22195
0
      op <<= 16;
22196
0
      Value |= op;
22197
      // op: Rv
22198
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
22199
0
      op &= UINT64_C(3);
22200
0
      op <<= 13;
22201
0
      Value |= op;
22202
      // op: i1
22203
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
22204
0
      op &= UINT64_C(1);
22205
0
      op <<= 10;
22206
0
      Value |= op;
22207
      // op: Zn
22208
0
      op = EncodeRegAsMultipleOf<4>(MI, 4, Fixups, STI);
22209
0
      op &= UINT64_C(7);
22210
0
      op <<= 7;
22211
0
      Value |= op;
22212
      // op: imm3
22213
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22214
0
      op &= UINT64_C(7);
22215
0
      Value |= op;
22216
0
      break;
22217
0
    }
22218
0
    case AArch64::BFMLAL_MZZI_HtoS:
22219
0
    case AArch64::BFMLSL_MZZI_HtoS:
22220
0
    case AArch64::FMLAL_MZZI_HtoS:
22221
0
    case AArch64::FMLSL_MZZI_HtoS:
22222
0
    case AArch64::SMLAL_MZZI_HtoS:
22223
0
    case AArch64::SMLSL_MZZI_HtoS:
22224
0
    case AArch64::UMLAL_MZZI_HtoS:
22225
0
    case AArch64::UMLSL_MZZI_HtoS: {
22226
      // op: Zm
22227
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
22228
0
      op &= UINT64_C(15);
22229
0
      op <<= 16;
22230
0
      Value |= op;
22231
      // op: Rv
22232
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
22233
0
      op &= UINT64_C(3);
22234
0
      op <<= 13;
22235
0
      Value |= op;
22236
      // op: i3
22237
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
22238
0
      Value |= (op & UINT64_C(4)) << 13;
22239
0
      Value |= (op & UINT64_C(3)) << 10;
22240
      // op: Zn
22241
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
22242
0
      op &= UINT64_C(31);
22243
0
      op <<= 5;
22244
0
      Value |= op;
22245
      // op: imm
22246
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22247
0
      op &= UINT64_C(7);
22248
0
      Value |= op;
22249
0
      break;
22250
0
    }
22251
0
    case AArch64::BFMLAL_VG2_M2ZZI_HtoS:
22252
0
    case AArch64::BFMLSL_VG2_M2ZZI_HtoS:
22253
0
    case AArch64::FMLAL_VG2_M2ZZI_HtoS:
22254
0
    case AArch64::FMLSL_VG2_M2ZZI_HtoS:
22255
0
    case AArch64::SMLAL_VG2_M2ZZI_S:
22256
0
    case AArch64::SMLSL_VG2_M2ZZI_S:
22257
0
    case AArch64::UMLAL_VG2_M2ZZI_S:
22258
0
    case AArch64::UMLSL_VG2_M2ZZI_S: {
22259
      // op: Zm
22260
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
22261
0
      op &= UINT64_C(15);
22262
0
      op <<= 16;
22263
0
      Value |= op;
22264
      // op: Rv
22265
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
22266
0
      op &= UINT64_C(3);
22267
0
      op <<= 13;
22268
0
      Value |= op;
22269
      // op: i3
22270
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
22271
0
      Value |= (op & UINT64_C(6)) << 9;
22272
0
      Value |= (op & UINT64_C(1)) << 2;
22273
      // op: Zn
22274
0
      op = EncodeRegAsMultipleOf<2>(MI, 4, Fixups, STI);
22275
0
      op &= UINT64_C(15);
22276
0
      op <<= 6;
22277
0
      Value |= op;
22278
      // op: imm
22279
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22280
0
      op &= UINT64_C(3);
22281
0
      Value |= op;
22282
0
      break;
22283
0
    }
22284
0
    case AArch64::BFMLAL_VG4_M4ZZI_HtoS:
22285
0
    case AArch64::BFMLSL_VG4_M4ZZI_HtoS:
22286
0
    case AArch64::FMLAL_VG4_M4ZZI_HtoS:
22287
0
    case AArch64::FMLSL_VG4_M4ZZI_HtoS:
22288
0
    case AArch64::SMLAL_VG4_M4ZZI_HtoS:
22289
0
    case AArch64::SMLSL_VG4_M4ZZI_HtoS:
22290
0
    case AArch64::UMLAL_VG4_M4ZZI_HtoS:
22291
0
    case AArch64::UMLSL_VG4_M4ZZI_HtoS: {
22292
      // op: Zm
22293
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
22294
0
      op &= UINT64_C(15);
22295
0
      op <<= 16;
22296
0
      Value |= op;
22297
      // op: Rv
22298
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
22299
0
      op &= UINT64_C(3);
22300
0
      op <<= 13;
22301
0
      Value |= op;
22302
      // op: i3
22303
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
22304
0
      Value |= (op & UINT64_C(6)) << 9;
22305
0
      Value |= (op & UINT64_C(1)) << 2;
22306
      // op: Zn
22307
0
      op = EncodeRegAsMultipleOf<4>(MI, 4, Fixups, STI);
22308
0
      op &= UINT64_C(7);
22309
0
      op <<= 7;
22310
0
      Value |= op;
22311
      // op: imm
22312
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22313
0
      op &= UINT64_C(3);
22314
0
      Value |= op;
22315
0
      break;
22316
0
    }
22317
0
    case AArch64::ADD_VG2_M2ZZ_D:
22318
0
    case AArch64::ADD_VG2_M2ZZ_S:
22319
0
    case AArch64::ADD_VG4_M4ZZ_D:
22320
0
    case AArch64::ADD_VG4_M4ZZ_S:
22321
0
    case AArch64::BFDOT_VG2_M2ZZ_HtoS:
22322
0
    case AArch64::BFDOT_VG4_M4ZZ_HtoS:
22323
0
    case AArch64::BFMLA_VG2_M2ZZ:
22324
0
    case AArch64::BFMLA_VG4_M4ZZ:
22325
0
    case AArch64::BFMLS_VG2_M2ZZ:
22326
0
    case AArch64::BFMLS_VG4_M4ZZ:
22327
0
    case AArch64::FDOT_VG2_M2ZZ_BtoH:
22328
0
    case AArch64::FDOT_VG2_M2ZZ_BtoS:
22329
0
    case AArch64::FDOT_VG2_M2ZZ_HtoS:
22330
0
    case AArch64::FDOT_VG4_M4ZZ_BtoH:
22331
0
    case AArch64::FDOT_VG4_M4ZZ_BtoS:
22332
0
    case AArch64::FDOT_VG4_M4ZZ_HtoS:
22333
0
    case AArch64::FMLA_VG2_M2ZZ_D:
22334
0
    case AArch64::FMLA_VG2_M2ZZ_H:
22335
0
    case AArch64::FMLA_VG2_M2ZZ_S:
22336
0
    case AArch64::FMLA_VG4_M4ZZ_D:
22337
0
    case AArch64::FMLA_VG4_M4ZZ_H:
22338
0
    case AArch64::FMLA_VG4_M4ZZ_S:
22339
0
    case AArch64::FMLS_VG2_M2ZZ_D:
22340
0
    case AArch64::FMLS_VG2_M2ZZ_H:
22341
0
    case AArch64::FMLS_VG2_M2ZZ_S:
22342
0
    case AArch64::FMLS_VG4_M4ZZ_D:
22343
0
    case AArch64::FMLS_VG4_M4ZZ_H:
22344
0
    case AArch64::FMLS_VG4_M4ZZ_S:
22345
0
    case AArch64::SDOT_VG2_M2ZZ_BtoS:
22346
0
    case AArch64::SDOT_VG2_M2ZZ_HtoD:
22347
0
    case AArch64::SDOT_VG2_M2ZZ_HtoS:
22348
0
    case AArch64::SDOT_VG4_M4ZZ_BtoS:
22349
0
    case AArch64::SDOT_VG4_M4ZZ_HtoD:
22350
0
    case AArch64::SDOT_VG4_M4ZZ_HtoS:
22351
0
    case AArch64::SUB_VG2_M2ZZ_D:
22352
0
    case AArch64::SUB_VG2_M2ZZ_S:
22353
0
    case AArch64::SUB_VG4_M4ZZ_D:
22354
0
    case AArch64::SUB_VG4_M4ZZ_S:
22355
0
    case AArch64::SUDOT_VG2_M2ZZ_BToS:
22356
0
    case AArch64::SUDOT_VG4_M4ZZ_BToS:
22357
0
    case AArch64::UDOT_VG2_M2ZZ_BtoS:
22358
0
    case AArch64::UDOT_VG2_M2ZZ_HtoD:
22359
0
    case AArch64::UDOT_VG2_M2ZZ_HtoS:
22360
0
    case AArch64::UDOT_VG4_M4ZZ_BtoS:
22361
0
    case AArch64::UDOT_VG4_M4ZZ_HtoD:
22362
0
    case AArch64::UDOT_VG4_M4ZZ_HtoS:
22363
0
    case AArch64::USDOT_VG2_M2ZZ_BToS:
22364
0
    case AArch64::USDOT_VG4_M4ZZ_BToS: {
22365
      // op: Zm
22366
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
22367
0
      op &= UINT64_C(15);
22368
0
      op <<= 16;
22369
0
      Value |= op;
22370
      // op: Zn
22371
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
22372
0
      op &= UINT64_C(31);
22373
0
      op <<= 5;
22374
0
      Value |= op;
22375
      // op: Rv
22376
0
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
22377
0
      op &= UINT64_C(3);
22378
0
      op <<= 13;
22379
0
      Value |= op;
22380
      // op: imm3
22381
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22382
0
      op &= UINT64_C(7);
22383
0
      Value |= op;
22384
0
      break;
22385
0
    }
22386
0
    case AArch64::BFMOPA_MPPZZ_H:
22387
0
    case AArch64::BFMOPS_MPPZZ_H:
22388
0
    case AArch64::FMOPA_MPPZZ_BtoH:
22389
0
    case AArch64::FMOPA_MPPZZ_H:
22390
0
    case AArch64::FMOPS_MPPZZ_H: {
22391
      // op: Zm
22392
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
22393
0
      op &= UINT64_C(31);
22394
0
      op <<= 16;
22395
0
      Value |= op;
22396
      // op: Pm
22397
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22398
0
      op &= UINT64_C(7);
22399
0
      op <<= 13;
22400
0
      Value |= op;
22401
      // op: Pn
22402
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
22403
0
      op &= UINT64_C(7);
22404
0
      op <<= 10;
22405
0
      Value |= op;
22406
      // op: Zn
22407
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
22408
0
      op &= UINT64_C(31);
22409
0
      op <<= 5;
22410
0
      Value |= op;
22411
      // op: ZAda
22412
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
22413
0
      op &= UINT64_C(1);
22414
0
      Value |= op;
22415
0
      break;
22416
0
    }
22417
0
    case AArch64::BFMOPA_MPPZZ:
22418
0
    case AArch64::BFMOPS_MPPZZ:
22419
0
    case AArch64::BMOPA_MPPZZ_S:
22420
0
    case AArch64::BMOPS_MPPZZ_S:
22421
0
    case AArch64::FMOPAL_MPPZZ:
22422
0
    case AArch64::FMOPA_MPPZZ_BtoS:
22423
0
    case AArch64::FMOPA_MPPZZ_S:
22424
0
    case AArch64::FMOPSL_MPPZZ:
22425
0
    case AArch64::FMOPS_MPPZZ_S:
22426
0
    case AArch64::SMOPA_MPPZZ_HtoS:
22427
0
    case AArch64::SMOPA_MPPZZ_S:
22428
0
    case AArch64::SMOPS_MPPZZ_HtoS:
22429
0
    case AArch64::SMOPS_MPPZZ_S:
22430
0
    case AArch64::SUMOPA_MPPZZ_S:
22431
0
    case AArch64::SUMOPS_MPPZZ_S:
22432
0
    case AArch64::UMOPA_MPPZZ_HtoS:
22433
0
    case AArch64::UMOPA_MPPZZ_S:
22434
0
    case AArch64::UMOPS_MPPZZ_HtoS:
22435
0
    case AArch64::UMOPS_MPPZZ_S:
22436
0
    case AArch64::USMOPA_MPPZZ_S:
22437
0
    case AArch64::USMOPS_MPPZZ_S: {
22438
      // op: Zm
22439
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
22440
0
      op &= UINT64_C(31);
22441
0
      op <<= 16;
22442
0
      Value |= op;
22443
      // op: Pm
22444
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22445
0
      op &= UINT64_C(7);
22446
0
      op <<= 13;
22447
0
      Value |= op;
22448
      // op: Pn
22449
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
22450
0
      op &= UINT64_C(7);
22451
0
      op <<= 10;
22452
0
      Value |= op;
22453
      // op: Zn
22454
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
22455
0
      op &= UINT64_C(31);
22456
0
      op <<= 5;
22457
0
      Value |= op;
22458
      // op: ZAda
22459
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
22460
0
      op &= UINT64_C(3);
22461
0
      Value |= op;
22462
0
      break;
22463
0
    }
22464
0
    case AArch64::FMOPA_MPPZZ_D:
22465
0
    case AArch64::FMOPS_MPPZZ_D:
22466
0
    case AArch64::SMOPA_MPPZZ_D:
22467
0
    case AArch64::SMOPS_MPPZZ_D:
22468
0
    case AArch64::SUMOPA_MPPZZ_D:
22469
0
    case AArch64::SUMOPS_MPPZZ_D:
22470
0
    case AArch64::UMOPA_MPPZZ_D:
22471
0
    case AArch64::UMOPS_MPPZZ_D:
22472
0
    case AArch64::USMOPA_MPPZZ_D:
22473
0
    case AArch64::USMOPS_MPPZZ_D: {
22474
      // op: Zm
22475
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
22476
0
      op &= UINT64_C(31);
22477
0
      op <<= 16;
22478
0
      Value |= op;
22479
      // op: Pm
22480
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22481
0
      op &= UINT64_C(7);
22482
0
      op <<= 13;
22483
0
      Value |= op;
22484
      // op: Pn
22485
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
22486
0
      op &= UINT64_C(7);
22487
0
      op <<= 10;
22488
0
      Value |= op;
22489
      // op: Zn
22490
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
22491
0
      op &= UINT64_C(31);
22492
0
      op <<= 5;
22493
0
      Value |= op;
22494
      // op: ZAda
22495
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
22496
0
      op &= UINT64_C(7);
22497
0
      Value |= op;
22498
0
      break;
22499
0
    }
22500
0
    case AArch64::FCVTZS_2Z2Z_StoS:
22501
0
    case AArch64::FCVTZU_2Z2Z_StoS:
22502
0
    case AArch64::FRINTA_2Z2Z_S:
22503
0
    case AArch64::FRINTM_2Z2Z_S:
22504
0
    case AArch64::FRINTN_2Z2Z_S:
22505
0
    case AArch64::FRINTP_2Z2Z_S:
22506
0
    case AArch64::SCVTF_2Z2Z_StoS:
22507
0
    case AArch64::UCVTF_2Z2Z_StoS: {
22508
      // op: Zn
22509
0
      op = EncodeRegAsMultipleOf<2>(MI, 1, Fixups, STI);
22510
0
      op &= UINT64_C(15);
22511
0
      op <<= 6;
22512
0
      Value |= op;
22513
      // op: Zd
22514
0
      op = EncodeRegAsMultipleOf<2>(MI, 0, Fixups, STI);
22515
0
      op &= UINT64_C(15);
22516
0
      op <<= 1;
22517
0
      Value |= op;
22518
0
      break;
22519
0
    }
22520
0
    case AArch64::SUNPK_VG4_4Z2Z_D:
22521
0
    case AArch64::SUNPK_VG4_4Z2Z_H:
22522
0
    case AArch64::SUNPK_VG4_4Z2Z_S:
22523
0
    case AArch64::UUNPK_VG4_4Z2Z_D:
22524
0
    case AArch64::UUNPK_VG4_4Z2Z_H:
22525
0
    case AArch64::UUNPK_VG4_4Z2Z_S: {
22526
      // op: Zn
22527
0
      op = EncodeRegAsMultipleOf<2>(MI, 1, Fixups, STI);
22528
0
      op &= UINT64_C(15);
22529
0
      op <<= 6;
22530
0
      Value |= op;
22531
      // op: Zd
22532
0
      op = EncodeRegAsMultipleOf<4>(MI, 0, Fixups, STI);
22533
0
      op &= UINT64_C(7);
22534
0
      op <<= 2;
22535
0
      Value |= op;
22536
0
      break;
22537
0
    }
22538
0
    case AArch64::BFCVTN_Z2Z_StoH:
22539
0
    case AArch64::BFCVT_Z2Z_HtoB:
22540
0
    case AArch64::BFCVT_Z2Z_StoH:
22541
0
    case AArch64::FCVTN_Z2Z_StoH:
22542
0
    case AArch64::FCVT_Z2Z_HtoB:
22543
0
    case AArch64::FCVT_Z2Z_StoH:
22544
0
    case AArch64::SQCVTU_Z2Z_StoH:
22545
0
    case AArch64::SQCVT_Z2Z_StoH:
22546
0
    case AArch64::UQCVT_Z2Z_StoH: {
22547
      // op: Zn
22548
0
      op = EncodeRegAsMultipleOf<2>(MI, 1, Fixups, STI);
22549
0
      op &= UINT64_C(15);
22550
0
      op <<= 6;
22551
0
      Value |= op;
22552
      // op: Zd
22553
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
22554
0
      op &= UINT64_C(31);
22555
0
      Value |= op;
22556
0
      break;
22557
0
    }
22558
0
    case AArch64::LUTI4_4ZZT2Z: {
22559
      // op: Zn
22560
0
      op = EncodeRegAsMultipleOf<2>(MI, 2, Fixups, STI);
22561
0
      op &= UINT64_C(15);
22562
0
      op <<= 6;
22563
0
      Value |= op;
22564
      // op: Zd
22565
0
      op = EncodeRegAsMultipleOf<4>(MI, 0, Fixups, STI);
22566
0
      op &= UINT64_C(7);
22567
0
      op <<= 2;
22568
0
      Value |= op;
22569
0
      break;
22570
0
    }
22571
0
    case AArch64::LUTI4_S_4ZZT2Z: {
22572
      // op: Zn
22573
0
      op = EncodeRegAsMultipleOf<2>(MI, 2, Fixups, STI);
22574
0
      op &= UINT64_C(15);
22575
0
      op <<= 6;
22576
0
      Value |= op;
22577
      // op: Zd
22578
0
      op = EncodeZPR4StridedRegisterClass(MI, 0, Fixups, STI);
22579
0
      Value |= (op & UINT64_C(4)) << 2;
22580
0
      Value |= (op & UINT64_C(3));
22581
0
      break;
22582
0
    }
22583
0
    case AArch64::FCVTZS_4Z4Z_StoS:
22584
0
    case AArch64::FCVTZU_4Z4Z_StoS:
22585
0
    case AArch64::FRINTA_4Z4Z_S:
22586
0
    case AArch64::FRINTM_4Z4Z_S:
22587
0
    case AArch64::FRINTN_4Z4Z_S:
22588
0
    case AArch64::FRINTP_4Z4Z_S:
22589
0
    case AArch64::SCVTF_4Z4Z_StoS:
22590
0
    case AArch64::UCVTF_4Z4Z_StoS:
22591
0
    case AArch64::UZP_VG4_4Z4Z_B:
22592
0
    case AArch64::UZP_VG4_4Z4Z_D:
22593
0
    case AArch64::UZP_VG4_4Z4Z_H:
22594
0
    case AArch64::UZP_VG4_4Z4Z_Q:
22595
0
    case AArch64::UZP_VG4_4Z4Z_S:
22596
0
    case AArch64::ZIP_VG4_4Z4Z_B:
22597
0
    case AArch64::ZIP_VG4_4Z4Z_D:
22598
0
    case AArch64::ZIP_VG4_4Z4Z_H:
22599
0
    case AArch64::ZIP_VG4_4Z4Z_Q:
22600
0
    case AArch64::ZIP_VG4_4Z4Z_S: {
22601
      // op: Zn
22602
0
      op = EncodeRegAsMultipleOf<4>(MI, 1, Fixups, STI);
22603
0
      op &= UINT64_C(7);
22604
0
      op <<= 7;
22605
0
      Value |= op;
22606
      // op: Zd
22607
0
      op = EncodeRegAsMultipleOf<4>(MI, 0, Fixups, STI);
22608
0
      op &= UINT64_C(7);
22609
0
      op <<= 2;
22610
0
      Value |= op;
22611
0
      break;
22612
0
    }
22613
0
    case AArch64::FCVTN_Z4Z_StoB_NAME:
22614
0
    case AArch64::FCVT_Z4Z_StoB_NAME:
22615
0
    case AArch64::SQCVTN_Z4Z_DtoH:
22616
0
    case AArch64::SQCVTN_Z4Z_StoB:
22617
0
    case AArch64::SQCVTUN_Z4Z_DtoH:
22618
0
    case AArch64::SQCVTUN_Z4Z_StoB:
22619
0
    case AArch64::SQCVTU_Z4Z_DtoH:
22620
0
    case AArch64::SQCVTU_Z4Z_StoB:
22621
0
    case AArch64::SQCVT_Z4Z_DtoH:
22622
0
    case AArch64::SQCVT_Z4Z_StoB:
22623
0
    case AArch64::UQCVTN_Z4Z_DtoH:
22624
0
    case AArch64::UQCVTN_Z4Z_StoB:
22625
0
    case AArch64::UQCVT_Z4Z_DtoH:
22626
0
    case AArch64::UQCVT_Z4Z_StoB: {
22627
      // op: Zn
22628
0
      op = EncodeRegAsMultipleOf<4>(MI, 1, Fixups, STI);
22629
0
      op &= UINT64_C(7);
22630
0
      op <<= 7;
22631
0
      Value |= op;
22632
      // op: Zd
22633
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
22634
0
      op &= UINT64_C(31);
22635
0
      Value |= op;
22636
0
      break;
22637
0
    }
22638
0
    case AArch64::SQRSHRN_VG4_Z4ZI_B:
22639
0
    case AArch64::SQRSHRUN_VG4_Z4ZI_B:
22640
0
    case AArch64::SQRSHRU_VG4_Z4ZI_B:
22641
0
    case AArch64::SQRSHR_VG4_Z4ZI_B:
22642
0
    case AArch64::UQRSHRN_VG4_Z4ZI_B:
22643
0
    case AArch64::UQRSHR_VG4_Z4ZI_B: {
22644
      // op: Zn
22645
0
      op = EncodeRegAsMultipleOf<4>(MI, 1, Fixups, STI);
22646
0
      op &= UINT64_C(7);
22647
0
      op <<= 7;
22648
0
      Value |= op;
22649
      // op: Zd
22650
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
22651
0
      op &= UINT64_C(31);
22652
0
      Value |= op;
22653
      // op: imm
22654
0
      op = getVecShiftR32OpValue(MI, 2, Fixups, STI);
22655
0
      op &= UINT64_C(31);
22656
0
      op <<= 16;
22657
0
      Value |= op;
22658
0
      break;
22659
0
    }
22660
0
    case AArch64::SQRSHRN_VG4_Z4ZI_H:
22661
0
    case AArch64::SQRSHRUN_VG4_Z4ZI_H:
22662
0
    case AArch64::SQRSHRU_VG4_Z4ZI_H:
22663
0
    case AArch64::SQRSHR_VG4_Z4ZI_H:
22664
0
    case AArch64::UQRSHRN_VG4_Z4ZI_H:
22665
0
    case AArch64::UQRSHR_VG4_Z4ZI_H: {
22666
      // op: Zn
22667
0
      op = EncodeRegAsMultipleOf<4>(MI, 1, Fixups, STI);
22668
0
      op &= UINT64_C(7);
22669
0
      op <<= 7;
22670
0
      Value |= op;
22671
      // op: Zd
22672
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
22673
0
      op &= UINT64_C(31);
22674
0
      Value |= op;
22675
      // op: imm
22676
0
      op = getVecShiftR64OpValue(MI, 2, Fixups, STI);
22677
0
      Value |= (op & UINT64_C(32)) << 17;
22678
0
      Value |= (op & UINT64_C(31)) << 16;
22679
0
      break;
22680
0
    }
22681
0
    case AArch64::BF1CVTL_2ZZ_BtoH_NAME:
22682
0
    case AArch64::BF1CVT_2ZZ_BtoH_NAME:
22683
0
    case AArch64::BF2CVTL_2ZZ_BtoH_NAME:
22684
0
    case AArch64::BF2CVT_2ZZ_BtoH_NAME:
22685
0
    case AArch64::F1CVTL_2ZZ_BtoH_NAME:
22686
0
    case AArch64::F1CVT_2ZZ_BtoH_NAME:
22687
0
    case AArch64::F2CVTL_2ZZ_BtoH_NAME:
22688
0
    case AArch64::F2CVT_2ZZ_BtoH_NAME:
22689
0
    case AArch64::FCVTL_2ZZ_H_S:
22690
0
    case AArch64::FCVT_2ZZ_H_S:
22691
0
    case AArch64::SUNPK_VG2_2ZZ_D:
22692
0
    case AArch64::SUNPK_VG2_2ZZ_H:
22693
0
    case AArch64::SUNPK_VG2_2ZZ_S:
22694
0
    case AArch64::UUNPK_VG2_2ZZ_D:
22695
0
    case AArch64::UUNPK_VG2_2ZZ_H:
22696
0
    case AArch64::UUNPK_VG2_2ZZ_S: {
22697
      // op: Zn
22698
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
22699
0
      op &= UINT64_C(31);
22700
0
      op <<= 5;
22701
0
      Value |= op;
22702
      // op: Zd
22703
0
      op = EncodeRegAsMultipleOf<2>(MI, 0, Fixups, STI);
22704
0
      op &= UINT64_C(15);
22705
0
      op <<= 1;
22706
0
      Value |= op;
22707
0
      break;
22708
0
    }
22709
0
    case AArch64::FADDV_VPZ_D:
22710
0
    case AArch64::FADDV_VPZ_H:
22711
0
    case AArch64::FADDV_VPZ_S:
22712
0
    case AArch64::FMAXNMV_VPZ_D:
22713
0
    case AArch64::FMAXNMV_VPZ_H:
22714
0
    case AArch64::FMAXNMV_VPZ_S:
22715
0
    case AArch64::FMAXV_VPZ_D:
22716
0
    case AArch64::FMAXV_VPZ_H:
22717
0
    case AArch64::FMAXV_VPZ_S:
22718
0
    case AArch64::FMINNMV_VPZ_D:
22719
0
    case AArch64::FMINNMV_VPZ_H:
22720
0
    case AArch64::FMINNMV_VPZ_S:
22721
0
    case AArch64::FMINV_VPZ_D:
22722
0
    case AArch64::FMINV_VPZ_H:
22723
0
    case AArch64::FMINV_VPZ_S: {
22724
      // op: Zn
22725
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
22726
0
      op &= UINT64_C(31);
22727
0
      op <<= 5;
22728
0
      Value |= op;
22729
      // op: Vd
22730
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
22731
0
      op &= UINT64_C(31);
22732
0
      Value |= op;
22733
      // op: Pg
22734
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
22735
0
      op &= UINT64_C(7);
22736
0
      op <<= 10;
22737
0
      Value |= op;
22738
0
      break;
22739
0
    }
22740
0
    case AArch64::LUTI4_2ZTZI_B:
22741
0
    case AArch64::LUTI4_2ZTZI_H:
22742
0
    case AArch64::LUTI4_2ZTZI_S: {
22743
      // op: Zn
22744
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
22745
0
      op &= UINT64_C(31);
22746
0
      op <<= 5;
22747
0
      Value |= op;
22748
      // op: Zd
22749
0
      op = EncodeRegAsMultipleOf<2>(MI, 0, Fixups, STI);
22750
0
      op &= UINT64_C(15);
22751
0
      op <<= 1;
22752
0
      Value |= op;
22753
      // op: i
22754
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22755
0
      op &= UINT64_C(3);
22756
0
      op <<= 15;
22757
0
      Value |= op;
22758
0
      break;
22759
0
    }
22760
0
    case AArch64::LUTI2_2ZTZI_B:
22761
0
    case AArch64::LUTI2_2ZTZI_H:
22762
0
    case AArch64::LUTI2_2ZTZI_S: {
22763
      // op: Zn
22764
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
22765
0
      op &= UINT64_C(31);
22766
0
      op <<= 5;
22767
0
      Value |= op;
22768
      // op: Zd
22769
0
      op = EncodeRegAsMultipleOf<2>(MI, 0, Fixups, STI);
22770
0
      op &= UINT64_C(15);
22771
0
      op <<= 1;
22772
0
      Value |= op;
22773
      // op: i
22774
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22775
0
      op &= UINT64_C(7);
22776
0
      op <<= 15;
22777
0
      Value |= op;
22778
0
      break;
22779
0
    }
22780
0
    case AArch64::LUTI4_4ZTZI_H:
22781
0
    case AArch64::LUTI4_4ZTZI_S: {
22782
      // op: Zn
22783
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
22784
0
      op &= UINT64_C(31);
22785
0
      op <<= 5;
22786
0
      Value |= op;
22787
      // op: Zd
22788
0
      op = EncodeRegAsMultipleOf<4>(MI, 0, Fixups, STI);
22789
0
      op &= UINT64_C(7);
22790
0
      op <<= 2;
22791
0
      Value |= op;
22792
      // op: i
22793
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22794
0
      op &= UINT64_C(1);
22795
0
      op <<= 16;
22796
0
      Value |= op;
22797
0
      break;
22798
0
    }
22799
0
    case AArch64::LUTI2_4ZTZI_B:
22800
0
    case AArch64::LUTI2_4ZTZI_H:
22801
0
    case AArch64::LUTI2_4ZTZI_S: {
22802
      // op: Zn
22803
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
22804
0
      op &= UINT64_C(31);
22805
0
      op <<= 5;
22806
0
      Value |= op;
22807
      // op: Zd
22808
0
      op = EncodeRegAsMultipleOf<4>(MI, 0, Fixups, STI);
22809
0
      op &= UINT64_C(7);
22810
0
      op <<= 2;
22811
0
      Value |= op;
22812
      // op: i
22813
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22814
0
      op &= UINT64_C(3);
22815
0
      op <<= 16;
22816
0
      Value |= op;
22817
0
      break;
22818
0
    }
22819
0
    case AArch64::LUTI4_S_2ZTZI_B:
22820
0
    case AArch64::LUTI4_S_2ZTZI_H: {
22821
      // op: Zn
22822
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
22823
0
      op &= UINT64_C(31);
22824
0
      op <<= 5;
22825
0
      Value |= op;
22826
      // op: Zd
22827
0
      op = EncodeZPR2StridedRegisterClass(MI, 0, Fixups, STI);
22828
0
      Value |= (op & UINT64_C(8)) << 1;
22829
0
      Value |= (op & UINT64_C(7));
22830
      // op: i
22831
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22832
0
      op &= UINT64_C(3);
22833
0
      op <<= 15;
22834
0
      Value |= op;
22835
0
      break;
22836
0
    }
22837
0
    case AArch64::LUTI2_S_2ZTZI_B:
22838
0
    case AArch64::LUTI2_S_2ZTZI_H: {
22839
      // op: Zn
22840
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
22841
0
      op &= UINT64_C(31);
22842
0
      op <<= 5;
22843
0
      Value |= op;
22844
      // op: Zd
22845
0
      op = EncodeZPR2StridedRegisterClass(MI, 0, Fixups, STI);
22846
0
      Value |= (op & UINT64_C(8)) << 1;
22847
0
      Value |= (op & UINT64_C(7));
22848
      // op: i
22849
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22850
0
      op &= UINT64_C(7);
22851
0
      op <<= 15;
22852
0
      Value |= op;
22853
0
      break;
22854
0
    }
22855
0
    case AArch64::LUTI4_S_4ZTZI_H: {
22856
      // op: Zn
22857
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
22858
0
      op &= UINT64_C(31);
22859
0
      op <<= 5;
22860
0
      Value |= op;
22861
      // op: Zd
22862
0
      op = EncodeZPR4StridedRegisterClass(MI, 0, Fixups, STI);
22863
0
      Value |= (op & UINT64_C(4)) << 2;
22864
0
      Value |= (op & UINT64_C(3));
22865
      // op: i
22866
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22867
0
      op &= UINT64_C(1);
22868
0
      op <<= 16;
22869
0
      Value |= op;
22870
0
      break;
22871
0
    }
22872
0
    case AArch64::LUTI2_S_4ZTZI_B:
22873
0
    case AArch64::LUTI2_S_4ZTZI_H: {
22874
      // op: Zn
22875
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
22876
0
      op &= UINT64_C(31);
22877
0
      op <<= 5;
22878
0
      Value |= op;
22879
      // op: Zd
22880
0
      op = EncodeZPR4StridedRegisterClass(MI, 0, Fixups, STI);
22881
0
      Value |= (op & UINT64_C(4)) << 2;
22882
0
      Value |= (op & UINT64_C(3));
22883
      // op: i
22884
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22885
0
      op &= UINT64_C(3);
22886
0
      op <<= 16;
22887
0
      Value |= op;
22888
0
      break;
22889
0
    }
22890
0
    case AArch64::LUTI2_ZTZI_B:
22891
0
    case AArch64::LUTI2_ZTZI_H:
22892
0
    case AArch64::LUTI2_ZTZI_S: {
22893
      // op: Zn
22894
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
22895
0
      op &= UINT64_C(31);
22896
0
      op <<= 5;
22897
0
      Value |= op;
22898
      // op: Zd
22899
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
22900
0
      op &= UINT64_C(31);
22901
0
      Value |= op;
22902
      // op: i
22903
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22904
0
      op &= UINT64_C(15);
22905
0
      op <<= 14;
22906
0
      Value |= op;
22907
0
      break;
22908
0
    }
22909
0
    case AArch64::LUTI4_ZTZI_B:
22910
0
    case AArch64::LUTI4_ZTZI_H:
22911
0
    case AArch64::LUTI4_ZTZI_S: {
22912
      // op: Zn
22913
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
22914
0
      op &= UINT64_C(31);
22915
0
      op <<= 5;
22916
0
      Value |= op;
22917
      // op: Zd
22918
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
22919
0
      op &= UINT64_C(31);
22920
0
      Value |= op;
22921
      // op: i
22922
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22923
0
      op &= UINT64_C(7);
22924
0
      op <<= 14;
22925
0
      Value |= op;
22926
0
      break;
22927
0
    }
22928
0
    case AArch64::LD1B_2Z:
22929
0
    case AArch64::LD1D_2Z:
22930
0
    case AArch64::LD1H_2Z:
22931
0
    case AArch64::LD1W_2Z:
22932
0
    case AArch64::LDNT1B_2Z:
22933
0
    case AArch64::LDNT1D_2Z:
22934
0
    case AArch64::LDNT1H_2Z:
22935
0
    case AArch64::LDNT1W_2Z:
22936
0
    case AArch64::ST1B_2Z:
22937
0
    case AArch64::ST1D_2Z:
22938
0
    case AArch64::ST1H_2Z:
22939
0
    case AArch64::ST1W_2Z:
22940
0
    case AArch64::STNT1B_2Z:
22941
0
    case AArch64::STNT1D_2Z:
22942
0
    case AArch64::STNT1H_2Z:
22943
0
    case AArch64::STNT1W_2Z: {
22944
      // op: Zt
22945
0
      op = EncodeRegAsMultipleOf<2>(MI, 0, Fixups, STI);
22946
0
      op &= UINT64_C(15);
22947
0
      op <<= 1;
22948
0
      Value |= op;
22949
      // op: Rm
22950
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22951
0
      op &= UINT64_C(31);
22952
0
      op <<= 16;
22953
0
      Value |= op;
22954
      // op: Rn
22955
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
22956
0
      op &= UINT64_C(31);
22957
0
      op <<= 5;
22958
0
      Value |= op;
22959
      // op: PNg
22960
0
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
22961
0
      op &= UINT64_C(7);
22962
0
      op <<= 10;
22963
0
      Value |= op;
22964
0
      break;
22965
0
    }
22966
0
    case AArch64::LD1B_2Z_IMM:
22967
0
    case AArch64::LD1D_2Z_IMM:
22968
0
    case AArch64::LD1H_2Z_IMM:
22969
0
    case AArch64::LD1W_2Z_IMM:
22970
0
    case AArch64::LDNT1B_2Z_IMM:
22971
0
    case AArch64::LDNT1D_2Z_IMM:
22972
0
    case AArch64::LDNT1H_2Z_IMM:
22973
0
    case AArch64::LDNT1W_2Z_IMM:
22974
0
    case AArch64::ST1B_2Z_IMM:
22975
0
    case AArch64::ST1D_2Z_IMM:
22976
0
    case AArch64::ST1H_2Z_IMM:
22977
0
    case AArch64::ST1W_2Z_IMM:
22978
0
    case AArch64::STNT1B_2Z_IMM:
22979
0
    case AArch64::STNT1D_2Z_IMM:
22980
0
    case AArch64::STNT1H_2Z_IMM:
22981
0
    case AArch64::STNT1W_2Z_IMM: {
22982
      // op: Zt
22983
0
      op = EncodeRegAsMultipleOf<2>(MI, 0, Fixups, STI);
22984
0
      op &= UINT64_C(15);
22985
0
      op <<= 1;
22986
0
      Value |= op;
22987
      // op: Rn
22988
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
22989
0
      op &= UINT64_C(31);
22990
0
      op <<= 5;
22991
0
      Value |= op;
22992
      // op: PNg
22993
0
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
22994
0
      op &= UINT64_C(7);
22995
0
      op <<= 10;
22996
0
      Value |= op;
22997
      // op: imm4
22998
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
22999
0
      op &= UINT64_C(15);
23000
0
      op <<= 16;
23001
0
      Value |= op;
23002
0
      break;
23003
0
    }
23004
0
    case AArch64::LD1B_4Z:
23005
0
    case AArch64::LD1D_4Z:
23006
0
    case AArch64::LD1H_4Z:
23007
0
    case AArch64::LD1W_4Z:
23008
0
    case AArch64::LDNT1B_4Z:
23009
0
    case AArch64::LDNT1D_4Z:
23010
0
    case AArch64::LDNT1H_4Z:
23011
0
    case AArch64::LDNT1W_4Z:
23012
0
    case AArch64::ST1B_4Z:
23013
0
    case AArch64::ST1D_4Z:
23014
0
    case AArch64::ST1H_4Z:
23015
0
    case AArch64::ST1W_4Z:
23016
0
    case AArch64::STNT1B_4Z:
23017
0
    case AArch64::STNT1D_4Z:
23018
0
    case AArch64::STNT1H_4Z:
23019
0
    case AArch64::STNT1W_4Z: {
23020
      // op: Zt
23021
0
      op = EncodeRegAsMultipleOf<4>(MI, 0, Fixups, STI);
23022
0
      op &= UINT64_C(7);
23023
0
      op <<= 2;
23024
0
      Value |= op;
23025
      // op: Rm
23026
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
23027
0
      op &= UINT64_C(31);
23028
0
      op <<= 16;
23029
0
      Value |= op;
23030
      // op: Rn
23031
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
23032
0
      op &= UINT64_C(31);
23033
0
      op <<= 5;
23034
0
      Value |= op;
23035
      // op: PNg
23036
0
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
23037
0
      op &= UINT64_C(7);
23038
0
      op <<= 10;
23039
0
      Value |= op;
23040
0
      break;
23041
0
    }
23042
0
    case AArch64::LD1B_4Z_IMM:
23043
0
    case AArch64::LD1D_4Z_IMM:
23044
0
    case AArch64::LD1H_4Z_IMM:
23045
0
    case AArch64::LD1W_4Z_IMM:
23046
0
    case AArch64::LDNT1B_4Z_IMM:
23047
0
    case AArch64::LDNT1D_4Z_IMM:
23048
0
    case AArch64::LDNT1H_4Z_IMM:
23049
0
    case AArch64::LDNT1W_4Z_IMM:
23050
0
    case AArch64::ST1B_4Z_IMM:
23051
0
    case AArch64::ST1D_4Z_IMM:
23052
0
    case AArch64::ST1H_4Z_IMM:
23053
0
    case AArch64::ST1W_4Z_IMM:
23054
0
    case AArch64::STNT1B_4Z_IMM:
23055
0
    case AArch64::STNT1D_4Z_IMM:
23056
0
    case AArch64::STNT1H_4Z_IMM:
23057
0
    case AArch64::STNT1W_4Z_IMM: {
23058
      // op: Zt
23059
0
      op = EncodeRegAsMultipleOf<4>(MI, 0, Fixups, STI);
23060
0
      op &= UINT64_C(7);
23061
0
      op <<= 2;
23062
0
      Value |= op;
23063
      // op: Rn
23064
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
23065
0
      op &= UINT64_C(31);
23066
0
      op <<= 5;
23067
0
      Value |= op;
23068
      // op: PNg
23069
0
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
23070
0
      op &= UINT64_C(7);
23071
0
      op <<= 10;
23072
0
      Value |= op;
23073
      // op: imm4
23074
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
23075
0
      op &= UINT64_C(15);
23076
0
      op <<= 16;
23077
0
      Value |= op;
23078
0
      break;
23079
0
    }
23080
0
    case AArch64::LD1B:
23081
0
    case AArch64::LD1B_D:
23082
0
    case AArch64::LD1B_H:
23083
0
    case AArch64::LD1B_S:
23084
0
    case AArch64::LD1D:
23085
0
    case AArch64::LD1H:
23086
0
    case AArch64::LD1H_D:
23087
0
    case AArch64::LD1H_S:
23088
0
    case AArch64::LD1SB_D:
23089
0
    case AArch64::LD1SB_H:
23090
0
    case AArch64::LD1SB_S:
23091
0
    case AArch64::LD1SH_D:
23092
0
    case AArch64::LD1SH_S:
23093
0
    case AArch64::LD1SW_D:
23094
0
    case AArch64::LD1W:
23095
0
    case AArch64::LD1W_D:
23096
0
    case AArch64::LDFF1B_D_REAL:
23097
0
    case AArch64::LDFF1B_H_REAL:
23098
0
    case AArch64::LDFF1B_REAL:
23099
0
    case AArch64::LDFF1B_S_REAL:
23100
0
    case AArch64::LDFF1D_REAL:
23101
0
    case AArch64::LDFF1H_D_REAL:
23102
0
    case AArch64::LDFF1H_REAL:
23103
0
    case AArch64::LDFF1H_S_REAL:
23104
0
    case AArch64::LDFF1SB_D_REAL:
23105
0
    case AArch64::LDFF1SB_H_REAL:
23106
0
    case AArch64::LDFF1SB_S_REAL:
23107
0
    case AArch64::LDFF1SH_D_REAL:
23108
0
    case AArch64::LDFF1SH_S_REAL:
23109
0
    case AArch64::LDFF1SW_D_REAL:
23110
0
    case AArch64::LDFF1W_D_REAL:
23111
0
    case AArch64::LDFF1W_REAL: {
23112
      // op: Zt
23113
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
23114
0
      op &= UINT64_C(31);
23115
0
      Value |= op;
23116
      // op: Pg
23117
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
23118
0
      op &= UINT64_C(7);
23119
0
      op <<= 10;
23120
0
      Value |= op;
23121
      // op: Rm
23122
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
23123
0
      op &= UINT64_C(31);
23124
0
      op <<= 16;
23125
0
      Value |= op;
23126
      // op: Rn
23127
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
23128
0
      op &= UINT64_C(31);
23129
0
      op <<= 5;
23130
0
      Value |= op;
23131
0
      break;
23132
0
    }
23133
0
    case AArch64::LD1RO_B:
23134
0
    case AArch64::LD1RO_D:
23135
0
    case AArch64::LD1RO_H:
23136
0
    case AArch64::LD1RO_W:
23137
0
    case AArch64::LD1RQ_B:
23138
0
    case AArch64::LD1RQ_D:
23139
0
    case AArch64::LD1RQ_H:
23140
0
    case AArch64::LD1RQ_W: {
23141
      // op: Zt
23142
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
23143
0
      op &= UINT64_C(31);
23144
0
      Value |= op;
23145
      // op: Pg
23146
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
23147
0
      op &= UINT64_C(7);
23148
0
      op <<= 10;
23149
0
      Value |= op;
23150
      // op: Rn
23151
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
23152
0
      op &= UINT64_C(31);
23153
0
      op <<= 5;
23154
0
      Value |= op;
23155
      // op: Rm
23156
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
23157
0
      op &= UINT64_C(31);
23158
0
      op <<= 16;
23159
0
      Value |= op;
23160
0
      break;
23161
0
    }
23162
0
    case AArch64::LD2B_IMM:
23163
0
    case AArch64::LD2D_IMM:
23164
0
    case AArch64::LD2H_IMM:
23165
0
    case AArch64::LD2Q_IMM:
23166
0
    case AArch64::LD2W_IMM:
23167
0
    case AArch64::LD3B_IMM:
23168
0
    case AArch64::LD3D_IMM:
23169
0
    case AArch64::LD3H_IMM:
23170
0
    case AArch64::LD3Q_IMM:
23171
0
    case AArch64::LD3W_IMM:
23172
0
    case AArch64::LD4B_IMM:
23173
0
    case AArch64::LD4D_IMM:
23174
0
    case AArch64::LD4H_IMM:
23175
0
    case AArch64::LD4Q_IMM:
23176
0
    case AArch64::LD4W_IMM:
23177
0
    case AArch64::LDNT1B_ZRI:
23178
0
    case AArch64::LDNT1D_ZRI:
23179
0
    case AArch64::LDNT1H_ZRI:
23180
0
    case AArch64::LDNT1W_ZRI: {
23181
      // op: Zt
23182
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
23183
0
      op &= UINT64_C(31);
23184
0
      Value |= op;
23185
      // op: Pg
23186
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
23187
0
      op &= UINT64_C(7);
23188
0
      op <<= 10;
23189
0
      Value |= op;
23190
      // op: Rn
23191
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
23192
0
      op &= UINT64_C(31);
23193
0
      op <<= 5;
23194
0
      Value |= op;
23195
      // op: imm4
23196
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
23197
0
      op &= UINT64_C(15);
23198
0
      op <<= 16;
23199
0
      Value |= op;
23200
0
      break;
23201
0
    }
23202
0
    case AArch64::LD1D_Q:
23203
0
    case AArch64::LD1W_Q:
23204
0
    case AArch64::ST2Q:
23205
0
    case AArch64::ST3Q:
23206
0
    case AArch64::ST4Q: {
23207
      // op: Zt
23208
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
23209
0
      op &= UINT64_C(31);
23210
0
      Value |= op;
23211
      // op: Rn
23212
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
23213
0
      op &= UINT64_C(31);
23214
0
      op <<= 5;
23215
0
      Value |= op;
23216
      // op: Pg
23217
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
23218
0
      op &= UINT64_C(7);
23219
0
      op <<= 10;
23220
0
      Value |= op;
23221
      // op: Rm
23222
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
23223
0
      op &= UINT64_C(31);
23224
0
      op <<= 16;
23225
0
      Value |= op;
23226
0
      break;
23227
0
    }
23228
0
    case AArch64::LD1D_Q_IMM:
23229
0
    case AArch64::LD1RO_B_IMM:
23230
0
    case AArch64::LD1RO_D_IMM:
23231
0
    case AArch64::LD1RO_H_IMM:
23232
0
    case AArch64::LD1RO_W_IMM:
23233
0
    case AArch64::LD1RQ_B_IMM:
23234
0
    case AArch64::LD1RQ_D_IMM:
23235
0
    case AArch64::LD1RQ_H_IMM:
23236
0
    case AArch64::LD1RQ_W_IMM:
23237
0
    case AArch64::LD1W_Q_IMM:
23238
0
    case AArch64::ST2Q_IMM:
23239
0
    case AArch64::ST3Q_IMM:
23240
0
    case AArch64::ST4Q_IMM: {
23241
      // op: Zt
23242
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
23243
0
      op &= UINT64_C(31);
23244
0
      Value |= op;
23245
      // op: Rn
23246
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
23247
0
      op &= UINT64_C(31);
23248
0
      op <<= 5;
23249
0
      Value |= op;
23250
      // op: Pg
23251
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
23252
0
      op &= UINT64_C(7);
23253
0
      op <<= 10;
23254
0
      Value |= op;
23255
      // op: imm4
23256
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
23257
0
      op &= UINT64_C(15);
23258
0
      op <<= 16;
23259
0
      Value |= op;
23260
0
      break;
23261
0
    }
23262
0
    case AArch64::GLD1Q:
23263
0
    case AArch64::SST1Q: {
23264
      // op: Zt
23265
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
23266
0
      op &= UINT64_C(31);
23267
0
      Value |= op;
23268
      // op: Zn
23269
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
23270
0
      op &= UINT64_C(31);
23271
0
      op <<= 5;
23272
0
      Value |= op;
23273
      // op: Pg
23274
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
23275
0
      op &= UINT64_C(7);
23276
0
      op <<= 10;
23277
0
      Value |= op;
23278
      // op: Rm
23279
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
23280
0
      op &= UINT64_C(31);
23281
0
      op <<= 16;
23282
0
      Value |= op;
23283
0
      break;
23284
0
    }
23285
0
    case AArch64::MOVT: {
23286
      // op: Zt
23287
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
23288
0
      op &= UINT64_C(31);
23289
0
      Value |= op;
23290
      // op: off2
23291
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
23292
0
      op &= UINT64_C(3);
23293
0
      op <<= 12;
23294
0
      Value |= op;
23295
0
      break;
23296
0
    }
23297
0
    case AArch64::B:
23298
0
    case AArch64::BL: {
23299
      // op: addr
23300
0
      op = getBranchTargetOpValue(MI, 0, Fixups, STI);
23301
0
      op &= UINT64_C(67108863);
23302
0
      Value |= op;
23303
0
      break;
23304
0
    }
23305
0
    case AArch64::BCcc:
23306
0
    case AArch64::Bcc: {
23307
      // op: cond
23308
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
23309
0
      op &= UINT64_C(15);
23310
0
      Value |= op;
23311
      // op: target
23312
0
      op = getCondBranchTargetOpValue(MI, 1, Fixups, STI);
23313
0
      op &= UINT64_C(524287);
23314
0
      op <<= 5;
23315
0
      Value |= op;
23316
0
      break;
23317
0
    }
23318
0
    case AArch64::DUPi64: {
23319
      // op: dst
23320
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
23321
0
      op &= UINT64_C(31);
23322
0
      Value |= op;
23323
      // op: src
23324
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
23325
0
      op &= UINT64_C(31);
23326
0
      op <<= 5;
23327
0
      Value |= op;
23328
      // op: idx
23329
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
23330
0
      op &= UINT64_C(1);
23331
0
      op <<= 20;
23332
0
      Value |= op;
23333
0
      break;
23334
0
    }
23335
0
    case AArch64::DUPi8: {
23336
      // op: dst
23337
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
23338
0
      op &= UINT64_C(31);
23339
0
      Value |= op;
23340
      // op: src
23341
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
23342
0
      op &= UINT64_C(31);
23343
0
      op <<= 5;
23344
0
      Value |= op;
23345
      // op: idx
23346
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
23347
0
      op &= UINT64_C(15);
23348
0
      op <<= 17;
23349
0
      Value |= op;
23350
0
      break;
23351
0
    }
23352
0
    case AArch64::DUPi32: {
23353
      // op: dst
23354
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
23355
0
      op &= UINT64_C(31);
23356
0
      Value |= op;
23357
      // op: src
23358
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
23359
0
      op &= UINT64_C(31);
23360
0
      op <<= 5;
23361
0
      Value |= op;
23362
      // op: idx
23363
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
23364
0
      op &= UINT64_C(3);
23365
0
      op <<= 19;
23366
0
      Value |= op;
23367
0
      break;
23368
0
    }
23369
0
    case AArch64::DUPi16: {
23370
      // op: dst
23371
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
23372
0
      op &= UINT64_C(31);
23373
0
      Value |= op;
23374
      // op: src
23375
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
23376
0
      op &= UINT64_C(31);
23377
0
      op <<= 5;
23378
0
      Value |= op;
23379
      // op: idx
23380
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
23381
0
      op &= UINT64_C(7);
23382
0
      op <<= 18;
23383
0
      Value |= op;
23384
0
      break;
23385
0
    }
23386
0
    case AArch64::ZERO_M: {
23387
      // op: imm
23388
0
      op = EncodeMatrixTileListRegisterClass(MI, 0, Fixups, STI);
23389
0
      op &= UINT64_C(255);
23390
0
      Value |= op;
23391
0
      break;
23392
0
    }
23393
0
    case AArch64::HINT: {
23394
      // op: imm
23395
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
23396
0
      op &= UINT64_C(127);
23397
0
      op <<= 5;
23398
0
      Value |= op;
23399
0
      break;
23400
0
    }
23401
0
    case AArch64::UDF: {
23402
      // op: imm
23403
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
23404
0
      op &= UINT64_C(65535);
23405
0
      Value |= op;
23406
0
      break;
23407
0
    }
23408
0
    case AArch64::BRK:
23409
0
    case AArch64::DCPS1:
23410
0
    case AArch64::DCPS2:
23411
0
    case AArch64::DCPS3:
23412
0
    case AArch64::HLT:
23413
0
    case AArch64::HVC:
23414
0
    case AArch64::SMC:
23415
0
    case AArch64::SVC:
23416
0
    case AArch64::TCANCEL: {
23417
      // op: imm
23418
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
23419
0
      op &= UINT64_C(65535);
23420
0
      op <<= 5;
23421
0
      Value |= op;
23422
0
      break;
23423
0
    }
23424
0
    case AArch64::MOVT_TIX: {
23425
      // op: imm3
23426
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
23427
0
      op &= UINT64_C(7);
23428
0
      op <<= 12;
23429
0
      Value |= op;
23430
      // op: Rt
23431
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
23432
0
      op &= UINT64_C(31);
23433
0
      Value |= op;
23434
0
      break;
23435
0
    }
23436
0
    case AArch64::MOVT_XTI: {
23437
      // op: imm3
23438
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
23439
0
      op &= UINT64_C(7);
23440
0
      op <<= 12;
23441
0
      Value |= op;
23442
      // op: Rt
23443
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
23444
0
      op &= UINT64_C(31);
23445
0
      Value |= op;
23446
0
      break;
23447
0
    }
23448
0
    case AArch64::LD1B_2Z_STRIDED_IMM:
23449
0
    case AArch64::LD1D_2Z_STRIDED_IMM:
23450
0
    case AArch64::LD1H_2Z_STRIDED_IMM:
23451
0
    case AArch64::LD1W_2Z_STRIDED_IMM:
23452
0
    case AArch64::LDNT1B_2Z_STRIDED_IMM:
23453
0
    case AArch64::LDNT1D_2Z_STRIDED_IMM:
23454
0
    case AArch64::LDNT1H_2Z_STRIDED_IMM:
23455
0
    case AArch64::LDNT1W_2Z_STRIDED_IMM:
23456
0
    case AArch64::ST1B_2Z_STRIDED_IMM:
23457
0
    case AArch64::ST1D_2Z_STRIDED_IMM:
23458
0
    case AArch64::ST1H_2Z_STRIDED_IMM:
23459
0
    case AArch64::ST1W_2Z_STRIDED_IMM:
23460
0
    case AArch64::STNT1B_2Z_STRIDED_IMM:
23461
0
    case AArch64::STNT1D_2Z_STRIDED_IMM:
23462
0
    case AArch64::STNT1H_2Z_STRIDED_IMM:
23463
0
    case AArch64::STNT1W_2Z_STRIDED_IMM: {
23464
      // op: imm4
23465
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
23466
0
      op &= UINT64_C(15);
23467
0
      op <<= 16;
23468
0
      Value |= op;
23469
      // op: PNg
23470
0
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
23471
0
      op &= UINT64_C(7);
23472
0
      op <<= 10;
23473
0
      Value |= op;
23474
      // op: Rn
23475
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
23476
0
      op &= UINT64_C(31);
23477
0
      op <<= 5;
23478
0
      Value |= op;
23479
      // op: Zt
23480
0
      op = EncodeZPR2StridedRegisterClass(MI, 0, Fixups, STI);
23481
0
      Value |= (op & UINT64_C(8)) << 1;
23482
0
      Value |= (op & UINT64_C(7));
23483
0
      break;
23484
0
    }
23485
0
    case AArch64::LD1B_4Z_STRIDED_IMM:
23486
0
    case AArch64::LD1D_4Z_STRIDED_IMM:
23487
0
    case AArch64::LD1H_4Z_STRIDED_IMM:
23488
0
    case AArch64::LD1W_4Z_STRIDED_IMM:
23489
0
    case AArch64::LDNT1B_4Z_STRIDED_IMM:
23490
0
    case AArch64::LDNT1D_4Z_STRIDED_IMM:
23491
0
    case AArch64::LDNT1H_4Z_STRIDED_IMM:
23492
0
    case AArch64::LDNT1W_4Z_STRIDED_IMM:
23493
0
    case AArch64::ST1B_4Z_STRIDED_IMM:
23494
0
    case AArch64::ST1D_4Z_STRIDED_IMM:
23495
0
    case AArch64::ST1H_4Z_STRIDED_IMM:
23496
0
    case AArch64::ST1W_4Z_STRIDED_IMM:
23497
0
    case AArch64::STNT1B_4Z_STRIDED_IMM:
23498
0
    case AArch64::STNT1D_4Z_STRIDED_IMM:
23499
0
    case AArch64::STNT1H_4Z_STRIDED_IMM:
23500
0
    case AArch64::STNT1W_4Z_STRIDED_IMM: {
23501
      // op: imm4
23502
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
23503
0
      op &= UINT64_C(15);
23504
0
      op <<= 16;
23505
0
      Value |= op;
23506
      // op: PNg
23507
0
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
23508
0
      op &= UINT64_C(7);
23509
0
      op <<= 10;
23510
0
      Value |= op;
23511
      // op: Rn
23512
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
23513
0
      op &= UINT64_C(31);
23514
0
      op <<= 5;
23515
0
      Value |= op;
23516
      // op: Zt
23517
0
      op = EncodeZPR4StridedRegisterClass(MI, 0, Fixups, STI);
23518
0
      Value |= (op & UINT64_C(4)) << 2;
23519
0
      Value |= (op & UINT64_C(3));
23520
0
      break;
23521
0
    }
23522
0
    case AArch64::SQRSHRU_VG2_Z2ZI_H:
23523
0
    case AArch64::SQRSHR_VG2_Z2ZI_H:
23524
0
    case AArch64::UQRSHR_VG2_Z2ZI_H: {
23525
      // op: imm4
23526
0
      op = getVecShiftR16OpValue(MI, 2, Fixups, STI);
23527
0
      op &= UINT64_C(15);
23528
0
      op <<= 16;
23529
0
      Value |= op;
23530
      // op: Zn
23531
0
      op = EncodeRegAsMultipleOf<2>(MI, 1, Fixups, STI);
23532
0
      op &= UINT64_C(15);
23533
0
      op <<= 6;
23534
0
      Value |= op;
23535
      // op: Zd
23536
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
23537
0
      op &= UINT64_C(31);
23538
0
      Value |= op;
23539
0
      break;
23540
0
    }
23541
0
    case AArch64::AUTIASPPCi:
23542
0
    case AArch64::AUTIBSPPCi:
23543
0
    case AArch64::RETAASPPCi:
23544
0
    case AArch64::RETABSPPCi: {
23545
      // op: label
23546
0
      op = getPAuthPCRelOpValue(MI, 0, Fixups, STI);
23547
0
      op &= UINT64_C(65535);
23548
0
      op <<= 5;
23549
0
      Value |= op;
23550
0
      break;
23551
0
    }
23552
0
    case AArch64::LDRAAindexed:
23553
0
    case AArch64::LDRABindexed: {
23554
      // op: offset
23555
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
23556
0
      Value |= (op & UINT64_C(512)) << 13;
23557
0
      Value |= (op & UINT64_C(511)) << 12;
23558
      // op: Rn
23559
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
23560
0
      op &= UINT64_C(31);
23561
0
      op <<= 5;
23562
0
      Value |= op;
23563
      // op: Rt
23564
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
23565
0
      op &= UINT64_C(31);
23566
0
      Value |= op;
23567
0
      break;
23568
0
    }
23569
0
    case AArch64::LDRAAwriteback:
23570
0
    case AArch64::LDRABwriteback: {
23571
      // op: offset
23572
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
23573
0
      Value |= (op & UINT64_C(512)) << 13;
23574
0
      Value |= (op & UINT64_C(511)) << 12;
23575
      // op: Rn
23576
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
23577
0
      op &= UINT64_C(31);
23578
0
      op <<= 5;
23579
0
      Value |= op;
23580
      // op: Rt
23581
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
23582
0
      op &= UINT64_C(31);
23583
0
      Value |= op;
23584
0
      break;
23585
0
    }
23586
0
    case AArch64::SYSPxt_XZR: {
23587
      // op: op1
23588
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
23589
0
      op &= UINT64_C(7);
23590
0
      op <<= 16;
23591
0
      Value |= op;
23592
      // op: Cn
23593
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
23594
0
      op &= UINT64_C(15);
23595
0
      op <<= 12;
23596
0
      Value |= op;
23597
      // op: Cm
23598
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
23599
0
      op &= UINT64_C(15);
23600
0
      op <<= 8;
23601
0
      Value |= op;
23602
      // op: op2
23603
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
23604
0
      op &= UINT64_C(7);
23605
0
      op <<= 5;
23606
0
      Value |= op;
23607
0
      break;
23608
0
    }
23609
0
    case AArch64::MSRpstateImm1: {
23610
      // op: pstatefield
23611
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
23612
0
      Value |= (op & UINT64_C(56)) << 13;
23613
0
      Value |= (op & UINT64_C(448)) << 3;
23614
0
      Value |= (op & UINT64_C(7)) << 5;
23615
      // op: imm
23616
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
23617
0
      op &= UINT64_C(1);
23618
0
      op <<= 8;
23619
0
      Value |= op;
23620
0
      break;
23621
0
    }
23622
0
    case AArch64::MSRpstateImm4: {
23623
      // op: pstatefield
23624
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
23625
0
      Value |= (op & UINT64_C(56)) << 13;
23626
0
      Value |= (op & UINT64_C(7)) << 5;
23627
      // op: imm
23628
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
23629
0
      op &= UINT64_C(15);
23630
0
      op <<= 8;
23631
0
      Value |= op;
23632
0
      break;
23633
0
    }
23634
0
    case AArch64::MSRpstatesvcrImm1: {
23635
      // op: pstatefield
23636
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
23637
0
      op &= UINT64_C(7);
23638
0
      op <<= 9;
23639
0
      Value |= op;
23640
      // op: imm
23641
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
23642
0
      op &= UINT64_C(1);
23643
0
      op <<= 8;
23644
0
      Value |= op;
23645
0
      break;
23646
0
    }
23647
0
  default:
23648
0
    std::string msg;
23649
0
    raw_string_ostream Msg(msg);
23650
0
    Msg << "Not supported instr: " << MI;
23651
0
    report_fatal_error(Msg.str().c_str());
23652
0
  }
23653
0
  return Value;
23654
0
}
23655
23656
#ifdef GET_OPERAND_BIT_OFFSET
23657
#undef GET_OPERAND_BIT_OFFSET
23658
23659
uint32_t AArch64MCCodeEmitter::getOperandBitOffset(const MCInst &MI,
23660
    unsigned OpNum,
23661
    const MCSubtargetInfo &STI) const {
23662
  switch (MI.getOpcode()) {
23663
    case AArch64::AUTIA1716:
23664
    case AArch64::AUTIA171615:
23665
    case AArch64::AUTIASP:
23666
    case AArch64::AUTIAZ:
23667
    case AArch64::AUTIB1716:
23668
    case AArch64::AUTIB171615:
23669
    case AArch64::AUTIBSP:
23670
    case AArch64::AUTIBZ:
23671
    case AArch64::AXFLAG:
23672
    case AArch64::BRB_IALL:
23673
    case AArch64::BRB_INJ:
23674
    case AArch64::CFINV:
23675
    case AArch64::CHKFEAT:
23676
    case AArch64::DRPS:
23677
    case AArch64::ERET:
23678
    case AArch64::ERETAA:
23679
    case AArch64::ERETAB:
23680
    case AArch64::GCSPOPCX:
23681
    case AArch64::GCSPOPX:
23682
    case AArch64::GCSPUSHX:
23683
    case AArch64::PACIA1716:
23684
    case AArch64::PACIA171615:
23685
    case AArch64::PACIASP:
23686
    case AArch64::PACIASPPC:
23687
    case AArch64::PACIAZ:
23688
    case AArch64::PACIB1716:
23689
    case AArch64::PACIB171615:
23690
    case AArch64::PACIBSP:
23691
    case AArch64::PACIBSPPC:
23692
    case AArch64::PACIBZ:
23693
    case AArch64::PACM:
23694
    case AArch64::PACNBIASPPC:
23695
    case AArch64::PACNBIBSPPC:
23696
    case AArch64::RETAA:
23697
    case AArch64::RETAB:
23698
    case AArch64::SB:
23699
    case AArch64::SETFFR:
23700
    case AArch64::TCOMMIT:
23701
    case AArch64::TSB:
23702
    case AArch64::XAFLAG:
23703
    case AArch64::XPACLRI:
23704
    case AArch64::ZERO_T: {
23705
      break;
23706
    }
23707
    case AArch64::DSBnXS: {
23708
      switch (OpNum) {
23709
      case 0:
23710
        // op: CRm
23711
        return 10;
23712
      }
23713
      break;
23714
    }
23715
    case AArch64::CLREX:
23716
    case AArch64::DMB:
23717
    case AArch64::DSB:
23718
    case AArch64::ISB: {
23719
      switch (OpNum) {
23720
      case 0:
23721
        // op: CRm
23722
        return 8;
23723
      }
23724
      break;
23725
    }
23726
    case AArch64::WHILEGE_CXX_B:
23727
    case AArch64::WHILEGE_CXX_D:
23728
    case AArch64::WHILEGE_CXX_H:
23729
    case AArch64::WHILEGE_CXX_S:
23730
    case AArch64::WHILEGT_CXX_B:
23731
    case AArch64::WHILEGT_CXX_D:
23732
    case AArch64::WHILEGT_CXX_H:
23733
    case AArch64::WHILEGT_CXX_S:
23734
    case AArch64::WHILEHI_CXX_B:
23735
    case AArch64::WHILEHI_CXX_D:
23736
    case AArch64::WHILEHI_CXX_H:
23737
    case AArch64::WHILEHI_CXX_S:
23738
    case AArch64::WHILEHS_CXX_B:
23739
    case AArch64::WHILEHS_CXX_D:
23740
    case AArch64::WHILEHS_CXX_H:
23741
    case AArch64::WHILEHS_CXX_S:
23742
    case AArch64::WHILELE_CXX_B:
23743
    case AArch64::WHILELE_CXX_D:
23744
    case AArch64::WHILELE_CXX_H:
23745
    case AArch64::WHILELE_CXX_S:
23746
    case AArch64::WHILELO_CXX_B:
23747
    case AArch64::WHILELO_CXX_D:
23748
    case AArch64::WHILELO_CXX_H:
23749
    case AArch64::WHILELO_CXX_S:
23750
    case AArch64::WHILELS_CXX_B:
23751
    case AArch64::WHILELS_CXX_D:
23752
    case AArch64::WHILELS_CXX_H:
23753
    case AArch64::WHILELS_CXX_S:
23754
    case AArch64::WHILELT_CXX_B:
23755
    case AArch64::WHILELT_CXX_D:
23756
    case AArch64::WHILELT_CXX_H:
23757
    case AArch64::WHILELT_CXX_S: {
23758
      switch (OpNum) {
23759
      case 0:
23760
        // op: PNd
23761
        return 0;
23762
      case 1:
23763
        // op: Rn
23764
        return 5;
23765
      case 3:
23766
        // op: vl
23767
        return 13;
23768
      case 2:
23769
        // op: Rm
23770
        return 16;
23771
      }
23772
      break;
23773
    }
23774
    case AArch64::PTRUE_C_B:
23775
    case AArch64::PTRUE_C_D:
23776
    case AArch64::PTRUE_C_H:
23777
    case AArch64::PTRUE_C_S: {
23778
      switch (OpNum) {
23779
      case 0:
23780
        // op: PNd
23781
        return 0;
23782
      }
23783
      break;
23784
    }
23785
    case AArch64::PEXT_2PCI_B:
23786
    case AArch64::PEXT_2PCI_D:
23787
    case AArch64::PEXT_2PCI_H:
23788
    case AArch64::PEXT_2PCI_S:
23789
    case AArch64::PEXT_PCI_B:
23790
    case AArch64::PEXT_PCI_D:
23791
    case AArch64::PEXT_PCI_H:
23792
    case AArch64::PEXT_PCI_S: {
23793
      switch (OpNum) {
23794
      case 0:
23795
        // op: Pd
23796
        return 0;
23797
      case 1:
23798
        // op: PNn
23799
        return 5;
23800
      case 2:
23801
        // op: index
23802
        return 8;
23803
      }
23804
      break;
23805
    }
23806
    case AArch64::BRKAS_PPzP:
23807
    case AArch64::BRKA_PPzP:
23808
    case AArch64::BRKBS_PPzP:
23809
    case AArch64::BRKB_PPzP: {
23810
      switch (OpNum) {
23811
      case 0:
23812
        // op: Pd
23813
        return 0;
23814
      case 1:
23815
        // op: Pg
23816
        return 10;
23817
      case 2:
23818
        // op: Pn
23819
        return 5;
23820
      }
23821
      break;
23822
    }
23823
    case AArch64::CMPEQ_PPzZI_B:
23824
    case AArch64::CMPEQ_PPzZI_D:
23825
    case AArch64::CMPEQ_PPzZI_H:
23826
    case AArch64::CMPEQ_PPzZI_S:
23827
    case AArch64::CMPGE_PPzZI_B:
23828
    case AArch64::CMPGE_PPzZI_D:
23829
    case AArch64::CMPGE_PPzZI_H:
23830
    case AArch64::CMPGE_PPzZI_S:
23831
    case AArch64::CMPGT_PPzZI_B:
23832
    case AArch64::CMPGT_PPzZI_D:
23833
    case AArch64::CMPGT_PPzZI_H:
23834
    case AArch64::CMPGT_PPzZI_S:
23835
    case AArch64::CMPLE_PPzZI_B:
23836
    case AArch64::CMPLE_PPzZI_D:
23837
    case AArch64::CMPLE_PPzZI_H:
23838
    case AArch64::CMPLE_PPzZI_S:
23839
    case AArch64::CMPLT_PPzZI_B:
23840
    case AArch64::CMPLT_PPzZI_D:
23841
    case AArch64::CMPLT_PPzZI_H:
23842
    case AArch64::CMPLT_PPzZI_S:
23843
    case AArch64::CMPNE_PPzZI_B:
23844
    case AArch64::CMPNE_PPzZI_D:
23845
    case AArch64::CMPNE_PPzZI_H:
23846
    case AArch64::CMPNE_PPzZI_S: {
23847
      switch (OpNum) {
23848
      case 0:
23849
        // op: Pd
23850
        return 0;
23851
      case 1:
23852
        // op: Pg
23853
        return 10;
23854
      case 2:
23855
        // op: Zn
23856
        return 5;
23857
      case 3:
23858
        // op: imm5
23859
        return 16;
23860
      }
23861
      break;
23862
    }
23863
    case AArch64::CMPHI_PPzZI_B:
23864
    case AArch64::CMPHI_PPzZI_D:
23865
    case AArch64::CMPHI_PPzZI_H:
23866
    case AArch64::CMPHI_PPzZI_S:
23867
    case AArch64::CMPHS_PPzZI_B:
23868
    case AArch64::CMPHS_PPzZI_D:
23869
    case AArch64::CMPHS_PPzZI_H:
23870
    case AArch64::CMPHS_PPzZI_S:
23871
    case AArch64::CMPLO_PPzZI_B:
23872
    case AArch64::CMPLO_PPzZI_D:
23873
    case AArch64::CMPLO_PPzZI_H:
23874
    case AArch64::CMPLO_PPzZI_S:
23875
    case AArch64::CMPLS_PPzZI_B:
23876
    case AArch64::CMPLS_PPzZI_D:
23877
    case AArch64::CMPLS_PPzZI_H:
23878
    case AArch64::CMPLS_PPzZI_S: {
23879
      switch (OpNum) {
23880
      case 0:
23881
        // op: Pd
23882
        return 0;
23883
      case 1:
23884
        // op: Pg
23885
        return 10;
23886
      case 2:
23887
        // op: Zn
23888
        return 5;
23889
      case 3:
23890
        // op: imm7
23891
        return 14;
23892
      }
23893
      break;
23894
    }
23895
    case AArch64::FCMEQ_PPzZ0_D:
23896
    case AArch64::FCMEQ_PPzZ0_H:
23897
    case AArch64::FCMEQ_PPzZ0_S:
23898
    case AArch64::FCMGE_PPzZ0_D:
23899
    case AArch64::FCMGE_PPzZ0_H:
23900
    case AArch64::FCMGE_PPzZ0_S:
23901
    case AArch64::FCMGT_PPzZ0_D:
23902
    case AArch64::FCMGT_PPzZ0_H:
23903
    case AArch64::FCMGT_PPzZ0_S:
23904
    case AArch64::FCMLE_PPzZ0_D:
23905
    case AArch64::FCMLE_PPzZ0_H:
23906
    case AArch64::FCMLE_PPzZ0_S:
23907
    case AArch64::FCMLT_PPzZ0_D:
23908
    case AArch64::FCMLT_PPzZ0_H:
23909
    case AArch64::FCMLT_PPzZ0_S:
23910
    case AArch64::FCMNE_PPzZ0_D:
23911
    case AArch64::FCMNE_PPzZ0_H:
23912
    case AArch64::FCMNE_PPzZ0_S: {
23913
      switch (OpNum) {
23914
      case 0:
23915
        // op: Pd
23916
        return 0;
23917
      case 1:
23918
        // op: Pg
23919
        return 10;
23920
      case 2:
23921
        // op: Zn
23922
        return 5;
23923
      }
23924
      break;
23925
    }
23926
    case AArch64::ANDS_PPzPP:
23927
    case AArch64::AND_PPzPP:
23928
    case AArch64::BICS_PPzPP:
23929
    case AArch64::BIC_PPzPP:
23930
    case AArch64::BRKPAS_PPzPP:
23931
    case AArch64::BRKPA_PPzPP:
23932
    case AArch64::BRKPBS_PPzPP:
23933
    case AArch64::BRKPB_PPzPP:
23934
    case AArch64::EORS_PPzPP:
23935
    case AArch64::EOR_PPzPP:
23936
    case AArch64::NANDS_PPzPP:
23937
    case AArch64::NAND_PPzPP:
23938
    case AArch64::NORS_PPzPP:
23939
    case AArch64::NOR_PPzPP:
23940
    case AArch64::ORNS_PPzPP:
23941
    case AArch64::ORN_PPzPP:
23942
    case AArch64::ORRS_PPzPP:
23943
    case AArch64::ORR_PPzPP:
23944
    case AArch64::SEL_PPPP: {
23945
      switch (OpNum) {
23946
      case 0:
23947
        // op: Pd
23948
        return 0;
23949
      case 1:
23950
        // op: Pg
23951
        return 10;
23952
      case 3:
23953
        // op: Pm
23954
        return 16;
23955
      case 2:
23956
        // op: Pn
23957
        return 5;
23958
      }
23959
      break;
23960
    }
23961
    case AArch64::CMPEQ_PPzZZ_B:
23962
    case AArch64::CMPEQ_PPzZZ_D:
23963
    case AArch64::CMPEQ_PPzZZ_H:
23964
    case AArch64::CMPEQ_PPzZZ_S:
23965
    case AArch64::CMPEQ_WIDE_PPzZZ_B:
23966
    case AArch64::CMPEQ_WIDE_PPzZZ_H:
23967
    case AArch64::CMPEQ_WIDE_PPzZZ_S:
23968
    case AArch64::CMPGE_PPzZZ_B:
23969
    case AArch64::CMPGE_PPzZZ_D:
23970
    case AArch64::CMPGE_PPzZZ_H:
23971
    case AArch64::CMPGE_PPzZZ_S:
23972
    case AArch64::CMPGE_WIDE_PPzZZ_B:
23973
    case AArch64::CMPGE_WIDE_PPzZZ_H:
23974
    case AArch64::CMPGE_WIDE_PPzZZ_S:
23975
    case AArch64::CMPGT_PPzZZ_B:
23976
    case AArch64::CMPGT_PPzZZ_D:
23977
    case AArch64::CMPGT_PPzZZ_H:
23978
    case AArch64::CMPGT_PPzZZ_S:
23979
    case AArch64::CMPGT_WIDE_PPzZZ_B:
23980
    case AArch64::CMPGT_WIDE_PPzZZ_H:
23981
    case AArch64::CMPGT_WIDE_PPzZZ_S:
23982
    case AArch64::CMPHI_PPzZZ_B:
23983
    case AArch64::CMPHI_PPzZZ_D:
23984
    case AArch64::CMPHI_PPzZZ_H:
23985
    case AArch64::CMPHI_PPzZZ_S:
23986
    case AArch64::CMPHI_WIDE_PPzZZ_B:
23987
    case AArch64::CMPHI_WIDE_PPzZZ_H:
23988
    case AArch64::CMPHI_WIDE_PPzZZ_S:
23989
    case AArch64::CMPHS_PPzZZ_B:
23990
    case AArch64::CMPHS_PPzZZ_D:
23991
    case AArch64::CMPHS_PPzZZ_H:
23992
    case AArch64::CMPHS_PPzZZ_S:
23993
    case AArch64::CMPHS_WIDE_PPzZZ_B:
23994
    case AArch64::CMPHS_WIDE_PPzZZ_H:
23995
    case AArch64::CMPHS_WIDE_PPzZZ_S:
23996
    case AArch64::CMPLE_WIDE_PPzZZ_B:
23997
    case AArch64::CMPLE_WIDE_PPzZZ_H:
23998
    case AArch64::CMPLE_WIDE_PPzZZ_S:
23999
    case AArch64::CMPLO_WIDE_PPzZZ_B:
24000
    case AArch64::CMPLO_WIDE_PPzZZ_H:
24001
    case AArch64::CMPLO_WIDE_PPzZZ_S:
24002
    case AArch64::CMPLS_WIDE_PPzZZ_B:
24003
    case AArch64::CMPLS_WIDE_PPzZZ_H:
24004
    case AArch64::CMPLS_WIDE_PPzZZ_S:
24005
    case AArch64::CMPLT_WIDE_PPzZZ_B:
24006
    case AArch64::CMPLT_WIDE_PPzZZ_H:
24007
    case AArch64::CMPLT_WIDE_PPzZZ_S:
24008
    case AArch64::CMPNE_PPzZZ_B:
24009
    case AArch64::CMPNE_PPzZZ_D:
24010
    case AArch64::CMPNE_PPzZZ_H:
24011
    case AArch64::CMPNE_PPzZZ_S:
24012
    case AArch64::CMPNE_WIDE_PPzZZ_B:
24013
    case AArch64::CMPNE_WIDE_PPzZZ_H:
24014
    case AArch64::CMPNE_WIDE_PPzZZ_S:
24015
    case AArch64::FACGE_PPzZZ_D:
24016
    case AArch64::FACGE_PPzZZ_H:
24017
    case AArch64::FACGE_PPzZZ_S:
24018
    case AArch64::FACGT_PPzZZ_D:
24019
    case AArch64::FACGT_PPzZZ_H:
24020
    case AArch64::FACGT_PPzZZ_S:
24021
    case AArch64::FCMEQ_PPzZZ_D:
24022
    case AArch64::FCMEQ_PPzZZ_H:
24023
    case AArch64::FCMEQ_PPzZZ_S:
24024
    case AArch64::FCMGE_PPzZZ_D:
24025
    case AArch64::FCMGE_PPzZZ_H:
24026
    case AArch64::FCMGE_PPzZZ_S:
24027
    case AArch64::FCMGT_PPzZZ_D:
24028
    case AArch64::FCMGT_PPzZZ_H:
24029
    case AArch64::FCMGT_PPzZZ_S:
24030
    case AArch64::FCMNE_PPzZZ_D:
24031
    case AArch64::FCMNE_PPzZZ_H:
24032
    case AArch64::FCMNE_PPzZZ_S:
24033
    case AArch64::FCMUO_PPzZZ_D:
24034
    case AArch64::FCMUO_PPzZZ_H:
24035
    case AArch64::FCMUO_PPzZZ_S:
24036
    case AArch64::MATCH_PPzZZ_B:
24037
    case AArch64::MATCH_PPzZZ_H:
24038
    case AArch64::NMATCH_PPzZZ_B:
24039
    case AArch64::NMATCH_PPzZZ_H: {
24040
      switch (OpNum) {
24041
      case 0:
24042
        // op: Pd
24043
        return 0;
24044
      case 1:
24045
        // op: Pg
24046
        return 10;
24047
      case 3:
24048
        // op: Zm
24049
        return 16;
24050
      case 2:
24051
        // op: Zn
24052
        return 5;
24053
      }
24054
      break;
24055
    }
24056
    case AArch64::RDFFRS_PPz:
24057
    case AArch64::RDFFR_PPz_REAL: {
24058
      switch (OpNum) {
24059
      case 0:
24060
        // op: Pd
24061
        return 0;
24062
      case 1:
24063
        // op: Pg
24064
        return 5;
24065
      }
24066
      break;
24067
    }
24068
    case AArch64::PUNPKHI_PP:
24069
    case AArch64::PUNPKLO_PP:
24070
    case AArch64::REV_PP_B:
24071
    case AArch64::REV_PP_D:
24072
    case AArch64::REV_PP_H:
24073
    case AArch64::REV_PP_S: {
24074
      switch (OpNum) {
24075
      case 0:
24076
        // op: Pd
24077
        return 0;
24078
      case 1:
24079
        // op: Pn
24080
        return 5;
24081
      }
24082
      break;
24083
    }
24084
    case AArch64::PMOV_PZI_D:
24085
    case AArch64::PMOV_PZI_H:
24086
    case AArch64::PMOV_PZI_S: {
24087
      switch (OpNum) {
24088
      case 0:
24089
        // op: Pd
24090
        return 0;
24091
      case 1:
24092
        // op: Zn
24093
        return 5;
24094
      case 2:
24095
        // op: index
24096
        return 17;
24097
      }
24098
      break;
24099
    }
24100
    case AArch64::PMOV_PZI_B: {
24101
      switch (OpNum) {
24102
      case 0:
24103
        // op: Pd
24104
        return 0;
24105
      case 1:
24106
        // op: Zn
24107
        return 5;
24108
      }
24109
      break;
24110
    }
24111
    case AArch64::PTRUES_B:
24112
    case AArch64::PTRUES_D:
24113
    case AArch64::PTRUES_H:
24114
    case AArch64::PTRUES_S:
24115
    case AArch64::PTRUE_B:
24116
    case AArch64::PTRUE_D:
24117
    case AArch64::PTRUE_H:
24118
    case AArch64::PTRUE_S: {
24119
      switch (OpNum) {
24120
      case 0:
24121
        // op: Pd
24122
        return 0;
24123
      case 1:
24124
        // op: pattern
24125
        return 5;
24126
      }
24127
      break;
24128
    }
24129
    case AArch64::BRKA_PPmP:
24130
    case AArch64::BRKB_PPmP: {
24131
      switch (OpNum) {
24132
      case 0:
24133
        // op: Pd
24134
        return 0;
24135
      case 2:
24136
        // op: Pg
24137
        return 10;
24138
      case 3:
24139
        // op: Pn
24140
        return 5;
24141
      }
24142
      break;
24143
    }
24144
    case AArch64::TRN1_PPP_B:
24145
    case AArch64::TRN1_PPP_D:
24146
    case AArch64::TRN1_PPP_H:
24147
    case AArch64::TRN1_PPP_S:
24148
    case AArch64::TRN2_PPP_B:
24149
    case AArch64::TRN2_PPP_D:
24150
    case AArch64::TRN2_PPP_H:
24151
    case AArch64::TRN2_PPP_S:
24152
    case AArch64::UZP1_PPP_B:
24153
    case AArch64::UZP1_PPP_D:
24154
    case AArch64::UZP1_PPP_H:
24155
    case AArch64::UZP1_PPP_S:
24156
    case AArch64::UZP2_PPP_B:
24157
    case AArch64::UZP2_PPP_D:
24158
    case AArch64::UZP2_PPP_H:
24159
    case AArch64::UZP2_PPP_S:
24160
    case AArch64::ZIP1_PPP_B:
24161
    case AArch64::ZIP1_PPP_D:
24162
    case AArch64::ZIP1_PPP_H:
24163
    case AArch64::ZIP1_PPP_S:
24164
    case AArch64::ZIP2_PPP_B:
24165
    case AArch64::ZIP2_PPP_D:
24166
    case AArch64::ZIP2_PPP_H:
24167
    case AArch64::ZIP2_PPP_S: {
24168
      switch (OpNum) {
24169
      case 0:
24170
        // op: Pd
24171
        return 0;
24172
      case 2:
24173
        // op: Pm
24174
        return 16;
24175
      case 1:
24176
        // op: Pn
24177
        return 5;
24178
      }
24179
      break;
24180
    }
24181
    case AArch64::WHILEGE_PWW_B:
24182
    case AArch64::WHILEGE_PWW_D:
24183
    case AArch64::WHILEGE_PWW_H:
24184
    case AArch64::WHILEGE_PWW_S:
24185
    case AArch64::WHILEGE_PXX_B:
24186
    case AArch64::WHILEGE_PXX_D:
24187
    case AArch64::WHILEGE_PXX_H:
24188
    case AArch64::WHILEGE_PXX_S:
24189
    case AArch64::WHILEGT_PWW_B:
24190
    case AArch64::WHILEGT_PWW_D:
24191
    case AArch64::WHILEGT_PWW_H:
24192
    case AArch64::WHILEGT_PWW_S:
24193
    case AArch64::WHILEGT_PXX_B:
24194
    case AArch64::WHILEGT_PXX_D:
24195
    case AArch64::WHILEGT_PXX_H:
24196
    case AArch64::WHILEGT_PXX_S:
24197
    case AArch64::WHILEHI_PWW_B:
24198
    case AArch64::WHILEHI_PWW_D:
24199
    case AArch64::WHILEHI_PWW_H:
24200
    case AArch64::WHILEHI_PWW_S:
24201
    case AArch64::WHILEHI_PXX_B:
24202
    case AArch64::WHILEHI_PXX_D:
24203
    case AArch64::WHILEHI_PXX_H:
24204
    case AArch64::WHILEHI_PXX_S:
24205
    case AArch64::WHILEHS_PWW_B:
24206
    case AArch64::WHILEHS_PWW_D:
24207
    case AArch64::WHILEHS_PWW_H:
24208
    case AArch64::WHILEHS_PWW_S:
24209
    case AArch64::WHILEHS_PXX_B:
24210
    case AArch64::WHILEHS_PXX_D:
24211
    case AArch64::WHILEHS_PXX_H:
24212
    case AArch64::WHILEHS_PXX_S:
24213
    case AArch64::WHILELE_PWW_B:
24214
    case AArch64::WHILELE_PWW_D:
24215
    case AArch64::WHILELE_PWW_H:
24216
    case AArch64::WHILELE_PWW_S:
24217
    case AArch64::WHILELE_PXX_B:
24218
    case AArch64::WHILELE_PXX_D:
24219
    case AArch64::WHILELE_PXX_H:
24220
    case AArch64::WHILELE_PXX_S:
24221
    case AArch64::WHILELO_PWW_B:
24222
    case AArch64::WHILELO_PWW_D:
24223
    case AArch64::WHILELO_PWW_H:
24224
    case AArch64::WHILELO_PWW_S:
24225
    case AArch64::WHILELO_PXX_B:
24226
    case AArch64::WHILELO_PXX_D:
24227
    case AArch64::WHILELO_PXX_H:
24228
    case AArch64::WHILELO_PXX_S:
24229
    case AArch64::WHILELS_PWW_B:
24230
    case AArch64::WHILELS_PWW_D:
24231
    case AArch64::WHILELS_PWW_H:
24232
    case AArch64::WHILELS_PWW_S:
24233
    case AArch64::WHILELS_PXX_B:
24234
    case AArch64::WHILELS_PXX_D:
24235
    case AArch64::WHILELS_PXX_H:
24236
    case AArch64::WHILELS_PXX_S:
24237
    case AArch64::WHILELT_PWW_B:
24238
    case AArch64::WHILELT_PWW_D:
24239
    case AArch64::WHILELT_PWW_H:
24240
    case AArch64::WHILELT_PWW_S:
24241
    case AArch64::WHILELT_PXX_B:
24242
    case AArch64::WHILELT_PXX_D:
24243
    case AArch64::WHILELT_PXX_H:
24244
    case AArch64::WHILELT_PXX_S:
24245
    case AArch64::WHILERW_PXX_B:
24246
    case AArch64::WHILERW_PXX_D:
24247
    case AArch64::WHILERW_PXX_H:
24248
    case AArch64::WHILERW_PXX_S:
24249
    case AArch64::WHILEWR_PXX_B:
24250
    case AArch64::WHILEWR_PXX_D:
24251
    case AArch64::WHILEWR_PXX_H:
24252
    case AArch64::WHILEWR_PXX_S: {
24253
      switch (OpNum) {
24254
      case 0:
24255
        // op: Pd
24256
        return 0;
24257
      case 2:
24258
        // op: Rm
24259
        return 16;
24260
      case 1:
24261
        // op: Rn
24262
        return 5;
24263
      }
24264
      break;
24265
    }
24266
    case AArch64::PFALSE:
24267
    case AArch64::RDFFR_P_REAL: {
24268
      switch (OpNum) {
24269
      case 0:
24270
        // op: Pd
24271
        return 0;
24272
      }
24273
      break;
24274
    }
24275
    case AArch64::WHILEGE_2PXX_B:
24276
    case AArch64::WHILEGE_2PXX_D:
24277
    case AArch64::WHILEGE_2PXX_H:
24278
    case AArch64::WHILEGE_2PXX_S:
24279
    case AArch64::WHILEGT_2PXX_B:
24280
    case AArch64::WHILEGT_2PXX_D:
24281
    case AArch64::WHILEGT_2PXX_H:
24282
    case AArch64::WHILEGT_2PXX_S:
24283
    case AArch64::WHILEHI_2PXX_B:
24284
    case AArch64::WHILEHI_2PXX_D:
24285
    case AArch64::WHILEHI_2PXX_H:
24286
    case AArch64::WHILEHI_2PXX_S:
24287
    case AArch64::WHILEHS_2PXX_B:
24288
    case AArch64::WHILEHS_2PXX_D:
24289
    case AArch64::WHILEHS_2PXX_H:
24290
    case AArch64::WHILEHS_2PXX_S:
24291
    case AArch64::WHILELE_2PXX_B:
24292
    case AArch64::WHILELE_2PXX_D:
24293
    case AArch64::WHILELE_2PXX_H:
24294
    case AArch64::WHILELE_2PXX_S:
24295
    case AArch64::WHILELO_2PXX_B:
24296
    case AArch64::WHILELO_2PXX_D:
24297
    case AArch64::WHILELO_2PXX_H:
24298
    case AArch64::WHILELO_2PXX_S:
24299
    case AArch64::WHILELS_2PXX_B:
24300
    case AArch64::WHILELS_2PXX_D:
24301
    case AArch64::WHILELS_2PXX_H:
24302
    case AArch64::WHILELS_2PXX_S:
24303
    case AArch64::WHILELT_2PXX_B:
24304
    case AArch64::WHILELT_2PXX_D:
24305
    case AArch64::WHILELT_2PXX_H:
24306
    case AArch64::WHILELT_2PXX_S: {
24307
      switch (OpNum) {
24308
      case 0:
24309
        // op: Pd
24310
        return 1;
24311
      case 1:
24312
        // op: Rn
24313
        return 5;
24314
      case 2:
24315
        // op: Rm
24316
        return 16;
24317
      }
24318
      break;
24319
    }
24320
    case AArch64::BRKNS_PPzP:
24321
    case AArch64::BRKN_PPzP: {
24322
      switch (OpNum) {
24323
      case 0:
24324
        // op: Pdm
24325
        return 0;
24326
      case 1:
24327
        // op: Pg
24328
        return 10;
24329
      case 2:
24330
        // op: Pn
24331
        return 5;
24332
      }
24333
      break;
24334
    }
24335
    case AArch64::PFIRST_B:
24336
    case AArch64::PNEXT_B:
24337
    case AArch64::PNEXT_D:
24338
    case AArch64::PNEXT_H:
24339
    case AArch64::PNEXT_S: {
24340
      switch (OpNum) {
24341
      case 0:
24342
        // op: Pdn
24343
        return 0;
24344
      case 1:
24345
        // op: Pg
24346
        return 5;
24347
      }
24348
      break;
24349
    }
24350
    case AArch64::PTEST_PP: {
24351
      switch (OpNum) {
24352
      case 0:
24353
        // op: Pg
24354
        return 10;
24355
      case 1:
24356
        // op: Pn
24357
        return 5;
24358
      }
24359
      break;
24360
    }
24361
    case AArch64::WRFFR: {
24362
      switch (OpNum) {
24363
      case 0:
24364
        // op: Pn
24365
        return 5;
24366
      }
24367
      break;
24368
    }
24369
    case AArch64::LDR_PXI:
24370
    case AArch64::STR_PXI: {
24371
      switch (OpNum) {
24372
      case 0:
24373
        // op: Pt
24374
        return 0;
24375
      case 1:
24376
        // op: Rn
24377
        return 5;
24378
      case 2:
24379
        // op: imm9
24380
        return 10;
24381
      }
24382
      break;
24383
    }
24384
    case AArch64::CNTP_XCI_B:
24385
    case AArch64::CNTP_XCI_D:
24386
    case AArch64::CNTP_XCI_H:
24387
    case AArch64::CNTP_XCI_S: {
24388
      switch (OpNum) {
24389
      case 0:
24390
        // op: Rd
24391
        return 0;
24392
      case 1:
24393
        // op: PNn
24394
        return 5;
24395
      case 2:
24396
        // op: vl
24397
        return 10;
24398
      }
24399
      break;
24400
    }
24401
    case AArch64::ADDPL_XXI:
24402
    case AArch64::ADDSPL_XXI:
24403
    case AArch64::ADDSVL_XXI:
24404
    case AArch64::ADDVL_XXI: {
24405
      switch (OpNum) {
24406
      case 0:
24407
        // op: Rd
24408
        return 0;
24409
      case 1:
24410
        // op: Rn
24411
        return 16;
24412
      case 2:
24413
        // op: imm6
24414
        return 5;
24415
      }
24416
      break;
24417
    }
24418
    case AArch64::FMADDDrrr:
24419
    case AArch64::FMADDHrrr:
24420
    case AArch64::FMADDSrrr:
24421
    case AArch64::FMSUBDrrr:
24422
    case AArch64::FMSUBHrrr:
24423
    case AArch64::FMSUBSrrr:
24424
    case AArch64::FNMADDDrrr:
24425
    case AArch64::FNMADDHrrr:
24426
    case AArch64::FNMADDSrrr:
24427
    case AArch64::FNMSUBDrrr:
24428
    case AArch64::FNMSUBHrrr:
24429
    case AArch64::FNMSUBSrrr:
24430
    case AArch64::MADDPT:
24431
    case AArch64::MADDWrrr:
24432
    case AArch64::MADDXrrr:
24433
    case AArch64::MSUBPT:
24434
    case AArch64::MSUBWrrr:
24435
    case AArch64::MSUBXrrr:
24436
    case AArch64::SMADDLrrr:
24437
    case AArch64::SMSUBLrrr:
24438
    case AArch64::UMADDLrrr:
24439
    case AArch64::UMSUBLrrr: {
24440
      switch (OpNum) {
24441
      case 0:
24442
        // op: Rd
24443
        return 0;
24444
      case 1:
24445
        // op: Rn
24446
        return 5;
24447
      case 2:
24448
        // op: Rm
24449
        return 16;
24450
      case 3:
24451
        // op: Ra
24452
        return 10;
24453
      }
24454
      break;
24455
    }
24456
    case AArch64::CSELWr:
24457
    case AArch64::CSELXr:
24458
    case AArch64::CSINCWr:
24459
    case AArch64::CSINCXr:
24460
    case AArch64::CSINVWr:
24461
    case AArch64::CSINVXr:
24462
    case AArch64::CSNEGWr:
24463
    case AArch64::CSNEGXr:
24464
    case AArch64::FCSELDrrr:
24465
    case AArch64::FCSELHrrr:
24466
    case AArch64::FCSELSrrr: {
24467
      switch (OpNum) {
24468
      case 0:
24469
        // op: Rd
24470
        return 0;
24471
      case 1:
24472
        // op: Rn
24473
        return 5;
24474
      case 2:
24475
        // op: Rm
24476
        return 16;
24477
      case 3:
24478
        // op: cond
24479
        return 12;
24480
      }
24481
      break;
24482
    }
24483
    case AArch64::ADDSXrx64:
24484
    case AArch64::ADDXrx64:
24485
    case AArch64::SUBSXrx64:
24486
    case AArch64::SUBXrx64: {
24487
      switch (OpNum) {
24488
      case 0:
24489
        // op: Rd
24490
        return 0;
24491
      case 1:
24492
        // op: Rn
24493
        return 5;
24494
      case 2:
24495
        // op: Rm
24496
        return 16;
24497
      case 3:
24498
        // op: ext
24499
        return 10;
24500
      }
24501
      break;
24502
    }
24503
    case AArch64::ADDSWrx:
24504
    case AArch64::ADDSXrx:
24505
    case AArch64::ADDWrx:
24506
    case AArch64::ADDXrx:
24507
    case AArch64::SUBSWrx:
24508
    case AArch64::SUBSXrx:
24509
    case AArch64::SUBWrx:
24510
    case AArch64::SUBXrx: {
24511
      switch (OpNum) {
24512
      case 0:
24513
        // op: Rd
24514
        return 0;
24515
      case 1:
24516
        // op: Rn
24517
        return 5;
24518
      case 2:
24519
        // op: Rm
24520
        return 16;
24521
      case 3:
24522
        // op: extend
24523
        return 10;
24524
      }
24525
      break;
24526
    }
24527
    case AArch64::FMULXv1i16_indexed:
24528
    case AArch64::FMULXv1i32_indexed:
24529
    case AArch64::FMULXv1i64_indexed:
24530
    case AArch64::FMULXv2i32_indexed:
24531
    case AArch64::FMULXv2i64_indexed:
24532
    case AArch64::FMULXv4i16_indexed:
24533
    case AArch64::FMULXv4i32_indexed:
24534
    case AArch64::FMULXv8i16_indexed:
24535
    case AArch64::FMULv1i16_indexed:
24536
    case AArch64::FMULv1i32_indexed:
24537
    case AArch64::FMULv1i64_indexed:
24538
    case AArch64::FMULv2i32_indexed:
24539
    case AArch64::FMULv2i64_indexed:
24540
    case AArch64::FMULv4i16_indexed:
24541
    case AArch64::FMULv4i32_indexed:
24542
    case AArch64::FMULv8i16_indexed:
24543
    case AArch64::MULv2i32_indexed:
24544
    case AArch64::MULv4i16_indexed:
24545
    case AArch64::MULv4i32_indexed:
24546
    case AArch64::MULv8i16_indexed:
24547
    case AArch64::SMULLv2i32_indexed:
24548
    case AArch64::SMULLv4i16_indexed:
24549
    case AArch64::SMULLv4i32_indexed:
24550
    case AArch64::SMULLv8i16_indexed:
24551
    case AArch64::SQDMULHv1i16_indexed:
24552
    case AArch64::SQDMULHv1i32_indexed:
24553
    case AArch64::SQDMULHv2i32_indexed:
24554
    case AArch64::SQDMULHv4i16_indexed:
24555
    case AArch64::SQDMULHv4i32_indexed:
24556
    case AArch64::SQDMULHv8i16_indexed:
24557
    case AArch64::SQDMULLv1i32_indexed:
24558
    case AArch64::SQDMULLv1i64_indexed:
24559
    case AArch64::SQDMULLv2i32_indexed:
24560
    case AArch64::SQDMULLv4i16_indexed:
24561
    case AArch64::SQDMULLv4i32_indexed:
24562
    case AArch64::SQDMULLv8i16_indexed:
24563
    case AArch64::SQRDMULHv1i16_indexed:
24564
    case AArch64::SQRDMULHv1i32_indexed:
24565
    case AArch64::SQRDMULHv2i32_indexed:
24566
    case AArch64::SQRDMULHv4i16_indexed:
24567
    case AArch64::SQRDMULHv4i32_indexed:
24568
    case AArch64::SQRDMULHv8i16_indexed:
24569
    case AArch64::UMULLv2i32_indexed:
24570
    case AArch64::UMULLv4i16_indexed:
24571
    case AArch64::UMULLv4i32_indexed:
24572
    case AArch64::UMULLv8i16_indexed: {
24573
      switch (OpNum) {
24574
      case 0:
24575
        // op: Rd
24576
        return 0;
24577
      case 1:
24578
        // op: Rn
24579
        return 5;
24580
      case 2:
24581
        // op: Rm
24582
        return 16;
24583
      case 3:
24584
        // op: idx
24585
        return 11;
24586
      }
24587
      break;
24588
    }
24589
    case AArch64::LUT2v8f16: {
24590
      switch (OpNum) {
24591
      case 0:
24592
        // op: Rd
24593
        return 0;
24594
      case 1:
24595
        // op: Rn
24596
        return 5;
24597
      case 2:
24598
        // op: Rm
24599
        return 16;
24600
      case 3:
24601
        // op: idx
24602
        return 12;
24603
      }
24604
      break;
24605
    }
24606
    case AArch64::LUT2v16f8:
24607
    case AArch64::LUT4v8f16: {
24608
      switch (OpNum) {
24609
      case 0:
24610
        // op: Rd
24611
        return 0;
24612
      case 1:
24613
        // op: Rn
24614
        return 5;
24615
      case 2:
24616
        // op: Rm
24617
        return 16;
24618
      case 3:
24619
        // op: idx
24620
        return 13;
24621
      }
24622
      break;
24623
    }
24624
    case AArch64::LUT4v16f8: {
24625
      switch (OpNum) {
24626
      case 0:
24627
        // op: Rd
24628
        return 0;
24629
      case 1:
24630
        // op: Rn
24631
        return 5;
24632
      case 2:
24633
        // op: Rm
24634
        return 16;
24635
      case 3:
24636
        // op: idx
24637
        return 14;
24638
      }
24639
      break;
24640
    }
24641
    case AArch64::EXTRWrri:
24642
    case AArch64::EXTRXrri: {
24643
      switch (OpNum) {
24644
      case 0:
24645
        // op: Rd
24646
        return 0;
24647
      case 1:
24648
        // op: Rn
24649
        return 5;
24650
      case 2:
24651
        // op: Rm
24652
        return 16;
24653
      case 3:
24654
        // op: imm
24655
        return 10;
24656
      }
24657
      break;
24658
    }
24659
    case AArch64::EXTv8i8:
24660
    case AArch64::EXTv16i8: {
24661
      switch (OpNum) {
24662
      case 0:
24663
        // op: Rd
24664
        return 0;
24665
      case 1:
24666
        // op: Rn
24667
        return 5;
24668
      case 2:
24669
        // op: Rm
24670
        return 16;
24671
      case 3:
24672
        // op: imm
24673
        return 11;
24674
      }
24675
      break;
24676
    }
24677
    case AArch64::FCADDv2f32:
24678
    case AArch64::FCADDv2f64:
24679
    case AArch64::FCADDv4f16:
24680
    case AArch64::FCADDv4f32:
24681
    case AArch64::FCADDv8f16: {
24682
      switch (OpNum) {
24683
      case 0:
24684
        // op: Rd
24685
        return 0;
24686
      case 1:
24687
        // op: Rn
24688
        return 5;
24689
      case 2:
24690
        // op: Rm
24691
        return 16;
24692
      case 3:
24693
        // op: rot
24694
        return 12;
24695
      }
24696
      break;
24697
    }
24698
    case AArch64::ADDSWrs:
24699
    case AArch64::ADDSXrs:
24700
    case AArch64::ADDWrs:
24701
    case AArch64::ADDXrs:
24702
    case AArch64::ANDSWrs:
24703
    case AArch64::ANDSXrs:
24704
    case AArch64::ANDWrs:
24705
    case AArch64::ANDXrs:
24706
    case AArch64::BICSWrs:
24707
    case AArch64::BICSXrs:
24708
    case AArch64::BICWrs:
24709
    case AArch64::BICXrs:
24710
    case AArch64::EONWrs:
24711
    case AArch64::EONXrs:
24712
    case AArch64::EORWrs:
24713
    case AArch64::EORXrs:
24714
    case AArch64::ORNWrs:
24715
    case AArch64::ORNXrs:
24716
    case AArch64::ORRWrs:
24717
    case AArch64::ORRXrs:
24718
    case AArch64::SUBSWrs:
24719
    case AArch64::SUBSXrs:
24720
    case AArch64::SUBWrs:
24721
    case AArch64::SUBXrs: {
24722
      switch (OpNum) {
24723
      case 0:
24724
        // op: Rd
24725
        return 0;
24726
      case 1:
24727
        // op: Rn
24728
        return 5;
24729
      case 2:
24730
        // op: Rm
24731
        return 16;
24732
      case 3:
24733
        // op: shift
24734
        return 10;
24735
      }
24736
      break;
24737
    }
24738
    case AArch64::ADDPT_shift:
24739
    case AArch64::SUBPT_shift: {
24740
      switch (OpNum) {
24741
      case 0:
24742
        // op: Rd
24743
        return 0;
24744
      case 1:
24745
        // op: Rn
24746
        return 5;
24747
      case 2:
24748
        // op: Rm
24749
        return 16;
24750
      case 3:
24751
        // op: shift_imm
24752
        return 10;
24753
      }
24754
      break;
24755
    }
24756
    case AArch64::ADCSWr:
24757
    case AArch64::ADCSXr:
24758
    case AArch64::ADCWr:
24759
    case AArch64::ADCXr:
24760
    case AArch64::ADDHNv2i64_v2i32:
24761
    case AArch64::ADDHNv4i32_v4i16:
24762
    case AArch64::ADDHNv8i16_v8i8:
24763
    case AArch64::ADDPv2i32:
24764
    case AArch64::ADDPv2i64:
24765
    case AArch64::ADDPv4i16:
24766
    case AArch64::ADDPv4i32:
24767
    case AArch64::ADDPv8i8:
24768
    case AArch64::ADDPv8i16:
24769
    case AArch64::ADDPv16i8:
24770
    case AArch64::ADDv1i64:
24771
    case AArch64::ADDv2i32:
24772
    case AArch64::ADDv2i64:
24773
    case AArch64::ADDv4i16:
24774
    case AArch64::ADDv4i32:
24775
    case AArch64::ADDv8i8:
24776
    case AArch64::ADDv8i16:
24777
    case AArch64::ADDv16i8:
24778
    case AArch64::ANDv8i8:
24779
    case AArch64::ANDv16i8:
24780
    case AArch64::ASRVWr:
24781
    case AArch64::ASRVXr:
24782
    case AArch64::BICv8i8:
24783
    case AArch64::BICv16i8:
24784
    case AArch64::CMEQv1i64:
24785
    case AArch64::CMEQv2i32:
24786
    case AArch64::CMEQv2i64:
24787
    case AArch64::CMEQv4i16:
24788
    case AArch64::CMEQv4i32:
24789
    case AArch64::CMEQv8i8:
24790
    case AArch64::CMEQv8i16:
24791
    case AArch64::CMEQv16i8:
24792
    case AArch64::CMGEv1i64:
24793
    case AArch64::CMGEv2i32:
24794
    case AArch64::CMGEv2i64:
24795
    case AArch64::CMGEv4i16:
24796
    case AArch64::CMGEv4i32:
24797
    case AArch64::CMGEv8i8:
24798
    case AArch64::CMGEv8i16:
24799
    case AArch64::CMGEv16i8:
24800
    case AArch64::CMGTv1i64:
24801
    case AArch64::CMGTv2i32:
24802
    case AArch64::CMGTv2i64:
24803
    case AArch64::CMGTv4i16:
24804
    case AArch64::CMGTv4i32:
24805
    case AArch64::CMGTv8i8:
24806
    case AArch64::CMGTv8i16:
24807
    case AArch64::CMGTv16i8:
24808
    case AArch64::CMHIv1i64:
24809
    case AArch64::CMHIv2i32:
24810
    case AArch64::CMHIv2i64:
24811
    case AArch64::CMHIv4i16:
24812
    case AArch64::CMHIv4i32:
24813
    case AArch64::CMHIv8i8:
24814
    case AArch64::CMHIv8i16:
24815
    case AArch64::CMHIv16i8:
24816
    case AArch64::CMHSv1i64:
24817
    case AArch64::CMHSv2i32:
24818
    case AArch64::CMHSv2i64:
24819
    case AArch64::CMHSv4i16:
24820
    case AArch64::CMHSv4i32:
24821
    case AArch64::CMHSv8i8:
24822
    case AArch64::CMHSv8i16:
24823
    case AArch64::CMHSv16i8:
24824
    case AArch64::CMTSTv1i64:
24825
    case AArch64::CMTSTv2i32:
24826
    case AArch64::CMTSTv2i64:
24827
    case AArch64::CMTSTv4i16:
24828
    case AArch64::CMTSTv4i32:
24829
    case AArch64::CMTSTv8i8:
24830
    case AArch64::CMTSTv8i16:
24831
    case AArch64::CMTSTv16i8:
24832
    case AArch64::CRC32Brr:
24833
    case AArch64::CRC32CBrr:
24834
    case AArch64::CRC32CHrr:
24835
    case AArch64::CRC32CWrr:
24836
    case AArch64::CRC32CXrr:
24837
    case AArch64::CRC32Hrr:
24838
    case AArch64::CRC32Wrr:
24839
    case AArch64::CRC32Xrr:
24840
    case AArch64::EORv8i8:
24841
    case AArch64::EORv16i8:
24842
    case AArch64::FABD16:
24843
    case AArch64::FABD32:
24844
    case AArch64::FABD64:
24845
    case AArch64::FABDv2f32:
24846
    case AArch64::FABDv2f64:
24847
    case AArch64::FABDv4f16:
24848
    case AArch64::FABDv4f32:
24849
    case AArch64::FABDv8f16:
24850
    case AArch64::FACGE16:
24851
    case AArch64::FACGE32:
24852
    case AArch64::FACGE64:
24853
    case AArch64::FACGEv2f32:
24854
    case AArch64::FACGEv2f64:
24855
    case AArch64::FACGEv4f16:
24856
    case AArch64::FACGEv4f32:
24857
    case AArch64::FACGEv8f16:
24858
    case AArch64::FACGT16:
24859
    case AArch64::FACGT32:
24860
    case AArch64::FACGT64:
24861
    case AArch64::FACGTv2f32:
24862
    case AArch64::FACGTv2f64:
24863
    case AArch64::FACGTv4f16:
24864
    case AArch64::FACGTv4f32:
24865
    case AArch64::FACGTv8f16:
24866
    case AArch64::FADDDrr:
24867
    case AArch64::FADDHrr:
24868
    case AArch64::FADDPv2f32:
24869
    case AArch64::FADDPv2f64:
24870
    case AArch64::FADDPv4f16:
24871
    case AArch64::FADDPv4f32:
24872
    case AArch64::FADDPv8f16:
24873
    case AArch64::FADDSrr:
24874
    case AArch64::FADDv2f32:
24875
    case AArch64::FADDv2f64:
24876
    case AArch64::FADDv4f16:
24877
    case AArch64::FADDv4f32:
24878
    case AArch64::FADDv8f16:
24879
    case AArch64::FAMAXv2f32:
24880
    case AArch64::FAMAXv2f64:
24881
    case AArch64::FAMAXv4f16:
24882
    case AArch64::FAMAXv4f32:
24883
    case AArch64::FAMAXv8f16:
24884
    case AArch64::FAMINv2f32:
24885
    case AArch64::FAMINv2f64:
24886
    case AArch64::FAMINv4f16:
24887
    case AArch64::FAMINv4f32:
24888
    case AArch64::FAMINv8f16:
24889
    case AArch64::FCMEQ16:
24890
    case AArch64::FCMEQ32:
24891
    case AArch64::FCMEQ64:
24892
    case AArch64::FCMEQv2f32:
24893
    case AArch64::FCMEQv2f64:
24894
    case AArch64::FCMEQv4f16:
24895
    case AArch64::FCMEQv4f32:
24896
    case AArch64::FCMEQv8f16:
24897
    case AArch64::FCMGE16:
24898
    case AArch64::FCMGE32:
24899
    case AArch64::FCMGE64:
24900
    case AArch64::FCMGEv2f32:
24901
    case AArch64::FCMGEv2f64:
24902
    case AArch64::FCMGEv4f16:
24903
    case AArch64::FCMGEv4f32:
24904
    case AArch64::FCMGEv8f16:
24905
    case AArch64::FCMGT16:
24906
    case AArch64::FCMGT32:
24907
    case AArch64::FCMGT64:
24908
    case AArch64::FCMGTv2f32:
24909
    case AArch64::FCMGTv2f64:
24910
    case AArch64::FCMGTv4f16:
24911
    case AArch64::FCMGTv4f32:
24912
    case AArch64::FCMGTv8f16:
24913
    case AArch64::FCVTN_F16_F8v8f8:
24914
    case AArch64::FCVTN_F16_F8v16f8:
24915
    case AArch64::FCVTN_F32_F8v8f8:
24916
    case AArch64::FDIVDrr:
24917
    case AArch64::FDIVHrr:
24918
    case AArch64::FDIVSrr:
24919
    case AArch64::FDIVv2f32:
24920
    case AArch64::FDIVv2f64:
24921
    case AArch64::FDIVv4f16:
24922
    case AArch64::FDIVv4f32:
24923
    case AArch64::FDIVv8f16:
24924
    case AArch64::FMAXDrr:
24925
    case AArch64::FMAXHrr:
24926
    case AArch64::FMAXNMDrr:
24927
    case AArch64::FMAXNMHrr:
24928
    case AArch64::FMAXNMPv2f32:
24929
    case AArch64::FMAXNMPv2f64:
24930
    case AArch64::FMAXNMPv4f16:
24931
    case AArch64::FMAXNMPv4f32:
24932
    case AArch64::FMAXNMPv8f16:
24933
    case AArch64::FMAXNMSrr:
24934
    case AArch64::FMAXNMv2f32:
24935
    case AArch64::FMAXNMv2f64:
24936
    case AArch64::FMAXNMv4f16:
24937
    case AArch64::FMAXNMv4f32:
24938
    case AArch64::FMAXNMv8f16:
24939
    case AArch64::FMAXPv2f32:
24940
    case AArch64::FMAXPv2f64:
24941
    case AArch64::FMAXPv4f16:
24942
    case AArch64::FMAXPv4f32:
24943
    case AArch64::FMAXPv8f16:
24944
    case AArch64::FMAXSrr:
24945
    case AArch64::FMAXv2f32:
24946
    case AArch64::FMAXv2f64:
24947
    case AArch64::FMAXv4f16:
24948
    case AArch64::FMAXv4f32:
24949
    case AArch64::FMAXv8f16:
24950
    case AArch64::FMINDrr:
24951
    case AArch64::FMINHrr:
24952
    case AArch64::FMINNMDrr:
24953
    case AArch64::FMINNMHrr:
24954
    case AArch64::FMINNMPv2f32:
24955
    case AArch64::FMINNMPv2f64:
24956
    case AArch64::FMINNMPv4f16:
24957
    case AArch64::FMINNMPv4f32:
24958
    case AArch64::FMINNMPv8f16:
24959
    case AArch64::FMINNMSrr:
24960
    case AArch64::FMINNMv2f32:
24961
    case AArch64::FMINNMv2f64:
24962
    case AArch64::FMINNMv4f16:
24963
    case AArch64::FMINNMv4f32:
24964
    case AArch64::FMINNMv8f16:
24965
    case AArch64::FMINPv2f32:
24966
    case AArch64::FMINPv2f64:
24967
    case AArch64::FMINPv4f16:
24968
    case AArch64::FMINPv4f32:
24969
    case AArch64::FMINPv8f16:
24970
    case AArch64::FMINSrr:
24971
    case AArch64::FMINv2f32:
24972
    case AArch64::FMINv2f64:
24973
    case AArch64::FMINv4f16:
24974
    case AArch64::FMINv4f32:
24975
    case AArch64::FMINv8f16:
24976
    case AArch64::FMULDrr:
24977
    case AArch64::FMULHrr:
24978
    case AArch64::FMULSrr:
24979
    case AArch64::FMULX16:
24980
    case AArch64::FMULX32:
24981
    case AArch64::FMULX64:
24982
    case AArch64::FMULXv2f32:
24983
    case AArch64::FMULXv2f64:
24984
    case AArch64::FMULXv4f16:
24985
    case AArch64::FMULXv4f32:
24986
    case AArch64::FMULXv8f16:
24987
    case AArch64::FMULv2f32:
24988
    case AArch64::FMULv2f64:
24989
    case AArch64::FMULv4f16:
24990
    case AArch64::FMULv4f32:
24991
    case AArch64::FMULv8f16:
24992
    case AArch64::FNMULDrr:
24993
    case AArch64::FNMULHrr:
24994
    case AArch64::FNMULSrr:
24995
    case AArch64::FRECPS16:
24996
    case AArch64::FRECPS32:
24997
    case AArch64::FRECPS64:
24998
    case AArch64::FRECPSv2f32:
24999
    case AArch64::FRECPSv2f64:
25000
    case AArch64::FRECPSv4f16:
25001
    case AArch64::FRECPSv4f32:
25002
    case AArch64::FRECPSv8f16:
25003
    case AArch64::FRSQRTS16:
25004
    case AArch64::FRSQRTS32:
25005
    case AArch64::FRSQRTS64:
25006
    case AArch64::FRSQRTSv2f32:
25007
    case AArch64::FRSQRTSv2f64:
25008
    case AArch64::FRSQRTSv4f16:
25009
    case AArch64::FRSQRTSv4f32:
25010
    case AArch64::FRSQRTSv8f16:
25011
    case AArch64::FSCALEv2f32:
25012
    case AArch64::FSCALEv2f64:
25013
    case AArch64::FSCALEv4f16:
25014
    case AArch64::FSCALEv4f32:
25015
    case AArch64::FSCALEv8f16:
25016
    case AArch64::FSUBDrr:
25017
    case AArch64::FSUBHrr:
25018
    case AArch64::FSUBSrr:
25019
    case AArch64::FSUBv2f32:
25020
    case AArch64::FSUBv2f64:
25021
    case AArch64::FSUBv4f16:
25022
    case AArch64::FSUBv4f32:
25023
    case AArch64::FSUBv8f16:
25024
    case AArch64::GMI:
25025
    case AArch64::IRG:
25026
    case AArch64::LSLVWr:
25027
    case AArch64::LSLVXr:
25028
    case AArch64::LSRVWr:
25029
    case AArch64::LSRVXr:
25030
    case AArch64::MULv2i32:
25031
    case AArch64::MULv4i16:
25032
    case AArch64::MULv4i32:
25033
    case AArch64::MULv8i8:
25034
    case AArch64::MULv8i16:
25035
    case AArch64::MULv16i8:
25036
    case AArch64::ORNv8i8:
25037
    case AArch64::ORNv16i8:
25038
    case AArch64::ORRv8i8:
25039
    case AArch64::ORRv16i8:
25040
    case AArch64::PACGA:
25041
    case AArch64::PMULLv1i64:
25042
    case AArch64::PMULLv2i64:
25043
    case AArch64::PMULLv8i8:
25044
    case AArch64::PMULLv16i8:
25045
    case AArch64::PMULv8i8:
25046
    case AArch64::PMULv16i8:
25047
    case AArch64::RADDHNv2i64_v2i32:
25048
    case AArch64::RADDHNv4i32_v4i16:
25049
    case AArch64::RADDHNv8i16_v8i8:
25050
    case AArch64::RORVWr:
25051
    case AArch64::RORVXr:
25052
    case AArch64::RSUBHNv2i64_v2i32:
25053
    case AArch64::RSUBHNv4i32_v4i16:
25054
    case AArch64::RSUBHNv8i16_v8i8:
25055
    case AArch64::SABDLv2i32_v2i64:
25056
    case AArch64::SABDLv4i16_v4i32:
25057
    case AArch64::SABDLv4i32_v2i64:
25058
    case AArch64::SABDLv8i8_v8i16:
25059
    case AArch64::SABDLv8i16_v4i32:
25060
    case AArch64::SABDLv16i8_v8i16:
25061
    case AArch64::SABDv2i32:
25062
    case AArch64::SABDv4i16:
25063
    case AArch64::SABDv4i32:
25064
    case AArch64::SABDv8i8:
25065
    case AArch64::SABDv8i16:
25066
    case AArch64::SABDv16i8:
25067
    case AArch64::SADDLv2i32_v2i64:
25068
    case AArch64::SADDLv4i16_v4i32:
25069
    case AArch64::SADDLv4i32_v2i64:
25070
    case AArch64::SADDLv8i8_v8i16:
25071
    case AArch64::SADDLv8i16_v4i32:
25072
    case AArch64::SADDLv16i8_v8i16:
25073
    case AArch64::SADDWv2i32_v2i64:
25074
    case AArch64::SADDWv4i16_v4i32:
25075
    case AArch64::SADDWv4i32_v2i64:
25076
    case AArch64::SADDWv8i8_v8i16:
25077
    case AArch64::SADDWv8i16_v4i32:
25078
    case AArch64::SADDWv16i8_v8i16:
25079
    case AArch64::SBCSWr:
25080
    case AArch64::SBCSXr:
25081
    case AArch64::SBCWr:
25082
    case AArch64::SBCXr:
25083
    case AArch64::SDIVWr:
25084
    case AArch64::SDIVXr:
25085
    case AArch64::SHADDv2i32:
25086
    case AArch64::SHADDv4i16:
25087
    case AArch64::SHADDv4i32:
25088
    case AArch64::SHADDv8i8:
25089
    case AArch64::SHADDv8i16:
25090
    case AArch64::SHADDv16i8:
25091
    case AArch64::SHSUBv2i32:
25092
    case AArch64::SHSUBv4i16:
25093
    case AArch64::SHSUBv4i32:
25094
    case AArch64::SHSUBv8i8:
25095
    case AArch64::SHSUBv8i16:
25096
    case AArch64::SHSUBv16i8:
25097
    case AArch64::SMAXPv2i32:
25098
    case AArch64::SMAXPv4i16:
25099
    case AArch64::SMAXPv4i32:
25100
    case AArch64::SMAXPv8i8:
25101
    case AArch64::SMAXPv8i16:
25102
    case AArch64::SMAXPv16i8:
25103
    case AArch64::SMAXWrr:
25104
    case AArch64::SMAXXrr:
25105
    case AArch64::SMAXv2i32:
25106
    case AArch64::SMAXv4i16:
25107
    case AArch64::SMAXv4i32:
25108
    case AArch64::SMAXv8i8:
25109
    case AArch64::SMAXv8i16:
25110
    case AArch64::SMAXv16i8:
25111
    case AArch64::SMINPv2i32:
25112
    case AArch64::SMINPv4i16:
25113
    case AArch64::SMINPv4i32:
25114
    case AArch64::SMINPv8i8:
25115
    case AArch64::SMINPv8i16:
25116
    case AArch64::SMINPv16i8:
25117
    case AArch64::SMINWrr:
25118
    case AArch64::SMINXrr:
25119
    case AArch64::SMINv2i32:
25120
    case AArch64::SMINv4i16:
25121
    case AArch64::SMINv4i32:
25122
    case AArch64::SMINv8i8:
25123
    case AArch64::SMINv8i16:
25124
    case AArch64::SMINv16i8:
25125
    case AArch64::SMULHrr:
25126
    case AArch64::SMULLv2i32_v2i64:
25127
    case AArch64::SMULLv4i16_v4i32:
25128
    case AArch64::SMULLv4i32_v2i64:
25129
    case AArch64::SMULLv8i8_v8i16:
25130
    case AArch64::SMULLv8i16_v4i32:
25131
    case AArch64::SMULLv16i8_v8i16:
25132
    case AArch64::SQADDv1i8:
25133
    case AArch64::SQADDv1i16:
25134
    case AArch64::SQADDv1i32:
25135
    case AArch64::SQADDv1i64:
25136
    case AArch64::SQADDv2i32:
25137
    case AArch64::SQADDv2i64:
25138
    case AArch64::SQADDv4i16:
25139
    case AArch64::SQADDv4i32:
25140
    case AArch64::SQADDv8i8:
25141
    case AArch64::SQADDv8i16:
25142
    case AArch64::SQADDv16i8:
25143
    case AArch64::SQDMULHv1i16:
25144
    case AArch64::SQDMULHv1i32:
25145
    case AArch64::SQDMULHv2i32:
25146
    case AArch64::SQDMULHv4i16:
25147
    case AArch64::SQDMULHv4i32:
25148
    case AArch64::SQDMULHv8i16:
25149
    case AArch64::SQDMULLi16:
25150
    case AArch64::SQDMULLi32:
25151
    case AArch64::SQDMULLv2i32_v2i64:
25152
    case AArch64::SQDMULLv4i16_v4i32:
25153
    case AArch64::SQDMULLv4i32_v2i64:
25154
    case AArch64::SQDMULLv8i16_v4i32:
25155
    case AArch64::SQRDMULHv1i16:
25156
    case AArch64::SQRDMULHv1i32:
25157
    case AArch64::SQRDMULHv2i32:
25158
    case AArch64::SQRDMULHv4i16:
25159
    case AArch64::SQRDMULHv4i32:
25160
    case AArch64::SQRDMULHv8i16:
25161
    case AArch64::SQRSHLv1i8:
25162
    case AArch64::SQRSHLv1i16:
25163
    case AArch64::SQRSHLv1i32:
25164
    case AArch64::SQRSHLv1i64:
25165
    case AArch64::SQRSHLv2i32:
25166
    case AArch64::SQRSHLv2i64:
25167
    case AArch64::SQRSHLv4i16:
25168
    case AArch64::SQRSHLv4i32:
25169
    case AArch64::SQRSHLv8i8:
25170
    case AArch64::SQRSHLv8i16:
25171
    case AArch64::SQRSHLv16i8:
25172
    case AArch64::SQSHLv1i8:
25173
    case AArch64::SQSHLv1i16:
25174
    case AArch64::SQSHLv1i32:
25175
    case AArch64::SQSHLv1i64:
25176
    case AArch64::SQSHLv2i32:
25177
    case AArch64::SQSHLv2i64:
25178
    case AArch64::SQSHLv4i16:
25179
    case AArch64::SQSHLv4i32:
25180
    case AArch64::SQSHLv8i8:
25181
    case AArch64::SQSHLv8i16:
25182
    case AArch64::SQSHLv16i8:
25183
    case AArch64::SQSUBv1i8:
25184
    case AArch64::SQSUBv1i16:
25185
    case AArch64::SQSUBv1i32:
25186
    case AArch64::SQSUBv1i64:
25187
    case AArch64::SQSUBv2i32:
25188
    case AArch64::SQSUBv2i64:
25189
    case AArch64::SQSUBv4i16:
25190
    case AArch64::SQSUBv4i32:
25191
    case AArch64::SQSUBv8i8:
25192
    case AArch64::SQSUBv8i16:
25193
    case AArch64::SQSUBv16i8:
25194
    case AArch64::SRHADDv2i32:
25195
    case AArch64::SRHADDv4i16:
25196
    case AArch64::SRHADDv4i32:
25197
    case AArch64::SRHADDv8i8:
25198
    case AArch64::SRHADDv8i16:
25199
    case AArch64::SRHADDv16i8:
25200
    case AArch64::SRSHLv1i64:
25201
    case AArch64::SRSHLv2i32:
25202
    case AArch64::SRSHLv2i64:
25203
    case AArch64::SRSHLv4i16:
25204
    case AArch64::SRSHLv4i32:
25205
    case AArch64::SRSHLv8i8:
25206
    case AArch64::SRSHLv8i16:
25207
    case AArch64::SRSHLv16i8:
25208
    case AArch64::SSHLv1i64:
25209
    case AArch64::SSHLv2i32:
25210
    case AArch64::SSHLv2i64:
25211
    case AArch64::SSHLv4i16:
25212
    case AArch64::SSHLv4i32:
25213
    case AArch64::SSHLv8i8:
25214
    case AArch64::SSHLv8i16:
25215
    case AArch64::SSHLv16i8:
25216
    case AArch64::SSUBLv2i32_v2i64:
25217
    case AArch64::SSUBLv4i16_v4i32:
25218
    case AArch64::SSUBLv4i32_v2i64:
25219
    case AArch64::SSUBLv8i8_v8i16:
25220
    case AArch64::SSUBLv8i16_v4i32:
25221
    case AArch64::SSUBLv16i8_v8i16:
25222
    case AArch64::SSUBWv2i32_v2i64:
25223
    case AArch64::SSUBWv4i16_v4i32:
25224
    case AArch64::SSUBWv4i32_v2i64:
25225
    case AArch64::SSUBWv8i8_v8i16:
25226
    case AArch64::SSUBWv8i16_v4i32:
25227
    case AArch64::SSUBWv16i8_v8i16:
25228
    case AArch64::SUBHNv2i64_v2i32:
25229
    case AArch64::SUBHNv4i32_v4i16:
25230
    case AArch64::SUBHNv8i16_v8i8:
25231
    case AArch64::SUBP:
25232
    case AArch64::SUBPS:
25233
    case AArch64::SUBv1i64:
25234
    case AArch64::SUBv2i32:
25235
    case AArch64::SUBv2i64:
25236
    case AArch64::SUBv4i16:
25237
    case AArch64::SUBv4i32:
25238
    case AArch64::SUBv8i8:
25239
    case AArch64::SUBv8i16:
25240
    case AArch64::SUBv16i8:
25241
    case AArch64::TRN1v2i32:
25242
    case AArch64::TRN1v2i64:
25243
    case AArch64::TRN1v4i16:
25244
    case AArch64::TRN1v4i32:
25245
    case AArch64::TRN1v8i8:
25246
    case AArch64::TRN1v8i16:
25247
    case AArch64::TRN1v16i8:
25248
    case AArch64::TRN2v2i32:
25249
    case AArch64::TRN2v2i64:
25250
    case AArch64::TRN2v4i16:
25251
    case AArch64::TRN2v4i32:
25252
    case AArch64::TRN2v8i8:
25253
    case AArch64::TRN2v8i16:
25254
    case AArch64::TRN2v16i8:
25255
    case AArch64::UABDLv2i32_v2i64:
25256
    case AArch64::UABDLv4i16_v4i32:
25257
    case AArch64::UABDLv4i32_v2i64:
25258
    case AArch64::UABDLv8i8_v8i16:
25259
    case AArch64::UABDLv8i16_v4i32:
25260
    case AArch64::UABDLv16i8_v8i16:
25261
    case AArch64::UABDv2i32:
25262
    case AArch64::UABDv4i16:
25263
    case AArch64::UABDv4i32:
25264
    case AArch64::UABDv8i8:
25265
    case AArch64::UABDv8i16:
25266
    case AArch64::UABDv16i8:
25267
    case AArch64::UADDLv2i32_v2i64:
25268
    case AArch64::UADDLv4i16_v4i32:
25269
    case AArch64::UADDLv4i32_v2i64:
25270
    case AArch64::UADDLv8i8_v8i16:
25271
    case AArch64::UADDLv8i16_v4i32:
25272
    case AArch64::UADDLv16i8_v8i16:
25273
    case AArch64::UADDWv2i32_v2i64:
25274
    case AArch64::UADDWv4i16_v4i32:
25275
    case AArch64::UADDWv4i32_v2i64:
25276
    case AArch64::UADDWv8i8_v8i16:
25277
    case AArch64::UADDWv8i16_v4i32:
25278
    case AArch64::UADDWv16i8_v8i16:
25279
    case AArch64::UDIVWr:
25280
    case AArch64::UDIVXr:
25281
    case AArch64::UHADDv2i32:
25282
    case AArch64::UHADDv4i16:
25283
    case AArch64::UHADDv4i32:
25284
    case AArch64::UHADDv8i8:
25285
    case AArch64::UHADDv8i16:
25286
    case AArch64::UHADDv16i8:
25287
    case AArch64::UHSUBv2i32:
25288
    case AArch64::UHSUBv4i16:
25289
    case AArch64::UHSUBv4i32:
25290
    case AArch64::UHSUBv8i8:
25291
    case AArch64::UHSUBv8i16:
25292
    case AArch64::UHSUBv16i8:
25293
    case AArch64::UMAXPv2i32:
25294
    case AArch64::UMAXPv4i16:
25295
    case AArch64::UMAXPv4i32:
25296
    case AArch64::UMAXPv8i8:
25297
    case AArch64::UMAXPv8i16:
25298
    case AArch64::UMAXPv16i8:
25299
    case AArch64::UMAXWrr:
25300
    case AArch64::UMAXXrr:
25301
    case AArch64::UMAXv2i32:
25302
    case AArch64::UMAXv4i16:
25303
    case AArch64::UMAXv4i32:
25304
    case AArch64::UMAXv8i8:
25305
    case AArch64::UMAXv8i16:
25306
    case AArch64::UMAXv16i8:
25307
    case AArch64::UMINPv2i32:
25308
    case AArch64::UMINPv4i16:
25309
    case AArch64::UMINPv4i32:
25310
    case AArch64::UMINPv8i8:
25311
    case AArch64::UMINPv8i16:
25312
    case AArch64::UMINPv16i8:
25313
    case AArch64::UMINWrr:
25314
    case AArch64::UMINXrr:
25315
    case AArch64::UMINv2i32:
25316
    case AArch64::UMINv4i16:
25317
    case AArch64::UMINv4i32:
25318
    case AArch64::UMINv8i8:
25319
    case AArch64::UMINv8i16:
25320
    case AArch64::UMINv16i8:
25321
    case AArch64::UMULHrr:
25322
    case AArch64::UMULLv2i32_v2i64:
25323
    case AArch64::UMULLv4i16_v4i32:
25324
    case AArch64::UMULLv4i32_v2i64:
25325
    case AArch64::UMULLv8i8_v8i16:
25326
    case AArch64::UMULLv8i16_v4i32:
25327
    case AArch64::UMULLv16i8_v8i16:
25328
    case AArch64::UQADDv1i8:
25329
    case AArch64::UQADDv1i16:
25330
    case AArch64::UQADDv1i32:
25331
    case AArch64::UQADDv1i64:
25332
    case AArch64::UQADDv2i32:
25333
    case AArch64::UQADDv2i64:
25334
    case AArch64::UQADDv4i16:
25335
    case AArch64::UQADDv4i32:
25336
    case AArch64::UQADDv8i8:
25337
    case AArch64::UQADDv8i16:
25338
    case AArch64::UQADDv16i8:
25339
    case AArch64::UQRSHLv1i8:
25340
    case AArch64::UQRSHLv1i16:
25341
    case AArch64::UQRSHLv1i32:
25342
    case AArch64::UQRSHLv1i64:
25343
    case AArch64::UQRSHLv2i32:
25344
    case AArch64::UQRSHLv2i64:
25345
    case AArch64::UQRSHLv4i16:
25346
    case AArch64::UQRSHLv4i32:
25347
    case AArch64::UQRSHLv8i8:
25348
    case AArch64::UQRSHLv8i16:
25349
    case AArch64::UQRSHLv16i8:
25350
    case AArch64::UQSHLv1i8:
25351
    case AArch64::UQSHLv1i16:
25352
    case AArch64::UQSHLv1i32:
25353
    case AArch64::UQSHLv1i64:
25354
    case AArch64::UQSHLv2i32:
25355
    case AArch64::UQSHLv2i64:
25356
    case AArch64::UQSHLv4i16:
25357
    case AArch64::UQSHLv4i32:
25358
    case AArch64::UQSHLv8i8:
25359
    case AArch64::UQSHLv8i16:
25360
    case AArch64::UQSHLv16i8:
25361
    case AArch64::UQSUBv1i8:
25362
    case AArch64::UQSUBv1i16:
25363
    case AArch64::UQSUBv1i32:
25364
    case AArch64::UQSUBv1i64:
25365
    case AArch64::UQSUBv2i32:
25366
    case AArch64::UQSUBv2i64:
25367
    case AArch64::UQSUBv4i16:
25368
    case AArch64::UQSUBv4i32:
25369
    case AArch64::UQSUBv8i8:
25370
    case AArch64::UQSUBv8i16:
25371
    case AArch64::UQSUBv16i8:
25372
    case AArch64::URHADDv2i32:
25373
    case AArch64::URHADDv4i16:
25374
    case AArch64::URHADDv4i32:
25375
    case AArch64::URHADDv8i8:
25376
    case AArch64::URHADDv8i16:
25377
    case AArch64::URHADDv16i8:
25378
    case AArch64::URSHLv1i64:
25379
    case AArch64::URSHLv2i32:
25380
    case AArch64::URSHLv2i64:
25381
    case AArch64::URSHLv4i16:
25382
    case AArch64::URSHLv4i32:
25383
    case AArch64::URSHLv8i8:
25384
    case AArch64::URSHLv8i16:
25385
    case AArch64::URSHLv16i8:
25386
    case AArch64::USHLv1i64:
25387
    case AArch64::USHLv2i32:
25388
    case AArch64::USHLv2i64:
25389
    case AArch64::USHLv4i16:
25390
    case AArch64::USHLv4i32:
25391
    case AArch64::USHLv8i8:
25392
    case AArch64::USHLv8i16:
25393
    case AArch64::USHLv16i8:
25394
    case AArch64::USUBLv2i32_v2i64:
25395
    case AArch64::USUBLv4i16_v4i32:
25396
    case AArch64::USUBLv4i32_v2i64:
25397
    case AArch64::USUBLv8i8_v8i16:
25398
    case AArch64::USUBLv8i16_v4i32:
25399
    case AArch64::USUBLv16i8_v8i16:
25400
    case AArch64::USUBWv2i32_v2i64:
25401
    case AArch64::USUBWv4i16_v4i32:
25402
    case AArch64::USUBWv4i32_v2i64:
25403
    case AArch64::USUBWv8i8_v8i16:
25404
    case AArch64::USUBWv8i16_v4i32:
25405
    case AArch64::USUBWv16i8_v8i16:
25406
    case AArch64::UZP1v2i32:
25407
    case AArch64::UZP1v2i64:
25408
    case AArch64::UZP1v4i16:
25409
    case AArch64::UZP1v4i32:
25410
    case AArch64::UZP1v8i8:
25411
    case AArch64::UZP1v8i16:
25412
    case AArch64::UZP1v16i8:
25413
    case AArch64::UZP2v2i32:
25414
    case AArch64::UZP2v2i64:
25415
    case AArch64::UZP2v4i16:
25416
    case AArch64::UZP2v4i32:
25417
    case AArch64::UZP2v8i8:
25418
    case AArch64::UZP2v8i16:
25419
    case AArch64::UZP2v16i8:
25420
    case AArch64::ZIP1v2i32:
25421
    case AArch64::ZIP1v2i64:
25422
    case AArch64::ZIP1v4i16:
25423
    case AArch64::ZIP1v4i32:
25424
    case AArch64::ZIP1v8i8:
25425
    case AArch64::ZIP1v8i16:
25426
    case AArch64::ZIP1v16i8:
25427
    case AArch64::ZIP2v2i32:
25428
    case AArch64::ZIP2v2i64:
25429
    case AArch64::ZIP2v4i16:
25430
    case AArch64::ZIP2v4i32:
25431
    case AArch64::ZIP2v8i8:
25432
    case AArch64::ZIP2v8i16:
25433
    case AArch64::ZIP2v16i8: {
25434
      switch (OpNum) {
25435
      case 0:
25436
        // op: Rd
25437
        return 0;
25438
      case 1:
25439
        // op: Rn
25440
        return 5;
25441
      case 2:
25442
        // op: Rm
25443
        return 16;
25444
      }
25445
      break;
25446
    }
25447
    case AArch64::DUPv8i8lane:
25448
    case AArch64::DUPv16i8lane:
25449
    case AArch64::SMOVvi8to32:
25450
    case AArch64::SMOVvi8to64:
25451
    case AArch64::UMOVvi8: {
25452
      switch (OpNum) {
25453
      case 0:
25454
        // op: Rd
25455
        return 0;
25456
      case 1:
25457
        // op: Rn
25458
        return 5;
25459
      case 2:
25460
        // op: idx
25461
        return 17;
25462
      }
25463
      break;
25464
    }
25465
    case AArch64::DUPv4i16lane:
25466
    case AArch64::DUPv8i16lane:
25467
    case AArch64::SMOVvi16to32:
25468
    case AArch64::SMOVvi16to64:
25469
    case AArch64::UMOVvi16: {
25470
      switch (OpNum) {
25471
      case 0:
25472
        // op: Rd
25473
        return 0;
25474
      case 1:
25475
        // op: Rn
25476
        return 5;
25477
      case 2:
25478
        // op: idx
25479
        return 18;
25480
      }
25481
      break;
25482
    }
25483
    case AArch64::DUPv2i32lane:
25484
    case AArch64::DUPv4i32lane:
25485
    case AArch64::SMOVvi32to64:
25486
    case AArch64::UMOVvi32: {
25487
      switch (OpNum) {
25488
      case 0:
25489
        // op: Rd
25490
        return 0;
25491
      case 1:
25492
        // op: Rn
25493
        return 5;
25494
      case 2:
25495
        // op: idx
25496
        return 19;
25497
      }
25498
      break;
25499
    }
25500
    case AArch64::DUPv2i64lane:
25501
    case AArch64::UMOVvi64: {
25502
      switch (OpNum) {
25503
      case 0:
25504
        // op: Rd
25505
        return 0;
25506
      case 1:
25507
        // op: Rn
25508
        return 5;
25509
      case 2:
25510
        // op: idx
25511
        return 20;
25512
      }
25513
      break;
25514
    }
25515
    case AArch64::ADDSWri:
25516
    case AArch64::ADDSXri:
25517
    case AArch64::ADDWri:
25518
    case AArch64::ADDXri:
25519
    case AArch64::ANDSWri:
25520
    case AArch64::ANDSXri:
25521
    case AArch64::ANDWri:
25522
    case AArch64::ANDXri:
25523
    case AArch64::EORWri:
25524
    case AArch64::EORXri:
25525
    case AArch64::ORRWri:
25526
    case AArch64::ORRXri:
25527
    case AArch64::SMAXWri:
25528
    case AArch64::SMAXXri:
25529
    case AArch64::SMINWri:
25530
    case AArch64::SMINXri:
25531
    case AArch64::SUBSWri:
25532
    case AArch64::SUBSXri:
25533
    case AArch64::SUBWri:
25534
    case AArch64::SUBXri:
25535
    case AArch64::UMAXWri:
25536
    case AArch64::UMAXXri:
25537
    case AArch64::UMINWri:
25538
    case AArch64::UMINXri: {
25539
      switch (OpNum) {
25540
      case 0:
25541
        // op: Rd
25542
        return 0;
25543
      case 1:
25544
        // op: Rn
25545
        return 5;
25546
      case 2:
25547
        // op: imm
25548
        return 10;
25549
      }
25550
      break;
25551
    }
25552
    case AArch64::FCVTZSd:
25553
    case AArch64::FCVTZSh:
25554
    case AArch64::FCVTZSs:
25555
    case AArch64::FCVTZSv2i32_shift:
25556
    case AArch64::FCVTZSv2i64_shift:
25557
    case AArch64::FCVTZSv4i16_shift:
25558
    case AArch64::FCVTZSv4i32_shift:
25559
    case AArch64::FCVTZSv8i16_shift:
25560
    case AArch64::FCVTZUd:
25561
    case AArch64::FCVTZUh:
25562
    case AArch64::FCVTZUs:
25563
    case AArch64::FCVTZUv2i32_shift:
25564
    case AArch64::FCVTZUv2i64_shift:
25565
    case AArch64::FCVTZUv4i16_shift:
25566
    case AArch64::FCVTZUv4i32_shift:
25567
    case AArch64::FCVTZUv8i16_shift:
25568
    case AArch64::RSHRNv2i32_shift:
25569
    case AArch64::RSHRNv4i16_shift:
25570
    case AArch64::RSHRNv8i8_shift:
25571
    case AArch64::SCVTFd:
25572
    case AArch64::SCVTFh:
25573
    case AArch64::SCVTFs:
25574
    case AArch64::SCVTFv2i32_shift:
25575
    case AArch64::SCVTFv2i64_shift:
25576
    case AArch64::SCVTFv4i16_shift:
25577
    case AArch64::SCVTFv4i32_shift:
25578
    case AArch64::SCVTFv8i16_shift:
25579
    case AArch64::SHLd:
25580
    case AArch64::SHLv2i32_shift:
25581
    case AArch64::SHLv2i64_shift:
25582
    case AArch64::SHLv4i16_shift:
25583
    case AArch64::SHLv4i32_shift:
25584
    case AArch64::SHLv8i8_shift:
25585
    case AArch64::SHLv8i16_shift:
25586
    case AArch64::SHLv16i8_shift:
25587
    case AArch64::SHRNv2i32_shift:
25588
    case AArch64::SHRNv4i16_shift:
25589
    case AArch64::SHRNv8i8_shift:
25590
    case AArch64::SQRSHRNb:
25591
    case AArch64::SQRSHRNh:
25592
    case AArch64::SQRSHRNs:
25593
    case AArch64::SQRSHRNv2i32_shift:
25594
    case AArch64::SQRSHRNv4i16_shift:
25595
    case AArch64::SQRSHRNv8i8_shift:
25596
    case AArch64::SQRSHRUNb:
25597
    case AArch64::SQRSHRUNh:
25598
    case AArch64::SQRSHRUNs:
25599
    case AArch64::SQRSHRUNv2i32_shift:
25600
    case AArch64::SQRSHRUNv4i16_shift:
25601
    case AArch64::SQRSHRUNv8i8_shift:
25602
    case AArch64::SQSHLUb:
25603
    case AArch64::SQSHLUd:
25604
    case AArch64::SQSHLUh:
25605
    case AArch64::SQSHLUs:
25606
    case AArch64::SQSHLUv2i32_shift:
25607
    case AArch64::SQSHLUv2i64_shift:
25608
    case AArch64::SQSHLUv4i16_shift:
25609
    case AArch64::SQSHLUv4i32_shift:
25610
    case AArch64::SQSHLUv8i8_shift:
25611
    case AArch64::SQSHLUv8i16_shift:
25612
    case AArch64::SQSHLUv16i8_shift:
25613
    case AArch64::SQSHLb:
25614
    case AArch64::SQSHLd:
25615
    case AArch64::SQSHLh:
25616
    case AArch64::SQSHLs:
25617
    case AArch64::SQSHLv2i32_shift:
25618
    case AArch64::SQSHLv2i64_shift:
25619
    case AArch64::SQSHLv4i16_shift:
25620
    case AArch64::SQSHLv4i32_shift:
25621
    case AArch64::SQSHLv8i8_shift:
25622
    case AArch64::SQSHLv8i16_shift:
25623
    case AArch64::SQSHLv16i8_shift:
25624
    case AArch64::SQSHRNb:
25625
    case AArch64::SQSHRNh:
25626
    case AArch64::SQSHRNs:
25627
    case AArch64::SQSHRNv2i32_shift:
25628
    case AArch64::SQSHRNv4i16_shift:
25629
    case AArch64::SQSHRNv8i8_shift:
25630
    case AArch64::SQSHRUNb:
25631
    case AArch64::SQSHRUNh:
25632
    case AArch64::SQSHRUNs:
25633
    case AArch64::SQSHRUNv2i32_shift:
25634
    case AArch64::SQSHRUNv4i16_shift:
25635
    case AArch64::SQSHRUNv8i8_shift:
25636
    case AArch64::SRSHRd:
25637
    case AArch64::SRSHRv2i32_shift:
25638
    case AArch64::SRSHRv2i64_shift:
25639
    case AArch64::SRSHRv4i16_shift:
25640
    case AArch64::SRSHRv4i32_shift:
25641
    case AArch64::SRSHRv8i8_shift:
25642
    case AArch64::SRSHRv8i16_shift:
25643
    case AArch64::SRSHRv16i8_shift:
25644
    case AArch64::SSHLLv2i32_shift:
25645
    case AArch64::SSHLLv4i16_shift:
25646
    case AArch64::SSHLLv4i32_shift:
25647
    case AArch64::SSHLLv8i8_shift:
25648
    case AArch64::SSHLLv8i16_shift:
25649
    case AArch64::SSHLLv16i8_shift:
25650
    case AArch64::SSHRd:
25651
    case AArch64::SSHRv2i32_shift:
25652
    case AArch64::SSHRv2i64_shift:
25653
    case AArch64::SSHRv4i16_shift:
25654
    case AArch64::SSHRv4i32_shift:
25655
    case AArch64::SSHRv8i8_shift:
25656
    case AArch64::SSHRv8i16_shift:
25657
    case AArch64::SSHRv16i8_shift:
25658
    case AArch64::UCVTFd:
25659
    case AArch64::UCVTFh:
25660
    case AArch64::UCVTFs:
25661
    case AArch64::UCVTFv2i32_shift:
25662
    case AArch64::UCVTFv2i64_shift:
25663
    case AArch64::UCVTFv4i16_shift:
25664
    case AArch64::UCVTFv4i32_shift:
25665
    case AArch64::UCVTFv8i16_shift:
25666
    case AArch64::UQRSHRNb:
25667
    case AArch64::UQRSHRNh:
25668
    case AArch64::UQRSHRNs:
25669
    case AArch64::UQRSHRNv2i32_shift:
25670
    case AArch64::UQRSHRNv4i16_shift:
25671
    case AArch64::UQRSHRNv8i8_shift:
25672
    case AArch64::UQSHLb:
25673
    case AArch64::UQSHLd:
25674
    case AArch64::UQSHLh:
25675
    case AArch64::UQSHLs:
25676
    case AArch64::UQSHLv2i32_shift:
25677
    case AArch64::UQSHLv2i64_shift:
25678
    case AArch64::UQSHLv4i16_shift:
25679
    case AArch64::UQSHLv4i32_shift:
25680
    case AArch64::UQSHLv8i8_shift:
25681
    case AArch64::UQSHLv8i16_shift:
25682
    case AArch64::UQSHLv16i8_shift:
25683
    case AArch64::UQSHRNb:
25684
    case AArch64::UQSHRNh:
25685
    case AArch64::UQSHRNs:
25686
    case AArch64::UQSHRNv2i32_shift:
25687
    case AArch64::UQSHRNv4i16_shift:
25688
    case AArch64::UQSHRNv8i8_shift:
25689
    case AArch64::URSHRd:
25690
    case AArch64::URSHRv2i32_shift:
25691
    case AArch64::URSHRv2i64_shift:
25692
    case AArch64::URSHRv4i16_shift:
25693
    case AArch64::URSHRv4i32_shift:
25694
    case AArch64::URSHRv8i8_shift:
25695
    case AArch64::URSHRv8i16_shift:
25696
    case AArch64::URSHRv16i8_shift:
25697
    case AArch64::USHLLv2i32_shift:
25698
    case AArch64::USHLLv4i16_shift:
25699
    case AArch64::USHLLv4i32_shift:
25700
    case AArch64::USHLLv8i8_shift:
25701
    case AArch64::USHLLv8i16_shift:
25702
    case AArch64::USHLLv16i8_shift:
25703
    case AArch64::USHRd:
25704
    case AArch64::USHRv2i32_shift:
25705
    case AArch64::USHRv2i64_shift:
25706
    case AArch64::USHRv4i16_shift:
25707
    case AArch64::USHRv4i32_shift:
25708
    case AArch64::USHRv8i8_shift:
25709
    case AArch64::USHRv8i16_shift:
25710
    case AArch64::USHRv16i8_shift: {
25711
      switch (OpNum) {
25712
      case 0:
25713
        // op: Rd
25714
        return 0;
25715
      case 1:
25716
        // op: Rn
25717
        return 5;
25718
      case 2:
25719
        // op: imm
25720
        return 16;
25721
      }
25722
      break;
25723
    }
25724
    case AArch64::ADDG:
25725
    case AArch64::SUBG: {
25726
      switch (OpNum) {
25727
      case 0:
25728
        // op: Rd
25729
        return 0;
25730
      case 1:
25731
        // op: Rn
25732
        return 5;
25733
      case 2:
25734
        // op: imm6
25735
        return 16;
25736
      case 3:
25737
        // op: imm4
25738
        return 10;
25739
      }
25740
      break;
25741
    }
25742
    case AArch64::SBFMWri:
25743
    case AArch64::SBFMXri:
25744
    case AArch64::UBFMWri:
25745
    case AArch64::UBFMXri: {
25746
      switch (OpNum) {
25747
      case 0:
25748
        // op: Rd
25749
        return 0;
25750
      case 1:
25751
        // op: Rn
25752
        return 5;
25753
      case 2:
25754
        // op: immr
25755
        return 16;
25756
      case 3:
25757
        // op: imms
25758
        return 10;
25759
      }
25760
      break;
25761
    }
25762
    case AArch64::FCVTZSSWDri:
25763
    case AArch64::FCVTZSSWHri:
25764
    case AArch64::FCVTZSSWSri:
25765
    case AArch64::FCVTZSSXDri:
25766
    case AArch64::FCVTZSSXHri:
25767
    case AArch64::FCVTZSSXSri:
25768
    case AArch64::FCVTZUSWDri:
25769
    case AArch64::FCVTZUSWHri:
25770
    case AArch64::FCVTZUSWSri:
25771
    case AArch64::FCVTZUSXDri:
25772
    case AArch64::FCVTZUSXHri:
25773
    case AArch64::FCVTZUSXSri:
25774
    case AArch64::SCVTFSWDri:
25775
    case AArch64::SCVTFSWHri:
25776
    case AArch64::SCVTFSWSri:
25777
    case AArch64::SCVTFSXDri:
25778
    case AArch64::SCVTFSXHri:
25779
    case AArch64::SCVTFSXSri:
25780
    case AArch64::UCVTFSWDri:
25781
    case AArch64::UCVTFSWHri:
25782
    case AArch64::UCVTFSWSri:
25783
    case AArch64::UCVTFSXDri:
25784
    case AArch64::UCVTFSXHri:
25785
    case AArch64::UCVTFSXSri: {
25786
      switch (OpNum) {
25787
      case 0:
25788
        // op: Rd
25789
        return 0;
25790
      case 1:
25791
        // op: Rn
25792
        return 5;
25793
      case 2:
25794
        // op: scale
25795
        return 10;
25796
      }
25797
      break;
25798
    }
25799
    case AArch64::ABSWr:
25800
    case AArch64::ABSXr:
25801
    case AArch64::ABSv1i64:
25802
    case AArch64::ABSv2i32:
25803
    case AArch64::ABSv2i64:
25804
    case AArch64::ABSv4i16:
25805
    case AArch64::ABSv4i32:
25806
    case AArch64::ABSv8i8:
25807
    case AArch64::ABSv8i16:
25808
    case AArch64::ABSv16i8:
25809
    case AArch64::ADDPv2i64p:
25810
    case AArch64::ADDVv4i16v:
25811
    case AArch64::ADDVv4i32v:
25812
    case AArch64::ADDVv8i8v:
25813
    case AArch64::ADDVv8i16v:
25814
    case AArch64::ADDVv16i8v:
25815
    case AArch64::AESIMCrr:
25816
    case AArch64::AESMCrr:
25817
    case AArch64::BF1CVTL2v8f16:
25818
    case AArch64::BF1CVTLv8f16:
25819
    case AArch64::BF2CVTL2v8f16:
25820
    case AArch64::BF2CVTLv8f16:
25821
    case AArch64::BFCVT:
25822
    case AArch64::BFCVTN:
25823
    case AArch64::CLSWr:
25824
    case AArch64::CLSXr:
25825
    case AArch64::CLSv2i32:
25826
    case AArch64::CLSv4i16:
25827
    case AArch64::CLSv4i32:
25828
    case AArch64::CLSv8i8:
25829
    case AArch64::CLSv8i16:
25830
    case AArch64::CLSv16i8:
25831
    case AArch64::CLZWr:
25832
    case AArch64::CLZXr:
25833
    case AArch64::CLZv2i32:
25834
    case AArch64::CLZv4i16:
25835
    case AArch64::CLZv4i32:
25836
    case AArch64::CLZv8i8:
25837
    case AArch64::CLZv8i16:
25838
    case AArch64::CLZv16i8:
25839
    case AArch64::CMEQv1i64rz:
25840
    case AArch64::CMEQv2i32rz:
25841
    case AArch64::CMEQv2i64rz:
25842
    case AArch64::CMEQv4i16rz:
25843
    case AArch64::CMEQv4i32rz:
25844
    case AArch64::CMEQv8i8rz:
25845
    case AArch64::CMEQv8i16rz:
25846
    case AArch64::CMEQv16i8rz:
25847
    case AArch64::CMGEv1i64rz:
25848
    case AArch64::CMGEv2i32rz:
25849
    case AArch64::CMGEv2i64rz:
25850
    case AArch64::CMGEv4i16rz:
25851
    case AArch64::CMGEv4i32rz:
25852
    case AArch64::CMGEv8i8rz:
25853
    case AArch64::CMGEv8i16rz:
25854
    case AArch64::CMGEv16i8rz:
25855
    case AArch64::CMGTv1i64rz:
25856
    case AArch64::CMGTv2i32rz:
25857
    case AArch64::CMGTv2i64rz:
25858
    case AArch64::CMGTv4i16rz:
25859
    case AArch64::CMGTv4i32rz:
25860
    case AArch64::CMGTv8i8rz:
25861
    case AArch64::CMGTv8i16rz:
25862
    case AArch64::CMGTv16i8rz:
25863
    case AArch64::CMLEv1i64rz:
25864
    case AArch64::CMLEv2i32rz:
25865
    case AArch64::CMLEv2i64rz:
25866
    case AArch64::CMLEv4i16rz:
25867
    case AArch64::CMLEv4i32rz:
25868
    case AArch64::CMLEv8i8rz:
25869
    case AArch64::CMLEv8i16rz:
25870
    case AArch64::CMLEv16i8rz:
25871
    case AArch64::CMLTv1i64rz:
25872
    case AArch64::CMLTv2i32rz:
25873
    case AArch64::CMLTv2i64rz:
25874
    case AArch64::CMLTv4i16rz:
25875
    case AArch64::CMLTv4i32rz:
25876
    case AArch64::CMLTv8i8rz:
25877
    case AArch64::CMLTv8i16rz:
25878
    case AArch64::CMLTv16i8rz:
25879
    case AArch64::CNTWr:
25880
    case AArch64::CNTXr:
25881
    case AArch64::CNTv8i8:
25882
    case AArch64::CNTv16i8:
25883
    case AArch64::CTZWr:
25884
    case AArch64::CTZXr:
25885
    case AArch64::DUPv2i32gpr:
25886
    case AArch64::DUPv2i64gpr:
25887
    case AArch64::DUPv4i16gpr:
25888
    case AArch64::DUPv4i32gpr:
25889
    case AArch64::DUPv8i8gpr:
25890
    case AArch64::DUPv8i16gpr:
25891
    case AArch64::DUPv16i8gpr:
25892
    case AArch64::F1CVTL2v8f16:
25893
    case AArch64::F1CVTLv8f16:
25894
    case AArch64::F2CVTL2v8f16:
25895
    case AArch64::F2CVTLv8f16:
25896
    case AArch64::FABSDr:
25897
    case AArch64::FABSHr:
25898
    case AArch64::FABSSr:
25899
    case AArch64::FABSv2f32:
25900
    case AArch64::FABSv2f64:
25901
    case AArch64::FABSv4f16:
25902
    case AArch64::FABSv4f32:
25903
    case AArch64::FABSv8f16:
25904
    case AArch64::FADDPv2i16p:
25905
    case AArch64::FADDPv2i32p:
25906
    case AArch64::FADDPv2i64p:
25907
    case AArch64::FCMEQv1i16rz:
25908
    case AArch64::FCMEQv1i32rz:
25909
    case AArch64::FCMEQv1i64rz:
25910
    case AArch64::FCMEQv2i32rz:
25911
    case AArch64::FCMEQv2i64rz:
25912
    case AArch64::FCMEQv4i16rz:
25913
    case AArch64::FCMEQv4i32rz:
25914
    case AArch64::FCMEQv8i16rz:
25915
    case AArch64::FCMGEv1i16rz:
25916
    case AArch64::FCMGEv1i32rz:
25917
    case AArch64::FCMGEv1i64rz:
25918
    case AArch64::FCMGEv2i32rz:
25919
    case AArch64::FCMGEv2i64rz:
25920
    case AArch64::FCMGEv4i16rz:
25921
    case AArch64::FCMGEv4i32rz:
25922
    case AArch64::FCMGEv8i16rz:
25923
    case AArch64::FCMGTv1i16rz:
25924
    case AArch64::FCMGTv1i32rz:
25925
    case AArch64::FCMGTv1i64rz:
25926
    case AArch64::FCMGTv2i32rz:
25927
    case AArch64::FCMGTv2i64rz:
25928
    case AArch64::FCMGTv4i16rz:
25929
    case AArch64::FCMGTv4i32rz:
25930
    case AArch64::FCMGTv8i16rz:
25931
    case AArch64::FCMLEv1i16rz:
25932
    case AArch64::FCMLEv1i32rz:
25933
    case AArch64::FCMLEv1i64rz:
25934
    case AArch64::FCMLEv2i32rz:
25935
    case AArch64::FCMLEv2i64rz:
25936
    case AArch64::FCMLEv4i16rz:
25937
    case AArch64::FCMLEv4i32rz:
25938
    case AArch64::FCMLEv8i16rz:
25939
    case AArch64::FCMLTv1i16rz:
25940
    case AArch64::FCMLTv1i32rz:
25941
    case AArch64::FCMLTv1i64rz:
25942
    case AArch64::FCMLTv2i32rz:
25943
    case AArch64::FCMLTv2i64rz:
25944
    case AArch64::FCMLTv4i16rz:
25945
    case AArch64::FCMLTv4i32rz:
25946
    case AArch64::FCMLTv8i16rz:
25947
    case AArch64::FCVTASUWDr:
25948
    case AArch64::FCVTASUWHr:
25949
    case AArch64::FCVTASUWSr:
25950
    case AArch64::FCVTASUXDr:
25951
    case AArch64::FCVTASUXHr:
25952
    case AArch64::FCVTASUXSr:
25953
    case AArch64::FCVTASv1f16:
25954
    case AArch64::FCVTASv1i32:
25955
    case AArch64::FCVTASv1i64:
25956
    case AArch64::FCVTASv2f32:
25957
    case AArch64::FCVTASv2f64:
25958
    case AArch64::FCVTASv4f16:
25959
    case AArch64::FCVTASv4f32:
25960
    case AArch64::FCVTASv8f16:
25961
    case AArch64::FCVTAUUWDr:
25962
    case AArch64::FCVTAUUWHr:
25963
    case AArch64::FCVTAUUWSr:
25964
    case AArch64::FCVTAUUXDr:
25965
    case AArch64::FCVTAUUXHr:
25966
    case AArch64::FCVTAUUXSr:
25967
    case AArch64::FCVTAUv1f16:
25968
    case AArch64::FCVTAUv1i32:
25969
    case AArch64::FCVTAUv1i64:
25970
    case AArch64::FCVTAUv2f32:
25971
    case AArch64::FCVTAUv2f64:
25972
    case AArch64::FCVTAUv4f16:
25973
    case AArch64::FCVTAUv4f32:
25974
    case AArch64::FCVTAUv8f16:
25975
    case AArch64::FCVTDHr:
25976
    case AArch64::FCVTDSr:
25977
    case AArch64::FCVTHDr:
25978
    case AArch64::FCVTHSr:
25979
    case AArch64::FCVTLv2i32:
25980
    case AArch64::FCVTLv4i16:
25981
    case AArch64::FCVTLv4i32:
25982
    case AArch64::FCVTLv8i16:
25983
    case AArch64::FCVTMSUWDr:
25984
    case AArch64::FCVTMSUWHr:
25985
    case AArch64::FCVTMSUWSr:
25986
    case AArch64::FCVTMSUXDr:
25987
    case AArch64::FCVTMSUXHr:
25988
    case AArch64::FCVTMSUXSr:
25989
    case AArch64::FCVTMSv1f16:
25990
    case AArch64::FCVTMSv1i32:
25991
    case AArch64::FCVTMSv1i64:
25992
    case AArch64::FCVTMSv2f32:
25993
    case AArch64::FCVTMSv2f64:
25994
    case AArch64::FCVTMSv4f16:
25995
    case AArch64::FCVTMSv4f32:
25996
    case AArch64::FCVTMSv8f16:
25997
    case AArch64::FCVTMUUWDr:
25998
    case AArch64::FCVTMUUWHr:
25999
    case AArch64::FCVTMUUWSr:
26000
    case AArch64::FCVTMUUXDr:
26001
    case AArch64::FCVTMUUXHr:
26002
    case AArch64::FCVTMUUXSr:
26003
    case AArch64::FCVTMUv1f16:
26004
    case AArch64::FCVTMUv1i32:
26005
    case AArch64::FCVTMUv1i64:
26006
    case AArch64::FCVTMUv2f32:
26007
    case AArch64::FCVTMUv2f64:
26008
    case AArch64::FCVTMUv4f16:
26009
    case AArch64::FCVTMUv4f32:
26010
    case AArch64::FCVTMUv8f16:
26011
    case AArch64::FCVTNSUWDr:
26012
    case AArch64::FCVTNSUWHr:
26013
    case AArch64::FCVTNSUWSr:
26014
    case AArch64::FCVTNSUXDr:
26015
    case AArch64::FCVTNSUXHr:
26016
    case AArch64::FCVTNSUXSr:
26017
    case AArch64::FCVTNSv1f16:
26018
    case AArch64::FCVTNSv1i32:
26019
    case AArch64::FCVTNSv1i64:
26020
    case AArch64::FCVTNSv2f32:
26021
    case AArch64::FCVTNSv2f64:
26022
    case AArch64::FCVTNSv4f16:
26023
    case AArch64::FCVTNSv4f32:
26024
    case AArch64::FCVTNSv8f16:
26025
    case AArch64::FCVTNUUWDr:
26026
    case AArch64::FCVTNUUWHr:
26027
    case AArch64::FCVTNUUWSr:
26028
    case AArch64::FCVTNUUXDr:
26029
    case AArch64::FCVTNUUXHr:
26030
    case AArch64::FCVTNUUXSr:
26031
    case AArch64::FCVTNUv1f16:
26032
    case AArch64::FCVTNUv1i32:
26033
    case AArch64::FCVTNUv1i64:
26034
    case AArch64::FCVTNUv2f32:
26035
    case AArch64::FCVTNUv2f64:
26036
    case AArch64::FCVTNUv4f16:
26037
    case AArch64::FCVTNUv4f32:
26038
    case AArch64::FCVTNUv8f16:
26039
    case AArch64::FCVTNv2i32:
26040
    case AArch64::FCVTNv4i16:
26041
    case AArch64::FCVTPSUWDr:
26042
    case AArch64::FCVTPSUWHr:
26043
    case AArch64::FCVTPSUWSr:
26044
    case AArch64::FCVTPSUXDr:
26045
    case AArch64::FCVTPSUXHr:
26046
    case AArch64::FCVTPSUXSr:
26047
    case AArch64::FCVTPSv1f16:
26048
    case AArch64::FCVTPSv1i32:
26049
    case AArch64::FCVTPSv1i64:
26050
    case AArch64::FCVTPSv2f32:
26051
    case AArch64::FCVTPSv2f64:
26052
    case AArch64::FCVTPSv4f16:
26053
    case AArch64::FCVTPSv4f32:
26054
    case AArch64::FCVTPSv8f16:
26055
    case AArch64::FCVTPUUWDr:
26056
    case AArch64::FCVTPUUWHr:
26057
    case AArch64::FCVTPUUWSr:
26058
    case AArch64::FCVTPUUXDr:
26059
    case AArch64::FCVTPUUXHr:
26060
    case AArch64::FCVTPUUXSr:
26061
    case AArch64::FCVTPUv1f16:
26062
    case AArch64::FCVTPUv1i32:
26063
    case AArch64::FCVTPUv1i64:
26064
    case AArch64::FCVTPUv2f32:
26065
    case AArch64::FCVTPUv2f64:
26066
    case AArch64::FCVTPUv4f16:
26067
    case AArch64::FCVTPUv4f32:
26068
    case AArch64::FCVTPUv8f16:
26069
    case AArch64::FCVTSDr:
26070
    case AArch64::FCVTSHr:
26071
    case AArch64::FCVTXNv1i64:
26072
    case AArch64::FCVTXNv2f32:
26073
    case AArch64::FCVTZSUWDr:
26074
    case AArch64::FCVTZSUWHr:
26075
    case AArch64::FCVTZSUWSr:
26076
    case AArch64::FCVTZSUXDr:
26077
    case AArch64::FCVTZSUXHr:
26078
    case AArch64::FCVTZSUXSr:
26079
    case AArch64::FCVTZSv1f16:
26080
    case AArch64::FCVTZSv1i32:
26081
    case AArch64::FCVTZSv1i64:
26082
    case AArch64::FCVTZSv2f32:
26083
    case AArch64::FCVTZSv2f64:
26084
    case AArch64::FCVTZSv4f16:
26085
    case AArch64::FCVTZSv4f32:
26086
    case AArch64::FCVTZSv8f16:
26087
    case AArch64::FCVTZUUWDr:
26088
    case AArch64::FCVTZUUWHr:
26089
    case AArch64::FCVTZUUWSr:
26090
    case AArch64::FCVTZUUXDr:
26091
    case AArch64::FCVTZUUXHr:
26092
    case AArch64::FCVTZUUXSr:
26093
    case AArch64::FCVTZUv1f16:
26094
    case AArch64::FCVTZUv1i32:
26095
    case AArch64::FCVTZUv1i64:
26096
    case AArch64::FCVTZUv2f32:
26097
    case AArch64::FCVTZUv2f64:
26098
    case AArch64::FCVTZUv4f16:
26099
    case AArch64::FCVTZUv4f32:
26100
    case AArch64::FCVTZUv8f16:
26101
    case AArch64::FJCVTZS:
26102
    case AArch64::FMAXNMPv2i16p:
26103
    case AArch64::FMAXNMPv2i32p:
26104
    case AArch64::FMAXNMPv2i64p:
26105
    case AArch64::FMAXNMVv4i16v:
26106
    case AArch64::FMAXNMVv4i32v:
26107
    case AArch64::FMAXNMVv8i16v:
26108
    case AArch64::FMAXPv2i16p:
26109
    case AArch64::FMAXPv2i32p:
26110
    case AArch64::FMAXPv2i64p:
26111
    case AArch64::FMAXVv4i16v:
26112
    case AArch64::FMAXVv4i32v:
26113
    case AArch64::FMAXVv8i16v:
26114
    case AArch64::FMINNMPv2i16p:
26115
    case AArch64::FMINNMPv2i32p:
26116
    case AArch64::FMINNMPv2i64p:
26117
    case AArch64::FMINNMVv4i16v:
26118
    case AArch64::FMINNMVv4i32v:
26119
    case AArch64::FMINNMVv8i16v:
26120
    case AArch64::FMINPv2i16p:
26121
    case AArch64::FMINPv2i32p:
26122
    case AArch64::FMINPv2i64p:
26123
    case AArch64::FMINVv4i16v:
26124
    case AArch64::FMINVv4i32v:
26125
    case AArch64::FMINVv8i16v:
26126
    case AArch64::FMOVDXHighr:
26127
    case AArch64::FMOVDXr:
26128
    case AArch64::FMOVDr:
26129
    case AArch64::FMOVHWr:
26130
    case AArch64::FMOVHXr:
26131
    case AArch64::FMOVHr:
26132
    case AArch64::FMOVSWr:
26133
    case AArch64::FMOVSr:
26134
    case AArch64::FMOVWHr:
26135
    case AArch64::FMOVWSr:
26136
    case AArch64::FMOVXDHighr:
26137
    case AArch64::FMOVXDr:
26138
    case AArch64::FMOVXHr:
26139
    case AArch64::FNEGDr:
26140
    case AArch64::FNEGHr:
26141
    case AArch64::FNEGSr:
26142
    case AArch64::FNEGv2f32:
26143
    case AArch64::FNEGv2f64:
26144
    case AArch64::FNEGv4f16:
26145
    case AArch64::FNEGv4f32:
26146
    case AArch64::FNEGv8f16:
26147
    case AArch64::FRECPEv1f16:
26148
    case AArch64::FRECPEv1i32:
26149
    case AArch64::FRECPEv1i64:
26150
    case AArch64::FRECPEv2f32:
26151
    case AArch64::FRECPEv2f64:
26152
    case AArch64::FRECPEv4f16:
26153
    case AArch64::FRECPEv4f32:
26154
    case AArch64::FRECPEv8f16:
26155
    case AArch64::FRECPXv1f16:
26156
    case AArch64::FRECPXv1i32:
26157
    case AArch64::FRECPXv1i64:
26158
    case AArch64::FRINT32XDr:
26159
    case AArch64::FRINT32XSr:
26160
    case AArch64::FRINT32Xv2f32:
26161
    case AArch64::FRINT32Xv2f64:
26162
    case AArch64::FRINT32Xv4f32:
26163
    case AArch64::FRINT32ZDr:
26164
    case AArch64::FRINT32ZSr:
26165
    case AArch64::FRINT32Zv2f32:
26166
    case AArch64::FRINT32Zv2f64:
26167
    case AArch64::FRINT32Zv4f32:
26168
    case AArch64::FRINT64XDr:
26169
    case AArch64::FRINT64XSr:
26170
    case AArch64::FRINT64Xv2f32:
26171
    case AArch64::FRINT64Xv2f64:
26172
    case AArch64::FRINT64Xv4f32:
26173
    case AArch64::FRINT64ZDr:
26174
    case AArch64::FRINT64ZSr:
26175
    case AArch64::FRINT64Zv2f32:
26176
    case AArch64::FRINT64Zv2f64:
26177
    case AArch64::FRINT64Zv4f32:
26178
    case AArch64::FRINTADr:
26179
    case AArch64::FRINTAHr:
26180
    case AArch64::FRINTASr:
26181
    case AArch64::FRINTAv2f32:
26182
    case AArch64::FRINTAv2f64:
26183
    case AArch64::FRINTAv4f16:
26184
    case AArch64::FRINTAv4f32:
26185
    case AArch64::FRINTAv8f16:
26186
    case AArch64::FRINTIDr:
26187
    case AArch64::FRINTIHr:
26188
    case AArch64::FRINTISr:
26189
    case AArch64::FRINTIv2f32:
26190
    case AArch64::FRINTIv2f64:
26191
    case AArch64::FRINTIv4f16:
26192
    case AArch64::FRINTIv4f32:
26193
    case AArch64::FRINTIv8f16:
26194
    case AArch64::FRINTMDr:
26195
    case AArch64::FRINTMHr:
26196
    case AArch64::FRINTMSr:
26197
    case AArch64::FRINTMv2f32:
26198
    case AArch64::FRINTMv2f64:
26199
    case AArch64::FRINTMv4f16:
26200
    case AArch64::FRINTMv4f32:
26201
    case AArch64::FRINTMv8f16:
26202
    case AArch64::FRINTNDr:
26203
    case AArch64::FRINTNHr:
26204
    case AArch64::FRINTNSr:
26205
    case AArch64::FRINTNv2f32:
26206
    case AArch64::FRINTNv2f64:
26207
    case AArch64::FRINTNv4f16:
26208
    case AArch64::FRINTNv4f32:
26209
    case AArch64::FRINTNv8f16:
26210
    case AArch64::FRINTPDr:
26211
    case AArch64::FRINTPHr:
26212
    case AArch64::FRINTPSr:
26213
    case AArch64::FRINTPv2f32:
26214
    case AArch64::FRINTPv2f64:
26215
    case AArch64::FRINTPv4f16:
26216
    case AArch64::FRINTPv4f32:
26217
    case AArch64::FRINTPv8f16:
26218
    case AArch64::FRINTXDr:
26219
    case AArch64::FRINTXHr:
26220
    case AArch64::FRINTXSr:
26221
    case AArch64::FRINTXv2f32:
26222
    case AArch64::FRINTXv2f64:
26223
    case AArch64::FRINTXv4f16:
26224
    case AArch64::FRINTXv4f32:
26225
    case AArch64::FRINTXv8f16:
26226
    case AArch64::FRINTZDr:
26227
    case AArch64::FRINTZHr:
26228
    case AArch64::FRINTZSr:
26229
    case AArch64::FRINTZv2f32:
26230
    case AArch64::FRINTZv2f64:
26231
    case AArch64::FRINTZv4f16:
26232
    case AArch64::FRINTZv4f32:
26233
    case AArch64::FRINTZv8f16:
26234
    case AArch64::FRSQRTEv1f16:
26235
    case AArch64::FRSQRTEv1i32:
26236
    case AArch64::FRSQRTEv1i64:
26237
    case AArch64::FRSQRTEv2f32:
26238
    case AArch64::FRSQRTEv2f64:
26239
    case AArch64::FRSQRTEv4f16:
26240
    case AArch64::FRSQRTEv4f32:
26241
    case AArch64::FRSQRTEv8f16:
26242
    case AArch64::FSQRTDr:
26243
    case AArch64::FSQRTHr:
26244
    case AArch64::FSQRTSr:
26245
    case AArch64::FSQRTv2f32:
26246
    case AArch64::FSQRTv2f64:
26247
    case AArch64::FSQRTv4f16:
26248
    case AArch64::FSQRTv4f32:
26249
    case AArch64::FSQRTv8f16:
26250
    case AArch64::NEGv1i64:
26251
    case AArch64::NEGv2i32:
26252
    case AArch64::NEGv2i64:
26253
    case AArch64::NEGv4i16:
26254
    case AArch64::NEGv4i32:
26255
    case AArch64::NEGv8i8:
26256
    case AArch64::NEGv8i16:
26257
    case AArch64::NEGv16i8:
26258
    case AArch64::NOTv8i8:
26259
    case AArch64::NOTv16i8:
26260
    case AArch64::RBITWr:
26261
    case AArch64::RBITXr:
26262
    case AArch64::RBITv8i8:
26263
    case AArch64::RBITv16i8:
26264
    case AArch64::REV16Wr:
26265
    case AArch64::REV16Xr:
26266
    case AArch64::REV16v8i8:
26267
    case AArch64::REV16v16i8:
26268
    case AArch64::REV32Xr:
26269
    case AArch64::REV32v4i16:
26270
    case AArch64::REV32v8i8:
26271
    case AArch64::REV32v8i16:
26272
    case AArch64::REV32v16i8:
26273
    case AArch64::REV64v2i32:
26274
    case AArch64::REV64v4i16:
26275
    case AArch64::REV64v4i32:
26276
    case AArch64::REV64v8i8:
26277
    case AArch64::REV64v8i16:
26278
    case AArch64::REV64v16i8:
26279
    case AArch64::REVWr:
26280
    case AArch64::REVXr:
26281
    case AArch64::SADDLPv2i32_v1i64:
26282
    case AArch64::SADDLPv4i16_v2i32:
26283
    case AArch64::SADDLPv4i32_v2i64:
26284
    case AArch64::SADDLPv8i8_v4i16:
26285
    case AArch64::SADDLPv8i16_v4i32:
26286
    case AArch64::SADDLPv16i8_v8i16:
26287
    case AArch64::SADDLVv4i16v:
26288
    case AArch64::SADDLVv4i32v:
26289
    case AArch64::SADDLVv8i8v:
26290
    case AArch64::SADDLVv8i16v:
26291
    case AArch64::SADDLVv16i8v:
26292
    case AArch64::SCVTFUWDri:
26293
    case AArch64::SCVTFUWHri:
26294
    case AArch64::SCVTFUWSri:
26295
    case AArch64::SCVTFUXDri:
26296
    case AArch64::SCVTFUXHri:
26297
    case AArch64::SCVTFUXSri:
26298
    case AArch64::SCVTFv1i16:
26299
    case AArch64::SCVTFv1i32:
26300
    case AArch64::SCVTFv1i64:
26301
    case AArch64::SCVTFv2f32:
26302
    case AArch64::SCVTFv2f64:
26303
    case AArch64::SCVTFv4f16:
26304
    case AArch64::SCVTFv4f32:
26305
    case AArch64::SCVTFv8f16:
26306
    case AArch64::SHA1Hrr:
26307
    case AArch64::SHLLv2i32:
26308
    case AArch64::SHLLv4i16:
26309
    case AArch64::SHLLv4i32:
26310
    case AArch64::SHLLv8i8:
26311
    case AArch64::SHLLv8i16:
26312
    case AArch64::SHLLv16i8:
26313
    case AArch64::SMAXVv4i16v:
26314
    case AArch64::SMAXVv4i32v:
26315
    case AArch64::SMAXVv8i8v:
26316
    case AArch64::SMAXVv8i16v:
26317
    case AArch64::SMAXVv16i8v:
26318
    case AArch64::SMINVv4i16v:
26319
    case AArch64::SMINVv4i32v:
26320
    case AArch64::SMINVv8i8v:
26321
    case AArch64::SMINVv8i16v:
26322
    case AArch64::SMINVv16i8v:
26323
    case AArch64::SMOVvi8to32_idx0:
26324
    case AArch64::SMOVvi8to64_idx0:
26325
    case AArch64::SMOVvi16to32_idx0:
26326
    case AArch64::SMOVvi16to64_idx0:
26327
    case AArch64::SMOVvi32to64_idx0:
26328
    case AArch64::SQABSv1i8:
26329
    case AArch64::SQABSv1i16:
26330
    case AArch64::SQABSv1i32:
26331
    case AArch64::SQABSv1i64:
26332
    case AArch64::SQABSv2i32:
26333
    case AArch64::SQABSv2i64:
26334
    case AArch64::SQABSv4i16:
26335
    case AArch64::SQABSv4i32:
26336
    case AArch64::SQABSv8i8:
26337
    case AArch64::SQABSv8i16:
26338
    case AArch64::SQABSv16i8:
26339
    case AArch64::SQNEGv1i8:
26340
    case AArch64::SQNEGv1i16:
26341
    case AArch64::SQNEGv1i32:
26342
    case AArch64::SQNEGv1i64:
26343
    case AArch64::SQNEGv2i32:
26344
    case AArch64::SQNEGv2i64:
26345
    case AArch64::SQNEGv4i16:
26346
    case AArch64::SQNEGv4i32:
26347
    case AArch64::SQNEGv8i8:
26348
    case AArch64::SQNEGv8i16:
26349
    case AArch64::SQNEGv16i8:
26350
    case AArch64::SQXTNv1i8:
26351
    case AArch64::SQXTNv1i16:
26352
    case AArch64::SQXTNv1i32:
26353
    case AArch64::SQXTNv2i32:
26354
    case AArch64::SQXTNv4i16:
26355
    case AArch64::SQXTNv8i8:
26356
    case AArch64::SQXTUNv1i8:
26357
    case AArch64::SQXTUNv1i16:
26358
    case AArch64::SQXTUNv1i32:
26359
    case AArch64::SQXTUNv2i32:
26360
    case AArch64::SQXTUNv4i16:
26361
    case AArch64::SQXTUNv8i8:
26362
    case AArch64::UADDLPv2i32_v1i64:
26363
    case AArch64::UADDLPv4i16_v2i32:
26364
    case AArch64::UADDLPv4i32_v2i64:
26365
    case AArch64::UADDLPv8i8_v4i16:
26366
    case AArch64::UADDLPv8i16_v4i32:
26367
    case AArch64::UADDLPv16i8_v8i16:
26368
    case AArch64::UADDLVv4i16v:
26369
    case AArch64::UADDLVv4i32v:
26370
    case AArch64::UADDLVv8i8v:
26371
    case AArch64::UADDLVv8i16v:
26372
    case AArch64::UADDLVv16i8v:
26373
    case AArch64::UCVTFUWDri:
26374
    case AArch64::UCVTFUWHri:
26375
    case AArch64::UCVTFUWSri:
26376
    case AArch64::UCVTFUXDri:
26377
    case AArch64::UCVTFUXHri:
26378
    case AArch64::UCVTFUXSri:
26379
    case AArch64::UCVTFv1i16:
26380
    case AArch64::UCVTFv1i32:
26381
    case AArch64::UCVTFv1i64:
26382
    case AArch64::UCVTFv2f32:
26383
    case AArch64::UCVTFv2f64:
26384
    case AArch64::UCVTFv4f16:
26385
    case AArch64::UCVTFv4f32:
26386
    case AArch64::UCVTFv8f16:
26387
    case AArch64::UMAXVv4i16v:
26388
    case AArch64::UMAXVv4i32v:
26389
    case AArch64::UMAXVv8i8v:
26390
    case AArch64::UMAXVv8i16v:
26391
    case AArch64::UMAXVv16i8v:
26392
    case AArch64::UMINVv4i16v:
26393
    case AArch64::UMINVv4i32v:
26394
    case AArch64::UMINVv8i8v:
26395
    case AArch64::UMINVv8i16v:
26396
    case AArch64::UMINVv16i8v:
26397
    case AArch64::UMOVvi8_idx0:
26398
    case AArch64::UMOVvi16_idx0:
26399
    case AArch64::UMOVvi32_idx0:
26400
    case AArch64::UMOVvi64_idx0:
26401
    case AArch64::UQXTNv1i8:
26402
    case AArch64::UQXTNv1i16:
26403
    case AArch64::UQXTNv1i32:
26404
    case AArch64::UQXTNv2i32:
26405
    case AArch64::UQXTNv4i16:
26406
    case AArch64::UQXTNv8i8:
26407
    case AArch64::URECPEv2i32:
26408
    case AArch64::URECPEv4i32:
26409
    case AArch64::URSQRTEv2i32:
26410
    case AArch64::URSQRTEv4i32:
26411
    case AArch64::XTNv2i32:
26412
    case AArch64::XTNv4i16:
26413
    case AArch64::XTNv8i8: {
26414
      switch (OpNum) {
26415
      case 0:
26416
        // op: Rd
26417
        return 0;
26418
      case 1:
26419
        // op: Rn
26420
        return 5;
26421
      }
26422
      break;
26423
    }
26424
    case AArch64::FMOVDi:
26425
    case AArch64::FMOVHi:
26426
    case AArch64::FMOVSi: {
26427
      switch (OpNum) {
26428
      case 0:
26429
        // op: Rd
26430
        return 0;
26431
      case 1:
26432
        // op: imm
26433
        return 13;
26434
      }
26435
      break;
26436
    }
26437
    case AArch64::MOVNWi:
26438
    case AArch64::MOVNXi:
26439
    case AArch64::MOVZWi:
26440
    case AArch64::MOVZXi: {
26441
      switch (OpNum) {
26442
      case 0:
26443
        // op: Rd
26444
        return 0;
26445
      case 1:
26446
        // op: imm
26447
        return 5;
26448
      case 2:
26449
        // op: shift
26450
        return 21;
26451
      }
26452
      break;
26453
    }
26454
    case AArch64::RDSVLI_XI:
26455
    case AArch64::RDVLI_XI: {
26456
      switch (OpNum) {
26457
      case 0:
26458
        // op: Rd
26459
        return 0;
26460
      case 1:
26461
        // op: imm6
26462
        return 5;
26463
      }
26464
      break;
26465
    }
26466
    case AArch64::MOVIv2s_msl:
26467
    case AArch64::MOVIv4s_msl:
26468
    case AArch64::MVNIv2s_msl:
26469
    case AArch64::MVNIv4s_msl: {
26470
      switch (OpNum) {
26471
      case 0:
26472
        // op: Rd
26473
        return 0;
26474
      case 1:
26475
        // op: imm8
26476
        return 5;
26477
      case 2:
26478
        // op: shift
26479
        return 12;
26480
      }
26481
      break;
26482
    }
26483
    case AArch64::MOVIv2i32:
26484
    case AArch64::MOVIv4i16:
26485
    case AArch64::MOVIv4i32:
26486
    case AArch64::MOVIv8i16:
26487
    case AArch64::MVNIv2i32:
26488
    case AArch64::MVNIv4i16:
26489
    case AArch64::MVNIv4i32:
26490
    case AArch64::MVNIv8i16: {
26491
      switch (OpNum) {
26492
      case 0:
26493
        // op: Rd
26494
        return 0;
26495
      case 1:
26496
        // op: imm8
26497
        return 5;
26498
      case 2:
26499
        // op: shift
26500
        return 13;
26501
      }
26502
      break;
26503
    }
26504
    case AArch64::FMOVv2f32_ns:
26505
    case AArch64::FMOVv2f64_ns:
26506
    case AArch64::FMOVv4f16_ns:
26507
    case AArch64::FMOVv4f32_ns:
26508
    case AArch64::FMOVv8f16_ns:
26509
    case AArch64::MOVID:
26510
    case AArch64::MOVIv2d_ns:
26511
    case AArch64::MOVIv8b_ns:
26512
    case AArch64::MOVIv16b_ns: {
26513
      switch (OpNum) {
26514
      case 0:
26515
        // op: Rd
26516
        return 0;
26517
      case 1:
26518
        // op: imm8
26519
        return 5;
26520
      }
26521
      break;
26522
    }
26523
    case AArch64::BFMWri:
26524
    case AArch64::BFMXri: {
26525
      switch (OpNum) {
26526
      case 0:
26527
        // op: Rd
26528
        return 0;
26529
      case 2:
26530
        // op: Rn
26531
        return 5;
26532
      case 3:
26533
        // op: immr
26534
        return 16;
26535
      case 4:
26536
        // op: imms
26537
        return 10;
26538
      }
26539
      break;
26540
    }
26541
    case AArch64::MOVKWi:
26542
    case AArch64::MOVKXi: {
26543
      switch (OpNum) {
26544
      case 0:
26545
        // op: Rd
26546
        return 0;
26547
      case 2:
26548
        // op: imm
26549
        return 5;
26550
      case 3:
26551
        // op: shift
26552
        return 21;
26553
      }
26554
      break;
26555
    }
26556
    case AArch64::CNTB_XPiI:
26557
    case AArch64::CNTD_XPiI:
26558
    case AArch64::CNTH_XPiI:
26559
    case AArch64::CNTW_XPiI: {
26560
      switch (OpNum) {
26561
      case 0:
26562
        // op: Rd
26563
        return 0;
26564
      case 2:
26565
        // op: imm4
26566
        return 16;
26567
      case 1:
26568
        // op: pattern
26569
        return 5;
26570
      }
26571
      break;
26572
    }
26573
    case AArch64::XPACD:
26574
    case AArch64::XPACI: {
26575
      switch (OpNum) {
26576
      case 0:
26577
        // op: Rd
26578
        return 0;
26579
      }
26580
      break;
26581
    }
26582
    case AArch64::DECP_XP_B:
26583
    case AArch64::DECP_XP_D:
26584
    case AArch64::DECP_XP_H:
26585
    case AArch64::DECP_XP_S:
26586
    case AArch64::INCP_XP_B:
26587
    case AArch64::INCP_XP_D:
26588
    case AArch64::INCP_XP_H:
26589
    case AArch64::INCP_XP_S:
26590
    case AArch64::SQDECP_XPWd_B:
26591
    case AArch64::SQDECP_XPWd_D:
26592
    case AArch64::SQDECP_XPWd_H:
26593
    case AArch64::SQDECP_XPWd_S:
26594
    case AArch64::SQDECP_XP_B:
26595
    case AArch64::SQDECP_XP_D:
26596
    case AArch64::SQDECP_XP_H:
26597
    case AArch64::SQDECP_XP_S:
26598
    case AArch64::SQINCP_XPWd_B:
26599
    case AArch64::SQINCP_XPWd_D:
26600
    case AArch64::SQINCP_XPWd_H:
26601
    case AArch64::SQINCP_XPWd_S:
26602
    case AArch64::SQINCP_XP_B:
26603
    case AArch64::SQINCP_XP_D:
26604
    case AArch64::SQINCP_XP_H:
26605
    case AArch64::SQINCP_XP_S:
26606
    case AArch64::UQDECP_WP_B:
26607
    case AArch64::UQDECP_WP_D:
26608
    case AArch64::UQDECP_WP_H:
26609
    case AArch64::UQDECP_WP_S:
26610
    case AArch64::UQDECP_XP_B:
26611
    case AArch64::UQDECP_XP_D:
26612
    case AArch64::UQDECP_XP_H:
26613
    case AArch64::UQDECP_XP_S:
26614
    case AArch64::UQINCP_WP_B:
26615
    case AArch64::UQINCP_WP_D:
26616
    case AArch64::UQINCP_WP_H:
26617
    case AArch64::UQINCP_WP_S:
26618
    case AArch64::UQINCP_XP_B:
26619
    case AArch64::UQINCP_XP_D:
26620
    case AArch64::UQINCP_XP_H:
26621
    case AArch64::UQINCP_XP_S: {
26622
      switch (OpNum) {
26623
      case 0:
26624
        // op: Rdn
26625
        return 0;
26626
      case 1:
26627
        // op: Pg
26628
        return 5;
26629
      }
26630
      break;
26631
    }
26632
    case AArch64::DECB_XPiI:
26633
    case AArch64::DECD_XPiI:
26634
    case AArch64::DECH_XPiI:
26635
    case AArch64::DECW_XPiI:
26636
    case AArch64::INCB_XPiI:
26637
    case AArch64::INCD_XPiI:
26638
    case AArch64::INCH_XPiI:
26639
    case AArch64::INCW_XPiI:
26640
    case AArch64::SQDECB_XPiI:
26641
    case AArch64::SQDECB_XPiWdI:
26642
    case AArch64::SQDECD_XPiI:
26643
    case AArch64::SQDECD_XPiWdI:
26644
    case AArch64::SQDECH_XPiI:
26645
    case AArch64::SQDECH_XPiWdI:
26646
    case AArch64::SQDECW_XPiI:
26647
    case AArch64::SQDECW_XPiWdI:
26648
    case AArch64::SQINCB_XPiI:
26649
    case AArch64::SQINCB_XPiWdI:
26650
    case AArch64::SQINCD_XPiI:
26651
    case AArch64::SQINCD_XPiWdI:
26652
    case AArch64::SQINCH_XPiI:
26653
    case AArch64::SQINCH_XPiWdI:
26654
    case AArch64::SQINCW_XPiI:
26655
    case AArch64::SQINCW_XPiWdI:
26656
    case AArch64::UQDECB_WPiI:
26657
    case AArch64::UQDECB_XPiI:
26658
    case AArch64::UQDECD_WPiI:
26659
    case AArch64::UQDECD_XPiI:
26660
    case AArch64::UQDECH_WPiI:
26661
    case AArch64::UQDECH_XPiI:
26662
    case AArch64::UQDECW_WPiI:
26663
    case AArch64::UQDECW_XPiI:
26664
    case AArch64::UQINCB_WPiI:
26665
    case AArch64::UQINCB_XPiI:
26666
    case AArch64::UQINCD_WPiI:
26667
    case AArch64::UQINCD_XPiI:
26668
    case AArch64::UQINCH_WPiI:
26669
    case AArch64::UQINCH_XPiI:
26670
    case AArch64::UQINCW_WPiI:
26671
    case AArch64::UQINCW_XPiI: {
26672
      switch (OpNum) {
26673
      case 0:
26674
        // op: Rdn
26675
        return 0;
26676
      case 2:
26677
        // op: pattern
26678
        return 5;
26679
      case 3:
26680
        // op: imm4
26681
        return 16;
26682
      }
26683
      break;
26684
    }
26685
    case AArch64::RETAASPPCr:
26686
    case AArch64::RETABSPPCr: {
26687
      switch (OpNum) {
26688
      case 0:
26689
        // op: Rm
26690
        return 0;
26691
      }
26692
      break;
26693
    }
26694
    case AArch64::BLRAA:
26695
    case AArch64::BLRAB:
26696
    case AArch64::BRAA:
26697
    case AArch64::BRAB: {
26698
      switch (OpNum) {
26699
      case 0:
26700
        // op: Rn
26701
        return 5;
26702
      case 1:
26703
        // op: Rm
26704
        return 0;
26705
      }
26706
      break;
26707
    }
26708
    case AArch64::CCMNWr:
26709
    case AArch64::CCMNXr:
26710
    case AArch64::CCMPWr:
26711
    case AArch64::CCMPXr:
26712
    case AArch64::FCCMPDrr:
26713
    case AArch64::FCCMPEDrr:
26714
    case AArch64::FCCMPEHrr:
26715
    case AArch64::FCCMPESrr:
26716
    case AArch64::FCCMPHrr:
26717
    case AArch64::FCCMPSrr: {
26718
      switch (OpNum) {
26719
      case 0:
26720
        // op: Rn
26721
        return 5;
26722
      case 1:
26723
        // op: Rm
26724
        return 16;
26725
      case 2:
26726
        // op: nzcv
26727
        return 0;
26728
      case 3:
26729
        // op: cond
26730
        return 12;
26731
      }
26732
      break;
26733
    }
26734
    case AArch64::RMIF: {
26735
      switch (OpNum) {
26736
      case 0:
26737
        // op: Rn
26738
        return 5;
26739
      case 1:
26740
        // op: imm
26741
        return 15;
26742
      case 2:
26743
        // op: mask
26744
        return 0;
26745
      }
26746
      break;
26747
    }
26748
    case AArch64::CCMNWi:
26749
    case AArch64::CCMNXi:
26750
    case AArch64::CCMPWi:
26751
    case AArch64::CCMPXi: {
26752
      switch (OpNum) {
26753
      case 0:
26754
        // op: Rn
26755
        return 5;
26756
      case 1:
26757
        // op: imm
26758
        return 16;
26759
      case 2:
26760
        // op: nzcv
26761
        return 0;
26762
      case 3:
26763
        // op: cond
26764
        return 12;
26765
      }
26766
      break;
26767
    }
26768
    case AArch64::AUTIASPPCr:
26769
    case AArch64::AUTIBSPPCr:
26770
    case AArch64::BLR:
26771
    case AArch64::BLRAAZ:
26772
    case AArch64::BLRABZ:
26773
    case AArch64::BR:
26774
    case AArch64::BRAAZ:
26775
    case AArch64::BRABZ:
26776
    case AArch64::FCMPDri:
26777
    case AArch64::FCMPEDri:
26778
    case AArch64::FCMPEHri:
26779
    case AArch64::FCMPESri:
26780
    case AArch64::FCMPHri:
26781
    case AArch64::FCMPSri:
26782
    case AArch64::RET:
26783
    case AArch64::SETF8:
26784
    case AArch64::SETF16: {
26785
      switch (OpNum) {
26786
      case 0:
26787
        // op: Rn
26788
        return 5;
26789
      }
26790
      break;
26791
    }
26792
    case AArch64::LDRBBroW:
26793
    case AArch64::LDRBBroX:
26794
    case AArch64::LDRBroW:
26795
    case AArch64::LDRBroX:
26796
    case AArch64::LDRDroW:
26797
    case AArch64::LDRDroX:
26798
    case AArch64::LDRHHroW:
26799
    case AArch64::LDRHHroX:
26800
    case AArch64::LDRHroW:
26801
    case AArch64::LDRHroX:
26802
    case AArch64::LDRQroW:
26803
    case AArch64::LDRQroX:
26804
    case AArch64::LDRSBWroW:
26805
    case AArch64::LDRSBWroX:
26806
    case AArch64::LDRSBXroW:
26807
    case AArch64::LDRSBXroX:
26808
    case AArch64::LDRSHWroW:
26809
    case AArch64::LDRSHWroX:
26810
    case AArch64::LDRSHXroW:
26811
    case AArch64::LDRSHXroX:
26812
    case AArch64::LDRSWroW:
26813
    case AArch64::LDRSWroX:
26814
    case AArch64::LDRSroW:
26815
    case AArch64::LDRSroX:
26816
    case AArch64::LDRWroW:
26817
    case AArch64::LDRWroX:
26818
    case AArch64::LDRXroW:
26819
    case AArch64::LDRXroX:
26820
    case AArch64::PRFMroW:
26821
    case AArch64::PRFMroX:
26822
    case AArch64::STRBBroW:
26823
    case AArch64::STRBBroX:
26824
    case AArch64::STRBroW:
26825
    case AArch64::STRBroX:
26826
    case AArch64::STRDroW:
26827
    case AArch64::STRDroX:
26828
    case AArch64::STRHHroW:
26829
    case AArch64::STRHHroX:
26830
    case AArch64::STRHroW:
26831
    case AArch64::STRHroX:
26832
    case AArch64::STRQroW:
26833
    case AArch64::STRQroX:
26834
    case AArch64::STRSroW:
26835
    case AArch64::STRSroX:
26836
    case AArch64::STRWroW:
26837
    case AArch64::STRWroX:
26838
    case AArch64::STRXroW:
26839
    case AArch64::STRXroX: {
26840
      switch (OpNum) {
26841
      case 0:
26842
        // op: Rt
26843
        return 0;
26844
      case 1:
26845
        // op: Rn
26846
        return 5;
26847
      case 2:
26848
        // op: Rm
26849
        return 16;
26850
      case 3:
26851
        // op: extend
26852
        return 12;
26853
      }
26854
      break;
26855
    }
26856
    case AArch64::LDRBBui:
26857
    case AArch64::LDRBui:
26858
    case AArch64::LDRDui:
26859
    case AArch64::LDRHHui:
26860
    case AArch64::LDRHui:
26861
    case AArch64::LDRQui:
26862
    case AArch64::LDRSBWui:
26863
    case AArch64::LDRSBXui:
26864
    case AArch64::LDRSHWui:
26865
    case AArch64::LDRSHXui:
26866
    case AArch64::LDRSWui:
26867
    case AArch64::LDRSui:
26868
    case AArch64::LDRWui:
26869
    case AArch64::LDRXui:
26870
    case AArch64::PRFMui:
26871
    case AArch64::STRBBui:
26872
    case AArch64::STRBui:
26873
    case AArch64::STRDui:
26874
    case AArch64::STRHHui:
26875
    case AArch64::STRHui:
26876
    case AArch64::STRQui:
26877
    case AArch64::STRSui:
26878
    case AArch64::STRWui:
26879
    case AArch64::STRXui: {
26880
      switch (OpNum) {
26881
      case 0:
26882
        // op: Rt
26883
        return 0;
26884
      case 1:
26885
        // op: Rn
26886
        return 5;
26887
      case 2:
26888
        // op: offset
26889
        return 10;
26890
      }
26891
      break;
26892
    }
26893
    case AArch64::LDAPURBi:
26894
    case AArch64::LDAPURHi:
26895
    case AArch64::LDAPURSBWi:
26896
    case AArch64::LDAPURSBXi:
26897
    case AArch64::LDAPURSHWi:
26898
    case AArch64::LDAPURSHXi:
26899
    case AArch64::LDAPURSWi:
26900
    case AArch64::LDAPURXi:
26901
    case AArch64::LDAPURi:
26902
    case AArch64::LDTRBi:
26903
    case AArch64::LDTRHi:
26904
    case AArch64::LDTRSBWi:
26905
    case AArch64::LDTRSBXi:
26906
    case AArch64::LDTRSHWi:
26907
    case AArch64::LDTRSHXi:
26908
    case AArch64::LDTRSWi:
26909
    case AArch64::LDTRWi:
26910
    case AArch64::LDTRXi:
26911
    case AArch64::LDURBBi:
26912
    case AArch64::LDURBi:
26913
    case AArch64::LDURDi:
26914
    case AArch64::LDURHHi:
26915
    case AArch64::LDURHi:
26916
    case AArch64::LDURQi:
26917
    case AArch64::LDURSBWi:
26918
    case AArch64::LDURSBXi:
26919
    case AArch64::LDURSHWi:
26920
    case AArch64::LDURSHXi:
26921
    case AArch64::LDURSWi:
26922
    case AArch64::LDURSi:
26923
    case AArch64::LDURWi:
26924
    case AArch64::LDURXi:
26925
    case AArch64::PRFUMi:
26926
    case AArch64::STLURBi:
26927
    case AArch64::STLURHi:
26928
    case AArch64::STLURWi:
26929
    case AArch64::STLURXi:
26930
    case AArch64::STTRBi:
26931
    case AArch64::STTRHi:
26932
    case AArch64::STTRWi:
26933
    case AArch64::STTRXi:
26934
    case AArch64::STURBBi:
26935
    case AArch64::STURBi:
26936
    case AArch64::STURDi:
26937
    case AArch64::STURHHi:
26938
    case AArch64::STURHi:
26939
    case AArch64::STURQi:
26940
    case AArch64::STURSi:
26941
    case AArch64::STURWi:
26942
    case AArch64::STURXi: {
26943
      switch (OpNum) {
26944
      case 0:
26945
        // op: Rt
26946
        return 0;
26947
      case 1:
26948
        // op: Rn
26949
        return 5;
26950
      case 2:
26951
        // op: offset
26952
        return 12;
26953
      }
26954
      break;
26955
    }
26956
    case AArch64::LDAPURbi:
26957
    case AArch64::LDAPURdi:
26958
    case AArch64::LDAPURhi:
26959
    case AArch64::LDAPURqi:
26960
    case AArch64::LDAPURsi:
26961
    case AArch64::STLURbi:
26962
    case AArch64::STLURdi:
26963
    case AArch64::STLURhi:
26964
    case AArch64::STLURqi:
26965
    case AArch64::STLURsi: {
26966
      switch (OpNum) {
26967
      case 0:
26968
        // op: Rt
26969
        return 0;
26970
      case 1:
26971
        // op: Rn
26972
        return 5;
26973
      case 2:
26974
        // op: simm
26975
        return 12;
26976
      }
26977
      break;
26978
    }
26979
    case AArch64::GCSSTR:
26980
    case AArch64::GCSSTTR:
26981
    case AArch64::LD64B:
26982
    case AArch64::LDARB:
26983
    case AArch64::LDARH:
26984
    case AArch64::LDARW:
26985
    case AArch64::LDARX:
26986
    case AArch64::LDAXRB:
26987
    case AArch64::LDAXRH:
26988
    case AArch64::LDAXRW:
26989
    case AArch64::LDAXRX:
26990
    case AArch64::LDLARB:
26991
    case AArch64::LDLARH:
26992
    case AArch64::LDLARW:
26993
    case AArch64::LDLARX:
26994
    case AArch64::LDXRB:
26995
    case AArch64::LDXRH:
26996
    case AArch64::LDXRW:
26997
    case AArch64::LDXRX:
26998
    case AArch64::ST64B:
26999
    case AArch64::STLLRB:
27000
    case AArch64::STLLRH:
27001
    case AArch64::STLLRW:
27002
    case AArch64::STLLRX:
27003
    case AArch64::STLRB:
27004
    case AArch64::STLRH:
27005
    case AArch64::STLRW:
27006
    case AArch64::STLRX: {
27007
      switch (OpNum) {
27008
      case 0:
27009
        // op: Rt
27010
        return 0;
27011
      case 1:
27012
        // op: Rn
27013
        return 5;
27014
      }
27015
      break;
27016
    }
27017
    case AArch64::LDNPDi:
27018
    case AArch64::LDNPQi:
27019
    case AArch64::LDNPSi:
27020
    case AArch64::LDNPWi:
27021
    case AArch64::LDNPXi:
27022
    case AArch64::LDPDi:
27023
    case AArch64::LDPQi:
27024
    case AArch64::LDPSWi:
27025
    case AArch64::LDPSi:
27026
    case AArch64::LDPWi:
27027
    case AArch64::LDPXi:
27028
    case AArch64::STGPi:
27029
    case AArch64::STNPDi:
27030
    case AArch64::STNPQi:
27031
    case AArch64::STNPSi:
27032
    case AArch64::STNPWi:
27033
    case AArch64::STNPXi:
27034
    case AArch64::STPDi:
27035
    case AArch64::STPQi:
27036
    case AArch64::STPSi:
27037
    case AArch64::STPWi:
27038
    case AArch64::STPXi: {
27039
      switch (OpNum) {
27040
      case 0:
27041
        // op: Rt
27042
        return 0;
27043
      case 1:
27044
        // op: Rt2
27045
        return 10;
27046
      case 2:
27047
        // op: Rn
27048
        return 5;
27049
      case 3:
27050
        // op: offset
27051
        return 15;
27052
      }
27053
      break;
27054
    }
27055
    case AArch64::LDAXPW:
27056
    case AArch64::LDAXPX:
27057
    case AArch64::LDXPW:
27058
    case AArch64::LDXPX: {
27059
      switch (OpNum) {
27060
      case 0:
27061
        // op: Rt
27062
        return 0;
27063
      case 1:
27064
        // op: Rt2
27065
        return 10;
27066
      case 2:
27067
        // op: Rn
27068
        return 5;
27069
      }
27070
      break;
27071
    }
27072
    case AArch64::TBNZW:
27073
    case AArch64::TBNZX:
27074
    case AArch64::TBZW:
27075
    case AArch64::TBZX: {
27076
      switch (OpNum) {
27077
      case 0:
27078
        // op: Rt
27079
        return 0;
27080
      case 1:
27081
        // op: bit_off
27082
        return 19;
27083
      case 2:
27084
        // op: target
27085
        return 5;
27086
      }
27087
      break;
27088
    }
27089
    case AArch64::LDRDl:
27090
    case AArch64::LDRQl:
27091
    case AArch64::LDRSWl:
27092
    case AArch64::LDRSl:
27093
    case AArch64::LDRWl:
27094
    case AArch64::LDRXl:
27095
    case AArch64::PRFMl: {
27096
      switch (OpNum) {
27097
      case 0:
27098
        // op: Rt
27099
        return 0;
27100
      case 1:
27101
        // op: label
27102
        return 5;
27103
      }
27104
      break;
27105
    }
27106
    case AArch64::SYSLxt: {
27107
      switch (OpNum) {
27108
      case 0:
27109
        // op: Rt
27110
        return 0;
27111
      case 1:
27112
        // op: op1
27113
        return 16;
27114
      case 2:
27115
        // op: Cn
27116
        return 12;
27117
      case 3:
27118
        // op: Cm
27119
        return 8;
27120
      case 4:
27121
        // op: op2
27122
        return 5;
27123
      }
27124
      break;
27125
    }
27126
    case AArch64::MRRS:
27127
    case AArch64::MRS: {
27128
      switch (OpNum) {
27129
      case 0:
27130
        // op: Rt
27131
        return 0;
27132
      case 1:
27133
        // op: systemreg
27134
        return 5;
27135
      }
27136
      break;
27137
    }
27138
    case AArch64::CBNZW:
27139
    case AArch64::CBNZX:
27140
    case AArch64::CBZW:
27141
    case AArch64::CBZX: {
27142
      switch (OpNum) {
27143
      case 0:
27144
        // op: Rt
27145
        return 0;
27146
      case 1:
27147
        // op: target
27148
        return 5;
27149
      }
27150
      break;
27151
    }
27152
    case AArch64::RPRFM: {
27153
      switch (OpNum) {
27154
      case 0:
27155
        // op: Rt
27156
        return 0;
27157
      case 2:
27158
        // op: Rn
27159
        return 5;
27160
      case 1:
27161
        // op: Rm
27162
        return 16;
27163
      }
27164
      break;
27165
    }
27166
    case AArch64::LDIAPPW:
27167
    case AArch64::LDIAPPX:
27168
    case AArch64::STILPW:
27169
    case AArch64::STILPX: {
27170
      switch (OpNum) {
27171
      case 0:
27172
        // op: Rt
27173
        return 0;
27174
      case 2:
27175
        // op: Rn
27176
        return 5;
27177
      case 1:
27178
        // op: Rt2
27179
        return 16;
27180
      }
27181
      break;
27182
    }
27183
    case AArch64::GCSPOPM:
27184
    case AArch64::GCSPUSHM:
27185
    case AArch64::GCSSS1:
27186
    case AArch64::GCSSS2:
27187
    case AArch64::TRCIT:
27188
    case AArch64::TSTART:
27189
    case AArch64::TTEST:
27190
    case AArch64::WFET:
27191
    case AArch64::WFIT: {
27192
      switch (OpNum) {
27193
      case 0:
27194
        // op: Rt
27195
        return 0;
27196
      }
27197
      break;
27198
    }
27199
    case AArch64::BCAX:
27200
    case AArch64::EOR3:
27201
    case AArch64::SM3SS1: {
27202
      switch (OpNum) {
27203
      case 0:
27204
        // op: Vd
27205
        return 0;
27206
      case 1:
27207
        // op: Vn
27208
        return 5;
27209
      case 2:
27210
        // op: Vm
27211
        return 16;
27212
      case 3:
27213
        // op: Va
27214
        return 10;
27215
      }
27216
      break;
27217
    }
27218
    case AArch64::RAX1:
27219
    case AArch64::SM4ENCKEY:
27220
    case AArch64::TBLv8i8Four:
27221
    case AArch64::TBLv8i8One:
27222
    case AArch64::TBLv8i8Three:
27223
    case AArch64::TBLv8i8Two:
27224
    case AArch64::TBLv16i8Four:
27225
    case AArch64::TBLv16i8One:
27226
    case AArch64::TBLv16i8Three:
27227
    case AArch64::TBLv16i8Two: {
27228
      switch (OpNum) {
27229
      case 0:
27230
        // op: Vd
27231
        return 0;
27232
      case 1:
27233
        // op: Vn
27234
        return 5;
27235
      case 2:
27236
        // op: Vm
27237
        return 16;
27238
      }
27239
      break;
27240
    }
27241
    case AArch64::XAR: {
27242
      switch (OpNum) {
27243
      case 0:
27244
        // op: Vd
27245
        return 0;
27246
      case 1:
27247
        // op: Vn
27248
        return 5;
27249
      case 3:
27250
        // op: imm
27251
        return 10;
27252
      case 2:
27253
        // op: Vm
27254
        return 16;
27255
      }
27256
      break;
27257
    }
27258
    case AArch64::ADDQV_VPZ_B:
27259
    case AArch64::ADDQV_VPZ_D:
27260
    case AArch64::ADDQV_VPZ_H:
27261
    case AArch64::ADDQV_VPZ_S:
27262
    case AArch64::ANDQV_VPZ_B:
27263
    case AArch64::ANDQV_VPZ_D:
27264
    case AArch64::ANDQV_VPZ_H:
27265
    case AArch64::ANDQV_VPZ_S:
27266
    case AArch64::EORQV_VPZ_B:
27267
    case AArch64::EORQV_VPZ_D:
27268
    case AArch64::EORQV_VPZ_H:
27269
    case AArch64::EORQV_VPZ_S:
27270
    case AArch64::FADDQV_D:
27271
    case AArch64::FADDQV_H:
27272
    case AArch64::FADDQV_S:
27273
    case AArch64::FMAXNMQV_D:
27274
    case AArch64::FMAXNMQV_H:
27275
    case AArch64::FMAXNMQV_S:
27276
    case AArch64::FMAXQV_D:
27277
    case AArch64::FMAXQV_H:
27278
    case AArch64::FMAXQV_S:
27279
    case AArch64::FMINNMQV_D:
27280
    case AArch64::FMINNMQV_H:
27281
    case AArch64::FMINNMQV_S:
27282
    case AArch64::FMINQV_D:
27283
    case AArch64::FMINQV_H:
27284
    case AArch64::FMINQV_S:
27285
    case AArch64::ORQV_VPZ_B:
27286
    case AArch64::ORQV_VPZ_D:
27287
    case AArch64::ORQV_VPZ_H:
27288
    case AArch64::ORQV_VPZ_S:
27289
    case AArch64::SMAXQV_VPZ_B:
27290
    case AArch64::SMAXQV_VPZ_D:
27291
    case AArch64::SMAXQV_VPZ_H:
27292
    case AArch64::SMAXQV_VPZ_S:
27293
    case AArch64::SMINQV_VPZ_B:
27294
    case AArch64::SMINQV_VPZ_D:
27295
    case AArch64::SMINQV_VPZ_H:
27296
    case AArch64::SMINQV_VPZ_S:
27297
    case AArch64::UMAXQV_VPZ_B:
27298
    case AArch64::UMAXQV_VPZ_D:
27299
    case AArch64::UMAXQV_VPZ_H:
27300
    case AArch64::UMAXQV_VPZ_S:
27301
    case AArch64::UMINQV_VPZ_B:
27302
    case AArch64::UMINQV_VPZ_D:
27303
    case AArch64::UMINQV_VPZ_H:
27304
    case AArch64::UMINQV_VPZ_S: {
27305
      switch (OpNum) {
27306
      case 0:
27307
        // op: Vd
27308
        return 0;
27309
      case 2:
27310
        // op: Zn
27311
        return 5;
27312
      case 1:
27313
        // op: Pg
27314
        return 10;
27315
      }
27316
      break;
27317
    }
27318
    case AArch64::LD1Fourv1d:
27319
    case AArch64::LD1Fourv2d:
27320
    case AArch64::LD1Fourv2s:
27321
    case AArch64::LD1Fourv4h:
27322
    case AArch64::LD1Fourv4s:
27323
    case AArch64::LD1Fourv8b:
27324
    case AArch64::LD1Fourv8h:
27325
    case AArch64::LD1Fourv16b:
27326
    case AArch64::LD1Onev1d:
27327
    case AArch64::LD1Onev2d:
27328
    case AArch64::LD1Onev2s:
27329
    case AArch64::LD1Onev4h:
27330
    case AArch64::LD1Onev4s:
27331
    case AArch64::LD1Onev8b:
27332
    case AArch64::LD1Onev8h:
27333
    case AArch64::LD1Onev16b:
27334
    case AArch64::LD1Rv1d:
27335
    case AArch64::LD1Rv2d:
27336
    case AArch64::LD1Rv2s:
27337
    case AArch64::LD1Rv4h:
27338
    case AArch64::LD1Rv4s:
27339
    case AArch64::LD1Rv8b:
27340
    case AArch64::LD1Rv8h:
27341
    case AArch64::LD1Rv16b:
27342
    case AArch64::LD1Threev1d:
27343
    case AArch64::LD1Threev2d:
27344
    case AArch64::LD1Threev2s:
27345
    case AArch64::LD1Threev4h:
27346
    case AArch64::LD1Threev4s:
27347
    case AArch64::LD1Threev8b:
27348
    case AArch64::LD1Threev8h:
27349
    case AArch64::LD1Threev16b:
27350
    case AArch64::LD1Twov1d:
27351
    case AArch64::LD1Twov2d:
27352
    case AArch64::LD1Twov2s:
27353
    case AArch64::LD1Twov4h:
27354
    case AArch64::LD1Twov4s:
27355
    case AArch64::LD1Twov8b:
27356
    case AArch64::LD1Twov8h:
27357
    case AArch64::LD1Twov16b:
27358
    case AArch64::LD2Rv1d:
27359
    case AArch64::LD2Rv2d:
27360
    case AArch64::LD2Rv2s:
27361
    case AArch64::LD2Rv4h:
27362
    case AArch64::LD2Rv4s:
27363
    case AArch64::LD2Rv8b:
27364
    case AArch64::LD2Rv8h:
27365
    case AArch64::LD2Rv16b:
27366
    case AArch64::LD2Twov2d:
27367
    case AArch64::LD2Twov2s:
27368
    case AArch64::LD2Twov4h:
27369
    case AArch64::LD2Twov4s:
27370
    case AArch64::LD2Twov8b:
27371
    case AArch64::LD2Twov8h:
27372
    case AArch64::LD2Twov16b:
27373
    case AArch64::LD3Rv1d:
27374
    case AArch64::LD3Rv2d:
27375
    case AArch64::LD3Rv2s:
27376
    case AArch64::LD3Rv4h:
27377
    case AArch64::LD3Rv4s:
27378
    case AArch64::LD3Rv8b:
27379
    case AArch64::LD3Rv8h:
27380
    case AArch64::LD3Rv16b:
27381
    case AArch64::LD3Threev2d:
27382
    case AArch64::LD3Threev2s:
27383
    case AArch64::LD3Threev4h:
27384
    case AArch64::LD3Threev4s:
27385
    case AArch64::LD3Threev8b:
27386
    case AArch64::LD3Threev8h:
27387
    case AArch64::LD3Threev16b:
27388
    case AArch64::LD4Fourv2d:
27389
    case AArch64::LD4Fourv2s:
27390
    case AArch64::LD4Fourv4h:
27391
    case AArch64::LD4Fourv4s:
27392
    case AArch64::LD4Fourv8b:
27393
    case AArch64::LD4Fourv8h:
27394
    case AArch64::LD4Fourv16b:
27395
    case AArch64::LD4Rv1d:
27396
    case AArch64::LD4Rv2d:
27397
    case AArch64::LD4Rv2s:
27398
    case AArch64::LD4Rv4h:
27399
    case AArch64::LD4Rv4s:
27400
    case AArch64::LD4Rv8b:
27401
    case AArch64::LD4Rv8h:
27402
    case AArch64::LD4Rv16b:
27403
    case AArch64::ST1Fourv1d:
27404
    case AArch64::ST1Fourv2d:
27405
    case AArch64::ST1Fourv2s:
27406
    case AArch64::ST1Fourv4h:
27407
    case AArch64::ST1Fourv4s:
27408
    case AArch64::ST1Fourv8b:
27409
    case AArch64::ST1Fourv8h:
27410
    case AArch64::ST1Fourv16b:
27411
    case AArch64::ST1Onev1d:
27412
    case AArch64::ST1Onev2d:
27413
    case AArch64::ST1Onev2s:
27414
    case AArch64::ST1Onev4h:
27415
    case AArch64::ST1Onev4s:
27416
    case AArch64::ST1Onev8b:
27417
    case AArch64::ST1Onev8h:
27418
    case AArch64::ST1Onev16b:
27419
    case AArch64::ST1Threev1d:
27420
    case AArch64::ST1Threev2d:
27421
    case AArch64::ST1Threev2s:
27422
    case AArch64::ST1Threev4h:
27423
    case AArch64::ST1Threev4s:
27424
    case AArch64::ST1Threev8b:
27425
    case AArch64::ST1Threev8h:
27426
    case AArch64::ST1Threev16b:
27427
    case AArch64::ST1Twov1d:
27428
    case AArch64::ST1Twov2d:
27429
    case AArch64::ST1Twov2s:
27430
    case AArch64::ST1Twov4h:
27431
    case AArch64::ST1Twov4s:
27432
    case AArch64::ST1Twov8b:
27433
    case AArch64::ST1Twov8h:
27434
    case AArch64::ST1Twov16b:
27435
    case AArch64::ST2Twov2d:
27436
    case AArch64::ST2Twov2s:
27437
    case AArch64::ST2Twov4h:
27438
    case AArch64::ST2Twov4s:
27439
    case AArch64::ST2Twov8b:
27440
    case AArch64::ST2Twov8h:
27441
    case AArch64::ST2Twov16b:
27442
    case AArch64::ST3Threev2d:
27443
    case AArch64::ST3Threev2s:
27444
    case AArch64::ST3Threev4h:
27445
    case AArch64::ST3Threev4s:
27446
    case AArch64::ST3Threev8b:
27447
    case AArch64::ST3Threev8h:
27448
    case AArch64::ST3Threev16b:
27449
    case AArch64::ST4Fourv2d:
27450
    case AArch64::ST4Fourv2s:
27451
    case AArch64::ST4Fourv4h:
27452
    case AArch64::ST4Fourv4s:
27453
    case AArch64::ST4Fourv8b:
27454
    case AArch64::ST4Fourv8h:
27455
    case AArch64::ST4Fourv16b: {
27456
      switch (OpNum) {
27457
      case 0:
27458
        // op: Vt
27459
        return 0;
27460
      case 1:
27461
        // op: Rn
27462
        return 5;
27463
      }
27464
      break;
27465
    }
27466
    case AArch64::STL1: {
27467
      switch (OpNum) {
27468
      case 0:
27469
        // op: Vt
27470
        return 0;
27471
      case 2:
27472
        // op: Rn
27473
        return 5;
27474
      case 1:
27475
        // op: Q
27476
        return 30;
27477
      }
27478
      break;
27479
    }
27480
    case AArch64::ST1i8:
27481
    case AArch64::ST2i8:
27482
    case AArch64::ST3i8:
27483
    case AArch64::ST4i8: {
27484
      switch (OpNum) {
27485
      case 0:
27486
        // op: Vt
27487
        return 0;
27488
      case 2:
27489
        // op: Rn
27490
        return 5;
27491
      case 1:
27492
        // op: idx
27493
        return 10;
27494
      }
27495
      break;
27496
    }
27497
    case AArch64::ST1i16:
27498
    case AArch64::ST2i16:
27499
    case AArch64::ST3i16:
27500
    case AArch64::ST4i16: {
27501
      switch (OpNum) {
27502
      case 0:
27503
        // op: Vt
27504
        return 0;
27505
      case 2:
27506
        // op: Rn
27507
        return 5;
27508
      case 1:
27509
        // op: idx
27510
        return 11;
27511
      }
27512
      break;
27513
    }
27514
    case AArch64::ST1i32:
27515
    case AArch64::ST2i32:
27516
    case AArch64::ST3i32:
27517
    case AArch64::ST4i32: {
27518
      switch (OpNum) {
27519
      case 0:
27520
        // op: Vt
27521
        return 0;
27522
      case 2:
27523
        // op: Rn
27524
        return 5;
27525
      case 1:
27526
        // op: idx
27527
        return 12;
27528
      }
27529
      break;
27530
    }
27531
    case AArch64::ST1i64:
27532
    case AArch64::ST2i64:
27533
    case AArch64::ST3i64:
27534
    case AArch64::ST4i64: {
27535
      switch (OpNum) {
27536
      case 0:
27537
        // op: Vt
27538
        return 0;
27539
      case 2:
27540
        // op: Rn
27541
        return 5;
27542
      case 1:
27543
        // op: idx
27544
        return 30;
27545
      }
27546
      break;
27547
    }
27548
    case AArch64::STLXRB:
27549
    case AArch64::STLXRH:
27550
    case AArch64::STLXRW:
27551
    case AArch64::STLXRX:
27552
    case AArch64::STXRB:
27553
    case AArch64::STXRH:
27554
    case AArch64::STXRW:
27555
    case AArch64::STXRX: {
27556
      switch (OpNum) {
27557
      case 0:
27558
        // op: Ws
27559
        return 16;
27560
      case 1:
27561
        // op: Rt
27562
        return 0;
27563
      case 2:
27564
        // op: Rn
27565
        return 5;
27566
      }
27567
      break;
27568
    }
27569
    case AArch64::STLXPW:
27570
    case AArch64::STLXPX:
27571
    case AArch64::STXPW:
27572
    case AArch64::STXPX: {
27573
      switch (OpNum) {
27574
      case 0:
27575
        // op: Ws
27576
        return 16;
27577
      case 1:
27578
        // op: Rt
27579
        return 0;
27580
      case 2:
27581
        // op: Rt2
27582
        return 10;
27583
      case 3:
27584
        // op: Rn
27585
        return 5;
27586
      }
27587
      break;
27588
    }
27589
    case AArch64::ADR:
27590
    case AArch64::ADRP: {
27591
      switch (OpNum) {
27592
      case 0:
27593
        // op: Xd
27594
        return 0;
27595
      case 1:
27596
        // op: label
27597
        return 5;
27598
      }
27599
      break;
27600
    }
27601
    case AArch64::CPY_ZPzI_B:
27602
    case AArch64::CPY_ZPzI_D:
27603
    case AArch64::CPY_ZPzI_H:
27604
    case AArch64::CPY_ZPzI_S: {
27605
      switch (OpNum) {
27606
      case 0:
27607
        // op: Zd
27608
        return 0;
27609
      case 1:
27610
        // op: Pg
27611
        return 16;
27612
      case 2:
27613
        // op: imm
27614
        return 5;
27615
      }
27616
      break;
27617
    }
27618
    case AArch64::LUTI2_ZZZI_H: {
27619
      switch (OpNum) {
27620
      case 0:
27621
        // op: Zd
27622
        return 0;
27623
      case 1:
27624
        // op: Zn
27625
        return 5;
27626
      case 2:
27627
        // op: Zm
27628
        return 16;
27629
      case 3:
27630
        // op: idx
27631
        return 12;
27632
      }
27633
      break;
27634
    }
27635
    case AArch64::LUTI2_ZZZI_B:
27636
    case AArch64::LUTI4_Z2ZZI_H:
27637
    case AArch64::LUTI4_ZZZI_H: {
27638
      switch (OpNum) {
27639
      case 0:
27640
        // op: Zd
27641
        return 0;
27642
      case 1:
27643
        // op: Zn
27644
        return 5;
27645
      case 2:
27646
        // op: Zm
27647
        return 16;
27648
      case 3:
27649
        // op: idx
27650
        return 22;
27651
      }
27652
      break;
27653
    }
27654
    case AArch64::LUTI4_ZZZI_B: {
27655
      switch (OpNum) {
27656
      case 0:
27657
        // op: Zd
27658
        return 0;
27659
      case 1:
27660
        // op: Zn
27661
        return 5;
27662
      case 2:
27663
        // op: Zm
27664
        return 16;
27665
      case 3:
27666
        // op: idx
27667
        return 23;
27668
      }
27669
      break;
27670
    }
27671
    case AArch64::SMULLB_ZZZI_D:
27672
    case AArch64::SMULLB_ZZZI_S:
27673
    case AArch64::SMULLT_ZZZI_D:
27674
    case AArch64::SMULLT_ZZZI_S:
27675
    case AArch64::SQDMULLB_ZZZI_D:
27676
    case AArch64::SQDMULLB_ZZZI_S:
27677
    case AArch64::SQDMULLT_ZZZI_D:
27678
    case AArch64::SQDMULLT_ZZZI_S:
27679
    case AArch64::UMULLB_ZZZI_D:
27680
    case AArch64::UMULLB_ZZZI_S:
27681
    case AArch64::UMULLT_ZZZI_D:
27682
    case AArch64::UMULLT_ZZZI_S: {
27683
      switch (OpNum) {
27684
      case 0:
27685
        // op: Zd
27686
        return 0;
27687
      case 1:
27688
        // op: Zn
27689
        return 5;
27690
      case 2:
27691
        // op: Zm
27692
        return 16;
27693
      case 3:
27694
        // op: iop
27695
        return 11;
27696
      }
27697
      break;
27698
    }
27699
    case AArch64::BFMUL_ZZZI:
27700
    case AArch64::FMUL_ZZZI_H:
27701
    case AArch64::FMUL_ZZZI_S:
27702
    case AArch64::MUL_ZZZI_H:
27703
    case AArch64::MUL_ZZZI_S:
27704
    case AArch64::SQDMULH_ZZZI_H:
27705
    case AArch64::SQDMULH_ZZZI_S:
27706
    case AArch64::SQRDMULH_ZZZI_H:
27707
    case AArch64::SQRDMULH_ZZZI_S: {
27708
      switch (OpNum) {
27709
      case 0:
27710
        // op: Zd
27711
        return 0;
27712
      case 1:
27713
        // op: Zn
27714
        return 5;
27715
      case 2:
27716
        // op: Zm
27717
        return 16;
27718
      case 3:
27719
        // op: iop
27720
        return 19;
27721
      }
27722
      break;
27723
    }
27724
    case AArch64::FMUL_ZZZI_D:
27725
    case AArch64::MUL_ZZZI_D:
27726
    case AArch64::SQDMULH_ZZZI_D:
27727
    case AArch64::SQRDMULH_ZZZI_D: {
27728
      switch (OpNum) {
27729
      case 0:
27730
        // op: Zd
27731
        return 0;
27732
      case 1:
27733
        // op: Zn
27734
        return 5;
27735
      case 2:
27736
        // op: Zm
27737
        return 16;
27738
      case 3:
27739
        // op: iop
27740
        return 20;
27741
      }
27742
      break;
27743
    }
27744
    case AArch64::ADDHNB_ZZZ_B:
27745
    case AArch64::ADDHNB_ZZZ_H:
27746
    case AArch64::ADDHNB_ZZZ_S:
27747
    case AArch64::ADR_LSL_ZZZ_D_0:
27748
    case AArch64::ADR_LSL_ZZZ_D_1:
27749
    case AArch64::ADR_LSL_ZZZ_D_2:
27750
    case AArch64::ADR_LSL_ZZZ_D_3:
27751
    case AArch64::ADR_LSL_ZZZ_S_0:
27752
    case AArch64::ADR_LSL_ZZZ_S_1:
27753
    case AArch64::ADR_LSL_ZZZ_S_2:
27754
    case AArch64::ADR_LSL_ZZZ_S_3:
27755
    case AArch64::ADR_SXTW_ZZZ_D_0:
27756
    case AArch64::ADR_SXTW_ZZZ_D_1:
27757
    case AArch64::ADR_SXTW_ZZZ_D_2:
27758
    case AArch64::ADR_SXTW_ZZZ_D_3:
27759
    case AArch64::ADR_UXTW_ZZZ_D_0:
27760
    case AArch64::ADR_UXTW_ZZZ_D_1:
27761
    case AArch64::ADR_UXTW_ZZZ_D_2:
27762
    case AArch64::ADR_UXTW_ZZZ_D_3:
27763
    case AArch64::BDEP_ZZZ_B:
27764
    case AArch64::BDEP_ZZZ_D:
27765
    case AArch64::BDEP_ZZZ_H:
27766
    case AArch64::BDEP_ZZZ_S:
27767
    case AArch64::BEXT_ZZZ_B:
27768
    case AArch64::BEXT_ZZZ_D:
27769
    case AArch64::BEXT_ZZZ_H:
27770
    case AArch64::BEXT_ZZZ_S:
27771
    case AArch64::BGRP_ZZZ_B:
27772
    case AArch64::BGRP_ZZZ_D:
27773
    case AArch64::BGRP_ZZZ_H:
27774
    case AArch64::BGRP_ZZZ_S:
27775
    case AArch64::HISTSEG_ZZZ:
27776
    case AArch64::PMULLB_ZZZ_D:
27777
    case AArch64::PMULLB_ZZZ_H:
27778
    case AArch64::PMULLB_ZZZ_Q:
27779
    case AArch64::PMULLT_ZZZ_D:
27780
    case AArch64::PMULLT_ZZZ_H:
27781
    case AArch64::PMULLT_ZZZ_Q:
27782
    case AArch64::RADDHNB_ZZZ_B:
27783
    case AArch64::RADDHNB_ZZZ_H:
27784
    case AArch64::RADDHNB_ZZZ_S:
27785
    case AArch64::RAX1_ZZZ_D:
27786
    case AArch64::RSUBHNB_ZZZ_B:
27787
    case AArch64::RSUBHNB_ZZZ_H:
27788
    case AArch64::RSUBHNB_ZZZ_S:
27789
    case AArch64::SABDLB_ZZZ_D:
27790
    case AArch64::SABDLB_ZZZ_H:
27791
    case AArch64::SABDLB_ZZZ_S:
27792
    case AArch64::SABDLT_ZZZ_D:
27793
    case AArch64::SABDLT_ZZZ_H:
27794
    case AArch64::SABDLT_ZZZ_S:
27795
    case AArch64::SADDLBT_ZZZ_D:
27796
    case AArch64::SADDLBT_ZZZ_H:
27797
    case AArch64::SADDLBT_ZZZ_S:
27798
    case AArch64::SADDLB_ZZZ_D:
27799
    case AArch64::SADDLB_ZZZ_H:
27800
    case AArch64::SADDLB_ZZZ_S:
27801
    case AArch64::SADDLT_ZZZ_D:
27802
    case AArch64::SADDLT_ZZZ_H:
27803
    case AArch64::SADDLT_ZZZ_S:
27804
    case AArch64::SADDWB_ZZZ_D:
27805
    case AArch64::SADDWB_ZZZ_H:
27806
    case AArch64::SADDWB_ZZZ_S:
27807
    case AArch64::SADDWT_ZZZ_D:
27808
    case AArch64::SADDWT_ZZZ_H:
27809
    case AArch64::SADDWT_ZZZ_S:
27810
    case AArch64::SM4EKEY_ZZZ_S:
27811
    case AArch64::SMULLB_ZZZ_D:
27812
    case AArch64::SMULLB_ZZZ_H:
27813
    case AArch64::SMULLB_ZZZ_S:
27814
    case AArch64::SMULLT_ZZZ_D:
27815
    case AArch64::SMULLT_ZZZ_H:
27816
    case AArch64::SMULLT_ZZZ_S:
27817
    case AArch64::SQDMULLB_ZZZ_D:
27818
    case AArch64::SQDMULLB_ZZZ_H:
27819
    case AArch64::SQDMULLB_ZZZ_S:
27820
    case AArch64::SQDMULLT_ZZZ_D:
27821
    case AArch64::SQDMULLT_ZZZ_H:
27822
    case AArch64::SQDMULLT_ZZZ_S:
27823
    case AArch64::SSUBLBT_ZZZ_D:
27824
    case AArch64::SSUBLBT_ZZZ_H:
27825
    case AArch64::SSUBLBT_ZZZ_S:
27826
    case AArch64::SSUBLB_ZZZ_D:
27827
    case AArch64::SSUBLB_ZZZ_H:
27828
    case AArch64::SSUBLB_ZZZ_S:
27829
    case AArch64::SSUBLTB_ZZZ_D:
27830
    case AArch64::SSUBLTB_ZZZ_H:
27831
    case AArch64::SSUBLTB_ZZZ_S:
27832
    case AArch64::SSUBLT_ZZZ_D:
27833
    case AArch64::SSUBLT_ZZZ_H:
27834
    case AArch64::SSUBLT_ZZZ_S:
27835
    case AArch64::SSUBWB_ZZZ_D:
27836
    case AArch64::SSUBWB_ZZZ_H:
27837
    case AArch64::SSUBWB_ZZZ_S:
27838
    case AArch64::SSUBWT_ZZZ_D:
27839
    case AArch64::SSUBWT_ZZZ_H:
27840
    case AArch64::SSUBWT_ZZZ_S:
27841
    case AArch64::SUBHNB_ZZZ_B:
27842
    case AArch64::SUBHNB_ZZZ_H:
27843
    case AArch64::SUBHNB_ZZZ_S:
27844
    case AArch64::TBLQ_ZZZ_B:
27845
    case AArch64::TBLQ_ZZZ_D:
27846
    case AArch64::TBLQ_ZZZ_H:
27847
    case AArch64::TBLQ_ZZZ_S:
27848
    case AArch64::UABDLB_ZZZ_D:
27849
    case AArch64::UABDLB_ZZZ_H:
27850
    case AArch64::UABDLB_ZZZ_S:
27851
    case AArch64::UABDLT_ZZZ_D:
27852
    case AArch64::UABDLT_ZZZ_H:
27853
    case AArch64::UABDLT_ZZZ_S:
27854
    case AArch64::UADDLB_ZZZ_D:
27855
    case AArch64::UADDLB_ZZZ_H:
27856
    case AArch64::UADDLB_ZZZ_S:
27857
    case AArch64::UADDLT_ZZZ_D:
27858
    case AArch64::UADDLT_ZZZ_H:
27859
    case AArch64::UADDLT_ZZZ_S:
27860
    case AArch64::UADDWB_ZZZ_D:
27861
    case AArch64::UADDWB_ZZZ_H:
27862
    case AArch64::UADDWB_ZZZ_S:
27863
    case AArch64::UADDWT_ZZZ_D:
27864
    case AArch64::UADDWT_ZZZ_H:
27865
    case AArch64::UADDWT_ZZZ_S:
27866
    case AArch64::UMULLB_ZZZ_D:
27867
    case AArch64::UMULLB_ZZZ_H:
27868
    case AArch64::UMULLB_ZZZ_S:
27869
    case AArch64::UMULLT_ZZZ_D:
27870
    case AArch64::UMULLT_ZZZ_H:
27871
    case AArch64::UMULLT_ZZZ_S:
27872
    case AArch64::USUBLB_ZZZ_D:
27873
    case AArch64::USUBLB_ZZZ_H:
27874
    case AArch64::USUBLB_ZZZ_S:
27875
    case AArch64::USUBLT_ZZZ_D:
27876
    case AArch64::USUBLT_ZZZ_H:
27877
    case AArch64::USUBLT_ZZZ_S:
27878
    case AArch64::USUBWB_ZZZ_D:
27879
    case AArch64::USUBWB_ZZZ_H:
27880
    case AArch64::USUBWB_ZZZ_S:
27881
    case AArch64::USUBWT_ZZZ_D:
27882
    case AArch64::USUBWT_ZZZ_H:
27883
    case AArch64::USUBWT_ZZZ_S:
27884
    case AArch64::UZPQ1_ZZZ_B:
27885
    case AArch64::UZPQ1_ZZZ_D:
27886
    case AArch64::UZPQ1_ZZZ_H:
27887
    case AArch64::UZPQ1_ZZZ_S:
27888
    case AArch64::UZPQ2_ZZZ_B:
27889
    case AArch64::UZPQ2_ZZZ_D:
27890
    case AArch64::UZPQ2_ZZZ_H:
27891
    case AArch64::UZPQ2_ZZZ_S:
27892
    case AArch64::ZIPQ1_ZZZ_B:
27893
    case AArch64::ZIPQ1_ZZZ_D:
27894
    case AArch64::ZIPQ1_ZZZ_H:
27895
    case AArch64::ZIPQ1_ZZZ_S:
27896
    case AArch64::ZIPQ2_ZZZ_B:
27897
    case AArch64::ZIPQ2_ZZZ_D:
27898
    case AArch64::ZIPQ2_ZZZ_H:
27899
    case AArch64::ZIPQ2_ZZZ_S: {
27900
      switch (OpNum) {
27901
      case 0:
27902
        // op: Zd
27903
        return 0;
27904
      case 1:
27905
        // op: Zn
27906
        return 5;
27907
      case 2:
27908
        // op: Zm
27909
        return 16;
27910
      }
27911
      break;
27912
    }
27913
    case AArch64::DUP_ZZI_B: {
27914
      switch (OpNum) {
27915
      case 0:
27916
        // op: Zd
27917
        return 0;
27918
      case 1:
27919
        // op: Zn
27920
        return 5;
27921
      case 2:
27922
        // op: idx
27923
        return 17;
27924
      }
27925
      break;
27926
    }
27927
    case AArch64::DUP_ZZI_H: {
27928
      switch (OpNum) {
27929
      case 0:
27930
        // op: Zd
27931
        return 0;
27932
      case 1:
27933
        // op: Zn
27934
        return 5;
27935
      case 2:
27936
        // op: idx
27937
        return 18;
27938
      }
27939
      break;
27940
    }
27941
    case AArch64::DUP_ZZI_S: {
27942
      switch (OpNum) {
27943
      case 0:
27944
        // op: Zd
27945
        return 0;
27946
      case 1:
27947
        // op: Zn
27948
        return 5;
27949
      case 2:
27950
        // op: idx
27951
        return 19;
27952
      }
27953
      break;
27954
    }
27955
    case AArch64::DUP_ZZI_D: {
27956
      switch (OpNum) {
27957
      case 0:
27958
        // op: Zd
27959
        return 0;
27960
      case 1:
27961
        // op: Zn
27962
        return 5;
27963
      case 2:
27964
        // op: idx
27965
        return 20;
27966
      }
27967
      break;
27968
    }
27969
    case AArch64::DUP_ZZI_Q: {
27970
      switch (OpNum) {
27971
      case 0:
27972
        // op: Zd
27973
        return 0;
27974
      case 1:
27975
        // op: Zn
27976
        return 5;
27977
      case 2:
27978
        // op: idx
27979
        return 22;
27980
      }
27981
      break;
27982
    }
27983
    case AArch64::ASR_ZZI_B:
27984
    case AArch64::ASR_ZZI_D:
27985
    case AArch64::ASR_ZZI_H:
27986
    case AArch64::ASR_ZZI_S:
27987
    case AArch64::LSL_ZZI_B:
27988
    case AArch64::LSL_ZZI_D:
27989
    case AArch64::LSL_ZZI_H:
27990
    case AArch64::LSL_ZZI_S:
27991
    case AArch64::LSR_ZZI_B:
27992
    case AArch64::LSR_ZZI_D:
27993
    case AArch64::LSR_ZZI_H:
27994
    case AArch64::LSR_ZZI_S:
27995
    case AArch64::RSHRNB_ZZI_B:
27996
    case AArch64::RSHRNB_ZZI_H:
27997
    case AArch64::RSHRNB_ZZI_S:
27998
    case AArch64::SHRNB_ZZI_B:
27999
    case AArch64::SHRNB_ZZI_H:
28000
    case AArch64::SHRNB_ZZI_S:
28001
    case AArch64::SQRSHRNB_ZZI_B:
28002
    case AArch64::SQRSHRNB_ZZI_H:
28003
    case AArch64::SQRSHRNB_ZZI_S:
28004
    case AArch64::SQRSHRUNB_ZZI_B:
28005
    case AArch64::SQRSHRUNB_ZZI_H:
28006
    case AArch64::SQRSHRUNB_ZZI_S:
28007
    case AArch64::SQSHRNB_ZZI_B:
28008
    case AArch64::SQSHRNB_ZZI_H:
28009
    case AArch64::SQSHRNB_ZZI_S:
28010
    case AArch64::SQSHRUNB_ZZI_B:
28011
    case AArch64::SQSHRUNB_ZZI_H:
28012
    case AArch64::SQSHRUNB_ZZI_S:
28013
    case AArch64::SSHLLB_ZZI_D:
28014
    case AArch64::SSHLLB_ZZI_H:
28015
    case AArch64::SSHLLB_ZZI_S:
28016
    case AArch64::SSHLLT_ZZI_D:
28017
    case AArch64::SSHLLT_ZZI_H:
28018
    case AArch64::SSHLLT_ZZI_S:
28019
    case AArch64::UQRSHRNB_ZZI_B:
28020
    case AArch64::UQRSHRNB_ZZI_H:
28021
    case AArch64::UQRSHRNB_ZZI_S:
28022
    case AArch64::UQSHRNB_ZZI_B:
28023
    case AArch64::UQSHRNB_ZZI_H:
28024
    case AArch64::UQSHRNB_ZZI_S:
28025
    case AArch64::USHLLB_ZZI_D:
28026
    case AArch64::USHLLB_ZZI_H:
28027
    case AArch64::USHLLB_ZZI_S:
28028
    case AArch64::USHLLT_ZZI_D:
28029
    case AArch64::USHLLT_ZZI_H:
28030
    case AArch64::USHLLT_ZZI_S: {
28031
      switch (OpNum) {
28032
      case 0:
28033
        // op: Zd
28034
        return 0;
28035
      case 1:
28036
        // op: Zn
28037
        return 5;
28038
      case 2:
28039
        // op: imm
28040
        return 16;
28041
      }
28042
      break;
28043
    }
28044
    case AArch64::EXT_ZZI_B: {
28045
      switch (OpNum) {
28046
      case 0:
28047
        // op: Zd
28048
        return 0;
28049
      case 1:
28050
        // op: Zn
28051
        return 5;
28052
      case 2:
28053
        // op: imm8
28054
        return 10;
28055
      }
28056
      break;
28057
    }
28058
    case AArch64::DUPQ_ZZI_B: {
28059
      switch (OpNum) {
28060
      case 0:
28061
        // op: Zd
28062
        return 0;
28063
      case 1:
28064
        // op: Zn
28065
        return 5;
28066
      case 2:
28067
        // op: index
28068
        return 17;
28069
      }
28070
      break;
28071
    }
28072
    case AArch64::DUPQ_ZZI_H: {
28073
      switch (OpNum) {
28074
      case 0:
28075
        // op: Zd
28076
        return 0;
28077
      case 1:
28078
        // op: Zn
28079
        return 5;
28080
      case 2:
28081
        // op: index
28082
        return 18;
28083
      }
28084
      break;
28085
    }
28086
    case AArch64::DUPQ_ZZI_S: {
28087
      switch (OpNum) {
28088
      case 0:
28089
        // op: Zd
28090
        return 0;
28091
      case 1:
28092
        // op: Zn
28093
        return 5;
28094
      case 2:
28095
        // op: index
28096
        return 19;
28097
      }
28098
      break;
28099
    }
28100
    case AArch64::DUPQ_ZZI_D: {
28101
      switch (OpNum) {
28102
      case 0:
28103
        // op: Zd
28104
        return 0;
28105
      case 1:
28106
        // op: Zn
28107
        return 5;
28108
      case 2:
28109
        // op: index
28110
        return 20;
28111
      }
28112
      break;
28113
    }
28114
    case AArch64::BF1CVTLT_ZZ_BtoH:
28115
    case AArch64::BF1CVT_ZZ_BtoH:
28116
    case AArch64::BF2CVTLT_ZZ_BtoH:
28117
    case AArch64::BF2CVT_ZZ_BtoH:
28118
    case AArch64::F1CVTLT_ZZ_BtoH:
28119
    case AArch64::F1CVT_ZZ_BtoH:
28120
    case AArch64::F2CVTLT_ZZ_BtoH:
28121
    case AArch64::F2CVT_ZZ_BtoH:
28122
    case AArch64::FEXPA_ZZ_D:
28123
    case AArch64::FEXPA_ZZ_H:
28124
    case AArch64::FEXPA_ZZ_S:
28125
    case AArch64::FRECPE_ZZ_D:
28126
    case AArch64::FRECPE_ZZ_H:
28127
    case AArch64::FRECPE_ZZ_S:
28128
    case AArch64::FRSQRTE_ZZ_D:
28129
    case AArch64::FRSQRTE_ZZ_H:
28130
    case AArch64::FRSQRTE_ZZ_S:
28131
    case AArch64::MOVPRFX_ZZ:
28132
    case AArch64::REV_ZZ_B:
28133
    case AArch64::REV_ZZ_D:
28134
    case AArch64::REV_ZZ_H:
28135
    case AArch64::REV_ZZ_S:
28136
    case AArch64::SQXTNB_ZZ_B:
28137
    case AArch64::SQXTNB_ZZ_H:
28138
    case AArch64::SQXTNB_ZZ_S:
28139
    case AArch64::SQXTUNB_ZZ_B:
28140
    case AArch64::SQXTUNB_ZZ_H:
28141
    case AArch64::SQXTUNB_ZZ_S:
28142
    case AArch64::SUNPKHI_ZZ_D:
28143
    case AArch64::SUNPKHI_ZZ_H:
28144
    case AArch64::SUNPKHI_ZZ_S:
28145
    case AArch64::SUNPKLO_ZZ_D:
28146
    case AArch64::SUNPKLO_ZZ_H:
28147
    case AArch64::SUNPKLO_ZZ_S:
28148
    case AArch64::UQXTNB_ZZ_B:
28149
    case AArch64::UQXTNB_ZZ_H:
28150
    case AArch64::UQXTNB_ZZ_S:
28151
    case AArch64::UUNPKHI_ZZ_D:
28152
    case AArch64::UUNPKHI_ZZ_H:
28153
    case AArch64::UUNPKHI_ZZ_S:
28154
    case AArch64::UUNPKLO_ZZ_D:
28155
    case AArch64::UUNPKLO_ZZ_H:
28156
    case AArch64::UUNPKLO_ZZ_S: {
28157
      switch (OpNum) {
28158
      case 0:
28159
        // op: Zd
28160
        return 0;
28161
      case 1:
28162
        // op: Zn
28163
        return 5;
28164
      }
28165
      break;
28166
    }
28167
    case AArch64::SQRSHRN_Z2ZI_StoH:
28168
    case AArch64::SQRSHRUN_Z2ZI_StoH:
28169
    case AArch64::UQRSHRN_Z2ZI_StoH: {
28170
      switch (OpNum) {
28171
      case 0:
28172
        // op: Zd
28173
        return 0;
28174
      case 1:
28175
        // op: Zn
28176
        return 6;
28177
      case 2:
28178
        // op: imm4
28179
        return 16;
28180
      }
28181
      break;
28182
    }
28183
    case AArch64::BFCVTN_Z2Z_HtoB:
28184
    case AArch64::FCVTNB_Z2Z_StoB:
28185
    case AArch64::FCVTNT_Z2Z_StoB:
28186
    case AArch64::FCVTN_Z2Z_HtoB:
28187
    case AArch64::SQCVTN_Z2Z_StoH:
28188
    case AArch64::SQCVTUN_Z2Z_StoH:
28189
    case AArch64::UQCVTN_Z2Z_StoH: {
28190
      switch (OpNum) {
28191
      case 0:
28192
        // op: Zd
28193
        return 0;
28194
      case 1:
28195
        // op: Zn
28196
        return 6;
28197
      }
28198
      break;
28199
    }
28200
    case AArch64::DUP_ZI_B:
28201
    case AArch64::DUP_ZI_D:
28202
    case AArch64::DUP_ZI_H:
28203
    case AArch64::DUP_ZI_S: {
28204
      switch (OpNum) {
28205
      case 0:
28206
        // op: Zd
28207
        return 0;
28208
      case 1:
28209
        // op: imm
28210
        return 5;
28211
      }
28212
      break;
28213
    }
28214
    case AArch64::INDEX_II_B:
28215
    case AArch64::INDEX_II_D:
28216
    case AArch64::INDEX_II_H:
28217
    case AArch64::INDEX_II_S: {
28218
      switch (OpNum) {
28219
      case 0:
28220
        // op: Zd
28221
        return 0;
28222
      case 1:
28223
        // op: imm5
28224
        return 5;
28225
      case 2:
28226
        // op: imm5b
28227
        return 16;
28228
      }
28229
      break;
28230
    }
28231
    case AArch64::FDUP_ZI_D:
28232
    case AArch64::FDUP_ZI_H:
28233
    case AArch64::FDUP_ZI_S: {
28234
      switch (OpNum) {
28235
      case 0:
28236
        // op: Zd
28237
        return 0;
28238
      case 1:
28239
        // op: imm8
28240
        return 5;
28241
      }
28242
      break;
28243
    }
28244
    case AArch64::DUPM_ZI: {
28245
      switch (OpNum) {
28246
      case 0:
28247
        // op: Zd
28248
        return 0;
28249
      case 1:
28250
        // op: imms
28251
        return 5;
28252
      }
28253
      break;
28254
    }
28255
    case AArch64::BFCVTNT_ZPmZ:
28256
    case AArch64::BFCVT_ZPmZ:
28257
    case AArch64::RBIT_ZPmZ_B:
28258
    case AArch64::RBIT_ZPmZ_D:
28259
    case AArch64::RBIT_ZPmZ_H:
28260
    case AArch64::RBIT_ZPmZ_S:
28261
    case AArch64::REVB_ZPmZ_D:
28262
    case AArch64::REVB_ZPmZ_H:
28263
    case AArch64::REVB_ZPmZ_S:
28264
    case AArch64::REVD_ZPmZ:
28265
    case AArch64::REVH_ZPmZ_D:
28266
    case AArch64::REVH_ZPmZ_S:
28267
    case AArch64::REVW_ZPmZ_D: {
28268
      switch (OpNum) {
28269
      case 0:
28270
        // op: Zd
28271
        return 0;
28272
      case 2:
28273
        // op: Pg
28274
        return 10;
28275
      case 3:
28276
        // op: Zn
28277
        return 5;
28278
      }
28279
      break;
28280
    }
28281
    case AArch64::CPY_ZPmI_B:
28282
    case AArch64::CPY_ZPmI_D:
28283
    case AArch64::CPY_ZPmI_H:
28284
    case AArch64::CPY_ZPmI_S: {
28285
      switch (OpNum) {
28286
      case 0:
28287
        // op: Zd
28288
        return 0;
28289
      case 2:
28290
        // op: Pg
28291
        return 16;
28292
      case 3:
28293
        // op: imm
28294
        return 5;
28295
      }
28296
      break;
28297
    }
28298
    case AArch64::INDEX_RR_B:
28299
    case AArch64::INDEX_RR_D:
28300
    case AArch64::INDEX_RR_H:
28301
    case AArch64::INDEX_RR_S: {
28302
      switch (OpNum) {
28303
      case 0:
28304
        // op: Zd
28305
        return 0;
28306
      case 2:
28307
        // op: Rm
28308
        return 16;
28309
      case 1:
28310
        // op: Rn
28311
        return 5;
28312
      }
28313
      break;
28314
    }
28315
    case AArch64::ADD_ZZZ_B:
28316
    case AArch64::ADD_ZZZ_CPA:
28317
    case AArch64::ADD_ZZZ_D:
28318
    case AArch64::ADD_ZZZ_H:
28319
    case AArch64::ADD_ZZZ_S:
28320
    case AArch64::AND_ZZZ:
28321
    case AArch64::ASR_WIDE_ZZZ_B:
28322
    case AArch64::ASR_WIDE_ZZZ_H:
28323
    case AArch64::ASR_WIDE_ZZZ_S:
28324
    case AArch64::BFADD_ZZZ:
28325
    case AArch64::BFMUL_ZZZ:
28326
    case AArch64::BFSUB_ZZZ:
28327
    case AArch64::BIC_ZZZ:
28328
    case AArch64::EOR_ZZZ:
28329
    case AArch64::FADD_ZZZ_D:
28330
    case AArch64::FADD_ZZZ_H:
28331
    case AArch64::FADD_ZZZ_S:
28332
    case AArch64::FMUL_ZZZ_D:
28333
    case AArch64::FMUL_ZZZ_H:
28334
    case AArch64::FMUL_ZZZ_S:
28335
    case AArch64::FRECPS_ZZZ_D:
28336
    case AArch64::FRECPS_ZZZ_H:
28337
    case AArch64::FRECPS_ZZZ_S:
28338
    case AArch64::FRSQRTS_ZZZ_D:
28339
    case AArch64::FRSQRTS_ZZZ_H:
28340
    case AArch64::FRSQRTS_ZZZ_S:
28341
    case AArch64::FSUB_ZZZ_D:
28342
    case AArch64::FSUB_ZZZ_H:
28343
    case AArch64::FSUB_ZZZ_S:
28344
    case AArch64::FTSMUL_ZZZ_D:
28345
    case AArch64::FTSMUL_ZZZ_H:
28346
    case AArch64::FTSMUL_ZZZ_S:
28347
    case AArch64::FTSSEL_ZZZ_D:
28348
    case AArch64::FTSSEL_ZZZ_H:
28349
    case AArch64::FTSSEL_ZZZ_S:
28350
    case AArch64::LSL_WIDE_ZZZ_B:
28351
    case AArch64::LSL_WIDE_ZZZ_H:
28352
    case AArch64::LSL_WIDE_ZZZ_S:
28353
    case AArch64::LSR_WIDE_ZZZ_B:
28354
    case AArch64::LSR_WIDE_ZZZ_H:
28355
    case AArch64::LSR_WIDE_ZZZ_S:
28356
    case AArch64::MUL_ZZZ_B:
28357
    case AArch64::MUL_ZZZ_D:
28358
    case AArch64::MUL_ZZZ_H:
28359
    case AArch64::MUL_ZZZ_S:
28360
    case AArch64::ORR_ZZZ:
28361
    case AArch64::PMUL_ZZZ_B:
28362
    case AArch64::SMULH_ZZZ_B:
28363
    case AArch64::SMULH_ZZZ_D:
28364
    case AArch64::SMULH_ZZZ_H:
28365
    case AArch64::SMULH_ZZZ_S:
28366
    case AArch64::SQADD_ZZZ_B:
28367
    case AArch64::SQADD_ZZZ_D:
28368
    case AArch64::SQADD_ZZZ_H:
28369
    case AArch64::SQADD_ZZZ_S:
28370
    case AArch64::SQDMULH_ZZZ_B:
28371
    case AArch64::SQDMULH_ZZZ_D:
28372
    case AArch64::SQDMULH_ZZZ_H:
28373
    case AArch64::SQDMULH_ZZZ_S:
28374
    case AArch64::SQRDMULH_ZZZ_B:
28375
    case AArch64::SQRDMULH_ZZZ_D:
28376
    case AArch64::SQRDMULH_ZZZ_H:
28377
    case AArch64::SQRDMULH_ZZZ_S:
28378
    case AArch64::SQSUB_ZZZ_B:
28379
    case AArch64::SQSUB_ZZZ_D:
28380
    case AArch64::SQSUB_ZZZ_H:
28381
    case AArch64::SQSUB_ZZZ_S:
28382
    case AArch64::SUB_ZZZ_B:
28383
    case AArch64::SUB_ZZZ_CPA:
28384
    case AArch64::SUB_ZZZ_D:
28385
    case AArch64::SUB_ZZZ_H:
28386
    case AArch64::SUB_ZZZ_S:
28387
    case AArch64::TBL_ZZZZ_B:
28388
    case AArch64::TBL_ZZZZ_D:
28389
    case AArch64::TBL_ZZZZ_H:
28390
    case AArch64::TBL_ZZZZ_S:
28391
    case AArch64::TBL_ZZZ_B:
28392
    case AArch64::TBL_ZZZ_D:
28393
    case AArch64::TBL_ZZZ_H:
28394
    case AArch64::TBL_ZZZ_S:
28395
    case AArch64::TRN1_ZZZ_B:
28396
    case AArch64::TRN1_ZZZ_D:
28397
    case AArch64::TRN1_ZZZ_H:
28398
    case AArch64::TRN1_ZZZ_Q:
28399
    case AArch64::TRN1_ZZZ_S:
28400
    case AArch64::TRN2_ZZZ_B:
28401
    case AArch64::TRN2_ZZZ_D:
28402
    case AArch64::TRN2_ZZZ_H:
28403
    case AArch64::TRN2_ZZZ_Q:
28404
    case AArch64::TRN2_ZZZ_S:
28405
    case AArch64::UMULH_ZZZ_B:
28406
    case AArch64::UMULH_ZZZ_D:
28407
    case AArch64::UMULH_ZZZ_H:
28408
    case AArch64::UMULH_ZZZ_S:
28409
    case AArch64::UQADD_ZZZ_B:
28410
    case AArch64::UQADD_ZZZ_D:
28411
    case AArch64::UQADD_ZZZ_H:
28412
    case AArch64::UQADD_ZZZ_S:
28413
    case AArch64::UQSUB_ZZZ_B:
28414
    case AArch64::UQSUB_ZZZ_D:
28415
    case AArch64::UQSUB_ZZZ_H:
28416
    case AArch64::UQSUB_ZZZ_S:
28417
    case AArch64::UZP1_ZZZ_B:
28418
    case AArch64::UZP1_ZZZ_D:
28419
    case AArch64::UZP1_ZZZ_H:
28420
    case AArch64::UZP1_ZZZ_Q:
28421
    case AArch64::UZP1_ZZZ_S:
28422
    case AArch64::UZP2_ZZZ_B:
28423
    case AArch64::UZP2_ZZZ_D:
28424
    case AArch64::UZP2_ZZZ_H:
28425
    case AArch64::UZP2_ZZZ_Q:
28426
    case AArch64::UZP2_ZZZ_S:
28427
    case AArch64::ZIP1_ZZZ_B:
28428
    case AArch64::ZIP1_ZZZ_D:
28429
    case AArch64::ZIP1_ZZZ_H:
28430
    case AArch64::ZIP1_ZZZ_Q:
28431
    case AArch64::ZIP1_ZZZ_S:
28432
    case AArch64::ZIP2_ZZZ_B:
28433
    case AArch64::ZIP2_ZZZ_D:
28434
    case AArch64::ZIP2_ZZZ_H:
28435
    case AArch64::ZIP2_ZZZ_Q:
28436
    case AArch64::ZIP2_ZZZ_S: {
28437
      switch (OpNum) {
28438
      case 0:
28439
        // op: Zd
28440
        return 0;
28441
      case 2:
28442
        // op: Zm
28443
        return 16;
28444
      case 1:
28445
        // op: Zn
28446
        return 5;
28447
      }
28448
      break;
28449
    }
28450
    case AArch64::HISTCNT_ZPzZZ_D:
28451
    case AArch64::HISTCNT_ZPzZZ_S: {
28452
      switch (OpNum) {
28453
      case 0:
28454
        // op: Zd
28455
        return 0;
28456
      case 2:
28457
        // op: Zn
28458
        return 5;
28459
      case 1:
28460
        // op: Pg
28461
        return 10;
28462
      case 3:
28463
        // op: Zm
28464
        return 16;
28465
      }
28466
      break;
28467
    }
28468
    case AArch64::ADDHNT_ZZZ_B:
28469
    case AArch64::ADDHNT_ZZZ_H:
28470
    case AArch64::ADDHNT_ZZZ_S:
28471
    case AArch64::EORBT_ZZZ_B:
28472
    case AArch64::EORBT_ZZZ_D:
28473
    case AArch64::EORBT_ZZZ_H:
28474
    case AArch64::EORBT_ZZZ_S:
28475
    case AArch64::EORTB_ZZZ_B:
28476
    case AArch64::EORTB_ZZZ_D:
28477
    case AArch64::EORTB_ZZZ_H:
28478
    case AArch64::EORTB_ZZZ_S:
28479
    case AArch64::RADDHNT_ZZZ_B:
28480
    case AArch64::RADDHNT_ZZZ_H:
28481
    case AArch64::RADDHNT_ZZZ_S:
28482
    case AArch64::RSUBHNT_ZZZ_B:
28483
    case AArch64::RSUBHNT_ZZZ_H:
28484
    case AArch64::RSUBHNT_ZZZ_S:
28485
    case AArch64::SUBHNT_ZZZ_B:
28486
    case AArch64::SUBHNT_ZZZ_H:
28487
    case AArch64::SUBHNT_ZZZ_S: {
28488
      switch (OpNum) {
28489
      case 0:
28490
        // op: Zd
28491
        return 0;
28492
      case 2:
28493
        // op: Zn
28494
        return 5;
28495
      case 3:
28496
        // op: Zm
28497
        return 16;
28498
      }
28499
      break;
28500
    }
28501
    case AArch64::RSHRNT_ZZI_B:
28502
    case AArch64::RSHRNT_ZZI_H:
28503
    case AArch64::RSHRNT_ZZI_S:
28504
    case AArch64::SHRNT_ZZI_B:
28505
    case AArch64::SHRNT_ZZI_H:
28506
    case AArch64::SHRNT_ZZI_S:
28507
    case AArch64::SLI_ZZI_B:
28508
    case AArch64::SLI_ZZI_D:
28509
    case AArch64::SLI_ZZI_H:
28510
    case AArch64::SLI_ZZI_S:
28511
    case AArch64::SQRSHRNT_ZZI_B:
28512
    case AArch64::SQRSHRNT_ZZI_H:
28513
    case AArch64::SQRSHRNT_ZZI_S:
28514
    case AArch64::SQRSHRUNT_ZZI_B:
28515
    case AArch64::SQRSHRUNT_ZZI_H:
28516
    case AArch64::SQRSHRUNT_ZZI_S:
28517
    case AArch64::SQSHRNT_ZZI_B:
28518
    case AArch64::SQSHRNT_ZZI_H:
28519
    case AArch64::SQSHRNT_ZZI_S:
28520
    case AArch64::SQSHRUNT_ZZI_B:
28521
    case AArch64::SQSHRUNT_ZZI_H:
28522
    case AArch64::SQSHRUNT_ZZI_S:
28523
    case AArch64::SRI_ZZI_B:
28524
    case AArch64::SRI_ZZI_D:
28525
    case AArch64::SRI_ZZI_H:
28526
    case AArch64::SRI_ZZI_S:
28527
    case AArch64::UQRSHRNT_ZZI_B:
28528
    case AArch64::UQRSHRNT_ZZI_H:
28529
    case AArch64::UQRSHRNT_ZZI_S:
28530
    case AArch64::UQSHRNT_ZZI_B:
28531
    case AArch64::UQSHRNT_ZZI_H:
28532
    case AArch64::UQSHRNT_ZZI_S: {
28533
      switch (OpNum) {
28534
      case 0:
28535
        // op: Zd
28536
        return 0;
28537
      case 2:
28538
        // op: Zn
28539
        return 5;
28540
      case 3:
28541
        // op: imm
28542
        return 16;
28543
      }
28544
      break;
28545
    }
28546
    case AArch64::SQXTNT_ZZ_B:
28547
    case AArch64::SQXTNT_ZZ_H:
28548
    case AArch64::SQXTNT_ZZ_S:
28549
    case AArch64::SQXTUNT_ZZ_B:
28550
    case AArch64::SQXTUNT_ZZ_H:
28551
    case AArch64::SQXTUNT_ZZ_S:
28552
    case AArch64::UQXTNT_ZZ_B:
28553
    case AArch64::UQXTNT_ZZ_H:
28554
    case AArch64::UQXTNT_ZZ_S: {
28555
      switch (OpNum) {
28556
      case 0:
28557
        // op: Zd
28558
        return 0;
28559
      case 2:
28560
        // op: Zn
28561
        return 5;
28562
      }
28563
      break;
28564
    }
28565
    case AArch64::PMOV_ZIP_D:
28566
    case AArch64::PMOV_ZIP_H:
28567
    case AArch64::PMOV_ZIP_S: {
28568
      switch (OpNum) {
28569
      case 0:
28570
        // op: Zd
28571
        return 0;
28572
      case 3:
28573
        // op: Pn
28574
        return 5;
28575
      case 2:
28576
        // op: index
28577
        return 17;
28578
      }
28579
      break;
28580
    }
28581
    case AArch64::PMOV_ZIP_B: {
28582
      switch (OpNum) {
28583
      case 0:
28584
        // op: Zd
28585
        return 0;
28586
      case 3:
28587
        // op: Pn
28588
        return 5;
28589
      }
28590
      break;
28591
    }
28592
    case AArch64::TBXQ_ZZZ_B:
28593
    case AArch64::TBXQ_ZZZ_D:
28594
    case AArch64::TBXQ_ZZZ_H:
28595
    case AArch64::TBXQ_ZZZ_S:
28596
    case AArch64::TBX_ZZZ_B:
28597
    case AArch64::TBX_ZZZ_D:
28598
    case AArch64::TBX_ZZZ_H:
28599
    case AArch64::TBX_ZZZ_S: {
28600
      switch (OpNum) {
28601
      case 0:
28602
        // op: Zd
28603
        return 0;
28604
      case 3:
28605
        // op: Zm
28606
        return 16;
28607
      case 2:
28608
        // op: Zn
28609
        return 5;
28610
      }
28611
      break;
28612
    }
28613
    case AArch64::FCVTLT_ZPmZ_HtoS:
28614
    case AArch64::FCVTLT_ZPmZ_StoD:
28615
    case AArch64::FCVTNT_ZPmZ_DtoS:
28616
    case AArch64::FCVTNT_ZPmZ_StoH:
28617
    case AArch64::FCVTXNT_ZPmZ_DtoS: {
28618
      switch (OpNum) {
28619
      case 0:
28620
        // op: Zd
28621
        return 0;
28622
      case 3:
28623
        // op: Zn
28624
        return 5;
28625
      case 2:
28626
        // op: Pg
28627
        return 10;
28628
      }
28629
      break;
28630
    }
28631
    case AArch64::MOVA_2ZMXI_H_D:
28632
    case AArch64::MOVA_2ZMXI_V_D: {
28633
      switch (OpNum) {
28634
      case 0:
28635
        // op: Zd
28636
        return 1;
28637
      case 2:
28638
        // op: Rs
28639
        return 13;
28640
      case 1:
28641
        // op: ZAn
28642
        return 5;
28643
      }
28644
      break;
28645
    }
28646
    case AArch64::MOVA_2ZMXI_H_S:
28647
    case AArch64::MOVA_2ZMXI_V_S: {
28648
      switch (OpNum) {
28649
      case 0:
28650
        // op: Zd
28651
        return 1;
28652
      case 2:
28653
        // op: Rs
28654
        return 13;
28655
      case 1:
28656
        // op: ZAn
28657
        return 6;
28658
      case 3:
28659
        // op: imm
28660
        return 5;
28661
      }
28662
      break;
28663
    }
28664
    case AArch64::MOVA_2ZMXI_H_H:
28665
    case AArch64::MOVA_2ZMXI_V_H: {
28666
      switch (OpNum) {
28667
      case 0:
28668
        // op: Zd
28669
        return 1;
28670
      case 2:
28671
        // op: Rs
28672
        return 13;
28673
      case 1:
28674
        // op: ZAn
28675
        return 7;
28676
      case 3:
28677
        // op: imm
28678
        return 5;
28679
      }
28680
      break;
28681
    }
28682
    case AArch64::MOVA_2ZMXI_H_B:
28683
    case AArch64::MOVA_2ZMXI_V_B: {
28684
      switch (OpNum) {
28685
      case 0:
28686
        // op: Zd
28687
        return 1;
28688
      case 2:
28689
        // op: Rs
28690
        return 13;
28691
      case 3:
28692
        // op: imm
28693
        return 5;
28694
      }
28695
      break;
28696
    }
28697
    case AArch64::UZP_VG2_2ZZZ_B:
28698
    case AArch64::UZP_VG2_2ZZZ_D:
28699
    case AArch64::UZP_VG2_2ZZZ_H:
28700
    case AArch64::UZP_VG2_2ZZZ_Q:
28701
    case AArch64::UZP_VG2_2ZZZ_S:
28702
    case AArch64::ZIP_VG2_2ZZZ_B:
28703
    case AArch64::ZIP_VG2_2ZZZ_D:
28704
    case AArch64::ZIP_VG2_2ZZZ_H:
28705
    case AArch64::ZIP_VG2_2ZZZ_Q:
28706
    case AArch64::ZIP_VG2_2ZZZ_S: {
28707
      switch (OpNum) {
28708
      case 0:
28709
        // op: Zd
28710
        return 1;
28711
      case 2:
28712
        // op: Zm
28713
        return 16;
28714
      case 1:
28715
        // op: Zn
28716
        return 5;
28717
      }
28718
      break;
28719
    }
28720
    case AArch64::MOVAZ_2ZMI_H_D:
28721
    case AArch64::MOVAZ_2ZMI_V_D: {
28722
      switch (OpNum) {
28723
      case 0:
28724
        // op: Zd
28725
        return 1;
28726
      case 3:
28727
        // op: Rs
28728
        return 13;
28729
      case 2:
28730
        // op: ZAn
28731
        return 5;
28732
      }
28733
      break;
28734
    }
28735
    case AArch64::MOVAZ_2ZMI_H_S:
28736
    case AArch64::MOVAZ_2ZMI_V_S: {
28737
      switch (OpNum) {
28738
      case 0:
28739
        // op: Zd
28740
        return 1;
28741
      case 3:
28742
        // op: Rs
28743
        return 13;
28744
      case 2:
28745
        // op: ZAn
28746
        return 6;
28747
      case 4:
28748
        // op: imm
28749
        return 5;
28750
      }
28751
      break;
28752
    }
28753
    case AArch64::MOVAZ_2ZMI_H_H:
28754
    case AArch64::MOVAZ_2ZMI_V_H: {
28755
      switch (OpNum) {
28756
      case 0:
28757
        // op: Zd
28758
        return 1;
28759
      case 3:
28760
        // op: Rs
28761
        return 13;
28762
      case 2:
28763
        // op: ZAn
28764
        return 7;
28765
      case 4:
28766
        // op: imm
28767
        return 5;
28768
      }
28769
      break;
28770
    }
28771
    case AArch64::MOVAZ_2ZMI_H_B:
28772
    case AArch64::MOVAZ_2ZMI_V_B: {
28773
      switch (OpNum) {
28774
      case 0:
28775
        // op: Zd
28776
        return 1;
28777
      case 3:
28778
        // op: Rs
28779
        return 13;
28780
      case 4:
28781
        // op: imm
28782
        return 5;
28783
      }
28784
      break;
28785
    }
28786
    case AArch64::MOVA_4ZMXI_H_D:
28787
    case AArch64::MOVA_4ZMXI_H_S:
28788
    case AArch64::MOVA_4ZMXI_V_D:
28789
    case AArch64::MOVA_4ZMXI_V_S: {
28790
      switch (OpNum) {
28791
      case 0:
28792
        // op: Zd
28793
        return 2;
28794
      case 2:
28795
        // op: Rs
28796
        return 13;
28797
      case 1:
28798
        // op: ZAn
28799
        return 5;
28800
      }
28801
      break;
28802
    }
28803
    case AArch64::MOVA_4ZMXI_H_H:
28804
    case AArch64::MOVA_4ZMXI_V_H: {
28805
      switch (OpNum) {
28806
      case 0:
28807
        // op: Zd
28808
        return 2;
28809
      case 2:
28810
        // op: Rs
28811
        return 13;
28812
      case 1:
28813
        // op: ZAn
28814
        return 6;
28815
      case 3:
28816
        // op: imm
28817
        return 5;
28818
      }
28819
      break;
28820
    }
28821
    case AArch64::MOVA_4ZMXI_H_B:
28822
    case AArch64::MOVA_4ZMXI_V_B: {
28823
      switch (OpNum) {
28824
      case 0:
28825
        // op: Zd
28826
        return 2;
28827
      case 2:
28828
        // op: Rs
28829
        return 13;
28830
      case 3:
28831
        // op: imm
28832
        return 5;
28833
      }
28834
      break;
28835
    }
28836
    case AArch64::MOVAZ_4ZMI_H_D:
28837
    case AArch64::MOVAZ_4ZMI_H_S:
28838
    case AArch64::MOVAZ_4ZMI_V_D:
28839
    case AArch64::MOVAZ_4ZMI_V_S: {
28840
      switch (OpNum) {
28841
      case 0:
28842
        // op: Zd
28843
        return 2;
28844
      case 3:
28845
        // op: Rs
28846
        return 13;
28847
      case 2:
28848
        // op: ZAn
28849
        return 5;
28850
      }
28851
      break;
28852
    }
28853
    case AArch64::MOVAZ_4ZMI_H_H:
28854
    case AArch64::MOVAZ_4ZMI_V_H: {
28855
      switch (OpNum) {
28856
      case 0:
28857
        // op: Zd
28858
        return 2;
28859
      case 3:
28860
        // op: Rs
28861
        return 13;
28862
      case 2:
28863
        // op: ZAn
28864
        return 6;
28865
      case 4:
28866
        // op: imm
28867
        return 5;
28868
      }
28869
      break;
28870
    }
28871
    case AArch64::MOVAZ_4ZMI_H_B:
28872
    case AArch64::MOVAZ_4ZMI_V_B: {
28873
      switch (OpNum) {
28874
      case 0:
28875
        // op: Zd
28876
        return 2;
28877
      case 3:
28878
        // op: Rs
28879
        return 13;
28880
      case 4:
28881
        // op: imm
28882
        return 5;
28883
      }
28884
      break;
28885
    }
28886
    case AArch64::FCMLA_ZPmZZ_D:
28887
    case AArch64::FCMLA_ZPmZZ_H:
28888
    case AArch64::FCMLA_ZPmZZ_S: {
28889
      switch (OpNum) {
28890
      case 0:
28891
        // op: Zda
28892
        return 0;
28893
      case 1:
28894
        // op: Pg
28895
        return 10;
28896
      case 3:
28897
        // op: Zn
28898
        return 5;
28899
      case 4:
28900
        // op: Zm
28901
        return 16;
28902
      case 5:
28903
        // op: imm
28904
        return 13;
28905
      }
28906
      break;
28907
    }
28908
    case AArch64::SDOT_ZZZI_HtoS:
28909
    case AArch64::UDOT_ZZZI_HtoS: {
28910
      switch (OpNum) {
28911
      case 0:
28912
        // op: Zda
28913
        return 0;
28914
      case 2:
28915
        // op: Zn
28916
        return 5;
28917
      case 3:
28918
        // op: Zm
28919
        return 16;
28920
      case 4:
28921
        // op: i2
28922
        return 19;
28923
      }
28924
      break;
28925
    }
28926
    case AArch64::SUDOT_ZZZI:
28927
    case AArch64::USDOT_ZZZI: {
28928
      switch (OpNum) {
28929
      case 0:
28930
        // op: Zda
28931
        return 0;
28932
      case 2:
28933
        // op: Zn
28934
        return 5;
28935
      case 3:
28936
        // op: Zm
28937
        return 16;
28938
      case 4:
28939
        // op: idx
28940
        return 19;
28941
      }
28942
      break;
28943
    }
28944
    case AArch64::FMLALB_ZZZI:
28945
    case AArch64::FMLALLBB_ZZZI:
28946
    case AArch64::FMLALLBT_ZZZI:
28947
    case AArch64::FMLALLTB_ZZZI:
28948
    case AArch64::FMLALLTT_ZZZI:
28949
    case AArch64::FMLALT_ZZZI: {
28950
      switch (OpNum) {
28951
      case 0:
28952
        // op: Zda
28953
        return 0;
28954
      case 2:
28955
        // op: Zn
28956
        return 5;
28957
      case 3:
28958
        // op: Zm
28959
        return 16;
28960
      case 4:
28961
        // op: imm4
28962
        return 10;
28963
      }
28964
      break;
28965
    }
28966
    case AArch64::BFMLALB_ZZZI:
28967
    case AArch64::BFMLALT_ZZZI:
28968
    case AArch64::BFMLSLB_ZZZI_S:
28969
    case AArch64::BFMLSLT_ZZZI_S:
28970
    case AArch64::FDOT_ZZZI_BtoH:
28971
    case AArch64::FMLALB_ZZZI_SHH:
28972
    case AArch64::FMLALT_ZZZI_SHH:
28973
    case AArch64::FMLSLB_ZZZI_SHH:
28974
    case AArch64::FMLSLT_ZZZI_SHH:
28975
    case AArch64::SMLALB_ZZZI_D:
28976
    case AArch64::SMLALB_ZZZI_S:
28977
    case AArch64::SMLALT_ZZZI_D:
28978
    case AArch64::SMLALT_ZZZI_S:
28979
    case AArch64::SMLSLB_ZZZI_D:
28980
    case AArch64::SMLSLB_ZZZI_S:
28981
    case AArch64::SMLSLT_ZZZI_D:
28982
    case AArch64::SMLSLT_ZZZI_S:
28983
    case AArch64::SQDMLALB_ZZZI_D:
28984
    case AArch64::SQDMLALB_ZZZI_S:
28985
    case AArch64::SQDMLALT_ZZZI_D:
28986
    case AArch64::SQDMLALT_ZZZI_S:
28987
    case AArch64::SQDMLSLB_ZZZI_D:
28988
    case AArch64::SQDMLSLB_ZZZI_S:
28989
    case AArch64::SQDMLSLT_ZZZI_D:
28990
    case AArch64::SQDMLSLT_ZZZI_S:
28991
    case AArch64::UMLALB_ZZZI_D:
28992
    case AArch64::UMLALB_ZZZI_S:
28993
    case AArch64::UMLALT_ZZZI_D:
28994
    case AArch64::UMLALT_ZZZI_S:
28995
    case AArch64::UMLSLB_ZZZI_D:
28996
    case AArch64::UMLSLB_ZZZI_S:
28997
    case AArch64::UMLSLT_ZZZI_D:
28998
    case AArch64::UMLSLT_ZZZI_S: {
28999
      switch (OpNum) {
29000
      case 0:
29001
        // op: Zda
29002
        return 0;
29003
      case 2:
29004
        // op: Zn
29005
        return 5;
29006
      case 3:
29007
        // op: Zm
29008
        return 16;
29009
      case 4:
29010
        // op: iop
29011
        return 11;
29012
      }
29013
      break;
29014
    }
29015
    case AArch64::BFDOT_ZZI:
29016
    case AArch64::BFMLA_ZZZI:
29017
    case AArch64::BFMLS_ZZZI:
29018
    case AArch64::FDOT_ZZZI_BtoS:
29019
    case AArch64::FDOT_ZZZI_S:
29020
    case AArch64::FMLA_ZZZI_H:
29021
    case AArch64::FMLA_ZZZI_S:
29022
    case AArch64::FMLS_ZZZI_H:
29023
    case AArch64::FMLS_ZZZI_S:
29024
    case AArch64::MLA_ZZZI_H:
29025
    case AArch64::MLA_ZZZI_S:
29026
    case AArch64::MLS_ZZZI_H:
29027
    case AArch64::MLS_ZZZI_S:
29028
    case AArch64::SQRDMLAH_ZZZI_H:
29029
    case AArch64::SQRDMLAH_ZZZI_S:
29030
    case AArch64::SQRDMLSH_ZZZI_H:
29031
    case AArch64::SQRDMLSH_ZZZI_S: {
29032
      switch (OpNum) {
29033
      case 0:
29034
        // op: Zda
29035
        return 0;
29036
      case 2:
29037
        // op: Zn
29038
        return 5;
29039
      case 3:
29040
        // op: Zm
29041
        return 16;
29042
      case 4:
29043
        // op: iop
29044
        return 19;
29045
      }
29046
      break;
29047
    }
29048
    case AArch64::FMLA_ZZZI_D:
29049
    case AArch64::FMLS_ZZZI_D:
29050
    case AArch64::MLA_ZZZI_D:
29051
    case AArch64::MLS_ZZZI_D:
29052
    case AArch64::SQRDMLAH_ZZZI_D:
29053
    case AArch64::SQRDMLSH_ZZZI_D: {
29054
      switch (OpNum) {
29055
      case 0:
29056
        // op: Zda
29057
        return 0;
29058
      case 2:
29059
        // op: Zn
29060
        return 5;
29061
      case 3:
29062
        // op: Zm
29063
        return 16;
29064
      case 4:
29065
        // op: iop
29066
        return 20;
29067
      }
29068
      break;
29069
    }
29070
    case AArch64::CDOT_ZZZ_D:
29071
    case AArch64::CDOT_ZZZ_S:
29072
    case AArch64::CMLA_ZZZ_B:
29073
    case AArch64::CMLA_ZZZ_D:
29074
    case AArch64::CMLA_ZZZ_H:
29075
    case AArch64::CMLA_ZZZ_S:
29076
    case AArch64::SQRDCMLAH_ZZZ_B:
29077
    case AArch64::SQRDCMLAH_ZZZ_D:
29078
    case AArch64::SQRDCMLAH_ZZZ_H:
29079
    case AArch64::SQRDCMLAH_ZZZ_S: {
29080
      switch (OpNum) {
29081
      case 0:
29082
        // op: Zda
29083
        return 0;
29084
      case 2:
29085
        // op: Zn
29086
        return 5;
29087
      case 3:
29088
        // op: Zm
29089
        return 16;
29090
      case 4:
29091
        // op: rot
29092
        return 10;
29093
      }
29094
      break;
29095
    }
29096
    case AArch64::ADCLB_ZZZ_D:
29097
    case AArch64::ADCLB_ZZZ_S:
29098
    case AArch64::ADCLT_ZZZ_D:
29099
    case AArch64::ADCLT_ZZZ_S:
29100
    case AArch64::BFDOT_ZZZ:
29101
    case AArch64::BFMLALB_ZZZ:
29102
    case AArch64::BFMLALT_ZZZ:
29103
    case AArch64::BFMLSLB_ZZZ_S:
29104
    case AArch64::BFMLSLT_ZZZ_S:
29105
    case AArch64::FDOT_ZZZ_BtoH:
29106
    case AArch64::FDOT_ZZZ_BtoS:
29107
    case AArch64::FDOT_ZZZ_S:
29108
    case AArch64::FMLALB_ZZZ:
29109
    case AArch64::FMLALB_ZZZ_SHH:
29110
    case AArch64::FMLALLBB_ZZZ:
29111
    case AArch64::FMLALLBT_ZZZ:
29112
    case AArch64::FMLALLTB_ZZZ:
29113
    case AArch64::FMLALLTT_ZZZ:
29114
    case AArch64::FMLALT_ZZZ:
29115
    case AArch64::FMLALT_ZZZ_SHH:
29116
    case AArch64::FMLSLB_ZZZ_SHH:
29117
    case AArch64::FMLSLT_ZZZ_SHH:
29118
    case AArch64::FMMLA_ZZZ_D:
29119
    case AArch64::FMMLA_ZZZ_S:
29120
    case AArch64::MLA_CPA:
29121
    case AArch64::SABALB_ZZZ_D:
29122
    case AArch64::SABALB_ZZZ_H:
29123
    case AArch64::SABALB_ZZZ_S:
29124
    case AArch64::SABALT_ZZZ_D:
29125
    case AArch64::SABALT_ZZZ_H:
29126
    case AArch64::SABALT_ZZZ_S:
29127
    case AArch64::SABA_ZZZ_B:
29128
    case AArch64::SABA_ZZZ_D:
29129
    case AArch64::SABA_ZZZ_H:
29130
    case AArch64::SABA_ZZZ_S:
29131
    case AArch64::SBCLB_ZZZ_D:
29132
    case AArch64::SBCLB_ZZZ_S:
29133
    case AArch64::SBCLT_ZZZ_D:
29134
    case AArch64::SBCLT_ZZZ_S:
29135
    case AArch64::SDOT_ZZZ_D:
29136
    case AArch64::SDOT_ZZZ_HtoS:
29137
    case AArch64::SDOT_ZZZ_S:
29138
    case AArch64::SMLALB_ZZZ_D:
29139
    case AArch64::SMLALB_ZZZ_H:
29140
    case AArch64::SMLALB_ZZZ_S:
29141
    case AArch64::SMLALT_ZZZ_D:
29142
    case AArch64::SMLALT_ZZZ_H:
29143
    case AArch64::SMLALT_ZZZ_S:
29144
    case AArch64::SMLSLB_ZZZ_D:
29145
    case AArch64::SMLSLB_ZZZ_H:
29146
    case AArch64::SMLSLB_ZZZ_S:
29147
    case AArch64::SMLSLT_ZZZ_D:
29148
    case AArch64::SMLSLT_ZZZ_H:
29149
    case AArch64::SMLSLT_ZZZ_S:
29150
    case AArch64::SMMLA_ZZZ:
29151
    case AArch64::SQDMLALBT_ZZZ_D:
29152
    case AArch64::SQDMLALBT_ZZZ_H:
29153
    case AArch64::SQDMLALBT_ZZZ_S:
29154
    case AArch64::SQDMLALB_ZZZ_D:
29155
    case AArch64::SQDMLALB_ZZZ_H:
29156
    case AArch64::SQDMLALB_ZZZ_S:
29157
    case AArch64::SQDMLALT_ZZZ_D:
29158
    case AArch64::SQDMLALT_ZZZ_H:
29159
    case AArch64::SQDMLALT_ZZZ_S:
29160
    case AArch64::SQDMLSLBT_ZZZ_D:
29161
    case AArch64::SQDMLSLBT_ZZZ_H:
29162
    case AArch64::SQDMLSLBT_ZZZ_S:
29163
    case AArch64::SQDMLSLB_ZZZ_D:
29164
    case AArch64::SQDMLSLB_ZZZ_H:
29165
    case AArch64::SQDMLSLB_ZZZ_S:
29166
    case AArch64::SQDMLSLT_ZZZ_D:
29167
    case AArch64::SQDMLSLT_ZZZ_H:
29168
    case AArch64::SQDMLSLT_ZZZ_S:
29169
    case AArch64::SQRDMLAH_ZZZ_B:
29170
    case AArch64::SQRDMLAH_ZZZ_D:
29171
    case AArch64::SQRDMLAH_ZZZ_H:
29172
    case AArch64::SQRDMLAH_ZZZ_S:
29173
    case AArch64::SQRDMLSH_ZZZ_B:
29174
    case AArch64::SQRDMLSH_ZZZ_D:
29175
    case AArch64::SQRDMLSH_ZZZ_H:
29176
    case AArch64::SQRDMLSH_ZZZ_S:
29177
    case AArch64::UABALB_ZZZ_D:
29178
    case AArch64::UABALB_ZZZ_H:
29179
    case AArch64::UABALB_ZZZ_S:
29180
    case AArch64::UABALT_ZZZ_D:
29181
    case AArch64::UABALT_ZZZ_H:
29182
    case AArch64::UABALT_ZZZ_S:
29183
    case AArch64::UABA_ZZZ_B:
29184
    case AArch64::UABA_ZZZ_D:
29185
    case AArch64::UABA_ZZZ_H:
29186
    case AArch64::UABA_ZZZ_S:
29187
    case AArch64::UDOT_ZZZ_D:
29188
    case AArch64::UDOT_ZZZ_HtoS:
29189
    case AArch64::UDOT_ZZZ_S:
29190
    case AArch64::UMLALB_ZZZ_D:
29191
    case AArch64::UMLALB_ZZZ_H:
29192
    case AArch64::UMLALB_ZZZ_S:
29193
    case AArch64::UMLALT_ZZZ_D:
29194
    case AArch64::UMLALT_ZZZ_H:
29195
    case AArch64::UMLALT_ZZZ_S:
29196
    case AArch64::UMLSLB_ZZZ_D:
29197
    case AArch64::UMLSLB_ZZZ_H:
29198
    case AArch64::UMLSLB_ZZZ_S:
29199
    case AArch64::UMLSLT_ZZZ_D:
29200
    case AArch64::UMLSLT_ZZZ_H:
29201
    case AArch64::UMLSLT_ZZZ_S:
29202
    case AArch64::UMMLA_ZZZ:
29203
    case AArch64::USDOT_ZZZ:
29204
    case AArch64::USMMLA_ZZZ: {
29205
      switch (OpNum) {
29206
      case 0:
29207
        // op: Zda
29208
        return 0;
29209
      case 2:
29210
        // op: Zn
29211
        return 5;
29212
      case 3:
29213
        // op: Zm
29214
        return 16;
29215
      }
29216
      break;
29217
    }
29218
    case AArch64::SRSRA_ZZI_B:
29219
    case AArch64::SRSRA_ZZI_D:
29220
    case AArch64::SRSRA_ZZI_H:
29221
    case AArch64::SRSRA_ZZI_S:
29222
    case AArch64::SSRA_ZZI_B:
29223
    case AArch64::SSRA_ZZI_D:
29224
    case AArch64::SSRA_ZZI_H:
29225
    case AArch64::SSRA_ZZI_S:
29226
    case AArch64::URSRA_ZZI_B:
29227
    case AArch64::URSRA_ZZI_D:
29228
    case AArch64::URSRA_ZZI_H:
29229
    case AArch64::URSRA_ZZI_S:
29230
    case AArch64::USRA_ZZI_B:
29231
    case AArch64::USRA_ZZI_D:
29232
    case AArch64::USRA_ZZI_H:
29233
    case AArch64::USRA_ZZI_S: {
29234
      switch (OpNum) {
29235
      case 0:
29236
        // op: Zda
29237
        return 0;
29238
      case 2:
29239
        // op: Zn
29240
        return 5;
29241
      case 3:
29242
        // op: imm
29243
        return 16;
29244
      }
29245
      break;
29246
    }
29247
    case AArch64::SDOT_ZZZI_S:
29248
    case AArch64::UDOT_ZZZI_S: {
29249
      switch (OpNum) {
29250
      case 0:
29251
        // op: Zda
29252
        return 0;
29253
      case 2:
29254
        // op: Zn
29255
        return 5;
29256
      case 4:
29257
        // op: iop
29258
        return 19;
29259
      case 3:
29260
        // op: Zm
29261
        return 16;
29262
      }
29263
      break;
29264
    }
29265
    case AArch64::SDOT_ZZZI_D:
29266
    case AArch64::UDOT_ZZZI_D: {
29267
      switch (OpNum) {
29268
      case 0:
29269
        // op: Zda
29270
        return 0;
29271
      case 2:
29272
        // op: Zn
29273
        return 5;
29274
      case 4:
29275
        // op: iop
29276
        return 20;
29277
      case 3:
29278
        // op: Zm
29279
        return 16;
29280
      }
29281
      break;
29282
    }
29283
    case AArch64::FCMLA_ZZZI_H: {
29284
      switch (OpNum) {
29285
      case 0:
29286
        // op: Zda
29287
        return 0;
29288
      case 2:
29289
        // op: Zn
29290
        return 5;
29291
      case 5:
29292
        // op: imm
29293
        return 10;
29294
      case 3:
29295
        // op: Zm
29296
        return 16;
29297
      case 4:
29298
        // op: iop
29299
        return 19;
29300
      }
29301
      break;
29302
    }
29303
    case AArch64::FCMLA_ZZZI_S: {
29304
      switch (OpNum) {
29305
      case 0:
29306
        // op: Zda
29307
        return 0;
29308
      case 2:
29309
        // op: Zn
29310
        return 5;
29311
      case 5:
29312
        // op: imm
29313
        return 10;
29314
      case 3:
29315
        // op: Zm
29316
        return 16;
29317
      case 4:
29318
        // op: iop
29319
        return 20;
29320
      }
29321
      break;
29322
    }
29323
    case AArch64::CDOT_ZZZI_S:
29324
    case AArch64::CMLA_ZZZI_H:
29325
    case AArch64::SQRDCMLAH_ZZZI_H: {
29326
      switch (OpNum) {
29327
      case 0:
29328
        // op: Zda
29329
        return 0;
29330
      case 2:
29331
        // op: Zn
29332
        return 5;
29333
      case 5:
29334
        // op: rot
29335
        return 10;
29336
      case 4:
29337
        // op: iop
29338
        return 19;
29339
      case 3:
29340
        // op: Zm
29341
        return 16;
29342
      }
29343
      break;
29344
    }
29345
    case AArch64::CDOT_ZZZI_D:
29346
    case AArch64::CMLA_ZZZI_S:
29347
    case AArch64::SQRDCMLAH_ZZZI_S: {
29348
      switch (OpNum) {
29349
      case 0:
29350
        // op: Zda
29351
        return 0;
29352
      case 2:
29353
        // op: Zn
29354
        return 5;
29355
      case 5:
29356
        // op: rot
29357
        return 10;
29358
      case 4:
29359
        // op: iop
29360
        return 20;
29361
      case 3:
29362
        // op: Zm
29363
        return 16;
29364
      }
29365
      break;
29366
    }
29367
    case AArch64::MAD_CPA: {
29368
      switch (OpNum) {
29369
      case 0:
29370
        // op: Zdn
29371
        return 0;
29372
      case 2:
29373
        // op: Zm
29374
        return 16;
29375
      case 3:
29376
        // op: Za
29377
        return 5;
29378
      }
29379
      break;
29380
    }
29381
    case AArch64::XAR_ZZZI_B:
29382
    case AArch64::XAR_ZZZI_D:
29383
    case AArch64::XAR_ZZZI_H:
29384
    case AArch64::XAR_ZZZI_S: {
29385
      switch (OpNum) {
29386
      case 0:
29387
        // op: Zdn
29388
        return 0;
29389
      case 2:
29390
        // op: Zm
29391
        return 5;
29392
      case 3:
29393
        // op: imm
29394
        return 16;
29395
      }
29396
      break;
29397
    }
29398
    case AArch64::FTMAD_ZZI_D:
29399
    case AArch64::FTMAD_ZZI_H:
29400
    case AArch64::FTMAD_ZZI_S: {
29401
      switch (OpNum) {
29402
      case 0:
29403
        // op: Zdn
29404
        return 0;
29405
      case 2:
29406
        // op: Zm
29407
        return 5;
29408
      case 3:
29409
        // op: imm3
29410
        return 16;
29411
      }
29412
      break;
29413
    }
29414
    case AArch64::EXTQ_ZZI: {
29415
      switch (OpNum) {
29416
      case 0:
29417
        // op: Zdn
29418
        return 0;
29419
      case 2:
29420
        // op: Zm
29421
        return 5;
29422
      case 3:
29423
        // op: imm4
29424
        return 16;
29425
      }
29426
      break;
29427
    }
29428
    case AArch64::EXT_ZZI: {
29429
      switch (OpNum) {
29430
      case 0:
29431
        // op: Zdn
29432
        return 0;
29433
      case 2:
29434
        // op: Zm
29435
        return 5;
29436
      case 3:
29437
        // op: imm8
29438
        return 10;
29439
      }
29440
      break;
29441
    }
29442
    case AArch64::CADD_ZZI_B:
29443
    case AArch64::CADD_ZZI_D:
29444
    case AArch64::CADD_ZZI_H:
29445
    case AArch64::CADD_ZZI_S:
29446
    case AArch64::SQCADD_ZZI_B:
29447
    case AArch64::SQCADD_ZZI_D:
29448
    case AArch64::SQCADD_ZZI_H:
29449
    case AArch64::SQCADD_ZZI_S: {
29450
      switch (OpNum) {
29451
      case 0:
29452
        // op: Zdn
29453
        return 0;
29454
      case 2:
29455
        // op: Zm
29456
        return 5;
29457
      case 3:
29458
        // op: rot
29459
        return 10;
29460
      }
29461
      break;
29462
    }
29463
    case AArch64::AESD_ZZZ_B:
29464
    case AArch64::AESE_ZZZ_B:
29465
    case AArch64::SM4E_ZZZ_S: {
29466
      switch (OpNum) {
29467
      case 0:
29468
        // op: Zdn
29469
        return 0;
29470
      case 2:
29471
        // op: Zm
29472
        return 5;
29473
      }
29474
      break;
29475
    }
29476
    case AArch64::ADD_ZI_B:
29477
    case AArch64::ADD_ZI_D:
29478
    case AArch64::ADD_ZI_H:
29479
    case AArch64::ADD_ZI_S:
29480
    case AArch64::MUL_ZI_B:
29481
    case AArch64::MUL_ZI_D:
29482
    case AArch64::MUL_ZI_H:
29483
    case AArch64::MUL_ZI_S:
29484
    case AArch64::SMAX_ZI_B:
29485
    case AArch64::SMAX_ZI_D:
29486
    case AArch64::SMAX_ZI_H:
29487
    case AArch64::SMAX_ZI_S:
29488
    case AArch64::SMIN_ZI_B:
29489
    case AArch64::SMIN_ZI_D:
29490
    case AArch64::SMIN_ZI_H:
29491
    case AArch64::SMIN_ZI_S:
29492
    case AArch64::SQADD_ZI_B:
29493
    case AArch64::SQADD_ZI_D:
29494
    case AArch64::SQADD_ZI_H:
29495
    case AArch64::SQADD_ZI_S:
29496
    case AArch64::SQSUB_ZI_B:
29497
    case AArch64::SQSUB_ZI_D:
29498
    case AArch64::SQSUB_ZI_H:
29499
    case AArch64::SQSUB_ZI_S:
29500
    case AArch64::SUBR_ZI_B:
29501
    case AArch64::SUBR_ZI_D:
29502
    case AArch64::SUBR_ZI_H:
29503
    case AArch64::SUBR_ZI_S:
29504
    case AArch64::SUB_ZI_B:
29505
    case AArch64::SUB_ZI_D:
29506
    case AArch64::SUB_ZI_H:
29507
    case AArch64::SUB_ZI_S:
29508
    case AArch64::UMAX_ZI_B:
29509
    case AArch64::UMAX_ZI_D:
29510
    case AArch64::UMAX_ZI_H:
29511
    case AArch64::UMAX_ZI_S:
29512
    case AArch64::UMIN_ZI_B:
29513
    case AArch64::UMIN_ZI_D:
29514
    case AArch64::UMIN_ZI_H:
29515
    case AArch64::UMIN_ZI_S:
29516
    case AArch64::UQADD_ZI_B:
29517
    case AArch64::UQADD_ZI_D:
29518
    case AArch64::UQADD_ZI_H:
29519
    case AArch64::UQADD_ZI_S:
29520
    case AArch64::UQSUB_ZI_B:
29521
    case AArch64::UQSUB_ZI_D:
29522
    case AArch64::UQSUB_ZI_H:
29523
    case AArch64::UQSUB_ZI_S: {
29524
      switch (OpNum) {
29525
      case 0:
29526
        // op: Zdn
29527
        return 0;
29528
      case 2:
29529
        // op: imm
29530
        return 5;
29531
      }
29532
      break;
29533
    }
29534
    case AArch64::AND_ZI:
29535
    case AArch64::EOR_ZI:
29536
    case AArch64::ORR_ZI: {
29537
      switch (OpNum) {
29538
      case 0:
29539
        // op: Zdn
29540
        return 0;
29541
      case 2:
29542
        // op: imms13
29543
        return 5;
29544
      }
29545
      break;
29546
    }
29547
    case AArch64::DECD_ZPiI:
29548
    case AArch64::DECH_ZPiI:
29549
    case AArch64::DECW_ZPiI:
29550
    case AArch64::INCD_ZPiI:
29551
    case AArch64::INCH_ZPiI:
29552
    case AArch64::INCW_ZPiI:
29553
    case AArch64::SQDECD_ZPiI:
29554
    case AArch64::SQDECH_ZPiI:
29555
    case AArch64::SQDECW_ZPiI:
29556
    case AArch64::SQINCD_ZPiI:
29557
    case AArch64::SQINCH_ZPiI:
29558
    case AArch64::SQINCW_ZPiI:
29559
    case AArch64::UQDECD_ZPiI:
29560
    case AArch64::UQDECH_ZPiI:
29561
    case AArch64::UQDECW_ZPiI:
29562
    case AArch64::UQINCD_ZPiI:
29563
    case AArch64::UQINCH_ZPiI:
29564
    case AArch64::UQINCW_ZPiI: {
29565
      switch (OpNum) {
29566
      case 0:
29567
        // op: Zdn
29568
        return 0;
29569
      case 2:
29570
        // op: pattern
29571
        return 5;
29572
      case 3:
29573
        // op: imm4
29574
        return 16;
29575
      }
29576
      break;
29577
    }
29578
    case AArch64::BCAX_ZZZZ:
29579
    case AArch64::BSL1N_ZZZZ:
29580
    case AArch64::BSL2N_ZZZZ:
29581
    case AArch64::BSL_ZZZZ:
29582
    case AArch64::EOR3_ZZZZ:
29583
    case AArch64::NBSL_ZZZZ: {
29584
      switch (OpNum) {
29585
      case 0:
29586
        // op: Zdn
29587
        return 0;
29588
      case 3:
29589
        // op: Zk
29590
        return 5;
29591
      case 2:
29592
        // op: Zm
29593
        return 16;
29594
      }
29595
      break;
29596
    }
29597
    case AArch64::FCADD_ZPmZ_D:
29598
    case AArch64::FCADD_ZPmZ_H:
29599
    case AArch64::FCADD_ZPmZ_S: {
29600
      switch (OpNum) {
29601
      case 0:
29602
        // op: Zdn
29603
        return 0;
29604
      case 3:
29605
        // op: Zm
29606
        return 5;
29607
      case 1:
29608
        // op: Pg
29609
        return 10;
29610
      case 4:
29611
        // op: imm
29612
        return 16;
29613
      }
29614
      break;
29615
    }
29616
    case AArch64::AESIMC_ZZ_B:
29617
    case AArch64::AESMC_ZZ_B: {
29618
      switch (OpNum) {
29619
      case 0:
29620
        // op: Zdn
29621
        return 0;
29622
      }
29623
      break;
29624
    }
29625
    case AArch64::LD1RO_B:
29626
    case AArch64::LD1RO_D:
29627
    case AArch64::LD1RO_H:
29628
    case AArch64::LD1RO_W:
29629
    case AArch64::LD1RQ_B:
29630
    case AArch64::LD1RQ_D:
29631
    case AArch64::LD1RQ_H:
29632
    case AArch64::LD1RQ_W: {
29633
      switch (OpNum) {
29634
      case 0:
29635
        // op: Zt
29636
        return 0;
29637
      case 1:
29638
        // op: Pg
29639
        return 10;
29640
      case 2:
29641
        // op: Rn
29642
        return 5;
29643
      case 3:
29644
        // op: Rm
29645
        return 16;
29646
      }
29647
      break;
29648
    }
29649
    case AArch64::LD2B_IMM:
29650
    case AArch64::LD2D_IMM:
29651
    case AArch64::LD2H_IMM:
29652
    case AArch64::LD2Q_IMM:
29653
    case AArch64::LD2W_IMM:
29654
    case AArch64::LD3B_IMM:
29655
    case AArch64::LD3D_IMM:
29656
    case AArch64::LD3H_IMM:
29657
    case AArch64::LD3Q_IMM:
29658
    case AArch64::LD3W_IMM:
29659
    case AArch64::LD4B_IMM:
29660
    case AArch64::LD4D_IMM:
29661
    case AArch64::LD4H_IMM:
29662
    case AArch64::LD4Q_IMM:
29663
    case AArch64::LD4W_IMM:
29664
    case AArch64::LDNT1B_ZRI:
29665
    case AArch64::LDNT1D_ZRI:
29666
    case AArch64::LDNT1H_ZRI:
29667
    case AArch64::LDNT1W_ZRI: {
29668
      switch (OpNum) {
29669
      case 0:
29670
        // op: Zt
29671
        return 0;
29672
      case 1:
29673
        // op: Pg
29674
        return 10;
29675
      case 2:
29676
        // op: Rn
29677
        return 5;
29678
      case 3:
29679
        // op: imm4
29680
        return 16;
29681
      }
29682
      break;
29683
    }
29684
    case AArch64::LD1B:
29685
    case AArch64::LD1B_D:
29686
    case AArch64::LD1B_H:
29687
    case AArch64::LD1B_S:
29688
    case AArch64::LD1D:
29689
    case AArch64::LD1H:
29690
    case AArch64::LD1H_D:
29691
    case AArch64::LD1H_S:
29692
    case AArch64::LD1SB_D:
29693
    case AArch64::LD1SB_H:
29694
    case AArch64::LD1SB_S:
29695
    case AArch64::LD1SH_D:
29696
    case AArch64::LD1SH_S:
29697
    case AArch64::LD1SW_D:
29698
    case AArch64::LD1W:
29699
    case AArch64::LD1W_D:
29700
    case AArch64::LDFF1B_D_REAL:
29701
    case AArch64::LDFF1B_H_REAL:
29702
    case AArch64::LDFF1B_REAL:
29703
    case AArch64::LDFF1B_S_REAL:
29704
    case AArch64::LDFF1D_REAL:
29705
    case AArch64::LDFF1H_D_REAL:
29706
    case AArch64::LDFF1H_REAL:
29707
    case AArch64::LDFF1H_S_REAL:
29708
    case AArch64::LDFF1SB_D_REAL:
29709
    case AArch64::LDFF1SB_H_REAL:
29710
    case AArch64::LDFF1SB_S_REAL:
29711
    case AArch64::LDFF1SH_D_REAL:
29712
    case AArch64::LDFF1SH_S_REAL:
29713
    case AArch64::LDFF1SW_D_REAL:
29714
    case AArch64::LDFF1W_D_REAL:
29715
    case AArch64::LDFF1W_REAL: {
29716
      switch (OpNum) {
29717
      case 0:
29718
        // op: Zt
29719
        return 0;
29720
      case 1:
29721
        // op: Pg
29722
        return 10;
29723
      case 3:
29724
        // op: Rm
29725
        return 16;
29726
      case 2:
29727
        // op: Rn
29728
        return 5;
29729
      }
29730
      break;
29731
    }
29732
    case AArch64::LD1D_Q:
29733
    case AArch64::LD1W_Q:
29734
    case AArch64::ST2Q:
29735
    case AArch64::ST3Q:
29736
    case AArch64::ST4Q: {
29737
      switch (OpNum) {
29738
      case 0:
29739
        // op: Zt
29740
        return 0;
29741
      case 2:
29742
        // op: Rn
29743
        return 5;
29744
      case 1:
29745
        // op: Pg
29746
        return 10;
29747
      case 3:
29748
        // op: Rm
29749
        return 16;
29750
      }
29751
      break;
29752
    }
29753
    case AArch64::LD1D_Q_IMM:
29754
    case AArch64::LD1RO_B_IMM:
29755
    case AArch64::LD1RO_D_IMM:
29756
    case AArch64::LD1RO_H_IMM:
29757
    case AArch64::LD1RO_W_IMM:
29758
    case AArch64::LD1RQ_B_IMM:
29759
    case AArch64::LD1RQ_D_IMM:
29760
    case AArch64::LD1RQ_H_IMM:
29761
    case AArch64::LD1RQ_W_IMM:
29762
    case AArch64::LD1W_Q_IMM:
29763
    case AArch64::ST2Q_IMM:
29764
    case AArch64::ST3Q_IMM:
29765
    case AArch64::ST4Q_IMM: {
29766
      switch (OpNum) {
29767
      case 0:
29768
        // op: Zt
29769
        return 0;
29770
      case 2:
29771
        // op: Rn
29772
        return 5;
29773
      case 1:
29774
        // op: Pg
29775
        return 10;
29776
      case 3:
29777
        // op: imm4
29778
        return 16;
29779
      }
29780
      break;
29781
    }
29782
    case AArch64::GLD1Q:
29783
    case AArch64::SST1Q: {
29784
      switch (OpNum) {
29785
      case 0:
29786
        // op: Zt
29787
        return 0;
29788
      case 2:
29789
        // op: Zn
29790
        return 5;
29791
      case 1:
29792
        // op: Pg
29793
        return 10;
29794
      case 3:
29795
        // op: Rm
29796
        return 16;
29797
      }
29798
      break;
29799
    }
29800
    case AArch64::LD1B_2Z_IMM:
29801
    case AArch64::LD1D_2Z_IMM:
29802
    case AArch64::LD1H_2Z_IMM:
29803
    case AArch64::LD1W_2Z_IMM:
29804
    case AArch64::LDNT1B_2Z_IMM:
29805
    case AArch64::LDNT1D_2Z_IMM:
29806
    case AArch64::LDNT1H_2Z_IMM:
29807
    case AArch64::LDNT1W_2Z_IMM:
29808
    case AArch64::ST1B_2Z_IMM:
29809
    case AArch64::ST1D_2Z_IMM:
29810
    case AArch64::ST1H_2Z_IMM:
29811
    case AArch64::ST1W_2Z_IMM:
29812
    case AArch64::STNT1B_2Z_IMM:
29813
    case AArch64::STNT1D_2Z_IMM:
29814
    case AArch64::STNT1H_2Z_IMM:
29815
    case AArch64::STNT1W_2Z_IMM: {
29816
      switch (OpNum) {
29817
      case 0:
29818
        // op: Zt
29819
        return 1;
29820
      case 2:
29821
        // op: Rn
29822
        return 5;
29823
      case 1:
29824
        // op: PNg
29825
        return 10;
29826
      case 3:
29827
        // op: imm4
29828
        return 16;
29829
      }
29830
      break;
29831
    }
29832
    case AArch64::LD1B_2Z:
29833
    case AArch64::LD1D_2Z:
29834
    case AArch64::LD1H_2Z:
29835
    case AArch64::LD1W_2Z:
29836
    case AArch64::LDNT1B_2Z:
29837
    case AArch64::LDNT1D_2Z:
29838
    case AArch64::LDNT1H_2Z:
29839
    case AArch64::LDNT1W_2Z:
29840
    case AArch64::ST1B_2Z:
29841
    case AArch64::ST1D_2Z:
29842
    case AArch64::ST1H_2Z:
29843
    case AArch64::ST1W_2Z:
29844
    case AArch64::STNT1B_2Z:
29845
    case AArch64::STNT1D_2Z:
29846
    case AArch64::STNT1H_2Z:
29847
    case AArch64::STNT1W_2Z: {
29848
      switch (OpNum) {
29849
      case 0:
29850
        // op: Zt
29851
        return 1;
29852
      case 3:
29853
        // op: Rm
29854
        return 16;
29855
      case 2:
29856
        // op: Rn
29857
        return 5;
29858
      case 1:
29859
        // op: PNg
29860
        return 10;
29861
      }
29862
      break;
29863
    }
29864
    case AArch64::LD1B_4Z_IMM:
29865
    case AArch64::LD1D_4Z_IMM:
29866
    case AArch64::LD1H_4Z_IMM:
29867
    case AArch64::LD1W_4Z_IMM:
29868
    case AArch64::LDNT1B_4Z_IMM:
29869
    case AArch64::LDNT1D_4Z_IMM:
29870
    case AArch64::LDNT1H_4Z_IMM:
29871
    case AArch64::LDNT1W_4Z_IMM:
29872
    case AArch64::ST1B_4Z_IMM:
29873
    case AArch64::ST1D_4Z_IMM:
29874
    case AArch64::ST1H_4Z_IMM:
29875
    case AArch64::ST1W_4Z_IMM:
29876
    case AArch64::STNT1B_4Z_IMM:
29877
    case AArch64::STNT1D_4Z_IMM:
29878
    case AArch64::STNT1H_4Z_IMM:
29879
    case AArch64::STNT1W_4Z_IMM: {
29880
      switch (OpNum) {
29881
      case 0:
29882
        // op: Zt
29883
        return 2;
29884
      case 2:
29885
        // op: Rn
29886
        return 5;
29887
      case 1:
29888
        // op: PNg
29889
        return 10;
29890
      case 3:
29891
        // op: imm4
29892
        return 16;
29893
      }
29894
      break;
29895
    }
29896
    case AArch64::LD1B_4Z:
29897
    case AArch64::LD1D_4Z:
29898
    case AArch64::LD1H_4Z:
29899
    case AArch64::LD1W_4Z:
29900
    case AArch64::LDNT1B_4Z:
29901
    case AArch64::LDNT1D_4Z:
29902
    case AArch64::LDNT1H_4Z:
29903
    case AArch64::LDNT1W_4Z:
29904
    case AArch64::ST1B_4Z:
29905
    case AArch64::ST1D_4Z:
29906
    case AArch64::ST1H_4Z:
29907
    case AArch64::ST1W_4Z:
29908
    case AArch64::STNT1B_4Z:
29909
    case AArch64::STNT1D_4Z:
29910
    case AArch64::STNT1H_4Z:
29911
    case AArch64::STNT1W_4Z: {
29912
      switch (OpNum) {
29913
      case 0:
29914
        // op: Zt
29915
        return 2;
29916
      case 3:
29917
        // op: Rm
29918
        return 16;
29919
      case 2:
29920
        // op: Rn
29921
        return 5;
29922
      case 1:
29923
        // op: PNg
29924
        return 10;
29925
      }
29926
      break;
29927
    }
29928
    case AArch64::B:
29929
    case AArch64::BL: {
29930
      switch (OpNum) {
29931
      case 0:
29932
        // op: addr
29933
        return 0;
29934
      }
29935
      break;
29936
    }
29937
    case AArch64::BCcc:
29938
    case AArch64::Bcc: {
29939
      switch (OpNum) {
29940
      case 0:
29941
        // op: cond
29942
        return 0;
29943
      case 1:
29944
        // op: target
29945
        return 5;
29946
      }
29947
      break;
29948
    }
29949
    case AArch64::DUPi8: {
29950
      switch (OpNum) {
29951
      case 0:
29952
        // op: dst
29953
        return 0;
29954
      case 1:
29955
        // op: src
29956
        return 5;
29957
      case 2:
29958
        // op: idx
29959
        return 17;
29960
      }
29961
      break;
29962
    }
29963
    case AArch64::DUPi16: {
29964
      switch (OpNum) {
29965
      case 0:
29966
        // op: dst
29967
        return 0;
29968
      case 1:
29969
        // op: src
29970
        return 5;
29971
      case 2:
29972
        // op: idx
29973
        return 18;
29974
      }
29975
      break;
29976
    }
29977
    case AArch64::DUPi32: {
29978
      switch (OpNum) {
29979
      case 0:
29980
        // op: dst
29981
        return 0;
29982
      case 1:
29983
        // op: src
29984
        return 5;
29985
      case 2:
29986
        // op: idx
29987
        return 19;
29988
      }
29989
      break;
29990
    }
29991
    case AArch64::DUPi64: {
29992
      switch (OpNum) {
29993
      case 0:
29994
        // op: dst
29995
        return 0;
29996
      case 1:
29997
        // op: src
29998
        return 5;
29999
      case 2:
30000
        // op: idx
30001
        return 20;
30002
      }
30003
      break;
30004
    }
30005
    case AArch64::UDF:
30006
    case AArch64::ZERO_M: {
30007
      switch (OpNum) {
30008
      case 0:
30009
        // op: imm
30010
        return 0;
30011
      }
30012
      break;
30013
    }
30014
    case AArch64::BRK:
30015
    case AArch64::DCPS1:
30016
    case AArch64::DCPS2:
30017
    case AArch64::DCPS3:
30018
    case AArch64::HINT:
30019
    case AArch64::HLT:
30020
    case AArch64::HVC:
30021
    case AArch64::SMC:
30022
    case AArch64::SVC:
30023
    case AArch64::TCANCEL: {
30024
      switch (OpNum) {
30025
      case 0:
30026
        // op: imm
30027
        return 5;
30028
      }
30029
      break;
30030
    }
30031
    case AArch64::AUTIASPPCi:
30032
    case AArch64::AUTIBSPPCi:
30033
    case AArch64::RETAASPPCi:
30034
    case AArch64::RETABSPPCi: {
30035
      switch (OpNum) {
30036
      case 0:
30037
        // op: label
30038
        return 5;
30039
      }
30040
      break;
30041
    }
30042
    case AArch64::SYSPxt_XZR: {
30043
      switch (OpNum) {
30044
      case 0:
30045
        // op: op1
30046
        return 16;
30047
      case 1:
30048
        // op: Cn
30049
        return 12;
30050
      case 2:
30051
        // op: Cm
30052
        return 8;
30053
      case 3:
30054
        // op: op2
30055
        return 5;
30056
      }
30057
      break;
30058
    }
30059
    case AArch64::MSRpstateImm1:
30060
    case AArch64::MSRpstateImm4: {
30061
      switch (OpNum) {
30062
      case 0:
30063
        // op: pstatefield
30064
        return 5;
30065
      case 1:
30066
        // op: imm
30067
        return 8;
30068
      }
30069
      break;
30070
    }
30071
    case AArch64::MSRpstatesvcrImm1: {
30072
      switch (OpNum) {
30073
      case 0:
30074
        // op: pstatefield
30075
        return 9;
30076
      case 1:
30077
        // op: imm
30078
        return 8;
30079
      }
30080
      break;
30081
    }
30082
    case AArch64::SEL_VG2_2ZC2Z2Z_B:
30083
    case AArch64::SEL_VG2_2ZC2Z2Z_D:
30084
    case AArch64::SEL_VG2_2ZC2Z2Z_H:
30085
    case AArch64::SEL_VG2_2ZC2Z2Z_S: {
30086
      switch (OpNum) {
30087
      case 1:
30088
        // op: PNg
30089
        return 10;
30090
      case 3:
30091
        // op: Zm
30092
        return 17;
30093
      case 2:
30094
        // op: Zn
30095
        return 6;
30096
      case 0:
30097
        // op: Zd
30098
        return 1;
30099
      }
30100
      break;
30101
    }
30102
    case AArch64::SEL_VG4_4ZC4Z4Z_B:
30103
    case AArch64::SEL_VG4_4ZC4Z4Z_D:
30104
    case AArch64::SEL_VG4_4ZC4Z4Z_H:
30105
    case AArch64::SEL_VG4_4ZC4Z4Z_S: {
30106
      switch (OpNum) {
30107
      case 1:
30108
        // op: PNg
30109
        return 10;
30110
      case 3:
30111
        // op: Zm
30112
        return 18;
30113
      case 2:
30114
        // op: Zn
30115
        return 7;
30116
      case 0:
30117
        // op: Zd
30118
        return 2;
30119
      }
30120
      break;
30121
    }
30122
    case AArch64::LASTA_RPZ_B:
30123
    case AArch64::LASTA_RPZ_D:
30124
    case AArch64::LASTA_RPZ_H:
30125
    case AArch64::LASTA_RPZ_S:
30126
    case AArch64::LASTB_RPZ_B:
30127
    case AArch64::LASTB_RPZ_D:
30128
    case AArch64::LASTB_RPZ_H:
30129
    case AArch64::LASTB_RPZ_S: {
30130
      switch (OpNum) {
30131
      case 1:
30132
        // op: Pg
30133
        return 10;
30134
      case 0:
30135
        // op: Rd
30136
        return 0;
30137
      case 2:
30138
        // op: Zn
30139
        return 5;
30140
      }
30141
      break;
30142
    }
30143
    case AArch64::CLASTA_RPZ_B:
30144
    case AArch64::CLASTA_RPZ_D:
30145
    case AArch64::CLASTA_RPZ_H:
30146
    case AArch64::CLASTA_RPZ_S:
30147
    case AArch64::CLASTB_RPZ_B:
30148
    case AArch64::CLASTB_RPZ_D:
30149
    case AArch64::CLASTB_RPZ_H:
30150
    case AArch64::CLASTB_RPZ_S: {
30151
      switch (OpNum) {
30152
      case 1:
30153
        // op: Pg
30154
        return 10;
30155
      case 0:
30156
        // op: Rdn
30157
        return 0;
30158
      case 3:
30159
        // op: Zm
30160
        return 5;
30161
      }
30162
      break;
30163
    }
30164
    case AArch64::ANDV_VPZ_B:
30165
    case AArch64::ANDV_VPZ_D:
30166
    case AArch64::ANDV_VPZ_H:
30167
    case AArch64::ANDV_VPZ_S:
30168
    case AArch64::EORV_VPZ_B:
30169
    case AArch64::EORV_VPZ_D:
30170
    case AArch64::EORV_VPZ_H:
30171
    case AArch64::EORV_VPZ_S:
30172
    case AArch64::LASTA_VPZ_B:
30173
    case AArch64::LASTA_VPZ_D:
30174
    case AArch64::LASTA_VPZ_H:
30175
    case AArch64::LASTA_VPZ_S:
30176
    case AArch64::LASTB_VPZ_B:
30177
    case AArch64::LASTB_VPZ_D:
30178
    case AArch64::LASTB_VPZ_H:
30179
    case AArch64::LASTB_VPZ_S:
30180
    case AArch64::ORV_VPZ_B:
30181
    case AArch64::ORV_VPZ_D:
30182
    case AArch64::ORV_VPZ_H:
30183
    case AArch64::ORV_VPZ_S:
30184
    case AArch64::SADDV_VPZ_B:
30185
    case AArch64::SADDV_VPZ_H:
30186
    case AArch64::SADDV_VPZ_S:
30187
    case AArch64::SMAXV_VPZ_B:
30188
    case AArch64::SMAXV_VPZ_D:
30189
    case AArch64::SMAXV_VPZ_H:
30190
    case AArch64::SMAXV_VPZ_S:
30191
    case AArch64::SMINV_VPZ_B:
30192
    case AArch64::SMINV_VPZ_D:
30193
    case AArch64::SMINV_VPZ_H:
30194
    case AArch64::SMINV_VPZ_S:
30195
    case AArch64::UADDV_VPZ_B:
30196
    case AArch64::UADDV_VPZ_D:
30197
    case AArch64::UADDV_VPZ_H:
30198
    case AArch64::UADDV_VPZ_S:
30199
    case AArch64::UMAXV_VPZ_B:
30200
    case AArch64::UMAXV_VPZ_D:
30201
    case AArch64::UMAXV_VPZ_H:
30202
    case AArch64::UMAXV_VPZ_S:
30203
    case AArch64::UMINV_VPZ_B:
30204
    case AArch64::UMINV_VPZ_D:
30205
    case AArch64::UMINV_VPZ_H:
30206
    case AArch64::UMINV_VPZ_S: {
30207
      switch (OpNum) {
30208
      case 1:
30209
        // op: Pg
30210
        return 10;
30211
      case 0:
30212
        // op: Vd
30213
        return 0;
30214
      case 2:
30215
        // op: Zn
30216
        return 5;
30217
      }
30218
      break;
30219
    }
30220
    case AArch64::CLASTA_VPZ_B:
30221
    case AArch64::CLASTA_VPZ_D:
30222
    case AArch64::CLASTA_VPZ_H:
30223
    case AArch64::CLASTA_VPZ_S:
30224
    case AArch64::CLASTB_VPZ_B:
30225
    case AArch64::CLASTB_VPZ_D:
30226
    case AArch64::CLASTB_VPZ_H:
30227
    case AArch64::CLASTB_VPZ_S:
30228
    case AArch64::FADDA_VPZ_D:
30229
    case AArch64::FADDA_VPZ_H:
30230
    case AArch64::FADDA_VPZ_S: {
30231
      switch (OpNum) {
30232
      case 1:
30233
        // op: Pg
30234
        return 10;
30235
      case 0:
30236
        // op: Vdn
30237
        return 0;
30238
      case 3:
30239
        // op: Zm
30240
        return 5;
30241
      }
30242
      break;
30243
    }
30244
    case AArch64::COMPACT_ZPZ_D:
30245
    case AArch64::COMPACT_ZPZ_S:
30246
    case AArch64::MOVPRFX_ZPzZ_B:
30247
    case AArch64::MOVPRFX_ZPzZ_D:
30248
    case AArch64::MOVPRFX_ZPzZ_H:
30249
    case AArch64::MOVPRFX_ZPzZ_S: {
30250
      switch (OpNum) {
30251
      case 1:
30252
        // op: Pg
30253
        return 10;
30254
      case 0:
30255
        // op: Zd
30256
        return 0;
30257
      case 2:
30258
        // op: Zn
30259
        return 5;
30260
      }
30261
      break;
30262
    }
30263
    case AArch64::SEL_ZPZZ_B:
30264
    case AArch64::SEL_ZPZZ_D:
30265
    case AArch64::SEL_ZPZZ_H:
30266
    case AArch64::SEL_ZPZZ_S: {
30267
      switch (OpNum) {
30268
      case 1:
30269
        // op: Pg
30270
        return 10;
30271
      case 0:
30272
        // op: Zd
30273
        return 0;
30274
      case 3:
30275
        // op: Zm
30276
        return 16;
30277
      case 2:
30278
        // op: Zn
30279
        return 5;
30280
      }
30281
      break;
30282
    }
30283
    case AArch64::BFMLA_ZPmZZ:
30284
    case AArch64::BFMLS_ZPmZZ:
30285
    case AArch64::FMLA_ZPmZZ_D:
30286
    case AArch64::FMLA_ZPmZZ_H:
30287
    case AArch64::FMLA_ZPmZZ_S:
30288
    case AArch64::FMLS_ZPmZZ_D:
30289
    case AArch64::FMLS_ZPmZZ_H:
30290
    case AArch64::FMLS_ZPmZZ_S:
30291
    case AArch64::FNMLA_ZPmZZ_D:
30292
    case AArch64::FNMLA_ZPmZZ_H:
30293
    case AArch64::FNMLA_ZPmZZ_S:
30294
    case AArch64::FNMLS_ZPmZZ_D:
30295
    case AArch64::FNMLS_ZPmZZ_H:
30296
    case AArch64::FNMLS_ZPmZZ_S:
30297
    case AArch64::MLA_ZPmZZ_B:
30298
    case AArch64::MLA_ZPmZZ_D:
30299
    case AArch64::MLA_ZPmZZ_H:
30300
    case AArch64::MLA_ZPmZZ_S:
30301
    case AArch64::MLS_ZPmZZ_B:
30302
    case AArch64::MLS_ZPmZZ_D:
30303
    case AArch64::MLS_ZPmZZ_H:
30304
    case AArch64::MLS_ZPmZZ_S: {
30305
      switch (OpNum) {
30306
      case 1:
30307
        // op: Pg
30308
        return 10;
30309
      case 0:
30310
        // op: Zda
30311
        return 0;
30312
      case 4:
30313
        // op: Zm
30314
        return 16;
30315
      case 3:
30316
        // op: Zn
30317
        return 5;
30318
      }
30319
      break;
30320
    }
30321
    case AArch64::ADD_ZPmZ_B:
30322
    case AArch64::ADD_ZPmZ_CPA:
30323
    case AArch64::ADD_ZPmZ_D:
30324
    case AArch64::ADD_ZPmZ_H:
30325
    case AArch64::ADD_ZPmZ_S:
30326
    case AArch64::AND_ZPmZ_B:
30327
    case AArch64::AND_ZPmZ_D:
30328
    case AArch64::AND_ZPmZ_H:
30329
    case AArch64::AND_ZPmZ_S:
30330
    case AArch64::ASRR_ZPmZ_B:
30331
    case AArch64::ASRR_ZPmZ_D:
30332
    case AArch64::ASRR_ZPmZ_H:
30333
    case AArch64::ASRR_ZPmZ_S:
30334
    case AArch64::ASR_WIDE_ZPmZ_B:
30335
    case AArch64::ASR_WIDE_ZPmZ_H:
30336
    case AArch64::ASR_WIDE_ZPmZ_S:
30337
    case AArch64::ASR_ZPmZ_B:
30338
    case AArch64::ASR_ZPmZ_D:
30339
    case AArch64::ASR_ZPmZ_H:
30340
    case AArch64::ASR_ZPmZ_S:
30341
    case AArch64::BFADD_ZPmZZ:
30342
    case AArch64::BFMAXNM_ZPmZZ:
30343
    case AArch64::BFMAX_ZPmZZ:
30344
    case AArch64::BFMINNM_ZPmZZ:
30345
    case AArch64::BFMIN_ZPmZZ:
30346
    case AArch64::BFMUL_ZPmZZ:
30347
    case AArch64::BFSUB_ZPmZZ:
30348
    case AArch64::BIC_ZPmZ_B:
30349
    case AArch64::BIC_ZPmZ_D:
30350
    case AArch64::BIC_ZPmZ_H:
30351
    case AArch64::BIC_ZPmZ_S:
30352
    case AArch64::CLASTA_ZPZ_B:
30353
    case AArch64::CLASTA_ZPZ_D:
30354
    case AArch64::CLASTA_ZPZ_H:
30355
    case AArch64::CLASTA_ZPZ_S:
30356
    case AArch64::CLASTB_ZPZ_B:
30357
    case AArch64::CLASTB_ZPZ_D:
30358
    case AArch64::CLASTB_ZPZ_H:
30359
    case AArch64::CLASTB_ZPZ_S:
30360
    case AArch64::EOR_ZPmZ_B:
30361
    case AArch64::EOR_ZPmZ_D:
30362
    case AArch64::EOR_ZPmZ_H:
30363
    case AArch64::EOR_ZPmZ_S:
30364
    case AArch64::FABD_ZPmZ_D:
30365
    case AArch64::FABD_ZPmZ_H:
30366
    case AArch64::FABD_ZPmZ_S:
30367
    case AArch64::FADD_ZPmZ_D:
30368
    case AArch64::FADD_ZPmZ_H:
30369
    case AArch64::FADD_ZPmZ_S:
30370
    case AArch64::FAMAX_ZPmZ_D:
30371
    case AArch64::FAMAX_ZPmZ_H:
30372
    case AArch64::FAMAX_ZPmZ_S:
30373
    case AArch64::FAMIN_ZPmZ_D:
30374
    case AArch64::FAMIN_ZPmZ_H:
30375
    case AArch64::FAMIN_ZPmZ_S:
30376
    case AArch64::FDIVR_ZPmZ_D:
30377
    case AArch64::FDIVR_ZPmZ_H:
30378
    case AArch64::FDIVR_ZPmZ_S:
30379
    case AArch64::FDIV_ZPmZ_D:
30380
    case AArch64::FDIV_ZPmZ_H:
30381
    case AArch64::FDIV_ZPmZ_S:
30382
    case AArch64::FMAXNM_ZPmZ_D:
30383
    case AArch64::FMAXNM_ZPmZ_H:
30384
    case AArch64::FMAXNM_ZPmZ_S:
30385
    case AArch64::FMAX_ZPmZ_D:
30386
    case AArch64::FMAX_ZPmZ_H:
30387
    case AArch64::FMAX_ZPmZ_S:
30388
    case AArch64::FMINNM_ZPmZ_D:
30389
    case AArch64::FMINNM_ZPmZ_H:
30390
    case AArch64::FMINNM_ZPmZ_S:
30391
    case AArch64::FMIN_ZPmZ_D:
30392
    case AArch64::FMIN_ZPmZ_H:
30393
    case AArch64::FMIN_ZPmZ_S:
30394
    case AArch64::FMULX_ZPmZ_D:
30395
    case AArch64::FMULX_ZPmZ_H:
30396
    case AArch64::FMULX_ZPmZ_S:
30397
    case AArch64::FMUL_ZPmZ_D:
30398
    case AArch64::FMUL_ZPmZ_H:
30399
    case AArch64::FMUL_ZPmZ_S:
30400
    case AArch64::FSCALE_ZPmZ_D:
30401
    case AArch64::FSCALE_ZPmZ_H:
30402
    case AArch64::FSCALE_ZPmZ_S:
30403
    case AArch64::FSUBR_ZPmZ_D:
30404
    case AArch64::FSUBR_ZPmZ_H:
30405
    case AArch64::FSUBR_ZPmZ_S:
30406
    case AArch64::FSUB_ZPmZ_D:
30407
    case AArch64::FSUB_ZPmZ_H:
30408
    case AArch64::FSUB_ZPmZ_S:
30409
    case AArch64::LSLR_ZPmZ_B:
30410
    case AArch64::LSLR_ZPmZ_D:
30411
    case AArch64::LSLR_ZPmZ_H:
30412
    case AArch64::LSLR_ZPmZ_S:
30413
    case AArch64::LSL_WIDE_ZPmZ_B:
30414
    case AArch64::LSL_WIDE_ZPmZ_H:
30415
    case AArch64::LSL_WIDE_ZPmZ_S:
30416
    case AArch64::LSL_ZPmZ_B:
30417
    case AArch64::LSL_ZPmZ_D:
30418
    case AArch64::LSL_ZPmZ_H:
30419
    case AArch64::LSL_ZPmZ_S:
30420
    case AArch64::LSRR_ZPmZ_B:
30421
    case AArch64::LSRR_ZPmZ_D:
30422
    case AArch64::LSRR_ZPmZ_H:
30423
    case AArch64::LSRR_ZPmZ_S:
30424
    case AArch64::LSR_WIDE_ZPmZ_B:
30425
    case AArch64::LSR_WIDE_ZPmZ_H:
30426
    case AArch64::LSR_WIDE_ZPmZ_S:
30427
    case AArch64::LSR_ZPmZ_B:
30428
    case AArch64::LSR_ZPmZ_D:
30429
    case AArch64::LSR_ZPmZ_H:
30430
    case AArch64::LSR_ZPmZ_S:
30431
    case AArch64::MUL_ZPmZ_B:
30432
    case AArch64::MUL_ZPmZ_D:
30433
    case AArch64::MUL_ZPmZ_H:
30434
    case AArch64::MUL_ZPmZ_S:
30435
    case AArch64::ORR_ZPmZ_B:
30436
    case AArch64::ORR_ZPmZ_D:
30437
    case AArch64::ORR_ZPmZ_H:
30438
    case AArch64::ORR_ZPmZ_S:
30439
    case AArch64::SABD_ZPmZ_B:
30440
    case AArch64::SABD_ZPmZ_D:
30441
    case AArch64::SABD_ZPmZ_H:
30442
    case AArch64::SABD_ZPmZ_S:
30443
    case AArch64::SDIVR_ZPmZ_D:
30444
    case AArch64::SDIVR_ZPmZ_S:
30445
    case AArch64::SDIV_ZPmZ_D:
30446
    case AArch64::SDIV_ZPmZ_S:
30447
    case AArch64::SMAX_ZPmZ_B:
30448
    case AArch64::SMAX_ZPmZ_D:
30449
    case AArch64::SMAX_ZPmZ_H:
30450
    case AArch64::SMAX_ZPmZ_S:
30451
    case AArch64::SMIN_ZPmZ_B:
30452
    case AArch64::SMIN_ZPmZ_D:
30453
    case AArch64::SMIN_ZPmZ_H:
30454
    case AArch64::SMIN_ZPmZ_S:
30455
    case AArch64::SMULH_ZPmZ_B:
30456
    case AArch64::SMULH_ZPmZ_D:
30457
    case AArch64::SMULH_ZPmZ_H:
30458
    case AArch64::SMULH_ZPmZ_S:
30459
    case AArch64::SPLICE_ZPZ_B:
30460
    case AArch64::SPLICE_ZPZ_D:
30461
    case AArch64::SPLICE_ZPZ_H:
30462
    case AArch64::SPLICE_ZPZ_S:
30463
    case AArch64::SUBR_ZPmZ_B:
30464
    case AArch64::SUBR_ZPmZ_D:
30465
    case AArch64::SUBR_ZPmZ_H:
30466
    case AArch64::SUBR_ZPmZ_S:
30467
    case AArch64::SUB_ZPmZ_B:
30468
    case AArch64::SUB_ZPmZ_CPA:
30469
    case AArch64::SUB_ZPmZ_D:
30470
    case AArch64::SUB_ZPmZ_H:
30471
    case AArch64::SUB_ZPmZ_S:
30472
    case AArch64::UABD_ZPmZ_B:
30473
    case AArch64::UABD_ZPmZ_D:
30474
    case AArch64::UABD_ZPmZ_H:
30475
    case AArch64::UABD_ZPmZ_S:
30476
    case AArch64::UDIVR_ZPmZ_D:
30477
    case AArch64::UDIVR_ZPmZ_S:
30478
    case AArch64::UDIV_ZPmZ_D:
30479
    case AArch64::UDIV_ZPmZ_S:
30480
    case AArch64::UMAX_ZPmZ_B:
30481
    case AArch64::UMAX_ZPmZ_D:
30482
    case AArch64::UMAX_ZPmZ_H:
30483
    case AArch64::UMAX_ZPmZ_S:
30484
    case AArch64::UMIN_ZPmZ_B:
30485
    case AArch64::UMIN_ZPmZ_D:
30486
    case AArch64::UMIN_ZPmZ_H:
30487
    case AArch64::UMIN_ZPmZ_S:
30488
    case AArch64::UMULH_ZPmZ_B:
30489
    case AArch64::UMULH_ZPmZ_D:
30490
    case AArch64::UMULH_ZPmZ_H:
30491
    case AArch64::UMULH_ZPmZ_S: {
30492
      switch (OpNum) {
30493
      case 1:
30494
        // op: Pg
30495
        return 10;
30496
      case 0:
30497
        // op: Zdn
30498
        return 0;
30499
      case 3:
30500
        // op: Zm
30501
        return 5;
30502
      }
30503
      break;
30504
    }
30505
    case AArch64::FADD_ZPmI_D:
30506
    case AArch64::FADD_ZPmI_H:
30507
    case AArch64::FADD_ZPmI_S:
30508
    case AArch64::FMAXNM_ZPmI_D:
30509
    case AArch64::FMAXNM_ZPmI_H:
30510
    case AArch64::FMAXNM_ZPmI_S:
30511
    case AArch64::FMAX_ZPmI_D:
30512
    case AArch64::FMAX_ZPmI_H:
30513
    case AArch64::FMAX_ZPmI_S:
30514
    case AArch64::FMINNM_ZPmI_D:
30515
    case AArch64::FMINNM_ZPmI_H:
30516
    case AArch64::FMINNM_ZPmI_S:
30517
    case AArch64::FMIN_ZPmI_D:
30518
    case AArch64::FMIN_ZPmI_H:
30519
    case AArch64::FMIN_ZPmI_S:
30520
    case AArch64::FMUL_ZPmI_D:
30521
    case AArch64::FMUL_ZPmI_H:
30522
    case AArch64::FMUL_ZPmI_S:
30523
    case AArch64::FSUBR_ZPmI_D:
30524
    case AArch64::FSUBR_ZPmI_H:
30525
    case AArch64::FSUBR_ZPmI_S:
30526
    case AArch64::FSUB_ZPmI_D:
30527
    case AArch64::FSUB_ZPmI_H:
30528
    case AArch64::FSUB_ZPmI_S: {
30529
      switch (OpNum) {
30530
      case 1:
30531
        // op: Pg
30532
        return 10;
30533
      case 0:
30534
        // op: Zdn
30535
        return 0;
30536
      case 3:
30537
        // op: i1
30538
        return 5;
30539
      }
30540
      break;
30541
    }
30542
    case AArch64::ASRD_ZPmI_B:
30543
    case AArch64::ASRD_ZPmI_D:
30544
    case AArch64::ASRD_ZPmI_H:
30545
    case AArch64::ASRD_ZPmI_S:
30546
    case AArch64::ASR_ZPmI_B:
30547
    case AArch64::ASR_ZPmI_D:
30548
    case AArch64::ASR_ZPmI_H:
30549
    case AArch64::ASR_ZPmI_S:
30550
    case AArch64::LSL_ZPmI_B:
30551
    case AArch64::LSL_ZPmI_D:
30552
    case AArch64::LSL_ZPmI_H:
30553
    case AArch64::LSL_ZPmI_S:
30554
    case AArch64::LSR_ZPmI_B:
30555
    case AArch64::LSR_ZPmI_D:
30556
    case AArch64::LSR_ZPmI_H:
30557
    case AArch64::LSR_ZPmI_S:
30558
    case AArch64::SQSHLU_ZPmI_B:
30559
    case AArch64::SQSHLU_ZPmI_D:
30560
    case AArch64::SQSHLU_ZPmI_H:
30561
    case AArch64::SQSHLU_ZPmI_S:
30562
    case AArch64::SQSHL_ZPmI_B:
30563
    case AArch64::SQSHL_ZPmI_D:
30564
    case AArch64::SQSHL_ZPmI_H:
30565
    case AArch64::SQSHL_ZPmI_S:
30566
    case AArch64::SRSHR_ZPmI_B:
30567
    case AArch64::SRSHR_ZPmI_D:
30568
    case AArch64::SRSHR_ZPmI_H:
30569
    case AArch64::SRSHR_ZPmI_S:
30570
    case AArch64::UQSHL_ZPmI_B:
30571
    case AArch64::UQSHL_ZPmI_D:
30572
    case AArch64::UQSHL_ZPmI_H:
30573
    case AArch64::UQSHL_ZPmI_S:
30574
    case AArch64::URSHR_ZPmI_B:
30575
    case AArch64::URSHR_ZPmI_D:
30576
    case AArch64::URSHR_ZPmI_H:
30577
    case AArch64::URSHR_ZPmI_S: {
30578
      switch (OpNum) {
30579
      case 1:
30580
        // op: Pg
30581
        return 10;
30582
      case 0:
30583
        // op: Zdn
30584
        return 0;
30585
      case 3:
30586
        // op: imm
30587
        return 5;
30588
      }
30589
      break;
30590
    }
30591
    case AArch64::MAD_ZPmZZ_B:
30592
    case AArch64::MAD_ZPmZZ_D:
30593
    case AArch64::MAD_ZPmZZ_H:
30594
    case AArch64::MAD_ZPmZZ_S:
30595
    case AArch64::MSB_ZPmZZ_B:
30596
    case AArch64::MSB_ZPmZZ_D:
30597
    case AArch64::MSB_ZPmZZ_H:
30598
    case AArch64::MSB_ZPmZZ_S: {
30599
      switch (OpNum) {
30600
      case 1:
30601
        // op: Pg
30602
        return 10;
30603
      case 0:
30604
        // op: Zdn
30605
        return 0;
30606
      case 4:
30607
        // op: Za
30608
        return 5;
30609
      case 3:
30610
        // op: Zm
30611
        return 16;
30612
      }
30613
      break;
30614
    }
30615
    case AArch64::CNTP_XPP_B:
30616
    case AArch64::CNTP_XPP_D:
30617
    case AArch64::CNTP_XPP_H:
30618
    case AArch64::CNTP_XPP_S: {
30619
      switch (OpNum) {
30620
      case 1:
30621
        // op: Pg
30622
        return 10;
30623
      case 2:
30624
        // op: Pn
30625
        return 5;
30626
      case 0:
30627
        // op: Rd
30628
        return 0;
30629
      }
30630
      break;
30631
    }
30632
    case AArch64::LD1B_D_IMM:
30633
    case AArch64::LD1B_H_IMM:
30634
    case AArch64::LD1B_IMM:
30635
    case AArch64::LD1B_S_IMM:
30636
    case AArch64::LD1D_IMM:
30637
    case AArch64::LD1H_D_IMM:
30638
    case AArch64::LD1H_IMM:
30639
    case AArch64::LD1H_S_IMM:
30640
    case AArch64::LD1SB_D_IMM:
30641
    case AArch64::LD1SB_H_IMM:
30642
    case AArch64::LD1SB_S_IMM:
30643
    case AArch64::LD1SH_D_IMM:
30644
    case AArch64::LD1SH_S_IMM:
30645
    case AArch64::LD1SW_D_IMM:
30646
    case AArch64::LD1W_D_IMM:
30647
    case AArch64::LD1W_IMM:
30648
    case AArch64::LDNF1B_D_IMM_REAL:
30649
    case AArch64::LDNF1B_H_IMM_REAL:
30650
    case AArch64::LDNF1B_IMM_REAL:
30651
    case AArch64::LDNF1B_S_IMM_REAL:
30652
    case AArch64::LDNF1D_IMM_REAL:
30653
    case AArch64::LDNF1H_D_IMM_REAL:
30654
    case AArch64::LDNF1H_IMM_REAL:
30655
    case AArch64::LDNF1H_S_IMM_REAL:
30656
    case AArch64::LDNF1SB_D_IMM_REAL:
30657
    case AArch64::LDNF1SB_H_IMM_REAL:
30658
    case AArch64::LDNF1SB_S_IMM_REAL:
30659
    case AArch64::LDNF1SH_D_IMM_REAL:
30660
    case AArch64::LDNF1SH_S_IMM_REAL:
30661
    case AArch64::LDNF1SW_D_IMM_REAL:
30662
    case AArch64::LDNF1W_D_IMM_REAL:
30663
    case AArch64::LDNF1W_IMM_REAL:
30664
    case AArch64::ST1B_D_IMM:
30665
    case AArch64::ST1B_H_IMM:
30666
    case AArch64::ST1B_IMM:
30667
    case AArch64::ST1B_S_IMM:
30668
    case AArch64::ST1D_IMM:
30669
    case AArch64::ST1D_Q_IMM:
30670
    case AArch64::ST1H_D_IMM:
30671
    case AArch64::ST1H_IMM:
30672
    case AArch64::ST1H_S_IMM:
30673
    case AArch64::ST1W_D_IMM:
30674
    case AArch64::ST1W_IMM:
30675
    case AArch64::ST1W_Q_IMM:
30676
    case AArch64::ST2B_IMM:
30677
    case AArch64::ST2D_IMM:
30678
    case AArch64::ST2H_IMM:
30679
    case AArch64::ST2W_IMM:
30680
    case AArch64::ST3B_IMM:
30681
    case AArch64::ST3D_IMM:
30682
    case AArch64::ST3H_IMM:
30683
    case AArch64::ST3W_IMM:
30684
    case AArch64::ST4B_IMM:
30685
    case AArch64::ST4D_IMM:
30686
    case AArch64::ST4H_IMM:
30687
    case AArch64::ST4W_IMM:
30688
    case AArch64::STNT1B_ZRI:
30689
    case AArch64::STNT1D_ZRI:
30690
    case AArch64::STNT1H_ZRI:
30691
    case AArch64::STNT1W_ZRI: {
30692
      switch (OpNum) {
30693
      case 1:
30694
        // op: Pg
30695
        return 10;
30696
      case 2:
30697
        // op: Rn
30698
        return 5;
30699
      case 0:
30700
        // op: Zt
30701
        return 0;
30702
      case 3:
30703
        // op: imm4
30704
        return 16;
30705
      }
30706
      break;
30707
    }
30708
    case AArch64::LD1RB_D_IMM:
30709
    case AArch64::LD1RB_H_IMM:
30710
    case AArch64::LD1RB_IMM:
30711
    case AArch64::LD1RB_S_IMM:
30712
    case AArch64::LD1RD_IMM:
30713
    case AArch64::LD1RH_D_IMM:
30714
    case AArch64::LD1RH_IMM:
30715
    case AArch64::LD1RH_S_IMM:
30716
    case AArch64::LD1RSB_D_IMM:
30717
    case AArch64::LD1RSB_H_IMM:
30718
    case AArch64::LD1RSB_S_IMM:
30719
    case AArch64::LD1RSH_D_IMM:
30720
    case AArch64::LD1RSH_S_IMM:
30721
    case AArch64::LD1RSW_IMM:
30722
    case AArch64::LD1RW_D_IMM:
30723
    case AArch64::LD1RW_IMM: {
30724
      switch (OpNum) {
30725
      case 1:
30726
        // op: Pg
30727
        return 10;
30728
      case 2:
30729
        // op: Rn
30730
        return 5;
30731
      case 0:
30732
        // op: Zt
30733
        return 0;
30734
      case 3:
30735
        // op: imm6
30736
        return 16;
30737
      }
30738
      break;
30739
    }
30740
    case AArch64::GLD1B_D_REAL:
30741
    case AArch64::GLD1B_D_SXTW_REAL:
30742
    case AArch64::GLD1B_D_UXTW_REAL:
30743
    case AArch64::GLD1B_S_SXTW_REAL:
30744
    case AArch64::GLD1B_S_UXTW_REAL:
30745
    case AArch64::GLD1D_REAL:
30746
    case AArch64::GLD1D_SCALED_REAL:
30747
    case AArch64::GLD1D_SXTW_REAL:
30748
    case AArch64::GLD1D_SXTW_SCALED_REAL:
30749
    case AArch64::GLD1D_UXTW_REAL:
30750
    case AArch64::GLD1D_UXTW_SCALED_REAL:
30751
    case AArch64::GLD1H_D_REAL:
30752
    case AArch64::GLD1H_D_SCALED_REAL:
30753
    case AArch64::GLD1H_D_SXTW_REAL:
30754
    case AArch64::GLD1H_D_SXTW_SCALED_REAL:
30755
    case AArch64::GLD1H_D_UXTW_REAL:
30756
    case AArch64::GLD1H_D_UXTW_SCALED_REAL:
30757
    case AArch64::GLD1H_S_SXTW_REAL:
30758
    case AArch64::GLD1H_S_SXTW_SCALED_REAL:
30759
    case AArch64::GLD1H_S_UXTW_REAL:
30760
    case AArch64::GLD1H_S_UXTW_SCALED_REAL:
30761
    case AArch64::GLD1SB_D_REAL:
30762
    case AArch64::GLD1SB_D_SXTW_REAL:
30763
    case AArch64::GLD1SB_D_UXTW_REAL:
30764
    case AArch64::GLD1SB_S_SXTW_REAL:
30765
    case AArch64::GLD1SB_S_UXTW_REAL:
30766
    case AArch64::GLD1SH_D_REAL:
30767
    case AArch64::GLD1SH_D_SCALED_REAL:
30768
    case AArch64::GLD1SH_D_SXTW_REAL:
30769
    case AArch64::GLD1SH_D_SXTW_SCALED_REAL:
30770
    case AArch64::GLD1SH_D_UXTW_REAL:
30771
    case AArch64::GLD1SH_D_UXTW_SCALED_REAL:
30772
    case AArch64::GLD1SH_S_SXTW_REAL:
30773
    case AArch64::GLD1SH_S_SXTW_SCALED_REAL:
30774
    case AArch64::GLD1SH_S_UXTW_REAL:
30775
    case AArch64::GLD1SH_S_UXTW_SCALED_REAL:
30776
    case AArch64::GLD1SW_D_REAL:
30777
    case AArch64::GLD1SW_D_SCALED_REAL:
30778
    case AArch64::GLD1SW_D_SXTW_REAL:
30779
    case AArch64::GLD1SW_D_SXTW_SCALED_REAL:
30780
    case AArch64::GLD1SW_D_UXTW_REAL:
30781
    case AArch64::GLD1SW_D_UXTW_SCALED_REAL:
30782
    case AArch64::GLD1W_D_REAL:
30783
    case AArch64::GLD1W_D_SCALED_REAL:
30784
    case AArch64::GLD1W_D_SXTW_REAL:
30785
    case AArch64::GLD1W_D_SXTW_SCALED_REAL:
30786
    case AArch64::GLD1W_D_UXTW_REAL:
30787
    case AArch64::GLD1W_D_UXTW_SCALED_REAL:
30788
    case AArch64::GLD1W_SXTW_REAL:
30789
    case AArch64::GLD1W_SXTW_SCALED_REAL:
30790
    case AArch64::GLD1W_UXTW_REAL:
30791
    case AArch64::GLD1W_UXTW_SCALED_REAL:
30792
    case AArch64::GLDFF1B_D_REAL:
30793
    case AArch64::GLDFF1B_D_SXTW_REAL:
30794
    case AArch64::GLDFF1B_D_UXTW_REAL:
30795
    case AArch64::GLDFF1B_S_SXTW_REAL:
30796
    case AArch64::GLDFF1B_S_UXTW_REAL:
30797
    case AArch64::GLDFF1D_REAL:
30798
    case AArch64::GLDFF1D_SCALED_REAL:
30799
    case AArch64::GLDFF1D_SXTW_REAL:
30800
    case AArch64::GLDFF1D_SXTW_SCALED_REAL:
30801
    case AArch64::GLDFF1D_UXTW_REAL:
30802
    case AArch64::GLDFF1D_UXTW_SCALED_REAL:
30803
    case AArch64::GLDFF1H_D_REAL:
30804
    case AArch64::GLDFF1H_D_SCALED_REAL:
30805
    case AArch64::GLDFF1H_D_SXTW_REAL:
30806
    case AArch64::GLDFF1H_D_SXTW_SCALED_REAL:
30807
    case AArch64::GLDFF1H_D_UXTW_REAL:
30808
    case AArch64::GLDFF1H_D_UXTW_SCALED_REAL:
30809
    case AArch64::GLDFF1H_S_SXTW_REAL:
30810
    case AArch64::GLDFF1H_S_SXTW_SCALED_REAL:
30811
    case AArch64::GLDFF1H_S_UXTW_REAL:
30812
    case AArch64::GLDFF1H_S_UXTW_SCALED_REAL:
30813
    case AArch64::GLDFF1SB_D_REAL:
30814
    case AArch64::GLDFF1SB_D_SXTW_REAL:
30815
    case AArch64::GLDFF1SB_D_UXTW_REAL:
30816
    case AArch64::GLDFF1SB_S_SXTW_REAL:
30817
    case AArch64::GLDFF1SB_S_UXTW_REAL:
30818
    case AArch64::GLDFF1SH_D_REAL:
30819
    case AArch64::GLDFF1SH_D_SCALED_REAL:
30820
    case AArch64::GLDFF1SH_D_SXTW_REAL:
30821
    case AArch64::GLDFF1SH_D_SXTW_SCALED_REAL:
30822
    case AArch64::GLDFF1SH_D_UXTW_REAL:
30823
    case AArch64::GLDFF1SH_D_UXTW_SCALED_REAL:
30824
    case AArch64::GLDFF1SH_S_SXTW_REAL:
30825
    case AArch64::GLDFF1SH_S_SXTW_SCALED_REAL:
30826
    case AArch64::GLDFF1SH_S_UXTW_REAL:
30827
    case AArch64::GLDFF1SH_S_UXTW_SCALED_REAL:
30828
    case AArch64::GLDFF1SW_D_REAL:
30829
    case AArch64::GLDFF1SW_D_SCALED_REAL:
30830
    case AArch64::GLDFF1SW_D_SXTW_REAL:
30831
    case AArch64::GLDFF1SW_D_SXTW_SCALED_REAL:
30832
    case AArch64::GLDFF1SW_D_UXTW_REAL:
30833
    case AArch64::GLDFF1SW_D_UXTW_SCALED_REAL:
30834
    case AArch64::GLDFF1W_D_REAL:
30835
    case AArch64::GLDFF1W_D_SCALED_REAL:
30836
    case AArch64::GLDFF1W_D_SXTW_REAL:
30837
    case AArch64::GLDFF1W_D_SXTW_SCALED_REAL:
30838
    case AArch64::GLDFF1W_D_UXTW_REAL:
30839
    case AArch64::GLDFF1W_D_UXTW_SCALED_REAL:
30840
    case AArch64::GLDFF1W_SXTW_REAL:
30841
    case AArch64::GLDFF1W_SXTW_SCALED_REAL:
30842
    case AArch64::GLDFF1W_UXTW_REAL:
30843
    case AArch64::GLDFF1W_UXTW_SCALED_REAL:
30844
    case AArch64::SST1B_D:
30845
    case AArch64::SST1B_D_SXTW:
30846
    case AArch64::SST1B_D_UXTW:
30847
    case AArch64::SST1B_S_SXTW:
30848
    case AArch64::SST1B_S_UXTW:
30849
    case AArch64::SST1D:
30850
    case AArch64::SST1D_SCALED:
30851
    case AArch64::SST1D_SXTW:
30852
    case AArch64::SST1D_SXTW_SCALED:
30853
    case AArch64::SST1D_UXTW:
30854
    case AArch64::SST1D_UXTW_SCALED:
30855
    case AArch64::SST1H_D:
30856
    case AArch64::SST1H_D_SCALED:
30857
    case AArch64::SST1H_D_SXTW:
30858
    case AArch64::SST1H_D_SXTW_SCALED:
30859
    case AArch64::SST1H_D_UXTW:
30860
    case AArch64::SST1H_D_UXTW_SCALED:
30861
    case AArch64::SST1H_S_SXTW:
30862
    case AArch64::SST1H_S_SXTW_SCALED:
30863
    case AArch64::SST1H_S_UXTW:
30864
    case AArch64::SST1H_S_UXTW_SCALED:
30865
    case AArch64::SST1W_D:
30866
    case AArch64::SST1W_D_SCALED:
30867
    case AArch64::SST1W_D_SXTW:
30868
    case AArch64::SST1W_D_SXTW_SCALED:
30869
    case AArch64::SST1W_D_UXTW:
30870
    case AArch64::SST1W_D_UXTW_SCALED:
30871
    case AArch64::SST1W_SXTW:
30872
    case AArch64::SST1W_SXTW_SCALED:
30873
    case AArch64::SST1W_UXTW:
30874
    case AArch64::SST1W_UXTW_SCALED: {
30875
      switch (OpNum) {
30876
      case 1:
30877
        // op: Pg
30878
        return 10;
30879
      case 2:
30880
        // op: Rn
30881
        return 5;
30882
      case 3:
30883
        // op: Zm
30884
        return 16;
30885
      case 0:
30886
        // op: Zt
30887
        return 0;
30888
      }
30889
      break;
30890
    }
30891
    case AArch64::PRFB_D_SCALED:
30892
    case AArch64::PRFB_D_SXTW_SCALED:
30893
    case AArch64::PRFB_D_UXTW_SCALED:
30894
    case AArch64::PRFB_S_SXTW_SCALED:
30895
    case AArch64::PRFB_S_UXTW_SCALED:
30896
    case AArch64::PRFD_D_SCALED:
30897
    case AArch64::PRFD_D_SXTW_SCALED:
30898
    case AArch64::PRFD_D_UXTW_SCALED:
30899
    case AArch64::PRFD_S_SXTW_SCALED:
30900
    case AArch64::PRFD_S_UXTW_SCALED:
30901
    case AArch64::PRFH_D_SCALED:
30902
    case AArch64::PRFH_D_SXTW_SCALED:
30903
    case AArch64::PRFH_D_UXTW_SCALED:
30904
    case AArch64::PRFH_S_SXTW_SCALED:
30905
    case AArch64::PRFH_S_UXTW_SCALED:
30906
    case AArch64::PRFW_D_SCALED:
30907
    case AArch64::PRFW_D_SXTW_SCALED:
30908
    case AArch64::PRFW_D_UXTW_SCALED:
30909
    case AArch64::PRFW_S_SXTW_SCALED:
30910
    case AArch64::PRFW_S_UXTW_SCALED: {
30911
      switch (OpNum) {
30912
      case 1:
30913
        // op: Pg
30914
        return 10;
30915
      case 2:
30916
        // op: Rn
30917
        return 5;
30918
      case 3:
30919
        // op: Zm
30920
        return 16;
30921
      case 0:
30922
        // op: prfop
30923
        return 0;
30924
      }
30925
      break;
30926
    }
30927
    case AArch64::SPLICE_ZPZZ_B:
30928
    case AArch64::SPLICE_ZPZZ_D:
30929
    case AArch64::SPLICE_ZPZZ_H:
30930
    case AArch64::SPLICE_ZPZZ_S: {
30931
      switch (OpNum) {
30932
      case 1:
30933
        // op: Pg
30934
        return 10;
30935
      case 2:
30936
        // op: Zn
30937
        return 5;
30938
      case 0:
30939
        // op: Zd
30940
        return 0;
30941
      }
30942
      break;
30943
    }
30944
    case AArch64::GLD1B_D_IMM_REAL:
30945
    case AArch64::GLD1B_S_IMM_REAL:
30946
    case AArch64::GLD1D_IMM_REAL:
30947
    case AArch64::GLD1H_D_IMM_REAL:
30948
    case AArch64::GLD1H_S_IMM_REAL:
30949
    case AArch64::GLD1SB_D_IMM_REAL:
30950
    case AArch64::GLD1SB_S_IMM_REAL:
30951
    case AArch64::GLD1SH_D_IMM_REAL:
30952
    case AArch64::GLD1SH_S_IMM_REAL:
30953
    case AArch64::GLD1SW_D_IMM_REAL:
30954
    case AArch64::GLD1W_D_IMM_REAL:
30955
    case AArch64::GLD1W_IMM_REAL:
30956
    case AArch64::GLDFF1B_D_IMM_REAL:
30957
    case AArch64::GLDFF1B_S_IMM_REAL:
30958
    case AArch64::GLDFF1D_IMM_REAL:
30959
    case AArch64::GLDFF1H_D_IMM_REAL:
30960
    case AArch64::GLDFF1H_S_IMM_REAL:
30961
    case AArch64::GLDFF1SB_D_IMM_REAL:
30962
    case AArch64::GLDFF1SB_S_IMM_REAL:
30963
    case AArch64::GLDFF1SH_D_IMM_REAL:
30964
    case AArch64::GLDFF1SH_S_IMM_REAL:
30965
    case AArch64::GLDFF1SW_D_IMM_REAL:
30966
    case AArch64::GLDFF1W_D_IMM_REAL:
30967
    case AArch64::GLDFF1W_IMM_REAL: {
30968
      switch (OpNum) {
30969
      case 1:
30970
        // op: Pg
30971
        return 10;
30972
      case 2:
30973
        // op: Zn
30974
        return 5;
30975
      case 0:
30976
        // op: Zt
30977
        return 0;
30978
      case 3:
30979
        // op: imm5
30980
        return 16;
30981
      }
30982
      break;
30983
    }
30984
    case AArch64::PRFB_D_PZI:
30985
    case AArch64::PRFB_S_PZI:
30986
    case AArch64::PRFD_D_PZI:
30987
    case AArch64::PRFD_S_PZI:
30988
    case AArch64::PRFH_D_PZI:
30989
    case AArch64::PRFH_S_PZI:
30990
    case AArch64::PRFW_D_PZI:
30991
    case AArch64::PRFW_S_PZI: {
30992
      switch (OpNum) {
30993
      case 1:
30994
        // op: Pg
30995
        return 10;
30996
      case 2:
30997
        // op: Zn
30998
        return 5;
30999
      case 3:
31000
        // op: imm5
31001
        return 16;
31002
      case 0:
31003
        // op: prfop
31004
        return 0;
31005
      }
31006
      break;
31007
    }
31008
    case AArch64::LD2B:
31009
    case AArch64::LD2D:
31010
    case AArch64::LD2H:
31011
    case AArch64::LD2Q:
31012
    case AArch64::LD2W:
31013
    case AArch64::LD3B:
31014
    case AArch64::LD3D:
31015
    case AArch64::LD3H:
31016
    case AArch64::LD3Q:
31017
    case AArch64::LD3W:
31018
    case AArch64::LD4B:
31019
    case AArch64::LD4D:
31020
    case AArch64::LD4H:
31021
    case AArch64::LD4Q:
31022
    case AArch64::LD4W:
31023
    case AArch64::LDNT1B_ZRR:
31024
    case AArch64::LDNT1D_ZRR:
31025
    case AArch64::LDNT1H_ZRR:
31026
    case AArch64::LDNT1W_ZRR:
31027
    case AArch64::ST1B:
31028
    case AArch64::ST1B_D:
31029
    case AArch64::ST1B_H:
31030
    case AArch64::ST1B_S:
31031
    case AArch64::ST1D:
31032
    case AArch64::ST1D_Q:
31033
    case AArch64::ST1H:
31034
    case AArch64::ST1H_D:
31035
    case AArch64::ST1H_S:
31036
    case AArch64::ST1W:
31037
    case AArch64::ST1W_D:
31038
    case AArch64::ST1W_Q:
31039
    case AArch64::ST2B:
31040
    case AArch64::ST2D:
31041
    case AArch64::ST2H:
31042
    case AArch64::ST2W:
31043
    case AArch64::ST3B:
31044
    case AArch64::ST3D:
31045
    case AArch64::ST3H:
31046
    case AArch64::ST3W:
31047
    case AArch64::ST4B:
31048
    case AArch64::ST4D:
31049
    case AArch64::ST4H:
31050
    case AArch64::ST4W:
31051
    case AArch64::STNT1B_ZRR:
31052
    case AArch64::STNT1D_ZRR:
31053
    case AArch64::STNT1H_ZRR:
31054
    case AArch64::STNT1W_ZRR: {
31055
      switch (OpNum) {
31056
      case 1:
31057
        // op: Pg
31058
        return 10;
31059
      case 3:
31060
        // op: Rm
31061
        return 16;
31062
      case 2:
31063
        // op: Rn
31064
        return 5;
31065
      case 0:
31066
        // op: Zt
31067
        return 0;
31068
      }
31069
      break;
31070
    }
31071
    case AArch64::LDNT1B_ZZR_D_REAL:
31072
    case AArch64::LDNT1B_ZZR_S_REAL:
31073
    case AArch64::LDNT1D_ZZR_D_REAL:
31074
    case AArch64::LDNT1H_ZZR_D_REAL:
31075
    case AArch64::LDNT1H_ZZR_S_REAL:
31076
    case AArch64::LDNT1SB_ZZR_D_REAL:
31077
    case AArch64::LDNT1SB_ZZR_S_REAL:
31078
    case AArch64::LDNT1SH_ZZR_D_REAL:
31079
    case AArch64::LDNT1SH_ZZR_S_REAL:
31080
    case AArch64::LDNT1SW_ZZR_D_REAL:
31081
    case AArch64::LDNT1W_ZZR_D_REAL:
31082
    case AArch64::LDNT1W_ZZR_S_REAL:
31083
    case AArch64::STNT1B_ZZR_D_REAL:
31084
    case AArch64::STNT1B_ZZR_S_REAL:
31085
    case AArch64::STNT1D_ZZR_D_REAL:
31086
    case AArch64::STNT1H_ZZR_D_REAL:
31087
    case AArch64::STNT1H_ZZR_S_REAL:
31088
    case AArch64::STNT1W_ZZR_D_REAL:
31089
    case AArch64::STNT1W_ZZR_S_REAL: {
31090
      switch (OpNum) {
31091
      case 1:
31092
        // op: Pg
31093
        return 10;
31094
      case 3:
31095
        // op: Rm
31096
        return 16;
31097
      case 2:
31098
        // op: Zn
31099
        return 5;
31100
      case 0:
31101
        // op: Zt
31102
        return 0;
31103
      }
31104
      break;
31105
    }
31106
    case AArch64::ADDP_ZPmZ_B:
31107
    case AArch64::ADDP_ZPmZ_D:
31108
    case AArch64::ADDP_ZPmZ_H:
31109
    case AArch64::ADDP_ZPmZ_S:
31110
    case AArch64::FADDP_ZPmZZ_D:
31111
    case AArch64::FADDP_ZPmZZ_H:
31112
    case AArch64::FADDP_ZPmZZ_S:
31113
    case AArch64::FMAXNMP_ZPmZZ_D:
31114
    case AArch64::FMAXNMP_ZPmZZ_H:
31115
    case AArch64::FMAXNMP_ZPmZZ_S:
31116
    case AArch64::FMAXP_ZPmZZ_D:
31117
    case AArch64::FMAXP_ZPmZZ_H:
31118
    case AArch64::FMAXP_ZPmZZ_S:
31119
    case AArch64::FMINNMP_ZPmZZ_D:
31120
    case AArch64::FMINNMP_ZPmZZ_H:
31121
    case AArch64::FMINNMP_ZPmZZ_S:
31122
    case AArch64::FMINP_ZPmZZ_D:
31123
    case AArch64::FMINP_ZPmZZ_H:
31124
    case AArch64::FMINP_ZPmZZ_S:
31125
    case AArch64::SHADD_ZPmZ_B:
31126
    case AArch64::SHADD_ZPmZ_D:
31127
    case AArch64::SHADD_ZPmZ_H:
31128
    case AArch64::SHADD_ZPmZ_S:
31129
    case AArch64::SHSUBR_ZPmZ_B:
31130
    case AArch64::SHSUBR_ZPmZ_D:
31131
    case AArch64::SHSUBR_ZPmZ_H:
31132
    case AArch64::SHSUBR_ZPmZ_S:
31133
    case AArch64::SHSUB_ZPmZ_B:
31134
    case AArch64::SHSUB_ZPmZ_D:
31135
    case AArch64::SHSUB_ZPmZ_H:
31136
    case AArch64::SHSUB_ZPmZ_S:
31137
    case AArch64::SMAXP_ZPmZ_B:
31138
    case AArch64::SMAXP_ZPmZ_D:
31139
    case AArch64::SMAXP_ZPmZ_H:
31140
    case AArch64::SMAXP_ZPmZ_S:
31141
    case AArch64::SMINP_ZPmZ_B:
31142
    case AArch64::SMINP_ZPmZ_D:
31143
    case AArch64::SMINP_ZPmZ_H:
31144
    case AArch64::SMINP_ZPmZ_S:
31145
    case AArch64::SQADD_ZPmZ_B:
31146
    case AArch64::SQADD_ZPmZ_D:
31147
    case AArch64::SQADD_ZPmZ_H:
31148
    case AArch64::SQADD_ZPmZ_S:
31149
    case AArch64::SQRSHLR_ZPmZ_B:
31150
    case AArch64::SQRSHLR_ZPmZ_D:
31151
    case AArch64::SQRSHLR_ZPmZ_H:
31152
    case AArch64::SQRSHLR_ZPmZ_S:
31153
    case AArch64::SQRSHL_ZPmZ_B:
31154
    case AArch64::SQRSHL_ZPmZ_D:
31155
    case AArch64::SQRSHL_ZPmZ_H:
31156
    case AArch64::SQRSHL_ZPmZ_S:
31157
    case AArch64::SQSHLR_ZPmZ_B:
31158
    case AArch64::SQSHLR_ZPmZ_D:
31159
    case AArch64::SQSHLR_ZPmZ_H:
31160
    case AArch64::SQSHLR_ZPmZ_S:
31161
    case AArch64::SQSHL_ZPmZ_B:
31162
    case AArch64::SQSHL_ZPmZ_D:
31163
    case AArch64::SQSHL_ZPmZ_H:
31164
    case AArch64::SQSHL_ZPmZ_S:
31165
    case AArch64::SQSUBR_ZPmZ_B:
31166
    case AArch64::SQSUBR_ZPmZ_D:
31167
    case AArch64::SQSUBR_ZPmZ_H:
31168
    case AArch64::SQSUBR_ZPmZ_S:
31169
    case AArch64::SQSUB_ZPmZ_B:
31170
    case AArch64::SQSUB_ZPmZ_D:
31171
    case AArch64::SQSUB_ZPmZ_H:
31172
    case AArch64::SQSUB_ZPmZ_S:
31173
    case AArch64::SRHADD_ZPmZ_B:
31174
    case AArch64::SRHADD_ZPmZ_D:
31175
    case AArch64::SRHADD_ZPmZ_H:
31176
    case AArch64::SRHADD_ZPmZ_S:
31177
    case AArch64::SRSHLR_ZPmZ_B:
31178
    case AArch64::SRSHLR_ZPmZ_D:
31179
    case AArch64::SRSHLR_ZPmZ_H:
31180
    case AArch64::SRSHLR_ZPmZ_S:
31181
    case AArch64::SRSHL_ZPmZ_B:
31182
    case AArch64::SRSHL_ZPmZ_D:
31183
    case AArch64::SRSHL_ZPmZ_H:
31184
    case AArch64::SRSHL_ZPmZ_S:
31185
    case AArch64::SUQADD_ZPmZ_B:
31186
    case AArch64::SUQADD_ZPmZ_D:
31187
    case AArch64::SUQADD_ZPmZ_H:
31188
    case AArch64::SUQADD_ZPmZ_S:
31189
    case AArch64::UHADD_ZPmZ_B:
31190
    case AArch64::UHADD_ZPmZ_D:
31191
    case AArch64::UHADD_ZPmZ_H:
31192
    case AArch64::UHADD_ZPmZ_S:
31193
    case AArch64::UHSUBR_ZPmZ_B:
31194
    case AArch64::UHSUBR_ZPmZ_D:
31195
    case AArch64::UHSUBR_ZPmZ_H:
31196
    case AArch64::UHSUBR_ZPmZ_S:
31197
    case AArch64::UHSUB_ZPmZ_B:
31198
    case AArch64::UHSUB_ZPmZ_D:
31199
    case AArch64::UHSUB_ZPmZ_H:
31200
    case AArch64::UHSUB_ZPmZ_S:
31201
    case AArch64::UMAXP_ZPmZ_B:
31202
    case AArch64::UMAXP_ZPmZ_D:
31203
    case AArch64::UMAXP_ZPmZ_H:
31204
    case AArch64::UMAXP_ZPmZ_S:
31205
    case AArch64::UMINP_ZPmZ_B:
31206
    case AArch64::UMINP_ZPmZ_D:
31207
    case AArch64::UMINP_ZPmZ_H:
31208
    case AArch64::UMINP_ZPmZ_S:
31209
    case AArch64::UQADD_ZPmZ_B:
31210
    case AArch64::UQADD_ZPmZ_D:
31211
    case AArch64::UQADD_ZPmZ_H:
31212
    case AArch64::UQADD_ZPmZ_S:
31213
    case AArch64::UQRSHLR_ZPmZ_B:
31214
    case AArch64::UQRSHLR_ZPmZ_D:
31215
    case AArch64::UQRSHLR_ZPmZ_H:
31216
    case AArch64::UQRSHLR_ZPmZ_S:
31217
    case AArch64::UQRSHL_ZPmZ_B:
31218
    case AArch64::UQRSHL_ZPmZ_D:
31219
    case AArch64::UQRSHL_ZPmZ_H:
31220
    case AArch64::UQRSHL_ZPmZ_S:
31221
    case AArch64::UQSHLR_ZPmZ_B:
31222
    case AArch64::UQSHLR_ZPmZ_D:
31223
    case AArch64::UQSHLR_ZPmZ_H:
31224
    case AArch64::UQSHLR_ZPmZ_S:
31225
    case AArch64::UQSHL_ZPmZ_B:
31226
    case AArch64::UQSHL_ZPmZ_D:
31227
    case AArch64::UQSHL_ZPmZ_H:
31228
    case AArch64::UQSHL_ZPmZ_S:
31229
    case AArch64::UQSUBR_ZPmZ_B:
31230
    case AArch64::UQSUBR_ZPmZ_D:
31231
    case AArch64::UQSUBR_ZPmZ_H:
31232
    case AArch64::UQSUBR_ZPmZ_S:
31233
    case AArch64::UQSUB_ZPmZ_B:
31234
    case AArch64::UQSUB_ZPmZ_D:
31235
    case AArch64::UQSUB_ZPmZ_H:
31236
    case AArch64::UQSUB_ZPmZ_S:
31237
    case AArch64::URHADD_ZPmZ_B:
31238
    case AArch64::URHADD_ZPmZ_D:
31239
    case AArch64::URHADD_ZPmZ_H:
31240
    case AArch64::URHADD_ZPmZ_S:
31241
    case AArch64::URSHLR_ZPmZ_B:
31242
    case AArch64::URSHLR_ZPmZ_D:
31243
    case AArch64::URSHLR_ZPmZ_H:
31244
    case AArch64::URSHLR_ZPmZ_S:
31245
    case AArch64::URSHL_ZPmZ_B:
31246
    case AArch64::URSHL_ZPmZ_D:
31247
    case AArch64::URSHL_ZPmZ_H:
31248
    case AArch64::URSHL_ZPmZ_S:
31249
    case AArch64::USQADD_ZPmZ_B:
31250
    case AArch64::USQADD_ZPmZ_D:
31251
    case AArch64::USQADD_ZPmZ_H:
31252
    case AArch64::USQADD_ZPmZ_S: {
31253
      switch (OpNum) {
31254
      case 1:
31255
        // op: Pg
31256
        return 10;
31257
      case 3:
31258
        // op: Zm
31259
        return 5;
31260
      case 0:
31261
        // op: Zdn
31262
        return 0;
31263
      }
31264
      break;
31265
    }
31266
    case AArch64::SADALP_ZPmZ_D:
31267
    case AArch64::SADALP_ZPmZ_H:
31268
    case AArch64::SADALP_ZPmZ_S:
31269
    case AArch64::UADALP_ZPmZ_D:
31270
    case AArch64::UADALP_ZPmZ_H:
31271
    case AArch64::UADALP_ZPmZ_S: {
31272
      switch (OpNum) {
31273
      case 1:
31274
        // op: Pg
31275
        return 10;
31276
      case 3:
31277
        // op: Zn
31278
        return 5;
31279
      case 0:
31280
        // op: Zda
31281
        return 0;
31282
      }
31283
      break;
31284
    }
31285
    case AArch64::SST1B_D_IMM:
31286
    case AArch64::SST1B_S_IMM:
31287
    case AArch64::SST1D_IMM:
31288
    case AArch64::SST1H_D_IMM:
31289
    case AArch64::SST1H_S_IMM:
31290
    case AArch64::SST1W_D_IMM:
31291
    case AArch64::SST1W_IMM: {
31292
      switch (OpNum) {
31293
      case 1:
31294
        // op: Pg
31295
        return 10;
31296
      case 3:
31297
        // op: imm5
31298
        return 16;
31299
      case 2:
31300
        // op: Zn
31301
        return 5;
31302
      case 0:
31303
        // op: Zt
31304
        return 0;
31305
      }
31306
      break;
31307
    }
31308
    case AArch64::FMAD_ZPmZZ_D:
31309
    case AArch64::FMAD_ZPmZZ_H:
31310
    case AArch64::FMAD_ZPmZZ_S:
31311
    case AArch64::FMSB_ZPmZZ_D:
31312
    case AArch64::FMSB_ZPmZZ_H:
31313
    case AArch64::FMSB_ZPmZZ_S:
31314
    case AArch64::FNMAD_ZPmZZ_D:
31315
    case AArch64::FNMAD_ZPmZZ_H:
31316
    case AArch64::FNMAD_ZPmZZ_S:
31317
    case AArch64::FNMSB_ZPmZZ_D:
31318
    case AArch64::FNMSB_ZPmZZ_H:
31319
    case AArch64::FNMSB_ZPmZZ_S: {
31320
      switch (OpNum) {
31321
      case 1:
31322
        // op: Pg
31323
        return 10;
31324
      case 4:
31325
        // op: Za
31326
        return 16;
31327
      case 0:
31328
        // op: Zdn
31329
        return 0;
31330
      case 3:
31331
        // op: Zm
31332
        return 5;
31333
      }
31334
      break;
31335
    }
31336
    case AArch64::BF16DOTlanev4bf16:
31337
    case AArch64::BF16DOTlanev8bf16:
31338
    case AArch64::BFMLALBIdx:
31339
    case AArch64::BFMLALTIdx:
31340
    case AArch64::FDOTlanev4f16:
31341
    case AArch64::FDOTlanev8f8:
31342
    case AArch64::FDOTlanev8f16:
31343
    case AArch64::FDOTlanev16f8:
31344
    case AArch64::FMLAL2lanev4f16:
31345
    case AArch64::FMLAL2lanev8f16:
31346
    case AArch64::FMLALBlanev8f16:
31347
    case AArch64::FMLALLBBlanev4f32:
31348
    case AArch64::FMLALLBTlanev4f32:
31349
    case AArch64::FMLALLTBlanev4f32:
31350
    case AArch64::FMLALLTTlanev4f32:
31351
    case AArch64::FMLALTlanev8f16:
31352
    case AArch64::FMLALlanev4f16:
31353
    case AArch64::FMLALlanev8f16:
31354
    case AArch64::FMLAv1i16_indexed:
31355
    case AArch64::FMLAv1i32_indexed:
31356
    case AArch64::FMLAv1i64_indexed:
31357
    case AArch64::FMLAv2i32_indexed:
31358
    case AArch64::FMLAv2i64_indexed:
31359
    case AArch64::FMLAv4i16_indexed:
31360
    case AArch64::FMLAv4i32_indexed:
31361
    case AArch64::FMLAv8i16_indexed:
31362
    case AArch64::FMLSL2lanev4f16:
31363
    case AArch64::FMLSL2lanev8f16:
31364
    case AArch64::FMLSLlanev4f16:
31365
    case AArch64::FMLSLlanev8f16:
31366
    case AArch64::FMLSv1i16_indexed:
31367
    case AArch64::FMLSv1i32_indexed:
31368
    case AArch64::FMLSv1i64_indexed:
31369
    case AArch64::FMLSv2i32_indexed:
31370
    case AArch64::FMLSv2i64_indexed:
31371
    case AArch64::FMLSv4i16_indexed:
31372
    case AArch64::FMLSv4i32_indexed:
31373
    case AArch64::FMLSv8i16_indexed:
31374
    case AArch64::MLAv2i32_indexed:
31375
    case AArch64::MLAv4i16_indexed:
31376
    case AArch64::MLAv4i32_indexed:
31377
    case AArch64::MLAv8i16_indexed:
31378
    case AArch64::MLSv2i32_indexed:
31379
    case AArch64::MLSv4i16_indexed:
31380
    case AArch64::MLSv4i32_indexed:
31381
    case AArch64::MLSv8i16_indexed:
31382
    case AArch64::SDOTlanev8i8:
31383
    case AArch64::SDOTlanev16i8:
31384
    case AArch64::SMLALv2i32_indexed:
31385
    case AArch64::SMLALv4i16_indexed:
31386
    case AArch64::SMLALv4i32_indexed:
31387
    case AArch64::SMLALv8i16_indexed:
31388
    case AArch64::SMLSLv2i32_indexed:
31389
    case AArch64::SMLSLv4i16_indexed:
31390
    case AArch64::SMLSLv4i32_indexed:
31391
    case AArch64::SMLSLv8i16_indexed:
31392
    case AArch64::SQDMLALv1i32_indexed:
31393
    case AArch64::SQDMLALv1i64_indexed:
31394
    case AArch64::SQDMLALv2i32_indexed:
31395
    case AArch64::SQDMLALv4i16_indexed:
31396
    case AArch64::SQDMLALv4i32_indexed:
31397
    case AArch64::SQDMLALv8i16_indexed:
31398
    case AArch64::SQDMLSLv1i32_indexed:
31399
    case AArch64::SQDMLSLv1i64_indexed:
31400
    case AArch64::SQDMLSLv2i32_indexed:
31401
    case AArch64::SQDMLSLv4i16_indexed:
31402
    case AArch64::SQDMLSLv4i32_indexed:
31403
    case AArch64::SQDMLSLv8i16_indexed:
31404
    case AArch64::SQRDMLAHv1i16_indexed:
31405
    case AArch64::SQRDMLAHv1i32_indexed:
31406
    case AArch64::SQRDMLAHv2i32_indexed:
31407
    case AArch64::SQRDMLAHv4i16_indexed:
31408
    case AArch64::SQRDMLAHv4i32_indexed:
31409
    case AArch64::SQRDMLAHv8i16_indexed:
31410
    case AArch64::SQRDMLSHv1i16_indexed:
31411
    case AArch64::SQRDMLSHv1i32_indexed:
31412
    case AArch64::SQRDMLSHv2i32_indexed:
31413
    case AArch64::SQRDMLSHv4i16_indexed:
31414
    case AArch64::SQRDMLSHv4i32_indexed:
31415
    case AArch64::SQRDMLSHv8i16_indexed:
31416
    case AArch64::SUDOTlanev8i8:
31417
    case AArch64::SUDOTlanev16i8:
31418
    case AArch64::UDOTlanev8i8:
31419
    case AArch64::UDOTlanev16i8:
31420
    case AArch64::UMLALv2i32_indexed:
31421
    case AArch64::UMLALv4i16_indexed:
31422
    case AArch64::UMLALv4i32_indexed:
31423
    case AArch64::UMLALv8i16_indexed:
31424
    case AArch64::UMLSLv2i32_indexed:
31425
    case AArch64::UMLSLv4i16_indexed:
31426
    case AArch64::UMLSLv4i32_indexed:
31427
    case AArch64::UMLSLv8i16_indexed:
31428
    case AArch64::USDOTlanev8i8:
31429
    case AArch64::USDOTlanev16i8: {
31430
      switch (OpNum) {
31431
      case 1:
31432
        // op: Rd
31433
        return 0;
31434
      case 2:
31435
        // op: Rn
31436
        return 5;
31437
      case 3:
31438
        // op: Rm
31439
        return 16;
31440
      case 4:
31441
        // op: idx
31442
        return 11;
31443
      }
31444
      break;
31445
    }
31446
    case AArch64::FCMLAv2f32:
31447
    case AArch64::FCMLAv2f64:
31448
    case AArch64::FCMLAv4f16:
31449
    case AArch64::FCMLAv4f32:
31450
    case AArch64::FCMLAv8f16: {
31451
      switch (OpNum) {
31452
      case 1:
31453
        // op: Rd
31454
        return 0;
31455
      case 2:
31456
        // op: Rn
31457
        return 5;
31458
      case 3:
31459
        // op: Rm
31460
        return 16;
31461
      case 4:
31462
        // op: rot
31463
        return 11;
31464
      }
31465
      break;
31466
    }
31467
    case AArch64::FCMLAv4f32_indexed:
31468
    case AArch64::FCMLAv8f16_indexed: {
31469
      switch (OpNum) {
31470
      case 1:
31471
        // op: Rd
31472
        return 0;
31473
      case 2:
31474
        // op: Rn
31475
        return 5;
31476
      case 3:
31477
        // op: Rm
31478
        return 16;
31479
      case 5:
31480
        // op: rot
31481
        return 13;
31482
      case 4:
31483
        // op: idx
31484
        return 11;
31485
      }
31486
      break;
31487
    }
31488
    case AArch64::FCMLAv4f16_indexed: {
31489
      switch (OpNum) {
31490
      case 1:
31491
        // op: Rd
31492
        return 0;
31493
      case 2:
31494
        // op: Rn
31495
        return 5;
31496
      case 3:
31497
        // op: Rm
31498
        return 16;
31499
      case 5:
31500
        // op: rot
31501
        return 13;
31502
      case 4:
31503
        // op: idx
31504
        return 21;
31505
      }
31506
      break;
31507
    }
31508
    case AArch64::ADDHNv2i64_v4i32:
31509
    case AArch64::ADDHNv4i32_v8i16:
31510
    case AArch64::ADDHNv8i16_v16i8:
31511
    case AArch64::BFDOTv4bf16:
31512
    case AArch64::BFDOTv8bf16:
31513
    case AArch64::BFMLALB:
31514
    case AArch64::BFMLALT:
31515
    case AArch64::BFMMLA:
31516
    case AArch64::BIFv8i8:
31517
    case AArch64::BIFv16i8:
31518
    case AArch64::BITv8i8:
31519
    case AArch64::BITv16i8:
31520
    case AArch64::BSLv8i8:
31521
    case AArch64::BSLv16i8:
31522
    case AArch64::FCVTN_F32_F82v16f8:
31523
    case AArch64::FDOTv2f32:
31524
    case AArch64::FDOTv4f16:
31525
    case AArch64::FDOTv4f32:
31526
    case AArch64::FDOTv8f16:
31527
    case AArch64::FMLAL2v4f16:
31528
    case AArch64::FMLAL2v8f16:
31529
    case AArch64::FMLALBv8f16:
31530
    case AArch64::FMLALLBBv4f32:
31531
    case AArch64::FMLALLBTv4f32:
31532
    case AArch64::FMLALLTBv4f32:
31533
    case AArch64::FMLALLTTv4f32:
31534
    case AArch64::FMLALTv8f16:
31535
    case AArch64::FMLALv4f16:
31536
    case AArch64::FMLALv8f16:
31537
    case AArch64::FMLAv2f32:
31538
    case AArch64::FMLAv2f64:
31539
    case AArch64::FMLAv4f16:
31540
    case AArch64::FMLAv4f32:
31541
    case AArch64::FMLAv8f16:
31542
    case AArch64::FMLSL2v4f16:
31543
    case AArch64::FMLSL2v8f16:
31544
    case AArch64::FMLSLv4f16:
31545
    case AArch64::FMLSLv8f16:
31546
    case AArch64::FMLSv2f32:
31547
    case AArch64::FMLSv2f64:
31548
    case AArch64::FMLSv4f16:
31549
    case AArch64::FMLSv4f32:
31550
    case AArch64::FMLSv8f16:
31551
    case AArch64::MLAv2i32:
31552
    case AArch64::MLAv4i16:
31553
    case AArch64::MLAv4i32:
31554
    case AArch64::MLAv8i8:
31555
    case AArch64::MLAv8i16:
31556
    case AArch64::MLAv16i8:
31557
    case AArch64::MLSv2i32:
31558
    case AArch64::MLSv4i16:
31559
    case AArch64::MLSv4i32:
31560
    case AArch64::MLSv8i8:
31561
    case AArch64::MLSv8i16:
31562
    case AArch64::MLSv16i8:
31563
    case AArch64::RADDHNv2i64_v4i32:
31564
    case AArch64::RADDHNv4i32_v8i16:
31565
    case AArch64::RADDHNv8i16_v16i8:
31566
    case AArch64::RSUBHNv2i64_v4i32:
31567
    case AArch64::RSUBHNv4i32_v8i16:
31568
    case AArch64::RSUBHNv8i16_v16i8:
31569
    case AArch64::SABALv2i32_v2i64:
31570
    case AArch64::SABALv4i16_v4i32:
31571
    case AArch64::SABALv4i32_v2i64:
31572
    case AArch64::SABALv8i8_v8i16:
31573
    case AArch64::SABALv8i16_v4i32:
31574
    case AArch64::SABALv16i8_v8i16:
31575
    case AArch64::SABAv2i32:
31576
    case AArch64::SABAv4i16:
31577
    case AArch64::SABAv4i32:
31578
    case AArch64::SABAv8i8:
31579
    case AArch64::SABAv8i16:
31580
    case AArch64::SABAv16i8:
31581
    case AArch64::SDOTv8i8:
31582
    case AArch64::SDOTv16i8:
31583
    case AArch64::SHA1Crrr:
31584
    case AArch64::SHA1Mrrr:
31585
    case AArch64::SHA1Prrr:
31586
    case AArch64::SHA1SU0rrr:
31587
    case AArch64::SHA256H2rrr:
31588
    case AArch64::SHA256Hrrr:
31589
    case AArch64::SHA256SU1rrr:
31590
    case AArch64::SMLALv2i32_v2i64:
31591
    case AArch64::SMLALv4i16_v4i32:
31592
    case AArch64::SMLALv4i32_v2i64:
31593
    case AArch64::SMLALv8i8_v8i16:
31594
    case AArch64::SMLALv8i16_v4i32:
31595
    case AArch64::SMLALv16i8_v8i16:
31596
    case AArch64::SMLSLv2i32_v2i64:
31597
    case AArch64::SMLSLv4i16_v4i32:
31598
    case AArch64::SMLSLv4i32_v2i64:
31599
    case AArch64::SMLSLv8i8_v8i16:
31600
    case AArch64::SMLSLv8i16_v4i32:
31601
    case AArch64::SMLSLv16i8_v8i16:
31602
    case AArch64::SMMLA:
31603
    case AArch64::SQDMLALi16:
31604
    case AArch64::SQDMLALi32:
31605
    case AArch64::SQDMLALv2i32_v2i64:
31606
    case AArch64::SQDMLALv4i16_v4i32:
31607
    case AArch64::SQDMLALv4i32_v2i64:
31608
    case AArch64::SQDMLALv8i16_v4i32:
31609
    case AArch64::SQDMLSLi16:
31610
    case AArch64::SQDMLSLi32:
31611
    case AArch64::SQDMLSLv2i32_v2i64:
31612
    case AArch64::SQDMLSLv4i16_v4i32:
31613
    case AArch64::SQDMLSLv4i32_v2i64:
31614
    case AArch64::SQDMLSLv8i16_v4i32:
31615
    case AArch64::SQRDMLAHv1i16:
31616
    case AArch64::SQRDMLAHv1i32:
31617
    case AArch64::SQRDMLAHv2i32:
31618
    case AArch64::SQRDMLAHv4i16:
31619
    case AArch64::SQRDMLAHv4i32:
31620
    case AArch64::SQRDMLAHv8i16:
31621
    case AArch64::SQRDMLSHv1i16:
31622
    case AArch64::SQRDMLSHv1i32:
31623
    case AArch64::SQRDMLSHv2i32:
31624
    case AArch64::SQRDMLSHv4i16:
31625
    case AArch64::SQRDMLSHv4i32:
31626
    case AArch64::SQRDMLSHv8i16:
31627
    case AArch64::SUBHNv2i64_v4i32:
31628
    case AArch64::SUBHNv4i32_v8i16:
31629
    case AArch64::SUBHNv8i16_v16i8:
31630
    case AArch64::UABALv2i32_v2i64:
31631
    case AArch64::UABALv4i16_v4i32:
31632
    case AArch64::UABALv4i32_v2i64:
31633
    case AArch64::UABALv8i8_v8i16:
31634
    case AArch64::UABALv8i16_v4i32:
31635
    case AArch64::UABALv16i8_v8i16:
31636
    case AArch64::UABAv2i32:
31637
    case AArch64::UABAv4i16:
31638
    case AArch64::UABAv4i32:
31639
    case AArch64::UABAv8i8:
31640
    case AArch64::UABAv8i16:
31641
    case AArch64::UABAv16i8:
31642
    case AArch64::UDOTv8i8:
31643
    case AArch64::UDOTv16i8:
31644
    case AArch64::UMLALv2i32_v2i64:
31645
    case AArch64::UMLALv4i16_v4i32:
31646
    case AArch64::UMLALv4i32_v2i64:
31647
    case AArch64::UMLALv8i8_v8i16:
31648
    case AArch64::UMLALv8i16_v4i32:
31649
    case AArch64::UMLALv16i8_v8i16:
31650
    case AArch64::UMLSLv2i32_v2i64:
31651
    case AArch64::UMLSLv4i16_v4i32:
31652
    case AArch64::UMLSLv4i32_v2i64:
31653
    case AArch64::UMLSLv8i8_v8i16:
31654
    case AArch64::UMLSLv8i16_v4i32:
31655
    case AArch64::UMLSLv16i8_v8i16:
31656
    case AArch64::UMMLA:
31657
    case AArch64::USDOTv8i8:
31658
    case AArch64::USDOTv16i8:
31659
    case AArch64::USMMLA: {
31660
      switch (OpNum) {
31661
      case 1:
31662
        // op: Rd
31663
        return 0;
31664
      case 2:
31665
        // op: Rn
31666
        return 5;
31667
      case 3:
31668
        // op: Rm
31669
        return 16;
31670
      }
31671
      break;
31672
    }
31673
    case AArch64::RSHRNv4i32_shift:
31674
    case AArch64::RSHRNv8i16_shift:
31675
    case AArch64::RSHRNv16i8_shift:
31676
    case AArch64::SHRNv4i32_shift:
31677
    case AArch64::SHRNv8i16_shift:
31678
    case AArch64::SHRNv16i8_shift:
31679
    case AArch64::SLId:
31680
    case AArch64::SLIv2i32_shift:
31681
    case AArch64::SLIv2i64_shift:
31682
    case AArch64::SLIv4i16_shift:
31683
    case AArch64::SLIv4i32_shift:
31684
    case AArch64::SLIv8i8_shift:
31685
    case AArch64::SLIv8i16_shift:
31686
    case AArch64::SLIv16i8_shift:
31687
    case AArch64::SQRSHRNv4i32_shift:
31688
    case AArch64::SQRSHRNv8i16_shift:
31689
    case AArch64::SQRSHRNv16i8_shift:
31690
    case AArch64::SQRSHRUNv4i32_shift:
31691
    case AArch64::SQRSHRUNv8i16_shift:
31692
    case AArch64::SQRSHRUNv16i8_shift:
31693
    case AArch64::SQSHRNv4i32_shift:
31694
    case AArch64::SQSHRNv8i16_shift:
31695
    case AArch64::SQSHRNv16i8_shift:
31696
    case AArch64::SQSHRUNv4i32_shift:
31697
    case AArch64::SQSHRUNv8i16_shift:
31698
    case AArch64::SQSHRUNv16i8_shift:
31699
    case AArch64::SRId:
31700
    case AArch64::SRIv2i32_shift:
31701
    case AArch64::SRIv2i64_shift:
31702
    case AArch64::SRIv4i16_shift:
31703
    case AArch64::SRIv4i32_shift:
31704
    case AArch64::SRIv8i8_shift:
31705
    case AArch64::SRIv8i16_shift:
31706
    case AArch64::SRIv16i8_shift:
31707
    case AArch64::SRSRAd:
31708
    case AArch64::SRSRAv2i32_shift:
31709
    case AArch64::SRSRAv2i64_shift:
31710
    case AArch64::SRSRAv4i16_shift:
31711
    case AArch64::SRSRAv4i32_shift:
31712
    case AArch64::SRSRAv8i8_shift:
31713
    case AArch64::SRSRAv8i16_shift:
31714
    case AArch64::SRSRAv16i8_shift:
31715
    case AArch64::SSRAd:
31716
    case AArch64::SSRAv2i32_shift:
31717
    case AArch64::SSRAv2i64_shift:
31718
    case AArch64::SSRAv4i16_shift:
31719
    case AArch64::SSRAv4i32_shift:
31720
    case AArch64::SSRAv8i8_shift:
31721
    case AArch64::SSRAv8i16_shift:
31722
    case AArch64::SSRAv16i8_shift:
31723
    case AArch64::UQRSHRNv4i32_shift:
31724
    case AArch64::UQRSHRNv8i16_shift:
31725
    case AArch64::UQRSHRNv16i8_shift:
31726
    case AArch64::UQSHRNv4i32_shift:
31727
    case AArch64::UQSHRNv8i16_shift:
31728
    case AArch64::UQSHRNv16i8_shift:
31729
    case AArch64::URSRAd:
31730
    case AArch64::URSRAv2i32_shift:
31731
    case AArch64::URSRAv2i64_shift:
31732
    case AArch64::URSRAv4i16_shift:
31733
    case AArch64::URSRAv4i32_shift:
31734
    case AArch64::URSRAv8i8_shift:
31735
    case AArch64::URSRAv8i16_shift:
31736
    case AArch64::URSRAv16i8_shift:
31737
    case AArch64::USRAd:
31738
    case AArch64::USRAv2i32_shift:
31739
    case AArch64::USRAv2i64_shift:
31740
    case AArch64::USRAv4i16_shift:
31741
    case AArch64::USRAv4i32_shift:
31742
    case AArch64::USRAv8i8_shift:
31743
    case AArch64::USRAv8i16_shift:
31744
    case AArch64::USRAv16i8_shift: {
31745
      switch (OpNum) {
31746
      case 1:
31747
        // op: Rd
31748
        return 0;
31749
      case 2:
31750
        // op: Rn
31751
        return 5;
31752
      case 3:
31753
        // op: imm
31754
        return 16;
31755
      }
31756
      break;
31757
    }
31758
    case AArch64::AESDrr:
31759
    case AArch64::AESErr:
31760
    case AArch64::AUTDA:
31761
    case AArch64::AUTDB:
31762
    case AArch64::AUTIA:
31763
    case AArch64::AUTIB:
31764
    case AArch64::BFCVTN2:
31765
    case AArch64::FCVTNv4i32:
31766
    case AArch64::FCVTNv8i16:
31767
    case AArch64::FCVTXNv4f32:
31768
    case AArch64::PACDA:
31769
    case AArch64::PACDB:
31770
    case AArch64::PACIA:
31771
    case AArch64::PACIB:
31772
    case AArch64::SADALPv2i32_v1i64:
31773
    case AArch64::SADALPv4i16_v2i32:
31774
    case AArch64::SADALPv4i32_v2i64:
31775
    case AArch64::SADALPv8i8_v4i16:
31776
    case AArch64::SADALPv8i16_v4i32:
31777
    case AArch64::SADALPv16i8_v8i16:
31778
    case AArch64::SHA1SU1rr:
31779
    case AArch64::SHA256SU0rr:
31780
    case AArch64::SQXTNv4i32:
31781
    case AArch64::SQXTNv8i16:
31782
    case AArch64::SQXTNv16i8:
31783
    case AArch64::SQXTUNv4i32:
31784
    case AArch64::SQXTUNv8i16:
31785
    case AArch64::SQXTUNv16i8:
31786
    case AArch64::SUQADDv1i8:
31787
    case AArch64::SUQADDv1i16:
31788
    case AArch64::SUQADDv1i32:
31789
    case AArch64::SUQADDv1i64:
31790
    case AArch64::SUQADDv2i32:
31791
    case AArch64::SUQADDv2i64:
31792
    case AArch64::SUQADDv4i16:
31793
    case AArch64::SUQADDv4i32:
31794
    case AArch64::SUQADDv8i8:
31795
    case AArch64::SUQADDv8i16:
31796
    case AArch64::SUQADDv16i8:
31797
    case AArch64::UADALPv2i32_v1i64:
31798
    case AArch64::UADALPv4i16_v2i32:
31799
    case AArch64::UADALPv4i32_v2i64:
31800
    case AArch64::UADALPv8i8_v4i16:
31801
    case AArch64::UADALPv8i16_v4i32:
31802
    case AArch64::UADALPv16i8_v8i16:
31803
    case AArch64::UQXTNv4i32:
31804
    case AArch64::UQXTNv8i16:
31805
    case AArch64::UQXTNv16i8:
31806
    case AArch64::USQADDv1i8:
31807
    case AArch64::USQADDv1i16:
31808
    case AArch64::USQADDv1i32:
31809
    case AArch64::USQADDv1i64:
31810
    case AArch64::USQADDv2i32:
31811
    case AArch64::USQADDv2i64:
31812
    case AArch64::USQADDv4i16:
31813
    case AArch64::USQADDv4i32:
31814
    case AArch64::USQADDv8i8:
31815
    case AArch64::USQADDv8i16:
31816
    case AArch64::USQADDv16i8:
31817
    case AArch64::XTNv4i32:
31818
    case AArch64::XTNv8i16:
31819
    case AArch64::XTNv16i8: {
31820
      switch (OpNum) {
31821
      case 1:
31822
        // op: Rd
31823
        return 0;
31824
      case 2:
31825
        // op: Rn
31826
        return 5;
31827
      }
31828
      break;
31829
    }
31830
    case AArch64::BICv2i32:
31831
    case AArch64::BICv4i16:
31832
    case AArch64::BICv4i32:
31833
    case AArch64::BICv8i16:
31834
    case AArch64::ORRv2i32:
31835
    case AArch64::ORRv4i16:
31836
    case AArch64::ORRv4i32:
31837
    case AArch64::ORRv8i16: {
31838
      switch (OpNum) {
31839
      case 1:
31840
        // op: Rd
31841
        return 0;
31842
      case 2:
31843
        // op: imm8
31844
        return 5;
31845
      case 3:
31846
        // op: shift
31847
        return 13;
31848
      }
31849
      break;
31850
    }
31851
    case AArch64::INSvi8lane: {
31852
      switch (OpNum) {
31853
      case 1:
31854
        // op: Rd
31855
        return 0;
31856
      case 3:
31857
        // op: Rn
31858
        return 5;
31859
      case 2:
31860
        // op: idx
31861
        return 17;
31862
      case 4:
31863
        // op: idx2
31864
        return 11;
31865
      }
31866
      break;
31867
    }
31868
    case AArch64::INSvi8gpr: {
31869
      switch (OpNum) {
31870
      case 1:
31871
        // op: Rd
31872
        return 0;
31873
      case 3:
31874
        // op: Rn
31875
        return 5;
31876
      case 2:
31877
        // op: idx
31878
        return 17;
31879
      }
31880
      break;
31881
    }
31882
    case AArch64::INSvi16lane: {
31883
      switch (OpNum) {
31884
      case 1:
31885
        // op: Rd
31886
        return 0;
31887
      case 3:
31888
        // op: Rn
31889
        return 5;
31890
      case 2:
31891
        // op: idx
31892
        return 18;
31893
      case 4:
31894
        // op: idx2
31895
        return 12;
31896
      }
31897
      break;
31898
    }
31899
    case AArch64::INSvi16gpr: {
31900
      switch (OpNum) {
31901
      case 1:
31902
        // op: Rd
31903
        return 0;
31904
      case 3:
31905
        // op: Rn
31906
        return 5;
31907
      case 2:
31908
        // op: idx
31909
        return 18;
31910
      }
31911
      break;
31912
    }
31913
    case AArch64::INSvi32lane: {
31914
      switch (OpNum) {
31915
      case 1:
31916
        // op: Rd
31917
        return 0;
31918
      case 3:
31919
        // op: Rn
31920
        return 5;
31921
      case 2:
31922
        // op: idx
31923
        return 19;
31924
      case 4:
31925
        // op: idx2
31926
        return 13;
31927
      }
31928
      break;
31929
    }
31930
    case AArch64::INSvi32gpr: {
31931
      switch (OpNum) {
31932
      case 1:
31933
        // op: Rd
31934
        return 0;
31935
      case 3:
31936
        // op: Rn
31937
        return 5;
31938
      case 2:
31939
        // op: idx
31940
        return 19;
31941
      }
31942
      break;
31943
    }
31944
    case AArch64::INSvi64lane: {
31945
      switch (OpNum) {
31946
      case 1:
31947
        // op: Rd
31948
        return 0;
31949
      case 3:
31950
        // op: Rn
31951
        return 5;
31952
      case 2:
31953
        // op: idx
31954
        return 20;
31955
      case 4:
31956
        // op: idx2
31957
        return 14;
31958
      }
31959
      break;
31960
    }
31961
    case AArch64::INSvi64gpr: {
31962
      switch (OpNum) {
31963
      case 1:
31964
        // op: Rd
31965
        return 0;
31966
      case 3:
31967
        // op: Rn
31968
        return 5;
31969
      case 2:
31970
        // op: idx
31971
        return 20;
31972
      }
31973
      break;
31974
    }
31975
    case AArch64::AUTDZA:
31976
    case AArch64::AUTDZB:
31977
    case AArch64::AUTIZA:
31978
    case AArch64::AUTIZB:
31979
    case AArch64::PACDZA:
31980
    case AArch64::PACDZB:
31981
    case AArch64::PACIZA:
31982
    case AArch64::PACIZB: {
31983
      switch (OpNum) {
31984
      case 1:
31985
        // op: Rd
31986
        return 0;
31987
      }
31988
      break;
31989
    }
31990
    case AArch64::CTERMEQ_WW:
31991
    case AArch64::CTERMEQ_XX:
31992
    case AArch64::CTERMNE_WW:
31993
    case AArch64::CTERMNE_XX:
31994
    case AArch64::FCMPDrr:
31995
    case AArch64::FCMPEDrr:
31996
    case AArch64::FCMPEHrr:
31997
    case AArch64::FCMPESrr:
31998
    case AArch64::FCMPHrr:
31999
    case AArch64::FCMPSrr: {
32000
      switch (OpNum) {
32001
      case 1:
32002
        // op: Rm
32003
        return 16;
32004
      case 0:
32005
        // op: Rn
32006
        return 5;
32007
      }
32008
      break;
32009
    }
32010
    case AArch64::ST2Gi:
32011
    case AArch64::STGi:
32012
    case AArch64::STZ2Gi:
32013
    case AArch64::STZGi: {
32014
      switch (OpNum) {
32015
      case 1:
32016
        // op: Rn
32017
        return 5;
32018
      case 0:
32019
        // op: Rt
32020
        return 0;
32021
      case 2:
32022
        // op: offset
32023
        return 12;
32024
      }
32025
      break;
32026
    }
32027
    case AArch64::LDAPRB:
32028
    case AArch64::LDAPRH:
32029
    case AArch64::LDAPRW:
32030
    case AArch64::LDAPRX:
32031
    case AArch64::LDGM:
32032
    case AArch64::STGM:
32033
    case AArch64::STZGM: {
32034
      switch (OpNum) {
32035
      case 1:
32036
        // op: Rn
32037
        return 5;
32038
      case 0:
32039
        // op: Rt
32040
        return 0;
32041
      }
32042
      break;
32043
    }
32044
    case AArch64::INDEX_RI_B:
32045
    case AArch64::INDEX_RI_D:
32046
    case AArch64::INDEX_RI_H:
32047
    case AArch64::INDEX_RI_S: {
32048
      switch (OpNum) {
32049
      case 1:
32050
        // op: Rn
32051
        return 5;
32052
      case 0:
32053
        // op: Zd
32054
        return 0;
32055
      case 2:
32056
        // op: imm5
32057
        return 16;
32058
      }
32059
      break;
32060
    }
32061
    case AArch64::DUP_ZR_B:
32062
    case AArch64::DUP_ZR_D:
32063
    case AArch64::DUP_ZR_H:
32064
    case AArch64::DUP_ZR_S: {
32065
      switch (OpNum) {
32066
      case 1:
32067
        // op: Rn
32068
        return 5;
32069
      case 0:
32070
        // op: Zd
32071
        return 0;
32072
      }
32073
      break;
32074
    }
32075
    case AArch64::LDR_ZXI:
32076
    case AArch64::STR_ZXI: {
32077
      switch (OpNum) {
32078
      case 1:
32079
        // op: Rn
32080
        return 5;
32081
      case 0:
32082
        // op: Zt
32083
        return 0;
32084
      case 2:
32085
        // op: imm9
32086
        return 10;
32087
      }
32088
      break;
32089
    }
32090
    case AArch64::LDR_TX:
32091
    case AArch64::STR_TX: {
32092
      switch (OpNum) {
32093
      case 1:
32094
        // op: Rn
32095
        return 5;
32096
      }
32097
      break;
32098
    }
32099
    case AArch64::LDADDAB:
32100
    case AArch64::LDADDAH:
32101
    case AArch64::LDADDALB:
32102
    case AArch64::LDADDALH:
32103
    case AArch64::LDADDALW:
32104
    case AArch64::LDADDALX:
32105
    case AArch64::LDADDAW:
32106
    case AArch64::LDADDAX:
32107
    case AArch64::LDADDB:
32108
    case AArch64::LDADDH:
32109
    case AArch64::LDADDLB:
32110
    case AArch64::LDADDLH:
32111
    case AArch64::LDADDLW:
32112
    case AArch64::LDADDLX:
32113
    case AArch64::LDADDW:
32114
    case AArch64::LDADDX:
32115
    case AArch64::LDCLRAB:
32116
    case AArch64::LDCLRAH:
32117
    case AArch64::LDCLRALB:
32118
    case AArch64::LDCLRALH:
32119
    case AArch64::LDCLRALW:
32120
    case AArch64::LDCLRALX:
32121
    case AArch64::LDCLRAW:
32122
    case AArch64::LDCLRAX:
32123
    case AArch64::LDCLRB:
32124
    case AArch64::LDCLRH:
32125
    case AArch64::LDCLRLB:
32126
    case AArch64::LDCLRLH:
32127
    case AArch64::LDCLRLW:
32128
    case AArch64::LDCLRLX:
32129
    case AArch64::LDCLRW:
32130
    case AArch64::LDCLRX:
32131
    case AArch64::LDEORAB:
32132
    case AArch64::LDEORAH:
32133
    case AArch64::LDEORALB:
32134
    case AArch64::LDEORALH:
32135
    case AArch64::LDEORALW:
32136
    case AArch64::LDEORALX:
32137
    case AArch64::LDEORAW:
32138
    case AArch64::LDEORAX:
32139
    case AArch64::LDEORB:
32140
    case AArch64::LDEORH:
32141
    case AArch64::LDEORLB:
32142
    case AArch64::LDEORLH:
32143
    case AArch64::LDEORLW:
32144
    case AArch64::LDEORLX:
32145
    case AArch64::LDEORW:
32146
    case AArch64::LDEORX:
32147
    case AArch64::LDSETAB:
32148
    case AArch64::LDSETAH:
32149
    case AArch64::LDSETALB:
32150
    case AArch64::LDSETALH:
32151
    case AArch64::LDSETALW:
32152
    case AArch64::LDSETALX:
32153
    case AArch64::LDSETAW:
32154
    case AArch64::LDSETAX:
32155
    case AArch64::LDSETB:
32156
    case AArch64::LDSETH:
32157
    case AArch64::LDSETLB:
32158
    case AArch64::LDSETLH:
32159
    case AArch64::LDSETLW:
32160
    case AArch64::LDSETLX:
32161
    case AArch64::LDSETW:
32162
    case AArch64::LDSETX:
32163
    case AArch64::LDSMAXAB:
32164
    case AArch64::LDSMAXAH:
32165
    case AArch64::LDSMAXALB:
32166
    case AArch64::LDSMAXALH:
32167
    case AArch64::LDSMAXALW:
32168
    case AArch64::LDSMAXALX:
32169
    case AArch64::LDSMAXAW:
32170
    case AArch64::LDSMAXAX:
32171
    case AArch64::LDSMAXB:
32172
    case AArch64::LDSMAXH:
32173
    case AArch64::LDSMAXLB:
32174
    case AArch64::LDSMAXLH:
32175
    case AArch64::LDSMAXLW:
32176
    case AArch64::LDSMAXLX:
32177
    case AArch64::LDSMAXW:
32178
    case AArch64::LDSMAXX:
32179
    case AArch64::LDSMINAB:
32180
    case AArch64::LDSMINAH:
32181
    case AArch64::LDSMINALB:
32182
    case AArch64::LDSMINALH:
32183
    case AArch64::LDSMINALW:
32184
    case AArch64::LDSMINALX:
32185
    case AArch64::LDSMINAW:
32186
    case AArch64::LDSMINAX:
32187
    case AArch64::LDSMINB:
32188
    case AArch64::LDSMINH:
32189
    case AArch64::LDSMINLB:
32190
    case AArch64::LDSMINLH:
32191
    case AArch64::LDSMINLW:
32192
    case AArch64::LDSMINLX:
32193
    case AArch64::LDSMINW:
32194
    case AArch64::LDSMINX:
32195
    case AArch64::LDUMAXAB:
32196
    case AArch64::LDUMAXAH:
32197
    case AArch64::LDUMAXALB:
32198
    case AArch64::LDUMAXALH:
32199
    case AArch64::LDUMAXALW:
32200
    case AArch64::LDUMAXALX:
32201
    case AArch64::LDUMAXAW:
32202
    case AArch64::LDUMAXAX:
32203
    case AArch64::LDUMAXB:
32204
    case AArch64::LDUMAXH:
32205
    case AArch64::LDUMAXLB:
32206
    case AArch64::LDUMAXLH:
32207
    case AArch64::LDUMAXLW:
32208
    case AArch64::LDUMAXLX:
32209
    case AArch64::LDUMAXW:
32210
    case AArch64::LDUMAXX:
32211
    case AArch64::LDUMINAB:
32212
    case AArch64::LDUMINAH:
32213
    case AArch64::LDUMINALB:
32214
    case AArch64::LDUMINALH:
32215
    case AArch64::LDUMINALW:
32216
    case AArch64::LDUMINALX:
32217
    case AArch64::LDUMINAW:
32218
    case AArch64::LDUMINAX:
32219
    case AArch64::LDUMINB:
32220
    case AArch64::LDUMINH:
32221
    case AArch64::LDUMINLB:
32222
    case AArch64::LDUMINLH:
32223
    case AArch64::LDUMINLW:
32224
    case AArch64::LDUMINLX:
32225
    case AArch64::LDUMINW:
32226
    case AArch64::LDUMINX:
32227
    case AArch64::RCWCLR:
32228
    case AArch64::RCWCLRA:
32229
    case AArch64::RCWCLRAL:
32230
    case AArch64::RCWCLRL:
32231
    case AArch64::RCWCLRS:
32232
    case AArch64::RCWCLRSA:
32233
    case AArch64::RCWCLRSAL:
32234
    case AArch64::RCWCLRSL:
32235
    case AArch64::RCWSET:
32236
    case AArch64::RCWSETA:
32237
    case AArch64::RCWSETAL:
32238
    case AArch64::RCWSETL:
32239
    case AArch64::RCWSETS:
32240
    case AArch64::RCWSETSA:
32241
    case AArch64::RCWSETSAL:
32242
    case AArch64::RCWSETSL:
32243
    case AArch64::RCWSWP:
32244
    case AArch64::RCWSWPA:
32245
    case AArch64::RCWSWPAL:
32246
    case AArch64::RCWSWPL:
32247
    case AArch64::RCWSWPS:
32248
    case AArch64::RCWSWPSA:
32249
    case AArch64::RCWSWPSAL:
32250
    case AArch64::RCWSWPSL:
32251
    case AArch64::SWPAB:
32252
    case AArch64::SWPAH:
32253
    case AArch64::SWPALB:
32254
    case AArch64::SWPALH:
32255
    case AArch64::SWPALW:
32256
    case AArch64::SWPALX:
32257
    case AArch64::SWPAW:
32258
    case AArch64::SWPAX:
32259
    case AArch64::SWPB:
32260
    case AArch64::SWPH:
32261
    case AArch64::SWPLB:
32262
    case AArch64::SWPLH:
32263
    case AArch64::SWPLW:
32264
    case AArch64::SWPLX:
32265
    case AArch64::SWPW:
32266
    case AArch64::SWPX: {
32267
      switch (OpNum) {
32268
      case 1:
32269
        // op: Rs
32270
        return 16;
32271
      case 2:
32272
        // op: Rn
32273
        return 5;
32274
      case 0:
32275
        // op: Rt
32276
        return 0;
32277
      }
32278
      break;
32279
    }
32280
    case AArch64::CASAB:
32281
    case AArch64::CASAH:
32282
    case AArch64::CASALB:
32283
    case AArch64::CASALH:
32284
    case AArch64::CASALW:
32285
    case AArch64::CASALX:
32286
    case AArch64::CASAW:
32287
    case AArch64::CASAX:
32288
    case AArch64::CASB:
32289
    case AArch64::CASH:
32290
    case AArch64::CASLB:
32291
    case AArch64::CASLH:
32292
    case AArch64::CASLW:
32293
    case AArch64::CASLX:
32294
    case AArch64::CASPALW:
32295
    case AArch64::CASPALX:
32296
    case AArch64::CASPAW:
32297
    case AArch64::CASPAX:
32298
    case AArch64::CASPLW:
32299
    case AArch64::CASPLX:
32300
    case AArch64::CASPW:
32301
    case AArch64::CASPX:
32302
    case AArch64::CASW:
32303
    case AArch64::CASX:
32304
    case AArch64::RCWCAS:
32305
    case AArch64::RCWCASA:
32306
    case AArch64::RCWCASAL:
32307
    case AArch64::RCWCASL:
32308
    case AArch64::RCWCASP:
32309
    case AArch64::RCWCASPA:
32310
    case AArch64::RCWCASPAL:
32311
    case AArch64::RCWCASPL:
32312
    case AArch64::RCWSCAS:
32313
    case AArch64::RCWSCASA:
32314
    case AArch64::RCWSCASAL:
32315
    case AArch64::RCWSCASL:
32316
    case AArch64::RCWSCASP:
32317
    case AArch64::RCWSCASPA:
32318
    case AArch64::RCWSCASPAL:
32319
    case AArch64::RCWSCASPL: {
32320
      switch (OpNum) {
32321
      case 1:
32322
        // op: Rs
32323
        return 16;
32324
      case 3:
32325
        // op: Rn
32326
        return 5;
32327
      case 2:
32328
        // op: Rt
32329
        return 0;
32330
      }
32331
      break;
32332
    }
32333
    case AArch64::MSR:
32334
    case AArch64::MSRR: {
32335
      switch (OpNum) {
32336
      case 1:
32337
        // op: Rt
32338
        return 0;
32339
      case 0:
32340
        // op: systemreg
32341
        return 5;
32342
      }
32343
      break;
32344
    }
32345
    case AArch64::ST64BV:
32346
    case AArch64::ST64BV0: {
32347
      switch (OpNum) {
32348
      case 1:
32349
        // op: Rt
32350
        return 0;
32351
      case 2:
32352
        // op: Rn
32353
        return 5;
32354
      case 0:
32355
        // op: Rs
32356
        return 16;
32357
      }
32358
      break;
32359
    }
32360
    case AArch64::LDRBBpost:
32361
    case AArch64::LDRBBpre:
32362
    case AArch64::LDRBpost:
32363
    case AArch64::LDRBpre:
32364
    case AArch64::LDRDpost:
32365
    case AArch64::LDRDpre:
32366
    case AArch64::LDRHHpost:
32367
    case AArch64::LDRHHpre:
32368
    case AArch64::LDRHpost:
32369
    case AArch64::LDRHpre:
32370
    case AArch64::LDRQpost:
32371
    case AArch64::LDRQpre:
32372
    case AArch64::LDRSBWpost:
32373
    case AArch64::LDRSBWpre:
32374
    case AArch64::LDRSBXpost:
32375
    case AArch64::LDRSBXpre:
32376
    case AArch64::LDRSHWpost:
32377
    case AArch64::LDRSHWpre:
32378
    case AArch64::LDRSHXpost:
32379
    case AArch64::LDRSHXpre:
32380
    case AArch64::LDRSWpost:
32381
    case AArch64::LDRSWpre:
32382
    case AArch64::LDRSpost:
32383
    case AArch64::LDRSpre:
32384
    case AArch64::LDRWpost:
32385
    case AArch64::LDRWpre:
32386
    case AArch64::LDRXpost:
32387
    case AArch64::LDRXpre:
32388
    case AArch64::STRBBpost:
32389
    case AArch64::STRBBpre:
32390
    case AArch64::STRBpost:
32391
    case AArch64::STRBpre:
32392
    case AArch64::STRDpost:
32393
    case AArch64::STRDpre:
32394
    case AArch64::STRHHpost:
32395
    case AArch64::STRHHpre:
32396
    case AArch64::STRHpost:
32397
    case AArch64::STRHpre:
32398
    case AArch64::STRQpost:
32399
    case AArch64::STRQpre:
32400
    case AArch64::STRSpost:
32401
    case AArch64::STRSpre:
32402
    case AArch64::STRWpost:
32403
    case AArch64::STRWpre:
32404
    case AArch64::STRXpost:
32405
    case AArch64::STRXpre: {
32406
      switch (OpNum) {
32407
      case 1:
32408
        // op: Rt
32409
        return 0;
32410
      case 2:
32411
        // op: Rn
32412
        return 5;
32413
      case 3:
32414
        // op: offset
32415
        return 12;
32416
      }
32417
      break;
32418
    }
32419
    case AArch64::LDAPRWpre:
32420
    case AArch64::LDAPRXpre:
32421
    case AArch64::STLRWpre:
32422
    case AArch64::STLRXpre: {
32423
      switch (OpNum) {
32424
      case 1:
32425
        // op: Rt
32426
        return 0;
32427
      case 2:
32428
        // op: Rn
32429
        return 5;
32430
      }
32431
      break;
32432
    }
32433
    case AArch64::LDPDpost:
32434
    case AArch64::LDPDpre:
32435
    case AArch64::LDPQpost:
32436
    case AArch64::LDPQpre:
32437
    case AArch64::LDPSWpost:
32438
    case AArch64::LDPSWpre:
32439
    case AArch64::LDPSpost:
32440
    case AArch64::LDPSpre:
32441
    case AArch64::LDPWpost:
32442
    case AArch64::LDPWpre:
32443
    case AArch64::LDPXpost:
32444
    case AArch64::LDPXpre:
32445
    case AArch64::STGPpost:
32446
    case AArch64::STGPpre:
32447
    case AArch64::STPDpost:
32448
    case AArch64::STPDpre:
32449
    case AArch64::STPQpost:
32450
    case AArch64::STPQpre:
32451
    case AArch64::STPSpost:
32452
    case AArch64::STPSpre:
32453
    case AArch64::STPWpost:
32454
    case AArch64::STPWpre:
32455
    case AArch64::STPXpost:
32456
    case AArch64::STPXpre: {
32457
      switch (OpNum) {
32458
      case 1:
32459
        // op: Rt
32460
        return 0;
32461
      case 2:
32462
        // op: Rt2
32463
        return 10;
32464
      case 3:
32465
        // op: Rn
32466
        return 5;
32467
      case 4:
32468
        // op: offset
32469
        return 15;
32470
      }
32471
      break;
32472
    }
32473
    case AArch64::LDIAPPWpre:
32474
    case AArch64::LDIAPPXpre:
32475
    case AArch64::STILPWpre:
32476
    case AArch64::STILPXpre: {
32477
      switch (OpNum) {
32478
      case 1:
32479
        // op: Rt
32480
        return 0;
32481
      case 3:
32482
        // op: Rn
32483
        return 5;
32484
      case 2:
32485
        // op: Rt2
32486
        return 16;
32487
      }
32488
      break;
32489
    }
32490
    case AArch64::LDR_ZA:
32491
    case AArch64::STR_ZA: {
32492
      switch (OpNum) {
32493
      case 1:
32494
        // op: Rv
32495
        return 13;
32496
      case 3:
32497
        // op: Rn
32498
        return 5;
32499
      case 2:
32500
        // op: imm4
32501
        return 0;
32502
      }
32503
      break;
32504
    }
32505
    case AArch64::SHA512H:
32506
    case AArch64::SHA512H2:
32507
    case AArch64::SHA512SU1:
32508
    case AArch64::SM3PARTW1:
32509
    case AArch64::SM3PARTW2:
32510
    case AArch64::TBXv8i8Four:
32511
    case AArch64::TBXv8i8One:
32512
    case AArch64::TBXv8i8Three:
32513
    case AArch64::TBXv8i8Two:
32514
    case AArch64::TBXv16i8Four:
32515
    case AArch64::TBXv16i8One:
32516
    case AArch64::TBXv16i8Three:
32517
    case AArch64::TBXv16i8Two: {
32518
      switch (OpNum) {
32519
      case 1:
32520
        // op: Vd
32521
        return 0;
32522
      case 2:
32523
        // op: Vn
32524
        return 5;
32525
      case 3:
32526
        // op: Vm
32527
        return 16;
32528
      }
32529
      break;
32530
    }
32531
    case AArch64::SM3TT1A:
32532
    case AArch64::SM3TT1B:
32533
    case AArch64::SM3TT2A:
32534
    case AArch64::SM3TT2B: {
32535
      switch (OpNum) {
32536
      case 1:
32537
        // op: Vd
32538
        return 0;
32539
      case 2:
32540
        // op: Vn
32541
        return 5;
32542
      case 4:
32543
        // op: imm
32544
        return 12;
32545
      case 3:
32546
        // op: Vm
32547
        return 16;
32548
      }
32549
      break;
32550
    }
32551
    case AArch64::SHA512SU0:
32552
    case AArch64::SM4E: {
32553
      switch (OpNum) {
32554
      case 1:
32555
        // op: Vd
32556
        return 0;
32557
      case 2:
32558
        // op: Vn
32559
        return 5;
32560
      }
32561
      break;
32562
    }
32563
    case AArch64::LD1Fourv1d_POST:
32564
    case AArch64::LD1Fourv2d_POST:
32565
    case AArch64::LD1Fourv2s_POST:
32566
    case AArch64::LD1Fourv4h_POST:
32567
    case AArch64::LD1Fourv4s_POST:
32568
    case AArch64::LD1Fourv8b_POST:
32569
    case AArch64::LD1Fourv8h_POST:
32570
    case AArch64::LD1Fourv16b_POST:
32571
    case AArch64::LD1Onev1d_POST:
32572
    case AArch64::LD1Onev2d_POST:
32573
    case AArch64::LD1Onev2s_POST:
32574
    case AArch64::LD1Onev4h_POST:
32575
    case AArch64::LD1Onev4s_POST:
32576
    case AArch64::LD1Onev8b_POST:
32577
    case AArch64::LD1Onev8h_POST:
32578
    case AArch64::LD1Onev16b_POST:
32579
    case AArch64::LD1Rv1d_POST:
32580
    case AArch64::LD1Rv2d_POST:
32581
    case AArch64::LD1Rv2s_POST:
32582
    case AArch64::LD1Rv4h_POST:
32583
    case AArch64::LD1Rv4s_POST:
32584
    case AArch64::LD1Rv8b_POST:
32585
    case AArch64::LD1Rv8h_POST:
32586
    case AArch64::LD1Rv16b_POST:
32587
    case AArch64::LD1Threev1d_POST:
32588
    case AArch64::LD1Threev2d_POST:
32589
    case AArch64::LD1Threev2s_POST:
32590
    case AArch64::LD1Threev4h_POST:
32591
    case AArch64::LD1Threev4s_POST:
32592
    case AArch64::LD1Threev8b_POST:
32593
    case AArch64::LD1Threev8h_POST:
32594
    case AArch64::LD1Threev16b_POST:
32595
    case AArch64::LD1Twov1d_POST:
32596
    case AArch64::LD1Twov2d_POST:
32597
    case AArch64::LD1Twov2s_POST:
32598
    case AArch64::LD1Twov4h_POST:
32599
    case AArch64::LD1Twov4s_POST:
32600
    case AArch64::LD1Twov8b_POST:
32601
    case AArch64::LD1Twov8h_POST:
32602
    case AArch64::LD1Twov16b_POST:
32603
    case AArch64::LD2Rv1d_POST:
32604
    case AArch64::LD2Rv2d_POST:
32605
    case AArch64::LD2Rv2s_POST:
32606
    case AArch64::LD2Rv4h_POST:
32607
    case AArch64::LD2Rv4s_POST:
32608
    case AArch64::LD2Rv8b_POST:
32609
    case AArch64::LD2Rv8h_POST:
32610
    case AArch64::LD2Rv16b_POST:
32611
    case AArch64::LD2Twov2d_POST:
32612
    case AArch64::LD2Twov2s_POST:
32613
    case AArch64::LD2Twov4h_POST:
32614
    case AArch64::LD2Twov4s_POST:
32615
    case AArch64::LD2Twov8b_POST:
32616
    case AArch64::LD2Twov8h_POST:
32617
    case AArch64::LD2Twov16b_POST:
32618
    case AArch64::LD3Rv1d_POST:
32619
    case AArch64::LD3Rv2d_POST:
32620
    case AArch64::LD3Rv2s_POST:
32621
    case AArch64::LD3Rv4h_POST:
32622
    case AArch64::LD3Rv4s_POST:
32623
    case AArch64::LD3Rv8b_POST:
32624
    case AArch64::LD3Rv8h_POST:
32625
    case AArch64::LD3Rv16b_POST:
32626
    case AArch64::LD3Threev2d_POST:
32627
    case AArch64::LD3Threev2s_POST:
32628
    case AArch64::LD3Threev4h_POST:
32629
    case AArch64::LD3Threev4s_POST:
32630
    case AArch64::LD3Threev8b_POST:
32631
    case AArch64::LD3Threev8h_POST:
32632
    case AArch64::LD3Threev16b_POST:
32633
    case AArch64::LD4Fourv2d_POST:
32634
    case AArch64::LD4Fourv2s_POST:
32635
    case AArch64::LD4Fourv4h_POST:
32636
    case AArch64::LD4Fourv4s_POST:
32637
    case AArch64::LD4Fourv8b_POST:
32638
    case AArch64::LD4Fourv8h_POST:
32639
    case AArch64::LD4Fourv16b_POST:
32640
    case AArch64::LD4Rv1d_POST:
32641
    case AArch64::LD4Rv2d_POST:
32642
    case AArch64::LD4Rv2s_POST:
32643
    case AArch64::LD4Rv4h_POST:
32644
    case AArch64::LD4Rv4s_POST:
32645
    case AArch64::LD4Rv8b_POST:
32646
    case AArch64::LD4Rv8h_POST:
32647
    case AArch64::LD4Rv16b_POST:
32648
    case AArch64::ST1Fourv1d_POST:
32649
    case AArch64::ST1Fourv2d_POST:
32650
    case AArch64::ST1Fourv2s_POST:
32651
    case AArch64::ST1Fourv4h_POST:
32652
    case AArch64::ST1Fourv4s_POST:
32653
    case AArch64::ST1Fourv8b_POST:
32654
    case AArch64::ST1Fourv8h_POST:
32655
    case AArch64::ST1Fourv16b_POST:
32656
    case AArch64::ST1Onev1d_POST:
32657
    case AArch64::ST1Onev2d_POST:
32658
    case AArch64::ST1Onev2s_POST:
32659
    case AArch64::ST1Onev4h_POST:
32660
    case AArch64::ST1Onev4s_POST:
32661
    case AArch64::ST1Onev8b_POST:
32662
    case AArch64::ST1Onev8h_POST:
32663
    case AArch64::ST1Onev16b_POST:
32664
    case AArch64::ST1Threev1d_POST:
32665
    case AArch64::ST1Threev2d_POST:
32666
    case AArch64::ST1Threev2s_POST:
32667
    case AArch64::ST1Threev4h_POST:
32668
    case AArch64::ST1Threev4s_POST:
32669
    case AArch64::ST1Threev8b_POST:
32670
    case AArch64::ST1Threev8h_POST:
32671
    case AArch64::ST1Threev16b_POST:
32672
    case AArch64::ST1Twov1d_POST:
32673
    case AArch64::ST1Twov2d_POST:
32674
    case AArch64::ST1Twov2s_POST:
32675
    case AArch64::ST1Twov4h_POST:
32676
    case AArch64::ST1Twov4s_POST:
32677
    case AArch64::ST1Twov8b_POST:
32678
    case AArch64::ST1Twov8h_POST:
32679
    case AArch64::ST1Twov16b_POST:
32680
    case AArch64::ST2Twov2d_POST:
32681
    case AArch64::ST2Twov2s_POST:
32682
    case AArch64::ST2Twov4h_POST:
32683
    case AArch64::ST2Twov4s_POST:
32684
    case AArch64::ST2Twov8b_POST:
32685
    case AArch64::ST2Twov8h_POST:
32686
    case AArch64::ST2Twov16b_POST:
32687
    case AArch64::ST3Threev2d_POST:
32688
    case AArch64::ST3Threev2s_POST:
32689
    case AArch64::ST3Threev4h_POST:
32690
    case AArch64::ST3Threev4s_POST:
32691
    case AArch64::ST3Threev8b_POST:
32692
    case AArch64::ST3Threev8h_POST:
32693
    case AArch64::ST3Threev16b_POST:
32694
    case AArch64::ST4Fourv2d_POST:
32695
    case AArch64::ST4Fourv2s_POST:
32696
    case AArch64::ST4Fourv4h_POST:
32697
    case AArch64::ST4Fourv4s_POST:
32698
    case AArch64::ST4Fourv8b_POST:
32699
    case AArch64::ST4Fourv8h_POST:
32700
    case AArch64::ST4Fourv16b_POST: {
32701
      switch (OpNum) {
32702
      case 1:
32703
        // op: Vt
32704
        return 0;
32705
      case 2:
32706
        // op: Rn
32707
        return 5;
32708
      case 3:
32709
        // op: Xm
32710
        return 16;
32711
      }
32712
      break;
32713
    }
32714
    case AArch64::LDAP1: {
32715
      switch (OpNum) {
32716
      case 1:
32717
        // op: Vt
32718
        return 0;
32719
      case 3:
32720
        // op: Rn
32721
        return 5;
32722
      case 2:
32723
        // op: Q
32724
        return 30;
32725
      }
32726
      break;
32727
    }
32728
    case AArch64::ST1i8_POST:
32729
    case AArch64::ST2i8_POST:
32730
    case AArch64::ST3i8_POST:
32731
    case AArch64::ST4i8_POST: {
32732
      switch (OpNum) {
32733
      case 1:
32734
        // op: Vt
32735
        return 0;
32736
      case 3:
32737
        // op: Rn
32738
        return 5;
32739
      case 2:
32740
        // op: idx
32741
        return 10;
32742
      case 4:
32743
        // op: Xm
32744
        return 16;
32745
      }
32746
      break;
32747
    }
32748
    case AArch64::LD1i8:
32749
    case AArch64::LD2i8:
32750
    case AArch64::LD3i8:
32751
    case AArch64::LD4i8: {
32752
      switch (OpNum) {
32753
      case 1:
32754
        // op: Vt
32755
        return 0;
32756
      case 3:
32757
        // op: Rn
32758
        return 5;
32759
      case 2:
32760
        // op: idx
32761
        return 10;
32762
      }
32763
      break;
32764
    }
32765
    case AArch64::ST1i16_POST:
32766
    case AArch64::ST2i16_POST:
32767
    case AArch64::ST3i16_POST:
32768
    case AArch64::ST4i16_POST: {
32769
      switch (OpNum) {
32770
      case 1:
32771
        // op: Vt
32772
        return 0;
32773
      case 3:
32774
        // op: Rn
32775
        return 5;
32776
      case 2:
32777
        // op: idx
32778
        return 11;
32779
      case 4:
32780
        // op: Xm
32781
        return 16;
32782
      }
32783
      break;
32784
    }
32785
    case AArch64::LD1i16:
32786
    case AArch64::LD2i16:
32787
    case AArch64::LD3i16:
32788
    case AArch64::LD4i16: {
32789
      switch (OpNum) {
32790
      case 1:
32791
        // op: Vt
32792
        return 0;
32793
      case 3:
32794
        // op: Rn
32795
        return 5;
32796
      case 2:
32797
        // op: idx
32798
        return 11;
32799
      }
32800
      break;
32801
    }
32802
    case AArch64::ST1i32_POST:
32803
    case AArch64::ST2i32_POST:
32804
    case AArch64::ST3i32_POST:
32805
    case AArch64::ST4i32_POST: {
32806
      switch (OpNum) {
32807
      case 1:
32808
        // op: Vt
32809
        return 0;
32810
      case 3:
32811
        // op: Rn
32812
        return 5;
32813
      case 2:
32814
        // op: idx
32815
        return 12;
32816
      case 4:
32817
        // op: Xm
32818
        return 16;
32819
      }
32820
      break;
32821
    }
32822
    case AArch64::LD1i32:
32823
    case AArch64::LD2i32:
32824
    case AArch64::LD3i32:
32825
    case AArch64::LD4i32: {
32826
      switch (OpNum) {
32827
      case 1:
32828
        // op: Vt
32829
        return 0;
32830
      case 3:
32831
        // op: Rn
32832
        return 5;
32833
      case 2:
32834
        // op: idx
32835
        return 12;
32836
      }
32837
      break;
32838
    }
32839
    case AArch64::ST1i64_POST:
32840
    case AArch64::ST2i64_POST:
32841
    case AArch64::ST3i64_POST:
32842
    case AArch64::ST4i64_POST: {
32843
      switch (OpNum) {
32844
      case 1:
32845
        // op: Vt
32846
        return 0;
32847
      case 3:
32848
        // op: Rn
32849
        return 5;
32850
      case 2:
32851
        // op: idx
32852
        return 30;
32853
      case 4:
32854
        // op: Xm
32855
        return 16;
32856
      }
32857
      break;
32858
    }
32859
    case AArch64::LD1i64:
32860
    case AArch64::LD2i64:
32861
    case AArch64::LD3i64:
32862
    case AArch64::LD4i64: {
32863
      switch (OpNum) {
32864
      case 1:
32865
        // op: Vt
32866
        return 0;
32867
      case 3:
32868
        // op: Rn
32869
        return 5;
32870
      case 2:
32871
        // op: idx
32872
        return 30;
32873
      }
32874
      break;
32875
    }
32876
    case AArch64::BF1CVTL_2ZZ_BtoH_NAME:
32877
    case AArch64::BF1CVT_2ZZ_BtoH_NAME:
32878
    case AArch64::BF2CVTL_2ZZ_BtoH_NAME:
32879
    case AArch64::BF2CVT_2ZZ_BtoH_NAME:
32880
    case AArch64::F1CVTL_2ZZ_BtoH_NAME:
32881
    case AArch64::F1CVT_2ZZ_BtoH_NAME:
32882
    case AArch64::F2CVTL_2ZZ_BtoH_NAME:
32883
    case AArch64::F2CVT_2ZZ_BtoH_NAME:
32884
    case AArch64::FCVTL_2ZZ_H_S:
32885
    case AArch64::FCVT_2ZZ_H_S:
32886
    case AArch64::SUNPK_VG2_2ZZ_D:
32887
    case AArch64::SUNPK_VG2_2ZZ_H:
32888
    case AArch64::SUNPK_VG2_2ZZ_S:
32889
    case AArch64::UUNPK_VG2_2ZZ_D:
32890
    case AArch64::UUNPK_VG2_2ZZ_H:
32891
    case AArch64::UUNPK_VG2_2ZZ_S: {
32892
      switch (OpNum) {
32893
      case 1:
32894
        // op: Zn
32895
        return 5;
32896
      case 0:
32897
        // op: Zd
32898
        return 1;
32899
      }
32900
      break;
32901
    }
32902
    case AArch64::BFCVTN_Z2Z_StoH:
32903
    case AArch64::BFCVT_Z2Z_HtoB:
32904
    case AArch64::BFCVT_Z2Z_StoH:
32905
    case AArch64::FCVTN_Z2Z_StoH:
32906
    case AArch64::FCVT_Z2Z_HtoB:
32907
    case AArch64::FCVT_Z2Z_StoH:
32908
    case AArch64::SQCVTU_Z2Z_StoH:
32909
    case AArch64::SQCVT_Z2Z_StoH:
32910
    case AArch64::UQCVT_Z2Z_StoH: {
32911
      switch (OpNum) {
32912
      case 1:
32913
        // op: Zn
32914
        return 6;
32915
      case 0:
32916
        // op: Zd
32917
        return 0;
32918
      }
32919
      break;
32920
    }
32921
    case AArch64::FCVTZS_2Z2Z_StoS:
32922
    case AArch64::FCVTZU_2Z2Z_StoS:
32923
    case AArch64::FRINTA_2Z2Z_S:
32924
    case AArch64::FRINTM_2Z2Z_S:
32925
    case AArch64::FRINTN_2Z2Z_S:
32926
    case AArch64::FRINTP_2Z2Z_S:
32927
    case AArch64::SCVTF_2Z2Z_StoS:
32928
    case AArch64::UCVTF_2Z2Z_StoS: {
32929
      switch (OpNum) {
32930
      case 1:
32931
        // op: Zn
32932
        return 6;
32933
      case 0:
32934
        // op: Zd
32935
        return 1;
32936
      }
32937
      break;
32938
    }
32939
    case AArch64::SUNPK_VG4_4Z2Z_D:
32940
    case AArch64::SUNPK_VG4_4Z2Z_H:
32941
    case AArch64::SUNPK_VG4_4Z2Z_S:
32942
    case AArch64::UUNPK_VG4_4Z2Z_D:
32943
    case AArch64::UUNPK_VG4_4Z2Z_H:
32944
    case AArch64::UUNPK_VG4_4Z2Z_S: {
32945
      switch (OpNum) {
32946
      case 1:
32947
        // op: Zn
32948
        return 6;
32949
      case 0:
32950
        // op: Zd
32951
        return 2;
32952
      }
32953
      break;
32954
    }
32955
    case AArch64::SQRSHRN_VG4_Z4ZI_B:
32956
    case AArch64::SQRSHRN_VG4_Z4ZI_H:
32957
    case AArch64::SQRSHRUN_VG4_Z4ZI_B:
32958
    case AArch64::SQRSHRUN_VG4_Z4ZI_H:
32959
    case AArch64::SQRSHRU_VG4_Z4ZI_B:
32960
    case AArch64::SQRSHRU_VG4_Z4ZI_H:
32961
    case AArch64::SQRSHR_VG4_Z4ZI_B:
32962
    case AArch64::SQRSHR_VG4_Z4ZI_H:
32963
    case AArch64::UQRSHRN_VG4_Z4ZI_B:
32964
    case AArch64::UQRSHRN_VG4_Z4ZI_H:
32965
    case AArch64::UQRSHR_VG4_Z4ZI_B:
32966
    case AArch64::UQRSHR_VG4_Z4ZI_H: {
32967
      switch (OpNum) {
32968
      case 1:
32969
        // op: Zn
32970
        return 7;
32971
      case 0:
32972
        // op: Zd
32973
        return 0;
32974
      case 2:
32975
        // op: imm
32976
        return 16;
32977
      }
32978
      break;
32979
    }
32980
    case AArch64::FCVTN_Z4Z_StoB_NAME:
32981
    case AArch64::FCVT_Z4Z_StoB_NAME:
32982
    case AArch64::SQCVTN_Z4Z_DtoH:
32983
    case AArch64::SQCVTN_Z4Z_StoB:
32984
    case AArch64::SQCVTUN_Z4Z_DtoH:
32985
    case AArch64::SQCVTUN_Z4Z_StoB:
32986
    case AArch64::SQCVTU_Z4Z_DtoH:
32987
    case AArch64::SQCVTU_Z4Z_StoB:
32988
    case AArch64::SQCVT_Z4Z_DtoH:
32989
    case AArch64::SQCVT_Z4Z_StoB:
32990
    case AArch64::UQCVTN_Z4Z_DtoH:
32991
    case AArch64::UQCVTN_Z4Z_StoB:
32992
    case AArch64::UQCVT_Z4Z_DtoH:
32993
    case AArch64::UQCVT_Z4Z_StoB: {
32994
      switch (OpNum) {
32995
      case 1:
32996
        // op: Zn
32997
        return 7;
32998
      case 0:
32999
        // op: Zd
33000
        return 0;
33001
      }
33002
      break;
33003
    }
33004
    case AArch64::FCVTZS_4Z4Z_StoS:
33005
    case AArch64::FCVTZU_4Z4Z_StoS:
33006
    case AArch64::FRINTA_4Z4Z_S:
33007
    case AArch64::FRINTM_4Z4Z_S:
33008
    case AArch64::FRINTN_4Z4Z_S:
33009
    case AArch64::FRINTP_4Z4Z_S:
33010
    case AArch64::SCVTF_4Z4Z_StoS:
33011
    case AArch64::UCVTF_4Z4Z_StoS:
33012
    case AArch64::UZP_VG4_4Z4Z_B:
33013
    case AArch64::UZP_VG4_4Z4Z_D:
33014
    case AArch64::UZP_VG4_4Z4Z_H:
33015
    case AArch64::UZP_VG4_4Z4Z_Q:
33016
    case AArch64::UZP_VG4_4Z4Z_S:
33017
    case AArch64::ZIP_VG4_4Z4Z_B:
33018
    case AArch64::ZIP_VG4_4Z4Z_D:
33019
    case AArch64::ZIP_VG4_4Z4Z_H:
33020
    case AArch64::ZIP_VG4_4Z4Z_Q:
33021
    case AArch64::ZIP_VG4_4Z4Z_S: {
33022
      switch (OpNum) {
33023
      case 1:
33024
        // op: Zn
33025
        return 7;
33026
      case 0:
33027
        // op: Zd
33028
        return 2;
33029
      }
33030
      break;
33031
    }
33032
    case AArch64::MOVT_TIX: {
33033
      switch (OpNum) {
33034
      case 1:
33035
        // op: imm3
33036
        return 12;
33037
      case 2:
33038
        // op: Rt
33039
        return 0;
33040
      }
33041
      break;
33042
    }
33043
    case AArch64::ABS_ZPmZ_B:
33044
    case AArch64::ABS_ZPmZ_D:
33045
    case AArch64::ABS_ZPmZ_H:
33046
    case AArch64::ABS_ZPmZ_S:
33047
    case AArch64::CLS_ZPmZ_B:
33048
    case AArch64::CLS_ZPmZ_D:
33049
    case AArch64::CLS_ZPmZ_H:
33050
    case AArch64::CLS_ZPmZ_S:
33051
    case AArch64::CLZ_ZPmZ_B:
33052
    case AArch64::CLZ_ZPmZ_D:
33053
    case AArch64::CLZ_ZPmZ_H:
33054
    case AArch64::CLZ_ZPmZ_S:
33055
    case AArch64::CNOT_ZPmZ_B:
33056
    case AArch64::CNOT_ZPmZ_D:
33057
    case AArch64::CNOT_ZPmZ_H:
33058
    case AArch64::CNOT_ZPmZ_S:
33059
    case AArch64::CNT_ZPmZ_B:
33060
    case AArch64::CNT_ZPmZ_D:
33061
    case AArch64::CNT_ZPmZ_H:
33062
    case AArch64::CNT_ZPmZ_S:
33063
    case AArch64::FABS_ZPmZ_D:
33064
    case AArch64::FABS_ZPmZ_H:
33065
    case AArch64::FABS_ZPmZ_S:
33066
    case AArch64::FCVTX_ZPmZ_DtoS:
33067
    case AArch64::FCVTZS_ZPmZ_DtoD:
33068
    case AArch64::FCVTZS_ZPmZ_DtoS:
33069
    case AArch64::FCVTZS_ZPmZ_HtoD:
33070
    case AArch64::FCVTZS_ZPmZ_HtoH:
33071
    case AArch64::FCVTZS_ZPmZ_HtoS:
33072
    case AArch64::FCVTZS_ZPmZ_StoD:
33073
    case AArch64::FCVTZS_ZPmZ_StoS:
33074
    case AArch64::FCVTZU_ZPmZ_DtoD:
33075
    case AArch64::FCVTZU_ZPmZ_DtoS:
33076
    case AArch64::FCVTZU_ZPmZ_HtoD:
33077
    case AArch64::FCVTZU_ZPmZ_HtoH:
33078
    case AArch64::FCVTZU_ZPmZ_HtoS:
33079
    case AArch64::FCVTZU_ZPmZ_StoD:
33080
    case AArch64::FCVTZU_ZPmZ_StoS:
33081
    case AArch64::FCVT_ZPmZ_DtoH:
33082
    case AArch64::FCVT_ZPmZ_DtoS:
33083
    case AArch64::FCVT_ZPmZ_HtoD:
33084
    case AArch64::FCVT_ZPmZ_HtoS:
33085
    case AArch64::FCVT_ZPmZ_StoD:
33086
    case AArch64::FCVT_ZPmZ_StoH:
33087
    case AArch64::FLOGB_ZPmZ_D:
33088
    case AArch64::FLOGB_ZPmZ_H:
33089
    case AArch64::FLOGB_ZPmZ_S:
33090
    case AArch64::FNEG_ZPmZ_D:
33091
    case AArch64::FNEG_ZPmZ_H:
33092
    case AArch64::FNEG_ZPmZ_S:
33093
    case AArch64::FRECPX_ZPmZ_D:
33094
    case AArch64::FRECPX_ZPmZ_H:
33095
    case AArch64::FRECPX_ZPmZ_S:
33096
    case AArch64::FRINTA_ZPmZ_D:
33097
    case AArch64::FRINTA_ZPmZ_H:
33098
    case AArch64::FRINTA_ZPmZ_S:
33099
    case AArch64::FRINTI_ZPmZ_D:
33100
    case AArch64::FRINTI_ZPmZ_H:
33101
    case AArch64::FRINTI_ZPmZ_S:
33102
    case AArch64::FRINTM_ZPmZ_D:
33103
    case AArch64::FRINTM_ZPmZ_H:
33104
    case AArch64::FRINTM_ZPmZ_S:
33105
    case AArch64::FRINTN_ZPmZ_D:
33106
    case AArch64::FRINTN_ZPmZ_H:
33107
    case AArch64::FRINTN_ZPmZ_S:
33108
    case AArch64::FRINTP_ZPmZ_D:
33109
    case AArch64::FRINTP_ZPmZ_H:
33110
    case AArch64::FRINTP_ZPmZ_S:
33111
    case AArch64::FRINTX_ZPmZ_D:
33112
    case AArch64::FRINTX_ZPmZ_H:
33113
    case AArch64::FRINTX_ZPmZ_S:
33114
    case AArch64::FRINTZ_ZPmZ_D:
33115
    case AArch64::FRINTZ_ZPmZ_H:
33116
    case AArch64::FRINTZ_ZPmZ_S:
33117
    case AArch64::FSQRT_ZPmZ_D:
33118
    case AArch64::FSQRT_ZPmZ_H:
33119
    case AArch64::FSQRT_ZPmZ_S:
33120
    case AArch64::MOVPRFX_ZPmZ_B:
33121
    case AArch64::MOVPRFX_ZPmZ_D:
33122
    case AArch64::MOVPRFX_ZPmZ_H:
33123
    case AArch64::MOVPRFX_ZPmZ_S:
33124
    case AArch64::NEG_ZPmZ_B:
33125
    case AArch64::NEG_ZPmZ_D:
33126
    case AArch64::NEG_ZPmZ_H:
33127
    case AArch64::NEG_ZPmZ_S:
33128
    case AArch64::NOT_ZPmZ_B:
33129
    case AArch64::NOT_ZPmZ_D:
33130
    case AArch64::NOT_ZPmZ_H:
33131
    case AArch64::NOT_ZPmZ_S:
33132
    case AArch64::SCVTF_ZPmZ_DtoD:
33133
    case AArch64::SCVTF_ZPmZ_DtoH:
33134
    case AArch64::SCVTF_ZPmZ_DtoS:
33135
    case AArch64::SCVTF_ZPmZ_HtoH:
33136
    case AArch64::SCVTF_ZPmZ_StoD:
33137
    case AArch64::SCVTF_ZPmZ_StoH:
33138
    case AArch64::SCVTF_ZPmZ_StoS:
33139
    case AArch64::SQABS_ZPmZ_B:
33140
    case AArch64::SQABS_ZPmZ_D:
33141
    case AArch64::SQABS_ZPmZ_H:
33142
    case AArch64::SQABS_ZPmZ_S:
33143
    case AArch64::SQNEG_ZPmZ_B:
33144
    case AArch64::SQNEG_ZPmZ_D:
33145
    case AArch64::SQNEG_ZPmZ_H:
33146
    case AArch64::SQNEG_ZPmZ_S:
33147
    case AArch64::SXTB_ZPmZ_D:
33148
    case AArch64::SXTB_ZPmZ_H:
33149
    case AArch64::SXTB_ZPmZ_S:
33150
    case AArch64::SXTH_ZPmZ_D:
33151
    case AArch64::SXTH_ZPmZ_S:
33152
    case AArch64::SXTW_ZPmZ_D:
33153
    case AArch64::UCVTF_ZPmZ_DtoD:
33154
    case AArch64::UCVTF_ZPmZ_DtoH:
33155
    case AArch64::UCVTF_ZPmZ_DtoS:
33156
    case AArch64::UCVTF_ZPmZ_HtoH:
33157
    case AArch64::UCVTF_ZPmZ_StoD:
33158
    case AArch64::UCVTF_ZPmZ_StoH:
33159
    case AArch64::UCVTF_ZPmZ_StoS:
33160
    case AArch64::URECPE_ZPmZ_S:
33161
    case AArch64::URSQRTE_ZPmZ_S:
33162
    case AArch64::UXTB_ZPmZ_D:
33163
    case AArch64::UXTB_ZPmZ_H:
33164
    case AArch64::UXTB_ZPmZ_S:
33165
    case AArch64::UXTH_ZPmZ_D:
33166
    case AArch64::UXTH_ZPmZ_S:
33167
    case AArch64::UXTW_ZPmZ_D: {
33168
      switch (OpNum) {
33169
      case 2:
33170
        // op: Pg
33171
        return 10;
33172
      case 0:
33173
        // op: Zd
33174
        return 0;
33175
      case 3:
33176
        // op: Zn
33177
        return 5;
33178
      }
33179
      break;
33180
    }
33181
    case AArch64::CPY_ZPmR_B:
33182
    case AArch64::CPY_ZPmR_D:
33183
    case AArch64::CPY_ZPmR_H:
33184
    case AArch64::CPY_ZPmR_S: {
33185
      switch (OpNum) {
33186
      case 2:
33187
        // op: Pg
33188
        return 10;
33189
      case 3:
33190
        // op: Rn
33191
        return 5;
33192
      case 0:
33193
        // op: Zd
33194
        return 0;
33195
      }
33196
      break;
33197
    }
33198
    case AArch64::CPY_ZPmV_B:
33199
    case AArch64::CPY_ZPmV_D:
33200
    case AArch64::CPY_ZPmV_H:
33201
    case AArch64::CPY_ZPmV_S: {
33202
      switch (OpNum) {
33203
      case 2:
33204
        // op: Pg
33205
        return 10;
33206
      case 3:
33207
        // op: Vn
33208
        return 5;
33209
      case 0:
33210
        // op: Zd
33211
        return 0;
33212
      }
33213
      break;
33214
    }
33215
    case AArch64::FCPY_ZPmI_D:
33216
    case AArch64::FCPY_ZPmI_H:
33217
    case AArch64::FCPY_ZPmI_S: {
33218
      switch (OpNum) {
33219
      case 2:
33220
        // op: Pg
33221
        return 16;
33222
      case 0:
33223
        // op: Zd
33224
        return 0;
33225
      case 3:
33226
        // op: imm8
33227
        return 5;
33228
      }
33229
      break;
33230
    }
33231
    case AArch64::DECP_ZP_D:
33232
    case AArch64::DECP_ZP_H:
33233
    case AArch64::DECP_ZP_S:
33234
    case AArch64::INCP_ZP_D:
33235
    case AArch64::INCP_ZP_H:
33236
    case AArch64::INCP_ZP_S:
33237
    case AArch64::SQDECP_ZP_D:
33238
    case AArch64::SQDECP_ZP_H:
33239
    case AArch64::SQDECP_ZP_S:
33240
    case AArch64::SQINCP_ZP_D:
33241
    case AArch64::SQINCP_ZP_H:
33242
    case AArch64::SQINCP_ZP_S:
33243
    case AArch64::UQDECP_ZP_D:
33244
    case AArch64::UQDECP_ZP_H:
33245
    case AArch64::UQDECP_ZP_S:
33246
    case AArch64::UQINCP_ZP_D:
33247
    case AArch64::UQINCP_ZP_H:
33248
    case AArch64::UQINCP_ZP_S: {
33249
      switch (OpNum) {
33250
      case 2:
33251
        // op: Pm
33252
        return 5;
33253
      case 0:
33254
        // op: Zdn
33255
        return 0;
33256
      }
33257
      break;
33258
    }
33259
    case AArch64::MOPSSETGE:
33260
    case AArch64::MOPSSETGEN:
33261
    case AArch64::MOPSSETGET:
33262
    case AArch64::MOPSSETGETN:
33263
    case AArch64::SETE:
33264
    case AArch64::SETEN:
33265
    case AArch64::SETET:
33266
    case AArch64::SETETN:
33267
    case AArch64::SETGM:
33268
    case AArch64::SETGMN:
33269
    case AArch64::SETGMT:
33270
    case AArch64::SETGMTN:
33271
    case AArch64::SETGP:
33272
    case AArch64::SETGPN:
33273
    case AArch64::SETGPT:
33274
    case AArch64::SETGPTN:
33275
    case AArch64::SETM:
33276
    case AArch64::SETMN:
33277
    case AArch64::SETMT:
33278
    case AArch64::SETMTN:
33279
    case AArch64::SETP:
33280
    case AArch64::SETPN:
33281
    case AArch64::SETPT:
33282
    case AArch64::SETPTN: {
33283
      switch (OpNum) {
33284
      case 2:
33285
        // op: Rd
33286
        return 0;
33287
      case 3:
33288
        // op: Rn
33289
        return 5;
33290
      case 4:
33291
        // op: Rm
33292
        return 16;
33293
      }
33294
      break;
33295
    }
33296
    case AArch64::INDEX_IR_B:
33297
    case AArch64::INDEX_IR_D:
33298
    case AArch64::INDEX_IR_H:
33299
    case AArch64::INDEX_IR_S: {
33300
      switch (OpNum) {
33301
      case 2:
33302
        // op: Rm
33303
        return 16;
33304
      case 0:
33305
        // op: Zd
33306
        return 0;
33307
      case 1:
33308
        // op: imm5
33309
        return 5;
33310
      }
33311
      break;
33312
    }
33313
    case AArch64::INSR_ZR_B:
33314
    case AArch64::INSR_ZR_D:
33315
    case AArch64::INSR_ZR_H:
33316
    case AArch64::INSR_ZR_S: {
33317
      switch (OpNum) {
33318
      case 2:
33319
        // op: Rm
33320
        return 5;
33321
      case 0:
33322
        // op: Zdn
33323
        return 0;
33324
      }
33325
      break;
33326
    }
33327
    case AArch64::PRFB_PRI:
33328
    case AArch64::PRFD_PRI:
33329
    case AArch64::PRFH_PRI:
33330
    case AArch64::PRFW_PRI: {
33331
      switch (OpNum) {
33332
      case 2:
33333
        // op: Rn
33334
        return 5;
33335
      case 1:
33336
        // op: Pg
33337
        return 10;
33338
      case 3:
33339
        // op: imm6
33340
        return 16;
33341
      case 0:
33342
        // op: prfop
33343
        return 0;
33344
      }
33345
      break;
33346
    }
33347
    case AArch64::LDG:
33348
    case AArch64::ST2GPostIndex:
33349
    case AArch64::ST2GPreIndex:
33350
    case AArch64::STGPostIndex:
33351
    case AArch64::STGPreIndex:
33352
    case AArch64::STZ2GPostIndex:
33353
    case AArch64::STZ2GPreIndex:
33354
    case AArch64::STZGPostIndex:
33355
    case AArch64::STZGPreIndex: {
33356
      switch (OpNum) {
33357
      case 2:
33358
        // op: Rn
33359
        return 5;
33360
      case 1:
33361
        // op: Rt
33362
        return 0;
33363
      case 3:
33364
        // op: offset
33365
        return 12;
33366
      }
33367
      break;
33368
    }
33369
    case AArch64::MOVA_VG2_MXI2Z: {
33370
      switch (OpNum) {
33371
      case 2:
33372
        // op: Rs
33373
        return 13;
33374
      case 3:
33375
        // op: imm
33376
        return 0;
33377
      case 4:
33378
        // op: Zn
33379
        return 6;
33380
      }
33381
      break;
33382
    }
33383
    case AArch64::MOVA_VG4_MXI4Z: {
33384
      switch (OpNum) {
33385
      case 2:
33386
        // op: Rs
33387
        return 13;
33388
      case 3:
33389
        // op: imm
33390
        return 0;
33391
      case 4:
33392
        // op: Zn
33393
        return 7;
33394
      }
33395
      break;
33396
    }
33397
    case AArch64::MOVA_VG2_2ZMXI: {
33398
      switch (OpNum) {
33399
      case 2:
33400
        // op: Rs
33401
        return 13;
33402
      case 3:
33403
        // op: imm
33404
        return 5;
33405
      case 0:
33406
        // op: Zd
33407
        return 1;
33408
      }
33409
      break;
33410
    }
33411
    case AArch64::MOVA_VG4_4ZMXI: {
33412
      switch (OpNum) {
33413
      case 2:
33414
        // op: Rs
33415
        return 13;
33416
      case 3:
33417
        // op: imm
33418
        return 5;
33419
      case 0:
33420
        // op: Zd
33421
        return 2;
33422
      }
33423
      break;
33424
    }
33425
    case AArch64::MOVA_MXI2Z_H_D:
33426
    case AArch64::MOVA_MXI2Z_V_D: {
33427
      switch (OpNum) {
33428
      case 2:
33429
        // op: Rs
33430
        return 13;
33431
      case 4:
33432
        // op: Zn
33433
        return 6;
33434
      case 0:
33435
        // op: ZAd
33436
        return 0;
33437
      }
33438
      break;
33439
    }
33440
    case AArch64::MOVA_MXI2Z_H_S:
33441
    case AArch64::MOVA_MXI2Z_V_S: {
33442
      switch (OpNum) {
33443
      case 2:
33444
        // op: Rs
33445
        return 13;
33446
      case 4:
33447
        // op: Zn
33448
        return 6;
33449
      case 0:
33450
        // op: ZAd
33451
        return 1;
33452
      case 3:
33453
        // op: imm
33454
        return 0;
33455
      }
33456
      break;
33457
    }
33458
    case AArch64::MOVA_MXI2Z_H_H:
33459
    case AArch64::MOVA_MXI2Z_V_H: {
33460
      switch (OpNum) {
33461
      case 2:
33462
        // op: Rs
33463
        return 13;
33464
      case 4:
33465
        // op: Zn
33466
        return 6;
33467
      case 0:
33468
        // op: ZAd
33469
        return 2;
33470
      case 3:
33471
        // op: imm
33472
        return 0;
33473
      }
33474
      break;
33475
    }
33476
    case AArch64::MOVA_MXI2Z_H_B:
33477
    case AArch64::MOVA_MXI2Z_V_B: {
33478
      switch (OpNum) {
33479
      case 2:
33480
        // op: Rs
33481
        return 13;
33482
      case 4:
33483
        // op: Zn
33484
        return 6;
33485
      case 3:
33486
        // op: imm
33487
        return 0;
33488
      }
33489
      break;
33490
    }
33491
    case AArch64::MOVA_MXI4Z_H_D:
33492
    case AArch64::MOVA_MXI4Z_H_S:
33493
    case AArch64::MOVA_MXI4Z_V_D:
33494
    case AArch64::MOVA_MXI4Z_V_S: {
33495
      switch (OpNum) {
33496
      case 2:
33497
        // op: Rs
33498
        return 13;
33499
      case 4:
33500
        // op: Zn
33501
        return 7;
33502
      case 0:
33503
        // op: ZAd
33504
        return 0;
33505
      }
33506
      break;
33507
    }
33508
    case AArch64::MOVA_MXI4Z_H_H:
33509
    case AArch64::MOVA_MXI4Z_V_H: {
33510
      switch (OpNum) {
33511
      case 2:
33512
        // op: Rs
33513
        return 13;
33514
      case 4:
33515
        // op: Zn
33516
        return 7;
33517
      case 0:
33518
        // op: ZAd
33519
        return 1;
33520
      case 3:
33521
        // op: imm
33522
        return 0;
33523
      }
33524
      break;
33525
    }
33526
    case AArch64::MOVA_MXI4Z_H_B:
33527
    case AArch64::MOVA_MXI4Z_V_B: {
33528
      switch (OpNum) {
33529
      case 2:
33530
        // op: Rs
33531
        return 13;
33532
      case 4:
33533
        // op: Zn
33534
        return 7;
33535
      case 3:
33536
        // op: imm
33537
        return 0;
33538
      }
33539
      break;
33540
    }
33541
    case AArch64::LDCLRP:
33542
    case AArch64::LDCLRPA:
33543
    case AArch64::LDCLRPAL:
33544
    case AArch64::LDCLRPL:
33545
    case AArch64::LDSETP:
33546
    case AArch64::LDSETPA:
33547
    case AArch64::LDSETPAL:
33548
    case AArch64::LDSETPL:
33549
    case AArch64::SWPP:
33550
    case AArch64::SWPPA:
33551
    case AArch64::SWPPAL:
33552
    case AArch64::SWPPL: {
33553
      switch (OpNum) {
33554
      case 2:
33555
        // op: Rt
33556
        return 0;
33557
      case 3:
33558
        // op: Rt2
33559
        return 16;
33560
      case 4:
33561
        // op: Rn
33562
        return 5;
33563
      }
33564
      break;
33565
    }
33566
    case AArch64::ZERO_MXI_2Z:
33567
    case AArch64::ZERO_MXI_4Z:
33568
    case AArch64::ZERO_MXI_VG2_2Z:
33569
    case AArch64::ZERO_MXI_VG2_4Z:
33570
    case AArch64::ZERO_MXI_VG2_Z:
33571
    case AArch64::ZERO_MXI_VG4_2Z:
33572
    case AArch64::ZERO_MXI_VG4_4Z:
33573
    case AArch64::ZERO_MXI_VG4_Z: {
33574
      switch (OpNum) {
33575
      case 2:
33576
        // op: Rv
33577
        return 13;
33578
      case 3:
33579
        // op: imm
33580
        return 0;
33581
      }
33582
      break;
33583
    }
33584
    case AArch64::ADD_VG2_M2Z_D:
33585
    case AArch64::ADD_VG2_M2Z_S:
33586
    case AArch64::BFADD_VG2_M2Z_H:
33587
    case AArch64::BFSUB_VG2_M2Z_H:
33588
    case AArch64::FADD_VG2_M2Z_D:
33589
    case AArch64::FADD_VG2_M2Z_H:
33590
    case AArch64::FADD_VG2_M2Z_S:
33591
    case AArch64::FSUB_VG2_M2Z_D:
33592
    case AArch64::FSUB_VG2_M2Z_H:
33593
    case AArch64::FSUB_VG2_M2Z_S:
33594
    case AArch64::SUB_VG2_M2Z_D:
33595
    case AArch64::SUB_VG2_M2Z_S: {
33596
      switch (OpNum) {
33597
      case 2:
33598
        // op: Rv
33599
        return 13;
33600
      case 3:
33601
        // op: imm3
33602
        return 0;
33603
      case 4:
33604
        // op: Zm
33605
        return 6;
33606
      }
33607
      break;
33608
    }
33609
    case AArch64::ADD_VG4_M4Z_D:
33610
    case AArch64::ADD_VG4_M4Z_S:
33611
    case AArch64::BFADD_VG4_M4Z_H:
33612
    case AArch64::BFSUB_VG4_M4Z_H:
33613
    case AArch64::FADD_VG4_M4Z_D:
33614
    case AArch64::FADD_VG4_M4Z_H:
33615
    case AArch64::FADD_VG4_M4Z_S:
33616
    case AArch64::FSUB_VG4_M4Z_D:
33617
    case AArch64::FSUB_VG4_M4Z_H:
33618
    case AArch64::FSUB_VG4_M4Z_S:
33619
    case AArch64::SUB_VG4_M4Z_D:
33620
    case AArch64::SUB_VG4_M4Z_S: {
33621
      switch (OpNum) {
33622
      case 2:
33623
        // op: Rv
33624
        return 13;
33625
      case 3:
33626
        // op: imm3
33627
        return 0;
33628
      case 4:
33629
        // op: Zm
33630
        return 7;
33631
      }
33632
      break;
33633
    }
33634
    case AArch64::INSERT_MXIPZ_H_Q:
33635
    case AArch64::INSERT_MXIPZ_V_Q: {
33636
      switch (OpNum) {
33637
      case 2:
33638
        // op: Rv
33639
        return 13;
33640
      case 4:
33641
        // op: Pg
33642
        return 10;
33643
      case 5:
33644
        // op: Zn
33645
        return 5;
33646
      case 0:
33647
        // op: ZAd
33648
        return 0;
33649
      }
33650
      break;
33651
    }
33652
    case AArch64::INSERT_MXIPZ_H_D:
33653
    case AArch64::INSERT_MXIPZ_V_D: {
33654
      switch (OpNum) {
33655
      case 2:
33656
        // op: Rv
33657
        return 13;
33658
      case 4:
33659
        // op: Pg
33660
        return 10;
33661
      case 5:
33662
        // op: Zn
33663
        return 5;
33664
      case 0:
33665
        // op: ZAd
33666
        return 1;
33667
      case 3:
33668
        // op: imm
33669
        return 0;
33670
      }
33671
      break;
33672
    }
33673
    case AArch64::INSERT_MXIPZ_H_S:
33674
    case AArch64::INSERT_MXIPZ_V_S: {
33675
      switch (OpNum) {
33676
      case 2:
33677
        // op: Rv
33678
        return 13;
33679
      case 4:
33680
        // op: Pg
33681
        return 10;
33682
      case 5:
33683
        // op: Zn
33684
        return 5;
33685
      case 0:
33686
        // op: ZAd
33687
        return 2;
33688
      case 3:
33689
        // op: imm
33690
        return 0;
33691
      }
33692
      break;
33693
    }
33694
    case AArch64::INSERT_MXIPZ_H_H:
33695
    case AArch64::INSERT_MXIPZ_V_H: {
33696
      switch (OpNum) {
33697
      case 2:
33698
        // op: Rv
33699
        return 13;
33700
      case 4:
33701
        // op: Pg
33702
        return 10;
33703
      case 5:
33704
        // op: Zn
33705
        return 5;
33706
      case 0:
33707
        // op: ZAd
33708
        return 3;
33709
      case 3:
33710
        // op: imm
33711
        return 0;
33712
      }
33713
      break;
33714
    }
33715
    case AArch64::INSERT_MXIPZ_H_B:
33716
    case AArch64::INSERT_MXIPZ_V_B: {
33717
      switch (OpNum) {
33718
      case 2:
33719
        // op: Rv
33720
        return 13;
33721
      case 4:
33722
        // op: Pg
33723
        return 10;
33724
      case 5:
33725
        // op: Zn
33726
        return 5;
33727
      case 3:
33728
        // op: imm
33729
        return 0;
33730
      }
33731
      break;
33732
    }
33733
    case AArch64::BFMLAL_MZZ_HtoS:
33734
    case AArch64::BFMLAL_VG2_M2ZZ_HtoS:
33735
    case AArch64::BFMLAL_VG4_M4ZZ_HtoS:
33736
    case AArch64::BFMLSL_MZZ_HtoS:
33737
    case AArch64::BFMLSL_VG2_M2ZZ_HtoS:
33738
    case AArch64::BFMLSL_VG4_M4ZZ_HtoS:
33739
    case AArch64::FMLAL_MZZ_HtoS:
33740
    case AArch64::FMLAL_VG2_M2ZZ_BtoH:
33741
    case AArch64::FMLAL_VG2_M2ZZ_HtoS:
33742
    case AArch64::FMLAL_VG2_MZZ_BtoH:
33743
    case AArch64::FMLAL_VG4_M4ZZ_BtoH:
33744
    case AArch64::FMLAL_VG4_M4ZZ_HtoS:
33745
    case AArch64::FMLSL_MZZ_HtoS:
33746
    case AArch64::FMLSL_VG2_M2ZZ_HtoS:
33747
    case AArch64::FMLSL_VG4_M4ZZ_HtoS:
33748
    case AArch64::SMLAL_MZZ_HtoS:
33749
    case AArch64::SMLAL_VG2_M2ZZ_HtoS:
33750
    case AArch64::SMLAL_VG4_M4ZZ_HtoS:
33751
    case AArch64::SMLSL_MZZ_HtoS:
33752
    case AArch64::SMLSL_VG2_M2ZZ_HtoS:
33753
    case AArch64::SMLSL_VG4_M4ZZ_HtoS:
33754
    case AArch64::UMLAL_MZZ_HtoS:
33755
    case AArch64::UMLAL_VG2_M2ZZ_HtoS:
33756
    case AArch64::UMLAL_VG4_M4ZZ_HtoS:
33757
    case AArch64::UMLSL_MZZ_HtoS:
33758
    case AArch64::UMLSL_VG2_M2ZZ_HtoS:
33759
    case AArch64::UMLSL_VG4_M4ZZ_HtoS: {
33760
      switch (OpNum) {
33761
      case 2:
33762
        // op: Rv
33763
        return 13;
33764
      case 5:
33765
        // op: Zm
33766
        return 16;
33767
      case 4:
33768
        // op: Zn
33769
        return 5;
33770
      case 3:
33771
        // op: imm
33772
        return 0;
33773
      }
33774
      break;
33775
    }
33776
    case AArch64::BFMLAL_VG2_M2Z2Z_HtoS:
33777
    case AArch64::BFMLSL_VG2_M2Z2Z_HtoS:
33778
    case AArch64::FMLAL_VG2_M2Z2Z_BtoH:
33779
    case AArch64::FMLAL_VG2_M2Z2Z_HtoS:
33780
    case AArch64::FMLSL_VG2_M2Z2Z_HtoS:
33781
    case AArch64::SMLAL_VG2_M2Z2Z_HtoS:
33782
    case AArch64::SMLSL_VG2_M2Z2Z_HtoS:
33783
    case AArch64::UMLAL_VG2_M2Z2Z_HtoS:
33784
    case AArch64::UMLSL_VG2_M2Z2Z_HtoS: {
33785
      switch (OpNum) {
33786
      case 2:
33787
        // op: Rv
33788
        return 13;
33789
      case 5:
33790
        // op: Zm
33791
        return 17;
33792
      case 4:
33793
        // op: Zn
33794
        return 6;
33795
      case 3:
33796
        // op: imm
33797
        return 0;
33798
      }
33799
      break;
33800
    }
33801
    case AArch64::BFMLAL_VG4_M4Z4Z_HtoS:
33802
    case AArch64::BFMLSL_VG4_M4Z4Z_HtoS:
33803
    case AArch64::FMLAL_VG4_M4Z4Z_BtoH:
33804
    case AArch64::FMLAL_VG4_M4Z4Z_HtoS:
33805
    case AArch64::FMLSL_VG4_M4Z4Z_HtoS:
33806
    case AArch64::SMLAL_VG4_M4Z4Z_HtoS:
33807
    case AArch64::SMLSL_VG4_M4Z4Z_HtoS:
33808
    case AArch64::UMLAL_VG4_M4Z4Z_HtoS:
33809
    case AArch64::UMLSL_VG4_M4Z4Z_HtoS: {
33810
      switch (OpNum) {
33811
      case 2:
33812
        // op: Rv
33813
        return 13;
33814
      case 5:
33815
        // op: Zm
33816
        return 18;
33817
      case 4:
33818
        // op: Zn
33819
        return 7;
33820
      case 3:
33821
        // op: imm
33822
        return 0;
33823
      }
33824
      break;
33825
    }
33826
    case AArch64::INSR_ZV_B:
33827
    case AArch64::INSR_ZV_D:
33828
    case AArch64::INSR_ZV_H:
33829
    case AArch64::INSR_ZV_S: {
33830
      switch (OpNum) {
33831
      case 2:
33832
        // op: Vm
33833
        return 5;
33834
      case 0:
33835
        // op: Zdn
33836
        return 0;
33837
      }
33838
      break;
33839
    }
33840
    case AArch64::LD1i8_POST:
33841
    case AArch64::LD2i8_POST:
33842
    case AArch64::LD3i8_POST:
33843
    case AArch64::LD4i8_POST: {
33844
      switch (OpNum) {
33845
      case 2:
33846
        // op: Vt
33847
        return 0;
33848
      case 4:
33849
        // op: Rn
33850
        return 5;
33851
      case 3:
33852
        // op: idx
33853
        return 10;
33854
      case 5:
33855
        // op: Xm
33856
        return 16;
33857
      }
33858
      break;
33859
    }
33860
    case AArch64::LD1i16_POST:
33861
    case AArch64::LD2i16_POST:
33862
    case AArch64::LD3i16_POST:
33863
    case AArch64::LD4i16_POST: {
33864
      switch (OpNum) {
33865
      case 2:
33866
        // op: Vt
33867
        return 0;
33868
      case 4:
33869
        // op: Rn
33870
        return 5;
33871
      case 3:
33872
        // op: idx
33873
        return 11;
33874
      case 5:
33875
        // op: Xm
33876
        return 16;
33877
      }
33878
      break;
33879
    }
33880
    case AArch64::LD1i32_POST:
33881
    case AArch64::LD2i32_POST:
33882
    case AArch64::LD3i32_POST:
33883
    case AArch64::LD4i32_POST: {
33884
      switch (OpNum) {
33885
      case 2:
33886
        // op: Vt
33887
        return 0;
33888
      case 4:
33889
        // op: Rn
33890
        return 5;
33891
      case 3:
33892
        // op: idx
33893
        return 12;
33894
      case 5:
33895
        // op: Xm
33896
        return 16;
33897
      }
33898
      break;
33899
    }
33900
    case AArch64::LD1i64_POST:
33901
    case AArch64::LD2i64_POST:
33902
    case AArch64::LD3i64_POST:
33903
    case AArch64::LD4i64_POST: {
33904
      switch (OpNum) {
33905
      case 2:
33906
        // op: Vt
33907
        return 0;
33908
      case 4:
33909
        // op: Rn
33910
        return 5;
33911
      case 3:
33912
        // op: idx
33913
        return 30;
33914
      case 5:
33915
        // op: Xm
33916
        return 16;
33917
      }
33918
      break;
33919
    }
33920
    case AArch64::ADD_VG2_2ZZ_B:
33921
    case AArch64::ADD_VG2_2ZZ_D:
33922
    case AArch64::ADD_VG2_2ZZ_H:
33923
    case AArch64::ADD_VG2_2ZZ_S:
33924
    case AArch64::BFMAXNM_VG2_2ZZ_H:
33925
    case AArch64::BFMAX_VG2_2ZZ_H:
33926
    case AArch64::BFMINNM_VG2_2ZZ_H:
33927
    case AArch64::BFMIN_VG2_2ZZ_H:
33928
    case AArch64::FMAXNM_VG2_2ZZ_D:
33929
    case AArch64::FMAXNM_VG2_2ZZ_H:
33930
    case AArch64::FMAXNM_VG2_2ZZ_S:
33931
    case AArch64::FMAX_VG2_2ZZ_D:
33932
    case AArch64::FMAX_VG2_2ZZ_H:
33933
    case AArch64::FMAX_VG2_2ZZ_S:
33934
    case AArch64::FMINNM_VG2_2ZZ_D:
33935
    case AArch64::FMINNM_VG2_2ZZ_H:
33936
    case AArch64::FMINNM_VG2_2ZZ_S:
33937
    case AArch64::FMIN_VG2_2ZZ_D:
33938
    case AArch64::FMIN_VG2_2ZZ_H:
33939
    case AArch64::FMIN_VG2_2ZZ_S:
33940
    case AArch64::FSCALE_2ZZ_D:
33941
    case AArch64::FSCALE_2ZZ_H:
33942
    case AArch64::FSCALE_2ZZ_S:
33943
    case AArch64::SMAX_VG2_2ZZ_B:
33944
    case AArch64::SMAX_VG2_2ZZ_D:
33945
    case AArch64::SMAX_VG2_2ZZ_H:
33946
    case AArch64::SMAX_VG2_2ZZ_S:
33947
    case AArch64::SMIN_VG2_2ZZ_B:
33948
    case AArch64::SMIN_VG2_2ZZ_D:
33949
    case AArch64::SMIN_VG2_2ZZ_H:
33950
    case AArch64::SMIN_VG2_2ZZ_S:
33951
    case AArch64::SQDMULH_VG2_2ZZ_B:
33952
    case AArch64::SQDMULH_VG2_2ZZ_D:
33953
    case AArch64::SQDMULH_VG2_2ZZ_H:
33954
    case AArch64::SQDMULH_VG2_2ZZ_S:
33955
    case AArch64::SRSHL_VG2_2ZZ_B:
33956
    case AArch64::SRSHL_VG2_2ZZ_D:
33957
    case AArch64::SRSHL_VG2_2ZZ_H:
33958
    case AArch64::SRSHL_VG2_2ZZ_S:
33959
    case AArch64::UMAX_VG2_2ZZ_B:
33960
    case AArch64::UMAX_VG2_2ZZ_D:
33961
    case AArch64::UMAX_VG2_2ZZ_H:
33962
    case AArch64::UMAX_VG2_2ZZ_S:
33963
    case AArch64::UMIN_VG2_2ZZ_B:
33964
    case AArch64::UMIN_VG2_2ZZ_D:
33965
    case AArch64::UMIN_VG2_2ZZ_H:
33966
    case AArch64::UMIN_VG2_2ZZ_S:
33967
    case AArch64::URSHL_VG2_2ZZ_B:
33968
    case AArch64::URSHL_VG2_2ZZ_D:
33969
    case AArch64::URSHL_VG2_2ZZ_H:
33970
    case AArch64::URSHL_VG2_2ZZ_S: {
33971
      switch (OpNum) {
33972
      case 2:
33973
        // op: Zm
33974
        return 16;
33975
      case 0:
33976
        // op: Zdn
33977
        return 1;
33978
      }
33979
      break;
33980
    }
33981
    case AArch64::ADD_VG4_4ZZ_B:
33982
    case AArch64::ADD_VG4_4ZZ_D:
33983
    case AArch64::ADD_VG4_4ZZ_H:
33984
    case AArch64::ADD_VG4_4ZZ_S:
33985
    case AArch64::BFMAXNM_VG4_4ZZ_H:
33986
    case AArch64::BFMAX_VG4_4ZZ_H:
33987
    case AArch64::BFMINNM_VG4_4ZZ_H:
33988
    case AArch64::BFMIN_VG4_4ZZ_H:
33989
    case AArch64::FMAXNM_VG4_4ZZ_D:
33990
    case AArch64::FMAXNM_VG4_4ZZ_H:
33991
    case AArch64::FMAXNM_VG4_4ZZ_S:
33992
    case AArch64::FMAX_VG4_4ZZ_D:
33993
    case AArch64::FMAX_VG4_4ZZ_H:
33994
    case AArch64::FMAX_VG4_4ZZ_S:
33995
    case AArch64::FMINNM_VG4_4ZZ_D:
33996
    case AArch64::FMINNM_VG4_4ZZ_H:
33997
    case AArch64::FMINNM_VG4_4ZZ_S:
33998
    case AArch64::FMIN_VG4_4ZZ_D:
33999
    case AArch64::FMIN_VG4_4ZZ_H:
34000
    case AArch64::FMIN_VG4_4ZZ_S:
34001
    case AArch64::FSCALE_4ZZ_D:
34002
    case AArch64::FSCALE_4ZZ_H:
34003
    case AArch64::FSCALE_4ZZ_S:
34004
    case AArch64::SMAX_VG4_4ZZ_B:
34005
    case AArch64::SMAX_VG4_4ZZ_D:
34006
    case AArch64::SMAX_VG4_4ZZ_H:
34007
    case AArch64::SMAX_VG4_4ZZ_S:
34008
    case AArch64::SMIN_VG4_4ZZ_B:
34009
    case AArch64::SMIN_VG4_4ZZ_D:
34010
    case AArch64::SMIN_VG4_4ZZ_H:
34011
    case AArch64::SMIN_VG4_4ZZ_S:
34012
    case AArch64::SQDMULH_VG4_4ZZ_B:
34013
    case AArch64::SQDMULH_VG4_4ZZ_D:
34014
    case AArch64::SQDMULH_VG4_4ZZ_H:
34015
    case AArch64::SQDMULH_VG4_4ZZ_S:
34016
    case AArch64::SRSHL_VG4_4ZZ_B:
34017
    case AArch64::SRSHL_VG4_4ZZ_D:
34018
    case AArch64::SRSHL_VG4_4ZZ_H:
34019
    case AArch64::SRSHL_VG4_4ZZ_S:
34020
    case AArch64::UMAX_VG4_4ZZ_B:
34021
    case AArch64::UMAX_VG4_4ZZ_D:
34022
    case AArch64::UMAX_VG4_4ZZ_H:
34023
    case AArch64::UMAX_VG4_4ZZ_S:
34024
    case AArch64::UMIN_VG4_4ZZ_B:
34025
    case AArch64::UMIN_VG4_4ZZ_D:
34026
    case AArch64::UMIN_VG4_4ZZ_H:
34027
    case AArch64::UMIN_VG4_4ZZ_S:
34028
    case AArch64::URSHL_VG4_4ZZ_B:
34029
    case AArch64::URSHL_VG4_4ZZ_D:
34030
    case AArch64::URSHL_VG4_4ZZ_H:
34031
    case AArch64::URSHL_VG4_4ZZ_S: {
34032
      switch (OpNum) {
34033
      case 2:
34034
        // op: Zm
34035
        return 16;
34036
      case 0:
34037
        // op: Zdn
34038
        return 2;
34039
      }
34040
      break;
34041
    }
34042
    case AArch64::BFMAXNM_VG2_2Z2Z_H:
34043
    case AArch64::BFMAX_VG2_2Z2Z_H:
34044
    case AArch64::BFMINNM_VG2_2Z2Z_H:
34045
    case AArch64::BFMIN_VG2_2Z2Z_H:
34046
    case AArch64::FAMAX_2Z2Z_D:
34047
    case AArch64::FAMAX_2Z2Z_H:
34048
    case AArch64::FAMAX_2Z2Z_S:
34049
    case AArch64::FAMIN_2Z2Z_D:
34050
    case AArch64::FAMIN_2Z2Z_H:
34051
    case AArch64::FAMIN_2Z2Z_S:
34052
    case AArch64::FMAXNM_VG2_2Z2Z_D:
34053
    case AArch64::FMAXNM_VG2_2Z2Z_H:
34054
    case AArch64::FMAXNM_VG2_2Z2Z_S:
34055
    case AArch64::FMAX_VG2_2Z2Z_D:
34056
    case AArch64::FMAX_VG2_2Z2Z_H:
34057
    case AArch64::FMAX_VG2_2Z2Z_S:
34058
    case AArch64::FMINNM_VG2_2Z2Z_D:
34059
    case AArch64::FMINNM_VG2_2Z2Z_H:
34060
    case AArch64::FMINNM_VG2_2Z2Z_S:
34061
    case AArch64::FMIN_VG2_2Z2Z_D:
34062
    case AArch64::FMIN_VG2_2Z2Z_H:
34063
    case AArch64::FMIN_VG2_2Z2Z_S:
34064
    case AArch64::FSCALE_2Z2Z_D:
34065
    case AArch64::FSCALE_2Z2Z_H:
34066
    case AArch64::FSCALE_2Z2Z_S:
34067
    case AArch64::SMAX_VG2_2Z2Z_B:
34068
    case AArch64::SMAX_VG2_2Z2Z_D:
34069
    case AArch64::SMAX_VG2_2Z2Z_H:
34070
    case AArch64::SMAX_VG2_2Z2Z_S:
34071
    case AArch64::SMIN_VG2_2Z2Z_B:
34072
    case AArch64::SMIN_VG2_2Z2Z_D:
34073
    case AArch64::SMIN_VG2_2Z2Z_H:
34074
    case AArch64::SMIN_VG2_2Z2Z_S:
34075
    case AArch64::SQDMULH_VG2_2Z2Z_B:
34076
    case AArch64::SQDMULH_VG2_2Z2Z_D:
34077
    case AArch64::SQDMULH_VG2_2Z2Z_H:
34078
    case AArch64::SQDMULH_VG2_2Z2Z_S:
34079
    case AArch64::SRSHL_VG2_2Z2Z_B:
34080
    case AArch64::SRSHL_VG2_2Z2Z_D:
34081
    case AArch64::SRSHL_VG2_2Z2Z_H:
34082
    case AArch64::SRSHL_VG2_2Z2Z_S:
34083
    case AArch64::UMAX_VG2_2Z2Z_B:
34084
    case AArch64::UMAX_VG2_2Z2Z_D:
34085
    case AArch64::UMAX_VG2_2Z2Z_H:
34086
    case AArch64::UMAX_VG2_2Z2Z_S:
34087
    case AArch64::UMIN_VG2_2Z2Z_B:
34088
    case AArch64::UMIN_VG2_2Z2Z_D:
34089
    case AArch64::UMIN_VG2_2Z2Z_H:
34090
    case AArch64::UMIN_VG2_2Z2Z_S:
34091
    case AArch64::URSHL_VG2_2Z2Z_B:
34092
    case AArch64::URSHL_VG2_2Z2Z_D:
34093
    case AArch64::URSHL_VG2_2Z2Z_H:
34094
    case AArch64::URSHL_VG2_2Z2Z_S: {
34095
      switch (OpNum) {
34096
      case 2:
34097
        // op: Zm
34098
        return 17;
34099
      case 0:
34100
        // op: Zdn
34101
        return 1;
34102
      }
34103
      break;
34104
    }
34105
    case AArch64::BFMAXNM_VG4_4Z2Z_H:
34106
    case AArch64::BFMAX_VG4_4Z2Z_H:
34107
    case AArch64::BFMINNM_VG4_4Z2Z_H:
34108
    case AArch64::BFMIN_VG4_4Z2Z_H:
34109
    case AArch64::FAMAX_4Z4Z_D:
34110
    case AArch64::FAMAX_4Z4Z_H:
34111
    case AArch64::FAMAX_4Z4Z_S:
34112
    case AArch64::FAMIN_4Z4Z_D:
34113
    case AArch64::FAMIN_4Z4Z_H:
34114
    case AArch64::FAMIN_4Z4Z_S:
34115
    case AArch64::FMAXNM_VG4_4Z4Z_D:
34116
    case AArch64::FMAXNM_VG4_4Z4Z_H:
34117
    case AArch64::FMAXNM_VG4_4Z4Z_S:
34118
    case AArch64::FMAX_VG4_4Z4Z_D:
34119
    case AArch64::FMAX_VG4_4Z4Z_H:
34120
    case AArch64::FMAX_VG4_4Z4Z_S:
34121
    case AArch64::FMINNM_VG4_4Z4Z_D:
34122
    case AArch64::FMINNM_VG4_4Z4Z_H:
34123
    case AArch64::FMINNM_VG4_4Z4Z_S:
34124
    case AArch64::FMIN_VG4_4Z4Z_D:
34125
    case AArch64::FMIN_VG4_4Z4Z_H:
34126
    case AArch64::FMIN_VG4_4Z4Z_S:
34127
    case AArch64::FSCALE_4Z4Z_D:
34128
    case AArch64::FSCALE_4Z4Z_H:
34129
    case AArch64::FSCALE_4Z4Z_S:
34130
    case AArch64::SMAX_VG4_4Z4Z_B:
34131
    case AArch64::SMAX_VG4_4Z4Z_D:
34132
    case AArch64::SMAX_VG4_4Z4Z_H:
34133
    case AArch64::SMAX_VG4_4Z4Z_S:
34134
    case AArch64::SMIN_VG4_4Z4Z_B:
34135
    case AArch64::SMIN_VG4_4Z4Z_D:
34136
    case AArch64::SMIN_VG4_4Z4Z_H:
34137
    case AArch64::SMIN_VG4_4Z4Z_S:
34138
    case AArch64::SQDMULH_VG4_4Z4Z_B:
34139
    case AArch64::SQDMULH_VG4_4Z4Z_D:
34140
    case AArch64::SQDMULH_VG4_4Z4Z_H:
34141
    case AArch64::SQDMULH_VG4_4Z4Z_S:
34142
    case AArch64::SRSHL_VG4_4Z4Z_B:
34143
    case AArch64::SRSHL_VG4_4Z4Z_D:
34144
    case AArch64::SRSHL_VG4_4Z4Z_H:
34145
    case AArch64::SRSHL_VG4_4Z4Z_S:
34146
    case AArch64::UMAX_VG4_4Z4Z_B:
34147
    case AArch64::UMAX_VG4_4Z4Z_D:
34148
    case AArch64::UMAX_VG4_4Z4Z_H:
34149
    case AArch64::UMAX_VG4_4Z4Z_S:
34150
    case AArch64::UMIN_VG4_4Z4Z_B:
34151
    case AArch64::UMIN_VG4_4Z4Z_D:
34152
    case AArch64::UMIN_VG4_4Z4Z_H:
34153
    case AArch64::UMIN_VG4_4Z4Z_S:
34154
    case AArch64::URSHL_VG4_4Z4Z_B:
34155
    case AArch64::URSHL_VG4_4Z4Z_D:
34156
    case AArch64::URSHL_VG4_4Z4Z_H:
34157
    case AArch64::URSHL_VG4_4Z4Z_S: {
34158
      switch (OpNum) {
34159
      case 2:
34160
        // op: Zm
34161
        return 18;
34162
      case 0:
34163
        // op: Zdn
34164
        return 2;
34165
      }
34166
      break;
34167
    }
34168
    case AArch64::FADDV_VPZ_D:
34169
    case AArch64::FADDV_VPZ_H:
34170
    case AArch64::FADDV_VPZ_S:
34171
    case AArch64::FMAXNMV_VPZ_D:
34172
    case AArch64::FMAXNMV_VPZ_H:
34173
    case AArch64::FMAXNMV_VPZ_S:
34174
    case AArch64::FMAXV_VPZ_D:
34175
    case AArch64::FMAXV_VPZ_H:
34176
    case AArch64::FMAXV_VPZ_S:
34177
    case AArch64::FMINNMV_VPZ_D:
34178
    case AArch64::FMINNMV_VPZ_H:
34179
    case AArch64::FMINNMV_VPZ_S:
34180
    case AArch64::FMINV_VPZ_D:
34181
    case AArch64::FMINV_VPZ_H:
34182
    case AArch64::FMINV_VPZ_S: {
34183
      switch (OpNum) {
34184
      case 2:
34185
        // op: Zn
34186
        return 5;
34187
      case 0:
34188
        // op: Vd
34189
        return 0;
34190
      case 1:
34191
        // op: Pg
34192
        return 10;
34193
      }
34194
      break;
34195
    }
34196
    case AArch64::LUTI2_ZTZI_B:
34197
    case AArch64::LUTI2_ZTZI_H:
34198
    case AArch64::LUTI2_ZTZI_S:
34199
    case AArch64::LUTI4_ZTZI_B:
34200
    case AArch64::LUTI4_ZTZI_H:
34201
    case AArch64::LUTI4_ZTZI_S: {
34202
      switch (OpNum) {
34203
      case 2:
34204
        // op: Zn
34205
        return 5;
34206
      case 0:
34207
        // op: Zd
34208
        return 0;
34209
      case 3:
34210
        // op: i
34211
        return 14;
34212
      }
34213
      break;
34214
    }
34215
    case AArch64::LUTI2_S_2ZTZI_B:
34216
    case AArch64::LUTI2_S_2ZTZI_H:
34217
    case AArch64::LUTI4_S_2ZTZI_B:
34218
    case AArch64::LUTI4_S_2ZTZI_H: {
34219
      switch (OpNum) {
34220
      case 2:
34221
        // op: Zn
34222
        return 5;
34223
      case 0:
34224
        // op: Zd
34225
        return 0;
34226
      case 3:
34227
        // op: i
34228
        return 15;
34229
      }
34230
      break;
34231
    }
34232
    case AArch64::LUTI2_S_4ZTZI_B:
34233
    case AArch64::LUTI2_S_4ZTZI_H:
34234
    case AArch64::LUTI4_S_4ZTZI_H: {
34235
      switch (OpNum) {
34236
      case 2:
34237
        // op: Zn
34238
        return 5;
34239
      case 0:
34240
        // op: Zd
34241
        return 0;
34242
      case 3:
34243
        // op: i
34244
        return 16;
34245
      }
34246
      break;
34247
    }
34248
    case AArch64::LUTI2_2ZTZI_B:
34249
    case AArch64::LUTI2_2ZTZI_H:
34250
    case AArch64::LUTI2_2ZTZI_S:
34251
    case AArch64::LUTI4_2ZTZI_B:
34252
    case AArch64::LUTI4_2ZTZI_H:
34253
    case AArch64::LUTI4_2ZTZI_S: {
34254
      switch (OpNum) {
34255
      case 2:
34256
        // op: Zn
34257
        return 5;
34258
      case 0:
34259
        // op: Zd
34260
        return 1;
34261
      case 3:
34262
        // op: i
34263
        return 15;
34264
      }
34265
      break;
34266
    }
34267
    case AArch64::LUTI2_4ZTZI_B:
34268
    case AArch64::LUTI2_4ZTZI_H:
34269
    case AArch64::LUTI2_4ZTZI_S:
34270
    case AArch64::LUTI4_4ZTZI_H:
34271
    case AArch64::LUTI4_4ZTZI_S: {
34272
      switch (OpNum) {
34273
      case 2:
34274
        // op: Zn
34275
        return 5;
34276
      case 0:
34277
        // op: Zd
34278
        return 2;
34279
      case 3:
34280
        // op: i
34281
        return 16;
34282
      }
34283
      break;
34284
    }
34285
    case AArch64::LUTI4_S_4ZZT2Z: {
34286
      switch (OpNum) {
34287
      case 2:
34288
        // op: Zn
34289
        return 6;
34290
      case 0:
34291
        // op: Zd
34292
        return 0;
34293
      }
34294
      break;
34295
    }
34296
    case AArch64::LUTI4_4ZZT2Z: {
34297
      switch (OpNum) {
34298
      case 2:
34299
        // op: Zn
34300
        return 6;
34301
      case 0:
34302
        // op: Zd
34303
        return 2;
34304
      }
34305
      break;
34306
    }
34307
    case AArch64::MOVT: {
34308
      switch (OpNum) {
34309
      case 2:
34310
        // op: Zt
34311
        return 0;
34312
      case 1:
34313
        // op: off2
34314
        return 12;
34315
      }
34316
      break;
34317
    }
34318
    case AArch64::MOVT_XTI: {
34319
      switch (OpNum) {
34320
      case 2:
34321
        // op: imm3
34322
        return 12;
34323
      case 0:
34324
        // op: Rt
34325
        return 0;
34326
      }
34327
      break;
34328
    }
34329
    case AArch64::SQRSHRU_VG2_Z2ZI_H:
34330
    case AArch64::SQRSHR_VG2_Z2ZI_H:
34331
    case AArch64::UQRSHR_VG2_Z2ZI_H: {
34332
      switch (OpNum) {
34333
      case 2:
34334
        // op: imm4
34335
        return 16;
34336
      case 1:
34337
        // op: Zn
34338
        return 6;
34339
      case 0:
34340
        // op: Zd
34341
        return 0;
34342
      }
34343
      break;
34344
    }
34345
    case AArch64::LDRAAindexed:
34346
    case AArch64::LDRABindexed: {
34347
      switch (OpNum) {
34348
      case 2:
34349
        // op: offset
34350
        return 12;
34351
      case 1:
34352
        // op: Rn
34353
        return 5;
34354
      case 0:
34355
        // op: Rt
34356
        return 0;
34357
      }
34358
      break;
34359
    }
34360
    case AArch64::ADDHA_MPPZ_D:
34361
    case AArch64::ADDHA_MPPZ_S:
34362
    case AArch64::ADDVA_MPPZ_D:
34363
    case AArch64::ADDVA_MPPZ_S: {
34364
      switch (OpNum) {
34365
      case 3:
34366
        // op: Pm
34367
        return 13;
34368
      case 2:
34369
        // op: Pn
34370
        return 10;
34371
      case 4:
34372
        // op: Zn
34373
        return 5;
34374
      case 0:
34375
        // op: ZAda
34376
        return 0;
34377
      }
34378
      break;
34379
    }
34380
    case AArch64::CPYE:
34381
    case AArch64::CPYEN:
34382
    case AArch64::CPYERN:
34383
    case AArch64::CPYERT:
34384
    case AArch64::CPYERTN:
34385
    case AArch64::CPYERTRN:
34386
    case AArch64::CPYERTWN:
34387
    case AArch64::CPYET:
34388
    case AArch64::CPYETN:
34389
    case AArch64::CPYETRN:
34390
    case AArch64::CPYETWN:
34391
    case AArch64::CPYEWN:
34392
    case AArch64::CPYEWT:
34393
    case AArch64::CPYEWTN:
34394
    case AArch64::CPYEWTRN:
34395
    case AArch64::CPYEWTWN:
34396
    case AArch64::CPYFE:
34397
    case AArch64::CPYFEN:
34398
    case AArch64::CPYFERN:
34399
    case AArch64::CPYFERT:
34400
    case AArch64::CPYFERTN:
34401
    case AArch64::CPYFERTRN:
34402
    case AArch64::CPYFERTWN:
34403
    case AArch64::CPYFET:
34404
    case AArch64::CPYFETN:
34405
    case AArch64::CPYFETRN:
34406
    case AArch64::CPYFETWN:
34407
    case AArch64::CPYFEWN:
34408
    case AArch64::CPYFEWT:
34409
    case AArch64::CPYFEWTN:
34410
    case AArch64::CPYFEWTRN:
34411
    case AArch64::CPYFEWTWN:
34412
    case AArch64::CPYFM:
34413
    case AArch64::CPYFMN:
34414
    case AArch64::CPYFMRN:
34415
    case AArch64::CPYFMRT:
34416
    case AArch64::CPYFMRTN:
34417
    case AArch64::CPYFMRTRN:
34418
    case AArch64::CPYFMRTWN:
34419
    case AArch64::CPYFMT:
34420
    case AArch64::CPYFMTN:
34421
    case AArch64::CPYFMTRN:
34422
    case AArch64::CPYFMTWN:
34423
    case AArch64::CPYFMWN:
34424
    case AArch64::CPYFMWT:
34425
    case AArch64::CPYFMWTN:
34426
    case AArch64::CPYFMWTRN:
34427
    case AArch64::CPYFMWTWN:
34428
    case AArch64::CPYFP:
34429
    case AArch64::CPYFPN:
34430
    case AArch64::CPYFPRN:
34431
    case AArch64::CPYFPRT:
34432
    case AArch64::CPYFPRTN:
34433
    case AArch64::CPYFPRTRN:
34434
    case AArch64::CPYFPRTWN:
34435
    case AArch64::CPYFPT:
34436
    case AArch64::CPYFPTN:
34437
    case AArch64::CPYFPTRN:
34438
    case AArch64::CPYFPTWN:
34439
    case AArch64::CPYFPWN:
34440
    case AArch64::CPYFPWT:
34441
    case AArch64::CPYFPWTN:
34442
    case AArch64::CPYFPWTRN:
34443
    case AArch64::CPYFPWTWN:
34444
    case AArch64::CPYM:
34445
    case AArch64::CPYMN:
34446
    case AArch64::CPYMRN:
34447
    case AArch64::CPYMRT:
34448
    case AArch64::CPYMRTN:
34449
    case AArch64::CPYMRTRN:
34450
    case AArch64::CPYMRTWN:
34451
    case AArch64::CPYMT:
34452
    case AArch64::CPYMTN:
34453
    case AArch64::CPYMTRN:
34454
    case AArch64::CPYMTWN:
34455
    case AArch64::CPYMWN:
34456
    case AArch64::CPYMWT:
34457
    case AArch64::CPYMWTN:
34458
    case AArch64::CPYMWTRN:
34459
    case AArch64::CPYMWTWN:
34460
    case AArch64::CPYP:
34461
    case AArch64::CPYPN:
34462
    case AArch64::CPYPRN:
34463
    case AArch64::CPYPRT:
34464
    case AArch64::CPYPRTN:
34465
    case AArch64::CPYPRTRN:
34466
    case AArch64::CPYPRTWN:
34467
    case AArch64::CPYPT:
34468
    case AArch64::CPYPTN:
34469
    case AArch64::CPYPTRN:
34470
    case AArch64::CPYPTWN:
34471
    case AArch64::CPYPWN:
34472
    case AArch64::CPYPWT:
34473
    case AArch64::CPYPWTN:
34474
    case AArch64::CPYPWTRN:
34475
    case AArch64::CPYPWTWN: {
34476
      switch (OpNum) {
34477
      case 3:
34478
        // op: Rd
34479
        return 0;
34480
      case 4:
34481
        // op: Rs
34482
        return 16;
34483
      case 5:
34484
        // op: Rn
34485
        return 5;
34486
      }
34487
      break;
34488
    }
34489
    case AArch64::LD1B_2Z_STRIDED:
34490
    case AArch64::LD1B_4Z_STRIDED:
34491
    case AArch64::LD1D_2Z_STRIDED:
34492
    case AArch64::LD1D_4Z_STRIDED:
34493
    case AArch64::LD1H_2Z_STRIDED:
34494
    case AArch64::LD1H_4Z_STRIDED:
34495
    case AArch64::LD1W_2Z_STRIDED:
34496
    case AArch64::LD1W_4Z_STRIDED:
34497
    case AArch64::LDNT1B_2Z_STRIDED:
34498
    case AArch64::LDNT1B_4Z_STRIDED:
34499
    case AArch64::LDNT1D_2Z_STRIDED:
34500
    case AArch64::LDNT1D_4Z_STRIDED:
34501
    case AArch64::LDNT1H_2Z_STRIDED:
34502
    case AArch64::LDNT1H_4Z_STRIDED:
34503
    case AArch64::LDNT1W_2Z_STRIDED:
34504
    case AArch64::LDNT1W_4Z_STRIDED:
34505
    case AArch64::ST1B_2Z_STRIDED:
34506
    case AArch64::ST1B_4Z_STRIDED:
34507
    case AArch64::ST1D_2Z_STRIDED:
34508
    case AArch64::ST1D_4Z_STRIDED:
34509
    case AArch64::ST1H_2Z_STRIDED:
34510
    case AArch64::ST1H_4Z_STRIDED:
34511
    case AArch64::ST1W_2Z_STRIDED:
34512
    case AArch64::ST1W_4Z_STRIDED:
34513
    case AArch64::STNT1B_2Z_STRIDED:
34514
    case AArch64::STNT1B_4Z_STRIDED:
34515
    case AArch64::STNT1D_2Z_STRIDED:
34516
    case AArch64::STNT1D_4Z_STRIDED:
34517
    case AArch64::STNT1H_2Z_STRIDED:
34518
    case AArch64::STNT1H_4Z_STRIDED:
34519
    case AArch64::STNT1W_2Z_STRIDED:
34520
    case AArch64::STNT1W_4Z_STRIDED: {
34521
      switch (OpNum) {
34522
      case 3:
34523
        // op: Rm
34524
        return 16;
34525
      case 1:
34526
        // op: PNg
34527
        return 10;
34528
      case 2:
34529
        // op: Rn
34530
        return 5;
34531
      case 0:
34532
        // op: Zt
34533
        return 0;
34534
      }
34535
      break;
34536
    }
34537
    case AArch64::PRFB_PRR:
34538
    case AArch64::PRFD_PRR:
34539
    case AArch64::PRFH_PRR:
34540
    case AArch64::PRFW_PRR: {
34541
      switch (OpNum) {
34542
      case 3:
34543
        // op: Rm
34544
        return 16;
34545
      case 2:
34546
        // op: Rn
34547
        return 5;
34548
      case 1:
34549
        // op: Pg
34550
        return 10;
34551
      case 0:
34552
        // op: prfop
34553
        return 0;
34554
      }
34555
      break;
34556
    }
34557
    case AArch64::MOVAZ_ZMI_H_Q:
34558
    case AArch64::MOVAZ_ZMI_V_Q: {
34559
      switch (OpNum) {
34560
      case 3:
34561
        // op: Rs
34562
        return 13;
34563
      case 0:
34564
        // op: Zd
34565
        return 0;
34566
      case 1:
34567
        // op: ZAn
34568
        return 5;
34569
      }
34570
      break;
34571
    }
34572
    case AArch64::MOVAZ_ZMI_H_D:
34573
    case AArch64::MOVAZ_ZMI_V_D: {
34574
      switch (OpNum) {
34575
      case 3:
34576
        // op: Rs
34577
        return 13;
34578
      case 0:
34579
        // op: Zd
34580
        return 0;
34581
      case 1:
34582
        // op: ZAn
34583
        return 6;
34584
      case 4:
34585
        // op: imm
34586
        return 5;
34587
      }
34588
      break;
34589
    }
34590
    case AArch64::MOVAZ_ZMI_H_S:
34591
    case AArch64::MOVAZ_ZMI_V_S: {
34592
      switch (OpNum) {
34593
      case 3:
34594
        // op: Rs
34595
        return 13;
34596
      case 0:
34597
        // op: Zd
34598
        return 0;
34599
      case 1:
34600
        // op: ZAn
34601
        return 7;
34602
      case 4:
34603
        // op: imm
34604
        return 5;
34605
      }
34606
      break;
34607
    }
34608
    case AArch64::MOVAZ_ZMI_H_H:
34609
    case AArch64::MOVAZ_ZMI_V_H: {
34610
      switch (OpNum) {
34611
      case 3:
34612
        // op: Rs
34613
        return 13;
34614
      case 0:
34615
        // op: Zd
34616
        return 0;
34617
      case 1:
34618
        // op: ZAn
34619
        return 8;
34620
      case 4:
34621
        // op: imm
34622
        return 5;
34623
      }
34624
      break;
34625
    }
34626
    case AArch64::MOVAZ_ZMI_H_B:
34627
    case AArch64::MOVAZ_ZMI_V_B: {
34628
      switch (OpNum) {
34629
      case 3:
34630
        // op: Rs
34631
        return 13;
34632
      case 0:
34633
        // op: Zd
34634
        return 0;
34635
      case 4:
34636
        // op: imm
34637
        return 5;
34638
      }
34639
      break;
34640
    }
34641
    case AArch64::MOVAZ_VG2_2ZM: {
34642
      switch (OpNum) {
34643
      case 3:
34644
        // op: Rs
34645
        return 13;
34646
      case 4:
34647
        // op: imm
34648
        return 5;
34649
      case 0:
34650
        // op: Zd
34651
        return 1;
34652
      }
34653
      break;
34654
    }
34655
    case AArch64::MOVAZ_VG4_4ZM: {
34656
      switch (OpNum) {
34657
      case 3:
34658
        // op: Rs
34659
        return 13;
34660
      case 4:
34661
        // op: imm
34662
        return 5;
34663
      case 0:
34664
        // op: Zd
34665
        return 2;
34666
      }
34667
      break;
34668
    }
34669
    case AArch64::RCWCLRP:
34670
    case AArch64::RCWCLRPA:
34671
    case AArch64::RCWCLRPAL:
34672
    case AArch64::RCWCLRPL:
34673
    case AArch64::RCWCLRSP:
34674
    case AArch64::RCWCLRSPA:
34675
    case AArch64::RCWCLRSPAL:
34676
    case AArch64::RCWCLRSPL:
34677
    case AArch64::RCWSETP:
34678
    case AArch64::RCWSETPA:
34679
    case AArch64::RCWSETPAL:
34680
    case AArch64::RCWSETPL:
34681
    case AArch64::RCWSETSP:
34682
    case AArch64::RCWSETSPA:
34683
    case AArch64::RCWSETSPAL:
34684
    case AArch64::RCWSETSPL:
34685
    case AArch64::RCWSWPP:
34686
    case AArch64::RCWSWPPA:
34687
    case AArch64::RCWSWPPAL:
34688
    case AArch64::RCWSWPPL:
34689
    case AArch64::RCWSWPSP:
34690
    case AArch64::RCWSWPSPA:
34691
    case AArch64::RCWSWPSPAL:
34692
    case AArch64::RCWSWPSPL: {
34693
      switch (OpNum) {
34694
      case 3:
34695
        // op: Rt2
34696
        return 16;
34697
      case 4:
34698
        // op: Rn
34699
        return 5;
34700
      case 2:
34701
        // op: Rt
34702
        return 0;
34703
      }
34704
      break;
34705
    }
34706
    case AArch64::PSEL_PPPRI_B: {
34707
      switch (OpNum) {
34708
      case 3:
34709
        // op: Rv
34710
        return 16;
34711
      case 1:
34712
        // op: Pn
34713
        return 10;
34714
      case 2:
34715
        // op: Pm
34716
        return 5;
34717
      case 0:
34718
        // op: Pd
34719
        return 0;
34720
      case 4:
34721
        // op: imm
34722
        return 19;
34723
      }
34724
      break;
34725
    }
34726
    case AArch64::PSEL_PPPRI_H: {
34727
      switch (OpNum) {
34728
      case 3:
34729
        // op: Rv
34730
        return 16;
34731
      case 1:
34732
        // op: Pn
34733
        return 10;
34734
      case 2:
34735
        // op: Pm
34736
        return 5;
34737
      case 0:
34738
        // op: Pd
34739
        return 0;
34740
      case 4:
34741
        // op: imm
34742
        return 20;
34743
      }
34744
      break;
34745
    }
34746
    case AArch64::PSEL_PPPRI_S: {
34747
      switch (OpNum) {
34748
      case 3:
34749
        // op: Rv
34750
        return 16;
34751
      case 1:
34752
        // op: Pn
34753
        return 10;
34754
      case 2:
34755
        // op: Pm
34756
        return 5;
34757
      case 0:
34758
        // op: Pd
34759
        return 0;
34760
      case 4:
34761
        // op: imm
34762
        return 22;
34763
      }
34764
      break;
34765
    }
34766
    case AArch64::PSEL_PPPRI_D: {
34767
      switch (OpNum) {
34768
      case 3:
34769
        // op: Rv
34770
        return 16;
34771
      case 1:
34772
        // op: Pn
34773
        return 10;
34774
      case 2:
34775
        // op: Pm
34776
        return 5;
34777
      case 0:
34778
        // op: Pd
34779
        return 0;
34780
      case 4:
34781
        // op: imm
34782
        return 23;
34783
      }
34784
      break;
34785
    }
34786
    case AArch64::BFMMLA_ZZZ: {
34787
      switch (OpNum) {
34788
      case 3:
34789
        // op: Zm
34790
        return 16;
34791
      case 0:
34792
        // op: Zda
34793
        return 0;
34794
      case 2:
34795
        // op: Zn
34796
        return 5;
34797
      }
34798
      break;
34799
    }
34800
    case AArch64::BFCLAMP_ZZZ:
34801
    case AArch64::FCLAMP_ZZZ_D:
34802
    case AArch64::FCLAMP_ZZZ_H:
34803
    case AArch64::FCLAMP_ZZZ_S:
34804
    case AArch64::SCLAMP_ZZZ_B:
34805
    case AArch64::SCLAMP_ZZZ_D:
34806
    case AArch64::SCLAMP_ZZZ_H:
34807
    case AArch64::SCLAMP_ZZZ_S:
34808
    case AArch64::UCLAMP_ZZZ_B:
34809
    case AArch64::UCLAMP_ZZZ_D:
34810
    case AArch64::UCLAMP_ZZZ_H:
34811
    case AArch64::UCLAMP_ZZZ_S: {
34812
      switch (OpNum) {
34813
      case 3:
34814
        // op: Zm
34815
        return 16;
34816
      case 2:
34817
        // op: Zn
34818
        return 5;
34819
      case 0:
34820
        // op: Zd
34821
        return 0;
34822
      }
34823
      break;
34824
    }
34825
    case AArch64::BFCLAMP_VG2_2ZZZ_H:
34826
    case AArch64::FCLAMP_VG2_2Z2Z_D:
34827
    case AArch64::FCLAMP_VG2_2Z2Z_H:
34828
    case AArch64::FCLAMP_VG2_2Z2Z_S:
34829
    case AArch64::SCLAMP_VG2_2Z2Z_B:
34830
    case AArch64::SCLAMP_VG2_2Z2Z_D:
34831
    case AArch64::SCLAMP_VG2_2Z2Z_H:
34832
    case AArch64::SCLAMP_VG2_2Z2Z_S:
34833
    case AArch64::UCLAMP_VG2_2Z2Z_B:
34834
    case AArch64::UCLAMP_VG2_2Z2Z_D:
34835
    case AArch64::UCLAMP_VG2_2Z2Z_H:
34836
    case AArch64::UCLAMP_VG2_2Z2Z_S: {
34837
      switch (OpNum) {
34838
      case 3:
34839
        // op: Zm
34840
        return 16;
34841
      case 2:
34842
        // op: Zn
34843
        return 5;
34844
      case 0:
34845
        // op: Zd
34846
        return 1;
34847
      }
34848
      break;
34849
    }
34850
    case AArch64::BFCLAMP_VG4_4ZZZ_H:
34851
    case AArch64::FCLAMP_VG4_4Z4Z_D:
34852
    case AArch64::FCLAMP_VG4_4Z4Z_H:
34853
    case AArch64::FCLAMP_VG4_4Z4Z_S:
34854
    case AArch64::SCLAMP_VG4_4Z4Z_B:
34855
    case AArch64::SCLAMP_VG4_4Z4Z_D:
34856
    case AArch64::SCLAMP_VG4_4Z4Z_H:
34857
    case AArch64::SCLAMP_VG4_4Z4Z_S:
34858
    case AArch64::UCLAMP_VG4_4Z4Z_B:
34859
    case AArch64::UCLAMP_VG4_4Z4Z_D:
34860
    case AArch64::UCLAMP_VG4_4Z4Z_H:
34861
    case AArch64::UCLAMP_VG4_4Z4Z_S: {
34862
      switch (OpNum) {
34863
      case 3:
34864
        // op: Zm
34865
        return 16;
34866
      case 2:
34867
        // op: Zn
34868
        return 5;
34869
      case 0:
34870
        // op: Zd
34871
        return 2;
34872
      }
34873
      break;
34874
    }
34875
    case AArch64::LD1B_2Z_STRIDED_IMM:
34876
    case AArch64::LD1B_4Z_STRIDED_IMM:
34877
    case AArch64::LD1D_2Z_STRIDED_IMM:
34878
    case AArch64::LD1D_4Z_STRIDED_IMM:
34879
    case AArch64::LD1H_2Z_STRIDED_IMM:
34880
    case AArch64::LD1H_4Z_STRIDED_IMM:
34881
    case AArch64::LD1W_2Z_STRIDED_IMM:
34882
    case AArch64::LD1W_4Z_STRIDED_IMM:
34883
    case AArch64::LDNT1B_2Z_STRIDED_IMM:
34884
    case AArch64::LDNT1B_4Z_STRIDED_IMM:
34885
    case AArch64::LDNT1D_2Z_STRIDED_IMM:
34886
    case AArch64::LDNT1D_4Z_STRIDED_IMM:
34887
    case AArch64::LDNT1H_2Z_STRIDED_IMM:
34888
    case AArch64::LDNT1H_4Z_STRIDED_IMM:
34889
    case AArch64::LDNT1W_2Z_STRIDED_IMM:
34890
    case AArch64::LDNT1W_4Z_STRIDED_IMM:
34891
    case AArch64::ST1B_2Z_STRIDED_IMM:
34892
    case AArch64::ST1B_4Z_STRIDED_IMM:
34893
    case AArch64::ST1D_2Z_STRIDED_IMM:
34894
    case AArch64::ST1D_4Z_STRIDED_IMM:
34895
    case AArch64::ST1H_2Z_STRIDED_IMM:
34896
    case AArch64::ST1H_4Z_STRIDED_IMM:
34897
    case AArch64::ST1W_2Z_STRIDED_IMM:
34898
    case AArch64::ST1W_4Z_STRIDED_IMM:
34899
    case AArch64::STNT1B_2Z_STRIDED_IMM:
34900
    case AArch64::STNT1B_4Z_STRIDED_IMM:
34901
    case AArch64::STNT1D_2Z_STRIDED_IMM:
34902
    case AArch64::STNT1D_4Z_STRIDED_IMM:
34903
    case AArch64::STNT1H_2Z_STRIDED_IMM:
34904
    case AArch64::STNT1H_4Z_STRIDED_IMM:
34905
    case AArch64::STNT1W_2Z_STRIDED_IMM:
34906
    case AArch64::STNT1W_4Z_STRIDED_IMM: {
34907
      switch (OpNum) {
34908
      case 3:
34909
        // op: imm4
34910
        return 16;
34911
      case 1:
34912
        // op: PNg
34913
        return 10;
34914
      case 2:
34915
        // op: Rn
34916
        return 5;
34917
      case 0:
34918
        // op: Zt
34919
        return 0;
34920
      }
34921
      break;
34922
    }
34923
    case AArch64::LDRAAwriteback:
34924
    case AArch64::LDRABwriteback: {
34925
      switch (OpNum) {
34926
      case 3:
34927
        // op: offset
34928
        return 12;
34929
      case 2:
34930
        // op: Rn
34931
        return 5;
34932
      case 1:
34933
        // op: Rt
34934
        return 0;
34935
      }
34936
      break;
34937
    }
34938
    case AArch64::SYSPxt:
34939
    case AArch64::SYSxt: {
34940
      switch (OpNum) {
34941
      case 4:
34942
        // op: Rt
34943
        return 0;
34944
      case 0:
34945
        // op: op1
34946
        return 16;
34947
      case 1:
34948
        // op: Cn
34949
        return 12;
34950
      case 2:
34951
        // op: Cm
34952
        return 8;
34953
      case 3:
34954
        // op: op2
34955
        return 5;
34956
      }
34957
      break;
34958
    }
34959
    case AArch64::EXTRACT_ZPMXI_H_Q:
34960
    case AArch64::EXTRACT_ZPMXI_V_Q: {
34961
      switch (OpNum) {
34962
      case 4:
34963
        // op: Rv
34964
        return 13;
34965
      case 2:
34966
        // op: Pg
34967
        return 10;
34968
      case 0:
34969
        // op: Zd
34970
        return 0;
34971
      case 3:
34972
        // op: ZAn
34973
        return 5;
34974
      }
34975
      break;
34976
    }
34977
    case AArch64::EXTRACT_ZPMXI_H_D:
34978
    case AArch64::EXTRACT_ZPMXI_V_D: {
34979
      switch (OpNum) {
34980
      case 4:
34981
        // op: Rv
34982
        return 13;
34983
      case 2:
34984
        // op: Pg
34985
        return 10;
34986
      case 0:
34987
        // op: Zd
34988
        return 0;
34989
      case 3:
34990
        // op: ZAn
34991
        return 6;
34992
      case 5:
34993
        // op: imm
34994
        return 5;
34995
      }
34996
      break;
34997
    }
34998
    case AArch64::EXTRACT_ZPMXI_H_S:
34999
    case AArch64::EXTRACT_ZPMXI_V_S: {
35000
      switch (OpNum) {
35001
      case 4:
35002
        // op: Rv
35003
        return 13;
35004
      case 2:
35005
        // op: Pg
35006
        return 10;
35007
      case 0:
35008
        // op: Zd
35009
        return 0;
35010
      case 3:
35011
        // op: ZAn
35012
        return 7;
35013
      case 5:
35014
        // op: imm
35015
        return 5;
35016
      }
35017
      break;
35018
    }
35019
    case AArch64::EXTRACT_ZPMXI_H_H:
35020
    case AArch64::EXTRACT_ZPMXI_V_H: {
35021
      switch (OpNum) {
35022
      case 4:
35023
        // op: Rv
35024
        return 13;
35025
      case 2:
35026
        // op: Pg
35027
        return 10;
35028
      case 0:
35029
        // op: Zd
35030
        return 0;
35031
      case 3:
35032
        // op: ZAn
35033
        return 8;
35034
      case 5:
35035
        // op: imm
35036
        return 5;
35037
      }
35038
      break;
35039
    }
35040
    case AArch64::EXTRACT_ZPMXI_H_B:
35041
    case AArch64::EXTRACT_ZPMXI_V_B: {
35042
      switch (OpNum) {
35043
      case 4:
35044
        // op: Rv
35045
        return 13;
35046
      case 2:
35047
        // op: Pg
35048
        return 10;
35049
      case 0:
35050
        // op: Zd
35051
        return 0;
35052
      case 5:
35053
        // op: imm
35054
        return 5;
35055
      }
35056
      break;
35057
    }
35058
    case AArch64::LD1_MXIPXX_H_Q:
35059
    case AArch64::LD1_MXIPXX_V_Q:
35060
    case AArch64::ST1_MXIPXX_H_Q:
35061
    case AArch64::ST1_MXIPXX_V_Q: {
35062
      switch (OpNum) {
35063
      case 5:
35064
        // op: Rm
35065
        return 16;
35066
      case 1:
35067
        // op: Rv
35068
        return 13;
35069
      case 3:
35070
        // op: Pg
35071
        return 10;
35072
      case 4:
35073
        // op: Rn
35074
        return 5;
35075
      case 0:
35076
        // op: ZAt
35077
        return 0;
35078
      }
35079
      break;
35080
    }
35081
    case AArch64::LD1_MXIPXX_H_D:
35082
    case AArch64::LD1_MXIPXX_V_D:
35083
    case AArch64::ST1_MXIPXX_H_D:
35084
    case AArch64::ST1_MXIPXX_V_D: {
35085
      switch (OpNum) {
35086
      case 5:
35087
        // op: Rm
35088
        return 16;
35089
      case 1:
35090
        // op: Rv
35091
        return 13;
35092
      case 3:
35093
        // op: Pg
35094
        return 10;
35095
      case 4:
35096
        // op: Rn
35097
        return 5;
35098
      case 0:
35099
        // op: ZAt
35100
        return 1;
35101
      case 2:
35102
        // op: imm
35103
        return 0;
35104
      }
35105
      break;
35106
    }
35107
    case AArch64::LD1_MXIPXX_H_S:
35108
    case AArch64::LD1_MXIPXX_V_S:
35109
    case AArch64::ST1_MXIPXX_H_S:
35110
    case AArch64::ST1_MXIPXX_V_S: {
35111
      switch (OpNum) {
35112
      case 5:
35113
        // op: Rm
35114
        return 16;
35115
      case 1:
35116
        // op: Rv
35117
        return 13;
35118
      case 3:
35119
        // op: Pg
35120
        return 10;
35121
      case 4:
35122
        // op: Rn
35123
        return 5;
35124
      case 0:
35125
        // op: ZAt
35126
        return 2;
35127
      case 2:
35128
        // op: imm
35129
        return 0;
35130
      }
35131
      break;
35132
    }
35133
    case AArch64::LD1_MXIPXX_H_H:
35134
    case AArch64::LD1_MXIPXX_V_H:
35135
    case AArch64::ST1_MXIPXX_H_H:
35136
    case AArch64::ST1_MXIPXX_V_H: {
35137
      switch (OpNum) {
35138
      case 5:
35139
        // op: Rm
35140
        return 16;
35141
      case 1:
35142
        // op: Rv
35143
        return 13;
35144
      case 3:
35145
        // op: Pg
35146
        return 10;
35147
      case 4:
35148
        // op: Rn
35149
        return 5;
35150
      case 0:
35151
        // op: ZAt
35152
        return 3;
35153
      case 2:
35154
        // op: imm
35155
        return 0;
35156
      }
35157
      break;
35158
    }
35159
    case AArch64::LD1_MXIPXX_H_B:
35160
    case AArch64::LD1_MXIPXX_V_B:
35161
    case AArch64::ST1_MXIPXX_H_B:
35162
    case AArch64::ST1_MXIPXX_V_B: {
35163
      switch (OpNum) {
35164
      case 5:
35165
        // op: Rm
35166
        return 16;
35167
      case 1:
35168
        // op: Rv
35169
        return 13;
35170
      case 3:
35171
        // op: Pg
35172
        return 10;
35173
      case 4:
35174
        // op: Rn
35175
        return 5;
35176
      case 2:
35177
        // op: imm
35178
        return 0;
35179
      }
35180
      break;
35181
    }
35182
    case AArch64::FMLALL_MZZ_BtoS:
35183
    case AArch64::FMLALL_VG2_M2ZZ_BtoS:
35184
    case AArch64::FMLALL_VG4_M4ZZ_BtoS:
35185
    case AArch64::SMLALL_MZZ_BtoS:
35186
    case AArch64::SMLALL_MZZ_HtoD:
35187
    case AArch64::SMLALL_VG2_M2ZZ_BtoS:
35188
    case AArch64::SMLALL_VG2_M2ZZ_HtoD:
35189
    case AArch64::SMLALL_VG4_M4ZZ_BtoS:
35190
    case AArch64::SMLALL_VG4_M4ZZ_HtoD:
35191
    case AArch64::SMLSLL_MZZ_BtoS:
35192
    case AArch64::SMLSLL_MZZ_HtoD:
35193
    case AArch64::SMLSLL_VG2_M2ZZ_BtoS:
35194
    case AArch64::SMLSLL_VG2_M2ZZ_HtoD:
35195
    case AArch64::SMLSLL_VG4_M4ZZ_BtoS:
35196
    case AArch64::SMLSLL_VG4_M4ZZ_HtoD:
35197
    case AArch64::SUMLALL_VG2_M2ZZ_BtoS:
35198
    case AArch64::SUMLALL_VG4_M4ZZ_BtoS:
35199
    case AArch64::UMLALL_MZZ_BtoS:
35200
    case AArch64::UMLALL_MZZ_HtoD:
35201
    case AArch64::UMLALL_VG2_M2ZZ_BtoS:
35202
    case AArch64::UMLALL_VG2_M2ZZ_HtoD:
35203
    case AArch64::UMLALL_VG4_M4ZZ_BtoS:
35204
    case AArch64::UMLALL_VG4_M4ZZ_HtoD:
35205
    case AArch64::UMLSLL_MZZ_BtoS:
35206
    case AArch64::UMLSLL_MZZ_HtoD:
35207
    case AArch64::UMLSLL_VG2_M2ZZ_BtoS:
35208
    case AArch64::UMLSLL_VG2_M2ZZ_HtoD:
35209
    case AArch64::UMLSLL_VG4_M4ZZ_BtoS:
35210
    case AArch64::UMLSLL_VG4_M4ZZ_HtoD:
35211
    case AArch64::USMLALL_MZZ_BtoS:
35212
    case AArch64::USMLALL_VG2_M2ZZ_BtoS:
35213
    case AArch64::USMLALL_VG4_M4ZZ_BtoS: {
35214
      switch (OpNum) {
35215
      case 5:
35216
        // op: Zm
35217
        return 16;
35218
      case 2:
35219
        // op: Rv
35220
        return 13;
35221
      case 4:
35222
        // op: Zn
35223
        return 5;
35224
      case 3:
35225
        // op: imm
35226
        return 0;
35227
      }
35228
      break;
35229
    }
35230
    case AArch64::BFDOT_VG2_M2ZZI_HtoS:
35231
    case AArch64::BFVDOT_VG2_M2ZZI_HtoS:
35232
    case AArch64::FDOT_VG2_M2ZZI_BtoS:
35233
    case AArch64::FDOT_VG2_M2ZZI_HtoS:
35234
    case AArch64::FMLA_VG2_M2ZZI_S:
35235
    case AArch64::FMLS_VG2_M2ZZI_S:
35236
    case AArch64::FVDOT_VG2_M2ZZI_HtoS:
35237
    case AArch64::SDOT_VG2_M2ZZI_BToS:
35238
    case AArch64::SDOT_VG2_M2ZZI_HToS:
35239
    case AArch64::SUDOT_VG2_M2ZZI_BToS:
35240
    case AArch64::SVDOT_VG2_M2ZZI_HtoS:
35241
    case AArch64::UDOT_VG2_M2ZZI_BToS:
35242
    case AArch64::UDOT_VG2_M2ZZI_HToS:
35243
    case AArch64::USDOT_VG2_M2ZZI_BToS:
35244
    case AArch64::UVDOT_VG2_M2ZZI_HtoS: {
35245
      switch (OpNum) {
35246
      case 5:
35247
        // op: Zm
35248
        return 16;
35249
      case 2:
35250
        // op: Rv
35251
        return 13;
35252
      case 4:
35253
        // op: Zn
35254
        return 6;
35255
      case 3:
35256
        // op: imm3
35257
        return 0;
35258
      case 6:
35259
        // op: i
35260
        return 10;
35261
      }
35262
      break;
35263
    }
35264
    case AArch64::BFMLA_VG2_M2ZZI:
35265
    case AArch64::BFMLS_VG2_M2ZZI:
35266
    case AArch64::FDOT_VG2_M2ZZI_BtoH:
35267
    case AArch64::FMLA_VG2_M2ZZI_H:
35268
    case AArch64::FMLS_VG2_M2ZZI_H:
35269
    case AArch64::FVDOTB_VG4_M2ZZI_BtoS:
35270
    case AArch64::FVDOTT_VG4_M2ZZI_BtoS:
35271
    case AArch64::FVDOT_VG2_M2ZZI_BtoH: {
35272
      switch (OpNum) {
35273
      case 5:
35274
        // op: Zm
35275
        return 16;
35276
      case 2:
35277
        // op: Rv
35278
        return 13;
35279
      case 4:
35280
        // op: Zn
35281
        return 6;
35282
      case 3:
35283
        // op: imm3
35284
        return 0;
35285
      case 6:
35286
        // op: i
35287
        return 3;
35288
      }
35289
      break;
35290
    }
35291
    case AArch64::BFDOT_VG4_M4ZZI_HtoS:
35292
    case AArch64::FDOT_VG4_M4ZZI_BtoS:
35293
    case AArch64::FDOT_VG4_M4ZZI_HtoS:
35294
    case AArch64::FMLA_VG4_M4ZZI_S:
35295
    case AArch64::FMLS_VG4_M4ZZI_S:
35296
    case AArch64::SDOT_VG4_M4ZZI_BToS:
35297
    case AArch64::SDOT_VG4_M4ZZI_HToS:
35298
    case AArch64::SUDOT_VG4_M4ZZI_BToS:
35299
    case AArch64::SUVDOT_VG4_M4ZZI_BToS:
35300
    case AArch64::SVDOT_VG4_M4ZZI_BtoS:
35301
    case AArch64::UDOT_VG4_M4ZZI_BtoS:
35302
    case AArch64::UDOT_VG4_M4ZZI_HToS:
35303
    case AArch64::USDOT_VG4_M4ZZI_BToS:
35304
    case AArch64::USVDOT_VG4_M4ZZI_BToS:
35305
    case AArch64::UVDOT_VG4_M4ZZI_BtoS: {
35306
      switch (OpNum) {
35307
      case 5:
35308
        // op: Zm
35309
        return 16;
35310
      case 2:
35311
        // op: Rv
35312
        return 13;
35313
      case 4:
35314
        // op: Zn
35315
        return 7;
35316
      case 3:
35317
        // op: imm3
35318
        return 0;
35319
      case 6:
35320
        // op: i
35321
        return 10;
35322
      }
35323
      break;
35324
    }
35325
    case AArch64::BFMLA_VG4_M4ZZI:
35326
    case AArch64::BFMLS_VG4_M4ZZI:
35327
    case AArch64::FDOT_VG4_M4ZZI_BtoH:
35328
    case AArch64::FMLA_VG4_M4ZZI_H:
35329
    case AArch64::FMLS_VG4_M4ZZI_H: {
35330
      switch (OpNum) {
35331
      case 5:
35332
        // op: Zm
35333
        return 16;
35334
      case 2:
35335
        // op: Rv
35336
        return 13;
35337
      case 4:
35338
        // op: Zn
35339
        return 7;
35340
      case 3:
35341
        // op: imm3
35342
        return 0;
35343
      case 6:
35344
        // op: i
35345
        return 3;
35346
      }
35347
      break;
35348
    }
35349
    case AArch64::FMLALL_MZZI_BtoS:
35350
    case AArch64::SMLALL_MZZI_BtoS:
35351
    case AArch64::SMLALL_MZZI_HtoD:
35352
    case AArch64::SMLSLL_MZZI_BtoS:
35353
    case AArch64::SMLSLL_MZZI_HtoD:
35354
    case AArch64::SUMLALL_MZZI_BtoS:
35355
    case AArch64::UMLALL_MZZI_BtoS:
35356
    case AArch64::UMLALL_MZZI_HtoD:
35357
    case AArch64::UMLSLL_MZZI_BtoS:
35358
    case AArch64::UMLSLL_MZZI_HtoD:
35359
    case AArch64::USMLALL_MZZI_BtoS: {
35360
      switch (OpNum) {
35361
      case 5:
35362
        // op: Zm
35363
        return 16;
35364
      case 2:
35365
        // op: Rv
35366
        return 13;
35367
      case 6:
35368
        // op: i
35369
        return 10;
35370
      case 4:
35371
        // op: Zn
35372
        return 5;
35373
      case 3:
35374
        // op: imm2
35375
        return 0;
35376
      }
35377
      break;
35378
    }
35379
    case AArch64::FMLALL_VG2_M2ZZI_BtoS:
35380
    case AArch64::SMLALL_VG2_M2ZZI_BtoS:
35381
    case AArch64::SMLALL_VG2_M2ZZI_HtoD:
35382
    case AArch64::SMLSLL_VG2_M2ZZI_BtoS:
35383
    case AArch64::SMLSLL_VG2_M2ZZI_HtoD:
35384
    case AArch64::SUMLALL_VG2_M2ZZI_BtoS:
35385
    case AArch64::UMLALL_VG2_M2ZZI_BtoS:
35386
    case AArch64::UMLALL_VG2_M2ZZI_HtoD:
35387
    case AArch64::UMLSLL_VG2_M2ZZI_BtoS:
35388
    case AArch64::UMLSLL_VG2_M2ZZI_HtoD:
35389
    case AArch64::USMLALL_VG2_M2ZZI_BtoS: {
35390
      switch (OpNum) {
35391
      case 5:
35392
        // op: Zm
35393
        return 16;
35394
      case 2:
35395
        // op: Rv
35396
        return 13;
35397
      case 6:
35398
        // op: i
35399
        return 1;
35400
      case 3:
35401
        // op: imm
35402
        return 0;
35403
      case 4:
35404
        // op: Zn
35405
        return 6;
35406
      }
35407
      break;
35408
    }
35409
    case AArch64::FMLALL_VG4_M4ZZI_BtoS:
35410
    case AArch64::SMLALL_VG4_M4ZZI_BtoS:
35411
    case AArch64::SMLALL_VG4_M4ZZI_HtoD:
35412
    case AArch64::SMLSLL_VG4_M4ZZI_BtoS:
35413
    case AArch64::SMLSLL_VG4_M4ZZI_HtoD:
35414
    case AArch64::SUMLALL_VG4_M4ZZI_BtoS:
35415
    case AArch64::UMLALL_VG4_M4ZZI_BtoS:
35416
    case AArch64::UMLALL_VG4_M4ZZI_HtoD:
35417
    case AArch64::UMLSLL_VG4_M4ZZI_BtoS:
35418
    case AArch64::UMLSLL_VG4_M4ZZI_HtoD:
35419
    case AArch64::USMLALL_VG4_M4ZZI_BtoS: {
35420
      switch (OpNum) {
35421
      case 5:
35422
        // op: Zm
35423
        return 16;
35424
      case 2:
35425
        // op: Rv
35426
        return 13;
35427
      case 6:
35428
        // op: i
35429
        return 1;
35430
      case 3:
35431
        // op: imm
35432
        return 0;
35433
      case 4:
35434
        // op: Zn
35435
        return 7;
35436
      }
35437
      break;
35438
    }
35439
    case AArch64::FMLAL_VG2_M2ZZI_BtoH: {
35440
      switch (OpNum) {
35441
      case 5:
35442
        // op: Zm
35443
        return 16;
35444
      case 2:
35445
        // op: Rv
35446
        return 13;
35447
      case 6:
35448
        // op: i
35449
        return 2;
35450
      case 3:
35451
        // op: imm2
35452
        return 0;
35453
      case 4:
35454
        // op: Zn
35455
        return 6;
35456
      }
35457
      break;
35458
    }
35459
    case AArch64::FMLAL_VG4_M4ZZI_BtoH: {
35460
      switch (OpNum) {
35461
      case 5:
35462
        // op: Zm
35463
        return 16;
35464
      case 2:
35465
        // op: Rv
35466
        return 13;
35467
      case 6:
35468
        // op: i
35469
        return 2;
35470
      case 3:
35471
        // op: imm2
35472
        return 0;
35473
      case 4:
35474
        // op: Zn
35475
        return 7;
35476
      }
35477
      break;
35478
    }
35479
    case AArch64::FMLAL_MZZI_BtoH: {
35480
      switch (OpNum) {
35481
      case 5:
35482
        // op: Zm
35483
        return 16;
35484
      case 2:
35485
        // op: Rv
35486
        return 13;
35487
      case 6:
35488
        // op: i
35489
        return 3;
35490
      case 4:
35491
        // op: Zn
35492
        return 5;
35493
      case 3:
35494
        // op: imm3
35495
        return 0;
35496
      }
35497
      break;
35498
    }
35499
    case AArch64::FMLA_VG2_M2ZZI_D:
35500
    case AArch64::FMLS_VG2_M2ZZI_D:
35501
    case AArch64::SDOT_VG2_M2ZZI_HtoD:
35502
    case AArch64::UDOT_VG2_M2ZZI_HtoD: {
35503
      switch (OpNum) {
35504
      case 5:
35505
        // op: Zm
35506
        return 16;
35507
      case 2:
35508
        // op: Rv
35509
        return 13;
35510
      case 6:
35511
        // op: i1
35512
        return 10;
35513
      case 4:
35514
        // op: Zn
35515
        return 6;
35516
      case 3:
35517
        // op: imm3
35518
        return 0;
35519
      }
35520
      break;
35521
    }
35522
    case AArch64::FMLA_VG4_M4ZZI_D:
35523
    case AArch64::FMLS_VG4_M4ZZI_D:
35524
    case AArch64::SDOT_VG4_M4ZZI_HtoD:
35525
    case AArch64::SVDOT_VG4_M4ZZI_HtoD:
35526
    case AArch64::UDOT_VG4_M4ZZI_HtoD:
35527
    case AArch64::UVDOT_VG4_M4ZZI_HtoD: {
35528
      switch (OpNum) {
35529
      case 5:
35530
        // op: Zm
35531
        return 16;
35532
      case 2:
35533
        // op: Rv
35534
        return 13;
35535
      case 6:
35536
        // op: i1
35537
        return 10;
35538
      case 4:
35539
        // op: Zn
35540
        return 7;
35541
      case 3:
35542
        // op: imm3
35543
        return 0;
35544
      }
35545
      break;
35546
    }
35547
    case AArch64::BFMLAL_MZZI_HtoS:
35548
    case AArch64::BFMLSL_MZZI_HtoS:
35549
    case AArch64::FMLAL_MZZI_HtoS:
35550
    case AArch64::FMLSL_MZZI_HtoS:
35551
    case AArch64::SMLAL_MZZI_HtoS:
35552
    case AArch64::SMLSL_MZZI_HtoS:
35553
    case AArch64::UMLAL_MZZI_HtoS:
35554
    case AArch64::UMLSL_MZZI_HtoS: {
35555
      switch (OpNum) {
35556
      case 5:
35557
        // op: Zm
35558
        return 16;
35559
      case 2:
35560
        // op: Rv
35561
        return 13;
35562
      case 6:
35563
        // op: i3
35564
        return 10;
35565
      case 4:
35566
        // op: Zn
35567
        return 5;
35568
      case 3:
35569
        // op: imm
35570
        return 0;
35571
      }
35572
      break;
35573
    }
35574
    case AArch64::BFMLAL_VG2_M2ZZI_HtoS:
35575
    case AArch64::BFMLSL_VG2_M2ZZI_HtoS:
35576
    case AArch64::FMLAL_VG2_M2ZZI_HtoS:
35577
    case AArch64::FMLSL_VG2_M2ZZI_HtoS:
35578
    case AArch64::SMLAL_VG2_M2ZZI_S:
35579
    case AArch64::SMLSL_VG2_M2ZZI_S:
35580
    case AArch64::UMLAL_VG2_M2ZZI_S:
35581
    case AArch64::UMLSL_VG2_M2ZZI_S: {
35582
      switch (OpNum) {
35583
      case 5:
35584
        // op: Zm
35585
        return 16;
35586
      case 2:
35587
        // op: Rv
35588
        return 13;
35589
      case 6:
35590
        // op: i3
35591
        return 2;
35592
      case 4:
35593
        // op: Zn
35594
        return 6;
35595
      case 3:
35596
        // op: imm
35597
        return 0;
35598
      }
35599
      break;
35600
    }
35601
    case AArch64::BFMLAL_VG4_M4ZZI_HtoS:
35602
    case AArch64::BFMLSL_VG4_M4ZZI_HtoS:
35603
    case AArch64::FMLAL_VG4_M4ZZI_HtoS:
35604
    case AArch64::FMLSL_VG4_M4ZZI_HtoS:
35605
    case AArch64::SMLAL_VG4_M4ZZI_HtoS:
35606
    case AArch64::SMLSL_VG4_M4ZZI_HtoS:
35607
    case AArch64::UMLAL_VG4_M4ZZI_HtoS:
35608
    case AArch64::UMLSL_VG4_M4ZZI_HtoS: {
35609
      switch (OpNum) {
35610
      case 5:
35611
        // op: Zm
35612
        return 16;
35613
      case 2:
35614
        // op: Rv
35615
        return 13;
35616
      case 6:
35617
        // op: i3
35618
        return 2;
35619
      case 4:
35620
        // op: Zn
35621
        return 7;
35622
      case 3:
35623
        // op: imm
35624
        return 0;
35625
      }
35626
      break;
35627
    }
35628
    case AArch64::BFMOPA_MPPZZ:
35629
    case AArch64::BFMOPA_MPPZZ_H:
35630
    case AArch64::BFMOPS_MPPZZ:
35631
    case AArch64::BFMOPS_MPPZZ_H:
35632
    case AArch64::BMOPA_MPPZZ_S:
35633
    case AArch64::BMOPS_MPPZZ_S:
35634
    case AArch64::FMOPAL_MPPZZ:
35635
    case AArch64::FMOPA_MPPZZ_BtoH:
35636
    case AArch64::FMOPA_MPPZZ_BtoS:
35637
    case AArch64::FMOPA_MPPZZ_D:
35638
    case AArch64::FMOPA_MPPZZ_H:
35639
    case AArch64::FMOPA_MPPZZ_S:
35640
    case AArch64::FMOPSL_MPPZZ:
35641
    case AArch64::FMOPS_MPPZZ_D:
35642
    case AArch64::FMOPS_MPPZZ_H:
35643
    case AArch64::FMOPS_MPPZZ_S:
35644
    case AArch64::SMOPA_MPPZZ_D:
35645
    case AArch64::SMOPA_MPPZZ_HtoS:
35646
    case AArch64::SMOPA_MPPZZ_S:
35647
    case AArch64::SMOPS_MPPZZ_D:
35648
    case AArch64::SMOPS_MPPZZ_HtoS:
35649
    case AArch64::SMOPS_MPPZZ_S:
35650
    case AArch64::SUMOPA_MPPZZ_D:
35651
    case AArch64::SUMOPA_MPPZZ_S:
35652
    case AArch64::SUMOPS_MPPZZ_D:
35653
    case AArch64::SUMOPS_MPPZZ_S:
35654
    case AArch64::UMOPA_MPPZZ_D:
35655
    case AArch64::UMOPA_MPPZZ_HtoS:
35656
    case AArch64::UMOPA_MPPZZ_S:
35657
    case AArch64::UMOPS_MPPZZ_D:
35658
    case AArch64::UMOPS_MPPZZ_HtoS:
35659
    case AArch64::UMOPS_MPPZZ_S:
35660
    case AArch64::USMOPA_MPPZZ_D:
35661
    case AArch64::USMOPA_MPPZZ_S:
35662
    case AArch64::USMOPS_MPPZZ_D:
35663
    case AArch64::USMOPS_MPPZZ_S: {
35664
      switch (OpNum) {
35665
      case 5:
35666
        // op: Zm
35667
        return 16;
35668
      case 3:
35669
        // op: Pm
35670
        return 13;
35671
      case 2:
35672
        // op: Pn
35673
        return 10;
35674
      case 4:
35675
        // op: Zn
35676
        return 5;
35677
      case 0:
35678
        // op: ZAda
35679
        return 0;
35680
      }
35681
      break;
35682
    }
35683
    case AArch64::ADD_VG2_M2ZZ_D:
35684
    case AArch64::ADD_VG2_M2ZZ_S:
35685
    case AArch64::ADD_VG4_M4ZZ_D:
35686
    case AArch64::ADD_VG4_M4ZZ_S:
35687
    case AArch64::BFDOT_VG2_M2ZZ_HtoS:
35688
    case AArch64::BFDOT_VG4_M4ZZ_HtoS:
35689
    case AArch64::BFMLA_VG2_M2ZZ:
35690
    case AArch64::BFMLA_VG4_M4ZZ:
35691
    case AArch64::BFMLS_VG2_M2ZZ:
35692
    case AArch64::BFMLS_VG4_M4ZZ:
35693
    case AArch64::FDOT_VG2_M2ZZ_BtoH:
35694
    case AArch64::FDOT_VG2_M2ZZ_BtoS:
35695
    case AArch64::FDOT_VG2_M2ZZ_HtoS:
35696
    case AArch64::FDOT_VG4_M4ZZ_BtoH:
35697
    case AArch64::FDOT_VG4_M4ZZ_BtoS:
35698
    case AArch64::FDOT_VG4_M4ZZ_HtoS:
35699
    case AArch64::FMLA_VG2_M2ZZ_D:
35700
    case AArch64::FMLA_VG2_M2ZZ_H:
35701
    case AArch64::FMLA_VG2_M2ZZ_S:
35702
    case AArch64::FMLA_VG4_M4ZZ_D:
35703
    case AArch64::FMLA_VG4_M4ZZ_H:
35704
    case AArch64::FMLA_VG4_M4ZZ_S:
35705
    case AArch64::FMLS_VG2_M2ZZ_D:
35706
    case AArch64::FMLS_VG2_M2ZZ_H:
35707
    case AArch64::FMLS_VG2_M2ZZ_S:
35708
    case AArch64::FMLS_VG4_M4ZZ_D:
35709
    case AArch64::FMLS_VG4_M4ZZ_H:
35710
    case AArch64::FMLS_VG4_M4ZZ_S:
35711
    case AArch64::SDOT_VG2_M2ZZ_BtoS:
35712
    case AArch64::SDOT_VG2_M2ZZ_HtoD:
35713
    case AArch64::SDOT_VG2_M2ZZ_HtoS:
35714
    case AArch64::SDOT_VG4_M4ZZ_BtoS:
35715
    case AArch64::SDOT_VG4_M4ZZ_HtoD:
35716
    case AArch64::SDOT_VG4_M4ZZ_HtoS:
35717
    case AArch64::SUB_VG2_M2ZZ_D:
35718
    case AArch64::SUB_VG2_M2ZZ_S:
35719
    case AArch64::SUB_VG4_M4ZZ_D:
35720
    case AArch64::SUB_VG4_M4ZZ_S:
35721
    case AArch64::SUDOT_VG2_M2ZZ_BToS:
35722
    case AArch64::SUDOT_VG4_M4ZZ_BToS:
35723
    case AArch64::UDOT_VG2_M2ZZ_BtoS:
35724
    case AArch64::UDOT_VG2_M2ZZ_HtoD:
35725
    case AArch64::UDOT_VG2_M2ZZ_HtoS:
35726
    case AArch64::UDOT_VG4_M4ZZ_BtoS:
35727
    case AArch64::UDOT_VG4_M4ZZ_HtoD:
35728
    case AArch64::UDOT_VG4_M4ZZ_HtoS:
35729
    case AArch64::USDOT_VG2_M2ZZ_BToS:
35730
    case AArch64::USDOT_VG4_M4ZZ_BToS: {
35731
      switch (OpNum) {
35732
      case 5:
35733
        // op: Zm
35734
        return 16;
35735
      case 4:
35736
        // op: Zn
35737
        return 5;
35738
      case 2:
35739
        // op: Rv
35740
        return 13;
35741
      case 3:
35742
        // op: imm3
35743
        return 0;
35744
      }
35745
      break;
35746
    }
35747
    case AArch64::FMLALL_VG2_M2Z2Z_BtoS:
35748
    case AArch64::SMLALL_VG2_M2Z2Z_BtoS:
35749
    case AArch64::SMLALL_VG2_M2Z2Z_HtoD:
35750
    case AArch64::SMLSLL_VG2_M2Z2Z_BtoS:
35751
    case AArch64::SMLSLL_VG2_M2Z2Z_HtoD:
35752
    case AArch64::UMLALL_VG2_M2Z2Z_BtoS:
35753
    case AArch64::UMLALL_VG2_M2Z2Z_HtoD:
35754
    case AArch64::UMLSLL_VG2_M2Z2Z_BtoS:
35755
    case AArch64::UMLSLL_VG2_M2Z2Z_HtoD:
35756
    case AArch64::USMLALL_VG2_M2Z2Z_BtoS: {
35757
      switch (OpNum) {
35758
      case 5:
35759
        // op: Zm
35760
        return 17;
35761
      case 2:
35762
        // op: Rv
35763
        return 13;
35764
      case 4:
35765
        // op: Zn
35766
        return 6;
35767
      case 3:
35768
        // op: imm
35769
        return 0;
35770
      }
35771
      break;
35772
    }
35773
    case AArch64::ADD_VG2_M2Z2Z_D:
35774
    case AArch64::ADD_VG2_M2Z2Z_S:
35775
    case AArch64::BFDOT_VG2_M2Z2Z_HtoS:
35776
    case AArch64::BFMLA_VG2_M2Z2Z:
35777
    case AArch64::BFMLS_VG2_M2Z2Z:
35778
    case AArch64::FDOT_VG2_M2Z2Z_BtoH:
35779
    case AArch64::FDOT_VG2_M2Z2Z_BtoS:
35780
    case AArch64::FDOT_VG2_M2Z2Z_HtoS:
35781
    case AArch64::FMLA_VG2_M2Z2Z_D:
35782
    case AArch64::FMLA_VG2_M2Z2Z_S:
35783
    case AArch64::FMLA_VG2_M2Z4Z_H:
35784
    case AArch64::FMLS_VG2_M2Z2Z_D:
35785
    case AArch64::FMLS_VG2_M2Z2Z_H:
35786
    case AArch64::FMLS_VG2_M2Z2Z_S:
35787
    case AArch64::SDOT_VG2_M2Z2Z_BtoS:
35788
    case AArch64::SDOT_VG2_M2Z2Z_HtoD:
35789
    case AArch64::SDOT_VG2_M2Z2Z_HtoS:
35790
    case AArch64::SUB_VG2_M2Z2Z_D:
35791
    case AArch64::SUB_VG2_M2Z2Z_S:
35792
    case AArch64::UDOT_VG2_M2Z2Z_BtoS:
35793
    case AArch64::UDOT_VG2_M2Z2Z_HtoD:
35794
    case AArch64::UDOT_VG2_M2Z2Z_HtoS:
35795
    case AArch64::USDOT_VG2_M2Z2Z_BToS: {
35796
      switch (OpNum) {
35797
      case 5:
35798
        // op: Zm
35799
        return 17;
35800
      case 4:
35801
        // op: Zn
35802
        return 6;
35803
      case 2:
35804
        // op: Rv
35805
        return 13;
35806
      case 3:
35807
        // op: imm3
35808
        return 0;
35809
      }
35810
      break;
35811
    }
35812
    case AArch64::FMLALL_VG4_M4Z4Z_BtoS:
35813
    case AArch64::SMLALL_VG4_M4Z4Z_BtoS:
35814
    case AArch64::SMLALL_VG4_M4Z4Z_HtoD:
35815
    case AArch64::SMLSLL_VG4_M4Z4Z_BtoS:
35816
    case AArch64::SMLSLL_VG4_M4Z4Z_HtoD:
35817
    case AArch64::UMLALL_VG4_M4Z4Z_BtoS:
35818
    case AArch64::UMLALL_VG4_M4Z4Z_HtoD:
35819
    case AArch64::UMLSLL_VG4_M4Z4Z_BtoS:
35820
    case AArch64::UMLSLL_VG4_M4Z4Z_HtoD:
35821
    case AArch64::USMLALL_VG4_M4Z4Z_BtoS: {
35822
      switch (OpNum) {
35823
      case 5:
35824
        // op: Zm
35825
        return 18;
35826
      case 2:
35827
        // op: Rv
35828
        return 13;
35829
      case 4:
35830
        // op: Zn
35831
        return 7;
35832
      case 3:
35833
        // op: imm
35834
        return 0;
35835
      }
35836
      break;
35837
    }
35838
    case AArch64::ADD_VG4_M4Z4Z_D:
35839
    case AArch64::ADD_VG4_M4Z4Z_S:
35840
    case AArch64::BFDOT_VG4_M4Z4Z_HtoS:
35841
    case AArch64::BFMLA_VG4_M4Z4Z:
35842
    case AArch64::BFMLS_VG4_M4Z4Z:
35843
    case AArch64::FDOT_VG4_M4Z4Z_BtoH:
35844
    case AArch64::FDOT_VG4_M4Z4Z_BtoS:
35845
    case AArch64::FDOT_VG4_M4Z4Z_HtoS:
35846
    case AArch64::FMLA_VG4_M4Z4Z_D:
35847
    case AArch64::FMLA_VG4_M4Z4Z_H:
35848
    case AArch64::FMLA_VG4_M4Z4Z_S:
35849
    case AArch64::FMLS_VG4_M4Z2Z_H:
35850
    case AArch64::FMLS_VG4_M4Z4Z_D:
35851
    case AArch64::FMLS_VG4_M4Z4Z_S:
35852
    case AArch64::SDOT_VG4_M4Z4Z_BtoS:
35853
    case AArch64::SDOT_VG4_M4Z4Z_HtoD:
35854
    case AArch64::SDOT_VG4_M4Z4Z_HtoS:
35855
    case AArch64::SUB_VG4_M4Z4Z_D:
35856
    case AArch64::SUB_VG4_M4Z4Z_S:
35857
    case AArch64::UDOT_VG4_M4Z4Z_BtoS:
35858
    case AArch64::UDOT_VG4_M4Z4Z_HtoD:
35859
    case AArch64::UDOT_VG4_M4Z4Z_HtoS:
35860
    case AArch64::USDOT_VG4_M4Z4Z_BToS: {
35861
      switch (OpNum) {
35862
      case 5:
35863
        // op: Zm
35864
        return 18;
35865
      case 4:
35866
        // op: Zn
35867
        return 7;
35868
      case 2:
35869
        // op: Rv
35870
        return 13;
35871
      case 3:
35872
        // op: imm3
35873
        return 0;
35874
      }
35875
      break;
35876
    }
35877
  }
35878
  std::string msg;
35879
  raw_string_ostream Msg(msg);
35880
  Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
35881
  report_fatal_error(Msg.str().c_str());
35882
}
35883
35884
#endif // GET_OPERAND_BIT_OFFSET
35885