/src/build/lib/Target/AArch64/AArch64GenMCPseudoLowering.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Pseudo-instruction MC lowering Source Fragment *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | bool AArch64AsmPrinter:: |
10 | | emitPseudoExpansionLowering(MCStreamer &OutStreamer, |
11 | 822k | const MachineInstr *MI) { |
12 | 822k | switch (MI->getOpcode()) { |
13 | 822k | default: return false; |
14 | 0 | case AArch64::BLRNoIP: { |
15 | 0 | MCInst TmpInst; |
16 | 0 | MCOperand MCOp; |
17 | 0 | TmpInst.setOpcode(AArch64::BLR); |
18 | | // Operand: Rn |
19 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
20 | 0 | TmpInst.addOperand(MCOp); |
21 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
22 | 0 | break; |
23 | 0 | } |
24 | 0 | case AArch64::GLD1B_D: { |
25 | 0 | MCInst TmpInst; |
26 | 0 | MCOperand MCOp; |
27 | 0 | TmpInst.setOpcode(AArch64::GLD1B_D_REAL); |
28 | | // Operand: Zt |
29 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
30 | 0 | TmpInst.addOperand(MCOp); |
31 | | // Operand: Pg |
32 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
33 | 0 | TmpInst.addOperand(MCOp); |
34 | | // Operand: Rn |
35 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
36 | 0 | TmpInst.addOperand(MCOp); |
37 | | // Operand: Zm |
38 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
39 | 0 | TmpInst.addOperand(MCOp); |
40 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
41 | 0 | break; |
42 | 0 | } |
43 | 0 | case AArch64::GLD1B_D_IMM: { |
44 | 0 | MCInst TmpInst; |
45 | 0 | MCOperand MCOp; |
46 | 0 | TmpInst.setOpcode(AArch64::GLD1B_D_IMM_REAL); |
47 | | // Operand: Zt |
48 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
49 | 0 | TmpInst.addOperand(MCOp); |
50 | | // Operand: Pg |
51 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
52 | 0 | TmpInst.addOperand(MCOp); |
53 | | // Operand: Zn |
54 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
55 | 0 | TmpInst.addOperand(MCOp); |
56 | | // Operand: imm5 |
57 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
58 | 0 | TmpInst.addOperand(MCOp); |
59 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
60 | 0 | break; |
61 | 0 | } |
62 | 0 | case AArch64::GLD1B_D_SXTW: { |
63 | 0 | MCInst TmpInst; |
64 | 0 | MCOperand MCOp; |
65 | 0 | TmpInst.setOpcode(AArch64::GLD1B_D_SXTW_REAL); |
66 | | // Operand: Zt |
67 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
68 | 0 | TmpInst.addOperand(MCOp); |
69 | | // Operand: Pg |
70 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
71 | 0 | TmpInst.addOperand(MCOp); |
72 | | // Operand: Rn |
73 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
74 | 0 | TmpInst.addOperand(MCOp); |
75 | | // Operand: Zm |
76 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
77 | 0 | TmpInst.addOperand(MCOp); |
78 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
79 | 0 | break; |
80 | 0 | } |
81 | 0 | case AArch64::GLD1B_D_UXTW: { |
82 | 0 | MCInst TmpInst; |
83 | 0 | MCOperand MCOp; |
84 | 0 | TmpInst.setOpcode(AArch64::GLD1B_D_UXTW_REAL); |
85 | | // Operand: Zt |
86 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
87 | 0 | TmpInst.addOperand(MCOp); |
88 | | // Operand: Pg |
89 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
90 | 0 | TmpInst.addOperand(MCOp); |
91 | | // Operand: Rn |
92 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
93 | 0 | TmpInst.addOperand(MCOp); |
94 | | // Operand: Zm |
95 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
96 | 0 | TmpInst.addOperand(MCOp); |
97 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
98 | 0 | break; |
99 | 0 | } |
100 | 0 | case AArch64::GLD1B_S_IMM: { |
101 | 0 | MCInst TmpInst; |
102 | 0 | MCOperand MCOp; |
103 | 0 | TmpInst.setOpcode(AArch64::GLD1B_S_IMM_REAL); |
104 | | // Operand: Zt |
105 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
106 | 0 | TmpInst.addOperand(MCOp); |
107 | | // Operand: Pg |
108 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
109 | 0 | TmpInst.addOperand(MCOp); |
110 | | // Operand: Zn |
111 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
112 | 0 | TmpInst.addOperand(MCOp); |
113 | | // Operand: imm5 |
114 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
115 | 0 | TmpInst.addOperand(MCOp); |
116 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
117 | 0 | break; |
118 | 0 | } |
119 | 0 | case AArch64::GLD1B_S_SXTW: { |
120 | 0 | MCInst TmpInst; |
121 | 0 | MCOperand MCOp; |
122 | 0 | TmpInst.setOpcode(AArch64::GLD1B_S_SXTW_REAL); |
123 | | // Operand: Zt |
124 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
125 | 0 | TmpInst.addOperand(MCOp); |
126 | | // Operand: Pg |
127 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
128 | 0 | TmpInst.addOperand(MCOp); |
129 | | // Operand: Rn |
130 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
131 | 0 | TmpInst.addOperand(MCOp); |
132 | | // Operand: Zm |
133 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
134 | 0 | TmpInst.addOperand(MCOp); |
135 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
136 | 0 | break; |
137 | 0 | } |
138 | 0 | case AArch64::GLD1B_S_UXTW: { |
139 | 0 | MCInst TmpInst; |
140 | 0 | MCOperand MCOp; |
141 | 0 | TmpInst.setOpcode(AArch64::GLD1B_S_UXTW_REAL); |
142 | | // Operand: Zt |
143 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
144 | 0 | TmpInst.addOperand(MCOp); |
145 | | // Operand: Pg |
146 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
147 | 0 | TmpInst.addOperand(MCOp); |
148 | | // Operand: Rn |
149 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
150 | 0 | TmpInst.addOperand(MCOp); |
151 | | // Operand: Zm |
152 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
153 | 0 | TmpInst.addOperand(MCOp); |
154 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
155 | 0 | break; |
156 | 0 | } |
157 | 0 | case AArch64::GLD1D: { |
158 | 0 | MCInst TmpInst; |
159 | 0 | MCOperand MCOp; |
160 | 0 | TmpInst.setOpcode(AArch64::GLD1D_REAL); |
161 | | // Operand: Zt |
162 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
163 | 0 | TmpInst.addOperand(MCOp); |
164 | | // Operand: Pg |
165 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
166 | 0 | TmpInst.addOperand(MCOp); |
167 | | // Operand: Rn |
168 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
169 | 0 | TmpInst.addOperand(MCOp); |
170 | | // Operand: Zm |
171 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
172 | 0 | TmpInst.addOperand(MCOp); |
173 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
174 | 0 | break; |
175 | 0 | } |
176 | 0 | case AArch64::GLD1D_IMM: { |
177 | 0 | MCInst TmpInst; |
178 | 0 | MCOperand MCOp; |
179 | 0 | TmpInst.setOpcode(AArch64::GLD1D_IMM_REAL); |
180 | | // Operand: Zt |
181 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
182 | 0 | TmpInst.addOperand(MCOp); |
183 | | // Operand: Pg |
184 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
185 | 0 | TmpInst.addOperand(MCOp); |
186 | | // Operand: Zn |
187 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
188 | 0 | TmpInst.addOperand(MCOp); |
189 | | // Operand: imm5 |
190 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
191 | 0 | TmpInst.addOperand(MCOp); |
192 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
193 | 0 | break; |
194 | 0 | } |
195 | 0 | case AArch64::GLD1D_SCALED: { |
196 | 0 | MCInst TmpInst; |
197 | 0 | MCOperand MCOp; |
198 | 0 | TmpInst.setOpcode(AArch64::GLD1D_SCALED_REAL); |
199 | | // Operand: Zt |
200 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
201 | 0 | TmpInst.addOperand(MCOp); |
202 | | // Operand: Pg |
203 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
204 | 0 | TmpInst.addOperand(MCOp); |
205 | | // Operand: Rn |
206 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
207 | 0 | TmpInst.addOperand(MCOp); |
208 | | // Operand: Zm |
209 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
210 | 0 | TmpInst.addOperand(MCOp); |
211 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
212 | 0 | break; |
213 | 0 | } |
214 | 0 | case AArch64::GLD1D_SXTW: { |
215 | 0 | MCInst TmpInst; |
216 | 0 | MCOperand MCOp; |
217 | 0 | TmpInst.setOpcode(AArch64::GLD1D_SXTW_REAL); |
218 | | // Operand: Zt |
219 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
220 | 0 | TmpInst.addOperand(MCOp); |
221 | | // Operand: Pg |
222 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
223 | 0 | TmpInst.addOperand(MCOp); |
224 | | // Operand: Rn |
225 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
226 | 0 | TmpInst.addOperand(MCOp); |
227 | | // Operand: Zm |
228 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
229 | 0 | TmpInst.addOperand(MCOp); |
230 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
231 | 0 | break; |
232 | 0 | } |
233 | 0 | case AArch64::GLD1D_SXTW_SCALED: { |
234 | 0 | MCInst TmpInst; |
235 | 0 | MCOperand MCOp; |
236 | 0 | TmpInst.setOpcode(AArch64::GLD1D_SXTW_SCALED_REAL); |
237 | | // Operand: Zt |
238 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
239 | 0 | TmpInst.addOperand(MCOp); |
240 | | // Operand: Pg |
241 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
242 | 0 | TmpInst.addOperand(MCOp); |
243 | | // Operand: Rn |
244 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
245 | 0 | TmpInst.addOperand(MCOp); |
246 | | // Operand: Zm |
247 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
248 | 0 | TmpInst.addOperand(MCOp); |
249 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
250 | 0 | break; |
251 | 0 | } |
252 | 0 | case AArch64::GLD1D_UXTW: { |
253 | 0 | MCInst TmpInst; |
254 | 0 | MCOperand MCOp; |
255 | 0 | TmpInst.setOpcode(AArch64::GLD1D_UXTW_REAL); |
256 | | // Operand: Zt |
257 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
258 | 0 | TmpInst.addOperand(MCOp); |
259 | | // Operand: Pg |
260 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
261 | 0 | TmpInst.addOperand(MCOp); |
262 | | // Operand: Rn |
263 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
264 | 0 | TmpInst.addOperand(MCOp); |
265 | | // Operand: Zm |
266 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
267 | 0 | TmpInst.addOperand(MCOp); |
268 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
269 | 0 | break; |
270 | 0 | } |
271 | 0 | case AArch64::GLD1D_UXTW_SCALED: { |
272 | 0 | MCInst TmpInst; |
273 | 0 | MCOperand MCOp; |
274 | 0 | TmpInst.setOpcode(AArch64::GLD1D_UXTW_SCALED_REAL); |
275 | | // Operand: Zt |
276 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
277 | 0 | TmpInst.addOperand(MCOp); |
278 | | // Operand: Pg |
279 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
280 | 0 | TmpInst.addOperand(MCOp); |
281 | | // Operand: Rn |
282 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
283 | 0 | TmpInst.addOperand(MCOp); |
284 | | // Operand: Zm |
285 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
286 | 0 | TmpInst.addOperand(MCOp); |
287 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
288 | 0 | break; |
289 | 0 | } |
290 | 0 | case AArch64::GLD1H_D: { |
291 | 0 | MCInst TmpInst; |
292 | 0 | MCOperand MCOp; |
293 | 0 | TmpInst.setOpcode(AArch64::GLD1H_D_REAL); |
294 | | // Operand: Zt |
295 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
296 | 0 | TmpInst.addOperand(MCOp); |
297 | | // Operand: Pg |
298 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
299 | 0 | TmpInst.addOperand(MCOp); |
300 | | // Operand: Rn |
301 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
302 | 0 | TmpInst.addOperand(MCOp); |
303 | | // Operand: Zm |
304 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
305 | 0 | TmpInst.addOperand(MCOp); |
306 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
307 | 0 | break; |
308 | 0 | } |
309 | 0 | case AArch64::GLD1H_D_IMM: { |
310 | 0 | MCInst TmpInst; |
311 | 0 | MCOperand MCOp; |
312 | 0 | TmpInst.setOpcode(AArch64::GLD1H_D_IMM_REAL); |
313 | | // Operand: Zt |
314 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
315 | 0 | TmpInst.addOperand(MCOp); |
316 | | // Operand: Pg |
317 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
318 | 0 | TmpInst.addOperand(MCOp); |
319 | | // Operand: Zn |
320 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
321 | 0 | TmpInst.addOperand(MCOp); |
322 | | // Operand: imm5 |
323 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
324 | 0 | TmpInst.addOperand(MCOp); |
325 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
326 | 0 | break; |
327 | 0 | } |
328 | 0 | case AArch64::GLD1H_D_SCALED: { |
329 | 0 | MCInst TmpInst; |
330 | 0 | MCOperand MCOp; |
331 | 0 | TmpInst.setOpcode(AArch64::GLD1H_D_SCALED_REAL); |
332 | | // Operand: Zt |
333 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
334 | 0 | TmpInst.addOperand(MCOp); |
335 | | // Operand: Pg |
336 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
337 | 0 | TmpInst.addOperand(MCOp); |
338 | | // Operand: Rn |
339 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
340 | 0 | TmpInst.addOperand(MCOp); |
341 | | // Operand: Zm |
342 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
343 | 0 | TmpInst.addOperand(MCOp); |
344 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
345 | 0 | break; |
346 | 0 | } |
347 | 0 | case AArch64::GLD1H_D_SXTW: { |
348 | 0 | MCInst TmpInst; |
349 | 0 | MCOperand MCOp; |
350 | 0 | TmpInst.setOpcode(AArch64::GLD1H_D_SXTW_REAL); |
351 | | // Operand: Zt |
352 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
353 | 0 | TmpInst.addOperand(MCOp); |
354 | | // Operand: Pg |
355 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
356 | 0 | TmpInst.addOperand(MCOp); |
357 | | // Operand: Rn |
358 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
359 | 0 | TmpInst.addOperand(MCOp); |
360 | | // Operand: Zm |
361 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
362 | 0 | TmpInst.addOperand(MCOp); |
363 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
364 | 0 | break; |
365 | 0 | } |
366 | 0 | case AArch64::GLD1H_D_SXTW_SCALED: { |
367 | 0 | MCInst TmpInst; |
368 | 0 | MCOperand MCOp; |
369 | 0 | TmpInst.setOpcode(AArch64::GLD1H_D_SXTW_SCALED_REAL); |
370 | | // Operand: Zt |
371 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
372 | 0 | TmpInst.addOperand(MCOp); |
373 | | // Operand: Pg |
374 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
375 | 0 | TmpInst.addOperand(MCOp); |
376 | | // Operand: Rn |
377 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
378 | 0 | TmpInst.addOperand(MCOp); |
379 | | // Operand: Zm |
380 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
381 | 0 | TmpInst.addOperand(MCOp); |
382 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
383 | 0 | break; |
384 | 0 | } |
385 | 0 | case AArch64::GLD1H_D_UXTW: { |
386 | 0 | MCInst TmpInst; |
387 | 0 | MCOperand MCOp; |
388 | 0 | TmpInst.setOpcode(AArch64::GLD1H_D_UXTW_REAL); |
389 | | // Operand: Zt |
390 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
391 | 0 | TmpInst.addOperand(MCOp); |
392 | | // Operand: Pg |
393 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
394 | 0 | TmpInst.addOperand(MCOp); |
395 | | // Operand: Rn |
396 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
397 | 0 | TmpInst.addOperand(MCOp); |
398 | | // Operand: Zm |
399 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
400 | 0 | TmpInst.addOperand(MCOp); |
401 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
402 | 0 | break; |
403 | 0 | } |
404 | 0 | case AArch64::GLD1H_D_UXTW_SCALED: { |
405 | 0 | MCInst TmpInst; |
406 | 0 | MCOperand MCOp; |
407 | 0 | TmpInst.setOpcode(AArch64::GLD1H_D_UXTW_SCALED_REAL); |
408 | | // Operand: Zt |
409 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
410 | 0 | TmpInst.addOperand(MCOp); |
411 | | // Operand: Pg |
412 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
413 | 0 | TmpInst.addOperand(MCOp); |
414 | | // Operand: Rn |
415 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
416 | 0 | TmpInst.addOperand(MCOp); |
417 | | // Operand: Zm |
418 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
419 | 0 | TmpInst.addOperand(MCOp); |
420 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
421 | 0 | break; |
422 | 0 | } |
423 | 0 | case AArch64::GLD1H_S_IMM: { |
424 | 0 | MCInst TmpInst; |
425 | 0 | MCOperand MCOp; |
426 | 0 | TmpInst.setOpcode(AArch64::GLD1H_S_IMM_REAL); |
427 | | // Operand: Zt |
428 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
429 | 0 | TmpInst.addOperand(MCOp); |
430 | | // Operand: Pg |
431 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
432 | 0 | TmpInst.addOperand(MCOp); |
433 | | // Operand: Zn |
434 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
435 | 0 | TmpInst.addOperand(MCOp); |
436 | | // Operand: imm5 |
437 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
438 | 0 | TmpInst.addOperand(MCOp); |
439 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
440 | 0 | break; |
441 | 0 | } |
442 | 0 | case AArch64::GLD1H_S_SXTW: { |
443 | 0 | MCInst TmpInst; |
444 | 0 | MCOperand MCOp; |
445 | 0 | TmpInst.setOpcode(AArch64::GLD1H_S_SXTW_REAL); |
446 | | // Operand: Zt |
447 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
448 | 0 | TmpInst.addOperand(MCOp); |
449 | | // Operand: Pg |
450 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
451 | 0 | TmpInst.addOperand(MCOp); |
452 | | // Operand: Rn |
453 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
454 | 0 | TmpInst.addOperand(MCOp); |
455 | | // Operand: Zm |
456 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
457 | 0 | TmpInst.addOperand(MCOp); |
458 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
459 | 0 | break; |
460 | 0 | } |
461 | 0 | case AArch64::GLD1H_S_SXTW_SCALED: { |
462 | 0 | MCInst TmpInst; |
463 | 0 | MCOperand MCOp; |
464 | 0 | TmpInst.setOpcode(AArch64::GLD1H_S_SXTW_SCALED_REAL); |
465 | | // Operand: Zt |
466 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
467 | 0 | TmpInst.addOperand(MCOp); |
468 | | // Operand: Pg |
469 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
470 | 0 | TmpInst.addOperand(MCOp); |
471 | | // Operand: Rn |
472 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
473 | 0 | TmpInst.addOperand(MCOp); |
474 | | // Operand: Zm |
475 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
476 | 0 | TmpInst.addOperand(MCOp); |
477 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
478 | 0 | break; |
479 | 0 | } |
480 | 0 | case AArch64::GLD1H_S_UXTW: { |
481 | 0 | MCInst TmpInst; |
482 | 0 | MCOperand MCOp; |
483 | 0 | TmpInst.setOpcode(AArch64::GLD1H_S_UXTW_REAL); |
484 | | // Operand: Zt |
485 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
486 | 0 | TmpInst.addOperand(MCOp); |
487 | | // Operand: Pg |
488 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
489 | 0 | TmpInst.addOperand(MCOp); |
490 | | // Operand: Rn |
491 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
492 | 0 | TmpInst.addOperand(MCOp); |
493 | | // Operand: Zm |
494 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
495 | 0 | TmpInst.addOperand(MCOp); |
496 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
497 | 0 | break; |
498 | 0 | } |
499 | 0 | case AArch64::GLD1H_S_UXTW_SCALED: { |
500 | 0 | MCInst TmpInst; |
501 | 0 | MCOperand MCOp; |
502 | 0 | TmpInst.setOpcode(AArch64::GLD1H_S_UXTW_SCALED_REAL); |
503 | | // Operand: Zt |
504 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
505 | 0 | TmpInst.addOperand(MCOp); |
506 | | // Operand: Pg |
507 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
508 | 0 | TmpInst.addOperand(MCOp); |
509 | | // Operand: Rn |
510 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
511 | 0 | TmpInst.addOperand(MCOp); |
512 | | // Operand: Zm |
513 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
514 | 0 | TmpInst.addOperand(MCOp); |
515 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
516 | 0 | break; |
517 | 0 | } |
518 | 0 | case AArch64::GLD1SB_D: { |
519 | 0 | MCInst TmpInst; |
520 | 0 | MCOperand MCOp; |
521 | 0 | TmpInst.setOpcode(AArch64::GLD1SB_D_REAL); |
522 | | // Operand: Zt |
523 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
524 | 0 | TmpInst.addOperand(MCOp); |
525 | | // Operand: Pg |
526 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
527 | 0 | TmpInst.addOperand(MCOp); |
528 | | // Operand: Rn |
529 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
530 | 0 | TmpInst.addOperand(MCOp); |
531 | | // Operand: Zm |
532 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
533 | 0 | TmpInst.addOperand(MCOp); |
534 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
535 | 0 | break; |
536 | 0 | } |
537 | 0 | case AArch64::GLD1SB_D_IMM: { |
538 | 0 | MCInst TmpInst; |
539 | 0 | MCOperand MCOp; |
540 | 0 | TmpInst.setOpcode(AArch64::GLD1SB_D_IMM_REAL); |
541 | | // Operand: Zt |
542 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
543 | 0 | TmpInst.addOperand(MCOp); |
544 | | // Operand: Pg |
545 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
546 | 0 | TmpInst.addOperand(MCOp); |
547 | | // Operand: Zn |
548 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
549 | 0 | TmpInst.addOperand(MCOp); |
550 | | // Operand: imm5 |
551 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
552 | 0 | TmpInst.addOperand(MCOp); |
553 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
554 | 0 | break; |
555 | 0 | } |
556 | 0 | case AArch64::GLD1SB_D_SXTW: { |
557 | 0 | MCInst TmpInst; |
558 | 0 | MCOperand MCOp; |
559 | 0 | TmpInst.setOpcode(AArch64::GLD1SB_D_SXTW_REAL); |
560 | | // Operand: Zt |
561 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
562 | 0 | TmpInst.addOperand(MCOp); |
563 | | // Operand: Pg |
564 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
565 | 0 | TmpInst.addOperand(MCOp); |
566 | | // Operand: Rn |
567 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
568 | 0 | TmpInst.addOperand(MCOp); |
569 | | // Operand: Zm |
570 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
571 | 0 | TmpInst.addOperand(MCOp); |
572 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
573 | 0 | break; |
574 | 0 | } |
575 | 0 | case AArch64::GLD1SB_D_UXTW: { |
576 | 0 | MCInst TmpInst; |
577 | 0 | MCOperand MCOp; |
578 | 0 | TmpInst.setOpcode(AArch64::GLD1SB_D_UXTW_REAL); |
579 | | // Operand: Zt |
580 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
581 | 0 | TmpInst.addOperand(MCOp); |
582 | | // Operand: Pg |
583 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
584 | 0 | TmpInst.addOperand(MCOp); |
585 | | // Operand: Rn |
586 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
587 | 0 | TmpInst.addOperand(MCOp); |
588 | | // Operand: Zm |
589 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
590 | 0 | TmpInst.addOperand(MCOp); |
591 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
592 | 0 | break; |
593 | 0 | } |
594 | 0 | case AArch64::GLD1SB_S_IMM: { |
595 | 0 | MCInst TmpInst; |
596 | 0 | MCOperand MCOp; |
597 | 0 | TmpInst.setOpcode(AArch64::GLD1SB_S_IMM_REAL); |
598 | | // Operand: Zt |
599 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
600 | 0 | TmpInst.addOperand(MCOp); |
601 | | // Operand: Pg |
602 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
603 | 0 | TmpInst.addOperand(MCOp); |
604 | | // Operand: Zn |
605 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
606 | 0 | TmpInst.addOperand(MCOp); |
607 | | // Operand: imm5 |
608 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
609 | 0 | TmpInst.addOperand(MCOp); |
610 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
611 | 0 | break; |
612 | 0 | } |
613 | 0 | case AArch64::GLD1SB_S_SXTW: { |
614 | 0 | MCInst TmpInst; |
615 | 0 | MCOperand MCOp; |
616 | 0 | TmpInst.setOpcode(AArch64::GLD1SB_S_SXTW_REAL); |
617 | | // Operand: Zt |
618 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
619 | 0 | TmpInst.addOperand(MCOp); |
620 | | // Operand: Pg |
621 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
622 | 0 | TmpInst.addOperand(MCOp); |
623 | | // Operand: Rn |
624 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
625 | 0 | TmpInst.addOperand(MCOp); |
626 | | // Operand: Zm |
627 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
628 | 0 | TmpInst.addOperand(MCOp); |
629 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
630 | 0 | break; |
631 | 0 | } |
632 | 0 | case AArch64::GLD1SB_S_UXTW: { |
633 | 0 | MCInst TmpInst; |
634 | 0 | MCOperand MCOp; |
635 | 0 | TmpInst.setOpcode(AArch64::GLD1SB_S_UXTW_REAL); |
636 | | // Operand: Zt |
637 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
638 | 0 | TmpInst.addOperand(MCOp); |
639 | | // Operand: Pg |
640 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
641 | 0 | TmpInst.addOperand(MCOp); |
642 | | // Operand: Rn |
643 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
644 | 0 | TmpInst.addOperand(MCOp); |
645 | | // Operand: Zm |
646 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
647 | 0 | TmpInst.addOperand(MCOp); |
648 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
649 | 0 | break; |
650 | 0 | } |
651 | 0 | case AArch64::GLD1SH_D: { |
652 | 0 | MCInst TmpInst; |
653 | 0 | MCOperand MCOp; |
654 | 0 | TmpInst.setOpcode(AArch64::GLD1SH_D_REAL); |
655 | | // Operand: Zt |
656 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
657 | 0 | TmpInst.addOperand(MCOp); |
658 | | // Operand: Pg |
659 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
660 | 0 | TmpInst.addOperand(MCOp); |
661 | | // Operand: Rn |
662 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
663 | 0 | TmpInst.addOperand(MCOp); |
664 | | // Operand: Zm |
665 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
666 | 0 | TmpInst.addOperand(MCOp); |
667 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
668 | 0 | break; |
669 | 0 | } |
670 | 0 | case AArch64::GLD1SH_D_IMM: { |
671 | 0 | MCInst TmpInst; |
672 | 0 | MCOperand MCOp; |
673 | 0 | TmpInst.setOpcode(AArch64::GLD1SH_D_IMM_REAL); |
674 | | // Operand: Zt |
675 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
676 | 0 | TmpInst.addOperand(MCOp); |
677 | | // Operand: Pg |
678 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
679 | 0 | TmpInst.addOperand(MCOp); |
680 | | // Operand: Zn |
681 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
682 | 0 | TmpInst.addOperand(MCOp); |
683 | | // Operand: imm5 |
684 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
685 | 0 | TmpInst.addOperand(MCOp); |
686 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
687 | 0 | break; |
688 | 0 | } |
689 | 0 | case AArch64::GLD1SH_D_SCALED: { |
690 | 0 | MCInst TmpInst; |
691 | 0 | MCOperand MCOp; |
692 | 0 | TmpInst.setOpcode(AArch64::GLD1SH_D_SCALED_REAL); |
693 | | // Operand: Zt |
694 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
695 | 0 | TmpInst.addOperand(MCOp); |
696 | | // Operand: Pg |
697 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
698 | 0 | TmpInst.addOperand(MCOp); |
699 | | // Operand: Rn |
700 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
701 | 0 | TmpInst.addOperand(MCOp); |
702 | | // Operand: Zm |
703 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
704 | 0 | TmpInst.addOperand(MCOp); |
705 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
706 | 0 | break; |
707 | 0 | } |
708 | 0 | case AArch64::GLD1SH_D_SXTW: { |
709 | 0 | MCInst TmpInst; |
710 | 0 | MCOperand MCOp; |
711 | 0 | TmpInst.setOpcode(AArch64::GLD1SH_D_SXTW_REAL); |
712 | | // Operand: Zt |
713 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
714 | 0 | TmpInst.addOperand(MCOp); |
715 | | // Operand: Pg |
716 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
717 | 0 | TmpInst.addOperand(MCOp); |
718 | | // Operand: Rn |
719 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
720 | 0 | TmpInst.addOperand(MCOp); |
721 | | // Operand: Zm |
722 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
723 | 0 | TmpInst.addOperand(MCOp); |
724 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
725 | 0 | break; |
726 | 0 | } |
727 | 0 | case AArch64::GLD1SH_D_SXTW_SCALED: { |
728 | 0 | MCInst TmpInst; |
729 | 0 | MCOperand MCOp; |
730 | 0 | TmpInst.setOpcode(AArch64::GLD1SH_D_SXTW_SCALED_REAL); |
731 | | // Operand: Zt |
732 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
733 | 0 | TmpInst.addOperand(MCOp); |
734 | | // Operand: Pg |
735 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
736 | 0 | TmpInst.addOperand(MCOp); |
737 | | // Operand: Rn |
738 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
739 | 0 | TmpInst.addOperand(MCOp); |
740 | | // Operand: Zm |
741 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
742 | 0 | TmpInst.addOperand(MCOp); |
743 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
744 | 0 | break; |
745 | 0 | } |
746 | 0 | case AArch64::GLD1SH_D_UXTW: { |
747 | 0 | MCInst TmpInst; |
748 | 0 | MCOperand MCOp; |
749 | 0 | TmpInst.setOpcode(AArch64::GLD1SH_D_UXTW_REAL); |
750 | | // Operand: Zt |
751 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
752 | 0 | TmpInst.addOperand(MCOp); |
753 | | // Operand: Pg |
754 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
755 | 0 | TmpInst.addOperand(MCOp); |
756 | | // Operand: Rn |
757 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
758 | 0 | TmpInst.addOperand(MCOp); |
759 | | // Operand: Zm |
760 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
761 | 0 | TmpInst.addOperand(MCOp); |
762 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
763 | 0 | break; |
764 | 0 | } |
765 | 0 | case AArch64::GLD1SH_D_UXTW_SCALED: { |
766 | 0 | MCInst TmpInst; |
767 | 0 | MCOperand MCOp; |
768 | 0 | TmpInst.setOpcode(AArch64::GLD1SH_D_UXTW_SCALED_REAL); |
769 | | // Operand: Zt |
770 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
771 | 0 | TmpInst.addOperand(MCOp); |
772 | | // Operand: Pg |
773 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
774 | 0 | TmpInst.addOperand(MCOp); |
775 | | // Operand: Rn |
776 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
777 | 0 | TmpInst.addOperand(MCOp); |
778 | | // Operand: Zm |
779 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
780 | 0 | TmpInst.addOperand(MCOp); |
781 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
782 | 0 | break; |
783 | 0 | } |
784 | 0 | case AArch64::GLD1SH_S_IMM: { |
785 | 0 | MCInst TmpInst; |
786 | 0 | MCOperand MCOp; |
787 | 0 | TmpInst.setOpcode(AArch64::GLD1SH_S_IMM_REAL); |
788 | | // Operand: Zt |
789 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
790 | 0 | TmpInst.addOperand(MCOp); |
791 | | // Operand: Pg |
792 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
793 | 0 | TmpInst.addOperand(MCOp); |
794 | | // Operand: Zn |
795 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
796 | 0 | TmpInst.addOperand(MCOp); |
797 | | // Operand: imm5 |
798 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
799 | 0 | TmpInst.addOperand(MCOp); |
800 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
801 | 0 | break; |
802 | 0 | } |
803 | 0 | case AArch64::GLD1SH_S_SXTW: { |
804 | 0 | MCInst TmpInst; |
805 | 0 | MCOperand MCOp; |
806 | 0 | TmpInst.setOpcode(AArch64::GLD1SH_S_SXTW_REAL); |
807 | | // Operand: Zt |
808 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
809 | 0 | TmpInst.addOperand(MCOp); |
810 | | // Operand: Pg |
811 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
812 | 0 | TmpInst.addOperand(MCOp); |
813 | | // Operand: Rn |
814 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
815 | 0 | TmpInst.addOperand(MCOp); |
816 | | // Operand: Zm |
817 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
818 | 0 | TmpInst.addOperand(MCOp); |
819 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
820 | 0 | break; |
821 | 0 | } |
822 | 0 | case AArch64::GLD1SH_S_SXTW_SCALED: { |
823 | 0 | MCInst TmpInst; |
824 | 0 | MCOperand MCOp; |
825 | 0 | TmpInst.setOpcode(AArch64::GLD1SH_S_SXTW_SCALED_REAL); |
826 | | // Operand: Zt |
827 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
828 | 0 | TmpInst.addOperand(MCOp); |
829 | | // Operand: Pg |
830 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
831 | 0 | TmpInst.addOperand(MCOp); |
832 | | // Operand: Rn |
833 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
834 | 0 | TmpInst.addOperand(MCOp); |
835 | | // Operand: Zm |
836 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
837 | 0 | TmpInst.addOperand(MCOp); |
838 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
839 | 0 | break; |
840 | 0 | } |
841 | 0 | case AArch64::GLD1SH_S_UXTW: { |
842 | 0 | MCInst TmpInst; |
843 | 0 | MCOperand MCOp; |
844 | 0 | TmpInst.setOpcode(AArch64::GLD1SH_S_UXTW_REAL); |
845 | | // Operand: Zt |
846 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
847 | 0 | TmpInst.addOperand(MCOp); |
848 | | // Operand: Pg |
849 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
850 | 0 | TmpInst.addOperand(MCOp); |
851 | | // Operand: Rn |
852 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
853 | 0 | TmpInst.addOperand(MCOp); |
854 | | // Operand: Zm |
855 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
856 | 0 | TmpInst.addOperand(MCOp); |
857 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
858 | 0 | break; |
859 | 0 | } |
860 | 0 | case AArch64::GLD1SH_S_UXTW_SCALED: { |
861 | 0 | MCInst TmpInst; |
862 | 0 | MCOperand MCOp; |
863 | 0 | TmpInst.setOpcode(AArch64::GLD1SH_S_UXTW_SCALED_REAL); |
864 | | // Operand: Zt |
865 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
866 | 0 | TmpInst.addOperand(MCOp); |
867 | | // Operand: Pg |
868 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
869 | 0 | TmpInst.addOperand(MCOp); |
870 | | // Operand: Rn |
871 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
872 | 0 | TmpInst.addOperand(MCOp); |
873 | | // Operand: Zm |
874 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
875 | 0 | TmpInst.addOperand(MCOp); |
876 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
877 | 0 | break; |
878 | 0 | } |
879 | 0 | case AArch64::GLD1SW_D: { |
880 | 0 | MCInst TmpInst; |
881 | 0 | MCOperand MCOp; |
882 | 0 | TmpInst.setOpcode(AArch64::GLD1SW_D_REAL); |
883 | | // Operand: Zt |
884 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
885 | 0 | TmpInst.addOperand(MCOp); |
886 | | // Operand: Pg |
887 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
888 | 0 | TmpInst.addOperand(MCOp); |
889 | | // Operand: Rn |
890 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
891 | 0 | TmpInst.addOperand(MCOp); |
892 | | // Operand: Zm |
893 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
894 | 0 | TmpInst.addOperand(MCOp); |
895 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
896 | 0 | break; |
897 | 0 | } |
898 | 0 | case AArch64::GLD1SW_D_IMM: { |
899 | 0 | MCInst TmpInst; |
900 | 0 | MCOperand MCOp; |
901 | 0 | TmpInst.setOpcode(AArch64::GLD1SW_D_IMM_REAL); |
902 | | // Operand: Zt |
903 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
904 | 0 | TmpInst.addOperand(MCOp); |
905 | | // Operand: Pg |
906 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
907 | 0 | TmpInst.addOperand(MCOp); |
908 | | // Operand: Zn |
909 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
910 | 0 | TmpInst.addOperand(MCOp); |
911 | | // Operand: imm5 |
912 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
913 | 0 | TmpInst.addOperand(MCOp); |
914 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
915 | 0 | break; |
916 | 0 | } |
917 | 0 | case AArch64::GLD1SW_D_SCALED: { |
918 | 0 | MCInst TmpInst; |
919 | 0 | MCOperand MCOp; |
920 | 0 | TmpInst.setOpcode(AArch64::GLD1SW_D_SCALED_REAL); |
921 | | // Operand: Zt |
922 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
923 | 0 | TmpInst.addOperand(MCOp); |
924 | | // Operand: Pg |
925 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
926 | 0 | TmpInst.addOperand(MCOp); |
927 | | // Operand: Rn |
928 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
929 | 0 | TmpInst.addOperand(MCOp); |
930 | | // Operand: Zm |
931 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
932 | 0 | TmpInst.addOperand(MCOp); |
933 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
934 | 0 | break; |
935 | 0 | } |
936 | 0 | case AArch64::GLD1SW_D_SXTW: { |
937 | 0 | MCInst TmpInst; |
938 | 0 | MCOperand MCOp; |
939 | 0 | TmpInst.setOpcode(AArch64::GLD1SW_D_SXTW_REAL); |
940 | | // Operand: Zt |
941 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
942 | 0 | TmpInst.addOperand(MCOp); |
943 | | // Operand: Pg |
944 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
945 | 0 | TmpInst.addOperand(MCOp); |
946 | | // Operand: Rn |
947 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
948 | 0 | TmpInst.addOperand(MCOp); |
949 | | // Operand: Zm |
950 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
951 | 0 | TmpInst.addOperand(MCOp); |
952 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
953 | 0 | break; |
954 | 0 | } |
955 | 0 | case AArch64::GLD1SW_D_SXTW_SCALED: { |
956 | 0 | MCInst TmpInst; |
957 | 0 | MCOperand MCOp; |
958 | 0 | TmpInst.setOpcode(AArch64::GLD1SW_D_SXTW_SCALED_REAL); |
959 | | // Operand: Zt |
960 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
961 | 0 | TmpInst.addOperand(MCOp); |
962 | | // Operand: Pg |
963 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
964 | 0 | TmpInst.addOperand(MCOp); |
965 | | // Operand: Rn |
966 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
967 | 0 | TmpInst.addOperand(MCOp); |
968 | | // Operand: Zm |
969 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
970 | 0 | TmpInst.addOperand(MCOp); |
971 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
972 | 0 | break; |
973 | 0 | } |
974 | 0 | case AArch64::GLD1SW_D_UXTW: { |
975 | 0 | MCInst TmpInst; |
976 | 0 | MCOperand MCOp; |
977 | 0 | TmpInst.setOpcode(AArch64::GLD1SW_D_UXTW_REAL); |
978 | | // Operand: Zt |
979 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
980 | 0 | TmpInst.addOperand(MCOp); |
981 | | // Operand: Pg |
982 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
983 | 0 | TmpInst.addOperand(MCOp); |
984 | | // Operand: Rn |
985 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
986 | 0 | TmpInst.addOperand(MCOp); |
987 | | // Operand: Zm |
988 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
989 | 0 | TmpInst.addOperand(MCOp); |
990 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
991 | 0 | break; |
992 | 0 | } |
993 | 0 | case AArch64::GLD1SW_D_UXTW_SCALED: { |
994 | 0 | MCInst TmpInst; |
995 | 0 | MCOperand MCOp; |
996 | 0 | TmpInst.setOpcode(AArch64::GLD1SW_D_UXTW_SCALED_REAL); |
997 | | // Operand: Zt |
998 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
999 | 0 | TmpInst.addOperand(MCOp); |
1000 | | // Operand: Pg |
1001 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1002 | 0 | TmpInst.addOperand(MCOp); |
1003 | | // Operand: Rn |
1004 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1005 | 0 | TmpInst.addOperand(MCOp); |
1006 | | // Operand: Zm |
1007 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1008 | 0 | TmpInst.addOperand(MCOp); |
1009 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1010 | 0 | break; |
1011 | 0 | } |
1012 | 0 | case AArch64::GLD1W_D: { |
1013 | 0 | MCInst TmpInst; |
1014 | 0 | MCOperand MCOp; |
1015 | 0 | TmpInst.setOpcode(AArch64::GLD1W_D_REAL); |
1016 | | // Operand: Zt |
1017 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1018 | 0 | TmpInst.addOperand(MCOp); |
1019 | | // Operand: Pg |
1020 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1021 | 0 | TmpInst.addOperand(MCOp); |
1022 | | // Operand: Rn |
1023 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1024 | 0 | TmpInst.addOperand(MCOp); |
1025 | | // Operand: Zm |
1026 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1027 | 0 | TmpInst.addOperand(MCOp); |
1028 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1029 | 0 | break; |
1030 | 0 | } |
1031 | 0 | case AArch64::GLD1W_D_IMM: { |
1032 | 0 | MCInst TmpInst; |
1033 | 0 | MCOperand MCOp; |
1034 | 0 | TmpInst.setOpcode(AArch64::GLD1W_D_IMM_REAL); |
1035 | | // Operand: Zt |
1036 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1037 | 0 | TmpInst.addOperand(MCOp); |
1038 | | // Operand: Pg |
1039 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1040 | 0 | TmpInst.addOperand(MCOp); |
1041 | | // Operand: Zn |
1042 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1043 | 0 | TmpInst.addOperand(MCOp); |
1044 | | // Operand: imm5 |
1045 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1046 | 0 | TmpInst.addOperand(MCOp); |
1047 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1048 | 0 | break; |
1049 | 0 | } |
1050 | 0 | case AArch64::GLD1W_D_SCALED: { |
1051 | 0 | MCInst TmpInst; |
1052 | 0 | MCOperand MCOp; |
1053 | 0 | TmpInst.setOpcode(AArch64::GLD1W_D_SCALED_REAL); |
1054 | | // Operand: Zt |
1055 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1056 | 0 | TmpInst.addOperand(MCOp); |
1057 | | // Operand: Pg |
1058 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1059 | 0 | TmpInst.addOperand(MCOp); |
1060 | | // Operand: Rn |
1061 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1062 | 0 | TmpInst.addOperand(MCOp); |
1063 | | // Operand: Zm |
1064 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1065 | 0 | TmpInst.addOperand(MCOp); |
1066 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1067 | 0 | break; |
1068 | 0 | } |
1069 | 0 | case AArch64::GLD1W_D_SXTW: { |
1070 | 0 | MCInst TmpInst; |
1071 | 0 | MCOperand MCOp; |
1072 | 0 | TmpInst.setOpcode(AArch64::GLD1W_D_SXTW_REAL); |
1073 | | // Operand: Zt |
1074 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1075 | 0 | TmpInst.addOperand(MCOp); |
1076 | | // Operand: Pg |
1077 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1078 | 0 | TmpInst.addOperand(MCOp); |
1079 | | // Operand: Rn |
1080 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1081 | 0 | TmpInst.addOperand(MCOp); |
1082 | | // Operand: Zm |
1083 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1084 | 0 | TmpInst.addOperand(MCOp); |
1085 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1086 | 0 | break; |
1087 | 0 | } |
1088 | 0 | case AArch64::GLD1W_D_SXTW_SCALED: { |
1089 | 0 | MCInst TmpInst; |
1090 | 0 | MCOperand MCOp; |
1091 | 0 | TmpInst.setOpcode(AArch64::GLD1W_D_SXTW_SCALED_REAL); |
1092 | | // Operand: Zt |
1093 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1094 | 0 | TmpInst.addOperand(MCOp); |
1095 | | // Operand: Pg |
1096 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1097 | 0 | TmpInst.addOperand(MCOp); |
1098 | | // Operand: Rn |
1099 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1100 | 0 | TmpInst.addOperand(MCOp); |
1101 | | // Operand: Zm |
1102 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1103 | 0 | TmpInst.addOperand(MCOp); |
1104 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1105 | 0 | break; |
1106 | 0 | } |
1107 | 0 | case AArch64::GLD1W_D_UXTW: { |
1108 | 0 | MCInst TmpInst; |
1109 | 0 | MCOperand MCOp; |
1110 | 0 | TmpInst.setOpcode(AArch64::GLD1W_D_UXTW_REAL); |
1111 | | // Operand: Zt |
1112 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1113 | 0 | TmpInst.addOperand(MCOp); |
1114 | | // Operand: Pg |
1115 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1116 | 0 | TmpInst.addOperand(MCOp); |
1117 | | // Operand: Rn |
1118 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1119 | 0 | TmpInst.addOperand(MCOp); |
1120 | | // Operand: Zm |
1121 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1122 | 0 | TmpInst.addOperand(MCOp); |
1123 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1124 | 0 | break; |
1125 | 0 | } |
1126 | 0 | case AArch64::GLD1W_D_UXTW_SCALED: { |
1127 | 0 | MCInst TmpInst; |
1128 | 0 | MCOperand MCOp; |
1129 | 0 | TmpInst.setOpcode(AArch64::GLD1W_D_UXTW_SCALED_REAL); |
1130 | | // Operand: Zt |
1131 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1132 | 0 | TmpInst.addOperand(MCOp); |
1133 | | // Operand: Pg |
1134 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1135 | 0 | TmpInst.addOperand(MCOp); |
1136 | | // Operand: Rn |
1137 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1138 | 0 | TmpInst.addOperand(MCOp); |
1139 | | // Operand: Zm |
1140 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1141 | 0 | TmpInst.addOperand(MCOp); |
1142 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1143 | 0 | break; |
1144 | 0 | } |
1145 | 0 | case AArch64::GLD1W_IMM: { |
1146 | 0 | MCInst TmpInst; |
1147 | 0 | MCOperand MCOp; |
1148 | 0 | TmpInst.setOpcode(AArch64::GLD1W_IMM_REAL); |
1149 | | // Operand: Zt |
1150 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1151 | 0 | TmpInst.addOperand(MCOp); |
1152 | | // Operand: Pg |
1153 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1154 | 0 | TmpInst.addOperand(MCOp); |
1155 | | // Operand: Zn |
1156 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1157 | 0 | TmpInst.addOperand(MCOp); |
1158 | | // Operand: imm5 |
1159 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1160 | 0 | TmpInst.addOperand(MCOp); |
1161 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1162 | 0 | break; |
1163 | 0 | } |
1164 | 0 | case AArch64::GLD1W_SXTW: { |
1165 | 0 | MCInst TmpInst; |
1166 | 0 | MCOperand MCOp; |
1167 | 0 | TmpInst.setOpcode(AArch64::GLD1W_SXTW_REAL); |
1168 | | // Operand: Zt |
1169 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1170 | 0 | TmpInst.addOperand(MCOp); |
1171 | | // Operand: Pg |
1172 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1173 | 0 | TmpInst.addOperand(MCOp); |
1174 | | // Operand: Rn |
1175 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1176 | 0 | TmpInst.addOperand(MCOp); |
1177 | | // Operand: Zm |
1178 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1179 | 0 | TmpInst.addOperand(MCOp); |
1180 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1181 | 0 | break; |
1182 | 0 | } |
1183 | 0 | case AArch64::GLD1W_SXTW_SCALED: { |
1184 | 0 | MCInst TmpInst; |
1185 | 0 | MCOperand MCOp; |
1186 | 0 | TmpInst.setOpcode(AArch64::GLD1W_SXTW_SCALED_REAL); |
1187 | | // Operand: Zt |
1188 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1189 | 0 | TmpInst.addOperand(MCOp); |
1190 | | // Operand: Pg |
1191 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1192 | 0 | TmpInst.addOperand(MCOp); |
1193 | | // Operand: Rn |
1194 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1195 | 0 | TmpInst.addOperand(MCOp); |
1196 | | // Operand: Zm |
1197 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1198 | 0 | TmpInst.addOperand(MCOp); |
1199 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1200 | 0 | break; |
1201 | 0 | } |
1202 | 0 | case AArch64::GLD1W_UXTW: { |
1203 | 0 | MCInst TmpInst; |
1204 | 0 | MCOperand MCOp; |
1205 | 0 | TmpInst.setOpcode(AArch64::GLD1W_UXTW_REAL); |
1206 | | // Operand: Zt |
1207 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1208 | 0 | TmpInst.addOperand(MCOp); |
1209 | | // Operand: Pg |
1210 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1211 | 0 | TmpInst.addOperand(MCOp); |
1212 | | // Operand: Rn |
1213 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1214 | 0 | TmpInst.addOperand(MCOp); |
1215 | | // Operand: Zm |
1216 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1217 | 0 | TmpInst.addOperand(MCOp); |
1218 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1219 | 0 | break; |
1220 | 0 | } |
1221 | 0 | case AArch64::GLD1W_UXTW_SCALED: { |
1222 | 0 | MCInst TmpInst; |
1223 | 0 | MCOperand MCOp; |
1224 | 0 | TmpInst.setOpcode(AArch64::GLD1W_UXTW_SCALED_REAL); |
1225 | | // Operand: Zt |
1226 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1227 | 0 | TmpInst.addOperand(MCOp); |
1228 | | // Operand: Pg |
1229 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1230 | 0 | TmpInst.addOperand(MCOp); |
1231 | | // Operand: Rn |
1232 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1233 | 0 | TmpInst.addOperand(MCOp); |
1234 | | // Operand: Zm |
1235 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1236 | 0 | TmpInst.addOperand(MCOp); |
1237 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1238 | 0 | break; |
1239 | 0 | } |
1240 | 0 | case AArch64::GLDFF1B_D: { |
1241 | 0 | MCInst TmpInst; |
1242 | 0 | MCOperand MCOp; |
1243 | 0 | TmpInst.setOpcode(AArch64::GLDFF1B_D_REAL); |
1244 | | // Operand: Zt |
1245 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1246 | 0 | TmpInst.addOperand(MCOp); |
1247 | | // Operand: Pg |
1248 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1249 | 0 | TmpInst.addOperand(MCOp); |
1250 | | // Operand: Rn |
1251 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1252 | 0 | TmpInst.addOperand(MCOp); |
1253 | | // Operand: Zm |
1254 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1255 | 0 | TmpInst.addOperand(MCOp); |
1256 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1257 | 0 | break; |
1258 | 0 | } |
1259 | 0 | case AArch64::GLDFF1B_D_IMM: { |
1260 | 0 | MCInst TmpInst; |
1261 | 0 | MCOperand MCOp; |
1262 | 0 | TmpInst.setOpcode(AArch64::GLDFF1B_D_IMM_REAL); |
1263 | | // Operand: Zt |
1264 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1265 | 0 | TmpInst.addOperand(MCOp); |
1266 | | // Operand: Pg |
1267 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1268 | 0 | TmpInst.addOperand(MCOp); |
1269 | | // Operand: Zn |
1270 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1271 | 0 | TmpInst.addOperand(MCOp); |
1272 | | // Operand: imm5 |
1273 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1274 | 0 | TmpInst.addOperand(MCOp); |
1275 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1276 | 0 | break; |
1277 | 0 | } |
1278 | 0 | case AArch64::GLDFF1B_D_SXTW: { |
1279 | 0 | MCInst TmpInst; |
1280 | 0 | MCOperand MCOp; |
1281 | 0 | TmpInst.setOpcode(AArch64::GLDFF1B_D_SXTW_REAL); |
1282 | | // Operand: Zt |
1283 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1284 | 0 | TmpInst.addOperand(MCOp); |
1285 | | // Operand: Pg |
1286 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1287 | 0 | TmpInst.addOperand(MCOp); |
1288 | | // Operand: Rn |
1289 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1290 | 0 | TmpInst.addOperand(MCOp); |
1291 | | // Operand: Zm |
1292 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1293 | 0 | TmpInst.addOperand(MCOp); |
1294 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1295 | 0 | break; |
1296 | 0 | } |
1297 | 0 | case AArch64::GLDFF1B_D_UXTW: { |
1298 | 0 | MCInst TmpInst; |
1299 | 0 | MCOperand MCOp; |
1300 | 0 | TmpInst.setOpcode(AArch64::GLDFF1B_D_UXTW_REAL); |
1301 | | // Operand: Zt |
1302 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1303 | 0 | TmpInst.addOperand(MCOp); |
1304 | | // Operand: Pg |
1305 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1306 | 0 | TmpInst.addOperand(MCOp); |
1307 | | // Operand: Rn |
1308 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1309 | 0 | TmpInst.addOperand(MCOp); |
1310 | | // Operand: Zm |
1311 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1312 | 0 | TmpInst.addOperand(MCOp); |
1313 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1314 | 0 | break; |
1315 | 0 | } |
1316 | 0 | case AArch64::GLDFF1B_S_IMM: { |
1317 | 0 | MCInst TmpInst; |
1318 | 0 | MCOperand MCOp; |
1319 | 0 | TmpInst.setOpcode(AArch64::GLDFF1B_S_IMM_REAL); |
1320 | | // Operand: Zt |
1321 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1322 | 0 | TmpInst.addOperand(MCOp); |
1323 | | // Operand: Pg |
1324 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1325 | 0 | TmpInst.addOperand(MCOp); |
1326 | | // Operand: Zn |
1327 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1328 | 0 | TmpInst.addOperand(MCOp); |
1329 | | // Operand: imm5 |
1330 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1331 | 0 | TmpInst.addOperand(MCOp); |
1332 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1333 | 0 | break; |
1334 | 0 | } |
1335 | 0 | case AArch64::GLDFF1B_S_SXTW: { |
1336 | 0 | MCInst TmpInst; |
1337 | 0 | MCOperand MCOp; |
1338 | 0 | TmpInst.setOpcode(AArch64::GLDFF1B_S_SXTW_REAL); |
1339 | | // Operand: Zt |
1340 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1341 | 0 | TmpInst.addOperand(MCOp); |
1342 | | // Operand: Pg |
1343 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1344 | 0 | TmpInst.addOperand(MCOp); |
1345 | | // Operand: Rn |
1346 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1347 | 0 | TmpInst.addOperand(MCOp); |
1348 | | // Operand: Zm |
1349 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1350 | 0 | TmpInst.addOperand(MCOp); |
1351 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1352 | 0 | break; |
1353 | 0 | } |
1354 | 0 | case AArch64::GLDFF1B_S_UXTW: { |
1355 | 0 | MCInst TmpInst; |
1356 | 0 | MCOperand MCOp; |
1357 | 0 | TmpInst.setOpcode(AArch64::GLDFF1B_S_UXTW_REAL); |
1358 | | // Operand: Zt |
1359 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1360 | 0 | TmpInst.addOperand(MCOp); |
1361 | | // Operand: Pg |
1362 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1363 | 0 | TmpInst.addOperand(MCOp); |
1364 | | // Operand: Rn |
1365 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1366 | 0 | TmpInst.addOperand(MCOp); |
1367 | | // Operand: Zm |
1368 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1369 | 0 | TmpInst.addOperand(MCOp); |
1370 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1371 | 0 | break; |
1372 | 0 | } |
1373 | 0 | case AArch64::GLDFF1D: { |
1374 | 0 | MCInst TmpInst; |
1375 | 0 | MCOperand MCOp; |
1376 | 0 | TmpInst.setOpcode(AArch64::GLDFF1D_REAL); |
1377 | | // Operand: Zt |
1378 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1379 | 0 | TmpInst.addOperand(MCOp); |
1380 | | // Operand: Pg |
1381 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1382 | 0 | TmpInst.addOperand(MCOp); |
1383 | | // Operand: Rn |
1384 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1385 | 0 | TmpInst.addOperand(MCOp); |
1386 | | // Operand: Zm |
1387 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1388 | 0 | TmpInst.addOperand(MCOp); |
1389 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1390 | 0 | break; |
1391 | 0 | } |
1392 | 0 | case AArch64::GLDFF1D_IMM: { |
1393 | 0 | MCInst TmpInst; |
1394 | 0 | MCOperand MCOp; |
1395 | 0 | TmpInst.setOpcode(AArch64::GLDFF1D_IMM_REAL); |
1396 | | // Operand: Zt |
1397 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1398 | 0 | TmpInst.addOperand(MCOp); |
1399 | | // Operand: Pg |
1400 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1401 | 0 | TmpInst.addOperand(MCOp); |
1402 | | // Operand: Zn |
1403 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1404 | 0 | TmpInst.addOperand(MCOp); |
1405 | | // Operand: imm5 |
1406 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1407 | 0 | TmpInst.addOperand(MCOp); |
1408 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1409 | 0 | break; |
1410 | 0 | } |
1411 | 0 | case AArch64::GLDFF1D_SCALED: { |
1412 | 0 | MCInst TmpInst; |
1413 | 0 | MCOperand MCOp; |
1414 | 0 | TmpInst.setOpcode(AArch64::GLDFF1D_SCALED_REAL); |
1415 | | // Operand: Zt |
1416 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1417 | 0 | TmpInst.addOperand(MCOp); |
1418 | | // Operand: Pg |
1419 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1420 | 0 | TmpInst.addOperand(MCOp); |
1421 | | // Operand: Rn |
1422 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1423 | 0 | TmpInst.addOperand(MCOp); |
1424 | | // Operand: Zm |
1425 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1426 | 0 | TmpInst.addOperand(MCOp); |
1427 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1428 | 0 | break; |
1429 | 0 | } |
1430 | 0 | case AArch64::GLDFF1D_SXTW: { |
1431 | 0 | MCInst TmpInst; |
1432 | 0 | MCOperand MCOp; |
1433 | 0 | TmpInst.setOpcode(AArch64::GLDFF1D_SXTW_REAL); |
1434 | | // Operand: Zt |
1435 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1436 | 0 | TmpInst.addOperand(MCOp); |
1437 | | // Operand: Pg |
1438 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1439 | 0 | TmpInst.addOperand(MCOp); |
1440 | | // Operand: Rn |
1441 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1442 | 0 | TmpInst.addOperand(MCOp); |
1443 | | // Operand: Zm |
1444 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1445 | 0 | TmpInst.addOperand(MCOp); |
1446 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1447 | 0 | break; |
1448 | 0 | } |
1449 | 0 | case AArch64::GLDFF1D_SXTW_SCALED: { |
1450 | 0 | MCInst TmpInst; |
1451 | 0 | MCOperand MCOp; |
1452 | 0 | TmpInst.setOpcode(AArch64::GLDFF1D_SXTW_SCALED_REAL); |
1453 | | // Operand: Zt |
1454 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1455 | 0 | TmpInst.addOperand(MCOp); |
1456 | | // Operand: Pg |
1457 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1458 | 0 | TmpInst.addOperand(MCOp); |
1459 | | // Operand: Rn |
1460 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1461 | 0 | TmpInst.addOperand(MCOp); |
1462 | | // Operand: Zm |
1463 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1464 | 0 | TmpInst.addOperand(MCOp); |
1465 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1466 | 0 | break; |
1467 | 0 | } |
1468 | 0 | case AArch64::GLDFF1D_UXTW: { |
1469 | 0 | MCInst TmpInst; |
1470 | 0 | MCOperand MCOp; |
1471 | 0 | TmpInst.setOpcode(AArch64::GLDFF1D_UXTW_REAL); |
1472 | | // Operand: Zt |
1473 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1474 | 0 | TmpInst.addOperand(MCOp); |
1475 | | // Operand: Pg |
1476 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1477 | 0 | TmpInst.addOperand(MCOp); |
1478 | | // Operand: Rn |
1479 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1480 | 0 | TmpInst.addOperand(MCOp); |
1481 | | // Operand: Zm |
1482 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1483 | 0 | TmpInst.addOperand(MCOp); |
1484 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1485 | 0 | break; |
1486 | 0 | } |
1487 | 0 | case AArch64::GLDFF1D_UXTW_SCALED: { |
1488 | 0 | MCInst TmpInst; |
1489 | 0 | MCOperand MCOp; |
1490 | 0 | TmpInst.setOpcode(AArch64::GLDFF1D_UXTW_SCALED_REAL); |
1491 | | // Operand: Zt |
1492 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1493 | 0 | TmpInst.addOperand(MCOp); |
1494 | | // Operand: Pg |
1495 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1496 | 0 | TmpInst.addOperand(MCOp); |
1497 | | // Operand: Rn |
1498 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1499 | 0 | TmpInst.addOperand(MCOp); |
1500 | | // Operand: Zm |
1501 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1502 | 0 | TmpInst.addOperand(MCOp); |
1503 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1504 | 0 | break; |
1505 | 0 | } |
1506 | 0 | case AArch64::GLDFF1H_D: { |
1507 | 0 | MCInst TmpInst; |
1508 | 0 | MCOperand MCOp; |
1509 | 0 | TmpInst.setOpcode(AArch64::GLDFF1H_D_REAL); |
1510 | | // Operand: Zt |
1511 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1512 | 0 | TmpInst.addOperand(MCOp); |
1513 | | // Operand: Pg |
1514 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1515 | 0 | TmpInst.addOperand(MCOp); |
1516 | | // Operand: Rn |
1517 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1518 | 0 | TmpInst.addOperand(MCOp); |
1519 | | // Operand: Zm |
1520 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1521 | 0 | TmpInst.addOperand(MCOp); |
1522 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1523 | 0 | break; |
1524 | 0 | } |
1525 | 0 | case AArch64::GLDFF1H_D_IMM: { |
1526 | 0 | MCInst TmpInst; |
1527 | 0 | MCOperand MCOp; |
1528 | 0 | TmpInst.setOpcode(AArch64::GLDFF1H_D_IMM_REAL); |
1529 | | // Operand: Zt |
1530 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1531 | 0 | TmpInst.addOperand(MCOp); |
1532 | | // Operand: Pg |
1533 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1534 | 0 | TmpInst.addOperand(MCOp); |
1535 | | // Operand: Zn |
1536 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1537 | 0 | TmpInst.addOperand(MCOp); |
1538 | | // Operand: imm5 |
1539 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1540 | 0 | TmpInst.addOperand(MCOp); |
1541 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1542 | 0 | break; |
1543 | 0 | } |
1544 | 0 | case AArch64::GLDFF1H_D_SCALED: { |
1545 | 0 | MCInst TmpInst; |
1546 | 0 | MCOperand MCOp; |
1547 | 0 | TmpInst.setOpcode(AArch64::GLDFF1H_D_SCALED_REAL); |
1548 | | // Operand: Zt |
1549 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1550 | 0 | TmpInst.addOperand(MCOp); |
1551 | | // Operand: Pg |
1552 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1553 | 0 | TmpInst.addOperand(MCOp); |
1554 | | // Operand: Rn |
1555 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1556 | 0 | TmpInst.addOperand(MCOp); |
1557 | | // Operand: Zm |
1558 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1559 | 0 | TmpInst.addOperand(MCOp); |
1560 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1561 | 0 | break; |
1562 | 0 | } |
1563 | 0 | case AArch64::GLDFF1H_D_SXTW: { |
1564 | 0 | MCInst TmpInst; |
1565 | 0 | MCOperand MCOp; |
1566 | 0 | TmpInst.setOpcode(AArch64::GLDFF1H_D_SXTW_REAL); |
1567 | | // Operand: Zt |
1568 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1569 | 0 | TmpInst.addOperand(MCOp); |
1570 | | // Operand: Pg |
1571 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1572 | 0 | TmpInst.addOperand(MCOp); |
1573 | | // Operand: Rn |
1574 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1575 | 0 | TmpInst.addOperand(MCOp); |
1576 | | // Operand: Zm |
1577 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1578 | 0 | TmpInst.addOperand(MCOp); |
1579 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1580 | 0 | break; |
1581 | 0 | } |
1582 | 0 | case AArch64::GLDFF1H_D_SXTW_SCALED: { |
1583 | 0 | MCInst TmpInst; |
1584 | 0 | MCOperand MCOp; |
1585 | 0 | TmpInst.setOpcode(AArch64::GLDFF1H_D_SXTW_SCALED_REAL); |
1586 | | // Operand: Zt |
1587 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1588 | 0 | TmpInst.addOperand(MCOp); |
1589 | | // Operand: Pg |
1590 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1591 | 0 | TmpInst.addOperand(MCOp); |
1592 | | // Operand: Rn |
1593 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1594 | 0 | TmpInst.addOperand(MCOp); |
1595 | | // Operand: Zm |
1596 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1597 | 0 | TmpInst.addOperand(MCOp); |
1598 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1599 | 0 | break; |
1600 | 0 | } |
1601 | 0 | case AArch64::GLDFF1H_D_UXTW: { |
1602 | 0 | MCInst TmpInst; |
1603 | 0 | MCOperand MCOp; |
1604 | 0 | TmpInst.setOpcode(AArch64::GLDFF1H_D_UXTW_REAL); |
1605 | | // Operand: Zt |
1606 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1607 | 0 | TmpInst.addOperand(MCOp); |
1608 | | // Operand: Pg |
1609 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1610 | 0 | TmpInst.addOperand(MCOp); |
1611 | | // Operand: Rn |
1612 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1613 | 0 | TmpInst.addOperand(MCOp); |
1614 | | // Operand: Zm |
1615 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1616 | 0 | TmpInst.addOperand(MCOp); |
1617 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1618 | 0 | break; |
1619 | 0 | } |
1620 | 0 | case AArch64::GLDFF1H_D_UXTW_SCALED: { |
1621 | 0 | MCInst TmpInst; |
1622 | 0 | MCOperand MCOp; |
1623 | 0 | TmpInst.setOpcode(AArch64::GLDFF1H_D_UXTW_SCALED_REAL); |
1624 | | // Operand: Zt |
1625 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1626 | 0 | TmpInst.addOperand(MCOp); |
1627 | | // Operand: Pg |
1628 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1629 | 0 | TmpInst.addOperand(MCOp); |
1630 | | // Operand: Rn |
1631 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1632 | 0 | TmpInst.addOperand(MCOp); |
1633 | | // Operand: Zm |
1634 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1635 | 0 | TmpInst.addOperand(MCOp); |
1636 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1637 | 0 | break; |
1638 | 0 | } |
1639 | 0 | case AArch64::GLDFF1H_S_IMM: { |
1640 | 0 | MCInst TmpInst; |
1641 | 0 | MCOperand MCOp; |
1642 | 0 | TmpInst.setOpcode(AArch64::GLDFF1H_S_IMM_REAL); |
1643 | | // Operand: Zt |
1644 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1645 | 0 | TmpInst.addOperand(MCOp); |
1646 | | // Operand: Pg |
1647 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1648 | 0 | TmpInst.addOperand(MCOp); |
1649 | | // Operand: Zn |
1650 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1651 | 0 | TmpInst.addOperand(MCOp); |
1652 | | // Operand: imm5 |
1653 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1654 | 0 | TmpInst.addOperand(MCOp); |
1655 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1656 | 0 | break; |
1657 | 0 | } |
1658 | 0 | case AArch64::GLDFF1H_S_SXTW: { |
1659 | 0 | MCInst TmpInst; |
1660 | 0 | MCOperand MCOp; |
1661 | 0 | TmpInst.setOpcode(AArch64::GLDFF1H_S_SXTW_REAL); |
1662 | | // Operand: Zt |
1663 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1664 | 0 | TmpInst.addOperand(MCOp); |
1665 | | // Operand: Pg |
1666 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1667 | 0 | TmpInst.addOperand(MCOp); |
1668 | | // Operand: Rn |
1669 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1670 | 0 | TmpInst.addOperand(MCOp); |
1671 | | // Operand: Zm |
1672 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1673 | 0 | TmpInst.addOperand(MCOp); |
1674 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1675 | 0 | break; |
1676 | 0 | } |
1677 | 0 | case AArch64::GLDFF1H_S_SXTW_SCALED: { |
1678 | 0 | MCInst TmpInst; |
1679 | 0 | MCOperand MCOp; |
1680 | 0 | TmpInst.setOpcode(AArch64::GLDFF1H_S_SXTW_SCALED_REAL); |
1681 | | // Operand: Zt |
1682 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1683 | 0 | TmpInst.addOperand(MCOp); |
1684 | | // Operand: Pg |
1685 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1686 | 0 | TmpInst.addOperand(MCOp); |
1687 | | // Operand: Rn |
1688 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1689 | 0 | TmpInst.addOperand(MCOp); |
1690 | | // Operand: Zm |
1691 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1692 | 0 | TmpInst.addOperand(MCOp); |
1693 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1694 | 0 | break; |
1695 | 0 | } |
1696 | 0 | case AArch64::GLDFF1H_S_UXTW: { |
1697 | 0 | MCInst TmpInst; |
1698 | 0 | MCOperand MCOp; |
1699 | 0 | TmpInst.setOpcode(AArch64::GLDFF1H_S_UXTW_REAL); |
1700 | | // Operand: Zt |
1701 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1702 | 0 | TmpInst.addOperand(MCOp); |
1703 | | // Operand: Pg |
1704 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1705 | 0 | TmpInst.addOperand(MCOp); |
1706 | | // Operand: Rn |
1707 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1708 | 0 | TmpInst.addOperand(MCOp); |
1709 | | // Operand: Zm |
1710 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1711 | 0 | TmpInst.addOperand(MCOp); |
1712 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1713 | 0 | break; |
1714 | 0 | } |
1715 | 0 | case AArch64::GLDFF1H_S_UXTW_SCALED: { |
1716 | 0 | MCInst TmpInst; |
1717 | 0 | MCOperand MCOp; |
1718 | 0 | TmpInst.setOpcode(AArch64::GLDFF1H_S_UXTW_SCALED_REAL); |
1719 | | // Operand: Zt |
1720 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1721 | 0 | TmpInst.addOperand(MCOp); |
1722 | | // Operand: Pg |
1723 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1724 | 0 | TmpInst.addOperand(MCOp); |
1725 | | // Operand: Rn |
1726 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1727 | 0 | TmpInst.addOperand(MCOp); |
1728 | | // Operand: Zm |
1729 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1730 | 0 | TmpInst.addOperand(MCOp); |
1731 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1732 | 0 | break; |
1733 | 0 | } |
1734 | 0 | case AArch64::GLDFF1SB_D: { |
1735 | 0 | MCInst TmpInst; |
1736 | 0 | MCOperand MCOp; |
1737 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SB_D_REAL); |
1738 | | // Operand: Zt |
1739 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1740 | 0 | TmpInst.addOperand(MCOp); |
1741 | | // Operand: Pg |
1742 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1743 | 0 | TmpInst.addOperand(MCOp); |
1744 | | // Operand: Rn |
1745 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1746 | 0 | TmpInst.addOperand(MCOp); |
1747 | | // Operand: Zm |
1748 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1749 | 0 | TmpInst.addOperand(MCOp); |
1750 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1751 | 0 | break; |
1752 | 0 | } |
1753 | 0 | case AArch64::GLDFF1SB_D_IMM: { |
1754 | 0 | MCInst TmpInst; |
1755 | 0 | MCOperand MCOp; |
1756 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SB_D_IMM_REAL); |
1757 | | // Operand: Zt |
1758 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1759 | 0 | TmpInst.addOperand(MCOp); |
1760 | | // Operand: Pg |
1761 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1762 | 0 | TmpInst.addOperand(MCOp); |
1763 | | // Operand: Zn |
1764 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1765 | 0 | TmpInst.addOperand(MCOp); |
1766 | | // Operand: imm5 |
1767 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1768 | 0 | TmpInst.addOperand(MCOp); |
1769 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1770 | 0 | break; |
1771 | 0 | } |
1772 | 0 | case AArch64::GLDFF1SB_D_SXTW: { |
1773 | 0 | MCInst TmpInst; |
1774 | 0 | MCOperand MCOp; |
1775 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SB_D_SXTW_REAL); |
1776 | | // Operand: Zt |
1777 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1778 | 0 | TmpInst.addOperand(MCOp); |
1779 | | // Operand: Pg |
1780 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1781 | 0 | TmpInst.addOperand(MCOp); |
1782 | | // Operand: Rn |
1783 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1784 | 0 | TmpInst.addOperand(MCOp); |
1785 | | // Operand: Zm |
1786 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1787 | 0 | TmpInst.addOperand(MCOp); |
1788 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1789 | 0 | break; |
1790 | 0 | } |
1791 | 0 | case AArch64::GLDFF1SB_D_UXTW: { |
1792 | 0 | MCInst TmpInst; |
1793 | 0 | MCOperand MCOp; |
1794 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SB_D_UXTW_REAL); |
1795 | | // Operand: Zt |
1796 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1797 | 0 | TmpInst.addOperand(MCOp); |
1798 | | // Operand: Pg |
1799 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1800 | 0 | TmpInst.addOperand(MCOp); |
1801 | | // Operand: Rn |
1802 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1803 | 0 | TmpInst.addOperand(MCOp); |
1804 | | // Operand: Zm |
1805 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1806 | 0 | TmpInst.addOperand(MCOp); |
1807 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1808 | 0 | break; |
1809 | 0 | } |
1810 | 0 | case AArch64::GLDFF1SB_S_IMM: { |
1811 | 0 | MCInst TmpInst; |
1812 | 0 | MCOperand MCOp; |
1813 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SB_S_IMM_REAL); |
1814 | | // Operand: Zt |
1815 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1816 | 0 | TmpInst.addOperand(MCOp); |
1817 | | // Operand: Pg |
1818 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1819 | 0 | TmpInst.addOperand(MCOp); |
1820 | | // Operand: Zn |
1821 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1822 | 0 | TmpInst.addOperand(MCOp); |
1823 | | // Operand: imm5 |
1824 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1825 | 0 | TmpInst.addOperand(MCOp); |
1826 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1827 | 0 | break; |
1828 | 0 | } |
1829 | 0 | case AArch64::GLDFF1SB_S_SXTW: { |
1830 | 0 | MCInst TmpInst; |
1831 | 0 | MCOperand MCOp; |
1832 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SB_S_SXTW_REAL); |
1833 | | // Operand: Zt |
1834 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1835 | 0 | TmpInst.addOperand(MCOp); |
1836 | | // Operand: Pg |
1837 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1838 | 0 | TmpInst.addOperand(MCOp); |
1839 | | // Operand: Rn |
1840 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1841 | 0 | TmpInst.addOperand(MCOp); |
1842 | | // Operand: Zm |
1843 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1844 | 0 | TmpInst.addOperand(MCOp); |
1845 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1846 | 0 | break; |
1847 | 0 | } |
1848 | 0 | case AArch64::GLDFF1SB_S_UXTW: { |
1849 | 0 | MCInst TmpInst; |
1850 | 0 | MCOperand MCOp; |
1851 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SB_S_UXTW_REAL); |
1852 | | // Operand: Zt |
1853 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1854 | 0 | TmpInst.addOperand(MCOp); |
1855 | | // Operand: Pg |
1856 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1857 | 0 | TmpInst.addOperand(MCOp); |
1858 | | // Operand: Rn |
1859 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1860 | 0 | TmpInst.addOperand(MCOp); |
1861 | | // Operand: Zm |
1862 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1863 | 0 | TmpInst.addOperand(MCOp); |
1864 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1865 | 0 | break; |
1866 | 0 | } |
1867 | 0 | case AArch64::GLDFF1SH_D: { |
1868 | 0 | MCInst TmpInst; |
1869 | 0 | MCOperand MCOp; |
1870 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SH_D_REAL); |
1871 | | // Operand: Zt |
1872 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1873 | 0 | TmpInst.addOperand(MCOp); |
1874 | | // Operand: Pg |
1875 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1876 | 0 | TmpInst.addOperand(MCOp); |
1877 | | // Operand: Rn |
1878 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1879 | 0 | TmpInst.addOperand(MCOp); |
1880 | | // Operand: Zm |
1881 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1882 | 0 | TmpInst.addOperand(MCOp); |
1883 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1884 | 0 | break; |
1885 | 0 | } |
1886 | 0 | case AArch64::GLDFF1SH_D_IMM: { |
1887 | 0 | MCInst TmpInst; |
1888 | 0 | MCOperand MCOp; |
1889 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SH_D_IMM_REAL); |
1890 | | // Operand: Zt |
1891 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1892 | 0 | TmpInst.addOperand(MCOp); |
1893 | | // Operand: Pg |
1894 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1895 | 0 | TmpInst.addOperand(MCOp); |
1896 | | // Operand: Zn |
1897 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1898 | 0 | TmpInst.addOperand(MCOp); |
1899 | | // Operand: imm5 |
1900 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1901 | 0 | TmpInst.addOperand(MCOp); |
1902 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1903 | 0 | break; |
1904 | 0 | } |
1905 | 0 | case AArch64::GLDFF1SH_D_SCALED: { |
1906 | 0 | MCInst TmpInst; |
1907 | 0 | MCOperand MCOp; |
1908 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SH_D_SCALED_REAL); |
1909 | | // Operand: Zt |
1910 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1911 | 0 | TmpInst.addOperand(MCOp); |
1912 | | // Operand: Pg |
1913 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1914 | 0 | TmpInst.addOperand(MCOp); |
1915 | | // Operand: Rn |
1916 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1917 | 0 | TmpInst.addOperand(MCOp); |
1918 | | // Operand: Zm |
1919 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1920 | 0 | TmpInst.addOperand(MCOp); |
1921 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1922 | 0 | break; |
1923 | 0 | } |
1924 | 0 | case AArch64::GLDFF1SH_D_SXTW: { |
1925 | 0 | MCInst TmpInst; |
1926 | 0 | MCOperand MCOp; |
1927 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SH_D_SXTW_REAL); |
1928 | | // Operand: Zt |
1929 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1930 | 0 | TmpInst.addOperand(MCOp); |
1931 | | // Operand: Pg |
1932 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1933 | 0 | TmpInst.addOperand(MCOp); |
1934 | | // Operand: Rn |
1935 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1936 | 0 | TmpInst.addOperand(MCOp); |
1937 | | // Operand: Zm |
1938 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1939 | 0 | TmpInst.addOperand(MCOp); |
1940 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1941 | 0 | break; |
1942 | 0 | } |
1943 | 0 | case AArch64::GLDFF1SH_D_SXTW_SCALED: { |
1944 | 0 | MCInst TmpInst; |
1945 | 0 | MCOperand MCOp; |
1946 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SH_D_SXTW_SCALED_REAL); |
1947 | | // Operand: Zt |
1948 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1949 | 0 | TmpInst.addOperand(MCOp); |
1950 | | // Operand: Pg |
1951 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1952 | 0 | TmpInst.addOperand(MCOp); |
1953 | | // Operand: Rn |
1954 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1955 | 0 | TmpInst.addOperand(MCOp); |
1956 | | // Operand: Zm |
1957 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1958 | 0 | TmpInst.addOperand(MCOp); |
1959 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1960 | 0 | break; |
1961 | 0 | } |
1962 | 0 | case AArch64::GLDFF1SH_D_UXTW: { |
1963 | 0 | MCInst TmpInst; |
1964 | 0 | MCOperand MCOp; |
1965 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SH_D_UXTW_REAL); |
1966 | | // Operand: Zt |
1967 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1968 | 0 | TmpInst.addOperand(MCOp); |
1969 | | // Operand: Pg |
1970 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1971 | 0 | TmpInst.addOperand(MCOp); |
1972 | | // Operand: Rn |
1973 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1974 | 0 | TmpInst.addOperand(MCOp); |
1975 | | // Operand: Zm |
1976 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1977 | 0 | TmpInst.addOperand(MCOp); |
1978 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1979 | 0 | break; |
1980 | 0 | } |
1981 | 0 | case AArch64::GLDFF1SH_D_UXTW_SCALED: { |
1982 | 0 | MCInst TmpInst; |
1983 | 0 | MCOperand MCOp; |
1984 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SH_D_UXTW_SCALED_REAL); |
1985 | | // Operand: Zt |
1986 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1987 | 0 | TmpInst.addOperand(MCOp); |
1988 | | // Operand: Pg |
1989 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1990 | 0 | TmpInst.addOperand(MCOp); |
1991 | | // Operand: Rn |
1992 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1993 | 0 | TmpInst.addOperand(MCOp); |
1994 | | // Operand: Zm |
1995 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
1996 | 0 | TmpInst.addOperand(MCOp); |
1997 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1998 | 0 | break; |
1999 | 0 | } |
2000 | 0 | case AArch64::GLDFF1SH_S_IMM: { |
2001 | 0 | MCInst TmpInst; |
2002 | 0 | MCOperand MCOp; |
2003 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SH_S_IMM_REAL); |
2004 | | // Operand: Zt |
2005 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2006 | 0 | TmpInst.addOperand(MCOp); |
2007 | | // Operand: Pg |
2008 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2009 | 0 | TmpInst.addOperand(MCOp); |
2010 | | // Operand: Zn |
2011 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2012 | 0 | TmpInst.addOperand(MCOp); |
2013 | | // Operand: imm5 |
2014 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2015 | 0 | TmpInst.addOperand(MCOp); |
2016 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2017 | 0 | break; |
2018 | 0 | } |
2019 | 0 | case AArch64::GLDFF1SH_S_SXTW: { |
2020 | 0 | MCInst TmpInst; |
2021 | 0 | MCOperand MCOp; |
2022 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SH_S_SXTW_REAL); |
2023 | | // Operand: Zt |
2024 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2025 | 0 | TmpInst.addOperand(MCOp); |
2026 | | // Operand: Pg |
2027 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2028 | 0 | TmpInst.addOperand(MCOp); |
2029 | | // Operand: Rn |
2030 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2031 | 0 | TmpInst.addOperand(MCOp); |
2032 | | // Operand: Zm |
2033 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2034 | 0 | TmpInst.addOperand(MCOp); |
2035 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2036 | 0 | break; |
2037 | 0 | } |
2038 | 0 | case AArch64::GLDFF1SH_S_SXTW_SCALED: { |
2039 | 0 | MCInst TmpInst; |
2040 | 0 | MCOperand MCOp; |
2041 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SH_S_SXTW_SCALED_REAL); |
2042 | | // Operand: Zt |
2043 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2044 | 0 | TmpInst.addOperand(MCOp); |
2045 | | // Operand: Pg |
2046 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2047 | 0 | TmpInst.addOperand(MCOp); |
2048 | | // Operand: Rn |
2049 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2050 | 0 | TmpInst.addOperand(MCOp); |
2051 | | // Operand: Zm |
2052 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2053 | 0 | TmpInst.addOperand(MCOp); |
2054 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2055 | 0 | break; |
2056 | 0 | } |
2057 | 0 | case AArch64::GLDFF1SH_S_UXTW: { |
2058 | 0 | MCInst TmpInst; |
2059 | 0 | MCOperand MCOp; |
2060 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SH_S_UXTW_REAL); |
2061 | | // Operand: Zt |
2062 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2063 | 0 | TmpInst.addOperand(MCOp); |
2064 | | // Operand: Pg |
2065 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2066 | 0 | TmpInst.addOperand(MCOp); |
2067 | | // Operand: Rn |
2068 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2069 | 0 | TmpInst.addOperand(MCOp); |
2070 | | // Operand: Zm |
2071 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2072 | 0 | TmpInst.addOperand(MCOp); |
2073 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2074 | 0 | break; |
2075 | 0 | } |
2076 | 0 | case AArch64::GLDFF1SH_S_UXTW_SCALED: { |
2077 | 0 | MCInst TmpInst; |
2078 | 0 | MCOperand MCOp; |
2079 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SH_S_UXTW_SCALED_REAL); |
2080 | | // Operand: Zt |
2081 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2082 | 0 | TmpInst.addOperand(MCOp); |
2083 | | // Operand: Pg |
2084 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2085 | 0 | TmpInst.addOperand(MCOp); |
2086 | | // Operand: Rn |
2087 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2088 | 0 | TmpInst.addOperand(MCOp); |
2089 | | // Operand: Zm |
2090 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2091 | 0 | TmpInst.addOperand(MCOp); |
2092 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2093 | 0 | break; |
2094 | 0 | } |
2095 | 0 | case AArch64::GLDFF1SW_D: { |
2096 | 0 | MCInst TmpInst; |
2097 | 0 | MCOperand MCOp; |
2098 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SW_D_REAL); |
2099 | | // Operand: Zt |
2100 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2101 | 0 | TmpInst.addOperand(MCOp); |
2102 | | // Operand: Pg |
2103 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2104 | 0 | TmpInst.addOperand(MCOp); |
2105 | | // Operand: Rn |
2106 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2107 | 0 | TmpInst.addOperand(MCOp); |
2108 | | // Operand: Zm |
2109 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2110 | 0 | TmpInst.addOperand(MCOp); |
2111 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2112 | 0 | break; |
2113 | 0 | } |
2114 | 0 | case AArch64::GLDFF1SW_D_IMM: { |
2115 | 0 | MCInst TmpInst; |
2116 | 0 | MCOperand MCOp; |
2117 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SW_D_IMM_REAL); |
2118 | | // Operand: Zt |
2119 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2120 | 0 | TmpInst.addOperand(MCOp); |
2121 | | // Operand: Pg |
2122 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2123 | 0 | TmpInst.addOperand(MCOp); |
2124 | | // Operand: Zn |
2125 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2126 | 0 | TmpInst.addOperand(MCOp); |
2127 | | // Operand: imm5 |
2128 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2129 | 0 | TmpInst.addOperand(MCOp); |
2130 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2131 | 0 | break; |
2132 | 0 | } |
2133 | 0 | case AArch64::GLDFF1SW_D_SCALED: { |
2134 | 0 | MCInst TmpInst; |
2135 | 0 | MCOperand MCOp; |
2136 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SW_D_SCALED_REAL); |
2137 | | // Operand: Zt |
2138 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2139 | 0 | TmpInst.addOperand(MCOp); |
2140 | | // Operand: Pg |
2141 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2142 | 0 | TmpInst.addOperand(MCOp); |
2143 | | // Operand: Rn |
2144 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2145 | 0 | TmpInst.addOperand(MCOp); |
2146 | | // Operand: Zm |
2147 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2148 | 0 | TmpInst.addOperand(MCOp); |
2149 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2150 | 0 | break; |
2151 | 0 | } |
2152 | 0 | case AArch64::GLDFF1SW_D_SXTW: { |
2153 | 0 | MCInst TmpInst; |
2154 | 0 | MCOperand MCOp; |
2155 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SW_D_SXTW_REAL); |
2156 | | // Operand: Zt |
2157 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2158 | 0 | TmpInst.addOperand(MCOp); |
2159 | | // Operand: Pg |
2160 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2161 | 0 | TmpInst.addOperand(MCOp); |
2162 | | // Operand: Rn |
2163 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2164 | 0 | TmpInst.addOperand(MCOp); |
2165 | | // Operand: Zm |
2166 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2167 | 0 | TmpInst.addOperand(MCOp); |
2168 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2169 | 0 | break; |
2170 | 0 | } |
2171 | 0 | case AArch64::GLDFF1SW_D_SXTW_SCALED: { |
2172 | 0 | MCInst TmpInst; |
2173 | 0 | MCOperand MCOp; |
2174 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SW_D_SXTW_SCALED_REAL); |
2175 | | // Operand: Zt |
2176 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2177 | 0 | TmpInst.addOperand(MCOp); |
2178 | | // Operand: Pg |
2179 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2180 | 0 | TmpInst.addOperand(MCOp); |
2181 | | // Operand: Rn |
2182 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2183 | 0 | TmpInst.addOperand(MCOp); |
2184 | | // Operand: Zm |
2185 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2186 | 0 | TmpInst.addOperand(MCOp); |
2187 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2188 | 0 | break; |
2189 | 0 | } |
2190 | 0 | case AArch64::GLDFF1SW_D_UXTW: { |
2191 | 0 | MCInst TmpInst; |
2192 | 0 | MCOperand MCOp; |
2193 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SW_D_UXTW_REAL); |
2194 | | // Operand: Zt |
2195 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2196 | 0 | TmpInst.addOperand(MCOp); |
2197 | | // Operand: Pg |
2198 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2199 | 0 | TmpInst.addOperand(MCOp); |
2200 | | // Operand: Rn |
2201 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2202 | 0 | TmpInst.addOperand(MCOp); |
2203 | | // Operand: Zm |
2204 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2205 | 0 | TmpInst.addOperand(MCOp); |
2206 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2207 | 0 | break; |
2208 | 0 | } |
2209 | 0 | case AArch64::GLDFF1SW_D_UXTW_SCALED: { |
2210 | 0 | MCInst TmpInst; |
2211 | 0 | MCOperand MCOp; |
2212 | 0 | TmpInst.setOpcode(AArch64::GLDFF1SW_D_UXTW_SCALED_REAL); |
2213 | | // Operand: Zt |
2214 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2215 | 0 | TmpInst.addOperand(MCOp); |
2216 | | // Operand: Pg |
2217 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2218 | 0 | TmpInst.addOperand(MCOp); |
2219 | | // Operand: Rn |
2220 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2221 | 0 | TmpInst.addOperand(MCOp); |
2222 | | // Operand: Zm |
2223 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2224 | 0 | TmpInst.addOperand(MCOp); |
2225 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2226 | 0 | break; |
2227 | 0 | } |
2228 | 0 | case AArch64::GLDFF1W_D: { |
2229 | 0 | MCInst TmpInst; |
2230 | 0 | MCOperand MCOp; |
2231 | 0 | TmpInst.setOpcode(AArch64::GLDFF1W_D_REAL); |
2232 | | // Operand: Zt |
2233 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2234 | 0 | TmpInst.addOperand(MCOp); |
2235 | | // Operand: Pg |
2236 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2237 | 0 | TmpInst.addOperand(MCOp); |
2238 | | // Operand: Rn |
2239 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2240 | 0 | TmpInst.addOperand(MCOp); |
2241 | | // Operand: Zm |
2242 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2243 | 0 | TmpInst.addOperand(MCOp); |
2244 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2245 | 0 | break; |
2246 | 0 | } |
2247 | 0 | case AArch64::GLDFF1W_D_IMM: { |
2248 | 0 | MCInst TmpInst; |
2249 | 0 | MCOperand MCOp; |
2250 | 0 | TmpInst.setOpcode(AArch64::GLDFF1W_D_IMM_REAL); |
2251 | | // Operand: Zt |
2252 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2253 | 0 | TmpInst.addOperand(MCOp); |
2254 | | // Operand: Pg |
2255 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2256 | 0 | TmpInst.addOperand(MCOp); |
2257 | | // Operand: Zn |
2258 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2259 | 0 | TmpInst.addOperand(MCOp); |
2260 | | // Operand: imm5 |
2261 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2262 | 0 | TmpInst.addOperand(MCOp); |
2263 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2264 | 0 | break; |
2265 | 0 | } |
2266 | 0 | case AArch64::GLDFF1W_D_SCALED: { |
2267 | 0 | MCInst TmpInst; |
2268 | 0 | MCOperand MCOp; |
2269 | 0 | TmpInst.setOpcode(AArch64::GLDFF1W_D_SCALED_REAL); |
2270 | | // Operand: Zt |
2271 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2272 | 0 | TmpInst.addOperand(MCOp); |
2273 | | // Operand: Pg |
2274 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2275 | 0 | TmpInst.addOperand(MCOp); |
2276 | | // Operand: Rn |
2277 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2278 | 0 | TmpInst.addOperand(MCOp); |
2279 | | // Operand: Zm |
2280 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2281 | 0 | TmpInst.addOperand(MCOp); |
2282 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2283 | 0 | break; |
2284 | 0 | } |
2285 | 0 | case AArch64::GLDFF1W_D_SXTW: { |
2286 | 0 | MCInst TmpInst; |
2287 | 0 | MCOperand MCOp; |
2288 | 0 | TmpInst.setOpcode(AArch64::GLDFF1W_D_SXTW_REAL); |
2289 | | // Operand: Zt |
2290 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2291 | 0 | TmpInst.addOperand(MCOp); |
2292 | | // Operand: Pg |
2293 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2294 | 0 | TmpInst.addOperand(MCOp); |
2295 | | // Operand: Rn |
2296 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2297 | 0 | TmpInst.addOperand(MCOp); |
2298 | | // Operand: Zm |
2299 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2300 | 0 | TmpInst.addOperand(MCOp); |
2301 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2302 | 0 | break; |
2303 | 0 | } |
2304 | 0 | case AArch64::GLDFF1W_D_SXTW_SCALED: { |
2305 | 0 | MCInst TmpInst; |
2306 | 0 | MCOperand MCOp; |
2307 | 0 | TmpInst.setOpcode(AArch64::GLDFF1W_D_SXTW_SCALED_REAL); |
2308 | | // Operand: Zt |
2309 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2310 | 0 | TmpInst.addOperand(MCOp); |
2311 | | // Operand: Pg |
2312 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2313 | 0 | TmpInst.addOperand(MCOp); |
2314 | | // Operand: Rn |
2315 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2316 | 0 | TmpInst.addOperand(MCOp); |
2317 | | // Operand: Zm |
2318 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2319 | 0 | TmpInst.addOperand(MCOp); |
2320 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2321 | 0 | break; |
2322 | 0 | } |
2323 | 0 | case AArch64::GLDFF1W_D_UXTW: { |
2324 | 0 | MCInst TmpInst; |
2325 | 0 | MCOperand MCOp; |
2326 | 0 | TmpInst.setOpcode(AArch64::GLDFF1W_D_UXTW_REAL); |
2327 | | // Operand: Zt |
2328 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2329 | 0 | TmpInst.addOperand(MCOp); |
2330 | | // Operand: Pg |
2331 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2332 | 0 | TmpInst.addOperand(MCOp); |
2333 | | // Operand: Rn |
2334 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2335 | 0 | TmpInst.addOperand(MCOp); |
2336 | | // Operand: Zm |
2337 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2338 | 0 | TmpInst.addOperand(MCOp); |
2339 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2340 | 0 | break; |
2341 | 0 | } |
2342 | 0 | case AArch64::GLDFF1W_D_UXTW_SCALED: { |
2343 | 0 | MCInst TmpInst; |
2344 | 0 | MCOperand MCOp; |
2345 | 0 | TmpInst.setOpcode(AArch64::GLDFF1W_D_UXTW_SCALED_REAL); |
2346 | | // Operand: Zt |
2347 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2348 | 0 | TmpInst.addOperand(MCOp); |
2349 | | // Operand: Pg |
2350 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2351 | 0 | TmpInst.addOperand(MCOp); |
2352 | | // Operand: Rn |
2353 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2354 | 0 | TmpInst.addOperand(MCOp); |
2355 | | // Operand: Zm |
2356 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2357 | 0 | TmpInst.addOperand(MCOp); |
2358 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2359 | 0 | break; |
2360 | 0 | } |
2361 | 0 | case AArch64::GLDFF1W_IMM: { |
2362 | 0 | MCInst TmpInst; |
2363 | 0 | MCOperand MCOp; |
2364 | 0 | TmpInst.setOpcode(AArch64::GLDFF1W_IMM_REAL); |
2365 | | // Operand: Zt |
2366 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2367 | 0 | TmpInst.addOperand(MCOp); |
2368 | | // Operand: Pg |
2369 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2370 | 0 | TmpInst.addOperand(MCOp); |
2371 | | // Operand: Zn |
2372 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2373 | 0 | TmpInst.addOperand(MCOp); |
2374 | | // Operand: imm5 |
2375 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2376 | 0 | TmpInst.addOperand(MCOp); |
2377 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2378 | 0 | break; |
2379 | 0 | } |
2380 | 0 | case AArch64::GLDFF1W_SXTW: { |
2381 | 0 | MCInst TmpInst; |
2382 | 0 | MCOperand MCOp; |
2383 | 0 | TmpInst.setOpcode(AArch64::GLDFF1W_SXTW_REAL); |
2384 | | // Operand: Zt |
2385 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2386 | 0 | TmpInst.addOperand(MCOp); |
2387 | | // Operand: Pg |
2388 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2389 | 0 | TmpInst.addOperand(MCOp); |
2390 | | // Operand: Rn |
2391 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2392 | 0 | TmpInst.addOperand(MCOp); |
2393 | | // Operand: Zm |
2394 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2395 | 0 | TmpInst.addOperand(MCOp); |
2396 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2397 | 0 | break; |
2398 | 0 | } |
2399 | 0 | case AArch64::GLDFF1W_SXTW_SCALED: { |
2400 | 0 | MCInst TmpInst; |
2401 | 0 | MCOperand MCOp; |
2402 | 0 | TmpInst.setOpcode(AArch64::GLDFF1W_SXTW_SCALED_REAL); |
2403 | | // Operand: Zt |
2404 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2405 | 0 | TmpInst.addOperand(MCOp); |
2406 | | // Operand: Pg |
2407 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2408 | 0 | TmpInst.addOperand(MCOp); |
2409 | | // Operand: Rn |
2410 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2411 | 0 | TmpInst.addOperand(MCOp); |
2412 | | // Operand: Zm |
2413 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2414 | 0 | TmpInst.addOperand(MCOp); |
2415 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2416 | 0 | break; |
2417 | 0 | } |
2418 | 0 | case AArch64::GLDFF1W_UXTW: { |
2419 | 0 | MCInst TmpInst; |
2420 | 0 | MCOperand MCOp; |
2421 | 0 | TmpInst.setOpcode(AArch64::GLDFF1W_UXTW_REAL); |
2422 | | // Operand: Zt |
2423 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2424 | 0 | TmpInst.addOperand(MCOp); |
2425 | | // Operand: Pg |
2426 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2427 | 0 | TmpInst.addOperand(MCOp); |
2428 | | // Operand: Rn |
2429 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2430 | 0 | TmpInst.addOperand(MCOp); |
2431 | | // Operand: Zm |
2432 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2433 | 0 | TmpInst.addOperand(MCOp); |
2434 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2435 | 0 | break; |
2436 | 0 | } |
2437 | 0 | case AArch64::GLDFF1W_UXTW_SCALED: { |
2438 | 0 | MCInst TmpInst; |
2439 | 0 | MCOperand MCOp; |
2440 | 0 | TmpInst.setOpcode(AArch64::GLDFF1W_UXTW_SCALED_REAL); |
2441 | | // Operand: Zt |
2442 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2443 | 0 | TmpInst.addOperand(MCOp); |
2444 | | // Operand: Pg |
2445 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2446 | 0 | TmpInst.addOperand(MCOp); |
2447 | | // Operand: Rn |
2448 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2449 | 0 | TmpInst.addOperand(MCOp); |
2450 | | // Operand: Zm |
2451 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2452 | 0 | TmpInst.addOperand(MCOp); |
2453 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2454 | 0 | break; |
2455 | 0 | } |
2456 | 0 | case AArch64::LDFF1B: { |
2457 | 0 | MCInst TmpInst; |
2458 | 0 | MCOperand MCOp; |
2459 | 0 | TmpInst.setOpcode(AArch64::LDFF1B_REAL); |
2460 | | // Operand: Zt |
2461 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2462 | 0 | TmpInst.addOperand(MCOp); |
2463 | | // Operand: Pg |
2464 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2465 | 0 | TmpInst.addOperand(MCOp); |
2466 | | // Operand: Rn |
2467 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2468 | 0 | TmpInst.addOperand(MCOp); |
2469 | | // Operand: Rm |
2470 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2471 | 0 | TmpInst.addOperand(MCOp); |
2472 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2473 | 0 | break; |
2474 | 0 | } |
2475 | 0 | case AArch64::LDFF1B_D: { |
2476 | 0 | MCInst TmpInst; |
2477 | 0 | MCOperand MCOp; |
2478 | 0 | TmpInst.setOpcode(AArch64::LDFF1B_D_REAL); |
2479 | | // Operand: Zt |
2480 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2481 | 0 | TmpInst.addOperand(MCOp); |
2482 | | // Operand: Pg |
2483 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2484 | 0 | TmpInst.addOperand(MCOp); |
2485 | | // Operand: Rn |
2486 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2487 | 0 | TmpInst.addOperand(MCOp); |
2488 | | // Operand: Rm |
2489 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2490 | 0 | TmpInst.addOperand(MCOp); |
2491 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2492 | 0 | break; |
2493 | 0 | } |
2494 | 0 | case AArch64::LDFF1B_H: { |
2495 | 0 | MCInst TmpInst; |
2496 | 0 | MCOperand MCOp; |
2497 | 0 | TmpInst.setOpcode(AArch64::LDFF1B_H_REAL); |
2498 | | // Operand: Zt |
2499 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2500 | 0 | TmpInst.addOperand(MCOp); |
2501 | | // Operand: Pg |
2502 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2503 | 0 | TmpInst.addOperand(MCOp); |
2504 | | // Operand: Rn |
2505 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2506 | 0 | TmpInst.addOperand(MCOp); |
2507 | | // Operand: Rm |
2508 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2509 | 0 | TmpInst.addOperand(MCOp); |
2510 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2511 | 0 | break; |
2512 | 0 | } |
2513 | 0 | case AArch64::LDFF1B_S: { |
2514 | 0 | MCInst TmpInst; |
2515 | 0 | MCOperand MCOp; |
2516 | 0 | TmpInst.setOpcode(AArch64::LDFF1B_S_REAL); |
2517 | | // Operand: Zt |
2518 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2519 | 0 | TmpInst.addOperand(MCOp); |
2520 | | // Operand: Pg |
2521 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2522 | 0 | TmpInst.addOperand(MCOp); |
2523 | | // Operand: Rn |
2524 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2525 | 0 | TmpInst.addOperand(MCOp); |
2526 | | // Operand: Rm |
2527 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2528 | 0 | TmpInst.addOperand(MCOp); |
2529 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2530 | 0 | break; |
2531 | 0 | } |
2532 | 0 | case AArch64::LDFF1D: { |
2533 | 0 | MCInst TmpInst; |
2534 | 0 | MCOperand MCOp; |
2535 | 0 | TmpInst.setOpcode(AArch64::LDFF1D_REAL); |
2536 | | // Operand: Zt |
2537 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2538 | 0 | TmpInst.addOperand(MCOp); |
2539 | | // Operand: Pg |
2540 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2541 | 0 | TmpInst.addOperand(MCOp); |
2542 | | // Operand: Rn |
2543 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2544 | 0 | TmpInst.addOperand(MCOp); |
2545 | | // Operand: Rm |
2546 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2547 | 0 | TmpInst.addOperand(MCOp); |
2548 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2549 | 0 | break; |
2550 | 0 | } |
2551 | 0 | case AArch64::LDFF1H: { |
2552 | 0 | MCInst TmpInst; |
2553 | 0 | MCOperand MCOp; |
2554 | 0 | TmpInst.setOpcode(AArch64::LDFF1H_REAL); |
2555 | | // Operand: Zt |
2556 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2557 | 0 | TmpInst.addOperand(MCOp); |
2558 | | // Operand: Pg |
2559 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2560 | 0 | TmpInst.addOperand(MCOp); |
2561 | | // Operand: Rn |
2562 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2563 | 0 | TmpInst.addOperand(MCOp); |
2564 | | // Operand: Rm |
2565 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2566 | 0 | TmpInst.addOperand(MCOp); |
2567 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2568 | 0 | break; |
2569 | 0 | } |
2570 | 0 | case AArch64::LDFF1H_D: { |
2571 | 0 | MCInst TmpInst; |
2572 | 0 | MCOperand MCOp; |
2573 | 0 | TmpInst.setOpcode(AArch64::LDFF1H_D_REAL); |
2574 | | // Operand: Zt |
2575 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2576 | 0 | TmpInst.addOperand(MCOp); |
2577 | | // Operand: Pg |
2578 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2579 | 0 | TmpInst.addOperand(MCOp); |
2580 | | // Operand: Rn |
2581 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2582 | 0 | TmpInst.addOperand(MCOp); |
2583 | | // Operand: Rm |
2584 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2585 | 0 | TmpInst.addOperand(MCOp); |
2586 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2587 | 0 | break; |
2588 | 0 | } |
2589 | 0 | case AArch64::LDFF1H_S: { |
2590 | 0 | MCInst TmpInst; |
2591 | 0 | MCOperand MCOp; |
2592 | 0 | TmpInst.setOpcode(AArch64::LDFF1H_S_REAL); |
2593 | | // Operand: Zt |
2594 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2595 | 0 | TmpInst.addOperand(MCOp); |
2596 | | // Operand: Pg |
2597 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2598 | 0 | TmpInst.addOperand(MCOp); |
2599 | | // Operand: Rn |
2600 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2601 | 0 | TmpInst.addOperand(MCOp); |
2602 | | // Operand: Rm |
2603 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2604 | 0 | TmpInst.addOperand(MCOp); |
2605 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2606 | 0 | break; |
2607 | 0 | } |
2608 | 0 | case AArch64::LDFF1SB_D: { |
2609 | 0 | MCInst TmpInst; |
2610 | 0 | MCOperand MCOp; |
2611 | 0 | TmpInst.setOpcode(AArch64::LDFF1SB_D_REAL); |
2612 | | // Operand: Zt |
2613 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2614 | 0 | TmpInst.addOperand(MCOp); |
2615 | | // Operand: Pg |
2616 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2617 | 0 | TmpInst.addOperand(MCOp); |
2618 | | // Operand: Rn |
2619 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2620 | 0 | TmpInst.addOperand(MCOp); |
2621 | | // Operand: Rm |
2622 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2623 | 0 | TmpInst.addOperand(MCOp); |
2624 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2625 | 0 | break; |
2626 | 0 | } |
2627 | 0 | case AArch64::LDFF1SB_H: { |
2628 | 0 | MCInst TmpInst; |
2629 | 0 | MCOperand MCOp; |
2630 | 0 | TmpInst.setOpcode(AArch64::LDFF1SB_H_REAL); |
2631 | | // Operand: Zt |
2632 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2633 | 0 | TmpInst.addOperand(MCOp); |
2634 | | // Operand: Pg |
2635 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2636 | 0 | TmpInst.addOperand(MCOp); |
2637 | | // Operand: Rn |
2638 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2639 | 0 | TmpInst.addOperand(MCOp); |
2640 | | // Operand: Rm |
2641 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2642 | 0 | TmpInst.addOperand(MCOp); |
2643 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2644 | 0 | break; |
2645 | 0 | } |
2646 | 0 | case AArch64::LDFF1SB_S: { |
2647 | 0 | MCInst TmpInst; |
2648 | 0 | MCOperand MCOp; |
2649 | 0 | TmpInst.setOpcode(AArch64::LDFF1SB_S_REAL); |
2650 | | // Operand: Zt |
2651 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2652 | 0 | TmpInst.addOperand(MCOp); |
2653 | | // Operand: Pg |
2654 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2655 | 0 | TmpInst.addOperand(MCOp); |
2656 | | // Operand: Rn |
2657 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2658 | 0 | TmpInst.addOperand(MCOp); |
2659 | | // Operand: Rm |
2660 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2661 | 0 | TmpInst.addOperand(MCOp); |
2662 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2663 | 0 | break; |
2664 | 0 | } |
2665 | 0 | case AArch64::LDFF1SH_D: { |
2666 | 0 | MCInst TmpInst; |
2667 | 0 | MCOperand MCOp; |
2668 | 0 | TmpInst.setOpcode(AArch64::LDFF1SH_D_REAL); |
2669 | | // Operand: Zt |
2670 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2671 | 0 | TmpInst.addOperand(MCOp); |
2672 | | // Operand: Pg |
2673 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2674 | 0 | TmpInst.addOperand(MCOp); |
2675 | | // Operand: Rn |
2676 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2677 | 0 | TmpInst.addOperand(MCOp); |
2678 | | // Operand: Rm |
2679 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2680 | 0 | TmpInst.addOperand(MCOp); |
2681 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2682 | 0 | break; |
2683 | 0 | } |
2684 | 0 | case AArch64::LDFF1SH_S: { |
2685 | 0 | MCInst TmpInst; |
2686 | 0 | MCOperand MCOp; |
2687 | 0 | TmpInst.setOpcode(AArch64::LDFF1SH_S_REAL); |
2688 | | // Operand: Zt |
2689 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2690 | 0 | TmpInst.addOperand(MCOp); |
2691 | | // Operand: Pg |
2692 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2693 | 0 | TmpInst.addOperand(MCOp); |
2694 | | // Operand: Rn |
2695 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2696 | 0 | TmpInst.addOperand(MCOp); |
2697 | | // Operand: Rm |
2698 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2699 | 0 | TmpInst.addOperand(MCOp); |
2700 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2701 | 0 | break; |
2702 | 0 | } |
2703 | 0 | case AArch64::LDFF1SW_D: { |
2704 | 0 | MCInst TmpInst; |
2705 | 0 | MCOperand MCOp; |
2706 | 0 | TmpInst.setOpcode(AArch64::LDFF1SW_D_REAL); |
2707 | | // Operand: Zt |
2708 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2709 | 0 | TmpInst.addOperand(MCOp); |
2710 | | // Operand: Pg |
2711 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2712 | 0 | TmpInst.addOperand(MCOp); |
2713 | | // Operand: Rn |
2714 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2715 | 0 | TmpInst.addOperand(MCOp); |
2716 | | // Operand: Rm |
2717 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2718 | 0 | TmpInst.addOperand(MCOp); |
2719 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2720 | 0 | break; |
2721 | 0 | } |
2722 | 0 | case AArch64::LDFF1W: { |
2723 | 0 | MCInst TmpInst; |
2724 | 0 | MCOperand MCOp; |
2725 | 0 | TmpInst.setOpcode(AArch64::LDFF1W_REAL); |
2726 | | // Operand: Zt |
2727 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2728 | 0 | TmpInst.addOperand(MCOp); |
2729 | | // Operand: Pg |
2730 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2731 | 0 | TmpInst.addOperand(MCOp); |
2732 | | // Operand: Rn |
2733 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2734 | 0 | TmpInst.addOperand(MCOp); |
2735 | | // Operand: Rm |
2736 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2737 | 0 | TmpInst.addOperand(MCOp); |
2738 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2739 | 0 | break; |
2740 | 0 | } |
2741 | 0 | case AArch64::LDFF1W_D: { |
2742 | 0 | MCInst TmpInst; |
2743 | 0 | MCOperand MCOp; |
2744 | 0 | TmpInst.setOpcode(AArch64::LDFF1W_D_REAL); |
2745 | | // Operand: Zt |
2746 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2747 | 0 | TmpInst.addOperand(MCOp); |
2748 | | // Operand: Pg |
2749 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2750 | 0 | TmpInst.addOperand(MCOp); |
2751 | | // Operand: Rn |
2752 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2753 | 0 | TmpInst.addOperand(MCOp); |
2754 | | // Operand: Rm |
2755 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2756 | 0 | TmpInst.addOperand(MCOp); |
2757 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2758 | 0 | break; |
2759 | 0 | } |
2760 | 0 | case AArch64::LDNF1B_D_IMM: { |
2761 | 0 | MCInst TmpInst; |
2762 | 0 | MCOperand MCOp; |
2763 | 0 | TmpInst.setOpcode(AArch64::LDNF1B_D_IMM_REAL); |
2764 | | // Operand: Zt |
2765 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2766 | 0 | TmpInst.addOperand(MCOp); |
2767 | | // Operand: Pg |
2768 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2769 | 0 | TmpInst.addOperand(MCOp); |
2770 | | // Operand: Rn |
2771 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2772 | 0 | TmpInst.addOperand(MCOp); |
2773 | | // Operand: imm4 |
2774 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2775 | 0 | TmpInst.addOperand(MCOp); |
2776 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2777 | 0 | break; |
2778 | 0 | } |
2779 | 0 | case AArch64::LDNF1B_H_IMM: { |
2780 | 0 | MCInst TmpInst; |
2781 | 0 | MCOperand MCOp; |
2782 | 0 | TmpInst.setOpcode(AArch64::LDNF1B_H_IMM_REAL); |
2783 | | // Operand: Zt |
2784 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2785 | 0 | TmpInst.addOperand(MCOp); |
2786 | | // Operand: Pg |
2787 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2788 | 0 | TmpInst.addOperand(MCOp); |
2789 | | // Operand: Rn |
2790 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2791 | 0 | TmpInst.addOperand(MCOp); |
2792 | | // Operand: imm4 |
2793 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2794 | 0 | TmpInst.addOperand(MCOp); |
2795 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2796 | 0 | break; |
2797 | 0 | } |
2798 | 0 | case AArch64::LDNF1B_IMM: { |
2799 | 0 | MCInst TmpInst; |
2800 | 0 | MCOperand MCOp; |
2801 | 0 | TmpInst.setOpcode(AArch64::LDNF1B_IMM_REAL); |
2802 | | // Operand: Zt |
2803 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2804 | 0 | TmpInst.addOperand(MCOp); |
2805 | | // Operand: Pg |
2806 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2807 | 0 | TmpInst.addOperand(MCOp); |
2808 | | // Operand: Rn |
2809 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2810 | 0 | TmpInst.addOperand(MCOp); |
2811 | | // Operand: imm4 |
2812 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2813 | 0 | TmpInst.addOperand(MCOp); |
2814 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2815 | 0 | break; |
2816 | 0 | } |
2817 | 0 | case AArch64::LDNF1B_S_IMM: { |
2818 | 0 | MCInst TmpInst; |
2819 | 0 | MCOperand MCOp; |
2820 | 0 | TmpInst.setOpcode(AArch64::LDNF1B_S_IMM_REAL); |
2821 | | // Operand: Zt |
2822 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2823 | 0 | TmpInst.addOperand(MCOp); |
2824 | | // Operand: Pg |
2825 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2826 | 0 | TmpInst.addOperand(MCOp); |
2827 | | // Operand: Rn |
2828 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2829 | 0 | TmpInst.addOperand(MCOp); |
2830 | | // Operand: imm4 |
2831 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2832 | 0 | TmpInst.addOperand(MCOp); |
2833 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2834 | 0 | break; |
2835 | 0 | } |
2836 | 0 | case AArch64::LDNF1D_IMM: { |
2837 | 0 | MCInst TmpInst; |
2838 | 0 | MCOperand MCOp; |
2839 | 0 | TmpInst.setOpcode(AArch64::LDNF1D_IMM_REAL); |
2840 | | // Operand: Zt |
2841 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2842 | 0 | TmpInst.addOperand(MCOp); |
2843 | | // Operand: Pg |
2844 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2845 | 0 | TmpInst.addOperand(MCOp); |
2846 | | // Operand: Rn |
2847 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2848 | 0 | TmpInst.addOperand(MCOp); |
2849 | | // Operand: imm4 |
2850 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2851 | 0 | TmpInst.addOperand(MCOp); |
2852 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2853 | 0 | break; |
2854 | 0 | } |
2855 | 0 | case AArch64::LDNF1H_D_IMM: { |
2856 | 0 | MCInst TmpInst; |
2857 | 0 | MCOperand MCOp; |
2858 | 0 | TmpInst.setOpcode(AArch64::LDNF1H_D_IMM_REAL); |
2859 | | // Operand: Zt |
2860 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2861 | 0 | TmpInst.addOperand(MCOp); |
2862 | | // Operand: Pg |
2863 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2864 | 0 | TmpInst.addOperand(MCOp); |
2865 | | // Operand: Rn |
2866 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2867 | 0 | TmpInst.addOperand(MCOp); |
2868 | | // Operand: imm4 |
2869 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2870 | 0 | TmpInst.addOperand(MCOp); |
2871 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2872 | 0 | break; |
2873 | 0 | } |
2874 | 0 | case AArch64::LDNF1H_IMM: { |
2875 | 0 | MCInst TmpInst; |
2876 | 0 | MCOperand MCOp; |
2877 | 0 | TmpInst.setOpcode(AArch64::LDNF1H_IMM_REAL); |
2878 | | // Operand: Zt |
2879 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2880 | 0 | TmpInst.addOperand(MCOp); |
2881 | | // Operand: Pg |
2882 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2883 | 0 | TmpInst.addOperand(MCOp); |
2884 | | // Operand: Rn |
2885 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2886 | 0 | TmpInst.addOperand(MCOp); |
2887 | | // Operand: imm4 |
2888 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2889 | 0 | TmpInst.addOperand(MCOp); |
2890 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2891 | 0 | break; |
2892 | 0 | } |
2893 | 0 | case AArch64::LDNF1H_S_IMM: { |
2894 | 0 | MCInst TmpInst; |
2895 | 0 | MCOperand MCOp; |
2896 | 0 | TmpInst.setOpcode(AArch64::LDNF1H_S_IMM_REAL); |
2897 | | // Operand: Zt |
2898 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2899 | 0 | TmpInst.addOperand(MCOp); |
2900 | | // Operand: Pg |
2901 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2902 | 0 | TmpInst.addOperand(MCOp); |
2903 | | // Operand: Rn |
2904 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2905 | 0 | TmpInst.addOperand(MCOp); |
2906 | | // Operand: imm4 |
2907 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2908 | 0 | TmpInst.addOperand(MCOp); |
2909 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2910 | 0 | break; |
2911 | 0 | } |
2912 | 0 | case AArch64::LDNF1SB_D_IMM: { |
2913 | 0 | MCInst TmpInst; |
2914 | 0 | MCOperand MCOp; |
2915 | 0 | TmpInst.setOpcode(AArch64::LDNF1SB_D_IMM_REAL); |
2916 | | // Operand: Zt |
2917 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2918 | 0 | TmpInst.addOperand(MCOp); |
2919 | | // Operand: Pg |
2920 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2921 | 0 | TmpInst.addOperand(MCOp); |
2922 | | // Operand: Rn |
2923 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2924 | 0 | TmpInst.addOperand(MCOp); |
2925 | | // Operand: imm4 |
2926 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2927 | 0 | TmpInst.addOperand(MCOp); |
2928 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2929 | 0 | break; |
2930 | 0 | } |
2931 | 0 | case AArch64::LDNF1SB_H_IMM: { |
2932 | 0 | MCInst TmpInst; |
2933 | 0 | MCOperand MCOp; |
2934 | 0 | TmpInst.setOpcode(AArch64::LDNF1SB_H_IMM_REAL); |
2935 | | // Operand: Zt |
2936 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2937 | 0 | TmpInst.addOperand(MCOp); |
2938 | | // Operand: Pg |
2939 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2940 | 0 | TmpInst.addOperand(MCOp); |
2941 | | // Operand: Rn |
2942 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2943 | 0 | TmpInst.addOperand(MCOp); |
2944 | | // Operand: imm4 |
2945 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2946 | 0 | TmpInst.addOperand(MCOp); |
2947 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2948 | 0 | break; |
2949 | 0 | } |
2950 | 0 | case AArch64::LDNF1SB_S_IMM: { |
2951 | 0 | MCInst TmpInst; |
2952 | 0 | MCOperand MCOp; |
2953 | 0 | TmpInst.setOpcode(AArch64::LDNF1SB_S_IMM_REAL); |
2954 | | // Operand: Zt |
2955 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2956 | 0 | TmpInst.addOperand(MCOp); |
2957 | | // Operand: Pg |
2958 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2959 | 0 | TmpInst.addOperand(MCOp); |
2960 | | // Operand: Rn |
2961 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2962 | 0 | TmpInst.addOperand(MCOp); |
2963 | | // Operand: imm4 |
2964 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2965 | 0 | TmpInst.addOperand(MCOp); |
2966 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2967 | 0 | break; |
2968 | 0 | } |
2969 | 0 | case AArch64::LDNF1SH_D_IMM: { |
2970 | 0 | MCInst TmpInst; |
2971 | 0 | MCOperand MCOp; |
2972 | 0 | TmpInst.setOpcode(AArch64::LDNF1SH_D_IMM_REAL); |
2973 | | // Operand: Zt |
2974 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2975 | 0 | TmpInst.addOperand(MCOp); |
2976 | | // Operand: Pg |
2977 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2978 | 0 | TmpInst.addOperand(MCOp); |
2979 | | // Operand: Rn |
2980 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
2981 | 0 | TmpInst.addOperand(MCOp); |
2982 | | // Operand: imm4 |
2983 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
2984 | 0 | TmpInst.addOperand(MCOp); |
2985 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
2986 | 0 | break; |
2987 | 0 | } |
2988 | 0 | case AArch64::LDNF1SH_S_IMM: { |
2989 | 0 | MCInst TmpInst; |
2990 | 0 | MCOperand MCOp; |
2991 | 0 | TmpInst.setOpcode(AArch64::LDNF1SH_S_IMM_REAL); |
2992 | | // Operand: Zt |
2993 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
2994 | 0 | TmpInst.addOperand(MCOp); |
2995 | | // Operand: Pg |
2996 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
2997 | 0 | TmpInst.addOperand(MCOp); |
2998 | | // Operand: Rn |
2999 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
3000 | 0 | TmpInst.addOperand(MCOp); |
3001 | | // Operand: imm4 |
3002 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
3003 | 0 | TmpInst.addOperand(MCOp); |
3004 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
3005 | 0 | break; |
3006 | 0 | } |
3007 | 0 | case AArch64::LDNF1SW_D_IMM: { |
3008 | 0 | MCInst TmpInst; |
3009 | 0 | MCOperand MCOp; |
3010 | 0 | TmpInst.setOpcode(AArch64::LDNF1SW_D_IMM_REAL); |
3011 | | // Operand: Zt |
3012 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
3013 | 0 | TmpInst.addOperand(MCOp); |
3014 | | // Operand: Pg |
3015 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
3016 | 0 | TmpInst.addOperand(MCOp); |
3017 | | // Operand: Rn |
3018 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
3019 | 0 | TmpInst.addOperand(MCOp); |
3020 | | // Operand: imm4 |
3021 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
3022 | 0 | TmpInst.addOperand(MCOp); |
3023 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
3024 | 0 | break; |
3025 | 0 | } |
3026 | 0 | case AArch64::LDNF1W_D_IMM: { |
3027 | 0 | MCInst TmpInst; |
3028 | 0 | MCOperand MCOp; |
3029 | 0 | TmpInst.setOpcode(AArch64::LDNF1W_D_IMM_REAL); |
3030 | | // Operand: Zt |
3031 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
3032 | 0 | TmpInst.addOperand(MCOp); |
3033 | | // Operand: Pg |
3034 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
3035 | 0 | TmpInst.addOperand(MCOp); |
3036 | | // Operand: Rn |
3037 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
3038 | 0 | TmpInst.addOperand(MCOp); |
3039 | | // Operand: imm4 |
3040 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
3041 | 0 | TmpInst.addOperand(MCOp); |
3042 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
3043 | 0 | break; |
3044 | 0 | } |
3045 | 0 | case AArch64::LDNF1W_IMM: { |
3046 | 0 | MCInst TmpInst; |
3047 | 0 | MCOperand MCOp; |
3048 | 0 | TmpInst.setOpcode(AArch64::LDNF1W_IMM_REAL); |
3049 | | // Operand: Zt |
3050 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
3051 | 0 | TmpInst.addOperand(MCOp); |
3052 | | // Operand: Pg |
3053 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
3054 | 0 | TmpInst.addOperand(MCOp); |
3055 | | // Operand: Rn |
3056 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
3057 | 0 | TmpInst.addOperand(MCOp); |
3058 | | // Operand: imm4 |
3059 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
3060 | 0 | TmpInst.addOperand(MCOp); |
3061 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
3062 | 0 | break; |
3063 | 0 | } |
3064 | 0 | case AArch64::MRS_FPCR: { |
3065 | 0 | MCInst TmpInst; |
3066 | 0 | MCOperand MCOp; |
3067 | 0 | TmpInst.setOpcode(AArch64::MRS); |
3068 | | // Operand: Rt |
3069 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
3070 | 0 | TmpInst.addOperand(MCOp); |
3071 | | // Operand: systemreg |
3072 | 0 | TmpInst.addOperand(MCOperand::createImm(55840)); |
3073 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
3074 | 0 | break; |
3075 | 0 | } |
3076 | 0 | case AArch64::MSR_FPCR: { |
3077 | 0 | MCInst TmpInst; |
3078 | 0 | MCOperand MCOp; |
3079 | 0 | TmpInst.setOpcode(AArch64::MSR); |
3080 | | // Operand: systemreg |
3081 | 0 | TmpInst.addOperand(MCOperand::createImm(55840)); |
3082 | | // Operand: Rt |
3083 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
3084 | 0 | TmpInst.addOperand(MCOp); |
3085 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
3086 | 0 | break; |
3087 | 0 | } |
3088 | 0 | case AArch64::PTEST_PP_ANY: { |
3089 | 0 | MCInst TmpInst; |
3090 | 0 | MCOperand MCOp; |
3091 | 0 | TmpInst.setOpcode(AArch64::PTEST_PP); |
3092 | | // Operand: Pg |
3093 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
3094 | 0 | TmpInst.addOperand(MCOp); |
3095 | | // Operand: Pn |
3096 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
3097 | 0 | TmpInst.addOperand(MCOp); |
3098 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
3099 | 0 | break; |
3100 | 0 | } |
3101 | 0 | case AArch64::RDFFR_P: { |
3102 | 0 | MCInst TmpInst; |
3103 | 0 | MCOperand MCOp; |
3104 | 0 | TmpInst.setOpcode(AArch64::RDFFR_P_REAL); |
3105 | | // Operand: Pd |
3106 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
3107 | 0 | TmpInst.addOperand(MCOp); |
3108 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
3109 | 0 | break; |
3110 | 0 | } |
3111 | 0 | case AArch64::RDFFR_PPz: { |
3112 | 0 | MCInst TmpInst; |
3113 | 0 | MCOperand MCOp; |
3114 | 0 | TmpInst.setOpcode(AArch64::RDFFR_PPz_REAL); |
3115 | | // Operand: Pd |
3116 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
3117 | 0 | TmpInst.addOperand(MCOp); |
3118 | | // Operand: Pg |
3119 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
3120 | 0 | TmpInst.addOperand(MCOp); |
3121 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
3122 | 0 | break; |
3123 | 0 | } |
3124 | 822k | } |
3125 | 0 | return true; |
3126 | 822k | } |
3127 | | |