Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/AArch64/AArch64GenRegisterBank.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Register Bank Source Fragments                                             *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGBANK_DECLARATIONS
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#undef GET_REGBANK_DECLARATIONS
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namespace llvm {
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namespace AArch64 {
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enum : unsigned {
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  InvalidRegBankID = ~0u,
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  CCRegBankID = 0,
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  FPRRegBankID = 1,
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  GPRRegBankID = 2,
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  NumRegisterBanks,
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};
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} // end namespace AArch64
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} // end namespace llvm
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#endif // GET_REGBANK_DECLARATIONS
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#ifdef GET_TARGET_REGBANK_CLASS
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#undef GET_TARGET_REGBANK_CLASS
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private:
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  static const RegisterBank *RegBanks[];
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  static const unsigned Sizes[];
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protected:
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  AArch64GenRegisterBankInfo(unsigned HwMode = 0);
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#endif // GET_TARGET_REGBANK_CLASS
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#ifdef GET_TARGET_REGBANK_IMPL
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#undef GET_TARGET_REGBANK_IMPL
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namespace llvm {
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namespace AArch64 {
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const uint32_t CCRegBankCoverageData[] = {
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    // 0-31
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    (1u << (AArch64::CCRRegClassID - 0)) |
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    0,
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    // 32-63
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    0,
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    // 64-95
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    0,
47
    // 96-127
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    0,
49
    // 128-159
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    0,
51
    // 160-191
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    0,
53
    // 192-223
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    0,
55
    // 224-255
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    0,
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    // 256-287
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    0,
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    // 288-319
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    0,
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};
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const uint32_t FPRRegBankCoverageData[] = {
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    // 0-31
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    (1u << (AArch64::FPR8RegClassID - 0)) |
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    (1u << (AArch64::FPR16RegClassID - 0)) |
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    (1u << (AArch64::FPR32RegClassID - 0)) |
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    (1u << (AArch64::FPR16_loRegClassID - 0)) |
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    (1u << (AArch64::FPR32_with_hsub_in_FPR16_loRegClassID - 0)) |
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    0,
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    // 32-63
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    (1u << (AArch64::FPR64RegClassID - 32)) |
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    (1u << (AArch64::DDRegClassID - 32)) |
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    (1u << (AArch64::FPR64_loRegClassID - 32)) |
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    (1u << (AArch64::DD_with_dsub0_in_FPR64_loRegClassID - 32)) |
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    (1u << (AArch64::DD_with_dsub1_in_FPR64_loRegClassID - 32)) |
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    (1u << (AArch64::DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loRegClassID - 32)) |
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    0,
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    // 64-95
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    (1u << (AArch64::FPR128RegClassID - 64)) |
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    (1u << (AArch64::DDDRegClassID - 64)) |
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    (1u << (AArch64::DDDDRegClassID - 64)) |
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    (1u << (AArch64::FPR128_loRegClassID - 64)) |
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    (1u << (AArch64::DDD_with_dsub0_in_FPR64_loRegClassID - 64)) |
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    (1u << (AArch64::DDDD_with_dsub0_in_FPR64_loRegClassID - 64)) |
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    (1u << (AArch64::DDD_with_dsub1_in_FPR64_loRegClassID - 64)) |
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    (1u << (AArch64::DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loRegClassID - 64)) |
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    (1u << (AArch64::DDDD_with_dsub1_in_FPR64_loRegClassID - 64)) |
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    (1u << (AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loRegClassID - 64)) |
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    (1u << (AArch64::DDD_with_dsub2_in_FPR64_loRegClassID - 64)) |
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    (1u << (AArch64::DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID - 64)) |
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    (1u << (AArch64::DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID - 64)) |
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    (1u << (AArch64::DDDD_with_dsub2_in_FPR64_loRegClassID - 64)) |
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    (1u << (AArch64::DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID - 64)) |
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    (1u << (AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID - 64)) |
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    (1u << (AArch64::DDDD_with_dsub3_in_FPR64_loRegClassID - 64)) |
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    (1u << (AArch64::DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID - 64)) |
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    (1u << (AArch64::DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID - 64)) |
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    (1u << (AArch64::FPR128_0to7RegClassID - 64)) |
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    0,
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    // 96-127
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    (1u << (AArch64::QQRegClassID - 96)) |
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    (1u << (AArch64::QQQRegClassID - 96)) |
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    (1u << (AArch64::QQ_with_dsub_in_FPR64_loRegClassID - 96)) |
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    (1u << (AArch64::QQQ_with_dsub_in_FPR64_loRegClassID - 96)) |
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    (1u << (AArch64::QQ_with_qsub1_in_FPR128_loRegClassID - 96)) |
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    (1u << (AArch64::QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID - 96)) |
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    (1u << (AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID - 96)) |
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    (1u << (AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID - 96)) |
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    (1u << (AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID - 96)) |
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    (1u << (AArch64::QQ_with_qsub0_in_FPR128_0to7RegClassID - 96)) |
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    (1u << (AArch64::QQ_with_qsub1_in_FPR128_0to7RegClassID - 96)) |
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    (1u << (AArch64::QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_0to7RegClassID - 96)) |
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    0,
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    // 128-159
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    (1u << (AArch64::QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID - 128)) |
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    (1u << (AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID - 128)) |
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    (1u << (AArch64::QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID - 128)) |
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    (1u << (AArch64::QQQ_with_qsub0_in_FPR128_0to7RegClassID - 128)) |
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    (1u << (AArch64::QQQ_with_qsub1_in_FPR128_0to7RegClassID - 128)) |
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    (1u << (AArch64::QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_0to7RegClassID - 128)) |
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    (1u << (AArch64::QQQ_with_qsub2_in_FPR128_0to7RegClassID - 128)) |
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    (1u << (AArch64::QQQ_with_qsub1_in_FPR128_0to7_and_QQQ_with_qsub2_in_FPR128_0to7RegClassID - 128)) |
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    (1u << (AArch64::QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_0to7RegClassID - 128)) |
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    0,
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    // 160-191
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    (1u << (AArch64::QQQQRegClassID - 160)) |
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    (1u << (AArch64::QQQQ_with_dsub_in_FPR64_loRegClassID - 160)) |
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    (1u << (AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID - 160)) |
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    (1u << (AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID - 160)) |
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    (1u << (AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 160)) |
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    (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_0to7RegClassID - 160)) |
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    (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID - 160)) |
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    (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID - 160)) |
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    (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 160)) |
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    (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_0to7RegClassID - 160)) |
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    (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID - 160)) |
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    (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 160)) |
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    (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_0to7RegClassID - 160)) |
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    (1u << (AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID - 160)) |
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    (1u << (AArch64::QQQQ_with_qsub3_in_FPR128_0to7RegClassID - 160)) |
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    0,
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    // 192-223
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    (1u << (AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_0to7RegClassID - 192)) |
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    (1u << (AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_0to7RegClassID - 192)) |
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    (1u << (AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID - 192)) |
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    (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_0to7_and_QQQQ_with_qsub2_in_FPR128_0to7RegClassID - 192)) |
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    (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_0to7_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID - 192)) |
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    (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_0to7_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID - 192)) |
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    0,
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    // 224-255
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    0,
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    // 256-287
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    0,
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    // 288-319
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    0,
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};
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const uint32_t GPRRegBankCoverageData[] = {
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    // 0-31
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    (1u << (AArch64::GPR32allRegClassID - 0)) |
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    (1u << (AArch64::GPR32RegClassID - 0)) |
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    (1u << (AArch64::GPR32spRegClassID - 0)) |
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    (1u << (AArch64::GPR32commonRegClassID - 0)) |
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    (1u << (AArch64::GPR32argRegClassID - 0)) |
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    (1u << (AArch64::MatrixIndexGPR32_12_15RegClassID - 0)) |
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    (1u << (AArch64::MatrixIndexGPR32_8_11RegClassID - 0)) |
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    0,
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    // 32-63
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    (1u << (AArch64::XSeqPairsClassRegClassID - 32)) |
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    (1u << (AArch64::WSeqPairsClassRegClassID - 32)) |
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    (1u << (AArch64::GPR64allRegClassID - 32)) |
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    (1u << (AArch64::GPR64RegClassID - 32)) |
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    (1u << (AArch64::GPR64spRegClassID - 32)) |
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    (1u << (AArch64::GPR64commonRegClassID - 32)) |
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    (1u << (AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClassID - 32)) |
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    (1u << (AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClassID - 32)) |
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    (1u << (AArch64::XSeqPairsClass_with_sube64_in_GPR64noipRegClassID - 32)) |
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    (1u << (AArch64::GPR64noipRegClassID - 32)) |
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    (1u << (AArch64::GPR64common_and_GPR64noipRegClassID - 32)) |
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    (1u << (AArch64::tcGPR64RegClassID - 32)) |
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    (1u << (AArch64::GPR64noip_and_tcGPR64RegClassID - 32)) |
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    (1u << (AArch64::WSeqPairsClass_with_sube32_in_GPR32argRegClassID - 32)) |
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    (1u << (AArch64::GPR64argRegClassID - 32)) |
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    (1u << (AArch64::WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15RegClassID - 32)) |
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    (1u << (AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID - 32)) |
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    (1u << (AArch64::WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_8_11RegClassID - 32)) |
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    (1u << (AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID - 32)) |
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    (1u << (AArch64::FIXED_REGSRegClassID - 32)) |
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    (1u << (AArch64::FIXED_REGS_with_sub_32RegClassID - 32)) |
189
    (1u << (AArch64::FIXED_REGS_and_GPR64RegClassID - 32)) |
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    (1u << (AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClassID - 32)) |
191
    (1u << (AArch64::rtcGPR64RegClassID - 32)) |
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    (1u << (AArch64::XSeqPairsClass_with_subo64_in_GPR64noipRegClassID - 32)) |
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    0,
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    // 64-95
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    (1u << (AArch64::XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClassID - 64)) |
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    (1u << (AArch64::XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64RegClassID - 64)) |
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    (1u << (AArch64::XSeqPairsClass_with_sub_32_in_GPR32argRegClassID - 64)) |
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    (1u << (AArch64::XSeqPairsClass_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID - 64)) |
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    (1u << (AArch64::XSeqPairsClass_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID - 64)) |
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    (1u << (AArch64::XSeqPairsClass_with_subo64_in_FIXED_REGSRegClassID - 64)) |
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    (1u << (AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClassID - 64)) |
202
    (1u << (AArch64::XSeqPairsClass_with_sube64_in_rtcGPR64RegClassID - 64)) |
203
    0,
204
    // 96-127
205
    0,
206
    // 128-159
207
    0,
208
    // 160-191
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    0,
210
    // 192-223
211
    0,
212
    // 224-255
213
    0,
214
    // 256-287
215
    0,
216
    // 288-319
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    0,
218
};
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constexpr RegisterBank CCRegBank(/* ID */ AArch64::CCRegBankID, /* Name */ "CC", /* CoveredRegClasses */ CCRegBankCoverageData, /* NumRegClasses */ 302);
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constexpr RegisterBank FPRRegBank(/* ID */ AArch64::FPRRegBankID, /* Name */ "FPR", /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 302);
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constexpr RegisterBank GPRRegBank(/* ID */ AArch64::GPRRegBankID, /* Name */ "GPR", /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 302);
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} // end namespace AArch64
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const RegisterBank *AArch64GenRegisterBankInfo::RegBanks[] = {
226
    &AArch64::CCRegBank,
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    &AArch64::FPRRegBank,
228
    &AArch64::GPRRegBank,
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};
230
231
const unsigned AArch64GenRegisterBankInfo::Sizes[] = {
232
    // Mode = 0 (Default)
233
    32,
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    512,
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    128,
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};
237
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AArch64GenRegisterBankInfo::AArch64GenRegisterBankInfo(unsigned HwMode)
239
25
    : RegisterBankInfo(RegBanks, AArch64::NumRegisterBanks, Sizes, HwMode) {
240
  // Assert that RegBank indices match their ID's
241
25
#ifndef NDEBUG
242
25
  for (auto RB : enumerate(RegBanks))
243
75
    assert(RB.index() == RB.value()->getID() && "Index != ID");
244
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#endif // NDEBUG
245
25
}
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} // end namespace llvm
247
#endif // GET_TARGET_REGBANK_IMPL