/src/build/lib/Target/AMDGPU/AMDGPUGenSubtargetInfo.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Subtarget Enumeration Source Fragment *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | |
10 | | #ifdef GET_SUBTARGETINFO_ENUM |
11 | | #undef GET_SUBTARGETINFO_ENUM |
12 | | |
13 | | namespace llvm { |
14 | | namespace AMDGPU { |
15 | | enum { |
16 | | Feature16BitInsts = 0, |
17 | | FeatureA16 = 1, |
18 | | FeatureAddNoCarryInsts = 2, |
19 | | FeatureApertureRegs = 3, |
20 | | FeatureArchitectedFlatScratch = 4, |
21 | | FeatureArchitectedSGPRs = 5, |
22 | | FeatureAtomicBufferGlobalPkAddF16Insts = 6, |
23 | | FeatureAtomicBufferGlobalPkAddF16NoRtnInsts = 7, |
24 | | FeatureAtomicCSubNoRtnInsts = 8, |
25 | | FeatureAtomicDsPkAdd16Insts = 9, |
26 | | FeatureAtomicFaddNoRtnInsts = 10, |
27 | | FeatureAtomicFaddRtnInsts = 11, |
28 | | FeatureAtomicFlatPkAdd16Insts = 12, |
29 | | FeatureAtomicGlobalPkAddBF16Inst = 13, |
30 | | FeatureAutoWaitcntBeforeBarrier = 14, |
31 | | FeatureBackOffBarrier = 15, |
32 | | FeatureCIInsts = 16, |
33 | | FeatureCuMode = 17, |
34 | | FeatureDLInsts = 18, |
35 | | FeatureDPALU_DPP = 19, |
36 | | FeatureDPP = 20, |
37 | | FeatureDPP8 = 21, |
38 | | FeatureDPPSrc1SGPR = 22, |
39 | | FeatureDefaultComponentBroadcast = 23, |
40 | | FeatureDefaultComponentZero = 24, |
41 | | FeatureDisable = 25, |
42 | | FeatureDot1Insts = 26, |
43 | | FeatureDot2Insts = 27, |
44 | | FeatureDot3Insts = 28, |
45 | | FeatureDot4Insts = 29, |
46 | | FeatureDot5Insts = 30, |
47 | | FeatureDot6Insts = 31, |
48 | | FeatureDot7Insts = 32, |
49 | | FeatureDot8Insts = 33, |
50 | | FeatureDot9Insts = 34, |
51 | | FeatureDot10Insts = 35, |
52 | | FeatureDsSrc2Insts = 36, |
53 | | FeatureDumpCode = 37, |
54 | | FeatureDumpCodeLower = 38, |
55 | | FeatureEnableDS128 = 39, |
56 | | FeatureEnableFlatScratch = 40, |
57 | | FeatureEnableLoadStoreOpt = 41, |
58 | | FeatureEnablePRTStrictNull = 42, |
59 | | FeatureEnableSIScheduler = 43, |
60 | | FeatureEnableUnsafeDSOffsetFolding = 44, |
61 | | FeatureExtendedImageInsts = 45, |
62 | | FeatureFMA = 46, |
63 | | FeatureFP8Insts = 47, |
64 | | FeatureFP64 = 48, |
65 | | FeatureFastDenormalF32 = 49, |
66 | | FeatureFastFMAF32 = 50, |
67 | | FeatureFlatAddressSpace = 51, |
68 | | FeatureFlatAtomicFaddF32Inst = 52, |
69 | | FeatureFlatForGlobal = 53, |
70 | | FeatureFlatGlobalInsts = 54, |
71 | | FeatureFlatInstOffsets = 55, |
72 | | FeatureFlatScratchInsts = 56, |
73 | | FeatureFlatSegmentOffsetBug = 57, |
74 | | FeatureFmaMixInsts = 58, |
75 | | FeatureFmacF64Inst = 59, |
76 | | FeatureForceStoreSC0SC1 = 60, |
77 | | FeatureG16 = 61, |
78 | | FeatureGCN3Encoding = 62, |
79 | | FeatureGDS = 63, |
80 | | FeatureGFX7GFX8GFX9Insts = 64, |
81 | | FeatureGFX8Insts = 65, |
82 | | FeatureGFX9 = 66, |
83 | | FeatureGFX9Insts = 67, |
84 | | FeatureGFX10 = 68, |
85 | | FeatureGFX10Insts = 69, |
86 | | FeatureGFX10_3Insts = 70, |
87 | | FeatureGFX10_AEncoding = 71, |
88 | | FeatureGFX10_BEncoding = 72, |
89 | | FeatureGFX11 = 73, |
90 | | FeatureGFX11FullVGPRs = 74, |
91 | | FeatureGFX11Insts = 75, |
92 | | FeatureGFX12 = 76, |
93 | | FeatureGFX12Insts = 77, |
94 | | FeatureGFX90AInsts = 78, |
95 | | FeatureGFX940Insts = 79, |
96 | | FeatureGWS = 80, |
97 | | FeatureGetWaveIdInst = 81, |
98 | | FeatureHasRestrictedSOffset = 82, |
99 | | FeatureImageGather4D16Bug = 83, |
100 | | FeatureImageInsts = 84, |
101 | | FeatureImageStoreD16Bug = 85, |
102 | | FeatureInstFwdPrefetchBug = 86, |
103 | | FeatureIntClamp = 87, |
104 | | FeatureInv2PiInlineImm = 88, |
105 | | FeatureKernargPreload = 89, |
106 | | FeatureLDSBankCount16 = 90, |
107 | | FeatureLDSBankCount32 = 91, |
108 | | FeatureLdsBranchVmemWARHazard = 92, |
109 | | FeatureLdsMisalignedBug = 93, |
110 | | FeatureLocalMemorySize32768 = 94, |
111 | | FeatureLocalMemorySize65536 = 95, |
112 | | FeatureMADIntraFwdBug = 96, |
113 | | FeatureMAIInsts = 97, |
114 | | FeatureMFMAInlineLiteralBug = 98, |
115 | | FeatureMIMG_R128 = 99, |
116 | | FeatureMSAALoadDstSelBug = 100, |
117 | | FeatureMadMacF32Insts = 101, |
118 | | FeatureMadMixInsts = 102, |
119 | | FeatureMaxPrivateElementSize4 = 103, |
120 | | FeatureMaxPrivateElementSize8 = 104, |
121 | | FeatureMaxPrivateElementSize16 = 105, |
122 | | FeatureMovrel = 106, |
123 | | FeatureNSAClauseBug = 107, |
124 | | FeatureNSAEncoding = 108, |
125 | | FeatureNSAtoVMEMBug = 109, |
126 | | FeatureNegativeScratchOffsetBug = 110, |
127 | | FeatureNegativeUnalignedScratchOffsetBug = 111, |
128 | | FeatureNoDataDepHazard = 112, |
129 | | FeatureNoSdstCMPX = 113, |
130 | | FeatureOffset3fBug = 114, |
131 | | FeaturePackedFP32Ops = 115, |
132 | | FeaturePackedTID = 116, |
133 | | FeaturePartialNSAEncoding = 117, |
134 | | FeaturePkFmacF16Inst = 118, |
135 | | FeaturePromoteAlloca = 119, |
136 | | FeaturePseudoScalarTrans = 120, |
137 | | FeatureR128A16 = 121, |
138 | | FeatureRealTrue16Insts = 122, |
139 | | FeatureSALUFloatInsts = 123, |
140 | | FeatureSDWA = 124, |
141 | | FeatureSDWAMac = 125, |
142 | | FeatureSDWAOmod = 126, |
143 | | FeatureSDWAOutModsVOPC = 127, |
144 | | FeatureSDWAScalar = 128, |
145 | | FeatureSDWASdst = 129, |
146 | | FeatureSGPRInitBug = 130, |
147 | | FeatureSMEMtoVectorWriteHazard = 131, |
148 | | FeatureSMemRealTime = 132, |
149 | | FeatureSMemTimeInst = 133, |
150 | | FeatureSRAMECC = 134, |
151 | | FeatureScalarAtomics = 135, |
152 | | FeatureScalarDwordx3Loads = 136, |
153 | | FeatureScalarFlatScratchInsts = 137, |
154 | | FeatureScalarStores = 138, |
155 | | FeatureSeaIslands = 139, |
156 | | FeatureShaderCyclesHiLoRegisters = 140, |
157 | | FeatureShaderCyclesRegister = 141, |
158 | | FeatureSouthernIslands = 142, |
159 | | FeatureSupportsSRAMECC = 143, |
160 | | FeatureSupportsXNACK = 144, |
161 | | FeatureTgSplit = 145, |
162 | | FeatureTrapHandler = 146, |
163 | | FeatureTrigReducedRange = 147, |
164 | | FeatureTrue16BitInsts = 148, |
165 | | FeatureUnalignedAccessMode = 149, |
166 | | FeatureUnalignedBufferAccess = 150, |
167 | | FeatureUnalignedDSAccess = 151, |
168 | | FeatureUnalignedScratchAccess = 152, |
169 | | FeatureUnpackedD16VMem = 153, |
170 | | FeatureUserSGPRInit16Bug = 154, |
171 | | FeatureVALUTransUseHazard = 155, |
172 | | FeatureVGPRIndexMode = 156, |
173 | | FeatureVGPRSingleUseHintInsts = 157, |
174 | | FeatureVMEMtoScalarWriteHazard = 158, |
175 | | FeatureVOP3Literal = 159, |
176 | | FeatureVOP3P = 160, |
177 | | FeatureVOPD = 161, |
178 | | FeatureVcmpxExecWARHazard = 162, |
179 | | FeatureVcmpxPermlaneHazard = 163, |
180 | | FeatureVolcanicIslands = 164, |
181 | | FeatureVscnt = 165, |
182 | | FeatureWavefrontSize16 = 166, |
183 | | FeatureWavefrontSize32 = 167, |
184 | | FeatureWavefrontSize64 = 168, |
185 | | FeatureXNACK = 169, |
186 | | FullRate64Ops = 170, |
187 | | HalfRate64Ops = 171, |
188 | | NumSubtargetFeatures = 172 |
189 | | }; |
190 | | } // end namespace AMDGPU |
191 | | } // end namespace llvm |
192 | | |
193 | | #endif // GET_SUBTARGETINFO_ENUM |
194 | | |
195 | | |
196 | | #ifdef GET_SUBTARGETINFO_MACRO |
197 | | GET_SUBTARGETINFO_MACRO(AddNoCarryInsts, false, addNoCarryInsts) |
198 | | GET_SUBTARGETINFO_MACRO(AutoWaitcntBeforeBarrier, false, autoWaitcntBeforeBarrier) |
199 | | GET_SUBTARGETINFO_MACRO(BackOffBarrier, false, backOffBarrier) |
200 | | GET_SUBTARGETINFO_MACRO(CIInsts, false, cIInsts) |
201 | | GET_SUBTARGETINFO_MACRO(DumpCode, false, dumpCode) |
202 | | GET_SUBTARGETINFO_MACRO(DumpCode, false, dumpCode) |
203 | | GET_SUBTARGETINFO_MACRO(EnableCuMode, false, enableCuMode) |
204 | | GET_SUBTARGETINFO_MACRO(EnableDS128, false, enableDS128) |
205 | | GET_SUBTARGETINFO_MACRO(EnableFlatScratch, false, enableFlatScratch) |
206 | | GET_SUBTARGETINFO_MACRO(EnableLoadStoreOpt, false, enableLoadStoreOpt) |
207 | | GET_SUBTARGETINFO_MACRO(EnablePRTStrictNull, false, enablePRTStrictNull) |
208 | | GET_SUBTARGETINFO_MACRO(EnablePromoteAlloca, false, enablePromoteAlloca) |
209 | | GET_SUBTARGETINFO_MACRO(EnableRealTrue16Insts, false, enableRealTrue16Insts) |
210 | | GET_SUBTARGETINFO_MACRO(EnableSIScheduler, false, enableSIScheduler) |
211 | | GET_SUBTARGETINFO_MACRO(EnableSRAMECC, false, enableSRAMECC) |
212 | | GET_SUBTARGETINFO_MACRO(EnableTgSplit, false, enableTgSplit) |
213 | | GET_SUBTARGETINFO_MACRO(EnableUnsafeDSOffsetFolding, false, enableUnsafeDSOffsetFolding) |
214 | | GET_SUBTARGETINFO_MACRO(EnableXNACK, false, enableXNACK) |
215 | | GET_SUBTARGETINFO_MACRO(FMA, false, fMA) |
216 | | GET_SUBTARGETINFO_MACRO(FP64, false, fP64) |
217 | | GET_SUBTARGETINFO_MACRO(FastDenormalF32, false, fastDenormalF32) |
218 | | GET_SUBTARGETINFO_MACRO(FastFMAF32, false, fastFMAF32) |
219 | | GET_SUBTARGETINFO_MACRO(FeatureDisable, false, featureDisable) |
220 | | GET_SUBTARGETINFO_MACRO(FlatAddressSpace, false, flatAddressSpace) |
221 | | GET_SUBTARGETINFO_MACRO(FlatForGlobal, false, flatForGlobal) |
222 | | GET_SUBTARGETINFO_MACRO(FlatGlobalInsts, false, flatGlobalInsts) |
223 | | GET_SUBTARGETINFO_MACRO(FlatInstOffsets, false, flatInstOffsets) |
224 | | GET_SUBTARGETINFO_MACRO(FlatScratchInsts, false, flatScratchInsts) |
225 | | GET_SUBTARGETINFO_MACRO(FullRate64Ops, false, fullRate64Ops) |
226 | | GET_SUBTARGETINFO_MACRO(GCN3Encoding, false, gCN3Encoding) |
227 | | GET_SUBTARGETINFO_MACRO(GFX10Insts, false, gFX10Insts) |
228 | | GET_SUBTARGETINFO_MACRO(GFX10_3Insts, false, gFX10_3Insts) |
229 | | GET_SUBTARGETINFO_MACRO(GFX10_AEncoding, false, gFX10_AEncoding) |
230 | | GET_SUBTARGETINFO_MACRO(GFX10_BEncoding, false, gFX10_BEncoding) |
231 | | GET_SUBTARGETINFO_MACRO(GFX11Insts, false, gFX11Insts) |
232 | | GET_SUBTARGETINFO_MACRO(GFX12Insts, false, gFX12Insts) |
233 | | GET_SUBTARGETINFO_MACRO(GFX7GFX8GFX9Insts, false, gFX7GFX8GFX9Insts) |
234 | | GET_SUBTARGETINFO_MACRO(GFX8Insts, false, gFX8Insts) |
235 | | GET_SUBTARGETINFO_MACRO(GFX90AInsts, false, gFX90AInsts) |
236 | | GET_SUBTARGETINFO_MACRO(GFX940Insts, false, gFX940Insts) |
237 | | GET_SUBTARGETINFO_MACRO(GFX9Insts, false, gFX9Insts) |
238 | | GET_SUBTARGETINFO_MACRO(HalfRate64Ops, false, halfRate64Ops) |
239 | | GET_SUBTARGETINFO_MACRO(Has16BitInsts, false, has16BitInsts) |
240 | | GET_SUBTARGETINFO_MACRO(HasA16, false, hasA16) |
241 | | GET_SUBTARGETINFO_MACRO(HasApertureRegs, false, hasApertureRegs) |
242 | | GET_SUBTARGETINFO_MACRO(HasArchitectedFlatScratch, false, hasArchitectedFlatScratch) |
243 | | GET_SUBTARGETINFO_MACRO(HasArchitectedSGPRs, false, hasArchitectedSGPRs) |
244 | | GET_SUBTARGETINFO_MACRO(HasAtomicBufferGlobalPkAddF16Insts, false, hasAtomicBufferGlobalPkAddF16Insts) |
245 | | GET_SUBTARGETINFO_MACRO(HasAtomicBufferGlobalPkAddF16NoRtnInsts, false, hasAtomicBufferGlobalPkAddF16NoRtnInsts) |
246 | | GET_SUBTARGETINFO_MACRO(HasAtomicCSubNoRtnInsts, false, hasAtomicCSubNoRtnInsts) |
247 | | GET_SUBTARGETINFO_MACRO(HasAtomicDsPkAdd16Insts, false, hasAtomicDsPkAdd16Insts) |
248 | | GET_SUBTARGETINFO_MACRO(HasAtomicFaddNoRtnInsts, false, hasAtomicFaddNoRtnInsts) |
249 | | GET_SUBTARGETINFO_MACRO(HasAtomicFaddRtnInsts, false, hasAtomicFaddRtnInsts) |
250 | | GET_SUBTARGETINFO_MACRO(HasAtomicFlatPkAdd16Insts, false, hasAtomicFlatPkAdd16Insts) |
251 | | GET_SUBTARGETINFO_MACRO(HasAtomicGlobalPkAddBF16Inst, false, hasAtomicGlobalPkAddBF16Inst) |
252 | | GET_SUBTARGETINFO_MACRO(HasDLInsts, false, hasDLInsts) |
253 | | GET_SUBTARGETINFO_MACRO(HasDPALU_DPP, false, hasDPALU_DPP) |
254 | | GET_SUBTARGETINFO_MACRO(HasDPP, false, hasDPP) |
255 | | GET_SUBTARGETINFO_MACRO(HasDPP8, false, hasDPP8) |
256 | | GET_SUBTARGETINFO_MACRO(HasDPPSrc1SGPR, false, hasDPPSrc1SGPR) |
257 | | GET_SUBTARGETINFO_MACRO(HasDefaultComponentBroadcast, false, hasDefaultComponentBroadcast) |
258 | | GET_SUBTARGETINFO_MACRO(HasDefaultComponentZero, false, hasDefaultComponentZero) |
259 | | GET_SUBTARGETINFO_MACRO(HasDot10Insts, false, hasDot10Insts) |
260 | | GET_SUBTARGETINFO_MACRO(HasDot1Insts, false, hasDot1Insts) |
261 | | GET_SUBTARGETINFO_MACRO(HasDot2Insts, false, hasDot2Insts) |
262 | | GET_SUBTARGETINFO_MACRO(HasDot3Insts, false, hasDot3Insts) |
263 | | GET_SUBTARGETINFO_MACRO(HasDot4Insts, false, hasDot4Insts) |
264 | | GET_SUBTARGETINFO_MACRO(HasDot5Insts, false, hasDot5Insts) |
265 | | GET_SUBTARGETINFO_MACRO(HasDot6Insts, false, hasDot6Insts) |
266 | | GET_SUBTARGETINFO_MACRO(HasDot7Insts, false, hasDot7Insts) |
267 | | GET_SUBTARGETINFO_MACRO(HasDot8Insts, false, hasDot8Insts) |
268 | | GET_SUBTARGETINFO_MACRO(HasDot9Insts, false, hasDot9Insts) |
269 | | GET_SUBTARGETINFO_MACRO(HasDsSrc2Insts, false, hasDsSrc2Insts) |
270 | | GET_SUBTARGETINFO_MACRO(HasExtendedImageInsts, false, hasExtendedImageInsts) |
271 | | GET_SUBTARGETINFO_MACRO(HasFP8Insts, false, hasFP8Insts) |
272 | | GET_SUBTARGETINFO_MACRO(HasFlatAtomicFaddF32Inst, false, hasFlatAtomicFaddF32Inst) |
273 | | GET_SUBTARGETINFO_MACRO(HasFlatSegmentOffsetBug, false, hasFlatSegmentOffsetBug) |
274 | | GET_SUBTARGETINFO_MACRO(HasFmaMixInsts, false, hasFmaMixInsts) |
275 | | GET_SUBTARGETINFO_MACRO(HasFmacF64Inst, false, hasFmacF64Inst) |
276 | | GET_SUBTARGETINFO_MACRO(HasForceStoreSC0SC1, false, hasForceStoreSC0SC1) |
277 | | GET_SUBTARGETINFO_MACRO(HasG16, false, hasG16) |
278 | | GET_SUBTARGETINFO_MACRO(HasGDS, false, hasGDS) |
279 | | GET_SUBTARGETINFO_MACRO(HasGFX11FullVGPRs, false, hasGFX11FullVGPRs) |
280 | | GET_SUBTARGETINFO_MACRO(HasGWS, false, hasGWS) |
281 | | GET_SUBTARGETINFO_MACRO(HasGetWaveIdInst, false, hasGetWaveIdInst) |
282 | | GET_SUBTARGETINFO_MACRO(HasImageGather4D16Bug, false, hasImageGather4D16Bug) |
283 | | GET_SUBTARGETINFO_MACRO(HasImageInsts, false, hasImageInsts) |
284 | | GET_SUBTARGETINFO_MACRO(HasImageStoreD16Bug, false, hasImageStoreD16Bug) |
285 | | GET_SUBTARGETINFO_MACRO(HasInstFwdPrefetchBug, false, hasInstFwdPrefetchBug) |
286 | | GET_SUBTARGETINFO_MACRO(HasIntClamp, false, hasIntClamp) |
287 | | GET_SUBTARGETINFO_MACRO(HasInv2PiInlineImm, false, hasInv2PiInlineImm) |
288 | | GET_SUBTARGETINFO_MACRO(HasLdsBranchVmemWARHazard, false, hasLdsBranchVmemWARHazard) |
289 | | GET_SUBTARGETINFO_MACRO(HasMADIntraFwdBug, false, hasMADIntraFwdBug) |
290 | | GET_SUBTARGETINFO_MACRO(HasMAIInsts, false, hasMAIInsts) |
291 | | GET_SUBTARGETINFO_MACRO(HasMFMAInlineLiteralBug, false, hasMFMAInlineLiteralBug) |
292 | | GET_SUBTARGETINFO_MACRO(HasMSAALoadDstSelBug, false, hasMSAALoadDstSelBug) |
293 | | GET_SUBTARGETINFO_MACRO(HasMadMacF32Insts, false, hasMadMacF32Insts) |
294 | | GET_SUBTARGETINFO_MACRO(HasMadMixInsts, false, hasMadMixInsts) |
295 | | GET_SUBTARGETINFO_MACRO(HasMovrel, false, hasMovrel) |
296 | | GET_SUBTARGETINFO_MACRO(HasNSAClauseBug, false, hasNSAClauseBug) |
297 | | GET_SUBTARGETINFO_MACRO(HasNSAEncoding, false, hasNSAEncoding) |
298 | | GET_SUBTARGETINFO_MACRO(HasNSAtoVMEMBug, false, hasNSAtoVMEMBug) |
299 | | GET_SUBTARGETINFO_MACRO(HasNoDataDepHazard, false, hasNoDataDepHazard) |
300 | | GET_SUBTARGETINFO_MACRO(HasNoSdstCMPX, false, hasNoSdstCMPX) |
301 | | GET_SUBTARGETINFO_MACRO(HasOffset3fBug, false, hasOffset3fBug) |
302 | | GET_SUBTARGETINFO_MACRO(HasPackedFP32Ops, false, hasPackedFP32Ops) |
303 | | GET_SUBTARGETINFO_MACRO(HasPackedTID, false, hasPackedTID) |
304 | | GET_SUBTARGETINFO_MACRO(HasPartialNSAEncoding, false, hasPartialNSAEncoding) |
305 | | GET_SUBTARGETINFO_MACRO(HasPkFmacF16Inst, false, hasPkFmacF16Inst) |
306 | | GET_SUBTARGETINFO_MACRO(HasPseudoScalarTrans, false, hasPseudoScalarTrans) |
307 | | GET_SUBTARGETINFO_MACRO(HasR128A16, false, hasR128A16) |
308 | | GET_SUBTARGETINFO_MACRO(HasRestrictedSOffset, false, hasRestrictedSOffset) |
309 | | GET_SUBTARGETINFO_MACRO(HasSALUFloatInsts, false, hasSALUFloatInsts) |
310 | | GET_SUBTARGETINFO_MACRO(HasSDWA, false, hasSDWA) |
311 | | GET_SUBTARGETINFO_MACRO(HasSDWAMac, false, hasSDWAMac) |
312 | | GET_SUBTARGETINFO_MACRO(HasSDWAOmod, false, hasSDWAOmod) |
313 | | GET_SUBTARGETINFO_MACRO(HasSDWAOutModsVOPC, false, hasSDWAOutModsVOPC) |
314 | | GET_SUBTARGETINFO_MACRO(HasSDWAScalar, false, hasSDWAScalar) |
315 | | GET_SUBTARGETINFO_MACRO(HasSDWASdst, false, hasSDWASdst) |
316 | | GET_SUBTARGETINFO_MACRO(HasSMEMtoVectorWriteHazard, false, hasSMEMtoVectorWriteHazard) |
317 | | GET_SUBTARGETINFO_MACRO(HasSMemRealTime, false, hasSMemRealTime) |
318 | | GET_SUBTARGETINFO_MACRO(HasSMemTimeInst, false, hasSMemTimeInst) |
319 | | GET_SUBTARGETINFO_MACRO(HasScalarAtomics, false, hasScalarAtomics) |
320 | | GET_SUBTARGETINFO_MACRO(HasScalarDwordx3Loads, false, hasScalarDwordx3Loads) |
321 | | GET_SUBTARGETINFO_MACRO(HasScalarStores, false, hasScalarStores) |
322 | | GET_SUBTARGETINFO_MACRO(HasShaderCyclesHiLoRegisters, false, hasShaderCyclesHiLoRegisters) |
323 | | GET_SUBTARGETINFO_MACRO(HasShaderCyclesRegister, false, hasShaderCyclesRegister) |
324 | | GET_SUBTARGETINFO_MACRO(HasTrigReducedRange, false, hasTrigReducedRange) |
325 | | GET_SUBTARGETINFO_MACRO(HasTrue16BitInsts, false, hasTrue16BitInsts) |
326 | | GET_SUBTARGETINFO_MACRO(HasUnpackedD16VMem, false, hasUnpackedD16VMem) |
327 | | GET_SUBTARGETINFO_MACRO(HasVALUTransUseHazard, false, hasVALUTransUseHazard) |
328 | | GET_SUBTARGETINFO_MACRO(HasVGPRIndexMode, false, hasVGPRIndexMode) |
329 | | GET_SUBTARGETINFO_MACRO(HasVGPRSingleUseHintInsts, false, hasVGPRSingleUseHintInsts) |
330 | | GET_SUBTARGETINFO_MACRO(HasVMEMtoScalarWriteHazard, false, hasVMEMtoScalarWriteHazard) |
331 | | GET_SUBTARGETINFO_MACRO(HasVOP3Literal, false, hasVOP3Literal) |
332 | | GET_SUBTARGETINFO_MACRO(HasVOP3PInsts, false, hasVOP3PInsts) |
333 | | GET_SUBTARGETINFO_MACRO(HasVOPDInsts, false, hasVOPDInsts) |
334 | | GET_SUBTARGETINFO_MACRO(HasVcmpxExecWARHazard, false, hasVcmpxExecWARHazard) |
335 | | GET_SUBTARGETINFO_MACRO(HasVcmpxPermlaneHazard, false, hasVcmpxPermlaneHazard) |
336 | | GET_SUBTARGETINFO_MACRO(HasVscnt, false, hasVscnt) |
337 | | GET_SUBTARGETINFO_MACRO(KernargPreload, false, kernargPreload) |
338 | | GET_SUBTARGETINFO_MACRO(LDSMisalignedBug, false, lDSMisalignedBug) |
339 | | GET_SUBTARGETINFO_MACRO(MIMG_R128, false, mIMG_R128) |
340 | | GET_SUBTARGETINFO_MACRO(NegativeScratchOffsetBug, false, negativeScratchOffsetBug) |
341 | | GET_SUBTARGETINFO_MACRO(NegativeUnalignedScratchOffsetBug, false, negativeUnalignedScratchOffsetBug) |
342 | | GET_SUBTARGETINFO_MACRO(SGPRInitBug, false, sGPRInitBug) |
343 | | GET_SUBTARGETINFO_MACRO(ScalarFlatScratchInsts, false, scalarFlatScratchInsts) |
344 | | GET_SUBTARGETINFO_MACRO(SupportsSRAMECC, false, supportsSRAMECC) |
345 | | GET_SUBTARGETINFO_MACRO(SupportsXNACK, false, supportsXNACK) |
346 | | GET_SUBTARGETINFO_MACRO(TrapHandler, false, trapHandler) |
347 | | GET_SUBTARGETINFO_MACRO(UnalignedAccessMode, false, unalignedAccessMode) |
348 | | GET_SUBTARGETINFO_MACRO(UnalignedBufferAccess, false, unalignedBufferAccess) |
349 | | GET_SUBTARGETINFO_MACRO(UnalignedDSAccess, false, unalignedDSAccess) |
350 | | GET_SUBTARGETINFO_MACRO(UnalignedScratchAccess, false, unalignedScratchAccess) |
351 | | GET_SUBTARGETINFO_MACRO(UserSGPRInit16Bug, false, userSGPRInit16Bug) |
352 | | #undef GET_SUBTARGETINFO_MACRO |
353 | | #endif // GET_SUBTARGETINFO_MACRO |
354 | | |
355 | | |
356 | | #ifdef GET_SUBTARGETINFO_MC_DESC |
357 | | #undef GET_SUBTARGETINFO_MC_DESC |
358 | | |
359 | | namespace llvm { |
360 | | // Sorted (by key) array of values for CPU features. |
361 | | extern const llvm::SubtargetFeatureKV AMDGPUFeatureKV[] = { |
362 | | { "16-bit-insts", "Has i16/f16 instructions", AMDGPU::Feature16BitInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
363 | | { "DumpCode", "Dump MachineInstrs in the CodeEmitter", AMDGPU::FeatureDumpCode, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
364 | | { "a16", "Support A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands", AMDGPU::FeatureA16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
365 | | { "add-no-carry-insts", "Have VALU add/sub instructions without carry out", AMDGPU::FeatureAddNoCarryInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
366 | | { "aperture-regs", "Has Memory Aperture Base and Size Registers", AMDGPU::FeatureApertureRegs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
367 | | { "architected-flat-scratch", "Flat Scratch register is a readonly SPI initialized architected register", AMDGPU::FeatureArchitectedFlatScratch, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
368 | | { "architected-sgprs", "Enable the architected SGPRs", AMDGPU::FeatureArchitectedSGPRs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
369 | | { "atomic-buffer-global-pk-add-f16-insts", "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that can return original value", AMDGPU::FeatureAtomicBufferGlobalPkAddF16Insts, { { { 0x40000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
370 | | { "atomic-buffer-global-pk-add-f16-no-rtn-insts", "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that don't return original value", AMDGPU::FeatureAtomicBufferGlobalPkAddF16NoRtnInsts, { { { 0x40000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
371 | | { "atomic-csub-no-rtn-insts", "Has buffer_atomic_csub and global_atomic_csub instructions that don't return original value", AMDGPU::FeatureAtomicCSubNoRtnInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
372 | | { "atomic-ds-pk-add-16-insts", "Has ds_pk_add_bf16, ds_pk_add_f16, ds_pk_add_rtn_bf16, ds_pk_add_rtn_f16 instructions", AMDGPU::FeatureAtomicDsPkAdd16Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
373 | | { "atomic-fadd-no-rtn-insts", "Has buffer_atomic_add_f32 and global_atomic_add_f32 instructions that don't return original value", AMDGPU::FeatureAtomicFaddNoRtnInsts, { { { 0x40000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
374 | | { "atomic-fadd-rtn-insts", "Has buffer_atomic_add_f32 and global_atomic_add_f32 instructions that return original value", AMDGPU::FeatureAtomicFaddRtnInsts, { { { 0x40000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
375 | | { "atomic-flat-pk-add-16-insts", "Has flat_atomic_pk_add_f16 and flat_atomic_pk_add_bf16 instructions", AMDGPU::FeatureAtomicFlatPkAdd16Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
376 | | { "atomic-global-pk-add-bf16-inst", "Has global_atomic_pk_add_bf16 instruction", AMDGPU::FeatureAtomicGlobalPkAddBF16Inst, { { { 0x40000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
377 | | { "auto-waitcnt-before-barrier", "Hardware automatically inserts waitcnt before barrier", AMDGPU::FeatureAutoWaitcntBeforeBarrier, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
378 | | { "back-off-barrier", "Hardware supports backing off s_barrier if an exception occurs", AMDGPU::FeatureBackOffBarrier, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
379 | | { "ci-insts", "Additional instructions for CI+", AMDGPU::FeatureCIInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
380 | | { "cumode", "Enable CU wavefront execution mode", AMDGPU::FeatureCuMode, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
381 | | { "default-component-broadcast", "BUFFER/IMAGE store instructions set unspecified components to x component (GFX12)", AMDGPU::FeatureDefaultComponentBroadcast, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
382 | | { "default-component-zero", "BUFFER/IMAGE store instructions set unspecified components to zero (before GFX12)", AMDGPU::FeatureDefaultComponentZero, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
383 | | { "dl-insts", "Has v_fmac_f32 and v_xnor_b32 instructions", AMDGPU::FeatureDLInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
384 | | { "dot1-insts", "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions", AMDGPU::FeatureDot1Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
385 | | { "dot10-insts", "Has v_dot2_f32_f16 instruction", AMDGPU::FeatureDot10Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
386 | | { "dot2-insts", "Has v_dot2_i32_i16, v_dot2_u32_u16 instructions", AMDGPU::FeatureDot2Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
387 | | { "dot3-insts", "Has v_dot8c_i32_i4 instruction", AMDGPU::FeatureDot3Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
388 | | { "dot4-insts", "Has v_dot2c_i32_i16 instruction", AMDGPU::FeatureDot4Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
389 | | { "dot5-insts", "Has v_dot2c_f32_f16 instruction", AMDGPU::FeatureDot5Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
390 | | { "dot6-insts", "Has v_dot4c_i32_i8 instruction", AMDGPU::FeatureDot6Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
391 | | { "dot7-insts", "Has v_dot4_u32_u8, v_dot8_u32_u4 instructions", AMDGPU::FeatureDot7Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
392 | | { "dot8-insts", "Has v_dot4_i32_iu8, v_dot8_i32_iu4 instructions", AMDGPU::FeatureDot8Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
393 | | { "dot9-insts", "Has v_dot2_f16_f16, v_dot2_bf16_bf16, v_dot2_f32_bf16 instructions", AMDGPU::FeatureDot9Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
394 | | { "dpp", "Support DPP (Data Parallel Primitives) extension", AMDGPU::FeatureDPP, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
395 | | { "dpp-64bit", "Support DPP (Data Parallel Primitives) extension in DP ALU", AMDGPU::FeatureDPALU_DPP, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
396 | | { "dpp-src1-sgpr", "Support SGPR for Src1 of DPP instructions", AMDGPU::FeatureDPPSrc1SGPR, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
397 | | { "dpp8", "Support DPP8 (Data Parallel Primitives) extension", AMDGPU::FeatureDPP8, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
398 | | { "ds-src2-insts", "Has ds_*_src2 instructions", AMDGPU::FeatureDsSrc2Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
399 | | { "dumpcode", "Dump MachineInstrs in the CodeEmitter", AMDGPU::FeatureDumpCodeLower, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
400 | | { "enable-ds128", "Use ds_{read|write}_b128", AMDGPU::FeatureEnableDS128, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
401 | | { "enable-flat-scratch", "Use scratch_* flat memory instructions to access scratch", AMDGPU::FeatureEnableFlatScratch, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
402 | | { "enable-prt-strict-null", "Enable zeroing of result registers for sparse texture fetches", AMDGPU::FeatureEnablePRTStrictNull, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
403 | | { "extended-image-insts", "Support mips != 0, lod != 0, gather4, and get_lod", AMDGPU::FeatureExtendedImageInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
404 | | { "fast-denormal-f32", "Enabling denormals does not cause f32 instructions to run at f64 rates", AMDGPU::FeatureFastDenormalF32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
405 | | { "fast-fmaf", "Assuming f32 fma is at least as fast as mul + add", AMDGPU::FeatureFastFMAF32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
406 | | { "flat-address-space", "Support flat address space", AMDGPU::FeatureFlatAddressSpace, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
407 | | { "flat-atomic-fadd-f32-inst", "Has flat_atomic_add_f32 instruction", AMDGPU::FeatureFlatAtomicFaddF32Inst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
408 | | { "flat-for-global", "Force to generate flat instruction for global", AMDGPU::FeatureFlatForGlobal, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
409 | | { "flat-global-insts", "Have global_* flat memory instructions", AMDGPU::FeatureFlatGlobalInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
410 | | { "flat-inst-offsets", "Flat instructions have immediate offset addressing mode", AMDGPU::FeatureFlatInstOffsets, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
411 | | { "flat-scratch-insts", "Have scratch_* flat memory instructions", AMDGPU::FeatureFlatScratchInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
412 | | { "flat-segment-offset-bug", "GFX10 bug where inst_offset is ignored when flat instructions access global memory", AMDGPU::FeatureFlatSegmentOffsetBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
413 | | { "fma-mix-insts", "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions", AMDGPU::FeatureFmaMixInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
414 | | { "fmacf64-inst", "Has v_fmac_f64 instruction", AMDGPU::FeatureFmacF64Inst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
415 | | { "fmaf", "Enable single precision FMA (not as fast as mul+add, but fused)", AMDGPU::FeatureFMA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
416 | | { "force-store-sc0-sc1", "Has SC0 and SC1 on stores", AMDGPU::FeatureForceStoreSC0SC1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
417 | | { "fp64", "Enable double precision operations", AMDGPU::FeatureFP64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
418 | | { "fp8-insts", "Has fp8 and bf8 instructions", AMDGPU::FeatureFP8Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
419 | | { "full-rate-64-ops", "Most fp64 instructions are full rate", AMDGPU::FullRate64Ops, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
420 | | { "g16", "Support G16 for 16-bit gradient image operands", AMDGPU::FeatureG16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
421 | | { "gcn3-encoding", "Encoding format for VI", AMDGPU::FeatureGCN3Encoding, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
422 | | { "gds", "Has Global Data Share", AMDGPU::FeatureGDS, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
423 | | { "get-wave-id-inst", "Has s_get_waveid_in_workgroup instruction", AMDGPU::FeatureGetWaveIdInst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
424 | | { "gfx10", "GFX10 GPU generation", AMDGPU::FeatureGFX10, { { { 0xa5cf20000131000fULL, 0x504304088191002aULL, 0x2180c00033ULL, 0x0ULL, 0x0ULL, } } } }, |
425 | | { "gfx10-3-insts", "Additional instructions for GFX10.3", AMDGPU::FeatureGFX10_3Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
426 | | { "gfx10-insts", "Additional instructions for GFX10+", AMDGPU::FeatureGFX10Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
427 | | { "gfx10_a-encoding", "Has BVH ray tracing instructions", AMDGPU::FeatureGFX10_AEncoding, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
428 | | { "gfx10_b-encoding", "Encoding format GFX10_B", AMDGPU::FeatureGFX10_BEncoding, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
429 | | { "gfx11", "GFX11 GPU generation", AMDGPU::FeatureGFX11, { { { 0xa5cf20000131000fULL, 0x430408818109eaULL, 0x2380d00000ULL, 0x0ULL, 0x0ULL, } } } }, |
430 | | { "gfx11-full-vgprs", "GFX11 with 50% more physical VGPRs and 50% larger allocation granule than GFX10", AMDGPU::FeatureGFX11FullVGPRs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
431 | | { "gfx11-insts", "Additional instructions for GFX11+", AMDGPU::FeatureGFX11Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
432 | | { "gfx12", "GFX12 GPU generation", AMDGPU::FeatureGFX12, { { { 0x25cf000000b1000fULL, 0x430408818029eaULL, 0x2380d00000ULL, 0x0ULL, 0x0ULL, } } } }, |
433 | | { "gfx12-insts", "Additional instructions for GFX12+", AMDGPU::FeatureGFX12Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
434 | | { "gfx7-gfx8-gfx9-insts", "Instructions shared in GFX7, GFX8, GFX9", AMDGPU::FeatureGFX7GFX8GFX9Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
435 | | { "gfx8-insts", "Additional instructions for GFX8+", AMDGPU::FeatureGFX8Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
436 | | { "gfx9", "GFX9 GPU generation", AMDGPU::FeatureGFX9, { { { 0x41cf00000111000fULL, 0x520040008181000bULL, 0x10110c106b3ULL, 0x0ULL, 0x0ULL, } } } }, |
437 | | { "gfx9-insts", "Additional instructions for GFX9+", AMDGPU::FeatureGFX9Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
438 | | { "gfx90a-insts", "Additional instructions for GFX90A+", AMDGPU::FeatureGFX90AInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
439 | | { "gfx940-insts", "Additional instructions for GFX940+", AMDGPU::FeatureGFX940Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
440 | | { "gws", "Has Global Wave Sync", AMDGPU::FeatureGWS, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
441 | | { "half-rate-64-ops", "Most fp64 instructions are half rate instead of quarter", AMDGPU::HalfRate64Ops, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
442 | | { "image-gather4-d16-bug", "Image Gather4 D16 hardware bug", AMDGPU::FeatureImageGather4D16Bug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
443 | | { "image-insts", "Support image instructions", AMDGPU::FeatureImageInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
444 | | { "image-store-d16-bug", "Image Store D16 hardware bug", AMDGPU::FeatureImageStoreD16Bug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
445 | | { "inst-fwd-prefetch-bug", "S_INST_PREFETCH instruction causes shader to hang", AMDGPU::FeatureInstFwdPrefetchBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
446 | | { "int-clamp-insts", "Support clamp for integer destination", AMDGPU::FeatureIntClamp, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
447 | | { "inv-2pi-inline-imm", "Has 1 / (2 * pi) as inline immediate", AMDGPU::FeatureInv2PiInlineImm, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
448 | | { "kernarg-preload", "Hardware supports preloading of kernel arguments in user SGPRs.", AMDGPU::FeatureKernargPreload, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
449 | | { "lds-branch-vmem-war-hazard", "Switching between LDS and VMEM-tex not waiting VM_VSRC=0", AMDGPU::FeatureLdsBranchVmemWARHazard, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
450 | | { "lds-misaligned-bug", "Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode", AMDGPU::FeatureLdsMisalignedBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
451 | | { "ldsbankcount16", "The number of LDS banks per compute unit.", AMDGPU::FeatureLDSBankCount16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
452 | | { "ldsbankcount32", "The number of LDS banks per compute unit.", AMDGPU::FeatureLDSBankCount32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
453 | | { "load-store-opt", "Enable SI load/store optimizer pass", AMDGPU::FeatureEnableLoadStoreOpt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
454 | | { "localmemorysize32768", "The size of local memory in bytes", AMDGPU::FeatureLocalMemorySize32768, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
455 | | { "localmemorysize65536", "The size of local memory in bytes", AMDGPU::FeatureLocalMemorySize65536, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
456 | | { "mad-intra-fwd-bug", "MAD_U64/I64 intra instruction forwarding bug", AMDGPU::FeatureMADIntraFwdBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
457 | | { "mad-mac-f32-insts", "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions", AMDGPU::FeatureMadMacF32Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
458 | | { "mad-mix-insts", "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions", AMDGPU::FeatureMadMixInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
459 | | { "mai-insts", "Has mAI instructions", AMDGPU::FeatureMAIInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
460 | | { "max-private-element-size-16", "Maximum private access size may be 16", AMDGPU::FeatureMaxPrivateElementSize16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
461 | | { "max-private-element-size-4", "Maximum private access size may be 4", AMDGPU::FeatureMaxPrivateElementSize4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
462 | | { "max-private-element-size-8", "Maximum private access size may be 8", AMDGPU::FeatureMaxPrivateElementSize8, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
463 | | { "mfma-inline-literal-bug", "MFMA cannot use inline literal as SrcC", AMDGPU::FeatureMFMAInlineLiteralBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
464 | | { "mimg-r128", "Support 128-bit texture resources", AMDGPU::FeatureMIMG_R128, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
465 | | { "movrel", "Has v_movrel*_b32 instructions", AMDGPU::FeatureMovrel, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
466 | | { "msaa-load-dst-sel-bug", "MSAA loads not honoring dst_sel bug", AMDGPU::FeatureMSAALoadDstSelBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
467 | | { "negative-scratch-offset-bug", "Negative immediate offsets in scratch instructions with an SGPR offset page fault on GFX9", AMDGPU::FeatureNegativeScratchOffsetBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
468 | | { "negative-unaligned-scratch-offset-bug", "Scratch instructions with a VGPR offset and a negative immediate offset that is not a multiple of 4 read wrong memory on GFX10", AMDGPU::FeatureNegativeUnalignedScratchOffsetBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
469 | | { "no-data-dep-hazard", "Does not need SW waitstates", AMDGPU::FeatureNoDataDepHazard, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
470 | | { "no-sdst-cmpx", "V_CMPX does not write VCC/SGPR in addition to EXEC", AMDGPU::FeatureNoSdstCMPX, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
471 | | { "nsa-clause-bug", "MIMG-NSA in a hard clause has unpredictable results on GFX10.1", AMDGPU::FeatureNSAClauseBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
472 | | { "nsa-encoding", "Support NSA encoding for image instructions", AMDGPU::FeatureNSAEncoding, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
473 | | { "nsa-to-vmem-bug", "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero", AMDGPU::FeatureNSAtoVMEMBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
474 | | { "offset-3f-bug", "Branch offset of 3f hardware bug", AMDGPU::FeatureOffset3fBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
475 | | { "packed-fp32-ops", "Support packed fp32 instructions", AMDGPU::FeaturePackedFP32Ops, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
476 | | { "packed-tid", "Workitem IDs are packed into v0 at kernel launch", AMDGPU::FeaturePackedTID, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
477 | | { "partial-nsa-encoding", "Support partial NSA encoding for image instructions", AMDGPU::FeaturePartialNSAEncoding, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
478 | | { "pk-fmac-f16-inst", "Has v_pk_fmac_f16 instruction", AMDGPU::FeaturePkFmacF16Inst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
479 | | { "promote-alloca", "Enable promote alloca pass", AMDGPU::FeaturePromoteAlloca, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
480 | | { "pseudo-scalar-trans", "Has Pseudo Scalar Transcendental instructions", AMDGPU::FeaturePseudoScalarTrans, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
481 | | { "r128-a16", "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128", AMDGPU::FeatureR128A16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
482 | | { "real-true16", "Use true 16-bit registers", AMDGPU::FeatureRealTrue16Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
483 | | { "restricted-soffset", "Has restricted SOffset (immediate not supported).", AMDGPU::FeatureHasRestrictedSOffset, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
484 | | { "s-memrealtime", "Has s_memrealtime instruction", AMDGPU::FeatureSMemRealTime, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
485 | | { "s-memtime-inst", "Has s_memtime instruction", AMDGPU::FeatureSMemTimeInst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
486 | | { "salu-float", "Has SALU floating point instructions", AMDGPU::FeatureSALUFloatInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
487 | | { "scalar-atomics", "Has atomic scalar memory instructions", AMDGPU::FeatureScalarAtomics, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
488 | | { "scalar-dwordx3-loads", "Has 96-bit scalar load instructions", AMDGPU::FeatureScalarDwordx3Loads, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
489 | | { "scalar-flat-scratch-insts", "Have s_scratch_* flat memory instructions", AMDGPU::FeatureScalarFlatScratchInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
490 | | { "scalar-stores", "Has store scalar memory instructions", AMDGPU::FeatureScalarStores, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
491 | | { "sdwa", "Support SDWA (Sub-DWORD Addressing) extension", AMDGPU::FeatureSDWA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
492 | | { "sdwa-mav", "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension", AMDGPU::FeatureSDWAMac, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
493 | | { "sdwa-omod", "Support OMod with SDWA (Sub-DWORD Addressing) extension", AMDGPU::FeatureSDWAOmod, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
494 | | { "sdwa-out-mods-vopc", "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension", AMDGPU::FeatureSDWAOutModsVOPC, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
495 | | { "sdwa-scalar", "Support scalar register with SDWA (Sub-DWORD Addressing) extension", AMDGPU::FeatureSDWAScalar, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
496 | | { "sdwa-sdst", "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension", AMDGPU::FeatureSDWASdst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
497 | | { "sea-islands", "SEA_ISLANDS GPU generation", AMDGPU::FeatureSeaIslands, { { { 0x8009201001010000ULL, 0x42880110001ULL, 0x10000480020ULL, 0x0ULL, 0x0ULL, } } } }, |
498 | | { "sgpr-init-bug", "VI SGPR initialization bug requiring a fixed SGPR allocation size", AMDGPU::FeatureSGPRInitBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
499 | | { "shader-cycles-hi-lo-registers", "Has SHADER_CYCLES_HI/LO hardware registers", AMDGPU::FeatureShaderCyclesHiLoRegisters, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
500 | | { "shader-cycles-register", "Has SHADER_CYCLES hardware register", AMDGPU::FeatureShaderCyclesRegister, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
501 | | { "si-scheduler", "Enable SI Machine Scheduler", AMDGPU::FeatureEnableSIScheduler, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
502 | | { "smem-to-vector-write-hazard", "s_load_dword followed by v_cmp page faults", AMDGPU::FeatureSMEMtoVectorWriteHazard, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
503 | | { "southern-islands", "SOUTHERN_ISLANDS GPU generation", AMDGPU::FeatureSouthernIslands, { { { 0x8001201001000000ULL, 0x42848110000ULL, 0x10000080020ULL, 0x0ULL, 0x0ULL, } } } }, |
504 | | { "sramecc", "Enable SRAMECC", AMDGPU::FeatureSRAMECC, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
505 | | { "sramecc-support", "Hardware supports SRAMECC", AMDGPU::FeatureSupportsSRAMECC, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
506 | | { "tgsplit", "Enable threadgroup split execution", AMDGPU::FeatureTgSplit, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
507 | | { "trap-handler", "Trap handler support", AMDGPU::FeatureTrapHandler, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
508 | | { "trig-reduced-range", "Requires use of fract on arguments to trig instructions", AMDGPU::FeatureTrigReducedRange, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
509 | | { "true16", "True 16-bit operand instructions", AMDGPU::FeatureTrue16BitInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
510 | | { "unaligned-access-mode", "Enable unaligned global, local and region loads and stores if the hardware supports it", AMDGPU::FeatureUnalignedAccessMode, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
511 | | { "unaligned-buffer-access", "Hardware supports unaligned global loads and stores", AMDGPU::FeatureUnalignedBufferAccess, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
512 | | { "unaligned-ds-access", "Hardware supports unaligned local and region loads and stores", AMDGPU::FeatureUnalignedDSAccess, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
513 | | { "unaligned-scratch-access", "Support unaligned scratch loads and stores", AMDGPU::FeatureUnalignedScratchAccess, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
514 | | { "unpacked-d16-vmem", "Has unpacked d16 vmem instructions", AMDGPU::FeatureUnpackedD16VMem, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
515 | | { "unsafe-ds-offset-folding", "Force using DS instruction immediate offsets on SI", AMDGPU::FeatureEnableUnsafeDSOffsetFolding, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
516 | | { "user-sgpr-init16-bug", "Bug requiring at least 16 user+system SGPRs to be enabled", AMDGPU::FeatureUserSGPRInit16Bug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
517 | | { "valu-trans-use-hazard", "Hazard when TRANS instructions are closely followed by a use of the result", AMDGPU::FeatureVALUTransUseHazard, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
518 | | { "vcmpx-exec-war-hazard", "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)", AMDGPU::FeatureVcmpxExecWARHazard, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
519 | | { "vcmpx-permlane-hazard", "TODO: describe me", AMDGPU::FeatureVcmpxPermlaneHazard, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
520 | | { "vgpr-index-mode", "Has VGPR mode register indexing", AMDGPU::FeatureVGPRIndexMode, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
521 | | { "vgpr-singleuse-hint", "Has single-use VGPR hint instructions", AMDGPU::FeatureVGPRSingleUseHintInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
522 | | { "vmem-to-scalar-write-hazard", "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution.", AMDGPU::FeatureVMEMtoScalarWriteHazard, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
523 | | { "volcanic-islands", "VOLCANIC_ISLANDS GPU generation", AMDGPU::FeatureVolcanicIslands, { { { 0xc00b201001110001ULL, 0xb000042881910003ULL, 0x10010480430ULL, 0x0ULL, 0x0ULL, } } } }, |
524 | | { "vop3-literal", "Can use one literal in VOP3", AMDGPU::FeatureVOP3Literal, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
525 | | { "vop3p", "Has VOP3P packed instructions", AMDGPU::FeatureVOP3P, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
526 | | { "vopd", "Has VOPD dual issue wave32 instructions", AMDGPU::FeatureVOPD, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
527 | | { "vscnt", "Has separate store vscnt counter", AMDGPU::FeatureVscnt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
528 | | { "wavefrontsize16", "The number of threads per wavefront", AMDGPU::FeatureWavefrontSize16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
529 | | { "wavefrontsize32", "The number of threads per wavefront", AMDGPU::FeatureWavefrontSize32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
530 | | { "wavefrontsize64", "The number of threads per wavefront", AMDGPU::FeatureWavefrontSize64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
531 | | { "xnack", "Enable XNACK support", AMDGPU::FeatureXNACK, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
532 | | { "xnack-support", "Hardware supports XNACK", AMDGPU::FeatureSupportsXNACK, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
533 | | }; |
534 | | |
535 | | #ifdef DBGFIELD |
536 | | #error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro" |
537 | | #endif |
538 | | #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) |
539 | | #define DBGFIELD(x) x, |
540 | | #else |
541 | | #define DBGFIELD(x) |
542 | | #endif |
543 | | |
544 | | // =============================================================== |
545 | | // Data tables for the new per-operand machine model. |
546 | | |
547 | | // {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle} |
548 | | extern const llvm::MCWriteProcResEntry AMDGPUWriteProcResTable[] = { |
549 | | { 0, 0, 0 }, // Invalid |
550 | | { 4, 1, 0}, // #1 |
551 | | { 5, 1, 0}, // #2 |
552 | | { 6, 1, 0}, // #3 |
553 | | { 3, 1, 0}, // #4 |
554 | | { 3, 2, 0}, // #5 |
555 | | { 2, 1, 0}, // #6 |
556 | | { 3, 1, 0}, // #7 |
557 | | { 6, 1, 0}, // #8 |
558 | | { 1, 1, 0}, // #9 |
559 | | { 5, 2, 0}, // #10 |
560 | | { 7, 2, 0}, // #11 |
561 | | { 7, 8, 0}, // #12 |
562 | | { 7, 16, 0}, // #13 |
563 | | { 4, 1, 0}, // #14 |
564 | | { 7, 1, 0}, // #15 |
565 | | { 4, 1, 0}, // #16 |
566 | | { 8, 1, 0}, // #17 |
567 | | { 3, 1, 0}, // #18 |
568 | | { 4, 1, 0}, // #19 |
569 | | { 3, 2, 0}, // #20 |
570 | | { 4, 2, 0}, // #21 |
571 | | { 2, 1, 0}, // #22 |
572 | | { 4, 1, 0}, // #23 |
573 | | { 3, 1, 0}, // #24 |
574 | | { 4, 2, 0}, // #25 |
575 | | { 8, 1, 0}, // #26 |
576 | | { 4, 2, 0}, // #27 |
577 | | { 5, 1, 0}, // #28 |
578 | | { 7, 1, 0}, // #29 |
579 | | { 4, 1, 0}, // #30 |
580 | | { 6, 1, 0}, // #31 |
581 | | { 4, 1, 0}, // #32 |
582 | | { 6, 1, 0}, // #33 |
583 | | { 7, 1, 0}, // #34 |
584 | | { 4, 2, 0}, // #35 |
585 | | { 7, 2, 0}, // #36 |
586 | | { 3, 1, 0}, // #37 |
587 | | { 4, 2, 0}, // #38 |
588 | | { 7, 1, 0}, // #39 |
589 | | { 4, 2, 0}, // #40 |
590 | | { 5, 1, 0}, // #41 |
591 | | { 6, 1, 0}, // #42 |
592 | | { 4, 2, 0}, // #43 |
593 | | { 6, 2, 0}, // #44 |
594 | | { 7, 4, 0} // #45 |
595 | | }; // AMDGPUWriteProcResTable |
596 | | |
597 | | // {Cycles, WriteResourceID} |
598 | | extern const llvm::MCWriteLatencyEntry AMDGPUWriteLatencyTable[] = { |
599 | | { 0, 0}, // Invalid |
600 | | { 1, 0}, // #1 WriteSALU_Write32Bit_WriteFloatFMA_WriteDoubleAdd_Write64Bit_WriteDoubleCvt_WriteIntMul |
601 | | {80, 0}, // #2 WriteVMEM |
602 | | { 5, 0}, // #3 WriteLDS_WriteSMEM_Write32Bit_WriteFloatCvt_WriteFloatFMA |
603 | | { 5, 0}, // #4 WriteLDS_Write32Bit |
604 | | { 5, 0}, // #5 WriteLDS |
605 | | { 4, 0}, // #6 WriteExport_WriteTrans32_WriteFloatCvt_WriteDoubleCvt_WriteQuarterRate32_WriteIntMul_WriteSFPU_WriteTrans64_Write4PassDGEMM_Write4PassMAI |
606 | | { 8, 0}, // #7 WriteBranch_WriteDoubleAdd_Write8PassMAI_WriteQuarterRate32_WriteIntMul |
607 | | {500, 0}, // #8 WriteBarrier |
608 | | { 1, 0}, // #9 WriteSALU |
609 | | { 2, 0}, // #10 Write64Bit_Write2PassMAI_WriteSALU_WriteDoubleAdd |
610 | | { 1, 0}, // #11 Write32Bit_WriteFloatFMA_WriteSALU_WriteDouble_WriteIntMul_Write64Bit |
611 | | { 1, 0}, // #12 WriteSALU_Write32Bit_Write64Bit |
612 | | {16, 0}, // #13 WriteFloatFMA_WriteDouble_WriteTrans64_Write16PassMAI_WriteExport_Write8PassDGEMM |
613 | | {16, 0}, // #14 WriteFloatFMA_WriteDouble |
614 | | { 1, 0}, // #15 WriteSALU |
615 | | { 4, 0}, // #16 WriteIntMul_WriteDouble |
616 | | { 1, 0}, // #17 WriteSALU |
617 | | { 2, 0}, // #18 Write64Bit |
618 | | { 2, 0}, // #19 Write64Bit |
619 | | {320, 0}, // #20 WriteVMEM |
620 | | {20, 0}, // #21 WriteLDS_WriteSMEM |
621 | | {20, 0}, // #22 WriteLDS |
622 | | {20, 0}, // #23 WriteLDS |
623 | | {32, 0}, // #24 WriteBranch |
624 | | {2000, 0}, // #25 WriteBarrier |
625 | | { 2, 0}, // #26 WriteSALU |
626 | | { 6, 0}, // #27 Write64Bit |
627 | | { 5, 0}, // #28 Write32Bit_WriteFloatFMA |
628 | | { 2, 0}, // #29 WriteSALU |
629 | | {22, 0}, // #30 WriteDoubleAdd_WriteDoubleCvt |
630 | | {10, 0}, // #31 WriteTrans32 |
631 | | {22, 0}, // #32 WriteDouble |
632 | | { 2, 0}, // #33 WriteSALU |
633 | | { 8, 0}, // #34 WriteIntMul |
634 | | { 2, 0}, // #35 WriteSALU |
635 | | {24, 0}, // #36 WriteTrans64 |
636 | | { 6, 0}, // #37 Write64Bit |
637 | | { 6, 0}, // #38 Write64Bit |
638 | | {38, 0}, // #39 WriteDoubleAdd_WriteDoubleCvt |
639 | | {38, 0}, // #40 WriteDouble |
640 | | { 2, 0}, // #41 WriteSALU |
641 | | {40, 0}, // #42 WriteTrans64 |
642 | | { 7, 0} // #43 WritePseudoScalarTrans |
643 | | }; // AMDGPUWriteLatencyTable |
644 | | |
645 | | // {UseIdx, WriteResourceID, Cycles} |
646 | | extern const llvm::MCReadAdvanceEntry AMDGPUReadAdvanceTable[] = { |
647 | | {0, 0, 0}, // Invalid |
648 | | {0, 0, -4}, // #1 |
649 | | {0, 0, -2} // #2 |
650 | | }; // AMDGPUReadAdvanceTable |
651 | | |
652 | | // {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#} |
653 | | static const llvm::MCSchedClassDesc SIQuarterSpeedModelSchedClasses[] = { |
654 | | {DBGFIELD("InvalidSchedClass") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, |
655 | | {DBGFIELD("NullALU_WriteSALU") 1, false, false, true, 1, 1, 1, 1, 0, 0}, // #1 |
656 | | {DBGFIELD("NullALU_Write32Bit") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #2 |
657 | | {DBGFIELD("NullALU_WriteVMEM") 1, false, false, true, 3, 1, 2, 1, 0, 0}, // #3 |
658 | | {DBGFIELD("NullALU_WriteLDS") 1, false, false, true, 4, 1, 3, 1, 0, 0}, // #4 |
659 | | {DBGFIELD("NullALU_WriteLDS_WriteLDS") 2, false, false, true, 5, 1, 4, 2, 0, 0}, // #5 |
660 | | {DBGFIELD("NullALU_WriteExport") 1, false, false, true, 6, 1, 6, 1, 0, 0}, // #6 |
661 | | {DBGFIELD("NullALU_WriteVMEM_WriteLDS") 2, false, false, true, 7, 2, 2, 2, 0, 0}, // #7 |
662 | | {DBGFIELD("WriteBranch") 1, false, false, true, 9, 1, 7, 1, 0, 0}, // #8 |
663 | | {DBGFIELD("NullALU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #9 |
664 | | {DBGFIELD("NullALU_WriteBranch") 1, false, false, true, 9, 1, 7, 1, 0, 0}, // #10 |
665 | | {DBGFIELD("NullALU_WriteSFPU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #11 |
666 | | {DBGFIELD("NullALU_WriteSMEM") 1, false, false, true, 4, 1, 3, 1, 0, 0}, // #12 |
667 | | {DBGFIELD("NullALU_WriteBarrier") 1, false, false, true, 9, 1, 8, 1, 0, 0}, // #13 |
668 | | {DBGFIELD("NullALU_WriteSALU_Write64Bit") 2, false, false, true, 1, 2, 9, 2, 0, 0}, // #14 |
669 | | {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #15 |
670 | | {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false, true, 2, 1, 7, 1, 0, 0}, // #16 |
671 | | {DBGFIELD("NullALU_Write64Bit") 1, false, false, true, 2, 1, 10, 1, 0, 0}, // #17 |
672 | | {DBGFIELD("NullALU_WriteTrans32") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #18 |
673 | | {DBGFIELD("NullALU_WriteFloatCvt") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #19 |
674 | | {DBGFIELD("NullALU_WriteDoubleCvt") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #20 |
675 | | {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false, true, 2, 1, 13, 1, 0, 0}, // #21 |
676 | | {DBGFIELD("NullALU_WriteDouble") 1, false, false, true, 2, 1, 13, 1, 0, 0}, // #22 |
677 | | {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false, true, 1, 2, 14, 2, 0, 0}, // #23 |
678 | | {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false, true, 1, 2, 14, 2, 0, 0}, // #24 |
679 | | {DBGFIELD("NullALU_WriteIntMul_WriteSALU") 2, false, false, true, 1, 2, 16, 2, 0, 0}, // #25 |
680 | | {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #26 |
681 | | {DBGFIELD("NullALU_WriteIntMul") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #27 |
682 | | {DBGFIELD("NullALU_WriteTrans64") 1, false, false, true, 2, 1, 13, 1, 0, 0}, // #28 |
683 | | {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false, true, 10, 1, 18, 2, 0, 0}, // #29 |
684 | | {DBGFIELD("NullALU_WritePseudoScalarTrans") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #30 |
685 | | {DBGFIELD("NullALU_Write32Bit_Write32Bit") 2, false, false, true, 10, 1, 11, 2, 0, 0}, // #31 |
686 | | {DBGFIELD("COPY") 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #32 |
687 | | {DBGFIELD("V_ACCVGPR_WRITE_B32_e64") 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #33 |
688 | | {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 11, 1, 10, 1, 1, 1}, // #34 |
689 | | {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #35 |
690 | | {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 13, 1, 13, 1, 1, 1}, // #36 |
691 | | {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 11, 1, 10, 1, 1, 1}, // #37 |
692 | | {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #38 |
693 | | {DBGFIELD("V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #39 |
694 | | {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #40 |
695 | | {DBGFIELD("V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #41 |
696 | | {DBGFIELD("V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #42 |
697 | | {DBGFIELD("V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd") 1, false, false, true, 13, 1, 13, 1, 1, 1}, // #43 |
698 | | {DBGFIELD("V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 13, 1, 13, 1, 1, 1}, // #44 |
699 | | {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd") 1, false, false, true, 13, 1, 13, 1, 1, 1}, // #45 |
700 | | {DBGFIELD("V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #46 |
701 | | {DBGFIELD("V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #47 |
702 | | {DBGFIELD("Write32Bit") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #48 |
703 | | {DBGFIELD("Write64Bit") 1, false, false, true, 2, 1, 10, 1, 0, 0}, // #49 |
704 | | {DBGFIELD("WriteSALU") 1, false, false, true, 1, 1, 1, 1, 0, 0}, // #50 |
705 | | {DBGFIELD("Write64Bit_MIVGPRRead") 1, false, false, true, 2, 1, 10, 1, 2, 1}, // #51 |
706 | | {DBGFIELD("Write64Bit_ReadDefault") 1, false, false, true, 2, 1, 10, 1, 0, 0}, // #52 |
707 | | }; // SIQuarterSpeedModelSchedClasses |
708 | | |
709 | | // {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#} |
710 | | static const llvm::MCSchedClassDesc GFX10SpeedModelSchedClasses[] = { |
711 | | {DBGFIELD("InvalidSchedClass") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, |
712 | | {DBGFIELD("NullALU_WriteSALU") 1, false, false, true, 1, 2, 10, 1, 0, 0}, // #1 |
713 | | {DBGFIELD("NullALU_Write32Bit") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #2 |
714 | | {DBGFIELD("NullALU_WriteVMEM") 1, false, false, true, 16, 2, 20, 1, 0, 0}, // #3 |
715 | | {DBGFIELD("NullALU_WriteLDS") 1, false, false, true, 18, 2, 21, 1, 0, 0}, // #4 |
716 | | {DBGFIELD("NullALU_WriteLDS_WriteLDS") 2, false, false, true, 20, 2, 22, 2, 0, 0}, // #5 |
717 | | {DBGFIELD("NullALU_WriteExport") 1, false, false, true, 22, 2, 13, 1, 0, 0}, // #6 |
718 | | {DBGFIELD("NullALU_WriteVMEM_WriteLDS") 2, false, false, true, 24, 3, 20, 2, 0, 0}, // #7 |
719 | | {DBGFIELD("WriteBranch") 1, false, false, true, 9, 1, 24, 1, 0, 0}, // #8 |
720 | | {DBGFIELD("NullALU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #9 |
721 | | {DBGFIELD("NullALU_WriteBranch") 1, false, false, true, 9, 1, 24, 1, 0, 0}, // #10 |
722 | | {DBGFIELD("NullALU_WriteSFPU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #11 |
723 | | {DBGFIELD("NullALU_WriteSMEM") 1, false, false, true, 18, 2, 21, 1, 0, 0}, // #12 |
724 | | {DBGFIELD("NullALU_WriteBarrier") 1, false, false, true, 9, 1, 25, 1, 0, 0}, // #13 |
725 | | {DBGFIELD("NullALU_WriteSALU_Write64Bit") 2, false, false, true, 27, 3, 26, 2, 0, 0}, // #14 |
726 | | {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false, true, 27, 3, 28, 2, 0, 0}, // #15 |
727 | | {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false, true, 14, 2, 30, 1, 0, 0}, // #16 |
728 | | {DBGFIELD("NullALU_Write64Bit") 1, false, false, true, 14, 2, 27, 1, 0, 0}, // #17 |
729 | | {DBGFIELD("NullALU_WriteTrans32") 1, false, false, true, 30, 2, 31, 1, 0, 0}, // #18 |
730 | | {DBGFIELD("NullALU_WriteFloatCvt") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #19 |
731 | | {DBGFIELD("NullALU_WriteDoubleCvt") 1, false, false, true, 14, 2, 30, 1, 0, 0}, // #20 |
732 | | {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #21 |
733 | | {DBGFIELD("NullALU_WriteDouble") 1, false, false, true, 14, 2, 30, 1, 0, 0}, // #22 |
734 | | {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false, true, 27, 3, 28, 2, 0, 0}, // #23 |
735 | | {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false, true, 27, 3, 32, 2, 0, 0}, // #24 |
736 | | {DBGFIELD("NullALU_WriteIntMul_WriteSALU") 2, false, false, true, 27, 3, 34, 2, 0, 0}, // #25 |
737 | | {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false, true, 14, 2, 7, 1, 0, 0}, // #26 |
738 | | {DBGFIELD("NullALU_WriteIntMul") 1, false, false, true, 14, 2, 7, 1, 0, 0}, // #27 |
739 | | {DBGFIELD("NullALU_WriteTrans64") 1, false, false, true, 32, 3, 36, 1, 0, 0}, // #28 |
740 | | {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false, true, 35, 2, 37, 2, 0, 0}, // #29 |
741 | | {DBGFIELD("NullALU_WritePseudoScalarTrans") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #30 |
742 | | {DBGFIELD("NullALU_Write32Bit_Write32Bit") 2, false, false, true, 35, 2, 3, 2, 0, 0}, // #31 |
743 | | {DBGFIELD("COPY") 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #32 |
744 | | {DBGFIELD("V_ACCVGPR_WRITE_B32_e64") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #33 |
745 | | {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #34 |
746 | | {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #35 |
747 | | {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #36 |
748 | | {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #37 |
749 | | {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #38 |
750 | | {DBGFIELD("V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #39 |
751 | | {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #40 |
752 | | {DBGFIELD("V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #41 |
753 | | {DBGFIELD("V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #42 |
754 | | {DBGFIELD("V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #43 |
755 | | {DBGFIELD("V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #44 |
756 | | {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #45 |
757 | | {DBGFIELD("V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #46 |
758 | | {DBGFIELD("V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #47 |
759 | | {DBGFIELD("Write32Bit") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #48 |
760 | | {DBGFIELD("Write64Bit") 1, false, false, true, 14, 2, 27, 1, 0, 0}, // #49 |
761 | | {DBGFIELD("WriteSALU") 1, false, false, true, 1, 2, 10, 1, 0, 0}, // #50 |
762 | | {DBGFIELD("Write64Bit_MIVGPRRead") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #51 |
763 | | {DBGFIELD("Write64Bit_ReadDefault") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #52 |
764 | | }; // GFX10SpeedModelSchedClasses |
765 | | |
766 | | // {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#} |
767 | | static const llvm::MCSchedClassDesc GFX11SpeedModelSchedClasses[] = { |
768 | | {DBGFIELD("InvalidSchedClass") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, |
769 | | {DBGFIELD("NullALU_WriteSALU") 1, false, false, true, 1, 2, 10, 1, 0, 0}, // #1 |
770 | | {DBGFIELD("NullALU_Write32Bit") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #2 |
771 | | {DBGFIELD("NullALU_WriteVMEM") 1, false, false, true, 16, 2, 20, 1, 0, 0}, // #3 |
772 | | {DBGFIELD("NullALU_WriteLDS") 1, false, false, true, 18, 2, 21, 1, 0, 0}, // #4 |
773 | | {DBGFIELD("NullALU_WriteLDS_WriteLDS") 2, false, false, true, 20, 2, 21, 2, 0, 0}, // #5 |
774 | | {DBGFIELD("NullALU_WriteExport") 1, false, false, true, 22, 2, 13, 1, 0, 0}, // #6 |
775 | | {DBGFIELD("NullALU_WriteVMEM_WriteLDS") 2, false, false, true, 24, 3, 20, 2, 0, 0}, // #7 |
776 | | {DBGFIELD("WriteBranch") 1, false, false, true, 9, 1, 24, 1, 0, 0}, // #8 |
777 | | {DBGFIELD("NullALU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #9 |
778 | | {DBGFIELD("NullALU_WriteBranch") 1, false, false, true, 9, 1, 24, 1, 0, 0}, // #10 |
779 | | {DBGFIELD("NullALU_WriteSFPU") 1, false, false, true, 1, 2, 6, 1, 0, 0}, // #11 |
780 | | {DBGFIELD("NullALU_WriteSMEM") 1, false, false, true, 18, 2, 21, 1, 0, 0}, // #12 |
781 | | {DBGFIELD("NullALU_WriteBarrier") 1, false, false, true, 9, 1, 25, 1, 0, 0}, // #13 |
782 | | {DBGFIELD("NullALU_WriteSALU_Write64Bit") 2, false, false, true, 27, 3, 26, 2, 0, 0}, // #14 |
783 | | {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false, true, 27, 3, 28, 2, 0, 0}, // #15 |
784 | | {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false, true, 14, 2, 39, 1, 0, 0}, // #16 |
785 | | {DBGFIELD("NullALU_Write64Bit") 1, false, false, true, 14, 2, 27, 1, 0, 0}, // #17 |
786 | | {DBGFIELD("NullALU_WriteTrans32") 1, false, false, true, 30, 2, 31, 1, 0, 0}, // #18 |
787 | | {DBGFIELD("NullALU_WriteFloatCvt") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #19 |
788 | | {DBGFIELD("NullALU_WriteDoubleCvt") 1, false, false, true, 14, 2, 39, 1, 0, 0}, // #20 |
789 | | {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #21 |
790 | | {DBGFIELD("NullALU_WriteDouble") 1, false, false, true, 14, 2, 39, 1, 0, 0}, // #22 |
791 | | {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false, true, 27, 3, 28, 2, 0, 0}, // #23 |
792 | | {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false, true, 27, 3, 40, 2, 0, 0}, // #24 |
793 | | {DBGFIELD("NullALU_WriteIntMul_WriteSALU") 2, false, false, true, 27, 3, 34, 2, 0, 0}, // #25 |
794 | | {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false, true, 14, 2, 7, 1, 0, 0}, // #26 |
795 | | {DBGFIELD("NullALU_WriteIntMul") 1, false, false, true, 14, 2, 7, 1, 0, 0}, // #27 |
796 | | {DBGFIELD("NullALU_WriteTrans64") 1, false, false, true, 32, 3, 42, 1, 0, 0}, // #28 |
797 | | {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false, true, 35, 2, 37, 2, 0, 0}, // #29 |
798 | | {DBGFIELD("NullALU_WritePseudoScalarTrans") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #30 |
799 | | {DBGFIELD("NullALU_Write32Bit_Write32Bit") 2, false, false, true, 35, 2, 3, 2, 0, 0}, // #31 |
800 | | {DBGFIELD("COPY") 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #32 |
801 | | {DBGFIELD("V_ACCVGPR_WRITE_B32_e64") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #33 |
802 | | {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #34 |
803 | | {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #35 |
804 | | {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #36 |
805 | | {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #37 |
806 | | {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #38 |
807 | | {DBGFIELD("V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #39 |
808 | | {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #40 |
809 | | {DBGFIELD("V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #41 |
810 | | {DBGFIELD("V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #42 |
811 | | {DBGFIELD("V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #43 |
812 | | {DBGFIELD("V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #44 |
813 | | {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #45 |
814 | | {DBGFIELD("V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #46 |
815 | | {DBGFIELD("V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #47 |
816 | | {DBGFIELD("Write32Bit") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #48 |
817 | | {DBGFIELD("Write64Bit") 1, false, false, true, 14, 2, 27, 1, 0, 0}, // #49 |
818 | | {DBGFIELD("WriteSALU") 1, false, false, true, 1, 2, 10, 1, 0, 0}, // #50 |
819 | | {DBGFIELD("Write64Bit_MIVGPRRead") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #51 |
820 | | {DBGFIELD("Write64Bit_ReadDefault") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #52 |
821 | | }; // GFX11SpeedModelSchedClasses |
822 | | |
823 | | // {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#} |
824 | | static const llvm::MCSchedClassDesc GFX12SpeedModelSchedClasses[] = { |
825 | | {DBGFIELD("InvalidSchedClass") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, |
826 | | {DBGFIELD("NullALU_WriteSALU") 1, false, false, false, 1, 2, 10, 1, 0, 0}, // #1 |
827 | | {DBGFIELD("NullALU_Write32Bit") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #2 |
828 | | {DBGFIELD("NullALU_WriteVMEM") 1, false, false, false, 14, 2, 20, 1, 0, 0}, // #3 |
829 | | {DBGFIELD("NullALU_WriteLDS") 1, false, false, false, 18, 2, 21, 1, 0, 0}, // #4 |
830 | | {DBGFIELD("NullALU_WriteLDS_WriteLDS") 2, false, false, false, 20, 2, 21, 2, 0, 0}, // #5 |
831 | | {DBGFIELD("NullALU_WriteExport") 1, false, false, false, 22, 2, 13, 1, 0, 0}, // #6 |
832 | | {DBGFIELD("NullALU_WriteVMEM_WriteLDS") 2, false, false, false, 37, 3, 20, 2, 0, 0}, // #7 |
833 | | {DBGFIELD("WriteBranch") 1, false, false, false, 9, 1, 24, 1, 0, 0}, // #8 |
834 | | {DBGFIELD("NullALU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #9 |
835 | | {DBGFIELD("NullALU_WriteBranch") 1, false, false, false, 9, 1, 24, 1, 0, 0}, // #10 |
836 | | {DBGFIELD("NullALU_WriteSFPU") 1, false, false, false, 1, 2, 6, 1, 0, 0}, // #11 |
837 | | {DBGFIELD("NullALU_WriteSMEM") 1, false, false, false, 18, 2, 21, 1, 0, 0}, // #12 |
838 | | {DBGFIELD("NullALU_WriteBarrier") 1, false, false, false, 9, 1, 25, 1, 0, 0}, // #13 |
839 | | {DBGFIELD("NullALU_WriteSALU_Write64Bit") 2, false, false, false, 40, 3, 26, 2, 0, 0}, // #14 |
840 | | {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false, false, 40, 3, 28, 2, 0, 0}, // #15 |
841 | | {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false, false, 30, 2, 39, 1, 0, 0}, // #16 |
842 | | {DBGFIELD("NullALU_Write64Bit") 1, false, false, false, 30, 2, 27, 1, 0, 0}, // #17 |
843 | | {DBGFIELD("NullALU_WriteTrans32") 1, false, false, false, 30, 2, 31, 1, 0, 0}, // #18 |
844 | | {DBGFIELD("NullALU_WriteFloatCvt") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #19 |
845 | | {DBGFIELD("NullALU_WriteDoubleCvt") 1, false, false, false, 30, 2, 39, 1, 0, 0}, // #20 |
846 | | {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #21 |
847 | | {DBGFIELD("NullALU_WriteDouble") 1, false, false, false, 30, 2, 39, 1, 0, 0}, // #22 |
848 | | {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false, false, 40, 3, 28, 2, 0, 0}, // #23 |
849 | | {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false, false, 40, 3, 40, 2, 0, 0}, // #24 |
850 | | {DBGFIELD("NullALU_WriteIntMul_WriteSALU") 2, false, false, false, 40, 3, 34, 2, 0, 0}, // #25 |
851 | | {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false, false, 30, 2, 7, 1, 0, 0}, // #26 |
852 | | {DBGFIELD("NullALU_WriteIntMul") 1, false, false, false, 30, 2, 7, 1, 0, 0}, // #27 |
853 | | {DBGFIELD("NullALU_WriteTrans64") 1, false, false, false, 30, 2, 42, 1, 0, 0}, // #28 |
854 | | {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false, false, 43, 2, 37, 2, 0, 0}, // #29 |
855 | | {DBGFIELD("NullALU_WritePseudoScalarTrans") 1, false, false, false, 30, 2, 43, 1, 0, 0}, // #30 |
856 | | {DBGFIELD("NullALU_Write32Bit_Write32Bit") 2, false, false, false, 43, 2, 3, 2, 0, 0}, // #31 |
857 | | {DBGFIELD("COPY") 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #32 |
858 | | {DBGFIELD("V_ACCVGPR_WRITE_B32_e64") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #33 |
859 | | {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #34 |
860 | | {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #35 |
861 | | {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #36 |
862 | | {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #37 |
863 | | {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #38 |
864 | | {DBGFIELD("V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #39 |
865 | | {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #40 |
866 | | {DBGFIELD("V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #41 |
867 | | {DBGFIELD("V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #42 |
868 | | {DBGFIELD("V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #43 |
869 | | {DBGFIELD("V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #44 |
870 | | {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #45 |
871 | | {DBGFIELD("V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #46 |
872 | | {DBGFIELD("V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #47 |
873 | | {DBGFIELD("Write32Bit") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #48 |
874 | | {DBGFIELD("Write64Bit") 1, false, false, false, 30, 2, 27, 1, 0, 0}, // #49 |
875 | | {DBGFIELD("WriteSALU") 1, false, false, false, 1, 2, 10, 1, 0, 0}, // #50 |
876 | | {DBGFIELD("Write64Bit_MIVGPRRead") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #51 |
877 | | {DBGFIELD("Write64Bit_ReadDefault") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #52 |
878 | | }; // GFX12SpeedModelSchedClasses |
879 | | |
880 | | // {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#} |
881 | | static const llvm::MCSchedClassDesc SIFullSpeedModelSchedClasses[] = { |
882 | | {DBGFIELD("InvalidSchedClass") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, |
883 | | {DBGFIELD("NullALU_WriteSALU") 1, false, false, true, 1, 1, 1, 1, 0, 0}, // #1 |
884 | | {DBGFIELD("NullALU_Write32Bit") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #2 |
885 | | {DBGFIELD("NullALU_WriteVMEM") 1, false, false, true, 3, 1, 2, 1, 0, 0}, // #3 |
886 | | {DBGFIELD("NullALU_WriteLDS") 1, false, false, true, 4, 1, 3, 1, 0, 0}, // #4 |
887 | | {DBGFIELD("NullALU_WriteLDS_WriteLDS") 2, false, false, true, 5, 1, 3, 2, 0, 0}, // #5 |
888 | | {DBGFIELD("NullALU_WriteExport") 1, false, false, true, 6, 1, 6, 1, 0, 0}, // #6 |
889 | | {DBGFIELD("NullALU_WriteVMEM_WriteLDS") 2, false, false, true, 7, 2, 2, 2, 0, 0}, // #7 |
890 | | {DBGFIELD("WriteBranch") 1, false, false, true, 9, 1, 7, 1, 0, 0}, // #8 |
891 | | {DBGFIELD("NullALU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #9 |
892 | | {DBGFIELD("NullALU_WriteBranch") 1, false, false, true, 9, 1, 7, 1, 0, 0}, // #10 |
893 | | {DBGFIELD("NullALU_WriteSFPU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #11 |
894 | | {DBGFIELD("NullALU_WriteSMEM") 1, false, false, true, 4, 1, 3, 1, 0, 0}, // #12 |
895 | | {DBGFIELD("NullALU_WriteBarrier") 1, false, false, true, 9, 1, 8, 1, 0, 0}, // #13 |
896 | | {DBGFIELD("NullALU_WriteSALU_Write64Bit") 2, false, false, true, 1, 2, 9, 2, 0, 0}, // #14 |
897 | | {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #15 |
898 | | {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false, true, 2, 1, 10, 1, 0, 0}, // #16 |
899 | | {DBGFIELD("NullALU_Write64Bit") 1, false, false, true, 2, 1, 10, 1, 0, 0}, // #17 |
900 | | {DBGFIELD("NullALU_WriteTrans32") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #18 |
901 | | {DBGFIELD("NullALU_WriteFloatCvt") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #19 |
902 | | {DBGFIELD("NullALU_WriteDoubleCvt") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #20 |
903 | | {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #21 |
904 | | {DBGFIELD("NullALU_WriteDouble") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #22 |
905 | | {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #23 |
906 | | {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false, true, 1, 2, 16, 2, 0, 0}, // #24 |
907 | | {DBGFIELD("NullALU_WriteIntMul_WriteSALU") 2, false, false, true, 1, 2, 16, 2, 0, 0}, // #25 |
908 | | {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #26 |
909 | | {DBGFIELD("NullALU_WriteIntMul") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #27 |
910 | | {DBGFIELD("NullALU_WriteTrans64") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #28 |
911 | | {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false, true, 10, 1, 18, 2, 0, 0}, // #29 |
912 | | {DBGFIELD("NullALU_WritePseudoScalarTrans") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #30 |
913 | | {DBGFIELD("NullALU_Write32Bit_Write32Bit") 2, false, false, true, 10, 1, 11, 2, 0, 0}, // #31 |
914 | | {DBGFIELD("COPY") 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #32 |
915 | | {DBGFIELD("V_ACCVGPR_WRITE_B32_e64") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #33 |
916 | | {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #34 |
917 | | {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #35 |
918 | | {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #36 |
919 | | {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #37 |
920 | | {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #38 |
921 | | {DBGFIELD("V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #39 |
922 | | {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #40 |
923 | | {DBGFIELD("V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #41 |
924 | | {DBGFIELD("V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #42 |
925 | | {DBGFIELD("V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #43 |
926 | | {DBGFIELD("V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #44 |
927 | | {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #45 |
928 | | {DBGFIELD("V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #46 |
929 | | {DBGFIELD("V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #47 |
930 | | {DBGFIELD("Write32Bit") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #48 |
931 | | {DBGFIELD("Write64Bit") 1, false, false, true, 2, 1, 10, 1, 0, 0}, // #49 |
932 | | {DBGFIELD("WriteSALU") 1, false, false, true, 1, 1, 1, 1, 0, 0}, // #50 |
933 | | {DBGFIELD("Write64Bit_MIVGPRRead") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #51 |
934 | | {DBGFIELD("Write64Bit_ReadDefault") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #52 |
935 | | }; // SIFullSpeedModelSchedClasses |
936 | | |
937 | | // {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#} |
938 | | static const llvm::MCSchedClassDesc SIDPFullSpeedModelSchedClasses[] = { |
939 | | {DBGFIELD("InvalidSchedClass") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, |
940 | | {DBGFIELD("NullALU_WriteSALU") 1, false, false, true, 1, 1, 1, 1, 0, 0}, // #1 |
941 | | {DBGFIELD("NullALU_Write32Bit") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #2 |
942 | | {DBGFIELD("NullALU_WriteVMEM") 1, false, false, true, 3, 1, 2, 1, 0, 0}, // #3 |
943 | | {DBGFIELD("NullALU_WriteLDS") 1, false, false, true, 4, 1, 3, 1, 0, 0}, // #4 |
944 | | {DBGFIELD("NullALU_WriteLDS_WriteLDS") 2, false, false, true, 5, 1, 3, 2, 0, 0}, // #5 |
945 | | {DBGFIELD("NullALU_WriteExport") 1, false, false, true, 6, 1, 6, 1, 0, 0}, // #6 |
946 | | {DBGFIELD("NullALU_WriteVMEM_WriteLDS") 2, false, false, true, 7, 2, 2, 2, 0, 0}, // #7 |
947 | | {DBGFIELD("WriteBranch") 1, false, false, true, 9, 1, 7, 1, 0, 0}, // #8 |
948 | | {DBGFIELD("NullALU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #9 |
949 | | {DBGFIELD("NullALU_WriteBranch") 1, false, false, true, 9, 1, 7, 1, 0, 0}, // #10 |
950 | | {DBGFIELD("NullALU_WriteSFPU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #11 |
951 | | {DBGFIELD("NullALU_WriteSMEM") 1, false, false, true, 4, 1, 3, 1, 0, 0}, // #12 |
952 | | {DBGFIELD("NullALU_WriteBarrier") 1, false, false, true, 9, 1, 8, 1, 0, 0}, // #13 |
953 | | {DBGFIELD("NullALU_WriteSALU_Write64Bit") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #14 |
954 | | {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #15 |
955 | | {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #16 |
956 | | {DBGFIELD("NullALU_Write64Bit") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #17 |
957 | | {DBGFIELD("NullALU_WriteTrans32") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #18 |
958 | | {DBGFIELD("NullALU_WriteFloatCvt") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #19 |
959 | | {DBGFIELD("NullALU_WriteDoubleCvt") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #20 |
960 | | {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #21 |
961 | | {DBGFIELD("NullALU_WriteDouble") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #22 |
962 | | {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #23 |
963 | | {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #24 |
964 | | {DBGFIELD("NullALU_WriteIntMul_WriteSALU") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #25 |
965 | | {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #26 |
966 | | {DBGFIELD("NullALU_WriteIntMul") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #27 |
967 | | {DBGFIELD("NullALU_WriteTrans64") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #28 |
968 | | {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false, true, 10, 1, 11, 2, 0, 0}, // #29 |
969 | | {DBGFIELD("NullALU_WritePseudoScalarTrans") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #30 |
970 | | {DBGFIELD("NullALU_Write32Bit_Write32Bit") 2, false, false, true, 10, 1, 11, 2, 0, 0}, // #31 |
971 | | {DBGFIELD("COPY") 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #32 |
972 | | {DBGFIELD("V_ACCVGPR_WRITE_B32_e64") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #33 |
973 | | {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 2, 1, 6, 1, 1, 1}, // #34 |
974 | | {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 2, 1, 13, 1, 1, 1}, // #35 |
975 | | {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 13, 1, 13, 1, 1, 1}, // #36 |
976 | | {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 11, 1, 10, 1, 1, 1}, // #37 |
977 | | {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #38 |
978 | | {DBGFIELD("V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #39 |
979 | | {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #40 |
980 | | {DBGFIELD("V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #41 |
981 | | {DBGFIELD("V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #42 |
982 | | {DBGFIELD("V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd") 1, false, false, true, 13, 1, 13, 1, 1, 1}, // #43 |
983 | | {DBGFIELD("V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 13, 1, 13, 1, 1, 1}, // #44 |
984 | | {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd") 1, false, false, true, 13, 1, 13, 1, 1, 1}, // #45 |
985 | | {DBGFIELD("V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #46 |
986 | | {DBGFIELD("V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #47 |
987 | | {DBGFIELD("Write32Bit") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #48 |
988 | | {DBGFIELD("Write64Bit") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #49 |
989 | | {DBGFIELD("WriteSALU") 1, false, false, true, 1, 1, 1, 1, 0, 0}, // #50 |
990 | | {DBGFIELD("Write64Bit_MIVGPRRead") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #51 |
991 | | {DBGFIELD("Write64Bit_ReadDefault") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #52 |
992 | | }; // SIDPFullSpeedModelSchedClasses |
993 | | |
994 | | // {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#} |
995 | | static const llvm::MCSchedClassDesc SIDPGFX940FullSpeedModelSchedClasses[] = { |
996 | | {DBGFIELD("InvalidSchedClass") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, |
997 | | {DBGFIELD("NullALU_WriteSALU") 1, false, false, true, 1, 1, 1, 1, 0, 0}, // #1 |
998 | | {DBGFIELD("NullALU_Write32Bit") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #2 |
999 | | {DBGFIELD("NullALU_WriteVMEM") 1, false, false, true, 3, 1, 2, 1, 0, 0}, // #3 |
1000 | | {DBGFIELD("NullALU_WriteLDS") 1, false, false, true, 4, 1, 3, 1, 0, 0}, // #4 |
1001 | | {DBGFIELD("NullALU_WriteLDS_WriteLDS") 2, false, false, true, 5, 1, 3, 2, 0, 0}, // #5 |
1002 | | {DBGFIELD("NullALU_WriteExport") 1, false, false, true, 6, 1, 6, 1, 0, 0}, // #6 |
1003 | | {DBGFIELD("NullALU_WriteVMEM_WriteLDS") 2, false, false, true, 7, 2, 2, 2, 0, 0}, // #7 |
1004 | | {DBGFIELD("WriteBranch") 1, false, false, true, 9, 1, 7, 1, 0, 0}, // #8 |
1005 | | {DBGFIELD("NullALU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #9 |
1006 | | {DBGFIELD("NullALU_WriteBranch") 1, false, false, true, 9, 1, 7, 1, 0, 0}, // #10 |
1007 | | {DBGFIELD("NullALU_WriteSFPU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #11 |
1008 | | {DBGFIELD("NullALU_WriteSMEM") 1, false, false, true, 4, 1, 3, 1, 0, 0}, // #12 |
1009 | | {DBGFIELD("NullALU_WriteBarrier") 1, false, false, true, 9, 1, 8, 1, 0, 0}, // #13 |
1010 | | {DBGFIELD("NullALU_WriteSALU_Write64Bit") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #14 |
1011 | | {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #15 |
1012 | | {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false, false, 2, 1, 1, 1, 0, 0}, // #16 |
1013 | | {DBGFIELD("NullALU_Write64Bit") 1, false, false, false, 2, 1, 1, 1, 0, 0}, // #17 |
1014 | | {DBGFIELD("NullALU_WriteTrans32") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #18 |
1015 | | {DBGFIELD("NullALU_WriteFloatCvt") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #19 |
1016 | | {DBGFIELD("NullALU_WriteDoubleCvt") 1, false, false, false, 2, 1, 1, 1, 0, 0}, // #20 |
1017 | | {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false, false, 2, 1, 1, 1, 0, 0}, // #21 |
1018 | | {DBGFIELD("NullALU_WriteDouble") 1, false, false, false, 2, 1, 1, 1, 0, 0}, // #22 |
1019 | | {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #23 |
1020 | | {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #24 |
1021 | | {DBGFIELD("NullALU_WriteIntMul_WriteSALU") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #25 |
1022 | | {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #26 |
1023 | | {DBGFIELD("NullALU_WriteIntMul") 1, false, false, false, 2, 1, 1, 1, 0, 0}, // #27 |
1024 | | {DBGFIELD("NullALU_WriteTrans64") 1, false, false, false, 2, 1, 6, 1, 0, 0}, // #28 |
1025 | | {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false, false, 10, 1, 11, 2, 0, 0}, // #29 |
1026 | | {DBGFIELD("NullALU_WritePseudoScalarTrans") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #30 |
1027 | | {DBGFIELD("NullALU_Write32Bit_Write32Bit") 2, false, false, true, 10, 1, 11, 2, 0, 0}, // #31 |
1028 | | {DBGFIELD("COPY") 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #32 |
1029 | | {DBGFIELD("V_ACCVGPR_WRITE_B32_e64") 1, false, false, false, 2, 1, 1, 1, 0, 0}, // #33 |
1030 | | {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 2, 1, 6, 1, 1, 1}, // #34 |
1031 | | {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 2, 1, 13, 1, 1, 1}, // #35 |
1032 | | {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 13, 1, 13, 1, 1, 1}, // #36 |
1033 | | {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 11, 1, 10, 1, 1, 1}, // #37 |
1034 | | {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #38 |
1035 | | {DBGFIELD("V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd") 1, false, false, true, 45, 1, 6, 1, 1, 1}, // #39 |
1036 | | {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi") 1, false, false, true, 45, 1, 6, 1, 1, 1}, // #40 |
1037 | | {DBGFIELD("V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd") 1, false, false, true, 45, 1, 6, 1, 1, 1}, // #41 |
1038 | | {DBGFIELD("V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #42 |
1039 | | {DBGFIELD("V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #43 |
1040 | | {DBGFIELD("V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #44 |
1041 | | {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #45 |
1042 | | {DBGFIELD("V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940") 1, false, false, true, 45, 1, 6, 1, 1, 1}, // #46 |
1043 | | {DBGFIELD("V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #47 |
1044 | | {DBGFIELD("Write32Bit") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #48 |
1045 | | {DBGFIELD("Write64Bit") 1, false, false, false, 2, 1, 1, 1, 0, 0}, // #49 |
1046 | | {DBGFIELD("WriteSALU") 1, false, false, true, 1, 1, 1, 1, 0, 0}, // #50 |
1047 | | {DBGFIELD("Write64Bit_MIVGPRRead") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #51 |
1048 | | {DBGFIELD("Write64Bit_ReadDefault") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #52 |
1049 | | }; // SIDPGFX940FullSpeedModelSchedClasses |
1050 | | |
1051 | | #undef DBGFIELD |
1052 | | |
1053 | | static const llvm::MCSchedModel NoSchedModel = { |
1054 | | MCSchedModel::DefaultIssueWidth, |
1055 | | MCSchedModel::DefaultMicroOpBufferSize, |
1056 | | MCSchedModel::DefaultLoopMicroOpBufferSize, |
1057 | | MCSchedModel::DefaultLoadLatency, |
1058 | | MCSchedModel::DefaultHighLatency, |
1059 | | MCSchedModel::DefaultMispredictPenalty, |
1060 | | false, // PostRAScheduler |
1061 | | false, // CompleteModel |
1062 | | false, // EnableIntervals |
1063 | | 0, // Processor ID |
1064 | | nullptr, nullptr, 0, 0, // No instruction-level machine model. |
1065 | | nullptr, // No Itinerary |
1066 | | nullptr // No extra processor descriptor |
1067 | | }; |
1068 | | |
1069 | | static const unsigned SIQuarterSpeedModelProcResourceSubUnits[] = { |
1070 | | 0, // Invalid |
1071 | | }; |
1072 | | |
1073 | | // {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin} |
1074 | | static const llvm::MCProcResourceDesc SIQuarterSpeedModelProcResources[] = { |
1075 | | {"InvalidUnit", 0, 0, 0, 0}, |
1076 | | {"HWBranch", 1, 0, 1, nullptr}, // #1 |
1077 | | {"HWExport", 1, 0, 1, nullptr}, // #2 |
1078 | | {"HWLGKM", 1, 0, 1, nullptr}, // #3 |
1079 | | {"HWSALU", 1, 0, 1, nullptr}, // #4 |
1080 | | {"HWVALU", 1, 0, 1, nullptr}, // #5 |
1081 | | {"HWVMEM", 1, 0, 1, nullptr}, // #6 |
1082 | | {"HWXDL", 1, 0, 0, nullptr}, // #7 |
1083 | | }; |
1084 | | |
1085 | | static const llvm::MCSchedModel SIQuarterSpeedModel = { |
1086 | | 1, // IssueWidth |
1087 | | 1, // MicroOpBufferSize |
1088 | | MCSchedModel::DefaultLoopMicroOpBufferSize, |
1089 | | MCSchedModel::DefaultLoadLatency, |
1090 | | MCSchedModel::DefaultHighLatency, |
1091 | | 20, // MispredictPenalty |
1092 | | true, // PostRAScheduler |
1093 | | true, // CompleteModel |
1094 | | false, // EnableIntervals |
1095 | | 1, // Processor ID |
1096 | | SIQuarterSpeedModelProcResources, |
1097 | | SIQuarterSpeedModelSchedClasses, |
1098 | | 8, |
1099 | | 53, |
1100 | | nullptr, // No Itinerary |
1101 | | nullptr // No extra processor descriptor |
1102 | | }; |
1103 | | |
1104 | | static const unsigned GFX10SpeedModelProcResourceSubUnits[] = { |
1105 | | 0, // Invalid |
1106 | | }; |
1107 | | |
1108 | | // {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin} |
1109 | | static const llvm::MCProcResourceDesc GFX10SpeedModelProcResources[] = { |
1110 | | {"InvalidUnit", 0, 0, 0, 0}, |
1111 | | {"HWBranch", 1, 0, 1, nullptr}, // #1 |
1112 | | {"HWExport", 1, 0, 1, nullptr}, // #2 |
1113 | | {"HWLGKM", 1, 0, 1, nullptr}, // #3 |
1114 | | {"HWRC", 1, 0, 1, nullptr}, // #4 |
1115 | | {"HWSALU", 1, 0, 1, nullptr}, // #5 |
1116 | | {"HWTransVALU", 1, 0, 1, nullptr}, // #6 |
1117 | | {"HWVALU", 1, 0, 1, nullptr}, // #7 |
1118 | | {"HWVMEM", 1, 0, 1, nullptr}, // #8 |
1119 | | }; |
1120 | | |
1121 | | static const llvm::MCSchedModel GFX10SpeedModel = { |
1122 | | 1, // IssueWidth |
1123 | | 1, // MicroOpBufferSize |
1124 | | MCSchedModel::DefaultLoopMicroOpBufferSize, |
1125 | | MCSchedModel::DefaultLoadLatency, |
1126 | | MCSchedModel::DefaultHighLatency, |
1127 | | 20, // MispredictPenalty |
1128 | | true, // PostRAScheduler |
1129 | | true, // CompleteModel |
1130 | | false, // EnableIntervals |
1131 | | 2, // Processor ID |
1132 | | GFX10SpeedModelProcResources, |
1133 | | GFX10SpeedModelSchedClasses, |
1134 | | 9, |
1135 | | 53, |
1136 | | nullptr, // No Itinerary |
1137 | | nullptr // No extra processor descriptor |
1138 | | }; |
1139 | | |
1140 | | static const unsigned GFX11SpeedModelProcResourceSubUnits[] = { |
1141 | | 0, // Invalid |
1142 | | }; |
1143 | | |
1144 | | // {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin} |
1145 | | static const llvm::MCProcResourceDesc GFX11SpeedModelProcResources[] = { |
1146 | | {"InvalidUnit", 0, 0, 0, 0}, |
1147 | | {"HWBranch", 1, 0, 1, nullptr}, // #1 |
1148 | | {"HWExport", 1, 0, 1, nullptr}, // #2 |
1149 | | {"HWLGKM", 1, 0, 1, nullptr}, // #3 |
1150 | | {"HWRC", 1, 0, 1, nullptr}, // #4 |
1151 | | {"HWSALU", 1, 0, 1, nullptr}, // #5 |
1152 | | {"HWTransVALU", 1, 0, 1, nullptr}, // #6 |
1153 | | {"HWVALU", 1, 0, 1, nullptr}, // #7 |
1154 | | {"HWVMEM", 1, 0, 1, nullptr}, // #8 |
1155 | | }; |
1156 | | |
1157 | | static const llvm::MCSchedModel GFX11SpeedModel = { |
1158 | | 1, // IssueWidth |
1159 | | 1, // MicroOpBufferSize |
1160 | | MCSchedModel::DefaultLoopMicroOpBufferSize, |
1161 | | MCSchedModel::DefaultLoadLatency, |
1162 | | MCSchedModel::DefaultHighLatency, |
1163 | | 20, // MispredictPenalty |
1164 | | true, // PostRAScheduler |
1165 | | true, // CompleteModel |
1166 | | false, // EnableIntervals |
1167 | | 3, // Processor ID |
1168 | | GFX11SpeedModelProcResources, |
1169 | | GFX11SpeedModelSchedClasses, |
1170 | | 9, |
1171 | | 53, |
1172 | | nullptr, // No Itinerary |
1173 | | nullptr // No extra processor descriptor |
1174 | | }; |
1175 | | |
1176 | | static const unsigned GFX12SpeedModelProcResourceSubUnits[] = { |
1177 | | 0, // Invalid |
1178 | | }; |
1179 | | |
1180 | | // {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin} |
1181 | | static const llvm::MCProcResourceDesc GFX12SpeedModelProcResources[] = { |
1182 | | {"InvalidUnit", 0, 0, 0, 0}, |
1183 | | {"HWBranch", 1, 0, 1, nullptr}, // #1 |
1184 | | {"HWExport", 1, 0, 1, nullptr}, // #2 |
1185 | | {"HWLGKM", 1, 0, 1, nullptr}, // #3 |
1186 | | {"HWRC", 1, 0, 1, nullptr}, // #4 |
1187 | | {"HWSALU", 1, 0, 1, nullptr}, // #5 |
1188 | | {"HWVALU", 1, 0, 1, nullptr}, // #6 |
1189 | | {"HWVMEM", 1, 0, 1, nullptr}, // #7 |
1190 | | }; |
1191 | | |
1192 | | static const llvm::MCSchedModel GFX12SpeedModel = { |
1193 | | 1, // IssueWidth |
1194 | | 1, // MicroOpBufferSize |
1195 | | MCSchedModel::DefaultLoopMicroOpBufferSize, |
1196 | | MCSchedModel::DefaultLoadLatency, |
1197 | | MCSchedModel::DefaultHighLatency, |
1198 | | 20, // MispredictPenalty |
1199 | | true, // PostRAScheduler |
1200 | | true, // CompleteModel |
1201 | | false, // EnableIntervals |
1202 | | 4, // Processor ID |
1203 | | GFX12SpeedModelProcResources, |
1204 | | GFX12SpeedModelSchedClasses, |
1205 | | 8, |
1206 | | 53, |
1207 | | nullptr, // No Itinerary |
1208 | | nullptr // No extra processor descriptor |
1209 | | }; |
1210 | | |
1211 | | static const unsigned SIFullSpeedModelProcResourceSubUnits[] = { |
1212 | | 0, // Invalid |
1213 | | }; |
1214 | | |
1215 | | // {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin} |
1216 | | static const llvm::MCProcResourceDesc SIFullSpeedModelProcResources[] = { |
1217 | | {"InvalidUnit", 0, 0, 0, 0}, |
1218 | | {"HWBranch", 1, 0, 1, nullptr}, // #1 |
1219 | | {"HWExport", 1, 0, 1, nullptr}, // #2 |
1220 | | {"HWLGKM", 1, 0, 1, nullptr}, // #3 |
1221 | | {"HWSALU", 1, 0, 1, nullptr}, // #4 |
1222 | | {"HWVALU", 1, 0, 1, nullptr}, // #5 |
1223 | | {"HWVMEM", 1, 0, 1, nullptr}, // #6 |
1224 | | {"HWXDL", 1, 0, 0, nullptr}, // #7 |
1225 | | }; |
1226 | | |
1227 | | static const llvm::MCSchedModel SIFullSpeedModel = { |
1228 | | 1, // IssueWidth |
1229 | | 1, // MicroOpBufferSize |
1230 | | MCSchedModel::DefaultLoopMicroOpBufferSize, |
1231 | | MCSchedModel::DefaultLoadLatency, |
1232 | | MCSchedModel::DefaultHighLatency, |
1233 | | 20, // MispredictPenalty |
1234 | | true, // PostRAScheduler |
1235 | | true, // CompleteModel |
1236 | | false, // EnableIntervals |
1237 | | 5, // Processor ID |
1238 | | SIFullSpeedModelProcResources, |
1239 | | SIFullSpeedModelSchedClasses, |
1240 | | 8, |
1241 | | 53, |
1242 | | nullptr, // No Itinerary |
1243 | | nullptr // No extra processor descriptor |
1244 | | }; |
1245 | | |
1246 | | static const unsigned SIDPFullSpeedModelProcResourceSubUnits[] = { |
1247 | | 0, // Invalid |
1248 | | }; |
1249 | | |
1250 | | // {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin} |
1251 | | static const llvm::MCProcResourceDesc SIDPFullSpeedModelProcResources[] = { |
1252 | | {"InvalidUnit", 0, 0, 0, 0}, |
1253 | | {"HWBranch", 1, 0, 1, nullptr}, // #1 |
1254 | | {"HWExport", 1, 0, 1, nullptr}, // #2 |
1255 | | {"HWLGKM", 1, 0, 1, nullptr}, // #3 |
1256 | | {"HWSALU", 1, 0, 1, nullptr}, // #4 |
1257 | | {"HWVALU", 1, 0, 1, nullptr}, // #5 |
1258 | | {"HWVMEM", 1, 0, 1, nullptr}, // #6 |
1259 | | {"HWXDL", 1, 0, 0, nullptr}, // #7 |
1260 | | }; |
1261 | | |
1262 | | static const llvm::MCSchedModel SIDPFullSpeedModel = { |
1263 | | 1, // IssueWidth |
1264 | | 1, // MicroOpBufferSize |
1265 | | MCSchedModel::DefaultLoopMicroOpBufferSize, |
1266 | | MCSchedModel::DefaultLoadLatency, |
1267 | | MCSchedModel::DefaultHighLatency, |
1268 | | 20, // MispredictPenalty |
1269 | | true, // PostRAScheduler |
1270 | | true, // CompleteModel |
1271 | | false, // EnableIntervals |
1272 | | 6, // Processor ID |
1273 | | SIDPFullSpeedModelProcResources, |
1274 | | SIDPFullSpeedModelSchedClasses, |
1275 | | 8, |
1276 | | 53, |
1277 | | nullptr, // No Itinerary |
1278 | | nullptr // No extra processor descriptor |
1279 | | }; |
1280 | | |
1281 | | static const unsigned SIDPGFX940FullSpeedModelProcResourceSubUnits[] = { |
1282 | | 0, // Invalid |
1283 | | }; |
1284 | | |
1285 | | // {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin} |
1286 | | static const llvm::MCProcResourceDesc SIDPGFX940FullSpeedModelProcResources[] = { |
1287 | | {"InvalidUnit", 0, 0, 0, 0}, |
1288 | | {"HWBranch", 1, 0, 1, nullptr}, // #1 |
1289 | | {"HWExport", 1, 0, 1, nullptr}, // #2 |
1290 | | {"HWLGKM", 1, 0, 1, nullptr}, // #3 |
1291 | | {"HWSALU", 1, 0, 1, nullptr}, // #4 |
1292 | | {"HWVALU", 1, 0, 1, nullptr}, // #5 |
1293 | | {"HWVMEM", 1, 0, 1, nullptr}, // #6 |
1294 | | {"HWXDL", 1, 0, 0, nullptr}, // #7 |
1295 | | }; |
1296 | | |
1297 | | static const llvm::MCSchedModel SIDPGFX940FullSpeedModel = { |
1298 | | 1, // IssueWidth |
1299 | | 1, // MicroOpBufferSize |
1300 | | MCSchedModel::DefaultLoopMicroOpBufferSize, |
1301 | | MCSchedModel::DefaultLoadLatency, |
1302 | | MCSchedModel::DefaultHighLatency, |
1303 | | 20, // MispredictPenalty |
1304 | | true, // PostRAScheduler |
1305 | | true, // CompleteModel |
1306 | | false, // EnableIntervals |
1307 | | 7, // Processor ID |
1308 | | SIDPGFX940FullSpeedModelProcResources, |
1309 | | SIDPGFX940FullSpeedModelSchedClasses, |
1310 | | 8, |
1311 | | 53, |
1312 | | nullptr, // No Itinerary |
1313 | | nullptr // No extra processor descriptor |
1314 | | }; |
1315 | | |
1316 | | // Sorted (by key) array of values for CPU subtype. |
1317 | | extern const llvm::SubtargetSubTypeKV AMDGPUSubTypeKV[] = { |
1318 | | { "bonaire", { { { 0x0ULL, 0x8000000ULL, 0x800ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1319 | | { "carrizo", { { { 0x4000000000000ULL, 0x8000000ULL, 0x81002010000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1320 | | { "fiji", { { { 0x0ULL, 0x8000000ULL, 0x1002000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1321 | | { "generic", { { { 0x8000000000000000ULL, 0x10000ULL, 0x10000000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel }, |
1322 | | { "generic-hsa", { { { 0x8008000000000000ULL, 0x10000ULL, 0x10000000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel }, |
1323 | | { "gfx1010", { { { 0x200001000048000ULL, 0x4b82038420010ULL, 0x8c40010688ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel }, |
1324 | | { "gfx1011", { { { 0x2000019cc048000ULL, 0x4b82038420010ULL, 0x8c40010688ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel }, |
1325 | | { "gfx1012", { { { 0x2000019cc048000ULL, 0x4b82038420010ULL, 0x8c40010688ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel }, |
1326 | | { "gfx1013", { { { 0x200001000048000ULL, 0x4b82038420090ULL, 0x8c40010688ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel }, |
1327 | | { "gfx1030", { { { 0x9cc048000ULL, 0x1000080001d0ULL, 0x8000002000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel }, |
1328 | | { "gfx1031", { { { 0x9cc048000ULL, 0x1000080001d0ULL, 0x8000002000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel }, |
1329 | | { "gfx1032", { { { 0x9cc048000ULL, 0x1000080001d0ULL, 0x8000002000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel }, |
1330 | | { "gfx1033", { { { 0x9cc048000ULL, 0x1000080001d0ULL, 0x8000002000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel }, |
1331 | | { "gfx1034", { { { 0x9cc048000ULL, 0x1000080001d0ULL, 0x8000002000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel }, |
1332 | | { "gfx1035", { { { 0x9cc048000ULL, 0x1000080001d0ULL, 0x8000002000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel }, |
1333 | | { "gfx1036", { { { 0x9cc048000ULL, 0x1000080001d0ULL, 0x8000002000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel }, |
1334 | | { "gfx1100", { { { 0x10000f40040c10ULL, 0x30101108100600ULL, 0x880c002000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX11SpeedModel }, |
1335 | | { "gfx1101", { { { 0x10000f40040c10ULL, 0x30101108100600ULL, 0x8808002000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX11SpeedModel }, |
1336 | | { "gfx1102", { { { 0x10000f40040c10ULL, 0x30101108100200ULL, 0x880c002000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX11SpeedModel }, |
1337 | | { "gfx1103", { { { 0x10000f40040c10ULL, 0x30101108100200ULL, 0x8808002000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX11SpeedModel }, |
1338 | | { "gfx1150", { { { 0x10000f40440c10ULL, 0x830100108100200ULL, 0x8820002000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX11SpeedModel }, |
1339 | | { "gfx1151", { { { 0x10000f40440c10ULL, 0x830100108100600ULL, 0x8820002000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX11SpeedModel }, |
1340 | | { "gfx1200", { { { 0x10200f40040c10ULL, 0x930100108141000ULL, 0x8820001100ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX12SpeedModel }, |
1341 | | { "gfx1201", { { { 0x10200f40040c10ULL, 0x930100108141000ULL, 0x8820001100ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX12SpeedModel }, |
1342 | | { "gfx600", { { { 0x4000000000000ULL, 0x8000000ULL, 0x80000004000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIFullSpeedModel }, |
1343 | | { "gfx601", { { { 0x0ULL, 0x8000000ULL, 0x4000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1344 | | { "gfx602", { { { 0x0ULL, 0x8000000ULL, 0x4000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1345 | | { "gfx700", { { { 0x0ULL, 0x8000000ULL, 0x800ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1346 | | { "gfx701", { { { 0x4000000000000ULL, 0x8000000ULL, 0x80000000800ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIFullSpeedModel }, |
1347 | | { "gfx702", { { { 0x4000000000000ULL, 0x4000000ULL, 0x800ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1348 | | { "gfx703", { { { 0x0ULL, 0x4000000ULL, 0x800ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1349 | | { "gfx704", { { { 0x0ULL, 0x8000000ULL, 0x800ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1350 | | { "gfx705", { { { 0x0ULL, 0x4000000ULL, 0x800ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1351 | | { "gfx801", { { { 0x4000000000000ULL, 0x8000000ULL, 0x81002010000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1352 | | { "gfx802", { { { 0x0ULL, 0x8000000ULL, 0x1002000004ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1353 | | { "gfx803", { { { 0x0ULL, 0x8000000ULL, 0x1002000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1354 | | { "gfx805", { { { 0x0ULL, 0x8000000ULL, 0x1002000004ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1355 | | { "gfx810", { { { 0x0ULL, 0x4280000ULL, 0x1000010000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1356 | | { "gfx900", { { { 0x8000201000000000ULL, 0x6008180004ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1357 | | { "gfx902", { { { 0x8000201000000000ULL, 0x6008180004ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1358 | | { "gfx904", { { { 0x8400201000000000ULL, 0x2008180004ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1359 | | { "gfx906", { { { 0x840020190c040000ULL, 0x2008180004ULL, 0x80000008000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1360 | | { "gfx908", { { { 0x84002019fc040480ULL, 0x40002608180004ULL, 0x80000008000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1361 | | { "gfx909", { { { 0x8000201000000000ULL, 0x6008180004ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1362 | | { "gfx90a", { { { 0xc000009fc0c8c40ULL, 0x5800220a104004ULL, 0x40000008000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIDPFullSpeedModel }, |
1363 | | { "gfx90c", { { { 0x8000201000000000ULL, 0x6008180004ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1364 | | { "gfx940", { { { 0x1c108009fc0cbe50ULL, 0x5800020a00c004ULL, 0x40000008000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIDPGFX940FullSpeedModel }, |
1365 | | { "gfx941", { { { 0x1c108009fc0cbe50ULL, 0x5800020a00c004ULL, 0x40000008000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIDPGFX940FullSpeedModel }, |
1366 | | { "gfx942", { { { 0xc108009fc0cbe50ULL, 0x5800020a00c004ULL, 0x40000008000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIDPGFX940FullSpeedModel }, |
1367 | | { "hainan", { { { 0x0ULL, 0x8000000ULL, 0x4000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1368 | | { "hawaii", { { { 0x4000000000000ULL, 0x8000000ULL, 0x80000000800ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIFullSpeedModel }, |
1369 | | { "iceland", { { { 0x0ULL, 0x8000000ULL, 0x1002000004ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1370 | | { "kabini", { { { 0x0ULL, 0x4000000ULL, 0x800ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1371 | | { "kaveri", { { { 0x0ULL, 0x8000000ULL, 0x800ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1372 | | { "mullins", { { { 0x0ULL, 0x4000000ULL, 0x800ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1373 | | { "oland", { { { 0x0ULL, 0x8000000ULL, 0x4000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1374 | | { "pitcairn", { { { 0x0ULL, 0x8000000ULL, 0x4000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1375 | | { "polaris10", { { { 0x0ULL, 0x8000000ULL, 0x1002000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1376 | | { "polaris11", { { { 0x0ULL, 0x8000000ULL, 0x1002000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1377 | | { "stoney", { { { 0x0ULL, 0x4280000ULL, 0x1000010000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1378 | | { "tahiti", { { { 0x4000000000000ULL, 0x8000000ULL, 0x80000004000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIFullSpeedModel }, |
1379 | | { "tonga", { { { 0x0ULL, 0x8000000ULL, 0x1002000004ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1380 | | { "tongapro", { { { 0x0ULL, 0x8000000ULL, 0x1002000004ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1381 | | { "verde", { { { 0x0ULL, 0x8000000ULL, 0x4000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel }, |
1382 | | }; |
1383 | | |
1384 | | namespace AMDGPU_MC { |
1385 | | unsigned resolveVariantSchedClassImpl(unsigned SchedClass, |
1386 | 0 | const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) { |
1387 | 0 | switch (SchedClass) { |
1388 | 0 | case 32: // COPY |
1389 | 0 | if (CPUID == 1) { // SIQuarterSpeedModel |
1390 | 0 | return 50; // WriteSALU |
1391 | 0 | } |
1392 | 0 | if (CPUID == 2) { // GFX10SpeedModel |
1393 | 0 | return 50; // WriteSALU |
1394 | 0 | } |
1395 | 0 | if (CPUID == 3) { // GFX11SpeedModel |
1396 | 0 | return 50; // WriteSALU |
1397 | 0 | } |
1398 | 0 | if (CPUID == 4) { // GFX12SpeedModel |
1399 | 0 | return 50; // WriteSALU |
1400 | 0 | } |
1401 | 0 | if (CPUID == 5) { // SIFullSpeedModel |
1402 | 0 | return 50; // WriteSALU |
1403 | 0 | } |
1404 | 0 | if (CPUID == 6) { // SIDPFullSpeedModel |
1405 | 0 | return 50; // WriteSALU |
1406 | 0 | } |
1407 | 0 | if (CPUID == 7) { // SIDPGFX940FullSpeedModel |
1408 | 0 | return 50; // WriteSALU |
1409 | 0 | } |
1410 | 0 | break; |
1411 | 0 | case 33: // V_ACCVGPR_WRITE_B32_e64 |
1412 | 0 | if (CPUID == 1) { // SIQuarterSpeedModel |
1413 | 0 | return 52; // Write64Bit_ReadDefault |
1414 | 0 | } |
1415 | 0 | break; |
1416 | 0 | }; |
1417 | | // Don't know how to resolve this scheduling class. |
1418 | 0 | return 0; |
1419 | 0 | } |
1420 | | } // end namespace AMDGPU_MC |
1421 | | |
1422 | | struct AMDGPUGenMCSubtargetInfo : public MCSubtargetInfo { |
1423 | | AMDGPUGenMCSubtargetInfo(const Triple &TT, |
1424 | | StringRef CPU, StringRef TuneCPU, StringRef FS, |
1425 | | ArrayRef<SubtargetFeatureKV> PF, |
1426 | | ArrayRef<SubtargetSubTypeKV> PD, |
1427 | | const MCWriteProcResEntry *WPR, |
1428 | | const MCWriteLatencyEntry *WL, |
1429 | | const MCReadAdvanceEntry *RA, const InstrStage *IS, |
1430 | | const unsigned *OC, const unsigned *FP) : |
1431 | | MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD, |
1432 | 0 | WPR, WL, RA, IS, OC, FP) { } |
1433 | | |
1434 | | unsigned resolveVariantSchedClass(unsigned SchedClass, |
1435 | | const MCInst *MI, const MCInstrInfo *MCII, |
1436 | 0 | unsigned CPUID) const override { |
1437 | 0 | return AMDGPU_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID); |
1438 | 0 | } |
1439 | | }; |
1440 | | |
1441 | 0 | static inline MCSubtargetInfo *createAMDGPUMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) { |
1442 | 0 | return new AMDGPUGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, AMDGPUFeatureKV, AMDGPUSubTypeKV, |
1443 | 0 | AMDGPUWriteProcResTable, AMDGPUWriteLatencyTable, AMDGPUReadAdvanceTable, |
1444 | 0 | nullptr, nullptr, nullptr); |
1445 | 0 | } |
1446 | | |
1447 | | } // end namespace llvm |
1448 | | |
1449 | | #endif // GET_SUBTARGETINFO_MC_DESC |
1450 | | |
1451 | | |
1452 | | #ifdef GET_SUBTARGETINFO_TARGET_DESC |
1453 | | #undef GET_SUBTARGETINFO_TARGET_DESC |
1454 | | |
1455 | | #include "llvm/Support/Debug.h" |
1456 | | #include "llvm/Support/raw_ostream.h" |
1457 | | |
1458 | | // ParseSubtargetFeatures - Parses features string setting specified |
1459 | | // subtarget options. |
1460 | 0 | void llvm::AMDGPUSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) { |
1461 | 0 | LLVM_DEBUG(dbgs() << "\nFeatures:" << FS); |
1462 | 0 | LLVM_DEBUG(dbgs() << "\nCPU:" << CPU); |
1463 | 0 | LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n"); |
1464 | 0 | InitMCProcessorInfo(CPU, TuneCPU, FS); |
1465 | 0 | const FeatureBitset &Bits = getFeatureBits(); |
1466 | 0 | if (Bits[AMDGPU::Feature16BitInsts]) Has16BitInsts = true; |
1467 | 0 | if (Bits[AMDGPU::FeatureA16]) HasA16 = true; |
1468 | 0 | if (Bits[AMDGPU::FeatureAddNoCarryInsts]) AddNoCarryInsts = true; |
1469 | 0 | if (Bits[AMDGPU::FeatureApertureRegs]) HasApertureRegs = true; |
1470 | 0 | if (Bits[AMDGPU::FeatureArchitectedFlatScratch]) HasArchitectedFlatScratch = true; |
1471 | 0 | if (Bits[AMDGPU::FeatureArchitectedSGPRs]) HasArchitectedSGPRs = true; |
1472 | 0 | if (Bits[AMDGPU::FeatureAtomicBufferGlobalPkAddF16Insts]) HasAtomicBufferGlobalPkAddF16Insts = true; |
1473 | 0 | if (Bits[AMDGPU::FeatureAtomicBufferGlobalPkAddF16NoRtnInsts]) HasAtomicBufferGlobalPkAddF16NoRtnInsts = true; |
1474 | 0 | if (Bits[AMDGPU::FeatureAtomicCSubNoRtnInsts]) HasAtomicCSubNoRtnInsts = true; |
1475 | 0 | if (Bits[AMDGPU::FeatureAtomicDsPkAdd16Insts]) HasAtomicDsPkAdd16Insts = true; |
1476 | 0 | if (Bits[AMDGPU::FeatureAtomicFaddNoRtnInsts]) HasAtomicFaddNoRtnInsts = true; |
1477 | 0 | if (Bits[AMDGPU::FeatureAtomicFaddRtnInsts]) HasAtomicFaddRtnInsts = true; |
1478 | 0 | if (Bits[AMDGPU::FeatureAtomicFlatPkAdd16Insts]) HasAtomicFlatPkAdd16Insts = true; |
1479 | 0 | if (Bits[AMDGPU::FeatureAtomicGlobalPkAddBF16Inst]) HasAtomicGlobalPkAddBF16Inst = true; |
1480 | 0 | if (Bits[AMDGPU::FeatureAutoWaitcntBeforeBarrier]) AutoWaitcntBeforeBarrier = true; |
1481 | 0 | if (Bits[AMDGPU::FeatureBackOffBarrier]) BackOffBarrier = true; |
1482 | 0 | if (Bits[AMDGPU::FeatureCIInsts]) CIInsts = true; |
1483 | 0 | if (Bits[AMDGPU::FeatureCuMode]) EnableCuMode = true; |
1484 | 0 | if (Bits[AMDGPU::FeatureDLInsts]) HasDLInsts = true; |
1485 | 0 | if (Bits[AMDGPU::FeatureDPALU_DPP]) HasDPALU_DPP = true; |
1486 | 0 | if (Bits[AMDGPU::FeatureDPP]) HasDPP = true; |
1487 | 0 | if (Bits[AMDGPU::FeatureDPP8]) HasDPP8 = true; |
1488 | 0 | if (Bits[AMDGPU::FeatureDPPSrc1SGPR]) HasDPPSrc1SGPR = true; |
1489 | 0 | if (Bits[AMDGPU::FeatureDefaultComponentBroadcast]) HasDefaultComponentBroadcast = true; |
1490 | 0 | if (Bits[AMDGPU::FeatureDefaultComponentZero]) HasDefaultComponentZero = true; |
1491 | 0 | if (Bits[AMDGPU::FeatureDisable]) FeatureDisable = true; |
1492 | 0 | if (Bits[AMDGPU::FeatureDot1Insts]) HasDot1Insts = true; |
1493 | 0 | if (Bits[AMDGPU::FeatureDot2Insts]) HasDot2Insts = true; |
1494 | 0 | if (Bits[AMDGPU::FeatureDot3Insts]) HasDot3Insts = true; |
1495 | 0 | if (Bits[AMDGPU::FeatureDot4Insts]) HasDot4Insts = true; |
1496 | 0 | if (Bits[AMDGPU::FeatureDot5Insts]) HasDot5Insts = true; |
1497 | 0 | if (Bits[AMDGPU::FeatureDot6Insts]) HasDot6Insts = true; |
1498 | 0 | if (Bits[AMDGPU::FeatureDot7Insts]) HasDot7Insts = true; |
1499 | 0 | if (Bits[AMDGPU::FeatureDot8Insts]) HasDot8Insts = true; |
1500 | 0 | if (Bits[AMDGPU::FeatureDot9Insts]) HasDot9Insts = true; |
1501 | 0 | if (Bits[AMDGPU::FeatureDot10Insts]) HasDot10Insts = true; |
1502 | 0 | if (Bits[AMDGPU::FeatureDsSrc2Insts]) HasDsSrc2Insts = true; |
1503 | 0 | if (Bits[AMDGPU::FeatureDumpCode]) DumpCode = true; |
1504 | 0 | if (Bits[AMDGPU::FeatureDumpCodeLower]) DumpCode = true; |
1505 | 0 | if (Bits[AMDGPU::FeatureEnableDS128]) EnableDS128 = true; |
1506 | 0 | if (Bits[AMDGPU::FeatureEnableFlatScratch]) EnableFlatScratch = true; |
1507 | 0 | if (Bits[AMDGPU::FeatureEnableLoadStoreOpt]) EnableLoadStoreOpt = true; |
1508 | 0 | if (Bits[AMDGPU::FeatureEnablePRTStrictNull]) EnablePRTStrictNull = true; |
1509 | 0 | if (Bits[AMDGPU::FeatureEnableSIScheduler]) EnableSIScheduler = true; |
1510 | 0 | if (Bits[AMDGPU::FeatureEnableUnsafeDSOffsetFolding]) EnableUnsafeDSOffsetFolding = true; |
1511 | 0 | if (Bits[AMDGPU::FeatureExtendedImageInsts]) HasExtendedImageInsts = true; |
1512 | 0 | if (Bits[AMDGPU::FeatureFMA]) FMA = true; |
1513 | 0 | if (Bits[AMDGPU::FeatureFP8Insts]) HasFP8Insts = true; |
1514 | 0 | if (Bits[AMDGPU::FeatureFP64]) FP64 = true; |
1515 | 0 | if (Bits[AMDGPU::FeatureFastDenormalF32]) FastDenormalF32 = true; |
1516 | 0 | if (Bits[AMDGPU::FeatureFastFMAF32]) FastFMAF32 = true; |
1517 | 0 | if (Bits[AMDGPU::FeatureFlatAddressSpace]) FlatAddressSpace = true; |
1518 | 0 | if (Bits[AMDGPU::FeatureFlatAtomicFaddF32Inst]) HasFlatAtomicFaddF32Inst = true; |
1519 | 0 | if (Bits[AMDGPU::FeatureFlatForGlobal]) FlatForGlobal = true; |
1520 | 0 | if (Bits[AMDGPU::FeatureFlatGlobalInsts]) FlatGlobalInsts = true; |
1521 | 0 | if (Bits[AMDGPU::FeatureFlatInstOffsets]) FlatInstOffsets = true; |
1522 | 0 | if (Bits[AMDGPU::FeatureFlatScratchInsts]) FlatScratchInsts = true; |
1523 | 0 | if (Bits[AMDGPU::FeatureFlatSegmentOffsetBug]) HasFlatSegmentOffsetBug = true; |
1524 | 0 | if (Bits[AMDGPU::FeatureFmaMixInsts]) HasFmaMixInsts = true; |
1525 | 0 | if (Bits[AMDGPU::FeatureFmacF64Inst]) HasFmacF64Inst = true; |
1526 | 0 | if (Bits[AMDGPU::FeatureForceStoreSC0SC1]) HasForceStoreSC0SC1 = true; |
1527 | 0 | if (Bits[AMDGPU::FeatureG16]) HasG16 = true; |
1528 | 0 | if (Bits[AMDGPU::FeatureGCN3Encoding]) GCN3Encoding = true; |
1529 | 0 | if (Bits[AMDGPU::FeatureGDS]) HasGDS = true; |
1530 | 0 | if (Bits[AMDGPU::FeatureGFX7GFX8GFX9Insts]) GFX7GFX8GFX9Insts = true; |
1531 | 0 | if (Bits[AMDGPU::FeatureGFX8Insts]) GFX8Insts = true; |
1532 | 0 | if (Bits[AMDGPU::FeatureGFX9] && Gen < GCNSubtarget::GFX9) Gen = GCNSubtarget::GFX9; |
1533 | 0 | if (Bits[AMDGPU::FeatureGFX9Insts]) GFX9Insts = true; |
1534 | 0 | if (Bits[AMDGPU::FeatureGFX10] && Gen < GCNSubtarget::GFX10) Gen = GCNSubtarget::GFX10; |
1535 | 0 | if (Bits[AMDGPU::FeatureGFX10Insts]) GFX10Insts = true; |
1536 | 0 | if (Bits[AMDGPU::FeatureGFX10_3Insts]) GFX10_3Insts = true; |
1537 | 0 | if (Bits[AMDGPU::FeatureGFX10_AEncoding]) GFX10_AEncoding = true; |
1538 | 0 | if (Bits[AMDGPU::FeatureGFX10_BEncoding]) GFX10_BEncoding = true; |
1539 | 0 | if (Bits[AMDGPU::FeatureGFX11] && Gen < GCNSubtarget::GFX11) Gen = GCNSubtarget::GFX11; |
1540 | 0 | if (Bits[AMDGPU::FeatureGFX11FullVGPRs]) HasGFX11FullVGPRs = true; |
1541 | 0 | if (Bits[AMDGPU::FeatureGFX11Insts]) GFX11Insts = true; |
1542 | 0 | if (Bits[AMDGPU::FeatureGFX12] && Gen < GCNSubtarget::GFX12) Gen = GCNSubtarget::GFX12; |
1543 | 0 | if (Bits[AMDGPU::FeatureGFX12Insts]) GFX12Insts = true; |
1544 | 0 | if (Bits[AMDGPU::FeatureGFX90AInsts]) GFX90AInsts = true; |
1545 | 0 | if (Bits[AMDGPU::FeatureGFX940Insts]) GFX940Insts = true; |
1546 | 0 | if (Bits[AMDGPU::FeatureGWS]) HasGWS = true; |
1547 | 0 | if (Bits[AMDGPU::FeatureGetWaveIdInst]) HasGetWaveIdInst = true; |
1548 | 0 | if (Bits[AMDGPU::FeatureHasRestrictedSOffset]) HasRestrictedSOffset = true; |
1549 | 0 | if (Bits[AMDGPU::FeatureImageGather4D16Bug]) HasImageGather4D16Bug = true; |
1550 | 0 | if (Bits[AMDGPU::FeatureImageInsts]) HasImageInsts = true; |
1551 | 0 | if (Bits[AMDGPU::FeatureImageStoreD16Bug]) HasImageStoreD16Bug = true; |
1552 | 0 | if (Bits[AMDGPU::FeatureInstFwdPrefetchBug]) HasInstFwdPrefetchBug = true; |
1553 | 0 | if (Bits[AMDGPU::FeatureIntClamp]) HasIntClamp = true; |
1554 | 0 | if (Bits[AMDGPU::FeatureInv2PiInlineImm]) HasInv2PiInlineImm = true; |
1555 | 0 | if (Bits[AMDGPU::FeatureKernargPreload]) KernargPreload = true; |
1556 | 0 | if (Bits[AMDGPU::FeatureLDSBankCount16] && LDSBankCount < 16) LDSBankCount = 16; |
1557 | 0 | if (Bits[AMDGPU::FeatureLDSBankCount32] && LDSBankCount < 32) LDSBankCount = 32; |
1558 | 0 | if (Bits[AMDGPU::FeatureLdsBranchVmemWARHazard]) HasLdsBranchVmemWARHazard = true; |
1559 | 0 | if (Bits[AMDGPU::FeatureLdsMisalignedBug]) LDSMisalignedBug = true; |
1560 | 0 | if (Bits[AMDGPU::FeatureLocalMemorySize32768] && LocalMemorySize < 32768) LocalMemorySize = 32768; |
1561 | 0 | if (Bits[AMDGPU::FeatureLocalMemorySize65536] && LocalMemorySize < 65536) LocalMemorySize = 65536; |
1562 | 0 | if (Bits[AMDGPU::FeatureMADIntraFwdBug]) HasMADIntraFwdBug = true; |
1563 | 0 | if (Bits[AMDGPU::FeatureMAIInsts]) HasMAIInsts = true; |
1564 | 0 | if (Bits[AMDGPU::FeatureMFMAInlineLiteralBug]) HasMFMAInlineLiteralBug = true; |
1565 | 0 | if (Bits[AMDGPU::FeatureMIMG_R128]) MIMG_R128 = true; |
1566 | 0 | if (Bits[AMDGPU::FeatureMSAALoadDstSelBug]) HasMSAALoadDstSelBug = true; |
1567 | 0 | if (Bits[AMDGPU::FeatureMadMacF32Insts]) HasMadMacF32Insts = true; |
1568 | 0 | if (Bits[AMDGPU::FeatureMadMixInsts]) HasMadMixInsts = true; |
1569 | 0 | if (Bits[AMDGPU::FeatureMaxPrivateElementSize4] && MaxPrivateElementSize < 4) MaxPrivateElementSize = 4; |
1570 | 0 | if (Bits[AMDGPU::FeatureMaxPrivateElementSize8] && MaxPrivateElementSize < 8) MaxPrivateElementSize = 8; |
1571 | 0 | if (Bits[AMDGPU::FeatureMaxPrivateElementSize16] && MaxPrivateElementSize < 16) MaxPrivateElementSize = 16; |
1572 | 0 | if (Bits[AMDGPU::FeatureMovrel]) HasMovrel = true; |
1573 | 0 | if (Bits[AMDGPU::FeatureNSAClauseBug]) HasNSAClauseBug = true; |
1574 | 0 | if (Bits[AMDGPU::FeatureNSAEncoding]) HasNSAEncoding = true; |
1575 | 0 | if (Bits[AMDGPU::FeatureNSAtoVMEMBug]) HasNSAtoVMEMBug = true; |
1576 | 0 | if (Bits[AMDGPU::FeatureNegativeScratchOffsetBug]) NegativeScratchOffsetBug = true; |
1577 | 0 | if (Bits[AMDGPU::FeatureNegativeUnalignedScratchOffsetBug]) NegativeUnalignedScratchOffsetBug = true; |
1578 | 0 | if (Bits[AMDGPU::FeatureNoDataDepHazard]) HasNoDataDepHazard = true; |
1579 | 0 | if (Bits[AMDGPU::FeatureNoSdstCMPX]) HasNoSdstCMPX = true; |
1580 | 0 | if (Bits[AMDGPU::FeatureOffset3fBug]) HasOffset3fBug = true; |
1581 | 0 | if (Bits[AMDGPU::FeaturePackedFP32Ops]) HasPackedFP32Ops = true; |
1582 | 0 | if (Bits[AMDGPU::FeaturePackedTID]) HasPackedTID = true; |
1583 | 0 | if (Bits[AMDGPU::FeaturePartialNSAEncoding]) HasPartialNSAEncoding = true; |
1584 | 0 | if (Bits[AMDGPU::FeaturePkFmacF16Inst]) HasPkFmacF16Inst = true; |
1585 | 0 | if (Bits[AMDGPU::FeaturePromoteAlloca]) EnablePromoteAlloca = true; |
1586 | 0 | if (Bits[AMDGPU::FeaturePseudoScalarTrans]) HasPseudoScalarTrans = true; |
1587 | 0 | if (Bits[AMDGPU::FeatureR128A16]) HasR128A16 = true; |
1588 | 0 | if (Bits[AMDGPU::FeatureRealTrue16Insts]) EnableRealTrue16Insts = true; |
1589 | 0 | if (Bits[AMDGPU::FeatureSALUFloatInsts]) HasSALUFloatInsts = true; |
1590 | 0 | if (Bits[AMDGPU::FeatureSDWA]) HasSDWA = true; |
1591 | 0 | if (Bits[AMDGPU::FeatureSDWAMac]) HasSDWAMac = true; |
1592 | 0 | if (Bits[AMDGPU::FeatureSDWAOmod]) HasSDWAOmod = true; |
1593 | 0 | if (Bits[AMDGPU::FeatureSDWAOutModsVOPC]) HasSDWAOutModsVOPC = true; |
1594 | 0 | if (Bits[AMDGPU::FeatureSDWAScalar]) HasSDWAScalar = true; |
1595 | 0 | if (Bits[AMDGPU::FeatureSDWASdst]) HasSDWASdst = true; |
1596 | 0 | if (Bits[AMDGPU::FeatureSGPRInitBug]) SGPRInitBug = true; |
1597 | 0 | if (Bits[AMDGPU::FeatureSMEMtoVectorWriteHazard]) HasSMEMtoVectorWriteHazard = true; |
1598 | 0 | if (Bits[AMDGPU::FeatureSMemRealTime]) HasSMemRealTime = true; |
1599 | 0 | if (Bits[AMDGPU::FeatureSMemTimeInst]) HasSMemTimeInst = true; |
1600 | 0 | if (Bits[AMDGPU::FeatureSRAMECC]) EnableSRAMECC = true; |
1601 | 0 | if (Bits[AMDGPU::FeatureScalarAtomics]) HasScalarAtomics = true; |
1602 | 0 | if (Bits[AMDGPU::FeatureScalarDwordx3Loads]) HasScalarDwordx3Loads = true; |
1603 | 0 | if (Bits[AMDGPU::FeatureScalarFlatScratchInsts]) ScalarFlatScratchInsts = true; |
1604 | 0 | if (Bits[AMDGPU::FeatureScalarStores]) HasScalarStores = true; |
1605 | 0 | if (Bits[AMDGPU::FeatureSeaIslands] && Gen < GCNSubtarget::SEA_ISLANDS) Gen = GCNSubtarget::SEA_ISLANDS; |
1606 | 0 | if (Bits[AMDGPU::FeatureShaderCyclesHiLoRegisters]) HasShaderCyclesHiLoRegisters = true; |
1607 | 0 | if (Bits[AMDGPU::FeatureShaderCyclesRegister]) HasShaderCyclesRegister = true; |
1608 | 0 | if (Bits[AMDGPU::FeatureSouthernIslands] && Gen < GCNSubtarget::SOUTHERN_ISLANDS) Gen = GCNSubtarget::SOUTHERN_ISLANDS; |
1609 | 0 | if (Bits[AMDGPU::FeatureSupportsSRAMECC]) SupportsSRAMECC = true; |
1610 | 0 | if (Bits[AMDGPU::FeatureSupportsXNACK]) SupportsXNACK = true; |
1611 | 0 | if (Bits[AMDGPU::FeatureTgSplit]) EnableTgSplit = true; |
1612 | 0 | if (Bits[AMDGPU::FeatureTrapHandler]) TrapHandler = true; |
1613 | 0 | if (Bits[AMDGPU::FeatureTrigReducedRange]) HasTrigReducedRange = true; |
1614 | 0 | if (Bits[AMDGPU::FeatureTrue16BitInsts]) HasTrue16BitInsts = true; |
1615 | 0 | if (Bits[AMDGPU::FeatureUnalignedAccessMode]) UnalignedAccessMode = true; |
1616 | 0 | if (Bits[AMDGPU::FeatureUnalignedBufferAccess]) UnalignedBufferAccess = true; |
1617 | 0 | if (Bits[AMDGPU::FeatureUnalignedDSAccess]) UnalignedDSAccess = true; |
1618 | 0 | if (Bits[AMDGPU::FeatureUnalignedScratchAccess]) UnalignedScratchAccess = true; |
1619 | 0 | if (Bits[AMDGPU::FeatureUnpackedD16VMem]) HasUnpackedD16VMem = true; |
1620 | 0 | if (Bits[AMDGPU::FeatureUserSGPRInit16Bug]) UserSGPRInit16Bug = true; |
1621 | 0 | if (Bits[AMDGPU::FeatureVALUTransUseHazard]) HasVALUTransUseHazard = true; |
1622 | 0 | if (Bits[AMDGPU::FeatureVGPRIndexMode]) HasVGPRIndexMode = true; |
1623 | 0 | if (Bits[AMDGPU::FeatureVGPRSingleUseHintInsts]) HasVGPRSingleUseHintInsts = true; |
1624 | 0 | if (Bits[AMDGPU::FeatureVMEMtoScalarWriteHazard]) HasVMEMtoScalarWriteHazard = true; |
1625 | 0 | if (Bits[AMDGPU::FeatureVOP3Literal]) HasVOP3Literal = true; |
1626 | 0 | if (Bits[AMDGPU::FeatureVOP3P]) HasVOP3PInsts = true; |
1627 | 0 | if (Bits[AMDGPU::FeatureVOPD]) HasVOPDInsts = true; |
1628 | 0 | if (Bits[AMDGPU::FeatureVcmpxExecWARHazard]) HasVcmpxExecWARHazard = true; |
1629 | 0 | if (Bits[AMDGPU::FeatureVcmpxPermlaneHazard]) HasVcmpxPermlaneHazard = true; |
1630 | 0 | if (Bits[AMDGPU::FeatureVolcanicIslands] && Gen < GCNSubtarget::VOLCANIC_ISLANDS) Gen = GCNSubtarget::VOLCANIC_ISLANDS; |
1631 | 0 | if (Bits[AMDGPU::FeatureVscnt]) HasVscnt = true; |
1632 | 0 | if (Bits[AMDGPU::FeatureWavefrontSize16] && WavefrontSizeLog2 < 4) WavefrontSizeLog2 = 4; |
1633 | 0 | if (Bits[AMDGPU::FeatureWavefrontSize32] && WavefrontSizeLog2 < 5) WavefrontSizeLog2 = 5; |
1634 | 0 | if (Bits[AMDGPU::FeatureWavefrontSize64] && WavefrontSizeLog2 < 6) WavefrontSizeLog2 = 6; |
1635 | 0 | if (Bits[AMDGPU::FeatureXNACK]) EnableXNACK = true; |
1636 | 0 | if (Bits[AMDGPU::FullRate64Ops]) FullRate64Ops = true; |
1637 | 0 | if (Bits[AMDGPU::HalfRate64Ops]) HalfRate64Ops = true; |
1638 | 0 | } |
1639 | | #endif // GET_SUBTARGETINFO_TARGET_DESC |
1640 | | |
1641 | | |
1642 | | #ifdef GET_SUBTARGETINFO_HEADER |
1643 | | #undef GET_SUBTARGETINFO_HEADER |
1644 | | |
1645 | | namespace llvm { |
1646 | | class DFAPacketizer; |
1647 | | namespace AMDGPU_MC { |
1648 | | unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID); |
1649 | | } // end namespace AMDGPU_MC |
1650 | | |
1651 | | struct AMDGPUGenSubtargetInfo : public TargetSubtargetInfo { |
1652 | | explicit AMDGPUGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS); |
1653 | | public: |
1654 | | unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override; |
1655 | | unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override; |
1656 | | DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const; |
1657 | | }; |
1658 | | } // end namespace llvm |
1659 | | |
1660 | | #endif // GET_SUBTARGETINFO_HEADER |
1661 | | |
1662 | | |
1663 | | #ifdef GET_SUBTARGETINFO_CTOR |
1664 | | #undef GET_SUBTARGETINFO_CTOR |
1665 | | |
1666 | | #include "llvm/CodeGen/TargetSchedule.h" |
1667 | | |
1668 | | namespace llvm { |
1669 | | extern const llvm::SubtargetFeatureKV AMDGPUFeatureKV[]; |
1670 | | extern const llvm::SubtargetSubTypeKV AMDGPUSubTypeKV[]; |
1671 | | extern const llvm::MCWriteProcResEntry AMDGPUWriteProcResTable[]; |
1672 | | extern const llvm::MCWriteLatencyEntry AMDGPUWriteLatencyTable[]; |
1673 | | extern const llvm::MCReadAdvanceEntry AMDGPUReadAdvanceTable[]; |
1674 | | AMDGPUGenSubtargetInfo::AMDGPUGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) |
1675 | | : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(AMDGPUFeatureKV, 171), ArrayRef(AMDGPUSubTypeKV, 64), |
1676 | | AMDGPUWriteProcResTable, AMDGPUWriteLatencyTable, AMDGPUReadAdvanceTable, |
1677 | 0 | nullptr, nullptr, nullptr) {} |
1678 | | |
1679 | | unsigned AMDGPUGenSubtargetInfo |
1680 | 0 | ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const { |
1681 | |
|
1682 | 0 | const SIInstrInfo *TII = |
1683 | 0 | static_cast<const SIInstrInfo*>(SchedModel->getInstrInfo()); |
1684 | 0 | (void)TII; |
1685 | |
|
1686 | 0 | switch (SchedClass) { |
1687 | 0 | case 32: // COPY |
1688 | 0 | if (SchedModel->getProcessorID() == 1) { // SIQuarterSpeedModel |
1689 | 0 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32) |
1690 | 0 | return 48; // Write32Bit |
1691 | 0 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32) |
1692 | 0 | return 49; // Write64Bit |
1693 | 0 | return 50; // WriteSALU |
1694 | 0 | } |
1695 | 0 | if (SchedModel->getProcessorID() == 2) { // GFX10SpeedModel |
1696 | 0 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32) |
1697 | 0 | return 48; // Write32Bit |
1698 | 0 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32) |
1699 | 0 | return 49; // Write64Bit |
1700 | 0 | return 50; // WriteSALU |
1701 | 0 | } |
1702 | 0 | if (SchedModel->getProcessorID() == 3) { // GFX11SpeedModel |
1703 | 0 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32) |
1704 | 0 | return 48; // Write32Bit |
1705 | 0 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32) |
1706 | 0 | return 49; // Write64Bit |
1707 | 0 | return 50; // WriteSALU |
1708 | 0 | } |
1709 | 0 | if (SchedModel->getProcessorID() == 4) { // GFX12SpeedModel |
1710 | 0 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32) |
1711 | 0 | return 48; // Write32Bit |
1712 | 0 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32) |
1713 | 0 | return 49; // Write64Bit |
1714 | 0 | return 50; // WriteSALU |
1715 | 0 | } |
1716 | 0 | if (SchedModel->getProcessorID() == 5) { // SIFullSpeedModel |
1717 | 0 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32) |
1718 | 0 | return 48; // Write32Bit |
1719 | 0 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32) |
1720 | 0 | return 49; // Write64Bit |
1721 | 0 | return 50; // WriteSALU |
1722 | 0 | } |
1723 | 0 | if (SchedModel->getProcessorID() == 6) { // SIDPFullSpeedModel |
1724 | 0 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32) |
1725 | 0 | return 48; // Write32Bit |
1726 | 0 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32) |
1727 | 0 | return 49; // Write64Bit |
1728 | 0 | return 50; // WriteSALU |
1729 | 0 | } |
1730 | 0 | if (SchedModel->getProcessorID() == 7) { // SIDPGFX940FullSpeedModel |
1731 | 0 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32) |
1732 | 0 | return 48; // Write32Bit |
1733 | 0 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32) |
1734 | 0 | return 49; // Write64Bit |
1735 | 0 | return 50; // WriteSALU |
1736 | 0 | } |
1737 | 0 | break; |
1738 | 0 | case 33: // V_ACCVGPR_WRITE_B32_e64 |
1739 | 0 | if (SchedModel->getProcessorID() == 1) { // SIQuarterSpeedModel |
1740 | 0 | if (TII->hasVGPRUses(*MI)) |
1741 | 0 | return 51; // Write64Bit_MIVGPRRead |
1742 | 0 | return 52; // Write64Bit_ReadDefault |
1743 | 0 | } |
1744 | 0 | break; |
1745 | 0 | }; |
1746 | 0 | report_fatal_error("Expected a variant SchedClass"); |
1747 | 0 | } // AMDGPUGenSubtargetInfo::resolveSchedClass |
1748 | | |
1749 | | unsigned AMDGPUGenSubtargetInfo |
1750 | 0 | ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const { |
1751 | 0 | return AMDGPU_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID); |
1752 | 0 | } // AMDGPUGenSubtargetInfo::resolveVariantSchedClass |
1753 | | |
1754 | | } // end namespace llvm |
1755 | | |
1756 | | #endif // GET_SUBTARGETINFO_CTOR |
1757 | | |
1758 | | |
1759 | | #ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS |
1760 | | #undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS |
1761 | | |
1762 | | #endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS |
1763 | | |
1764 | | |
1765 | | #ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS |
1766 | | #undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS |
1767 | | |
1768 | | #endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS |
1769 | | |