/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\

|*                                                                            *|

|* Target Instruction Enum Values and Descriptors                             *|

|*                                                                            *|

|* Automatically generated file, do not edit!                                 *|

|*                                                                            *|

\*===----------------------------------------------------------------------===*/

#ifdef GET_INSTRINFO_ENUM

#undef GET_INSTRINFO_ENUM

namespace llvm {

namespace R600 {

  enum {

    PHI = 0,

    INLINEASM = 1,

    INLINEASM_BR  = 2,

    CFI_INSTRUCTION = 3,

    EH_LABEL  = 4,

    GC_LABEL  = 5,

    ANNOTATION_LABEL  = 6,

    KILL  = 7,

    EXTRACT_SUBREG  = 8,

    INSERT_SUBREG = 9,

    IMPLICIT_DEF  = 10,

    SUBREG_TO_REG = 11,

    COPY_TO_REGCLASS  = 12,

    DBG_VALUE = 13,

    DBG_VALUE_LIST  = 14,

    DBG_INSTR_REF = 15,

    DBG_PHI = 16,

    DBG_LABEL = 17,

    REG_SEQUENCE  = 18,

    COPY  = 19,

    BUNDLE  = 20,

    LIFETIME_START  = 21,

    LIFETIME_END  = 22,

    PSEUDO_PROBE  = 23,

    ARITH_FENCE = 24,

    STACKMAP  = 25,

    FENTRY_CALL = 26,

    PATCHPOINT  = 27,

    LOAD_STACK_GUARD  = 28,

    PREALLOCATED_SETUP  = 29,

    PREALLOCATED_ARG  = 30,

    STATEPOINT  = 31,

    LOCAL_ESCAPE  = 32,

    FAULTING_OP = 33,

    PATCHABLE_OP  = 34,

    PATCHABLE_FUNCTION_ENTER  = 35,

    PATCHABLE_RET = 36,

    PATCHABLE_FUNCTION_EXIT = 37,

    PATCHABLE_TAIL_CALL = 38,

    PATCHABLE_EVENT_CALL  = 39,

    PATCHABLE_TYPED_EVENT_CALL  = 40,

    ICALL_BRANCH_FUNNEL = 41,

    MEMBARRIER  = 42,

    JUMP_TABLE_DEBUG_INFO = 43,

    G_ASSERT_SEXT = 44,

    G_ASSERT_ZEXT = 45,

    G_ASSERT_ALIGN  = 46,

    G_ADD = 47,

    G_SUB = 48,

    G_MUL = 49,

    G_SDIV  = 50,

    G_UDIV  = 51,

    G_SREM  = 52,

    G_UREM  = 53,

    G_SDIVREM = 54,

    G_UDIVREM = 55,

    G_AND = 56,

    G_OR  = 57,

    G_XOR = 58,

    G_IMPLICIT_DEF  = 59,

    G_PHI = 60,

    G_FRAME_INDEX = 61,

    G_GLOBAL_VALUE  = 62,

    G_CONSTANT_POOL = 63,

    G_EXTRACT = 64,

    G_UNMERGE_VALUES  = 65,

    G_INSERT  = 66,

    G_MERGE_VALUES  = 67,

    G_BUILD_VECTOR  = 68,

    G_BUILD_VECTOR_TRUNC  = 69,

    G_CONCAT_VECTORS  = 70,

    G_PTRTOINT  = 71,

    G_INTTOPTR  = 72,

    G_BITCAST = 73,

    G_FREEZE  = 74,

    G_CONSTANT_FOLD_BARRIER = 75,

    G_INTRINSIC_FPTRUNC_ROUND = 76,

    G_INTRINSIC_TRUNC = 77,

    G_INTRINSIC_ROUND = 78,

    G_INTRINSIC_LRINT = 79,

    G_INTRINSIC_ROUNDEVEN = 80,

    G_READCYCLECOUNTER  = 81,

    G_LOAD  = 82,

    G_SEXTLOAD  = 83,

    G_ZEXTLOAD  = 84,

    G_INDEXED_LOAD  = 85,

    G_INDEXED_SEXTLOAD  = 86,

    G_INDEXED_ZEXTLOAD  = 87,

    G_STORE = 88,

    G_INDEXED_STORE = 89,

    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 90,

    G_ATOMIC_CMPXCHG  = 91,

    G_ATOMICRMW_XCHG  = 92,

    G_ATOMICRMW_ADD = 93,

    G_ATOMICRMW_SUB = 94,

    G_ATOMICRMW_AND = 95,

    G_ATOMICRMW_NAND  = 96,

    G_ATOMICRMW_OR  = 97,

    G_ATOMICRMW_XOR = 98,

    G_ATOMICRMW_MAX = 99,

    G_ATOMICRMW_MIN = 100,

    G_ATOMICRMW_UMAX  = 101,

    G_ATOMICRMW_UMIN  = 102,

    G_ATOMICRMW_FADD  = 103,

    G_ATOMICRMW_FSUB  = 104,

    G_ATOMICRMW_FMAX  = 105,

    G_ATOMICRMW_FMIN  = 106,

    G_ATOMICRMW_UINC_WRAP = 107,

    G_ATOMICRMW_UDEC_WRAP = 108,

    G_FENCE = 109,

    G_PREFETCH  = 110,

    G_BRCOND  = 111,

    G_BRINDIRECT  = 112,

    G_INVOKE_REGION_START = 113,

    G_INTRINSIC = 114,

    G_INTRINSIC_W_SIDE_EFFECTS  = 115,

    G_INTRINSIC_CONVERGENT  = 116,

    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 117,

    G_ANYEXT  = 118,

    G_TRUNC = 119,

    G_CONSTANT  = 120,

    G_FCONSTANT = 121,

    G_VASTART = 122,

    G_VAARG = 123,

    G_SEXT  = 124,

    G_SEXT_INREG  = 125,

    G_ZEXT  = 126,

    G_SHL = 127,

    G_LSHR  = 128,

    G_ASHR  = 129,

    G_FSHL  = 130,

    G_FSHR  = 131,

    G_ROTR  = 132,

    G_ROTL  = 133,

    G_ICMP  = 134,

    G_FCMP  = 135,

    G_SELECT  = 136,

    G_UADDO = 137,

    G_UADDE = 138,

    G_USUBO = 139,

    G_USUBE = 140,

    G_SADDO = 141,

    G_SADDE = 142,

    G_SSUBO = 143,

    G_SSUBE = 144,

    G_UMULO = 145,

    G_SMULO = 146,

    G_UMULH = 147,

    G_SMULH = 148,

    G_UADDSAT = 149,

    G_SADDSAT = 150,

    G_USUBSAT = 151,

    G_SSUBSAT = 152,

    G_USHLSAT = 153,

    G_SSHLSAT = 154,

    G_SMULFIX = 155,

    G_UMULFIX = 156,

    G_SMULFIXSAT  = 157,

    G_UMULFIXSAT  = 158,

    G_SDIVFIX = 159,

    G_UDIVFIX = 160,

    G_SDIVFIXSAT  = 161,

    G_UDIVFIXSAT  = 162,

    G_FADD  = 163,

    G_FSUB  = 164,

    G_FMUL  = 165,

    G_FMA = 166,

    G_FMAD  = 167,

    G_FDIV  = 168,

    G_FREM  = 169,

    G_FPOW  = 170,

    G_FPOWI = 171,

    G_FEXP  = 172,

    G_FEXP2 = 173,

    G_FEXP10  = 174,

    G_FLOG  = 175,

    G_FLOG2 = 176,

    G_FLOG10  = 177,

    G_FLDEXP  = 178,

    G_FFREXP  = 179,

    G_FNEG  = 180,

    G_FPEXT = 181,

    G_FPTRUNC = 182,

    G_FPTOSI  = 183,

    G_FPTOUI  = 184,

    G_SITOFP  = 185,

    G_UITOFP  = 186,

    G_FABS  = 187,

    G_FCOPYSIGN = 188,

    G_IS_FPCLASS  = 189,

    G_FCANONICALIZE = 190,

    G_FMINNUM = 191,

    G_FMAXNUM = 192,

    G_FMINNUM_IEEE  = 193,

    G_FMAXNUM_IEEE  = 194,

    G_FMINIMUM  = 195,

    G_FMAXIMUM  = 196,

    G_GET_FPENV = 197,

    G_SET_FPENV = 198,

    G_RESET_FPENV = 199,

    G_GET_FPMODE  = 200,

    G_SET_FPMODE  = 201,

    G_RESET_FPMODE  = 202,

    G_PTR_ADD = 203,

    G_PTRMASK = 204,

    G_SMIN  = 205,

    G_SMAX  = 206,

    G_UMIN  = 207,

    G_UMAX  = 208,

    G_ABS = 209,

    G_LROUND  = 210,

    G_LLROUND = 211,

    G_BR  = 212,

    G_BRJT  = 213,

    G_INSERT_VECTOR_ELT = 214,

    G_EXTRACT_VECTOR_ELT  = 215,

    G_SHUFFLE_VECTOR  = 216,

    G_CTTZ  = 217,

    G_CTTZ_ZERO_UNDEF = 218,

    G_CTLZ  = 219,

    G_CTLZ_ZERO_UNDEF = 220,

    G_CTPOP = 221,

    G_BSWAP = 222,

    G_BITREVERSE  = 223,

    G_FCEIL = 224,

    G_FCOS  = 225,

    G_FSIN  = 226,

    G_FSQRT = 227,

    G_FFLOOR  = 228,

    G_FRINT = 229,

    G_FNEARBYINT  = 230,

    G_ADDRSPACE_CAST  = 231,

    G_BLOCK_ADDR  = 232,

    G_JUMP_TABLE  = 233,

    G_DYN_STACKALLOC  = 234,

    G_STACKSAVE = 235,

    G_STACKRESTORE  = 236,

    G_STRICT_FADD = 237,

    G_STRICT_FSUB = 238,

    G_STRICT_FMUL = 239,

    G_STRICT_FDIV = 240,

    G_STRICT_FREM = 241,

    G_STRICT_FMA  = 242,

    G_STRICT_FSQRT  = 243,

    G_STRICT_FLDEXP = 244,

    G_READ_REGISTER = 245,

    G_WRITE_REGISTER  = 246,

    G_MEMCPY  = 247,

    G_MEMCPY_INLINE = 248,

    G_MEMMOVE = 249,

    G_MEMSET  = 250,

    G_BZERO = 251,

    G_VECREDUCE_SEQ_FADD  = 252,

    G_VECREDUCE_SEQ_FMUL  = 253,

    G_VECREDUCE_FADD  = 254,

    G_VECREDUCE_FMUL  = 255,

    G_VECREDUCE_FMAX  = 256,

    G_VECREDUCE_FMIN  = 257,

    G_VECREDUCE_FMAXIMUM  = 258,

    G_VECREDUCE_FMINIMUM  = 259,

    G_VECREDUCE_ADD = 260,

    G_VECREDUCE_MUL = 261,

    G_VECREDUCE_AND = 262,

    G_VECREDUCE_OR  = 263,

    G_VECREDUCE_XOR = 264,

    G_VECREDUCE_SMAX  = 265,

    G_VECREDUCE_SMIN  = 266,

    G_VECREDUCE_UMAX  = 267,

    G_VECREDUCE_UMIN  = 268,

    G_SBFX  = 269,

    G_UBFX  = 270,

    BRANCH  = 271,

    BRANCH_COND_f32 = 272,

    BRANCH_COND_i32 = 273,

    BREAK = 274,

    BREAKC_f32  = 275,

    BREAKC_i32  = 276,

    BREAK_LOGICALNZ_f32 = 277,

    BREAK_LOGICALNZ_i32 = 278,

    BREAK_LOGICALZ_f32  = 279,

    BREAK_LOGICALZ_i32  = 280,

    CONST_COPY  = 281,

    CONTINUE  = 282,

    CONTINUEC_f32 = 283,

    CONTINUEC_i32 = 284,

    CONTINUE_LOGICALNZ_f32  = 285,

    CONTINUE_LOGICALNZ_i32  = 286,

    CONTINUE_LOGICALZ_f32 = 287,

    CONTINUE_LOGICALZ_i32 = 288,

    CUBE_eg_pseudo  = 289,

    CUBE_r600_pseudo  = 290,

    DEFAULT = 291,

    DOT_4 = 292,

    DUMMY_CHAIN = 293,

    ELSE  = 294,

    END = 295,

    ENDFUNC = 296,

    ENDIF = 297,

    ENDLOOP = 298,

    ENDMAIN = 299,

    ENDSWITCH = 300,

    FABS_R600 = 301,

    FNEG_R600 = 302,

    FUNC  = 303,

    IFC_f32 = 304,

    IFC_i32 = 305,

    IF_LOGICALNZ_f32  = 306,

    IF_LOGICALNZ_i32  = 307,

    IF_LOGICALZ_f32 = 308,

    IF_LOGICALZ_i32 = 309,

    IF_PREDICATE_SET  = 310,

    JUMP  = 311,

    JUMP_COND = 312,

    MASK_WRITE  = 313,

    MOV_IMM_F32 = 314,

    MOV_IMM_GLOBAL_ADDR = 315,

    MOV_IMM_I32 = 316,

    PRED_X  = 317,

    R600_EXTRACT_ELT_V2 = 318,

    R600_EXTRACT_ELT_V4 = 319,

    R600_INSERT_ELT_V2  = 320,

    R600_INSERT_ELT_V4  = 321,

    R600_RegisterLoad = 322,

    R600_RegisterStore  = 323,

    RETDYN  = 324,

    RETURN  = 325,

    TXD = 326,

    TXD_SHADOW  = 327,

    WHILELOOP = 328,

    ADD = 329,

    ADDC_UINT = 330,

    ADD_INT = 331,

    ALU_CLAUSE  = 332,

    AND_INT = 333,

    ASHR_eg = 334,

    ASHR_r600 = 335,

    BCNT_INT  = 336,

    BFE_INT_eg  = 337,

    BFE_UINT_eg = 338,

    BFI_INT_eg  = 339,

    BFM_INT_eg  = 340,

    BIT_ALIGN_INT_eg  = 341,

    CEIL  = 342,

    CF_ALU  = 343,

    CF_ALU_BREAK  = 344,

    CF_ALU_CONTINUE = 345,

    CF_ALU_ELSE_AFTER = 346,

    CF_ALU_POP_AFTER  = 347,

    CF_ALU_PUSH_BEFORE  = 348,

    CF_CALL_FS_EG = 349,

    CF_CALL_FS_R600 = 350,

    CF_CONTINUE_EG  = 351,

    CF_CONTINUE_R600  = 352,

    CF_ELSE_EG  = 353,

    CF_ELSE_R600  = 354,

    CF_END_CM = 355,

    CF_END_EG = 356,

    CF_END_R600 = 357,

    CF_JUMP_EG  = 358,

    CF_JUMP_R600  = 359,

    CF_PUSH_EG  = 360,

    CF_PUSH_ELSE_R600 = 361,

    CF_TC_EG  = 362,

    CF_TC_R600  = 363,

    CF_VC_EG  = 364,

    CF_VC_R600  = 365,

    CNDE_INT  = 366,

    CNDE_eg = 367,

    CNDE_r600 = 368,

    CNDGE_INT = 369,

    CNDGE_eg  = 370,

    CNDGE_r600  = 371,

    CNDGT_INT = 372,

    CNDGT_eg  = 373,

    CNDGT_r600  = 374,

    COS_cm  = 375,

    COS_eg  = 376,

    COS_r600  = 377,

    COS_r700  = 378,

    CUBE_eg_real  = 379,

    CUBE_r600_real  = 380,

    DOT4_eg = 381,

    DOT4_r600 = 382,

    EG_ExportBuf  = 383,

    EG_ExportSwz  = 384,

    END_LOOP_EG = 385,

    END_LOOP_R600 = 386,

    EXP_IEEE_cm = 387,

    EXP_IEEE_eg = 388,

    EXP_IEEE_r600 = 389,

    FETCH_CLAUSE  = 390,

    FFBH_UINT = 391,

    FFBL_INT  = 392,

    FLOOR = 393,

    FLT16_TO_FLT32  = 394,

    FLT32_TO_FLT16  = 395,

    FLT_TO_INT_eg = 396,

    FLT_TO_INT_r600 = 397,

    FLT_TO_UINT_eg  = 398,

    FLT_TO_UINT_r600  = 399,

    FMA_eg  = 400,

    FRACT = 401,

    GROUP_BARRIER = 402,

    INTERP_LOAD_P0  = 403,

    INTERP_PAIR_XY  = 404,

    INTERP_PAIR_ZW  = 405,

    INTERP_VEC_LOAD = 406,

    INTERP_XY = 407,

    INTERP_ZW = 408,

    INT_TO_FLT_eg = 409,

    INT_TO_FLT_r600 = 410,

    KILLGT  = 411,

    LDS_ADD = 412,

    LDS_ADD_RET = 413,

    LDS_AND = 414,

    LDS_AND_RET = 415,

    LDS_BYTE_READ_RET = 416,

    LDS_BYTE_WRITE  = 417,

    LDS_CMPST = 418,

    LDS_CMPST_RET = 419,

    LDS_MAX_INT = 420,

    LDS_MAX_INT_RET = 421,

    LDS_MAX_UINT  = 422,

    LDS_MAX_UINT_RET  = 423,

    LDS_MIN_INT = 424,

    LDS_MIN_INT_RET = 425,

    LDS_MIN_UINT  = 426,

    LDS_MIN_UINT_RET  = 427,

    LDS_OR  = 428,

    LDS_OR_RET  = 429,

    LDS_READ_RET  = 430,

    LDS_SHORT_READ_RET  = 431,

    LDS_SHORT_WRITE = 432,

    LDS_SUB = 433,

    LDS_SUB_RET = 434,

    LDS_UBYTE_READ_RET  = 435,

    LDS_USHORT_READ_RET = 436,

    LDS_WRITE = 437,

    LDS_WRXCHG  = 438,

    LDS_WRXCHG_RET  = 439,

    LDS_XOR = 440,

    LDS_XOR_RET = 441,

    LITERALS  = 442,

    LOG_CLAMPED_eg  = 443,

    LOG_CLAMPED_r600  = 444,

    LOG_IEEE_cm = 445,

    LOG_IEEE_eg = 446,

    LOG_IEEE_r600 = 447,

    LOOP_BREAK_EG = 448,

    LOOP_BREAK_R600 = 449,

    LSHL_eg = 450,

    LSHL_r600 = 451,

    LSHR_eg = 452,

    LSHR_r600 = 453,

    MAX = 454,

    MAX_DX10  = 455,

    MAX_INT = 456,

    MAX_UINT  = 457,

    MIN = 458,

    MIN_DX10  = 459,

    MIN_INT = 460,

    MIN_UINT  = 461,

    MOV = 462,

    MOVA_INT_eg = 463,

    MUL = 464,

    MULADD_IEEE_eg  = 465,

    MULADD_IEEE_r600  = 466,

    MULADD_INT24_cm = 467,

    MULADD_UINT24_eg  = 468,

    MULADD_eg = 469,

    MULADD_r600 = 470,

    MULHI_INT_cm  = 471,

    MULHI_INT_cm24  = 472,

    MULHI_INT_eg  = 473,

    MULHI_INT_r600  = 474,

    MULHI_UINT24_eg = 475,

    MULHI_UINT_cm = 476,

    MULHI_UINT_cm24 = 477,

    MULHI_UINT_eg = 478,

    MULHI_UINT_r600 = 479,

    MULLO_INT_cm  = 480,

    MULLO_INT_eg  = 481,

    MULLO_INT_r600  = 482,

    MULLO_UINT_cm = 483,

    MULLO_UINT_eg = 484,

    MULLO_UINT_r600 = 485,

    MUL_IEEE  = 486,

    MUL_INT24_cm  = 487,

    MUL_LIT_eg  = 488,

    MUL_LIT_r600  = 489,

    MUL_UINT24_eg = 490,

    NOT_INT = 491,

    OR_INT  = 492,

    PAD = 493,

    POP_EG  = 494,

    POP_R600  = 495,

    PRED_SETE = 496,

    PRED_SETE_INT = 497,

    PRED_SETGE  = 498,

    PRED_SETGE_INT  = 499,

    PRED_SETGT  = 500,

    PRED_SETGT_INT  = 501,

    PRED_SETNE  = 502,

    PRED_SETNE_INT  = 503,

    R600_ExportBuf  = 504,

    R600_ExportSwz  = 505,

    RAT_ATOMIC_ADD_NORET  = 506,

    RAT_ATOMIC_ADD_RTN  = 507,

    RAT_ATOMIC_AND_NORET  = 508,

    RAT_ATOMIC_AND_RTN  = 509,

    RAT_ATOMIC_CMPXCHG_INT_NORET  = 510,

    RAT_ATOMIC_CMPXCHG_INT_RTN  = 511,

    RAT_ATOMIC_DEC_UINT_NORET = 512,

    RAT_ATOMIC_DEC_UINT_RTN = 513,

    RAT_ATOMIC_INC_UINT_NORET = 514,

    RAT_ATOMIC_INC_UINT_RTN = 515,

    RAT_ATOMIC_MAX_INT_NORET  = 516,

    RAT_ATOMIC_MAX_INT_RTN  = 517,

    RAT_ATOMIC_MAX_UINT_NORET = 518,

    RAT_ATOMIC_MAX_UINT_RTN = 519,

    RAT_ATOMIC_MIN_INT_NORET  = 520,

    RAT_ATOMIC_MIN_INT_RTN  = 521,

    RAT_ATOMIC_MIN_UINT_NORET = 522,

    RAT_ATOMIC_MIN_UINT_RTN = 523,

    RAT_ATOMIC_OR_NORET = 524,

    RAT_ATOMIC_OR_RTN = 525,

    RAT_ATOMIC_RSUB_NORET = 526,

    RAT_ATOMIC_RSUB_RTN = 527,

    RAT_ATOMIC_SUB_NORET  = 528,

    RAT_ATOMIC_SUB_RTN  = 529,

    RAT_ATOMIC_XCHG_INT_NORET = 530,

    RAT_ATOMIC_XCHG_INT_RTN = 531,

    RAT_ATOMIC_XOR_NORET  = 532,

    RAT_ATOMIC_XOR_RTN  = 533,

    RAT_MSKOR = 534,

    RAT_STORE_DWORD128  = 535,

    RAT_STORE_DWORD32 = 536,

    RAT_STORE_DWORD64 = 537,

    RAT_STORE_TYPED_cm  = 538,

    RAT_STORE_TYPED_eg  = 539,

    RAT_WRITE_CACHELESS_128_eg  = 540,

    RAT_WRITE_CACHELESS_32_eg = 541,

    RAT_WRITE_CACHELESS_64_eg = 542,

    RECIPSQRT_CLAMPED_cm  = 543,

    RECIPSQRT_CLAMPED_eg  = 544,

    RECIPSQRT_CLAMPED_r600  = 545,

    RECIPSQRT_IEEE_cm = 546,

    RECIPSQRT_IEEE_eg = 547,

    RECIPSQRT_IEEE_r600 = 548,

    RECIP_CLAMPED_cm  = 549,

    RECIP_CLAMPED_eg  = 550,

    RECIP_CLAMPED_r600  = 551,

    RECIP_IEEE_cm = 552,

    RECIP_IEEE_eg = 553,

    RECIP_IEEE_r600 = 554,

    RECIP_UINT_eg = 555,

    RECIP_UINT_r600 = 556,

    RNDNE = 557,

    SETE  = 558,

    SETE_DX10 = 559,

    SETE_INT  = 560,

    SETGE_DX10  = 561,

    SETGE_INT = 562,

    SETGE_UINT  = 563,

    SETGT_DX10  = 564,

    SETGT_INT = 565,

    SETGT_UINT  = 566,

    SETNE_DX10  = 567,

    SETNE_INT = 568,

    SGE = 569,

    SGT = 570,

    SIN_cm  = 571,

    SIN_eg  = 572,

    SIN_r600  = 573,

    SIN_r700  = 574,

    SNE = 575,

    SUBB_UINT = 576,

    SUB_INT = 577,

    TEX_GET_GRADIENTS_H = 578,

    TEX_GET_GRADIENTS_V = 579,

    TEX_GET_TEXTURE_RESINFO = 580,

    TEX_LD  = 581,

    TEX_LDPTR = 582,

    TEX_SAMPLE  = 583,

    TEX_SAMPLE_C  = 584,

    TEX_SAMPLE_C_G  = 585,

    TEX_SAMPLE_C_L  = 586,

    TEX_SAMPLE_C_LB = 587,

    TEX_SAMPLE_G  = 588,

    TEX_SAMPLE_L  = 589,

    TEX_SAMPLE_LB = 590,

    TEX_SET_GRADIENTS_H = 591,

    TEX_SET_GRADIENTS_V = 592,

    TEX_VTX_CONSTBUF  = 593,

    TEX_VTX_TEXBUF  = 594,

    TRUNC = 595,

    UINT_TO_FLT_eg  = 596,

    UINT_TO_FLT_r600  = 597,

    VTX_READ_128_cm = 598,

    VTX_READ_128_eg = 599,

    VTX_READ_16_cm  = 600,

    VTX_READ_16_eg  = 601,

    VTX_READ_32_cm  = 602,

    VTX_READ_32_eg  = 603,

    VTX_READ_64_cm  = 604,

    VTX_READ_64_eg  = 605,

    VTX_READ_8_cm = 606,

    VTX_READ_8_eg = 607,

    WHILE_LOOP_EG = 608,

    WHILE_LOOP_R600 = 609,

    XOR_INT = 610,

    INSTRUCTION_LIST_END = 611

  };

} // end namespace R600

} // end namespace llvm

#endif // GET_INSTRINFO_ENUM

#ifdef GET_INSTRINFO_SCHED_ENUM

#undef GET_INSTRINFO_SCHED_ENUM

namespace llvm {

namespace R600 {

namespace Sched {

  enum {

    NoInstrModel  = 0,

    NullALU = 1,

    VecALU  = 2,

    AnyALU  = 3,

    TransALU  = 4,

    XALU  = 5,

    SCHED_LIST_END = 6

  };

} // end namespace Sched

} // end namespace R600

} // end namespace llvm

#endif // GET_INSTRINFO_SCHED_ENUM

#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)

namespace llvm {

struct R600InstrTable {

  MCInstrDesc Insts[611];

  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");

  MCOperandInfo OperandInfo[450];

  static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");

  MCPhysReg ImplicitOps[1];

};

} // end namespace llvm

#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)

#ifdef GET_INSTRINFO_MC_DESC

#undef GET_INSTRINFO_MC_DESC

namespace llvm {

static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);

static constexpr unsigned R600ImpOpBase = sizeof R600InstrTable::OperandInfo / (sizeof(MCPhysReg));

extern const R600InstrTable R600Descs = {

  {

    { 610,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #610 = XOR_INT

    { 609,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #609 = WHILE_LOOP_R600

    { 608,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #608 = WHILE_LOOP_EG

    { 607,  4,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  438,  0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // Inst #607 = VTX_READ_8_eg

    { 606,  4,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  438,  0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // Inst #606 = VTX_READ_8_cm

    { 605,  4,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  446,  0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // Inst #605 = VTX_READ_64_eg

    { 604,  4,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  446,  0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // Inst #604 = VTX_READ_64_cm

    { 603,  4,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  442,  0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // Inst #603 = VTX_READ_32_eg

    { 602,  4,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  442,  0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // Inst #602 = VTX_READ_32_cm

    { 601,  4,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  438,  0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // Inst #601 = VTX_READ_16_eg

    { 600,  4,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  438,  0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // Inst #600 = VTX_READ_16_cm

    { 599,  4,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  434,  0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // Inst #599 = VTX_READ_128_eg

    { 598,  4,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  434,  0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // Inst #598 = VTX_READ_128_cm

    { 597,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #597 = UINT_TO_FLT_r600

    { 596,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #596 = UINT_TO_FLT_eg

    { 595,  14, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #595 = TRUNC

    { 594,  4,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  434,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x1000ULL },  // Inst #594 = TEX_VTX_TEXBUF

    { 593,  4,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  434,  0, 0x1000ULL },  // Inst #593 = TEX_VTX_CONSTBUF

    { 592,  19, 1,  0,  1,  0,  0,  R600ImpOpBase + 0,  415,  0, 0x2000ULL },  // Inst #592 = TEX_SET_GRADIENTS_V

    { 591,  19, 1,  0,  1,  0,  0,  R600ImpOpBase + 0,  415,  0, 0x2000ULL },  // Inst #591 = TEX_SET_GRADIENTS_H

    { 590,  19, 1,  0,  1,  0,  0,  R600ImpOpBase + 0,  415,  0, 0x2000ULL },  // Inst #590 = TEX_SAMPLE_LB

    { 589,  19, 1,  0,  1,  0,  0,  R600ImpOpBase + 0,  415,  0, 0x2000ULL },  // Inst #589 = TEX_SAMPLE_L

    { 588,  19, 1,  0,  1,  0,  0,  R600ImpOpBase + 0,  415,  0, 0x2000ULL },  // Inst #588 = TEX_SAMPLE_G

    { 587,  19, 1,  0,  1,  0,  0,  R600ImpOpBase + 0,  415,  0, 0x2000ULL },  // Inst #587 = TEX_SAMPLE_C_LB

    { 586,  19, 1,  0,  1,  0,  0,  R600ImpOpBase + 0,  415,  0, 0x2000ULL },  // Inst #586 = TEX_SAMPLE_C_L

    { 585,  19, 1,  0,  1,  0,  0,  R600ImpOpBase + 0,  415,  0, 0x2000ULL },  // Inst #585 = TEX_SAMPLE_C_G

    { 584,  19, 1,  0,  1,  0,  0,  R600ImpOpBase + 0,  415,  0, 0x2000ULL },  // Inst #584 = TEX_SAMPLE_C

    { 583,  19, 1,  0,  1,  0,  0,  R600ImpOpBase + 0,  415,  0, 0x2000ULL },  // Inst #583 = TEX_SAMPLE

    { 582,  19, 1,  0,  1,  0,  0,  R600ImpOpBase + 0,  415,  0, 0x2000ULL },  // Inst #582 = TEX_LDPTR

    { 581,  19, 1,  0,  1,  0,  0,  R600ImpOpBase + 0,  415,  0, 0x2000ULL },  // Inst #581 = TEX_LD

    { 580,  19, 1,  0,  1,  0,  0,  R600ImpOpBase + 0,  415,  0, 0x2000ULL },  // Inst #580 = TEX_GET_TEXTURE_RESINFO

    { 579,  19, 1,  0,  1,  0,  0,  R600ImpOpBase + 0,  415,  0, 0x2000ULL },  // Inst #579 = TEX_GET_GRADIENTS_V

    { 578,  19, 1,  0,  1,  0,  0,  R600ImpOpBase + 0,  415,  0, 0x2000ULL },  // Inst #578 = TEX_GET_GRADIENTS_H

    { 577,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #577 = SUB_INT

    { 576,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #576 = SUBB_UINT

    { 575,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #575 = SNE

    { 574,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4610ULL },  // Inst #574 = SIN_r700

    { 573,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4610ULL },  // Inst #573 = SIN_r600

    { 572,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4610ULL },  // Inst #572 = SIN_eg

    { 571,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4650ULL },  // Inst #571 = SIN_cm

    { 570,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #570 = SGT

    { 569,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #569 = SGE

    { 568,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #568 = SETNE_INT

    { 567,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #567 = SETNE_DX10

    { 566,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #566 = SETGT_UINT

    { 565,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #565 = SETGT_INT

    { 564,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #564 = SETGT_DX10

    { 563,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #563 = SETGE_UINT

    { 562,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #562 = SETGE_INT

    { 561,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #561 = SETGE_DX10

    { 560,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #560 = SETE_INT

    { 559,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #559 = SETE_DX10

    { 558,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #558 = SETE

    { 557,  14, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #557 = RNDNE

    { 556,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #556 = RECIP_UINT_r600

    { 555,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #555 = RECIP_UINT_eg

    { 554,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #554 = RECIP_IEEE_r600

    { 553,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #553 = RECIP_IEEE_eg

    { 552,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4640ULL },  // Inst #552 = RECIP_IEEE_cm

    { 551,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #551 = RECIP_CLAMPED_r600

    { 550,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #550 = RECIP_CLAMPED_eg

    { 549,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4640ULL },  // Inst #549 = RECIP_CLAMPED_cm

    { 548,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #548 = RECIPSQRT_IEEE_r600

    { 547,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #547 = RECIPSQRT_IEEE_eg

    { 546,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4640ULL },  // Inst #546 = RECIPSQRT_IEEE_cm

    { 545,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #545 = RECIPSQRT_CLAMPED_r600

    { 544,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #544 = RECIPSQRT_CLAMPED_eg

    { 543,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4640ULL },  // Inst #543 = RECIPSQRT_CLAMPED_cm

    { 542,  3,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  412,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL },  // Inst #542 = RAT_WRITE_CACHELESS_64_eg

    { 541,  3,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  409,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL },  // Inst #541 = RAT_WRITE_CACHELESS_32_eg

    { 540,  3,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  406,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL },  // Inst #540 = RAT_WRITE_CACHELESS_128_eg

    { 539,  4,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  402,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #539 = RAT_STORE_TYPED_eg

    { 538,  4,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  402,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #538 = RAT_STORE_TYPED_cm

    { 537,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  400,  0|(1ULL<<MCID::MayStore), 0x20000ULL },  // Inst #537 = RAT_STORE_DWORD64

    { 536,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  398,  0|(1ULL<<MCID::MayStore), 0x20000ULL },  // Inst #536 = RAT_STORE_DWORD32

    { 535,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  396,  0|(1ULL<<MCID::MayStore), 0x20000ULL },  // Inst #535 = RAT_STORE_DWORD128

    { 534,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  396,  0|(1ULL<<MCID::MayStore), 0x20000ULL },  // Inst #534 = RAT_MSKOR

    { 533,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #533 = RAT_ATOMIC_XOR_RTN

    { 532,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #532 = RAT_ATOMIC_XOR_NORET

    { 531,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #531 = RAT_ATOMIC_XCHG_INT_RTN

    { 530,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #530 = RAT_ATOMIC_XCHG_INT_NORET

    { 529,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #529 = RAT_ATOMIC_SUB_RTN

    { 528,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #528 = RAT_ATOMIC_SUB_NORET

    { 527,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #527 = RAT_ATOMIC_RSUB_RTN

    { 526,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #526 = RAT_ATOMIC_RSUB_NORET

    { 525,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #525 = RAT_ATOMIC_OR_RTN

    { 524,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #524 = RAT_ATOMIC_OR_NORET

    { 523,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #523 = RAT_ATOMIC_MIN_UINT_RTN

    { 522,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #522 = RAT_ATOMIC_MIN_UINT_NORET

    { 521,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #521 = RAT_ATOMIC_MIN_INT_RTN

    { 520,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #520 = RAT_ATOMIC_MIN_INT_NORET

    { 519,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #519 = RAT_ATOMIC_MAX_UINT_RTN

    { 518,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #518 = RAT_ATOMIC_MAX_UINT_NORET

    { 517,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #517 = RAT_ATOMIC_MAX_INT_RTN

    { 516,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #516 = RAT_ATOMIC_MAX_INT_NORET

    { 515,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #515 = RAT_ATOMIC_INC_UINT_RTN

    { 514,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #514 = RAT_ATOMIC_INC_UINT_NORET

    { 513,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #513 = RAT_ATOMIC_DEC_UINT_RTN

    { 512,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #512 = RAT_ATOMIC_DEC_UINT_NORET

    { 511,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #511 = RAT_ATOMIC_CMPXCHG_INT_RTN

    { 510,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #510 = RAT_ATOMIC_CMPXCHG_INT_NORET

    { 509,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #509 = RAT_ATOMIC_AND_RTN

    { 508,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #508 = RAT_ATOMIC_AND_NORET

    { 507,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #507 = RAT_ATOMIC_ADD_RTN

    { 506,  3,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  393,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #506 = RAT_ATOMIC_ADD_NORET

    { 505,  9,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  321,  0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #505 = R600_ExportSwz

    { 504,  7,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  314,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #504 = R600_ExportBuf

    { 503,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #503 = PRED_SETNE_INT

    { 502,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #502 = PRED_SETNE

    { 501,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #501 = PRED_SETGT_INT

    { 500,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #500 = PRED_SETGT

    { 499,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #499 = PRED_SETGE_INT

    { 498,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #498 = PRED_SETGE

    { 497,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #497 = PRED_SETE_INT

    { 496,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #496 = PRED_SETE

    { 495,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #495 = POP_R600

    { 494,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #494 = POP_EG

    { 493,  0,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #493 = PAD

    { 492,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #492 = OR_INT

    { 491,  14, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #491 = NOT_INT

    { 490,  21, 1,  0,  2,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #490 = MUL_UINT24_eg

    { 489,  19, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  286,  0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #489 = MUL_LIT_r600

    { 488,  19, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  286,  0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #488 = MUL_LIT_eg

    { 487,  21, 1,  0,  2,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #487 = MUL_INT24_cm

    { 486,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #486 = MUL_IEEE

    { 485,  21, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #485 = MULLO_UINT_r600

    { 484,  21, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #484 = MULLO_UINT_eg

    { 483,  21, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a40ULL },  // Inst #483 = MULLO_UINT_cm

    { 482,  21, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #482 = MULLO_INT_r600

    { 481,  21, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #481 = MULLO_INT_eg

    { 480,  21, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a40ULL },  // Inst #480 = MULLO_INT_cm

    { 479,  21, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #479 = MULHI_UINT_r600

    { 478,  21, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #478 = MULHI_UINT_eg

    { 477,  21, 1,  0,  2,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a40ULL },  // Inst #477 = MULHI_UINT_cm24

    { 476,  21, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a40ULL },  // Inst #476 = MULHI_UINT_cm

    { 475,  21, 1,  0,  2,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #475 = MULHI_UINT24_eg

    { 474,  21, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #474 = MULHI_INT_r600

    { 473,  21, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #473 = MULHI_INT_eg

    { 472,  21, 1,  0,  2,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a40ULL },  // Inst #472 = MULHI_INT_cm24

    { 471,  21, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a40ULL },  // Inst #471 = MULHI_INT_cm

    { 470,  19, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  286,  0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #470 = MULADD_r600

    { 469,  19, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  286,  0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #469 = MULADD_eg

    { 468,  19, 1,  0,  2,  0,  0,  R600ImpOpBase + 0,  286,  0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #468 = MULADD_UINT24_eg

    { 467,  19, 1,  0,  2,  0,  0,  R600ImpOpBase + 0,  286,  0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #467 = MULADD_INT24_cm

    { 466,  19, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  286,  0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #466 = MULADD_IEEE_r600

    { 465,  19, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  286,  0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #465 = MULADD_IEEE_eg

    { 464,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #464 = MUL

    { 463,  14, 1,  0,  2,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4600ULL },  // Inst #463 = MOVA_INT_eg

    { 462,  14, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #462 = MOV

    { 461,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #461 = MIN_UINT

    { 460,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #460 = MIN_INT

    { 459,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #459 = MIN_DX10

    { 458,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #458 = MIN

    { 457,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #457 = MAX_UINT

    { 456,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #456 = MAX_INT

    { 455,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #455 = MAX_DX10

    { 454,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #454 = MAX

    { 453,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #453 = LSHR_r600

    { 452,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #452 = LSHR_eg

    { 451,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #451 = LSHL_r600

    { 450,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #450 = LSHL_eg

    { 449,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #449 = LOOP_BREAK_R600

    { 448,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #448 = LOOP_BREAK_EG

    { 447,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #447 = LOG_IEEE_r600

    { 446,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #446 = LOG_IEEE_eg

    { 445,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4640ULL },  // Inst #445 = LOG_IEEE_cm

    { 444,  14, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #444 = LOG_CLAMPED_r600

    { 443,  14, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #443 = LOG_CLAMPED_eg

    { 442,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  13, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #442 = LITERALS

    { 441,  10, 1,  0,  5,  0,  0,  R600ImpOpBase + 0,  351,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // Inst #441 = LDS_XOR_RET

    { 440,  9,  0,  0,  5,  0,  0,  R600ImpOpBase + 0,  342,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // Inst #440 = LDS_XOR

    { 439,  10, 1,  0,  5,  0,  0,  R600ImpOpBase + 0,  351,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // Inst #439 = LDS_WRXCHG_RET

    { 438,  9,  0,  0,  5,  0,  0,  R600ImpOpBase + 0,  342,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // Inst #438 = LDS_WRXCHG

    { 437,  9,  0,  0,  5,  0,  0,  R600ImpOpBase + 0,  342,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL },  // Inst #437 = LDS_WRITE

    { 436,  7,  1,  0,  5,  0,  0,  R600ImpOpBase + 0,  361,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL },  // Inst #436 = LDS_USHORT_READ_RET

    { 435,  7,  1,  0,  5,  0,  0,  R600ImpOpBase + 0,  361,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL },  // Inst #435 = LDS_UBYTE_READ_RET

    { 434,  10, 1,  0,  5,  0,  0,  R600ImpOpBase + 0,  351,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // Inst #434 = LDS_SUB_RET

    { 433,  9,  0,  0,  5,  0,  0,  R600ImpOpBase + 0,  342,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // Inst #433 = LDS_SUB

    { 432,  9,  0,  0,  5,  0,  0,  R600ImpOpBase + 0,  342,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL },  // Inst #432 = LDS_SHORT_WRITE

    { 431,  7,  1,  0,  5,  0,  0,  R600ImpOpBase + 0,  361,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL },  // Inst #431 = LDS_SHORT_READ_RET

    { 430,  7,  1,  0,  5,  0,  0,  R600ImpOpBase + 0,  361,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL },  // Inst #430 = LDS_READ_RET

    { 429,  10, 1,  0,  5,  0,  0,  R600ImpOpBase + 0,  351,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // Inst #429 = LDS_OR_RET

    { 428,  9,  0,  0,  5,  0,  0,  R600ImpOpBase + 0,  342,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // Inst #428 = LDS_OR

    { 427,  10, 1,  0,  5,  0,  0,  R600ImpOpBase + 0,  351,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // Inst #427 = LDS_MIN_UINT_RET

    { 426,  9,  0,  0,  5,  0,  0,  R600ImpOpBase + 0,  342,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // Inst #426 = LDS_MIN_UINT

    { 425,  10, 1,  0,  5,  0,  0,  R600ImpOpBase + 0,  351,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // Inst #425 = LDS_MIN_INT_RET

    { 424,  9,  0,  0,  5,  0,  0,  R600ImpOpBase + 0,  342,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // Inst #424 = LDS_MIN_INT

    { 423,  10, 1,  0,  5,  0,  0,  R600ImpOpBase + 0,  351,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // Inst #423 = LDS_MAX_UINT_RET

    { 422,  9,  0,  0,  5,  0,  0,  R600ImpOpBase + 0,  342,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // Inst #422 = LDS_MAX_UINT

    { 421,  10, 1,  0,  5,  0,  0,  R600ImpOpBase + 0,  351,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // Inst #421 = LDS_MAX_INT_RET

    { 420,  9,  0,  0,  5,  0,  0,  R600ImpOpBase + 0,  342,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // Inst #420 = LDS_MAX_INT

    { 419,  13, 1,  0,  5,  0,  0,  R600ImpOpBase + 0,  380,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x44200ULL },  // Inst #419 = LDS_CMPST_RET

    { 418,  12, 0,  0,  5,  0,  0,  R600ImpOpBase + 0,  368,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44200ULL },  // Inst #418 = LDS_CMPST

    { 417,  9,  0,  0,  5,  0,  0,  R600ImpOpBase + 0,  342,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL },  // Inst #417 = LDS_BYTE_WRITE

    { 416,  7,  1,  0,  5,  0,  0,  R600ImpOpBase + 0,  361,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL },  // Inst #416 = LDS_BYTE_READ_RET

    { 415,  10, 1,  0,  5,  0,  0,  R600ImpOpBase + 0,  351,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // Inst #415 = LDS_AND_RET

    { 414,  9,  0,  0,  5,  0,  0,  R600ImpOpBase + 0,  342,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // Inst #414 = LDS_AND

    { 413,  10, 1,  0,  5,  0,  0,  R600ImpOpBase + 0,  351,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // Inst #413 = LDS_ADD_RET

    { 412,  9,  0,  0,  5,  0,  0,  R600ImpOpBase + 0,  342,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // Inst #412 = LDS_ADD

    { 411,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4a00ULL },  // Inst #411 = KILLGT

    { 410,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #410 = INT_TO_FLT_r600

    { 409,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #409 = INT_TO_FLT_eg

    { 408,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #408 = INTERP_ZW

    { 407,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #407 = INTERP_XY

    { 406,  2,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  340,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #406 = INTERP_VEC_LOAD

    { 405,  5,  2,  0,  1,  0,  0,  R600ImpOpBase + 0,  335,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #405 = INTERP_PAIR_ZW

    { 404,  5,  2,  0,  1,  0,  0,  R600ImpOpBase + 0,  330,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #404 = INTERP_PAIR_XY

    { 403,  14, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #403 = INTERP_LOAD_P0

    { 402,  0,  0,  0,  3,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4000ULL },  // Inst #402 = GROUP_BARRIER

    { 401,  14, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #401 = FRACT

    { 400,  19, 1,  0,  2,  0,  0,  R600ImpOpBase + 0,  286,  0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #400 = FMA_eg

    { 399,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #399 = FLT_TO_UINT_r600

    { 398,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #398 = FLT_TO_UINT_eg

    { 397,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #397 = FLT_TO_INT_r600

    { 396,  14, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #396 = FLT_TO_INT_eg

    { 395,  14, 1,  0,  2,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #395 = FLT32_TO_FLT16

    { 394,  14, 1,  0,  2,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #394 = FLT16_TO_FLT32

    { 393,  14, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #393 = FLOOR

    { 392,  14, 1,  0,  2,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #392 = FFBL_INT

    { 391,  14, 1,  0,  2,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #391 = FFBH_UINT

    { 390,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #390 = FETCH_CLAUSE

    { 389,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #389 = EXP_IEEE_r600

    { 388,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #388 = EXP_IEEE_eg

    { 387,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4640ULL },  // Inst #387 = EXP_IEEE_cm

    { 386,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #386 = END_LOOP_R600

    { 385,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #385 = END_LOOP_EG

    { 384,  9,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  321,  0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #384 = EG_ExportSwz

    { 383,  7,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  314,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #383 = EG_ExportBuf

    { 382,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #382 = DOT4_r600

    { 381,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #381 = DOT4_eg

    { 380,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #380 = CUBE_r600_real

    { 379,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #379 = CUBE_eg_real

    { 378,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4610ULL },  // Inst #378 = COS_r700

    { 377,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4610ULL },  // Inst #377 = COS_r600

    { 376,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4610ULL },  // Inst #376 = COS_eg

    { 375,  14, 1,  0,  4,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4650ULL },  // Inst #375 = COS_cm

    { 374,  19, 1,  0,  2,  0,  0,  R600ImpOpBase + 0,  286,  0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #374 = CNDGT_r600

    { 373,  19, 1,  0,  2,  0,  0,  R600ImpOpBase + 0,  286,  0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #373 = CNDGT_eg

    { 372,  19, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  286,  0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #372 = CNDGT_INT

    { 371,  19, 1,  0,  2,  0,  0,  R600ImpOpBase + 0,  286,  0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #371 = CNDGE_r600

    { 370,  19, 1,  0,  2,  0,  0,  R600ImpOpBase + 0,  286,  0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #370 = CNDGE_eg

    { 369,  19, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  286,  0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #369 = CNDGE_INT

    { 368,  19, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  286,  0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #368 = CNDE_r600

    { 367,  19, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  286,  0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #367 = CNDE_eg

    { 366,  19, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  286,  0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #366 = CNDE_INT

    { 365,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #365 = CF_VC_R600

    { 364,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #364 = CF_VC_EG

    { 363,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #363 = CF_TC_R600

    { 362,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #362 = CF_TC_EG

    { 361,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #361 = CF_PUSH_ELSE_R600

    { 360,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #360 = CF_PUSH_EG

    { 359,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #359 = CF_JUMP_R600

    { 358,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #358 = CF_JUMP_EG

    { 357,  0,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #357 = CF_END_R600

    { 356,  0,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #356 = CF_END_EG

    { 355,  0,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #355 = CF_END_CM

    { 354,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #354 = CF_ELSE_R600

    { 353,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #353 = CF_ELSE_EG

    { 352,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #352 = CF_CONTINUE_R600

    { 351,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #351 = CF_CONTINUE_EG

    { 350,  0,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #350 = CF_CALL_FS_R600

    { 349,  0,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #349 = CF_CALL_FS_EG

    { 348,  9,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  305,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #348 = CF_ALU_PUSH_BEFORE

    { 347,  9,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  305,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #347 = CF_ALU_POP_AFTER

    { 346,  9,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  305,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #346 = CF_ALU_ELSE_AFTER

    { 345,  9,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  305,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #345 = CF_ALU_CONTINUE

    { 344,  9,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  305,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #344 = CF_ALU_BREAK

    { 343,  9,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  305,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #343 = CF_ALU

    { 342,  14, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #342 = CEIL

    { 341,  19, 1,  0,  2,  0,  0,  R600ImpOpBase + 0,  286,  0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #341 = BIT_ALIGN_INT_eg

    { 340,  21, 1,  0,  2,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #340 = BFM_INT_eg

    { 339,  19, 1,  0,  2,  0,  0,  R600ImpOpBase + 0,  286,  0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #339 = BFI_INT_eg

    { 338,  19, 1,  0,  2,  0,  0,  R600ImpOpBase + 0,  286,  0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #338 = BFE_UINT_eg

    { 337,  19, 1,  0,  2,  0,  0,  R600ImpOpBase + 0,  286,  0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #337 = BFE_INT_eg

    { 336,  14, 1,  0,  2,  0,  0,  R600ImpOpBase + 0,  272,  0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #336 = BCNT_INT

    { 335,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #335 = ASHR_r600

    { 334,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #334 = ASHR_eg

    { 333,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #333 = AND_INT

    { 332,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #332 = ALU_CLAUSE

    { 331,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #331 = ADD_INT

    { 330,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #330 = ADDC_UINT

    { 329,  21, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  251,  0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #329 = ADD

    { 328,  0,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #328 = WHILELOOP

    { 327,  7,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  244,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL },  // Inst #327 = TXD_SHADOW

    { 326,  7,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  244,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL },  // Inst #326 = TXD

    { 325,  0,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #325 = RETURN

    { 324,  0,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #324 = RETDYN

    { 323,  4,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  240,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000000000000000ULL },  // Inst #323 = R600_RegisterStore

    { 322,  4,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  240,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8000000000000000ULL },  // Inst #322 = R600_RegisterLoad

    { 321,  4,  1,  0,  3,  0,  0,  R600ImpOpBase + 0,  236,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #321 = R600_INSERT_ELT_V4

    { 320,  4,  1,  0,  3,  0,  0,  R600ImpOpBase + 0,  232,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #320 = R600_INSERT_ELT_V2

    { 319,  3,  1,  0,  3,  0,  0,  R600ImpOpBase + 0,  229,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #319 = R600_EXTRACT_ELT_V4

    { 318,  3,  1,  0,  3,  0,  0,  R600ImpOpBase + 0,  226,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #318 = R600_EXTRACT_ELT_V2

    { 317,  4,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  222,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL },  // Inst #317 = PRED_X

    { 316,  2,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  145,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #316 = MOV_IMM_I32

    { 315,  2,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  145,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #315 = MOV_IMM_GLOBAL_ADDR

    { 314,  2,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  145,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #314 = MOV_IMM_F32

    { 313,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  144,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #313 = MASK_WRITE

    { 312,  2,  0,  0,  3,  0,  0,  R600ImpOpBase + 0,  220,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #312 = JUMP_COND

    { 311,  1,  0,  0,  3,  0,  0,  R600ImpOpBase + 0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #311 = JUMP

    { 310,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  144,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #310 = IF_PREDICATE_SET

    { 309,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  144,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #309 = IF_LOGICALZ_i32

    { 308,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  144,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #308 = IF_LOGICALZ_f32

    { 307,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  144,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #307 = IF_LOGICALNZ_i32

    { 306,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  144,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #306 = IF_LOGICALNZ_f32

    { 305,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  142,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #305 = IFC_i32

    { 304,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  142,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #304 = IFC_f32

    { 303,  0,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #303 = FUNC

    { 302,  2,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  142,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #302 = FNEG_R600

    { 301,  2,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  142,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #301 = FABS_R600

    { 300,  0,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #300 = ENDSWITCH

    { 299,  0,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #299 = ENDMAIN

    { 298,  0,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #298 = ENDLOOP

    { 297,  0,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #297 = ENDIF

    { 296,  0,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #296 = ENDFUNC

    { 295,  0,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #295 = END

    { 294,  0,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #294 = ELSE

    { 293,  0,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #293 = DUMMY_CHAIN

    { 292,  71, 1,  0,  3,  0,  0,  R600ImpOpBase + 0,  149,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL },  // Inst #292 = DOT_4

    { 291,  0,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #291 = DEFAULT

    { 290,  2,  1,  0,  2,  0,  0,  R600ImpOpBase + 0,  147,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #290 = CUBE_r600_pseudo

    { 289,  2,  1,  0,  2,  0,  0,  R600ImpOpBase + 0,  147,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #289 = CUBE_eg_pseudo

    { 288,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  144,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #288 = CONTINUE_LOGICALZ_i32

    { 287,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  144,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #287 = CONTINUE_LOGICALZ_f32

    { 286,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  144,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #286 = CONTINUE_LOGICALNZ_i32

    { 285,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  144,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #285 = CONTINUE_LOGICALNZ_f32

    { 284,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  142,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #284 = CONTINUEC_i32

    { 283,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  142,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #283 = CONTINUEC_f32

    { 282,  0,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #282 = CONTINUE

    { 281,  2,  1,  0,  1,  0,  0,  R600ImpOpBase + 0,  145,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // Inst #281 = CONST_COPY

    { 280,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  144,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #280 = BREAK_LOGICALZ_i32

    { 279,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  144,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #279 = BREAK_LOGICALZ_f32

    { 278,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  144,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #278 = BREAK_LOGICALNZ_i32

    { 277,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  144,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #277 = BREAK_LOGICALNZ_f32

    { 276,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  142,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #276 = BREAKC_i32

    { 275,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  142,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #275 = BREAKC_f32

    { 274,  0,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #274 = BREAK

    { 273,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #273 = BRANCH_COND_i32

    { 272,  2,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #272 = BRANCH_COND_f32

    { 271,  1,  0,  0,  1,  0,  0,  R600ImpOpBase + 0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #271 = BRANCH

    { 270,  4,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  136,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #270 = G_UBFX

    { 269,  4,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  136,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #269 = G_SBFX

    { 268,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #268 = G_VECREDUCE_UMIN

    { 267,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #267 = G_VECREDUCE_UMAX

    { 266,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #266 = G_VECREDUCE_SMIN

    { 265,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #265 = G_VECREDUCE_SMAX

    { 264,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #264 = G_VECREDUCE_XOR

    { 263,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #263 = G_VECREDUCE_OR

    { 262,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #262 = G_VECREDUCE_AND

    { 261,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #261 = G_VECREDUCE_MUL

    { 260,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #260 = G_VECREDUCE_ADD

    { 259,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #259 = G_VECREDUCE_FMINIMUM

    { 258,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #258 = G_VECREDUCE_FMAXIMUM

    { 257,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #257 = G_VECREDUCE_FMIN

    { 256,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #256 = G_VECREDUCE_FMAX

    { 255,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #255 = G_VECREDUCE_FMUL

    { 254,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #254 = G_VECREDUCE_FADD

    { 253,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #253 = G_VECREDUCE_SEQ_FMUL

    { 252,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #252 = G_VECREDUCE_SEQ_FADD

    { 251,  3,  0,  0,  0,  0,  0,  R600ImpOpBase + 0,  53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #251 = G_BZERO

    { 250,  4,  0,  0,  0,  0,  0,  R600ImpOpBase + 0,  132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #250 = G_MEMSET

    { 249,  4,  0,  0,  0,  0,  0,  R600ImpOpBase + 0,  132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #249 = G_MEMMOVE

    { 248,  3,  0,  0,  0,  0,  0,  R600ImpOpBase + 0,  123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #248 = G_MEMCPY_INLINE

    { 247,  4,  0,  0,  0,  0,  0,  R600ImpOpBase + 0,  132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #247 = G_MEMCPY

    { 246,  2,  0,  0,  0,  0,  0,  R600ImpOpBase + 0,  130,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #246 = G_WRITE_REGISTER

    { 245,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #245 = G_READ_REGISTER

    { 244,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #244 = G_STRICT_FLDEXP

    { 243,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #243 = G_STRICT_FSQRT

    { 242,  4,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #242 = G_STRICT_FMA

    { 241,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #241 = G_STRICT_FREM

    { 240,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #240 = G_STRICT_FDIV

    { 239,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #239 = G_STRICT_FMUL

    { 238,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #238 = G_STRICT_FSUB

    { 237,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #237 = G_STRICT_FADD

    { 236,  1,  0,  0,  0,  0,  0,  R600ImpOpBase + 0,  50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #236 = G_STACKRESTORE

    { 235,  1,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #235 = G_STACKSAVE

    { 234,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  64, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #234 = G_DYN_STACKALLOC

    { 233,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #233 = G_JUMP_TABLE

    { 232,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #232 = G_BLOCK_ADDR

    { 231,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #231 = G_ADDRSPACE_CAST

    { 230,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #230 = G_FNEARBYINT

    { 229,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #229 = G_FRINT

    { 228,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #228 = G_FFLOOR

    { 227,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #227 = G_FSQRT

    { 226,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #226 = G_FSIN

    { 225,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #225 = G_FCOS

    { 224,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #224 = G_FCEIL

    { 223,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #223 = G_BITREVERSE

    { 222,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #222 = G_BSWAP

    { 221,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #221 = G_CTPOP

    { 220,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #220 = G_CTLZ_ZERO_UNDEF

    { 219,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #219 = G_CTLZ

    { 218,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #218 = G_CTTZ_ZERO_UNDEF

    { 217,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #217 = G_CTTZ

    { 216,  4,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  126,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #216 = G_SHUFFLE_VECTOR

    { 215,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #215 = G_EXTRACT_VECTOR_ELT

    { 214,  4,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  119,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #214 = G_INSERT_VECTOR_ELT

    { 213,  3,  0,  0,  0,  0,  0,  R600ImpOpBase + 0,  116,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #213 = G_BRJT

    { 212,  1,  0,  0,  0,  0,  0,  R600ImpOpBase + 0,  0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #212 = G_BR

    { 211,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #211 = G_LLROUND

    { 210,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #210 = G_LROUND

    { 209,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #209 = G_ABS

    { 208,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #208 = G_UMAX

    { 207,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #207 = G_UMIN

    { 206,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #206 = G_SMAX

    { 205,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #205 = G_SMIN

    { 204,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #204 = G_PTRMASK

    { 203,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #203 = G_PTR_ADD

    { 202,  0,  0,  0,  0,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #202 = G_RESET_FPMODE

    { 201,  1,  0,  0,  0,  0,  0,  R600ImpOpBase + 0,  50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #201 = G_SET_FPMODE

    { 200,  1,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #200 = G_GET_FPMODE

    { 199,  0,  0,  0,  0,  0,  0,  R600ImpOpBase + 0,  1,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #199 = G_RESET_FPENV

    { 198,  1,  0,  0,  0,  0,  0,  R600ImpOpBase + 0,  50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #198 = G_SET_FPENV

    { 197,  1,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #197 = G_GET_FPENV

    { 196,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #196 = G_FMAXIMUM

    { 195,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #195 = G_FMINIMUM

    { 194,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #194 = G_FMAXNUM_IEEE

    { 193,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #193 = G_FMINNUM_IEEE

    { 192,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #192 = G_FMAXNUM

    { 191,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #191 = G_FMINNUM

    { 190,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #190 = G_FCANONICALIZE

    { 189,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  93, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #189 = G_IS_FPCLASS

    { 188,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #188 = G_FCOPYSIGN

    { 187,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #187 = G_FABS

    { 186,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #186 = G_UITOFP

    { 185,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #185 = G_SITOFP

    { 184,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #184 = G_FPTOUI

    { 183,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #183 = G_FPTOSI

    { 182,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #182 = G_FPTRUNC

    { 181,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #181 = G_FPEXT

    { 180,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #180 = G_FNEG

    { 179,  3,  2,  0,  0,  0,  0,  R600ImpOpBase + 0,  86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #179 = G_FFREXP

    { 178,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #178 = G_FLDEXP

    { 177,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #177 = G_FLOG10

    { 176,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #176 = G_FLOG2

    { 175,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #175 = G_FLOG

    { 174,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #174 = G_FEXP10

    { 173,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #173 = G_FEXP2

    { 172,  2,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #172 = G_FEXP

    { 171,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #171 = G_FPOWI

    { 170,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #170 = G_FPOW

    { 169,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #169 = G_FREM

    { 168,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #168 = G_FDIV

    { 167,  4,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #167 = G_FMAD

    { 166,  4,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #166 = G_FMA

    { 165,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #165 = G_FMUL

    { 164,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #164 = G_FSUB

    { 163,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #163 = G_FADD

    { 162,  4,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #162 = G_UDIVFIXSAT

    { 161,  4,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #161 = G_SDIVFIXSAT

    { 160,  4,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #160 = G_UDIVFIX

    { 159,  4,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #159 = G_SDIVFIX

    { 158,  4,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #158 = G_UMULFIXSAT

    { 157,  4,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #157 = G_SMULFIXSAT

    { 156,  4,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #156 = G_UMULFIX

    { 155,  4,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #155 = G_SMULFIX

    { 154,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #154 = G_SSHLSAT

    { 153,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #153 = G_USHLSAT

    { 152,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #152 = G_SSUBSAT

    { 151,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #151 = G_USUBSAT

    { 150,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #150 = G_SADDSAT

    { 149,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #149 = G_UADDSAT

    { 148,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #148 = G_SMULH

    { 147,  3,  1,  0,  0,  0,  0,  R600ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #147 = G_UMULH

    { 146,  4,  2,  0,  0,  0,  0,  R600ImpOpBase + 0,  82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #146 = G_SMULO