/src/build/lib/Target/AMDGPU/R600GenMCCodeEmitter.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Machine Code Emitter *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | uint64_t R600MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, |
10 | | SmallVectorImpl<MCFixup> &Fixups, |
11 | 0 | const MCSubtargetInfo &STI) const { |
12 | 0 | static const uint64_t InstBits[] = { |
13 | 0 | UINT64_C(0), |
14 | 0 | UINT64_C(0), |
15 | 0 | UINT64_C(0), |
16 | 0 | UINT64_C(0), |
17 | 0 | UINT64_C(0), |
18 | 0 | UINT64_C(0), |
19 | 0 | UINT64_C(0), |
20 | 0 | UINT64_C(0), |
21 | 0 | UINT64_C(0), |
22 | 0 | UINT64_C(0), |
23 | 0 | UINT64_C(0), |
24 | 0 | UINT64_C(0), |
25 | 0 | UINT64_C(0), |
26 | 0 | UINT64_C(0), |
27 | 0 | UINT64_C(0), |
28 | 0 | UINT64_C(0), |
29 | 0 | UINT64_C(0), |
30 | 0 | UINT64_C(0), |
31 | 0 | UINT64_C(0), |
32 | 0 | UINT64_C(0), |
33 | 0 | UINT64_C(0), |
34 | 0 | UINT64_C(0), |
35 | 0 | UINT64_C(0), |
36 | 0 | UINT64_C(0), |
37 | 0 | UINT64_C(0), |
38 | 0 | UINT64_C(0), |
39 | 0 | UINT64_C(0), |
40 | 0 | UINT64_C(0), |
41 | 0 | UINT64_C(0), |
42 | 0 | UINT64_C(0), |
43 | 0 | UINT64_C(0), |
44 | 0 | UINT64_C(0), |
45 | 0 | UINT64_C(0), |
46 | 0 | UINT64_C(0), |
47 | 0 | UINT64_C(0), |
48 | 0 | UINT64_C(0), |
49 | 0 | UINT64_C(0), |
50 | 0 | UINT64_C(0), |
51 | 0 | UINT64_C(0), |
52 | 0 | UINT64_C(0), |
53 | 0 | UINT64_C(0), |
54 | 0 | UINT64_C(0), |
55 | 0 | UINT64_C(0), |
56 | 0 | UINT64_C(0), |
57 | 0 | UINT64_C(0), |
58 | 0 | UINT64_C(0), |
59 | 0 | UINT64_C(0), |
60 | 0 | UINT64_C(0), |
61 | 0 | UINT64_C(0), |
62 | 0 | UINT64_C(0), |
63 | 0 | UINT64_C(0), |
64 | 0 | UINT64_C(0), |
65 | 0 | UINT64_C(0), |
66 | 0 | UINT64_C(0), |
67 | 0 | UINT64_C(0), |
68 | 0 | UINT64_C(0), |
69 | 0 | UINT64_C(0), |
70 | 0 | UINT64_C(0), |
71 | 0 | UINT64_C(0), |
72 | 0 | UINT64_C(0), |
73 | 0 | UINT64_C(0), |
74 | 0 | UINT64_C(0), |
75 | 0 | UINT64_C(0), |
76 | 0 | UINT64_C(0), |
77 | 0 | UINT64_C(0), |
78 | 0 | UINT64_C(0), |
79 | 0 | UINT64_C(0), |
80 | 0 | UINT64_C(0), |
81 | 0 | UINT64_C(0), |
82 | 0 | UINT64_C(0), |
83 | 0 | UINT64_C(0), |
84 | 0 | UINT64_C(0), |
85 | 0 | UINT64_C(0), |
86 | 0 | UINT64_C(0), |
87 | 0 | UINT64_C(0), |
88 | 0 | UINT64_C(0), |
89 | 0 | UINT64_C(0), |
90 | 0 | UINT64_C(0), |
91 | 0 | UINT64_C(0), |
92 | 0 | UINT64_C(0), |
93 | 0 | UINT64_C(0), |
94 | 0 | UINT64_C(0), |
95 | 0 | UINT64_C(0), |
96 | 0 | UINT64_C(0), |
97 | 0 | UINT64_C(0), |
98 | 0 | UINT64_C(0), |
99 | 0 | UINT64_C(0), |
100 | 0 | UINT64_C(0), |
101 | 0 | UINT64_C(0), |
102 | 0 | UINT64_C(0), |
103 | 0 | UINT64_C(0), |
104 | 0 | UINT64_C(0), |
105 | 0 | UINT64_C(0), |
106 | 0 | UINT64_C(0), |
107 | 0 | UINT64_C(0), |
108 | 0 | UINT64_C(0), |
109 | 0 | UINT64_C(0), |
110 | 0 | UINT64_C(0), |
111 | 0 | UINT64_C(0), |
112 | 0 | UINT64_C(0), |
113 | 0 | UINT64_C(0), |
114 | 0 | UINT64_C(0), |
115 | 0 | UINT64_C(0), |
116 | 0 | UINT64_C(0), |
117 | 0 | UINT64_C(0), |
118 | 0 | UINT64_C(0), |
119 | 0 | UINT64_C(0), |
120 | 0 | UINT64_C(0), |
121 | 0 | UINT64_C(0), |
122 | 0 | UINT64_C(0), |
123 | 0 | UINT64_C(0), |
124 | 0 | UINT64_C(0), |
125 | 0 | UINT64_C(0), |
126 | 0 | UINT64_C(0), |
127 | 0 | UINT64_C(0), |
128 | 0 | UINT64_C(0), |
129 | 0 | UINT64_C(0), |
130 | 0 | UINT64_C(0), |
131 | 0 | UINT64_C(0), |
132 | 0 | UINT64_C(0), |
133 | 0 | UINT64_C(0), |
134 | 0 | UINT64_C(0), |
135 | 0 | UINT64_C(0), |
136 | 0 | UINT64_C(0), |
137 | 0 | UINT64_C(0), |
138 | 0 | UINT64_C(0), |
139 | 0 | UINT64_C(0), |
140 | 0 | UINT64_C(0), |
141 | 0 | UINT64_C(0), |
142 | 0 | UINT64_C(0), |
143 | 0 | UINT64_C(0), |
144 | 0 | UINT64_C(0), |
145 | 0 | UINT64_C(0), |
146 | 0 | UINT64_C(0), |
147 | 0 | UINT64_C(0), |
148 | 0 | UINT64_C(0), |
149 | 0 | UINT64_C(0), |
150 | 0 | UINT64_C(0), |
151 | 0 | UINT64_C(0), |
152 | 0 | UINT64_C(0), |
153 | 0 | UINT64_C(0), |
154 | 0 | UINT64_C(0), |
155 | 0 | UINT64_C(0), |
156 | 0 | UINT64_C(0), |
157 | 0 | UINT64_C(0), |
158 | 0 | UINT64_C(0), |
159 | 0 | UINT64_C(0), |
160 | 0 | UINT64_C(0), |
161 | 0 | UINT64_C(0), |
162 | 0 | UINT64_C(0), |
163 | 0 | UINT64_C(0), |
164 | 0 | UINT64_C(0), |
165 | 0 | UINT64_C(0), |
166 | 0 | UINT64_C(0), |
167 | 0 | UINT64_C(0), |
168 | 0 | UINT64_C(0), |
169 | 0 | UINT64_C(0), |
170 | 0 | UINT64_C(0), |
171 | 0 | UINT64_C(0), |
172 | 0 | UINT64_C(0), |
173 | 0 | UINT64_C(0), |
174 | 0 | UINT64_C(0), |
175 | 0 | UINT64_C(0), |
176 | 0 | UINT64_C(0), |
177 | 0 | UINT64_C(0), |
178 | 0 | UINT64_C(0), |
179 | 0 | UINT64_C(0), |
180 | 0 | UINT64_C(0), |
181 | 0 | UINT64_C(0), |
182 | 0 | UINT64_C(0), |
183 | 0 | UINT64_C(0), |
184 | 0 | UINT64_C(0), |
185 | 0 | UINT64_C(0), |
186 | 0 | UINT64_C(0), |
187 | 0 | UINT64_C(0), |
188 | 0 | UINT64_C(0), |
189 | 0 | UINT64_C(0), |
190 | 0 | UINT64_C(0), |
191 | 0 | UINT64_C(0), |
192 | 0 | UINT64_C(0), |
193 | 0 | UINT64_C(0), |
194 | 0 | UINT64_C(0), |
195 | 0 | UINT64_C(0), |
196 | 0 | UINT64_C(0), |
197 | 0 | UINT64_C(0), |
198 | 0 | UINT64_C(0), |
199 | 0 | UINT64_C(0), |
200 | 0 | UINT64_C(0), |
201 | 0 | UINT64_C(0), |
202 | 0 | UINT64_C(0), |
203 | 0 | UINT64_C(0), |
204 | 0 | UINT64_C(0), |
205 | 0 | UINT64_C(0), |
206 | 0 | UINT64_C(0), |
207 | 0 | UINT64_C(0), |
208 | 0 | UINT64_C(0), |
209 | 0 | UINT64_C(0), |
210 | 0 | UINT64_C(0), |
211 | 0 | UINT64_C(0), |
212 | 0 | UINT64_C(0), |
213 | 0 | UINT64_C(0), |
214 | 0 | UINT64_C(0), |
215 | 0 | UINT64_C(0), |
216 | 0 | UINT64_C(0), |
217 | 0 | UINT64_C(0), |
218 | 0 | UINT64_C(0), |
219 | 0 | UINT64_C(0), |
220 | 0 | UINT64_C(0), |
221 | 0 | UINT64_C(0), |
222 | 0 | UINT64_C(0), |
223 | 0 | UINT64_C(0), |
224 | 0 | UINT64_C(0), |
225 | 0 | UINT64_C(0), |
226 | 0 | UINT64_C(0), |
227 | 0 | UINT64_C(0), |
228 | 0 | UINT64_C(0), |
229 | 0 | UINT64_C(0), |
230 | 0 | UINT64_C(0), |
231 | 0 | UINT64_C(0), |
232 | 0 | UINT64_C(0), |
233 | 0 | UINT64_C(0), |
234 | 0 | UINT64_C(0), |
235 | 0 | UINT64_C(0), |
236 | 0 | UINT64_C(0), |
237 | 0 | UINT64_C(0), |
238 | 0 | UINT64_C(0), |
239 | 0 | UINT64_C(0), |
240 | 0 | UINT64_C(0), |
241 | 0 | UINT64_C(0), |
242 | 0 | UINT64_C(0), |
243 | 0 | UINT64_C(0), |
244 | 0 | UINT64_C(0), |
245 | 0 | UINT64_C(0), |
246 | 0 | UINT64_C(0), |
247 | 0 | UINT64_C(0), |
248 | 0 | UINT64_C(0), |
249 | 0 | UINT64_C(0), |
250 | 0 | UINT64_C(0), |
251 | 0 | UINT64_C(0), |
252 | 0 | UINT64_C(0), |
253 | 0 | UINT64_C(0), |
254 | 0 | UINT64_C(0), |
255 | 0 | UINT64_C(0), |
256 | 0 | UINT64_C(0), |
257 | 0 | UINT64_C(0), |
258 | 0 | UINT64_C(0), |
259 | 0 | UINT64_C(0), |
260 | 0 | UINT64_C(0), |
261 | 0 | UINT64_C(0), |
262 | 0 | UINT64_C(0), |
263 | 0 | UINT64_C(0), |
264 | 0 | UINT64_C(0), |
265 | 0 | UINT64_C(0), |
266 | 0 | UINT64_C(0), |
267 | 0 | UINT64_C(0), |
268 | 0 | UINT64_C(0), |
269 | 0 | UINT64_C(0), |
270 | 0 | UINT64_C(0), |
271 | 0 | UINT64_C(0), |
272 | 0 | UINT64_C(0), |
273 | 0 | UINT64_C(0), |
274 | 0 | UINT64_C(0), |
275 | 0 | UINT64_C(0), |
276 | 0 | UINT64_C(0), |
277 | 0 | UINT64_C(0), |
278 | 0 | UINT64_C(0), |
279 | 0 | UINT64_C(0), |
280 | 0 | UINT64_C(0), |
281 | 0 | UINT64_C(0), |
282 | 0 | UINT64_C(0), |
283 | 0 | UINT64_C(0), |
284 | 0 | UINT64_C(0), |
285 | 0 | UINT64_C(0), |
286 | 0 | UINT64_C(0), |
287 | 0 | UINT64_C(0), |
288 | 0 | UINT64_C(0), |
289 | 0 | UINT64_C(0), |
290 | 0 | UINT64_C(0), |
291 | 0 | UINT64_C(0), |
292 | 0 | UINT64_C(0), |
293 | 0 | UINT64_C(0), |
294 | 0 | UINT64_C(0), |
295 | 0 | UINT64_C(0), |
296 | 0 | UINT64_C(0), |
297 | 0 | UINT64_C(0), |
298 | 0 | UINT64_C(0), |
299 | 0 | UINT64_C(0), |
300 | 0 | UINT64_C(0), |
301 | 0 | UINT64_C(0), |
302 | 0 | UINT64_C(0), |
303 | 0 | UINT64_C(0), |
304 | 0 | UINT64_C(0), |
305 | 0 | UINT64_C(0), |
306 | 0 | UINT64_C(0), |
307 | 0 | UINT64_C(0), |
308 | 0 | UINT64_C(0), |
309 | 0 | UINT64_C(0), |
310 | 0 | UINT64_C(0), |
311 | 0 | UINT64_C(0), |
312 | 0 | UINT64_C(0), |
313 | 0 | UINT64_C(0), |
314 | 0 | UINT64_C(0), |
315 | 0 | UINT64_C(0), |
316 | 0 | UINT64_C(0), |
317 | 0 | UINT64_C(0), |
318 | 0 | UINT64_C(0), |
319 | 0 | UINT64_C(0), |
320 | 0 | UINT64_C(0), |
321 | 0 | UINT64_C(0), |
322 | 0 | UINT64_C(0), |
323 | 0 | UINT64_C(0), |
324 | 0 | UINT64_C(0), |
325 | 0 | UINT64_C(0), |
326 | 0 | UINT64_C(0), |
327 | 0 | UINT64_C(0), |
328 | 0 | UINT64_C(0), |
329 | 0 | UINT64_C(0), |
330 | 0 | UINT64_C(0), |
331 | 0 | UINT64_C(0), |
332 | 0 | UINT64_C(0), |
333 | 0 | UINT64_C(0), |
334 | 0 | UINT64_C(0), |
335 | 0 | UINT64_C(0), |
336 | 0 | UINT64_C(0), |
337 | 0 | UINT64_C(0), |
338 | 0 | UINT64_C(0), |
339 | 0 | UINT64_C(0), |
340 | 0 | UINT64_C(0), |
341 | 0 | UINT64_C(0), |
342 | 0 | UINT64_C(0), // ADD |
343 | 0 | UINT64_C(45079976738816), // ADDC_UINT |
344 | 0 | UINT64_C(28587302322176), // ADD_INT |
345 | 0 | UINT64_C(0), // ALU_CLAUSE |
346 | 0 | UINT64_C(26388279066624), // AND_INT |
347 | 0 | UINT64_C(11544872091648), // ASHR_eg |
348 | 0 | UINT64_C(61572651155456), // ASHR_r600 |
349 | 0 | UINT64_C(93458488360960), // BCNT_INT |
350 | 0 | UINT64_C(175921860444160), // BFE_INT_eg |
351 | 0 | UINT64_C(140737488355328), // BFE_UINT_eg |
352 | 0 | UINT64_C(211106232532992), // BFI_INT_eg |
353 | 0 | UINT64_C(87960930222080), // BFM_INT_eg |
354 | 0 | UINT64_C(422212465065984), // BIT_ALIGN_INT_eg |
355 | 0 | UINT64_C(9895604649984), // CEIL |
356 | 0 | UINT64_C(11529215046068469760), // CF_ALU |
357 | 0 | UINT64_C(13258597302978740224), // CF_ALU_BREAK |
358 | 0 | UINT64_C(12970366926827028480), // CF_ALU_CONTINUE |
359 | 0 | UINT64_C(13546827679130451968), // CF_ALU_ELSE_AFTER |
360 | 0 | UINT64_C(12105675798371893248), // CF_ALU_POP_AFTER |
361 | 0 | UINT64_C(11817445422220181504), // CF_ALU_PUSH_BEFORE |
362 | 0 | UINT64_C(9565645608534933504), // CF_CALL_FS_EG |
363 | 0 | UINT64_C(9907919180215091200), // CF_CALL_FS_R600 |
364 | 0 | UINT64_C(9367487224930631680), // CF_CONTINUE_EG |
365 | 0 | UINT64_C(9511602413006487552), // CF_CONTINUE_R600 |
366 | 0 | UINT64_C(9457559217478041600), // CF_ELSE_EG |
367 | 0 | UINT64_C(9691746398101307392), // CF_ELSE_R600 |
368 | 0 | UINT64_C(9799832789158199296), // CF_END_CM |
369 | 0 | UINT64_C(9232379236109516800), // CF_END_EG |
370 | 0 | UINT64_C(9232379236109516800), // CF_END_R600 |
371 | 0 | UINT64_C(9403516021949595648), // CF_JUMP_EG |
372 | 0 | UINT64_C(9583660007044415488), // CF_JUMP_R600 |
373 | 0 | UINT64_C(9421530420459077632), // CF_PUSH_EG |
374 | 0 | UINT64_C(9655717601082343424), // CF_PUSH_ELSE_R600 |
375 | 0 | UINT64_C(9241386435364257792), // CF_TC_EG |
376 | 0 | UINT64_C(9259400833873739776), // CF_TC_R600 |
377 | 0 | UINT64_C(9259400833873739776), // CF_VC_EG |
378 | 0 | UINT64_C(9295429630892703744), // CF_VC_R600 |
379 | 0 | UINT64_C(985162418487296), // CNDE_INT |
380 | 0 | UINT64_C(879609302220800), // CNDE_eg |
381 | 0 | UINT64_C(844424930131968), // CNDE_r600 |
382 | 0 | UINT64_C(1055531162664960), // CNDGE_INT |
383 | 0 | UINT64_C(949978046398464), // CNDGE_eg |
384 | 0 | UINT64_C(914793674309632), // CNDGE_r600 |
385 | 0 | UINT64_C(1020346790576128), // CNDGT_INT |
386 | 0 | UINT64_C(914793674309632), // CNDGT_eg |
387 | 0 | UINT64_C(879609302220800), // CNDGT_r600 |
388 | 0 | UINT64_C(78065325572096), // COS_cm |
389 | 0 | UINT64_C(78065325572096), // COS_eg |
390 | 0 | UINT64_C(61022895341568), // COS_r600 |
391 | 0 | UINT64_C(61022895341568), // COS_r700 |
392 | 0 | UINT64_C(105553116266496), // CUBE_eg_real |
393 | 0 | UINT64_C(45079976738816), // CUBE_r600_real |
394 | 0 | UINT64_C(104453604638720), // DOT4_eg |
395 | 0 | UINT64_C(43980465111040), // DOT4_r600 |
396 | 0 | UINT64_C(9223372036854775808), // EG_ExportBuf |
397 | 0 | UINT64_C(9223372040076001280), // EG_ExportSwz |
398 | 0 | UINT64_C(9313444029402185728), // END_LOOP_EG |
399 | 0 | UINT64_C(9403516021949595648), // END_LOOP_R600 |
400 | 0 | UINT64_C(70918499991552), // EXP_IEEE_cm |
401 | 0 | UINT64_C(70918499991552), // EXP_IEEE_eg |
402 | 0 | UINT64_C(53326313947136), // EXP_IEEE_r600 |
403 | 0 | UINT64_C(0), // FETCH_CLAUSE |
404 | 0 | UINT64_C(94008244174848), // FFBH_UINT |
405 | 0 | UINT64_C(94557999988736), // FFBL_INT |
406 | 0 | UINT64_C(10995116277760), // FLOOR |
407 | 0 | UINT64_C(89610197663744), // FLT16_TO_FLT32 |
408 | 0 | UINT64_C(89060441849856), // FLT32_TO_FLT16 |
409 | 0 | UINT64_C(43980465111040), // FLT_TO_INT_eg |
410 | 0 | UINT64_C(58823872086016), // FLT_TO_INT_r600 |
411 | 0 | UINT64_C(84662395338752), // FLT_TO_UINT_eg |
412 | 0 | UINT64_C(66520453480448), // FLT_TO_UINT_r600 |
413 | 0 | UINT64_C(246290604621824), // FMA_eg |
414 | 0 | UINT64_C(8796093022208), // FRACT |
415 | 0 | UINT64_C(46181635850240), // GROUP_BARRIER |
416 | 0 | UINT64_C(123145302310912), // INTERP_LOAD_P0 |
417 | 0 | UINT64_C(4294967295), // INTERP_PAIR_XY |
418 | 0 | UINT64_C(4294967295), // INTERP_PAIR_ZW |
419 | 0 | UINT64_C(4294967295), // INTERP_VEC_LOAD |
420 | 0 | UINT64_C(5747147278385152), // INTERP_XY |
421 | 0 | UINT64_C(5747697034199040), // INTERP_ZW |
422 | 0 | UINT64_C(85212151152640), // INT_TO_FLT_eg |
423 | 0 | UINT64_C(59373627899904), // INT_TO_FLT_r600 |
424 | 0 | UINT64_C(24739011624960), // KILLGT |
425 | 0 | UINT64_C(598134325510144), // LDS_ADD |
426 | 0 | UINT64_C(288828510477221888), // LDS_ADD_RET |
427 | 0 | UINT64_C(81662927618179072), // LDS_AND |
428 | 0 | UINT64_C(369893303769890816), // LDS_AND_RET |
429 | 0 | UINT64_C(486986894081523712), // LDS_BYTE_READ_RET |
430 | 0 | UINT64_C(162727720910848000), // LDS_BYTE_WRITE |
431 | 0 | UINT64_C(144713322401366016), // LDS_CMPST |
432 | 0 | UINT64_C(432943698553077760), // LDS_CMPST_RET |
433 | 0 | UINT64_C(54641329853956096), // LDS_MAX_INT |
434 | 0 | UINT64_C(342871706005667840), // LDS_MAX_INT_RET |
435 | 0 | UINT64_C(72655728363438080), // LDS_MAX_UINT |
436 | 0 | UINT64_C(360886104515149824), // LDS_MAX_UINT_RET |
437 | 0 | UINT64_C(45634130599215104), // LDS_MIN_INT |
438 | 0 | UINT64_C(333864506750926848), // LDS_MIN_INT_RET |
439 | 0 | UINT64_C(63648529108697088), // LDS_MIN_UINT |
440 | 0 | UINT64_C(351878905260408832), // LDS_MIN_UINT_RET |
441 | 0 | UINT64_C(90670126872920064), // LDS_OR |
442 | 0 | UINT64_C(378900503024631808), // LDS_OR_RET |
443 | 0 | UINT64_C(450958097062559744), // LDS_READ_RET |
444 | 0 | UINT64_C(505001292591005696), // LDS_SHORT_READ_RET |
445 | 0 | UINT64_C(171734920165588992), // LDS_SHORT_WRITE |
446 | 0 | UINT64_C(9605333580251136), // LDS_SUB |
447 | 0 | UINT64_C(297835709731962880), // LDS_SUB_RET |
448 | 0 | UINT64_C(495994093336264704), // LDS_UBYTE_READ_RET |
449 | 0 | UINT64_C(514008491845746688), // LDS_USHORT_READ_RET |
450 | 0 | UINT64_C(117691724637143040), // LDS_WRITE |
451 | 0 | UINT64_C(117691724637143040), // LDS_WRXCHG |
452 | 0 | UINT64_C(405922100788854784), // LDS_WRXCHG_RET |
453 | 0 | UINT64_C(99677326127661056), // LDS_XOR |
454 | 0 | UINT64_C(387907702279372800), // LDS_XOR_RET |
455 | 0 | UINT64_C(0), // LITERALS |
456 | 0 | UINT64_C(71468255805440), // LOG_CLAMPED_eg |
457 | 0 | UINT64_C(53876069761024), // LOG_CLAMPED_r600 |
458 | 0 | UINT64_C(72018011619328), // LOG_IEEE_cm |
459 | 0 | UINT64_C(72018011619328), // LOG_IEEE_eg |
460 | 0 | UINT64_C(54425825574912), // LOG_IEEE_r600 |
461 | 0 | UINT64_C(9385501623440113664), // LOOP_BREAK_EG |
462 | 0 | UINT64_C(9547631210025451520), // LOOP_BREAK_R600 |
463 | 0 | UINT64_C(12644383719424), // LSHL_eg |
464 | 0 | UINT64_C(62672162783232), // LSHL_r600 |
465 | 0 | UINT64_C(12094627905536), // LSHR_eg |
466 | 0 | UINT64_C(62122406969344), // LSHR_r600 |
467 | 0 | UINT64_C(1649267441664), // MAX |
468 | 0 | UINT64_C(2748779069440), // MAX_DX10 |
469 | 0 | UINT64_C(29686813949952), // MAX_INT |
470 | 0 | UINT64_C(30786325577728), // MAX_UINT |
471 | 0 | UINT64_C(2199023255552), // MIN |
472 | 0 | UINT64_C(3298534883328), // MIN_DX10 |
473 | 0 | UINT64_C(30236569763840), // MIN_INT |
474 | 0 | UINT64_C(31336081391616), // MIN_UINT |
475 | 0 | UINT64_C(13743895347200), // MOV |
476 | 0 | UINT64_C(112150186033152), // MOVA_INT_eg |
477 | 0 | UINT64_C(549755813888), // MUL |
478 | 0 | UINT64_C(844424930131968), // MULADD_IEEE_eg |
479 | 0 | UINT64_C(703687441776640), // MULADD_IEEE_r600 |
480 | 0 | UINT64_C(281474976710656), // MULADD_INT24_cm |
481 | 0 | UINT64_C(562949953421312), // MULADD_UINT24_eg |
482 | 0 | UINT64_C(703687441776640), // MULADD_eg |
483 | 0 | UINT64_C(562949953421312), // MULADD_r600 |
484 | 0 | UINT64_C(79164837199872), // MULHI_INT_cm |
485 | 0 | UINT64_C(50577534877696), // MULHI_INT_cm24 |
486 | 0 | UINT64_C(79164837199872), // MULHI_INT_eg |
487 | 0 | UINT64_C(63771674411008), // MULHI_INT_r600 |
488 | 0 | UINT64_C(97856534872064), // MULHI_UINT24_eg |
489 | 0 | UINT64_C(80264348827648), // MULHI_UINT_cm |
490 | 0 | UINT64_C(97856534872064), // MULHI_UINT_cm24 |
491 | 0 | UINT64_C(80264348827648), // MULHI_UINT_eg |
492 | 0 | UINT64_C(64871186038784), // MULHI_UINT_r600 |
493 | 0 | UINT64_C(78615081385984), // MULLO_INT_cm |
494 | 0 | UINT64_C(78615081385984), // MULLO_INT_eg |
495 | 0 | UINT64_C(63221918597120), // MULLO_INT_r600 |
496 | 0 | UINT64_C(79714593013760), // MULLO_UINT_cm |
497 | 0 | UINT64_C(79714593013760), // MULLO_UINT_eg |
498 | 0 | UINT64_C(64321430224896), // MULLO_UINT_r600 |
499 | 0 | UINT64_C(1099511627776), // MUL_IEEE |
500 | 0 | UINT64_C(50027779063808), // MUL_INT24_cm |
501 | 0 | UINT64_C(1090715534753792), // MUL_LIT_eg |
502 | 0 | UINT64_C(422212465065984), // MUL_LIT_r600 |
503 | 0 | UINT64_C(99505802313728), // MUL_UINT24_eg |
504 | 0 | UINT64_C(28037546508288), // NOT_INT |
505 | 0 | UINT64_C(26938034880512), // OR_INT |
506 | 0 | UINT64_C(0), // PAD |
507 | 0 | UINT64_C(9475573615987523584), // POP_EG |
508 | 0 | UINT64_C(9727775195120271360), // POP_R600 |
509 | 0 | UINT64_C(17592186044416), // PRED_SETE |
510 | 0 | UINT64_C(36283883716608), // PRED_SETE_INT |
511 | 0 | UINT64_C(18691697672192), // PRED_SETGE |
512 | 0 | UINT64_C(37383395344384), // PRED_SETGE_INT |
513 | 0 | UINT64_C(18141941858304), // PRED_SETGT |
514 | 0 | UINT64_C(36833639530496), // PRED_SETGT_INT |
515 | 0 | UINT64_C(19241453486080), // PRED_SETNE |
516 | 0 | UINT64_C(37933151158272), // PRED_SETNE_INT |
517 | 0 | UINT64_C(9223372036854775808), // R600_ExportBuf |
518 | 0 | UINT64_C(9223372040076001280), // R600_ExportSwz |
519 | 0 | UINT64_C(10772874191460901488), // RAT_ATOMIC_ADD_NORET |
520 | 0 | UINT64_C(10772874191460900976), // RAT_ATOMIC_ADD_RTN |
521 | 0 | UINT64_C(10772874191460901600), // RAT_ATOMIC_AND_NORET |
522 | 0 | UINT64_C(10772874191460901088), // RAT_ATOMIC_AND_RTN |
523 | 0 | UINT64_C(10772874191460901440), // RAT_ATOMIC_CMPXCHG_INT_NORET |
524 | 0 | UINT64_C(10772874191460900928), // RAT_ATOMIC_CMPXCHG_INT_RTN |
525 | 0 | UINT64_C(10772874191460901680), // RAT_ATOMIC_DEC_UINT_NORET |
526 | 0 | UINT64_C(10772874191460901168), // RAT_ATOMIC_DEC_UINT_RTN |
527 | 0 | UINT64_C(10772874191460901664), // RAT_ATOMIC_INC_UINT_NORET |
528 | 0 | UINT64_C(10772874191460901152), // RAT_ATOMIC_INC_UINT_RTN |
529 | 0 | UINT64_C(10772874191460901568), // RAT_ATOMIC_MAX_INT_NORET |
530 | 0 | UINT64_C(10772874191460901056), // RAT_ATOMIC_MAX_INT_RTN |
531 | 0 | UINT64_C(10772874191460901584), // RAT_ATOMIC_MAX_UINT_NORET |
532 | 0 | UINT64_C(10772874191460901072), // RAT_ATOMIC_MAX_UINT_RTN |
533 | 0 | UINT64_C(10772874191460901536), // RAT_ATOMIC_MIN_INT_NORET |
534 | 0 | UINT64_C(10772874191460901024), // RAT_ATOMIC_MIN_INT_RTN |
535 | 0 | UINT64_C(10772874191460901552), // RAT_ATOMIC_MIN_UINT_NORET |
536 | 0 | UINT64_C(10772874191460901040), // RAT_ATOMIC_MIN_UINT_RTN |
537 | 0 | UINT64_C(10772874191460901616), // RAT_ATOMIC_OR_NORET |
538 | 0 | UINT64_C(10772874191460901104), // RAT_ATOMIC_OR_RTN |
539 | 0 | UINT64_C(10772874191460901520), // RAT_ATOMIC_RSUB_NORET |
540 | 0 | UINT64_C(10772874191460901008), // RAT_ATOMIC_RSUB_RTN |
541 | 0 | UINT64_C(10772874191460901504), // RAT_ATOMIC_SUB_NORET |
542 | 0 | UINT64_C(10772874191460900992), // RAT_ATOMIC_SUB_RTN |
543 | 0 | UINT64_C(10772874191460901408), // RAT_ATOMIC_XCHG_INT_NORET |
544 | 0 | UINT64_C(10772874191460900880), // RAT_ATOMIC_XCHG_INT_RTN |
545 | 0 | UINT64_C(10772874191460901632), // RAT_ATOMIC_XOR_NORET |
546 | 0 | UINT64_C(10772874191460901120), // RAT_ATOMIC_XOR_RTN |
547 | 0 | UINT64_C(10772874191460901136), // RAT_MSKOR |
548 | 0 | UINT64_C(10790888589970383168), // RAT_STORE_DWORD128 |
549 | 0 | UINT64_C(10790642299365761344), // RAT_STORE_DWORD32 |
550 | 0 | UINT64_C(10790677483737850176), // RAT_STORE_DWORD64 |
551 | 0 | UINT64_C(10772874191460900880), // RAT_STORE_TYPED_cm |
552 | 0 | UINT64_C(10772874191460900880), // RAT_STORE_TYPED_eg |
553 | 0 | UINT64_C(10790888589970382880), // RAT_WRITE_CACHELESS_128_eg |
554 | 0 | UINT64_C(10790642299365761056), // RAT_WRITE_CACHELESS_32_eg |
555 | 0 | UINT64_C(10790677483737849888), // RAT_WRITE_CACHELESS_64_eg |
556 | 0 | UINT64_C(74217034874880), // RECIPSQRT_CLAMPED_cm |
557 | 0 | UINT64_C(74217034874880), // RECIPSQRT_CLAMPED_eg |
558 | 0 | UINT64_C(56624848830464), // RECIPSQRT_CLAMPED_r600 |
559 | 0 | UINT64_C(75316546502656), // RECIPSQRT_IEEE_cm |
560 | 0 | UINT64_C(75316546502656), // RECIPSQRT_IEEE_eg |
561 | 0 | UINT64_C(57724360458240), // RECIPSQRT_IEEE_r600 |
562 | 0 | UINT64_C(72567767433216), // RECIP_CLAMPED_cm |
563 | 0 | UINT64_C(72567767433216), // RECIP_CLAMPED_eg |
564 | 0 | UINT64_C(54975581388800), // RECIP_CLAMPED_r600 |
565 | 0 | UINT64_C(73667279060992), // RECIP_IEEE_cm |
566 | 0 | UINT64_C(73667279060992), // RECIP_IEEE_eg |
567 | 0 | UINT64_C(56075093016576), // RECIP_IEEE_r600 |
568 | 0 | UINT64_C(81363860455424), // RECIP_UINT_eg |
569 | 0 | UINT64_C(65970697666560), // RECIP_UINT_r600 |
570 | 0 | UINT64_C(10445360463872), // RNDNE |
571 | 0 | UINT64_C(4398046511104), // SETE |
572 | 0 | UINT64_C(6597069766656), // SETE_DX10 |
573 | 0 | UINT64_C(31885837205504), // SETE_INT |
574 | 0 | UINT64_C(7696581394432), // SETGE_DX10 |
575 | 0 | UINT64_C(32985348833280), // SETGE_INT |
576 | 0 | UINT64_C(34634616274944), // SETGE_UINT |
577 | 0 | UINT64_C(7146825580544), // SETGT_DX10 |
578 | 0 | UINT64_C(32435593019392), // SETGT_INT |
579 | 0 | UINT64_C(34084860461056), // SETGT_UINT |
580 | 0 | UINT64_C(8246337208320), // SETNE_DX10 |
581 | 0 | UINT64_C(33535104647168), // SETNE_INT |
582 | 0 | UINT64_C(5497558138880), // SGE |
583 | 0 | UINT64_C(4947802324992), // SGT |
584 | 0 | UINT64_C(77515569758208), // SIN_cm |
585 | 0 | UINT64_C(77515569758208), // SIN_eg |
586 | 0 | UINT64_C(60473139527680), // SIN_r600 |
587 | 0 | UINT64_C(60473139527680), // SIN_r700 |
588 | 0 | UINT64_C(6047313952768), // SNE |
589 | 0 | UINT64_C(45629732552704), // SUBB_UINT |
590 | 0 | UINT64_C(29137058136064), // SUB_INT |
591 | 0 | UINT64_C(7), // TEX_GET_GRADIENTS_H |
592 | 0 | UINT64_C(8), // TEX_GET_GRADIENTS_V |
593 | 0 | UINT64_C(4), // TEX_GET_TEXTURE_RESINFO |
594 | 0 | UINT64_C(3), // TEX_LD |
595 | 0 | UINT64_C(35), // TEX_LDPTR |
596 | 0 | UINT64_C(16), // TEX_SAMPLE |
597 | 0 | UINT64_C(24), // TEX_SAMPLE_C |
598 | 0 | UINT64_C(28), // TEX_SAMPLE_C_G |
599 | 0 | UINT64_C(25), // TEX_SAMPLE_C_L |
600 | 0 | UINT64_C(26), // TEX_SAMPLE_C_LB |
601 | 0 | UINT64_C(20), // TEX_SAMPLE_G |
602 | 0 | UINT64_C(17), // TEX_SAMPLE_L |
603 | 0 | UINT64_C(18), // TEX_SAMPLE_LB |
604 | 0 | UINT64_C(11), // TEX_SET_GRADIENTS_H |
605 | 0 | UINT64_C(12), // TEX_SET_GRADIENTS_V |
606 | 0 | UINT64_C(16775081780284751936), // TEX_VTX_CONSTBUF |
607 | 0 | UINT64_C(9236056004066541632), // TEX_VTX_TEXBUF |
608 | 0 | UINT64_C(9345848836096), // TRUNC |
609 | 0 | UINT64_C(85761906966528), // UINT_TO_FLT_eg |
610 | 0 | UINT64_C(59923383713792), // UINT_TO_FLT_r600 |
611 | 0 | UINT64_C(1769087820812517440), // VTX_READ_128_cm |
612 | 0 | UINT64_C(1769087821886259264), // VTX_READ_128_eg |
613 | 0 | UINT64_C(1251983104222953536), // VTX_READ_16_cm |
614 | 0 | UINT64_C(1251983104357171264), // VTX_READ_16_eg |
615 | 0 | UINT64_C(1396098292298809408), // VTX_READ_32_cm |
616 | 0 | UINT64_C(1396098292567244864), // VTX_READ_32_eg |
617 | 0 | UINT64_C(1684223115334254656), // VTX_READ_64_cm |
618 | 0 | UINT64_C(1684223115871125568), // VTX_READ_64_eg |
619 | 0 | UINT64_C(1179925510185025600), // VTX_READ_8_cm |
620 | 0 | UINT64_C(1179925510252134464), // VTX_READ_8_eg |
621 | 0 | UINT64_C(9331458427911667712), // WHILE_LOOP_EG |
622 | 0 | UINT64_C(9439544818968559616), // WHILE_LOOP_R600 |
623 | 0 | UINT64_C(27487790694400), // XOR_INT |
624 | 0 | UINT64_C(0) |
625 | 0 | }; |
626 | 0 | const unsigned opcode = MI.getOpcode(); |
627 | 0 | uint64_t Value = InstBits[opcode]; |
628 | 0 | uint64_t op = 0; |
629 | 0 | (void)op; // suppress warning |
630 | 0 | switch (opcode) { |
631 | 0 | case R600::CF_CALL_FS_EG: |
632 | 0 | case R600::CF_CALL_FS_R600: |
633 | 0 | case R600::CF_END_CM: |
634 | 0 | case R600::CF_END_EG: |
635 | 0 | case R600::CF_END_R600: |
636 | 0 | case R600::GROUP_BARRIER: |
637 | 0 | case R600::INTERP_PAIR_XY: |
638 | 0 | case R600::INTERP_PAIR_ZW: |
639 | 0 | case R600::INTERP_VEC_LOAD: |
640 | 0 | case R600::PAD: { |
641 | 0 | break; |
642 | 0 | } |
643 | 0 | case R600::CF_CONTINUE_EG: |
644 | 0 | case R600::END_LOOP_EG: |
645 | 0 | case R600::LOOP_BREAK_EG: |
646 | 0 | case R600::WHILE_LOOP_EG: { |
647 | | // op: ADDR |
648 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
649 | 0 | op &= UINT64_C(16777215); |
650 | 0 | Value |= op; |
651 | 0 | break; |
652 | 0 | } |
653 | 0 | case R600::CF_TC_EG: |
654 | 0 | case R600::CF_VC_EG: { |
655 | | // op: ADDR |
656 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
657 | 0 | op &= UINT64_C(16777215); |
658 | 0 | Value |= op; |
659 | | // op: COUNT |
660 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
661 | 0 | op &= UINT64_C(63); |
662 | 0 | op <<= 42; |
663 | 0 | Value |= op; |
664 | 0 | break; |
665 | 0 | } |
666 | 0 | case R600::CF_ELSE_EG: |
667 | 0 | case R600::CF_JUMP_EG: |
668 | 0 | case R600::CF_PUSH_EG: |
669 | 0 | case R600::POP_EG: { |
670 | | // op: ADDR |
671 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
672 | 0 | op &= UINT64_C(16777215); |
673 | 0 | Value |= op; |
674 | | // op: POP_COUNT |
675 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
676 | 0 | op &= UINT64_C(7); |
677 | 0 | op <<= 32; |
678 | 0 | Value |= op; |
679 | 0 | break; |
680 | 0 | } |
681 | 0 | case R600::CF_ALU: |
682 | 0 | case R600::CF_ALU_BREAK: |
683 | 0 | case R600::CF_ALU_CONTINUE: |
684 | 0 | case R600::CF_ALU_ELSE_AFTER: |
685 | 0 | case R600::CF_ALU_POP_AFTER: |
686 | 0 | case R600::CF_ALU_PUSH_BEFORE: { |
687 | | // op: ADDR |
688 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
689 | 0 | op &= UINT64_C(4194303); |
690 | 0 | Value |= op; |
691 | | // op: KCACHE_BANK0 |
692 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
693 | 0 | op &= UINT64_C(15); |
694 | 0 | op <<= 22; |
695 | 0 | Value |= op; |
696 | | // op: KCACHE_BANK1 |
697 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
698 | 0 | op &= UINT64_C(15); |
699 | 0 | op <<= 26; |
700 | 0 | Value |= op; |
701 | | // op: KCACHE_MODE0 |
702 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
703 | 0 | op &= UINT64_C(3); |
704 | 0 | op <<= 30; |
705 | 0 | Value |= op; |
706 | | // op: KCACHE_MODE1 |
707 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
708 | 0 | op &= UINT64_C(3); |
709 | 0 | op <<= 32; |
710 | 0 | Value |= op; |
711 | | // op: KCACHE_ADDR0 |
712 | 0 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
713 | 0 | op &= UINT64_C(255); |
714 | 0 | op <<= 34; |
715 | 0 | Value |= op; |
716 | | // op: KCACHE_ADDR1 |
717 | 0 | op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); |
718 | 0 | op &= UINT64_C(255); |
719 | 0 | op <<= 42; |
720 | 0 | Value |= op; |
721 | | // op: COUNT |
722 | 0 | op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); |
723 | 0 | op &= UINT64_C(127); |
724 | 0 | op <<= 50; |
725 | 0 | Value |= op; |
726 | 0 | break; |
727 | 0 | } |
728 | 0 | case R600::CF_CONTINUE_R600: |
729 | 0 | case R600::CF_PUSH_ELSE_R600: |
730 | 0 | case R600::END_LOOP_R600: |
731 | 0 | case R600::LOOP_BREAK_R600: |
732 | 0 | case R600::WHILE_LOOP_R600: { |
733 | | // op: ADDR |
734 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
735 | 0 | op &= UINT64_C(4294967295); |
736 | 0 | Value |= op; |
737 | 0 | break; |
738 | 0 | } |
739 | 0 | case R600::CF_TC_R600: |
740 | 0 | case R600::CF_VC_R600: { |
741 | | // op: ADDR |
742 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
743 | 0 | op &= UINT64_C(4294967295); |
744 | 0 | Value |= op; |
745 | | // op: CNT |
746 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
747 | 0 | Value |= (op & UINT64_C(8)) << 48; |
748 | 0 | Value |= (op & UINT64_C(7)) << 42; |
749 | 0 | break; |
750 | 0 | } |
751 | 0 | case R600::CF_ELSE_R600: |
752 | 0 | case R600::CF_JUMP_R600: |
753 | 0 | case R600::POP_R600: { |
754 | | // op: ADDR |
755 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
756 | 0 | op &= UINT64_C(4294967295); |
757 | 0 | Value |= op; |
758 | | // op: POP_COUNT |
759 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
760 | 0 | op &= UINT64_C(7); |
761 | 0 | op <<= 32; |
762 | 0 | Value |= op; |
763 | 0 | break; |
764 | 0 | } |
765 | 0 | case R600::TEX_GET_GRADIENTS_H: |
766 | 0 | case R600::TEX_GET_GRADIENTS_V: |
767 | 0 | case R600::TEX_GET_TEXTURE_RESINFO: |
768 | 0 | case R600::TEX_LD: |
769 | 0 | case R600::TEX_LDPTR: |
770 | 0 | case R600::TEX_SAMPLE: |
771 | 0 | case R600::TEX_SAMPLE_C: |
772 | 0 | case R600::TEX_SAMPLE_C_G: |
773 | 0 | case R600::TEX_SAMPLE_C_L: |
774 | 0 | case R600::TEX_SAMPLE_C_LB: |
775 | 0 | case R600::TEX_SAMPLE_G: |
776 | 0 | case R600::TEX_SAMPLE_L: |
777 | 0 | case R600::TEX_SAMPLE_LB: |
778 | 0 | case R600::TEX_SET_GRADIENTS_H: |
779 | 0 | case R600::TEX_SET_GRADIENTS_V: { |
780 | | // op: RESOURCE_ID |
781 | 0 | op = getMachineOpValue(MI, MI.getOperand(13), Fixups, STI); |
782 | 0 | op &= UINT64_C(255); |
783 | 0 | op <<= 8; |
784 | 0 | Value |= op; |
785 | | // op: SRC_GPR |
786 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
787 | 0 | op &= UINT64_C(127); |
788 | 0 | op <<= 16; |
789 | 0 | Value |= op; |
790 | | // op: DST_GPR |
791 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
792 | 0 | op &= UINT64_C(127); |
793 | 0 | op <<= 32; |
794 | 0 | Value |= op; |
795 | | // op: DST_SEL_X |
796 | 0 | op = getMachineOpValue(MI, MI.getOperand(9), Fixups, STI); |
797 | 0 | op &= UINT64_C(7); |
798 | 0 | op <<= 41; |
799 | 0 | Value |= op; |
800 | | // op: DST_SEL_Y |
801 | 0 | op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); |
802 | 0 | op &= UINT64_C(7); |
803 | 0 | op <<= 44; |
804 | 0 | Value |= op; |
805 | | // op: DST_SEL_Z |
806 | 0 | op = getMachineOpValue(MI, MI.getOperand(11), Fixups, STI); |
807 | 0 | op &= UINT64_C(7); |
808 | 0 | op <<= 47; |
809 | 0 | Value |= op; |
810 | | // op: DST_SEL_W |
811 | 0 | op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI); |
812 | 0 | op &= UINT64_C(7); |
813 | 0 | op <<= 50; |
814 | 0 | Value |= op; |
815 | | // op: COORD_TYPE_X |
816 | 0 | op = getMachineOpValue(MI, MI.getOperand(15), Fixups, STI); |
817 | 0 | op &= UINT64_C(1); |
818 | 0 | op <<= 60; |
819 | 0 | Value |= op; |
820 | | // op: COORD_TYPE_Y |
821 | 0 | op = getMachineOpValue(MI, MI.getOperand(16), Fixups, STI); |
822 | 0 | op &= UINT64_C(1); |
823 | 0 | op <<= 61; |
824 | 0 | Value |= op; |
825 | | // op: COORD_TYPE_Z |
826 | 0 | op = getMachineOpValue(MI, MI.getOperand(17), Fixups, STI); |
827 | 0 | op &= UINT64_C(1); |
828 | 0 | op <<= 62; |
829 | 0 | Value |= op; |
830 | | // op: COORD_TYPE_W |
831 | 0 | op = getMachineOpValue(MI, MI.getOperand(18), Fixups, STI); |
832 | 0 | op &= UINT64_C(1); |
833 | 0 | op <<= 63; |
834 | 0 | Value |= op; |
835 | 0 | break; |
836 | 0 | } |
837 | 0 | case R600::ALU_CLAUSE: |
838 | 0 | case R600::FETCH_CLAUSE: { |
839 | | // op: addr |
840 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
841 | 0 | op &= UINT64_C(255); |
842 | 0 | Value |= op; |
843 | 0 | break; |
844 | 0 | } |
845 | 0 | case R600::EG_ExportBuf: { |
846 | | // op: arraybase |
847 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
848 | 0 | op &= UINT64_C(8191); |
849 | 0 | Value |= op; |
850 | | // op: type |
851 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
852 | 0 | op &= UINT64_C(3); |
853 | 0 | op <<= 13; |
854 | 0 | Value |= op; |
855 | | // op: gpr |
856 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
857 | 0 | op &= UINT64_C(127); |
858 | 0 | op <<= 15; |
859 | 0 | Value |= op; |
860 | | // op: arraySize |
861 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
862 | 0 | op &= UINT64_C(4095); |
863 | 0 | op <<= 32; |
864 | 0 | Value |= op; |
865 | | // op: compMask |
866 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
867 | 0 | op &= UINT64_C(15); |
868 | 0 | op <<= 44; |
869 | 0 | Value |= op; |
870 | | // op: eop |
871 | 0 | op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); |
872 | 0 | op &= UINT64_C(1); |
873 | 0 | op <<= 53; |
874 | 0 | Value |= op; |
875 | | // op: inst |
876 | 0 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
877 | 0 | op &= UINT64_C(255); |
878 | 0 | op <<= 54; |
879 | 0 | Value |= op; |
880 | 0 | break; |
881 | 0 | } |
882 | 0 | case R600::R600_ExportBuf: { |
883 | | // op: arraybase |
884 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
885 | 0 | op &= UINT64_C(8191); |
886 | 0 | Value |= op; |
887 | | // op: type |
888 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
889 | 0 | op &= UINT64_C(3); |
890 | 0 | op <<= 13; |
891 | 0 | Value |= op; |
892 | | // op: gpr |
893 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
894 | 0 | op &= UINT64_C(127); |
895 | 0 | op <<= 15; |
896 | 0 | Value |= op; |
897 | | // op: arraySize |
898 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
899 | 0 | op &= UINT64_C(4095); |
900 | 0 | op <<= 32; |
901 | 0 | Value |= op; |
902 | | // op: compMask |
903 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
904 | 0 | op &= UINT64_C(15); |
905 | 0 | op <<= 44; |
906 | 0 | Value |= op; |
907 | | // op: eop |
908 | 0 | op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); |
909 | 0 | op &= UINT64_C(1); |
910 | 0 | op <<= 53; |
911 | 0 | Value |= op; |
912 | | // op: inst |
913 | 0 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
914 | 0 | op &= UINT64_C(255); |
915 | 0 | op <<= 55; |
916 | 0 | Value |= op; |
917 | 0 | break; |
918 | 0 | } |
919 | 0 | case R600::EG_ExportSwz: { |
920 | | // op: arraybase |
921 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
922 | 0 | op &= UINT64_C(8191); |
923 | 0 | Value |= op; |
924 | | // op: type |
925 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
926 | 0 | op &= UINT64_C(3); |
927 | 0 | op <<= 13; |
928 | 0 | Value |= op; |
929 | | // op: gpr |
930 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
931 | 0 | op &= UINT64_C(127); |
932 | 0 | op <<= 15; |
933 | 0 | Value |= op; |
934 | | // op: sw_x |
935 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
936 | 0 | op &= UINT64_C(7); |
937 | 0 | op <<= 32; |
938 | 0 | Value |= op; |
939 | | // op: sw_y |
940 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
941 | 0 | op &= UINT64_C(7); |
942 | 0 | op <<= 35; |
943 | 0 | Value |= op; |
944 | | // op: sw_z |
945 | 0 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
946 | 0 | op &= UINT64_C(7); |
947 | 0 | op <<= 38; |
948 | 0 | Value |= op; |
949 | | // op: sw_w |
950 | 0 | op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); |
951 | 0 | op &= UINT64_C(7); |
952 | 0 | op <<= 41; |
953 | 0 | Value |= op; |
954 | | // op: eop |
955 | 0 | op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); |
956 | 0 | op &= UINT64_C(1); |
957 | 0 | op <<= 53; |
958 | 0 | Value |= op; |
959 | | // op: inst |
960 | 0 | op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); |
961 | 0 | op &= UINT64_C(255); |
962 | 0 | op <<= 54; |
963 | 0 | Value |= op; |
964 | 0 | break; |
965 | 0 | } |
966 | 0 | case R600::R600_ExportSwz: { |
967 | | // op: arraybase |
968 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
969 | 0 | op &= UINT64_C(8191); |
970 | 0 | Value |= op; |
971 | | // op: type |
972 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
973 | 0 | op &= UINT64_C(3); |
974 | 0 | op <<= 13; |
975 | 0 | Value |= op; |
976 | | // op: gpr |
977 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
978 | 0 | op &= UINT64_C(127); |
979 | 0 | op <<= 15; |
980 | 0 | Value |= op; |
981 | | // op: sw_x |
982 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
983 | 0 | op &= UINT64_C(7); |
984 | 0 | op <<= 32; |
985 | 0 | Value |= op; |
986 | | // op: sw_y |
987 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
988 | 0 | op &= UINT64_C(7); |
989 | 0 | op <<= 35; |
990 | 0 | Value |= op; |
991 | | // op: sw_z |
992 | 0 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
993 | 0 | op &= UINT64_C(7); |
994 | 0 | op <<= 38; |
995 | 0 | Value |= op; |
996 | | // op: sw_w |
997 | 0 | op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); |
998 | 0 | op &= UINT64_C(7); |
999 | 0 | op <<= 41; |
1000 | 0 | Value |= op; |
1001 | | // op: eop |
1002 | 0 | op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); |
1003 | 0 | op &= UINT64_C(1); |
1004 | 0 | op <<= 53; |
1005 | 0 | Value |= op; |
1006 | | // op: inst |
1007 | 0 | op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); |
1008 | 0 | op &= UINT64_C(255); |
1009 | 0 | op <<= 55; |
1010 | 0 | Value |= op; |
1011 | 0 | break; |
1012 | 0 | } |
1013 | 0 | case R600::TEX_VTX_CONSTBUF: |
1014 | 0 | case R600::TEX_VTX_TEXBUF: { |
1015 | | // op: dst_gpr |
1016 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1017 | 0 | op &= UINT64_C(127); |
1018 | 0 | op <<= 32; |
1019 | 0 | Value |= op; |
1020 | | // op: src_gpr |
1021 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1022 | 0 | op &= UINT64_C(127); |
1023 | 0 | op <<= 16; |
1024 | 0 | Value |= op; |
1025 | | // op: buffer_id |
1026 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
1027 | 0 | op &= UINT64_C(255); |
1028 | 0 | op <<= 8; |
1029 | 0 | Value |= op; |
1030 | 0 | break; |
1031 | 0 | } |
1032 | 0 | case R600::LITERALS: { |
1033 | | // op: literal1 |
1034 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1035 | 0 | op &= UINT64_C(4294967295); |
1036 | 0 | Value |= op; |
1037 | | // op: literal2 |
1038 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1039 | 0 | op &= UINT64_C(4294967295); |
1040 | 0 | op <<= 32; |
1041 | 0 | Value |= op; |
1042 | 0 | break; |
1043 | 0 | } |
1044 | 0 | case R600::RAT_STORE_TYPED_cm: { |
1045 | | // op: rat_id |
1046 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1047 | 0 | op &= UINT64_C(15); |
1048 | 0 | Value |= op; |
1049 | | // op: rw_gpr |
1050 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1051 | 0 | op &= UINT64_C(127); |
1052 | 0 | op <<= 15; |
1053 | 0 | Value |= op; |
1054 | | // op: index_gpr |
1055 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1056 | 0 | op &= UINT64_C(127); |
1057 | 0 | op <<= 23; |
1058 | 0 | Value |= op; |
1059 | 0 | break; |
1060 | 0 | } |
1061 | 0 | case R600::RAT_STORE_TYPED_eg: { |
1062 | | // op: rat_id |
1063 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1064 | 0 | op &= UINT64_C(15); |
1065 | 0 | Value |= op; |
1066 | | // op: rw_gpr |
1067 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1068 | 0 | op &= UINT64_C(127); |
1069 | 0 | op <<= 15; |
1070 | 0 | Value |= op; |
1071 | | // op: index_gpr |
1072 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1073 | 0 | op &= UINT64_C(127); |
1074 | 0 | op <<= 23; |
1075 | 0 | Value |= op; |
1076 | | // op: eop |
1077 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
1078 | 0 | op &= UINT64_C(1); |
1079 | 0 | op <<= 53; |
1080 | 0 | Value |= op; |
1081 | 0 | break; |
1082 | 0 | } |
1083 | 0 | case R600::RAT_MSKOR: |
1084 | 0 | case R600::RAT_STORE_DWORD32: |
1085 | 0 | case R600::RAT_STORE_DWORD64: |
1086 | 0 | case R600::RAT_STORE_DWORD128: { |
1087 | | // op: rw_gpr |
1088 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1089 | 0 | op &= UINT64_C(127); |
1090 | 0 | op <<= 15; |
1091 | 0 | Value |= op; |
1092 | | // op: index_gpr |
1093 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1094 | 0 | op &= UINT64_C(127); |
1095 | 0 | op <<= 23; |
1096 | 0 | Value |= op; |
1097 | 0 | break; |
1098 | 0 | } |
1099 | 0 | case R600::RAT_WRITE_CACHELESS_32_eg: |
1100 | 0 | case R600::RAT_WRITE_CACHELESS_64_eg: |
1101 | 0 | case R600::RAT_WRITE_CACHELESS_128_eg: { |
1102 | | // op: rw_gpr |
1103 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1104 | 0 | op &= UINT64_C(127); |
1105 | 0 | op <<= 15; |
1106 | 0 | Value |= op; |
1107 | | // op: index_gpr |
1108 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1109 | 0 | op &= UINT64_C(127); |
1110 | 0 | op <<= 23; |
1111 | 0 | Value |= op; |
1112 | | // op: eop |
1113 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1114 | 0 | op &= UINT64_C(1); |
1115 | 0 | op <<= 53; |
1116 | 0 | Value |= op; |
1117 | 0 | break; |
1118 | 0 | } |
1119 | 0 | case R600::RAT_ATOMIC_ADD_NORET: |
1120 | 0 | case R600::RAT_ATOMIC_ADD_RTN: |
1121 | 0 | case R600::RAT_ATOMIC_AND_NORET: |
1122 | 0 | case R600::RAT_ATOMIC_AND_RTN: |
1123 | 0 | case R600::RAT_ATOMIC_CMPXCHG_INT_NORET: |
1124 | 0 | case R600::RAT_ATOMIC_CMPXCHG_INT_RTN: |
1125 | 0 | case R600::RAT_ATOMIC_DEC_UINT_NORET: |
1126 | 0 | case R600::RAT_ATOMIC_DEC_UINT_RTN: |
1127 | 0 | case R600::RAT_ATOMIC_INC_UINT_NORET: |
1128 | 0 | case R600::RAT_ATOMIC_INC_UINT_RTN: |
1129 | 0 | case R600::RAT_ATOMIC_MAX_INT_NORET: |
1130 | 0 | case R600::RAT_ATOMIC_MAX_INT_RTN: |
1131 | 0 | case R600::RAT_ATOMIC_MAX_UINT_NORET: |
1132 | 0 | case R600::RAT_ATOMIC_MAX_UINT_RTN: |
1133 | 0 | case R600::RAT_ATOMIC_MIN_INT_NORET: |
1134 | 0 | case R600::RAT_ATOMIC_MIN_INT_RTN: |
1135 | 0 | case R600::RAT_ATOMIC_MIN_UINT_NORET: |
1136 | 0 | case R600::RAT_ATOMIC_MIN_UINT_RTN: |
1137 | 0 | case R600::RAT_ATOMIC_OR_NORET: |
1138 | 0 | case R600::RAT_ATOMIC_OR_RTN: |
1139 | 0 | case R600::RAT_ATOMIC_RSUB_NORET: |
1140 | 0 | case R600::RAT_ATOMIC_RSUB_RTN: |
1141 | 0 | case R600::RAT_ATOMIC_SUB_NORET: |
1142 | 0 | case R600::RAT_ATOMIC_SUB_RTN: |
1143 | 0 | case R600::RAT_ATOMIC_XCHG_INT_NORET: |
1144 | 0 | case R600::RAT_ATOMIC_XCHG_INT_RTN: |
1145 | 0 | case R600::RAT_ATOMIC_XOR_NORET: |
1146 | 0 | case R600::RAT_ATOMIC_XOR_RTN: { |
1147 | | // op: rw_gpr |
1148 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1149 | 0 | op &= UINT64_C(127); |
1150 | 0 | op <<= 15; |
1151 | 0 | Value |= op; |
1152 | | // op: index_gpr |
1153 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1154 | 0 | op &= UINT64_C(127); |
1155 | 0 | op <<= 23; |
1156 | 0 | Value |= op; |
1157 | 0 | break; |
1158 | 0 | } |
1159 | 0 | case R600::LDS_CMPST: { |
1160 | | // op: src0 |
1161 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1162 | 0 | Value |= (op & UINT64_C(1536)) << 1; |
1163 | 0 | Value |= (op & UINT64_C(511)); |
1164 | | // op: src0_rel |
1165 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1166 | 0 | op &= UINT64_C(1); |
1167 | 0 | op <<= 9; |
1168 | 0 | Value |= op; |
1169 | | // op: src1 |
1170 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
1171 | 0 | Value |= (op & UINT64_C(1536)) << 14; |
1172 | 0 | Value |= (op & UINT64_C(511)) << 13; |
1173 | | // op: src1_rel |
1174 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
1175 | 0 | op &= UINT64_C(1); |
1176 | 0 | op <<= 22; |
1177 | 0 | Value |= op; |
1178 | | // op: pred_sel |
1179 | 0 | op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); |
1180 | 0 | op &= UINT64_C(3); |
1181 | 0 | op <<= 29; |
1182 | 0 | Value |= op; |
1183 | | // op: last |
1184 | 0 | op = getMachineOpValue(MI, MI.getOperand(9), Fixups, STI); |
1185 | 0 | op &= UINT64_C(1); |
1186 | 0 | op <<= 31; |
1187 | 0 | Value |= op; |
1188 | | // op: src2 |
1189 | 0 | op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); |
1190 | 0 | Value |= (op & UINT64_C(1536)) << 33; |
1191 | 0 | Value |= (op & UINT64_C(511)) << 32; |
1192 | | // op: src2_rel |
1193 | 0 | op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); |
1194 | 0 | op &= UINT64_C(1); |
1195 | 0 | op <<= 41; |
1196 | 0 | Value |= op; |
1197 | | // op: bank_swizzle |
1198 | 0 | op = getMachineOpValue(MI, MI.getOperand(11), Fixups, STI); |
1199 | 0 | op &= UINT64_C(7); |
1200 | 0 | op <<= 50; |
1201 | 0 | Value |= op; |
1202 | 0 | break; |
1203 | 0 | } |
1204 | 0 | case R600::LDS_ADD: |
1205 | 0 | case R600::LDS_AND: |
1206 | 0 | case R600::LDS_BYTE_WRITE: |
1207 | 0 | case R600::LDS_MAX_INT: |
1208 | 0 | case R600::LDS_MAX_UINT: |
1209 | 0 | case R600::LDS_MIN_INT: |
1210 | 0 | case R600::LDS_MIN_UINT: |
1211 | 0 | case R600::LDS_OR: |
1212 | 0 | case R600::LDS_SHORT_WRITE: |
1213 | 0 | case R600::LDS_SUB: |
1214 | 0 | case R600::LDS_WRITE: |
1215 | 0 | case R600::LDS_WRXCHG: |
1216 | 0 | case R600::LDS_XOR: { |
1217 | | // op: src0 |
1218 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1219 | 0 | Value |= (op & UINT64_C(1536)) << 1; |
1220 | 0 | Value |= (op & UINT64_C(511)); |
1221 | | // op: src0_rel |
1222 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1223 | 0 | op &= UINT64_C(1); |
1224 | 0 | op <<= 9; |
1225 | 0 | Value |= op; |
1226 | | // op: src1 |
1227 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
1228 | 0 | Value |= (op & UINT64_C(1536)) << 14; |
1229 | 0 | Value |= (op & UINT64_C(511)) << 13; |
1230 | | // op: src1_rel |
1231 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
1232 | 0 | op &= UINT64_C(1); |
1233 | 0 | op <<= 22; |
1234 | 0 | Value |= op; |
1235 | | // op: pred_sel |
1236 | 0 | op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); |
1237 | 0 | op &= UINT64_C(3); |
1238 | 0 | op <<= 29; |
1239 | 0 | Value |= op; |
1240 | | // op: last |
1241 | 0 | op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); |
1242 | 0 | op &= UINT64_C(1); |
1243 | 0 | op <<= 31; |
1244 | 0 | Value |= op; |
1245 | | // op: bank_swizzle |
1246 | 0 | op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); |
1247 | 0 | op &= UINT64_C(7); |
1248 | 0 | op <<= 50; |
1249 | 0 | Value |= op; |
1250 | 0 | break; |
1251 | 0 | } |
1252 | 0 | case R600::LDS_BYTE_READ_RET: |
1253 | 0 | case R600::LDS_READ_RET: |
1254 | 0 | case R600::LDS_SHORT_READ_RET: |
1255 | 0 | case R600::LDS_UBYTE_READ_RET: |
1256 | 0 | case R600::LDS_USHORT_READ_RET: { |
1257 | | // op: src0 |
1258 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1259 | 0 | Value |= (op & UINT64_C(1536)) << 1; |
1260 | 0 | Value |= (op & UINT64_C(511)); |
1261 | | // op: src0_rel |
1262 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1263 | 0 | op &= UINT64_C(1); |
1264 | 0 | op <<= 9; |
1265 | 0 | Value |= op; |
1266 | | // op: pred_sel |
1267 | 0 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
1268 | 0 | op &= UINT64_C(3); |
1269 | 0 | op <<= 29; |
1270 | 0 | Value |= op; |
1271 | | // op: last |
1272 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
1273 | 0 | op &= UINT64_C(1); |
1274 | 0 | op <<= 31; |
1275 | 0 | Value |= op; |
1276 | | // op: bank_swizzle |
1277 | 0 | op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); |
1278 | 0 | op &= UINT64_C(7); |
1279 | 0 | op <<= 50; |
1280 | 0 | Value |= op; |
1281 | 0 | break; |
1282 | 0 | } |
1283 | 0 | case R600::LDS_CMPST_RET: { |
1284 | | // op: src0 |
1285 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1286 | 0 | Value |= (op & UINT64_C(1536)) << 1; |
1287 | 0 | Value |= (op & UINT64_C(511)); |
1288 | | // op: src0_rel |
1289 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1290 | 0 | op &= UINT64_C(1); |
1291 | 0 | op <<= 9; |
1292 | 0 | Value |= op; |
1293 | | // op: src1 |
1294 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
1295 | 0 | Value |= (op & UINT64_C(1536)) << 14; |
1296 | 0 | Value |= (op & UINT64_C(511)) << 13; |
1297 | | // op: src1_rel |
1298 | 0 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
1299 | 0 | op &= UINT64_C(1); |
1300 | 0 | op <<= 22; |
1301 | 0 | Value |= op; |
1302 | | // op: pred_sel |
1303 | 0 | op = getMachineOpValue(MI, MI.getOperand(11), Fixups, STI); |
1304 | 0 | op &= UINT64_C(3); |
1305 | 0 | op <<= 29; |
1306 | 0 | Value |= op; |
1307 | | // op: last |
1308 | 0 | op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); |
1309 | 0 | op &= UINT64_C(1); |
1310 | 0 | op <<= 31; |
1311 | 0 | Value |= op; |
1312 | | // op: src2 |
1313 | 0 | op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); |
1314 | 0 | Value |= (op & UINT64_C(1536)) << 33; |
1315 | 0 | Value |= (op & UINT64_C(511)) << 32; |
1316 | | // op: src2_rel |
1317 | 0 | op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); |
1318 | 0 | op &= UINT64_C(1); |
1319 | 0 | op <<= 41; |
1320 | 0 | Value |= op; |
1321 | | // op: bank_swizzle |
1322 | 0 | op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI); |
1323 | 0 | op &= UINT64_C(7); |
1324 | 0 | op <<= 50; |
1325 | 0 | Value |= op; |
1326 | 0 | break; |
1327 | 0 | } |
1328 | 0 | case R600::LDS_ADD_RET: |
1329 | 0 | case R600::LDS_AND_RET: |
1330 | 0 | case R600::LDS_MAX_INT_RET: |
1331 | 0 | case R600::LDS_MAX_UINT_RET: |
1332 | 0 | case R600::LDS_MIN_INT_RET: |
1333 | 0 | case R600::LDS_MIN_UINT_RET: |
1334 | 0 | case R600::LDS_OR_RET: |
1335 | 0 | case R600::LDS_SUB_RET: |
1336 | 0 | case R600::LDS_WRXCHG_RET: |
1337 | 0 | case R600::LDS_XOR_RET: { |
1338 | | // op: src0 |
1339 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1340 | 0 | Value |= (op & UINT64_C(1536)) << 1; |
1341 | 0 | Value |= (op & UINT64_C(511)); |
1342 | | // op: src0_rel |
1343 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1344 | 0 | op &= UINT64_C(1); |
1345 | 0 | op <<= 9; |
1346 | 0 | Value |= op; |
1347 | | // op: src1 |
1348 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
1349 | 0 | Value |= (op & UINT64_C(1536)) << 14; |
1350 | 0 | Value |= (op & UINT64_C(511)) << 13; |
1351 | | // op: src1_rel |
1352 | 0 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
1353 | 0 | op &= UINT64_C(1); |
1354 | 0 | op <<= 22; |
1355 | 0 | Value |= op; |
1356 | | // op: pred_sel |
1357 | 0 | op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); |
1358 | 0 | op &= UINT64_C(3); |
1359 | 0 | op <<= 29; |
1360 | 0 | Value |= op; |
1361 | | // op: last |
1362 | 0 | op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); |
1363 | 0 | op &= UINT64_C(1); |
1364 | 0 | op <<= 31; |
1365 | 0 | Value |= op; |
1366 | | // op: bank_swizzle |
1367 | 0 | op = getMachineOpValue(MI, MI.getOperand(9), Fixups, STI); |
1368 | 0 | op &= UINT64_C(7); |
1369 | 0 | op <<= 50; |
1370 | 0 | Value |= op; |
1371 | 0 | break; |
1372 | 0 | } |
1373 | 0 | case R600::BFE_INT_eg: |
1374 | 0 | case R600::BFE_UINT_eg: |
1375 | 0 | case R600::BFI_INT_eg: |
1376 | 0 | case R600::BIT_ALIGN_INT_eg: |
1377 | 0 | case R600::CNDE_INT: |
1378 | 0 | case R600::CNDE_eg: |
1379 | 0 | case R600::CNDE_r600: |
1380 | 0 | case R600::CNDGE_INT: |
1381 | 0 | case R600::CNDGE_eg: |
1382 | 0 | case R600::CNDGE_r600: |
1383 | 0 | case R600::CNDGT_INT: |
1384 | 0 | case R600::CNDGT_eg: |
1385 | 0 | case R600::CNDGT_r600: |
1386 | 0 | case R600::FMA_eg: |
1387 | 0 | case R600::MULADD_IEEE_eg: |
1388 | 0 | case R600::MULADD_IEEE_r600: |
1389 | 0 | case R600::MULADD_INT24_cm: |
1390 | 0 | case R600::MULADD_UINT24_eg: |
1391 | 0 | case R600::MULADD_eg: |
1392 | 0 | case R600::MULADD_r600: |
1393 | 0 | case R600::MUL_LIT_eg: |
1394 | 0 | case R600::MUL_LIT_r600: { |
1395 | | // op: src0 |
1396 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
1397 | 0 | Value |= (op & UINT64_C(1536)) << 1; |
1398 | 0 | Value |= (op & UINT64_C(511)); |
1399 | | // op: src0_rel |
1400 | 0 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
1401 | 0 | op &= UINT64_C(1); |
1402 | 0 | op <<= 9; |
1403 | 0 | Value |= op; |
1404 | | // op: src1 |
1405 | 0 | op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); |
1406 | 0 | Value |= (op & UINT64_C(1536)) << 14; |
1407 | 0 | Value |= (op & UINT64_C(511)) << 13; |
1408 | | // op: src1_rel |
1409 | 0 | op = getMachineOpValue(MI, MI.getOperand(9), Fixups, STI); |
1410 | 0 | op &= UINT64_C(1); |
1411 | 0 | op <<= 22; |
1412 | 0 | Value |= op; |
1413 | | // op: pred_sel |
1414 | 0 | op = getMachineOpValue(MI, MI.getOperand(16), Fixups, STI); |
1415 | 0 | op &= UINT64_C(3); |
1416 | 0 | op <<= 29; |
1417 | 0 | Value |= op; |
1418 | | // op: last |
1419 | 0 | op = getMachineOpValue(MI, MI.getOperand(15), Fixups, STI); |
1420 | 0 | op &= UINT64_C(1); |
1421 | 0 | op <<= 31; |
1422 | 0 | Value |= op; |
1423 | | // op: src0_neg |
1424 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
1425 | 0 | op &= UINT64_C(1); |
1426 | 0 | op <<= 12; |
1427 | 0 | Value |= op; |
1428 | | // op: src1_neg |
1429 | 0 | op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); |
1430 | 0 | op &= UINT64_C(1); |
1431 | 0 | op <<= 25; |
1432 | 0 | Value |= op; |
1433 | | // op: dst |
1434 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1435 | 0 | Value |= (op & UINT64_C(1536)) << 52; |
1436 | 0 | Value |= (op & UINT64_C(127)) << 53; |
1437 | | // op: bank_swizzle |
1438 | 0 | op = getMachineOpValue(MI, MI.getOperand(18), Fixups, STI); |
1439 | 0 | op &= UINT64_C(7); |
1440 | 0 | op <<= 50; |
1441 | 0 | Value |= op; |
1442 | | // op: dst_rel |
1443 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1444 | 0 | op &= UINT64_C(1); |
1445 | 0 | op <<= 60; |
1446 | 0 | Value |= op; |
1447 | | // op: clamp |
1448 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1449 | 0 | op &= UINT64_C(1); |
1450 | 0 | op <<= 63; |
1451 | 0 | Value |= op; |
1452 | | // op: src2 |
1453 | 0 | op = getMachineOpValue(MI, MI.getOperand(11), Fixups, STI); |
1454 | 0 | Value |= (op & UINT64_C(1536)) << 33; |
1455 | 0 | Value |= (op & UINT64_C(511)) << 32; |
1456 | | // op: src2_rel |
1457 | 0 | op = getMachineOpValue(MI, MI.getOperand(13), Fixups, STI); |
1458 | 0 | op &= UINT64_C(1); |
1459 | 0 | op <<= 41; |
1460 | 0 | Value |= op; |
1461 | | // op: src2_neg |
1462 | 0 | op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI); |
1463 | 0 | op &= UINT64_C(1); |
1464 | 0 | op <<= 44; |
1465 | 0 | Value |= op; |
1466 | 0 | break; |
1467 | 0 | } |
1468 | 0 | case R600::BCNT_INT: |
1469 | 0 | case R600::CEIL: |
1470 | 0 | case R600::COS_cm: |
1471 | 0 | case R600::COS_eg: |
1472 | 0 | case R600::COS_r600: |
1473 | 0 | case R600::COS_r700: |
1474 | 0 | case R600::EXP_IEEE_cm: |
1475 | 0 | case R600::EXP_IEEE_eg: |
1476 | 0 | case R600::EXP_IEEE_r600: |
1477 | 0 | case R600::FFBH_UINT: |
1478 | 0 | case R600::FFBL_INT: |
1479 | 0 | case R600::FLOOR: |
1480 | 0 | case R600::FLT16_TO_FLT32: |
1481 | 0 | case R600::FLT32_TO_FLT16: |
1482 | 0 | case R600::FLT_TO_INT_eg: |
1483 | 0 | case R600::FLT_TO_INT_r600: |
1484 | 0 | case R600::FLT_TO_UINT_eg: |
1485 | 0 | case R600::FLT_TO_UINT_r600: |
1486 | 0 | case R600::FRACT: |
1487 | 0 | case R600::INTERP_LOAD_P0: |
1488 | 0 | case R600::INT_TO_FLT_eg: |
1489 | 0 | case R600::INT_TO_FLT_r600: |
1490 | 0 | case R600::LOG_CLAMPED_eg: |
1491 | 0 | case R600::LOG_CLAMPED_r600: |
1492 | 0 | case R600::LOG_IEEE_cm: |
1493 | 0 | case R600::LOG_IEEE_eg: |
1494 | 0 | case R600::LOG_IEEE_r600: |
1495 | 0 | case R600::MOV: |
1496 | 0 | case R600::MOVA_INT_eg: |
1497 | 0 | case R600::NOT_INT: |
1498 | 0 | case R600::RECIPSQRT_CLAMPED_cm: |
1499 | 0 | case R600::RECIPSQRT_CLAMPED_eg: |
1500 | 0 | case R600::RECIPSQRT_CLAMPED_r600: |
1501 | 0 | case R600::RECIPSQRT_IEEE_cm: |
1502 | 0 | case R600::RECIPSQRT_IEEE_eg: |
1503 | 0 | case R600::RECIPSQRT_IEEE_r600: |
1504 | 0 | case R600::RECIP_CLAMPED_cm: |
1505 | 0 | case R600::RECIP_CLAMPED_eg: |
1506 | 0 | case R600::RECIP_CLAMPED_r600: |
1507 | 0 | case R600::RECIP_IEEE_cm: |
1508 | 0 | case R600::RECIP_IEEE_eg: |
1509 | 0 | case R600::RECIP_IEEE_r600: |
1510 | 0 | case R600::RECIP_UINT_eg: |
1511 | 0 | case R600::RECIP_UINT_r600: |
1512 | 0 | case R600::RNDNE: |
1513 | 0 | case R600::SIN_cm: |
1514 | 0 | case R600::SIN_eg: |
1515 | 0 | case R600::SIN_r600: |
1516 | 0 | case R600::SIN_r700: |
1517 | 0 | case R600::TRUNC: |
1518 | 0 | case R600::UINT_TO_FLT_eg: |
1519 | 0 | case R600::UINT_TO_FLT_r600: { |
1520 | | // op: src0 |
1521 | 0 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
1522 | 0 | Value |= (op & UINT64_C(1536)) << 1; |
1523 | 0 | Value |= (op & UINT64_C(511)); |
1524 | | // op: src0_rel |
1525 | 0 | op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); |
1526 | 0 | op &= UINT64_C(1); |
1527 | 0 | op <<= 9; |
1528 | 0 | Value |= op; |
1529 | | // op: pred_sel |
1530 | 0 | op = getMachineOpValue(MI, MI.getOperand(11), Fixups, STI); |
1531 | 0 | op &= UINT64_C(3); |
1532 | 0 | op <<= 29; |
1533 | 0 | Value |= op; |
1534 | | // op: last |
1535 | 0 | op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); |
1536 | 0 | op &= UINT64_C(1); |
1537 | 0 | op <<= 31; |
1538 | 0 | Value |= op; |
1539 | | // op: src0_neg |
1540 | 0 | op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); |
1541 | 0 | op &= UINT64_C(1); |
1542 | 0 | op <<= 12; |
1543 | 0 | Value |= op; |
1544 | | // op: dst |
1545 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1546 | 0 | Value |= (op & UINT64_C(1536)) << 52; |
1547 | 0 | Value |= (op & UINT64_C(127)) << 53; |
1548 | | // op: bank_swizzle |
1549 | 0 | op = getMachineOpValue(MI, MI.getOperand(13), Fixups, STI); |
1550 | 0 | op &= UINT64_C(7); |
1551 | 0 | op <<= 50; |
1552 | 0 | Value |= op; |
1553 | | // op: dst_rel |
1554 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
1555 | 0 | op &= UINT64_C(1); |
1556 | 0 | op <<= 60; |
1557 | 0 | Value |= op; |
1558 | | // op: clamp |
1559 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
1560 | 0 | op &= UINT64_C(1); |
1561 | 0 | op <<= 63; |
1562 | 0 | Value |= op; |
1563 | | // op: src0_abs |
1564 | 0 | op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); |
1565 | 0 | op &= UINT64_C(1); |
1566 | 0 | op <<= 32; |
1567 | 0 | Value |= op; |
1568 | | // op: write |
1569 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1570 | 0 | op &= UINT64_C(1); |
1571 | 0 | op <<= 36; |
1572 | 0 | Value |= op; |
1573 | | // op: omod |
1574 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1575 | 0 | op &= UINT64_C(3); |
1576 | 0 | op <<= 37; |
1577 | 0 | Value |= op; |
1578 | 0 | break; |
1579 | 0 | } |
1580 | 0 | case R600::ADD: |
1581 | 0 | case R600::ADDC_UINT: |
1582 | 0 | case R600::ADD_INT: |
1583 | 0 | case R600::AND_INT: |
1584 | 0 | case R600::ASHR_eg: |
1585 | 0 | case R600::ASHR_r600: |
1586 | 0 | case R600::BFM_INT_eg: |
1587 | 0 | case R600::CUBE_eg_real: |
1588 | 0 | case R600::CUBE_r600_real: |
1589 | 0 | case R600::DOT4_eg: |
1590 | 0 | case R600::DOT4_r600: |
1591 | 0 | case R600::KILLGT: |
1592 | 0 | case R600::LSHL_eg: |
1593 | 0 | case R600::LSHL_r600: |
1594 | 0 | case R600::LSHR_eg: |
1595 | 0 | case R600::LSHR_r600: |
1596 | 0 | case R600::MAX: |
1597 | 0 | case R600::MAX_DX10: |
1598 | 0 | case R600::MAX_INT: |
1599 | 0 | case R600::MAX_UINT: |
1600 | 0 | case R600::MIN: |
1601 | 0 | case R600::MIN_DX10: |
1602 | 0 | case R600::MIN_INT: |
1603 | 0 | case R600::MIN_UINT: |
1604 | 0 | case R600::MUL: |
1605 | 0 | case R600::MULHI_INT_cm: |
1606 | 0 | case R600::MULHI_INT_cm24: |
1607 | 0 | case R600::MULHI_INT_eg: |
1608 | 0 | case R600::MULHI_INT_r600: |
1609 | 0 | case R600::MULHI_UINT24_eg: |
1610 | 0 | case R600::MULHI_UINT_cm: |
1611 | 0 | case R600::MULHI_UINT_cm24: |
1612 | 0 | case R600::MULHI_UINT_eg: |
1613 | 0 | case R600::MULHI_UINT_r600: |
1614 | 0 | case R600::MULLO_INT_cm: |
1615 | 0 | case R600::MULLO_INT_eg: |
1616 | 0 | case R600::MULLO_INT_r600: |
1617 | 0 | case R600::MULLO_UINT_cm: |
1618 | 0 | case R600::MULLO_UINT_eg: |
1619 | 0 | case R600::MULLO_UINT_r600: |
1620 | 0 | case R600::MUL_IEEE: |
1621 | 0 | case R600::MUL_INT24_cm: |
1622 | 0 | case R600::MUL_UINT24_eg: |
1623 | 0 | case R600::OR_INT: |
1624 | 0 | case R600::PRED_SETE: |
1625 | 0 | case R600::PRED_SETE_INT: |
1626 | 0 | case R600::PRED_SETGE: |
1627 | 0 | case R600::PRED_SETGE_INT: |
1628 | 0 | case R600::PRED_SETGT: |
1629 | 0 | case R600::PRED_SETGT_INT: |
1630 | 0 | case R600::PRED_SETNE: |
1631 | 0 | case R600::PRED_SETNE_INT: |
1632 | 0 | case R600::SETE: |
1633 | 0 | case R600::SETE_DX10: |
1634 | 0 | case R600::SETE_INT: |
1635 | 0 | case R600::SETGE_DX10: |
1636 | 0 | case R600::SETGE_INT: |
1637 | 0 | case R600::SETGE_UINT: |
1638 | 0 | case R600::SETGT_DX10: |
1639 | 0 | case R600::SETGT_INT: |
1640 | 0 | case R600::SETGT_UINT: |
1641 | 0 | case R600::SETNE_DX10: |
1642 | 0 | case R600::SETNE_INT: |
1643 | 0 | case R600::SGE: |
1644 | 0 | case R600::SGT: |
1645 | 0 | case R600::SNE: |
1646 | 0 | case R600::SUBB_UINT: |
1647 | 0 | case R600::SUB_INT: |
1648 | 0 | case R600::XOR_INT: { |
1649 | | // op: src0 |
1650 | 0 | op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); |
1651 | 0 | Value |= (op & UINT64_C(1536)) << 1; |
1652 | 0 | Value |= (op & UINT64_C(511)); |
1653 | | // op: src0_rel |
1654 | 0 | op = getMachineOpValue(MI, MI.getOperand(9), Fixups, STI); |
1655 | 0 | op &= UINT64_C(1); |
1656 | 0 | op <<= 9; |
1657 | 0 | Value |= op; |
1658 | | // op: src1 |
1659 | 0 | op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI); |
1660 | 0 | Value |= (op & UINT64_C(1536)) << 14; |
1661 | 0 | Value |= (op & UINT64_C(511)) << 13; |
1662 | | // op: src1_rel |
1663 | 0 | op = getMachineOpValue(MI, MI.getOperand(14), Fixups, STI); |
1664 | 0 | op &= UINT64_C(1); |
1665 | 0 | op <<= 22; |
1666 | 0 | Value |= op; |
1667 | | // op: pred_sel |
1668 | 0 | op = getMachineOpValue(MI, MI.getOperand(18), Fixups, STI); |
1669 | 0 | op &= UINT64_C(3); |
1670 | 0 | op <<= 29; |
1671 | 0 | Value |= op; |
1672 | | // op: last |
1673 | 0 | op = getMachineOpValue(MI, MI.getOperand(17), Fixups, STI); |
1674 | 0 | op &= UINT64_C(1); |
1675 | 0 | op <<= 31; |
1676 | 0 | Value |= op; |
1677 | | // op: src0_neg |
1678 | 0 | op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); |
1679 | 0 | op &= UINT64_C(1); |
1680 | 0 | op <<= 12; |
1681 | 0 | Value |= op; |
1682 | | // op: src1_neg |
1683 | 0 | op = getMachineOpValue(MI, MI.getOperand(13), Fixups, STI); |
1684 | 0 | op &= UINT64_C(1); |
1685 | 0 | op <<= 25; |
1686 | 0 | Value |= op; |
1687 | | // op: dst |
1688 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1689 | 0 | Value |= (op & UINT64_C(1536)) << 52; |
1690 | 0 | Value |= (op & UINT64_C(127)) << 53; |
1691 | | // op: bank_swizzle |
1692 | 0 | op = getMachineOpValue(MI, MI.getOperand(20), Fixups, STI); |
1693 | 0 | op &= UINT64_C(7); |
1694 | 0 | op <<= 50; |
1695 | 0 | Value |= op; |
1696 | | // op: dst_rel |
1697 | 0 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
1698 | 0 | op &= UINT64_C(1); |
1699 | 0 | op <<= 60; |
1700 | 0 | Value |= op; |
1701 | | // op: clamp |
1702 | 0 | op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); |
1703 | 0 | op &= UINT64_C(1); |
1704 | 0 | op <<= 63; |
1705 | 0 | Value |= op; |
1706 | | // op: src0_abs |
1707 | 0 | op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); |
1708 | 0 | op &= UINT64_C(1); |
1709 | 0 | op <<= 32; |
1710 | 0 | Value |= op; |
1711 | | // op: src1_abs |
1712 | 0 | op = getMachineOpValue(MI, MI.getOperand(15), Fixups, STI); |
1713 | 0 | op &= UINT64_C(1); |
1714 | 0 | op <<= 33; |
1715 | 0 | Value |= op; |
1716 | | // op: update_exec_mask |
1717 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1718 | 0 | op &= UINT64_C(1); |
1719 | 0 | op <<= 34; |
1720 | 0 | Value |= op; |
1721 | | // op: update_pred |
1722 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1723 | 0 | op &= UINT64_C(1); |
1724 | 0 | op <<= 35; |
1725 | 0 | Value |= op; |
1726 | | // op: write |
1727 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
1728 | 0 | op &= UINT64_C(1); |
1729 | 0 | op <<= 36; |
1730 | 0 | Value |= op; |
1731 | | // op: omod |
1732 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
1733 | 0 | op &= UINT64_C(3); |
1734 | 0 | op <<= 37; |
1735 | 0 | Value |= op; |
1736 | 0 | break; |
1737 | 0 | } |
1738 | 0 | case R600::INTERP_XY: |
1739 | 0 | case R600::INTERP_ZW: { |
1740 | | // op: src0 |
1741 | 0 | op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); |
1742 | 0 | Value |= (op & UINT64_C(1536)) << 1; |
1743 | 0 | Value |= (op & UINT64_C(511)); |
1744 | | // op: src0_rel |
1745 | 0 | op = getMachineOpValue(MI, MI.getOperand(9), Fixups, STI); |
1746 | 0 | op &= UINT64_C(1); |
1747 | 0 | op <<= 9; |
1748 | 0 | Value |= op; |
1749 | | // op: src1 |
1750 | 0 | op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI); |
1751 | 0 | Value |= (op & UINT64_C(1536)) << 14; |
1752 | 0 | Value |= (op & UINT64_C(511)) << 13; |
1753 | | // op: src1_rel |
1754 | 0 | op = getMachineOpValue(MI, MI.getOperand(14), Fixups, STI); |
1755 | 0 | op &= UINT64_C(1); |
1756 | 0 | op <<= 22; |
1757 | 0 | Value |= op; |
1758 | | // op: pred_sel |
1759 | 0 | op = getMachineOpValue(MI, MI.getOperand(18), Fixups, STI); |
1760 | 0 | op &= UINT64_C(3); |
1761 | 0 | op <<= 29; |
1762 | 0 | Value |= op; |
1763 | | // op: last |
1764 | 0 | op = getMachineOpValue(MI, MI.getOperand(17), Fixups, STI); |
1765 | 0 | op &= UINT64_C(1); |
1766 | 0 | op <<= 31; |
1767 | 0 | Value |= op; |
1768 | | // op: src0_neg |
1769 | 0 | op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); |
1770 | 0 | op &= UINT64_C(1); |
1771 | 0 | op <<= 12; |
1772 | 0 | Value |= op; |
1773 | | // op: src1_neg |
1774 | 0 | op = getMachineOpValue(MI, MI.getOperand(13), Fixups, STI); |
1775 | 0 | op &= UINT64_C(1); |
1776 | 0 | op <<= 25; |
1777 | 0 | Value |= op; |
1778 | | // op: dst |
1779 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1780 | 0 | Value |= (op & UINT64_C(1536)) << 52; |
1781 | 0 | Value |= (op & UINT64_C(127)) << 53; |
1782 | | // op: dst_rel |
1783 | 0 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
1784 | 0 | op &= UINT64_C(1); |
1785 | 0 | op <<= 60; |
1786 | 0 | Value |= op; |
1787 | | // op: clamp |
1788 | 0 | op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); |
1789 | 0 | op &= UINT64_C(1); |
1790 | 0 | op <<= 63; |
1791 | 0 | Value |= op; |
1792 | | // op: src0_abs |
1793 | 0 | op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); |
1794 | 0 | op &= UINT64_C(1); |
1795 | 0 | op <<= 32; |
1796 | 0 | Value |= op; |
1797 | | // op: src1_abs |
1798 | 0 | op = getMachineOpValue(MI, MI.getOperand(15), Fixups, STI); |
1799 | 0 | op &= UINT64_C(1); |
1800 | 0 | op <<= 33; |
1801 | 0 | Value |= op; |
1802 | | // op: update_exec_mask |
1803 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1804 | 0 | op &= UINT64_C(1); |
1805 | 0 | op <<= 34; |
1806 | 0 | Value |= op; |
1807 | | // op: update_pred |
1808 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1809 | 0 | op &= UINT64_C(1); |
1810 | 0 | op <<= 35; |
1811 | 0 | Value |= op; |
1812 | | // op: write |
1813 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
1814 | 0 | op &= UINT64_C(1); |
1815 | 0 | op <<= 36; |
1816 | 0 | Value |= op; |
1817 | | // op: omod |
1818 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
1819 | 0 | op &= UINT64_C(3); |
1820 | 0 | op <<= 37; |
1821 | 0 | Value |= op; |
1822 | 0 | break; |
1823 | 0 | } |
1824 | 0 | case R600::VTX_READ_8_cm: |
1825 | 0 | case R600::VTX_READ_8_eg: |
1826 | 0 | case R600::VTX_READ_16_cm: |
1827 | 0 | case R600::VTX_READ_16_eg: |
1828 | 0 | case R600::VTX_READ_32_cm: |
1829 | 0 | case R600::VTX_READ_32_eg: |
1830 | 0 | case R600::VTX_READ_64_cm: |
1831 | 0 | case R600::VTX_READ_64_eg: |
1832 | 0 | case R600::VTX_READ_128_cm: |
1833 | 0 | case R600::VTX_READ_128_eg: { |
1834 | | // op: src_gpr |
1835 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1836 | 0 | op &= UINT64_C(127); |
1837 | 0 | op <<= 16; |
1838 | 0 | Value |= op; |
1839 | | // op: buffer_id |
1840 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
1841 | 0 | op &= UINT64_C(255); |
1842 | 0 | op <<= 8; |
1843 | 0 | Value |= op; |
1844 | | // op: dst_gpr |
1845 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1846 | 0 | op &= UINT64_C(127); |
1847 | 0 | op <<= 32; |
1848 | 0 | Value |= op; |
1849 | 0 | break; |
1850 | 0 | } |
1851 | 0 | default: |
1852 | 0 | std::string msg; |
1853 | 0 | raw_string_ostream Msg(msg); |
1854 | 0 | Msg << "Not supported instr: " << MI; |
1855 | 0 | report_fatal_error(Msg.str().c_str()); |
1856 | 0 | } |
1857 | 0 | return Value; |
1858 | 0 | } |
1859 | | |
1860 | | #ifdef GET_OPERAND_BIT_OFFSET |
1861 | | #undef GET_OPERAND_BIT_OFFSET |
1862 | | |
1863 | | uint32_t R600MCCodeEmitter::getOperandBitOffset(const MCInst &MI, |
1864 | | unsigned OpNum, |
1865 | | const MCSubtargetInfo &STI) const { |
1866 | | switch (MI.getOpcode()) { |
1867 | | case R600::CF_CALL_FS_EG: |
1868 | | case R600::CF_CALL_FS_R600: |
1869 | | case R600::CF_END_CM: |
1870 | | case R600::CF_END_EG: |
1871 | | case R600::CF_END_R600: |
1872 | | case R600::GROUP_BARRIER: |
1873 | | case R600::INTERP_PAIR_XY: |
1874 | | case R600::INTERP_PAIR_ZW: |
1875 | | case R600::INTERP_VEC_LOAD: |
1876 | | case R600::PAD: { |
1877 | | break; |
1878 | | } |
1879 | | case R600::CF_TC_R600: |
1880 | | case R600::CF_VC_R600: { |
1881 | | switch (OpNum) { |
1882 | | case 0: |
1883 | | // op: ADDR |
1884 | | return 0; |
1885 | | case 1: |
1886 | | // op: CNT |
1887 | | return 42; |
1888 | | } |
1889 | | break; |
1890 | | } |
1891 | | case R600::CF_TC_EG: |
1892 | | case R600::CF_VC_EG: { |
1893 | | switch (OpNum) { |
1894 | | case 0: |
1895 | | // op: ADDR |
1896 | | return 0; |
1897 | | case 1: |
1898 | | // op: COUNT |
1899 | | return 42; |
1900 | | } |
1901 | | break; |
1902 | | } |
1903 | | case R600::CF_ALU: |
1904 | | case R600::CF_ALU_BREAK: |
1905 | | case R600::CF_ALU_CONTINUE: |
1906 | | case R600::CF_ALU_ELSE_AFTER: |
1907 | | case R600::CF_ALU_POP_AFTER: |
1908 | | case R600::CF_ALU_PUSH_BEFORE: { |
1909 | | switch (OpNum) { |
1910 | | case 0: |
1911 | | // op: ADDR |
1912 | | return 0; |
1913 | | case 1: |
1914 | | // op: KCACHE_BANK0 |
1915 | | return 22; |
1916 | | case 2: |
1917 | | // op: KCACHE_BANK1 |
1918 | | return 26; |
1919 | | case 3: |
1920 | | // op: KCACHE_MODE0 |
1921 | | return 30; |
1922 | | case 4: |
1923 | | // op: KCACHE_MODE1 |
1924 | | return 32; |
1925 | | case 5: |
1926 | | // op: KCACHE_ADDR0 |
1927 | | return 34; |
1928 | | case 6: |
1929 | | // op: KCACHE_ADDR1 |
1930 | | return 42; |
1931 | | case 7: |
1932 | | // op: COUNT |
1933 | | return 50; |
1934 | | } |
1935 | | break; |
1936 | | } |
1937 | | case R600::CF_ELSE_EG: |
1938 | | case R600::CF_ELSE_R600: |
1939 | | case R600::CF_JUMP_EG: |
1940 | | case R600::CF_JUMP_R600: |
1941 | | case R600::CF_PUSH_EG: |
1942 | | case R600::POP_EG: |
1943 | | case R600::POP_R600: { |
1944 | | switch (OpNum) { |
1945 | | case 0: |
1946 | | // op: ADDR |
1947 | | return 0; |
1948 | | case 1: |
1949 | | // op: POP_COUNT |
1950 | | return 32; |
1951 | | } |
1952 | | break; |
1953 | | } |
1954 | | case R600::CF_CONTINUE_EG: |
1955 | | case R600::CF_CONTINUE_R600: |
1956 | | case R600::CF_PUSH_ELSE_R600: |
1957 | | case R600::END_LOOP_EG: |
1958 | | case R600::END_LOOP_R600: |
1959 | | case R600::LOOP_BREAK_EG: |
1960 | | case R600::LOOP_BREAK_R600: |
1961 | | case R600::WHILE_LOOP_EG: |
1962 | | case R600::WHILE_LOOP_R600: { |
1963 | | switch (OpNum) { |
1964 | | case 0: |
1965 | | // op: ADDR |
1966 | | return 0; |
1967 | | } |
1968 | | break; |
1969 | | } |
1970 | | case R600::ALU_CLAUSE: |
1971 | | case R600::FETCH_CLAUSE: { |
1972 | | switch (OpNum) { |
1973 | | case 0: |
1974 | | // op: addr |
1975 | | return 0; |
1976 | | } |
1977 | | break; |
1978 | | } |
1979 | | case R600::TEX_VTX_CONSTBUF: |
1980 | | case R600::TEX_VTX_TEXBUF: { |
1981 | | switch (OpNum) { |
1982 | | case 0: |
1983 | | // op: dst_gpr |
1984 | | return 32; |
1985 | | case 1: |
1986 | | // op: src_gpr |
1987 | | return 16; |
1988 | | case 3: |
1989 | | // op: buffer_id |
1990 | | return 8; |
1991 | | } |
1992 | | break; |
1993 | | } |
1994 | | case R600::LITERALS: { |
1995 | | switch (OpNum) { |
1996 | | case 0: |
1997 | | // op: literal1 |
1998 | | return 0; |
1999 | | case 1: |
2000 | | // op: literal2 |
2001 | | return 32; |
2002 | | } |
2003 | | break; |
2004 | | } |
2005 | | case R600::RAT_WRITE_CACHELESS_32_eg: |
2006 | | case R600::RAT_WRITE_CACHELESS_64_eg: |
2007 | | case R600::RAT_WRITE_CACHELESS_128_eg: { |
2008 | | switch (OpNum) { |
2009 | | case 0: |
2010 | | // op: rw_gpr |
2011 | | return 15; |
2012 | | case 1: |
2013 | | // op: index_gpr |
2014 | | return 23; |
2015 | | case 2: |
2016 | | // op: eop |
2017 | | return 53; |
2018 | | } |
2019 | | break; |
2020 | | } |
2021 | | case R600::RAT_MSKOR: |
2022 | | case R600::RAT_STORE_DWORD32: |
2023 | | case R600::RAT_STORE_DWORD64: |
2024 | | case R600::RAT_STORE_DWORD128: { |
2025 | | switch (OpNum) { |
2026 | | case 0: |
2027 | | // op: rw_gpr |
2028 | | return 15; |
2029 | | case 1: |
2030 | | // op: index_gpr |
2031 | | return 23; |
2032 | | } |
2033 | | break; |
2034 | | } |
2035 | | case R600::LDS_CMPST: { |
2036 | | switch (OpNum) { |
2037 | | case 0: |
2038 | | // op: src0 |
2039 | | return 0; |
2040 | | case 1: |
2041 | | // op: src0_rel |
2042 | | return 9; |
2043 | | case 3: |
2044 | | // op: src1 |
2045 | | return 13; |
2046 | | case 4: |
2047 | | // op: src1_rel |
2048 | | return 22; |
2049 | | case 10: |
2050 | | // op: pred_sel |
2051 | | return 29; |
2052 | | case 9: |
2053 | | // op: last |
2054 | | return 31; |
2055 | | case 6: |
2056 | | // op: src2 |
2057 | | return 32; |
2058 | | case 7: |
2059 | | // op: src2_rel |
2060 | | return 41; |
2061 | | case 11: |
2062 | | // op: bank_swizzle |
2063 | | return 50; |
2064 | | } |
2065 | | break; |
2066 | | } |
2067 | | case R600::LDS_ADD: |
2068 | | case R600::LDS_AND: |
2069 | | case R600::LDS_BYTE_WRITE: |
2070 | | case R600::LDS_MAX_INT: |
2071 | | case R600::LDS_MAX_UINT: |
2072 | | case R600::LDS_MIN_INT: |
2073 | | case R600::LDS_MIN_UINT: |
2074 | | case R600::LDS_OR: |
2075 | | case R600::LDS_SHORT_WRITE: |
2076 | | case R600::LDS_SUB: |
2077 | | case R600::LDS_WRITE: |
2078 | | case R600::LDS_WRXCHG: |
2079 | | case R600::LDS_XOR: { |
2080 | | switch (OpNum) { |
2081 | | case 0: |
2082 | | // op: src0 |
2083 | | return 0; |
2084 | | case 1: |
2085 | | // op: src0_rel |
2086 | | return 9; |
2087 | | case 3: |
2088 | | // op: src1 |
2089 | | return 13; |
2090 | | case 4: |
2091 | | // op: src1_rel |
2092 | | return 22; |
2093 | | case 7: |
2094 | | // op: pred_sel |
2095 | | return 29; |
2096 | | case 6: |
2097 | | // op: last |
2098 | | return 31; |
2099 | | case 8: |
2100 | | // op: bank_swizzle |
2101 | | return 50; |
2102 | | } |
2103 | | break; |
2104 | | } |
2105 | | case R600::TEX_GET_GRADIENTS_H: |
2106 | | case R600::TEX_GET_GRADIENTS_V: |
2107 | | case R600::TEX_GET_TEXTURE_RESINFO: |
2108 | | case R600::TEX_LD: |
2109 | | case R600::TEX_LDPTR: |
2110 | | case R600::TEX_SAMPLE: |
2111 | | case R600::TEX_SAMPLE_C: |
2112 | | case R600::TEX_SAMPLE_C_G: |
2113 | | case R600::TEX_SAMPLE_C_L: |
2114 | | case R600::TEX_SAMPLE_C_LB: |
2115 | | case R600::TEX_SAMPLE_G: |
2116 | | case R600::TEX_SAMPLE_L: |
2117 | | case R600::TEX_SAMPLE_LB: |
2118 | | case R600::TEX_SET_GRADIENTS_H: |
2119 | | case R600::TEX_SET_GRADIENTS_V: { |
2120 | | switch (OpNum) { |
2121 | | case 13: |
2122 | | // op: RESOURCE_ID |
2123 | | return 8; |
2124 | | case 1: |
2125 | | // op: SRC_GPR |
2126 | | return 16; |
2127 | | case 0: |
2128 | | // op: DST_GPR |
2129 | | return 32; |
2130 | | case 9: |
2131 | | // op: DST_SEL_X |
2132 | | return 41; |
2133 | | case 10: |
2134 | | // op: DST_SEL_Y |
2135 | | return 44; |
2136 | | case 11: |
2137 | | // op: DST_SEL_Z |
2138 | | return 47; |
2139 | | case 12: |
2140 | | // op: DST_SEL_W |
2141 | | return 50; |
2142 | | case 15: |
2143 | | // op: COORD_TYPE_X |
2144 | | return 60; |
2145 | | case 16: |
2146 | | // op: COORD_TYPE_Y |
2147 | | return 61; |
2148 | | case 17: |
2149 | | // op: COORD_TYPE_Z |
2150 | | return 62; |
2151 | | case 18: |
2152 | | // op: COORD_TYPE_W |
2153 | | return 63; |
2154 | | } |
2155 | | break; |
2156 | | } |
2157 | | case R600::RAT_ATOMIC_ADD_NORET: |
2158 | | case R600::RAT_ATOMIC_ADD_RTN: |
2159 | | case R600::RAT_ATOMIC_AND_NORET: |
2160 | | case R600::RAT_ATOMIC_AND_RTN: |
2161 | | case R600::RAT_ATOMIC_CMPXCHG_INT_NORET: |
2162 | | case R600::RAT_ATOMIC_CMPXCHG_INT_RTN: |
2163 | | case R600::RAT_ATOMIC_DEC_UINT_NORET: |
2164 | | case R600::RAT_ATOMIC_DEC_UINT_RTN: |
2165 | | case R600::RAT_ATOMIC_INC_UINT_NORET: |
2166 | | case R600::RAT_ATOMIC_INC_UINT_RTN: |
2167 | | case R600::RAT_ATOMIC_MAX_INT_NORET: |
2168 | | case R600::RAT_ATOMIC_MAX_INT_RTN: |
2169 | | case R600::RAT_ATOMIC_MAX_UINT_NORET: |
2170 | | case R600::RAT_ATOMIC_MAX_UINT_RTN: |
2171 | | case R600::RAT_ATOMIC_MIN_INT_NORET: |
2172 | | case R600::RAT_ATOMIC_MIN_INT_RTN: |
2173 | | case R600::RAT_ATOMIC_MIN_UINT_NORET: |
2174 | | case R600::RAT_ATOMIC_MIN_UINT_RTN: |
2175 | | case R600::RAT_ATOMIC_OR_NORET: |
2176 | | case R600::RAT_ATOMIC_OR_RTN: |
2177 | | case R600::RAT_ATOMIC_RSUB_NORET: |
2178 | | case R600::RAT_ATOMIC_RSUB_RTN: |
2179 | | case R600::RAT_ATOMIC_SUB_NORET: |
2180 | | case R600::RAT_ATOMIC_SUB_RTN: |
2181 | | case R600::RAT_ATOMIC_XCHG_INT_NORET: |
2182 | | case R600::RAT_ATOMIC_XCHG_INT_RTN: |
2183 | | case R600::RAT_ATOMIC_XOR_NORET: |
2184 | | case R600::RAT_ATOMIC_XOR_RTN: { |
2185 | | switch (OpNum) { |
2186 | | case 1: |
2187 | | // op: rw_gpr |
2188 | | return 15; |
2189 | | case 2: |
2190 | | // op: index_gpr |
2191 | | return 23; |
2192 | | } |
2193 | | break; |
2194 | | } |
2195 | | case R600::LDS_CMPST_RET: { |
2196 | | switch (OpNum) { |
2197 | | case 1: |
2198 | | // op: src0 |
2199 | | return 0; |
2200 | | case 2: |
2201 | | // op: src0_rel |
2202 | | return 9; |
2203 | | case 4: |
2204 | | // op: src1 |
2205 | | return 13; |
2206 | | case 5: |
2207 | | // op: src1_rel |
2208 | | return 22; |
2209 | | case 11: |
2210 | | // op: pred_sel |
2211 | | return 29; |
2212 | | case 10: |
2213 | | // op: last |
2214 | | return 31; |
2215 | | case 7: |
2216 | | // op: src2 |
2217 | | return 32; |
2218 | | case 8: |
2219 | | // op: src2_rel |
2220 | | return 41; |
2221 | | case 12: |
2222 | | // op: bank_swizzle |
2223 | | return 50; |
2224 | | } |
2225 | | break; |
2226 | | } |
2227 | | case R600::LDS_ADD_RET: |
2228 | | case R600::LDS_AND_RET: |
2229 | | case R600::LDS_MAX_INT_RET: |
2230 | | case R600::LDS_MAX_UINT_RET: |
2231 | | case R600::LDS_MIN_INT_RET: |
2232 | | case R600::LDS_MIN_UINT_RET: |
2233 | | case R600::LDS_OR_RET: |
2234 | | case R600::LDS_SUB_RET: |
2235 | | case R600::LDS_WRXCHG_RET: |
2236 | | case R600::LDS_XOR_RET: { |
2237 | | switch (OpNum) { |
2238 | | case 1: |
2239 | | // op: src0 |
2240 | | return 0; |
2241 | | case 2: |
2242 | | // op: src0_rel |
2243 | | return 9; |
2244 | | case 4: |
2245 | | // op: src1 |
2246 | | return 13; |
2247 | | case 5: |
2248 | | // op: src1_rel |
2249 | | return 22; |
2250 | | case 8: |
2251 | | // op: pred_sel |
2252 | | return 29; |
2253 | | case 7: |
2254 | | // op: last |
2255 | | return 31; |
2256 | | case 9: |
2257 | | // op: bank_swizzle |
2258 | | return 50; |
2259 | | } |
2260 | | break; |
2261 | | } |
2262 | | case R600::LDS_BYTE_READ_RET: |
2263 | | case R600::LDS_READ_RET: |
2264 | | case R600::LDS_SHORT_READ_RET: |
2265 | | case R600::LDS_UBYTE_READ_RET: |
2266 | | case R600::LDS_USHORT_READ_RET: { |
2267 | | switch (OpNum) { |
2268 | | case 1: |
2269 | | // op: src0 |
2270 | | return 0; |
2271 | | case 2: |
2272 | | // op: src0_rel |
2273 | | return 9; |
2274 | | case 5: |
2275 | | // op: pred_sel |
2276 | | return 29; |
2277 | | case 4: |
2278 | | // op: last |
2279 | | return 31; |
2280 | | case 6: |
2281 | | // op: bank_swizzle |
2282 | | return 50; |
2283 | | } |
2284 | | break; |
2285 | | } |
2286 | | case R600::VTX_READ_8_cm: |
2287 | | case R600::VTX_READ_8_eg: |
2288 | | case R600::VTX_READ_16_cm: |
2289 | | case R600::VTX_READ_16_eg: |
2290 | | case R600::VTX_READ_32_cm: |
2291 | | case R600::VTX_READ_32_eg: |
2292 | | case R600::VTX_READ_64_cm: |
2293 | | case R600::VTX_READ_64_eg: |
2294 | | case R600::VTX_READ_128_cm: |
2295 | | case R600::VTX_READ_128_eg: { |
2296 | | switch (OpNum) { |
2297 | | case 1: |
2298 | | // op: src_gpr |
2299 | | return 16; |
2300 | | case 3: |
2301 | | // op: buffer_id |
2302 | | return 8; |
2303 | | case 0: |
2304 | | // op: dst_gpr |
2305 | | return 32; |
2306 | | } |
2307 | | break; |
2308 | | } |
2309 | | case R600::EG_ExportBuf: { |
2310 | | switch (OpNum) { |
2311 | | case 2: |
2312 | | // op: arraybase |
2313 | | return 0; |
2314 | | case 1: |
2315 | | // op: type |
2316 | | return 13; |
2317 | | case 0: |
2318 | | // op: gpr |
2319 | | return 15; |
2320 | | case 3: |
2321 | | // op: arraySize |
2322 | | return 32; |
2323 | | case 4: |
2324 | | // op: compMask |
2325 | | return 44; |
2326 | | case 6: |
2327 | | // op: eop |
2328 | | return 53; |
2329 | | case 5: |
2330 | | // op: inst |
2331 | | return 54; |
2332 | | } |
2333 | | break; |
2334 | | } |
2335 | | case R600::R600_ExportBuf: { |
2336 | | switch (OpNum) { |
2337 | | case 2: |
2338 | | // op: arraybase |
2339 | | return 0; |
2340 | | case 1: |
2341 | | // op: type |
2342 | | return 13; |
2343 | | case 0: |
2344 | | // op: gpr |
2345 | | return 15; |
2346 | | case 3: |
2347 | | // op: arraySize |
2348 | | return 32; |
2349 | | case 4: |
2350 | | // op: compMask |
2351 | | return 44; |
2352 | | case 6: |
2353 | | // op: eop |
2354 | | return 53; |
2355 | | case 5: |
2356 | | // op: inst |
2357 | | return 55; |
2358 | | } |
2359 | | break; |
2360 | | } |
2361 | | case R600::EG_ExportSwz: { |
2362 | | switch (OpNum) { |
2363 | | case 2: |
2364 | | // op: arraybase |
2365 | | return 0; |
2366 | | case 1: |
2367 | | // op: type |
2368 | | return 13; |
2369 | | case 0: |
2370 | | // op: gpr |
2371 | | return 15; |
2372 | | case 3: |
2373 | | // op: sw_x |
2374 | | return 32; |
2375 | | case 4: |
2376 | | // op: sw_y |
2377 | | return 35; |
2378 | | case 5: |
2379 | | // op: sw_z |
2380 | | return 38; |
2381 | | case 6: |
2382 | | // op: sw_w |
2383 | | return 41; |
2384 | | case 8: |
2385 | | // op: eop |
2386 | | return 53; |
2387 | | case 7: |
2388 | | // op: inst |
2389 | | return 54; |
2390 | | } |
2391 | | break; |
2392 | | } |
2393 | | case R600::R600_ExportSwz: { |
2394 | | switch (OpNum) { |
2395 | | case 2: |
2396 | | // op: arraybase |
2397 | | return 0; |
2398 | | case 1: |
2399 | | // op: type |
2400 | | return 13; |
2401 | | case 0: |
2402 | | // op: gpr |
2403 | | return 15; |
2404 | | case 3: |
2405 | | // op: sw_x |
2406 | | return 32; |
2407 | | case 4: |
2408 | | // op: sw_y |
2409 | | return 35; |
2410 | | case 5: |
2411 | | // op: sw_z |
2412 | | return 38; |
2413 | | case 6: |
2414 | | // op: sw_w |
2415 | | return 41; |
2416 | | case 8: |
2417 | | // op: eop |
2418 | | return 53; |
2419 | | case 7: |
2420 | | // op: inst |
2421 | | return 55; |
2422 | | } |
2423 | | break; |
2424 | | } |
2425 | | case R600::RAT_STORE_TYPED_eg: { |
2426 | | switch (OpNum) { |
2427 | | case 2: |
2428 | | // op: rat_id |
2429 | | return 0; |
2430 | | case 0: |
2431 | | // op: rw_gpr |
2432 | | return 15; |
2433 | | case 1: |
2434 | | // op: index_gpr |
2435 | | return 23; |
2436 | | case 3: |
2437 | | // op: eop |
2438 | | return 53; |
2439 | | } |
2440 | | break; |
2441 | | } |
2442 | | case R600::RAT_STORE_TYPED_cm: { |
2443 | | switch (OpNum) { |
2444 | | case 2: |
2445 | | // op: rat_id |
2446 | | return 0; |
2447 | | case 0: |
2448 | | // op: rw_gpr |
2449 | | return 15; |
2450 | | case 1: |
2451 | | // op: index_gpr |
2452 | | return 23; |
2453 | | } |
2454 | | break; |
2455 | | } |
2456 | | case R600::BFE_INT_eg: |
2457 | | case R600::BFE_UINT_eg: |
2458 | | case R600::BFI_INT_eg: |
2459 | | case R600::BIT_ALIGN_INT_eg: |
2460 | | case R600::CNDE_INT: |
2461 | | case R600::CNDE_eg: |
2462 | | case R600::CNDE_r600: |
2463 | | case R600::CNDGE_INT: |
2464 | | case R600::CNDGE_eg: |
2465 | | case R600::CNDGE_r600: |
2466 | | case R600::CNDGT_INT: |
2467 | | case R600::CNDGT_eg: |
2468 | | case R600::CNDGT_r600: |
2469 | | case R600::FMA_eg: |
2470 | | case R600::MULADD_IEEE_eg: |
2471 | | case R600::MULADD_IEEE_r600: |
2472 | | case R600::MULADD_INT24_cm: |
2473 | | case R600::MULADD_UINT24_eg: |
2474 | | case R600::MULADD_eg: |
2475 | | case R600::MULADD_r600: |
2476 | | case R600::MUL_LIT_eg: |
2477 | | case R600::MUL_LIT_r600: { |
2478 | | switch (OpNum) { |
2479 | | case 3: |
2480 | | // op: src0 |
2481 | | return 0; |
2482 | | case 5: |
2483 | | // op: src0_rel |
2484 | | return 9; |
2485 | | case 7: |
2486 | | // op: src1 |
2487 | | return 13; |
2488 | | case 9: |
2489 | | // op: src1_rel |
2490 | | return 22; |
2491 | | case 16: |
2492 | | // op: pred_sel |
2493 | | return 29; |
2494 | | case 15: |
2495 | | // op: last |
2496 | | return 31; |
2497 | | case 4: |
2498 | | // op: src0_neg |
2499 | | return 12; |
2500 | | case 8: |
2501 | | // op: src1_neg |
2502 | | return 25; |
2503 | | case 0: |
2504 | | // op: dst |
2505 | | return 53; |
2506 | | case 18: |
2507 | | // op: bank_swizzle |
2508 | | return 50; |
2509 | | case 1: |
2510 | | // op: dst_rel |
2511 | | return 60; |
2512 | | case 2: |
2513 | | // op: clamp |
2514 | | return 63; |
2515 | | case 11: |
2516 | | // op: src2 |
2517 | | return 32; |
2518 | | case 13: |
2519 | | // op: src2_rel |
2520 | | return 41; |
2521 | | case 12: |
2522 | | // op: src2_neg |
2523 | | return 44; |
2524 | | } |
2525 | | break; |
2526 | | } |
2527 | | case R600::BCNT_INT: |
2528 | | case R600::CEIL: |
2529 | | case R600::COS_cm: |
2530 | | case R600::COS_eg: |
2531 | | case R600::COS_r600: |
2532 | | case R600::COS_r700: |
2533 | | case R600::EXP_IEEE_cm: |
2534 | | case R600::EXP_IEEE_eg: |
2535 | | case R600::EXP_IEEE_r600: |
2536 | | case R600::FFBH_UINT: |
2537 | | case R600::FFBL_INT: |
2538 | | case R600::FLOOR: |
2539 | | case R600::FLT16_TO_FLT32: |
2540 | | case R600::FLT32_TO_FLT16: |
2541 | | case R600::FLT_TO_INT_eg: |
2542 | | case R600::FLT_TO_INT_r600: |
2543 | | case R600::FLT_TO_UINT_eg: |
2544 | | case R600::FLT_TO_UINT_r600: |
2545 | | case R600::FRACT: |
2546 | | case R600::INTERP_LOAD_P0: |
2547 | | case R600::INT_TO_FLT_eg: |
2548 | | case R600::INT_TO_FLT_r600: |
2549 | | case R600::LOG_CLAMPED_eg: |
2550 | | case R600::LOG_CLAMPED_r600: |
2551 | | case R600::LOG_IEEE_cm: |
2552 | | case R600::LOG_IEEE_eg: |
2553 | | case R600::LOG_IEEE_r600: |
2554 | | case R600::MOV: |
2555 | | case R600::MOVA_INT_eg: |
2556 | | case R600::NOT_INT: |
2557 | | case R600::RECIPSQRT_CLAMPED_cm: |
2558 | | case R600::RECIPSQRT_CLAMPED_eg: |
2559 | | case R600::RECIPSQRT_CLAMPED_r600: |
2560 | | case R600::RECIPSQRT_IEEE_cm: |
2561 | | case R600::RECIPSQRT_IEEE_eg: |
2562 | | case R600::RECIPSQRT_IEEE_r600: |
2563 | | case R600::RECIP_CLAMPED_cm: |
2564 | | case R600::RECIP_CLAMPED_eg: |
2565 | | case R600::RECIP_CLAMPED_r600: |
2566 | | case R600::RECIP_IEEE_cm: |
2567 | | case R600::RECIP_IEEE_eg: |
2568 | | case R600::RECIP_IEEE_r600: |
2569 | | case R600::RECIP_UINT_eg: |
2570 | | case R600::RECIP_UINT_r600: |
2571 | | case R600::RNDNE: |
2572 | | case R600::SIN_cm: |
2573 | | case R600::SIN_eg: |
2574 | | case R600::SIN_r600: |
2575 | | case R600::SIN_r700: |
2576 | | case R600::TRUNC: |
2577 | | case R600::UINT_TO_FLT_eg: |
2578 | | case R600::UINT_TO_FLT_r600: { |
2579 | | switch (OpNum) { |
2580 | | case 5: |
2581 | | // op: src0 |
2582 | | return 0; |
2583 | | case 7: |
2584 | | // op: src0_rel |
2585 | | return 9; |
2586 | | case 11: |
2587 | | // op: pred_sel |
2588 | | return 29; |
2589 | | case 10: |
2590 | | // op: last |
2591 | | return 31; |
2592 | | case 6: |
2593 | | // op: src0_neg |
2594 | | return 12; |
2595 | | case 0: |
2596 | | // op: dst |
2597 | | return 53; |
2598 | | case 13: |
2599 | | // op: bank_swizzle |
2600 | | return 50; |
2601 | | case 3: |
2602 | | // op: dst_rel |
2603 | | return 60; |
2604 | | case 4: |
2605 | | // op: clamp |
2606 | | return 63; |
2607 | | case 8: |
2608 | | // op: src0_abs |
2609 | | return 32; |
2610 | | case 1: |
2611 | | // op: write |
2612 | | return 36; |
2613 | | case 2: |
2614 | | // op: omod |
2615 | | return 37; |
2616 | | } |
2617 | | break; |
2618 | | } |
2619 | | case R600::ADD: |
2620 | | case R600::ADDC_UINT: |
2621 | | case R600::ADD_INT: |
2622 | | case R600::AND_INT: |
2623 | | case R600::ASHR_eg: |
2624 | | case R600::ASHR_r600: |
2625 | | case R600::BFM_INT_eg: |
2626 | | case R600::CUBE_eg_real: |
2627 | | case R600::CUBE_r600_real: |
2628 | | case R600::DOT4_eg: |
2629 | | case R600::DOT4_r600: |
2630 | | case R600::KILLGT: |
2631 | | case R600::LSHL_eg: |
2632 | | case R600::LSHL_r600: |
2633 | | case R600::LSHR_eg: |
2634 | | case R600::LSHR_r600: |
2635 | | case R600::MAX: |
2636 | | case R600::MAX_DX10: |
2637 | | case R600::MAX_INT: |
2638 | | case R600::MAX_UINT: |
2639 | | case R600::MIN: |
2640 | | case R600::MIN_DX10: |
2641 | | case R600::MIN_INT: |
2642 | | case R600::MIN_UINT: |
2643 | | case R600::MUL: |
2644 | | case R600::MULHI_INT_cm: |
2645 | | case R600::MULHI_INT_cm24: |
2646 | | case R600::MULHI_INT_eg: |
2647 | | case R600::MULHI_INT_r600: |
2648 | | case R600::MULHI_UINT24_eg: |
2649 | | case R600::MULHI_UINT_cm: |
2650 | | case R600::MULHI_UINT_cm24: |
2651 | | case R600::MULHI_UINT_eg: |
2652 | | case R600::MULHI_UINT_r600: |
2653 | | case R600::MULLO_INT_cm: |
2654 | | case R600::MULLO_INT_eg: |
2655 | | case R600::MULLO_INT_r600: |
2656 | | case R600::MULLO_UINT_cm: |
2657 | | case R600::MULLO_UINT_eg: |
2658 | | case R600::MULLO_UINT_r600: |
2659 | | case R600::MUL_IEEE: |
2660 | | case R600::MUL_INT24_cm: |
2661 | | case R600::MUL_UINT24_eg: |
2662 | | case R600::OR_INT: |
2663 | | case R600::PRED_SETE: |
2664 | | case R600::PRED_SETE_INT: |
2665 | | case R600::PRED_SETGE: |
2666 | | case R600::PRED_SETGE_INT: |
2667 | | case R600::PRED_SETGT: |
2668 | | case R600::PRED_SETGT_INT: |
2669 | | case R600::PRED_SETNE: |
2670 | | case R600::PRED_SETNE_INT: |
2671 | | case R600::SETE: |
2672 | | case R600::SETE_DX10: |
2673 | | case R600::SETE_INT: |
2674 | | case R600::SETGE_DX10: |
2675 | | case R600::SETGE_INT: |
2676 | | case R600::SETGE_UINT: |
2677 | | case R600::SETGT_DX10: |
2678 | | case R600::SETGT_INT: |
2679 | | case R600::SETGT_UINT: |
2680 | | case R600::SETNE_DX10: |
2681 | | case R600::SETNE_INT: |
2682 | | case R600::SGE: |
2683 | | case R600::SGT: |
2684 | | case R600::SNE: |
2685 | | case R600::SUBB_UINT: |
2686 | | case R600::SUB_INT: |
2687 | | case R600::XOR_INT: { |
2688 | | switch (OpNum) { |
2689 | | case 7: |
2690 | | // op: src0 |
2691 | | return 0; |
2692 | | case 9: |
2693 | | // op: src0_rel |
2694 | | return 9; |
2695 | | case 12: |
2696 | | // op: src1 |
2697 | | return 13; |
2698 | | case 14: |
2699 | | // op: src1_rel |
2700 | | return 22; |
2701 | | case 18: |
2702 | | // op: pred_sel |
2703 | | return 29; |
2704 | | case 17: |
2705 | | // op: last |
2706 | | return 31; |
2707 | | case 8: |
2708 | | // op: src0_neg |
2709 | | return 12; |
2710 | | case 13: |
2711 | | // op: src1_neg |
2712 | | return 25; |
2713 | | case 0: |
2714 | | // op: dst |
2715 | | return 53; |
2716 | | case 20: |
2717 | | // op: bank_swizzle |
2718 | | return 50; |
2719 | | case 5: |
2720 | | // op: dst_rel |
2721 | | return 60; |
2722 | | case 6: |
2723 | | // op: clamp |
2724 | | return 63; |
2725 | | case 10: |
2726 | | // op: src0_abs |
2727 | | return 32; |
2728 | | case 15: |
2729 | | // op: src1_abs |
2730 | | return 33; |
2731 | | case 1: |
2732 | | // op: update_exec_mask |
2733 | | return 34; |
2734 | | case 2: |
2735 | | // op: update_pred |
2736 | | return 35; |
2737 | | case 3: |
2738 | | // op: write |
2739 | | return 36; |
2740 | | case 4: |
2741 | | // op: omod |
2742 | | return 37; |
2743 | | } |
2744 | | break; |
2745 | | } |
2746 | | case R600::INTERP_XY: |
2747 | | case R600::INTERP_ZW: { |
2748 | | switch (OpNum) { |
2749 | | case 7: |
2750 | | // op: src0 |
2751 | | return 0; |
2752 | | case 9: |
2753 | | // op: src0_rel |
2754 | | return 9; |
2755 | | case 12: |
2756 | | // op: src1 |
2757 | | return 13; |
2758 | | case 14: |
2759 | | // op: src1_rel |
2760 | | return 22; |
2761 | | case 18: |
2762 | | // op: pred_sel |
2763 | | return 29; |
2764 | | case 17: |
2765 | | // op: last |
2766 | | return 31; |
2767 | | case 8: |
2768 | | // op: src0_neg |
2769 | | return 12; |
2770 | | case 13: |
2771 | | // op: src1_neg |
2772 | | return 25; |
2773 | | case 0: |
2774 | | // op: dst |
2775 | | return 53; |
2776 | | case 5: |
2777 | | // op: dst_rel |
2778 | | return 60; |
2779 | | case 6: |
2780 | | // op: clamp |
2781 | | return 63; |
2782 | | case 10: |
2783 | | // op: src0_abs |
2784 | | return 32; |
2785 | | case 15: |
2786 | | // op: src1_abs |
2787 | | return 33; |
2788 | | case 1: |
2789 | | // op: update_exec_mask |
2790 | | return 34; |
2791 | | case 2: |
2792 | | // op: update_pred |
2793 | | return 35; |
2794 | | case 3: |
2795 | | // op: write |
2796 | | return 36; |
2797 | | case 4: |
2798 | | // op: omod |
2799 | | return 37; |
2800 | | } |
2801 | | break; |
2802 | | } |
2803 | | } |
2804 | | std::string msg; |
2805 | | raw_string_ostream Msg(msg); |
2806 | | Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]"; |
2807 | | report_fatal_error(Msg.str().c_str()); |
2808 | | } |
2809 | | |
2810 | | #endif // GET_OPERAND_BIT_OFFSET |
2811 | | |