/src/build/lib/Target/AMDGPU/R600GenRegisterInfo.inc
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1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Target Register Enum Values *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | |
10 | | #ifdef GET_REGINFO_ENUM |
11 | | #undef GET_REGINFO_ENUM |
12 | | |
13 | | namespace llvm { |
14 | | |
15 | | class MCRegisterClass; |
16 | | extern const MCRegisterClass R600MCRegisterClasses[]; |
17 | | |
18 | | namespace R600 { |
19 | | enum { |
20 | | NoRegister, |
21 | | ALU_CONST = 1, |
22 | | ALU_LITERAL_W = 2, |
23 | | ALU_LITERAL_X = 3, |
24 | | ALU_LITERAL_Y = 4, |
25 | | ALU_LITERAL_Z = 5, |
26 | | ALU_PARAM = 6, |
27 | | AR_X = 7, |
28 | | HALF = 8, |
29 | | INDIRECT_BASE_ADDR = 9, |
30 | | LDS_DIRECT_A = 10, |
31 | | LDS_DIRECT_B = 11, |
32 | | NEG_HALF = 12, |
33 | | NEG_ONE = 13, |
34 | | ONE = 14, |
35 | | ONE_INT = 15, |
36 | | OQA = 16, |
37 | | OQAP = 17, |
38 | | OQB = 18, |
39 | | OQBP = 19, |
40 | | PREDICATE_BIT = 20, |
41 | | PRED_SEL_OFF = 21, |
42 | | PRED_SEL_ONE = 22, |
43 | | PRED_SEL_ZERO = 23, |
44 | | PS = 24, |
45 | | PV_W = 25, |
46 | | PV_X = 26, |
47 | | PV_Y = 27, |
48 | | PV_Z = 28, |
49 | | ZERO = 29, |
50 | | ArrayBase448 = 30, |
51 | | ArrayBase449 = 31, |
52 | | ArrayBase450 = 32, |
53 | | ArrayBase451 = 33, |
54 | | ArrayBase452 = 34, |
55 | | ArrayBase453 = 35, |
56 | | ArrayBase454 = 36, |
57 | | ArrayBase455 = 37, |
58 | | ArrayBase456 = 38, |
59 | | ArrayBase457 = 39, |
60 | | ArrayBase458 = 40, |
61 | | ArrayBase459 = 41, |
62 | | ArrayBase460 = 42, |
63 | | ArrayBase461 = 43, |
64 | | ArrayBase462 = 44, |
65 | | ArrayBase463 = 45, |
66 | | ArrayBase464 = 46, |
67 | | ArrayBase465 = 47, |
68 | | ArrayBase466 = 48, |
69 | | ArrayBase467 = 49, |
70 | | ArrayBase468 = 50, |
71 | | ArrayBase469 = 51, |
72 | | ArrayBase470 = 52, |
73 | | ArrayBase471 = 53, |
74 | | ArrayBase472 = 54, |
75 | | ArrayBase473 = 55, |
76 | | ArrayBase474 = 56, |
77 | | ArrayBase475 = 57, |
78 | | ArrayBase476 = 58, |
79 | | ArrayBase477 = 59, |
80 | | ArrayBase478 = 60, |
81 | | ArrayBase479 = 61, |
82 | | ArrayBase480 = 62, |
83 | | Addr0_W = 63, |
84 | | Addr1_W = 64, |
85 | | Addr2_W = 65, |
86 | | Addr3_W = 66, |
87 | | Addr4_W = 67, |
88 | | Addr5_W = 68, |
89 | | Addr6_W = 69, |
90 | | Addr7_W = 70, |
91 | | Addr8_W = 71, |
92 | | Addr9_W = 72, |
93 | | Addr10_W = 73, |
94 | | Addr11_W = 74, |
95 | | Addr12_W = 75, |
96 | | Addr13_W = 76, |
97 | | Addr14_W = 77, |
98 | | Addr15_W = 78, |
99 | | Addr16_W = 79, |
100 | | Addr17_W = 80, |
101 | | Addr18_W = 81, |
102 | | Addr19_W = 82, |
103 | | Addr20_W = 83, |
104 | | Addr21_W = 84, |
105 | | Addr22_W = 85, |
106 | | Addr23_W = 86, |
107 | | Addr24_W = 87, |
108 | | Addr25_W = 88, |
109 | | Addr26_W = 89, |
110 | | Addr27_W = 90, |
111 | | Addr28_W = 91, |
112 | | Addr29_W = 92, |
113 | | Addr30_W = 93, |
114 | | Addr31_W = 94, |
115 | | Addr32_W = 95, |
116 | | Addr33_W = 96, |
117 | | Addr34_W = 97, |
118 | | Addr35_W = 98, |
119 | | Addr36_W = 99, |
120 | | Addr37_W = 100, |
121 | | Addr38_W = 101, |
122 | | Addr39_W = 102, |
123 | | Addr40_W = 103, |
124 | | Addr41_W = 104, |
125 | | Addr42_W = 105, |
126 | | Addr43_W = 106, |
127 | | Addr44_W = 107, |
128 | | Addr45_W = 108, |
129 | | Addr46_W = 109, |
130 | | Addr47_W = 110, |
131 | | Addr48_W = 111, |
132 | | Addr49_W = 112, |
133 | | Addr50_W = 113, |
134 | | Addr51_W = 114, |
135 | | Addr52_W = 115, |
136 | | Addr53_W = 116, |
137 | | Addr54_W = 117, |
138 | | Addr55_W = 118, |
139 | | Addr56_W = 119, |
140 | | Addr57_W = 120, |
141 | | Addr58_W = 121, |
142 | | Addr59_W = 122, |
143 | | Addr60_W = 123, |
144 | | Addr61_W = 124, |
145 | | Addr62_W = 125, |
146 | | Addr63_W = 126, |
147 | | Addr64_W = 127, |
148 | | Addr65_W = 128, |
149 | | Addr66_W = 129, |
150 | | Addr67_W = 130, |
151 | | Addr68_W = 131, |
152 | | Addr69_W = 132, |
153 | | Addr70_W = 133, |
154 | | Addr71_W = 134, |
155 | | Addr72_W = 135, |
156 | | Addr73_W = 136, |
157 | | Addr74_W = 137, |
158 | | Addr75_W = 138, |
159 | | Addr76_W = 139, |
160 | | Addr77_W = 140, |
161 | | Addr78_W = 141, |
162 | | Addr79_W = 142, |
163 | | Addr80_W = 143, |
164 | | Addr81_W = 144, |
165 | | Addr82_W = 145, |
166 | | Addr83_W = 146, |
167 | | Addr84_W = 147, |
168 | | Addr85_W = 148, |
169 | | Addr86_W = 149, |
170 | | Addr87_W = 150, |
171 | | Addr88_W = 151, |
172 | | Addr89_W = 152, |
173 | | Addr90_W = 153, |
174 | | Addr91_W = 154, |
175 | | Addr92_W = 155, |
176 | | Addr93_W = 156, |
177 | | Addr94_W = 157, |
178 | | Addr95_W = 158, |
179 | | Addr96_W = 159, |
180 | | Addr97_W = 160, |
181 | | Addr98_W = 161, |
182 | | Addr99_W = 162, |
183 | | Addr100_W = 163, |
184 | | Addr101_W = 164, |
185 | | Addr102_W = 165, |
186 | | Addr103_W = 166, |
187 | | Addr104_W = 167, |
188 | | Addr105_W = 168, |
189 | | Addr106_W = 169, |
190 | | Addr107_W = 170, |
191 | | Addr108_W = 171, |
192 | | Addr109_W = 172, |
193 | | Addr110_W = 173, |
194 | | Addr111_W = 174, |
195 | | Addr112_W = 175, |
196 | | Addr113_W = 176, |
197 | | Addr114_W = 177, |
198 | | Addr115_W = 178, |
199 | | Addr116_W = 179, |
200 | | Addr117_W = 180, |
201 | | Addr118_W = 181, |
202 | | Addr119_W = 182, |
203 | | Addr120_W = 183, |
204 | | Addr121_W = 184, |
205 | | Addr122_W = 185, |
206 | | Addr123_W = 186, |
207 | | Addr124_W = 187, |
208 | | Addr125_W = 188, |
209 | | Addr126_W = 189, |
210 | | Addr127_W = 190, |
211 | | Addr0_X = 191, |
212 | | Addr1_X = 192, |
213 | | Addr2_X = 193, |
214 | | Addr3_X = 194, |
215 | | Addr4_X = 195, |
216 | | Addr5_X = 196, |
217 | | Addr6_X = 197, |
218 | | Addr7_X = 198, |
219 | | Addr8_X = 199, |
220 | | Addr9_X = 200, |
221 | | Addr10_X = 201, |
222 | | Addr11_X = 202, |
223 | | Addr12_X = 203, |
224 | | Addr13_X = 204, |
225 | | Addr14_X = 205, |
226 | | Addr15_X = 206, |
227 | | Addr16_X = 207, |
228 | | Addr17_X = 208, |
229 | | Addr18_X = 209, |
230 | | Addr19_X = 210, |
231 | | Addr20_X = 211, |
232 | | Addr21_X = 212, |
233 | | Addr22_X = 213, |
234 | | Addr23_X = 214, |
235 | | Addr24_X = 215, |
236 | | Addr25_X = 216, |
237 | | Addr26_X = 217, |
238 | | Addr27_X = 218, |
239 | | Addr28_X = 219, |
240 | | Addr29_X = 220, |
241 | | Addr30_X = 221, |
242 | | Addr31_X = 222, |
243 | | Addr32_X = 223, |
244 | | Addr33_X = 224, |
245 | | Addr34_X = 225, |
246 | | Addr35_X = 226, |
247 | | Addr36_X = 227, |
248 | | Addr37_X = 228, |
249 | | Addr38_X = 229, |
250 | | Addr39_X = 230, |
251 | | Addr40_X = 231, |
252 | | Addr41_X = 232, |
253 | | Addr42_X = 233, |
254 | | Addr43_X = 234, |
255 | | Addr44_X = 235, |
256 | | Addr45_X = 236, |
257 | | Addr46_X = 237, |
258 | | Addr47_X = 238, |
259 | | Addr48_X = 239, |
260 | | Addr49_X = 240, |
261 | | Addr50_X = 241, |
262 | | Addr51_X = 242, |
263 | | Addr52_X = 243, |
264 | | Addr53_X = 244, |
265 | | Addr54_X = 245, |
266 | | Addr55_X = 246, |
267 | | Addr56_X = 247, |
268 | | Addr57_X = 248, |
269 | | Addr58_X = 249, |
270 | | Addr59_X = 250, |
271 | | Addr60_X = 251, |
272 | | Addr61_X = 252, |
273 | | Addr62_X = 253, |
274 | | Addr63_X = 254, |
275 | | Addr64_X = 255, |
276 | | Addr65_X = 256, |
277 | | Addr66_X = 257, |
278 | | Addr67_X = 258, |
279 | | Addr68_X = 259, |
280 | | Addr69_X = 260, |
281 | | Addr70_X = 261, |
282 | | Addr71_X = 262, |
283 | | Addr72_X = 263, |
284 | | Addr73_X = 264, |
285 | | Addr74_X = 265, |
286 | | Addr75_X = 266, |
287 | | Addr76_X = 267, |
288 | | Addr77_X = 268, |
289 | | Addr78_X = 269, |
290 | | Addr79_X = 270, |
291 | | Addr80_X = 271, |
292 | | Addr81_X = 272, |
293 | | Addr82_X = 273, |
294 | | Addr83_X = 274, |
295 | | Addr84_X = 275, |
296 | | Addr85_X = 276, |
297 | | Addr86_X = 277, |
298 | | Addr87_X = 278, |
299 | | Addr88_X = 279, |
300 | | Addr89_X = 280, |
301 | | Addr90_X = 281, |
302 | | Addr91_X = 282, |
303 | | Addr92_X = 283, |
304 | | Addr93_X = 284, |
305 | | Addr94_X = 285, |
306 | | Addr95_X = 286, |
307 | | Addr96_X = 287, |
308 | | Addr97_X = 288, |
309 | | Addr98_X = 289, |
310 | | Addr99_X = 290, |
311 | | Addr100_X = 291, |
312 | | Addr101_X = 292, |
313 | | Addr102_X = 293, |
314 | | Addr103_X = 294, |
315 | | Addr104_X = 295, |
316 | | Addr105_X = 296, |
317 | | Addr106_X = 297, |
318 | | Addr107_X = 298, |
319 | | Addr108_X = 299, |
320 | | Addr109_X = 300, |
321 | | Addr110_X = 301, |
322 | | Addr111_X = 302, |
323 | | Addr112_X = 303, |
324 | | Addr113_X = 304, |
325 | | Addr114_X = 305, |
326 | | Addr115_X = 306, |
327 | | Addr116_X = 307, |
328 | | Addr117_X = 308, |
329 | | Addr118_X = 309, |
330 | | Addr119_X = 310, |
331 | | Addr120_X = 311, |
332 | | Addr121_X = 312, |
333 | | Addr122_X = 313, |
334 | | Addr123_X = 314, |
335 | | Addr124_X = 315, |
336 | | Addr125_X = 316, |
337 | | Addr126_X = 317, |
338 | | Addr127_X = 318, |
339 | | Addr0_Y = 319, |
340 | | Addr1_Y = 320, |
341 | | Addr2_Y = 321, |
342 | | Addr3_Y = 322, |
343 | | Addr4_Y = 323, |
344 | | Addr5_Y = 324, |
345 | | Addr6_Y = 325, |
346 | | Addr7_Y = 326, |
347 | | Addr8_Y = 327, |
348 | | Addr9_Y = 328, |
349 | | Addr10_Y = 329, |
350 | | Addr11_Y = 330, |
351 | | Addr12_Y = 331, |
352 | | Addr13_Y = 332, |
353 | | Addr14_Y = 333, |
354 | | Addr15_Y = 334, |
355 | | Addr16_Y = 335, |
356 | | Addr17_Y = 336, |
357 | | Addr18_Y = 337, |
358 | | Addr19_Y = 338, |
359 | | Addr20_Y = 339, |
360 | | Addr21_Y = 340, |
361 | | Addr22_Y = 341, |
362 | | Addr23_Y = 342, |
363 | | Addr24_Y = 343, |
364 | | Addr25_Y = 344, |
365 | | Addr26_Y = 345, |
366 | | Addr27_Y = 346, |
367 | | Addr28_Y = 347, |
368 | | Addr29_Y = 348, |
369 | | Addr30_Y = 349, |
370 | | Addr31_Y = 350, |
371 | | Addr32_Y = 351, |
372 | | Addr33_Y = 352, |
373 | | Addr34_Y = 353, |
374 | | Addr35_Y = 354, |
375 | | Addr36_Y = 355, |
376 | | Addr37_Y = 356, |
377 | | Addr38_Y = 357, |
378 | | Addr39_Y = 358, |
379 | | Addr40_Y = 359, |
380 | | Addr41_Y = 360, |
381 | | Addr42_Y = 361, |
382 | | Addr43_Y = 362, |
383 | | Addr44_Y = 363, |
384 | | Addr45_Y = 364, |
385 | | Addr46_Y = 365, |
386 | | Addr47_Y = 366, |
387 | | Addr48_Y = 367, |
388 | | Addr49_Y = 368, |
389 | | Addr50_Y = 369, |
390 | | Addr51_Y = 370, |
391 | | Addr52_Y = 371, |
392 | | Addr53_Y = 372, |
393 | | Addr54_Y = 373, |
394 | | Addr55_Y = 374, |
395 | | Addr56_Y = 375, |
396 | | Addr57_Y = 376, |
397 | | Addr58_Y = 377, |
398 | | Addr59_Y = 378, |
399 | | Addr60_Y = 379, |
400 | | Addr61_Y = 380, |
401 | | Addr62_Y = 381, |
402 | | Addr63_Y = 382, |
403 | | Addr64_Y = 383, |
404 | | Addr65_Y = 384, |
405 | | Addr66_Y = 385, |
406 | | Addr67_Y = 386, |
407 | | Addr68_Y = 387, |
408 | | Addr69_Y = 388, |
409 | | Addr70_Y = 389, |
410 | | Addr71_Y = 390, |
411 | | Addr72_Y = 391, |
412 | | Addr73_Y = 392, |
413 | | Addr74_Y = 393, |
414 | | Addr75_Y = 394, |
415 | | Addr76_Y = 395, |
416 | | Addr77_Y = 396, |
417 | | Addr78_Y = 397, |
418 | | Addr79_Y = 398, |
419 | | Addr80_Y = 399, |
420 | | Addr81_Y = 400, |
421 | | Addr82_Y = 401, |
422 | | Addr83_Y = 402, |
423 | | Addr84_Y = 403, |
424 | | Addr85_Y = 404, |
425 | | Addr86_Y = 405, |
426 | | Addr87_Y = 406, |
427 | | Addr88_Y = 407, |
428 | | Addr89_Y = 408, |
429 | | Addr90_Y = 409, |
430 | | Addr91_Y = 410, |
431 | | Addr92_Y = 411, |
432 | | Addr93_Y = 412, |
433 | | Addr94_Y = 413, |
434 | | Addr95_Y = 414, |
435 | | Addr96_Y = 415, |
436 | | Addr97_Y = 416, |
437 | | Addr98_Y = 417, |
438 | | Addr99_Y = 418, |
439 | | Addr100_Y = 419, |
440 | | Addr101_Y = 420, |
441 | | Addr102_Y = 421, |
442 | | Addr103_Y = 422, |
443 | | Addr104_Y = 423, |
444 | | Addr105_Y = 424, |
445 | | Addr106_Y = 425, |
446 | | Addr107_Y = 426, |
447 | | Addr108_Y = 427, |
448 | | Addr109_Y = 428, |
449 | | Addr110_Y = 429, |
450 | | Addr111_Y = 430, |
451 | | Addr112_Y = 431, |
452 | | Addr113_Y = 432, |
453 | | Addr114_Y = 433, |
454 | | Addr115_Y = 434, |
455 | | Addr116_Y = 435, |
456 | | Addr117_Y = 436, |
457 | | Addr118_Y = 437, |
458 | | Addr119_Y = 438, |
459 | | Addr120_Y = 439, |
460 | | Addr121_Y = 440, |
461 | | Addr122_Y = 441, |
462 | | Addr123_Y = 442, |
463 | | Addr124_Y = 443, |
464 | | Addr125_Y = 444, |
465 | | Addr126_Y = 445, |
466 | | Addr127_Y = 446, |
467 | | Addr0_Z = 447, |
468 | | Addr1_Z = 448, |
469 | | Addr2_Z = 449, |
470 | | Addr3_Z = 450, |
471 | | Addr4_Z = 451, |
472 | | Addr5_Z = 452, |
473 | | Addr6_Z = 453, |
474 | | Addr7_Z = 454, |
475 | | Addr8_Z = 455, |
476 | | Addr9_Z = 456, |
477 | | Addr10_Z = 457, |
478 | | Addr11_Z = 458, |
479 | | Addr12_Z = 459, |
480 | | Addr13_Z = 460, |
481 | | Addr14_Z = 461, |
482 | | Addr15_Z = 462, |
483 | | Addr16_Z = 463, |
484 | | Addr17_Z = 464, |
485 | | Addr18_Z = 465, |
486 | | Addr19_Z = 466, |
487 | | Addr20_Z = 467, |
488 | | Addr21_Z = 468, |
489 | | Addr22_Z = 469, |
490 | | Addr23_Z = 470, |
491 | | Addr24_Z = 471, |
492 | | Addr25_Z = 472, |
493 | | Addr26_Z = 473, |
494 | | Addr27_Z = 474, |
495 | | Addr28_Z = 475, |
496 | | Addr29_Z = 476, |
497 | | Addr30_Z = 477, |
498 | | Addr31_Z = 478, |
499 | | Addr32_Z = 479, |
500 | | Addr33_Z = 480, |
501 | | Addr34_Z = 481, |
502 | | Addr35_Z = 482, |
503 | | Addr36_Z = 483, |
504 | | Addr37_Z = 484, |
505 | | Addr38_Z = 485, |
506 | | Addr39_Z = 486, |
507 | | Addr40_Z = 487, |
508 | | Addr41_Z = 488, |
509 | | Addr42_Z = 489, |
510 | | Addr43_Z = 490, |
511 | | Addr44_Z = 491, |
512 | | Addr45_Z = 492, |
513 | | Addr46_Z = 493, |
514 | | Addr47_Z = 494, |
515 | | Addr48_Z = 495, |
516 | | Addr49_Z = 496, |
517 | | Addr50_Z = 497, |
518 | | Addr51_Z = 498, |
519 | | Addr52_Z = 499, |
520 | | Addr53_Z = 500, |
521 | | Addr54_Z = 501, |
522 | | Addr55_Z = 502, |
523 | | Addr56_Z = 503, |
524 | | Addr57_Z = 504, |
525 | | Addr58_Z = 505, |
526 | | Addr59_Z = 506, |
527 | | Addr60_Z = 507, |
528 | | Addr61_Z = 508, |
529 | | Addr62_Z = 509, |
530 | | Addr63_Z = 510, |
531 | | Addr64_Z = 511, |
532 | | Addr65_Z = 512, |
533 | | Addr66_Z = 513, |
534 | | Addr67_Z = 514, |
535 | | Addr68_Z = 515, |
536 | | Addr69_Z = 516, |
537 | | Addr70_Z = 517, |
538 | | Addr71_Z = 518, |
539 | | Addr72_Z = 519, |
540 | | Addr73_Z = 520, |
541 | | Addr74_Z = 521, |
542 | | Addr75_Z = 522, |
543 | | Addr76_Z = 523, |
544 | | Addr77_Z = 524, |
545 | | Addr78_Z = 525, |
546 | | Addr79_Z = 526, |
547 | | Addr80_Z = 527, |
548 | | Addr81_Z = 528, |
549 | | Addr82_Z = 529, |
550 | | Addr83_Z = 530, |
551 | | Addr84_Z = 531, |
552 | | Addr85_Z = 532, |
553 | | Addr86_Z = 533, |
554 | | Addr87_Z = 534, |
555 | | Addr88_Z = 535, |
556 | | Addr89_Z = 536, |
557 | | Addr90_Z = 537, |
558 | | Addr91_Z = 538, |
559 | | Addr92_Z = 539, |
560 | | Addr93_Z = 540, |
561 | | Addr94_Z = 541, |
562 | | Addr95_Z = 542, |
563 | | Addr96_Z = 543, |
564 | | Addr97_Z = 544, |
565 | | Addr98_Z = 545, |
566 | | Addr99_Z = 546, |
567 | | Addr100_Z = 547, |
568 | | Addr101_Z = 548, |
569 | | Addr102_Z = 549, |
570 | | Addr103_Z = 550, |
571 | | Addr104_Z = 551, |
572 | | Addr105_Z = 552, |
573 | | Addr106_Z = 553, |
574 | | Addr107_Z = 554, |
575 | | Addr108_Z = 555, |
576 | | Addr109_Z = 556, |
577 | | Addr110_Z = 557, |
578 | | Addr111_Z = 558, |
579 | | Addr112_Z = 559, |
580 | | Addr113_Z = 560, |
581 | | Addr114_Z = 561, |
582 | | Addr115_Z = 562, |
583 | | Addr116_Z = 563, |
584 | | Addr117_Z = 564, |
585 | | Addr118_Z = 565, |
586 | | Addr119_Z = 566, |
587 | | Addr120_Z = 567, |
588 | | Addr121_Z = 568, |
589 | | Addr122_Z = 569, |
590 | | Addr123_Z = 570, |
591 | | Addr124_Z = 571, |
592 | | Addr125_Z = 572, |
593 | | Addr126_Z = 573, |
594 | | Addr127_Z = 574, |
595 | | T0_W = 575, |
596 | | T1_W = 576, |
597 | | T2_W = 577, |
598 | | T3_W = 578, |
599 | | T4_W = 579, |
600 | | T5_W = 580, |
601 | | T6_W = 581, |
602 | | T7_W = 582, |
603 | | T8_W = 583, |
604 | | T9_W = 584, |
605 | | T10_W = 585, |
606 | | T11_W = 586, |
607 | | T12_W = 587, |
608 | | T13_W = 588, |
609 | | T14_W = 589, |
610 | | T15_W = 590, |
611 | | T16_W = 591, |
612 | | T17_W = 592, |
613 | | T18_W = 593, |
614 | | T19_W = 594, |
615 | | T20_W = 595, |
616 | | T21_W = 596, |
617 | | T22_W = 597, |
618 | | T23_W = 598, |
619 | | T24_W = 599, |
620 | | T25_W = 600, |
621 | | T26_W = 601, |
622 | | T27_W = 602, |
623 | | T28_W = 603, |
624 | | T29_W = 604, |
625 | | T30_W = 605, |
626 | | T31_W = 606, |
627 | | T32_W = 607, |
628 | | T33_W = 608, |
629 | | T34_W = 609, |
630 | | T35_W = 610, |
631 | | T36_W = 611, |
632 | | T37_W = 612, |
633 | | T38_W = 613, |
634 | | T39_W = 614, |
635 | | T40_W = 615, |
636 | | T41_W = 616, |
637 | | T42_W = 617, |
638 | | T43_W = 618, |
639 | | T44_W = 619, |
640 | | T45_W = 620, |
641 | | T46_W = 621, |
642 | | T47_W = 622, |
643 | | T48_W = 623, |
644 | | T49_W = 624, |
645 | | T50_W = 625, |
646 | | T51_W = 626, |
647 | | T52_W = 627, |
648 | | T53_W = 628, |
649 | | T54_W = 629, |
650 | | T55_W = 630, |
651 | | T56_W = 631, |
652 | | T57_W = 632, |
653 | | T58_W = 633, |
654 | | T59_W = 634, |
655 | | T60_W = 635, |
656 | | T61_W = 636, |
657 | | T62_W = 637, |
658 | | T63_W = 638, |
659 | | T64_W = 639, |
660 | | T65_W = 640, |
661 | | T66_W = 641, |
662 | | T67_W = 642, |
663 | | T68_W = 643, |
664 | | T69_W = 644, |
665 | | T70_W = 645, |
666 | | T71_W = 646, |
667 | | T72_W = 647, |
668 | | T73_W = 648, |
669 | | T74_W = 649, |
670 | | T75_W = 650, |
671 | | T76_W = 651, |
672 | | T77_W = 652, |
673 | | T78_W = 653, |
674 | | T79_W = 654, |
675 | | T80_W = 655, |
676 | | T81_W = 656, |
677 | | T82_W = 657, |
678 | | T83_W = 658, |
679 | | T84_W = 659, |
680 | | T85_W = 660, |
681 | | T86_W = 661, |
682 | | T87_W = 662, |
683 | | T88_W = 663, |
684 | | T89_W = 664, |
685 | | T90_W = 665, |
686 | | T91_W = 666, |
687 | | T92_W = 667, |
688 | | T93_W = 668, |
689 | | T94_W = 669, |
690 | | T95_W = 670, |
691 | | T96_W = 671, |
692 | | T97_W = 672, |
693 | | T98_W = 673, |
694 | | T99_W = 674, |
695 | | T100_W = 675, |
696 | | T101_W = 676, |
697 | | T102_W = 677, |
698 | | T103_W = 678, |
699 | | T104_W = 679, |
700 | | T105_W = 680, |
701 | | T106_W = 681, |
702 | | T107_W = 682, |
703 | | T108_W = 683, |
704 | | T109_W = 684, |
705 | | T110_W = 685, |
706 | | T111_W = 686, |
707 | | T112_W = 687, |
708 | | T113_W = 688, |
709 | | T114_W = 689, |
710 | | T115_W = 690, |
711 | | T116_W = 691, |
712 | | T117_W = 692, |
713 | | T118_W = 693, |
714 | | T119_W = 694, |
715 | | T120_W = 695, |
716 | | T121_W = 696, |
717 | | T122_W = 697, |
718 | | T123_W = 698, |
719 | | T124_W = 699, |
720 | | T125_W = 700, |
721 | | T126_W = 701, |
722 | | T127_W = 702, |
723 | | T0_X = 703, |
724 | | T1_X = 704, |
725 | | T2_X = 705, |
726 | | T3_X = 706, |
727 | | T4_X = 707, |
728 | | T5_X = 708, |
729 | | T6_X = 709, |
730 | | T7_X = 710, |
731 | | T8_X = 711, |
732 | | T9_X = 712, |
733 | | T10_X = 713, |
734 | | T11_X = 714, |
735 | | T12_X = 715, |
736 | | T13_X = 716, |
737 | | T14_X = 717, |
738 | | T15_X = 718, |
739 | | T16_X = 719, |
740 | | T17_X = 720, |
741 | | T18_X = 721, |
742 | | T19_X = 722, |
743 | | T20_X = 723, |
744 | | T21_X = 724, |
745 | | T22_X = 725, |
746 | | T23_X = 726, |
747 | | T24_X = 727, |
748 | | T25_X = 728, |
749 | | T26_X = 729, |
750 | | T27_X = 730, |
751 | | T28_X = 731, |
752 | | T29_X = 732, |
753 | | T30_X = 733, |
754 | | T31_X = 734, |
755 | | T32_X = 735, |
756 | | T33_X = 736, |
757 | | T34_X = 737, |
758 | | T35_X = 738, |
759 | | T36_X = 739, |
760 | | T37_X = 740, |
761 | | T38_X = 741, |
762 | | T39_X = 742, |
763 | | T40_X = 743, |
764 | | T41_X = 744, |
765 | | T42_X = 745, |
766 | | T43_X = 746, |
767 | | T44_X = 747, |
768 | | T45_X = 748, |
769 | | T46_X = 749, |
770 | | T47_X = 750, |
771 | | T48_X = 751, |
772 | | T49_X = 752, |
773 | | T50_X = 753, |
774 | | T51_X = 754, |
775 | | T52_X = 755, |
776 | | T53_X = 756, |
777 | | T54_X = 757, |
778 | | T55_X = 758, |
779 | | T56_X = 759, |
780 | | T57_X = 760, |
781 | | T58_X = 761, |
782 | | T59_X = 762, |
783 | | T60_X = 763, |
784 | | T61_X = 764, |
785 | | T62_X = 765, |
786 | | T63_X = 766, |
787 | | T64_X = 767, |
788 | | T65_X = 768, |
789 | | T66_X = 769, |
790 | | T67_X = 770, |
791 | | T68_X = 771, |
792 | | T69_X = 772, |
793 | | T70_X = 773, |
794 | | T71_X = 774, |
795 | | T72_X = 775, |
796 | | T73_X = 776, |
797 | | T74_X = 777, |
798 | | T75_X = 778, |
799 | | T76_X = 779, |
800 | | T77_X = 780, |
801 | | T78_X = 781, |
802 | | T79_X = 782, |
803 | | T80_X = 783, |
804 | | T81_X = 784, |
805 | | T82_X = 785, |
806 | | T83_X = 786, |
807 | | T84_X = 787, |
808 | | T85_X = 788, |
809 | | T86_X = 789, |
810 | | T87_X = 790, |
811 | | T88_X = 791, |
812 | | T89_X = 792, |
813 | | T90_X = 793, |
814 | | T91_X = 794, |
815 | | T92_X = 795, |
816 | | T93_X = 796, |
817 | | T94_X = 797, |
818 | | T95_X = 798, |
819 | | T96_X = 799, |
820 | | T97_X = 800, |
821 | | T98_X = 801, |
822 | | T99_X = 802, |
823 | | T100_X = 803, |
824 | | T101_X = 804, |
825 | | T102_X = 805, |
826 | | T103_X = 806, |
827 | | T104_X = 807, |
828 | | T105_X = 808, |
829 | | T106_X = 809, |
830 | | T107_X = 810, |
831 | | T108_X = 811, |
832 | | T109_X = 812, |
833 | | T110_X = 813, |
834 | | T111_X = 814, |
835 | | T112_X = 815, |
836 | | T113_X = 816, |
837 | | T114_X = 817, |
838 | | T115_X = 818, |
839 | | T116_X = 819, |
840 | | T117_X = 820, |
841 | | T118_X = 821, |
842 | | T119_X = 822, |
843 | | T120_X = 823, |
844 | | T121_X = 824, |
845 | | T122_X = 825, |
846 | | T123_X = 826, |
847 | | T124_X = 827, |
848 | | T125_X = 828, |
849 | | T126_X = 829, |
850 | | T127_X = 830, |
851 | | T0_XY = 831, |
852 | | T1_XY = 832, |
853 | | T2_XY = 833, |
854 | | T3_XY = 834, |
855 | | T4_XY = 835, |
856 | | T5_XY = 836, |
857 | | T6_XY = 837, |
858 | | T7_XY = 838, |
859 | | T8_XY = 839, |
860 | | T9_XY = 840, |
861 | | T10_XY = 841, |
862 | | T11_XY = 842, |
863 | | T12_XY = 843, |
864 | | T13_XY = 844, |
865 | | T14_XY = 845, |
866 | | T15_XY = 846, |
867 | | T16_XY = 847, |
868 | | T17_XY = 848, |
869 | | T18_XY = 849, |
870 | | T19_XY = 850, |
871 | | T20_XY = 851, |
872 | | T21_XY = 852, |
873 | | T22_XY = 853, |
874 | | T23_XY = 854, |
875 | | T24_XY = 855, |
876 | | T25_XY = 856, |
877 | | T26_XY = 857, |
878 | | T27_XY = 858, |
879 | | T28_XY = 859, |
880 | | T29_XY = 860, |
881 | | T30_XY = 861, |
882 | | T31_XY = 862, |
883 | | T32_XY = 863, |
884 | | T33_XY = 864, |
885 | | T34_XY = 865, |
886 | | T35_XY = 866, |
887 | | T36_XY = 867, |
888 | | T37_XY = 868, |
889 | | T38_XY = 869, |
890 | | T39_XY = 870, |
891 | | T40_XY = 871, |
892 | | T41_XY = 872, |
893 | | T42_XY = 873, |
894 | | T43_XY = 874, |
895 | | T44_XY = 875, |
896 | | T45_XY = 876, |
897 | | T46_XY = 877, |
898 | | T47_XY = 878, |
899 | | T48_XY = 879, |
900 | | T49_XY = 880, |
901 | | T50_XY = 881, |
902 | | T51_XY = 882, |
903 | | T52_XY = 883, |
904 | | T53_XY = 884, |
905 | | T54_XY = 885, |
906 | | T55_XY = 886, |
907 | | T56_XY = 887, |
908 | | T57_XY = 888, |
909 | | T58_XY = 889, |
910 | | T59_XY = 890, |
911 | | T60_XY = 891, |
912 | | T61_XY = 892, |
913 | | T62_XY = 893, |
914 | | T63_XY = 894, |
915 | | T64_XY = 895, |
916 | | T65_XY = 896, |
917 | | T66_XY = 897, |
918 | | T67_XY = 898, |
919 | | T68_XY = 899, |
920 | | T69_XY = 900, |
921 | | T70_XY = 901, |
922 | | T71_XY = 902, |
923 | | T72_XY = 903, |
924 | | T73_XY = 904, |
925 | | T74_XY = 905, |
926 | | T75_XY = 906, |
927 | | T76_XY = 907, |
928 | | T77_XY = 908, |
929 | | T78_XY = 909, |
930 | | T79_XY = 910, |
931 | | T80_XY = 911, |
932 | | T81_XY = 912, |
933 | | T82_XY = 913, |
934 | | T83_XY = 914, |
935 | | T84_XY = 915, |
936 | | T85_XY = 916, |
937 | | T86_XY = 917, |
938 | | T87_XY = 918, |
939 | | T88_XY = 919, |
940 | | T89_XY = 920, |
941 | | T90_XY = 921, |
942 | | T91_XY = 922, |
943 | | T92_XY = 923, |
944 | | T93_XY = 924, |
945 | | T94_XY = 925, |
946 | | T95_XY = 926, |
947 | | T96_XY = 927, |
948 | | T97_XY = 928, |
949 | | T98_XY = 929, |
950 | | T99_XY = 930, |
951 | | T100_XY = 931, |
952 | | T101_XY = 932, |
953 | | T102_XY = 933, |
954 | | T103_XY = 934, |
955 | | T104_XY = 935, |
956 | | T105_XY = 936, |
957 | | T106_XY = 937, |
958 | | T107_XY = 938, |
959 | | T108_XY = 939, |
960 | | T109_XY = 940, |
961 | | T110_XY = 941, |
962 | | T111_XY = 942, |
963 | | T112_XY = 943, |
964 | | T113_XY = 944, |
965 | | T114_XY = 945, |
966 | | T115_XY = 946, |
967 | | T116_XY = 947, |
968 | | T117_XY = 948, |
969 | | T118_XY = 949, |
970 | | T119_XY = 950, |
971 | | T120_XY = 951, |
972 | | T121_XY = 952, |
973 | | T122_XY = 953, |
974 | | T123_XY = 954, |
975 | | T124_XY = 955, |
976 | | T125_XY = 956, |
977 | | T126_XY = 957, |
978 | | T127_XY = 958, |
979 | | T0_XYZW = 959, |
980 | | T1_XYZW = 960, |
981 | | T2_XYZW = 961, |
982 | | T3_XYZW = 962, |
983 | | T4_XYZW = 963, |
984 | | T5_XYZW = 964, |
985 | | T6_XYZW = 965, |
986 | | T7_XYZW = 966, |
987 | | T8_XYZW = 967, |
988 | | T9_XYZW = 968, |
989 | | T10_XYZW = 969, |
990 | | T11_XYZW = 970, |
991 | | T12_XYZW = 971, |
992 | | T13_XYZW = 972, |
993 | | T14_XYZW = 973, |
994 | | T15_XYZW = 974, |
995 | | T16_XYZW = 975, |
996 | | T17_XYZW = 976, |
997 | | T18_XYZW = 977, |
998 | | T19_XYZW = 978, |
999 | | T20_XYZW = 979, |
1000 | | T21_XYZW = 980, |
1001 | | T22_XYZW = 981, |
1002 | | T23_XYZW = 982, |
1003 | | T24_XYZW = 983, |
1004 | | T25_XYZW = 984, |
1005 | | T26_XYZW = 985, |
1006 | | T27_XYZW = 986, |
1007 | | T28_XYZW = 987, |
1008 | | T29_XYZW = 988, |
1009 | | T30_XYZW = 989, |
1010 | | T31_XYZW = 990, |
1011 | | T32_XYZW = 991, |
1012 | | T33_XYZW = 992, |
1013 | | T34_XYZW = 993, |
1014 | | T35_XYZW = 994, |
1015 | | T36_XYZW = 995, |
1016 | | T37_XYZW = 996, |
1017 | | T38_XYZW = 997, |
1018 | | T39_XYZW = 998, |
1019 | | T40_XYZW = 999, |
1020 | | T41_XYZW = 1000, |
1021 | | T42_XYZW = 1001, |
1022 | | T43_XYZW = 1002, |
1023 | | T44_XYZW = 1003, |
1024 | | T45_XYZW = 1004, |
1025 | | T46_XYZW = 1005, |
1026 | | T47_XYZW = 1006, |
1027 | | T48_XYZW = 1007, |
1028 | | T49_XYZW = 1008, |
1029 | | T50_XYZW = 1009, |
1030 | | T51_XYZW = 1010, |
1031 | | T52_XYZW = 1011, |
1032 | | T53_XYZW = 1012, |
1033 | | T54_XYZW = 1013, |
1034 | | T55_XYZW = 1014, |
1035 | | T56_XYZW = 1015, |
1036 | | T57_XYZW = 1016, |
1037 | | T58_XYZW = 1017, |
1038 | | T59_XYZW = 1018, |
1039 | | T60_XYZW = 1019, |
1040 | | T61_XYZW = 1020, |
1041 | | T62_XYZW = 1021, |
1042 | | T63_XYZW = 1022, |
1043 | | T64_XYZW = 1023, |
1044 | | T65_XYZW = 1024, |
1045 | | T66_XYZW = 1025, |
1046 | | T67_XYZW = 1026, |
1047 | | T68_XYZW = 1027, |
1048 | | T69_XYZW = 1028, |
1049 | | T70_XYZW = 1029, |
1050 | | T71_XYZW = 1030, |
1051 | | T72_XYZW = 1031, |
1052 | | T73_XYZW = 1032, |
1053 | | T74_XYZW = 1033, |
1054 | | T75_XYZW = 1034, |
1055 | | T76_XYZW = 1035, |
1056 | | T77_XYZW = 1036, |
1057 | | T78_XYZW = 1037, |
1058 | | T79_XYZW = 1038, |
1059 | | T80_XYZW = 1039, |
1060 | | T81_XYZW = 1040, |
1061 | | T82_XYZW = 1041, |
1062 | | T83_XYZW = 1042, |
1063 | | T84_XYZW = 1043, |
1064 | | T85_XYZW = 1044, |
1065 | | T86_XYZW = 1045, |
1066 | | T87_XYZW = 1046, |
1067 | | T88_XYZW = 1047, |
1068 | | T89_XYZW = 1048, |
1069 | | T90_XYZW = 1049, |
1070 | | T91_XYZW = 1050, |
1071 | | T92_XYZW = 1051, |
1072 | | T93_XYZW = 1052, |
1073 | | T94_XYZW = 1053, |
1074 | | T95_XYZW = 1054, |
1075 | | T96_XYZW = 1055, |
1076 | | T97_XYZW = 1056, |
1077 | | T98_XYZW = 1057, |
1078 | | T99_XYZW = 1058, |
1079 | | T100_XYZW = 1059, |
1080 | | T101_XYZW = 1060, |
1081 | | T102_XYZW = 1061, |
1082 | | T103_XYZW = 1062, |
1083 | | T104_XYZW = 1063, |
1084 | | T105_XYZW = 1064, |
1085 | | T106_XYZW = 1065, |
1086 | | T107_XYZW = 1066, |
1087 | | T108_XYZW = 1067, |
1088 | | T109_XYZW = 1068, |
1089 | | T110_XYZW = 1069, |
1090 | | T111_XYZW = 1070, |
1091 | | T112_XYZW = 1071, |
1092 | | T113_XYZW = 1072, |
1093 | | T114_XYZW = 1073, |
1094 | | T115_XYZW = 1074, |
1095 | | T116_XYZW = 1075, |
1096 | | T117_XYZW = 1076, |
1097 | | T118_XYZW = 1077, |
1098 | | T119_XYZW = 1078, |
1099 | | T120_XYZW = 1079, |
1100 | | T121_XYZW = 1080, |
1101 | | T122_XYZW = 1081, |
1102 | | T123_XYZW = 1082, |
1103 | | T124_XYZW = 1083, |
1104 | | T125_XYZW = 1084, |
1105 | | T126_XYZW = 1085, |
1106 | | T127_XYZW = 1086, |
1107 | | T0_Y = 1087, |
1108 | | T1_Y = 1088, |
1109 | | T2_Y = 1089, |
1110 | | T3_Y = 1090, |
1111 | | T4_Y = 1091, |
1112 | | T5_Y = 1092, |
1113 | | T6_Y = 1093, |
1114 | | T7_Y = 1094, |
1115 | | T8_Y = 1095, |
1116 | | T9_Y = 1096, |
1117 | | T10_Y = 1097, |
1118 | | T11_Y = 1098, |
1119 | | T12_Y = 1099, |
1120 | | T13_Y = 1100, |
1121 | | T14_Y = 1101, |
1122 | | T15_Y = 1102, |
1123 | | T16_Y = 1103, |
1124 | | T17_Y = 1104, |
1125 | | T18_Y = 1105, |
1126 | | T19_Y = 1106, |
1127 | | T20_Y = 1107, |
1128 | | T21_Y = 1108, |
1129 | | T22_Y = 1109, |
1130 | | T23_Y = 1110, |
1131 | | T24_Y = 1111, |
1132 | | T25_Y = 1112, |
1133 | | T26_Y = 1113, |
1134 | | T27_Y = 1114, |
1135 | | T28_Y = 1115, |
1136 | | T29_Y = 1116, |
1137 | | T30_Y = 1117, |
1138 | | T31_Y = 1118, |
1139 | | T32_Y = 1119, |
1140 | | T33_Y = 1120, |
1141 | | T34_Y = 1121, |
1142 | | T35_Y = 1122, |
1143 | | T36_Y = 1123, |
1144 | | T37_Y = 1124, |
1145 | | T38_Y = 1125, |
1146 | | T39_Y = 1126, |
1147 | | T40_Y = 1127, |
1148 | | T41_Y = 1128, |
1149 | | T42_Y = 1129, |
1150 | | T43_Y = 1130, |
1151 | | T44_Y = 1131, |
1152 | | T45_Y = 1132, |
1153 | | T46_Y = 1133, |
1154 | | T47_Y = 1134, |
1155 | | T48_Y = 1135, |
1156 | | T49_Y = 1136, |
1157 | | T50_Y = 1137, |
1158 | | T51_Y = 1138, |
1159 | | T52_Y = 1139, |
1160 | | T53_Y = 1140, |
1161 | | T54_Y = 1141, |
1162 | | T55_Y = 1142, |
1163 | | T56_Y = 1143, |
1164 | | T57_Y = 1144, |
1165 | | T58_Y = 1145, |
1166 | | T59_Y = 1146, |
1167 | | T60_Y = 1147, |
1168 | | T61_Y = 1148, |
1169 | | T62_Y = 1149, |
1170 | | T63_Y = 1150, |
1171 | | T64_Y = 1151, |
1172 | | T65_Y = 1152, |
1173 | | T66_Y = 1153, |
1174 | | T67_Y = 1154, |
1175 | | T68_Y = 1155, |
1176 | | T69_Y = 1156, |
1177 | | T70_Y = 1157, |
1178 | | T71_Y = 1158, |
1179 | | T72_Y = 1159, |
1180 | | T73_Y = 1160, |
1181 | | T74_Y = 1161, |
1182 | | T75_Y = 1162, |
1183 | | T76_Y = 1163, |
1184 | | T77_Y = 1164, |
1185 | | T78_Y = 1165, |
1186 | | T79_Y = 1166, |
1187 | | T80_Y = 1167, |
1188 | | T81_Y = 1168, |
1189 | | T82_Y = 1169, |
1190 | | T83_Y = 1170, |
1191 | | T84_Y = 1171, |
1192 | | T85_Y = 1172, |
1193 | | T86_Y = 1173, |
1194 | | T87_Y = 1174, |
1195 | | T88_Y = 1175, |
1196 | | T89_Y = 1176, |
1197 | | T90_Y = 1177, |
1198 | | T91_Y = 1178, |
1199 | | T92_Y = 1179, |
1200 | | T93_Y = 1180, |
1201 | | T94_Y = 1181, |
1202 | | T95_Y = 1182, |
1203 | | T96_Y = 1183, |
1204 | | T97_Y = 1184, |
1205 | | T98_Y = 1185, |
1206 | | T99_Y = 1186, |
1207 | | T100_Y = 1187, |
1208 | | T101_Y = 1188, |
1209 | | T102_Y = 1189, |
1210 | | T103_Y = 1190, |
1211 | | T104_Y = 1191, |
1212 | | T105_Y = 1192, |
1213 | | T106_Y = 1193, |
1214 | | T107_Y = 1194, |
1215 | | T108_Y = 1195, |
1216 | | T109_Y = 1196, |
1217 | | T110_Y = 1197, |
1218 | | T111_Y = 1198, |
1219 | | T112_Y = 1199, |
1220 | | T113_Y = 1200, |
1221 | | T114_Y = 1201, |
1222 | | T115_Y = 1202, |
1223 | | T116_Y = 1203, |
1224 | | T117_Y = 1204, |
1225 | | T118_Y = 1205, |
1226 | | T119_Y = 1206, |
1227 | | T120_Y = 1207, |
1228 | | T121_Y = 1208, |
1229 | | T122_Y = 1209, |
1230 | | T123_Y = 1210, |
1231 | | T124_Y = 1211, |
1232 | | T125_Y = 1212, |
1233 | | T126_Y = 1213, |
1234 | | T127_Y = 1214, |
1235 | | T0_Z = 1215, |
1236 | | T1_Z = 1216, |
1237 | | T2_Z = 1217, |
1238 | | T3_Z = 1218, |
1239 | | T4_Z = 1219, |
1240 | | T5_Z = 1220, |
1241 | | T6_Z = 1221, |
1242 | | T7_Z = 1222, |
1243 | | T8_Z = 1223, |
1244 | | T9_Z = 1224, |
1245 | | T10_Z = 1225, |
1246 | | T11_Z = 1226, |
1247 | | T12_Z = 1227, |
1248 | | T13_Z = 1228, |
1249 | | T14_Z = 1229, |
1250 | | T15_Z = 1230, |
1251 | | T16_Z = 1231, |
1252 | | T17_Z = 1232, |
1253 | | T18_Z = 1233, |
1254 | | T19_Z = 1234, |
1255 | | T20_Z = 1235, |
1256 | | T21_Z = 1236, |
1257 | | T22_Z = 1237, |
1258 | | T23_Z = 1238, |
1259 | | T24_Z = 1239, |
1260 | | T25_Z = 1240, |
1261 | | T26_Z = 1241, |
1262 | | T27_Z = 1242, |
1263 | | T28_Z = 1243, |
1264 | | T29_Z = 1244, |
1265 | | T30_Z = 1245, |
1266 | | T31_Z = 1246, |
1267 | | T32_Z = 1247, |
1268 | | T33_Z = 1248, |
1269 | | T34_Z = 1249, |
1270 | | T35_Z = 1250, |
1271 | | T36_Z = 1251, |
1272 | | T37_Z = 1252, |
1273 | | T38_Z = 1253, |
1274 | | T39_Z = 1254, |
1275 | | T40_Z = 1255, |
1276 | | T41_Z = 1256, |
1277 | | T42_Z = 1257, |
1278 | | T43_Z = 1258, |
1279 | | T44_Z = 1259, |
1280 | | T45_Z = 1260, |
1281 | | T46_Z = 1261, |
1282 | | T47_Z = 1262, |
1283 | | T48_Z = 1263, |
1284 | | T49_Z = 1264, |
1285 | | T50_Z = 1265, |
1286 | | T51_Z = 1266, |
1287 | | T52_Z = 1267, |
1288 | | T53_Z = 1268, |
1289 | | T54_Z = 1269, |
1290 | | T55_Z = 1270, |
1291 | | T56_Z = 1271, |
1292 | | T57_Z = 1272, |
1293 | | T58_Z = 1273, |
1294 | | T59_Z = 1274, |
1295 | | T60_Z = 1275, |
1296 | | T61_Z = 1276, |
1297 | | T62_Z = 1277, |
1298 | | T63_Z = 1278, |
1299 | | T64_Z = 1279, |
1300 | | T65_Z = 1280, |
1301 | | T66_Z = 1281, |
1302 | | T67_Z = 1282, |
1303 | | T68_Z = 1283, |
1304 | | T69_Z = 1284, |
1305 | | T70_Z = 1285, |
1306 | | T71_Z = 1286, |
1307 | | T72_Z = 1287, |
1308 | | T73_Z = 1288, |
1309 | | T74_Z = 1289, |
1310 | | T75_Z = 1290, |
1311 | | T76_Z = 1291, |
1312 | | T77_Z = 1292, |
1313 | | T78_Z = 1293, |
1314 | | T79_Z = 1294, |
1315 | | T80_Z = 1295, |
1316 | | T81_Z = 1296, |
1317 | | T82_Z = 1297, |
1318 | | T83_Z = 1298, |
1319 | | T84_Z = 1299, |
1320 | | T85_Z = 1300, |
1321 | | T86_Z = 1301, |
1322 | | T87_Z = 1302, |
1323 | | T88_Z = 1303, |
1324 | | T89_Z = 1304, |
1325 | | T90_Z = 1305, |
1326 | | T91_Z = 1306, |
1327 | | T92_Z = 1307, |
1328 | | T93_Z = 1308, |
1329 | | T94_Z = 1309, |
1330 | | T95_Z = 1310, |
1331 | | T96_Z = 1311, |
1332 | | T97_Z = 1312, |
1333 | | T98_Z = 1313, |
1334 | | T99_Z = 1314, |
1335 | | T100_Z = 1315, |
1336 | | T101_Z = 1316, |
1337 | | T102_Z = 1317, |
1338 | | T103_Z = 1318, |
1339 | | T104_Z = 1319, |
1340 | | T105_Z = 1320, |
1341 | | T106_Z = 1321, |
1342 | | T107_Z = 1322, |
1343 | | T108_Z = 1323, |
1344 | | T109_Z = 1324, |
1345 | | T110_Z = 1325, |
1346 | | T111_Z = 1326, |
1347 | | T112_Z = 1327, |
1348 | | T113_Z = 1328, |
1349 | | T114_Z = 1329, |
1350 | | T115_Z = 1330, |
1351 | | T116_Z = 1331, |
1352 | | T117_Z = 1332, |
1353 | | T118_Z = 1333, |
1354 | | T119_Z = 1334, |
1355 | | T120_Z = 1335, |
1356 | | T121_Z = 1336, |
1357 | | T122_Z = 1337, |
1358 | | T123_Z = 1338, |
1359 | | T124_Z = 1339, |
1360 | | T125_Z = 1340, |
1361 | | T126_Z = 1341, |
1362 | | T127_Z = 1342, |
1363 | | V01_W = 1343, |
1364 | | V23_W = 1344, |
1365 | | V0123_W = 1345, |
1366 | | V01_X = 1346, |
1367 | | V23_X = 1347, |
1368 | | V0123_X = 1348, |
1369 | | V01_Y = 1349, |
1370 | | V23_Y = 1350, |
1371 | | V0123_Y = 1351, |
1372 | | V01_Z = 1352, |
1373 | | V23_Z = 1353, |
1374 | | V0123_Z = 1354, |
1375 | | KC0_128_W = 1355, |
1376 | | KC0_129_W = 1356, |
1377 | | KC0_130_W = 1357, |
1378 | | KC0_131_W = 1358, |
1379 | | KC0_132_W = 1359, |
1380 | | KC0_133_W = 1360, |
1381 | | KC0_134_W = 1361, |
1382 | | KC0_135_W = 1362, |
1383 | | KC0_136_W = 1363, |
1384 | | KC0_137_W = 1364, |
1385 | | KC0_138_W = 1365, |
1386 | | KC0_139_W = 1366, |
1387 | | KC0_140_W = 1367, |
1388 | | KC0_141_W = 1368, |
1389 | | KC0_142_W = 1369, |
1390 | | KC0_143_W = 1370, |
1391 | | KC0_144_W = 1371, |
1392 | | KC0_145_W = 1372, |
1393 | | KC0_146_W = 1373, |
1394 | | KC0_147_W = 1374, |
1395 | | KC0_148_W = 1375, |
1396 | | KC0_149_W = 1376, |
1397 | | KC0_150_W = 1377, |
1398 | | KC0_151_W = 1378, |
1399 | | KC0_152_W = 1379, |
1400 | | KC0_153_W = 1380, |
1401 | | KC0_154_W = 1381, |
1402 | | KC0_155_W = 1382, |
1403 | | KC0_156_W = 1383, |
1404 | | KC0_157_W = 1384, |
1405 | | KC0_158_W = 1385, |
1406 | | KC0_159_W = 1386, |
1407 | | KC1_160_W = 1387, |
1408 | | KC1_161_W = 1388, |
1409 | | KC1_162_W = 1389, |
1410 | | KC1_163_W = 1390, |
1411 | | KC1_164_W = 1391, |
1412 | | KC1_165_W = 1392, |
1413 | | KC1_166_W = 1393, |
1414 | | KC1_167_W = 1394, |
1415 | | KC1_168_W = 1395, |
1416 | | KC1_169_W = 1396, |
1417 | | KC1_170_W = 1397, |
1418 | | KC1_171_W = 1398, |
1419 | | KC1_172_W = 1399, |
1420 | | KC1_173_W = 1400, |
1421 | | KC1_174_W = 1401, |
1422 | | KC1_175_W = 1402, |
1423 | | KC1_176_W = 1403, |
1424 | | KC1_177_W = 1404, |
1425 | | KC1_178_W = 1405, |
1426 | | KC1_179_W = 1406, |
1427 | | KC1_180_W = 1407, |
1428 | | KC1_181_W = 1408, |
1429 | | KC1_182_W = 1409, |
1430 | | KC1_183_W = 1410, |
1431 | | KC1_184_W = 1411, |
1432 | | KC1_185_W = 1412, |
1433 | | KC1_186_W = 1413, |
1434 | | KC1_187_W = 1414, |
1435 | | KC1_188_W = 1415, |
1436 | | KC1_189_W = 1416, |
1437 | | KC1_190_W = 1417, |
1438 | | KC1_191_W = 1418, |
1439 | | KC0_128_X = 1419, |
1440 | | KC0_129_X = 1420, |
1441 | | KC0_130_X = 1421, |
1442 | | KC0_131_X = 1422, |
1443 | | KC0_132_X = 1423, |
1444 | | KC0_133_X = 1424, |
1445 | | KC0_134_X = 1425, |
1446 | | KC0_135_X = 1426, |
1447 | | KC0_136_X = 1427, |
1448 | | KC0_137_X = 1428, |
1449 | | KC0_138_X = 1429, |
1450 | | KC0_139_X = 1430, |
1451 | | KC0_140_X = 1431, |
1452 | | KC0_141_X = 1432, |
1453 | | KC0_142_X = 1433, |
1454 | | KC0_143_X = 1434, |
1455 | | KC0_144_X = 1435, |
1456 | | KC0_145_X = 1436, |
1457 | | KC0_146_X = 1437, |
1458 | | KC0_147_X = 1438, |
1459 | | KC0_148_X = 1439, |
1460 | | KC0_149_X = 1440, |
1461 | | KC0_150_X = 1441, |
1462 | | KC0_151_X = 1442, |
1463 | | KC0_152_X = 1443, |
1464 | | KC0_153_X = 1444, |
1465 | | KC0_154_X = 1445, |
1466 | | KC0_155_X = 1446, |
1467 | | KC0_156_X = 1447, |
1468 | | KC0_157_X = 1448, |
1469 | | KC0_158_X = 1449, |
1470 | | KC0_159_X = 1450, |
1471 | | KC1_160_X = 1451, |
1472 | | KC1_161_X = 1452, |
1473 | | KC1_162_X = 1453, |
1474 | | KC1_163_X = 1454, |
1475 | | KC1_164_X = 1455, |
1476 | | KC1_165_X = 1456, |
1477 | | KC1_166_X = 1457, |
1478 | | KC1_167_X = 1458, |
1479 | | KC1_168_X = 1459, |
1480 | | KC1_169_X = 1460, |
1481 | | KC1_170_X = 1461, |
1482 | | KC1_171_X = 1462, |
1483 | | KC1_172_X = 1463, |
1484 | | KC1_173_X = 1464, |
1485 | | KC1_174_X = 1465, |
1486 | | KC1_175_X = 1466, |
1487 | | KC1_176_X = 1467, |
1488 | | KC1_177_X = 1468, |
1489 | | KC1_178_X = 1469, |
1490 | | KC1_179_X = 1470, |
1491 | | KC1_180_X = 1471, |
1492 | | KC1_181_X = 1472, |
1493 | | KC1_182_X = 1473, |
1494 | | KC1_183_X = 1474, |
1495 | | KC1_184_X = 1475, |
1496 | | KC1_185_X = 1476, |
1497 | | KC1_186_X = 1477, |
1498 | | KC1_187_X = 1478, |
1499 | | KC1_188_X = 1479, |
1500 | | KC1_189_X = 1480, |
1501 | | KC1_190_X = 1481, |
1502 | | KC1_191_X = 1482, |
1503 | | KC0_128_XYZW = 1483, |
1504 | | KC0_129_XYZW = 1484, |
1505 | | KC0_130_XYZW = 1485, |
1506 | | KC0_131_XYZW = 1486, |
1507 | | KC0_132_XYZW = 1487, |
1508 | | KC0_133_XYZW = 1488, |
1509 | | KC0_134_XYZW = 1489, |
1510 | | KC0_135_XYZW = 1490, |
1511 | | KC0_136_XYZW = 1491, |
1512 | | KC0_137_XYZW = 1492, |
1513 | | KC0_138_XYZW = 1493, |
1514 | | KC0_139_XYZW = 1494, |
1515 | | KC0_140_XYZW = 1495, |
1516 | | KC0_141_XYZW = 1496, |
1517 | | KC0_142_XYZW = 1497, |
1518 | | KC0_143_XYZW = 1498, |
1519 | | KC0_144_XYZW = 1499, |
1520 | | KC0_145_XYZW = 1500, |
1521 | | KC0_146_XYZW = 1501, |
1522 | | KC0_147_XYZW = 1502, |
1523 | | KC0_148_XYZW = 1503, |
1524 | | KC0_149_XYZW = 1504, |
1525 | | KC0_150_XYZW = 1505, |
1526 | | KC0_151_XYZW = 1506, |
1527 | | KC0_152_XYZW = 1507, |
1528 | | KC0_153_XYZW = 1508, |
1529 | | KC0_154_XYZW = 1509, |
1530 | | KC0_155_XYZW = 1510, |
1531 | | KC0_156_XYZW = 1511, |
1532 | | KC0_157_XYZW = 1512, |
1533 | | KC0_158_XYZW = 1513, |
1534 | | KC0_159_XYZW = 1514, |
1535 | | KC1_160_XYZW = 1515, |
1536 | | KC1_161_XYZW = 1516, |
1537 | | KC1_162_XYZW = 1517, |
1538 | | KC1_163_XYZW = 1518, |
1539 | | KC1_164_XYZW = 1519, |
1540 | | KC1_165_XYZW = 1520, |
1541 | | KC1_166_XYZW = 1521, |
1542 | | KC1_167_XYZW = 1522, |
1543 | | KC1_168_XYZW = 1523, |
1544 | | KC1_169_XYZW = 1524, |
1545 | | KC1_170_XYZW = 1525, |
1546 | | KC1_171_XYZW = 1526, |
1547 | | KC1_172_XYZW = 1527, |
1548 | | KC1_173_XYZW = 1528, |
1549 | | KC1_174_XYZW = 1529, |
1550 | | KC1_175_XYZW = 1530, |
1551 | | KC1_176_XYZW = 1531, |
1552 | | KC1_177_XYZW = 1532, |
1553 | | KC1_178_XYZW = 1533, |
1554 | | KC1_179_XYZW = 1534, |
1555 | | KC1_180_XYZW = 1535, |
1556 | | KC1_181_XYZW = 1536, |
1557 | | KC1_182_XYZW = 1537, |
1558 | | KC1_183_XYZW = 1538, |
1559 | | KC1_184_XYZW = 1539, |
1560 | | KC1_185_XYZW = 1540, |
1561 | | KC1_186_XYZW = 1541, |
1562 | | KC1_187_XYZW = 1542, |
1563 | | KC1_188_XYZW = 1543, |
1564 | | KC1_189_XYZW = 1544, |
1565 | | KC1_190_XYZW = 1545, |
1566 | | KC1_191_XYZW = 1546, |
1567 | | KC0_128_Y = 1547, |
1568 | | KC0_129_Y = 1548, |
1569 | | KC0_130_Y = 1549, |
1570 | | KC0_131_Y = 1550, |
1571 | | KC0_132_Y = 1551, |
1572 | | KC0_133_Y = 1552, |
1573 | | KC0_134_Y = 1553, |
1574 | | KC0_135_Y = 1554, |
1575 | | KC0_136_Y = 1555, |
1576 | | KC0_137_Y = 1556, |
1577 | | KC0_138_Y = 1557, |
1578 | | KC0_139_Y = 1558, |
1579 | | KC0_140_Y = 1559, |
1580 | | KC0_141_Y = 1560, |
1581 | | KC0_142_Y = 1561, |
1582 | | KC0_143_Y = 1562, |
1583 | | KC0_144_Y = 1563, |
1584 | | KC0_145_Y = 1564, |
1585 | | KC0_146_Y = 1565, |
1586 | | KC0_147_Y = 1566, |
1587 | | KC0_148_Y = 1567, |
1588 | | KC0_149_Y = 1568, |
1589 | | KC0_150_Y = 1569, |
1590 | | KC0_151_Y = 1570, |
1591 | | KC0_152_Y = 1571, |
1592 | | KC0_153_Y = 1572, |
1593 | | KC0_154_Y = 1573, |
1594 | | KC0_155_Y = 1574, |
1595 | | KC0_156_Y = 1575, |
1596 | | KC0_157_Y = 1576, |
1597 | | KC0_158_Y = 1577, |
1598 | | KC0_159_Y = 1578, |
1599 | | KC1_160_Y = 1579, |
1600 | | KC1_161_Y = 1580, |
1601 | | KC1_162_Y = 1581, |
1602 | | KC1_163_Y = 1582, |
1603 | | KC1_164_Y = 1583, |
1604 | | KC1_165_Y = 1584, |
1605 | | KC1_166_Y = 1585, |
1606 | | KC1_167_Y = 1586, |
1607 | | KC1_168_Y = 1587, |
1608 | | KC1_169_Y = 1588, |
1609 | | KC1_170_Y = 1589, |
1610 | | KC1_171_Y = 1590, |
1611 | | KC1_172_Y = 1591, |
1612 | | KC1_173_Y = 1592, |
1613 | | KC1_174_Y = 1593, |
1614 | | KC1_175_Y = 1594, |
1615 | | KC1_176_Y = 1595, |
1616 | | KC1_177_Y = 1596, |
1617 | | KC1_178_Y = 1597, |
1618 | | KC1_179_Y = 1598, |
1619 | | KC1_180_Y = 1599, |
1620 | | KC1_181_Y = 1600, |
1621 | | KC1_182_Y = 1601, |
1622 | | KC1_183_Y = 1602, |
1623 | | KC1_184_Y = 1603, |
1624 | | KC1_185_Y = 1604, |
1625 | | KC1_186_Y = 1605, |
1626 | | KC1_187_Y = 1606, |
1627 | | KC1_188_Y = 1607, |
1628 | | KC1_189_Y = 1608, |
1629 | | KC1_190_Y = 1609, |
1630 | | KC1_191_Y = 1610, |
1631 | | KC0_128_Z = 1611, |
1632 | | KC0_129_Z = 1612, |
1633 | | KC0_130_Z = 1613, |
1634 | | KC0_131_Z = 1614, |
1635 | | KC0_132_Z = 1615, |
1636 | | KC0_133_Z = 1616, |
1637 | | KC0_134_Z = 1617, |
1638 | | KC0_135_Z = 1618, |
1639 | | KC0_136_Z = 1619, |
1640 | | KC0_137_Z = 1620, |
1641 | | KC0_138_Z = 1621, |
1642 | | KC0_139_Z = 1622, |
1643 | | KC0_140_Z = 1623, |
1644 | | KC0_141_Z = 1624, |
1645 | | KC0_142_Z = 1625, |
1646 | | KC0_143_Z = 1626, |
1647 | | KC0_144_Z = 1627, |
1648 | | KC0_145_Z = 1628, |
1649 | | KC0_146_Z = 1629, |
1650 | | KC0_147_Z = 1630, |
1651 | | KC0_148_Z = 1631, |
1652 | | KC0_149_Z = 1632, |
1653 | | KC0_150_Z = 1633, |
1654 | | KC0_151_Z = 1634, |
1655 | | KC0_152_Z = 1635, |
1656 | | KC0_153_Z = 1636, |
1657 | | KC0_154_Z = 1637, |
1658 | | KC0_155_Z = 1638, |
1659 | | KC0_156_Z = 1639, |
1660 | | KC0_157_Z = 1640, |
1661 | | KC0_158_Z = 1641, |
1662 | | KC0_159_Z = 1642, |
1663 | | KC1_160_Z = 1643, |
1664 | | KC1_161_Z = 1644, |
1665 | | KC1_162_Z = 1645, |
1666 | | KC1_163_Z = 1646, |
1667 | | KC1_164_Z = 1647, |
1668 | | KC1_165_Z = 1648, |
1669 | | KC1_166_Z = 1649, |
1670 | | KC1_167_Z = 1650, |
1671 | | KC1_168_Z = 1651, |
1672 | | KC1_169_Z = 1652, |
1673 | | KC1_170_Z = 1653, |
1674 | | KC1_171_Z = 1654, |
1675 | | KC1_172_Z = 1655, |
1676 | | KC1_173_Z = 1656, |
1677 | | KC1_174_Z = 1657, |
1678 | | KC1_175_Z = 1658, |
1679 | | KC1_176_Z = 1659, |
1680 | | KC1_177_Z = 1660, |
1681 | | KC1_178_Z = 1661, |
1682 | | KC1_179_Z = 1662, |
1683 | | KC1_180_Z = 1663, |
1684 | | KC1_181_Z = 1664, |
1685 | | KC1_182_Z = 1665, |
1686 | | KC1_183_Z = 1666, |
1687 | | KC1_184_Z = 1667, |
1688 | | KC1_185_Z = 1668, |
1689 | | KC1_186_Z = 1669, |
1690 | | KC1_187_Z = 1670, |
1691 | | KC1_188_Z = 1671, |
1692 | | KC1_189_Z = 1672, |
1693 | | KC1_190_Z = 1673, |
1694 | | KC1_191_Z = 1674, |
1695 | | NUM_TARGET_REGS // 1675 |
1696 | | }; |
1697 | | } // end namespace R600 |
1698 | | |
1699 | | // Register classes |
1700 | | |
1701 | | namespace R600 { |
1702 | | enum { |
1703 | | R600_Reg32RegClassID = 0, |
1704 | | R600_TReg32RegClassID = 1, |
1705 | | R600_TReg32_XRegClassID = 2, |
1706 | | R600_AddrRegClassID = 3, |
1707 | | R600_KC0RegClassID = 4, |
1708 | | R600_KC1RegClassID = 5, |
1709 | | R600_TReg32_WRegClassID = 6, |
1710 | | R600_TReg32_YRegClassID = 7, |
1711 | | R600_TReg32_ZRegClassID = 8, |
1712 | | R600_ArrayBaseRegClassID = 9, |
1713 | | R600_KC0_WRegClassID = 10, |
1714 | | R600_KC0_XRegClassID = 11, |
1715 | | R600_KC0_YRegClassID = 12, |
1716 | | R600_KC0_ZRegClassID = 13, |
1717 | | R600_KC1_WRegClassID = 14, |
1718 | | R600_KC1_XRegClassID = 15, |
1719 | | R600_KC1_YRegClassID = 16, |
1720 | | R600_KC1_ZRegClassID = 17, |
1721 | | R600_LDS_SRC_REGRegClassID = 18, |
1722 | | R600_PredicateRegClassID = 19, |
1723 | | R600_Addr_WRegClassID = 20, |
1724 | | R600_Addr_YRegClassID = 21, |
1725 | | R600_Addr_ZRegClassID = 22, |
1726 | | R600_LDS_SRC_REG_and_R600_Reg32RegClassID = 23, |
1727 | | R600_Predicate_BitRegClassID = 24, |
1728 | | R600_Reg64RegClassID = 25, |
1729 | | R600_Reg64VerticalRegClassID = 26, |
1730 | | R600_Reg64Vertical_with_sub0_in_R600_TReg32_WRegClassID = 27, |
1731 | | R600_Reg64Vertical_with_sub0_in_R600_TReg32_XRegClassID = 28, |
1732 | | R600_Reg64Vertical_with_sub0_in_R600_TReg32_YRegClassID = 29, |
1733 | | R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZRegClassID = 30, |
1734 | | R600_Reg128RegClassID = 31, |
1735 | | R600_Reg128VerticalRegClassID = 32, |
1736 | | R600_Reg128Vertical_with_sub0_in_R600_TReg32_WRegClassID = 33, |
1737 | | R600_Reg128Vertical_with_sub0_in_R600_TReg32_XRegClassID = 34, |
1738 | | R600_Reg128Vertical_with_sub0_in_R600_TReg32_YRegClassID = 35, |
1739 | | R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZRegClassID = 36, |
1740 | | |
1741 | | }; |
1742 | | } // end namespace R600 |
1743 | | |
1744 | | |
1745 | | // Subregister indices |
1746 | | |
1747 | | namespace R600 { |
1748 | | enum : uint16_t { |
1749 | | NoSubRegister, |
1750 | | sub0, // 1 |
1751 | | sub1, // 2 |
1752 | | sub2, // 3 |
1753 | | sub3, // 4 |
1754 | | sub4, // 5 |
1755 | | sub5, // 6 |
1756 | | sub6, // 7 |
1757 | | sub7, // 8 |
1758 | | sub8, // 9 |
1759 | | sub9, // 10 |
1760 | | sub10, // 11 |
1761 | | sub11, // 12 |
1762 | | sub12, // 13 |
1763 | | sub13, // 14 |
1764 | | sub14, // 15 |
1765 | | sub15, // 16 |
1766 | | NUM_TARGET_SUBREGS |
1767 | | }; |
1768 | | } // end namespace R600 |
1769 | | |
1770 | | // Register pressure sets enum. |
1771 | | namespace R600 { |
1772 | | enum RegisterPressureSets { |
1773 | | R600_LDS_SRC_REG_and_R600_Reg32 = 0, |
1774 | | R600_Predicate_Bit = 1, |
1775 | | R600_Predicate = 2, |
1776 | | R600_Reg64Vertical_with_sub0_in_R600_TReg32_W = 3, |
1777 | | R600_Reg64Vertical_with_sub0_in_R600_TReg32_X = 4, |
1778 | | R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y = 5, |
1779 | | R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z = 6, |
1780 | | R600_Reg64Vertical = 7, |
1781 | | R600_ArrayBase = 8, |
1782 | | R600_TReg32_W = 9, |
1783 | | R600_TReg32_Y = 10, |
1784 | | R600_TReg32_Z = 11, |
1785 | | R600_Reg64 = 12, |
1786 | | R600_TReg32_X = 13, |
1787 | | R600_Reg64_with_R600_Reg64Vertical = 14, |
1788 | | R600_TReg32_W_with_R600_Reg64Vertical = 15, |
1789 | | R600_TReg32_Y_with_R600_Reg64Vertical = 16, |
1790 | | R600_TReg32_Z_with_R600_Reg64Vertical = 17, |
1791 | | R600_TReg32_X_with_R600_Reg64Vertical = 18, |
1792 | | R600_TReg32_Y_with_R600_Reg64 = 19, |
1793 | | R600_TReg32_X_with_R600_Reg64 = 20, |
1794 | | R600_TReg32 = 21, |
1795 | | R600_Reg32 = 22, |
1796 | | }; |
1797 | | } // end namespace R600 |
1798 | | |
1799 | | } // end namespace llvm |
1800 | | |
1801 | | #endif // GET_REGINFO_ENUM |
1802 | | |
1803 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
1804 | | |* *| |
1805 | | |* MC Register Information *| |
1806 | | |* *| |
1807 | | |* Automatically generated file, do not edit! *| |
1808 | | |* *| |
1809 | | \*===----------------------------------------------------------------------===*/ |
1810 | | |
1811 | | |
1812 | | #ifdef GET_REGINFO_MC_DESC |
1813 | | #undef GET_REGINFO_MC_DESC |
1814 | | |
1815 | | namespace llvm { |
1816 | | |
1817 | | extern const int16_t R600RegDiffLists[] = { |
1818 | | /* 0 */ -256, 384, 128, -640, 0, |
1819 | | /* 5 */ -64, 128, 64, -256, 0, |
1820 | | /* 10 */ -128, 0, |
1821 | | /* 12 */ -64, 0, |
1822 | | /* 14 */ -768, 1, 0, |
1823 | | /* 17 */ -767, 1, 0, |
1824 | | /* 20 */ -643, 1, 0, |
1825 | | /* 23 */ -642, 1, 0, |
1826 | | /* 26 */ -262, 1, 0, |
1827 | | /* 29 */ -261, 1, 0, |
1828 | | /* 32 */ -137, 1, 0, |
1829 | | /* 35 */ -136, 1, 0, |
1830 | | /* 38 */ -770, 1, 1, 1, 0, |
1831 | | /* 43 */ -645, 1, 1, 1, 0, |
1832 | | /* 48 */ -264, 1, 1, 1, 0, |
1833 | | /* 53 */ -139, 1, 1, 1, 0, |
1834 | | /* 58 */ 64, 64, 1, 0, |
1835 | | /* 62 */ 64, 65, 1, 0, |
1836 | | /* 66 */ 64, 66, 1, 0, |
1837 | | /* 70 */ 64, 67, 1, 0, |
1838 | | /* 74 */ 64, 68, 1, 0, |
1839 | | /* 78 */ 64, 69, 1, 0, |
1840 | | /* 82 */ 64, 70, 1, 0, |
1841 | | /* 86 */ 64, 71, 1, 0, |
1842 | | /* 90 */ 64, 72, 1, 0, |
1843 | | /* 94 */ 64, 73, 1, 0, |
1844 | | /* 98 */ 64, 74, 1, 0, |
1845 | | /* 102 */ 64, 75, 1, 0, |
1846 | | /* 106 */ 64, 76, 1, 0, |
1847 | | /* 110 */ 64, 77, 1, 0, |
1848 | | /* 114 */ 64, 78, 1, 0, |
1849 | | /* 118 */ 64, 79, 1, 0, |
1850 | | /* 122 */ 64, 80, 1, 0, |
1851 | | /* 126 */ 64, 81, 1, 0, |
1852 | | /* 130 */ 64, 82, 1, 0, |
1853 | | /* 134 */ 64, 83, 1, 0, |
1854 | | /* 138 */ 64, 84, 1, 0, |
1855 | | /* 142 */ 64, 85, 1, 0, |
1856 | | /* 146 */ 64, 86, 1, 0, |
1857 | | /* 150 */ 64, 87, 1, 0, |
1858 | | /* 154 */ 64, 88, 1, 0, |
1859 | | /* 158 */ 64, 89, 1, 0, |
1860 | | /* 162 */ 64, 90, 1, 0, |
1861 | | /* 166 */ 64, 91, 1, 0, |
1862 | | /* 170 */ 64, 92, 1, 0, |
1863 | | /* 174 */ 64, 93, 1, 0, |
1864 | | /* 178 */ 64, 94, 1, 0, |
1865 | | /* 182 */ 64, 95, 1, 0, |
1866 | | /* 186 */ 64, 96, 1, 0, |
1867 | | /* 190 */ 64, 97, 1, 0, |
1868 | | /* 194 */ 64, 98, 1, 0, |
1869 | | /* 198 */ 64, 99, 1, 0, |
1870 | | /* 202 */ 64, 100, 1, 0, |
1871 | | /* 206 */ 64, 101, 1, 0, |
1872 | | /* 210 */ 64, 102, 1, 0, |
1873 | | /* 214 */ 64, 103, 1, 0, |
1874 | | /* 218 */ 64, 104, 1, 0, |
1875 | | /* 222 */ 64, 105, 1, 0, |
1876 | | /* 226 */ 64, 106, 1, 0, |
1877 | | /* 230 */ 64, 107, 1, 0, |
1878 | | /* 234 */ 64, 108, 1, 0, |
1879 | | /* 238 */ 64, 109, 1, 0, |
1880 | | /* 242 */ 64, 110, 1, 0, |
1881 | | /* 246 */ 64, 111, 1, 0, |
1882 | | /* 250 */ 64, 112, 1, 0, |
1883 | | /* 254 */ 64, 113, 1, 0, |
1884 | | /* 258 */ 64, 114, 1, 0, |
1885 | | /* 262 */ 64, 115, 1, 0, |
1886 | | /* 266 */ 64, 116, 1, 0, |
1887 | | /* 270 */ 64, 117, 1, 0, |
1888 | | /* 274 */ 64, 118, 1, 0, |
1889 | | /* 278 */ 64, 119, 1, 0, |
1890 | | /* 282 */ 64, 120, 1, 0, |
1891 | | /* 286 */ 64, 121, 1, 0, |
1892 | | /* 290 */ 64, 122, 1, 0, |
1893 | | /* 294 */ 64, 123, 1, 0, |
1894 | | /* 298 */ 64, 124, 1, 0, |
1895 | | /* 302 */ 64, 125, 1, 0, |
1896 | | /* 306 */ 64, 126, 1, 0, |
1897 | | /* 310 */ 64, 127, 1, 0, |
1898 | | /* 314 */ 384, 382, 1, 0, |
1899 | | /* 318 */ 384, 383, 1, 0, |
1900 | | /* 322 */ 128, 128, 385, 1, 0, |
1901 | | /* 327 */ 128, 128, 386, 1, 0, |
1902 | | /* 332 */ -256, 128, 388, 1, 0, |
1903 | | /* 337 */ -256, 128, 389, 1, 0, |
1904 | | /* 342 */ -256, 391, 1, 0, |
1905 | | /* 346 */ -256, 392, 1, 0, |
1906 | | /* 350 */ 384, 383, 2, 0, |
1907 | | /* 354 */ 384, 384, 2, 0, |
1908 | | /* 358 */ 128, 128, 386, 2, 0, |
1909 | | /* 363 */ 128, 128, 387, 2, 0, |
1910 | | /* 368 */ -256, 128, 389, 2, 0, |
1911 | | /* 373 */ -256, 128, 390, 2, 0, |
1912 | | /* 378 */ -256, 392, 2, 0, |
1913 | | /* 382 */ -256, 393, 2, 0, |
1914 | | /* 386 */ 64, 0, |
1915 | | /* 388 */ -256, 128, 0, |
1916 | | /* 391 */ 128, 128, 128, 0, |
1917 | | /* 395 */ -128, 384, 0, |
1918 | | }; |
1919 | | |
1920 | | extern const LaneBitmask R600LaneMaskLists[] = { |
1921 | | /* 0 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), LaneBitmask::getAll(), |
1922 | | /* 3 */ LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask::getAll(), |
1923 | | /* 8 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask::getAll(), |
1924 | | /* 13 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(), |
1925 | | }; |
1926 | | |
1927 | | extern const uint16_t R600SubRegIdxLists[] = { |
1928 | | /* 0 */ 1, 2, 0, |
1929 | | /* 3 */ 1, 2, 3, 4, 0, |
1930 | | }; |
1931 | | |
1932 | | extern const MCRegisterInfo::SubRegCoveredBits R600SubRegIdxRanges[] = { |
1933 | | { 65535, 65535 }, |
1934 | | { 0, 32 }, // sub0 |
1935 | | { 32, 32 }, // sub1 |
1936 | | { 64, 32 }, // sub2 |
1937 | | { 96, 32 }, // sub3 |
1938 | | { 128, 32 }, // sub4 |
1939 | | { 160, 32 }, // sub5 |
1940 | | { 192, 32 }, // sub6 |
1941 | | { 224, 32 }, // sub7 |
1942 | | { 256, 32 }, // sub8 |
1943 | | { 288, 32 }, // sub9 |
1944 | | { 320, 32 }, // sub10 |
1945 | | { 352, 32 }, // sub11 |
1946 | | { 384, 32 }, // sub12 |
1947 | | { 416, 32 }, // sub13 |
1948 | | { 448, 32 }, // sub14 |
1949 | | { 480, 32 }, // sub15 |
1950 | | }; |
1951 | | |
1952 | | |
1953 | | #ifdef __GNUC__ |
1954 | | #pragma GCC diagnostic push |
1955 | | #pragma GCC diagnostic ignored "-Woverlength-strings" |
1956 | | #endif |
1957 | | extern const char R600RegStrings[] = { |
1958 | | /* 0 */ "ArrayBase450\0" |
1959 | | /* 13 */ "ArrayBase460\0" |
1960 | | /* 26 */ "ArrayBase470\0" |
1961 | | /* 39 */ "ArrayBase480\0" |
1962 | | /* 52 */ "ArrayBase451\0" |
1963 | | /* 65 */ "ArrayBase461\0" |
1964 | | /* 78 */ "ArrayBase471\0" |
1965 | | /* 91 */ "ArrayBase452\0" |
1966 | | /* 104 */ "ArrayBase462\0" |
1967 | | /* 117 */ "ArrayBase472\0" |
1968 | | /* 130 */ "ArrayBase453\0" |
1969 | | /* 143 */ "ArrayBase463\0" |
1970 | | /* 156 */ "ArrayBase473\0" |
1971 | | /* 169 */ "ArrayBase454\0" |
1972 | | /* 182 */ "ArrayBase464\0" |
1973 | | /* 195 */ "ArrayBase474\0" |
1974 | | /* 208 */ "ArrayBase455\0" |
1975 | | /* 221 */ "ArrayBase465\0" |
1976 | | /* 234 */ "ArrayBase475\0" |
1977 | | /* 247 */ "ArrayBase456\0" |
1978 | | /* 260 */ "ArrayBase466\0" |
1979 | | /* 273 */ "ArrayBase476\0" |
1980 | | /* 286 */ "ArrayBase457\0" |
1981 | | /* 299 */ "ArrayBase467\0" |
1982 | | /* 312 */ "ArrayBase477\0" |
1983 | | /* 325 */ "ArrayBase448\0" |
1984 | | /* 338 */ "ArrayBase458\0" |
1985 | | /* 351 */ "ArrayBase468\0" |
1986 | | /* 364 */ "ArrayBase478\0" |
1987 | | /* 377 */ "ArrayBase449\0" |
1988 | | /* 390 */ "ArrayBase459\0" |
1989 | | /* 403 */ "ArrayBase469\0" |
1990 | | /* 416 */ "ArrayBase479\0" |
1991 | | /* 429 */ "OQA\0" |
1992 | | /* 433 */ "LDS_DIRECT_A\0" |
1993 | | /* 446 */ "OQB\0" |
1994 | | /* 450 */ "LDS_DIRECT_B\0" |
1995 | | /* 463 */ "NEG_ONE\0" |
1996 | | /* 471 */ "PRED_SEL_ONE\0" |
1997 | | /* 484 */ "PRED_SEL_OFF\0" |
1998 | | /* 497 */ "NEG_HALF\0" |
1999 | | /* 506 */ "ALU_PARAM\0" |
2000 | | /* 516 */ "PRED_SEL_ZERO\0" |
2001 | | /* 530 */ "OQAP\0" |
2002 | | /* 535 */ "OQBP\0" |
2003 | | /* 540 */ "INDIRECT_BASE_ADDR\0" |
2004 | | /* 559 */ "PS\0" |
2005 | | /* 562 */ "PREDICATE_BIT\0" |
2006 | | /* 576 */ "ONE_INT\0" |
2007 | | /* 584 */ "ALU_CONST\0" |
2008 | | /* 594 */ "T100_XYZW\0" |
2009 | | /* 604 */ "T110_XYZW\0" |
2010 | | /* 614 */ "T10_XYZW\0" |
2011 | | /* 623 */ "T120_XYZW\0" |
2012 | | /* 633 */ "T20_XYZW\0" |
2013 | | /* 642 */ "KC0_130_XYZW\0" |
2014 | | /* 655 */ "T30_XYZW\0" |
2015 | | /* 664 */ "KC0_140_XYZW\0" |
2016 | | /* 677 */ "T40_XYZW\0" |
2017 | | /* 686 */ "KC0_150_XYZW\0" |
2018 | | /* 699 */ "T50_XYZW\0" |
2019 | | /* 708 */ "KC1_160_XYZW\0" |
2020 | | /* 721 */ "T60_XYZW\0" |
2021 | | /* 730 */ "KC1_170_XYZW\0" |
2022 | | /* 743 */ "T70_XYZW\0" |
2023 | | /* 752 */ "KC1_180_XYZW\0" |
2024 | | /* 765 */ "T80_XYZW\0" |
2025 | | /* 774 */ "KC1_190_XYZW\0" |
2026 | | /* 787 */ "T90_XYZW\0" |
2027 | | /* 796 */ "T0_XYZW\0" |
2028 | | /* 804 */ "T101_XYZW\0" |
2029 | | /* 814 */ "T111_XYZW\0" |
2030 | | /* 824 */ "T11_XYZW\0" |
2031 | | /* 833 */ "T121_XYZW\0" |
2032 | | /* 843 */ "T21_XYZW\0" |
2033 | | /* 852 */ "KC0_131_XYZW\0" |
2034 | | /* 865 */ "T31_XYZW\0" |
2035 | | /* 874 */ "KC0_141_XYZW\0" |
2036 | | /* 887 */ "T41_XYZW\0" |
2037 | | /* 896 */ "KC0_151_XYZW\0" |
2038 | | /* 909 */ "T51_XYZW\0" |
2039 | | /* 918 */ "KC1_161_XYZW\0" |
2040 | | /* 931 */ "T61_XYZW\0" |
2041 | | /* 940 */ "KC1_171_XYZW\0" |
2042 | | /* 953 */ "T71_XYZW\0" |
2043 | | /* 962 */ "KC1_181_XYZW\0" |
2044 | | /* 975 */ "T81_XYZW\0" |
2045 | | /* 984 */ "KC1_191_XYZW\0" |
2046 | | /* 997 */ "T91_XYZW\0" |
2047 | | /* 1006 */ "T1_XYZW\0" |
2048 | | /* 1014 */ "T102_XYZW\0" |
2049 | | /* 1024 */ "T112_XYZW\0" |
2050 | | /* 1034 */ "T12_XYZW\0" |
2051 | | /* 1043 */ "T122_XYZW\0" |
2052 | | /* 1053 */ "T22_XYZW\0" |
2053 | | /* 1062 */ "KC0_132_XYZW\0" |
2054 | | /* 1075 */ "T32_XYZW\0" |
2055 | | /* 1084 */ "KC0_142_XYZW\0" |
2056 | | /* 1097 */ "T42_XYZW\0" |
2057 | | /* 1106 */ "KC0_152_XYZW\0" |
2058 | | /* 1119 */ "T52_XYZW\0" |
2059 | | /* 1128 */ "KC1_162_XYZW\0" |
2060 | | /* 1141 */ "T62_XYZW\0" |
2061 | | /* 1150 */ "KC1_172_XYZW\0" |
2062 | | /* 1163 */ "T72_XYZW\0" |
2063 | | /* 1172 */ "KC1_182_XYZW\0" |
2064 | | /* 1185 */ "T82_XYZW\0" |
2065 | | /* 1194 */ "T92_XYZW\0" |
2066 | | /* 1203 */ "T2_XYZW\0" |
2067 | | /* 1211 */ "T103_XYZW\0" |
2068 | | /* 1221 */ "T113_XYZW\0" |
2069 | | /* 1231 */ "T13_XYZW\0" |
2070 | | /* 1240 */ "T123_XYZW\0" |
2071 | | /* 1250 */ "T23_XYZW\0" |
2072 | | /* 1259 */ "KC0_133_XYZW\0" |
2073 | | /* 1272 */ "T33_XYZW\0" |
2074 | | /* 1281 */ "KC0_143_XYZW\0" |
2075 | | /* 1294 */ "T43_XYZW\0" |
2076 | | /* 1303 */ "KC0_153_XYZW\0" |
2077 | | /* 1316 */ "T53_XYZW\0" |
2078 | | /* 1325 */ "KC1_163_XYZW\0" |
2079 | | /* 1338 */ "T63_XYZW\0" |
2080 | | /* 1347 */ "KC1_173_XYZW\0" |
2081 | | /* 1360 */ "T73_XYZW\0" |
2082 | | /* 1369 */ "KC1_183_XYZW\0" |
2083 | | /* 1382 */ "T83_XYZW\0" |
2084 | | /* 1391 */ "T93_XYZW\0" |
2085 | | /* 1400 */ "T3_XYZW\0" |
2086 | | /* 1408 */ "T104_XYZW\0" |
2087 | | /* 1418 */ "T114_XYZW\0" |
2088 | | /* 1428 */ "T14_XYZW\0" |
2089 | | /* 1437 */ "T124_XYZW\0" |
2090 | | /* 1447 */ "T24_XYZW\0" |
2091 | | /* 1456 */ "KC0_134_XYZW\0" |
2092 | | /* 1469 */ "T34_XYZW\0" |
2093 | | /* 1478 */ "KC0_144_XYZW\0" |
2094 | | /* 1491 */ "T44_XYZW\0" |
2095 | | /* 1500 */ "KC0_154_XYZW\0" |
2096 | | /* 1513 */ "T54_XYZW\0" |
2097 | | /* 1522 */ "KC1_164_XYZW\0" |
2098 | | /* 1535 */ "T64_XYZW\0" |
2099 | | /* 1544 */ "KC1_174_XYZW\0" |
2100 | | /* 1557 */ "T74_XYZW\0" |
2101 | | /* 1566 */ "KC1_184_XYZW\0" |
2102 | | /* 1579 */ "T84_XYZW\0" |
2103 | | /* 1588 */ "T94_XYZW\0" |
2104 | | /* 1597 */ "T4_XYZW\0" |
2105 | | /* 1605 */ "T105_XYZW\0" |
2106 | | /* 1615 */ "T115_XYZW\0" |
2107 | | /* 1625 */ "T15_XYZW\0" |
2108 | | /* 1634 */ "T125_XYZW\0" |
2109 | | /* 1644 */ "T25_XYZW\0" |
2110 | | /* 1653 */ "KC0_135_XYZW\0" |
2111 | | /* 1666 */ "T35_XYZW\0" |
2112 | | /* 1675 */ "KC0_145_XYZW\0" |
2113 | | /* 1688 */ "T45_XYZW\0" |
2114 | | /* 1697 */ "KC0_155_XYZW\0" |
2115 | | /* 1710 */ "T55_XYZW\0" |
2116 | | /* 1719 */ "KC1_165_XYZW\0" |
2117 | | /* 1732 */ "T65_XYZW\0" |
2118 | | /* 1741 */ "KC1_175_XYZW\0" |
2119 | | /* 1754 */ "T75_XYZW\0" |
2120 | | /* 1763 */ "KC1_185_XYZW\0" |
2121 | | /* 1776 */ "T85_XYZW\0" |
2122 | | /* 1785 */ "T95_XYZW\0" |
2123 | | /* 1794 */ "T5_XYZW\0" |
2124 | | /* 1802 */ "T106_XYZW\0" |
2125 | | /* 1812 */ "T116_XYZW\0" |
2126 | | /* 1822 */ "T16_XYZW\0" |
2127 | | /* 1831 */ "T126_XYZW\0" |
2128 | | /* 1841 */ "T26_XYZW\0" |
2129 | | /* 1850 */ "KC0_136_XYZW\0" |
2130 | | /* 1863 */ "T36_XYZW\0" |
2131 | | /* 1872 */ "KC0_146_XYZW\0" |
2132 | | /* 1885 */ "T46_XYZW\0" |
2133 | | /* 1894 */ "KC0_156_XYZW\0" |
2134 | | /* 1907 */ "T56_XYZW\0" |
2135 | | /* 1916 */ "KC1_166_XYZW\0" |
2136 | | /* 1929 */ "T66_XYZW\0" |
2137 | | /* 1938 */ "KC1_176_XYZW\0" |
2138 | | /* 1951 */ "T76_XYZW\0" |
2139 | | /* 1960 */ "KC1_186_XYZW\0" |
2140 | | /* 1973 */ "T86_XYZW\0" |
2141 | | /* 1982 */ "T96_XYZW\0" |
2142 | | /* 1991 */ "T6_XYZW\0" |
2143 | | /* 1999 */ "T107_XYZW\0" |
2144 | | /* 2009 */ "T117_XYZW\0" |
2145 | | /* 2019 */ "T17_XYZW\0" |
2146 | | /* 2028 */ "T127_XYZW\0" |
2147 | | /* 2038 */ "T27_XYZW\0" |
2148 | | /* 2047 */ "KC0_137_XYZW\0" |
2149 | | /* 2060 */ "T37_XYZW\0" |
2150 | | /* 2069 */ "KC0_147_XYZW\0" |
2151 | | /* 2082 */ "T47_XYZW\0" |
2152 | | /* 2091 */ "KC0_157_XYZW\0" |
2153 | | /* 2104 */ "T57_XYZW\0" |
2154 | | /* 2113 */ "KC1_167_XYZW\0" |
2155 | | /* 2126 */ "T67_XYZW\0" |
2156 | | /* 2135 */ "KC1_177_XYZW\0" |
2157 | | /* 2148 */ "T77_XYZW\0" |
2158 | | /* 2157 */ "KC1_187_XYZW\0" |
2159 | | /* 2170 */ "T87_XYZW\0" |
2160 | | /* 2179 */ "T97_XYZW\0" |
2161 | | /* 2188 */ "T7_XYZW\0" |
2162 | | /* 2196 */ "T108_XYZW\0" |
2163 | | /* 2206 */ "T118_XYZW\0" |
2164 | | /* 2216 */ "T18_XYZW\0" |
2165 | | /* 2225 */ "KC0_128_XYZW\0" |
2166 | | /* 2238 */ "T28_XYZW\0" |
2167 | | /* 2247 */ "KC0_138_XYZW\0" |
2168 | | /* 2260 */ "T38_XYZW\0" |
2169 | | /* 2269 */ "KC0_148_XYZW\0" |
2170 | | /* 2282 */ "T48_XYZW\0" |
2171 | | /* 2291 */ "KC0_158_XYZW\0" |
2172 | | /* 2304 */ "T58_XYZW\0" |
2173 | | /* 2313 */ "KC1_168_XYZW\0" |
2174 | | /* 2326 */ "T68_XYZW\0" |
2175 | | /* 2335 */ "KC1_178_XYZW\0" |
2176 | | /* 2348 */ "T78_XYZW\0" |
2177 | | /* 2357 */ "KC1_188_XYZW\0" |
2178 | | /* 2370 */ "T88_XYZW\0" |
2179 | | /* 2379 */ "T98_XYZW\0" |
2180 | | /* 2388 */ "T8_XYZW\0" |
2181 | | /* 2396 */ "T109_XYZW\0" |
2182 | | /* 2406 */ "T119_XYZW\0" |
2183 | | /* 2416 */ "T19_XYZW\0" |
2184 | | /* 2425 */ "KC0_129_XYZW\0" |
2185 | | /* 2438 */ "T29_XYZW\0" |
2186 | | /* 2447 */ "KC0_139_XYZW\0" |
2187 | | /* 2460 */ "T39_XYZW\0" |
2188 | | /* 2469 */ "KC0_149_XYZW\0" |
2189 | | /* 2482 */ "T49_XYZW\0" |
2190 | | /* 2491 */ "KC0_159_XYZW\0" |
2191 | | /* 2504 */ "T59_XYZW\0" |
2192 | | /* 2513 */ "KC1_169_XYZW\0" |
2193 | | /* 2526 */ "T69_XYZW\0" |
2194 | | /* 2535 */ "KC1_179_XYZW\0" |
2195 | | /* 2548 */ "T79_XYZW\0" |
2196 | | /* 2557 */ "KC1_189_XYZW\0" |
2197 | | /* 2570 */ "T89_XYZW\0" |
2198 | | /* 2579 */ "T99_XYZW\0" |
2199 | | /* 2588 */ "T9_XYZW\0" |
2200 | | /* 2596 */ "T100_W\0" |
2201 | | /* 2603 */ "Addr100_W\0" |
2202 | | /* 2613 */ "T110_W\0" |
2203 | | /* 2620 */ "Addr110_W\0" |
2204 | | /* 2630 */ "T10_W\0" |
2205 | | /* 2636 */ "Addr10_W\0" |
2206 | | /* 2645 */ "T120_W\0" |
2207 | | /* 2652 */ "Addr120_W\0" |
2208 | | /* 2662 */ "T20_W\0" |
2209 | | /* 2668 */ "Addr20_W\0" |
2210 | | /* 2677 */ "KC0_130_W\0" |
2211 | | /* 2687 */ "T30_W\0" |
2212 | | /* 2693 */ "Addr30_W\0" |
2213 | | /* 2702 */ "KC0_140_W\0" |
2214 | | /* 2712 */ "T40_W\0" |
2215 | | /* 2718 */ "Addr40_W\0" |
2216 | | /* 2727 */ "KC0_150_W\0" |
2217 | | /* 2737 */ "T50_W\0" |
2218 | | /* 2743 */ "Addr50_W\0" |
2219 | | /* 2752 */ "KC1_160_W\0" |
2220 | | /* 2762 */ "T60_W\0" |
2221 | | /* 2768 */ "Addr60_W\0" |
2222 | | /* 2777 */ "KC1_170_W\0" |
2223 | | /* 2787 */ "T70_W\0" |
2224 | | /* 2793 */ "Addr70_W\0" |
2225 | | /* 2802 */ "KC1_180_W\0" |
2226 | | /* 2812 */ "T80_W\0" |
2227 | | /* 2818 */ "Addr80_W\0" |
2228 | | /* 2827 */ "KC1_190_W\0" |
2229 | | /* 2837 */ "T90_W\0" |
2230 | | /* 2843 */ "Addr90_W\0" |
2231 | | /* 2852 */ "T0_W\0" |
2232 | | /* 2857 */ "Addr0_W\0" |
2233 | | /* 2865 */ "T101_W\0" |
2234 | | /* 2872 */ "Addr101_W\0" |
2235 | | /* 2882 */ "V01_W\0" |
2236 | | /* 2888 */ "T111_W\0" |
2237 | | /* 2895 */ "Addr111_W\0" |
2238 | | /* 2905 */ "T11_W\0" |
2239 | | /* 2911 */ "Addr11_W\0" |
2240 | | /* 2920 */ "T121_W\0" |
2241 | | /* 2927 */ "Addr121_W\0" |
2242 | | /* 2937 */ "T21_W\0" |
2243 | | /* 2943 */ "Addr21_W\0" |
2244 | | /* 2952 */ "KC0_131_W\0" |
2245 | | /* 2962 */ "T31_W\0" |
2246 | | /* 2968 */ "Addr31_W\0" |
2247 | | /* 2977 */ "KC0_141_W\0" |
2248 | | /* 2987 */ "T41_W\0" |
2249 | | /* 2993 */ "Addr41_W\0" |
2250 | | /* 3002 */ "KC0_151_W\0" |
2251 | | /* 3012 */ "T51_W\0" |
2252 | | /* 3018 */ "Addr51_W\0" |
2253 | | /* 3027 */ "KC1_161_W\0" |
2254 | | /* 3037 */ "T61_W\0" |
2255 | | /* 3043 */ "Addr61_W\0" |
2256 | | /* 3052 */ "KC1_171_W\0" |
2257 | | /* 3062 */ "T71_W\0" |
2258 | | /* 3068 */ "Addr71_W\0" |
2259 | | /* 3077 */ "KC1_181_W\0" |
2260 | | /* 3087 */ "T81_W\0" |
2261 | | /* 3093 */ "Addr81_W\0" |
2262 | | /* 3102 */ "KC1_191_W\0" |
2263 | | /* 3112 */ "T91_W\0" |
2264 | | /* 3118 */ "Addr91_W\0" |
2265 | | /* 3127 */ "T1_W\0" |
2266 | | /* 3132 */ "Addr1_W\0" |
2267 | | /* 3140 */ "T102_W\0" |
2268 | | /* 3147 */ "Addr102_W\0" |
2269 | | /* 3157 */ "T112_W\0" |
2270 | | /* 3164 */ "Addr112_W\0" |
2271 | | /* 3174 */ "T12_W\0" |
2272 | | /* 3180 */ "Addr12_W\0" |
2273 | | /* 3189 */ "T122_W\0" |
2274 | | /* 3196 */ "Addr122_W\0" |
2275 | | /* 3206 */ "T22_W\0" |
2276 | | /* 3212 */ "Addr22_W\0" |
2277 | | /* 3221 */ "KC0_132_W\0" |
2278 | | /* 3231 */ "T32_W\0" |
2279 | | /* 3237 */ "Addr32_W\0" |
2280 | | /* 3246 */ "KC0_142_W\0" |
2281 | | /* 3256 */ "T42_W\0" |
2282 | | /* 3262 */ "Addr42_W\0" |
2283 | | /* 3271 */ "KC0_152_W\0" |
2284 | | /* 3281 */ "T52_W\0" |
2285 | | /* 3287 */ "Addr52_W\0" |
2286 | | /* 3296 */ "KC1_162_W\0" |
2287 | | /* 3306 */ "T62_W\0" |
2288 | | /* 3312 */ "Addr62_W\0" |
2289 | | /* 3321 */ "KC1_172_W\0" |
2290 | | /* 3331 */ "T72_W\0" |
2291 | | /* 3337 */ "Addr72_W\0" |
2292 | | /* 3346 */ "KC1_182_W\0" |
2293 | | /* 3356 */ "T82_W\0" |
2294 | | /* 3362 */ "Addr82_W\0" |
2295 | | /* 3371 */ "T92_W\0" |
2296 | | /* 3377 */ "Addr92_W\0" |
2297 | | /* 3386 */ "T2_W\0" |
2298 | | /* 3391 */ "Addr2_W\0" |
2299 | | /* 3399 */ "T103_W\0" |
2300 | | /* 3406 */ "Addr103_W\0" |
2301 | | /* 3416 */ "T113_W\0" |
2302 | | /* 3423 */ "Addr113_W\0" |
2303 | | /* 3433 */ "T13_W\0" |
2304 | | /* 3439 */ "Addr13_W\0" |
2305 | | /* 3448 */ "V0123_W\0" |
2306 | | /* 3456 */ "T123_W\0" |
2307 | | /* 3463 */ "Addr123_W\0" |
2308 | | /* 3473 */ "T23_W\0" |
2309 | | /* 3479 */ "V23_W\0" |
2310 | | /* 3485 */ "Addr23_W\0" |
2311 | | /* 3494 */ "KC0_133_W\0" |
2312 | | /* 3504 */ "T33_W\0" |
2313 | | /* 3510 */ "Addr33_W\0" |
2314 | | /* 3519 */ "KC0_143_W\0" |
2315 | | /* 3529 */ "T43_W\0" |
2316 | | /* 3535 */ "Addr43_W\0" |
2317 | | /* 3544 */ "KC0_153_W\0" |
2318 | | /* 3554 */ "T53_W\0" |
2319 | | /* 3560 */ "Addr53_W\0" |
2320 | | /* 3569 */ "KC1_163_W\0" |
2321 | | /* 3579 */ "T63_W\0" |
2322 | | /* 3585 */ "Addr63_W\0" |
2323 | | /* 3594 */ "KC1_173_W\0" |
2324 | | /* 3604 */ "T73_W\0" |
2325 | | /* 3610 */ "Addr73_W\0" |
2326 | | /* 3619 */ "KC1_183_W\0" |
2327 | | /* 3629 */ "T83_W\0" |
2328 | | /* 3635 */ "Addr83_W\0" |
2329 | | /* 3644 */ "T93_W\0" |
2330 | | /* 3650 */ "Addr93_W\0" |
2331 | | /* 3659 */ "T3_W\0" |
2332 | | /* 3664 */ "Addr3_W\0" |
2333 | | /* 3672 */ "T104_W\0" |
2334 | | /* 3679 */ "Addr104_W\0" |
2335 | | /* 3689 */ "T114_W\0" |
2336 | | /* 3696 */ "Addr114_W\0" |
2337 | | /* 3706 */ "T14_W\0" |
2338 | | /* 3712 */ "Addr14_W\0" |
2339 | | /* 3721 */ "T124_W\0" |
2340 | | /* 3728 */ "Addr124_W\0" |
2341 | | /* 3738 */ "T24_W\0" |
2342 | | /* 3744 */ "Addr24_W\0" |
2343 | | /* 3753 */ "KC0_134_W\0" |
2344 | | /* 3763 */ "T34_W\0" |
2345 | | /* 3769 */ "Addr34_W\0" |
2346 | | /* 3778 */ "KC0_144_W\0" |
2347 | | /* 3788 */ "T44_W\0" |
2348 | | /* 3794 */ "Addr44_W\0" |
2349 | | /* 3803 */ "KC0_154_W\0" |
2350 | | /* 3813 */ "T54_W\0" |
2351 | | /* 3819 */ "Addr54_W\0" |
2352 | | /* 3828 */ "KC1_164_W\0" |
2353 | | /* 3838 */ "T64_W\0" |
2354 | | /* 3844 */ "Addr64_W\0" |
2355 | | /* 3853 */ "KC1_174_W\0" |
2356 | | /* 3863 */ "T74_W\0" |
2357 | | /* 3869 */ "Addr74_W\0" |
2358 | | /* 3878 */ "KC1_184_W\0" |
2359 | | /* 3888 */ "T84_W\0" |
2360 | | /* 3894 */ "Addr84_W\0" |
2361 | | /* 3903 */ "T94_W\0" |
2362 | | /* 3909 */ "Addr94_W\0" |
2363 | | /* 3918 */ "T4_W\0" |
2364 | | /* 3923 */ "Addr4_W\0" |
2365 | | /* 3931 */ "T105_W\0" |
2366 | | /* 3938 */ "Addr105_W\0" |
2367 | | /* 3948 */ "T115_W\0" |
2368 | | /* 3955 */ "Addr115_W\0" |
2369 | | /* 3965 */ "T15_W\0" |
2370 | | /* 3971 */ "Addr15_W\0" |
2371 | | /* 3980 */ "T125_W\0" |
2372 | | /* 3987 */ "Addr125_W\0" |
2373 | | /* 3997 */ "T25_W\0" |
2374 | | /* 4003 */ "Addr25_W\0" |
2375 | | /* 4012 */ "KC0_135_W\0" |
2376 | | /* 4022 */ "T35_W\0" |
2377 | | /* 4028 */ "Addr35_W\0" |
2378 | | /* 4037 */ "KC0_145_W\0" |
2379 | | /* 4047 */ "T45_W\0" |
2380 | | /* 4053 */ "Addr45_W\0" |
2381 | | /* 4062 */ "KC0_155_W\0" |
2382 | | /* 4072 */ "T55_W\0" |
2383 | | /* 4078 */ "Addr55_W\0" |
2384 | | /* 4087 */ "KC1_165_W\0" |
2385 | | /* 4097 */ "T65_W\0" |
2386 | | /* 4103 */ "Addr65_W\0" |
2387 | | /* 4112 */ "KC1_175_W\0" |
2388 | | /* 4122 */ "T75_W\0" |
2389 | | /* 4128 */ "Addr75_W\0" |
2390 | | /* 4137 */ "KC1_185_W\0" |
2391 | | /* 4147 */ "T85_W\0" |
2392 | | /* 4153 */ "Addr85_W\0" |
2393 | | /* 4162 */ "T95_W\0" |
2394 | | /* 4168 */ "Addr95_W\0" |
2395 | | /* 4177 */ "T5_W\0" |
2396 | | /* 4182 */ "Addr5_W\0" |
2397 | | /* 4190 */ "T106_W\0" |
2398 | | /* 4197 */ "Addr106_W\0" |
2399 | | /* 4207 */ "T116_W\0" |
2400 | | /* 4214 */ "Addr116_W\0" |
2401 | | /* 4224 */ "T16_W\0" |
2402 | | /* 4230 */ "Addr16_W\0" |
2403 | | /* 4239 */ "T126_W\0" |
2404 | | /* 4246 */ "Addr126_W\0" |
2405 | | /* 4256 */ "T26_W\0" |
2406 | | /* 4262 */ "Addr26_W\0" |
2407 | | /* 4271 */ "KC0_136_W\0" |
2408 | | /* 4281 */ "T36_W\0" |
2409 | | /* 4287 */ "Addr36_W\0" |
2410 | | /* 4296 */ "KC0_146_W\0" |
2411 | | /* 4306 */ "T46_W\0" |
2412 | | /* 4312 */ "Addr46_W\0" |
2413 | | /* 4321 */ "KC0_156_W\0" |
2414 | | /* 4331 */ "T56_W\0" |
2415 | | /* 4337 */ "Addr56_W\0" |
2416 | | /* 4346 */ "KC1_166_W\0" |
2417 | | /* 4356 */ "T66_W\0" |
2418 | | /* 4362 */ "Addr66_W\0" |
2419 | | /* 4371 */ "KC1_176_W\0" |
2420 | | /* 4381 */ "T76_W\0" |
2421 | | /* 4387 */ "Addr76_W\0" |
2422 | | /* 4396 */ "KC1_186_W\0" |
2423 | | /* 4406 */ "T86_W\0" |
2424 | | /* 4412 */ "Addr86_W\0" |
2425 | | /* 4421 */ "T96_W\0" |
2426 | | /* 4427 */ "Addr96_W\0" |
2427 | | /* 4436 */ "T6_W\0" |
2428 | | /* 4441 */ "Addr6_W\0" |
2429 | | /* 4449 */ "T107_W\0" |
2430 | | /* 4456 */ "Addr107_W\0" |
2431 | | /* 4466 */ "T117_W\0" |
2432 | | /* 4473 */ "Addr117_W\0" |
2433 | | /* 4483 */ "T17_W\0" |
2434 | | /* 4489 */ "Addr17_W\0" |
2435 | | /* 4498 */ "T127_W\0" |
2436 | | /* 4505 */ "Addr127_W\0" |
2437 | | /* 4515 */ "T27_W\0" |
2438 | | /* 4521 */ "Addr27_W\0" |
2439 | | /* 4530 */ "KC0_137_W\0" |
2440 | | /* 4540 */ "T37_W\0" |
2441 | | /* 4546 */ "Addr37_W\0" |
2442 | | /* 4555 */ "KC0_147_W\0" |
2443 | | /* 4565 */ "T47_W\0" |
2444 | | /* 4571 */ "Addr47_W\0" |
2445 | | /* 4580 */ "KC0_157_W\0" |
2446 | | /* 4590 */ "T57_W\0" |
2447 | | /* 4596 */ "Addr57_W\0" |
2448 | | /* 4605 */ "KC1_167_W\0" |
2449 | | /* 4615 */ "T67_W\0" |
2450 | | /* 4621 */ "Addr67_W\0" |
2451 | | /* 4630 */ "KC1_177_W\0" |
2452 | | /* 4640 */ "T77_W\0" |
2453 | | /* 4646 */ "Addr77_W\0" |
2454 | | /* 4655 */ "KC1_187_W\0" |
2455 | | /* 4665 */ "T87_W\0" |
2456 | | /* 4671 */ "Addr87_W\0" |
2457 | | /* 4680 */ "T97_W\0" |
2458 | | /* 4686 */ "Addr97_W\0" |
2459 | | /* 4695 */ "T7_W\0" |
2460 | | /* 4700 */ "Addr7_W\0" |
2461 | | /* 4708 */ "T108_W\0" |
2462 | | /* 4715 */ "Addr108_W\0" |
2463 | | /* 4725 */ "T118_W\0" |
2464 | | /* 4732 */ "Addr118_W\0" |
2465 | | /* 4742 */ "T18_W\0" |
2466 | | /* 4748 */ "Addr18_W\0" |
2467 | | /* 4757 */ "KC0_128_W\0" |
2468 | | /* 4767 */ "T28_W\0" |
2469 | | /* 4773 */ "Addr28_W\0" |
2470 | | /* 4782 */ "KC0_138_W\0" |
2471 | | /* 4792 */ "T38_W\0" |
2472 | | /* 4798 */ "Addr38_W\0" |
2473 | | /* 4807 */ "KC0_148_W\0" |
2474 | | /* 4817 */ "T48_W\0" |
2475 | | /* 4823 */ "Addr48_W\0" |
2476 | | /* 4832 */ "KC0_158_W\0" |
2477 | | /* 4842 */ "T58_W\0" |
2478 | | /* 4848 */ "Addr58_W\0" |
2479 | | /* 4857 */ "KC1_168_W\0" |
2480 | | /* 4867 */ "T68_W\0" |
2481 | | /* 4873 */ "Addr68_W\0" |
2482 | | /* 4882 */ "KC1_178_W\0" |
2483 | | /* 4892 */ "T78_W\0" |
2484 | | /* 4898 */ "Addr78_W\0" |
2485 | | /* 4907 */ "KC1_188_W\0" |
2486 | | /* 4917 */ "T88_W\0" |
2487 | | /* 4923 */ "Addr88_W\0" |
2488 | | /* 4932 */ "T98_W\0" |
2489 | | /* 4938 */ "Addr98_W\0" |
2490 | | /* 4947 */ "T8_W\0" |
2491 | | /* 4952 */ "Addr8_W\0" |
2492 | | /* 4960 */ "T109_W\0" |
2493 | | /* 4967 */ "Addr109_W\0" |
2494 | | /* 4977 */ "T119_W\0" |
2495 | | /* 4984 */ "Addr119_W\0" |
2496 | | /* 4994 */ "T19_W\0" |
2497 | | /* 5000 */ "Addr19_W\0" |
2498 | | /* 5009 */ "KC0_129_W\0" |
2499 | | /* 5019 */ "T29_W\0" |
2500 | | /* 5025 */ "Addr29_W\0" |
2501 | | /* 5034 */ "KC0_139_W\0" |
2502 | | /* 5044 */ "T39_W\0" |
2503 | | /* 5050 */ "Addr39_W\0" |
2504 | | /* 5059 */ "KC0_149_W\0" |
2505 | | /* 5069 */ "T49_W\0" |
2506 | | /* 5075 */ "Addr49_W\0" |
2507 | | /* 5084 */ "KC0_159_W\0" |
2508 | | /* 5094 */ "T59_W\0" |
2509 | | /* 5100 */ "Addr59_W\0" |
2510 | | /* 5109 */ "KC1_169_W\0" |
2511 | | /* 5119 */ "T69_W\0" |
2512 | | /* 5125 */ "Addr69_W\0" |
2513 | | /* 5134 */ "KC1_179_W\0" |
2514 | | /* 5144 */ "T79_W\0" |
2515 | | /* 5150 */ "Addr79_W\0" |
2516 | | /* 5159 */ "KC1_189_W\0" |
2517 | | /* 5169 */ "T89_W\0" |
2518 | | /* 5175 */ "Addr89_W\0" |
2519 | | /* 5184 */ "T99_W\0" |
2520 | | /* 5190 */ "Addr99_W\0" |
2521 | | /* 5199 */ "T9_W\0" |
2522 | | /* 5204 */ "Addr9_W\0" |
2523 | | /* 5212 */ "ALU_LITERAL_W\0" |
2524 | | /* 5226 */ "PV_W\0" |
2525 | | /* 5231 */ "T100_X\0" |
2526 | | /* 5238 */ "Addr100_X\0" |
2527 | | /* 5248 */ "T110_X\0" |
2528 | | /* 5255 */ "Addr110_X\0" |
2529 | | /* 5265 */ "T10_X\0" |
2530 | | /* 5271 */ "Addr10_X\0" |
2531 | | /* 5280 */ "T120_X\0" |
2532 | | /* 5287 */ "Addr120_X\0" |
2533 | | /* 5297 */ "T20_X\0" |
2534 | | /* 5303 */ "Addr20_X\0" |
2535 | | /* 5312 */ "KC0_130_X\0" |
2536 | | /* 5322 */ "T30_X\0" |
2537 | | /* 5328 */ "Addr30_X\0" |
2538 | | /* 5337 */ "KC0_140_X\0" |
2539 | | /* 5347 */ "T40_X\0" |
2540 | | /* 5353 */ "Addr40_X\0" |
2541 | | /* 5362 */ "KC0_150_X\0" |
2542 | | /* 5372 */ "T50_X\0" |
2543 | | /* 5378 */ "Addr50_X\0" |
2544 | | /* 5387 */ "KC1_160_X\0" |
2545 | | /* 5397 */ "T60_X\0" |
2546 | | /* 5403 */ "Addr60_X\0" |
2547 | | /* 5412 */ "KC1_170_X\0" |
2548 | | /* 5422 */ "T70_X\0" |
2549 | | /* 5428 */ "Addr70_X\0" |
2550 | | /* 5437 */ "KC1_180_X\0" |
2551 | | /* 5447 */ "T80_X\0" |
2552 | | /* 5453 */ "Addr80_X\0" |
2553 | | /* 5462 */ "KC1_190_X\0" |
2554 | | /* 5472 */ "T90_X\0" |
2555 | | /* 5478 */ "Addr90_X\0" |
2556 | | /* 5487 */ "T0_X\0" |
2557 | | /* 5492 */ "Addr0_X\0" |
2558 | | /* 5500 */ "T101_X\0" |
2559 | | /* 5507 */ "Addr101_X\0" |
2560 | | /* 5517 */ "V01_X\0" |
2561 | | /* 5523 */ "T111_X\0" |
2562 | | /* 5530 */ "Addr111_X\0" |
2563 | | /* 5540 */ "T11_X\0" |
2564 | | /* 5546 */ "Addr11_X\0" |
2565 | | /* 5555 */ "T121_X\0" |
2566 | | /* 5562 */ "Addr121_X\0" |
2567 | | /* 5572 */ "T21_X\0" |
2568 | | /* 5578 */ "Addr21_X\0" |
2569 | | /* 5587 */ "KC0_131_X\0" |
2570 | | /* 5597 */ "T31_X\0" |
2571 | | /* 5603 */ "Addr31_X\0" |
2572 | | /* 5612 */ "KC0_141_X\0" |
2573 | | /* 5622 */ "T41_X\0" |
2574 | | /* 5628 */ "Addr41_X\0" |
2575 | | /* 5637 */ "KC0_151_X\0" |
2576 | | /* 5647 */ "T51_X\0" |
2577 | | /* 5653 */ "Addr51_X\0" |
2578 | | /* 5662 */ "KC1_161_X\0" |
2579 | | /* 5672 */ "T61_X\0" |
2580 | | /* 5678 */ "Addr61_X\0" |
2581 | | /* 5687 */ "KC1_171_X\0" |
2582 | | /* 5697 */ "T71_X\0" |
2583 | | /* 5703 */ "Addr71_X\0" |
2584 | | /* 5712 */ "KC1_181_X\0" |
2585 | | /* 5722 */ "T81_X\0" |
2586 | | /* 5728 */ "Addr81_X\0" |
2587 | | /* 5737 */ "KC1_191_X\0" |
2588 | | /* 5747 */ "T91_X\0" |
2589 | | /* 5753 */ "Addr91_X\0" |
2590 | | /* 5762 */ "T1_X\0" |
2591 | | /* 5767 */ "Addr1_X\0" |
2592 | | /* 5775 */ "T102_X\0" |
2593 | | /* 5782 */ "Addr102_X\0" |
2594 | | /* 5792 */ "T112_X\0" |
2595 | | /* 5799 */ "Addr112_X\0" |
2596 | | /* 5809 */ "T12_X\0" |
2597 | | /* 5815 */ "Addr12_X\0" |
2598 | | /* 5824 */ "T122_X\0" |
2599 | | /* 5831 */ "Addr122_X\0" |
2600 | | /* 5841 */ "T22_X\0" |
2601 | | /* 5847 */ "Addr22_X\0" |
2602 | | /* 5856 */ "KC0_132_X\0" |
2603 | | /* 5866 */ "T32_X\0" |
2604 | | /* 5872 */ "Addr32_X\0" |
2605 | | /* 5881 */ "KC0_142_X\0" |
2606 | | /* 5891 */ "T42_X\0" |
2607 | | /* 5897 */ "Addr42_X\0" |
2608 | | /* 5906 */ "KC0_152_X\0" |
2609 | | /* 5916 */ "T52_X\0" |
2610 | | /* 5922 */ "Addr52_X\0" |
2611 | | /* 5931 */ "KC1_162_X\0" |
2612 | | /* 5941 */ "T62_X\0" |
2613 | | /* 5947 */ "Addr62_X\0" |
2614 | | /* 5956 */ "KC1_172_X\0" |
2615 | | /* 5966 */ "T72_X\0" |
2616 | | /* 5972 */ "Addr72_X\0" |
2617 | | /* 5981 */ "KC1_182_X\0" |
2618 | | /* 5991 */ "T82_X\0" |
2619 | | /* 5997 */ "Addr82_X\0" |
2620 | | /* 6006 */ "T92_X\0" |
2621 | | /* 6012 */ "Addr92_X\0" |
2622 | | /* 6021 */ "T2_X\0" |
2623 | | /* 6026 */ "Addr2_X\0" |
2624 | | /* 6034 */ "T103_X\0" |
2625 | | /* 6041 */ "Addr103_X\0" |
2626 | | /* 6051 */ "T113_X\0" |
2627 | | /* 6058 */ "Addr113_X\0" |
2628 | | /* 6068 */ "T13_X\0" |
2629 | | /* 6074 */ "Addr13_X\0" |
2630 | | /* 6083 */ "V0123_X\0" |
2631 | | /* 6091 */ "T123_X\0" |
2632 | | /* 6098 */ "Addr123_X\0" |
2633 | | /* 6108 */ "T23_X\0" |
2634 | | /* 6114 */ "V23_X\0" |
2635 | | /* 6120 */ "Addr23_X\0" |
2636 | | /* 6129 */ "KC0_133_X\0" |
2637 | | /* 6139 */ "T33_X\0" |
2638 | | /* 6145 */ "Addr33_X\0" |
2639 | | /* 6154 */ "KC0_143_X\0" |
2640 | | /* 6164 */ "T43_X\0" |
2641 | | /* 6170 */ "Addr43_X\0" |
2642 | | /* 6179 */ "KC0_153_X\0" |
2643 | | /* 6189 */ "T53_X\0" |
2644 | | /* 6195 */ "Addr53_X\0" |
2645 | | /* 6204 */ "KC1_163_X\0" |
2646 | | /* 6214 */ "T63_X\0" |
2647 | | /* 6220 */ "Addr63_X\0" |
2648 | | /* 6229 */ "KC1_173_X\0" |
2649 | | /* 6239 */ "T73_X\0" |
2650 | | /* 6245 */ "Addr73_X\0" |
2651 | | /* 6254 */ "KC1_183_X\0" |
2652 | | /* 6264 */ "T83_X\0" |
2653 | | /* 6270 */ "Addr83_X\0" |
2654 | | /* 6279 */ "T93_X\0" |
2655 | | /* 6285 */ "Addr93_X\0" |
2656 | | /* 6294 */ "T3_X\0" |
2657 | | /* 6299 */ "Addr3_X\0" |
2658 | | /* 6307 */ "T104_X\0" |
2659 | | /* 6314 */ "Addr104_X\0" |
2660 | | /* 6324 */ "T114_X\0" |
2661 | | /* 6331 */ "Addr114_X\0" |
2662 | | /* 6341 */ "T14_X\0" |
2663 | | /* 6347 */ "Addr14_X\0" |
2664 | | /* 6356 */ "T124_X\0" |
2665 | | /* 6363 */ "Addr124_X\0" |
2666 | | /* 6373 */ "T24_X\0" |
2667 | | /* 6379 */ "Addr24_X\0" |
2668 | | /* 6388 */ "KC0_134_X\0" |
2669 | | /* 6398 */ "T34_X\0" |
2670 | | /* 6404 */ "Addr34_X\0" |
2671 | | /* 6413 */ "KC0_144_X\0" |
2672 | | /* 6423 */ "T44_X\0" |
2673 | | /* 6429 */ "Addr44_X\0" |
2674 | | /* 6438 */ "KC0_154_X\0" |
2675 | | /* 6448 */ "T54_X\0" |
2676 | | /* 6454 */ "Addr54_X\0" |
2677 | | /* 6463 */ "KC1_164_X\0" |
2678 | | /* 6473 */ "T64_X\0" |
2679 | | /* 6479 */ "Addr64_X\0" |
2680 | | /* 6488 */ "KC1_174_X\0" |
2681 | | /* 6498 */ "T74_X\0" |
2682 | | /* 6504 */ "Addr74_X\0" |
2683 | | /* 6513 */ "KC1_184_X\0" |
2684 | | /* 6523 */ "T84_X\0" |
2685 | | /* 6529 */ "Addr84_X\0" |
2686 | | /* 6538 */ "T94_X\0" |
2687 | | /* 6544 */ "Addr94_X\0" |
2688 | | /* 6553 */ "T4_X\0" |
2689 | | /* 6558 */ "Addr4_X\0" |
2690 | | /* 6566 */ "T105_X\0" |
2691 | | /* 6573 */ "Addr105_X\0" |
2692 | | /* 6583 */ "T115_X\0" |
2693 | | /* 6590 */ "Addr115_X\0" |
2694 | | /* 6600 */ "T15_X\0" |
2695 | | /* 6606 */ "Addr15_X\0" |
2696 | | /* 6615 */ "T125_X\0" |
2697 | | /* 6622 */ "Addr125_X\0" |
2698 | | /* 6632 */ "T25_X\0" |
2699 | | /* 6638 */ "Addr25_X\0" |
2700 | | /* 6647 */ "KC0_135_X\0" |
2701 | | /* 6657 */ "T35_X\0" |
2702 | | /* 6663 */ "Addr35_X\0" |
2703 | | /* 6672 */ "KC0_145_X\0" |
2704 | | /* 6682 */ "T45_X\0" |
2705 | | /* 6688 */ "Addr45_X\0" |
2706 | | /* 6697 */ "KC0_155_X\0" |
2707 | | /* 6707 */ "T55_X\0" |
2708 | | /* 6713 */ "Addr55_X\0" |
2709 | | /* 6722 */ "KC1_165_X\0" |
2710 | | /* 6732 */ "T65_X\0" |
2711 | | /* 6738 */ "Addr65_X\0" |
2712 | | /* 6747 */ "KC1_175_X\0" |
2713 | | /* 6757 */ "T75_X\0" |
2714 | | /* 6763 */ "Addr75_X\0" |
2715 | | /* 6772 */ "KC1_185_X\0" |
2716 | | /* 6782 */ "T85_X\0" |
2717 | | /* 6788 */ "Addr85_X\0" |
2718 | | /* 6797 */ "T95_X\0" |
2719 | | /* 6803 */ "Addr95_X\0" |
2720 | | /* 6812 */ "T5_X\0" |
2721 | | /* 6817 */ "Addr5_X\0" |
2722 | | /* 6825 */ "T106_X\0" |
2723 | | /* 6832 */ "Addr106_X\0" |
2724 | | /* 6842 */ "T116_X\0" |
2725 | | /* 6849 */ "Addr116_X\0" |
2726 | | /* 6859 */ "T16_X\0" |
2727 | | /* 6865 */ "Addr16_X\0" |
2728 | | /* 6874 */ "T126_X\0" |
2729 | | /* 6881 */ "Addr126_X\0" |
2730 | | /* 6891 */ "T26_X\0" |
2731 | | /* 6897 */ "Addr26_X\0" |
2732 | | /* 6906 */ "KC0_136_X\0" |
2733 | | /* 6916 */ "T36_X\0" |
2734 | | /* 6922 */ "Addr36_X\0" |
2735 | | /* 6931 */ "KC0_146_X\0" |
2736 | | /* 6941 */ "T46_X\0" |
2737 | | /* 6947 */ "Addr46_X\0" |
2738 | | /* 6956 */ "KC0_156_X\0" |
2739 | | /* 6966 */ "T56_X\0" |
2740 | | /* 6972 */ "Addr56_X\0" |
2741 | | /* 6981 */ "KC1_166_X\0" |
2742 | | /* 6991 */ "T66_X\0" |
2743 | | /* 6997 */ "Addr66_X\0" |
2744 | | /* 7006 */ "KC1_176_X\0" |
2745 | | /* 7016 */ "T76_X\0" |
2746 | | /* 7022 */ "Addr76_X\0" |
2747 | | /* 7031 */ "KC1_186_X\0" |
2748 | | /* 7041 */ "T86_X\0" |
2749 | | /* 7047 */ "Addr86_X\0" |
2750 | | /* 7056 */ "T96_X\0" |
2751 | | /* 7062 */ "Addr96_X\0" |
2752 | | /* 7071 */ "T6_X\0" |
2753 | | /* 7076 */ "Addr6_X\0" |
2754 | | /* 7084 */ "T107_X\0" |
2755 | | /* 7091 */ "Addr107_X\0" |
2756 | | /* 7101 */ "T117_X\0" |
2757 | | /* 7108 */ "Addr117_X\0" |
2758 | | /* 7118 */ "T17_X\0" |
2759 | | /* 7124 */ "Addr17_X\0" |
2760 | | /* 7133 */ "T127_X\0" |
2761 | | /* 7140 */ "Addr127_X\0" |
2762 | | /* 7150 */ "T27_X\0" |
2763 | | /* 7156 */ "Addr27_X\0" |
2764 | | /* 7165 */ "KC0_137_X\0" |
2765 | | /* 7175 */ "T37_X\0" |
2766 | | /* 7181 */ "Addr37_X\0" |
2767 | | /* 7190 */ "KC0_147_X\0" |
2768 | | /* 7200 */ "T47_X\0" |
2769 | | /* 7206 */ "Addr47_X\0" |
2770 | | /* 7215 */ "KC0_157_X\0" |
2771 | | /* 7225 */ "T57_X\0" |
2772 | | /* 7231 */ "Addr57_X\0" |
2773 | | /* 7240 */ "KC1_167_X\0" |
2774 | | /* 7250 */ "T67_X\0" |
2775 | | /* 7256 */ "Addr67_X\0" |
2776 | | /* 7265 */ "KC1_177_X\0" |
2777 | | /* 7275 */ "T77_X\0" |
2778 | | /* 7281 */ "Addr77_X\0" |
2779 | | /* 7290 */ "KC1_187_X\0" |
2780 | | /* 7300 */ "T87_X\0" |
2781 | | /* 7306 */ "Addr87_X\0" |
2782 | | /* 7315 */ "T97_X\0" |
2783 | | /* 7321 */ "Addr97_X\0" |
2784 | | /* 7330 */ "T7_X\0" |
2785 | | /* 7335 */ "Addr7_X\0" |
2786 | | /* 7343 */ "T108_X\0" |
2787 | | /* 7350 */ "Addr108_X\0" |
2788 | | /* 7360 */ "T118_X\0" |
2789 | | /* 7367 */ "Addr118_X\0" |
2790 | | /* 7377 */ "T18_X\0" |
2791 | | /* 7383 */ "Addr18_X\0" |
2792 | | /* 7392 */ "KC0_128_X\0" |
2793 | | /* 7402 */ "T28_X\0" |
2794 | | /* 7408 */ "Addr28_X\0" |
2795 | | /* 7417 */ "KC0_138_X\0" |
2796 | | /* 7427 */ "T38_X\0" |
2797 | | /* 7433 */ "Addr38_X\0" |
2798 | | /* 7442 */ "KC0_148_X\0" |
2799 | | /* 7452 */ "T48_X\0" |
2800 | | /* 7458 */ "Addr48_X\0" |
2801 | | /* 7467 */ "KC0_158_X\0" |
2802 | | /* 7477 */ "T58_X\0" |
2803 | | /* 7483 */ "Addr58_X\0" |
2804 | | /* 7492 */ "KC1_168_X\0" |
2805 | | /* 7502 */ "T68_X\0" |
2806 | | /* 7508 */ "Addr68_X\0" |
2807 | | /* 7517 */ "KC1_178_X\0" |
2808 | | /* 7527 */ "T78_X\0" |
2809 | | /* 7533 */ "Addr78_X\0" |
2810 | | /* 7542 */ "KC1_188_X\0" |
2811 | | /* 7552 */ "T88_X\0" |
2812 | | /* 7558 */ "Addr88_X\0" |
2813 | | /* 7567 */ "T98_X\0" |
2814 | | /* 7573 */ "Addr98_X\0" |
2815 | | /* 7582 */ "T8_X\0" |
2816 | | /* 7587 */ "Addr8_X\0" |
2817 | | /* 7595 */ "T109_X\0" |
2818 | | /* 7602 */ "Addr109_X\0" |
2819 | | /* 7612 */ "T119_X\0" |
2820 | | /* 7619 */ "Addr119_X\0" |
2821 | | /* 7629 */ "T19_X\0" |
2822 | | /* 7635 */ "Addr19_X\0" |
2823 | | /* 7644 */ "KC0_129_X\0" |
2824 | | /* 7654 */ "T29_X\0" |
2825 | | /* 7660 */ "Addr29_X\0" |
2826 | | /* 7669 */ "KC0_139_X\0" |
2827 | | /* 7679 */ "T39_X\0" |
2828 | | /* 7685 */ "Addr39_X\0" |
2829 | | /* 7694 */ "KC0_149_X\0" |
2830 | | /* 7704 */ "T49_X\0" |
2831 | | /* 7710 */ "Addr49_X\0" |
2832 | | /* 7719 */ "KC0_159_X\0" |
2833 | | /* 7729 */ "T59_X\0" |
2834 | | /* 7735 */ "Addr59_X\0" |
2835 | | /* 7744 */ "KC1_169_X\0" |
2836 | | /* 7754 */ "T69_X\0" |
2837 | | /* 7760 */ "Addr69_X\0" |
2838 | | /* 7769 */ "KC1_179_X\0" |
2839 | | /* 7779 */ "T79_X\0" |
2840 | | /* 7785 */ "Addr79_X\0" |
2841 | | /* 7794 */ "KC1_189_X\0" |
2842 | | /* 7804 */ "T89_X\0" |
2843 | | /* 7810 */ "Addr89_X\0" |
2844 | | /* 7819 */ "T99_X\0" |
2845 | | /* 7825 */ "Addr99_X\0" |
2846 | | /* 7834 */ "T9_X\0" |
2847 | | /* 7839 */ "Addr9_X\0" |
2848 | | /* 7847 */ "ALU_LITERAL_X\0" |
2849 | | /* 7861 */ "AR_X\0" |
2850 | | /* 7866 */ "PV_X\0" |
2851 | | /* 7871 */ "T100_XY\0" |
2852 | | /* 7879 */ "T110_XY\0" |
2853 | | /* 7887 */ "T10_XY\0" |
2854 | | /* 7894 */ "T120_XY\0" |
2855 | | /* 7902 */ "T20_XY\0" |
2856 | | /* 7909 */ "T30_XY\0" |
2857 | | /* 7916 */ "T40_XY\0" |
2858 | | /* 7923 */ "T50_XY\0" |
2859 | | /* 7930 */ "T60_XY\0" |
2860 | | /* 7937 */ "T70_XY\0" |
2861 | | /* 7944 */ "T80_XY\0" |
2862 | | /* 7951 */ "T90_XY\0" |
2863 | | /* 7958 */ "T0_XY\0" |
2864 | | /* 7964 */ "T101_XY\0" |
2865 | | /* 7972 */ "T111_XY\0" |
2866 | | /* 7980 */ "T11_XY\0" |
2867 | | /* 7987 */ "T121_XY\0" |
2868 | | /* 7995 */ "T21_XY\0" |
2869 | | /* 8002 */ "T31_XY\0" |
2870 | | /* 8009 */ "T41_XY\0" |
2871 | | /* 8016 */ "T51_XY\0" |
2872 | | /* 8023 */ "T61_XY\0" |
2873 | | /* 8030 */ "T71_XY\0" |
2874 | | /* 8037 */ "T81_XY\0" |
2875 | | /* 8044 */ "T91_XY\0" |
2876 | | /* 8051 */ "T1_XY\0" |
2877 | | /* 8057 */ "T102_XY\0" |
2878 | | /* 8065 */ "T112_XY\0" |
2879 | | /* 8073 */ "T12_XY\0" |
2880 | | /* 8080 */ "T122_XY\0" |
2881 | | /* 8088 */ "T22_XY\0" |
2882 | | /* 8095 */ "T32_XY\0" |
2883 | | /* 8102 */ "T42_XY\0" |
2884 | | /* 8109 */ "T52_XY\0" |
2885 | | /* 8116 */ "T62_XY\0" |
2886 | | /* 8123 */ "T72_XY\0" |
2887 | | /* 8130 */ "T82_XY\0" |
2888 | | /* 8137 */ "T92_XY\0" |
2889 | | /* 8144 */ "T2_XY\0" |
2890 | | /* 8150 */ "T103_XY\0" |
2891 | | /* 8158 */ "T113_XY\0" |
2892 | | /* 8166 */ "T13_XY\0" |
2893 | | /* 8173 */ "T123_XY\0" |
2894 | | /* 8181 */ "T23_XY\0" |
2895 | | /* 8188 */ "T33_XY\0" |
2896 | | /* 8195 */ "T43_XY\0" |
2897 | | /* 8202 */ "T53_XY\0" |
2898 | | /* 8209 */ "T63_XY\0" |
2899 | | /* 8216 */ "T73_XY\0" |
2900 | | /* 8223 */ "T83_XY\0" |
2901 | | /* 8230 */ "T93_XY\0" |
2902 | | /* 8237 */ "T3_XY\0" |
2903 | | /* 8243 */ "T104_XY\0" |
2904 | | /* 8251 */ "T114_XY\0" |
2905 | | /* 8259 */ "T14_XY\0" |
2906 | | /* 8266 */ "T124_XY\0" |
2907 | | /* 8274 */ "T24_XY\0" |
2908 | | /* 8281 */ "T34_XY\0" |
2909 | | /* 8288 */ "T44_XY\0" |
2910 | | /* 8295 */ "T54_XY\0" |
2911 | | /* 8302 */ "T64_XY\0" |
2912 | | /* 8309 */ "T74_XY\0" |
2913 | | /* 8316 */ "T84_XY\0" |
2914 | | /* 8323 */ "T94_XY\0" |
2915 | | /* 8330 */ "T4_XY\0" |
2916 | | /* 8336 */ "T105_XY\0" |
2917 | | /* 8344 */ "T115_XY\0" |
2918 | | /* 8352 */ "T15_XY\0" |
2919 | | /* 8359 */ "T125_XY\0" |
2920 | | /* 8367 */ "T25_XY\0" |
2921 | | /* 8374 */ "T35_XY\0" |
2922 | | /* 8381 */ "T45_XY\0" |
2923 | | /* 8388 */ "T55_XY\0" |
2924 | | /* 8395 */ "T65_XY\0" |
2925 | | /* 8402 */ "T75_XY\0" |
2926 | | /* 8409 */ "T85_XY\0" |
2927 | | /* 8416 */ "T95_XY\0" |
2928 | | /* 8423 */ "T5_XY\0" |
2929 | | /* 8429 */ "T106_XY\0" |
2930 | | /* 8437 */ "T116_XY\0" |
2931 | | /* 8445 */ "T16_XY\0" |
2932 | | /* 8452 */ "T126_XY\0" |
2933 | | /* 8460 */ "T26_XY\0" |
2934 | | /* 8467 */ "T36_XY\0" |
2935 | | /* 8474 */ "T46_XY\0" |
2936 | | /* 8481 */ "T56_XY\0" |
2937 | | /* 8488 */ "T66_XY\0" |
2938 | | /* 8495 */ "T76_XY\0" |
2939 | | /* 8502 */ "T86_XY\0" |
2940 | | /* 8509 */ "T96_XY\0" |
2941 | | /* 8516 */ "T6_XY\0" |
2942 | | /* 8522 */ "T107_XY\0" |
2943 | | /* 8530 */ "T117_XY\0" |
2944 | | /* 8538 */ "T17_XY\0" |
2945 | | /* 8545 */ "T127_XY\0" |
2946 | | /* 8553 */ "T27_XY\0" |
2947 | | /* 8560 */ "T37_XY\0" |
2948 | | /* 8567 */ "T47_XY\0" |
2949 | | /* 8574 */ "T57_XY\0" |
2950 | | /* 8581 */ "T67_XY\0" |
2951 | | /* 8588 */ "T77_XY\0" |
2952 | | /* 8595 */ "T87_XY\0" |
2953 | | /* 8602 */ "T97_XY\0" |
2954 | | /* 8609 */ "T7_XY\0" |
2955 | | /* 8615 */ "T108_XY\0" |
2956 | | /* 8623 */ "T118_XY\0" |
2957 | | /* 8631 */ "T18_XY\0" |
2958 | | /* 8638 */ "T28_XY\0" |
2959 | | /* 8645 */ "T38_XY\0" |
2960 | | /* 8652 */ "T48_XY\0" |
2961 | | /* 8659 */ "T58_XY\0" |
2962 | | /* 8666 */ "T68_XY\0" |
2963 | | /* 8673 */ "T78_XY\0" |
2964 | | /* 8680 */ "T88_XY\0" |
2965 | | /* 8687 */ "T98_XY\0" |
2966 | | /* 8694 */ "T8_XY\0" |
2967 | | /* 8700 */ "T109_XY\0" |
2968 | | /* 8708 */ "T119_XY\0" |
2969 | | /* 8716 */ "T19_XY\0" |
2970 | | /* 8723 */ "T29_XY\0" |
2971 | | /* 8730 */ "T39_XY\0" |
2972 | | /* 8737 */ "T49_XY\0" |
2973 | | /* 8744 */ "T59_XY\0" |
2974 | | /* 8751 */ "T69_XY\0" |
2975 | | /* 8758 */ "T79_XY\0" |
2976 | | /* 8765 */ "T89_XY\0" |
2977 | | /* 8772 */ "T99_XY\0" |
2978 | | /* 8779 */ "T9_XY\0" |
2979 | | /* 8785 */ "T100_Y\0" |
2980 | | /* 8792 */ "Addr100_Y\0" |
2981 | | /* 8802 */ "T110_Y\0" |
2982 | | /* 8809 */ "Addr110_Y\0" |
2983 | | /* 8819 */ "T10_Y\0" |
2984 | | /* 8825 */ "Addr10_Y\0" |
2985 | | /* 8834 */ "T120_Y\0" |
2986 | | /* 8841 */ "Addr120_Y\0" |
2987 | | /* 8851 */ "T20_Y\0" |
2988 | | /* 8857 */ "Addr20_Y\0" |
2989 | | /* 8866 */ "KC0_130_Y\0" |
2990 | | /* 8876 */ "T30_Y\0" |
2991 | | /* 8882 */ "Addr30_Y\0" |
2992 | | /* 8891 */ "KC0_140_Y\0" |
2993 | | /* 8901 */ "T40_Y\0" |
2994 | | /* 8907 */ "Addr40_Y\0" |
2995 | | /* 8916 */ "KC0_150_Y\0" |
2996 | | /* 8926 */ "T50_Y\0" |
2997 | | /* 8932 */ "Addr50_Y\0" |
2998 | | /* 8941 */ "KC1_160_Y\0" |
2999 | | /* 8951 */ "T60_Y\0" |
3000 | | /* 8957 */ "Addr60_Y\0" |
3001 | | /* 8966 */ "KC1_170_Y\0" |
3002 | | /* 8976 */ "T70_Y\0" |
3003 | | /* 8982 */ "Addr70_Y\0" |
3004 | | /* 8991 */ "KC1_180_Y\0" |
3005 | | /* 9001 */ "T80_Y\0" |
3006 | | /* 9007 */ "Addr80_Y\0" |
3007 | | /* 9016 */ "KC1_190_Y\0" |
3008 | | /* 9026 */ "T90_Y\0" |
3009 | | /* 9032 */ "Addr90_Y\0" |
3010 | | /* 9041 */ "T0_Y\0" |
3011 | | /* 9046 */ "Addr0_Y\0" |
3012 | | /* 9054 */ "T101_Y\0" |
3013 | | /* 9061 */ "Addr101_Y\0" |
3014 | | /* 9071 */ "V01_Y\0" |
3015 | | /* 9077 */ "T111_Y\0" |
3016 | | /* 9084 */ "Addr111_Y\0" |
3017 | | /* 9094 */ "T11_Y\0" |
3018 | | /* 9100 */ "Addr11_Y\0" |
3019 | | /* 9109 */ "T121_Y\0" |
3020 | | /* 9116 */ "Addr121_Y\0" |
3021 | | /* 9126 */ "T21_Y\0" |
3022 | | /* 9132 */ "Addr21_Y\0" |
3023 | | /* 9141 */ "KC0_131_Y\0" |
3024 | | /* 9151 */ "T31_Y\0" |
3025 | | /* 9157 */ "Addr31_Y\0" |
3026 | | /* 9166 */ "KC0_141_Y\0" |
3027 | | /* 9176 */ "T41_Y\0" |
3028 | | /* 9182 */ "Addr41_Y\0" |
3029 | | /* 9191 */ "KC0_151_Y\0" |
3030 | | /* 9201 */ "T51_Y\0" |
3031 | | /* 9207 */ "Addr51_Y\0" |
3032 | | /* 9216 */ "KC1_161_Y\0" |
3033 | | /* 9226 */ "T61_Y\0" |
3034 | | /* 9232 */ "Addr61_Y\0" |
3035 | | /* 9241 */ "KC1_171_Y\0" |
3036 | | /* 9251 */ "T71_Y\0" |
3037 | | /* 9257 */ "Addr71_Y\0" |
3038 | | /* 9266 */ "KC1_181_Y\0" |
3039 | | /* 9276 */ "T81_Y\0" |
3040 | | /* 9282 */ "Addr81_Y\0" |
3041 | | /* 9291 */ "KC1_191_Y\0" |
3042 | | /* 9301 */ "T91_Y\0" |
3043 | | /* 9307 */ "Addr91_Y\0" |
3044 | | /* 9316 */ "T1_Y\0" |
3045 | | /* 9321 */ "Addr1_Y\0" |
3046 | | /* 9329 */ "T102_Y\0" |
3047 | | /* 9336 */ "Addr102_Y\0" |
3048 | | /* 9346 */ "T112_Y\0" |
3049 | | /* 9353 */ "Addr112_Y\0" |
3050 | | /* 9363 */ "T12_Y\0" |
3051 | | /* 9369 */ "Addr12_Y\0" |
3052 | | /* 9378 */ "T122_Y\0" |
3053 | | /* 9385 */ "Addr122_Y\0" |
3054 | | /* 9395 */ "T22_Y\0" |
3055 | | /* 9401 */ "Addr22_Y\0" |
3056 | | /* 9410 */ "KC0_132_Y\0" |
3057 | | /* 9420 */ "T32_Y\0" |
3058 | | /* 9426 */ "Addr32_Y\0" |
3059 | | /* 9435 */ "KC0_142_Y\0" |
3060 | | /* 9445 */ "T42_Y\0" |
3061 | | /* 9451 */ "Addr42_Y\0" |
3062 | | /* 9460 */ "KC0_152_Y\0" |
3063 | | /* 9470 */ "T52_Y\0" |
3064 | | /* 9476 */ "Addr52_Y\0" |
3065 | | /* 9485 */ "KC1_162_Y\0" |
3066 | | /* 9495 */ "T62_Y\0" |
3067 | | /* 9501 */ "Addr62_Y\0" |
3068 | | /* 9510 */ "KC1_172_Y\0" |
3069 | | /* 9520 */ "T72_Y\0" |
3070 | | /* 9526 */ "Addr72_Y\0" |
3071 | | /* 9535 */ "KC1_182_Y\0" |
3072 | | /* 9545 */ "T82_Y\0" |
3073 | | /* 9551 */ "Addr82_Y\0" |
3074 | | /* 9560 */ "T92_Y\0" |
3075 | | /* 9566 */ "Addr92_Y\0" |
3076 | | /* 9575 */ "T2_Y\0" |
3077 | | /* 9580 */ "Addr2_Y\0" |
3078 | | /* 9588 */ "T103_Y\0" |
3079 | | /* 9595 */ "Addr103_Y\0" |
3080 | | /* 9605 */ "T113_Y\0" |
3081 | | /* 9612 */ "Addr113_Y\0" |
3082 | | /* 9622 */ "T13_Y\0" |
3083 | | /* 9628 */ "Addr13_Y\0" |
3084 | | /* 9637 */ "V0123_Y\0" |
3085 | | /* 9645 */ "T123_Y\0" |
3086 | | /* 9652 */ "Addr123_Y\0" |
3087 | | /* 9662 */ "T23_Y\0" |
3088 | | /* 9668 */ "V23_Y\0" |
3089 | | /* 9674 */ "Addr23_Y\0" |
3090 | | /* 9683 */ "KC0_133_Y\0" |
3091 | | /* 9693 */ "T33_Y\0" |
3092 | | /* 9699 */ "Addr33_Y\0" |
3093 | | /* 9708 */ "KC0_143_Y\0" |
3094 | | /* 9718 */ "T43_Y\0" |
3095 | | /* 9724 */ "Addr43_Y\0" |
3096 | | /* 9733 */ "KC0_153_Y\0" |
3097 | | /* 9743 */ "T53_Y\0" |
3098 | | /* 9749 */ "Addr53_Y\0" |
3099 | | /* 9758 */ "KC1_163_Y\0" |
3100 | | /* 9768 */ "T63_Y\0" |
3101 | | /* 9774 */ "Addr63_Y\0" |
3102 | | /* 9783 */ "KC1_173_Y\0" |
3103 | | /* 9793 */ "T73_Y\0" |
3104 | | /* 9799 */ "Addr73_Y\0" |
3105 | | /* 9808 */ "KC1_183_Y\0" |
3106 | | /* 9818 */ "T83_Y\0" |
3107 | | /* 9824 */ "Addr83_Y\0" |
3108 | | /* 9833 */ "T93_Y\0" |
3109 | | /* 9839 */ "Addr93_Y\0" |
3110 | | /* 9848 */ "T3_Y\0" |
3111 | | /* 9853 */ "Addr3_Y\0" |
3112 | | /* 9861 */ "T104_Y\0" |
3113 | | /* 9868 */ "Addr104_Y\0" |
3114 | | /* 9878 */ "T114_Y\0" |
3115 | | /* 9885 */ "Addr114_Y\0" |
3116 | | /* 9895 */ "T14_Y\0" |
3117 | | /* 9901 */ "Addr14_Y\0" |
3118 | | /* 9910 */ "T124_Y\0" |
3119 | | /* 9917 */ "Addr124_Y\0" |
3120 | | /* 9927 */ "T24_Y\0" |
3121 | | /* 9933 */ "Addr24_Y\0" |
3122 | | /* 9942 */ "KC0_134_Y\0" |
3123 | | /* 9952 */ "T34_Y\0" |
3124 | | /* 9958 */ "Addr34_Y\0" |
3125 | | /* 9967 */ "KC0_144_Y\0" |
3126 | | /* 9977 */ "T44_Y\0" |
3127 | | /* 9983 */ "Addr44_Y\0" |
3128 | | /* 9992 */ "KC0_154_Y\0" |
3129 | | /* 10002 */ "T54_Y\0" |
3130 | | /* 10008 */ "Addr54_Y\0" |
3131 | | /* 10017 */ "KC1_164_Y\0" |
3132 | | /* 10027 */ "T64_Y\0" |
3133 | | /* 10033 */ "Addr64_Y\0" |
3134 | | /* 10042 */ "KC1_174_Y\0" |
3135 | | /* 10052 */ "T74_Y\0" |
3136 | | /* 10058 */ "Addr74_Y\0" |
3137 | | /* 10067 */ "KC1_184_Y\0" |
3138 | | /* 10077 */ "T84_Y\0" |
3139 | | /* 10083 */ "Addr84_Y\0" |
3140 | | /* 10092 */ "T94_Y\0" |
3141 | | /* 10098 */ "Addr94_Y\0" |
3142 | | /* 10107 */ "T4_Y\0" |
3143 | | /* 10112 */ "Addr4_Y\0" |
3144 | | /* 10120 */ "T105_Y\0" |
3145 | | /* 10127 */ "Addr105_Y\0" |
3146 | | /* 10137 */ "T115_Y\0" |
3147 | | /* 10144 */ "Addr115_Y\0" |
3148 | | /* 10154 */ "T15_Y\0" |
3149 | | /* 10160 */ "Addr15_Y\0" |
3150 | | /* 10169 */ "T125_Y\0" |
3151 | | /* 10176 */ "Addr125_Y\0" |
3152 | | /* 10186 */ "T25_Y\0" |
3153 | | /* 10192 */ "Addr25_Y\0" |
3154 | | /* 10201 */ "KC0_135_Y\0" |
3155 | | /* 10211 */ "T35_Y\0" |
3156 | | /* 10217 */ "Addr35_Y\0" |
3157 | | /* 10226 */ "KC0_145_Y\0" |
3158 | | /* 10236 */ "T45_Y\0" |
3159 | | /* 10242 */ "Addr45_Y\0" |
3160 | | /* 10251 */ "KC0_155_Y\0" |
3161 | | /* 10261 */ "T55_Y\0" |
3162 | | /* 10267 */ "Addr55_Y\0" |
3163 | | /* 10276 */ "KC1_165_Y\0" |
3164 | | /* 10286 */ "T65_Y\0" |
3165 | | /* 10292 */ "Addr65_Y\0" |
3166 | | /* 10301 */ "KC1_175_Y\0" |
3167 | | /* 10311 */ "T75_Y\0" |
3168 | | /* 10317 */ "Addr75_Y\0" |
3169 | | /* 10326 */ "KC1_185_Y\0" |
3170 | | /* 10336 */ "T85_Y\0" |
3171 | | /* 10342 */ "Addr85_Y\0" |
3172 | | /* 10351 */ "T95_Y\0" |
3173 | | /* 10357 */ "Addr95_Y\0" |
3174 | | /* 10366 */ "T5_Y\0" |
3175 | | /* 10371 */ "Addr5_Y\0" |
3176 | | /* 10379 */ "T106_Y\0" |
3177 | | /* 10386 */ "Addr106_Y\0" |
3178 | | /* 10396 */ "T116_Y\0" |
3179 | | /* 10403 */ "Addr116_Y\0" |
3180 | | /* 10413 */ "T16_Y\0" |
3181 | | /* 10419 */ "Addr16_Y\0" |
3182 | | /* 10428 */ "T126_Y\0" |
3183 | | /* 10435 */ "Addr126_Y\0" |
3184 | | /* 10445 */ "T26_Y\0" |
3185 | | /* 10451 */ "Addr26_Y\0" |
3186 | | /* 10460 */ "KC0_136_Y\0" |
3187 | | /* 10470 */ "T36_Y\0" |
3188 | | /* 10476 */ "Addr36_Y\0" |
3189 | | /* 10485 */ "KC0_146_Y\0" |
3190 | | /* 10495 */ "T46_Y\0" |
3191 | | /* 10501 */ "Addr46_Y\0" |
3192 | | /* 10510 */ "KC0_156_Y\0" |
3193 | | /* 10520 */ "T56_Y\0" |
3194 | | /* 10526 */ "Addr56_Y\0" |
3195 | | /* 10535 */ "KC1_166_Y\0" |
3196 | | /* 10545 */ "T66_Y\0" |
3197 | | /* 10551 */ "Addr66_Y\0" |
3198 | | /* 10560 */ "KC1_176_Y\0" |
3199 | | /* 10570 */ "T76_Y\0" |
3200 | | /* 10576 */ "Addr76_Y\0" |
3201 | | /* 10585 */ "KC1_186_Y\0" |
3202 | | /* 10595 */ "T86_Y\0" |
3203 | | /* 10601 */ "Addr86_Y\0" |
3204 | | /* 10610 */ "T96_Y\0" |
3205 | | /* 10616 */ "Addr96_Y\0" |
3206 | | /* 10625 */ "T6_Y\0" |
3207 | | /* 10630 */ "Addr6_Y\0" |
3208 | | /* 10638 */ "T107_Y\0" |
3209 | | /* 10645 */ "Addr107_Y\0" |
3210 | | /* 10655 */ "T117_Y\0" |
3211 | | /* 10662 */ "Addr117_Y\0" |
3212 | | /* 10672 */ "T17_Y\0" |
3213 | | /* 10678 */ "Addr17_Y\0" |
3214 | | /* 10687 */ "T127_Y\0" |
3215 | | /* 10694 */ "Addr127_Y\0" |
3216 | | /* 10704 */ "T27_Y\0" |
3217 | | /* 10710 */ "Addr27_Y\0" |
3218 | | /* 10719 */ "KC0_137_Y\0" |
3219 | | /* 10729 */ "T37_Y\0" |
3220 | | /* 10735 */ "Addr37_Y\0" |
3221 | | /* 10744 */ "KC0_147_Y\0" |
3222 | | /* 10754 */ "T47_Y\0" |
3223 | | /* 10760 */ "Addr47_Y\0" |
3224 | | /* 10769 */ "KC0_157_Y\0" |
3225 | | /* 10779 */ "T57_Y\0" |
3226 | | /* 10785 */ "Addr57_Y\0" |
3227 | | /* 10794 */ "KC1_167_Y\0" |
3228 | | /* 10804 */ "T67_Y\0" |
3229 | | /* 10810 */ "Addr67_Y\0" |
3230 | | /* 10819 */ "KC1_177_Y\0" |
3231 | | /* 10829 */ "T77_Y\0" |
3232 | | /* 10835 */ "Addr77_Y\0" |
3233 | | /* 10844 */ "KC1_187_Y\0" |
3234 | | /* 10854 */ "T87_Y\0" |
3235 | | /* 10860 */ "Addr87_Y\0" |
3236 | | /* 10869 */ "T97_Y\0" |
3237 | | /* 10875 */ "Addr97_Y\0" |
3238 | | /* 10884 */ "T7_Y\0" |
3239 | | /* 10889 */ "Addr7_Y\0" |
3240 | | /* 10897 */ "T108_Y\0" |
3241 | | /* 10904 */ "Addr108_Y\0" |
3242 | | /* 10914 */ "T118_Y\0" |
3243 | | /* 10921 */ "Addr118_Y\0" |
3244 | | /* 10931 */ "T18_Y\0" |
3245 | | /* 10937 */ "Addr18_Y\0" |
3246 | | /* 10946 */ "KC0_128_Y\0" |
3247 | | /* 10956 */ "T28_Y\0" |
3248 | | /* 10962 */ "Addr28_Y\0" |
3249 | | /* 10971 */ "KC0_138_Y\0" |
3250 | | /* 10981 */ "T38_Y\0" |
3251 | | /* 10987 */ "Addr38_Y\0" |
3252 | | /* 10996 */ "KC0_148_Y\0" |
3253 | | /* 11006 */ "T48_Y\0" |
3254 | | /* 11012 */ "Addr48_Y\0" |
3255 | | /* 11021 */ "KC0_158_Y\0" |
3256 | | /* 11031 */ "T58_Y\0" |
3257 | | /* 11037 */ "Addr58_Y\0" |
3258 | | /* 11046 */ "KC1_168_Y\0" |
3259 | | /* 11056 */ "T68_Y\0" |
3260 | | /* 11062 */ "Addr68_Y\0" |
3261 | | /* 11071 */ "KC1_178_Y\0" |
3262 | | /* 11081 */ "T78_Y\0" |
3263 | | /* 11087 */ "Addr78_Y\0" |
3264 | | /* 11096 */ "KC1_188_Y\0" |
3265 | | /* 11106 */ "T88_Y\0" |
3266 | | /* 11112 */ "Addr88_Y\0" |
3267 | | /* 11121 */ "T98_Y\0" |
3268 | | /* 11127 */ "Addr98_Y\0" |
3269 | | /* 11136 */ "T8_Y\0" |
3270 | | /* 11141 */ "Addr8_Y\0" |
3271 | | /* 11149 */ "T109_Y\0" |
3272 | | /* 11156 */ "Addr109_Y\0" |
3273 | | /* 11166 */ "T119_Y\0" |
3274 | | /* 11173 */ "Addr119_Y\0" |
3275 | | /* 11183 */ "T19_Y\0" |
3276 | | /* 11189 */ "Addr19_Y\0" |
3277 | | /* 11198 */ "KC0_129_Y\0" |
3278 | | /* 11208 */ "T29_Y\0" |
3279 | | /* 11214 */ "Addr29_Y\0" |
3280 | | /* 11223 */ "KC0_139_Y\0" |
3281 | | /* 11233 */ "T39_Y\0" |
3282 | | /* 11239 */ "Addr39_Y\0" |
3283 | | /* 11248 */ "KC0_149_Y\0" |
3284 | | /* 11258 */ "T49_Y\0" |
3285 | | /* 11264 */ "Addr49_Y\0" |
3286 | | /* 11273 */ "KC0_159_Y\0" |
3287 | | /* 11283 */ "T59_Y\0" |
3288 | | /* 11289 */ "Addr59_Y\0" |
3289 | | /* 11298 */ "KC1_169_Y\0" |
3290 | | /* 11308 */ "T69_Y\0" |
3291 | | /* 11314 */ "Addr69_Y\0" |
3292 | | /* 11323 */ "KC1_179_Y\0" |
3293 | | /* 11333 */ "T79_Y\0" |
3294 | | /* 11339 */ "Addr79_Y\0" |
3295 | | /* 11348 */ "KC1_189_Y\0" |
3296 | | /* 11358 */ "T89_Y\0" |
3297 | | /* 11364 */ "Addr89_Y\0" |
3298 | | /* 11373 */ "T99_Y\0" |
3299 | | /* 11379 */ "Addr99_Y\0" |
3300 | | /* 11388 */ "T9_Y\0" |
3301 | | /* 11393 */ "Addr9_Y\0" |
3302 | | /* 11401 */ "ALU_LITERAL_Y\0" |
3303 | | /* 11415 */ "PV_Y\0" |
3304 | | /* 11420 */ "T100_Z\0" |
3305 | | /* 11427 */ "Addr100_Z\0" |
3306 | | /* 11437 */ "T110_Z\0" |
3307 | | /* 11444 */ "Addr110_Z\0" |
3308 | | /* 11454 */ "T10_Z\0" |
3309 | | /* 11460 */ "Addr10_Z\0" |
3310 | | /* 11469 */ "T120_Z\0" |
3311 | | /* 11476 */ "Addr120_Z\0" |
3312 | | /* 11486 */ "T20_Z\0" |
3313 | | /* 11492 */ "Addr20_Z\0" |
3314 | | /* 11501 */ "KC0_130_Z\0" |
3315 | | /* 11511 */ "T30_Z\0" |
3316 | | /* 11517 */ "Addr30_Z\0" |
3317 | | /* 11526 */ "KC0_140_Z\0" |
3318 | | /* 11536 */ "T40_Z\0" |
3319 | | /* 11542 */ "Addr40_Z\0" |
3320 | | /* 11551 */ "KC0_150_Z\0" |
3321 | | /* 11561 */ "T50_Z\0" |
3322 | | /* 11567 */ "Addr50_Z\0" |
3323 | | /* 11576 */ "KC1_160_Z\0" |
3324 | | /* 11586 */ "T60_Z\0" |
3325 | | /* 11592 */ "Addr60_Z\0" |
3326 | | /* 11601 */ "KC1_170_Z\0" |
3327 | | /* 11611 */ "T70_Z\0" |
3328 | | /* 11617 */ "Addr70_Z\0" |
3329 | | /* 11626 */ "KC1_180_Z\0" |
3330 | | /* 11636 */ "T80_Z\0" |
3331 | | /* 11642 */ "Addr80_Z\0" |
3332 | | /* 11651 */ "KC1_190_Z\0" |
3333 | | /* 11661 */ "T90_Z\0" |
3334 | | /* 11667 */ "Addr90_Z\0" |
3335 | | /* 11676 */ "T0_Z\0" |
3336 | | /* 11681 */ "Addr0_Z\0" |
3337 | | /* 11689 */ "T101_Z\0" |
3338 | | /* 11696 */ "Addr101_Z\0" |
3339 | | /* 11706 */ "V01_Z\0" |
3340 | | /* 11712 */ "T111_Z\0" |
3341 | | /* 11719 */ "Addr111_Z\0" |
3342 | | /* 11729 */ "T11_Z\0" |
3343 | | /* 11735 */ "Addr11_Z\0" |
3344 | | /* 11744 */ "T121_Z\0" |
3345 | | /* 11751 */ "Addr121_Z\0" |
3346 | | /* 11761 */ "T21_Z\0" |
3347 | | /* 11767 */ "Addr21_Z\0" |
3348 | | /* 11776 */ "KC0_131_Z\0" |
3349 | | /* 11786 */ "T31_Z\0" |
3350 | | /* 11792 */ "Addr31_Z\0" |
3351 | | /* 11801 */ "KC0_141_Z\0" |
3352 | | /* 11811 */ "T41_Z\0" |
3353 | | /* 11817 */ "Addr41_Z\0" |
3354 | | /* 11826 */ "KC0_151_Z\0" |
3355 | | /* 11836 */ "T51_Z\0" |
3356 | | /* 11842 */ "Addr51_Z\0" |
3357 | | /* 11851 */ "KC1_161_Z\0" |
3358 | | /* 11861 */ "T61_Z\0" |
3359 | | /* 11867 */ "Addr61_Z\0" |
3360 | | /* 11876 */ "KC1_171_Z\0" |
3361 | | /* 11886 */ "T71_Z\0" |
3362 | | /* 11892 */ "Addr71_Z\0" |
3363 | | /* 11901 */ "KC1_181_Z\0" |
3364 | | /* 11911 */ "T81_Z\0" |
3365 | | /* 11917 */ "Addr81_Z\0" |
3366 | | /* 11926 */ "KC1_191_Z\0" |
3367 | | /* 11936 */ "T91_Z\0" |
3368 | | /* 11942 */ "Addr91_Z\0" |
3369 | | /* 11951 */ "T1_Z\0" |
3370 | | /* 11956 */ "Addr1_Z\0" |
3371 | | /* 11964 */ "T102_Z\0" |
3372 | | /* 11971 */ "Addr102_Z\0" |
3373 | | /* 11981 */ "T112_Z\0" |
3374 | | /* 11988 */ "Addr112_Z\0" |
3375 | | /* 11998 */ "T12_Z\0" |
3376 | | /* 12004 */ "Addr12_Z\0" |
3377 | | /* 12013 */ "T122_Z\0" |
3378 | | /* 12020 */ "Addr122_Z\0" |
3379 | | /* 12030 */ "T22_Z\0" |
3380 | | /* 12036 */ "Addr22_Z\0" |
3381 | | /* 12045 */ "KC0_132_Z\0" |
3382 | | /* 12055 */ "T32_Z\0" |
3383 | | /* 12061 */ "Addr32_Z\0" |
3384 | | /* 12070 */ "KC0_142_Z\0" |
3385 | | /* 12080 */ "T42_Z\0" |
3386 | | /* 12086 */ "Addr42_Z\0" |
3387 | | /* 12095 */ "KC0_152_Z\0" |
3388 | | /* 12105 */ "T52_Z\0" |
3389 | | /* 12111 */ "Addr52_Z\0" |
3390 | | /* 12120 */ "KC1_162_Z\0" |
3391 | | /* 12130 */ "T62_Z\0" |
3392 | | /* 12136 */ "Addr62_Z\0" |
3393 | | /* 12145 */ "KC1_172_Z\0" |
3394 | | /* 12155 */ "T72_Z\0" |
3395 | | /* 12161 */ "Addr72_Z\0" |
3396 | | /* 12170 */ "KC1_182_Z\0" |
3397 | | /* 12180 */ "T82_Z\0" |
3398 | | /* 12186 */ "Addr82_Z\0" |
3399 | | /* 12195 */ "T92_Z\0" |
3400 | | /* 12201 */ "Addr92_Z\0" |
3401 | | /* 12210 */ "T2_Z\0" |
3402 | | /* 12215 */ "Addr2_Z\0" |
3403 | | /* 12223 */ "T103_Z\0" |
3404 | | /* 12230 */ "Addr103_Z\0" |
3405 | | /* 12240 */ "T113_Z\0" |
3406 | | /* 12247 */ "Addr113_Z\0" |
3407 | | /* 12257 */ "T13_Z\0" |
3408 | | /* 12263 */ "Addr13_Z\0" |
3409 | | /* 12272 */ "V0123_Z\0" |
3410 | | /* 12280 */ "T123_Z\0" |
3411 | | /* 12287 */ "Addr123_Z\0" |
3412 | | /* 12297 */ "T23_Z\0" |
3413 | | /* 12303 */ "V23_Z\0" |
3414 | | /* 12309 */ "Addr23_Z\0" |
3415 | | /* 12318 */ "KC0_133_Z\0" |
3416 | | /* 12328 */ "T33_Z\0" |
3417 | | /* 12334 */ "Addr33_Z\0" |
3418 | | /* 12343 */ "KC0_143_Z\0" |
3419 | | /* 12353 */ "T43_Z\0" |
3420 | | /* 12359 */ "Addr43_Z\0" |
3421 | | /* 12368 */ "KC0_153_Z\0" |
3422 | | /* 12378 */ "T53_Z\0" |
3423 | | /* 12384 */ "Addr53_Z\0" |
3424 | | /* 12393 */ "KC1_163_Z\0" |
3425 | | /* 12403 */ "T63_Z\0" |
3426 | | /* 12409 */ "Addr63_Z\0" |
3427 | | /* 12418 */ "KC1_173_Z\0" |
3428 | | /* 12428 */ "T73_Z\0" |
3429 | | /* 12434 */ "Addr73_Z\0" |
3430 | | /* 12443 */ "KC1_183_Z\0" |
3431 | | /* 12453 */ "T83_Z\0" |
3432 | | /* 12459 */ "Addr83_Z\0" |
3433 | | /* 12468 */ "T93_Z\0" |
3434 | | /* 12474 */ "Addr93_Z\0" |
3435 | | /* 12483 */ "T3_Z\0" |
3436 | | /* 12488 */ "Addr3_Z\0" |
3437 | | /* 12496 */ "T104_Z\0" |
3438 | | /* 12503 */ "Addr104_Z\0" |
3439 | | /* 12513 */ "T114_Z\0" |
3440 | | /* 12520 */ "Addr114_Z\0" |
3441 | | /* 12530 */ "T14_Z\0" |
3442 | | /* 12536 */ "Addr14_Z\0" |
3443 | | /* 12545 */ "T124_Z\0" |
3444 | | /* 12552 */ "Addr124_Z\0" |
3445 | | /* 12562 */ "T24_Z\0" |
3446 | | /* 12568 */ "Addr24_Z\0" |
3447 | | /* 12577 */ "KC0_134_Z\0" |
3448 | | /* 12587 */ "T34_Z\0" |
3449 | | /* 12593 */ "Addr34_Z\0" |
3450 | | /* 12602 */ "KC0_144_Z\0" |
3451 | | /* 12612 */ "T44_Z\0" |
3452 | | /* 12618 */ "Addr44_Z\0" |
3453 | | /* 12627 */ "KC0_154_Z\0" |
3454 | | /* 12637 */ "T54_Z\0" |
3455 | | /* 12643 */ "Addr54_Z\0" |
3456 | | /* 12652 */ "KC1_164_Z\0" |
3457 | | /* 12662 */ "T64_Z\0" |
3458 | | /* 12668 */ "Addr64_Z\0" |
3459 | | /* 12677 */ "KC1_174_Z\0" |
3460 | | /* 12687 */ "T74_Z\0" |
3461 | | /* 12693 */ "Addr74_Z\0" |
3462 | | /* 12702 */ "KC1_184_Z\0" |
3463 | | /* 12712 */ "T84_Z\0" |
3464 | | /* 12718 */ "Addr84_Z\0" |
3465 | | /* 12727 */ "T94_Z\0" |
3466 | | /* 12733 */ "Addr94_Z\0" |
3467 | | /* 12742 */ "T4_Z\0" |
3468 | | /* 12747 */ "Addr4_Z\0" |
3469 | | /* 12755 */ "T105_Z\0" |
3470 | | /* 12762 */ "Addr105_Z\0" |
3471 | | /* 12772 */ "T115_Z\0" |
3472 | | /* 12779 */ "Addr115_Z\0" |
3473 | | /* 12789 */ "T15_Z\0" |
3474 | | /* 12795 */ "Addr15_Z\0" |
3475 | | /* 12804 */ "T125_Z\0" |
3476 | | /* 12811 */ "Addr125_Z\0" |
3477 | | /* 12821 */ "T25_Z\0" |
3478 | | /* 12827 */ "Addr25_Z\0" |
3479 | | /* 12836 */ "KC0_135_Z\0" |
3480 | | /* 12846 */ "T35_Z\0" |
3481 | | /* 12852 */ "Addr35_Z\0" |
3482 | | /* 12861 */ "KC0_145_Z\0" |
3483 | | /* 12871 */ "T45_Z\0" |
3484 | | /* 12877 */ "Addr45_Z\0" |
3485 | | /* 12886 */ "KC0_155_Z\0" |
3486 | | /* 12896 */ "T55_Z\0" |
3487 | | /* 12902 */ "Addr55_Z\0" |
3488 | | /* 12911 */ "KC1_165_Z\0" |
3489 | | /* 12921 */ "T65_Z\0" |
3490 | | /* 12927 */ "Addr65_Z\0" |
3491 | | /* 12936 */ "KC1_175_Z\0" |
3492 | | /* 12946 */ "T75_Z\0" |
3493 | | /* 12952 */ "Addr75_Z\0" |
3494 | | /* 12961 */ "KC1_185_Z\0" |
3495 | | /* 12971 */ "T85_Z\0" |
3496 | | /* 12977 */ "Addr85_Z\0" |
3497 | | /* 12986 */ "T95_Z\0" |
3498 | | /* 12992 */ "Addr95_Z\0" |
3499 | | /* 13001 */ "T5_Z\0" |
3500 | | /* 13006 */ "Addr5_Z\0" |
3501 | | /* 13014 */ "T106_Z\0" |
3502 | | /* 13021 */ "Addr106_Z\0" |
3503 | | /* 13031 */ "T116_Z\0" |
3504 | | /* 13038 */ "Addr116_Z\0" |
3505 | | /* 13048 */ "T16_Z\0" |
3506 | | /* 13054 */ "Addr16_Z\0" |
3507 | | /* 13063 */ "T126_Z\0" |
3508 | | /* 13070 */ "Addr126_Z\0" |
3509 | | /* 13080 */ "T26_Z\0" |
3510 | | /* 13086 */ "Addr26_Z\0" |
3511 | | /* 13095 */ "KC0_136_Z\0" |
3512 | | /* 13105 */ "T36_Z\0" |
3513 | | /* 13111 */ "Addr36_Z\0" |
3514 | | /* 13120 */ "KC0_146_Z\0" |
3515 | | /* 13130 */ "T46_Z\0" |
3516 | | /* 13136 */ "Addr46_Z\0" |
3517 | | /* 13145 */ "KC0_156_Z\0" |
3518 | | /* 13155 */ "T56_Z\0" |
3519 | | /* 13161 */ "Addr56_Z\0" |
3520 | | /* 13170 */ "KC1_166_Z\0" |
3521 | | /* 13180 */ "T66_Z\0" |
3522 | | /* 13186 */ "Addr66_Z\0" |
3523 | | /* 13195 */ "KC1_176_Z\0" |
3524 | | /* 13205 */ "T76_Z\0" |
3525 | | /* 13211 */ "Addr76_Z\0" |
3526 | | /* 13220 */ "KC1_186_Z\0" |
3527 | | /* 13230 */ "T86_Z\0" |
3528 | | /* 13236 */ "Addr86_Z\0" |
3529 | | /* 13245 */ "T96_Z\0" |
3530 | | /* 13251 */ "Addr96_Z\0" |
3531 | | /* 13260 */ "T6_Z\0" |
3532 | | /* 13265 */ "Addr6_Z\0" |
3533 | | /* 13273 */ "T107_Z\0" |
3534 | | /* 13280 */ "Addr107_Z\0" |
3535 | | /* 13290 */ "T117_Z\0" |
3536 | | /* 13297 */ "Addr117_Z\0" |
3537 | | /* 13307 */ "T17_Z\0" |
3538 | | /* 13313 */ "Addr17_Z\0" |
3539 | | /* 13322 */ "T127_Z\0" |
3540 | | /* 13329 */ "Addr127_Z\0" |
3541 | | /* 13339 */ "T27_Z\0" |
3542 | | /* 13345 */ "Addr27_Z\0" |
3543 | | /* 13354 */ "KC0_137_Z\0" |
3544 | | /* 13364 */ "T37_Z\0" |
3545 | | /* 13370 */ "Addr37_Z\0" |
3546 | | /* 13379 */ "KC0_147_Z\0" |
3547 | | /* 13389 */ "T47_Z\0" |
3548 | | /* 13395 */ "Addr47_Z\0" |
3549 | | /* 13404 */ "KC0_157_Z\0" |
3550 | | /* 13414 */ "T57_Z\0" |
3551 | | /* 13420 */ "Addr57_Z\0" |
3552 | | /* 13429 */ "KC1_167_Z\0" |
3553 | | /* 13439 */ "T67_Z\0" |
3554 | | /* 13445 */ "Addr67_Z\0" |
3555 | | /* 13454 */ "KC1_177_Z\0" |
3556 | | /* 13464 */ "T77_Z\0" |
3557 | | /* 13470 */ "Addr77_Z\0" |
3558 | | /* 13479 */ "KC1_187_Z\0" |
3559 | | /* 13489 */ "T87_Z\0" |
3560 | | /* 13495 */ "Addr87_Z\0" |
3561 | | /* 13504 */ "T97_Z\0" |
3562 | | /* 13510 */ "Addr97_Z\0" |
3563 | | /* 13519 */ "T7_Z\0" |
3564 | | /* 13524 */ "Addr7_Z\0" |
3565 | | /* 13532 */ "T108_Z\0" |
3566 | | /* 13539 */ "Addr108_Z\0" |
3567 | | /* 13549 */ "T118_Z\0" |
3568 | | /* 13556 */ "Addr118_Z\0" |
3569 | | /* 13566 */ "T18_Z\0" |
3570 | | /* 13572 */ "Addr18_Z\0" |
3571 | | /* 13581 */ "KC0_128_Z\0" |
3572 | | /* 13591 */ "T28_Z\0" |
3573 | | /* 13597 */ "Addr28_Z\0" |
3574 | | /* 13606 */ "KC0_138_Z\0" |
3575 | | /* 13616 */ "T38_Z\0" |
3576 | | /* 13622 */ "Addr38_Z\0" |
3577 | | /* 13631 */ "KC0_148_Z\0" |
3578 | | /* 13641 */ "T48_Z\0" |
3579 | | /* 13647 */ "Addr48_Z\0" |
3580 | | /* 13656 */ "KC0_158_Z\0" |
3581 | | /* 13666 */ "T58_Z\0" |
3582 | | /* 13672 */ "Addr58_Z\0" |
3583 | | /* 13681 */ "KC1_168_Z\0" |
3584 | | /* 13691 */ "T68_Z\0" |
3585 | | /* 13697 */ "Addr68_Z\0" |
3586 | | /* 13706 */ "KC1_178_Z\0" |
3587 | | /* 13716 */ "T78_Z\0" |
3588 | | /* 13722 */ "Addr78_Z\0" |
3589 | | /* 13731 */ "KC1_188_Z\0" |
3590 | | /* 13741 */ "T88_Z\0" |
3591 | | /* 13747 */ "Addr88_Z\0" |
3592 | | /* 13756 */ "T98_Z\0" |
3593 | | /* 13762 */ "Addr98_Z\0" |
3594 | | /* 13771 */ "T8_Z\0" |
3595 | | /* 13776 */ "Addr8_Z\0" |
3596 | | /* 13784 */ "T109_Z\0" |
3597 | | /* 13791 */ "Addr109_Z\0" |
3598 | | /* 13801 */ "T119_Z\0" |
3599 | | /* 13808 */ "Addr119_Z\0" |
3600 | | /* 13818 */ "T19_Z\0" |
3601 | | /* 13824 */ "Addr19_Z\0" |
3602 | | /* 13833 */ "KC0_129_Z\0" |
3603 | | /* 13843 */ "T29_Z\0" |
3604 | | /* 13849 */ "Addr29_Z\0" |
3605 | | /* 13858 */ "KC0_139_Z\0" |
3606 | | /* 13868 */ "T39_Z\0" |
3607 | | /* 13874 */ "Addr39_Z\0" |
3608 | | /* 13883 */ "KC0_149_Z\0" |
3609 | | /* 13893 */ "T49_Z\0" |
3610 | | /* 13899 */ "Addr49_Z\0" |
3611 | | /* 13908 */ "KC0_159_Z\0" |
3612 | | /* 13918 */ "T59_Z\0" |
3613 | | /* 13924 */ "Addr59_Z\0" |
3614 | | /* 13933 */ "KC1_169_Z\0" |
3615 | | /* 13943 */ "T69_Z\0" |
3616 | | /* 13949 */ "Addr69_Z\0" |
3617 | | /* 13958 */ "KC1_179_Z\0" |
3618 | | /* 13968 */ "T79_Z\0" |
3619 | | /* 13974 */ "Addr79_Z\0" |
3620 | | /* 13983 */ "KC1_189_Z\0" |
3621 | | /* 13993 */ "T89_Z\0" |
3622 | | /* 13999 */ "Addr89_Z\0" |
3623 | | /* 14008 */ "T99_Z\0" |
3624 | | /* 14014 */ "Addr99_Z\0" |
3625 | | /* 14023 */ "T9_Z\0" |
3626 | | /* 14028 */ "Addr9_Z\0" |
3627 | | /* 14036 */ "ALU_LITERAL_Z\0" |
3628 | | /* 14050 */ "PV_Z\0" |
3629 | | }; |
3630 | | #ifdef __GNUC__ |
3631 | | #pragma GCC diagnostic pop |
3632 | | #endif |
3633 | | |
3634 | | extern const MCRegisterDesc R600RegDesc[] = { // Descriptors |
3635 | | { 12, 0, 0, 0, 0, 0 }, |
3636 | | { 584, 4, 4, 2, 16384, 13 }, |
3637 | | { 5212, 4, 4, 2, 16385, 13 }, |
3638 | | { 7847, 4, 4, 2, 16386, 13 }, |
3639 | | { 11401, 4, 4, 2, 16387, 13 }, |
3640 | | { 14036, 4, 4, 2, 16388, 13 }, |
3641 | | { 506, 4, 4, 2, 16389, 13 }, |
3642 | | { 7861, 4, 4, 2, 16390, 13 }, |
3643 | | { 501, 4, 4, 2, 16391, 13 }, |
3644 | | { 540, 4, 4, 2, 16392, 13 }, |
3645 | | { 433, 4, 4, 2, 16393, 13 }, |
3646 | | { 450, 4, 4, 2, 16394, 13 }, |
3647 | | { 497, 4, 4, 2, 16395, 13 }, |
3648 | | { 463, 4, 4, 2, 16396, 13 }, |
3649 | | { 467, 4, 4, 2, 16397, 13 }, |
3650 | | { 576, 4, 4, 2, 16398, 13 }, |
3651 | | { 429, 4, 4, 2, 16399, 13 }, |
3652 | | { 530, 4, 4, 2, 16400, 13 }, |
3653 | | { 446, 4, 4, 2, 16401, 13 }, |
3654 | | { 535, 4, 4, 2, 16402, 13 }, |
3655 | | { 562, 4, 4, 2, 16403, 13 }, |
3656 | | { 484, 4, 4, 2, 16404, 13 }, |
3657 | | { 471, 4, 4, 2, 16405, 13 }, |
3658 | | { 516, 4, 4, 2, 16406, 13 }, |
3659 | | { 559, 4, 4, 2, 16407, 13 }, |
3660 | | { 5226, 4, 4, 2, 16408, 13 }, |
3661 | | { 7866, 4, 4, 2, 16409, 13 }, |
3662 | | { 11415, 4, 4, 2, 16410, 13 }, |
3663 | | { 14050, 4, 4, 2, 16411, 13 }, |
3664 | | { 525, 4, 4, 2, 16412, 13 }, |
3665 | | { 325, 4, 4, 2, 16413, 13 }, |
3666 | | { 377, 4, 4, 2, 16414, 13 }, |
3667 | | { 0, 4, 4, 2, 16415, 13 }, |
3668 | | { 52, 4, 4, 2, 16416, 13 }, |
3669 | | { 91, 4, 4, 2, 16417, 13 }, |
3670 | | { 130, 4, 4, 2, 16418, 13 }, |
3671 | | { 169, 4, 4, 2, 16419, 13 }, |
3672 | | { 208, 4, 4, 2, 16420, 13 }, |
3673 | | { 247, 4, 4, 2, 16421, 13 }, |
3674 | | { 286, 4, 4, 2, 16422, 13 }, |
3675 | | { 338, 4, 4, 2, 16423, 13 }, |
3676 | | { 390, 4, 4, 2, 16424, 13 }, |
3677 | | { 13, 4, 4, 2, 16425, 13 }, |
3678 | | { 65, 4, 4, 2, 16426, 13 }, |
3679 | | { 104, 4, 4, 2, 16427, 13 }, |
3680 | | { 143, 4, 4, 2, 16428, 13 }, |
3681 | | { 182, 4, 4, 2, 16429, 13 }, |
3682 | | { 221, 4, 4, 2, 16430, 13 }, |
3683 | | { 260, 4, 4, 2, 16431, 13 }, |
3684 | | { 299, 4, 4, 2, 16432, 13 }, |
3685 | | { 351, 4, 4, 2, 16433, 13 }, |
3686 | | { 403, 4, 4, 2, 16434, 13 }, |
3687 | | { 26, 4, 4, 2, 16435, 13 }, |
3688 | | { 78, 4, 4, 2, 16436, 13 }, |
3689 | | { 117, 4, 4, 2, 16437, 13 }, |
3690 | | { 156, 4, 4, 2, 16438, 13 }, |
3691 | | { 195, 4, 4, 2, 16439, 13 }, |
3692 | | { 234, 4, 4, 2, 16440, 13 }, |
3693 | | { 273, 4, 4, 2, 16441, 13 }, |
3694 | | { 312, 4, 4, 2, 16442, 13 }, |
3695 | | { 364, 4, 4, 2, 16443, 13 }, |
3696 | | { 416, 4, 4, 2, 16444, 13 }, |
3697 | | { 39, 4, 4, 2, 16445, 13 }, |
3698 | | { 2857, 4, 4, 2, 16446, 13 }, |
3699 | | { 3132, 4, 4, 2, 16447, 13 }, |
3700 | | { 3391, 4, 4, 2, 16448, 13 }, |
3701 | | { 3664, 4, 4, 2, 16449, 13 }, |
3702 | | { 3923, 4, 4, 2, 16450, 13 }, |
3703 | | { 4182, 4, 4, 2, 16451, 13 }, |
3704 | | { 4441, 4, 4, 2, 16452, 13 }, |
3705 | | { 4700, 4, 4, 2, 16453, 13 }, |
3706 | | { 4952, 4, 4, 2, 16454, 13 }, |
3707 | | { 5204, 4, 4, 2, 16455, 13 }, |
3708 | | { 2636, 4, 4, 2, 16456, 13 }, |
3709 | | { 2911, 4, 4, 2, 16457, 13 }, |
3710 | | { 3180, 4, 4, 2, 16458, 13 }, |
3711 | | { 3439, 4, 4, 2, 16459, 13 }, |
3712 | | { 3712, 4, 4, 2, 16460, 13 }, |
3713 | | { 3971, 4, 4, 2, 16461, 13 }, |
3714 | | { 4230, 4, 4, 2, 16462, 13 }, |
3715 | | { 4489, 4, 4, 2, 16463, 13 }, |
3716 | | { 4748, 4, 4, 2, 16464, 13 }, |
3717 | | { 5000, 4, 4, 2, 16465, 13 }, |
3718 | | { 2668, 4, 4, 2, 16466, 13 }, |
3719 | | { 2943, 4, 4, 2, 16467, 13 }, |
3720 | | { 3212, 4, 4, 2, 16468, 13 }, |
3721 | | { 3485, 4, 4, 2, 16469, 13 }, |
3722 | | { 3744, 4, 4, 2, 16470, 13 }, |
3723 | | { 4003, 4, 4, 2, 16471, 13 }, |
3724 | | { 4262, 4, 4, 2, 16472, 13 }, |
3725 | | { 4521, 4, 4, 2, 16473, 13 }, |
3726 | | { 4773, 4, 4, 2, 16474, 13 }, |
3727 | | { 5025, 4, 4, 2, 16475, 13 }, |
3728 | | { 2693, 4, 4, 2, 16476, 13 }, |
3729 | | { 2968, 4, 4, 2, 16477, 13 }, |
3730 | | { 3237, 4, 4, 2, 16478, 13 }, |
3731 | | { 3510, 4, 4, 2, 16479, 13 }, |
3732 | | { 3769, 4, 4, 2, 16480, 13 }, |
3733 | | { 4028, 4, 4, 2, 16481, 13 }, |
3734 | | { 4287, 4, 4, 2, 16482, 13 }, |
3735 | | { 4546, 4, 4, 2, 16483, 13 }, |
3736 | | { 4798, 4, 4, 2, 16484, 13 }, |
3737 | | { 5050, 4, 4, 2, 16485, 13 }, |
3738 | | { 2718, 4, 4, 2, 16486, 13 }, |
3739 | | { 2993, 4, 4, 2, 16487, 13 }, |
3740 | | { 3262, 4, 4, 2, 16488, 13 }, |
3741 | | { 3535, 4, 4, 2, 16489, 13 }, |
3742 | | { 3794, 4, 4, 2, 16490, 13 }, |
3743 | | { 4053, 4, 4, 2, 16491, 13 }, |
3744 | | { 4312, 4, 4, 2, 16492, 13 }, |
3745 | | { 4571, 4, 4, 2, 16493, 13 }, |
3746 | | { 4823, 4, 4, 2, 16494, 13 }, |
3747 | | { 5075, 4, 4, 2, 16495, 13 }, |
3748 | | { 2743, 4, 4, 2, 16496, 13 }, |
3749 | | { 3018, 4, 4, 2, 16497, 13 }, |
3750 | | { 3287, 4, 4, 2, 16498, 13 }, |
3751 | | { 3560, 4, 4, 2, 16499, 13 }, |
3752 | | { 3819, 4, 4, 2, 16500, 13 }, |
3753 | | { 4078, 4, 4, 2, 16501, 13 }, |
3754 | | { 4337, 4, 4, 2, 16502, 13 }, |
3755 | | { 4596, 4, 4, 2, 16503, 13 }, |
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5220 | | { 10535, 4, 12, 2, 17674, 13 }, |
5221 | | { 10794, 4, 12, 2, 17676, 13 }, |
5222 | | { 11046, 4, 12, 2, 17678, 13 }, |
5223 | | { 11298, 4, 12, 2, 17680, 13 }, |
5224 | | { 8966, 4, 12, 2, 17682, 13 }, |
5225 | | { 9241, 4, 12, 2, 17684, 13 }, |
5226 | | { 9510, 4, 12, 2, 17686, 13 }, |
5227 | | { 9783, 4, 12, 2, 17688, 13 }, |
5228 | | { 10042, 4, 12, 2, 17690, 13 }, |
5229 | | { 10301, 4, 12, 2, 17692, 13 }, |
5230 | | { 10560, 4, 12, 2, 17694, 13 }, |
5231 | | { 10819, 4, 12, 2, 17696, 13 }, |
5232 | | { 11071, 4, 12, 2, 17698, 13 }, |
5233 | | { 11323, 4, 12, 2, 17700, 13 }, |
5234 | | { 8991, 4, 12, 2, 17702, 13 }, |
5235 | | { 9266, 4, 12, 2, 17704, 13 }, |
5236 | | { 9535, 4, 12, 2, 17706, 13 }, |
5237 | | { 9808, 4, 12, 2, 17708, 13 }, |
5238 | | { 10067, 4, 12, 2, 17710, 13 }, |
5239 | | { 10326, 4, 12, 2, 17712, 13 }, |
5240 | | { 10585, 4, 12, 2, 17714, 13 }, |
5241 | | { 10844, 4, 12, 2, 17716, 13 }, |
5242 | | { 11096, 4, 12, 2, 17718, 13 }, |
5243 | | { 11348, 4, 12, 2, 17720, 13 }, |
5244 | | { 9016, 4, 12, 2, 17722, 13 }, |
5245 | | { 9291, 4, 12, 2, 17724, 13 }, |
5246 | | { 13581, 4, 10, 2, 17599, 13 }, |
5247 | | { 13833, 4, 10, 2, 17601, 13 }, |
5248 | | { 11501, 4, 10, 2, 17603, 13 }, |
5249 | | { 11776, 4, 10, 2, 17605, 13 }, |
5250 | | { 12045, 4, 10, 2, 17607, 13 }, |
5251 | | { 12318, 4, 10, 2, 17609, 13 }, |
5252 | | { 12577, 4, 10, 2, 17611, 13 }, |
5253 | | { 12836, 4, 10, 2, 17613, 13 }, |
5254 | | { 13095, 4, 10, 2, 17615, 13 }, |
5255 | | { 13354, 4, 10, 2, 17617, 13 }, |
5256 | | { 13606, 4, 10, 2, 17619, 13 }, |
5257 | | { 13858, 4, 10, 2, 17621, 13 }, |
5258 | | { 11526, 4, 10, 2, 17623, 13 }, |
5259 | | { 11801, 4, 10, 2, 17625, 13 }, |
5260 | | { 12070, 4, 10, 2, 17627, 13 }, |
5261 | | { 12343, 4, 10, 2, 17629, 13 }, |
5262 | | { 12602, 4, 10, 2, 17631, 13 }, |
5263 | | { 12861, 4, 10, 2, 17633, 13 }, |
5264 | | { 13120, 4, 10, 2, 17635, 13 }, |
5265 | | { 13379, 4, 10, 2, 17637, 13 }, |
5266 | | { 13631, 4, 10, 2, 17639, 13 }, |
5267 | | { 13883, 4, 10, 2, 17641, 13 }, |
5268 | | { 11551, 4, 10, 2, 17643, 13 }, |
5269 | | { 11826, 4, 10, 2, 17645, 13 }, |
5270 | | { 12095, 4, 10, 2, 17647, 13 }, |
5271 | | { 12368, 4, 10, 2, 17649, 13 }, |
5272 | | { 12627, 4, 10, 2, 17651, 13 }, |
5273 | | { 12886, 4, 10, 2, 17653, 13 }, |
5274 | | { 13145, 4, 10, 2, 17655, 13 }, |
5275 | | { 13404, 4, 10, 2, 17657, 13 }, |
5276 | | { 13656, 4, 10, 2, 17659, 13 }, |
5277 | | { 13908, 4, 10, 2, 17661, 13 }, |
5278 | | { 11576, 4, 10, 2, 17663, 13 }, |
5279 | | { 11851, 4, 10, 2, 17665, 13 }, |
5280 | | { 12120, 4, 10, 2, 17667, 13 }, |
5281 | | { 12393, 4, 10, 2, 17669, 13 }, |
5282 | | { 12652, 4, 10, 2, 17671, 13 }, |
5283 | | { 12911, 4, 10, 2, 17673, 13 }, |
5284 | | { 13170, 4, 10, 2, 17675, 13 }, |
5285 | | { 13429, 4, 10, 2, 17677, 13 }, |
5286 | | { 13681, 4, 10, 2, 17679, 13 }, |
5287 | | { 13933, 4, 10, 2, 17681, 13 }, |
5288 | | { 11601, 4, 10, 2, 17683, 13 }, |
5289 | | { 11876, 4, 10, 2, 17685, 13 }, |
5290 | | { 12145, 4, 10, 2, 17687, 13 }, |
5291 | | { 12418, 4, 10, 2, 17689, 13 }, |
5292 | | { 12677, 4, 10, 2, 17691, 13 }, |
5293 | | { 12936, 4, 10, 2, 17693, 13 }, |
5294 | | { 13195, 4, 10, 2, 17695, 13 }, |
5295 | | { 13454, 4, 10, 2, 17697, 13 }, |
5296 | | { 13706, 4, 10, 2, 17699, 13 }, |
5297 | | { 13958, 4, 10, 2, 17701, 13 }, |
5298 | | { 11626, 4, 10, 2, 17703, 13 }, |
5299 | | { 11901, 4, 10, 2, 17705, 13 }, |
5300 | | { 12170, 4, 10, 2, 17707, 13 }, |
5301 | | { 12443, 4, 10, 2, 17709, 13 }, |
5302 | | { 12702, 4, 10, 2, 17711, 13 }, |
5303 | | { 12961, 4, 10, 2, 17713, 13 }, |
5304 | | { 13220, 4, 10, 2, 17715, 13 }, |
5305 | | { 13479, 4, 10, 2, 17717, 13 }, |
5306 | | { 13731, 4, 10, 2, 17719, 13 }, |
5307 | | { 13983, 4, 10, 2, 17721, 13 }, |
5308 | | { 11651, 4, 10, 2, 17723, 13 }, |
5309 | | { 11926, 4, 10, 2, 17725, 13 }, |
5310 | | }; |
5311 | | |
5312 | | extern const MCPhysReg R600RegUnitRoots[][2] = { |
5313 | | { R600::ALU_CONST }, |
5314 | | { R600::ALU_LITERAL_W }, |
5315 | | { R600::ALU_LITERAL_X }, |
5316 | | { R600::ALU_LITERAL_Y }, |
5317 | | { R600::ALU_LITERAL_Z }, |
5318 | | { R600::ALU_PARAM }, |
5319 | | { R600::AR_X }, |
5320 | | { R600::HALF }, |
5321 | | { R600::INDIRECT_BASE_ADDR }, |
5322 | | { R600::LDS_DIRECT_A }, |
5323 | | { R600::LDS_DIRECT_B }, |
5324 | | { R600::NEG_HALF }, |
5325 | | { R600::NEG_ONE }, |
5326 | | { R600::ONE }, |
5327 | | { R600::ONE_INT }, |
5328 | | { R600::OQA }, |
5329 | | { R600::OQAP }, |
5330 | | { R600::OQB }, |
5331 | | { R600::OQBP }, |
5332 | | { R600::PREDICATE_BIT }, |
5333 | | { R600::PRED_SEL_OFF }, |
5334 | | { R600::PRED_SEL_ONE }, |
5335 | | { R600::PRED_SEL_ZERO }, |
5336 | | { R600::PS }, |
5337 | | { R600::PV_W }, |
5338 | | { R600::PV_X }, |
5339 | | { R600::PV_Y }, |
5340 | | { R600::PV_Z }, |
5341 | | { R600::ZERO }, |
5342 | | { R600::ArrayBase448 }, |
5343 | | { R600::ArrayBase449 }, |
5344 | | { R600::ArrayBase450 }, |
5345 | | { R600::ArrayBase451 }, |
5346 | | { R600::ArrayBase452 }, |
5347 | | { R600::ArrayBase453 }, |
5348 | | { R600::ArrayBase454 }, |
5349 | | { R600::ArrayBase455 }, |
5350 | | { R600::ArrayBase456 }, |
5351 | | { R600::ArrayBase457 }, |
5352 | | { R600::ArrayBase458 }, |
5353 | | { R600::ArrayBase459 }, |
5354 | | { R600::ArrayBase460 }, |
5355 | | { R600::ArrayBase461 }, |
5356 | | { R600::ArrayBase462 }, |
5357 | | { R600::ArrayBase463 }, |
5358 | | { R600::ArrayBase464 }, |
5359 | | { R600::ArrayBase465 }, |
5360 | | { R600::ArrayBase466 }, |
5361 | | { R600::ArrayBase467 }, |
5362 | | { R600::ArrayBase468 }, |
5363 | | { R600::ArrayBase469 }, |
5364 | | { R600::ArrayBase470 }, |
5365 | | { R600::ArrayBase471 }, |
5366 | | { R600::ArrayBase472 }, |
5367 | | { R600::ArrayBase473 }, |
5368 | | { R600::ArrayBase474 }, |
5369 | | { R600::ArrayBase475 }, |
5370 | | { R600::ArrayBase476 }, |
5371 | | { R600::ArrayBase477 }, |
5372 | | { R600::ArrayBase478 }, |
5373 | | { R600::ArrayBase479 }, |
5374 | | { R600::ArrayBase480 }, |
5375 | | { R600::Addr0_W }, |
5376 | | { R600::Addr1_W }, |
5377 | | { R600::Addr2_W }, |
5378 | | { R600::Addr3_W }, |
5379 | | { R600::Addr4_W }, |
5380 | | { R600::Addr5_W }, |
5381 | | { R600::Addr6_W }, |
5382 | | { R600::Addr7_W }, |
5383 | | { R600::Addr8_W }, |
5384 | | { R600::Addr9_W }, |
5385 | | { R600::Addr10_W }, |
5386 | | { R600::Addr11_W }, |
5387 | | { R600::Addr12_W }, |
5388 | | { R600::Addr13_W }, |
5389 | | { R600::Addr14_W }, |
5390 | | { R600::Addr15_W }, |
5391 | | { R600::Addr16_W }, |
5392 | | { R600::Addr17_W }, |
5393 | | { R600::Addr18_W }, |
5394 | | { R600::Addr19_W }, |
5395 | | { R600::Addr20_W }, |
5396 | | { R600::Addr21_W }, |
5397 | | { R600::Addr22_W }, |
5398 | | { R600::Addr23_W }, |
5399 | | { R600::Addr24_W }, |
5400 | | { R600::Addr25_W }, |
5401 | | { R600::Addr26_W }, |
5402 | | { R600::Addr27_W }, |
5403 | | { R600::Addr28_W }, |
5404 | | { R600::Addr29_W }, |
5405 | | { R600::Addr30_W }, |
5406 | | { R600::Addr31_W }, |
5407 | | { R600::Addr32_W }, |
5408 | | { R600::Addr33_W }, |
5409 | | { R600::Addr34_W }, |
5410 | | { R600::Addr35_W }, |
5411 | | { R600::Addr36_W }, |
5412 | | { R600::Addr37_W }, |
5413 | | { R600::Addr38_W }, |
5414 | | { R600::Addr39_W }, |
5415 | | { R600::Addr40_W }, |
5416 | | { R600::Addr41_W }, |
5417 | | { R600::Addr42_W }, |
5418 | | { R600::Addr43_W }, |
5419 | | { R600::Addr44_W }, |
5420 | | { R600::Addr45_W }, |
5421 | | { R600::Addr46_W }, |
5422 | | { R600::Addr47_W }, |
5423 | | { R600::Addr48_W }, |
5424 | | { R600::Addr49_W }, |
5425 | | { R600::Addr50_W }, |
5426 | | { R600::Addr51_W }, |
5427 | | { R600::Addr52_W }, |
5428 | | { R600::Addr53_W }, |
5429 | | { R600::Addr54_W }, |
5430 | | { R600::Addr55_W }, |
5431 | | { R600::Addr56_W }, |
5432 | | { R600::Addr57_W }, |
5433 | | { R600::Addr58_W }, |
5434 | | { R600::Addr59_W }, |
5435 | | { R600::Addr60_W }, |
5436 | | { R600::Addr61_W }, |
5437 | | { R600::Addr62_W }, |
5438 | | { R600::Addr63_W }, |
5439 | | { R600::Addr64_W }, |
5440 | | { R600::Addr65_W }, |
5441 | | { R600::Addr66_W }, |
5442 | | { R600::Addr67_W }, |
5443 | | { R600::Addr68_W }, |
5444 | | { R600::Addr69_W }, |
5445 | | { R600::Addr70_W }, |
5446 | | { R600::Addr71_W }, |
5447 | | { R600::Addr72_W }, |
5448 | | { R600::Addr73_W }, |
5449 | | { R600::Addr74_W }, |
5450 | | { R600::Addr75_W }, |
5451 | | { R600::Addr76_W }, |
5452 | | { R600::Addr77_W }, |
5453 | | { R600::Addr78_W }, |
5454 | | { R600::Addr79_W }, |
5455 | | { R600::Addr80_W }, |
5456 | | { R600::Addr81_W }, |
5457 | | { R600::Addr82_W }, |
5458 | | { R600::Addr83_W }, |
5459 | | { R600::Addr84_W }, |
5460 | | { R600::Addr85_W }, |
5461 | | { R600::Addr86_W }, |
5462 | | { R600::Addr87_W }, |
5463 | | { R600::Addr88_W }, |
5464 | | { R600::Addr89_W }, |
5465 | | { R600::Addr90_W }, |
5466 | | { R600::Addr91_W }, |
5467 | | { R600::Addr92_W }, |
5468 | | { R600::Addr93_W }, |
5469 | | { R600::Addr94_W }, |
5470 | | { R600::Addr95_W }, |
5471 | | { R600::Addr96_W }, |
5472 | | { R600::Addr97_W }, |
5473 | | { R600::Addr98_W }, |
5474 | | { R600::Addr99_W }, |
5475 | | { R600::Addr100_W }, |
5476 | | { R600::Addr101_W }, |
5477 | | { R600::Addr102_W }, |
5478 | | { R600::Addr103_W }, |
5479 | | { R600::Addr104_W }, |
5480 | | { R600::Addr105_W }, |
5481 | | { R600::Addr106_W }, |
5482 | | { R600::Addr107_W }, |
5483 | | { R600::Addr108_W }, |
5484 | | { R600::Addr109_W }, |
5485 | | { R600::Addr110_W }, |
5486 | | { R600::Addr111_W }, |
5487 | | { R600::Addr112_W }, |
5488 | | { R600::Addr113_W }, |
5489 | | { R600::Addr114_W }, |
5490 | | { R600::Addr115_W }, |
5491 | | { R600::Addr116_W }, |
5492 | | { R600::Addr117_W }, |
5493 | | { R600::Addr118_W }, |
5494 | | { R600::Addr119_W }, |
5495 | | { R600::Addr120_W }, |
5496 | | { R600::Addr121_W }, |
5497 | | { R600::Addr122_W }, |
5498 | | { R600::Addr123_W }, |
5499 | | { R600::Addr124_W }, |
5500 | | { R600::Addr125_W }, |
5501 | | { R600::Addr126_W }, |
5502 | | { R600::Addr127_W }, |
5503 | | { R600::Addr0_X }, |
5504 | | { R600::Addr1_X }, |
5505 | | { R600::Addr2_X }, |
5506 | | { R600::Addr3_X }, |
5507 | | { R600::Addr4_X }, |
5508 | | { R600::Addr5_X }, |
5509 | | { R600::Addr6_X }, |
5510 | | { R600::Addr7_X }, |
5511 | | { R600::Addr8_X }, |
5512 | | { R600::Addr9_X }, |
5513 | | { R600::Addr10_X }, |
5514 | | { R600::Addr11_X }, |
5515 | | { R600::Addr12_X }, |
5516 | | { R600::Addr13_X }, |
5517 | | { R600::Addr14_X }, |
5518 | | { R600::Addr15_X }, |
5519 | | { R600::Addr16_X }, |
5520 | | { R600::Addr17_X }, |
5521 | | { R600::Addr18_X }, |
5522 | | { R600::Addr19_X }, |
5523 | | { R600::Addr20_X }, |
5524 | | { R600::Addr21_X }, |
5525 | | { R600::Addr22_X }, |
5526 | | { R600::Addr23_X }, |
5527 | | { R600::Addr24_X }, |
5528 | | { R600::Addr25_X }, |
5529 | | { R600::Addr26_X }, |
5530 | | { R600::Addr27_X }, |
5531 | | { R600::Addr28_X }, |
5532 | | { R600::Addr29_X }, |
5533 | | { R600::Addr30_X }, |
5534 | | { R600::Addr31_X }, |
5535 | | { R600::Addr32_X }, |
5536 | | { R600::Addr33_X }, |
5537 | | { R600::Addr34_X }, |
5538 | | { R600::Addr35_X }, |
5539 | | { R600::Addr36_X }, |
5540 | | { R600::Addr37_X }, |
5541 | | { R600::Addr38_X }, |
5542 | | { R600::Addr39_X }, |
5543 | | { R600::Addr40_X }, |
5544 | | { R600::Addr41_X }, |
5545 | | { R600::Addr42_X }, |
5546 | | { R600::Addr43_X }, |
5547 | | { R600::Addr44_X }, |
5548 | | { R600::Addr45_X }, |
5549 | | { R600::Addr46_X }, |
5550 | | { R600::Addr47_X }, |
5551 | | { R600::Addr48_X }, |
5552 | | { R600::Addr49_X }, |
5553 | | { R600::Addr50_X }, |
5554 | | { R600::Addr51_X }, |
5555 | | { R600::Addr52_X }, |
5556 | | { R600::Addr53_X }, |
5557 | | { R600::Addr54_X }, |
5558 | | { R600::Addr55_X }, |
5559 | | { R600::Addr56_X }, |
5560 | | { R600::Addr57_X }, |
5561 | | { R600::Addr58_X }, |
5562 | | { R600::Addr59_X }, |
5563 | | { R600::Addr60_X }, |
5564 | | { R600::Addr61_X }, |
5565 | | { R600::Addr62_X }, |
5566 | | { R600::Addr63_X }, |
5567 | | { R600::Addr64_X }, |
5568 | | { R600::Addr65_X }, |
5569 | | { R600::Addr66_X }, |
5570 | | { R600::Addr67_X }, |
5571 | | { R600::Addr68_X }, |
5572 | | { R600::Addr69_X }, |
5573 | | { R600::Addr70_X }, |
5574 | | { R600::Addr71_X }, |
5575 | | { R600::Addr72_X }, |
5576 | | { R600::Addr73_X }, |
5577 | | { R600::Addr74_X }, |
5578 | | { R600::Addr75_X }, |
5579 | | { R600::Addr76_X }, |
5580 | | { R600::Addr77_X }, |
5581 | | { R600::Addr78_X }, |
5582 | | { R600::Addr79_X }, |
5583 | | { R600::Addr80_X }, |
5584 | | { R600::Addr81_X }, |
5585 | | { R600::Addr82_X }, |
5586 | | { R600::Addr83_X }, |
5587 | | { R600::Addr84_X }, |
5588 | | { R600::Addr85_X }, |
5589 | | { R600::Addr86_X }, |
5590 | | { R600::Addr87_X }, |
5591 | | { R600::Addr88_X }, |
5592 | | { R600::Addr89_X }, |
5593 | | { R600::Addr90_X }, |
5594 | | { R600::Addr91_X }, |
5595 | | { R600::Addr92_X }, |
5596 | | { R600::Addr93_X }, |
5597 | | { R600::Addr94_X }, |
5598 | | { R600::Addr95_X }, |
5599 | | { R600::Addr96_X }, |
5600 | | { R600::Addr97_X }, |
5601 | | { R600::Addr98_X }, |
5602 | | { R600::Addr99_X }, |
5603 | | { R600::Addr100_X }, |
5604 | | { R600::Addr101_X }, |
5605 | | { R600::Addr102_X }, |
5606 | | { R600::Addr103_X }, |
5607 | | { R600::Addr104_X }, |
5608 | | { R600::Addr105_X }, |
5609 | | { R600::Addr106_X }, |
5610 | | { R600::Addr107_X }, |
5611 | | { R600::Addr108_X }, |
5612 | | { R600::Addr109_X }, |
5613 | | { R600::Addr110_X }, |
5614 | | { R600::Addr111_X }, |
5615 | | { R600::Addr112_X }, |
5616 | | { R600::Addr113_X }, |
5617 | | { R600::Addr114_X }, |
5618 | | { R600::Addr115_X }, |
5619 | | { R600::Addr116_X }, |
5620 | | { R600::Addr117_X }, |
5621 | | { R600::Addr118_X }, |
5622 | | { R600::Addr119_X }, |
5623 | | { R600::Addr120_X }, |
5624 | | { R600::Addr121_X }, |
5625 | | { R600::Addr122_X }, |
5626 | | { R600::Addr123_X }, |
5627 | | { R600::Addr124_X }, |
5628 | | { R600::Addr125_X }, |
5629 | | { R600::Addr126_X }, |
5630 | | { R600::Addr127_X }, |
5631 | | { R600::Addr0_Y }, |
5632 | | { R600::Addr1_Y }, |
5633 | | { R600::Addr2_Y }, |
5634 | | { R600::Addr3_Y }, |
5635 | | { R600::Addr4_Y }, |
5636 | | { R600::Addr5_Y }, |
5637 | | { R600::Addr6_Y }, |
5638 | | { R600::Addr7_Y }, |
5639 | | { R600::Addr8_Y }, |
5640 | | { R600::Addr9_Y }, |
5641 | | { R600::Addr10_Y }, |
5642 | | { R600::Addr11_Y }, |
5643 | | { R600::Addr12_Y }, |
5644 | | { R600::Addr13_Y }, |
5645 | | { R600::Addr14_Y }, |
5646 | | { R600::Addr15_Y }, |
5647 | | { R600::Addr16_Y }, |
5648 | | { R600::Addr17_Y }, |
5649 | | { R600::Addr18_Y }, |
5650 | | { R600::Addr19_Y }, |
5651 | | { R600::Addr20_Y }, |
5652 | | { R600::Addr21_Y }, |
5653 | | { R600::Addr22_Y }, |
5654 | | { R600::Addr23_Y }, |
5655 | | { R600::Addr24_Y }, |
5656 | | { R600::Addr25_Y }, |
5657 | | { R600::Addr26_Y }, |
5658 | | { R600::Addr27_Y }, |
5659 | | { R600::Addr28_Y }, |
5660 | | { R600::Addr29_Y }, |
5661 | | { R600::Addr30_Y }, |
5662 | | { R600::Addr31_Y }, |
5663 | | { R600::Addr32_Y }, |
5664 | | { R600::Addr33_Y }, |
5665 | | { R600::Addr34_Y }, |
5666 | | { R600::Addr35_Y }, |
5667 | | { R600::Addr36_Y }, |
5668 | | { R600::Addr37_Y }, |
5669 | | { R600::Addr38_Y }, |
5670 | | { R600::Addr39_Y }, |
5671 | | { R600::Addr40_Y }, |
5672 | | { R600::Addr41_Y }, |
5673 | | { R600::Addr42_Y }, |
5674 | | { R600::Addr43_Y }, |
5675 | | { R600::Addr44_Y }, |
5676 | | { R600::Addr45_Y }, |
5677 | | { R600::Addr46_Y }, |
5678 | | { R600::Addr47_Y }, |
5679 | | { R600::Addr48_Y }, |
5680 | | { R600::Addr49_Y }, |
5681 | | { R600::Addr50_Y }, |
5682 | | { R600::Addr51_Y }, |
5683 | | { R600::Addr52_Y }, |
5684 | | { R600::Addr53_Y }, |
5685 | | { R600::Addr54_Y }, |
5686 | | { R600::Addr55_Y }, |
5687 | | { R600::Addr56_Y }, |
5688 | | { R600::Addr57_Y }, |
5689 | | { R600::Addr58_Y }, |
5690 | | { R600::Addr59_Y }, |
5691 | | { R600::Addr60_Y }, |
5692 | | { R600::Addr61_Y }, |
5693 | | { R600::Addr62_Y }, |
5694 | | { R600::Addr63_Y }, |
5695 | | { R600::Addr64_Y }, |
5696 | | { R600::Addr65_Y }, |
5697 | | { R600::Addr66_Y }, |
5698 | | { R600::Addr67_Y }, |
5699 | | { R600::Addr68_Y }, |
5700 | | { R600::Addr69_Y }, |
5701 | | { R600::Addr70_Y }, |
5702 | | { R600::Addr71_Y }, |
5703 | | { R600::Addr72_Y }, |
5704 | | { R600::Addr73_Y }, |
5705 | | { R600::Addr74_Y }, |
5706 | | { R600::Addr75_Y }, |
5707 | | { R600::Addr76_Y }, |
5708 | | { R600::Addr77_Y }, |
5709 | | { R600::Addr78_Y }, |
5710 | | { R600::Addr79_Y }, |
5711 | | { R600::Addr80_Y }, |
5712 | | { R600::Addr81_Y }, |
5713 | | { R600::Addr82_Y }, |
5714 | | { R600::Addr83_Y }, |
5715 | | { R600::Addr84_Y }, |
5716 | | { R600::Addr85_Y }, |
5717 | | { R600::Addr86_Y }, |
5718 | | { R600::Addr87_Y }, |
5719 | | { R600::Addr88_Y }, |
5720 | | { R600::Addr89_Y }, |
5721 | | { R600::Addr90_Y }, |
5722 | | { R600::Addr91_Y }, |
5723 | | { R600::Addr92_Y }, |
5724 | | { R600::Addr93_Y }, |
5725 | | { R600::Addr94_Y }, |
5726 | | { R600::Addr95_Y }, |
5727 | | { R600::Addr96_Y }, |
5728 | | { R600::Addr97_Y }, |
5729 | | { R600::Addr98_Y }, |
5730 | | { R600::Addr99_Y }, |
5731 | | { R600::Addr100_Y }, |
5732 | | { R600::Addr101_Y }, |
5733 | | { R600::Addr102_Y }, |
5734 | | { R600::Addr103_Y }, |
5735 | | { R600::Addr104_Y }, |
5736 | | { R600::Addr105_Y }, |
5737 | | { R600::Addr106_Y }, |
5738 | | { R600::Addr107_Y }, |
5739 | | { R600::Addr108_Y }, |
5740 | | { R600::Addr109_Y }, |
5741 | | { R600::Addr110_Y }, |
5742 | | { R600::Addr111_Y }, |
5743 | | { R600::Addr112_Y }, |
5744 | | { R600::Addr113_Y }, |
5745 | | { R600::Addr114_Y }, |
5746 | | { R600::Addr115_Y }, |
5747 | | { R600::Addr116_Y }, |
5748 | | { R600::Addr117_Y }, |
5749 | | { R600::Addr118_Y }, |
5750 | | { R600::Addr119_Y }, |
5751 | | { R600::Addr120_Y }, |
5752 | | { R600::Addr121_Y }, |
5753 | | { R600::Addr122_Y }, |
5754 | | { R600::Addr123_Y }, |
5755 | | { R600::Addr124_Y }, |
5756 | | { R600::Addr125_Y }, |
5757 | | { R600::Addr126_Y }, |
5758 | | { R600::Addr127_Y }, |
5759 | | { R600::Addr0_Z }, |
5760 | | { R600::Addr1_Z }, |
5761 | | { R600::Addr2_Z }, |
5762 | | { R600::Addr3_Z }, |
5763 | | { R600::Addr4_Z }, |
5764 | | { R600::Addr5_Z }, |
5765 | | { R600::Addr6_Z }, |
5766 | | { R600::Addr7_Z }, |
5767 | | { R600::Addr8_Z }, |
5768 | | { R600::Addr9_Z }, |
5769 | | { R600::Addr10_Z }, |
5770 | | { R600::Addr11_Z }, |
5771 | | { R600::Addr12_Z }, |
5772 | | { R600::Addr13_Z }, |
5773 | | { R600::Addr14_Z }, |
5774 | | { R600::Addr15_Z }, |
5775 | | { R600::Addr16_Z }, |
5776 | | { R600::Addr17_Z }, |
5777 | | { R600::Addr18_Z }, |
5778 | | { R600::Addr19_Z }, |
5779 | | { R600::Addr20_Z }, |
5780 | | { R600::Addr21_Z }, |
5781 | | { R600::Addr22_Z }, |
5782 | | { R600::Addr23_Z }, |
5783 | | { R600::Addr24_Z }, |
5784 | | { R600::Addr25_Z }, |
5785 | | { R600::Addr26_Z }, |
5786 | | { R600::Addr27_Z }, |
5787 | | { R600::Addr28_Z }, |
5788 | | { R600::Addr29_Z }, |
5789 | | { R600::Addr30_Z }, |
5790 | | { R600::Addr31_Z }, |
5791 | | { R600::Addr32_Z }, |
5792 | | { R600::Addr33_Z }, |
5793 | | { R600::Addr34_Z }, |
5794 | | { R600::Addr35_Z }, |
5795 | | { R600::Addr36_Z }, |
5796 | | { R600::Addr37_Z }, |
5797 | | { R600::Addr38_Z }, |
5798 | | { R600::Addr39_Z }, |
5799 | | { R600::Addr40_Z }, |
5800 | | { R600::Addr41_Z }, |
5801 | | { R600::Addr42_Z }, |
5802 | | { R600::Addr43_Z }, |
5803 | | { R600::Addr44_Z }, |
5804 | | { R600::Addr45_Z }, |
5805 | | { R600::Addr46_Z }, |
5806 | | { R600::Addr47_Z }, |
5807 | | { R600::Addr48_Z }, |
5808 | | { R600::Addr49_Z }, |
5809 | | { R600::Addr50_Z }, |
5810 | | { R600::Addr51_Z }, |
5811 | | { R600::Addr52_Z }, |
5812 | | { R600::Addr53_Z }, |
5813 | | { R600::Addr54_Z }, |
5814 | | { R600::Addr55_Z }, |
5815 | | { R600::Addr56_Z }, |
5816 | | { R600::Addr57_Z }, |
5817 | | { R600::Addr58_Z }, |
5818 | | { R600::Addr59_Z }, |
5819 | | { R600::Addr60_Z }, |
5820 | | { R600::Addr61_Z }, |
5821 | | { R600::Addr62_Z }, |
5822 | | { R600::Addr63_Z }, |
5823 | | { R600::Addr64_Z }, |
5824 | | { R600::Addr65_Z }, |
5825 | | { R600::Addr66_Z }, |
5826 | | { R600::Addr67_Z }, |
5827 | | { R600::Addr68_Z }, |
5828 | | { R600::Addr69_Z }, |
5829 | | { R600::Addr70_Z }, |
5830 | | { R600::Addr71_Z }, |
5831 | | { R600::Addr72_Z }, |
5832 | | { R600::Addr73_Z }, |
5833 | | { R600::Addr74_Z }, |
5834 | | { R600::Addr75_Z }, |
5835 | | { R600::Addr76_Z }, |
5836 | | { R600::Addr77_Z }, |
5837 | | { R600::Addr78_Z }, |
5838 | | { R600::Addr79_Z }, |
5839 | | { R600::Addr80_Z }, |
5840 | | { R600::Addr81_Z }, |
5841 | | { R600::Addr82_Z }, |
5842 | | { R600::Addr83_Z }, |
5843 | | { R600::Addr84_Z }, |
5844 | | { R600::Addr85_Z }, |
5845 | | { R600::Addr86_Z }, |
5846 | | { R600::Addr87_Z }, |
5847 | | { R600::Addr88_Z }, |
5848 | | { R600::Addr89_Z }, |
5849 | | { R600::Addr90_Z }, |
5850 | | { R600::Addr91_Z }, |
5851 | | { R600::Addr92_Z }, |
5852 | | { R600::Addr93_Z }, |
5853 | | { R600::Addr94_Z }, |
5854 | | { R600::Addr95_Z }, |
5855 | | { R600::Addr96_Z }, |
5856 | | { R600::Addr97_Z }, |
5857 | | { R600::Addr98_Z }, |
5858 | | { R600::Addr99_Z }, |
5859 | | { R600::Addr100_Z }, |
5860 | | { R600::Addr101_Z }, |
5861 | | { R600::Addr102_Z }, |
5862 | | { R600::Addr103_Z }, |
5863 | | { R600::Addr104_Z }, |
5864 | | { R600::Addr105_Z }, |
5865 | | { R600::Addr106_Z }, |
5866 | | { R600::Addr107_Z }, |
5867 | | { R600::Addr108_Z }, |
5868 | | { R600::Addr109_Z }, |
5869 | | { R600::Addr110_Z }, |
5870 | | { R600::Addr111_Z }, |
5871 | | { R600::Addr112_Z }, |
5872 | | { R600::Addr113_Z }, |
5873 | | { R600::Addr114_Z }, |
5874 | | { R600::Addr115_Z }, |
5875 | | { R600::Addr116_Z }, |
5876 | | { R600::Addr117_Z }, |
5877 | | { R600::Addr118_Z }, |
5878 | | { R600::Addr119_Z }, |
5879 | | { R600::Addr120_Z }, |
5880 | | { R600::Addr121_Z }, |
5881 | | { R600::Addr122_Z }, |
5882 | | { R600::Addr123_Z }, |
5883 | | { R600::Addr124_Z }, |
5884 | | { R600::Addr125_Z }, |
5885 | | { R600::Addr126_Z }, |
5886 | | { R600::Addr127_Z }, |
5887 | | { R600::T0_W }, |
5888 | | { R600::T1_W }, |
5889 | | { R600::T2_W }, |
5890 | | { R600::T3_W }, |
5891 | | { R600::T4_W }, |
5892 | | { R600::T5_W }, |
5893 | | { R600::T6_W }, |
5894 | | { R600::T7_W }, |
5895 | | { R600::T8_W }, |
5896 | | { R600::T9_W }, |
5897 | | { R600::T10_W }, |
5898 | | { R600::T11_W }, |
5899 | | { R600::T12_W }, |
5900 | | { R600::T13_W }, |
5901 | | { R600::T14_W }, |
5902 | | { R600::T15_W }, |
5903 | | { R600::T16_W }, |
5904 | | { R600::T17_W }, |
5905 | | { R600::T18_W }, |
5906 | | { R600::T19_W }, |
5907 | | { R600::T20_W }, |
5908 | | { R600::T21_W }, |
5909 | | { R600::T22_W }, |
5910 | | { R600::T23_W }, |
5911 | | { R600::T24_W }, |
5912 | | { R600::T25_W }, |
5913 | | { R600::T26_W }, |
5914 | | { R600::T27_W }, |
5915 | | { R600::T28_W }, |
5916 | | { R600::T29_W }, |
5917 | | { R600::T30_W }, |
5918 | | { R600::T31_W }, |
5919 | | { R600::T32_W }, |
5920 | | { R600::T33_W }, |
5921 | | { R600::T34_W }, |
5922 | | { R600::T35_W }, |
5923 | | { R600::T36_W }, |
5924 | | { R600::T37_W }, |
5925 | | { R600::T38_W }, |
5926 | | { R600::T39_W }, |
5927 | | { R600::T40_W }, |
5928 | | { R600::T41_W }, |
5929 | | { R600::T42_W }, |
5930 | | { R600::T43_W }, |
5931 | | { R600::T44_W }, |
5932 | | { R600::T45_W }, |
5933 | | { R600::T46_W }, |
5934 | | { R600::T47_W }, |
5935 | | { R600::T48_W }, |
5936 | | { R600::T49_W }, |
5937 | | { R600::T50_W }, |
5938 | | { R600::T51_W }, |
5939 | | { R600::T52_W }, |
5940 | | { R600::T53_W }, |
5941 | | { R600::T54_W }, |
5942 | | { R600::T55_W }, |
5943 | | { R600::T56_W }, |
5944 | | { R600::T57_W }, |
5945 | | { R600::T58_W }, |
5946 | | { R600::T59_W }, |
5947 | | { R600::T60_W }, |
5948 | | { R600::T61_W }, |
5949 | | { R600::T62_W }, |
5950 | | { R600::T63_W }, |
5951 | | { R600::T64_W }, |
5952 | | { R600::T65_W }, |
5953 | | { R600::T66_W }, |
5954 | | { R600::T67_W }, |
5955 | | { R600::T68_W }, |
5956 | | { R600::T69_W }, |
5957 | | { R600::T70_W }, |
5958 | | { R600::T71_W }, |
5959 | | { R600::T72_W }, |
5960 | | { R600::T73_W }, |
5961 | | { R600::T74_W }, |
5962 | | { R600::T75_W }, |
5963 | | { R600::T76_W }, |
5964 | | { R600::T77_W }, |
5965 | | { R600::T78_W }, |
5966 | | { R600::T79_W }, |
5967 | | { R600::T80_W }, |
5968 | | { R600::T81_W }, |
5969 | | { R600::T82_W }, |
5970 | | { R600::T83_W }, |
5971 | | { R600::T84_W }, |
5972 | | { R600::T85_W }, |
5973 | | { R600::T86_W }, |
5974 | | { R600::T87_W }, |
5975 | | { R600::T88_W }, |
5976 | | { R600::T89_W }, |
5977 | | { R600::T90_W }, |
5978 | | { R600::T91_W }, |
5979 | | { R600::T92_W }, |
5980 | | { R600::T93_W }, |
5981 | | { R600::T94_W }, |
5982 | | { R600::T95_W }, |
5983 | | { R600::T96_W }, |
5984 | | { R600::T97_W }, |
5985 | | { R600::T98_W }, |
5986 | | { R600::T99_W }, |
5987 | | { R600::T100_W }, |
5988 | | { R600::T101_W }, |
5989 | | { R600::T102_W }, |
5990 | | { R600::T103_W }, |
5991 | | { R600::T104_W }, |
5992 | | { R600::T105_W }, |
5993 | | { R600::T106_W }, |
5994 | | { R600::T107_W }, |
5995 | | { R600::T108_W }, |
5996 | | { R600::T109_W }, |
5997 | | { R600::T110_W }, |
5998 | | { R600::T111_W }, |
5999 | | { R600::T112_W }, |
6000 | | { R600::T113_W }, |
6001 | | { R600::T114_W }, |
6002 | | { R600::T115_W }, |
6003 | | { R600::T116_W }, |
6004 | | { R600::T117_W }, |
6005 | | { R600::T118_W }, |
6006 | | { R600::T119_W }, |
6007 | | { R600::T120_W }, |
6008 | | { R600::T121_W }, |
6009 | | { R600::T122_W }, |
6010 | | { R600::T123_W }, |
6011 | | { R600::T124_W }, |
6012 | | { R600::T125_W }, |
6013 | | { R600::T126_W }, |
6014 | | { R600::T127_W }, |
6015 | | { R600::T0_X }, |
6016 | | { R600::T1_X }, |
6017 | | { R600::T2_X }, |
6018 | | { R600::T3_X }, |
6019 | | { R600::T4_X }, |
6020 | | { R600::T5_X }, |
6021 | | { R600::T6_X }, |
6022 | | { R600::T7_X }, |
6023 | | { R600::T8_X }, |
6024 | | { R600::T9_X }, |
6025 | | { R600::T10_X }, |
6026 | | { R600::T11_X }, |
6027 | | { R600::T12_X }, |
6028 | | { R600::T13_X }, |
6029 | | { R600::T14_X }, |
6030 | | { R600::T15_X }, |
6031 | | { R600::T16_X }, |
6032 | | { R600::T17_X }, |
6033 | | { R600::T18_X }, |
6034 | | { R600::T19_X }, |
6035 | | { R600::T20_X }, |
6036 | | { R600::T21_X }, |
6037 | | { R600::T22_X }, |
6038 | | { R600::T23_X }, |
6039 | | { R600::T24_X }, |
6040 | | { R600::T25_X }, |
6041 | | { R600::T26_X }, |
6042 | | { R600::T27_X }, |
6043 | | { R600::T28_X }, |
6044 | | { R600::T29_X }, |
6045 | | { R600::T30_X }, |
6046 | | { R600::T31_X }, |
6047 | | { R600::T32_X }, |
6048 | | { R600::T33_X }, |
6049 | | { R600::T34_X }, |
6050 | | { R600::T35_X }, |
6051 | | { R600::T36_X }, |
6052 | | { R600::T37_X }, |
6053 | | { R600::T38_X }, |
6054 | | { R600::T39_X }, |
6055 | | { R600::T40_X }, |
6056 | | { R600::T41_X }, |
6057 | | { R600::T42_X }, |
6058 | | { R600::T43_X }, |
6059 | | { R600::T44_X }, |
6060 | | { R600::T45_X }, |
6061 | | { R600::T46_X }, |
6062 | | { R600::T47_X }, |
6063 | | { R600::T48_X }, |
6064 | | { R600::T49_X }, |
6065 | | { R600::T50_X }, |
6066 | | { R600::T51_X }, |
6067 | | { R600::T52_X }, |
6068 | | { R600::T53_X }, |
6069 | | { R600::T54_X }, |
6070 | | { R600::T55_X }, |
6071 | | { R600::T56_X }, |
6072 | | { R600::T57_X }, |
6073 | | { R600::T58_X }, |
6074 | | { R600::T59_X }, |
6075 | | { R600::T60_X }, |
6076 | | { R600::T61_X }, |
6077 | | { R600::T62_X }, |
6078 | | { R600::T63_X }, |
6079 | | { R600::T64_X }, |
6080 | | { R600::T65_X }, |
6081 | | { R600::T66_X }, |
6082 | | { R600::T67_X }, |
6083 | | { R600::T68_X }, |
6084 | | { R600::T69_X }, |
6085 | | { R600::T70_X }, |
6086 | | { R600::T71_X }, |
6087 | | { R600::T72_X }, |
6088 | | { R600::T73_X }, |
6089 | | { R600::T74_X }, |
6090 | | { R600::T75_X }, |
6091 | | { R600::T76_X }, |
6092 | | { R600::T77_X }, |
6093 | | { R600::T78_X }, |
6094 | | { R600::T79_X }, |
6095 | | { R600::T80_X }, |
6096 | | { R600::T81_X }, |
6097 | | { R600::T82_X }, |
6098 | | { R600::T83_X }, |
6099 | | { R600::T84_X }, |
6100 | | { R600::T85_X }, |
6101 | | { R600::T86_X }, |
6102 | | { R600::T87_X }, |
6103 | | { R600::T88_X }, |
6104 | | { R600::T89_X }, |
6105 | | { R600::T90_X }, |
6106 | | { R600::T91_X }, |
6107 | | { R600::T92_X }, |
6108 | | { R600::T93_X }, |
6109 | | { R600::T94_X }, |
6110 | | { R600::T95_X }, |
6111 | | { R600::T96_X }, |
6112 | | { R600::T97_X }, |
6113 | | { R600::T98_X }, |
6114 | | { R600::T99_X }, |
6115 | | { R600::T100_X }, |
6116 | | { R600::T101_X }, |
6117 | | { R600::T102_X }, |
6118 | | { R600::T103_X }, |
6119 | | { R600::T104_X }, |
6120 | | { R600::T105_X }, |
6121 | | { R600::T106_X }, |
6122 | | { R600::T107_X }, |
6123 | | { R600::T108_X }, |
6124 | | { R600::T109_X }, |
6125 | | { R600::T110_X }, |
6126 | | { R600::T111_X }, |
6127 | | { R600::T112_X }, |
6128 | | { R600::T113_X }, |
6129 | | { R600::T114_X }, |
6130 | | { R600::T115_X }, |
6131 | | { R600::T116_X }, |
6132 | | { R600::T117_X }, |
6133 | | { R600::T118_X }, |
6134 | | { R600::T119_X }, |
6135 | | { R600::T120_X }, |
6136 | | { R600::T121_X }, |
6137 | | { R600::T122_X }, |
6138 | | { R600::T123_X }, |
6139 | | { R600::T124_X }, |
6140 | | { R600::T125_X }, |
6141 | | { R600::T126_X }, |
6142 | | { R600::T127_X }, |
6143 | | { R600::T0_Y }, |
6144 | | { R600::T1_Y }, |
6145 | | { R600::T2_Y }, |
6146 | | { R600::T3_Y }, |
6147 | | { R600::T4_Y }, |
6148 | | { R600::T5_Y }, |
6149 | | { R600::T6_Y }, |
6150 | | { R600::T7_Y }, |
6151 | | { R600::T8_Y }, |
6152 | | { R600::T9_Y }, |
6153 | | { R600::T10_Y }, |
6154 | | { R600::T11_Y }, |
6155 | | { R600::T12_Y }, |
6156 | | { R600::T13_Y }, |
6157 | | { R600::T14_Y }, |
6158 | | { R600::T15_Y }, |
6159 | | { R600::T16_Y }, |
6160 | | { R600::T17_Y }, |
6161 | | { R600::T18_Y }, |
6162 | | { R600::T19_Y }, |
6163 | | { R600::T20_Y }, |
6164 | | { R600::T21_Y }, |
6165 | | { R600::T22_Y }, |
6166 | | { R600::T23_Y }, |
6167 | | { R600::T24_Y }, |
6168 | | { R600::T25_Y }, |
6169 | | { R600::T26_Y }, |
6170 | | { R600::T27_Y }, |
6171 | | { R600::T28_Y }, |
6172 | | { R600::T29_Y }, |
6173 | | { R600::T30_Y }, |
6174 | | { R600::T31_Y }, |
6175 | | { R600::T32_Y }, |
6176 | | { R600::T33_Y }, |
6177 | | { R600::T34_Y }, |
6178 | | { R600::T35_Y }, |
6179 | | { R600::T36_Y }, |
6180 | | { R600::T37_Y }, |
6181 | | { R600::T38_Y }, |
6182 | | { R600::T39_Y }, |
6183 | | { R600::T40_Y }, |
6184 | | { R600::T41_Y }, |
6185 | | { R600::T42_Y }, |
6186 | | { R600::T43_Y }, |
6187 | | { R600::T44_Y }, |
6188 | | { R600::T45_Y }, |
6189 | | { R600::T46_Y }, |
6190 | | { R600::T47_Y }, |
6191 | | { R600::T48_Y }, |
6192 | | { R600::T49_Y }, |
6193 | | { R600::T50_Y }, |
6194 | | { R600::T51_Y }, |
6195 | | { R600::T52_Y }, |
6196 | | { R600::T53_Y }, |
6197 | | { R600::T54_Y }, |
6198 | | { R600::T55_Y }, |
6199 | | { R600::T56_Y }, |
6200 | | { R600::T57_Y }, |
6201 | | { R600::T58_Y }, |
6202 | | { R600::T59_Y }, |
6203 | | { R600::T60_Y }, |
6204 | | { R600::T61_Y }, |
6205 | | { R600::T62_Y }, |
6206 | | { R600::T63_Y }, |
6207 | | { R600::T64_Y }, |
6208 | | { R600::T65_Y }, |
6209 | | { R600::T66_Y }, |
6210 | | { R600::T67_Y }, |
6211 | | { R600::T68_Y }, |
6212 | | { R600::T69_Y }, |
6213 | | { R600::T70_Y }, |
6214 | | { R600::T71_Y }, |
6215 | | { R600::T72_Y }, |
6216 | | { R600::T73_Y }, |
6217 | | { R600::T74_Y }, |
6218 | | { R600::T75_Y }, |
6219 | | { R600::T76_Y }, |
6220 | | { R600::T77_Y }, |
6221 | | { R600::T78_Y }, |
6222 | | { R600::T79_Y }, |
6223 | | { R600::T80_Y }, |
6224 | | { R600::T81_Y }, |
6225 | | { R600::T82_Y }, |
6226 | | { R600::T83_Y }, |
6227 | | { R600::T84_Y }, |
6228 | | { R600::T85_Y }, |
6229 | | { R600::T86_Y }, |
6230 | | { R600::T87_Y }, |
6231 | | { R600::T88_Y }, |
6232 | | { R600::T89_Y }, |
6233 | | { R600::T90_Y }, |
6234 | | { R600::T91_Y }, |
6235 | | { R600::T92_Y }, |
6236 | | { R600::T93_Y }, |
6237 | | { R600::T94_Y }, |
6238 | | { R600::T95_Y }, |
6239 | | { R600::T96_Y }, |
6240 | | { R600::T97_Y }, |
6241 | | { R600::T98_Y }, |
6242 | | { R600::T99_Y }, |
6243 | | { R600::T100_Y }, |
6244 | | { R600::T101_Y }, |
6245 | | { R600::T102_Y }, |
6246 | | { R600::T103_Y }, |
6247 | | { R600::T104_Y }, |
6248 | | { R600::T105_Y }, |
6249 | | { R600::T106_Y }, |
6250 | | { R600::T107_Y }, |
6251 | | { R600::T108_Y }, |
6252 | | { R600::T109_Y }, |
6253 | | { R600::T110_Y }, |
6254 | | { R600::T111_Y }, |
6255 | | { R600::T112_Y }, |
6256 | | { R600::T113_Y }, |
6257 | | { R600::T114_Y }, |
6258 | | { R600::T115_Y }, |
6259 | | { R600::T116_Y }, |
6260 | | { R600::T117_Y }, |
6261 | | { R600::T118_Y }, |
6262 | | { R600::T119_Y }, |
6263 | | { R600::T120_Y }, |
6264 | | { R600::T121_Y }, |
6265 | | { R600::T122_Y }, |
6266 | | { R600::T123_Y }, |
6267 | | { R600::T124_Y }, |
6268 | | { R600::T125_Y }, |
6269 | | { R600::T126_Y }, |
6270 | | { R600::T127_Y }, |
6271 | | { R600::T0_Z }, |
6272 | | { R600::T1_Z }, |
6273 | | { R600::T2_Z }, |
6274 | | { R600::T3_Z }, |
6275 | | { R600::T4_Z }, |
6276 | | { R600::T5_Z }, |
6277 | | { R600::T6_Z }, |
6278 | | { R600::T7_Z }, |
6279 | | { R600::T8_Z }, |
6280 | | { R600::T9_Z }, |
6281 | | { R600::T10_Z }, |
6282 | | { R600::T11_Z }, |
6283 | | { R600::T12_Z }, |
6284 | | { R600::T13_Z }, |
6285 | | { R600::T14_Z }, |
6286 | | { R600::T15_Z }, |
6287 | | { R600::T16_Z }, |
6288 | | { R600::T17_Z }, |
6289 | | { R600::T18_Z }, |
6290 | | { R600::T19_Z }, |
6291 | | { R600::T20_Z }, |
6292 | | { R600::T21_Z }, |
6293 | | { R600::T22_Z }, |
6294 | | { R600::T23_Z }, |
6295 | | { R600::T24_Z }, |
6296 | | { R600::T25_Z }, |
6297 | | { R600::T26_Z }, |
6298 | | { R600::T27_Z }, |
6299 | | { R600::T28_Z }, |
6300 | | { R600::T29_Z }, |
6301 | | { R600::T30_Z }, |
6302 | | { R600::T31_Z }, |
6303 | | { R600::T32_Z }, |
6304 | | { R600::T33_Z }, |
6305 | | { R600::T34_Z }, |
6306 | | { R600::T35_Z }, |
6307 | | { R600::T36_Z }, |
6308 | | { R600::T37_Z }, |
6309 | | { R600::T38_Z }, |
6310 | | { R600::T39_Z }, |
6311 | | { R600::T40_Z }, |
6312 | | { R600::T41_Z }, |
6313 | | { R600::T42_Z }, |
6314 | | { R600::T43_Z }, |
6315 | | { R600::T44_Z }, |
6316 | | { R600::T45_Z }, |
6317 | | { R600::T46_Z }, |
6318 | | { R600::T47_Z }, |
6319 | | { R600::T48_Z }, |
6320 | | { R600::T49_Z }, |
6321 | | { R600::T50_Z }, |
6322 | | { R600::T51_Z }, |
6323 | | { R600::T52_Z }, |
6324 | | { R600::T53_Z }, |
6325 | | { R600::T54_Z }, |
6326 | | { R600::T55_Z }, |
6327 | | { R600::T56_Z }, |
6328 | | { R600::T57_Z }, |
6329 | | { R600::T58_Z }, |
6330 | | { R600::T59_Z }, |
6331 | | { R600::T60_Z }, |
6332 | | { R600::T61_Z }, |
6333 | | { R600::T62_Z }, |
6334 | | { R600::T63_Z }, |
6335 | | { R600::T64_Z }, |
6336 | | { R600::T65_Z }, |
6337 | | { R600::T66_Z }, |
6338 | | { R600::T67_Z }, |
6339 | | { R600::T68_Z }, |
6340 | | { R600::T69_Z }, |
6341 | | { R600::T70_Z }, |
6342 | | { R600::T71_Z }, |
6343 | | { R600::T72_Z }, |
6344 | | { R600::T73_Z }, |
6345 | | { R600::T74_Z }, |
6346 | | { R600::T75_Z }, |
6347 | | { R600::T76_Z }, |
6348 | | { R600::T77_Z }, |
6349 | | { R600::T78_Z }, |
6350 | | { R600::T79_Z }, |
6351 | | { R600::T80_Z }, |
6352 | | { R600::T81_Z }, |
6353 | | { R600::T82_Z }, |
6354 | | { R600::T83_Z }, |
6355 | | { R600::T84_Z }, |
6356 | | { R600::T85_Z }, |
6357 | | { R600::T86_Z }, |
6358 | | { R600::T87_Z }, |
6359 | | { R600::T88_Z }, |
6360 | | { R600::T89_Z }, |
6361 | | { R600::T90_Z }, |
6362 | | { R600::T91_Z }, |
6363 | | { R600::T92_Z }, |
6364 | | { R600::T93_Z }, |
6365 | | { R600::T94_Z }, |
6366 | | { R600::T95_Z }, |
6367 | | { R600::T96_Z }, |
6368 | | { R600::T97_Z }, |
6369 | | { R600::T98_Z }, |
6370 | | { R600::T99_Z }, |
6371 | | { R600::T100_Z }, |
6372 | | { R600::T101_Z }, |
6373 | | { R600::T102_Z }, |
6374 | | { R600::T103_Z }, |
6375 | | { R600::T104_Z }, |
6376 | | { R600::T105_Z }, |
6377 | | { R600::T106_Z }, |
6378 | | { R600::T107_Z }, |
6379 | | { R600::T108_Z }, |
6380 | | { R600::T109_Z }, |
6381 | | { R600::T110_Z }, |
6382 | | { R600::T111_Z }, |
6383 | | { R600::T112_Z }, |
6384 | | { R600::T113_Z }, |
6385 | | { R600::T114_Z }, |
6386 | | { R600::T115_Z }, |
6387 | | { R600::T116_Z }, |
6388 | | { R600::T117_Z }, |
6389 | | { R600::T118_Z }, |
6390 | | { R600::T119_Z }, |
6391 | | { R600::T120_Z }, |
6392 | | { R600::T121_Z }, |
6393 | | { R600::T122_Z }, |
6394 | | { R600::T123_Z }, |
6395 | | { R600::T124_Z }, |
6396 | | { R600::T125_Z }, |
6397 | | { R600::T126_Z }, |
6398 | | { R600::T127_Z }, |
6399 | | { R600::KC0_128_W }, |
6400 | | { R600::KC0_129_W }, |
6401 | | { R600::KC0_130_W }, |
6402 | | { R600::KC0_131_W }, |
6403 | | { R600::KC0_132_W }, |
6404 | | { R600::KC0_133_W }, |
6405 | | { R600::KC0_134_W }, |
6406 | | { R600::KC0_135_W }, |
6407 | | { R600::KC0_136_W }, |
6408 | | { R600::KC0_137_W }, |
6409 | | { R600::KC0_138_W }, |
6410 | | { R600::KC0_139_W }, |
6411 | | { R600::KC0_140_W }, |
6412 | | { R600::KC0_141_W }, |
6413 | | { R600::KC0_142_W }, |
6414 | | { R600::KC0_143_W }, |
6415 | | { R600::KC0_144_W }, |
6416 | | { R600::KC0_145_W }, |
6417 | | { R600::KC0_146_W }, |
6418 | | { R600::KC0_147_W }, |
6419 | | { R600::KC0_148_W }, |
6420 | | { R600::KC0_149_W }, |
6421 | | { R600::KC0_150_W }, |
6422 | | { R600::KC0_151_W }, |
6423 | | { R600::KC0_152_W }, |
6424 | | { R600::KC0_153_W }, |
6425 | | { R600::KC0_154_W }, |
6426 | | { R600::KC0_155_W }, |
6427 | | { R600::KC0_156_W }, |
6428 | | { R600::KC0_157_W }, |
6429 | | { R600::KC0_158_W }, |
6430 | | { R600::KC0_159_W }, |
6431 | | { R600::KC1_160_W }, |
6432 | | { R600::KC1_161_W }, |
6433 | | { R600::KC1_162_W }, |
6434 | | { R600::KC1_163_W }, |
6435 | | { R600::KC1_164_W }, |
6436 | | { R600::KC1_165_W }, |
6437 | | { R600::KC1_166_W }, |
6438 | | { R600::KC1_167_W }, |
6439 | | { R600::KC1_168_W }, |
6440 | | { R600::KC1_169_W }, |
6441 | | { R600::KC1_170_W }, |
6442 | | { R600::KC1_171_W }, |
6443 | | { R600::KC1_172_W }, |
6444 | | { R600::KC1_173_W }, |
6445 | | { R600::KC1_174_W }, |
6446 | | { R600::KC1_175_W }, |
6447 | | { R600::KC1_176_W }, |
6448 | | { R600::KC1_177_W }, |
6449 | | { R600::KC1_178_W }, |
6450 | | { R600::KC1_179_W }, |
6451 | | { R600::KC1_180_W }, |
6452 | | { R600::KC1_181_W }, |
6453 | | { R600::KC1_182_W }, |
6454 | | { R600::KC1_183_W }, |
6455 | | { R600::KC1_184_W }, |
6456 | | { R600::KC1_185_W }, |
6457 | | { R600::KC1_186_W }, |
6458 | | { R600::KC1_187_W }, |
6459 | | { R600::KC1_188_W }, |
6460 | | { R600::KC1_189_W }, |
6461 | | { R600::KC1_190_W }, |
6462 | | { R600::KC1_191_W }, |
6463 | | { R600::KC0_128_X }, |
6464 | | { R600::KC0_129_X }, |
6465 | | { R600::KC0_130_X }, |
6466 | | { R600::KC0_131_X }, |
6467 | | { R600::KC0_132_X }, |
6468 | | { R600::KC0_133_X }, |
6469 | | { R600::KC0_134_X }, |
6470 | | { R600::KC0_135_X }, |
6471 | | { R600::KC0_136_X }, |
6472 | | { R600::KC0_137_X }, |
6473 | | { R600::KC0_138_X }, |
6474 | | { R600::KC0_139_X }, |
6475 | | { R600::KC0_140_X }, |
6476 | | { R600::KC0_141_X }, |
6477 | | { R600::KC0_142_X }, |
6478 | | { R600::KC0_143_X }, |
6479 | | { R600::KC0_144_X }, |
6480 | | { R600::KC0_145_X }, |
6481 | | { R600::KC0_146_X }, |
6482 | | { R600::KC0_147_X }, |
6483 | | { R600::KC0_148_X }, |
6484 | | { R600::KC0_149_X }, |
6485 | | { R600::KC0_150_X }, |
6486 | | { R600::KC0_151_X }, |
6487 | | { R600::KC0_152_X }, |
6488 | | { R600::KC0_153_X }, |
6489 | | { R600::KC0_154_X }, |
6490 | | { R600::KC0_155_X }, |
6491 | | { R600::KC0_156_X }, |
6492 | | { R600::KC0_157_X }, |
6493 | | { R600::KC0_158_X }, |
6494 | | { R600::KC0_159_X }, |
6495 | | { R600::KC1_160_X }, |
6496 | | { R600::KC1_161_X }, |
6497 | | { R600::KC1_162_X }, |
6498 | | { R600::KC1_163_X }, |
6499 | | { R600::KC1_164_X }, |
6500 | | { R600::KC1_165_X }, |
6501 | | { R600::KC1_166_X }, |
6502 | | { R600::KC1_167_X }, |
6503 | | { R600::KC1_168_X }, |
6504 | | { R600::KC1_169_X }, |
6505 | | { R600::KC1_170_X }, |
6506 | | { R600::KC1_171_X }, |
6507 | | { R600::KC1_172_X }, |
6508 | | { R600::KC1_173_X }, |
6509 | | { R600::KC1_174_X }, |
6510 | | { R600::KC1_175_X }, |
6511 | | { R600::KC1_176_X }, |
6512 | | { R600::KC1_177_X }, |
6513 | | { R600::KC1_178_X }, |
6514 | | { R600::KC1_179_X }, |
6515 | | { R600::KC1_180_X }, |
6516 | | { R600::KC1_181_X }, |
6517 | | { R600::KC1_182_X }, |
6518 | | { R600::KC1_183_X }, |
6519 | | { R600::KC1_184_X }, |
6520 | | { R600::KC1_185_X }, |
6521 | | { R600::KC1_186_X }, |
6522 | | { R600::KC1_187_X }, |
6523 | | { R600::KC1_188_X }, |
6524 | | { R600::KC1_189_X }, |
6525 | | { R600::KC1_190_X }, |
6526 | | { R600::KC1_191_X }, |
6527 | | { R600::KC0_128_Y }, |
6528 | | { R600::KC0_128_Z }, |
6529 | | { R600::KC0_129_Y }, |
6530 | | { R600::KC0_129_Z }, |
6531 | | { R600::KC0_130_Y }, |
6532 | | { R600::KC0_130_Z }, |
6533 | | { R600::KC0_131_Y }, |
6534 | | { R600::KC0_131_Z }, |
6535 | | { R600::KC0_132_Y }, |
6536 | | { R600::KC0_132_Z }, |
6537 | | { R600::KC0_133_Y }, |
6538 | | { R600::KC0_133_Z }, |
6539 | | { R600::KC0_134_Y }, |
6540 | | { R600::KC0_134_Z }, |
6541 | | { R600::KC0_135_Y }, |
6542 | | { R600::KC0_135_Z }, |
6543 | | { R600::KC0_136_Y }, |
6544 | | { R600::KC0_136_Z }, |
6545 | | { R600::KC0_137_Y }, |
6546 | | { R600::KC0_137_Z }, |
6547 | | { R600::KC0_138_Y }, |
6548 | | { R600::KC0_138_Z }, |
6549 | | { R600::KC0_139_Y }, |
6550 | | { R600::KC0_139_Z }, |
6551 | | { R600::KC0_140_Y }, |
6552 | | { R600::KC0_140_Z }, |
6553 | | { R600::KC0_141_Y }, |
6554 | | { R600::KC0_141_Z }, |
6555 | | { R600::KC0_142_Y }, |
6556 | | { R600::KC0_142_Z }, |
6557 | | { R600::KC0_143_Y }, |
6558 | | { R600::KC0_143_Z }, |
6559 | | { R600::KC0_144_Y }, |
6560 | | { R600::KC0_144_Z }, |
6561 | | { R600::KC0_145_Y }, |
6562 | | { R600::KC0_145_Z }, |
6563 | | { R600::KC0_146_Y }, |
6564 | | { R600::KC0_146_Z }, |
6565 | | { R600::KC0_147_Y }, |
6566 | | { R600::KC0_147_Z }, |
6567 | | { R600::KC0_148_Y }, |
6568 | | { R600::KC0_148_Z }, |
6569 | | { R600::KC0_149_Y }, |
6570 | | { R600::KC0_149_Z }, |
6571 | | { R600::KC0_150_Y }, |
6572 | | { R600::KC0_150_Z }, |
6573 | | { R600::KC0_151_Y }, |
6574 | | { R600::KC0_151_Z }, |
6575 | | { R600::KC0_152_Y }, |
6576 | | { R600::KC0_152_Z }, |
6577 | | { R600::KC0_153_Y }, |
6578 | | { R600::KC0_153_Z }, |
6579 | | { R600::KC0_154_Y }, |
6580 | | { R600::KC0_154_Z }, |
6581 | | { R600::KC0_155_Y }, |
6582 | | { R600::KC0_155_Z }, |
6583 | | { R600::KC0_156_Y }, |
6584 | | { R600::KC0_156_Z }, |
6585 | | { R600::KC0_157_Y }, |
6586 | | { R600::KC0_157_Z }, |
6587 | | { R600::KC0_158_Y }, |
6588 | | { R600::KC0_158_Z }, |
6589 | | { R600::KC0_159_Y }, |
6590 | | { R600::KC0_159_Z }, |
6591 | | { R600::KC1_160_Y }, |
6592 | | { R600::KC1_160_Z }, |
6593 | | { R600::KC1_161_Y }, |
6594 | | { R600::KC1_161_Z }, |
6595 | | { R600::KC1_162_Y }, |
6596 | | { R600::KC1_162_Z }, |
6597 | | { R600::KC1_163_Y }, |
6598 | | { R600::KC1_163_Z }, |
6599 | | { R600::KC1_164_Y }, |
6600 | | { R600::KC1_164_Z }, |
6601 | | { R600::KC1_165_Y }, |
6602 | | { R600::KC1_165_Z }, |
6603 | | { R600::KC1_166_Y }, |
6604 | | { R600::KC1_166_Z }, |
6605 | | { R600::KC1_167_Y }, |
6606 | | { R600::KC1_167_Z }, |
6607 | | { R600::KC1_168_Y }, |
6608 | | { R600::KC1_168_Z }, |
6609 | | { R600::KC1_169_Y }, |
6610 | | { R600::KC1_169_Z }, |
6611 | | { R600::KC1_170_Y }, |
6612 | | { R600::KC1_170_Z }, |
6613 | | { R600::KC1_171_Y }, |
6614 | | { R600::KC1_171_Z }, |
6615 | | { R600::KC1_172_Y }, |
6616 | | { R600::KC1_172_Z }, |
6617 | | { R600::KC1_173_Y }, |
6618 | | { R600::KC1_173_Z }, |
6619 | | { R600::KC1_174_Y }, |
6620 | | { R600::KC1_174_Z }, |
6621 | | { R600::KC1_175_Y }, |
6622 | | { R600::KC1_175_Z }, |
6623 | | { R600::KC1_176_Y }, |
6624 | | { R600::KC1_176_Z }, |
6625 | | { R600::KC1_177_Y }, |
6626 | | { R600::KC1_177_Z }, |
6627 | | { R600::KC1_178_Y }, |
6628 | | { R600::KC1_178_Z }, |
6629 | | { R600::KC1_179_Y }, |
6630 | | { R600::KC1_179_Z }, |
6631 | | { R600::KC1_180_Y }, |
6632 | | { R600::KC1_180_Z }, |
6633 | | { R600::KC1_181_Y }, |
6634 | | { R600::KC1_181_Z }, |
6635 | | { R600::KC1_182_Y }, |
6636 | | { R600::KC1_182_Z }, |
6637 | | { R600::KC1_183_Y }, |
6638 | | { R600::KC1_183_Z }, |
6639 | | { R600::KC1_184_Y }, |
6640 | | { R600::KC1_184_Z }, |
6641 | | { R600::KC1_185_Y }, |
6642 | | { R600::KC1_185_Z }, |
6643 | | { R600::KC1_186_Y }, |
6644 | | { R600::KC1_186_Z }, |
6645 | | { R600::KC1_187_Y }, |
6646 | | { R600::KC1_187_Z }, |
6647 | | { R600::KC1_188_Y }, |
6648 | | { R600::KC1_188_Z }, |
6649 | | { R600::KC1_189_Y }, |
6650 | | { R600::KC1_189_Z }, |
6651 | | { R600::KC1_190_Y }, |
6652 | | { R600::KC1_190_Z }, |
6653 | | { R600::KC1_191_Y }, |
6654 | | { R600::KC1_191_Z }, |
6655 | | }; |
6656 | | |
6657 | | namespace { // Register classes... |
6658 | | // R600_Reg32 Register Class... |
6659 | | const MCPhysReg R600_Reg32[] = { |
6660 | | R600::T0_X, R600::T0_Y, R600::T0_Z, R600::T0_W, R600::T1_X, R600::T1_Y, R600::T1_Z, R600::T1_W, R600::T2_X, R600::T2_Y, R600::T2_Z, R600::T2_W, R600::T3_X, R600::T3_Y, R600::T3_Z, R600::T3_W, R600::T4_X, R600::T4_Y, R600::T4_Z, R600::T4_W, R600::T5_X, R600::T5_Y, R600::T5_Z, R600::T5_W, R600::T6_X, R600::T6_Y, R600::T6_Z, R600::T6_W, R600::T7_X, R600::T7_Y, R600::T7_Z, R600::T7_W, R600::T8_X, R600::T8_Y, R600::T8_Z, R600::T8_W, R600::T9_X, R600::T9_Y, R600::T9_Z, R600::T9_W, R600::T10_X, R600::T10_Y, R600::T10_Z, R600::T10_W, R600::T11_X, R600::T11_Y, R600::T11_Z, R600::T11_W, R600::T12_X, R600::T12_Y, R600::T12_Z, R600::T12_W, R600::T13_X, R600::T13_Y, R600::T13_Z, R600::T13_W, R600::T14_X, R600::T14_Y, R600::T14_Z, R600::T14_W, R600::T15_X, R600::T15_Y, R600::T15_Z, R600::T15_W, R600::T16_X, R600::T16_Y, R600::T16_Z, R600::T16_W, R600::T17_X, R600::T17_Y, R600::T17_Z, R600::T17_W, R600::T18_X, R600::T18_Y, R600::T18_Z, R600::T18_W, R600::T19_X, R600::T19_Y, R600::T19_Z, R600::T19_W, R600::T20_X, R600::T20_Y, R600::T20_Z, R600::T20_W, R600::T21_X, R600::T21_Y, R600::T21_Z, R600::T21_W, R600::T22_X, R600::T22_Y, R600::T22_Z, R600::T22_W, R600::T23_X, R600::T23_Y, R600::T23_Z, R600::T23_W, R600::T24_X, R600::T24_Y, R600::T24_Z, R600::T24_W, R600::T25_X, R600::T25_Y, R600::T25_Z, R600::T25_W, R600::T26_X, R600::T26_Y, R600::T26_Z, R600::T26_W, R600::T27_X, R600::T27_Y, R600::T27_Z, R600::T27_W, R600::T28_X, R600::T28_Y, R600::T28_Z, R600::T28_W, R600::T29_X, R600::T29_Y, R600::T29_Z, R600::T29_W, R600::T30_X, R600::T30_Y, R600::T30_Z, R600::T30_W, R600::T31_X, R600::T31_Y, R600::T31_Z, R600::T31_W, R600::T32_X, R600::T32_Y, R600::T32_Z, R600::T32_W, R600::T33_X, R600::T33_Y, R600::T33_Z, R600::T33_W, R600::T34_X, R600::T34_Y, R600::T34_Z, R600::T34_W, R600::T35_X, R600::T35_Y, R600::T35_Z, R600::T35_W, R600::T36_X, R600::T36_Y, R600::T36_Z, R600::T36_W, R600::T37_X, R600::T37_Y, R600::T37_Z, R600::T37_W, R600::T38_X, R600::T38_Y, R600::T38_Z, R600::T38_W, R600::T39_X, R600::T39_Y, R600::T39_Z, R600::T39_W, R600::T40_X, R600::T40_Y, R600::T40_Z, R600::T40_W, R600::T41_X, R600::T41_Y, R600::T41_Z, R600::T41_W, R600::T42_X, R600::T42_Y, R600::T42_Z, R600::T42_W, R600::T43_X, R600::T43_Y, R600::T43_Z, R600::T43_W, R600::T44_X, R600::T44_Y, R600::T44_Z, R600::T44_W, R600::T45_X, R600::T45_Y, R600::T45_Z, R600::T45_W, R600::T46_X, R600::T46_Y, R600::T46_Z, R600::T46_W, R600::T47_X, R600::T47_Y, R600::T47_Z, R600::T47_W, R600::T48_X, R600::T48_Y, R600::T48_Z, R600::T48_W, R600::T49_X, R600::T49_Y, R600::T49_Z, R600::T49_W, R600::T50_X, R600::T50_Y, R600::T50_Z, R600::T50_W, R600::T51_X, R600::T51_Y, R600::T51_Z, R600::T51_W, R600::T52_X, R600::T52_Y, R600::T52_Z, R600::T52_W, R600::T53_X, R600::T53_Y, R600::T53_Z, R600::T53_W, R600::T54_X, R600::T54_Y, R600::T54_Z, R600::T54_W, R600::T55_X, R600::T55_Y, R600::T55_Z, R600::T55_W, R600::T56_X, R600::T56_Y, R600::T56_Z, R600::T56_W, R600::T57_X, R600::T57_Y, R600::T57_Z, R600::T57_W, R600::T58_X, R600::T58_Y, R600::T58_Z, R600::T58_W, R600::T59_X, R600::T59_Y, R600::T59_Z, R600::T59_W, R600::T60_X, R600::T60_Y, R600::T60_Z, R600::T60_W, R600::T61_X, R600::T61_Y, R600::T61_Z, R600::T61_W, R600::T62_X, R600::T62_Y, R600::T62_Z, R600::T62_W, R600::T63_X, R600::T63_Y, R600::T63_Z, R600::T63_W, R600::T64_X, R600::T64_Y, R600::T64_Z, R600::T64_W, R600::T65_X, R600::T65_Y, R600::T65_Z, R600::T65_W, R600::T66_X, R600::T66_Y, R600::T66_Z, R600::T66_W, R600::T67_X, R600::T67_Y, R600::T67_Z, R600::T67_W, R600::T68_X, R600::T68_Y, R600::T68_Z, R600::T68_W, R600::T69_X, R600::T69_Y, R600::T69_Z, R600::T69_W, R600::T70_X, R600::T70_Y, R600::T70_Z, R600::T70_W, R600::T71_X, R600::T71_Y, R600::T71_Z, R600::T71_W, R600::T72_X, R600::T72_Y, R600::T72_Z, R600::T72_W, R600::T73_X, R600::T73_Y, R600::T73_Z, R600::T73_W, R600::T74_X, R600::T74_Y, R600::T74_Z, R600::T74_W, R600::T75_X, R600::T75_Y, R600::T75_Z, R600::T75_W, R600::T76_X, R600::T76_Y, R600::T76_Z, R600::T76_W, R600::T77_X, R600::T77_Y, R600::T77_Z, R600::T77_W, R600::T78_X, R600::T78_Y, R600::T78_Z, R600::T78_W, R600::T79_X, R600::T79_Y, R600::T79_Z, R600::T79_W, R600::T80_X, R600::T80_Y, R600::T80_Z, R600::T80_W, R600::T81_X, R600::T81_Y, R600::T81_Z, R600::T81_W, R600::T82_X, R600::T82_Y, R600::T82_Z, R600::T82_W, R600::T83_X, R600::T83_Y, R600::T83_Z, R600::T83_W, R600::T84_X, R600::T84_Y, R600::T84_Z, R600::T84_W, R600::T85_X, R600::T85_Y, R600::T85_Z, R600::T85_W, R600::T86_X, R600::T86_Y, R600::T86_Z, R600::T86_W, R600::T87_X, R600::T87_Y, R600::T87_Z, R600::T87_W, R600::T88_X, R600::T88_Y, R600::T88_Z, R600::T88_W, R600::T89_X, R600::T89_Y, R600::T89_Z, R600::T89_W, R600::T90_X, R600::T90_Y, R600::T90_Z, R600::T90_W, R600::T91_X, R600::T91_Y, R600::T91_Z, R600::T91_W, R600::T92_X, R600::T92_Y, R600::T92_Z, R600::T92_W, R600::T93_X, R600::T93_Y, R600::T93_Z, R600::T93_W, R600::T94_X, R600::T94_Y, R600::T94_Z, R600::T94_W, R600::T95_X, R600::T95_Y, R600::T95_Z, R600::T95_W, R600::T96_X, R600::T96_Y, R600::T96_Z, R600::T96_W, R600::T97_X, R600::T97_Y, R600::T97_Z, R600::T97_W, R600::T98_X, R600::T98_Y, R600::T98_Z, R600::T98_W, R600::T99_X, R600::T99_Y, R600::T99_Z, R600::T99_W, R600::T100_X, R600::T100_Y, R600::T100_Z, R600::T100_W, R600::T101_X, R600::T101_Y, R600::T101_Z, R600::T101_W, R600::T102_X, R600::T102_Y, R600::T102_Z, R600::T102_W, R600::T103_X, R600::T103_Y, R600::T103_Z, R600::T103_W, R600::T104_X, R600::T104_Y, R600::T104_Z, R600::T104_W, R600::T105_X, R600::T105_Y, R600::T105_Z, R600::T105_W, R600::T106_X, R600::T106_Y, R600::T106_Z, R600::T106_W, R600::T107_X, R600::T107_Y, R600::T107_Z, R600::T107_W, R600::T108_X, R600::T108_Y, R600::T108_Z, R600::T108_W, R600::T109_X, R600::T109_Y, R600::T109_Z, R600::T109_W, R600::T110_X, R600::T110_Y, R600::T110_Z, R600::T110_W, R600::T111_X, R600::T111_Y, R600::T111_Z, R600::T111_W, R600::T112_X, R600::T112_Y, R600::T112_Z, R600::T112_W, R600::T113_X, R600::T113_Y, R600::T113_Z, R600::T113_W, R600::T114_X, R600::T114_Y, R600::T114_Z, R600::T114_W, R600::T115_X, R600::T115_Y, R600::T115_Z, R600::T115_W, R600::T116_X, R600::T116_Y, R600::T116_Z, R600::T116_W, R600::T117_X, R600::T117_Y, R600::T117_Z, R600::T117_W, R600::T118_X, R600::T118_Y, R600::T118_Z, R600::T118_W, R600::T119_X, R600::T119_Y, R600::T119_Z, R600::T119_W, R600::T120_X, R600::T120_Y, R600::T120_Z, R600::T120_W, R600::T121_X, R600::T121_Y, R600::T121_Z, R600::T121_W, R600::T122_X, R600::T122_Y, R600::T122_Z, R600::T122_W, R600::T123_X, R600::T123_Y, R600::T123_Z, R600::T123_W, R600::T124_X, R600::T124_Y, R600::T124_Z, R600::T124_W, R600::T125_X, R600::T125_Y, R600::T125_Z, R600::T125_W, R600::T126_X, R600::T126_Y, R600::T126_Z, R600::T126_W, R600::T127_X, R600::T127_Y, R600::T127_Z, R600::T127_W, R600::AR_X, R600::ArrayBase448, R600::ArrayBase449, R600::ArrayBase450, R600::ArrayBase451, R600::ArrayBase452, R600::ArrayBase453, R600::ArrayBase454, R600::ArrayBase455, R600::ArrayBase456, R600::ArrayBase457, R600::ArrayBase458, R600::ArrayBase459, R600::ArrayBase460, R600::ArrayBase461, R600::ArrayBase462, R600::ArrayBase463, R600::ArrayBase464, R600::ArrayBase465, R600::ArrayBase466, R600::ArrayBase467, R600::ArrayBase468, R600::ArrayBase469, R600::ArrayBase470, R600::ArrayBase471, R600::ArrayBase472, R600::ArrayBase473, R600::ArrayBase474, R600::ArrayBase475, R600::ArrayBase476, R600::ArrayBase477, R600::ArrayBase478, R600::ArrayBase479, R600::ArrayBase480, R600::Addr0_X, R600::Addr1_X, R600::Addr2_X, R600::Addr3_X, R600::Addr4_X, R600::Addr5_X, R600::Addr6_X, R600::Addr7_X, R600::Addr8_X, R600::Addr9_X, R600::Addr10_X, R600::Addr11_X, R600::Addr12_X, R600::Addr13_X, R600::Addr14_X, R600::Addr15_X, R600::Addr16_X, R600::Addr17_X, R600::Addr18_X, R600::Addr19_X, R600::Addr20_X, R600::Addr21_X, R600::Addr22_X, R600::Addr23_X, R600::Addr24_X, R600::Addr25_X, R600::Addr26_X, R600::Addr27_X, R600::Addr28_X, R600::Addr29_X, R600::Addr30_X, R600::Addr31_X, R600::Addr32_X, R600::Addr33_X, R600::Addr34_X, R600::Addr35_X, R600::Addr36_X, R600::Addr37_X, R600::Addr38_X, R600::Addr39_X, R600::Addr40_X, R600::Addr41_X, R600::Addr42_X, R600::Addr43_X, R600::Addr44_X, R600::Addr45_X, R600::Addr46_X, R600::Addr47_X, R600::Addr48_X, R600::Addr49_X, R600::Addr50_X, R600::Addr51_X, R600::Addr52_X, R600::Addr53_X, R600::Addr54_X, R600::Addr55_X, R600::Addr56_X, R600::Addr57_X, R600::Addr58_X, R600::Addr59_X, R600::Addr60_X, R600::Addr61_X, R600::Addr62_X, R600::Addr63_X, R600::Addr64_X, R600::Addr65_X, R600::Addr66_X, R600::Addr67_X, R600::Addr68_X, R600::Addr69_X, R600::Addr70_X, R600::Addr71_X, R600::Addr72_X, R600::Addr73_X, R600::Addr74_X, R600::Addr75_X, R600::Addr76_X, R600::Addr77_X, R600::Addr78_X, R600::Addr79_X, R600::Addr80_X, R600::Addr81_X, R600::Addr82_X, R600::Addr83_X, R600::Addr84_X, R600::Addr85_X, R600::Addr86_X, R600::Addr87_X, R600::Addr88_X, R600::Addr89_X, R600::Addr90_X, R600::Addr91_X, R600::Addr92_X, R600::Addr93_X, R600::Addr94_X, R600::Addr95_X, R600::Addr96_X, R600::Addr97_X, R600::Addr98_X, R600::Addr99_X, R600::Addr100_X, R600::Addr101_X, R600::Addr102_X, R600::Addr103_X, R600::Addr104_X, R600::Addr105_X, R600::Addr106_X, R600::Addr107_X, R600::Addr108_X, R600::Addr109_X, R600::Addr110_X, R600::Addr111_X, R600::Addr112_X, R600::Addr113_X, R600::Addr114_X, R600::Addr115_X, R600::Addr116_X, R600::Addr117_X, R600::Addr118_X, R600::Addr119_X, R600::Addr120_X, R600::Addr121_X, R600::Addr122_X, R600::Addr123_X, R600::Addr124_X, R600::Addr125_X, R600::Addr126_X, R600::Addr127_X, R600::KC0_128_X, R600::KC0_128_Y, R600::KC0_128_Z, R600::KC0_128_W, R600::KC0_129_X, R600::KC0_129_Y, R600::KC0_129_Z, R600::KC0_129_W, R600::KC0_130_X, R600::KC0_130_Y, R600::KC0_130_Z, R600::KC0_130_W, R600::KC0_131_X, R600::KC0_131_Y, R600::KC0_131_Z, R600::KC0_131_W, R600::KC0_132_X, R600::KC0_132_Y, R600::KC0_132_Z, R600::KC0_132_W, R600::KC0_133_X, R600::KC0_133_Y, R600::KC0_133_Z, R600::KC0_133_W, R600::KC0_134_X, R600::KC0_134_Y, R600::KC0_134_Z, R600::KC0_134_W, R600::KC0_135_X, R600::KC0_135_Y, R600::KC0_135_Z, R600::KC0_135_W, R600::KC0_136_X, R600::KC0_136_Y, R600::KC0_136_Z, R600::KC0_136_W, R600::KC0_137_X, R600::KC0_137_Y, R600::KC0_137_Z, R600::KC0_137_W, R600::KC0_138_X, R600::KC0_138_Y, R600::KC0_138_Z, R600::KC0_138_W, R600::KC0_139_X, R600::KC0_139_Y, R600::KC0_139_Z, R600::KC0_139_W, R600::KC0_140_X, R600::KC0_140_Y, R600::KC0_140_Z, R600::KC0_140_W, R600::KC0_141_X, R600::KC0_141_Y, R600::KC0_141_Z, R600::KC0_141_W, R600::KC0_142_X, R600::KC0_142_Y, R600::KC0_142_Z, R600::KC0_142_W, R600::KC0_143_X, R600::KC0_143_Y, R600::KC0_143_Z, R600::KC0_143_W, R600::KC0_144_X, R600::KC0_144_Y, R600::KC0_144_Z, R600::KC0_144_W, R600::KC0_145_X, R600::KC0_145_Y, R600::KC0_145_Z, R600::KC0_145_W, R600::KC0_146_X, R600::KC0_146_Y, R600::KC0_146_Z, R600::KC0_146_W, R600::KC0_147_X, R600::KC0_147_Y, R600::KC0_147_Z, R600::KC0_147_W, R600::KC0_148_X, R600::KC0_148_Y, R600::KC0_148_Z, R600::KC0_148_W, R600::KC0_149_X, R600::KC0_149_Y, R600::KC0_149_Z, R600::KC0_149_W, R600::KC0_150_X, R600::KC0_150_Y, R600::KC0_150_Z, R600::KC0_150_W, R600::KC0_151_X, R600::KC0_151_Y, R600::KC0_151_Z, R600::KC0_151_W, R600::KC0_152_X, R600::KC0_152_Y, R600::KC0_152_Z, R600::KC0_152_W, R600::KC0_153_X, R600::KC0_153_Y, R600::KC0_153_Z, R600::KC0_153_W, R600::KC0_154_X, R600::KC0_154_Y, R600::KC0_154_Z, R600::KC0_154_W, R600::KC0_155_X, R600::KC0_155_Y, R600::KC0_155_Z, R600::KC0_155_W, R600::KC0_156_X, R600::KC0_156_Y, R600::KC0_156_Z, R600::KC0_156_W, R600::KC0_157_X, R600::KC0_157_Y, R600::KC0_157_Z, R600::KC0_157_W, R600::KC0_158_X, R600::KC0_158_Y, R600::KC0_158_Z, R600::KC0_158_W, R600::KC0_159_X, R600::KC0_159_Y, R600::KC0_159_Z, R600::KC0_159_W, R600::KC1_160_X, R600::KC1_160_Y, R600::KC1_160_Z, R600::KC1_160_W, R600::KC1_161_X, R600::KC1_161_Y, R600::KC1_161_Z, R600::KC1_161_W, R600::KC1_162_X, R600::KC1_162_Y, R600::KC1_162_Z, R600::KC1_162_W, R600::KC1_163_X, R600::KC1_163_Y, R600::KC1_163_Z, R600::KC1_163_W, R600::KC1_164_X, R600::KC1_164_Y, R600::KC1_164_Z, R600::KC1_164_W, R600::KC1_165_X, R600::KC1_165_Y, R600::KC1_165_Z, R600::KC1_165_W, R600::KC1_166_X, R600::KC1_166_Y, R600::KC1_166_Z, R600::KC1_166_W, R600::KC1_167_X, R600::KC1_167_Y, R600::KC1_167_Z, R600::KC1_167_W, R600::KC1_168_X, R600::KC1_168_Y, R600::KC1_168_Z, R600::KC1_168_W, R600::KC1_169_X, R600::KC1_169_Y, R600::KC1_169_Z, R600::KC1_169_W, R600::KC1_170_X, R600::KC1_170_Y, R600::KC1_170_Z, R600::KC1_170_W, R600::KC1_171_X, R600::KC1_171_Y, R600::KC1_171_Z, R600::KC1_171_W, R600::KC1_172_X, R600::KC1_172_Y, R600::KC1_172_Z, R600::KC1_172_W, R600::KC1_173_X, R600::KC1_173_Y, R600::KC1_173_Z, R600::KC1_173_W, R600::KC1_174_X, R600::KC1_174_Y, R600::KC1_174_Z, R600::KC1_174_W, R600::KC1_175_X, R600::KC1_175_Y, R600::KC1_175_Z, R600::KC1_175_W, R600::KC1_176_X, R600::KC1_176_Y, R600::KC1_176_Z, R600::KC1_176_W, R600::KC1_177_X, R600::KC1_177_Y, R600::KC1_177_Z, R600::KC1_177_W, R600::KC1_178_X, R600::KC1_178_Y, R600::KC1_178_Z, R600::KC1_178_W, R600::KC1_179_X, R600::KC1_179_Y, R600::KC1_179_Z, R600::KC1_179_W, R600::KC1_180_X, R600::KC1_180_Y, R600::KC1_180_Z, R600::KC1_180_W, R600::KC1_181_X, R600::KC1_181_Y, R600::KC1_181_Z, R600::KC1_181_W, R600::KC1_182_X, R600::KC1_182_Y, R600::KC1_182_Z, R600::KC1_182_W, R600::KC1_183_X, R600::KC1_183_Y, R600::KC1_183_Z, R600::KC1_183_W, R600::KC1_184_X, R600::KC1_184_Y, R600::KC1_184_Z, R600::KC1_184_W, R600::KC1_185_X, R600::KC1_185_Y, R600::KC1_185_Z, R600::KC1_185_W, R600::KC1_186_X, R600::KC1_186_Y, R600::KC1_186_Z, R600::KC1_186_W, R600::KC1_187_X, R600::KC1_187_Y, R600::KC1_187_Z, R600::KC1_187_W, R600::KC1_188_X, R600::KC1_188_Y, R600::KC1_188_Z, R600::KC1_188_W, R600::KC1_189_X, R600::KC1_189_Y, R600::KC1_189_Z, R600::KC1_189_W, R600::KC1_190_X, R600::KC1_190_Y, R600::KC1_190_Z, R600::KC1_190_W, R600::KC1_191_X, R600::KC1_191_Y, R600::KC1_191_Z, R600::KC1_191_W, R600::ZERO, R600::HALF, R600::ONE, R600::ONE_INT, R600::PV_X, R600::ALU_LITERAL_X, R600::NEG_ONE, R600::NEG_HALF, R600::ALU_CONST, R600::ALU_PARAM, R600::OQAP, R600::INDIRECT_BASE_ADDR, |
6661 | | }; |
6662 | | |
6663 | | // R600_Reg32 Bit set. |
6664 | | const uint8_t R600_Reg32Bits[] = { |
6665 | | 0xca, 0xf3, 0x02, 0xe4, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x00, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, |
6666 | | }; |
6667 | | |
6668 | | // R600_TReg32 Register Class... |
6669 | | const MCPhysReg R600_TReg32[] = { |
6670 | | R600::T0_X, R600::T0_Y, R600::T0_Z, R600::T0_W, R600::T1_X, R600::T1_Y, R600::T1_Z, R600::T1_W, R600::T2_X, R600::T2_Y, R600::T2_Z, R600::T2_W, R600::T3_X, R600::T3_Y, R600::T3_Z, R600::T3_W, R600::T4_X, R600::T4_Y, R600::T4_Z, R600::T4_W, R600::T5_X, R600::T5_Y, R600::T5_Z, R600::T5_W, R600::T6_X, R600::T6_Y, R600::T6_Z, R600::T6_W, R600::T7_X, R600::T7_Y, R600::T7_Z, R600::T7_W, R600::T8_X, R600::T8_Y, R600::T8_Z, R600::T8_W, R600::T9_X, R600::T9_Y, R600::T9_Z, R600::T9_W, R600::T10_X, R600::T10_Y, R600::T10_Z, R600::T10_W, R600::T11_X, R600::T11_Y, R600::T11_Z, R600::T11_W, R600::T12_X, R600::T12_Y, R600::T12_Z, R600::T12_W, R600::T13_X, R600::T13_Y, R600::T13_Z, R600::T13_W, R600::T14_X, R600::T14_Y, R600::T14_Z, R600::T14_W, R600::T15_X, R600::T15_Y, R600::T15_Z, R600::T15_W, R600::T16_X, R600::T16_Y, R600::T16_Z, R600::T16_W, R600::T17_X, R600::T17_Y, R600::T17_Z, R600::T17_W, R600::T18_X, R600::T18_Y, R600::T18_Z, R600::T18_W, R600::T19_X, R600::T19_Y, R600::T19_Z, R600::T19_W, R600::T20_X, R600::T20_Y, R600::T20_Z, R600::T20_W, R600::T21_X, R600::T21_Y, R600::T21_Z, R600::T21_W, R600::T22_X, R600::T22_Y, R600::T22_Z, R600::T22_W, R600::T23_X, R600::T23_Y, R600::T23_Z, R600::T23_W, R600::T24_X, R600::T24_Y, R600::T24_Z, R600::T24_W, R600::T25_X, R600::T25_Y, R600::T25_Z, R600::T25_W, R600::T26_X, R600::T26_Y, R600::T26_Z, R600::T26_W, R600::T27_X, R600::T27_Y, R600::T27_Z, R600::T27_W, R600::T28_X, R600::T28_Y, R600::T28_Z, R600::T28_W, R600::T29_X, R600::T29_Y, R600::T29_Z, R600::T29_W, R600::T30_X, R600::T30_Y, R600::T30_Z, R600::T30_W, R600::T31_X, R600::T31_Y, R600::T31_Z, R600::T31_W, R600::T32_X, R600::T32_Y, R600::T32_Z, R600::T32_W, R600::T33_X, R600::T33_Y, R600::T33_Z, R600::T33_W, R600::T34_X, R600::T34_Y, R600::T34_Z, R600::T34_W, R600::T35_X, R600::T35_Y, R600::T35_Z, R600::T35_W, R600::T36_X, R600::T36_Y, R600::T36_Z, R600::T36_W, R600::T37_X, R600::T37_Y, R600::T37_Z, R600::T37_W, R600::T38_X, R600::T38_Y, R600::T38_Z, R600::T38_W, R600::T39_X, R600::T39_Y, R600::T39_Z, R600::T39_W, R600::T40_X, R600::T40_Y, R600::T40_Z, R600::T40_W, R600::T41_X, R600::T41_Y, R600::T41_Z, R600::T41_W, R600::T42_X, R600::T42_Y, R600::T42_Z, R600::T42_W, R600::T43_X, R600::T43_Y, R600::T43_Z, R600::T43_W, R600::T44_X, R600::T44_Y, R600::T44_Z, R600::T44_W, R600::T45_X, R600::T45_Y, R600::T45_Z, R600::T45_W, R600::T46_X, R600::T46_Y, R600::T46_Z, R600::T46_W, R600::T47_X, R600::T47_Y, R600::T47_Z, R600::T47_W, R600::T48_X, R600::T48_Y, R600::T48_Z, R600::T48_W, R600::T49_X, R600::T49_Y, R600::T49_Z, R600::T49_W, R600::T50_X, R600::T50_Y, R600::T50_Z, R600::T50_W, R600::T51_X, R600::T51_Y, R600::T51_Z, R600::T51_W, R600::T52_X, R600::T52_Y, R600::T52_Z, R600::T52_W, R600::T53_X, R600::T53_Y, R600::T53_Z, R600::T53_W, R600::T54_X, R600::T54_Y, R600::T54_Z, R600::T54_W, R600::T55_X, R600::T55_Y, R600::T55_Z, R600::T55_W, R600::T56_X, R600::T56_Y, R600::T56_Z, R600::T56_W, R600::T57_X, R600::T57_Y, R600::T57_Z, R600::T57_W, R600::T58_X, R600::T58_Y, R600::T58_Z, R600::T58_W, R600::T59_X, R600::T59_Y, R600::T59_Z, R600::T59_W, R600::T60_X, R600::T60_Y, R600::T60_Z, R600::T60_W, R600::T61_X, R600::T61_Y, R600::T61_Z, R600::T61_W, R600::T62_X, R600::T62_Y, R600::T62_Z, R600::T62_W, R600::T63_X, R600::T63_Y, R600::T63_Z, R600::T63_W, R600::T64_X, R600::T64_Y, R600::T64_Z, R600::T64_W, R600::T65_X, R600::T65_Y, R600::T65_Z, R600::T65_W, R600::T66_X, R600::T66_Y, R600::T66_Z, R600::T66_W, R600::T67_X, R600::T67_Y, R600::T67_Z, R600::T67_W, R600::T68_X, R600::T68_Y, R600::T68_Z, R600::T68_W, R600::T69_X, R600::T69_Y, R600::T69_Z, R600::T69_W, R600::T70_X, R600::T70_Y, R600::T70_Z, R600::T70_W, R600::T71_X, R600::T71_Y, R600::T71_Z, R600::T71_W, R600::T72_X, R600::T72_Y, R600::T72_Z, R600::T72_W, R600::T73_X, R600::T73_Y, R600::T73_Z, R600::T73_W, R600::T74_X, R600::T74_Y, R600::T74_Z, R600::T74_W, R600::T75_X, R600::T75_Y, R600::T75_Z, R600::T75_W, R600::T76_X, R600::T76_Y, R600::T76_Z, R600::T76_W, R600::T77_X, R600::T77_Y, R600::T77_Z, R600::T77_W, R600::T78_X, R600::T78_Y, R600::T78_Z, R600::T78_W, R600::T79_X, R600::T79_Y, R600::T79_Z, R600::T79_W, R600::T80_X, R600::T80_Y, R600::T80_Z, R600::T80_W, R600::T81_X, R600::T81_Y, R600::T81_Z, R600::T81_W, R600::T82_X, R600::T82_Y, R600::T82_Z, R600::T82_W, R600::T83_X, R600::T83_Y, R600::T83_Z, R600::T83_W, R600::T84_X, R600::T84_Y, R600::T84_Z, R600::T84_W, R600::T85_X, R600::T85_Y, R600::T85_Z, R600::T85_W, R600::T86_X, R600::T86_Y, R600::T86_Z, R600::T86_W, R600::T87_X, R600::T87_Y, R600::T87_Z, R600::T87_W, R600::T88_X, R600::T88_Y, R600::T88_Z, R600::T88_W, R600::T89_X, R600::T89_Y, R600::T89_Z, R600::T89_W, R600::T90_X, R600::T90_Y, R600::T90_Z, R600::T90_W, R600::T91_X, R600::T91_Y, R600::T91_Z, R600::T91_W, R600::T92_X, R600::T92_Y, R600::T92_Z, R600::T92_W, R600::T93_X, R600::T93_Y, R600::T93_Z, R600::T93_W, R600::T94_X, R600::T94_Y, R600::T94_Z, R600::T94_W, R600::T95_X, R600::T95_Y, R600::T95_Z, R600::T95_W, R600::T96_X, R600::T96_Y, R600::T96_Z, R600::T96_W, R600::T97_X, R600::T97_Y, R600::T97_Z, R600::T97_W, R600::T98_X, R600::T98_Y, R600::T98_Z, R600::T98_W, R600::T99_X, R600::T99_Y, R600::T99_Z, R600::T99_W, R600::T100_X, R600::T100_Y, R600::T100_Z, R600::T100_W, R600::T101_X, R600::T101_Y, R600::T101_Z, R600::T101_W, R600::T102_X, R600::T102_Y, R600::T102_Z, R600::T102_W, R600::T103_X, R600::T103_Y, R600::T103_Z, R600::T103_W, R600::T104_X, R600::T104_Y, R600::T104_Z, R600::T104_W, R600::T105_X, R600::T105_Y, R600::T105_Z, R600::T105_W, R600::T106_X, R600::T106_Y, R600::T106_Z, R600::T106_W, R600::T107_X, R600::T107_Y, R600::T107_Z, R600::T107_W, R600::T108_X, R600::T108_Y, R600::T108_Z, R600::T108_W, R600::T109_X, R600::T109_Y, R600::T109_Z, R600::T109_W, R600::T110_X, R600::T110_Y, R600::T110_Z, R600::T110_W, R600::T111_X, R600::T111_Y, R600::T111_Z, R600::T111_W, R600::T112_X, R600::T112_Y, R600::T112_Z, R600::T112_W, R600::T113_X, R600::T113_Y, R600::T113_Z, R600::T113_W, R600::T114_X, R600::T114_Y, R600::T114_Z, R600::T114_W, R600::T115_X, R600::T115_Y, R600::T115_Z, R600::T115_W, R600::T116_X, R600::T116_Y, R600::T116_Z, R600::T116_W, R600::T117_X, R600::T117_Y, R600::T117_Z, R600::T117_W, R600::T118_X, R600::T118_Y, R600::T118_Z, R600::T118_W, R600::T119_X, R600::T119_Y, R600::T119_Z, R600::T119_W, R600::T120_X, R600::T120_Y, R600::T120_Z, R600::T120_W, R600::T121_X, R600::T121_Y, R600::T121_Z, R600::T121_W, R600::T122_X, R600::T122_Y, R600::T122_Z, R600::T122_W, R600::T123_X, R600::T123_Y, R600::T123_Z, R600::T123_W, R600::T124_X, R600::T124_Y, R600::T124_Z, R600::T124_W, R600::T125_X, R600::T125_Y, R600::T125_Z, R600::T125_W, R600::T126_X, R600::T126_Y, R600::T126_Z, R600::T126_W, R600::T127_X, R600::T127_Y, R600::T127_Z, R600::T127_W, R600::AR_X, |
6671 | | }; |
6672 | | |
6673 | | // R600_TReg32 Bit set. |
6674 | | const uint8_t R600_TReg32Bits[] = { |
6675 | | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, |
6676 | | }; |
6677 | | |
6678 | | // R600_TReg32_X Register Class... |
6679 | | const MCPhysReg R600_TReg32_X[] = { |
6680 | | R600::T0_X, R600::T1_X, R600::T2_X, R600::T3_X, R600::T4_X, R600::T5_X, R600::T6_X, R600::T7_X, R600::T8_X, R600::T9_X, R600::T10_X, R600::T11_X, R600::T12_X, R600::T13_X, R600::T14_X, R600::T15_X, R600::T16_X, R600::T17_X, R600::T18_X, R600::T19_X, R600::T20_X, R600::T21_X, R600::T22_X, R600::T23_X, R600::T24_X, R600::T25_X, R600::T26_X, R600::T27_X, R600::T28_X, R600::T29_X, R600::T30_X, R600::T31_X, R600::T32_X, R600::T33_X, R600::T34_X, R600::T35_X, R600::T36_X, R600::T37_X, R600::T38_X, R600::T39_X, R600::T40_X, R600::T41_X, R600::T42_X, R600::T43_X, R600::T44_X, R600::T45_X, R600::T46_X, R600::T47_X, R600::T48_X, R600::T49_X, R600::T50_X, R600::T51_X, R600::T52_X, R600::T53_X, R600::T54_X, R600::T55_X, R600::T56_X, R600::T57_X, R600::T58_X, R600::T59_X, R600::T60_X, R600::T61_X, R600::T62_X, R600::T63_X, R600::T64_X, R600::T65_X, R600::T66_X, R600::T67_X, R600::T68_X, R600::T69_X, R600::T70_X, R600::T71_X, R600::T72_X, R600::T73_X, R600::T74_X, R600::T75_X, R600::T76_X, R600::T77_X, R600::T78_X, R600::T79_X, R600::T80_X, R600::T81_X, R600::T82_X, R600::T83_X, R600::T84_X, R600::T85_X, R600::T86_X, R600::T87_X, R600::T88_X, R600::T89_X, R600::T90_X, R600::T91_X, R600::T92_X, R600::T93_X, R600::T94_X, R600::T95_X, R600::T96_X, R600::T97_X, R600::T98_X, R600::T99_X, R600::T100_X, R600::T101_X, R600::T102_X, R600::T103_X, R600::T104_X, R600::T105_X, R600::T106_X, R600::T107_X, R600::T108_X, R600::T109_X, R600::T110_X, R600::T111_X, R600::T112_X, R600::T113_X, R600::T114_X, R600::T115_X, R600::T116_X, R600::T117_X, R600::T118_X, R600::T119_X, R600::T120_X, R600::T121_X, R600::T122_X, R600::T123_X, R600::T124_X, R600::T125_X, R600::T126_X, R600::T127_X, R600::AR_X, |
6681 | | }; |
6682 | | |
6683 | | // R600_TReg32_X Bit set. |
6684 | | const uint8_t R600_TReg32_XBits[] = { |
6685 | | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, |
6686 | | }; |
6687 | | |
6688 | | // R600_Addr Register Class... |
6689 | | const MCPhysReg R600_Addr[] = { |
6690 | | R600::Addr0_X, R600::Addr1_X, R600::Addr2_X, R600::Addr3_X, R600::Addr4_X, R600::Addr5_X, R600::Addr6_X, R600::Addr7_X, R600::Addr8_X, R600::Addr9_X, R600::Addr10_X, R600::Addr11_X, R600::Addr12_X, R600::Addr13_X, R600::Addr14_X, R600::Addr15_X, R600::Addr16_X, R600::Addr17_X, R600::Addr18_X, R600::Addr19_X, R600::Addr20_X, R600::Addr21_X, R600::Addr22_X, R600::Addr23_X, R600::Addr24_X, R600::Addr25_X, R600::Addr26_X, R600::Addr27_X, R600::Addr28_X, R600::Addr29_X, R600::Addr30_X, R600::Addr31_X, R600::Addr32_X, R600::Addr33_X, R600::Addr34_X, R600::Addr35_X, R600::Addr36_X, R600::Addr37_X, R600::Addr38_X, R600::Addr39_X, R600::Addr40_X, R600::Addr41_X, R600::Addr42_X, R600::Addr43_X, R600::Addr44_X, R600::Addr45_X, R600::Addr46_X, R600::Addr47_X, R600::Addr48_X, R600::Addr49_X, R600::Addr50_X, R600::Addr51_X, R600::Addr52_X, R600::Addr53_X, R600::Addr54_X, R600::Addr55_X, R600::Addr56_X, R600::Addr57_X, R600::Addr58_X, R600::Addr59_X, R600::Addr60_X, R600::Addr61_X, R600::Addr62_X, R600::Addr63_X, R600::Addr64_X, R600::Addr65_X, R600::Addr66_X, R600::Addr67_X, R600::Addr68_X, R600::Addr69_X, R600::Addr70_X, R600::Addr71_X, R600::Addr72_X, R600::Addr73_X, R600::Addr74_X, R600::Addr75_X, R600::Addr76_X, R600::Addr77_X, R600::Addr78_X, R600::Addr79_X, R600::Addr80_X, R600::Addr81_X, R600::Addr82_X, R600::Addr83_X, R600::Addr84_X, R600::Addr85_X, R600::Addr86_X, R600::Addr87_X, R600::Addr88_X, R600::Addr89_X, R600::Addr90_X, R600::Addr91_X, R600::Addr92_X, R600::Addr93_X, R600::Addr94_X, R600::Addr95_X, R600::Addr96_X, R600::Addr97_X, R600::Addr98_X, R600::Addr99_X, R600::Addr100_X, R600::Addr101_X, R600::Addr102_X, R600::Addr103_X, R600::Addr104_X, R600::Addr105_X, R600::Addr106_X, R600::Addr107_X, R600::Addr108_X, R600::Addr109_X, R600::Addr110_X, R600::Addr111_X, R600::Addr112_X, R600::Addr113_X, R600::Addr114_X, R600::Addr115_X, R600::Addr116_X, R600::Addr117_X, R600::Addr118_X, R600::Addr119_X, R600::Addr120_X, R600::Addr121_X, R600::Addr122_X, R600::Addr123_X, R600::Addr124_X, R600::Addr125_X, R600::Addr126_X, R600::Addr127_X, |
6691 | | }; |
6692 | | |
6693 | | // R600_Addr Bit set. |
6694 | | const uint8_t R600_AddrBits[] = { |
6695 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, |
6696 | | }; |
6697 | | |
6698 | | // R600_KC0 Register Class... |
6699 | | const MCPhysReg R600_KC0[] = { |
6700 | | R600::KC0_128_X, R600::KC0_128_Y, R600::KC0_128_Z, R600::KC0_128_W, R600::KC0_129_X, R600::KC0_129_Y, R600::KC0_129_Z, R600::KC0_129_W, R600::KC0_130_X, R600::KC0_130_Y, R600::KC0_130_Z, R600::KC0_130_W, R600::KC0_131_X, R600::KC0_131_Y, R600::KC0_131_Z, R600::KC0_131_W, R600::KC0_132_X, R600::KC0_132_Y, R600::KC0_132_Z, R600::KC0_132_W, R600::KC0_133_X, R600::KC0_133_Y, R600::KC0_133_Z, R600::KC0_133_W, R600::KC0_134_X, R600::KC0_134_Y, R600::KC0_134_Z, R600::KC0_134_W, R600::KC0_135_X, R600::KC0_135_Y, R600::KC0_135_Z, R600::KC0_135_W, R600::KC0_136_X, R600::KC0_136_Y, R600::KC0_136_Z, R600::KC0_136_W, R600::KC0_137_X, R600::KC0_137_Y, R600::KC0_137_Z, R600::KC0_137_W, R600::KC0_138_X, R600::KC0_138_Y, R600::KC0_138_Z, R600::KC0_138_W, R600::KC0_139_X, R600::KC0_139_Y, R600::KC0_139_Z, R600::KC0_139_W, R600::KC0_140_X, R600::KC0_140_Y, R600::KC0_140_Z, R600::KC0_140_W, R600::KC0_141_X, R600::KC0_141_Y, R600::KC0_141_Z, R600::KC0_141_W, R600::KC0_142_X, R600::KC0_142_Y, R600::KC0_142_Z, R600::KC0_142_W, R600::KC0_143_X, R600::KC0_143_Y, R600::KC0_143_Z, R600::KC0_143_W, R600::KC0_144_X, R600::KC0_144_Y, R600::KC0_144_Z, R600::KC0_144_W, R600::KC0_145_X, R600::KC0_145_Y, R600::KC0_145_Z, R600::KC0_145_W, R600::KC0_146_X, R600::KC0_146_Y, R600::KC0_146_Z, R600::KC0_146_W, R600::KC0_147_X, R600::KC0_147_Y, R600::KC0_147_Z, R600::KC0_147_W, R600::KC0_148_X, R600::KC0_148_Y, R600::KC0_148_Z, R600::KC0_148_W, R600::KC0_149_X, R600::KC0_149_Y, R600::KC0_149_Z, R600::KC0_149_W, R600::KC0_150_X, R600::KC0_150_Y, R600::KC0_150_Z, R600::KC0_150_W, R600::KC0_151_X, R600::KC0_151_Y, R600::KC0_151_Z, R600::KC0_151_W, R600::KC0_152_X, R600::KC0_152_Y, R600::KC0_152_Z, R600::KC0_152_W, R600::KC0_153_X, R600::KC0_153_Y, R600::KC0_153_Z, R600::KC0_153_W, R600::KC0_154_X, R600::KC0_154_Y, R600::KC0_154_Z, R600::KC0_154_W, R600::KC0_155_X, R600::KC0_155_Y, R600::KC0_155_Z, R600::KC0_155_W, R600::KC0_156_X, R600::KC0_156_Y, R600::KC0_156_Z, R600::KC0_156_W, R600::KC0_157_X, R600::KC0_157_Y, R600::KC0_157_Z, R600::KC0_157_W, R600::KC0_158_X, R600::KC0_158_Y, R600::KC0_158_Z, R600::KC0_158_W, R600::KC0_159_X, R600::KC0_159_Y, R600::KC0_159_Z, R600::KC0_159_W, |
6701 | | }; |
6702 | | |
6703 | | // R600_KC0 Bit set. |
6704 | | const uint8_t R600_KC0Bits[] = { |
6705 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
6706 | | }; |
6707 | | |
6708 | | // R600_KC1 Register Class... |
6709 | | const MCPhysReg R600_KC1[] = { |
6710 | | R600::KC1_160_X, R600::KC1_160_Y, R600::KC1_160_Z, R600::KC1_160_W, R600::KC1_161_X, R600::KC1_161_Y, R600::KC1_161_Z, R600::KC1_161_W, R600::KC1_162_X, R600::KC1_162_Y, R600::KC1_162_Z, R600::KC1_162_W, R600::KC1_163_X, R600::KC1_163_Y, R600::KC1_163_Z, R600::KC1_163_W, R600::KC1_164_X, R600::KC1_164_Y, R600::KC1_164_Z, R600::KC1_164_W, R600::KC1_165_X, R600::KC1_165_Y, R600::KC1_165_Z, R600::KC1_165_W, R600::KC1_166_X, R600::KC1_166_Y, R600::KC1_166_Z, R600::KC1_166_W, R600::KC1_167_X, R600::KC1_167_Y, R600::KC1_167_Z, R600::KC1_167_W, R600::KC1_168_X, R600::KC1_168_Y, R600::KC1_168_Z, R600::KC1_168_W, R600::KC1_169_X, R600::KC1_169_Y, R600::KC1_169_Z, R600::KC1_169_W, R600::KC1_170_X, R600::KC1_170_Y, R600::KC1_170_Z, R600::KC1_170_W, R600::KC1_171_X, R600::KC1_171_Y, R600::KC1_171_Z, R600::KC1_171_W, R600::KC1_172_X, R600::KC1_172_Y, R600::KC1_172_Z, R600::KC1_172_W, R600::KC1_173_X, R600::KC1_173_Y, R600::KC1_173_Z, R600::KC1_173_W, R600::KC1_174_X, R600::KC1_174_Y, R600::KC1_174_Z, R600::KC1_174_W, R600::KC1_175_X, R600::KC1_175_Y, R600::KC1_175_Z, R600::KC1_175_W, R600::KC1_176_X, R600::KC1_176_Y, R600::KC1_176_Z, R600::KC1_176_W, R600::KC1_177_X, R600::KC1_177_Y, R600::KC1_177_Z, R600::KC1_177_W, R600::KC1_178_X, R600::KC1_178_Y, R600::KC1_178_Z, R600::KC1_178_W, R600::KC1_179_X, R600::KC1_179_Y, R600::KC1_179_Z, R600::KC1_179_W, R600::KC1_180_X, R600::KC1_180_Y, R600::KC1_180_Z, R600::KC1_180_W, R600::KC1_181_X, R600::KC1_181_Y, R600::KC1_181_Z, R600::KC1_181_W, R600::KC1_182_X, R600::KC1_182_Y, R600::KC1_182_Z, R600::KC1_182_W, R600::KC1_183_X, R600::KC1_183_Y, R600::KC1_183_Z, R600::KC1_183_W, R600::KC1_184_X, R600::KC1_184_Y, R600::KC1_184_Z, R600::KC1_184_W, R600::KC1_185_X, R600::KC1_185_Y, R600::KC1_185_Z, R600::KC1_185_W, R600::KC1_186_X, R600::KC1_186_Y, R600::KC1_186_Z, R600::KC1_186_W, R600::KC1_187_X, R600::KC1_187_Y, R600::KC1_187_Z, R600::KC1_187_W, R600::KC1_188_X, R600::KC1_188_Y, R600::KC1_188_Z, R600::KC1_188_W, R600::KC1_189_X, R600::KC1_189_Y, R600::KC1_189_Z, R600::KC1_189_W, R600::KC1_190_X, R600::KC1_190_Y, R600::KC1_190_Z, R600::KC1_190_W, R600::KC1_191_X, R600::KC1_191_Y, R600::KC1_191_Z, R600::KC1_191_W, |
6711 | | }; |
6712 | | |
6713 | | // R600_KC1 Bit set. |
6714 | | const uint8_t R600_KC1Bits[] = { |
6715 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
6716 | | }; |
6717 | | |
6718 | | // R600_TReg32_W Register Class... |
6719 | | const MCPhysReg R600_TReg32_W[] = { |
6720 | | R600::T0_W, R600::T1_W, R600::T2_W, R600::T3_W, R600::T4_W, R600::T5_W, R600::T6_W, R600::T7_W, R600::T8_W, R600::T9_W, R600::T10_W, R600::T11_W, R600::T12_W, R600::T13_W, R600::T14_W, R600::T15_W, R600::T16_W, R600::T17_W, R600::T18_W, R600::T19_W, R600::T20_W, R600::T21_W, R600::T22_W, R600::T23_W, R600::T24_W, R600::T25_W, R600::T26_W, R600::T27_W, R600::T28_W, R600::T29_W, R600::T30_W, R600::T31_W, R600::T32_W, R600::T33_W, R600::T34_W, R600::T35_W, R600::T36_W, R600::T37_W, R600::T38_W, R600::T39_W, R600::T40_W, R600::T41_W, R600::T42_W, R600::T43_W, R600::T44_W, R600::T45_W, R600::T46_W, R600::T47_W, R600::T48_W, R600::T49_W, R600::T50_W, R600::T51_W, R600::T52_W, R600::T53_W, R600::T54_W, R600::T55_W, R600::T56_W, R600::T57_W, R600::T58_W, R600::T59_W, R600::T60_W, R600::T61_W, R600::T62_W, R600::T63_W, R600::T64_W, R600::T65_W, R600::T66_W, R600::T67_W, R600::T68_W, R600::T69_W, R600::T70_W, R600::T71_W, R600::T72_W, R600::T73_W, R600::T74_W, R600::T75_W, R600::T76_W, R600::T77_W, R600::T78_W, R600::T79_W, R600::T80_W, R600::T81_W, R600::T82_W, R600::T83_W, R600::T84_W, R600::T85_W, R600::T86_W, R600::T87_W, R600::T88_W, R600::T89_W, R600::T90_W, R600::T91_W, R600::T92_W, R600::T93_W, R600::T94_W, R600::T95_W, R600::T96_W, R600::T97_W, R600::T98_W, R600::T99_W, R600::T100_W, R600::T101_W, R600::T102_W, R600::T103_W, R600::T104_W, R600::T105_W, R600::T106_W, R600::T107_W, R600::T108_W, R600::T109_W, R600::T110_W, R600::T111_W, R600::T112_W, R600::T113_W, R600::T114_W, R600::T115_W, R600::T116_W, R600::T117_W, R600::T118_W, R600::T119_W, R600::T120_W, R600::T121_W, R600::T122_W, R600::T123_W, R600::T124_W, R600::T125_W, R600::T126_W, R600::T127_W, |
6721 | | }; |
6722 | | |
6723 | | // R600_TReg32_W Bit set. |
6724 | | const uint8_t R600_TReg32_WBits[] = { |
6725 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, |
6726 | | }; |
6727 | | |
6728 | | // R600_TReg32_Y Register Class... |
6729 | | const MCPhysReg R600_TReg32_Y[] = { |
6730 | | R600::T0_Y, R600::T1_Y, R600::T2_Y, R600::T3_Y, R600::T4_Y, R600::T5_Y, R600::T6_Y, R600::T7_Y, R600::T8_Y, R600::T9_Y, R600::T10_Y, R600::T11_Y, R600::T12_Y, R600::T13_Y, R600::T14_Y, R600::T15_Y, R600::T16_Y, R600::T17_Y, R600::T18_Y, R600::T19_Y, R600::T20_Y, R600::T21_Y, R600::T22_Y, R600::T23_Y, R600::T24_Y, R600::T25_Y, R600::T26_Y, R600::T27_Y, R600::T28_Y, R600::T29_Y, R600::T30_Y, R600::T31_Y, R600::T32_Y, R600::T33_Y, R600::T34_Y, R600::T35_Y, R600::T36_Y, R600::T37_Y, R600::T38_Y, R600::T39_Y, R600::T40_Y, R600::T41_Y, R600::T42_Y, R600::T43_Y, R600::T44_Y, R600::T45_Y, R600::T46_Y, R600::T47_Y, R600::T48_Y, R600::T49_Y, R600::T50_Y, R600::T51_Y, R600::T52_Y, R600::T53_Y, R600::T54_Y, R600::T55_Y, R600::T56_Y, R600::T57_Y, R600::T58_Y, R600::T59_Y, R600::T60_Y, R600::T61_Y, R600::T62_Y, R600::T63_Y, R600::T64_Y, R600::T65_Y, R600::T66_Y, R600::T67_Y, R600::T68_Y, R600::T69_Y, R600::T70_Y, R600::T71_Y, R600::T72_Y, R600::T73_Y, R600::T74_Y, R600::T75_Y, R600::T76_Y, R600::T77_Y, R600::T78_Y, R600::T79_Y, R600::T80_Y, R600::T81_Y, R600::T82_Y, R600::T83_Y, R600::T84_Y, R600::T85_Y, R600::T86_Y, R600::T87_Y, R600::T88_Y, R600::T89_Y, R600::T90_Y, R600::T91_Y, R600::T92_Y, R600::T93_Y, R600::T94_Y, R600::T95_Y, R600::T96_Y, R600::T97_Y, R600::T98_Y, R600::T99_Y, R600::T100_Y, R600::T101_Y, R600::T102_Y, R600::T103_Y, R600::T104_Y, R600::T105_Y, R600::T106_Y, R600::T107_Y, R600::T108_Y, R600::T109_Y, R600::T110_Y, R600::T111_Y, R600::T112_Y, R600::T113_Y, R600::T114_Y, R600::T115_Y, R600::T116_Y, R600::T117_Y, R600::T118_Y, R600::T119_Y, R600::T120_Y, R600::T121_Y, R600::T122_Y, R600::T123_Y, R600::T124_Y, R600::T125_Y, R600::T126_Y, R600::T127_Y, |
6731 | | }; |
6732 | | |
6733 | | // R600_TReg32_Y Bit set. |
6734 | | const uint8_t R600_TReg32_YBits[] = { |
6735 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, |
6736 | | }; |
6737 | | |
6738 | | // R600_TReg32_Z Register Class... |
6739 | | const MCPhysReg R600_TReg32_Z[] = { |
6740 | | R600::T0_Z, R600::T1_Z, R600::T2_Z, R600::T3_Z, R600::T4_Z, R600::T5_Z, R600::T6_Z, R600::T7_Z, R600::T8_Z, R600::T9_Z, R600::T10_Z, R600::T11_Z, R600::T12_Z, R600::T13_Z, R600::T14_Z, R600::T15_Z, R600::T16_Z, R600::T17_Z, R600::T18_Z, R600::T19_Z, R600::T20_Z, R600::T21_Z, R600::T22_Z, R600::T23_Z, R600::T24_Z, R600::T25_Z, R600::T26_Z, R600::T27_Z, R600::T28_Z, R600::T29_Z, R600::T30_Z, R600::T31_Z, R600::T32_Z, R600::T33_Z, R600::T34_Z, R600::T35_Z, R600::T36_Z, R600::T37_Z, R600::T38_Z, R600::T39_Z, R600::T40_Z, R600::T41_Z, R600::T42_Z, R600::T43_Z, R600::T44_Z, R600::T45_Z, R600::T46_Z, R600::T47_Z, R600::T48_Z, R600::T49_Z, R600::T50_Z, R600::T51_Z, R600::T52_Z, R600::T53_Z, R600::T54_Z, R600::T55_Z, R600::T56_Z, R600::T57_Z, R600::T58_Z, R600::T59_Z, R600::T60_Z, R600::T61_Z, R600::T62_Z, R600::T63_Z, R600::T64_Z, R600::T65_Z, R600::T66_Z, R600::T67_Z, R600::T68_Z, R600::T69_Z, R600::T70_Z, R600::T71_Z, R600::T72_Z, R600::T73_Z, R600::T74_Z, R600::T75_Z, R600::T76_Z, R600::T77_Z, R600::T78_Z, R600::T79_Z, R600::T80_Z, R600::T81_Z, R600::T82_Z, R600::T83_Z, R600::T84_Z, R600::T85_Z, R600::T86_Z, R600::T87_Z, R600::T88_Z, R600::T89_Z, R600::T90_Z, R600::T91_Z, R600::T92_Z, R600::T93_Z, R600::T94_Z, R600::T95_Z, R600::T96_Z, R600::T97_Z, R600::T98_Z, R600::T99_Z, R600::T100_Z, R600::T101_Z, R600::T102_Z, R600::T103_Z, R600::T104_Z, R600::T105_Z, R600::T106_Z, R600::T107_Z, R600::T108_Z, R600::T109_Z, R600::T110_Z, R600::T111_Z, R600::T112_Z, R600::T113_Z, R600::T114_Z, R600::T115_Z, R600::T116_Z, R600::T117_Z, R600::T118_Z, R600::T119_Z, R600::T120_Z, R600::T121_Z, R600::T122_Z, R600::T123_Z, R600::T124_Z, R600::T125_Z, R600::T126_Z, R600::T127_Z, |
6741 | | }; |
6742 | | |
6743 | | // R600_TReg32_Z Bit set. |
6744 | | const uint8_t R600_TReg32_ZBits[] = { |
6745 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, |
6746 | | }; |
6747 | | |
6748 | | // R600_ArrayBase Register Class... |
6749 | | const MCPhysReg R600_ArrayBase[] = { |
6750 | | R600::ArrayBase448, R600::ArrayBase449, R600::ArrayBase450, R600::ArrayBase451, R600::ArrayBase452, R600::ArrayBase453, R600::ArrayBase454, R600::ArrayBase455, R600::ArrayBase456, R600::ArrayBase457, R600::ArrayBase458, R600::ArrayBase459, R600::ArrayBase460, R600::ArrayBase461, R600::ArrayBase462, R600::ArrayBase463, R600::ArrayBase464, R600::ArrayBase465, R600::ArrayBase466, R600::ArrayBase467, R600::ArrayBase468, R600::ArrayBase469, R600::ArrayBase470, R600::ArrayBase471, R600::ArrayBase472, R600::ArrayBase473, R600::ArrayBase474, R600::ArrayBase475, R600::ArrayBase476, R600::ArrayBase477, R600::ArrayBase478, R600::ArrayBase479, R600::ArrayBase480, |
6751 | | }; |
6752 | | |
6753 | | // R600_ArrayBase Bit set. |
6754 | | const uint8_t R600_ArrayBaseBits[] = { |
6755 | | 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x7f, |
6756 | | }; |
6757 | | |
6758 | | // R600_KC0_W Register Class... |
6759 | | const MCPhysReg R600_KC0_W[] = { |
6760 | | R600::KC0_128_W, R600::KC0_129_W, R600::KC0_130_W, R600::KC0_131_W, R600::KC0_132_W, R600::KC0_133_W, R600::KC0_134_W, R600::KC0_135_W, R600::KC0_136_W, R600::KC0_137_W, R600::KC0_138_W, R600::KC0_139_W, R600::KC0_140_W, R600::KC0_141_W, R600::KC0_142_W, R600::KC0_143_W, R600::KC0_144_W, R600::KC0_145_W, R600::KC0_146_W, R600::KC0_147_W, R600::KC0_148_W, R600::KC0_149_W, R600::KC0_150_W, R600::KC0_151_W, R600::KC0_152_W, R600::KC0_153_W, R600::KC0_154_W, R600::KC0_155_W, R600::KC0_156_W, R600::KC0_157_W, R600::KC0_158_W, R600::KC0_159_W, |
6761 | | }; |
6762 | | |
6763 | | // R600_KC0_W Bit set. |
6764 | | const uint8_t R600_KC0_WBits[] = { |
6765 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
6766 | | }; |
6767 | | |
6768 | | // R600_KC0_X Register Class... |
6769 | | const MCPhysReg R600_KC0_X[] = { |
6770 | | R600::KC0_128_X, R600::KC0_129_X, R600::KC0_130_X, R600::KC0_131_X, R600::KC0_132_X, R600::KC0_133_X, R600::KC0_134_X, R600::KC0_135_X, R600::KC0_136_X, R600::KC0_137_X, R600::KC0_138_X, R600::KC0_139_X, R600::KC0_140_X, R600::KC0_141_X, R600::KC0_142_X, R600::KC0_143_X, R600::KC0_144_X, R600::KC0_145_X, R600::KC0_146_X, R600::KC0_147_X, R600::KC0_148_X, R600::KC0_149_X, R600::KC0_150_X, R600::KC0_151_X, R600::KC0_152_X, R600::KC0_153_X, R600::KC0_154_X, R600::KC0_155_X, R600::KC0_156_X, R600::KC0_157_X, R600::KC0_158_X, R600::KC0_159_X, |
6771 | | }; |
6772 | | |
6773 | | // R600_KC0_X Bit set. |
6774 | | const uint8_t R600_KC0_XBits[] = { |
6775 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
6776 | | }; |
6777 | | |
6778 | | // R600_KC0_Y Register Class... |
6779 | | const MCPhysReg R600_KC0_Y[] = { |
6780 | | R600::KC0_128_Y, R600::KC0_129_Y, R600::KC0_130_Y, R600::KC0_131_Y, R600::KC0_132_Y, R600::KC0_133_Y, R600::KC0_134_Y, R600::KC0_135_Y, R600::KC0_136_Y, R600::KC0_137_Y, R600::KC0_138_Y, R600::KC0_139_Y, R600::KC0_140_Y, R600::KC0_141_Y, R600::KC0_142_Y, R600::KC0_143_Y, R600::KC0_144_Y, R600::KC0_145_Y, R600::KC0_146_Y, R600::KC0_147_Y, R600::KC0_148_Y, R600::KC0_149_Y, R600::KC0_150_Y, R600::KC0_151_Y, R600::KC0_152_Y, R600::KC0_153_Y, R600::KC0_154_Y, R600::KC0_155_Y, R600::KC0_156_Y, R600::KC0_157_Y, R600::KC0_158_Y, R600::KC0_159_Y, |
6781 | | }; |
6782 | | |
6783 | | // R600_KC0_Y Bit set. |
6784 | | const uint8_t R600_KC0_YBits[] = { |
6785 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
6786 | | }; |
6787 | | |
6788 | | // R600_KC0_Z Register Class... |
6789 | | const MCPhysReg R600_KC0_Z[] = { |
6790 | | R600::KC0_128_Z, R600::KC0_129_Z, R600::KC0_130_Z, R600::KC0_131_Z, R600::KC0_132_Z, R600::KC0_133_Z, R600::KC0_134_Z, R600::KC0_135_Z, R600::KC0_136_Z, R600::KC0_137_Z, R600::KC0_138_Z, R600::KC0_139_Z, R600::KC0_140_Z, R600::KC0_141_Z, R600::KC0_142_Z, R600::KC0_143_Z, R600::KC0_144_Z, R600::KC0_145_Z, R600::KC0_146_Z, R600::KC0_147_Z, R600::KC0_148_Z, R600::KC0_149_Z, R600::KC0_150_Z, R600::KC0_151_Z, R600::KC0_152_Z, R600::KC0_153_Z, R600::KC0_154_Z, R600::KC0_155_Z, R600::KC0_156_Z, R600::KC0_157_Z, R600::KC0_158_Z, R600::KC0_159_Z, |
6791 | | }; |
6792 | | |
6793 | | // R600_KC0_Z Bit set. |
6794 | | const uint8_t R600_KC0_ZBits[] = { |
6795 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
6796 | | }; |
6797 | | |
6798 | | // R600_KC1_W Register Class... |
6799 | | const MCPhysReg R600_KC1_W[] = { |
6800 | | R600::KC1_160_W, R600::KC1_161_W, R600::KC1_162_W, R600::KC1_163_W, R600::KC1_164_W, R600::KC1_165_W, R600::KC1_166_W, R600::KC1_167_W, R600::KC1_168_W, R600::KC1_169_W, R600::KC1_170_W, R600::KC1_171_W, R600::KC1_172_W, R600::KC1_173_W, R600::KC1_174_W, R600::KC1_175_W, R600::KC1_176_W, R600::KC1_177_W, R600::KC1_178_W, R600::KC1_179_W, R600::KC1_180_W, R600::KC1_181_W, R600::KC1_182_W, R600::KC1_183_W, R600::KC1_184_W, R600::KC1_185_W, R600::KC1_186_W, R600::KC1_187_W, R600::KC1_188_W, R600::KC1_189_W, R600::KC1_190_W, R600::KC1_191_W, |
6801 | | }; |
6802 | | |
6803 | | // R600_KC1_W Bit set. |
6804 | | const uint8_t R600_KC1_WBits[] = { |
6805 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
6806 | | }; |
6807 | | |
6808 | | // R600_KC1_X Register Class... |
6809 | | const MCPhysReg R600_KC1_X[] = { |
6810 | | R600::KC1_160_X, R600::KC1_161_X, R600::KC1_162_X, R600::KC1_163_X, R600::KC1_164_X, R600::KC1_165_X, R600::KC1_166_X, R600::KC1_167_X, R600::KC1_168_X, R600::KC1_169_X, R600::KC1_170_X, R600::KC1_171_X, R600::KC1_172_X, R600::KC1_173_X, R600::KC1_174_X, R600::KC1_175_X, R600::KC1_176_X, R600::KC1_177_X, R600::KC1_178_X, R600::KC1_179_X, R600::KC1_180_X, R600::KC1_181_X, R600::KC1_182_X, R600::KC1_183_X, R600::KC1_184_X, R600::KC1_185_X, R600::KC1_186_X, R600::KC1_187_X, R600::KC1_188_X, R600::KC1_189_X, R600::KC1_190_X, R600::KC1_191_X, |
6811 | | }; |
6812 | | |
6813 | | // R600_KC1_X Bit set. |
6814 | | const uint8_t R600_KC1_XBits[] = { |
6815 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
6816 | | }; |
6817 | | |
6818 | | // R600_KC1_Y Register Class... |
6819 | | const MCPhysReg R600_KC1_Y[] = { |
6820 | | R600::KC1_160_Y, R600::KC1_161_Y, R600::KC1_162_Y, R600::KC1_163_Y, R600::KC1_164_Y, R600::KC1_165_Y, R600::KC1_166_Y, R600::KC1_167_Y, R600::KC1_168_Y, R600::KC1_169_Y, R600::KC1_170_Y, R600::KC1_171_Y, R600::KC1_172_Y, R600::KC1_173_Y, R600::KC1_174_Y, R600::KC1_175_Y, R600::KC1_176_Y, R600::KC1_177_Y, R600::KC1_178_Y, R600::KC1_179_Y, R600::KC1_180_Y, R600::KC1_181_Y, R600::KC1_182_Y, R600::KC1_183_Y, R600::KC1_184_Y, R600::KC1_185_Y, R600::KC1_186_Y, R600::KC1_187_Y, R600::KC1_188_Y, R600::KC1_189_Y, R600::KC1_190_Y, R600::KC1_191_Y, |
6821 | | }; |
6822 | | |
6823 | | // R600_KC1_Y Bit set. |
6824 | | const uint8_t R600_KC1_YBits[] = { |
6825 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
6826 | | }; |
6827 | | |
6828 | | // R600_KC1_Z Register Class... |
6829 | | const MCPhysReg R600_KC1_Z[] = { |
6830 | | R600::KC1_160_Z, R600::KC1_161_Z, R600::KC1_162_Z, R600::KC1_163_Z, R600::KC1_164_Z, R600::KC1_165_Z, R600::KC1_166_Z, R600::KC1_167_Z, R600::KC1_168_Z, R600::KC1_169_Z, R600::KC1_170_Z, R600::KC1_171_Z, R600::KC1_172_Z, R600::KC1_173_Z, R600::KC1_174_Z, R600::KC1_175_Z, R600::KC1_176_Z, R600::KC1_177_Z, R600::KC1_178_Z, R600::KC1_179_Z, R600::KC1_180_Z, R600::KC1_181_Z, R600::KC1_182_Z, R600::KC1_183_Z, R600::KC1_184_Z, R600::KC1_185_Z, R600::KC1_186_Z, R600::KC1_187_Z, R600::KC1_188_Z, R600::KC1_189_Z, R600::KC1_190_Z, R600::KC1_191_Z, |
6831 | | }; |
6832 | | |
6833 | | // R600_KC1_Z Bit set. |
6834 | | const uint8_t R600_KC1_ZBits[] = { |
6835 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
6836 | | }; |
6837 | | |
6838 | | // R600_LDS_SRC_REG Register Class... |
6839 | | const MCPhysReg R600_LDS_SRC_REG[] = { |
6840 | | R600::OQA, R600::OQB, R600::OQAP, R600::OQBP, R600::LDS_DIRECT_A, R600::LDS_DIRECT_B, |
6841 | | }; |
6842 | | |
6843 | | // R600_LDS_SRC_REG Bit set. |
6844 | | const uint8_t R600_LDS_SRC_REGBits[] = { |
6845 | | 0x00, 0x0c, 0x0f, |
6846 | | }; |
6847 | | |
6848 | | // R600_Predicate Register Class... |
6849 | | const MCPhysReg R600_Predicate[] = { |
6850 | | R600::PRED_SEL_OFF, R600::PRED_SEL_ZERO, R600::PRED_SEL_ONE, |
6851 | | }; |
6852 | | |
6853 | | // R600_Predicate Bit set. |
6854 | | const uint8_t R600_PredicateBits[] = { |
6855 | | 0x00, 0x00, 0xe0, |
6856 | | }; |
6857 | | |
6858 | | // R600_Addr_W Register Class... |
6859 | | const MCPhysReg R600_Addr_W[] = { |
6860 | | R600::Addr0_W, |
6861 | | }; |
6862 | | |
6863 | | // R600_Addr_W Bit set. |
6864 | | const uint8_t R600_Addr_WBits[] = { |
6865 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, |
6866 | | }; |
6867 | | |
6868 | | // R600_Addr_Y Register Class... |
6869 | | const MCPhysReg R600_Addr_Y[] = { |
6870 | | R600::Addr0_Y, |
6871 | | }; |
6872 | | |
6873 | | // R600_Addr_Y Bit set. |
6874 | | const uint8_t R600_Addr_YBits[] = { |
6875 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, |
6876 | | }; |
6877 | | |
6878 | | // R600_Addr_Z Register Class... |
6879 | | const MCPhysReg R600_Addr_Z[] = { |
6880 | | R600::Addr0_Z, |
6881 | | }; |
6882 | | |
6883 | | // R600_Addr_Z Bit set. |
6884 | | const uint8_t R600_Addr_ZBits[] = { |
6885 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, |
6886 | | }; |
6887 | | |
6888 | | // R600_LDS_SRC_REG_and_R600_Reg32 Register Class... |
6889 | | const MCPhysReg R600_LDS_SRC_REG_and_R600_Reg32[] = { |
6890 | | R600::OQAP, |
6891 | | }; |
6892 | | |
6893 | | // R600_LDS_SRC_REG_and_R600_Reg32 Bit set. |
6894 | | const uint8_t R600_LDS_SRC_REG_and_R600_Reg32Bits[] = { |
6895 | | 0x00, 0x00, 0x02, |
6896 | | }; |
6897 | | |
6898 | | // R600_Predicate_Bit Register Class... |
6899 | | const MCPhysReg R600_Predicate_Bit[] = { |
6900 | | R600::PREDICATE_BIT, |
6901 | | }; |
6902 | | |
6903 | | // R600_Predicate_Bit Bit set. |
6904 | | const uint8_t R600_Predicate_BitBits[] = { |
6905 | | 0x00, 0x00, 0x10, |
6906 | | }; |
6907 | | |
6908 | | // R600_Reg64 Register Class... |
6909 | | const MCPhysReg R600_Reg64[] = { |
6910 | | R600::T0_XY, R600::T1_XY, R600::T2_XY, R600::T3_XY, R600::T4_XY, R600::T5_XY, R600::T6_XY, R600::T7_XY, R600::T8_XY, R600::T9_XY, R600::T10_XY, R600::T11_XY, R600::T12_XY, R600::T13_XY, R600::T14_XY, R600::T15_XY, R600::T16_XY, R600::T17_XY, R600::T18_XY, R600::T19_XY, R600::T20_XY, R600::T21_XY, R600::T22_XY, R600::T23_XY, R600::T24_XY, R600::T25_XY, R600::T26_XY, R600::T27_XY, R600::T28_XY, R600::T29_XY, R600::T30_XY, R600::T31_XY, R600::T32_XY, R600::T33_XY, R600::T34_XY, R600::T35_XY, R600::T36_XY, R600::T37_XY, R600::T38_XY, R600::T39_XY, R600::T40_XY, R600::T41_XY, R600::T42_XY, R600::T43_XY, R600::T44_XY, R600::T45_XY, R600::T46_XY, R600::T47_XY, R600::T48_XY, R600::T49_XY, R600::T50_XY, R600::T51_XY, R600::T52_XY, R600::T53_XY, R600::T54_XY, R600::T55_XY, R600::T56_XY, R600::T57_XY, R600::T58_XY, R600::T59_XY, R600::T60_XY, R600::T61_XY, R600::T62_XY, R600::T63_XY, |
6911 | | }; |
6912 | | |
6913 | | // R600_Reg64 Bit set. |
6914 | | const uint8_t R600_Reg64Bits[] = { |
6915 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, |
6916 | | }; |
6917 | | |
6918 | | // R600_Reg64Vertical Register Class... |
6919 | | const MCPhysReg R600_Reg64Vertical[] = { |
6920 | | R600::V01_X, R600::V01_Y, R600::V01_Z, R600::V01_W, R600::V23_X, R600::V23_Y, R600::V23_Z, R600::V23_W, |
6921 | | }; |
6922 | | |
6923 | | // R600_Reg64Vertical Bit set. |
6924 | | const uint8_t R600_Reg64VerticalBits[] = { |
6925 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x6d, 0x03, |
6926 | | }; |
6927 | | |
6928 | | // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W Register Class... |
6929 | | const MCPhysReg R600_Reg64Vertical_with_sub0_in_R600_TReg32_W[] = { |
6930 | | R600::V01_W, R600::V23_W, |
6931 | | }; |
6932 | | |
6933 | | // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W Bit set. |
6934 | | const uint8_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_WBits[] = { |
6935 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, |
6936 | | }; |
6937 | | |
6938 | | // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X Register Class... |
6939 | | const MCPhysReg R600_Reg64Vertical_with_sub0_in_R600_TReg32_X[] = { |
6940 | | R600::V01_X, R600::V23_X, |
6941 | | }; |
6942 | | |
6943 | | // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X Bit set. |
6944 | | const uint8_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_XBits[] = { |
6945 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, |
6946 | | }; |
6947 | | |
6948 | | // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y Register Class... |
6949 | | const MCPhysReg R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y[] = { |
6950 | | R600::V01_Y, R600::V23_Y, |
6951 | | }; |
6952 | | |
6953 | | // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y Bit set. |
6954 | | const uint8_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_YBits[] = { |
6955 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, |
6956 | | }; |
6957 | | |
6958 | | // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z Register Class... |
6959 | | const MCPhysReg R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z[] = { |
6960 | | R600::V01_Z, R600::V23_Z, |
6961 | | }; |
6962 | | |
6963 | | // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z Bit set. |
6964 | | const uint8_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZBits[] = { |
6965 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, |
6966 | | }; |
6967 | | |
6968 | | // R600_Reg128 Register Class... |
6969 | | const MCPhysReg R600_Reg128[] = { |
6970 | | R600::T0_XYZW, R600::T1_XYZW, R600::T2_XYZW, R600::T3_XYZW, R600::T4_XYZW, R600::T5_XYZW, R600::T6_XYZW, R600::T7_XYZW, R600::T8_XYZW, R600::T9_XYZW, R600::T10_XYZW, R600::T11_XYZW, R600::T12_XYZW, R600::T13_XYZW, R600::T14_XYZW, R600::T15_XYZW, R600::T16_XYZW, R600::T17_XYZW, R600::T18_XYZW, R600::T19_XYZW, R600::T20_XYZW, R600::T21_XYZW, R600::T22_XYZW, R600::T23_XYZW, R600::T24_XYZW, R600::T25_XYZW, R600::T26_XYZW, R600::T27_XYZW, R600::T28_XYZW, R600::T29_XYZW, R600::T30_XYZW, R600::T31_XYZW, R600::T32_XYZW, R600::T33_XYZW, R600::T34_XYZW, R600::T35_XYZW, R600::T36_XYZW, R600::T37_XYZW, R600::T38_XYZW, R600::T39_XYZW, R600::T40_XYZW, R600::T41_XYZW, R600::T42_XYZW, R600::T43_XYZW, R600::T44_XYZW, R600::T45_XYZW, R600::T46_XYZW, R600::T47_XYZW, R600::T48_XYZW, R600::T49_XYZW, R600::T50_XYZW, R600::T51_XYZW, R600::T52_XYZW, R600::T53_XYZW, R600::T54_XYZW, R600::T55_XYZW, R600::T56_XYZW, R600::T57_XYZW, R600::T58_XYZW, R600::T59_XYZW, R600::T60_XYZW, R600::T61_XYZW, R600::T62_XYZW, R600::T63_XYZW, R600::T64_XYZW, R600::T65_XYZW, R600::T66_XYZW, R600::T67_XYZW, R600::T68_XYZW, R600::T69_XYZW, R600::T70_XYZW, R600::T71_XYZW, R600::T72_XYZW, R600::T73_XYZW, R600::T74_XYZW, R600::T75_XYZW, R600::T76_XYZW, R600::T77_XYZW, R600::T78_XYZW, R600::T79_XYZW, R600::T80_XYZW, R600::T81_XYZW, R600::T82_XYZW, R600::T83_XYZW, R600::T84_XYZW, R600::T85_XYZW, R600::T86_XYZW, R600::T87_XYZW, R600::T88_XYZW, R600::T89_XYZW, R600::T90_XYZW, R600::T91_XYZW, R600::T92_XYZW, R600::T93_XYZW, R600::T94_XYZW, R600::T95_XYZW, R600::T96_XYZW, R600::T97_XYZW, R600::T98_XYZW, R600::T99_XYZW, R600::T100_XYZW, R600::T101_XYZW, R600::T102_XYZW, R600::T103_XYZW, R600::T104_XYZW, R600::T105_XYZW, R600::T106_XYZW, R600::T107_XYZW, R600::T108_XYZW, R600::T109_XYZW, R600::T110_XYZW, R600::T111_XYZW, R600::T112_XYZW, R600::T113_XYZW, R600::T114_XYZW, R600::T115_XYZW, R600::T116_XYZW, R600::T117_XYZW, R600::T118_XYZW, R600::T119_XYZW, R600::T120_XYZW, R600::T121_XYZW, R600::T122_XYZW, R600::T123_XYZW, R600::T124_XYZW, R600::T125_XYZW, R600::T126_XYZW, R600::T127_XYZW, |
6971 | | }; |
6972 | | |
6973 | | // R600_Reg128 Bit set. |
6974 | | const uint8_t R600_Reg128Bits[] = { |
6975 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, |
6976 | | }; |
6977 | | |
6978 | | // R600_Reg128Vertical Register Class... |
6979 | | const MCPhysReg R600_Reg128Vertical[] = { |
6980 | | R600::V0123_W, R600::V0123_Z, R600::V0123_Y, R600::V0123_X, |
6981 | | }; |
6982 | | |
6983 | | // R600_Reg128Vertical Bit set. |
6984 | | const uint8_t R600_Reg128VerticalBits[] = { |
6985 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x92, 0x04, |
6986 | | }; |
6987 | | |
6988 | | // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W Register Class... |
6989 | | const MCPhysReg R600_Reg128Vertical_with_sub0_in_R600_TReg32_W[] = { |
6990 | | R600::V0123_W, |
6991 | | }; |
6992 | | |
6993 | | // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W Bit set. |
6994 | | const uint8_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_WBits[] = { |
6995 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, |
6996 | | }; |
6997 | | |
6998 | | // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X Register Class... |
6999 | | const MCPhysReg R600_Reg128Vertical_with_sub0_in_R600_TReg32_X[] = { |
7000 | | R600::V0123_X, |
7001 | | }; |
7002 | | |
7003 | | // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X Bit set. |
7004 | | const uint8_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_XBits[] = { |
7005 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, |
7006 | | }; |
7007 | | |
7008 | | // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y Register Class... |
7009 | | const MCPhysReg R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y[] = { |
7010 | | R600::V0123_Y, |
7011 | | }; |
7012 | | |
7013 | | // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y Bit set. |
7014 | | const uint8_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_YBits[] = { |
7015 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, |
7016 | | }; |
7017 | | |
7018 | | // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z Register Class... |
7019 | | const MCPhysReg R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z[] = { |
7020 | | R600::V0123_Z, |
7021 | | }; |
7022 | | |
7023 | | // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z Bit set. |
7024 | | const uint8_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZBits[] = { |
7025 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, |
7026 | | }; |
7027 | | |
7028 | | } // end anonymous namespace |
7029 | | |
7030 | | |
7031 | | #ifdef __GNUC__ |
7032 | | #pragma GCC diagnostic push |
7033 | | #pragma GCC diagnostic ignored "-Woverlength-strings" |
7034 | | #endif |
7035 | | extern const char R600RegClassStrings[] = { |
7036 | | /* 0 */ "R600_KC0\0" |
7037 | | /* 9 */ "R600_KC1\0" |
7038 | | /* 18 */ "R600_TReg32\0" |
7039 | | /* 30 */ "R600_LDS_SRC_REG_and_R600_Reg32\0" |
7040 | | /* 62 */ "R600_Reg64\0" |
7041 | | /* 73 */ "R600_Reg128\0" |
7042 | | /* 85 */ "R600_LDS_SRC_REG\0" |
7043 | | /* 102 */ "R600_KC0_W\0" |
7044 | | /* 113 */ "R600_KC1_W\0" |
7045 | | /* 124 */ "R600_Reg64Vertical_with_sub0_in_R600_TReg32_W\0" |
7046 | | /* 170 */ "R600_Reg128Vertical_with_sub0_in_R600_TReg32_W\0" |
7047 | | /* 217 */ "R600_Addr_W\0" |
7048 | | /* 229 */ "R600_KC0_X\0" |
7049 | | /* 240 */ "R600_KC1_X\0" |
7050 | | /* 251 */ "R600_Reg64Vertical_with_sub0_in_R600_TReg32_X\0" |
7051 | | /* 297 */ "R600_Reg128Vertical_with_sub0_in_R600_TReg32_X\0" |
7052 | | /* 344 */ "R600_KC0_Y\0" |
7053 | | /* 355 */ "R600_KC1_Y\0" |
7054 | | /* 366 */ "R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y\0" |
7055 | | /* 412 */ "R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y\0" |
7056 | | /* 459 */ "R600_Addr_Y\0" |
7057 | | /* 471 */ "R600_KC0_Z\0" |
7058 | | /* 482 */ "R600_KC1_Z\0" |
7059 | | /* 493 */ "R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z\0" |
7060 | | /* 539 */ "R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z\0" |
7061 | | /* 586 */ "R600_Addr_Z\0" |
7062 | | /* 598 */ "R600_ArrayBase\0" |
7063 | | /* 613 */ "R600_Predicate\0" |
7064 | | /* 628 */ "R600_Reg64Vertical\0" |
7065 | | /* 647 */ "R600_Reg128Vertical\0" |
7066 | | /* 667 */ "R600_Addr\0" |
7067 | | /* 677 */ "R600_Predicate_Bit\0" |
7068 | | }; |
7069 | | #ifdef __GNUC__ |
7070 | | #pragma GCC diagnostic pop |
7071 | | #endif |
7072 | | |
7073 | | extern const MCRegisterClass R600MCRegisterClasses[] = { |
7074 | | { R600_Reg32, R600_Reg32Bits, 51, 942, sizeof(R600_Reg32Bits), R600::R600_Reg32RegClassID, 32, 1, true }, |
7075 | | { R600_TReg32, R600_TReg32Bits, 18, 513, sizeof(R600_TReg32Bits), R600::R600_TReg32RegClassID, 32, 1, true }, |
7076 | | { R600_TReg32_X, R600_TReg32_XBits, 283, 129, sizeof(R600_TReg32_XBits), R600::R600_TReg32_XRegClassID, 32, 1, true }, |
7077 | | { R600_Addr, R600_AddrBits, 667, 128, sizeof(R600_AddrBits), R600::R600_AddrRegClassID, 32, 1, false }, |
7078 | | { R600_KC0, R600_KC0Bits, 0, 128, sizeof(R600_KC0Bits), R600::R600_KC0RegClassID, 32, 1, false }, |
7079 | | { R600_KC1, R600_KC1Bits, 9, 128, sizeof(R600_KC1Bits), R600::R600_KC1RegClassID, 32, 1, false }, |
7080 | | { R600_TReg32_W, R600_TReg32_WBits, 156, 128, sizeof(R600_TReg32_WBits), R600::R600_TReg32_WRegClassID, 32, 1, true }, |
7081 | | { R600_TReg32_Y, R600_TReg32_YBits, 398, 128, sizeof(R600_TReg32_YBits), R600::R600_TReg32_YRegClassID, 32, 1, true }, |
7082 | | { R600_TReg32_Z, R600_TReg32_ZBits, 525, 128, sizeof(R600_TReg32_ZBits), R600::R600_TReg32_ZRegClassID, 32, 1, true }, |
7083 | | { R600_ArrayBase, R600_ArrayBaseBits, 598, 33, sizeof(R600_ArrayBaseBits), R600::R600_ArrayBaseRegClassID, 32, 1, true }, |
7084 | | { R600_KC0_W, R600_KC0_WBits, 102, 32, sizeof(R600_KC0_WBits), R600::R600_KC0_WRegClassID, 32, 1, false }, |
7085 | | { R600_KC0_X, R600_KC0_XBits, 229, 32, sizeof(R600_KC0_XBits), R600::R600_KC0_XRegClassID, 32, 1, false }, |
7086 | | { R600_KC0_Y, R600_KC0_YBits, 344, 32, sizeof(R600_KC0_YBits), R600::R600_KC0_YRegClassID, 32, 1, false }, |
7087 | | { R600_KC0_Z, R600_KC0_ZBits, 471, 32, sizeof(R600_KC0_ZBits), R600::R600_KC0_ZRegClassID, 32, 1, false }, |
7088 | | { R600_KC1_W, R600_KC1_WBits, 113, 32, sizeof(R600_KC1_WBits), R600::R600_KC1_WRegClassID, 32, 1, false }, |
7089 | | { R600_KC1_X, R600_KC1_XBits, 240, 32, sizeof(R600_KC1_XBits), R600::R600_KC1_XRegClassID, 32, 1, false }, |
7090 | | { R600_KC1_Y, R600_KC1_YBits, 355, 32, sizeof(R600_KC1_YBits), R600::R600_KC1_YRegClassID, 32, 1, false }, |
7091 | | { R600_KC1_Z, R600_KC1_ZBits, 482, 32, sizeof(R600_KC1_ZBits), R600::R600_KC1_ZRegClassID, 32, 1, false }, |
7092 | | { R600_LDS_SRC_REG, R600_LDS_SRC_REGBits, 85, 6, sizeof(R600_LDS_SRC_REGBits), R600::R600_LDS_SRC_REGRegClassID, 32, 1, false }, |
7093 | | { R600_Predicate, R600_PredicateBits, 613, 3, sizeof(R600_PredicateBits), R600::R600_PredicateRegClassID, 32, 1, true }, |
7094 | | { R600_Addr_W, R600_Addr_WBits, 217, 1, sizeof(R600_Addr_WBits), R600::R600_Addr_WRegClassID, 32, 1, false }, |
7095 | | { R600_Addr_Y, R600_Addr_YBits, 459, 1, sizeof(R600_Addr_YBits), R600::R600_Addr_YRegClassID, 32, 1, false }, |
7096 | | { R600_Addr_Z, R600_Addr_ZBits, 586, 1, sizeof(R600_Addr_ZBits), R600::R600_Addr_ZRegClassID, 32, 1, false }, |
7097 | | { R600_LDS_SRC_REG_and_R600_Reg32, R600_LDS_SRC_REG_and_R600_Reg32Bits, 30, 1, sizeof(R600_LDS_SRC_REG_and_R600_Reg32Bits), R600::R600_LDS_SRC_REG_and_R600_Reg32RegClassID, 32, 1, true }, |
7098 | | { R600_Predicate_Bit, R600_Predicate_BitBits, 677, 1, sizeof(R600_Predicate_BitBits), R600::R600_Predicate_BitRegClassID, 32, 1, true }, |
7099 | | { R600_Reg64, R600_Reg64Bits, 62, 64, sizeof(R600_Reg64Bits), R600::R600_Reg64RegClassID, 64, 1, true }, |
7100 | | { R600_Reg64Vertical, R600_Reg64VerticalBits, 628, 8, sizeof(R600_Reg64VerticalBits), R600::R600_Reg64VerticalRegClassID, 64, 1, true }, |
7101 | | { R600_Reg64Vertical_with_sub0_in_R600_TReg32_W, R600_Reg64Vertical_with_sub0_in_R600_TReg32_WBits, 124, 2, sizeof(R600_Reg64Vertical_with_sub0_in_R600_TReg32_WBits), R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_WRegClassID, 64, 1, true }, |
7102 | | { R600_Reg64Vertical_with_sub0_in_R600_TReg32_X, R600_Reg64Vertical_with_sub0_in_R600_TReg32_XBits, 251, 2, sizeof(R600_Reg64Vertical_with_sub0_in_R600_TReg32_XBits), R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_XRegClassID, 64, 1, true }, |
7103 | | { R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y, R600_Reg64Vertical_with_sub0_in_R600_TReg32_YBits, 366, 2, sizeof(R600_Reg64Vertical_with_sub0_in_R600_TReg32_YBits), R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_YRegClassID, 64, 1, true }, |
7104 | | { R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z, R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZBits, 493, 2, sizeof(R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZBits), R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZRegClassID, 64, 1, true }, |
7105 | | { R600_Reg128, R600_Reg128Bits, 73, 128, sizeof(R600_Reg128Bits), R600::R600_Reg128RegClassID, 128, -1, true }, |
7106 | | { R600_Reg128Vertical, R600_Reg128VerticalBits, 647, 4, sizeof(R600_Reg128VerticalBits), R600::R600_Reg128VerticalRegClassID, 128, 1, true }, |
7107 | | { R600_Reg128Vertical_with_sub0_in_R600_TReg32_W, R600_Reg128Vertical_with_sub0_in_R600_TReg32_WBits, 170, 1, sizeof(R600_Reg128Vertical_with_sub0_in_R600_TReg32_WBits), R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_WRegClassID, 128, 1, true }, |
7108 | | { R600_Reg128Vertical_with_sub0_in_R600_TReg32_X, R600_Reg128Vertical_with_sub0_in_R600_TReg32_XBits, 297, 1, sizeof(R600_Reg128Vertical_with_sub0_in_R600_TReg32_XBits), R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_XRegClassID, 128, 1, true }, |
7109 | | { R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y, R600_Reg128Vertical_with_sub0_in_R600_TReg32_YBits, 412, 1, sizeof(R600_Reg128Vertical_with_sub0_in_R600_TReg32_YBits), R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_YRegClassID, 128, 1, true }, |
7110 | | { R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z, R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZBits, 539, 1, sizeof(R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZBits), R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZRegClassID, 128, 1, true }, |
7111 | | }; |
7112 | | |
7113 | | extern const uint16_t R600RegEncodingTable[] = { |
7114 | | 0, |
7115 | | 0, |
7116 | | 1789, |
7117 | | 253, |
7118 | | 765, |
7119 | | 1277, |
7120 | | 0, |
7121 | | 0, |
7122 | | 252, |
7123 | | 0, |
7124 | | 223, |
7125 | | 224, |
7126 | | 252, |
7127 | | 249, |
7128 | | 249, |
7129 | | 250, |
7130 | | 219, |
7131 | | 221, |
7132 | | 220, |
7133 | | 222, |
7134 | | 0, |
7135 | | 0, |
7136 | | 3, |
7137 | | 2, |
7138 | | 255, |
7139 | | 1790, |
7140 | | 254, |
7141 | | 766, |
7142 | | 1278, |
7143 | | 248, |
7144 | | 448, |
7145 | | 449, |
7146 | | 450, |
7147 | | 451, |
7148 | | 452, |
7149 | | 453, |
7150 | | 454, |
7151 | | 455, |
7152 | | 456, |
7153 | | 457, |
7154 | | 458, |
7155 | | 459, |
7156 | | 460, |
7157 | | 461, |
7158 | | 462, |
7159 | | 463, |
7160 | | 464, |
7161 | | 465, |
7162 | | 466, |
7163 | | 467, |
7164 | | 468, |
7165 | | 469, |
7166 | | 470, |
7167 | | 471, |
7168 | | 472, |
7169 | | 473, |
7170 | | 474, |
7171 | | 475, |
7172 | | 476, |
7173 | | 477, |
7174 | | 478, |
7175 | | 479, |
7176 | | 480, |
7177 | | 1536, |
7178 | | 1537, |
7179 | | 1538, |
7180 | | 1539, |
7181 | | 1540, |
7182 | | 1541, |
7183 | | 1542, |
7184 | | 1543, |
7185 | | 1544, |
7186 | | 1545, |
7187 | | 1546, |
7188 | | 1547, |
7189 | | 1548, |
7190 | | 1549, |
7191 | | 1550, |
7192 | | 1551, |
7193 | | 1552, |
7194 | | 1553, |
7195 | | 1554, |
7196 | | 1555, |
7197 | | 1556, |
7198 | | 1557, |
7199 | | 1558, |
7200 | | 1559, |
7201 | | 1560, |
7202 | | 1561, |
7203 | | 1562, |
7204 | | 1563, |
7205 | | 1564, |
7206 | | 1565, |
7207 | | 1566, |
7208 | | 1567, |
7209 | | 1568, |
7210 | | 1569, |
7211 | | 1570, |
7212 | | 1571, |
7213 | | 1572, |
7214 | | 1573, |
7215 | | 1574, |
7216 | | 1575, |
7217 | | 1576, |
7218 | | 1577, |
7219 | | 1578, |
7220 | | 1579, |
7221 | | 1580, |
7222 | | 1581, |
7223 | | 1582, |
7224 | | 1583, |
7225 | | 1584, |
7226 | | 1585, |
7227 | | 1586, |
7228 | | 1587, |
7229 | | 1588, |
7230 | | 1589, |
7231 | | 1590, |
7232 | | 1591, |
7233 | | 1592, |
7234 | | 1593, |
7235 | | 1594, |
7236 | | 1595, |
7237 | | 1596, |
7238 | | 1597, |
7239 | | 1598, |
7240 | | 1599, |
7241 | | 1600, |
7242 | | 1601, |
7243 | | 1602, |
7244 | | 1603, |
7245 | | 1604, |
7246 | | 1605, |
7247 | | 1606, |
7248 | | 1607, |
7249 | | 1608, |
7250 | | 1609, |
7251 | | 1610, |
7252 | | 1611, |
7253 | | 1612, |
7254 | | 1613, |
7255 | | 1614, |
7256 | | 1615, |
7257 | | 1616, |
7258 | | 1617, |
7259 | | 1618, |
7260 | | 1619, |
7261 | | 1620, |
7262 | | 1621, |
7263 | | 1622, |
7264 | | 1623, |
7265 | | 1624, |
7266 | | 1625, |
7267 | | 1626, |
7268 | | 1627, |
7269 | | 1628, |
7270 | | 1629, |
7271 | | 1630, |
7272 | | 1631, |
7273 | | 1632, |
7274 | | 1633, |
7275 | | 1634, |
7276 | | 1635, |
7277 | | 1636, |
7278 | | 1637, |
7279 | | 1638, |
7280 | | 1639, |
7281 | | 1640, |
7282 | | 1641, |
7283 | | 1642, |
7284 | | 1643, |
7285 | | 1644, |
7286 | | 1645, |
7287 | | 1646, |
7288 | | 1647, |
7289 | | 1648, |
7290 | | 1649, |
7291 | | 1650, |
7292 | | 1651, |
7293 | | 1652, |
7294 | | 1653, |
7295 | | 1654, |
7296 | | 1655, |
7297 | | 1656, |
7298 | | 1657, |
7299 | | 1658, |
7300 | | 1659, |
7301 | | 1660, |
7302 | | 1661, |
7303 | | 1662, |
7304 | | 1663, |
7305 | | 0, |
7306 | | 1, |
7307 | | 2, |
7308 | | 3, |
7309 | | 4, |
7310 | | 5, |
7311 | | 6, |
7312 | | 7, |
7313 | | 8, |
7314 | | 9, |
7315 | | 10, |
7316 | | 11, |
7317 | | 12, |
7318 | | 13, |
7319 | | 14, |
7320 | | 15, |
7321 | | 16, |
7322 | | 17, |
7323 | | 18, |
7324 | | 19, |
7325 | | 20, |
7326 | | 21, |
7327 | | 22, |
7328 | | 23, |
7329 | | 24, |
7330 | | 25, |
7331 | | 26, |
7332 | | 27, |
7333 | | 28, |
7334 | | 29, |
7335 | | 30, |
7336 | | 31, |
7337 | | 32, |
7338 | | 33, |
7339 | | 34, |
7340 | | 35, |
7341 | | 36, |
7342 | | 37, |
7343 | | 38, |
7344 | | 39, |
7345 | | 40, |
7346 | | 41, |
7347 | | 42, |
7348 | | 43, |
7349 | | 44, |
7350 | | 45, |
7351 | | 46, |
7352 | | 47, |
7353 | | 48, |
7354 | | 49, |
7355 | | 50, |
7356 | | 51, |
7357 | | 52, |
7358 | | 53, |
7359 | | 54, |
7360 | | 55, |
7361 | | 56, |
7362 | | 57, |
7363 | | 58, |
7364 | | 59, |
7365 | | 60, |
7366 | | 61, |
7367 | | 62, |
7368 | | 63, |
7369 | | 64, |
7370 | | 65, |
7371 | | 66, |
7372 | | 67, |
7373 | | 68, |
7374 | | 69, |
7375 | | 70, |
7376 | | 71, |
7377 | | 72, |
7378 | | 73, |
7379 | | 74, |
7380 | | 75, |
7381 | | 76, |
7382 | | 77, |
7383 | | 78, |
7384 | | 79, |
7385 | | 80, |
7386 | | 81, |
7387 | | 82, |
7388 | | 83, |
7389 | | 84, |
7390 | | 85, |
7391 | | 86, |
7392 | | 87, |
7393 | | 88, |
7394 | | 89, |
7395 | | 90, |
7396 | | 91, |
7397 | | 92, |
7398 | | 93, |
7399 | | 94, |
7400 | | 95, |
7401 | | 96, |
7402 | | 97, |
7403 | | 98, |
7404 | | 99, |
7405 | | 100, |
7406 | | 101, |
7407 | | 102, |
7408 | | 103, |
7409 | | 104, |
7410 | | 105, |
7411 | | 106, |
7412 | | 107, |
7413 | | 108, |
7414 | | 109, |
7415 | | 110, |
7416 | | 111, |
7417 | | 112, |
7418 | | 113, |
7419 | | 114, |
7420 | | 115, |
7421 | | 116, |
7422 | | 117, |
7423 | | 118, |
7424 | | 119, |
7425 | | 120, |
7426 | | 121, |
7427 | | 122, |
7428 | | 123, |
7429 | | 124, |
7430 | | 125, |
7431 | | 126, |
7432 | | 127, |
7433 | | 512, |
7434 | | 513, |
7435 | | 514, |
7436 | | 515, |
7437 | | 516, |
7438 | | 517, |
7439 | | 518, |
7440 | | 519, |
7441 | | 520, |
7442 | | 521, |
7443 | | 522, |
7444 | | 523, |
7445 | | 524, |
7446 | | 525, |
7447 | | 526, |
7448 | | 527, |
7449 | | 528, |
7450 | | 529, |
7451 | | 530, |
7452 | | 531, |
7453 | | 532, |
7454 | | 533, |
7455 | | 534, |
7456 | | 535, |
7457 | | 536, |
7458 | | 537, |
7459 | | 538, |
7460 | | 539, |
7461 | | 540, |
7462 | | 541, |
7463 | | 542, |
7464 | | 543, |
7465 | | 544, |
7466 | | 545, |
7467 | | 546, |
7468 | | 547, |
7469 | | 548, |
7470 | | 549, |
7471 | | 550, |
7472 | | 551, |
7473 | | 552, |
7474 | | 553, |
7475 | | 554, |
7476 | | 555, |
7477 | | 556, |
7478 | | 557, |
7479 | | 558, |
7480 | | 559, |
7481 | | 560, |
7482 | | 561, |
7483 | | 562, |
7484 | | 563, |
7485 | | 564, |
7486 | | 565, |
7487 | | 566, |
7488 | | 567, |
7489 | | 568, |
7490 | | 569, |
7491 | | 570, |
7492 | | 571, |
7493 | | 572, |
7494 | | 573, |
7495 | | 574, |
7496 | | 575, |
7497 | | 576, |
7498 | | 577, |
7499 | | 578, |
7500 | | 579, |
7501 | | 580, |
7502 | | 581, |
7503 | | 582, |
7504 | | 583, |
7505 | | 584, |
7506 | | 585, |
7507 | | 586, |
7508 | | 587, |
7509 | | 588, |
7510 | | 589, |
7511 | | 590, |
7512 | | 591, |
7513 | | 592, |
7514 | | 593, |
7515 | | 594, |
7516 | | 595, |
7517 | | 596, |
7518 | | 597, |
7519 | | 598, |
7520 | | 599, |
7521 | | 600, |
7522 | | 601, |
7523 | | 602, |
7524 | | 603, |
7525 | | 604, |
7526 | | 605, |
7527 | | 606, |
7528 | | 607, |
7529 | | 608, |
7530 | | 609, |
7531 | | 610, |
7532 | | 611, |
7533 | | 612, |
7534 | | 613, |
7535 | | 614, |
7536 | | 615, |
7537 | | 616, |
7538 | | 617, |
7539 | | 618, |
7540 | | 619, |
7541 | | 620, |
7542 | | 621, |
7543 | | 622, |
7544 | | 623, |
7545 | | 624, |
7546 | | 625, |
7547 | | 626, |
7548 | | 627, |
7549 | | 628, |
7550 | | 629, |
7551 | | 630, |
7552 | | 631, |
7553 | | 632, |
7554 | | 633, |
7555 | | 634, |
7556 | | 635, |
7557 | | 636, |
7558 | | 637, |
7559 | | 638, |
7560 | | 639, |
7561 | | 1024, |
7562 | | 1025, |
7563 | | 1026, |
7564 | | 1027, |
7565 | | 1028, |
7566 | | 1029, |
7567 | | 1030, |
7568 | | 1031, |
7569 | | 1032, |
7570 | | 1033, |
7571 | | 1034, |
7572 | | 1035, |
7573 | | 1036, |
7574 | | 1037, |
7575 | | 1038, |
7576 | | 1039, |
7577 | | 1040, |
7578 | | 1041, |
7579 | | 1042, |
7580 | | 1043, |
7581 | | 1044, |
7582 | | 1045, |
7583 | | 1046, |
7584 | | 1047, |
7585 | | 1048, |
7586 | | 1049, |
7587 | | 1050, |
7588 | | 1051, |
7589 | | 1052, |
7590 | | 1053, |
7591 | | 1054, |
7592 | | 1055, |
7593 | | 1056, |
7594 | | 1057, |
7595 | | 1058, |
7596 | | 1059, |
7597 | | 1060, |
7598 | | 1061, |
7599 | | 1062, |
7600 | | 1063, |
7601 | | 1064, |
7602 | | 1065, |
7603 | | 1066, |
7604 | | 1067, |
7605 | | 1068, |
7606 | | 1069, |
7607 | | 1070, |
7608 | | 1071, |
7609 | | 1072, |
7610 | | 1073, |
7611 | | 1074, |
7612 | | 1075, |
7613 | | 1076, |
7614 | | 1077, |
7615 | | 1078, |
7616 | | 1079, |
7617 | | 1080, |
7618 | | 1081, |
7619 | | 1082, |
7620 | | 1083, |
7621 | | 1084, |
7622 | | 1085, |
7623 | | 1086, |
7624 | | 1087, |
7625 | | 1088, |
7626 | | 1089, |
7627 | | 1090, |
7628 | | 1091, |
7629 | | 1092, |
7630 | | 1093, |
7631 | | 1094, |
7632 | | 1095, |
7633 | | 1096, |
7634 | | 1097, |
7635 | | 1098, |
7636 | | 1099, |
7637 | | 1100, |
7638 | | 1101, |
7639 | | 1102, |
7640 | | 1103, |
7641 | | 1104, |
7642 | | 1105, |
7643 | | 1106, |
7644 | | 1107, |
7645 | | 1108, |
7646 | | 1109, |
7647 | | 1110, |
7648 | | 1111, |
7649 | | 1112, |
7650 | | 1113, |
7651 | | 1114, |
7652 | | 1115, |
7653 | | 1116, |
7654 | | 1117, |
7655 | | 1118, |
7656 | | 1119, |
7657 | | 1120, |
7658 | | 1121, |
7659 | | 1122, |
7660 | | 1123, |
7661 | | 1124, |
7662 | | 1125, |
7663 | | 1126, |
7664 | | 1127, |
7665 | | 1128, |
7666 | | 1129, |
7667 | | 1130, |
7668 | | 1131, |
7669 | | 1132, |
7670 | | 1133, |
7671 | | 1134, |
7672 | | 1135, |
7673 | | 1136, |
7674 | | 1137, |
7675 | | 1138, |
7676 | | 1139, |
7677 | | 1140, |
7678 | | 1141, |
7679 | | 1142, |
7680 | | 1143, |
7681 | | 1144, |
7682 | | 1145, |
7683 | | 1146, |
7684 | | 1147, |
7685 | | 1148, |
7686 | | 1149, |
7687 | | 1150, |
7688 | | 1151, |
7689 | | 1536, |
7690 | | 1537, |
7691 | | 1538, |
7692 | | 1539, |
7693 | | 1540, |
7694 | | 1541, |
7695 | | 1542, |
7696 | | 1543, |
7697 | | 1544, |
7698 | | 1545, |
7699 | | 1546, |
7700 | | 1547, |
7701 | | 1548, |
7702 | | 1549, |
7703 | | 1550, |
7704 | | 1551, |
7705 | | 1552, |
7706 | | 1553, |
7707 | | 1554, |
7708 | | 1555, |
7709 | | 1556, |
7710 | | 1557, |
7711 | | 1558, |
7712 | | 1559, |
7713 | | 1560, |
7714 | | 1561, |
7715 | | 1562, |
7716 | | 1563, |
7717 | | 1564, |
7718 | | 1565, |
7719 | | 1566, |
7720 | | 1567, |
7721 | | 1568, |
7722 | | 1569, |
7723 | | 1570, |
7724 | | 1571, |
7725 | | 1572, |
7726 | | 1573, |
7727 | | 1574, |
7728 | | 1575, |
7729 | | 1576, |
7730 | | 1577, |
7731 | | 1578, |
7732 | | 1579, |
7733 | | 1580, |
7734 | | 1581, |
7735 | | 1582, |
7736 | | 1583, |
7737 | | 1584, |
7738 | | 1585, |
7739 | | 1586, |
7740 | | 1587, |
7741 | | 1588, |
7742 | | 1589, |
7743 | | 1590, |
7744 | | 1591, |
7745 | | 1592, |
7746 | | 1593, |
7747 | | 1594, |
7748 | | 1595, |
7749 | | 1596, |
7750 | | 1597, |
7751 | | 1598, |
7752 | | 1599, |
7753 | | 1600, |
7754 | | 1601, |
7755 | | 1602, |
7756 | | 1603, |
7757 | | 1604, |
7758 | | 1605, |
7759 | | 1606, |
7760 | | 1607, |
7761 | | 1608, |
7762 | | 1609, |
7763 | | 1610, |
7764 | | 1611, |
7765 | | 1612, |
7766 | | 1613, |
7767 | | 1614, |
7768 | | 1615, |
7769 | | 1616, |
7770 | | 1617, |
7771 | | 1618, |
7772 | | 1619, |
7773 | | 1620, |
7774 | | 1621, |
7775 | | 1622, |
7776 | | 1623, |
7777 | | 1624, |
7778 | | 1625, |
7779 | | 1626, |
7780 | | 1627, |
7781 | | 1628, |
7782 | | 1629, |
7783 | | 1630, |
7784 | | 1631, |
7785 | | 1632, |
7786 | | 1633, |
7787 | | 1634, |
7788 | | 1635, |
7789 | | 1636, |
7790 | | 1637, |
7791 | | 1638, |
7792 | | 1639, |
7793 | | 1640, |
7794 | | 1641, |
7795 | | 1642, |
7796 | | 1643, |
7797 | | 1644, |
7798 | | 1645, |
7799 | | 1646, |
7800 | | 1647, |
7801 | | 1648, |
7802 | | 1649, |
7803 | | 1650, |
7804 | | 1651, |
7805 | | 1652, |
7806 | | 1653, |
7807 | | 1654, |
7808 | | 1655, |
7809 | | 1656, |
7810 | | 1657, |
7811 | | 1658, |
7812 | | 1659, |
7813 | | 1660, |
7814 | | 1661, |
7815 | | 1662, |
7816 | | 1663, |
7817 | | 0, |
7818 | | 1, |
7819 | | 2, |
7820 | | 3, |
7821 | | 4, |
7822 | | 5, |
7823 | | 6, |
7824 | | 7, |
7825 | | 8, |
7826 | | 9, |
7827 | | 10, |
7828 | | 11, |
7829 | | 12, |
7830 | | 13, |
7831 | | 14, |
7832 | | 15, |
7833 | | 16, |
7834 | | 17, |
7835 | | 18, |
7836 | | 19, |
7837 | | 20, |
7838 | | 21, |
7839 | | 22, |
7840 | | 23, |
7841 | | 24, |
7842 | | 25, |
7843 | | 26, |
7844 | | 27, |
7845 | | 28, |
7846 | | 29, |
7847 | | 30, |
7848 | | 31, |
7849 | | 32, |
7850 | | 33, |
7851 | | 34, |
7852 | | 35, |
7853 | | 36, |
7854 | | 37, |
7855 | | 38, |
7856 | | 39, |
7857 | | 40, |
7858 | | 41, |
7859 | | 42, |
7860 | | 43, |
7861 | | 44, |
7862 | | 45, |
7863 | | 46, |
7864 | | 47, |
7865 | | 48, |
7866 | | 49, |
7867 | | 50, |
7868 | | 51, |
7869 | | 52, |
7870 | | 53, |
7871 | | 54, |
7872 | | 55, |
7873 | | 56, |
7874 | | 57, |
7875 | | 58, |
7876 | | 59, |
7877 | | 60, |
7878 | | 61, |
7879 | | 62, |
7880 | | 63, |
7881 | | 64, |
7882 | | 65, |
7883 | | 66, |
7884 | | 67, |
7885 | | 68, |
7886 | | 69, |
7887 | | 70, |
7888 | | 71, |
7889 | | 72, |
7890 | | 73, |
7891 | | 74, |
7892 | | 75, |
7893 | | 76, |
7894 | | 77, |
7895 | | 78, |
7896 | | 79, |
7897 | | 80, |
7898 | | 81, |
7899 | | 82, |
7900 | | 83, |
7901 | | 84, |
7902 | | 85, |
7903 | | 86, |
7904 | | 87, |
7905 | | 88, |
7906 | | 89, |
7907 | | 90, |
7908 | | 91, |
7909 | | 92, |
7910 | | 93, |
7911 | | 94, |
7912 | | 95, |
7913 | | 96, |
7914 | | 97, |
7915 | | 98, |
7916 | | 99, |
7917 | | 100, |
7918 | | 101, |
7919 | | 102, |
7920 | | 103, |
7921 | | 104, |
7922 | | 105, |
7923 | | 106, |
7924 | | 107, |
7925 | | 108, |
7926 | | 109, |
7927 | | 110, |
7928 | | 111, |
7929 | | 112, |
7930 | | 113, |
7931 | | 114, |
7932 | | 115, |
7933 | | 116, |
7934 | | 117, |
7935 | | 118, |
7936 | | 119, |
7937 | | 120, |
7938 | | 121, |
7939 | | 122, |
7940 | | 123, |
7941 | | 124, |
7942 | | 125, |
7943 | | 126, |
7944 | | 127, |
7945 | | 0, |
7946 | | 1, |
7947 | | 2, |
7948 | | 3, |
7949 | | 4, |
7950 | | 5, |
7951 | | 6, |
7952 | | 7, |
7953 | | 8, |
7954 | | 9, |
7955 | | 10, |
7956 | | 11, |
7957 | | 12, |
7958 | | 13, |
7959 | | 14, |
7960 | | 15, |
7961 | | 16, |
7962 | | 17, |
7963 | | 18, |
7964 | | 19, |
7965 | | 20, |
7966 | | 21, |
7967 | | 22, |
7968 | | 23, |
7969 | | 24, |
7970 | | 25, |
7971 | | 26, |
7972 | | 27, |
7973 | | 28, |
7974 | | 29, |
7975 | | 30, |
7976 | | 31, |
7977 | | 32, |
7978 | | 33, |
7979 | | 34, |
7980 | | 35, |
7981 | | 36, |
7982 | | 37, |
7983 | | 38, |
7984 | | 39, |
7985 | | 40, |
7986 | | 41, |
7987 | | 42, |
7988 | | 43, |
7989 | | 44, |
7990 | | 45, |
7991 | | 46, |
7992 | | 47, |
7993 | | 48, |
7994 | | 49, |
7995 | | 50, |
7996 | | 51, |
7997 | | 52, |
7998 | | 53, |
7999 | | 54, |
8000 | | 55, |
8001 | | 56, |
8002 | | 57, |
8003 | | 58, |
8004 | | 59, |
8005 | | 60, |
8006 | | 61, |
8007 | | 62, |
8008 | | 63, |
8009 | | 64, |
8010 | | 65, |
8011 | | 66, |
8012 | | 67, |
8013 | | 68, |
8014 | | 69, |
8015 | | 70, |
8016 | | 71, |
8017 | | 72, |
8018 | | 73, |
8019 | | 74, |
8020 | | 75, |
8021 | | 76, |
8022 | | 77, |
8023 | | 78, |
8024 | | 79, |
8025 | | 80, |
8026 | | 81, |
8027 | | 82, |
8028 | | 83, |
8029 | | 84, |
8030 | | 85, |
8031 | | 86, |
8032 | | 87, |
8033 | | 88, |
8034 | | 89, |
8035 | | 90, |
8036 | | 91, |
8037 | | 92, |
8038 | | 93, |
8039 | | 94, |
8040 | | 95, |
8041 | | 96, |
8042 | | 97, |
8043 | | 98, |
8044 | | 99, |
8045 | | 100, |
8046 | | 101, |
8047 | | 102, |
8048 | | 103, |
8049 | | 104, |
8050 | | 105, |
8051 | | 106, |
8052 | | 107, |
8053 | | 108, |
8054 | | 109, |
8055 | | 110, |
8056 | | 111, |
8057 | | 112, |
8058 | | 113, |
8059 | | 114, |
8060 | | 115, |
8061 | | 116, |
8062 | | 117, |
8063 | | 118, |
8064 | | 119, |
8065 | | 120, |
8066 | | 121, |
8067 | | 122, |
8068 | | 123, |
8069 | | 124, |
8070 | | 125, |
8071 | | 126, |
8072 | | 127, |
8073 | | 0, |
8074 | | 1, |
8075 | | 2, |
8076 | | 3, |
8077 | | 4, |
8078 | | 5, |
8079 | | 6, |
8080 | | 7, |
8081 | | 8, |
8082 | | 9, |
8083 | | 10, |
8084 | | 11, |
8085 | | 12, |
8086 | | 13, |
8087 | | 14, |
8088 | | 15, |
8089 | | 16, |
8090 | | 17, |
8091 | | 18, |
8092 | | 19, |
8093 | | 20, |
8094 | | 21, |
8095 | | 22, |
8096 | | 23, |
8097 | | 24, |
8098 | | 25, |
8099 | | 26, |
8100 | | 27, |
8101 | | 28, |
8102 | | 29, |
8103 | | 30, |
8104 | | 31, |
8105 | | 32, |
8106 | | 33, |
8107 | | 34, |
8108 | | 35, |
8109 | | 36, |
8110 | | 37, |
8111 | | 38, |
8112 | | 39, |
8113 | | 40, |
8114 | | 41, |
8115 | | 42, |
8116 | | 43, |
8117 | | 44, |
8118 | | 45, |
8119 | | 46, |
8120 | | 47, |
8121 | | 48, |
8122 | | 49, |
8123 | | 50, |
8124 | | 51, |
8125 | | 52, |
8126 | | 53, |
8127 | | 54, |
8128 | | 55, |
8129 | | 56, |
8130 | | 57, |
8131 | | 58, |
8132 | | 59, |
8133 | | 60, |
8134 | | 61, |
8135 | | 62, |
8136 | | 63, |
8137 | | 64, |
8138 | | 65, |
8139 | | 66, |
8140 | | 67, |
8141 | | 68, |
8142 | | 69, |
8143 | | 70, |
8144 | | 71, |
8145 | | 72, |
8146 | | 73, |
8147 | | 74, |
8148 | | 75, |
8149 | | 76, |
8150 | | 77, |
8151 | | 78, |
8152 | | 79, |
8153 | | 80, |
8154 | | 81, |
8155 | | 82, |
8156 | | 83, |
8157 | | 84, |
8158 | | 85, |
8159 | | 86, |
8160 | | 87, |
8161 | | 88, |
8162 | | 89, |
8163 | | 90, |
8164 | | 91, |
8165 | | 92, |
8166 | | 93, |
8167 | | 94, |
8168 | | 95, |
8169 | | 96, |
8170 | | 97, |
8171 | | 98, |
8172 | | 99, |
8173 | | 100, |
8174 | | 101, |
8175 | | 102, |
8176 | | 103, |
8177 | | 104, |
8178 | | 105, |
8179 | | 106, |
8180 | | 107, |
8181 | | 108, |
8182 | | 109, |
8183 | | 110, |
8184 | | 111, |
8185 | | 112, |
8186 | | 113, |
8187 | | 114, |
8188 | | 115, |
8189 | | 116, |
8190 | | 117, |
8191 | | 118, |
8192 | | 119, |
8193 | | 120, |
8194 | | 121, |
8195 | | 122, |
8196 | | 123, |
8197 | | 124, |
8198 | | 125, |
8199 | | 126, |
8200 | | 127, |
8201 | | 512, |
8202 | | 513, |
8203 | | 514, |
8204 | | 515, |
8205 | | 516, |
8206 | | 517, |
8207 | | 518, |
8208 | | 519, |
8209 | | 520, |
8210 | | 521, |
8211 | | 522, |
8212 | | 523, |
8213 | | 524, |
8214 | | 525, |
8215 | | 526, |
8216 | | 527, |
8217 | | 528, |
8218 | | 529, |
8219 | | 530, |
8220 | | 531, |
8221 | | 532, |
8222 | | 533, |
8223 | | 534, |
8224 | | 535, |
8225 | | 536, |
8226 | | 537, |
8227 | | 538, |
8228 | | 539, |
8229 | | 540, |
8230 | | 541, |
8231 | | 542, |
8232 | | 543, |
8233 | | 544, |
8234 | | 545, |
8235 | | 546, |
8236 | | 547, |
8237 | | 548, |
8238 | | 549, |
8239 | | 550, |
8240 | | 551, |
8241 | | 552, |
8242 | | 553, |
8243 | | 554, |
8244 | | 555, |
8245 | | 556, |
8246 | | 557, |
8247 | | 558, |
8248 | | 559, |
8249 | | 560, |
8250 | | 561, |
8251 | | 562, |
8252 | | 563, |
8253 | | 564, |
8254 | | 565, |
8255 | | 566, |
8256 | | 567, |
8257 | | 568, |
8258 | | 569, |
8259 | | 570, |
8260 | | 571, |
8261 | | 572, |
8262 | | 573, |
8263 | | 574, |
8264 | | 575, |
8265 | | 576, |
8266 | | 577, |
8267 | | 578, |
8268 | | 579, |
8269 | | 580, |
8270 | | 581, |
8271 | | 582, |
8272 | | 583, |
8273 | | 584, |
8274 | | 585, |
8275 | | 586, |
8276 | | 587, |
8277 | | 588, |
8278 | | 589, |
8279 | | 590, |
8280 | | 591, |
8281 | | 592, |
8282 | | 593, |
8283 | | 594, |
8284 | | 595, |
8285 | | 596, |
8286 | | 597, |
8287 | | 598, |
8288 | | 599, |
8289 | | 600, |
8290 | | 601, |
8291 | | 602, |
8292 | | 603, |
8293 | | 604, |
8294 | | 605, |
8295 | | 606, |
8296 | | 607, |
8297 | | 608, |
8298 | | 609, |
8299 | | 610, |
8300 | | 611, |
8301 | | 612, |
8302 | | 613, |
8303 | | 614, |
8304 | | 615, |
8305 | | 616, |
8306 | | 617, |
8307 | | 618, |
8308 | | 619, |
8309 | | 620, |
8310 | | 621, |
8311 | | 622, |
8312 | | 623, |
8313 | | 624, |
8314 | | 625, |
8315 | | 626, |
8316 | | 627, |
8317 | | 628, |
8318 | | 629, |
8319 | | 630, |
8320 | | 631, |
8321 | | 632, |
8322 | | 633, |
8323 | | 634, |
8324 | | 635, |
8325 | | 636, |
8326 | | 637, |
8327 | | 638, |
8328 | | 639, |
8329 | | 1024, |
8330 | | 1025, |
8331 | | 1026, |
8332 | | 1027, |
8333 | | 1028, |
8334 | | 1029, |
8335 | | 1030, |
8336 | | 1031, |
8337 | | 1032, |
8338 | | 1033, |
8339 | | 1034, |
8340 | | 1035, |
8341 | | 1036, |
8342 | | 1037, |
8343 | | 1038, |
8344 | | 1039, |
8345 | | 1040, |
8346 | | 1041, |
8347 | | 1042, |
8348 | | 1043, |
8349 | | 1044, |
8350 | | 1045, |
8351 | | 1046, |
8352 | | 1047, |
8353 | | 1048, |
8354 | | 1049, |
8355 | | 1050, |
8356 | | 1051, |
8357 | | 1052, |
8358 | | 1053, |
8359 | | 1054, |
8360 | | 1055, |
8361 | | 1056, |
8362 | | 1057, |
8363 | | 1058, |
8364 | | 1059, |
8365 | | 1060, |
8366 | | 1061, |
8367 | | 1062, |
8368 | | 1063, |
8369 | | 1064, |
8370 | | 1065, |
8371 | | 1066, |
8372 | | 1067, |
8373 | | 1068, |
8374 | | 1069, |
8375 | | 1070, |
8376 | | 1071, |
8377 | | 1072, |
8378 | | 1073, |
8379 | | 1074, |
8380 | | 1075, |
8381 | | 1076, |
8382 | | 1077, |
8383 | | 1078, |
8384 | | 1079, |
8385 | | 1080, |
8386 | | 1081, |
8387 | | 1082, |
8388 | | 1083, |
8389 | | 1084, |
8390 | | 1085, |
8391 | | 1086, |
8392 | | 1087, |
8393 | | 1088, |
8394 | | 1089, |
8395 | | 1090, |
8396 | | 1091, |
8397 | | 1092, |
8398 | | 1093, |
8399 | | 1094, |
8400 | | 1095, |
8401 | | 1096, |
8402 | | 1097, |
8403 | | 1098, |
8404 | | 1099, |
8405 | | 1100, |
8406 | | 1101, |
8407 | | 1102, |
8408 | | 1103, |
8409 | | 1104, |
8410 | | 1105, |
8411 | | 1106, |
8412 | | 1107, |
8413 | | 1108, |
8414 | | 1109, |
8415 | | 1110, |
8416 | | 1111, |
8417 | | 1112, |
8418 | | 1113, |
8419 | | 1114, |
8420 | | 1115, |
8421 | | 1116, |
8422 | | 1117, |
8423 | | 1118, |
8424 | | 1119, |
8425 | | 1120, |
8426 | | 1121, |
8427 | | 1122, |
8428 | | 1123, |
8429 | | 1124, |
8430 | | 1125, |
8431 | | 1126, |
8432 | | 1127, |
8433 | | 1128, |
8434 | | 1129, |
8435 | | 1130, |
8436 | | 1131, |
8437 | | 1132, |
8438 | | 1133, |
8439 | | 1134, |
8440 | | 1135, |
8441 | | 1136, |
8442 | | 1137, |
8443 | | 1138, |
8444 | | 1139, |
8445 | | 1140, |
8446 | | 1141, |
8447 | | 1142, |
8448 | | 1143, |
8449 | | 1144, |
8450 | | 1145, |
8451 | | 1146, |
8452 | | 1147, |
8453 | | 1148, |
8454 | | 1149, |
8455 | | 1150, |
8456 | | 1151, |
8457 | | 1536, |
8458 | | 1538, |
8459 | | 1536, |
8460 | | 0, |
8461 | | 2, |
8462 | | 0, |
8463 | | 512, |
8464 | | 514, |
8465 | | 512, |
8466 | | 1024, |
8467 | | 1026, |
8468 | | 1024, |
8469 | | 1664, |
8470 | | 1665, |
8471 | | 1666, |
8472 | | 1667, |
8473 | | 1668, |
8474 | | 1669, |
8475 | | 1670, |
8476 | | 1671, |
8477 | | 1672, |
8478 | | 1673, |
8479 | | 1674, |
8480 | | 1675, |
8481 | | 1676, |
8482 | | 1677, |
8483 | | 1678, |
8484 | | 1679, |
8485 | | 1680, |
8486 | | 1681, |
8487 | | 1682, |
8488 | | 1683, |
8489 | | 1684, |
8490 | | 1685, |
8491 | | 1686, |
8492 | | 1687, |
8493 | | 1688, |
8494 | | 1689, |
8495 | | 1690, |
8496 | | 1691, |
8497 | | 1692, |
8498 | | 1693, |
8499 | | 1694, |
8500 | | 1695, |
8501 | | 1696, |
8502 | | 1697, |
8503 | | 1698, |
8504 | | 1699, |
8505 | | 1700, |
8506 | | 1701, |
8507 | | 1702, |
8508 | | 1703, |
8509 | | 1704, |
8510 | | 1705, |
8511 | | 1706, |
8512 | | 1707, |
8513 | | 1708, |
8514 | | 1709, |
8515 | | 1710, |
8516 | | 1711, |
8517 | | 1712, |
8518 | | 1713, |
8519 | | 1714, |
8520 | | 1715, |
8521 | | 1716, |
8522 | | 1717, |
8523 | | 1718, |
8524 | | 1719, |
8525 | | 1720, |
8526 | | 1721, |
8527 | | 1722, |
8528 | | 1723, |
8529 | | 1724, |
8530 | | 1725, |
8531 | | 1726, |
8532 | | 1727, |
8533 | | 128, |
8534 | | 129, |
8535 | | 130, |
8536 | | 131, |
8537 | | 132, |
8538 | | 133, |
8539 | | 134, |
8540 | | 135, |
8541 | | 136, |
8542 | | 137, |
8543 | | 138, |
8544 | | 139, |
8545 | | 140, |
8546 | | 141, |
8547 | | 142, |
8548 | | 143, |
8549 | | 144, |
8550 | | 145, |
8551 | | 146, |
8552 | | 147, |
8553 | | 148, |
8554 | | 149, |
8555 | | 150, |
8556 | | 151, |
8557 | | 152, |
8558 | | 153, |
8559 | | 154, |
8560 | | 155, |
8561 | | 156, |
8562 | | 157, |
8563 | | 158, |
8564 | | 159, |
8565 | | 160, |
8566 | | 161, |
8567 | | 162, |
8568 | | 163, |
8569 | | 164, |
8570 | | 165, |
8571 | | 166, |
8572 | | 167, |
8573 | | 168, |
8574 | | 169, |
8575 | | 170, |
8576 | | 171, |
8577 | | 172, |
8578 | | 173, |
8579 | | 174, |
8580 | | 175, |
8581 | | 176, |
8582 | | 177, |
8583 | | 178, |
8584 | | 179, |
8585 | | 180, |
8586 | | 181, |
8587 | | 182, |
8588 | | 183, |
8589 | | 184, |
8590 | | 185, |
8591 | | 186, |
8592 | | 187, |
8593 | | 188, |
8594 | | 189, |
8595 | | 190, |
8596 | | 191, |
8597 | | 128, |
8598 | | 129, |
8599 | | 130, |
8600 | | 131, |
8601 | | 132, |
8602 | | 133, |
8603 | | 134, |
8604 | | 135, |
8605 | | 136, |
8606 | | 137, |
8607 | | 138, |
8608 | | 139, |
8609 | | 140, |
8610 | | 141, |
8611 | | 142, |
8612 | | 143, |
8613 | | 144, |
8614 | | 145, |
8615 | | 146, |
8616 | | 147, |
8617 | | 148, |
8618 | | 149, |
8619 | | 150, |
8620 | | 151, |
8621 | | 152, |
8622 | | 153, |
8623 | | 154, |
8624 | | 155, |
8625 | | 156, |
8626 | | 157, |
8627 | | 158, |
8628 | | 159, |
8629 | | 160, |
8630 | | 161, |
8631 | | 162, |
8632 | | 163, |
8633 | | 164, |
8634 | | 165, |
8635 | | 166, |
8636 | | 167, |
8637 | | 168, |
8638 | | 169, |
8639 | | 170, |
8640 | | 171, |
8641 | | 172, |
8642 | | 173, |
8643 | | 174, |
8644 | | 175, |
8645 | | 176, |
8646 | | 177, |
8647 | | 178, |
8648 | | 179, |
8649 | | 180, |
8650 | | 181, |
8651 | | 182, |
8652 | | 183, |
8653 | | 184, |
8654 | | 185, |
8655 | | 186, |
8656 | | 187, |
8657 | | 188, |
8658 | | 189, |
8659 | | 190, |
8660 | | 191, |
8661 | | 640, |
8662 | | 641, |
8663 | | 642, |
8664 | | 643, |
8665 | | 644, |
8666 | | 645, |
8667 | | 646, |
8668 | | 647, |
8669 | | 648, |
8670 | | 649, |
8671 | | 650, |
8672 | | 651, |
8673 | | 652, |
8674 | | 653, |
8675 | | 654, |
8676 | | 655, |
8677 | | 656, |
8678 | | 657, |
8679 | | 658, |
8680 | | 659, |
8681 | | 660, |
8682 | | 661, |
8683 | | 662, |
8684 | | 663, |
8685 | | 664, |
8686 | | 665, |
8687 | | 666, |
8688 | | 667, |
8689 | | 668, |
8690 | | 669, |
8691 | | 670, |
8692 | | 671, |
8693 | | 672, |
8694 | | 673, |
8695 | | 674, |
8696 | | 675, |
8697 | | 676, |
8698 | | 677, |
8699 | | 678, |
8700 | | 679, |
8701 | | 680, |
8702 | | 681, |
8703 | | 682, |
8704 | | 683, |
8705 | | 684, |
8706 | | 685, |
8707 | | 686, |
8708 | | 687, |
8709 | | 688, |
8710 | | 689, |
8711 | | 690, |
8712 | | 691, |
8713 | | 692, |
8714 | | 693, |
8715 | | 694, |
8716 | | 695, |
8717 | | 696, |
8718 | | 697, |
8719 | | 698, |
8720 | | 699, |
8721 | | 700, |
8722 | | 701, |
8723 | | 702, |
8724 | | 703, |
8725 | | 1152, |
8726 | | 1153, |
8727 | | 1154, |
8728 | | 1155, |
8729 | | 1156, |
8730 | | 1157, |
8731 | | 1158, |
8732 | | 1159, |
8733 | | 1160, |
8734 | | 1161, |
8735 | | 1162, |
8736 | | 1163, |
8737 | | 1164, |
8738 | | 1165, |
8739 | | 1166, |
8740 | | 1167, |
8741 | | 1168, |
8742 | | 1169, |
8743 | | 1170, |
8744 | | 1171, |
8745 | | 1172, |
8746 | | 1173, |
8747 | | 1174, |
8748 | | 1175, |
8749 | | 1176, |
8750 | | 1177, |
8751 | | 1178, |
8752 | | 1179, |
8753 | | 1180, |
8754 | | 1181, |
8755 | | 1182, |
8756 | | 1183, |
8757 | | 1184, |
8758 | | 1185, |
8759 | | 1186, |
8760 | | 1187, |
8761 | | 1188, |
8762 | | 1189, |
8763 | | 1190, |
8764 | | 1191, |
8765 | | 1192, |
8766 | | 1193, |
8767 | | 1194, |
8768 | | 1195, |
8769 | | 1196, |
8770 | | 1197, |
8771 | | 1198, |
8772 | | 1199, |
8773 | | 1200, |
8774 | | 1201, |
8775 | | 1202, |
8776 | | 1203, |
8777 | | 1204, |
8778 | | 1205, |
8779 | | 1206, |
8780 | | 1207, |
8781 | | 1208, |
8782 | | 1209, |
8783 | | 1210, |
8784 | | 1211, |
8785 | | 1212, |
8786 | | 1213, |
8787 | | 1214, |
8788 | | 1215, |
8789 | | }; |
8790 | 0 | static inline void InitR600MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) { |
8791 | 0 | RI->InitMCRegisterInfo(R600RegDesc, 1675, RA, PC, R600MCRegisterClasses, 37, R600RegUnitRoots, 1342, R600RegDiffLists, R600LaneMaskLists, R600RegStrings, R600RegClassStrings, R600SubRegIdxLists, 17, |
8792 | 0 | R600SubRegIdxRanges, R600RegEncodingTable); |
8793 | |
|
8794 | 0 | } |
8795 | | |
8796 | | } // end namespace llvm |
8797 | | |
8798 | | #endif // GET_REGINFO_MC_DESC |
8799 | | |
8800 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
8801 | | |* *| |
8802 | | |* Register Information Header Fragment *| |
8803 | | |* *| |
8804 | | |* Automatically generated file, do not edit! *| |
8805 | | |* *| |
8806 | | \*===----------------------------------------------------------------------===*/ |
8807 | | |
8808 | | |
8809 | | #ifdef GET_REGINFO_HEADER |
8810 | | #undef GET_REGINFO_HEADER |
8811 | | |
8812 | | #include "llvm/CodeGen/TargetRegisterInfo.h" |
8813 | | |
8814 | | namespace llvm { |
8815 | | |
8816 | | class R600FrameLowering; |
8817 | | |
8818 | | struct R600GenRegisterInfo : public TargetRegisterInfo { |
8819 | | explicit R600GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0, |
8820 | | unsigned PC = 0, unsigned HwMode = 0); |
8821 | | unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override; |
8822 | | LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; |
8823 | | LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; |
8824 | | const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override; |
8825 | | const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override; |
8826 | | const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override; |
8827 | | unsigned getRegUnitWeight(unsigned RegUnit) const override; |
8828 | | unsigned getNumRegPressureSets() const override; |
8829 | | const char *getRegPressureSetName(unsigned Idx) const override; |
8830 | | unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override; |
8831 | | const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override; |
8832 | | const int *getRegUnitPressureSets(unsigned RegUnit) const override; |
8833 | | ArrayRef<const char *> getRegMaskNames() const override; |
8834 | | ArrayRef<const uint32_t *> getRegMasks() const override; |
8835 | | bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override; |
8836 | | bool isFixedRegister(const MachineFunction &, MCRegister) const override; |
8837 | | bool isArgumentRegister(const MachineFunction &, MCRegister) const override; |
8838 | | bool isConstantPhysReg(MCRegister PhysReg) const override final; |
8839 | | /// Devirtualized TargetFrameLowering. |
8840 | | static const R600FrameLowering *getFrameLowering( |
8841 | | const MachineFunction &MF); |
8842 | | }; |
8843 | | |
8844 | | namespace R600 { // Register classes |
8845 | | extern const TargetRegisterClass R600_Reg32RegClass; |
8846 | | extern const TargetRegisterClass R600_TReg32RegClass; |
8847 | | extern const TargetRegisterClass R600_TReg32_XRegClass; |
8848 | | extern const TargetRegisterClass R600_AddrRegClass; |
8849 | | extern const TargetRegisterClass R600_KC0RegClass; |
8850 | | extern const TargetRegisterClass R600_KC1RegClass; |
8851 | | extern const TargetRegisterClass R600_TReg32_WRegClass; |
8852 | | extern const TargetRegisterClass R600_TReg32_YRegClass; |
8853 | | extern const TargetRegisterClass R600_TReg32_ZRegClass; |
8854 | | extern const TargetRegisterClass R600_ArrayBaseRegClass; |
8855 | | extern const TargetRegisterClass R600_KC0_WRegClass; |
8856 | | extern const TargetRegisterClass R600_KC0_XRegClass; |
8857 | | extern const TargetRegisterClass R600_KC0_YRegClass; |
8858 | | extern const TargetRegisterClass R600_KC0_ZRegClass; |
8859 | | extern const TargetRegisterClass R600_KC1_WRegClass; |
8860 | | extern const TargetRegisterClass R600_KC1_XRegClass; |
8861 | | extern const TargetRegisterClass R600_KC1_YRegClass; |
8862 | | extern const TargetRegisterClass R600_KC1_ZRegClass; |
8863 | | extern const TargetRegisterClass R600_LDS_SRC_REGRegClass; |
8864 | | extern const TargetRegisterClass R600_PredicateRegClass; |
8865 | | extern const TargetRegisterClass R600_Addr_WRegClass; |
8866 | | extern const TargetRegisterClass R600_Addr_YRegClass; |
8867 | | extern const TargetRegisterClass R600_Addr_ZRegClass; |
8868 | | extern const TargetRegisterClass R600_LDS_SRC_REG_and_R600_Reg32RegClass; |
8869 | | extern const TargetRegisterClass R600_Predicate_BitRegClass; |
8870 | | extern const TargetRegisterClass R600_Reg64RegClass; |
8871 | | extern const TargetRegisterClass R600_Reg64VerticalRegClass; |
8872 | | extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_WRegClass; |
8873 | | extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_XRegClass; |
8874 | | extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_YRegClass; |
8875 | | extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZRegClass; |
8876 | | extern const TargetRegisterClass R600_Reg128RegClass; |
8877 | | extern const TargetRegisterClass R600_Reg128VerticalRegClass; |
8878 | | extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_WRegClass; |
8879 | | extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_XRegClass; |
8880 | | extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_YRegClass; |
8881 | | extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZRegClass; |
8882 | | } // end namespace R600 |
8883 | | |
8884 | | } // end namespace llvm |
8885 | | |
8886 | | #endif // GET_REGINFO_HEADER |
8887 | | |
8888 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
8889 | | |* *| |
8890 | | |* Target Register and Register Classes Information *| |
8891 | | |* *| |
8892 | | |* Automatically generated file, do not edit! *| |
8893 | | |* *| |
8894 | | \*===----------------------------------------------------------------------===*/ |
8895 | | |
8896 | | |
8897 | | #ifdef GET_REGINFO_TARGET_DESC |
8898 | | #undef GET_REGINFO_TARGET_DESC |
8899 | | |
8900 | | namespace llvm { |
8901 | | |
8902 | | extern const MCRegisterClass R600MCRegisterClasses[]; |
8903 | | |
8904 | | static const MVT::SimpleValueType VTLists[] = { |
8905 | | /* 0 */ MVT::f32, MVT::i32, MVT::Other, |
8906 | | /* 3 */ MVT::v2f32, MVT::v2i32, MVT::i64, MVT::f64, MVT::Other, |
8907 | | /* 8 */ MVT::v2f32, MVT::v2i32, MVT::Other, |
8908 | | /* 11 */ MVT::v4f32, MVT::v4i32, MVT::Other, |
8909 | | }; |
8910 | | |
8911 | | static const char *SubRegIndexNameTable[] = { "sub0", "sub1", "sub2", "sub3", "sub4", "sub5", "sub6", "sub7", "sub8", "sub9", "sub10", "sub11", "sub12", "sub13", "sub14", "sub15", "" }; |
8912 | | |
8913 | | |
8914 | | static const LaneBitmask SubRegIndexLaneMaskTable[] = { |
8915 | | LaneBitmask::getAll(), |
8916 | | LaneBitmask(0x0000000000000001), // sub0 |
8917 | | LaneBitmask(0x0000000000000002), // sub1 |
8918 | | LaneBitmask(0x0000000000000004), // sub2 |
8919 | | LaneBitmask(0x0000000000000008), // sub3 |
8920 | | LaneBitmask(0x0000000000000010), // sub4 |
8921 | | LaneBitmask(0x0000000000000020), // sub5 |
8922 | | LaneBitmask(0x0000000000000040), // sub6 |
8923 | | LaneBitmask(0x0000000000000080), // sub7 |
8924 | | LaneBitmask(0x0000000000000100), // sub8 |
8925 | | LaneBitmask(0x0000000000000200), // sub9 |
8926 | | LaneBitmask(0x0000000000000400), // sub10 |
8927 | | LaneBitmask(0x0000000000000800), // sub11 |
8928 | | LaneBitmask(0x0000000000001000), // sub12 |
8929 | | LaneBitmask(0x0000000000002000), // sub13 |
8930 | | LaneBitmask(0x0000000000004000), // sub14 |
8931 | | LaneBitmask(0x0000000000008000), // sub15 |
8932 | | }; |
8933 | | |
8934 | | |
8935 | | |
8936 | | static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = { |
8937 | | // Mode = 0 (Default) |
8938 | | { 32, 32, 32, /*VTLists+*/0 }, // R600_Reg32 |
8939 | | { 32, 32, 32, /*VTLists+*/0 }, // R600_TReg32 |
8940 | | { 32, 32, 32, /*VTLists+*/0 }, // R600_TReg32_X |
8941 | | { 32, 32, 32, /*VTLists+*/1 }, // R600_Addr |
8942 | | { 32, 32, 32, /*VTLists+*/0 }, // R600_KC0 |
8943 | | { 32, 32, 32, /*VTLists+*/0 }, // R600_KC1 |
8944 | | { 32, 32, 32, /*VTLists+*/0 }, // R600_TReg32_W |
8945 | | { 32, 32, 32, /*VTLists+*/0 }, // R600_TReg32_Y |
8946 | | { 32, 32, 32, /*VTLists+*/0 }, // R600_TReg32_Z |
8947 | | { 32, 32, 32, /*VTLists+*/0 }, // R600_ArrayBase |
8948 | | { 32, 32, 32, /*VTLists+*/0 }, // R600_KC0_W |
8949 | | { 32, 32, 32, /*VTLists+*/0 }, // R600_KC0_X |
8950 | | { 32, 32, 32, /*VTLists+*/0 }, // R600_KC0_Y |
8951 | | { 32, 32, 32, /*VTLists+*/0 }, // R600_KC0_Z |
8952 | | { 32, 32, 32, /*VTLists+*/0 }, // R600_KC1_W |
8953 | | { 32, 32, 32, /*VTLists+*/0 }, // R600_KC1_X |
8954 | | { 32, 32, 32, /*VTLists+*/0 }, // R600_KC1_Y |
8955 | | { 32, 32, 32, /*VTLists+*/0 }, // R600_KC1_Z |
8956 | | { 32, 32, 32, /*VTLists+*/1 }, // R600_LDS_SRC_REG |
8957 | | { 32, 32, 32, /*VTLists+*/1 }, // R600_Predicate |
8958 | | { 32, 32, 32, /*VTLists+*/1 }, // R600_Addr_W |
8959 | | { 32, 32, 32, /*VTLists+*/1 }, // R600_Addr_Y |
8960 | | { 32, 32, 32, /*VTLists+*/1 }, // R600_Addr_Z |
8961 | | { 32, 32, 32, /*VTLists+*/1 }, // R600_LDS_SRC_REG_and_R600_Reg32 |
8962 | | { 32, 32, 32, /*VTLists+*/1 }, // R600_Predicate_Bit |
8963 | | { 64, 64, 64, /*VTLists+*/3 }, // R600_Reg64 |
8964 | | { 64, 64, 64, /*VTLists+*/8 }, // R600_Reg64Vertical |
8965 | | { 64, 64, 64, /*VTLists+*/8 }, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W |
8966 | | { 64, 64, 64, /*VTLists+*/8 }, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X |
8967 | | { 64, 64, 64, /*VTLists+*/8 }, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y |
8968 | | { 64, 64, 64, /*VTLists+*/8 }, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z |
8969 | | { 128, 128, 128, /*VTLists+*/11 }, // R600_Reg128 |
8970 | | { 128, 128, 128, /*VTLists+*/11 }, // R600_Reg128Vertical |
8971 | | { 128, 128, 128, /*VTLists+*/11 }, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W |
8972 | | { 128, 128, 128, /*VTLists+*/11 }, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X |
8973 | | { 128, 128, 128, /*VTLists+*/11 }, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y |
8974 | | { 128, 128, 128, /*VTLists+*/11 }, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z |
8975 | | }; |
8976 | | |
8977 | | static const TargetRegisterClass *const NullRegClasses[] = { nullptr }; |
8978 | | |
8979 | | static const uint32_t R600_Reg32SubClassMask[] = { |
8980 | | 0x0083ffff, 0x00000000, |
8981 | | 0xfe000000, 0x0000001f, // sub0 |
8982 | | 0xfe000000, 0x0000001f, // sub1 |
8983 | | 0x80000000, 0x0000001f, // sub2 |
8984 | | 0x80000000, 0x0000001f, // sub3 |
8985 | | }; |
8986 | | |
8987 | | static const uint32_t R600_TReg32SubClassMask[] = { |
8988 | | 0x000001c6, 0x00000000, |
8989 | | 0xfe000000, 0x0000001f, // sub0 |
8990 | | 0xfe000000, 0x0000001f, // sub1 |
8991 | | 0x80000000, 0x0000001f, // sub2 |
8992 | | 0x80000000, 0x0000001f, // sub3 |
8993 | | }; |
8994 | | |
8995 | | static const uint32_t R600_TReg32_XSubClassMask[] = { |
8996 | | 0x00000004, 0x00000000, |
8997 | | 0x92000000, 0x00000004, // sub0 |
8998 | | 0x10000000, 0x00000004, // sub1 |
8999 | | 0x00000000, 0x00000004, // sub2 |
9000 | | 0x00000000, 0x00000004, // sub3 |
9001 | | }; |
9002 | | |
9003 | | static const uint32_t R600_AddrSubClassMask[] = { |
9004 | | 0x00000008, 0x00000000, |
9005 | | }; |
9006 | | |
9007 | | static const uint32_t R600_KC0SubClassMask[] = { |
9008 | | 0x00003c10, 0x00000000, |
9009 | | }; |
9010 | | |
9011 | | static const uint32_t R600_KC1SubClassMask[] = { |
9012 | | 0x0003c020, 0x00000000, |
9013 | | }; |
9014 | | |
9015 | | static const uint32_t R600_TReg32_WSubClassMask[] = { |
9016 | | 0x00000040, 0x00000000, |
9017 | | 0x08000000, 0x00000002, // sub0 |
9018 | | 0x08000000, 0x00000002, // sub1 |
9019 | | 0x00000000, 0x00000002, // sub2 |
9020 | | 0x80000000, 0x00000002, // sub3 |
9021 | | }; |
9022 | | |
9023 | | static const uint32_t R600_TReg32_YSubClassMask[] = { |
9024 | | 0x00000080, 0x00000000, |
9025 | | 0x20000000, 0x00000008, // sub0 |
9026 | | 0xa2000000, 0x00000008, // sub1 |
9027 | | 0x00000000, 0x00000008, // sub2 |
9028 | | 0x00000000, 0x00000008, // sub3 |
9029 | | }; |
9030 | | |
9031 | | static const uint32_t R600_TReg32_ZSubClassMask[] = { |
9032 | | 0x00000100, 0x00000000, |
9033 | | 0x40000000, 0x00000010, // sub0 |
9034 | | 0x40000000, 0x00000010, // sub1 |
9035 | | 0x80000000, 0x00000010, // sub2 |
9036 | | 0x00000000, 0x00000010, // sub3 |
9037 | | }; |
9038 | | |
9039 | | static const uint32_t R600_ArrayBaseSubClassMask[] = { |
9040 | | 0x00000200, 0x00000000, |
9041 | | }; |
9042 | | |
9043 | | static const uint32_t R600_KC0_WSubClassMask[] = { |
9044 | | 0x00000400, 0x00000000, |
9045 | | }; |
9046 | | |
9047 | | static const uint32_t R600_KC0_XSubClassMask[] = { |
9048 | | 0x00000800, 0x00000000, |
9049 | | }; |
9050 | | |
9051 | | static const uint32_t R600_KC0_YSubClassMask[] = { |
9052 | | 0x00001000, 0x00000000, |
9053 | | }; |
9054 | | |
9055 | | static const uint32_t R600_KC0_ZSubClassMask[] = { |
9056 | | 0x00002000, 0x00000000, |
9057 | | }; |
9058 | | |
9059 | | static const uint32_t R600_KC1_WSubClassMask[] = { |
9060 | | 0x00004000, 0x00000000, |
9061 | | }; |
9062 | | |
9063 | | static const uint32_t R600_KC1_XSubClassMask[] = { |
9064 | | 0x00008000, 0x00000000, |
9065 | | }; |
9066 | | |
9067 | | static const uint32_t R600_KC1_YSubClassMask[] = { |
9068 | | 0x00010000, 0x00000000, |
9069 | | }; |
9070 | | |
9071 | | static const uint32_t R600_KC1_ZSubClassMask[] = { |
9072 | | 0x00020000, 0x00000000, |
9073 | | }; |
9074 | | |
9075 | | static const uint32_t R600_LDS_SRC_REGSubClassMask[] = { |
9076 | | 0x00840000, 0x00000000, |
9077 | | }; |
9078 | | |
9079 | | static const uint32_t R600_PredicateSubClassMask[] = { |
9080 | | 0x00080000, 0x00000000, |
9081 | | }; |
9082 | | |
9083 | | static const uint32_t R600_Addr_WSubClassMask[] = { |
9084 | | 0x00100000, 0x00000000, |
9085 | | }; |
9086 | | |
9087 | | static const uint32_t R600_Addr_YSubClassMask[] = { |
9088 | | 0x00200000, 0x00000000, |
9089 | | }; |
9090 | | |
9091 | | static const uint32_t R600_Addr_ZSubClassMask[] = { |
9092 | | 0x00400000, 0x00000000, |
9093 | | }; |
9094 | | |
9095 | | static const uint32_t R600_LDS_SRC_REG_and_R600_Reg32SubClassMask[] = { |
9096 | | 0x00800000, 0x00000000, |
9097 | | }; |
9098 | | |
9099 | | static const uint32_t R600_Predicate_BitSubClassMask[] = { |
9100 | | 0x01000000, 0x00000000, |
9101 | | }; |
9102 | | |
9103 | | static const uint32_t R600_Reg64SubClassMask[] = { |
9104 | | 0x02000000, 0x00000000, |
9105 | | }; |
9106 | | |
9107 | | static const uint32_t R600_Reg64VerticalSubClassMask[] = { |
9108 | | 0x7c000000, 0x00000000, |
9109 | | }; |
9110 | | |
9111 | | static const uint32_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_WSubClassMask[] = { |
9112 | | 0x08000000, 0x00000000, |
9113 | | }; |
9114 | | |
9115 | | static const uint32_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_XSubClassMask[] = { |
9116 | | 0x10000000, 0x00000000, |
9117 | | }; |
9118 | | |
9119 | | static const uint32_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_YSubClassMask[] = { |
9120 | | 0x20000000, 0x00000000, |
9121 | | }; |
9122 | | |
9123 | | static const uint32_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZSubClassMask[] = { |
9124 | | 0x40000000, 0x00000000, |
9125 | | }; |
9126 | | |
9127 | | static const uint32_t R600_Reg128SubClassMask[] = { |
9128 | | 0x80000000, 0x00000000, |
9129 | | }; |
9130 | | |
9131 | | static const uint32_t R600_Reg128VerticalSubClassMask[] = { |
9132 | | 0x00000000, 0x0000001f, |
9133 | | }; |
9134 | | |
9135 | | static const uint32_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_WSubClassMask[] = { |
9136 | | 0x00000000, 0x00000002, |
9137 | | }; |
9138 | | |
9139 | | static const uint32_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_XSubClassMask[] = { |
9140 | | 0x00000000, 0x00000004, |
9141 | | }; |
9142 | | |
9143 | | static const uint32_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_YSubClassMask[] = { |
9144 | | 0x00000000, 0x00000008, |
9145 | | }; |
9146 | | |
9147 | | static const uint32_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZSubClassMask[] = { |
9148 | | 0x00000000, 0x00000010, |
9149 | | }; |
9150 | | |
9151 | | static const uint16_t SuperRegIdxSeqs[] = { |
9152 | | /* 0 */ 1, 2, 3, 4, 0, |
9153 | | }; |
9154 | | |
9155 | | static const TargetRegisterClass *const R600_TReg32Superclasses[] = { |
9156 | | &R600::R600_Reg32RegClass, |
9157 | | nullptr |
9158 | | }; |
9159 | | |
9160 | | static const TargetRegisterClass *const R600_TReg32_XSuperclasses[] = { |
9161 | | &R600::R600_Reg32RegClass, |
9162 | | &R600::R600_TReg32RegClass, |
9163 | | nullptr |
9164 | | }; |
9165 | | |
9166 | | static const TargetRegisterClass *const R600_AddrSuperclasses[] = { |
9167 | | &R600::R600_Reg32RegClass, |
9168 | | nullptr |
9169 | | }; |
9170 | | |
9171 | | static const TargetRegisterClass *const R600_KC0Superclasses[] = { |
9172 | | &R600::R600_Reg32RegClass, |
9173 | | nullptr |
9174 | | }; |
9175 | | |
9176 | | static const TargetRegisterClass *const R600_KC1Superclasses[] = { |
9177 | | &R600::R600_Reg32RegClass, |
9178 | | nullptr |
9179 | | }; |
9180 | | |
9181 | | static const TargetRegisterClass *const R600_TReg32_WSuperclasses[] = { |
9182 | | &R600::R600_Reg32RegClass, |
9183 | | &R600::R600_TReg32RegClass, |
9184 | | nullptr |
9185 | | }; |
9186 | | |
9187 | | static const TargetRegisterClass *const R600_TReg32_YSuperclasses[] = { |
9188 | | &R600::R600_Reg32RegClass, |
9189 | | &R600::R600_TReg32RegClass, |
9190 | | nullptr |
9191 | | }; |
9192 | | |
9193 | | static const TargetRegisterClass *const R600_TReg32_ZSuperclasses[] = { |
9194 | | &R600::R600_Reg32RegClass, |
9195 | | &R600::R600_TReg32RegClass, |
9196 | | nullptr |
9197 | | }; |
9198 | | |
9199 | | static const TargetRegisterClass *const R600_ArrayBaseSuperclasses[] = { |
9200 | | &R600::R600_Reg32RegClass, |
9201 | | nullptr |
9202 | | }; |
9203 | | |
9204 | | static const TargetRegisterClass *const R600_KC0_WSuperclasses[] = { |
9205 | | &R600::R600_Reg32RegClass, |
9206 | | &R600::R600_KC0RegClass, |
9207 | | nullptr |
9208 | | }; |
9209 | | |
9210 | | static const TargetRegisterClass *const R600_KC0_XSuperclasses[] = { |
9211 | | &R600::R600_Reg32RegClass, |
9212 | | &R600::R600_KC0RegClass, |
9213 | | nullptr |
9214 | | }; |
9215 | | |
9216 | | static const TargetRegisterClass *const R600_KC0_YSuperclasses[] = { |
9217 | | &R600::R600_Reg32RegClass, |
9218 | | &R600::R600_KC0RegClass, |
9219 | | nullptr |
9220 | | }; |
9221 | | |
9222 | | static const TargetRegisterClass *const R600_KC0_ZSuperclasses[] = { |
9223 | | &R600::R600_Reg32RegClass, |
9224 | | &R600::R600_KC0RegClass, |
9225 | | nullptr |
9226 | | }; |
9227 | | |
9228 | | static const TargetRegisterClass *const R600_KC1_WSuperclasses[] = { |
9229 | | &R600::R600_Reg32RegClass, |
9230 | | &R600::R600_KC1RegClass, |
9231 | | nullptr |
9232 | | }; |
9233 | | |
9234 | | static const TargetRegisterClass *const R600_KC1_XSuperclasses[] = { |
9235 | | &R600::R600_Reg32RegClass, |
9236 | | &R600::R600_KC1RegClass, |
9237 | | nullptr |
9238 | | }; |
9239 | | |
9240 | | static const TargetRegisterClass *const R600_KC1_YSuperclasses[] = { |
9241 | | &R600::R600_Reg32RegClass, |
9242 | | &R600::R600_KC1RegClass, |
9243 | | nullptr |
9244 | | }; |
9245 | | |
9246 | | static const TargetRegisterClass *const R600_KC1_ZSuperclasses[] = { |
9247 | | &R600::R600_Reg32RegClass, |
9248 | | &R600::R600_KC1RegClass, |
9249 | | nullptr |
9250 | | }; |
9251 | | |
9252 | | static const TargetRegisterClass *const R600_LDS_SRC_REG_and_R600_Reg32Superclasses[] = { |
9253 | | &R600::R600_Reg32RegClass, |
9254 | | &R600::R600_LDS_SRC_REGRegClass, |
9255 | | nullptr |
9256 | | }; |
9257 | | |
9258 | | static const TargetRegisterClass *const R600_Reg64Vertical_with_sub0_in_R600_TReg32_WSuperclasses[] = { |
9259 | | &R600::R600_Reg64VerticalRegClass, |
9260 | | nullptr |
9261 | | }; |
9262 | | |
9263 | | static const TargetRegisterClass *const R600_Reg64Vertical_with_sub0_in_R600_TReg32_XSuperclasses[] = { |
9264 | | &R600::R600_Reg64VerticalRegClass, |
9265 | | nullptr |
9266 | | }; |
9267 | | |
9268 | | static const TargetRegisterClass *const R600_Reg64Vertical_with_sub0_in_R600_TReg32_YSuperclasses[] = { |
9269 | | &R600::R600_Reg64VerticalRegClass, |
9270 | | nullptr |
9271 | | }; |
9272 | | |
9273 | | static const TargetRegisterClass *const R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZSuperclasses[] = { |
9274 | | &R600::R600_Reg64VerticalRegClass, |
9275 | | nullptr |
9276 | | }; |
9277 | | |
9278 | | static const TargetRegisterClass *const R600_Reg128Vertical_with_sub0_in_R600_TReg32_WSuperclasses[] = { |
9279 | | &R600::R600_Reg128VerticalRegClass, |
9280 | | nullptr |
9281 | | }; |
9282 | | |
9283 | | static const TargetRegisterClass *const R600_Reg128Vertical_with_sub0_in_R600_TReg32_XSuperclasses[] = { |
9284 | | &R600::R600_Reg128VerticalRegClass, |
9285 | | nullptr |
9286 | | }; |
9287 | | |
9288 | | static const TargetRegisterClass *const R600_Reg128Vertical_with_sub0_in_R600_TReg32_YSuperclasses[] = { |
9289 | | &R600::R600_Reg128VerticalRegClass, |
9290 | | nullptr |
9291 | | }; |
9292 | | |
9293 | | static const TargetRegisterClass *const R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZSuperclasses[] = { |
9294 | | &R600::R600_Reg128VerticalRegClass, |
9295 | | nullptr |
9296 | | }; |
9297 | | |
9298 | | |
9299 | | namespace R600 { // Register class instances |
9300 | | extern const TargetRegisterClass R600_Reg32RegClass = { |
9301 | | &R600MCRegisterClasses[R600_Reg32RegClassID], |
9302 | | R600_Reg32SubClassMask, |
9303 | | SuperRegIdxSeqs + 0, |
9304 | | LaneBitmask(0x0000000000000001), |
9305 | | 0, |
9306 | | false, |
9307 | | 0x00, /* TSFlags */ |
9308 | | false, /* HasDisjunctSubRegs */ |
9309 | | false, /* CoveredBySubRegs */ |
9310 | | NullRegClasses, |
9311 | | nullptr |
9312 | | }; |
9313 | | |
9314 | | extern const TargetRegisterClass R600_TReg32RegClass = { |
9315 | | &R600MCRegisterClasses[R600_TReg32RegClassID], |
9316 | | R600_TReg32SubClassMask, |
9317 | | SuperRegIdxSeqs + 0, |
9318 | | LaneBitmask(0x0000000000000001), |
9319 | | 0, |
9320 | | false, |
9321 | | 0x00, /* TSFlags */ |
9322 | | false, /* HasDisjunctSubRegs */ |
9323 | | false, /* CoveredBySubRegs */ |
9324 | | R600_TReg32Superclasses, |
9325 | | nullptr |
9326 | | }; |
9327 | | |
9328 | | extern const TargetRegisterClass R600_TReg32_XRegClass = { |
9329 | | &R600MCRegisterClasses[R600_TReg32_XRegClassID], |
9330 | | R600_TReg32_XSubClassMask, |
9331 | | SuperRegIdxSeqs + 0, |
9332 | | LaneBitmask(0x0000000000000001), |
9333 | | 0, |
9334 | | false, |
9335 | | 0x00, /* TSFlags */ |
9336 | | false, /* HasDisjunctSubRegs */ |
9337 | | false, /* CoveredBySubRegs */ |
9338 | | R600_TReg32_XSuperclasses, |
9339 | | nullptr |
9340 | | }; |
9341 | | |
9342 | | extern const TargetRegisterClass R600_AddrRegClass = { |
9343 | | &R600MCRegisterClasses[R600_AddrRegClassID], |
9344 | | R600_AddrSubClassMask, |
9345 | | SuperRegIdxSeqs + 4, |
9346 | | LaneBitmask(0x0000000000000001), |
9347 | | 0, |
9348 | | false, |
9349 | | 0x00, /* TSFlags */ |
9350 | | false, /* HasDisjunctSubRegs */ |
9351 | | false, /* CoveredBySubRegs */ |
9352 | | R600_AddrSuperclasses, |
9353 | | nullptr |
9354 | | }; |
9355 | | |
9356 | | extern const TargetRegisterClass R600_KC0RegClass = { |
9357 | | &R600MCRegisterClasses[R600_KC0RegClassID], |
9358 | | R600_KC0SubClassMask, |
9359 | | SuperRegIdxSeqs + 4, |
9360 | | LaneBitmask(0x0000000000000001), |
9361 | | 0, |
9362 | | false, |
9363 | | 0x00, /* TSFlags */ |
9364 | | false, /* HasDisjunctSubRegs */ |
9365 | | false, /* CoveredBySubRegs */ |
9366 | | R600_KC0Superclasses, |
9367 | | nullptr |
9368 | | }; |
9369 | | |
9370 | | extern const TargetRegisterClass R600_KC1RegClass = { |
9371 | | &R600MCRegisterClasses[R600_KC1RegClassID], |
9372 | | R600_KC1SubClassMask, |
9373 | | SuperRegIdxSeqs + 4, |
9374 | | LaneBitmask(0x0000000000000001), |
9375 | | 0, |
9376 | | false, |
9377 | | 0x00, /* TSFlags */ |
9378 | | false, /* HasDisjunctSubRegs */ |
9379 | | false, /* CoveredBySubRegs */ |
9380 | | R600_KC1Superclasses, |
9381 | | nullptr |
9382 | | }; |
9383 | | |
9384 | | extern const TargetRegisterClass R600_TReg32_WRegClass = { |
9385 | | &R600MCRegisterClasses[R600_TReg32_WRegClassID], |
9386 | | R600_TReg32_WSubClassMask, |
9387 | | SuperRegIdxSeqs + 0, |
9388 | | LaneBitmask(0x0000000000000001), |
9389 | | 0, |
9390 | | false, |
9391 | | 0x00, /* TSFlags */ |
9392 | | false, /* HasDisjunctSubRegs */ |
9393 | | false, /* CoveredBySubRegs */ |
9394 | | R600_TReg32_WSuperclasses, |
9395 | | nullptr |
9396 | | }; |
9397 | | |
9398 | | extern const TargetRegisterClass R600_TReg32_YRegClass = { |
9399 | | &R600MCRegisterClasses[R600_TReg32_YRegClassID], |
9400 | | R600_TReg32_YSubClassMask, |
9401 | | SuperRegIdxSeqs + 0, |
9402 | | LaneBitmask(0x0000000000000001), |
9403 | | 0, |
9404 | | false, |
9405 | | 0x00, /* TSFlags */ |
9406 | | false, /* HasDisjunctSubRegs */ |
9407 | | false, /* CoveredBySubRegs */ |
9408 | | R600_TReg32_YSuperclasses, |
9409 | | nullptr |
9410 | | }; |
9411 | | |
9412 | | extern const TargetRegisterClass R600_TReg32_ZRegClass = { |
9413 | | &R600MCRegisterClasses[R600_TReg32_ZRegClassID], |
9414 | | R600_TReg32_ZSubClassMask, |
9415 | | SuperRegIdxSeqs + 0, |
9416 | | LaneBitmask(0x0000000000000001), |
9417 | | 0, |
9418 | | false, |
9419 | | 0x00, /* TSFlags */ |
9420 | | false, /* HasDisjunctSubRegs */ |
9421 | | false, /* CoveredBySubRegs */ |
9422 | | R600_TReg32_ZSuperclasses, |
9423 | | nullptr |
9424 | | }; |
9425 | | |
9426 | | extern const TargetRegisterClass R600_ArrayBaseRegClass = { |
9427 | | &R600MCRegisterClasses[R600_ArrayBaseRegClassID], |
9428 | | R600_ArrayBaseSubClassMask, |
9429 | | SuperRegIdxSeqs + 4, |
9430 | | LaneBitmask(0x0000000000000001), |
9431 | | 0, |
9432 | | false, |
9433 | | 0x00, /* TSFlags */ |
9434 | | false, /* HasDisjunctSubRegs */ |
9435 | | false, /* CoveredBySubRegs */ |
9436 | | R600_ArrayBaseSuperclasses, |
9437 | | nullptr |
9438 | | }; |
9439 | | |
9440 | | extern const TargetRegisterClass R600_KC0_WRegClass = { |
9441 | | &R600MCRegisterClasses[R600_KC0_WRegClassID], |
9442 | | R600_KC0_WSubClassMask, |
9443 | | SuperRegIdxSeqs + 4, |
9444 | | LaneBitmask(0x0000000000000001), |
9445 | | 0, |
9446 | | false, |
9447 | | 0x00, /* TSFlags */ |
9448 | | false, /* HasDisjunctSubRegs */ |
9449 | | false, /* CoveredBySubRegs */ |
9450 | | R600_KC0_WSuperclasses, |
9451 | | nullptr |
9452 | | }; |
9453 | | |
9454 | | extern const TargetRegisterClass R600_KC0_XRegClass = { |
9455 | | &R600MCRegisterClasses[R600_KC0_XRegClassID], |
9456 | | R600_KC0_XSubClassMask, |
9457 | | SuperRegIdxSeqs + 4, |
9458 | | LaneBitmask(0x0000000000000001), |
9459 | | 0, |
9460 | | false, |
9461 | | 0x00, /* TSFlags */ |
9462 | | false, /* HasDisjunctSubRegs */ |
9463 | | false, /* CoveredBySubRegs */ |
9464 | | R600_KC0_XSuperclasses, |
9465 | | nullptr |
9466 | | }; |
9467 | | |
9468 | | extern const TargetRegisterClass R600_KC0_YRegClass = { |
9469 | | &R600MCRegisterClasses[R600_KC0_YRegClassID], |
9470 | | R600_KC0_YSubClassMask, |
9471 | | SuperRegIdxSeqs + 4, |
9472 | | LaneBitmask(0x0000000000000001), |
9473 | | 0, |
9474 | | false, |
9475 | | 0x00, /* TSFlags */ |
9476 | | false, /* HasDisjunctSubRegs */ |
9477 | | false, /* CoveredBySubRegs */ |
9478 | | R600_KC0_YSuperclasses, |
9479 | | nullptr |
9480 | | }; |
9481 | | |
9482 | | extern const TargetRegisterClass R600_KC0_ZRegClass = { |
9483 | | &R600MCRegisterClasses[R600_KC0_ZRegClassID], |
9484 | | R600_KC0_ZSubClassMask, |
9485 | | SuperRegIdxSeqs + 4, |
9486 | | LaneBitmask(0x0000000000000001), |
9487 | | 0, |
9488 | | false, |
9489 | | 0x00, /* TSFlags */ |
9490 | | false, /* HasDisjunctSubRegs */ |
9491 | | false, /* CoveredBySubRegs */ |
9492 | | R600_KC0_ZSuperclasses, |
9493 | | nullptr |
9494 | | }; |
9495 | | |
9496 | | extern const TargetRegisterClass R600_KC1_WRegClass = { |
9497 | | &R600MCRegisterClasses[R600_KC1_WRegClassID], |
9498 | | R600_KC1_WSubClassMask, |
9499 | | SuperRegIdxSeqs + 4, |
9500 | | LaneBitmask(0x0000000000000001), |
9501 | | 0, |
9502 | | false, |
9503 | | 0x00, /* TSFlags */ |
9504 | | false, /* HasDisjunctSubRegs */ |
9505 | | false, /* CoveredBySubRegs */ |
9506 | | R600_KC1_WSuperclasses, |
9507 | | nullptr |
9508 | | }; |
9509 | | |
9510 | | extern const TargetRegisterClass R600_KC1_XRegClass = { |
9511 | | &R600MCRegisterClasses[R600_KC1_XRegClassID], |
9512 | | R600_KC1_XSubClassMask, |
9513 | | SuperRegIdxSeqs + 4, |
9514 | | LaneBitmask(0x0000000000000001), |
9515 | | 0, |
9516 | | false, |
9517 | | 0x00, /* TSFlags */ |
9518 | | false, /* HasDisjunctSubRegs */ |
9519 | | false, /* CoveredBySubRegs */ |
9520 | | R600_KC1_XSuperclasses, |
9521 | | nullptr |
9522 | | }; |
9523 | | |
9524 | | extern const TargetRegisterClass R600_KC1_YRegClass = { |
9525 | | &R600MCRegisterClasses[R600_KC1_YRegClassID], |
9526 | | R600_KC1_YSubClassMask, |
9527 | | SuperRegIdxSeqs + 4, |
9528 | | LaneBitmask(0x0000000000000001), |
9529 | | 0, |
9530 | | false, |
9531 | | 0x00, /* TSFlags */ |
9532 | | false, /* HasDisjunctSubRegs */ |
9533 | | false, /* CoveredBySubRegs */ |
9534 | | R600_KC1_YSuperclasses, |
9535 | | nullptr |
9536 | | }; |
9537 | | |
9538 | | extern const TargetRegisterClass R600_KC1_ZRegClass = { |
9539 | | &R600MCRegisterClasses[R600_KC1_ZRegClassID], |
9540 | | R600_KC1_ZSubClassMask, |
9541 | | SuperRegIdxSeqs + 4, |
9542 | | LaneBitmask(0x0000000000000001), |
9543 | | 0, |
9544 | | false, |
9545 | | 0x00, /* TSFlags */ |
9546 | | false, /* HasDisjunctSubRegs */ |
9547 | | false, /* CoveredBySubRegs */ |
9548 | | R600_KC1_ZSuperclasses, |
9549 | | nullptr |
9550 | | }; |
9551 | | |
9552 | | extern const TargetRegisterClass R600_LDS_SRC_REGRegClass = { |
9553 | | &R600MCRegisterClasses[R600_LDS_SRC_REGRegClassID], |
9554 | | R600_LDS_SRC_REGSubClassMask, |
9555 | | SuperRegIdxSeqs + 4, |
9556 | | LaneBitmask(0x0000000000000001), |
9557 | | 0, |
9558 | | false, |
9559 | | 0x00, /* TSFlags */ |
9560 | | false, /* HasDisjunctSubRegs */ |
9561 | | false, /* CoveredBySubRegs */ |
9562 | | NullRegClasses, |
9563 | | nullptr |
9564 | | }; |
9565 | | |
9566 | | extern const TargetRegisterClass R600_PredicateRegClass = { |
9567 | | &R600MCRegisterClasses[R600_PredicateRegClassID], |
9568 | | R600_PredicateSubClassMask, |
9569 | | SuperRegIdxSeqs + 4, |
9570 | | LaneBitmask(0x0000000000000001), |
9571 | | 0, |
9572 | | false, |
9573 | | 0x00, /* TSFlags */ |
9574 | | false, /* HasDisjunctSubRegs */ |
9575 | | false, /* CoveredBySubRegs */ |
9576 | | NullRegClasses, |
9577 | | nullptr |
9578 | | }; |
9579 | | |
9580 | | extern const TargetRegisterClass R600_Addr_WRegClass = { |
9581 | | &R600MCRegisterClasses[R600_Addr_WRegClassID], |
9582 | | R600_Addr_WSubClassMask, |
9583 | | SuperRegIdxSeqs + 4, |
9584 | | LaneBitmask(0x0000000000000001), |
9585 | | 0, |
9586 | | false, |
9587 | | 0x00, /* TSFlags */ |
9588 | | false, /* HasDisjunctSubRegs */ |
9589 | | false, /* CoveredBySubRegs */ |
9590 | | NullRegClasses, |
9591 | | nullptr |
9592 | | }; |
9593 | | |
9594 | | extern const TargetRegisterClass R600_Addr_YRegClass = { |
9595 | | &R600MCRegisterClasses[R600_Addr_YRegClassID], |
9596 | | R600_Addr_YSubClassMask, |
9597 | | SuperRegIdxSeqs + 4, |
9598 | | LaneBitmask(0x0000000000000001), |
9599 | | 0, |
9600 | | false, |
9601 | | 0x00, /* TSFlags */ |
9602 | | false, /* HasDisjunctSubRegs */ |
9603 | | false, /* CoveredBySubRegs */ |
9604 | | NullRegClasses, |
9605 | | nullptr |
9606 | | }; |
9607 | | |
9608 | | extern const TargetRegisterClass R600_Addr_ZRegClass = { |
9609 | | &R600MCRegisterClasses[R600_Addr_ZRegClassID], |
9610 | | R600_Addr_ZSubClassMask, |
9611 | | SuperRegIdxSeqs + 4, |
9612 | | LaneBitmask(0x0000000000000001), |
9613 | | 0, |
9614 | | false, |
9615 | | 0x00, /* TSFlags */ |
9616 | | false, /* HasDisjunctSubRegs */ |
9617 | | false, /* CoveredBySubRegs */ |
9618 | | NullRegClasses, |
9619 | | nullptr |
9620 | | }; |
9621 | | |
9622 | | extern const TargetRegisterClass R600_LDS_SRC_REG_and_R600_Reg32RegClass = { |
9623 | | &R600MCRegisterClasses[R600_LDS_SRC_REG_and_R600_Reg32RegClassID], |
9624 | | R600_LDS_SRC_REG_and_R600_Reg32SubClassMask, |
9625 | | SuperRegIdxSeqs + 4, |
9626 | | LaneBitmask(0x0000000000000001), |
9627 | | 0, |
9628 | | false, |
9629 | | 0x00, /* TSFlags */ |
9630 | | false, /* HasDisjunctSubRegs */ |
9631 | | false, /* CoveredBySubRegs */ |
9632 | | R600_LDS_SRC_REG_and_R600_Reg32Superclasses, |
9633 | | nullptr |
9634 | | }; |
9635 | | |
9636 | | extern const TargetRegisterClass R600_Predicate_BitRegClass = { |
9637 | | &R600MCRegisterClasses[R600_Predicate_BitRegClassID], |
9638 | | R600_Predicate_BitSubClassMask, |
9639 | | SuperRegIdxSeqs + 4, |
9640 | | LaneBitmask(0x0000000000000001), |
9641 | | 0, |
9642 | | false, |
9643 | | 0x00, /* TSFlags */ |
9644 | | false, /* HasDisjunctSubRegs */ |
9645 | | false, /* CoveredBySubRegs */ |
9646 | | NullRegClasses, |
9647 | | nullptr |
9648 | | }; |
9649 | | |
9650 | | extern const TargetRegisterClass R600_Reg64RegClass = { |
9651 | | &R600MCRegisterClasses[R600_Reg64RegClassID], |
9652 | | R600_Reg64SubClassMask, |
9653 | | SuperRegIdxSeqs + 4, |
9654 | | LaneBitmask(0x0000000000000003), |
9655 | | 0, |
9656 | | false, |
9657 | | 0x00, /* TSFlags */ |
9658 | | true, /* HasDisjunctSubRegs */ |
9659 | | false, /* CoveredBySubRegs */ |
9660 | | NullRegClasses, |
9661 | | nullptr |
9662 | | }; |
9663 | | |
9664 | | extern const TargetRegisterClass R600_Reg64VerticalRegClass = { |
9665 | | &R600MCRegisterClasses[R600_Reg64VerticalRegClassID], |
9666 | | R600_Reg64VerticalSubClassMask, |
9667 | | SuperRegIdxSeqs + 4, |
9668 | | LaneBitmask(0x0000000000000003), |
9669 | | 0, |
9670 | | false, |
9671 | | 0x00, /* TSFlags */ |
9672 | | true, /* HasDisjunctSubRegs */ |
9673 | | false, /* CoveredBySubRegs */ |
9674 | | NullRegClasses, |
9675 | | nullptr |
9676 | | }; |
9677 | | |
9678 | | extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_WRegClass = { |
9679 | | &R600MCRegisterClasses[R600_Reg64Vertical_with_sub0_in_R600_TReg32_WRegClassID], |
9680 | | R600_Reg64Vertical_with_sub0_in_R600_TReg32_WSubClassMask, |
9681 | | SuperRegIdxSeqs + 4, |
9682 | | LaneBitmask(0x0000000000000003), |
9683 | | 0, |
9684 | | false, |
9685 | | 0x00, /* TSFlags */ |
9686 | | true, /* HasDisjunctSubRegs */ |
9687 | | false, /* CoveredBySubRegs */ |
9688 | | R600_Reg64Vertical_with_sub0_in_R600_TReg32_WSuperclasses, |
9689 | | nullptr |
9690 | | }; |
9691 | | |
9692 | | extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_XRegClass = { |
9693 | | &R600MCRegisterClasses[R600_Reg64Vertical_with_sub0_in_R600_TReg32_XRegClassID], |
9694 | | R600_Reg64Vertical_with_sub0_in_R600_TReg32_XSubClassMask, |
9695 | | SuperRegIdxSeqs + 4, |
9696 | | LaneBitmask(0x0000000000000003), |
9697 | | 0, |
9698 | | false, |
9699 | | 0x00, /* TSFlags */ |
9700 | | true, /* HasDisjunctSubRegs */ |
9701 | | false, /* CoveredBySubRegs */ |
9702 | | R600_Reg64Vertical_with_sub0_in_R600_TReg32_XSuperclasses, |
9703 | | nullptr |
9704 | | }; |
9705 | | |
9706 | | extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_YRegClass = { |
9707 | | &R600MCRegisterClasses[R600_Reg64Vertical_with_sub0_in_R600_TReg32_YRegClassID], |
9708 | | R600_Reg64Vertical_with_sub0_in_R600_TReg32_YSubClassMask, |
9709 | | SuperRegIdxSeqs + 4, |
9710 | | LaneBitmask(0x0000000000000003), |
9711 | | 0, |
9712 | | false, |
9713 | | 0x00, /* TSFlags */ |
9714 | | true, /* HasDisjunctSubRegs */ |
9715 | | false, /* CoveredBySubRegs */ |
9716 | | R600_Reg64Vertical_with_sub0_in_R600_TReg32_YSuperclasses, |
9717 | | nullptr |
9718 | | }; |
9719 | | |
9720 | | extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZRegClass = { |
9721 | | &R600MCRegisterClasses[R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZRegClassID], |
9722 | | R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZSubClassMask, |
9723 | | SuperRegIdxSeqs + 4, |
9724 | | LaneBitmask(0x0000000000000003), |
9725 | | 0, |
9726 | | false, |
9727 | | 0x00, /* TSFlags */ |
9728 | | true, /* HasDisjunctSubRegs */ |
9729 | | false, /* CoveredBySubRegs */ |
9730 | | R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZSuperclasses, |
9731 | | nullptr |
9732 | | }; |
9733 | | |
9734 | | extern const TargetRegisterClass R600_Reg128RegClass = { |
9735 | | &R600MCRegisterClasses[R600_Reg128RegClassID], |
9736 | | R600_Reg128SubClassMask, |
9737 | | SuperRegIdxSeqs + 4, |
9738 | | LaneBitmask(0x000000000000000F), |
9739 | | 0, |
9740 | | false, |
9741 | | 0x00, /* TSFlags */ |
9742 | | true, /* HasDisjunctSubRegs */ |
9743 | | false, /* CoveredBySubRegs */ |
9744 | | NullRegClasses, |
9745 | | nullptr |
9746 | | }; |
9747 | | |
9748 | | extern const TargetRegisterClass R600_Reg128VerticalRegClass = { |
9749 | | &R600MCRegisterClasses[R600_Reg128VerticalRegClassID], |
9750 | | R600_Reg128VerticalSubClassMask, |
9751 | | SuperRegIdxSeqs + 4, |
9752 | | LaneBitmask(0x000000000000000F), |
9753 | | 0, |
9754 | | false, |
9755 | | 0x00, /* TSFlags */ |
9756 | | true, /* HasDisjunctSubRegs */ |
9757 | | false, /* CoveredBySubRegs */ |
9758 | | NullRegClasses, |
9759 | | nullptr |
9760 | | }; |
9761 | | |
9762 | | extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_WRegClass = { |
9763 | | &R600MCRegisterClasses[R600_Reg128Vertical_with_sub0_in_R600_TReg32_WRegClassID], |
9764 | | R600_Reg128Vertical_with_sub0_in_R600_TReg32_WSubClassMask, |
9765 | | SuperRegIdxSeqs + 4, |
9766 | | LaneBitmask(0x000000000000000F), |
9767 | | 0, |
9768 | | false, |
9769 | | 0x00, /* TSFlags */ |
9770 | | true, /* HasDisjunctSubRegs */ |
9771 | | false, /* CoveredBySubRegs */ |
9772 | | R600_Reg128Vertical_with_sub0_in_R600_TReg32_WSuperclasses, |
9773 | | nullptr |
9774 | | }; |
9775 | | |
9776 | | extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_XRegClass = { |
9777 | | &R600MCRegisterClasses[R600_Reg128Vertical_with_sub0_in_R600_TReg32_XRegClassID], |
9778 | | R600_Reg128Vertical_with_sub0_in_R600_TReg32_XSubClassMask, |
9779 | | SuperRegIdxSeqs + 4, |
9780 | | LaneBitmask(0x000000000000000F), |
9781 | | 0, |
9782 | | false, |
9783 | | 0x00, /* TSFlags */ |
9784 | | true, /* HasDisjunctSubRegs */ |
9785 | | false, /* CoveredBySubRegs */ |
9786 | | R600_Reg128Vertical_with_sub0_in_R600_TReg32_XSuperclasses, |
9787 | | nullptr |
9788 | | }; |
9789 | | |
9790 | | extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_YRegClass = { |
9791 | | &R600MCRegisterClasses[R600_Reg128Vertical_with_sub0_in_R600_TReg32_YRegClassID], |
9792 | | R600_Reg128Vertical_with_sub0_in_R600_TReg32_YSubClassMask, |
9793 | | SuperRegIdxSeqs + 4, |
9794 | | LaneBitmask(0x000000000000000F), |
9795 | | 0, |
9796 | | false, |
9797 | | 0x00, /* TSFlags */ |
9798 | | true, /* HasDisjunctSubRegs */ |
9799 | | false, /* CoveredBySubRegs */ |
9800 | | R600_Reg128Vertical_with_sub0_in_R600_TReg32_YSuperclasses, |
9801 | | nullptr |
9802 | | }; |
9803 | | |
9804 | | extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZRegClass = { |
9805 | | &R600MCRegisterClasses[R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZRegClassID], |
9806 | | R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZSubClassMask, |
9807 | | SuperRegIdxSeqs + 4, |
9808 | | LaneBitmask(0x000000000000000F), |
9809 | | 0, |
9810 | | false, |
9811 | | 0x00, /* TSFlags */ |
9812 | | true, /* HasDisjunctSubRegs */ |
9813 | | false, /* CoveredBySubRegs */ |
9814 | | R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZSuperclasses, |
9815 | | nullptr |
9816 | | }; |
9817 | | |
9818 | | } // end namespace R600 |
9819 | | |
9820 | | namespace { |
9821 | | const TargetRegisterClass *const RegisterClasses[] = { |
9822 | | &R600::R600_Reg32RegClass, |
9823 | | &R600::R600_TReg32RegClass, |
9824 | | &R600::R600_TReg32_XRegClass, |
9825 | | &R600::R600_AddrRegClass, |
9826 | | &R600::R600_KC0RegClass, |
9827 | | &R600::R600_KC1RegClass, |
9828 | | &R600::R600_TReg32_WRegClass, |
9829 | | &R600::R600_TReg32_YRegClass, |
9830 | | &R600::R600_TReg32_ZRegClass, |
9831 | | &R600::R600_ArrayBaseRegClass, |
9832 | | &R600::R600_KC0_WRegClass, |
9833 | | &R600::R600_KC0_XRegClass, |
9834 | | &R600::R600_KC0_YRegClass, |
9835 | | &R600::R600_KC0_ZRegClass, |
9836 | | &R600::R600_KC1_WRegClass, |
9837 | | &R600::R600_KC1_XRegClass, |
9838 | | &R600::R600_KC1_YRegClass, |
9839 | | &R600::R600_KC1_ZRegClass, |
9840 | | &R600::R600_LDS_SRC_REGRegClass, |
9841 | | &R600::R600_PredicateRegClass, |
9842 | | &R600::R600_Addr_WRegClass, |
9843 | | &R600::R600_Addr_YRegClass, |
9844 | | &R600::R600_Addr_ZRegClass, |
9845 | | &R600::R600_LDS_SRC_REG_and_R600_Reg32RegClass, |
9846 | | &R600::R600_Predicate_BitRegClass, |
9847 | | &R600::R600_Reg64RegClass, |
9848 | | &R600::R600_Reg64VerticalRegClass, |
9849 | | &R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_WRegClass, |
9850 | | &R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_XRegClass, |
9851 | | &R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_YRegClass, |
9852 | | &R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZRegClass, |
9853 | | &R600::R600_Reg128RegClass, |
9854 | | &R600::R600_Reg128VerticalRegClass, |
9855 | | &R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_WRegClass, |
9856 | | &R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_XRegClass, |
9857 | | &R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_YRegClass, |
9858 | | &R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZRegClass, |
9859 | | }; |
9860 | | } // end anonymous namespace |
9861 | | |
9862 | | static const uint8_t CostPerUseTable[] = { |
9863 | | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; |
9864 | | |
9865 | | |
9866 | | static const bool InAllocatableClassTable[] = { |
9867 | | false, true, false, true, false, false, true, true, true, true, false, false, true, true, true, true, false, true, false, false, true, true, true, true, false, false, true, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, }; |
9868 | | |
9869 | | |
9870 | | static const TargetRegisterInfoDesc R600RegInfoDesc = { // Extra Descriptors |
9871 | | CostPerUseTable, 1, InAllocatableClassTable}; |
9872 | | |
9873 | 0 | unsigned R600GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const { |
9874 | 0 | static const uint8_t Rows[1][16] = { |
9875 | 0 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, |
9876 | 0 | }; |
9877 | |
|
9878 | 0 | --IdxA; assert(IdxA < 16); (void) IdxA; |
9879 | 0 | --IdxB; assert(IdxB < 16); |
9880 | 0 | return Rows[0][IdxB]; |
9881 | 0 | } |
9882 | | |
9883 | | struct MaskRolOp { |
9884 | | LaneBitmask Mask; |
9885 | | uint8_t RotateLeft; |
9886 | | }; |
9887 | | static const MaskRolOp LaneMaskComposeSequences[] = { |
9888 | | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0 |
9889 | | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2 |
9890 | | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4 |
9891 | | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 6 |
9892 | | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 8 |
9893 | | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 10 |
9894 | | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 }, // Sequence 12 |
9895 | | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 7 }, { LaneBitmask::getNone(), 0 }, // Sequence 14 |
9896 | | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 8 }, { LaneBitmask::getNone(), 0 }, // Sequence 16 |
9897 | | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 9 }, { LaneBitmask::getNone(), 0 }, // Sequence 18 |
9898 | | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 10 }, { LaneBitmask::getNone(), 0 }, // Sequence 20 |
9899 | | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 11 }, { LaneBitmask::getNone(), 0 }, // Sequence 22 |
9900 | | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 12 }, { LaneBitmask::getNone(), 0 }, // Sequence 24 |
9901 | | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 13 }, { LaneBitmask::getNone(), 0 }, // Sequence 26 |
9902 | | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 14 }, { LaneBitmask::getNone(), 0 }, // Sequence 28 |
9903 | | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 15 }, { LaneBitmask::getNone(), 0 } // Sequence 30 |
9904 | | }; |
9905 | | static const uint8_t CompositeSequences[] = { |
9906 | | 0, // to sub0 |
9907 | | 2, // to sub1 |
9908 | | 4, // to sub2 |
9909 | | 6, // to sub3 |
9910 | | 8, // to sub4 |
9911 | | 10, // to sub5 |
9912 | | 12, // to sub6 |
9913 | | 14, // to sub7 |
9914 | | 16, // to sub8 |
9915 | | 18, // to sub9 |
9916 | | 20, // to sub10 |
9917 | | 22, // to sub11 |
9918 | | 24, // to sub12 |
9919 | | 26, // to sub13 |
9920 | | 28, // to sub14 |
9921 | | 30 // to sub15 |
9922 | | }; |
9923 | | |
9924 | 0 | LaneBitmask R600GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { |
9925 | 0 | --IdxA; assert(IdxA < 16 && "Subregister index out of bounds"); |
9926 | 0 | LaneBitmask Result; |
9927 | 0 | for (const MaskRolOp *Ops = |
9928 | 0 | &LaneMaskComposeSequences[CompositeSequences[IdxA]]; |
9929 | 0 | Ops->Mask.any(); ++Ops) { |
9930 | 0 | LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger(); |
9931 | 0 | if (unsigned S = Ops->RotateLeft) |
9932 | 0 | Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S))); |
9933 | 0 | else |
9934 | 0 | Result |= LaneBitmask(M); |
9935 | 0 | } |
9936 | 0 | return Result; |
9937 | 0 | } |
9938 | | |
9939 | 0 | LaneBitmask R600GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { |
9940 | 0 | LaneMask &= getSubRegIndexLaneMask(IdxA); |
9941 | 0 | --IdxA; assert(IdxA < 16 && "Subregister index out of bounds"); |
9942 | 0 | LaneBitmask Result; |
9943 | 0 | for (const MaskRolOp *Ops = |
9944 | 0 | &LaneMaskComposeSequences[CompositeSequences[IdxA]]; |
9945 | 0 | Ops->Mask.any(); ++Ops) { |
9946 | 0 | LaneBitmask::Type M = LaneMask.getAsInteger(); |
9947 | 0 | if (unsigned S = Ops->RotateLeft) |
9948 | 0 | Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S))); |
9949 | 0 | else |
9950 | 0 | Result |= LaneBitmask(M); |
9951 | 0 | } |
9952 | 0 | return Result; |
9953 | 0 | } |
9954 | | |
9955 | 0 | const TargetRegisterClass *R600GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { |
9956 | 0 | static const uint8_t Table[37][16] = { |
9957 | 0 | { // R600_Reg32 |
9958 | 0 | 0, // sub0 |
9959 | 0 | 0, // sub1 |
9960 | 0 | 0, // sub2 |
9961 | 0 | 0, // sub3 |
9962 | 0 | 0, // sub4 |
9963 | 0 | 0, // sub5 |
9964 | 0 | 0, // sub6 |
9965 | 0 | 0, // sub7 |
9966 | 0 | 0, // sub8 |
9967 | 0 | 0, // sub9 |
9968 | 0 | 0, // sub10 |
9969 | 0 | 0, // sub11 |
9970 | 0 | 0, // sub12 |
9971 | 0 | 0, // sub13 |
9972 | 0 | 0, // sub14 |
9973 | 0 | 0, // sub15 |
9974 | 0 | }, |
9975 | 0 | { // R600_TReg32 |
9976 | 0 | 0, // sub0 |
9977 | 0 | 0, // sub1 |
9978 | 0 | 0, // sub2 |
9979 | 0 | 0, // sub3 |
9980 | 0 | 0, // sub4 |
9981 | 0 | 0, // sub5 |
9982 | 0 | 0, // sub6 |
9983 | 0 | 0, // sub7 |
9984 | 0 | 0, // sub8 |
9985 | 0 | 0, // sub9 |
9986 | 0 | 0, // sub10 |
9987 | 0 | 0, // sub11 |
9988 | 0 | 0, // sub12 |
9989 | 0 | 0, // sub13 |
9990 | 0 | 0, // sub14 |
9991 | 0 | 0, // sub15 |
9992 | 0 | }, |
9993 | 0 | { // R600_TReg32_X |
9994 | 0 | 0, // sub0 |
9995 | 0 | 0, // sub1 |
9996 | 0 | 0, // sub2 |
9997 | 0 | 0, // sub3 |
9998 | 0 | 0, // sub4 |
9999 | 0 | 0, // sub5 |
10000 | 0 | 0, // sub6 |
10001 | 0 | 0, // sub7 |
10002 | 0 | 0, // sub8 |
10003 | 0 | 0, // sub9 |
10004 | 0 | 0, // sub10 |
10005 | 0 | 0, // sub11 |
10006 | 0 | 0, // sub12 |
10007 | 0 | 0, // sub13 |
10008 | 0 | 0, // sub14 |
10009 | 0 | 0, // sub15 |
10010 | 0 | }, |
10011 | 0 | { // R600_Addr |
10012 | 0 | 0, // sub0 |
10013 | 0 | 0, // sub1 |
10014 | 0 | 0, // sub2 |
10015 | 0 | 0, // sub3 |
10016 | 0 | 0, // sub4 |
10017 | 0 | 0, // sub5 |
10018 | 0 | 0, // sub6 |
10019 | 0 | 0, // sub7 |
10020 | 0 | 0, // sub8 |
10021 | 0 | 0, // sub9 |
10022 | 0 | 0, // sub10 |
10023 | 0 | 0, // sub11 |
10024 | 0 | 0, // sub12 |
10025 | 0 | 0, // sub13 |
10026 | 0 | 0, // sub14 |
10027 | 0 | 0, // sub15 |
10028 | 0 | }, |
10029 | 0 | { // R600_KC0 |
10030 | 0 | 0, // sub0 |
10031 | 0 | 0, // sub1 |
10032 | 0 | 0, // sub2 |
10033 | 0 | 0, // sub3 |
10034 | 0 | 0, // sub4 |
10035 | 0 | 0, // sub5 |
10036 | 0 | 0, // sub6 |
10037 | 0 | 0, // sub7 |
10038 | 0 | 0, // sub8 |
10039 | 0 | 0, // sub9 |
10040 | 0 | 0, // sub10 |
10041 | 0 | 0, // sub11 |
10042 | 0 | 0, // sub12 |
10043 | 0 | 0, // sub13 |
10044 | 0 | 0, // sub14 |
10045 | 0 | 0, // sub15 |
10046 | 0 | }, |
10047 | 0 | { // R600_KC1 |
10048 | 0 | 0, // sub0 |
10049 | 0 | 0, // sub1 |
10050 | 0 | 0, // sub2 |
10051 | 0 | 0, // sub3 |
10052 | 0 | 0, // sub4 |
10053 | 0 | 0, // sub5 |
10054 | 0 | 0, // sub6 |
10055 | 0 | 0, // sub7 |
10056 | 0 | 0, // sub8 |
10057 | 0 | 0, // sub9 |
10058 | 0 | 0, // sub10 |
10059 | 0 | 0, // sub11 |
10060 | 0 | 0, // sub12 |
10061 | 0 | 0, // sub13 |
10062 | 0 | 0, // sub14 |
10063 | 0 | 0, // sub15 |
10064 | 0 | }, |
10065 | 0 | { // R600_TReg32_W |
10066 | 0 | 0, // sub0 |
10067 | 0 | 0, // sub1 |
10068 | 0 | 0, // sub2 |
10069 | 0 | 0, // sub3 |
10070 | 0 | 0, // sub4 |
10071 | 0 | 0, // sub5 |
10072 | 0 | 0, // sub6 |
10073 | 0 | 0, // sub7 |
10074 | 0 | 0, // sub8 |
10075 | 0 | 0, // sub9 |
10076 | 0 | 0, // sub10 |
10077 | 0 | 0, // sub11 |
10078 | 0 | 0, // sub12 |
10079 | 0 | 0, // sub13 |
10080 | 0 | 0, // sub14 |
10081 | 0 | 0, // sub15 |
10082 | 0 | }, |
10083 | 0 | { // R600_TReg32_Y |
10084 | 0 | 0, // sub0 |
10085 | 0 | 0, // sub1 |
10086 | 0 | 0, // sub2 |
10087 | 0 | 0, // sub3 |
10088 | 0 | 0, // sub4 |
10089 | 0 | 0, // sub5 |
10090 | 0 | 0, // sub6 |
10091 | 0 | 0, // sub7 |
10092 | 0 | 0, // sub8 |
10093 | 0 | 0, // sub9 |
10094 | 0 | 0, // sub10 |
10095 | 0 | 0, // sub11 |
10096 | 0 | 0, // sub12 |
10097 | 0 | 0, // sub13 |
10098 | 0 | 0, // sub14 |
10099 | 0 | 0, // sub15 |
10100 | 0 | }, |
10101 | 0 | { // R600_TReg32_Z |
10102 | 0 | 0, // sub0 |
10103 | 0 | 0, // sub1 |
10104 | 0 | 0, // sub2 |
10105 | 0 | 0, // sub3 |
10106 | 0 | 0, // sub4 |
10107 | 0 | 0, // sub5 |
10108 | 0 | 0, // sub6 |
10109 | 0 | 0, // sub7 |
10110 | 0 | 0, // sub8 |
10111 | 0 | 0, // sub9 |
10112 | 0 | 0, // sub10 |
10113 | 0 | 0, // sub11 |
10114 | 0 | 0, // sub12 |
10115 | 0 | 0, // sub13 |
10116 | 0 | 0, // sub14 |
10117 | 0 | 0, // sub15 |
10118 | 0 | }, |
10119 | 0 | { // R600_ArrayBase |
10120 | 0 | 0, // sub0 |
10121 | 0 | 0, // sub1 |
10122 | 0 | 0, // sub2 |
10123 | 0 | 0, // sub3 |
10124 | 0 | 0, // sub4 |
10125 | 0 | 0, // sub5 |
10126 | 0 | 0, // sub6 |
10127 | 0 | 0, // sub7 |
10128 | 0 | 0, // sub8 |
10129 | 0 | 0, // sub9 |
10130 | 0 | 0, // sub10 |
10131 | 0 | 0, // sub11 |
10132 | 0 | 0, // sub12 |
10133 | 0 | 0, // sub13 |
10134 | 0 | 0, // sub14 |
10135 | 0 | 0, // sub15 |
10136 | 0 | }, |
10137 | 0 | { // R600_KC0_W |
10138 | 0 | 0, // sub0 |
10139 | 0 | 0, // sub1 |
10140 | 0 | 0, // sub2 |
10141 | 0 | 0, // sub3 |
10142 | 0 | 0, // sub4 |
10143 | 0 | 0, // sub5 |
10144 | 0 | 0, // sub6 |
10145 | 0 | 0, // sub7 |
10146 | 0 | 0, // sub8 |
10147 | 0 | 0, // sub9 |
10148 | 0 | 0, // sub10 |
10149 | 0 | 0, // sub11 |
10150 | 0 | 0, // sub12 |
10151 | 0 | 0, // sub13 |
10152 | 0 | 0, // sub14 |
10153 | 0 | 0, // sub15 |
10154 | 0 | }, |
10155 | 0 | { // R600_KC0_X |
10156 | 0 | 0, // sub0 |
10157 | 0 | 0, // sub1 |
10158 | 0 | 0, // sub2 |
10159 | 0 | 0, // sub3 |
10160 | 0 | 0, // sub4 |
10161 | 0 | 0, // sub5 |
10162 | 0 | 0, // sub6 |
10163 | 0 | 0, // sub7 |
10164 | 0 | 0, // sub8 |
10165 | 0 | 0, // sub9 |
10166 | 0 | 0, // sub10 |
10167 | 0 | 0, // sub11 |
10168 | 0 | 0, // sub12 |
10169 | 0 | 0, // sub13 |
10170 | 0 | 0, // sub14 |
10171 | 0 | 0, // sub15 |
10172 | 0 | }, |
10173 | 0 | { // R600_KC0_Y |
10174 | 0 | 0, // sub0 |
10175 | 0 | 0, // sub1 |
10176 | 0 | 0, // sub2 |
10177 | 0 | 0, // sub3 |
10178 | 0 | 0, // sub4 |
10179 | 0 | 0, // sub5 |
10180 | 0 | 0, // sub6 |
10181 | 0 | 0, // sub7 |
10182 | 0 | 0, // sub8 |
10183 | 0 | 0, // sub9 |
10184 | 0 | 0, // sub10 |
10185 | 0 | 0, // sub11 |
10186 | 0 | 0, // sub12 |
10187 | 0 | 0, // sub13 |
10188 | 0 | 0, // sub14 |
10189 | 0 | 0, // sub15 |
10190 | 0 | }, |
10191 | 0 | { // R600_KC0_Z |
10192 | 0 | 0, // sub0 |
10193 | 0 | 0, // sub1 |
10194 | 0 | 0, // sub2 |
10195 | 0 | 0, // sub3 |
10196 | 0 | 0, // sub4 |
10197 | 0 | 0, // sub5 |
10198 | 0 | 0, // sub6 |
10199 | 0 | 0, // sub7 |
10200 | 0 | 0, // sub8 |
10201 | 0 | 0, // sub9 |
10202 | 0 | 0, // sub10 |
10203 | 0 | 0, // sub11 |
10204 | 0 | 0, // sub12 |
10205 | 0 | 0, // sub13 |
10206 | 0 | 0, // sub14 |
10207 | 0 | 0, // sub15 |
10208 | 0 | }, |
10209 | 0 | { // R600_KC1_W |
10210 | 0 | 0, // sub0 |
10211 | 0 | 0, // sub1 |
10212 | 0 | 0, // sub2 |
10213 | 0 | 0, // sub3 |
10214 | 0 | 0, // sub4 |
10215 | 0 | 0, // sub5 |
10216 | 0 | 0, // sub6 |
10217 | 0 | 0, // sub7 |
10218 | 0 | 0, // sub8 |
10219 | 0 | 0, // sub9 |
10220 | 0 | 0, // sub10 |
10221 | 0 | 0, // sub11 |
10222 | 0 | 0, // sub12 |
10223 | 0 | 0, // sub13 |
10224 | 0 | 0, // sub14 |
10225 | 0 | 0, // sub15 |
10226 | 0 | }, |
10227 | 0 | { // R600_KC1_X |
10228 | 0 | 0, // sub0 |
10229 | 0 | 0, // sub1 |
10230 | 0 | 0, // sub2 |
10231 | 0 | 0, // sub3 |
10232 | 0 | 0, // sub4 |
10233 | 0 | 0, // sub5 |
10234 | 0 | 0, // sub6 |
10235 | 0 | 0, // sub7 |
10236 | 0 | 0, // sub8 |
10237 | 0 | 0, // sub9 |
10238 | 0 | 0, // sub10 |
10239 | 0 | 0, // sub11 |
10240 | 0 | 0, // sub12 |
10241 | 0 | 0, // sub13 |
10242 | 0 | 0, // sub14 |
10243 | 0 | 0, // sub15 |
10244 | 0 | }, |
10245 | 0 | { // R600_KC1_Y |
10246 | 0 | 0, // sub0 |
10247 | 0 | 0, // sub1 |
10248 | 0 | 0, // sub2 |
10249 | 0 | 0, // sub3 |
10250 | 0 | 0, // sub4 |
10251 | 0 | 0, // sub5 |
10252 | 0 | 0, // sub6 |
10253 | 0 | 0, // sub7 |
10254 | 0 | 0, // sub8 |
10255 | 0 | 0, // sub9 |
10256 | 0 | 0, // sub10 |
10257 | 0 | 0, // sub11 |
10258 | 0 | 0, // sub12 |
10259 | 0 | 0, // sub13 |
10260 | 0 | 0, // sub14 |
10261 | 0 | 0, // sub15 |
10262 | 0 | }, |
10263 | 0 | { // R600_KC1_Z |
10264 | 0 | 0, // sub0 |
10265 | 0 | 0, // sub1 |
10266 | 0 | 0, // sub2 |
10267 | 0 | 0, // sub3 |
10268 | 0 | 0, // sub4 |
10269 | 0 | 0, // sub5 |
10270 | 0 | 0, // sub6 |
10271 | 0 | 0, // sub7 |
10272 | 0 | 0, // sub8 |
10273 | 0 | 0, // sub9 |
10274 | 0 | 0, // sub10 |
10275 | 0 | 0, // sub11 |
10276 | 0 | 0, // sub12 |
10277 | 0 | 0, // sub13 |
10278 | 0 | 0, // sub14 |
10279 | 0 | 0, // sub15 |
10280 | 0 | }, |
10281 | 0 | { // R600_LDS_SRC_REG |
10282 | 0 | 0, // sub0 |
10283 | 0 | 0, // sub1 |
10284 | 0 | 0, // sub2 |
10285 | 0 | 0, // sub3 |
10286 | 0 | 0, // sub4 |
10287 | 0 | 0, // sub5 |
10288 | 0 | 0, // sub6 |
10289 | 0 | 0, // sub7 |
10290 | 0 | 0, // sub8 |
10291 | 0 | 0, // sub9 |
10292 | 0 | 0, // sub10 |
10293 | 0 | 0, // sub11 |
10294 | 0 | 0, // sub12 |
10295 | 0 | 0, // sub13 |
10296 | 0 | 0, // sub14 |
10297 | 0 | 0, // sub15 |
10298 | 0 | }, |
10299 | 0 | { // R600_Predicate |
10300 | 0 | 0, // sub0 |
10301 | 0 | 0, // sub1 |
10302 | 0 | 0, // sub2 |
10303 | 0 | 0, // sub3 |
10304 | 0 | 0, // sub4 |
10305 | 0 | 0, // sub5 |
10306 | 0 | 0, // sub6 |
10307 | 0 | 0, // sub7 |
10308 | 0 | 0, // sub8 |
10309 | 0 | 0, // sub9 |
10310 | 0 | 0, // sub10 |
10311 | 0 | 0, // sub11 |
10312 | 0 | 0, // sub12 |
10313 | 0 | 0, // sub13 |
10314 | 0 | 0, // sub14 |
10315 | 0 | 0, // sub15 |
10316 | 0 | }, |
10317 | 0 | { // R600_Addr_W |
10318 | 0 | 0, // sub0 |
10319 | 0 | 0, // sub1 |
10320 | 0 | 0, // sub2 |
10321 | 0 | 0, // sub3 |
10322 | 0 | 0, // sub4 |
10323 | 0 | 0, // sub5 |
10324 | 0 | 0, // sub6 |
10325 | 0 | 0, // sub7 |
10326 | 0 | 0, // sub8 |
10327 | 0 | 0, // sub9 |
10328 | 0 | 0, // sub10 |
10329 | 0 | 0, // sub11 |
10330 | 0 | 0, // sub12 |
10331 | 0 | 0, // sub13 |
10332 | 0 | 0, // sub14 |
10333 | 0 | 0, // sub15 |
10334 | 0 | }, |
10335 | 0 | { // R600_Addr_Y |
10336 | 0 | 0, // sub0 |
10337 | 0 | 0, // sub1 |
10338 | 0 | 0, // sub2 |
10339 | 0 | 0, // sub3 |
10340 | 0 | 0, // sub4 |
10341 | 0 | 0, // sub5 |
10342 | 0 | 0, // sub6 |
10343 | 0 | 0, // sub7 |
10344 | 0 | 0, // sub8 |
10345 | 0 | 0, // sub9 |
10346 | 0 | 0, // sub10 |
10347 | 0 | 0, // sub11 |
10348 | 0 | 0, // sub12 |
10349 | 0 | 0, // sub13 |
10350 | 0 | 0, // sub14 |
10351 | 0 | 0, // sub15 |
10352 | 0 | }, |
10353 | 0 | { // R600_Addr_Z |
10354 | 0 | 0, // sub0 |
10355 | 0 | 0, // sub1 |
10356 | 0 | 0, // sub2 |
10357 | 0 | 0, // sub3 |
10358 | 0 | 0, // sub4 |
10359 | 0 | 0, // sub5 |
10360 | 0 | 0, // sub6 |
10361 | 0 | 0, // sub7 |
10362 | 0 | 0, // sub8 |
10363 | 0 | 0, // sub9 |
10364 | 0 | 0, // sub10 |
10365 | 0 | 0, // sub11 |
10366 | 0 | 0, // sub12 |
10367 | 0 | 0, // sub13 |
10368 | 0 | 0, // sub14 |
10369 | 0 | 0, // sub15 |
10370 | 0 | }, |
10371 | 0 | { // R600_LDS_SRC_REG_and_R600_Reg32 |
10372 | 0 | 0, // sub0 |
10373 | 0 | 0, // sub1 |
10374 | 0 | 0, // sub2 |
10375 | 0 | 0, // sub3 |
10376 | 0 | 0, // sub4 |
10377 | 0 | 0, // sub5 |
10378 | 0 | 0, // sub6 |
10379 | 0 | 0, // sub7 |
10380 | 0 | 0, // sub8 |
10381 | 0 | 0, // sub9 |
10382 | 0 | 0, // sub10 |
10383 | 0 | 0, // sub11 |
10384 | 0 | 0, // sub12 |
10385 | 0 | 0, // sub13 |
10386 | 0 | 0, // sub14 |
10387 | 0 | 0, // sub15 |
10388 | 0 | }, |
10389 | 0 | { // R600_Predicate_Bit |
10390 | 0 | 0, // sub0 |
10391 | 0 | 0, // sub1 |
10392 | 0 | 0, // sub2 |
10393 | 0 | 0, // sub3 |
10394 | 0 | 0, // sub4 |
10395 | 0 | 0, // sub5 |
10396 | 0 | 0, // sub6 |
10397 | 0 | 0, // sub7 |
10398 | 0 | 0, // sub8 |
10399 | 0 | 0, // sub9 |
10400 | 0 | 0, // sub10 |
10401 | 0 | 0, // sub11 |
10402 | 0 | 0, // sub12 |
10403 | 0 | 0, // sub13 |
10404 | 0 | 0, // sub14 |
10405 | 0 | 0, // sub15 |
10406 | 0 | }, |
10407 | 0 | { // R600_Reg64 |
10408 | 0 | 26, // sub0 -> R600_Reg64 |
10409 | 0 | 26, // sub1 -> R600_Reg64 |
10410 | 0 | 0, // sub2 |
10411 | 0 | 0, // sub3 |
10412 | 0 | 0, // sub4 |
10413 | 0 | 0, // sub5 |
10414 | 0 | 0, // sub6 |
10415 | 0 | 0, // sub7 |
10416 | 0 | 0, // sub8 |
10417 | 0 | 0, // sub9 |
10418 | 0 | 0, // sub10 |
10419 | 0 | 0, // sub11 |
10420 | 0 | 0, // sub12 |
10421 | 0 | 0, // sub13 |
10422 | 0 | 0, // sub14 |
10423 | 0 | 0, // sub15 |
10424 | 0 | }, |
10425 | 0 | { // R600_Reg64Vertical |
10426 | 0 | 27, // sub0 -> R600_Reg64Vertical |
10427 | 0 | 27, // sub1 -> R600_Reg64Vertical |
10428 | 0 | 0, // sub2 |
10429 | 0 | 0, // sub3 |
10430 | 0 | 0, // sub4 |
10431 | 0 | 0, // sub5 |
10432 | 0 | 0, // sub6 |
10433 | 0 | 0, // sub7 |
10434 | 0 | 0, // sub8 |
10435 | 0 | 0, // sub9 |
10436 | 0 | 0, // sub10 |
10437 | 0 | 0, // sub11 |
10438 | 0 | 0, // sub12 |
10439 | 0 | 0, // sub13 |
10440 | 0 | 0, // sub14 |
10441 | 0 | 0, // sub15 |
10442 | 0 | }, |
10443 | 0 | { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W |
10444 | 0 | 28, // sub0 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_W |
10445 | 0 | 28, // sub1 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_W |
10446 | 0 | 0, // sub2 |
10447 | 0 | 0, // sub3 |
10448 | 0 | 0, // sub4 |
10449 | 0 | 0, // sub5 |
10450 | 0 | 0, // sub6 |
10451 | 0 | 0, // sub7 |
10452 | 0 | 0, // sub8 |
10453 | 0 | 0, // sub9 |
10454 | 0 | 0, // sub10 |
10455 | 0 | 0, // sub11 |
10456 | 0 | 0, // sub12 |
10457 | 0 | 0, // sub13 |
10458 | 0 | 0, // sub14 |
10459 | 0 | 0, // sub15 |
10460 | 0 | }, |
10461 | 0 | { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X |
10462 | 0 | 29, // sub0 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_X |
10463 | 0 | 29, // sub1 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_X |
10464 | 0 | 0, // sub2 |
10465 | 0 | 0, // sub3 |
10466 | 0 | 0, // sub4 |
10467 | 0 | 0, // sub5 |
10468 | 0 | 0, // sub6 |
10469 | 0 | 0, // sub7 |
10470 | 0 | 0, // sub8 |
10471 | 0 | 0, // sub9 |
10472 | 0 | 0, // sub10 |
10473 | 0 | 0, // sub11 |
10474 | 0 | 0, // sub12 |
10475 | 0 | 0, // sub13 |
10476 | 0 | 0, // sub14 |
10477 | 0 | 0, // sub15 |
10478 | 0 | }, |
10479 | 0 | { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y |
10480 | 0 | 30, // sub0 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y |
10481 | 0 | 30, // sub1 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y |
10482 | 0 | 0, // sub2 |
10483 | 0 | 0, // sub3 |
10484 | 0 | 0, // sub4 |
10485 | 0 | 0, // sub5 |
10486 | 0 | 0, // sub6 |
10487 | 0 | 0, // sub7 |
10488 | 0 | 0, // sub8 |
10489 | 0 | 0, // sub9 |
10490 | 0 | 0, // sub10 |
10491 | 0 | 0, // sub11 |
10492 | 0 | 0, // sub12 |
10493 | 0 | 0, // sub13 |
10494 | 0 | 0, // sub14 |
10495 | 0 | 0, // sub15 |
10496 | 0 | }, |
10497 | 0 | { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z |
10498 | 0 | 31, // sub0 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z |
10499 | 0 | 31, // sub1 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z |
10500 | 0 | 0, // sub2 |
10501 | 0 | 0, // sub3 |
10502 | 0 | 0, // sub4 |
10503 | 0 | 0, // sub5 |
10504 | 0 | 0, // sub6 |
10505 | 0 | 0, // sub7 |
10506 | 0 | 0, // sub8 |
10507 | 0 | 0, // sub9 |
10508 | 0 | 0, // sub10 |
10509 | 0 | 0, // sub11 |
10510 | 0 | 0, // sub12 |
10511 | 0 | 0, // sub13 |
10512 | 0 | 0, // sub14 |
10513 | 0 | 0, // sub15 |
10514 | 0 | }, |
10515 | 0 | { // R600_Reg128 |
10516 | 0 | 32, // sub0 -> R600_Reg128 |
10517 | 0 | 32, // sub1 -> R600_Reg128 |
10518 | 0 | 32, // sub2 -> R600_Reg128 |
10519 | 0 | 32, // sub3 -> R600_Reg128 |
10520 | 0 | 0, // sub4 |
10521 | 0 | 0, // sub5 |
10522 | 0 | 0, // sub6 |
10523 | 0 | 0, // sub7 |
10524 | 0 | 0, // sub8 |
10525 | 0 | 0, // sub9 |
10526 | 0 | 0, // sub10 |
10527 | 0 | 0, // sub11 |
10528 | 0 | 0, // sub12 |
10529 | 0 | 0, // sub13 |
10530 | 0 | 0, // sub14 |
10531 | 0 | 0, // sub15 |
10532 | 0 | }, |
10533 | 0 | { // R600_Reg128Vertical |
10534 | 0 | 33, // sub0 -> R600_Reg128Vertical |
10535 | 0 | 33, // sub1 -> R600_Reg128Vertical |
10536 | 0 | 33, // sub2 -> R600_Reg128Vertical |
10537 | 0 | 33, // sub3 -> R600_Reg128Vertical |
10538 | 0 | 0, // sub4 |
10539 | 0 | 0, // sub5 |
10540 | 0 | 0, // sub6 |
10541 | 0 | 0, // sub7 |
10542 | 0 | 0, // sub8 |
10543 | 0 | 0, // sub9 |
10544 | 0 | 0, // sub10 |
10545 | 0 | 0, // sub11 |
10546 | 0 | 0, // sub12 |
10547 | 0 | 0, // sub13 |
10548 | 0 | 0, // sub14 |
10549 | 0 | 0, // sub15 |
10550 | 0 | }, |
10551 | 0 | { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W |
10552 | 0 | 34, // sub0 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_W |
10553 | 0 | 34, // sub1 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_W |
10554 | 0 | 34, // sub2 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_W |
10555 | 0 | 34, // sub3 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_W |
10556 | 0 | 0, // sub4 |
10557 | 0 | 0, // sub5 |
10558 | 0 | 0, // sub6 |
10559 | 0 | 0, // sub7 |
10560 | 0 | 0, // sub8 |
10561 | 0 | 0, // sub9 |
10562 | 0 | 0, // sub10 |
10563 | 0 | 0, // sub11 |
10564 | 0 | 0, // sub12 |
10565 | 0 | 0, // sub13 |
10566 | 0 | 0, // sub14 |
10567 | 0 | 0, // sub15 |
10568 | 0 | }, |
10569 | 0 | { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X |
10570 | 0 | 35, // sub0 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_X |
10571 | 0 | 35, // sub1 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_X |
10572 | 0 | 35, // sub2 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_X |
10573 | 0 | 35, // sub3 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_X |
10574 | 0 | 0, // sub4 |
10575 | 0 | 0, // sub5 |
10576 | 0 | 0, // sub6 |
10577 | 0 | 0, // sub7 |
10578 | 0 | 0, // sub8 |
10579 | 0 | 0, // sub9 |
10580 | 0 | 0, // sub10 |
10581 | 0 | 0, // sub11 |
10582 | 0 | 0, // sub12 |
10583 | 0 | 0, // sub13 |
10584 | 0 | 0, // sub14 |
10585 | 0 | 0, // sub15 |
10586 | 0 | }, |
10587 | 0 | { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y |
10588 | 0 | 36, // sub0 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y |
10589 | 0 | 36, // sub1 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y |
10590 | 0 | 36, // sub2 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y |
10591 | 0 | 36, // sub3 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y |
10592 | 0 | 0, // sub4 |
10593 | 0 | 0, // sub5 |
10594 | 0 | 0, // sub6 |
10595 | 0 | 0, // sub7 |
10596 | 0 | 0, // sub8 |
10597 | 0 | 0, // sub9 |
10598 | 0 | 0, // sub10 |
10599 | 0 | 0, // sub11 |
10600 | 0 | 0, // sub12 |
10601 | 0 | 0, // sub13 |
10602 | 0 | 0, // sub14 |
10603 | 0 | 0, // sub15 |
10604 | 0 | }, |
10605 | 0 | { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z |
10606 | 0 | 37, // sub0 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z |
10607 | 0 | 37, // sub1 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z |
10608 | 0 | 37, // sub2 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z |
10609 | 0 | 37, // sub3 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z |
10610 | 0 | 0, // sub4 |
10611 | 0 | 0, // sub5 |
10612 | 0 | 0, // sub6 |
10613 | 0 | 0, // sub7 |
10614 | 0 | 0, // sub8 |
10615 | 0 | 0, // sub9 |
10616 | 0 | 0, // sub10 |
10617 | 0 | 0, // sub11 |
10618 | 0 | 0, // sub12 |
10619 | 0 | 0, // sub13 |
10620 | 0 | 0, // sub14 |
10621 | 0 | 0, // sub15 |
10622 | 0 | }, |
10623 | 0 | }; |
10624 | 0 | assert(RC && "Missing regclass"); |
10625 | 0 | if (!Idx) return RC; |
10626 | 0 | --Idx; |
10627 | 0 | assert(Idx < 16 && "Bad subreg"); |
10628 | 0 | unsigned TV = Table[RC->getID()][Idx]; |
10629 | 0 | return TV ? getRegClass(TV - 1) : nullptr; |
10630 | 0 | } |
10631 | | |
10632 | 0 | const TargetRegisterClass *R600GenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const { |
10633 | 0 | static const uint8_t Table[37][16] = { |
10634 | 0 | { // R600_Reg32 |
10635 | 0 | 0, // R600_Reg32:sub0 |
10636 | 0 | 0, // R600_Reg32:sub1 |
10637 | 0 | 0, // R600_Reg32:sub2 |
10638 | 0 | 0, // R600_Reg32:sub3 |
10639 | 0 | 0, // R600_Reg32:sub4 |
10640 | 0 | 0, // R600_Reg32:sub5 |
10641 | 0 | 0, // R600_Reg32:sub6 |
10642 | 0 | 0, // R600_Reg32:sub7 |
10643 | 0 | 0, // R600_Reg32:sub8 |
10644 | 0 | 0, // R600_Reg32:sub9 |
10645 | 0 | 0, // R600_Reg32:sub10 |
10646 | 0 | 0, // R600_Reg32:sub11 |
10647 | 0 | 0, // R600_Reg32:sub12 |
10648 | 0 | 0, // R600_Reg32:sub13 |
10649 | 0 | 0, // R600_Reg32:sub14 |
10650 | 0 | 0, // R600_Reg32:sub15 |
10651 | 0 | }, |
10652 | 0 | { // R600_TReg32 |
10653 | 0 | 0, // R600_TReg32:sub0 |
10654 | 0 | 0, // R600_TReg32:sub1 |
10655 | 0 | 0, // R600_TReg32:sub2 |
10656 | 0 | 0, // R600_TReg32:sub3 |
10657 | 0 | 0, // R600_TReg32:sub4 |
10658 | 0 | 0, // R600_TReg32:sub5 |
10659 | 0 | 0, // R600_TReg32:sub6 |
10660 | 0 | 0, // R600_TReg32:sub7 |
10661 | 0 | 0, // R600_TReg32:sub8 |
10662 | 0 | 0, // R600_TReg32:sub9 |
10663 | 0 | 0, // R600_TReg32:sub10 |
10664 | 0 | 0, // R600_TReg32:sub11 |
10665 | 0 | 0, // R600_TReg32:sub12 |
10666 | 0 | 0, // R600_TReg32:sub13 |
10667 | 0 | 0, // R600_TReg32:sub14 |
10668 | 0 | 0, // R600_TReg32:sub15 |
10669 | 0 | }, |
10670 | 0 | { // R600_TReg32_X |
10671 | 0 | 0, // R600_TReg32_X:sub0 |
10672 | 0 | 0, // R600_TReg32_X:sub1 |
10673 | 0 | 0, // R600_TReg32_X:sub2 |
10674 | 0 | 0, // R600_TReg32_X:sub3 |
10675 | 0 | 0, // R600_TReg32_X:sub4 |
10676 | 0 | 0, // R600_TReg32_X:sub5 |
10677 | 0 | 0, // R600_TReg32_X:sub6 |
10678 | 0 | 0, // R600_TReg32_X:sub7 |
10679 | 0 | 0, // R600_TReg32_X:sub8 |
10680 | 0 | 0, // R600_TReg32_X:sub9 |
10681 | 0 | 0, // R600_TReg32_X:sub10 |
10682 | 0 | 0, // R600_TReg32_X:sub11 |
10683 | 0 | 0, // R600_TReg32_X:sub12 |
10684 | 0 | 0, // R600_TReg32_X:sub13 |
10685 | 0 | 0, // R600_TReg32_X:sub14 |
10686 | 0 | 0, // R600_TReg32_X:sub15 |
10687 | 0 | }, |
10688 | 0 | { // R600_Addr |
10689 | 0 | 0, // R600_Addr:sub0 |
10690 | 0 | 0, // R600_Addr:sub1 |
10691 | 0 | 0, // R600_Addr:sub2 |
10692 | 0 | 0, // R600_Addr:sub3 |
10693 | 0 | 0, // R600_Addr:sub4 |
10694 | 0 | 0, // R600_Addr:sub5 |
10695 | 0 | 0, // R600_Addr:sub6 |
10696 | 0 | 0, // R600_Addr:sub7 |
10697 | 0 | 0, // R600_Addr:sub8 |
10698 | 0 | 0, // R600_Addr:sub9 |
10699 | 0 | 0, // R600_Addr:sub10 |
10700 | 0 | 0, // R600_Addr:sub11 |
10701 | 0 | 0, // R600_Addr:sub12 |
10702 | 0 | 0, // R600_Addr:sub13 |
10703 | 0 | 0, // R600_Addr:sub14 |
10704 | 0 | 0, // R600_Addr:sub15 |
10705 | 0 | }, |
10706 | 0 | { // R600_KC0 |
10707 | 0 | 0, // R600_KC0:sub0 |
10708 | 0 | 0, // R600_KC0:sub1 |
10709 | 0 | 0, // R600_KC0:sub2 |
10710 | 0 | 0, // R600_KC0:sub3 |
10711 | 0 | 0, // R600_KC0:sub4 |
10712 | 0 | 0, // R600_KC0:sub5 |
10713 | 0 | 0, // R600_KC0:sub6 |
10714 | 0 | 0, // R600_KC0:sub7 |
10715 | 0 | 0, // R600_KC0:sub8 |
10716 | 0 | 0, // R600_KC0:sub9 |
10717 | 0 | 0, // R600_KC0:sub10 |
10718 | 0 | 0, // R600_KC0:sub11 |
10719 | 0 | 0, // R600_KC0:sub12 |
10720 | 0 | 0, // R600_KC0:sub13 |
10721 | 0 | 0, // R600_KC0:sub14 |
10722 | 0 | 0, // R600_KC0:sub15 |
10723 | 0 | }, |
10724 | 0 | { // R600_KC1 |
10725 | 0 | 0, // R600_KC1:sub0 |
10726 | 0 | 0, // R600_KC1:sub1 |
10727 | 0 | 0, // R600_KC1:sub2 |
10728 | 0 | 0, // R600_KC1:sub3 |
10729 | 0 | 0, // R600_KC1:sub4 |
10730 | 0 | 0, // R600_KC1:sub5 |
10731 | 0 | 0, // R600_KC1:sub6 |
10732 | 0 | 0, // R600_KC1:sub7 |
10733 | 0 | 0, // R600_KC1:sub8 |
10734 | 0 | 0, // R600_KC1:sub9 |
10735 | 0 | 0, // R600_KC1:sub10 |
10736 | 0 | 0, // R600_KC1:sub11 |
10737 | 0 | 0, // R600_KC1:sub12 |
10738 | 0 | 0, // R600_KC1:sub13 |
10739 | 0 | 0, // R600_KC1:sub14 |
10740 | 0 | 0, // R600_KC1:sub15 |
10741 | 0 | }, |
10742 | 0 | { // R600_TReg32_W |
10743 | 0 | 0, // R600_TReg32_W:sub0 |
10744 | 0 | 0, // R600_TReg32_W:sub1 |
10745 | 0 | 0, // R600_TReg32_W:sub2 |
10746 | 0 | 0, // R600_TReg32_W:sub3 |
10747 | 0 | 0, // R600_TReg32_W:sub4 |
10748 | 0 | 0, // R600_TReg32_W:sub5 |
10749 | 0 | 0, // R600_TReg32_W:sub6 |
10750 | 0 | 0, // R600_TReg32_W:sub7 |
10751 | 0 | 0, // R600_TReg32_W:sub8 |
10752 | 0 | 0, // R600_TReg32_W:sub9 |
10753 | 0 | 0, // R600_TReg32_W:sub10 |
10754 | 0 | 0, // R600_TReg32_W:sub11 |
10755 | 0 | 0, // R600_TReg32_W:sub12 |
10756 | 0 | 0, // R600_TReg32_W:sub13 |
10757 | 0 | 0, // R600_TReg32_W:sub14 |
10758 | 0 | 0, // R600_TReg32_W:sub15 |
10759 | 0 | }, |
10760 | 0 | { // R600_TReg32_Y |
10761 | 0 | 0, // R600_TReg32_Y:sub0 |
10762 | 0 | 0, // R600_TReg32_Y:sub1 |
10763 | 0 | 0, // R600_TReg32_Y:sub2 |
10764 | 0 | 0, // R600_TReg32_Y:sub3 |
10765 | 0 | 0, // R600_TReg32_Y:sub4 |
10766 | 0 | 0, // R600_TReg32_Y:sub5 |
10767 | 0 | 0, // R600_TReg32_Y:sub6 |
10768 | 0 | 0, // R600_TReg32_Y:sub7 |
10769 | 0 | 0, // R600_TReg32_Y:sub8 |
10770 | 0 | 0, // R600_TReg32_Y:sub9 |
10771 | 0 | 0, // R600_TReg32_Y:sub10 |
10772 | 0 | 0, // R600_TReg32_Y:sub11 |
10773 | 0 | 0, // R600_TReg32_Y:sub12 |
10774 | 0 | 0, // R600_TReg32_Y:sub13 |
10775 | 0 | 0, // R600_TReg32_Y:sub14 |
10776 | 0 | 0, // R600_TReg32_Y:sub15 |
10777 | 0 | }, |
10778 | 0 | { // R600_TReg32_Z |
10779 | 0 | 0, // R600_TReg32_Z:sub0 |
10780 | 0 | 0, // R600_TReg32_Z:sub1 |
10781 | 0 | 0, // R600_TReg32_Z:sub2 |
10782 | 0 | 0, // R600_TReg32_Z:sub3 |
10783 | 0 | 0, // R600_TReg32_Z:sub4 |
10784 | 0 | 0, // R600_TReg32_Z:sub5 |
10785 | 0 | 0, // R600_TReg32_Z:sub6 |
10786 | 0 | 0, // R600_TReg32_Z:sub7 |
10787 | 0 | 0, // R600_TReg32_Z:sub8 |
10788 | 0 | 0, // R600_TReg32_Z:sub9 |
10789 | 0 | 0, // R600_TReg32_Z:sub10 |
10790 | 0 | 0, // R600_TReg32_Z:sub11 |
10791 | 0 | 0, // R600_TReg32_Z:sub12 |
10792 | 0 | 0, // R600_TReg32_Z:sub13 |
10793 | 0 | 0, // R600_TReg32_Z:sub14 |
10794 | 0 | 0, // R600_TReg32_Z:sub15 |
10795 | 0 | }, |
10796 | 0 | { // R600_ArrayBase |
10797 | 0 | 0, // R600_ArrayBase:sub0 |
10798 | 0 | 0, // R600_ArrayBase:sub1 |
10799 | 0 | 0, // R600_ArrayBase:sub2 |
10800 | 0 | 0, // R600_ArrayBase:sub3 |
10801 | 0 | 0, // R600_ArrayBase:sub4 |
10802 | 0 | 0, // R600_ArrayBase:sub5 |
10803 | 0 | 0, // R600_ArrayBase:sub6 |
10804 | 0 | 0, // R600_ArrayBase:sub7 |
10805 | 0 | 0, // R600_ArrayBase:sub8 |
10806 | 0 | 0, // R600_ArrayBase:sub9 |
10807 | 0 | 0, // R600_ArrayBase:sub10 |
10808 | 0 | 0, // R600_ArrayBase:sub11 |
10809 | 0 | 0, // R600_ArrayBase:sub12 |
10810 | 0 | 0, // R600_ArrayBase:sub13 |
10811 | 0 | 0, // R600_ArrayBase:sub14 |
10812 | 0 | 0, // R600_ArrayBase:sub15 |
10813 | 0 | }, |
10814 | 0 | { // R600_KC0_W |
10815 | 0 | 0, // R600_KC0_W:sub0 |
10816 | 0 | 0, // R600_KC0_W:sub1 |
10817 | 0 | 0, // R600_KC0_W:sub2 |
10818 | 0 | 0, // R600_KC0_W:sub3 |
10819 | 0 | 0, // R600_KC0_W:sub4 |
10820 | 0 | 0, // R600_KC0_W:sub5 |
10821 | 0 | 0, // R600_KC0_W:sub6 |
10822 | 0 | 0, // R600_KC0_W:sub7 |
10823 | 0 | 0, // R600_KC0_W:sub8 |
10824 | 0 | 0, // R600_KC0_W:sub9 |
10825 | 0 | 0, // R600_KC0_W:sub10 |
10826 | 0 | 0, // R600_KC0_W:sub11 |
10827 | 0 | 0, // R600_KC0_W:sub12 |
10828 | 0 | 0, // R600_KC0_W:sub13 |
10829 | 0 | 0, // R600_KC0_W:sub14 |
10830 | 0 | 0, // R600_KC0_W:sub15 |
10831 | 0 | }, |
10832 | 0 | { // R600_KC0_X |
10833 | 0 | 0, // R600_KC0_X:sub0 |
10834 | 0 | 0, // R600_KC0_X:sub1 |
10835 | 0 | 0, // R600_KC0_X:sub2 |
10836 | 0 | 0, // R600_KC0_X:sub3 |
10837 | 0 | 0, // R600_KC0_X:sub4 |
10838 | 0 | 0, // R600_KC0_X:sub5 |
10839 | 0 | 0, // R600_KC0_X:sub6 |
10840 | 0 | 0, // R600_KC0_X:sub7 |
10841 | 0 | 0, // R600_KC0_X:sub8 |
10842 | 0 | 0, // R600_KC0_X:sub9 |
10843 | 0 | 0, // R600_KC0_X:sub10 |
10844 | 0 | 0, // R600_KC0_X:sub11 |
10845 | 0 | 0, // R600_KC0_X:sub12 |
10846 | 0 | 0, // R600_KC0_X:sub13 |
10847 | 0 | 0, // R600_KC0_X:sub14 |
10848 | 0 | 0, // R600_KC0_X:sub15 |
10849 | 0 | }, |
10850 | 0 | { // R600_KC0_Y |
10851 | 0 | 0, // R600_KC0_Y:sub0 |
10852 | 0 | 0, // R600_KC0_Y:sub1 |
10853 | 0 | 0, // R600_KC0_Y:sub2 |
10854 | 0 | 0, // R600_KC0_Y:sub3 |
10855 | 0 | 0, // R600_KC0_Y:sub4 |
10856 | 0 | 0, // R600_KC0_Y:sub5 |
10857 | 0 | 0, // R600_KC0_Y:sub6 |
10858 | 0 | 0, // R600_KC0_Y:sub7 |
10859 | 0 | 0, // R600_KC0_Y:sub8 |
10860 | 0 | 0, // R600_KC0_Y:sub9 |
10861 | 0 | 0, // R600_KC0_Y:sub10 |
10862 | 0 | 0, // R600_KC0_Y:sub11 |
10863 | 0 | 0, // R600_KC0_Y:sub12 |
10864 | 0 | 0, // R600_KC0_Y:sub13 |
10865 | 0 | 0, // R600_KC0_Y:sub14 |
10866 | 0 | 0, // R600_KC0_Y:sub15 |
10867 | 0 | }, |
10868 | 0 | { // R600_KC0_Z |
10869 | 0 | 0, // R600_KC0_Z:sub0 |
10870 | 0 | 0, // R600_KC0_Z:sub1 |
10871 | 0 | 0, // R600_KC0_Z:sub2 |
10872 | 0 | 0, // R600_KC0_Z:sub3 |
10873 | 0 | 0, // R600_KC0_Z:sub4 |
10874 | 0 | 0, // R600_KC0_Z:sub5 |
10875 | 0 | 0, // R600_KC0_Z:sub6 |
10876 | 0 | 0, // R600_KC0_Z:sub7 |
10877 | 0 | 0, // R600_KC0_Z:sub8 |
10878 | 0 | 0, // R600_KC0_Z:sub9 |
10879 | 0 | 0, // R600_KC0_Z:sub10 |
10880 | 0 | 0, // R600_KC0_Z:sub11 |
10881 | 0 | 0, // R600_KC0_Z:sub12 |
10882 | 0 | 0, // R600_KC0_Z:sub13 |
10883 | 0 | 0, // R600_KC0_Z:sub14 |
10884 | 0 | 0, // R600_KC0_Z:sub15 |
10885 | 0 | }, |
10886 | 0 | { // R600_KC1_W |
10887 | 0 | 0, // R600_KC1_W:sub0 |
10888 | 0 | 0, // R600_KC1_W:sub1 |
10889 | 0 | 0, // R600_KC1_W:sub2 |
10890 | 0 | 0, // R600_KC1_W:sub3 |
10891 | 0 | 0, // R600_KC1_W:sub4 |
10892 | 0 | 0, // R600_KC1_W:sub5 |
10893 | 0 | 0, // R600_KC1_W:sub6 |
10894 | 0 | 0, // R600_KC1_W:sub7 |
10895 | 0 | 0, // R600_KC1_W:sub8 |
10896 | 0 | 0, // R600_KC1_W:sub9 |
10897 | 0 | 0, // R600_KC1_W:sub10 |
10898 | 0 | 0, // R600_KC1_W:sub11 |
10899 | 0 | 0, // R600_KC1_W:sub12 |
10900 | 0 | 0, // R600_KC1_W:sub13 |
10901 | 0 | 0, // R600_KC1_W:sub14 |
10902 | 0 | 0, // R600_KC1_W:sub15 |
10903 | 0 | }, |
10904 | 0 | { // R600_KC1_X |
10905 | 0 | 0, // R600_KC1_X:sub0 |
10906 | 0 | 0, // R600_KC1_X:sub1 |
10907 | 0 | 0, // R600_KC1_X:sub2 |
10908 | 0 | 0, // R600_KC1_X:sub3 |
10909 | 0 | 0, // R600_KC1_X:sub4 |
10910 | 0 | 0, // R600_KC1_X:sub5 |
10911 | 0 | 0, // R600_KC1_X:sub6 |
10912 | 0 | 0, // R600_KC1_X:sub7 |
10913 | 0 | 0, // R600_KC1_X:sub8 |
10914 | 0 | 0, // R600_KC1_X:sub9 |
10915 | 0 | 0, // R600_KC1_X:sub10 |
10916 | 0 | 0, // R600_KC1_X:sub11 |
10917 | 0 | 0, // R600_KC1_X:sub12 |
10918 | 0 | 0, // R600_KC1_X:sub13 |
10919 | 0 | 0, // R600_KC1_X:sub14 |
10920 | 0 | 0, // R600_KC1_X:sub15 |
10921 | 0 | }, |
10922 | 0 | { // R600_KC1_Y |
10923 | 0 | 0, // R600_KC1_Y:sub0 |
10924 | 0 | 0, // R600_KC1_Y:sub1 |
10925 | 0 | 0, // R600_KC1_Y:sub2 |
10926 | 0 | 0, // R600_KC1_Y:sub3 |
10927 | 0 | 0, // R600_KC1_Y:sub4 |
10928 | 0 | 0, // R600_KC1_Y:sub5 |
10929 | 0 | 0, // R600_KC1_Y:sub6 |
10930 | 0 | 0, // R600_KC1_Y:sub7 |
10931 | 0 | 0, // R600_KC1_Y:sub8 |
10932 | 0 | 0, // R600_KC1_Y:sub9 |
10933 | 0 | 0, // R600_KC1_Y:sub10 |
10934 | 0 | 0, // R600_KC1_Y:sub11 |
10935 | 0 | 0, // R600_KC1_Y:sub12 |
10936 | 0 | 0, // R600_KC1_Y:sub13 |
10937 | 0 | 0, // R600_KC1_Y:sub14 |
10938 | 0 | 0, // R600_KC1_Y:sub15 |
10939 | 0 | }, |
10940 | 0 | { // R600_KC1_Z |
10941 | 0 | 0, // R600_KC1_Z:sub0 |
10942 | 0 | 0, // R600_KC1_Z:sub1 |
10943 | 0 | 0, // R600_KC1_Z:sub2 |
10944 | 0 | 0, // R600_KC1_Z:sub3 |
10945 | 0 | 0, // R600_KC1_Z:sub4 |
10946 | 0 | 0, // R600_KC1_Z:sub5 |
10947 | 0 | 0, // R600_KC1_Z:sub6 |
10948 | 0 | 0, // R600_KC1_Z:sub7 |
10949 | 0 | 0, // R600_KC1_Z:sub8 |
10950 | 0 | 0, // R600_KC1_Z:sub9 |
10951 | 0 | 0, // R600_KC1_Z:sub10 |
10952 | 0 | 0, // R600_KC1_Z:sub11 |
10953 | 0 | 0, // R600_KC1_Z:sub12 |
10954 | 0 | 0, // R600_KC1_Z:sub13 |
10955 | 0 | 0, // R600_KC1_Z:sub14 |
10956 | 0 | 0, // R600_KC1_Z:sub15 |
10957 | 0 | }, |
10958 | 0 | { // R600_LDS_SRC_REG |
10959 | 0 | 0, // R600_LDS_SRC_REG:sub0 |
10960 | 0 | 0, // R600_LDS_SRC_REG:sub1 |
10961 | 0 | 0, // R600_LDS_SRC_REG:sub2 |
10962 | 0 | 0, // R600_LDS_SRC_REG:sub3 |
10963 | 0 | 0, // R600_LDS_SRC_REG:sub4 |
10964 | 0 | 0, // R600_LDS_SRC_REG:sub5 |
10965 | 0 | 0, // R600_LDS_SRC_REG:sub6 |
10966 | 0 | 0, // R600_LDS_SRC_REG:sub7 |
10967 | 0 | 0, // R600_LDS_SRC_REG:sub8 |
10968 | 0 | 0, // R600_LDS_SRC_REG:sub9 |
10969 | 0 | 0, // R600_LDS_SRC_REG:sub10 |
10970 | 0 | 0, // R600_LDS_SRC_REG:sub11 |
10971 | 0 | 0, // R600_LDS_SRC_REG:sub12 |
10972 | 0 | 0, // R600_LDS_SRC_REG:sub13 |
10973 | 0 | 0, // R600_LDS_SRC_REG:sub14 |
10974 | 0 | 0, // R600_LDS_SRC_REG:sub15 |
10975 | 0 | }, |
10976 | 0 | { // R600_Predicate |
10977 | 0 | 0, // R600_Predicate:sub0 |
10978 | 0 | 0, // R600_Predicate:sub1 |
10979 | 0 | 0, // R600_Predicate:sub2 |
10980 | 0 | 0, // R600_Predicate:sub3 |
10981 | 0 | 0, // R600_Predicate:sub4 |
10982 | 0 | 0, // R600_Predicate:sub5 |
10983 | 0 | 0, // R600_Predicate:sub6 |
10984 | 0 | 0, // R600_Predicate:sub7 |
10985 | 0 | 0, // R600_Predicate:sub8 |
10986 | 0 | 0, // R600_Predicate:sub9 |
10987 | 0 | 0, // R600_Predicate:sub10 |
10988 | 0 | 0, // R600_Predicate:sub11 |
10989 | 0 | 0, // R600_Predicate:sub12 |
10990 | 0 | 0, // R600_Predicate:sub13 |
10991 | 0 | 0, // R600_Predicate:sub14 |
10992 | 0 | 0, // R600_Predicate:sub15 |
10993 | 0 | }, |
10994 | 0 | { // R600_Addr_W |
10995 | 0 | 0, // R600_Addr_W:sub0 |
10996 | 0 | 0, // R600_Addr_W:sub1 |
10997 | 0 | 0, // R600_Addr_W:sub2 |
10998 | 0 | 0, // R600_Addr_W:sub3 |
10999 | 0 | 0, // R600_Addr_W:sub4 |
11000 | 0 | 0, // R600_Addr_W:sub5 |
11001 | 0 | 0, // R600_Addr_W:sub6 |
11002 | 0 | 0, // R600_Addr_W:sub7 |
11003 | 0 | 0, // R600_Addr_W:sub8 |
11004 | 0 | 0, // R600_Addr_W:sub9 |
11005 | 0 | 0, // R600_Addr_W:sub10 |
11006 | 0 | 0, // R600_Addr_W:sub11 |
11007 | 0 | 0, // R600_Addr_W:sub12 |
11008 | 0 | 0, // R600_Addr_W:sub13 |
11009 | 0 | 0, // R600_Addr_W:sub14 |
11010 | 0 | 0, // R600_Addr_W:sub15 |
11011 | 0 | }, |
11012 | 0 | { // R600_Addr_Y |
11013 | 0 | 0, // R600_Addr_Y:sub0 |
11014 | 0 | 0, // R600_Addr_Y:sub1 |
11015 | 0 | 0, // R600_Addr_Y:sub2 |
11016 | 0 | 0, // R600_Addr_Y:sub3 |
11017 | 0 | 0, // R600_Addr_Y:sub4 |
11018 | 0 | 0, // R600_Addr_Y:sub5 |
11019 | 0 | 0, // R600_Addr_Y:sub6 |
11020 | 0 | 0, // R600_Addr_Y:sub7 |
11021 | 0 | 0, // R600_Addr_Y:sub8 |
11022 | 0 | 0, // R600_Addr_Y:sub9 |
11023 | 0 | 0, // R600_Addr_Y:sub10 |
11024 | 0 | 0, // R600_Addr_Y:sub11 |
11025 | 0 | 0, // R600_Addr_Y:sub12 |
11026 | 0 | 0, // R600_Addr_Y:sub13 |
11027 | 0 | 0, // R600_Addr_Y:sub14 |
11028 | 0 | 0, // R600_Addr_Y:sub15 |
11029 | 0 | }, |
11030 | 0 | { // R600_Addr_Z |
11031 | 0 | 0, // R600_Addr_Z:sub0 |
11032 | 0 | 0, // R600_Addr_Z:sub1 |
11033 | 0 | 0, // R600_Addr_Z:sub2 |
11034 | 0 | 0, // R600_Addr_Z:sub3 |
11035 | 0 | 0, // R600_Addr_Z:sub4 |
11036 | 0 | 0, // R600_Addr_Z:sub5 |
11037 | 0 | 0, // R600_Addr_Z:sub6 |
11038 | 0 | 0, // R600_Addr_Z:sub7 |
11039 | 0 | 0, // R600_Addr_Z:sub8 |
11040 | 0 | 0, // R600_Addr_Z:sub9 |
11041 | 0 | 0, // R600_Addr_Z:sub10 |
11042 | 0 | 0, // R600_Addr_Z:sub11 |
11043 | 0 | 0, // R600_Addr_Z:sub12 |
11044 | 0 | 0, // R600_Addr_Z:sub13 |
11045 | 0 | 0, // R600_Addr_Z:sub14 |
11046 | 0 | 0, // R600_Addr_Z:sub15 |
11047 | 0 | }, |
11048 | 0 | { // R600_LDS_SRC_REG_and_R600_Reg32 |
11049 | 0 | 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub0 |
11050 | 0 | 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub1 |
11051 | 0 | 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub2 |
11052 | 0 | 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub3 |
11053 | 0 | 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub4 |
11054 | 0 | 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub5 |
11055 | 0 | 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub6 |
11056 | 0 | 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub7 |
11057 | 0 | 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub8 |
11058 | 0 | 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub9 |
11059 | 0 | 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub10 |
11060 | 0 | 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub11 |
11061 | 0 | 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub12 |
11062 | 0 | 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub13 |
11063 | 0 | 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub14 |
11064 | 0 | 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub15 |
11065 | 0 | }, |
11066 | 0 | { // R600_Predicate_Bit |
11067 | 0 | 0, // R600_Predicate_Bit:sub0 |
11068 | 0 | 0, // R600_Predicate_Bit:sub1 |
11069 | 0 | 0, // R600_Predicate_Bit:sub2 |
11070 | 0 | 0, // R600_Predicate_Bit:sub3 |
11071 | 0 | 0, // R600_Predicate_Bit:sub4 |
11072 | 0 | 0, // R600_Predicate_Bit:sub5 |
11073 | 0 | 0, // R600_Predicate_Bit:sub6 |
11074 | 0 | 0, // R600_Predicate_Bit:sub7 |
11075 | 0 | 0, // R600_Predicate_Bit:sub8 |
11076 | 0 | 0, // R600_Predicate_Bit:sub9 |
11077 | 0 | 0, // R600_Predicate_Bit:sub10 |
11078 | 0 | 0, // R600_Predicate_Bit:sub11 |
11079 | 0 | 0, // R600_Predicate_Bit:sub12 |
11080 | 0 | 0, // R600_Predicate_Bit:sub13 |
11081 | 0 | 0, // R600_Predicate_Bit:sub14 |
11082 | 0 | 0, // R600_Predicate_Bit:sub15 |
11083 | 0 | }, |
11084 | 0 | { // R600_Reg64 |
11085 | 0 | 3, // R600_Reg64:sub0 -> R600_TReg32_X |
11086 | 0 | 8, // R600_Reg64:sub1 -> R600_TReg32_Y |
11087 | 0 | 0, // R600_Reg64:sub2 |
11088 | 0 | 0, // R600_Reg64:sub3 |
11089 | 0 | 0, // R600_Reg64:sub4 |
11090 | 0 | 0, // R600_Reg64:sub5 |
11091 | 0 | 0, // R600_Reg64:sub6 |
11092 | 0 | 0, // R600_Reg64:sub7 |
11093 | 0 | 0, // R600_Reg64:sub8 |
11094 | 0 | 0, // R600_Reg64:sub9 |
11095 | 0 | 0, // R600_Reg64:sub10 |
11096 | 0 | 0, // R600_Reg64:sub11 |
11097 | 0 | 0, // R600_Reg64:sub12 |
11098 | 0 | 0, // R600_Reg64:sub13 |
11099 | 0 | 0, // R600_Reg64:sub14 |
11100 | 0 | 0, // R600_Reg64:sub15 |
11101 | 0 | }, |
11102 | 0 | { // R600_Reg64Vertical |
11103 | 0 | 2, // R600_Reg64Vertical:sub0 -> R600_TReg32 |
11104 | 0 | 2, // R600_Reg64Vertical:sub1 -> R600_TReg32 |
11105 | 0 | 0, // R600_Reg64Vertical:sub2 |
11106 | 0 | 0, // R600_Reg64Vertical:sub3 |
11107 | 0 | 0, // R600_Reg64Vertical:sub4 |
11108 | 0 | 0, // R600_Reg64Vertical:sub5 |
11109 | 0 | 0, // R600_Reg64Vertical:sub6 |
11110 | 0 | 0, // R600_Reg64Vertical:sub7 |
11111 | 0 | 0, // R600_Reg64Vertical:sub8 |
11112 | 0 | 0, // R600_Reg64Vertical:sub9 |
11113 | 0 | 0, // R600_Reg64Vertical:sub10 |
11114 | 0 | 0, // R600_Reg64Vertical:sub11 |
11115 | 0 | 0, // R600_Reg64Vertical:sub12 |
11116 | 0 | 0, // R600_Reg64Vertical:sub13 |
11117 | 0 | 0, // R600_Reg64Vertical:sub14 |
11118 | 0 | 0, // R600_Reg64Vertical:sub15 |
11119 | 0 | }, |
11120 | 0 | { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W |
11121 | 0 | 7, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub0 -> R600_TReg32_W |
11122 | 0 | 7, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub1 -> R600_TReg32_W |
11123 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub2 |
11124 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub3 |
11125 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub4 |
11126 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub5 |
11127 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub6 |
11128 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub7 |
11129 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub8 |
11130 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub9 |
11131 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub10 |
11132 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub11 |
11133 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub12 |
11134 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub13 |
11135 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub14 |
11136 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub15 |
11137 | 0 | }, |
11138 | 0 | { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X |
11139 | 0 | 3, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub0 -> R600_TReg32_X |
11140 | 0 | 3, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub1 -> R600_TReg32_X |
11141 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub2 |
11142 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub3 |
11143 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub4 |
11144 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub5 |
11145 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub6 |
11146 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub7 |
11147 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub8 |
11148 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub9 |
11149 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub10 |
11150 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub11 |
11151 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub12 |
11152 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub13 |
11153 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub14 |
11154 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub15 |
11155 | 0 | }, |
11156 | 0 | { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y |
11157 | 0 | 8, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub0 -> R600_TReg32_Y |
11158 | 0 | 8, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub1 -> R600_TReg32_Y |
11159 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub2 |
11160 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub3 |
11161 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub4 |
11162 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub5 |
11163 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub6 |
11164 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub7 |
11165 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub8 |
11166 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub9 |
11167 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub10 |
11168 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub11 |
11169 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub12 |
11170 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub13 |
11171 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub14 |
11172 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub15 |
11173 | 0 | }, |
11174 | 0 | { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z |
11175 | 0 | 9, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub0 -> R600_TReg32_Z |
11176 | 0 | 9, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub1 -> R600_TReg32_Z |
11177 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub2 |
11178 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub3 |
11179 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub4 |
11180 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub5 |
11181 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub6 |
11182 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub7 |
11183 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub8 |
11184 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub9 |
11185 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub10 |
11186 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub11 |
11187 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub12 |
11188 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub13 |
11189 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub14 |
11190 | 0 | 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub15 |
11191 | 0 | }, |
11192 | 0 | { // R600_Reg128 |
11193 | 0 | 3, // R600_Reg128:sub0 -> R600_TReg32_X |
11194 | 0 | 8, // R600_Reg128:sub1 -> R600_TReg32_Y |
11195 | 0 | 9, // R600_Reg128:sub2 -> R600_TReg32_Z |
11196 | 0 | 7, // R600_Reg128:sub3 -> R600_TReg32_W |
11197 | 0 | 0, // R600_Reg128:sub4 |
11198 | 0 | 0, // R600_Reg128:sub5 |
11199 | 0 | 0, // R600_Reg128:sub6 |
11200 | 0 | 0, // R600_Reg128:sub7 |
11201 | 0 | 0, // R600_Reg128:sub8 |
11202 | 0 | 0, // R600_Reg128:sub9 |
11203 | 0 | 0, // R600_Reg128:sub10 |
11204 | 0 | 0, // R600_Reg128:sub11 |
11205 | 0 | 0, // R600_Reg128:sub12 |
11206 | 0 | 0, // R600_Reg128:sub13 |
11207 | 0 | 0, // R600_Reg128:sub14 |
11208 | 0 | 0, // R600_Reg128:sub15 |
11209 | 0 | }, |
11210 | 0 | { // R600_Reg128Vertical |
11211 | 0 | 2, // R600_Reg128Vertical:sub0 -> R600_TReg32 |
11212 | 0 | 2, // R600_Reg128Vertical:sub1 -> R600_TReg32 |
11213 | 0 | 2, // R600_Reg128Vertical:sub2 -> R600_TReg32 |
11214 | 0 | 2, // R600_Reg128Vertical:sub3 -> R600_TReg32 |
11215 | 0 | 0, // R600_Reg128Vertical:sub4 |
11216 | 0 | 0, // R600_Reg128Vertical:sub5 |
11217 | 0 | 0, // R600_Reg128Vertical:sub6 |
11218 | 0 | 0, // R600_Reg128Vertical:sub7 |
11219 | 0 | 0, // R600_Reg128Vertical:sub8 |
11220 | 0 | 0, // R600_Reg128Vertical:sub9 |
11221 | 0 | 0, // R600_Reg128Vertical:sub10 |
11222 | 0 | 0, // R600_Reg128Vertical:sub11 |
11223 | 0 | 0, // R600_Reg128Vertical:sub12 |
11224 | 0 | 0, // R600_Reg128Vertical:sub13 |
11225 | 0 | 0, // R600_Reg128Vertical:sub14 |
11226 | 0 | 0, // R600_Reg128Vertical:sub15 |
11227 | 0 | }, |
11228 | 0 | { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W |
11229 | 0 | 7, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub0 -> R600_TReg32_W |
11230 | 0 | 7, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub1 -> R600_TReg32_W |
11231 | 0 | 7, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub2 -> R600_TReg32_W |
11232 | 0 | 7, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub3 -> R600_TReg32_W |
11233 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub4 |
11234 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub5 |
11235 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub6 |
11236 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub7 |
11237 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub8 |
11238 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub9 |
11239 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub10 |
11240 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub11 |
11241 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub12 |
11242 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub13 |
11243 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub14 |
11244 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub15 |
11245 | 0 | }, |
11246 | 0 | { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X |
11247 | 0 | 3, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub0 -> R600_TReg32_X |
11248 | 0 | 3, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub1 -> R600_TReg32_X |
11249 | 0 | 3, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub2 -> R600_TReg32_X |
11250 | 0 | 3, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub3 -> R600_TReg32_X |
11251 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub4 |
11252 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub5 |
11253 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub6 |
11254 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub7 |
11255 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub8 |
11256 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub9 |
11257 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub10 |
11258 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub11 |
11259 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub12 |
11260 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub13 |
11261 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub14 |
11262 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub15 |
11263 | 0 | }, |
11264 | 0 | { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y |
11265 | 0 | 8, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub0 -> R600_TReg32_Y |
11266 | 0 | 8, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub1 -> R600_TReg32_Y |
11267 | 0 | 8, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub2 -> R600_TReg32_Y |
11268 | 0 | 8, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub3 -> R600_TReg32_Y |
11269 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub4 |
11270 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub5 |
11271 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub6 |
11272 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub7 |
11273 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub8 |
11274 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub9 |
11275 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub10 |
11276 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub11 |
11277 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub12 |
11278 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub13 |
11279 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub14 |
11280 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub15 |
11281 | 0 | }, |
11282 | 0 | { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z |
11283 | 0 | 9, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub0 -> R600_TReg32_Z |
11284 | 0 | 9, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub1 -> R600_TReg32_Z |
11285 | 0 | 9, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub2 -> R600_TReg32_Z |
11286 | 0 | 9, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub3 -> R600_TReg32_Z |
11287 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub4 |
11288 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub5 |
11289 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub6 |
11290 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub7 |
11291 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub8 |
11292 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub9 |
11293 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub10 |
11294 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub11 |
11295 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub12 |
11296 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub13 |
11297 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub14 |
11298 | 0 | 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub15 |
11299 | 0 | }, |
11300 | 0 | }; |
11301 | 0 | assert(RC && "Missing regclass"); |
11302 | 0 | if (!Idx) return RC; |
11303 | 0 | --Idx; |
11304 | 0 | assert(Idx < 16 && "Bad subreg"); |
11305 | 0 | unsigned TV = Table[RC->getID()][Idx]; |
11306 | 0 | return TV ? getRegClass(TV - 1) : nullptr; |
11307 | 0 | } |
11308 | | |
11309 | | /// Get the weight in units of pressure for this register class. |
11310 | | const RegClassWeight &R600GenRegisterInfo:: |
11311 | 0 | getRegClassWeight(const TargetRegisterClass *RC) const { |
11312 | 0 | static const RegClassWeight RCWeightTable[] = { |
11313 | 0 | {0, 942}, // R600_Reg32 |
11314 | 0 | {0, 513}, // R600_TReg32 |
11315 | 0 | {0, 129}, // R600_TReg32_X |
11316 | 0 | {0, 128}, // R600_Addr |
11317 | 0 | {0, 128}, // R600_KC0 |
11318 | 0 | {0, 128}, // R600_KC1 |
11319 | 0 | {0, 128}, // R600_TReg32_W |
11320 | 0 | {0, 128}, // R600_TReg32_Y |
11321 | 0 | {0, 128}, // R600_TReg32_Z |
11322 | 0 | {0, 33}, // R600_ArrayBase |
11323 | 0 | {0, 32}, // R600_KC0_W |
11324 | 0 | {0, 32}, // R600_KC0_X |
11325 | 0 | {0, 32}, // R600_KC0_Y |
11326 | 0 | {0, 32}, // R600_KC0_Z |
11327 | 0 | {0, 32}, // R600_KC1_W |
11328 | 0 | {0, 32}, // R600_KC1_X |
11329 | 0 | {0, 32}, // R600_KC1_Y |
11330 | 0 | {0, 32}, // R600_KC1_Z |
11331 | 0 | {0, 1}, // R600_LDS_SRC_REG |
11332 | 0 | {0, 3}, // R600_Predicate |
11333 | 0 | {0, 0}, // R600_Addr_W |
11334 | 0 | {0, 0}, // R600_Addr_Y |
11335 | 0 | {0, 0}, // R600_Addr_Z |
11336 | 0 | {1, 1}, // R600_LDS_SRC_REG_and_R600_Reg32 |
11337 | 0 | {0, 1}, // R600_Predicate_Bit |
11338 | 0 | {0, 128}, // R600_Reg64 |
11339 | 0 | {0, 16}, // R600_Reg64Vertical |
11340 | 0 | {2, 4}, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W |
11341 | 0 | {2, 4}, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X |
11342 | 0 | {2, 4}, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y |
11343 | 0 | {2, 4}, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z |
11344 | 0 | {0, 512}, // R600_Reg128 |
11345 | 0 | {0, 16}, // R600_Reg128Vertical |
11346 | 0 | {4, 4}, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W |
11347 | 0 | {4, 4}, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X |
11348 | 0 | {4, 4}, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y |
11349 | 0 | {4, 4}, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z |
11350 | 0 | }; |
11351 | 0 | return RCWeightTable[RC->getID()]; |
11352 | 0 | } |
11353 | | |
11354 | | /// Get the weight in units of pressure for this register unit. |
11355 | | unsigned R600GenRegisterInfo:: |
11356 | 0 | getRegUnitWeight(unsigned RegUnit) const { |
11357 | 0 | assert(RegUnit < 1342 && "invalid register unit"); |
11358 | | // All register units have unit weight. |
11359 | 0 | return 1; |
11360 | 0 | } |
11361 | | |
11362 | | |
11363 | | // Get the number of dimensions of register pressure. |
11364 | 0 | unsigned R600GenRegisterInfo::getNumRegPressureSets() const { |
11365 | 0 | return 23; |
11366 | 0 | } |
11367 | | |
11368 | | // Get the name of this register unit pressure set. |
11369 | | const char *R600GenRegisterInfo:: |
11370 | 0 | getRegPressureSetName(unsigned Idx) const { |
11371 | 0 | static const char *PressureNameTable[] = { |
11372 | 0 | "R600_LDS_SRC_REG_and_R600_Reg32", |
11373 | 0 | "R600_Predicate_Bit", |
11374 | 0 | "R600_Predicate", |
11375 | 0 | "R600_Reg64Vertical_with_sub0_in_R600_TReg32_W", |
11376 | 0 | "R600_Reg64Vertical_with_sub0_in_R600_TReg32_X", |
11377 | 0 | "R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y", |
11378 | 0 | "R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z", |
11379 | 0 | "R600_Reg64Vertical", |
11380 | 0 | "R600_ArrayBase", |
11381 | 0 | "R600_TReg32_W", |
11382 | 0 | "R600_TReg32_Y", |
11383 | 0 | "R600_TReg32_Z", |
11384 | 0 | "R600_Reg64", |
11385 | 0 | "R600_TReg32_X", |
11386 | 0 | "R600_Reg64_with_R600_Reg64Vertical", |
11387 | 0 | "R600_TReg32_W_with_R600_Reg64Vertical", |
11388 | 0 | "R600_TReg32_Y_with_R600_Reg64Vertical", |
11389 | 0 | "R600_TReg32_Z_with_R600_Reg64Vertical", |
11390 | 0 | "R600_TReg32_X_with_R600_Reg64Vertical", |
11391 | 0 | "R600_TReg32_Y_with_R600_Reg64", |
11392 | 0 | "R600_TReg32_X_with_R600_Reg64", |
11393 | 0 | "R600_TReg32", |
11394 | 0 | "R600_Reg32", |
11395 | 0 | }; |
11396 | 0 | return PressureNameTable[Idx]; |
11397 | 0 | } |
11398 | | |
11399 | | // Get the register unit pressure limit for this dimension. |
11400 | | // This limit must be adjusted dynamically for reserved registers. |
11401 | | unsigned R600GenRegisterInfo:: |
11402 | 0 | getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const { |
11403 | 0 | static const uint16_t PressureLimitTable[] = { |
11404 | 0 | 1, // 0: R600_LDS_SRC_REG_and_R600_Reg32 |
11405 | 0 | 1, // 1: R600_Predicate_Bit |
11406 | 0 | 3, // 2: R600_Predicate |
11407 | 0 | 4, // 3: R600_Reg64Vertical_with_sub0_in_R600_TReg32_W |
11408 | 0 | 4, // 4: R600_Reg64Vertical_with_sub0_in_R600_TReg32_X |
11409 | 0 | 4, // 5: R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y |
11410 | 0 | 4, // 6: R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z |
11411 | 0 | 16, // 7: R600_Reg64Vertical |
11412 | 0 | 33, // 8: R600_ArrayBase |
11413 | 0 | 128, // 9: R600_TReg32_W |
11414 | 0 | 128, // 10: R600_TReg32_Y |
11415 | 0 | 128, // 11: R600_TReg32_Z |
11416 | 0 | 128, // 12: R600_Reg64 |
11417 | 0 | 129, // 13: R600_TReg32_X |
11418 | 0 | 136, // 14: R600_Reg64_with_R600_Reg64Vertical |
11419 | 0 | 140, // 15: R600_TReg32_W_with_R600_Reg64Vertical |
11420 | 0 | 140, // 16: R600_TReg32_Y_with_R600_Reg64Vertical |
11421 | 0 | 140, // 17: R600_TReg32_Z_with_R600_Reg64Vertical |
11422 | 0 | 141, // 18: R600_TReg32_X_with_R600_Reg64Vertical |
11423 | 0 | 192, // 19: R600_TReg32_Y_with_R600_Reg64 |
11424 | 0 | 193, // 20: R600_TReg32_X_with_R600_Reg64 |
11425 | 0 | 513, // 21: R600_TReg32 |
11426 | 0 | 942, // 22: R600_Reg32 |
11427 | 0 | }; |
11428 | 0 | return PressureLimitTable[Idx]; |
11429 | 0 | } |
11430 | | |
11431 | | /// Table of pressure sets per register class or unit. |
11432 | | static const int RCSetsTable[] = { |
11433 | | /* 0 */ 1, -1, |
11434 | | /* 2 */ 2, -1, |
11435 | | /* 4 */ 0, 22, -1, |
11436 | | /* 7 */ 8, 22, -1, |
11437 | | /* 10 */ 9, 15, 21, 22, -1, |
11438 | | /* 15 */ 11, 17, 21, 22, -1, |
11439 | | /* 20 */ 7, 14, 15, 16, 17, 18, 21, 22, -1, |
11440 | | /* 29 */ 3, 7, 9, 14, 15, 16, 17, 18, 21, 22, -1, |
11441 | | /* 40 */ 6, 7, 11, 14, 15, 16, 17, 18, 21, 22, -1, |
11442 | | /* 51 */ 10, 16, 19, 21, 22, -1, |
11443 | | /* 57 */ 13, 18, 20, 21, 22, -1, |
11444 | | /* 63 */ 12, 14, 19, 20, 21, 22, -1, |
11445 | | /* 70 */ 10, 12, 14, 16, 19, 20, 21, 22, -1, |
11446 | | /* 79 */ 12, 13, 14, 18, 19, 20, 21, 22, -1, |
11447 | | /* 88 */ 5, 7, 10, 12, 14, 15, 16, 17, 18, 19, 20, 21, 22, -1, |
11448 | | /* 102 */ 4, 7, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, -1, |
11449 | | }; |
11450 | | |
11451 | | /// Get the dimensions of register pressure impacted by this register class. |
11452 | | /// Returns a -1 terminated array of pressure set IDs |
11453 | | const int *R600GenRegisterInfo:: |
11454 | 0 | getRegClassPressureSets(const TargetRegisterClass *RC) const { |
11455 | 0 | static const uint8_t RCSetStartTable[] = { |
11456 | 0 | 5,12,57,1,1,1,10,51,15,7,1,1,1,1,1,1,1,1,1,2,1,1,1,4,0,63,20,29,102,88,40,12,20,29,102,88,40,}; |
11457 | 0 | return &RCSetsTable[RCSetStartTable[RC->getID()]]; |
11458 | 0 | } |
11459 | | |
11460 | | /// Get the dimensions of register pressure impacted by this register unit. |
11461 | | /// Returns a -1 terminated array of pressure set IDs |
11462 | | const int *R600GenRegisterInfo:: |
11463 | 0 | getRegUnitPressureSets(unsigned RegUnit) const { |
11464 | 0 | assert(RegUnit < 1342 && "invalid register unit"); |
11465 | 0 | static const uint8_t RUSetStartTable[] = { |
11466 | 0 | 5,1,5,1,1,5,57,5,5,1,1,5,5,5,5,1,4,1,1,0,2,2,2,1,1,5,1,1,5,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,29,29,29,29,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,102,102,102,102,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,88,88,88,88,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,40,40,40,40,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,}; |
11467 | 0 | return &RCSetsTable[RUSetStartTable[RegUnit]]; |
11468 | 0 | } |
11469 | | |
11470 | | extern const MCRegisterDesc R600RegDesc[]; |
11471 | | extern const int16_t R600RegDiffLists[]; |
11472 | | extern const LaneBitmask R600LaneMaskLists[]; |
11473 | | extern const char R600RegStrings[]; |
11474 | | extern const char R600RegClassStrings[]; |
11475 | | extern const MCPhysReg R600RegUnitRoots[][2]; |
11476 | | extern const uint16_t R600SubRegIdxLists[]; |
11477 | | extern const MCRegisterInfo::SubRegCoveredBits R600SubRegIdxRanges[]; |
11478 | | extern const uint16_t R600RegEncodingTable[]; |
11479 | | R600GenRegisterInfo:: |
11480 | | R600GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, |
11481 | | unsigned PC, unsigned HwMode) |
11482 | | : TargetRegisterInfo(&R600RegInfoDesc, RegisterClasses, RegisterClasses+37, |
11483 | | SubRegIndexNameTable, SubRegIndexLaneMaskTable, |
11484 | 0 | LaneBitmask(0xFFFFFFFFFFFFFFF0), RegClassInfos, VTLists, HwMode) { |
11485 | 0 | InitMCRegisterInfo(R600RegDesc, 1675, RA, PC, |
11486 | 0 | R600MCRegisterClasses, 37, |
11487 | 0 | R600RegUnitRoots, |
11488 | 0 | 1342, |
11489 | 0 | R600RegDiffLists, |
11490 | 0 | R600LaneMaskLists, |
11491 | 0 | R600RegStrings, |
11492 | 0 | R600RegClassStrings, |
11493 | 0 | R600SubRegIdxLists, |
11494 | 0 | 17, |
11495 | 0 | R600SubRegIdxRanges, |
11496 | 0 | R600RegEncodingTable); |
11497 | |
|
11498 | 0 | } |
11499 | | |
11500 | | |
11501 | | |
11502 | 0 | ArrayRef<const uint32_t *> R600GenRegisterInfo::getRegMasks() const { |
11503 | 0 | return std::nullopt; |
11504 | 0 | } |
11505 | | |
11506 | | bool R600GenRegisterInfo:: |
11507 | 0 | isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const { |
11508 | 0 | return |
11509 | 0 | false; |
11510 | 0 | } |
11511 | | |
11512 | | bool R600GenRegisterInfo:: |
11513 | 0 | isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const { |
11514 | 0 | return |
11515 | 0 | false; |
11516 | 0 | } |
11517 | | |
11518 | | bool R600GenRegisterInfo:: |
11519 | 0 | isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const { |
11520 | 0 | return |
11521 | 0 | false; |
11522 | 0 | } |
11523 | | |
11524 | | bool R600GenRegisterInfo:: |
11525 | 0 | isConstantPhysReg(MCRegister PhysReg) const { |
11526 | 0 | return |
11527 | 0 | false; |
11528 | 0 | } |
11529 | | |
11530 | 0 | ArrayRef<const char *> R600GenRegisterInfo::getRegMaskNames() const { |
11531 | 0 | return std::nullopt; |
11532 | 0 | } |
11533 | | |
11534 | | const R600FrameLowering * |
11535 | 0 | R600GenRegisterInfo::getFrameLowering(const MachineFunction &MF) { |
11536 | 0 | return static_cast<const R600FrameLowering *>( |
11537 | 0 | MF.getSubtarget().getFrameLowering()); |
11538 | 0 | } |
11539 | | |
11540 | | } // end namespace llvm |
11541 | | |
11542 | | #endif // GET_REGINFO_TARGET_DESC |
11543 | | |