/src/build/lib/Target/ARM/ARMGenCallingConv.inc
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1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Calling Convention Implementation Fragment *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | #ifndef GET_CC_REGISTER_LISTS |
10 | | |
11 | | bool llvm::CC_ARM_AAPCS(unsigned ValNo, MVT ValVT, |
12 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
13 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
14 | | static bool CC_ARM_AAPCS_Common(unsigned ValNo, MVT ValVT, |
15 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
16 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
17 | | bool llvm::CC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT, |
18 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
19 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
20 | | bool llvm::CC_ARM_APCS(unsigned ValNo, MVT ValVT, |
21 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
22 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
23 | | bool llvm::CC_ARM_APCS_GHC(unsigned ValNo, MVT ValVT, |
24 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
25 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
26 | | bool llvm::CC_ARM_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT, |
27 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
28 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
29 | | bool llvm::FastCC_ARM_APCS(unsigned ValNo, MVT ValVT, |
30 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
31 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
32 | | bool llvm::RetCC_ARM_AAPCS(unsigned ValNo, MVT ValVT, |
33 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
34 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
35 | | static bool RetCC_ARM_AAPCS_Common(unsigned ValNo, MVT ValVT, |
36 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
37 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
38 | | bool llvm::RetCC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT, |
39 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
40 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
41 | | bool llvm::RetCC_ARM_APCS(unsigned ValNo, MVT ValVT, |
42 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
43 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
44 | | bool llvm::RetFastCC_ARM_APCS(unsigned ValNo, MVT ValVT, |
45 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
46 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
47 | | |
48 | | |
49 | | bool llvm::CC_ARM_AAPCS(unsigned ValNo, MVT ValVT, |
50 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
51 | 36.1k | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
52 | | |
53 | 36.1k | if (ArgFlags.isByVal()) { |
54 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, Align(4), ArgFlags); |
55 | 0 | return false; |
56 | 0 | } |
57 | | |
58 | 36.1k | if (ArgFlags.isNest()) { |
59 | 0 | if (unsigned Reg = State.AllocateReg(ARM::R12)) { |
60 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
61 | 0 | return false; |
62 | 0 | } |
63 | 0 | } |
64 | | |
65 | 36.1k | if (LocVT == MVT::v1i64 || |
66 | 36.1k | LocVT == MVT::v2i32 || |
67 | 36.1k | LocVT == MVT::v4i16 || |
68 | 36.1k | LocVT == MVT::v4f16 || |
69 | 36.1k | LocVT == MVT::v4bf16 || |
70 | 36.1k | LocVT == MVT::v8i8 || |
71 | 36.1k | LocVT == MVT::v2f32) { |
72 | 0 | LocVT = MVT::f64; |
73 | 0 | LocInfo = CCValAssign::BCvt; |
74 | 0 | } |
75 | | |
76 | 36.1k | if (LocVT == MVT::v2i64 || |
77 | 36.1k | LocVT == MVT::v4i32 || |
78 | 36.1k | LocVT == MVT::v8i16 || |
79 | 36.1k | LocVT == MVT::v8f16 || |
80 | 36.1k | LocVT == MVT::v8bf16 || |
81 | 36.1k | LocVT == MVT::v16i8 || |
82 | 36.1k | LocVT == MVT::v4f32) { |
83 | 0 | LocVT = MVT::v2f64; |
84 | 0 | LocInfo = CCValAssign::BCvt; |
85 | 0 | } |
86 | | |
87 | 36.1k | if (ArgFlags.isSwiftSelf()) { |
88 | 0 | if (LocVT == MVT::i32) { |
89 | 0 | if (unsigned Reg = State.AllocateReg(ARM::R10)) { |
90 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
91 | 0 | return false; |
92 | 0 | } |
93 | 0 | } |
94 | 0 | } |
95 | | |
96 | 36.1k | if (ArgFlags.isSwiftError()) { |
97 | 0 | if (LocVT == MVT::i32) { |
98 | 0 | if (unsigned Reg = State.AllocateReg(ARM::R8)) { |
99 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
100 | 0 | return false; |
101 | 0 | } |
102 | 0 | } |
103 | 0 | } |
104 | | |
105 | 36.1k | if (LocVT == MVT::f64 || |
106 | 36.1k | LocVT == MVT::v2f64) { |
107 | 0 | if (CC_ARM_AAPCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
108 | 0 | return false; |
109 | 0 | } |
110 | | |
111 | 36.1k | if (LocVT == MVT::f32) { |
112 | 0 | LocVT = MVT::i32; |
113 | 0 | LocInfo = CCValAssign::BCvt; |
114 | 0 | } |
115 | | |
116 | 36.1k | if (LocVT == MVT::f16 || |
117 | 36.1k | LocVT == MVT::bf16) { |
118 | 0 | if (CC_ARM_AAPCS_Custom_f16(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
119 | 0 | return false; |
120 | 0 | } |
121 | | |
122 | 36.1k | if (!CC_ARM_AAPCS_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
123 | 36.1k | return false; |
124 | | |
125 | 0 | return true; // CC didn't match. |
126 | 36.1k | } |
127 | | |
128 | | |
129 | | static bool CC_ARM_AAPCS_Common(unsigned ValNo, MVT ValVT, |
130 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
131 | 36.1k | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
132 | | |
133 | 36.1k | if (LocVT == MVT::i1 || |
134 | 36.1k | LocVT == MVT::i8 || |
135 | 36.1k | LocVT == MVT::i16) { |
136 | 0 | LocVT = MVT::i32; |
137 | 0 | if (ArgFlags.isSExt()) |
138 | 0 | LocInfo = CCValAssign::SExt; |
139 | 0 | else if (ArgFlags.isZExt()) |
140 | 0 | LocInfo = CCValAssign::ZExt; |
141 | 0 | else |
142 | 0 | LocInfo = CCValAssign::AExt; |
143 | 0 | } |
144 | | |
145 | 36.1k | if (LocVT == MVT::i32) { |
146 | 36.1k | if (ArgFlags.getNonZeroOrigAlign() == 8) { |
147 | 12.0k | static const MCPhysReg RegList1[] = { |
148 | 12.0k | ARM::R0, ARM::R2 |
149 | 12.0k | }; |
150 | 12.0k | static const MCPhysReg RegList2[] = { |
151 | 12.0k | ARM::R0, ARM::R1 |
152 | 12.0k | }; |
153 | 12.0k | if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) { |
154 | 11.2k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
155 | 11.2k | return false; |
156 | 11.2k | } |
157 | 12.0k | } |
158 | 36.1k | } |
159 | | |
160 | 24.9k | if (LocVT == MVT::i32) { |
161 | 24.9k | if (ArgFlags.getNonZeroOrigAlign() != Align(8)) { |
162 | 24.0k | static const MCPhysReg RegList3[] = { |
163 | 24.0k | ARM::R0, ARM::R1, ARM::R2, ARM::R3 |
164 | 24.0k | }; |
165 | 24.0k | if (unsigned Reg = State.AllocateReg(RegList3)) { |
166 | 21.4k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
167 | 21.4k | return false; |
168 | 21.4k | } |
169 | 24.0k | } |
170 | 24.9k | } |
171 | | |
172 | 3.47k | if (LocVT == MVT::i32) { |
173 | 3.47k | if (ArgFlags.getNonZeroOrigAlign() == 8) { |
174 | 855 | static const MCPhysReg ShadowRegList4[] = { |
175 | 855 | ARM::R0, ARM::R1, ARM::R2, ARM::R3 |
176 | 855 | }; |
177 | 855 | int64_t Offset5 = State.AllocateStack(4, Align(8), ShadowRegList4); |
178 | 855 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo)); |
179 | 855 | return false; |
180 | 855 | } |
181 | 3.47k | } |
182 | | |
183 | 2.61k | if (LocVT == MVT::i32) { |
184 | 2.61k | static const MCPhysReg ShadowRegList6[] = { |
185 | 2.61k | ARM::R0, ARM::R1, ARM::R2, ARM::R3 |
186 | 2.61k | }; |
187 | 2.61k | int64_t Offset7 = State.AllocateStack(4, Align(4), ShadowRegList6); |
188 | 2.61k | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo)); |
189 | 2.61k | return false; |
190 | 2.61k | } |
191 | | |
192 | 0 | if (LocVT == MVT::f16 || |
193 | 0 | LocVT == MVT::bf16 || |
194 | 0 | LocVT == MVT::f32) { |
195 | 0 | static const MCPhysReg ShadowRegList8[] = { |
196 | 0 | ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 |
197 | 0 | }; |
198 | 0 | int64_t Offset9 = State.AllocateStack(4, Align(4), ShadowRegList8); |
199 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo)); |
200 | 0 | return false; |
201 | 0 | } |
202 | | |
203 | 0 | if (LocVT == MVT::f64) { |
204 | 0 | static const MCPhysReg ShadowRegList10[] = { |
205 | 0 | ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 |
206 | 0 | }; |
207 | 0 | int64_t Offset11 = State.AllocateStack(8, Align(8), ShadowRegList10); |
208 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo)); |
209 | 0 | return false; |
210 | 0 | } |
211 | | |
212 | 0 | if (LocVT == MVT::v2f64) { |
213 | 0 | if (ArgFlags.getNonZeroOrigAlign() == 16) { |
214 | 0 | static const MCPhysReg ShadowRegList12[] = { |
215 | 0 | ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 |
216 | 0 | }; |
217 | 0 | int64_t Offset13 = State.AllocateStack(16, Align(16), ShadowRegList12); |
218 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo)); |
219 | 0 | return false; |
220 | 0 | } |
221 | 0 | } |
222 | | |
223 | 0 | if (LocVT == MVT::v2f64) { |
224 | 0 | static const MCPhysReg ShadowRegList14[] = { |
225 | 0 | ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 |
226 | 0 | }; |
227 | 0 | int64_t Offset15 = State.AllocateStack(16, Align(8), ShadowRegList14); |
228 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset15, LocVT, LocInfo)); |
229 | 0 | return false; |
230 | 0 | } |
231 | | |
232 | 0 | return true; // CC didn't match. |
233 | 0 | } |
234 | | |
235 | | |
236 | | bool llvm::CC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT, |
237 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
238 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
239 | |
|
240 | 0 | if (ArgFlags.isByVal()) { |
241 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, Align(4), ArgFlags); |
242 | 0 | return false; |
243 | 0 | } |
244 | | |
245 | 0 | if (LocVT == MVT::v1i64 || |
246 | 0 | LocVT == MVT::v2i32 || |
247 | 0 | LocVT == MVT::v4i16 || |
248 | 0 | LocVT == MVT::v4f16 || |
249 | 0 | LocVT == MVT::v4bf16 || |
250 | 0 | LocVT == MVT::v8i8 || |
251 | 0 | LocVT == MVT::v2f32) { |
252 | 0 | LocVT = MVT::f64; |
253 | 0 | LocInfo = CCValAssign::BCvt; |
254 | 0 | } |
255 | |
|
256 | 0 | if (LocVT == MVT::v2i64 || |
257 | 0 | LocVT == MVT::v4i32 || |
258 | 0 | LocVT == MVT::v8i16 || |
259 | 0 | LocVT == MVT::v8f16 || |
260 | 0 | LocVT == MVT::v8bf16 || |
261 | 0 | LocVT == MVT::v16i8 || |
262 | 0 | LocVT == MVT::v4f32) { |
263 | 0 | LocVT = MVT::v2f64; |
264 | 0 | LocInfo = CCValAssign::BCvt; |
265 | 0 | } |
266 | |
|
267 | 0 | if (ArgFlags.isSwiftSelf()) { |
268 | 0 | if (LocVT == MVT::i32) { |
269 | 0 | if (unsigned Reg = State.AllocateReg(ARM::R10)) { |
270 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
271 | 0 | return false; |
272 | 0 | } |
273 | 0 | } |
274 | 0 | } |
275 | | |
276 | 0 | if (ArgFlags.isSwiftError()) { |
277 | 0 | if (LocVT == MVT::i32) { |
278 | 0 | if (unsigned Reg = State.AllocateReg(ARM::R8)) { |
279 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
280 | 0 | return false; |
281 | 0 | } |
282 | 0 | } |
283 | 0 | } |
284 | | |
285 | 0 | if (ArgFlags.isInConsecutiveRegs()) { |
286 | 0 | if (CC_ARM_AAPCS_Custom_Aggregate(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
287 | 0 | return false; |
288 | 0 | } |
289 | | |
290 | 0 | if (LocVT == MVT::v2f64) { |
291 | 0 | static const MCPhysReg RegList1[] = { |
292 | 0 | ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 |
293 | 0 | }; |
294 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
295 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
296 | 0 | return false; |
297 | 0 | } |
298 | 0 | } |
299 | | |
300 | 0 | if (LocVT == MVT::f64) { |
301 | 0 | static const MCPhysReg RegList2[] = { |
302 | 0 | ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7 |
303 | 0 | }; |
304 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
305 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
306 | 0 | return false; |
307 | 0 | } |
308 | 0 | } |
309 | | |
310 | 0 | if (LocVT == MVT::f32) { |
311 | 0 | static const MCPhysReg RegList3[] = { |
312 | 0 | ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15 |
313 | 0 | }; |
314 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
315 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
316 | 0 | return false; |
317 | 0 | } |
318 | 0 | } |
319 | | |
320 | 0 | if (LocVT == MVT::f16 || |
321 | 0 | LocVT == MVT::bf16) { |
322 | 0 | if (CC_ARM_AAPCS_VFP_Custom_f16(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
323 | 0 | return false; |
324 | 0 | } |
325 | | |
326 | 0 | if (!CC_ARM_AAPCS_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
327 | 0 | return false; |
328 | | |
329 | 0 | return true; // CC didn't match. |
330 | 0 | } |
331 | | |
332 | | |
333 | | bool llvm::CC_ARM_APCS(unsigned ValNo, MVT ValVT, |
334 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
335 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
336 | |
|
337 | 0 | if (ArgFlags.isByVal()) { |
338 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, Align(4), ArgFlags); |
339 | 0 | return false; |
340 | 0 | } |
341 | | |
342 | 0 | if (LocVT == MVT::i1 || |
343 | 0 | LocVT == MVT::i8 || |
344 | 0 | LocVT == MVT::i16) { |
345 | 0 | LocVT = MVT::i32; |
346 | 0 | if (ArgFlags.isSExt()) |
347 | 0 | LocInfo = CCValAssign::SExt; |
348 | 0 | else if (ArgFlags.isZExt()) |
349 | 0 | LocInfo = CCValAssign::ZExt; |
350 | 0 | else |
351 | 0 | LocInfo = CCValAssign::AExt; |
352 | 0 | } |
353 | |
|
354 | 0 | if (ArgFlags.isSwiftSelf()) { |
355 | 0 | if (LocVT == MVT::i32) { |
356 | 0 | if (unsigned Reg = State.AllocateReg(ARM::R10)) { |
357 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
358 | 0 | return false; |
359 | 0 | } |
360 | 0 | } |
361 | 0 | } |
362 | | |
363 | 0 | if (ArgFlags.isSwiftError()) { |
364 | 0 | if (LocVT == MVT::i32) { |
365 | 0 | if (unsigned Reg = State.AllocateReg(ARM::R8)) { |
366 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
367 | 0 | return false; |
368 | 0 | } |
369 | 0 | } |
370 | 0 | } |
371 | | |
372 | 0 | if (LocVT == MVT::v1i64 || |
373 | 0 | LocVT == MVT::v2i32 || |
374 | 0 | LocVT == MVT::v4i16 || |
375 | 0 | LocVT == MVT::v4f16 || |
376 | 0 | LocVT == MVT::v4bf16 || |
377 | 0 | LocVT == MVT::v8i8 || |
378 | 0 | LocVT == MVT::v2f32) { |
379 | 0 | LocVT = MVT::f64; |
380 | 0 | LocInfo = CCValAssign::BCvt; |
381 | 0 | } |
382 | |
|
383 | 0 | if (LocVT == MVT::v2i64 || |
384 | 0 | LocVT == MVT::v4i32 || |
385 | 0 | LocVT == MVT::v8i16 || |
386 | 0 | LocVT == MVT::v8f16 || |
387 | 0 | LocVT == MVT::v8bf16 || |
388 | 0 | LocVT == MVT::v16i8 || |
389 | 0 | LocVT == MVT::v4f32) { |
390 | 0 | LocVT = MVT::v2f64; |
391 | 0 | LocInfo = CCValAssign::BCvt; |
392 | 0 | } |
393 | |
|
394 | 0 | if (LocVT == MVT::f64 || |
395 | 0 | LocVT == MVT::v2f64) { |
396 | 0 | if (CC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
397 | 0 | return false; |
398 | 0 | } |
399 | | |
400 | 0 | if (LocVT == MVT::f32) { |
401 | 0 | LocVT = MVT::i32; |
402 | 0 | LocInfo = CCValAssign::BCvt; |
403 | 0 | } |
404 | |
|
405 | 0 | if (LocVT == MVT::i32) { |
406 | 0 | static const MCPhysReg RegList1[] = { |
407 | 0 | ARM::R0, ARM::R1, ARM::R2, ARM::R3 |
408 | 0 | }; |
409 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
410 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
411 | 0 | return false; |
412 | 0 | } |
413 | 0 | } |
414 | | |
415 | 0 | if (LocVT == MVT::i32) { |
416 | 0 | int64_t Offset2 = State.AllocateStack(4, Align(4)); |
417 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); |
418 | 0 | return false; |
419 | 0 | } |
420 | | |
421 | 0 | if (LocVT == MVT::f64) { |
422 | 0 | int64_t Offset3 = State.AllocateStack(8, Align(4)); |
423 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo)); |
424 | 0 | return false; |
425 | 0 | } |
426 | | |
427 | 0 | if (LocVT == MVT::v2f64) { |
428 | 0 | int64_t Offset4 = State.AllocateStack(16, Align(4)); |
429 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo)); |
430 | 0 | return false; |
431 | 0 | } |
432 | | |
433 | 0 | return true; // CC didn't match. |
434 | 0 | } |
435 | | |
436 | | |
437 | | bool llvm::CC_ARM_APCS_GHC(unsigned ValNo, MVT ValVT, |
438 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
439 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
440 | |
|
441 | 0 | if (LocVT == MVT::v1i64 || |
442 | 0 | LocVT == MVT::v2i32 || |
443 | 0 | LocVT == MVT::v4i16 || |
444 | 0 | LocVT == MVT::v4f16 || |
445 | 0 | LocVT == MVT::v4bf16 || |
446 | 0 | LocVT == MVT::v8i8 || |
447 | 0 | LocVT == MVT::v2f32) { |
448 | 0 | LocVT = MVT::f64; |
449 | 0 | LocInfo = CCValAssign::BCvt; |
450 | 0 | } |
451 | |
|
452 | 0 | if (LocVT == MVT::v2i64 || |
453 | 0 | LocVT == MVT::v4i32 || |
454 | 0 | LocVT == MVT::v8i16 || |
455 | 0 | LocVT == MVT::v8f16 || |
456 | 0 | LocVT == MVT::v8bf16 || |
457 | 0 | LocVT == MVT::v16i8 || |
458 | 0 | LocVT == MVT::v4f32) { |
459 | 0 | LocVT = MVT::v2f64; |
460 | 0 | LocInfo = CCValAssign::BCvt; |
461 | 0 | } |
462 | |
|
463 | 0 | if (LocVT == MVT::v2f64) { |
464 | 0 | static const MCPhysReg RegList1[] = { |
465 | 0 | ARM::Q4, ARM::Q5 |
466 | 0 | }; |
467 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
468 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
469 | 0 | return false; |
470 | 0 | } |
471 | 0 | } |
472 | | |
473 | 0 | if (LocVT == MVT::f64) { |
474 | 0 | static const MCPhysReg RegList2[] = { |
475 | 0 | ARM::D8, ARM::D9, ARM::D10, ARM::D11 |
476 | 0 | }; |
477 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
478 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
479 | 0 | return false; |
480 | 0 | } |
481 | 0 | } |
482 | | |
483 | 0 | if (LocVT == MVT::f32) { |
484 | 0 | static const MCPhysReg RegList3[] = { |
485 | 0 | ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23 |
486 | 0 | }; |
487 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
488 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
489 | 0 | return false; |
490 | 0 | } |
491 | 0 | } |
492 | | |
493 | 0 | if (LocVT == MVT::i8 || |
494 | 0 | LocVT == MVT::i16) { |
495 | 0 | LocVT = MVT::i32; |
496 | 0 | if (ArgFlags.isSExt()) |
497 | 0 | LocInfo = CCValAssign::SExt; |
498 | 0 | else if (ArgFlags.isZExt()) |
499 | 0 | LocInfo = CCValAssign::ZExt; |
500 | 0 | else |
501 | 0 | LocInfo = CCValAssign::AExt; |
502 | 0 | } |
503 | |
|
504 | 0 | if (LocVT == MVT::i32) { |
505 | 0 | static const MCPhysReg RegList4[] = { |
506 | 0 | ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11 |
507 | 0 | }; |
508 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
509 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
510 | 0 | return false; |
511 | 0 | } |
512 | 0 | } |
513 | | |
514 | 0 | return true; // CC didn't match. |
515 | 0 | } |
516 | | |
517 | | |
518 | | bool llvm::CC_ARM_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT, |
519 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
520 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
521 | |
|
522 | 0 | if (LocVT == MVT::i32) { |
523 | 0 | if (unsigned Reg = State.AllocateReg(ARM::R0)) { |
524 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
525 | 0 | return false; |
526 | 0 | } |
527 | 0 | } |
528 | | |
529 | 0 | return true; // CC didn't match. |
530 | 0 | } |
531 | | |
532 | | |
533 | | bool llvm::FastCC_ARM_APCS(unsigned ValNo, MVT ValVT, |
534 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
535 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
536 | |
|
537 | 0 | if (LocVT == MVT::v1i64 || |
538 | 0 | LocVT == MVT::v2i32 || |
539 | 0 | LocVT == MVT::v4i16 || |
540 | 0 | LocVT == MVT::v4f16 || |
541 | 0 | LocVT == MVT::v4bf16 || |
542 | 0 | LocVT == MVT::v8i8 || |
543 | 0 | LocVT == MVT::v2f32) { |
544 | 0 | LocVT = MVT::f64; |
545 | 0 | LocInfo = CCValAssign::BCvt; |
546 | 0 | } |
547 | |
|
548 | 0 | if (LocVT == MVT::v2i64 || |
549 | 0 | LocVT == MVT::v4i32 || |
550 | 0 | LocVT == MVT::v8i16 || |
551 | 0 | LocVT == MVT::v8f16 || |
552 | 0 | LocVT == MVT::v8bf16 || |
553 | 0 | LocVT == MVT::v16i8 || |
554 | 0 | LocVT == MVT::v4f32) { |
555 | 0 | LocVT = MVT::v2f64; |
556 | 0 | LocInfo = CCValAssign::BCvt; |
557 | 0 | } |
558 | |
|
559 | 0 | if (LocVT == MVT::v2f64) { |
560 | 0 | static const MCPhysReg RegList1[] = { |
561 | 0 | ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 |
562 | 0 | }; |
563 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
564 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
565 | 0 | return false; |
566 | 0 | } |
567 | 0 | } |
568 | | |
569 | 0 | if (LocVT == MVT::f64) { |
570 | 0 | static const MCPhysReg RegList2[] = { |
571 | 0 | ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7 |
572 | 0 | }; |
573 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
574 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
575 | 0 | return false; |
576 | 0 | } |
577 | 0 | } |
578 | | |
579 | 0 | if (LocVT == MVT::f32) { |
580 | 0 | static const MCPhysReg RegList3[] = { |
581 | 0 | ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15 |
582 | 0 | }; |
583 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
584 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
585 | 0 | return false; |
586 | 0 | } |
587 | 0 | } |
588 | | |
589 | 0 | if (LocVT == MVT::f32) { |
590 | 0 | static const MCPhysReg ShadowRegList4[] = { |
591 | 0 | ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 |
592 | 0 | }; |
593 | 0 | int64_t Offset5 = State.AllocateStack(4, Align(4), ShadowRegList4); |
594 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo)); |
595 | 0 | return false; |
596 | 0 | } |
597 | | |
598 | 0 | if (LocVT == MVT::f64) { |
599 | 0 | static const MCPhysReg ShadowRegList6[] = { |
600 | 0 | ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 |
601 | 0 | }; |
602 | 0 | int64_t Offset7 = State.AllocateStack(8, Align(4), ShadowRegList6); |
603 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo)); |
604 | 0 | return false; |
605 | 0 | } |
606 | | |
607 | 0 | if (LocVT == MVT::v2f64) { |
608 | 0 | static const MCPhysReg ShadowRegList8[] = { |
609 | 0 | ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 |
610 | 0 | }; |
611 | 0 | int64_t Offset9 = State.AllocateStack(16, Align(4), ShadowRegList8); |
612 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo)); |
613 | 0 | return false; |
614 | 0 | } |
615 | | |
616 | 0 | if (!CC_ARM_APCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
617 | 0 | return false; |
618 | | |
619 | 0 | return true; // CC didn't match. |
620 | 0 | } |
621 | | |
622 | | |
623 | | bool llvm::RetCC_ARM_AAPCS(unsigned ValNo, MVT ValVT, |
624 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
625 | 28.4k | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
626 | | |
627 | 28.4k | if (LocVT == MVT::v1i64 || |
628 | 28.4k | LocVT == MVT::v2i32 || |
629 | 28.4k | LocVT == MVT::v4i16 || |
630 | 28.4k | LocVT == MVT::v4f16 || |
631 | 28.4k | LocVT == MVT::v4bf16 || |
632 | 28.4k | LocVT == MVT::v8i8 || |
633 | 28.4k | LocVT == MVT::v2f32) { |
634 | 0 | LocVT = MVT::f64; |
635 | 0 | LocInfo = CCValAssign::BCvt; |
636 | 0 | } |
637 | | |
638 | 28.4k | if (LocVT == MVT::v2i64 || |
639 | 28.4k | LocVT == MVT::v4i32 || |
640 | 28.4k | LocVT == MVT::v8i16 || |
641 | 28.4k | LocVT == MVT::v8f16 || |
642 | 28.4k | LocVT == MVT::v8bf16 || |
643 | 28.4k | LocVT == MVT::v16i8 || |
644 | 28.4k | LocVT == MVT::v4f32) { |
645 | 0 | LocVT = MVT::v2f64; |
646 | 0 | LocInfo = CCValAssign::BCvt; |
647 | 0 | } |
648 | | |
649 | 28.4k | if (ArgFlags.isSwiftSelf()) { |
650 | 0 | if (LocVT == MVT::i32) { |
651 | 0 | if (unsigned Reg = State.AllocateReg(ARM::R10)) { |
652 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
653 | 0 | return false; |
654 | 0 | } |
655 | 0 | } |
656 | 0 | } |
657 | | |
658 | 28.4k | if (ArgFlags.isSwiftError()) { |
659 | 0 | if (LocVT == MVT::i32) { |
660 | 0 | if (unsigned Reg = State.AllocateReg(ARM::R8)) { |
661 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
662 | 0 | return false; |
663 | 0 | } |
664 | 0 | } |
665 | 0 | } |
666 | | |
667 | 28.4k | if (LocVT == MVT::f64 || |
668 | 28.4k | LocVT == MVT::v2f64) { |
669 | 0 | if (RetCC_ARM_AAPCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
670 | 0 | return false; |
671 | 0 | } |
672 | | |
673 | 28.4k | if (LocVT == MVT::f32) { |
674 | 0 | LocVT = MVT::i32; |
675 | 0 | LocInfo = CCValAssign::BCvt; |
676 | 0 | } |
677 | | |
678 | 28.4k | if (LocVT == MVT::f16 || |
679 | 28.4k | LocVT == MVT::bf16) { |
680 | 0 | if (CC_ARM_AAPCS_Custom_f16(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
681 | 0 | return false; |
682 | 0 | } |
683 | | |
684 | 28.4k | if (!RetCC_ARM_AAPCS_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
685 | 28.4k | return false; |
686 | | |
687 | 0 | return true; // CC didn't match. |
688 | 28.4k | } |
689 | | |
690 | | |
691 | | static bool RetCC_ARM_AAPCS_Common(unsigned ValNo, MVT ValVT, |
692 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
693 | 28.4k | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
694 | | |
695 | 28.4k | if (LocVT == MVT::i1 || |
696 | 28.4k | LocVT == MVT::i8 || |
697 | 28.4k | LocVT == MVT::i16) { |
698 | 0 | LocVT = MVT::i32; |
699 | 0 | if (ArgFlags.isSExt()) |
700 | 0 | LocInfo = CCValAssign::SExt; |
701 | 0 | else if (ArgFlags.isZExt()) |
702 | 0 | LocInfo = CCValAssign::ZExt; |
703 | 0 | else |
704 | 0 | LocInfo = CCValAssign::AExt; |
705 | 0 | } |
706 | | |
707 | 28.4k | if (LocVT == MVT::i32) { |
708 | 28.4k | static const MCPhysReg RegList1[] = { |
709 | 28.4k | ARM::R0, ARM::R1, ARM::R2, ARM::R3 |
710 | 28.4k | }; |
711 | 28.4k | if (unsigned Reg = State.AllocateReg(RegList1)) { |
712 | 28.4k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
713 | 28.4k | return false; |
714 | 28.4k | } |
715 | 28.4k | } |
716 | | |
717 | 0 | if (LocVT == MVT::i64) { |
718 | 0 | static const MCPhysReg RegList2[] = { |
719 | 0 | ARM::R0, ARM::R2 |
720 | 0 | }; |
721 | 0 | static const MCPhysReg RegList3[] = { |
722 | 0 | ARM::R1, ARM::R3 |
723 | 0 | }; |
724 | 0 | if (unsigned Reg = State.AllocateReg(RegList2, RegList3)) { |
725 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
726 | 0 | return false; |
727 | 0 | } |
728 | 0 | } |
729 | | |
730 | 0 | return true; // CC didn't match. |
731 | 0 | } |
732 | | |
733 | | |
734 | | bool llvm::RetCC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT, |
735 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
736 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
737 | |
|
738 | 0 | if (LocVT == MVT::v1i64 || |
739 | 0 | LocVT == MVT::v2i32 || |
740 | 0 | LocVT == MVT::v4i16 || |
741 | 0 | LocVT == MVT::v4f16 || |
742 | 0 | LocVT == MVT::v4bf16 || |
743 | 0 | LocVT == MVT::v8i8 || |
744 | 0 | LocVT == MVT::v2f32) { |
745 | 0 | LocVT = MVT::f64; |
746 | 0 | LocInfo = CCValAssign::BCvt; |
747 | 0 | } |
748 | |
|
749 | 0 | if (LocVT == MVT::v2i64 || |
750 | 0 | LocVT == MVT::v4i32 || |
751 | 0 | LocVT == MVT::v8i16 || |
752 | 0 | LocVT == MVT::v8f16 || |
753 | 0 | LocVT == MVT::v8bf16 || |
754 | 0 | LocVT == MVT::v16i8 || |
755 | 0 | LocVT == MVT::v4f32) { |
756 | 0 | LocVT = MVT::v2f64; |
757 | 0 | LocInfo = CCValAssign::BCvt; |
758 | 0 | } |
759 | |
|
760 | 0 | if (ArgFlags.isSwiftSelf()) { |
761 | 0 | if (LocVT == MVT::i32) { |
762 | 0 | if (unsigned Reg = State.AllocateReg(ARM::R10)) { |
763 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
764 | 0 | return false; |
765 | 0 | } |
766 | 0 | } |
767 | 0 | } |
768 | | |
769 | 0 | if (ArgFlags.isSwiftError()) { |
770 | 0 | if (LocVT == MVT::i32) { |
771 | 0 | if (unsigned Reg = State.AllocateReg(ARM::R8)) { |
772 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
773 | 0 | return false; |
774 | 0 | } |
775 | 0 | } |
776 | 0 | } |
777 | | |
778 | 0 | if (LocVT == MVT::v2f64) { |
779 | 0 | static const MCPhysReg RegList1[] = { |
780 | 0 | ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 |
781 | 0 | }; |
782 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
783 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
784 | 0 | return false; |
785 | 0 | } |
786 | 0 | } |
787 | | |
788 | 0 | if (LocVT == MVT::f64) { |
789 | 0 | static const MCPhysReg RegList2[] = { |
790 | 0 | ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7 |
791 | 0 | }; |
792 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
793 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
794 | 0 | return false; |
795 | 0 | } |
796 | 0 | } |
797 | | |
798 | 0 | if (LocVT == MVT::f32) { |
799 | 0 | static const MCPhysReg RegList3[] = { |
800 | 0 | ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15 |
801 | 0 | }; |
802 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
803 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
804 | 0 | return false; |
805 | 0 | } |
806 | 0 | } |
807 | | |
808 | 0 | if (LocVT == MVT::f16 || |
809 | 0 | LocVT == MVT::bf16) { |
810 | 0 | if (CC_ARM_AAPCS_VFP_Custom_f16(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
811 | 0 | return false; |
812 | 0 | } |
813 | | |
814 | 0 | if (!RetCC_ARM_AAPCS_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
815 | 0 | return false; |
816 | | |
817 | 0 | return true; // CC didn't match. |
818 | 0 | } |
819 | | |
820 | | |
821 | | bool llvm::RetCC_ARM_APCS(unsigned ValNo, MVT ValVT, |
822 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
823 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
824 | |
|
825 | 0 | if (LocVT == MVT::i1 || |
826 | 0 | LocVT == MVT::i8 || |
827 | 0 | LocVT == MVT::i16) { |
828 | 0 | LocVT = MVT::i32; |
829 | 0 | if (ArgFlags.isSExt()) |
830 | 0 | LocInfo = CCValAssign::SExt; |
831 | 0 | else if (ArgFlags.isZExt()) |
832 | 0 | LocInfo = CCValAssign::ZExt; |
833 | 0 | else |
834 | 0 | LocInfo = CCValAssign::AExt; |
835 | 0 | } |
836 | |
|
837 | 0 | if (LocVT == MVT::f32) { |
838 | 0 | LocVT = MVT::i32; |
839 | 0 | LocInfo = CCValAssign::BCvt; |
840 | 0 | } |
841 | |
|
842 | 0 | if (ArgFlags.isSwiftSelf()) { |
843 | 0 | if (LocVT == MVT::i32) { |
844 | 0 | if (unsigned Reg = State.AllocateReg(ARM::R10)) { |
845 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
846 | 0 | return false; |
847 | 0 | } |
848 | 0 | } |
849 | 0 | } |
850 | | |
851 | 0 | if (ArgFlags.isSwiftError()) { |
852 | 0 | if (LocVT == MVT::i32) { |
853 | 0 | if (unsigned Reg = State.AllocateReg(ARM::R8)) { |
854 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
855 | 0 | return false; |
856 | 0 | } |
857 | 0 | } |
858 | 0 | } |
859 | | |
860 | 0 | if (LocVT == MVT::v1i64 || |
861 | 0 | LocVT == MVT::v2i32 || |
862 | 0 | LocVT == MVT::v4i16 || |
863 | 0 | LocVT == MVT::v4f16 || |
864 | 0 | LocVT == MVT::v4bf16 || |
865 | 0 | LocVT == MVT::v8i8 || |
866 | 0 | LocVT == MVT::v2f32) { |
867 | 0 | LocVT = MVT::f64; |
868 | 0 | LocInfo = CCValAssign::BCvt; |
869 | 0 | } |
870 | |
|
871 | 0 | if (LocVT == MVT::v2i64 || |
872 | 0 | LocVT == MVT::v4i32 || |
873 | 0 | LocVT == MVT::v8i16 || |
874 | 0 | LocVT == MVT::v8f16 || |
875 | 0 | LocVT == MVT::v8bf16 || |
876 | 0 | LocVT == MVT::v16i8 || |
877 | 0 | LocVT == MVT::v4f32) { |
878 | 0 | LocVT = MVT::v2f64; |
879 | 0 | LocInfo = CCValAssign::BCvt; |
880 | 0 | } |
881 | |
|
882 | 0 | if (LocVT == MVT::f64 || |
883 | 0 | LocVT == MVT::v2f64) { |
884 | 0 | if (RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
885 | 0 | return false; |
886 | 0 | } |
887 | | |
888 | 0 | if (LocVT == MVT::i32) { |
889 | 0 | static const MCPhysReg RegList1[] = { |
890 | 0 | ARM::R0, ARM::R1, ARM::R2, ARM::R3 |
891 | 0 | }; |
892 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
893 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
894 | 0 | return false; |
895 | 0 | } |
896 | 0 | } |
897 | | |
898 | 0 | if (LocVT == MVT::i64) { |
899 | 0 | static const MCPhysReg RegList2[] = { |
900 | 0 | ARM::R0, ARM::R2 |
901 | 0 | }; |
902 | 0 | static const MCPhysReg RegList3[] = { |
903 | 0 | ARM::R1, ARM::R3 |
904 | 0 | }; |
905 | 0 | if (unsigned Reg = State.AllocateReg(RegList2, RegList3)) { |
906 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
907 | 0 | return false; |
908 | 0 | } |
909 | 0 | } |
910 | | |
911 | 0 | return true; // CC didn't match. |
912 | 0 | } |
913 | | |
914 | | |
915 | | bool llvm::RetFastCC_ARM_APCS(unsigned ValNo, MVT ValVT, |
916 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
917 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
918 | |
|
919 | 0 | if (LocVT == MVT::v1i64 || |
920 | 0 | LocVT == MVT::v2i32 || |
921 | 0 | LocVT == MVT::v4i16 || |
922 | 0 | LocVT == MVT::v4f16 || |
923 | 0 | LocVT == MVT::v4bf16 || |
924 | 0 | LocVT == MVT::v8i8 || |
925 | 0 | LocVT == MVT::v2f32) { |
926 | 0 | LocVT = MVT::f64; |
927 | 0 | LocInfo = CCValAssign::BCvt; |
928 | 0 | } |
929 | |
|
930 | 0 | if (LocVT == MVT::v2i64 || |
931 | 0 | LocVT == MVT::v4i32 || |
932 | 0 | LocVT == MVT::v8i16 || |
933 | 0 | LocVT == MVT::v8f16 || |
934 | 0 | LocVT == MVT::v8bf16 || |
935 | 0 | LocVT == MVT::v16i8 || |
936 | 0 | LocVT == MVT::v4f32) { |
937 | 0 | LocVT = MVT::v2f64; |
938 | 0 | LocInfo = CCValAssign::BCvt; |
939 | 0 | } |
940 | |
|
941 | 0 | if (LocVT == MVT::v2f64) { |
942 | 0 | static const MCPhysReg RegList1[] = { |
943 | 0 | ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 |
944 | 0 | }; |
945 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
946 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
947 | 0 | return false; |
948 | 0 | } |
949 | 0 | } |
950 | | |
951 | 0 | if (LocVT == MVT::f64) { |
952 | 0 | static const MCPhysReg RegList2[] = { |
953 | 0 | ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7 |
954 | 0 | }; |
955 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
956 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
957 | 0 | return false; |
958 | 0 | } |
959 | 0 | } |
960 | | |
961 | 0 | if (LocVT == MVT::f32) { |
962 | 0 | static const MCPhysReg RegList3[] = { |
963 | 0 | ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15 |
964 | 0 | }; |
965 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
966 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
967 | 0 | return false; |
968 | 0 | } |
969 | 0 | } |
970 | | |
971 | 0 | if (!RetCC_ARM_APCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
972 | 0 | return false; |
973 | | |
974 | 0 | return true; // CC didn't match. |
975 | 0 | } |
976 | | |
977 | | #else |
978 | | |
979 | | const MCRegister CC_ARM_AAPCS_ArgRegs[] = { ARM::R12 }; |
980 | | const MCRegister CC_ARM_AAPCS_Common_ArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; |
981 | | const MCRegister CC_ARM_AAPCS_VFP_ArgRegs[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::S0, ARM::S1, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9 }; |
982 | | const MCRegister CC_ARM_APCS_ArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; |
983 | | const MCRegister CC_ARM_APCS_GHC_ArgRegs[] = { ARM::D10, ARM::D11, ARM::D8, ARM::D9, ARM::Q4, ARM::Q5, ARM::R10, ARM::R11, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23 }; |
984 | | const MCRegister CC_ARM_Win32_CFGuard_Check_ArgRegs[] = { ARM::R0 }; |
985 | | const MCRegister FastCC_ARM_APCS_ArgRegs[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::S0, ARM::S1, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9 }; |
986 | | const MCRegister RetCC_ARM_AAPCS_ArgRegs[] = { 0 }; |
987 | | const MCRegister RetCC_ARM_AAPCS_Common_ArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; |
988 | | const MCRegister RetCC_ARM_AAPCS_VFP_ArgRegs[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::S0, ARM::S1, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9 }; |
989 | | const MCRegister RetCC_ARM_APCS_ArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; |
990 | | const MCRegister RetFastCC_ARM_APCS_ArgRegs[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::S0, ARM::S1, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9 }; |
991 | | |
992 | | // Registers used by Swift. |
993 | | const MCRegister CC_ARM_AAPCS_Swift_ArgRegs[] = { ARM::R10, ARM::R8 }; |
994 | | const MCRegister CC_ARM_AAPCS_VFP_Swift_ArgRegs[] = { ARM::R10, ARM::R8 }; |
995 | | const MCRegister CC_ARM_APCS_Swift_ArgRegs[] = { ARM::R10, ARM::R8 }; |
996 | | const MCRegister RetCC_ARM_AAPCS_Swift_ArgRegs[] = { ARM::R10, ARM::R8 }; |
997 | | const MCRegister RetCC_ARM_AAPCS_VFP_Swift_ArgRegs[] = { ARM::R10, ARM::R8 }; |
998 | | const MCRegister RetCC_ARM_APCS_Swift_ArgRegs[] = { ARM::R10, ARM::R8 }; |
999 | | |
1000 | | #endif // CC_REGISTER_LIST |