Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/ARM/ARMGenGlobalISel.inc
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Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Global Instruction Selector for the ARM target                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
const unsigned MAX_SUBTARGET_PREDICATES = 85;
11
using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>;
12
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13
14
#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15
  mutable MatcherState State;
16
  typedef ComplexRendererFns(ARMInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17
  typedef void(ARMInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
18
  const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
19
  static ARMInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20
  static ARMInstructionSelector::CustomRendererFn CustomRenderers[];
21
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24
  const uint8_t *getMatchTable() const override;
25
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
26
  bool testSimplePredicate(unsigned PredicateID) const override;
27
  void runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override;
28
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
29
30
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
31
, State(0),
32
ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
33
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
34
35
#ifdef GET_GLOBALISEL_IMPL
36
// LLT Objects.
37
enum {
38
  GILLT_s16,
39
  GILLT_s32,
40
  GILLT_s64,
41
  GILLT_v2s1,
42
  GILLT_v2s32,
43
  GILLT_v2s64,
44
  GILLT_v4s1,
45
  GILLT_v4s16,
46
  GILLT_v4s32,
47
  GILLT_v4s64,
48
  GILLT_v8s1,
49
  GILLT_v8s8,
50
  GILLT_v8s16,
51
  GILLT_v8s64,
52
  GILLT_v16s1,
53
  GILLT_v16s8,
54
};
55
const static size_t NumTypeObjects = 16;
56
const static LLT TypeObjects[] = {
57
  LLT::scalar(16),
58
  LLT::scalar(32),
59
  LLT::scalar(64),
60
  LLT::vector(ElementCount::getFixed(2), 1),
61
  LLT::vector(ElementCount::getFixed(2), 32),
62
  LLT::vector(ElementCount::getFixed(2), 64),
63
  LLT::vector(ElementCount::getFixed(4), 1),
64
  LLT::vector(ElementCount::getFixed(4), 16),
65
  LLT::vector(ElementCount::getFixed(4), 32),
66
  LLT::vector(ElementCount::getFixed(4), 64),
67
  LLT::vector(ElementCount::getFixed(8), 1),
68
  LLT::vector(ElementCount::getFixed(8), 8),
69
  LLT::vector(ElementCount::getFixed(8), 16),
70
  LLT::vector(ElementCount::getFixed(8), 64),
71
  LLT::vector(ElementCount::getFixed(16), 1),
72
  LLT::vector(ElementCount::getFixed(16), 8),
73
};
74
75
// Bits for subtarget features that participate in instruction matching.
76
enum SubtargetFeatureBits : uint8_t {
77
  Feature_NoHonorSignDependentRoundingBit = 76,
78
  Feature_HasV4TBit = 6,
79
  Feature_NoV4TBit = 7,
80
  Feature_HasV5TBit = 13,
81
  Feature_NoV5TBit = 67,
82
  Feature_HasV5TEBit = 11,
83
  Feature_HasV6Bit = 0,
84
  Feature_NoV6Bit = 9,
85
  Feature_HasV6MBit = 28,
86
  Feature_HasV8MBaselineBit = 35,
87
  Feature_HasV8_1MMainlineBit = 41,
88
  Feature_HasMVEIntBit = 65,
89
  Feature_HasMVEFloatBit = 66,
90
  Feature_HasCDEBit = 84,
91
  Feature_HasFPRegsBit = 42,
92
  Feature_HasFPRegs16Bit = 43,
93
  Feature_HasNoFPRegs16Bit = 75,
94
  Feature_HasFPRegs64Bit = 52,
95
  Feature_HasV6T2Bit = 8,
96
  Feature_HasV6KBit = 18,
97
  Feature_HasV7Bit = 3,
98
  Feature_HasV8Bit = 56,
99
  Feature_PreV8Bit = 19,
100
  Feature_HasV8_1aBit = 78,
101
  Feature_HasV8_3aBit = 79,
102
  Feature_NoVFPBit = 22,
103
  Feature_HasVFP2Bit = 21,
104
  Feature_HasVFP3Bit = 53,
105
  Feature_HasVFP4Bit = 50,
106
  Feature_HasDPVFPBit = 44,
107
  Feature_HasFPARMv8Bit = 47,
108
  Feature_HasNEONBit = 54,
109
  Feature_HasSHA2Bit = 63,
110
  Feature_HasAESBit = 55,
111
  Feature_HasDotProdBit = 57,
112
  Feature_HasCRCBit = 14,
113
  Feature_HasLOBBit = 40,
114
  Feature_HasFP16Bit = 62,
115
  Feature_HasFullFP16Bit = 46,
116
  Feature_HasBF16Bit = 64,
117
  Feature_HasMatMulInt8Bit = 58,
118
  Feature_HasDivideInThumbBit = 37,
119
  Feature_HasDivideInARMBit = 12,
120
  Feature_HasDSPBit = 36,
121
  Feature_HasDBBit = 15,
122
  Feature_HasV7ClrexBit = 17,
123
  Feature_HasAcquireReleaseBit = 16,
124
  Feature_HasMPBit = 2,
125
  Feature_Has8MSecExtBit = 29,
126
  Feature_HasZCZBit = 59,
127
  Feature_UseNEONForFPBit = 82,
128
  Feature_DontUseNEONForFPBit = 45,
129
  Feature_IsThumbBit = 26,
130
  Feature_IsThumb1OnlyBit = 27,
131
  Feature_IsThumb2Bit = 34,
132
  Feature_IsNotMClassBit = 38,
133
  Feature_IsARMBit = 1,
134
  Feature_IsWindowsBit = 30,
135
  Feature_IsNotWindowsBit = 31,
136
  Feature_IsReadTPTPIDRURWBit = 70,
137
  Feature_IsReadTPTPIDRUROBit = 71,
138
  Feature_IsReadTPTPIDRPRWBit = 72,
139
  Feature_IsReadTPSoftBit = 20,
140
  Feature_UseNaClTrapBit = 4,
141
  Feature_DontUseNaClTrapBit = 5,
142
  Feature_UseMovtBit = 39,
143
  Feature_DontUseMovtBit = 23,
144
  Feature_UseMovtInPicBit = 24,
145
  Feature_DontUseMovtInPicBit = 25,
146
  Feature_UseFPVMLxBit = 49,
147
  Feature_SLSBLRMitigationBit = 69,
148
  Feature_NoSLSBLRMitigationBit = 68,
149
  Feature_UseMulOpsBit = 10,
150
  Feature_UseFusedMACBit = 51,
151
  Feature_HasFastVGETLNi32Bit = 60,
152
  Feature_HasSlowVGETLNi32Bit = 80,
153
  Feature_HasFastVDUP32Bit = 61,
154
  Feature_HasSlowVDUP32Bit = 81,
155
  Feature_UseVMOVSRBit = 48,
156
  Feature_DontUseVMOVSRBit = 83,
157
  Feature_IsLEBit = 74,
158
  Feature_IsBEBit = 77,
159
  Feature_GenExecuteOnlyBit = 33,
160
  Feature_DontGenExecuteOnlyBit = 32,
161
  Feature_GenT1ExecuteOnlyBit = 73,
162
};
163
164
PredicateBitset ARMInstructionSelector::
165
2.47k
computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const {
166
2.47k
  PredicateBitset Features;
167
2.47k
  if (!TM.Options.HonorSignDependentRoundingFPMath())
168
2.47k
    Features.set(Feature_NoHonorSignDependentRoundingBit);
169
2.47k
  if (Subtarget->hasV4TOps())
170
0
    Features.set(Feature_HasV4TBit);
171
2.47k
  if (!Subtarget->hasV4TOps())
172
2.47k
    Features.set(Feature_NoV4TBit);
173
2.47k
  if (Subtarget->hasV5TOps())
174
0
    Features.set(Feature_HasV5TBit);
175
2.47k
  if (!Subtarget->hasV5TOps())
176
2.47k
    Features.set(Feature_NoV5TBit);
177
2.47k
  if (Subtarget->hasV5TEOps())
178
0
    Features.set(Feature_HasV5TEBit);
179
2.47k
  if (Subtarget->hasV6Ops())
180
0
    Features.set(Feature_HasV6Bit);
181
2.47k
  if (!Subtarget->hasV6Ops())
182
2.47k
    Features.set(Feature_NoV6Bit);
183
2.47k
  if (Subtarget->hasV6MOps())
184
0
    Features.set(Feature_HasV6MBit);
185
2.47k
  if (Subtarget->hasV8MBaselineOps())
186
0
    Features.set(Feature_HasV8MBaselineBit);
187
2.47k
  if (Subtarget->hasV8_1MMainlineOps())
188
0
    Features.set(Feature_HasV8_1MMainlineBit);
189
2.47k
  if (Subtarget->hasMVEIntegerOps())
190
0
    Features.set(Feature_HasMVEIntBit);
191
2.47k
  if (Subtarget->hasMVEFloatOps())
192
0
    Features.set(Feature_HasMVEFloatBit);
193
2.47k
  if (Subtarget->hasCDEOps())
194
0
    Features.set(Feature_HasCDEBit);
195
2.47k
  if (Subtarget->hasFPRegs())
196
0
    Features.set(Feature_HasFPRegsBit);
197
2.47k
  if (Subtarget->hasFPRegs16())
198
0
    Features.set(Feature_HasFPRegs16Bit);
199
2.47k
  if (!Subtarget->hasFPRegs16())
200
2.47k
    Features.set(Feature_HasNoFPRegs16Bit);
201
2.47k
  if (Subtarget->hasFPRegs64())
202
0
    Features.set(Feature_HasFPRegs64Bit);
203
2.47k
  if (Subtarget->hasV6T2Ops())
204
0
    Features.set(Feature_HasV6T2Bit);
205
2.47k
  if (Subtarget->hasV6KOps())
206
0
    Features.set(Feature_HasV6KBit);
207
2.47k
  if (Subtarget->hasV7Ops())
208
0
    Features.set(Feature_HasV7Bit);
209
2.47k
  if (Subtarget->hasV8Ops())
210
0
    Features.set(Feature_HasV8Bit);
211
2.47k
  if (!Subtarget->hasV8Ops())
212
2.47k
    Features.set(Feature_PreV8Bit);
213
2.47k
  if (Subtarget->hasV8_1aOps())
214
0
    Features.set(Feature_HasV8_1aBit);
215
2.47k
  if (Subtarget->hasV8_3aOps())
216
0
    Features.set(Feature_HasV8_3aBit);
217
2.47k
  if (!Subtarget->hasVFP2Base())
218
2.47k
    Features.set(Feature_NoVFPBit);
219
2.47k
  if (Subtarget->hasVFP2Base())
220
0
    Features.set(Feature_HasVFP2Bit);
221
2.47k
  if (Subtarget->hasVFP3Base())
222
0
    Features.set(Feature_HasVFP3Bit);
223
2.47k
  if (Subtarget->hasVFP4Base())
224
0
    Features.set(Feature_HasVFP4Bit);
225
2.47k
  if (Subtarget->hasFP64())
226
0
    Features.set(Feature_HasDPVFPBit);
227
2.47k
  if (Subtarget->hasFPARMv8Base())
228
0
    Features.set(Feature_HasFPARMv8Bit);
229
2.47k
  if (Subtarget->hasNEON())
230
0
    Features.set(Feature_HasNEONBit);
231
2.47k
  if (Subtarget->hasSHA2())
232
0
    Features.set(Feature_HasSHA2Bit);
233
2.47k
  if (Subtarget->hasAES())
234
0
    Features.set(Feature_HasAESBit);
235
2.47k
  if (Subtarget->hasDotProd())
236
0
    Features.set(Feature_HasDotProdBit);
237
2.47k
  if (Subtarget->hasCRC())
238
0
    Features.set(Feature_HasCRCBit);
239
2.47k
  if (Subtarget->hasLOB())
240
0
    Features.set(Feature_HasLOBBit);
241
2.47k
  if (Subtarget->hasFP16())
242
0
    Features.set(Feature_HasFP16Bit);
243
2.47k
  if (Subtarget->hasFullFP16())
244
0
    Features.set(Feature_HasFullFP16Bit);
245
2.47k
  if (Subtarget->hasBF16())
246
0
    Features.set(Feature_HasBF16Bit);
247
2.47k
  if (Subtarget->hasMatMulInt8())
248
0
    Features.set(Feature_HasMatMulInt8Bit);
249
2.47k
  if (Subtarget->hasDivideInThumbMode())
250
0
    Features.set(Feature_HasDivideInThumbBit);
251
2.47k
  if (Subtarget->hasDivideInARMMode())
252
0
    Features.set(Feature_HasDivideInARMBit);
253
2.47k
  if (Subtarget->hasDSP())
254
0
    Features.set(Feature_HasDSPBit);
255
2.47k
  if (Subtarget->hasDataBarrier())
256
0
    Features.set(Feature_HasDBBit);
257
2.47k
  if (Subtarget->hasV7Clrex())
258
0
    Features.set(Feature_HasV7ClrexBit);
259
2.47k
  if (Subtarget->hasAcquireRelease())
260
0
    Features.set(Feature_HasAcquireReleaseBit);
261
2.47k
  if (Subtarget->hasMPExtension())
262
0
    Features.set(Feature_HasMPBit);
263
2.47k
  if (Subtarget->has8MSecExt())
264
0
    Features.set(Feature_Has8MSecExtBit);
265
2.47k
  if (Subtarget->hasZeroCycleZeroing())
266
0
    Features.set(Feature_HasZCZBit);
267
2.47k
  if (Subtarget->useNEONForSinglePrecisionFP())
268
0
    Features.set(Feature_UseNEONForFPBit);
269
2.47k
  if (!Subtarget->useNEONForSinglePrecisionFP())
270
2.47k
    Features.set(Feature_DontUseNEONForFPBit);
271
2.47k
  if (Subtarget->isThumb())
272
0
    Features.set(Feature_IsThumbBit);
273
2.47k
  if (Subtarget->isThumb1Only())
274
0
    Features.set(Feature_IsThumb1OnlyBit);
275
2.47k
  if (Subtarget->isThumb2())
276
0
    Features.set(Feature_IsThumb2Bit);
277
2.47k
  if (!Subtarget->isMClass())
278
2.47k
    Features.set(Feature_IsNotMClassBit);
279
2.47k
  if (!Subtarget->isThumb())
280
2.47k
    Features.set(Feature_IsARMBit);
281
2.47k
  if (Subtarget->isTargetWindows())
282
0
    Features.set(Feature_IsWindowsBit);
283
2.47k
  if (!Subtarget->isTargetWindows())
284
2.47k
    Features.set(Feature_IsNotWindowsBit);
285
2.47k
  if (Subtarget->isReadTPTPIDRURW())
286
0
    Features.set(Feature_IsReadTPTPIDRURWBit);
287
2.47k
  if (Subtarget->isReadTPTPIDRURO())
288
0
    Features.set(Feature_IsReadTPTPIDRUROBit);
289
2.47k
  if (Subtarget->isReadTPTPIDRPRW())
290
0
    Features.set(Feature_IsReadTPTPIDRPRWBit);
291
2.47k
  if (Subtarget->isReadTPSoft())
292
2.47k
    Features.set(Feature_IsReadTPSoftBit);
293
2.47k
  if (Subtarget->useNaClTrap())
294
0
    Features.set(Feature_UseNaClTrapBit);
295
2.47k
  if (!Subtarget->useNaClTrap())
296
2.47k
    Features.set(Feature_DontUseNaClTrapBit);
297
2.47k
  if (Subtarget->useMulOps())
298
2.47k
    Features.set(Feature_UseMulOpsBit);
299
2.47k
  if (TM.Options.AllowFPOpFusion ==  FPOpFusion::Fast && Subtarget->useFPVFMx())
300
0
    Features.set(Feature_UseFusedMACBit);
301
2.47k
  if (!Subtarget->hasSlowVGETLNi32())
302
2.47k
    Features.set(Feature_HasFastVGETLNi32Bit);
303
2.47k
  if (Subtarget->hasSlowVGETLNi32())
304
0
    Features.set(Feature_HasSlowVGETLNi32Bit);
305
2.47k
  if (!Subtarget->hasSlowVDUP32())
306
2.47k
    Features.set(Feature_HasFastVDUP32Bit);
307
2.47k
  if (Subtarget->hasSlowVDUP32())
308
0
    Features.set(Feature_HasSlowVDUP32Bit);
309
2.47k
  if (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())
310
2.47k
    Features.set(Feature_UseVMOVSRBit);
311
2.47k
  if (!Subtarget->preferVMOVSR() &&Subtarget->useNEONForSinglePrecisionFP())
312
0
    Features.set(Feature_DontUseVMOVSRBit);
313
2.47k
  if (Subtarget->genExecuteOnly())
314
0
    Features.set(Feature_GenExecuteOnlyBit);
315
2.47k
  if (!Subtarget->genExecuteOnly())
316
2.47k
    Features.set(Feature_DontGenExecuteOnlyBit);
317
2.47k
  if (Subtarget->genExecuteOnly() && Subtarget->isThumb1Only() && !Subtarget->hasV8MBaselineOps())
318
0
    Features.set(Feature_GenT1ExecuteOnlyBit);
319
2.47k
  return Features;
320
2.47k
}
321
322
0
void ARMInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
323
0
  AvailableFunctionFeatures = computeAvailableFunctionFeatures((const ARMSubtarget *)&MF.getSubtarget(), &MF);
324
0
}
325
PredicateBitset ARMInstructionSelector::
326
0
computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, const MachineFunction *MF) const {
327
0
  PredicateBitset Features;
328
0
  if (Subtarget->useMovt())
329
0
    Features.set(Feature_UseMovtBit);
330
0
  if (!Subtarget->useMovt())
331
0
    Features.set(Feature_DontUseMovtBit);
332
0
  if (Subtarget->useMovt() && Subtarget->allowPositionIndependentMovt())
333
0
    Features.set(Feature_UseMovtInPicBit);
334
0
  if (!Subtarget->useMovt() || !Subtarget->allowPositionIndependentMovt())
335
0
    Features.set(Feature_DontUseMovtInPicBit);
336
0
  if (((Subtarget->useFPVMLx() &&  TM.Options.AllowFPOpFusion != FPOpFusion::Fast) ||Subtarget->hasMinSize()))
337
0
    Features.set(Feature_UseFPVMLxBit);
338
0
  if ( MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() )
339
0
    Features.set(Feature_SLSBLRMitigationBit);
340
0
  if ( !MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() )
341
0
    Features.set(Feature_NoSLSBLRMitigationBit);
342
0
  if (MF->getDataLayout().isLittleEndian())
343
0
    Features.set(Feature_IsLEBit);
344
0
  if (MF->getDataLayout().isBigEndian())
345
0
    Features.set(Feature_IsBEBit);
346
0
  return Features;
347
0
}
348
349
// Feature bitsets.
350
enum {
351
  GIFBS_Invalid,
352
  GIFBS_HasDotProd,
353
  GIFBS_HasFP16,
354
  GIFBS_HasFPARMv8,
355
  GIFBS_HasFPRegs,
356
  GIFBS_HasFullFP16,
357
  GIFBS_HasMVEFloat,
358
  GIFBS_HasMVEInt,
359
  GIFBS_HasMatMulInt8,
360
  GIFBS_HasNEON,
361
  GIFBS_HasVFP2,
362
  GIFBS_HasVFP3,
363
  GIFBS_HasVFP4,
364
  GIFBS_IsARM,
365
  GIFBS_IsThumb,
366
  GIFBS_IsThumb2,
367
  GIFBS_NoHonorSignDependentRounding,
368
  GIFBS_DontUseNEONForFP_HasVFP2,
369
  GIFBS_DontUseVMOVSR_HasNEON,
370
  GIFBS_Has8MSecExt_IsThumb,
371
  GIFBS_HasAES_HasV8,
372
  GIFBS_HasBF16_HasNEON,
373
  GIFBS_HasCRC_IsARM,
374
  GIFBS_HasCRC_IsThumb2,
375
  GIFBS_HasDB_IsARM,
376
  GIFBS_HasDB_IsThumb,
377
  GIFBS_HasDPVFP_HasFPARMv8,
378
  GIFBS_HasDPVFP_HasVFP2,
379
  GIFBS_HasDPVFP_HasVFP3,
380
  GIFBS_HasDPVFP_HasVFP4,
381
  GIFBS_HasDPVFP_NoHonorSignDependentRounding,
382
  GIFBS_HasDSP_IsThumb2,
383
  GIFBS_HasDivideInARM_IsARM,
384
  GIFBS_HasFP16_HasNEON,
385
  GIFBS_HasFPARMv8_HasNEON,
386
  GIFBS_HasFPRegs_HasFastVGETLNi32,
387
  GIFBS_HasFPRegs_UseVMOVSR,
388
  GIFBS_HasFullFP16_HasNEON,
389
  GIFBS_HasMVEInt_HasV8_1MMainline,
390
  GIFBS_HasMVEInt_IsBE,
391
  GIFBS_HasMVEInt_IsLE,
392
  GIFBS_HasNEON_HasV8,
393
  GIFBS_HasNEON_HasV8_1a,
394
  GIFBS_HasNEON_HasV8_3a,
395
  GIFBS_HasNEON_HasVFP4,
396
  GIFBS_HasNEON_IsBE,
397
  GIFBS_HasNEON_IsLE,
398
  GIFBS_HasNEON_UseNEONForFP,
399
  GIFBS_HasSHA2_HasV8,
400
  GIFBS_HasV5T_IsARM,
401
  GIFBS_HasV5TE_IsARM,
402
  GIFBS_HasV6_IsARM,
403
  GIFBS_HasV6K_IsARM,
404
  GIFBS_HasV6M_IsThumb,
405
  GIFBS_HasV6T2_IsARM,
406
  GIFBS_HasV7_IsARM,
407
  GIFBS_HasV7Clrex_IsThumb,
408
  GIFBS_HasV8MBaseline_IsThumb,
409
  GIFBS_IsARM_NoV6,
410
  GIFBS_IsARM_PreV8,
411
  GIFBS_IsThumb_IsThumb1Only,
412
  GIFBS_IsThumb_IsWindows,
413
  GIFBS_IsThumb_UseMovt,
414
  GIFBS_IsThumb2_PreV8,
415
  GIFBS_IsThumb2_UseMulOps,
416
  GIFBS_DontUseMovt_GenExecuteOnly_IsThumb1Only,
417
  GIFBS_HasDSP_IsThumb2_UseMulOps,
418
  GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
419
  GIFBS_HasFPARMv8_HasFullFP16_HasNEON,
420
  GIFBS_HasFullFP16_HasNEON_HasV8,
421
  GIFBS_HasFullFP16_HasNEON_HasV8_3a,
422
  GIFBS_HasFullFP16_HasNEON_UseFPVMLx,
423
  GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
424
  GIFBS_HasLOB_HasV8_1MMainline_IsThumb2,
425
  GIFBS_HasNEON_UseFPVMLx_UseNEONForFP,
426
  GIFBS_HasV5TE_IsARM_UseMulOps,
427
  GIFBS_HasV6_IsARM_UseMulOps,
428
  GIFBS_HasV6_IsThumb_IsThumb1Only,
429
  GIFBS_HasV6T2_IsARM_UseMulOps,
430
  GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP,
431
  GIFBS_IsARM_NoV6_UseMulOps,
432
};
433
constexpr static PredicateBitset FeatureBitsets[] {
434
  {}, // GIFBS_Invalid
435
  {Feature_HasDotProdBit, },
436
  {Feature_HasFP16Bit, },
437
  {Feature_HasFPARMv8Bit, },
438
  {Feature_HasFPRegsBit, },
439
  {Feature_HasFullFP16Bit, },
440
  {Feature_HasMVEFloatBit, },
441
  {Feature_HasMVEIntBit, },
442
  {Feature_HasMatMulInt8Bit, },
443
  {Feature_HasNEONBit, },
444
  {Feature_HasVFP2Bit, },
445
  {Feature_HasVFP3Bit, },
446
  {Feature_HasVFP4Bit, },
447
  {Feature_IsARMBit, },
448
  {Feature_IsThumbBit, },
449
  {Feature_IsThumb2Bit, },
450
  {Feature_NoHonorSignDependentRoundingBit, },
451
  {Feature_DontUseNEONForFPBit, Feature_HasVFP2Bit, },
452
  {Feature_DontUseVMOVSRBit, Feature_HasNEONBit, },
453
  {Feature_Has8MSecExtBit, Feature_IsThumbBit, },
454
  {Feature_HasAESBit, Feature_HasV8Bit, },
455
  {Feature_HasBF16Bit, Feature_HasNEONBit, },
456
  {Feature_HasCRCBit, Feature_IsARMBit, },
457
  {Feature_HasCRCBit, Feature_IsThumb2Bit, },
458
  {Feature_HasDBBit, Feature_IsARMBit, },
459
  {Feature_HasDBBit, Feature_IsThumbBit, },
460
  {Feature_HasDPVFPBit, Feature_HasFPARMv8Bit, },
461
  {Feature_HasDPVFPBit, Feature_HasVFP2Bit, },
462
  {Feature_HasDPVFPBit, Feature_HasVFP3Bit, },
463
  {Feature_HasDPVFPBit, Feature_HasVFP4Bit, },
464
  {Feature_HasDPVFPBit, Feature_NoHonorSignDependentRoundingBit, },
465
  {Feature_HasDSPBit, Feature_IsThumb2Bit, },
466
  {Feature_HasDivideInARMBit, Feature_IsARMBit, },
467
  {Feature_HasFP16Bit, Feature_HasNEONBit, },
468
  {Feature_HasFPARMv8Bit, Feature_HasNEONBit, },
469
  {Feature_HasFPRegsBit, Feature_HasFastVGETLNi32Bit, },
470
  {Feature_HasFPRegsBit, Feature_UseVMOVSRBit, },
471
  {Feature_HasFullFP16Bit, Feature_HasNEONBit, },
472
  {Feature_HasMVEIntBit, Feature_HasV8_1MMainlineBit, },
473
  {Feature_HasMVEIntBit, Feature_IsBEBit, },
474
  {Feature_HasMVEIntBit, Feature_IsLEBit, },
475
  {Feature_HasNEONBit, Feature_HasV8Bit, },
476
  {Feature_HasNEONBit, Feature_HasV8_1aBit, },
477
  {Feature_HasNEONBit, Feature_HasV8_3aBit, },
478
  {Feature_HasNEONBit, Feature_HasVFP4Bit, },
479
  {Feature_HasNEONBit, Feature_IsBEBit, },
480
  {Feature_HasNEONBit, Feature_IsLEBit, },
481
  {Feature_HasNEONBit, Feature_UseNEONForFPBit, },
482
  {Feature_HasSHA2Bit, Feature_HasV8Bit, },
483
  {Feature_HasV5TBit, Feature_IsARMBit, },
484
  {Feature_HasV5TEBit, Feature_IsARMBit, },
485
  {Feature_HasV6Bit, Feature_IsARMBit, },
486
  {Feature_HasV6KBit, Feature_IsARMBit, },
487
  {Feature_HasV6MBit, Feature_IsThumbBit, },
488
  {Feature_HasV6T2Bit, Feature_IsARMBit, },
489
  {Feature_HasV7Bit, Feature_IsARMBit, },
490
  {Feature_HasV7ClrexBit, Feature_IsThumbBit, },
491
  {Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
492
  {Feature_IsARMBit, Feature_NoV6Bit, },
493
  {Feature_IsARMBit, Feature_PreV8Bit, },
494
  {Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
495
  {Feature_IsThumbBit, Feature_IsWindowsBit, },
496
  {Feature_IsThumbBit, Feature_UseMovtBit, },
497
  {Feature_IsThumb2Bit, Feature_PreV8Bit, },
498
  {Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
499
  {Feature_DontUseMovtBit, Feature_GenExecuteOnlyBit, Feature_IsThumb1OnlyBit, },
500
  {Feature_HasDSPBit, Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
501
  {Feature_HasDivideInThumbBit, Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
502
  {Feature_HasFPARMv8Bit, Feature_HasFullFP16Bit, Feature_HasNEONBit, },
503
  {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8Bit, },
504
  {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8_3aBit, },
505
  {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFPVMLxBit, },
506
  {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFusedMACBit, },
507
  {Feature_HasLOBBit, Feature_HasV8_1MMainlineBit, Feature_IsThumb2Bit, },
508
  {Feature_HasNEONBit, Feature_UseFPVMLxBit, Feature_UseNEONForFPBit, },
509
  {Feature_HasV5TEBit, Feature_IsARMBit, Feature_UseMulOpsBit, },
510
  {Feature_HasV6Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
511
  {Feature_HasV6Bit, Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
512
  {Feature_HasV6T2Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
513
  {Feature_HasVFP4Bit, Feature_UseFusedMACBit, Feature_UseNEONForFPBit, },
514
  {Feature_IsARMBit, Feature_NoV6Bit, Feature_UseMulOpsBit, },
515
};
516
517
// ComplexPattern predicates.
518
enum {
519
  GICP_Invalid,
520
};
521
// See constructor for table contents
522
523
ARMInstructionSelector::ComplexMatcherMemFn
524
ARMInstructionSelector::ComplexPredicateFns[] = {
525
  nullptr, // GICP_Invalid
526
};
527
528
// PatFrag predicates.
529
enum {
530
  GICXXPred_MI_Predicate_bf_inv_mask_imm = GICXXPred_Invalid + 1,
531
  GICXXPred_MI_Predicate_vfp_f32imm,
532
  GICXXPred_MI_Predicate_vfp_f64imm,
533
};
534
0
bool ARMInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const {
535
0
  const MachineFunction &MF = *MI.getParent()->getParent();
536
0
  const MachineRegisterInfo &MRI = MF.getRegInfo();
537
0
  const auto &Operands = State.RecordedOperands;
538
0
  (void)Operands;
539
0
  (void)MRI;
540
0
  switch (PredicateID) {
541
0
  case GICXXPred_MI_Predicate_bf_inv_mask_imm: {
542
    
543
        // There's better methods of implementing this check. IntImmLeaf<> would be
544
        // equivalent and have less boilerplate but we need a test for C++
545
        // predicates and this one causes new rules to be imported into GlobalISel
546
        // without requiring additional features first.
547
0
        const auto &MO = MI.getOperand(1);
548
0
        if (!MO.isCImm())
549
0
          return false;
550
0
        return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue());
551
      
552
0
    llvm_unreachable("bf_inv_mask_imm should have returned");
553
0
  }
554
0
  case GICXXPred_MI_Predicate_vfp_f32imm: {
555
    
556
0
          const auto &MO = MI.getOperand(1);
557
0
          if (!MO.isFPImm())
558
0
            return false;
559
0
          return ARM_AM::getFP32Imm(MO.getFPImm()->getValueAPF()) != -1;
560
        
561
0
    llvm_unreachable("vfp_f32imm should have returned");
562
0
  }
563
0
  case GICXXPred_MI_Predicate_vfp_f64imm: {
564
    
565
0
          const auto &MO = MI.getOperand(1);
566
0
          if (!MO.isFPImm())
567
0
            return false;
568
0
          return ARM_AM::getFP64Imm(MO.getFPImm()->getValueAPF()) != -1;
569
        
570
0
    llvm_unreachable("vfp_f64imm should have returned");
571
0
  }
572
0
  }
573
0
  llvm_unreachable("Unknown predicate");
574
0
  return false;
575
0
}
576
// PatFrag predicates.
577
enum {
578
  GICXXPred_I64_Predicate_VectorIndex8 = GICXXPred_Invalid + 1,
579
  GICXXPred_I64_Predicate_VectorIndex16,
580
  GICXXPred_I64_Predicate_VectorIndex32,
581
  GICXXPred_I64_Predicate_VectorIndex64,
582
  GICXXPred_I64_Predicate_asr_imm,
583
  GICXXPred_I64_Predicate_imm0_7,
584
  GICXXPred_I64_Predicate_imm0_15,
585
  GICXXPred_I64_Predicate_imm0_31,
586
  GICXXPred_I64_Predicate_imm0_32,
587
  GICXXPred_I64_Predicate_imm0_63,
588
  GICXXPred_I64_Predicate_imm0_239,
589
  GICXXPred_I64_Predicate_imm0_255,
590
  GICXXPred_I64_Predicate_imm0_255_expr,
591
  GICXXPred_I64_Predicate_imm0_4095,
592
  GICXXPred_I64_Predicate_imm0_65535,
593
  GICXXPred_I64_Predicate_imm0_65535_expr,
594
  GICXXPred_I64_Predicate_imm0_65535_neg,
595
  GICXXPred_I64_Predicate_imm1_7,
596
  GICXXPred_I64_Predicate_imm1_15,
597
  GICXXPred_I64_Predicate_imm1_16,
598
  GICXXPred_I64_Predicate_imm1_31,
599
  GICXXPred_I64_Predicate_imm8,
600
  GICXXPred_I64_Predicate_imm8_255,
601
  GICXXPred_I64_Predicate_imm8_or_16,
602
  GICXXPred_I64_Predicate_imm16,
603
  GICXXPred_I64_Predicate_imm16_31,
604
  GICXXPred_I64_Predicate_imm24b,
605
  GICXXPred_I64_Predicate_imm32,
606
  GICXXPred_I64_Predicate_imm256_510,
607
  GICXXPred_I64_Predicate_imm_3b,
608
  GICXXPred_I64_Predicate_imm_4b,
609
  GICXXPred_I64_Predicate_imm_6b,
610
  GICXXPred_I64_Predicate_imm_7b,
611
  GICXXPred_I64_Predicate_imm_9b,
612
  GICXXPred_I64_Predicate_imm_11b,
613
  GICXXPred_I64_Predicate_imm_12b,
614
  GICXXPred_I64_Predicate_imm_13b,
615
  GICXXPred_I64_Predicate_imm_even,
616
  GICXXPred_I64_Predicate_imm_odd,
617
  GICXXPred_I64_Predicate_long_shift,
618
  GICXXPred_I64_Predicate_mod_imm,
619
  GICXXPred_I64_Predicate_pkh_asr_amt,
620
  GICXXPred_I64_Predicate_pkh_lsl_amt,
621
  GICXXPred_I64_Predicate_shr_imm8,
622
  GICXXPred_I64_Predicate_shr_imm16,
623
  GICXXPred_I64_Predicate_shr_imm32,
624
  GICXXPred_I64_Predicate_shr_imm64,
625
  GICXXPred_I64_Predicate_t2_so_imm,
626
  GICXXPred_I64_Predicate_t2_so_imm_neg,
627
};
628
0
bool ARMInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
629
0
  switch (PredicateID) {
630
0
  case GICXXPred_I64_Predicate_VectorIndex8: {
631
    
632
0
      return ((uint64_t)Imm) < 8;
633
    
634
0
  }
635
0
  case GICXXPred_I64_Predicate_VectorIndex16: {
636
    
637
0
      return ((uint64_t)Imm) < 4;
638
    
639
0
  }
640
0
  case GICXXPred_I64_Predicate_VectorIndex32: {
641
    
642
0
      return ((uint64_t)Imm) < 2;
643
    
644
0
  }
645
0
  case GICXXPred_I64_Predicate_VectorIndex64: {
646
    
647
0
      return ((uint64_t)Imm) < 1;
648
    
649
0
  }
650
0
  case GICXXPred_I64_Predicate_asr_imm: {
651
0
     return Imm > 0 && Imm <= 32; 
652
0
  }
653
0
  case GICXXPred_I64_Predicate_imm0_7: {
654
    
655
0
      return Imm >= 0 && Imm < 8;
656
    
657
0
  }
658
0
  case GICXXPred_I64_Predicate_imm0_15: {
659
    
660
0
      return Imm >= 0 && Imm < 16;
661
    
662
0
  }
663
0
  case GICXXPred_I64_Predicate_imm0_31: {
664
    
665
0
      return Imm >= 0 && Imm < 32;
666
    
667
0
  }
668
0
  case GICXXPred_I64_Predicate_imm0_32: {
669
    
670
0
      return Imm >= 0 && Imm < 33;
671
    
672
0
  }
673
0
  case GICXXPred_I64_Predicate_imm0_63: {
674
    
675
0
      return Imm >= 0 && Imm < 64;
676
    
677
0
  }
678
0
  case GICXXPred_I64_Predicate_imm0_239: {
679
0
     return Imm >= 0 && Imm < 240; 
680
0
  }
681
0
  case GICXXPred_I64_Predicate_imm0_255: {
682
0
     return Imm >= 0 && Imm < 256; 
683
0
  }
684
0
  case GICXXPred_I64_Predicate_imm0_255_expr: {
685
0
     return Imm >= 0 && Imm < 256; 
686
0
  }
687
0
  case GICXXPred_I64_Predicate_imm0_4095: {
688
    
689
0
      return Imm >= 0 && Imm < 4096;
690
    
691
0
  }
692
0
  case GICXXPred_I64_Predicate_imm0_65535: {
693
    
694
0
      return Imm >= 0 && Imm < 65536;
695
    
696
0
  }
697
0
  case GICXXPred_I64_Predicate_imm0_65535_expr: {
698
    
699
0
      return Imm >= 0 && Imm < 65536;
700
    
701
0
  }
702
0
  case GICXXPred_I64_Predicate_imm0_65535_neg: {
703
    
704
0
      return -Imm >= 0 && -Imm < 65536;
705
    
706
0
  }
707
0
  case GICXXPred_I64_Predicate_imm1_7: {
708
0
     return Imm > 0 && Imm < 8; 
709
0
  }
710
0
  case GICXXPred_I64_Predicate_imm1_15: {
711
0
     return Imm > 0 && Imm < 16; 
712
0
  }
713
0
  case GICXXPred_I64_Predicate_imm1_16: {
714
    
715
0
        return Imm > 0 && Imm <= 16;
716
      
717
0
  }
718
0
  case GICXXPred_I64_Predicate_imm1_31: {
719
0
     return Imm > 0 && Imm < 32; 
720
0
  }
721
0
  case GICXXPred_I64_Predicate_imm8: {
722
0
     return Imm == 8; 
723
0
  }
724
0
  case GICXXPred_I64_Predicate_imm8_255: {
725
    
726
0
      return Imm >= 8 && Imm < 256;
727
    
728
0
  }
729
0
  case GICXXPred_I64_Predicate_imm8_or_16: {
730
0
     return Imm == 8 || Imm == 16;
731
0
  }
732
0
  case GICXXPred_I64_Predicate_imm16: {
733
0
     return Imm == 16; 
734
0
  }
735
0
  case GICXXPred_I64_Predicate_imm16_31: {
736
    
737
0
      return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
738
    
739
0
  }
740
0
  case GICXXPred_I64_Predicate_imm24b: {
741
    
742
0
      return Imm >= 0 && Imm <= 0xffffff;
743
    
744
0
  }
745
0
  case GICXXPred_I64_Predicate_imm32: {
746
0
     return Imm == 32; 
747
0
  }
748
0
  case GICXXPred_I64_Predicate_imm256_510: {
749
    
750
0
      return Imm >= 256 && Imm < 511;
751
    
752
0
  }
753
0
  case GICXXPred_I64_Predicate_imm_3b: {
754
0
    { return Imm >= 0 && Imm < (1 << 3); }
755
0
    llvm_unreachable("imm_3b should have returned");
756
0
  }
757
0
  case GICXXPred_I64_Predicate_imm_4b: {
758
0
    { return Imm >= 0 && Imm < (1 << 4); }
759
0
    llvm_unreachable("imm_4b should have returned");
760
0
  }
761
0
  case GICXXPred_I64_Predicate_imm_6b: {
762
0
    { return Imm >= 0 && Imm < (1 << 6); }
763
0
    llvm_unreachable("imm_6b should have returned");
764
0
  }
765
0
  case GICXXPred_I64_Predicate_imm_7b: {
766
0
    { return Imm >= 0 && Imm < (1 << 7); }
767
0
    llvm_unreachable("imm_7b should have returned");
768
0
  }
769
0
  case GICXXPred_I64_Predicate_imm_9b: {
770
0
    { return Imm >= 0 && Imm < (1 << 9); }
771
0
    llvm_unreachable("imm_9b should have returned");
772
0
  }
773
0
  case GICXXPred_I64_Predicate_imm_11b: {
774
0
    { return Imm >= 0 && Imm < (1 << 11); }
775
0
    llvm_unreachable("imm_11b should have returned");
776
0
  }
777
0
  case GICXXPred_I64_Predicate_imm_12b: {
778
0
    { return Imm >= 0 && Imm < (1 << 12); }
779
0
    llvm_unreachable("imm_12b should have returned");
780
0
  }
781
0
  case GICXXPred_I64_Predicate_imm_13b: {
782
0
    { return Imm >= 0 && Imm < (1 << 13); }
783
0
    llvm_unreachable("imm_13b should have returned");
784
0
  }
785
0
  case GICXXPred_I64_Predicate_imm_even: {
786
0
     return (Imm & 1) == 0; 
787
0
  }
788
0
  case GICXXPred_I64_Predicate_imm_odd: {
789
0
     return (Imm & 1) == 1; 
790
0
  }
791
0
  case GICXXPred_I64_Predicate_long_shift: {
792
0
     return Imm > 0 && Imm <= 32; 
793
0
  }
794
0
  case GICXXPred_I64_Predicate_mod_imm: {
795
    
796
0
        return ARM_AM::getSOImmVal(Imm) != -1;
797
      
798
0
  }
799
0
  case GICXXPred_I64_Predicate_pkh_asr_amt: {
800
0
     return Imm > 0 && Imm <= 32; 
801
0
  }
802
0
  case GICXXPred_I64_Predicate_pkh_lsl_amt: {
803
0
     return Imm >= 0 && Imm < 32; 
804
0
  }
805
0
  case GICXXPred_I64_Predicate_shr_imm8: {
806
0
     return Imm > 0 && Imm <= 8; 
807
0
  }
808
0
  case GICXXPred_I64_Predicate_shr_imm16: {
809
0
     return Imm > 0 && Imm <= 16; 
810
0
  }
811
0
  case GICXXPred_I64_Predicate_shr_imm32: {
812
0
     return Imm > 0 && Imm <= 32; 
813
0
  }
814
0
  case GICXXPred_I64_Predicate_shr_imm64: {
815
0
     return Imm > 0 && Imm <= 64; 
816
0
  }
817
0
  case GICXXPred_I64_Predicate_t2_so_imm: {
818
    
819
0
        return ARM_AM::getT2SOImmVal(Imm) != -1;
820
      
821
0
  }
822
0
  case GICXXPred_I64_Predicate_t2_so_imm_neg: {
823
    
824
0
      return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
825
    
826
0
  }
827
0
  }
828
0
  llvm_unreachable("Unknown predicate");
829
0
  return false;
830
0
}
831
// PatFrag predicates.
832
0
bool ARMInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
833
0
  llvm_unreachable("Unknown predicate");
834
0
  return false;
835
0
}
836
// PatFrag predicates.
837
enum {
838
  GICXXPred_APInt_Predicate_arm_i32imm = GICXXPred_Invalid + 1,
839
};
840
0
bool ARMInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
841
0
  switch (PredicateID) {
842
0
  case GICXXPred_APInt_Predicate_arm_i32imm: {
843
    
844
0
      if (Subtarget->useMovt())
845
0
        return true;
846
0
      if (ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue()))
847
0
        return true;
848
0
      return ARM_AM::isSOImmTwoPartValNeg(Imm.getZExtValue());
849
    
850
0
    llvm_unreachable("arm_i32imm should have returned");
851
0
  }
852
0
  }
853
0
  llvm_unreachable("Unknown predicate");
854
0
  return false;
855
0
}
856
0
bool ARMInstructionSelector::testSimplePredicate(unsigned) const {
857
0
    llvm_unreachable("ARMInstructionSelector does not support simple predicates!");
858
0
  return false;
859
0
}
860
// Custom renderers.
861
enum {
862
  GICR_Invalid,
863
  GICR_renderVFPF32Imm,
864
  GICR_renderVFPF64Imm,
865
};
866
ARMInstructionSelector::CustomRendererFn
867
ARMInstructionSelector::CustomRenderers[] = {
868
  nullptr, // GICR_Invalid
869
  &ARMInstructionSelector::renderVFPF32Imm,
870
  &ARMInstructionSelector::renderVFPF64Imm,
871
};
872
873
0
bool ARMInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
874
0
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
875
0
  MachineIRBuilder B(I);
876
0
  State.MIs.clear();
877
0
  State.MIs.push_back(&I);
878
879
0
  if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) {
880
0
    return true;
881
0
  }
882
883
0
  return false;
884
0
}
885
886
0
void ARMInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const {
887
0
    llvm_unreachable("ARMInstructionSelector does not support custom C++ actions!");
888
0
}
889
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
890
0
#define GIMT_Encode2(Val) uint8_t(Val), uint8_t((uint16_t)Val >> 8)
891
0
#define GIMT_Encode4(Val) uint8_t(Val), uint8_t((uint32_t)Val >> 8), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 24)
892
0
#define GIMT_Encode8(Val) uint8_t(Val), uint8_t((uint64_t)Val >> 8), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 24),  uint8_t((uint64_t)Val >> 32), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 56)
893
#else
894
#define GIMT_Encode2(Val) uint8_t((uint16_t)Val >> 8), uint8_t(Val)
895
#define GIMT_Encode4(Val) uint8_t((uint32_t)Val >> 24), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 8), uint8_t(Val)
896
#define GIMT_Encode8(Val) uint8_t((uint64_t)Val >> 56), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 32),  uint8_t((uint64_t)Val >> 24), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 8), uint8_t(Val)
897
#endif
898
0
const uint8_t *ARMInstructionSelector::getMatchTable() const {
899
0
  constexpr static uint8_t MatchTable0[] = {
900
0
    GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(47), GIMT_Encode2(269), /*)*//*default:*//*Label 74*/ GIMT_Encode4(157540),
901
0
    /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(898),
902
0
    /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(10663),
903
0
    /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(14339),
904
0
    /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(15397),
905
0
    /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(15522), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
906
0
    /*TargetOpcode::G_AND*//*Label 5*/ GIMT_Encode4(15647),
907
0
    /*TargetOpcode::G_OR*//*Label 6*/ GIMT_Encode4(19058),
908
0
    /*TargetOpcode::G_XOR*//*Label 7*/ GIMT_Encode4(25513), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
909
0
    /*TargetOpcode::G_CONCAT_VECTORS*//*Label 8*/ GIMT_Encode4(27380), GIMT_Encode4(0), GIMT_Encode4(0),
910
0
    /*TargetOpcode::G_BITCAST*//*Label 9*/ GIMT_Encode4(27889), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
911
0
    /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 10*/ GIMT_Encode4(41273),
912
0
    /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 11*/ GIMT_Encode4(41620), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
913
0
    /*TargetOpcode::G_SEXTLOAD*//*Label 12*/ GIMT_Encode4(41913), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
914
0
    /*TargetOpcode::G_FENCE*//*Label 13*/ GIMT_Encode4(42088), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
915
0
    /*TargetOpcode::G_INTRINSIC*//*Label 14*/ GIMT_Encode4(42114),
916
0
    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 15*/ GIMT_Encode4(112629), GIMT_Encode4(0), GIMT_Encode4(0),
917
0
    /*TargetOpcode::G_ANYEXT*//*Label 16*/ GIMT_Encode4(122223),
918
0
    /*TargetOpcode::G_TRUNC*//*Label 17*/ GIMT_Encode4(122414),
919
0
    /*TargetOpcode::G_CONSTANT*//*Label 18*/ GIMT_Encode4(122605),
920
0
    /*TargetOpcode::G_FCONSTANT*//*Label 19*/ GIMT_Encode4(122891), GIMT_Encode4(0), GIMT_Encode4(0),
921
0
    /*TargetOpcode::G_SEXT*//*Label 20*/ GIMT_Encode4(123001), GIMT_Encode4(0),
922
0
    /*TargetOpcode::G_ZEXT*//*Label 21*/ GIMT_Encode4(123192),
923
0
    /*TargetOpcode::G_SHL*//*Label 22*/ GIMT_Encode4(123845),
924
0
    /*TargetOpcode::G_LSHR*//*Label 23*/ GIMT_Encode4(123980),
925
0
    /*TargetOpcode::G_ASHR*//*Label 24*/ GIMT_Encode4(124052), GIMT_Encode4(0), GIMT_Encode4(0),
926
0
    /*TargetOpcode::G_ROTR*//*Label 25*/ GIMT_Encode4(124317), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
927
0
    /*TargetOpcode::G_UMULH*//*Label 26*/ GIMT_Encode4(124644),
928
0
    /*TargetOpcode::G_SMULH*//*Label 27*/ GIMT_Encode4(124931),
929
0
    /*TargetOpcode::G_UADDSAT*//*Label 28*/ GIMT_Encode4(125367),
930
0
    /*TargetOpcode::G_SADDSAT*//*Label 29*/ GIMT_Encode4(126165),
931
0
    /*TargetOpcode::G_USUBSAT*//*Label 30*/ GIMT_Encode4(127724),
932
0
    /*TargetOpcode::G_SSUBSAT*//*Label 31*/ GIMT_Encode4(128522), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
933
0
    /*TargetOpcode::G_FADD*//*Label 32*/ GIMT_Encode4(129761),
934
0
    /*TargetOpcode::G_FSUB*//*Label 33*/ GIMT_Encode4(132278),
935
0
    /*TargetOpcode::G_FMUL*//*Label 34*/ GIMT_Encode4(134131),
936
0
    /*TargetOpcode::G_FMA*//*Label 35*/ GIMT_Encode4(135288), GIMT_Encode4(0),
937
0
    /*TargetOpcode::G_FDIV*//*Label 36*/ GIMT_Encode4(137492), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
938
0
    /*TargetOpcode::G_FNEG*//*Label 37*/ GIMT_Encode4(137702),
939
0
    /*TargetOpcode::G_FPEXT*//*Label 38*/ GIMT_Encode4(139435),
940
0
    /*TargetOpcode::G_FPTRUNC*//*Label 39*/ GIMT_Encode4(139705),
941
0
    /*TargetOpcode::G_FPTOSI*//*Label 40*/ GIMT_Encode4(140015),
942
0
    /*TargetOpcode::G_FPTOUI*//*Label 41*/ GIMT_Encode4(141526),
943
0
    /*TargetOpcode::G_SITOFP*//*Label 42*/ GIMT_Encode4(143037),
944
0
    /*TargetOpcode::G_UITOFP*//*Label 43*/ GIMT_Encode4(143779),
945
0
    /*TargetOpcode::G_FABS*//*Label 44*/ GIMT_Encode4(144521), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
946
0
    /*TargetOpcode::G_FMINNUM*//*Label 45*/ GIMT_Encode4(145409),
947
0
    /*TargetOpcode::G_FMAXNUM*//*Label 46*/ GIMT_Encode4(146083), GIMT_Encode4(0), GIMT_Encode4(0),
948
0
    /*TargetOpcode::G_FMINIMUM*//*Label 47*/ GIMT_Encode4(146757),
949
0
    /*TargetOpcode::G_FMAXIMUM*//*Label 48*/ GIMT_Encode4(147553),
950
0
    /*TargetOpcode::G_GET_FPENV*//*Label 49*/ GIMT_Encode4(148349),
951
0
    /*TargetOpcode::G_SET_FPENV*//*Label 50*/ GIMT_Encode4(148390),
952
0
    /*TargetOpcode::G_RESET_FPENV*//*Label 51*/ GIMT_Encode4(148434),
953
0
    /*TargetOpcode::G_GET_FPMODE*//*Label 52*/ GIMT_Encode4(148565), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
954
0
    /*TargetOpcode::G_SMIN*//*Label 53*/ GIMT_Encode4(148606),
955
0
    /*TargetOpcode::G_SMAX*//*Label 54*/ GIMT_Encode4(149272),
956
0
    /*TargetOpcode::G_UMIN*//*Label 55*/ GIMT_Encode4(149938),
957
0
    /*TargetOpcode::G_UMAX*//*Label 56*/ GIMT_Encode4(151042),
958
0
    /*TargetOpcode::G_ABS*//*Label 57*/ GIMT_Encode4(152146), GIMT_Encode4(0), GIMT_Encode4(0),
959
0
    /*TargetOpcode::G_BR*//*Label 58*/ GIMT_Encode4(152905), GIMT_Encode4(0), GIMT_Encode4(0),
960
0
    /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 59*/ GIMT_Encode4(152991), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
961
0
    /*TargetOpcode::G_CTLZ*//*Label 60*/ GIMT_Encode4(153167), GIMT_Encode4(0),
962
0
    /*TargetOpcode::G_CTPOP*//*Label 61*/ GIMT_Encode4(153839),
963
0
    /*TargetOpcode::G_BSWAP*//*Label 62*/ GIMT_Encode4(153969),
964
0
    /*TargetOpcode::G_BITREVERSE*//*Label 63*/ GIMT_Encode4(154308),
965
0
    /*TargetOpcode::G_FCEIL*//*Label 64*/ GIMT_Encode4(154788), GIMT_Encode4(0), GIMT_Encode4(0),
966
0
    /*TargetOpcode::G_FSQRT*//*Label 65*/ GIMT_Encode4(155081),
967
0
    /*TargetOpcode::G_FFLOOR*//*Label 66*/ GIMT_Encode4(155252),
968
0
    /*TargetOpcode::G_FRINT*//*Label 67*/ GIMT_Encode4(155545),
969
0
    /*TargetOpcode::G_FNEARBYINT*//*Label 68*/ GIMT_Encode4(155892), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
970
0
    /*TargetOpcode::G_VECREDUCE_ADD*//*Label 69*/ GIMT_Encode4(156063), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
971
0
    /*TargetOpcode::G_VECREDUCE_SMAX*//*Label 70*/ GIMT_Encode4(156270),
972
0
    /*TargetOpcode::G_VECREDUCE_SMIN*//*Label 71*/ GIMT_Encode4(156581),
973
0
    /*TargetOpcode::G_VECREDUCE_UMAX*//*Label 72*/ GIMT_Encode4(156901),
974
0
    /*TargetOpcode::G_VECREDUCE_UMIN*//*Label 73*/ GIMT_Encode4(157213),
975
    // Label 0: @898
976
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 84*/ GIMT_Encode4(10662),
977
0
    /*GILLT_s32*//*Label 75*/ GIMT_Encode4(969),
978
0
    /*GILLT_s64*//*Label 76*/ GIMT_Encode4(3356), GIMT_Encode4(0),
979
0
    /*GILLT_v2s32*//*Label 77*/ GIMT_Encode4(3418),
980
0
    /*GILLT_v2s64*//*Label 78*/ GIMT_Encode4(3968), GIMT_Encode4(0),
981
0
    /*GILLT_v4s16*//*Label 79*/ GIMT_Encode4(5176),
982
0
    /*GILLT_v4s32*//*Label 80*/ GIMT_Encode4(5726), GIMT_Encode4(0), GIMT_Encode4(0),
983
0
    /*GILLT_v8s8*//*Label 81*/ GIMT_Encode4(7593),
984
0
    /*GILLT_v8s16*//*Label 82*/ GIMT_Encode4(8143), GIMT_Encode4(0), GIMT_Encode4(0),
985
0
    /*GILLT_v16s8*//*Label 83*/ GIMT_Encode4(10010),
986
    // Label 75: @969
987
0
    GIM_Try, /*On fail goto*//*Label 85*/ GIMT_Encode4(3355),
988
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
989
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
990
0
      GIM_Try, /*On fail goto*//*Label 86*/ GIMT_Encode4(1067), // Rule ID 5796 //
991
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
992
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
993
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
994
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
995
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
996
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
997
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
998
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
999
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1000
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1001
        // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1002
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UXTAB),
1003
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1004
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1005
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1006
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1007
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1008
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1009
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1010
0
        GIR_EraseFromParent, /*InsnID*/0,
1011
        // GIR_Coverage, 5796,
1012
0
        GIR_Done,
1013
      // Label 86: @1067
1014
0
      GIM_Try, /*On fail goto*//*Label 87*/ GIMT_Encode4(1152), // Rule ID 5797 //
1015
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
1016
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1017
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1018
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1019
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1020
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1021
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1022
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
1023
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1024
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1025
        // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1026
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UXTAH),
1027
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1028
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1029
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1030
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1031
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1032
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1033
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1034
0
        GIR_EraseFromParent, /*InsnID*/0,
1035
        // GIR_Coverage, 5797,
1036
0
        GIR_Done,
1037
      // Label 87: @1152
1038
0
      GIM_Try, /*On fail goto*//*Label 88*/ GIMT_Encode4(1237), // Rule ID 5831 //
1039
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1040
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1041
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1042
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1043
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1044
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1045
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1046
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
1047
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1048
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1049
        // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1050
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB),
1051
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1052
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1053
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1054
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1055
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1056
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1057
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1058
0
        GIR_EraseFromParent, /*InsnID*/0,
1059
        // GIR_Coverage, 5831,
1060
0
        GIR_Done,
1061
      // Label 88: @1237
1062
0
      GIM_Try, /*On fail goto*//*Label 89*/ GIMT_Encode4(1322), // Rule ID 5832 //
1063
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1064
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1065
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1066
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1067
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1068
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1069
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1070
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
1071
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1072
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1073
        // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1074
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UXTAH),
1075
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1076
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1077
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1078
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1079
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1080
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1081
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1082
0
        GIR_EraseFromParent, /*InsnID*/0,
1083
        // GIR_Coverage, 5832,
1084
0
        GIR_Done,
1085
      // Label 89: @1322
1086
0
      GIM_Try, /*On fail goto*//*Label 90*/ GIMT_Encode4(1407), // Rule ID 2018 //
1087
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
1088
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1089
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1090
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1091
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1092
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1093
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1094
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1095
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
1096
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1097
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }))  =>  (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1098
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UXTAB),
1099
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1100
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1101
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1102
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1103
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1104
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1105
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1106
0
        GIR_EraseFromParent, /*InsnID*/0,
1107
        // GIR_Coverage, 2018,
1108
0
        GIR_Done,
1109
      // Label 90: @1407
1110
0
      GIM_Try, /*On fail goto*//*Label 91*/ GIMT_Encode4(1492), // Rule ID 2019 //
1111
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
1112
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1113
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1114
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1115
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1116
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1117
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1118
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1119
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
1120
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1121
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }))  =>  (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1122
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UXTAH),
1123
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1124
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1125
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1126
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1127
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1128
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1129
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1130
0
        GIR_EraseFromParent, /*InsnID*/0,
1131
        // GIR_Coverage, 2019,
1132
0
        GIR_Done,
1133
      // Label 91: @1492
1134
0
      GIM_Try, /*On fail goto*//*Label 92*/ GIMT_Encode4(1577), // Rule ID 2246 //
1135
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1136
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1137
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1138
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1139
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1140
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1141
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1142
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1143
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
1144
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1145
        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }))  =>  (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1146
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB),
1147
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1148
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1149
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1150
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1151
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1152
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1153
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1154
0
        GIR_EraseFromParent, /*InsnID*/0,
1155
        // GIR_Coverage, 2246,
1156
0
        GIR_Done,
1157
      // Label 92: @1577
1158
0
      GIM_Try, /*On fail goto*//*Label 93*/ GIMT_Encode4(1662), // Rule ID 2247 //
1159
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1160
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1161
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1162
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1163
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1164
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1165
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1166
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1167
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
1168
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1169
        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }))  =>  (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1170
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UXTAH),
1171
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1172
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1173
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1174
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1175
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1176
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1177
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1178
0
        GIR_EraseFromParent, /*InsnID*/0,
1179
        // GIR_Coverage, 2247,
1180
0
        GIR_Done,
1181
      // Label 93: @1662
1182
0
      GIM_Try, /*On fail goto*//*Label 94*/ GIMT_Encode4(1786), // Rule ID 5575 //
1183
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps),
1184
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1185
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1186
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1187
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1188
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1189
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1190
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1191
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1192
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1193
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1194
0
        GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1195
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1196
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1197
0
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1198
0
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1199
0
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1200
0
        GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1201
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1202
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1203
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1204
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1205
        // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra)  =>  (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1206
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMLATT),
1207
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1208
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1209
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1210
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1211
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1212
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1213
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1214
0
        GIR_EraseFromParent, /*InsnID*/0,
1215
        // GIR_Coverage, 5575,
1216
0
        GIR_Done,
1217
      // Label 94: @1786
1218
0
      GIM_Try, /*On fail goto*//*Label 95*/ GIMT_Encode4(1910), // Rule ID 5612 //
1219
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
1220
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1221
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1222
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1223
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1224
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1225
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1226
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1227
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1228
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1229
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1230
0
        GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1231
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1232
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1233
0
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1234
0
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1235
0
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1236
0
        GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1237
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1238
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1239
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1240
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1241
        // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra)  =>  (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1242
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT),
1243
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1244
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1245
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1246
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1247
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1248
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1249
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1250
0
        GIR_EraseFromParent, /*InsnID*/0,
1251
        // GIR_Coverage, 5612,
1252
0
        GIR_Done,
1253
      // Label 95: @1910
1254
0
      GIM_Try, /*On fail goto*//*Label 96*/ GIMT_Encode4(2034), // Rule ID 192 //
1255
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps),
1256
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1257
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1258
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1259
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1260
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1261
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1262
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1263
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1264
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1265
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1266
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1267
0
        GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1268
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1269
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1270
0
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1271
0
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1272
0
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1273
0
        GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1274
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1275
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1276
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1277
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })))  =>  (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1278
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMLATT),
1279
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1280
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1281
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1282
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1283
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1284
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1285
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1286
0
        GIR_EraseFromParent, /*InsnID*/0,
1287
        // GIR_Coverage, 192,
1288
0
        GIR_Done,
1289
      // Label 96: @2034
1290
0
      GIM_Try, /*On fail goto*//*Label 97*/ GIMT_Encode4(2158), // Rule ID 529 //
1291
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
1292
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1293
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1294
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1295
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1296
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1297
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1298
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1299
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1300
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1301
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1302
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1303
0
        GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1304
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1305
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1306
0
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1307
0
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1308
0
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1309
0
        GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1310
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1311
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1312
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
1313
        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })))  =>  (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1314
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT),
1315
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1316
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1317
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1318
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1319
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1320
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1321
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1322
0
        GIR_EraseFromParent, /*InsnID*/0,
1323
        // GIR_Coverage, 529,
1324
0
        GIR_Done,
1325
      // Label 97: @2158
1326
0
      GIM_Try, /*On fail goto*//*Label 98*/ GIMT_Encode4(2225), // Rule ID 72 //
1327
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
1328
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1329
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1330
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1331
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
1332
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
1333
        // MIs[1] Operand 1
1334
        // No operand predicates
1335
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1336
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (ADDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1337
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::ADDri),
1338
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1339
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1340
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1341
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1342
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1343
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1344
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1345
0
        GIR_EraseFromParent, /*InsnID*/0,
1346
        // GIR_Coverage, 72,
1347
0
        GIR_Done,
1348
      // Label 98: @2225
1349
0
      GIM_Try, /*On fail goto*//*Label 99*/ GIMT_Encode4(2292), // Rule ID 415 //
1350
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
1351
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1352
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1353
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1354
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
1355
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
1356
        // MIs[1] Operand 1
1357
        // No operand predicates
1358
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1359
        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2ADDri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1360
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2ADDri),
1361
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1362
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1363
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1364
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1365
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1366
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1367
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1368
0
        GIR_EraseFromParent, /*InsnID*/0,
1369
        // GIR_Coverage, 415,
1370
0
        GIR_Done,
1371
      // Label 99: @2292
1372
0
      GIM_Try, /*On fail goto*//*Label 100*/ GIMT_Encode4(2353), // Rule ID 416 //
1373
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
1374
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1375
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1376
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1377
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
1378
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_4095),
1379
        // MIs[1] Operand 1
1380
        // No operand predicates
1381
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1382
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm)  =>  (t2ADDri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1383
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2ADDri12),
1384
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1385
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1386
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1387
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1388
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1389
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1390
0
        GIR_EraseFromParent, /*InsnID*/0,
1391
        // GIR_Coverage, 416,
1392
0
        GIR_Done,
1393
      // Label 100: @2353
1394
0
      GIM_Try, /*On fail goto*//*Label 101*/ GIMT_Encode4(2439), // Rule ID 171 //
1395
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps),
1396
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1397
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1398
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1399
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1400
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1401
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1402
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1403
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1404
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1405
        // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra)  =>  (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1406
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MLA),
1407
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1408
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1409
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1410
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1411
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1412
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1413
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1414
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1415
0
        GIR_EraseFromParent, /*InsnID*/0,
1416
        // GIR_Coverage, 171,
1417
0
        GIR_Done,
1418
      // Label 101: @2439
1419
0
      GIM_Try, /*On fail goto*//*Label 102*/ GIMT_Encode4(2525), // Rule ID 172 //
1420
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV6),
1421
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1422
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1423
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1424
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1425
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1426
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1427
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1428
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1429
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1430
        // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra)  =>  (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1431
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MLAv5),
1432
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1433
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1434
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1435
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1436
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1437
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1438
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1439
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1440
0
        GIR_EraseFromParent, /*InsnID*/0,
1441
        // GIR_Coverage, 172,
1442
0
        GIR_Done,
1443
      // Label 102: @2525
1444
0
      GIM_Try, /*On fail goto*//*Label 103*/ GIMT_Encode4(2605), // Rule ID 511 //
1445
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_UseMulOps),
1446
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1447
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1448
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1449
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1450
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1451
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1452
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1453
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1454
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1455
        // (add:{ *:[i32] } (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm), rGPR:{ *:[i32] }:$Ra)  =>  (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1456
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2MLA),
1457
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1458
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1459
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1460
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1461
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1462
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1463
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1464
0
        GIR_EraseFromParent, /*InsnID*/0,
1465
        // GIR_Coverage, 511,
1466
0
        GIR_Done,
1467
      // Label 103: @2605
1468
0
      GIM_Try, /*On fail goto*//*Label 104*/ GIMT_Encode4(2685), // Rule ID 180 //
1469
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps),
1470
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1471
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1472
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH),
1473
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1474
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1475
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1476
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1477
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1478
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1479
        // (add:{ *:[i32] } (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm), GPR:{ *:[i32] }:$Ra)  =>  (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1480
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMMLA),
1481
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1482
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1483
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1484
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1485
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1486
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1487
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1488
0
        GIR_EraseFromParent, /*InsnID*/0,
1489
        // GIR_Coverage, 180,
1490
0
        GIR_Done,
1491
      // Label 104: @2685
1492
0
      GIM_Try, /*On fail goto*//*Label 105*/ GIMT_Encode4(2765), // Rule ID 517 //
1493
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
1494
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1495
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1496
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH),
1497
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1498
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1499
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1500
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1501
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1502
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1503
        // (add:{ *:[i32] } (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Ra)  =>  (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1504
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMMLA),
1505
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1506
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1507
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1508
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1509
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1510
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1511
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1512
0
        GIR_EraseFromParent, /*InsnID*/0,
1513
        // GIR_Coverage, 517,
1514
0
        GIR_Done,
1515
      // Label 105: @2765
1516
0
      GIM_Try, /*On fail goto*//*Label 106*/ GIMT_Encode4(2851), // Rule ID 5569 //
1517
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps),
1518
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1519
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1520
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1521
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1522
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1523
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1524
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1525
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1526
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1527
        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm))  =>  (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1528
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MLA),
1529
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1530
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1531
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1532
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1533
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1534
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1535
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1536
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1537
0
        GIR_EraseFromParent, /*InsnID*/0,
1538
        // GIR_Coverage, 5569,
1539
0
        GIR_Done,
1540
      // Label 106: @2851
1541
0
      GIM_Try, /*On fail goto*//*Label 107*/ GIMT_Encode4(2937), // Rule ID 5570 //
1542
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV6),
1543
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1544
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1545
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1546
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1547
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1548
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1549
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1550
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1551
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1552
        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm))  =>  (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1553
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MLAv5),
1554
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1555
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1556
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1557
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1558
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1559
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1560
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1561
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1562
0
        GIR_EraseFromParent, /*InsnID*/0,
1563
        // GIR_Coverage, 5570,
1564
0
        GIR_Done,
1565
      // Label 107: @2937
1566
0
      GIM_Try, /*On fail goto*//*Label 108*/ GIMT_Encode4(3017), // Rule ID 5607 //
1567
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_UseMulOps),
1568
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1569
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1570
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1571
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1572
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1573
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1574
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1575
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1576
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1577
        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm))  =>  (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1578
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2MLA),
1579
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1580
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1581
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1582
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1583
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1584
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1585
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1586
0
        GIR_EraseFromParent, /*InsnID*/0,
1587
        // GIR_Coverage, 5607,
1588
0
        GIR_Done,
1589
      // Label 108: @3017
1590
0
      GIM_Try, /*On fail goto*//*Label 109*/ GIMT_Encode4(3097), // Rule ID 5571 //
1591
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps),
1592
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1593
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1594
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1595
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH),
1596
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1597
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1598
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1599
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1600
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1601
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm))  =>  (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1602
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMMLA),
1603
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1604
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1605
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1606
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1607
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1608
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1609
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1610
0
        GIR_EraseFromParent, /*InsnID*/0,
1611
        // GIR_Coverage, 5571,
1612
0
        GIR_Done,
1613
      // Label 109: @3097
1614
0
      GIM_Try, /*On fail goto*//*Label 110*/ GIMT_Encode4(3177), // Rule ID 5608 //
1615
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
1616
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1617
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1618
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1619
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH),
1620
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1621
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1622
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1623
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1624
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1625
        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn))  =>  (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1626
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMMLA),
1627
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1628
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1629
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1630
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1631
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1632
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1633
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1634
0
        GIR_EraseFromParent, /*InsnID*/0,
1635
        // GIR_Coverage, 5608,
1636
0
        GIR_Done,
1637
      // Label 110: @3177
1638
0
      GIM_Try, /*On fail goto*//*Label 111*/ GIMT_Encode4(3236), // Rule ID 73 //
1639
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
1640
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1641
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1642
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1643
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (ADDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
1644
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::ADDrr),
1645
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1646
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1647
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
1648
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1649
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1650
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1651
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1652
0
        GIR_EraseFromParent, /*InsnID*/0,
1653
        // GIR_Coverage, 73,
1654
0
        GIR_Done,
1655
      // Label 111: @3236
1656
0
      GIM_Try, /*On fail goto*//*Label 112*/ GIMT_Encode4(3295), // Rule ID 417 //
1657
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
1658
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1659
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1660
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1661
        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
1662
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2ADDrr),
1663
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1664
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1665
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
1666
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1667
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1668
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1669
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1670
0
        GIR_EraseFromParent, /*InsnID*/0,
1671
        // GIR_Coverage, 417,
1672
0
        GIR_Done,
1673
      // Label 112: @3295
1674
0
      GIM_Try, /*On fail goto*//*Label 113*/ GIMT_Encode4(3354), // Rule ID 5589 //
1675
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
1676
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1677
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1678
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1679
        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)  =>  (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
1680
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2ADDrr),
1681
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
1682
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1683
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
1684
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1685
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1686
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1687
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1688
0
        GIR_EraseFromParent, /*InsnID*/0,
1689
        // GIR_Coverage, 5589,
1690
0
        GIR_Done,
1691
      // Label 113: @3354
1692
0
      GIM_Reject,
1693
    // Label 85: @3355
1694
0
    GIM_Reject,
1695
    // Label 76: @3356
1696
0
    GIM_Try, /*On fail goto*//*Label 114*/ GIMT_Encode4(3417), // Rule ID 779 //
1697
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
1698
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1699
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1700
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1701
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1702
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1703
      // (add:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VADDv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
1704
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDv1i64),
1705
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
1706
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1707
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
1708
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1709
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1710
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1711
0
      GIR_EraseFromParent, /*InsnID*/0,
1712
      // GIR_Coverage, 779,
1713
0
      GIR_Done,
1714
    // Label 114: @3417
1715
0
    GIM_Reject,
1716
    // Label 77: @3418
1717
0
    GIM_Try, /*On fail goto*//*Label 115*/ GIMT_Encode4(3967),
1718
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1719
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
1720
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1721
0
      GIM_Try, /*On fail goto*//*Label 116*/ GIMT_Encode4(3519), // Rule ID 5728 //
1722
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
1723
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1724
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
1725
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1726
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
1727
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1728
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1729
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1730
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1731
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1732
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1733
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 3062:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1)  =>  (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1734
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAsv2i32),
1735
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
1736
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1737
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1738
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1739
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1740
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1741
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1742
0
        GIR_EraseFromParent, /*InsnID*/0,
1743
        // GIR_Coverage, 5728,
1744
0
        GIR_Done,
1745
      // Label 116: @3519
1746
0
      GIM_Try, /*On fail goto*//*Label 117*/ GIMT_Encode4(3602), // Rule ID 5734 //
1747
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
1748
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1749
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
1750
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1751
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
1752
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1753
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1754
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1755
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1756
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1757
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1758
        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 3063:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1)  =>  (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1759
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAuv2i32),
1760
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
1761
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1762
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1763
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1764
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1765
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1766
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1767
0
        GIR_EraseFromParent, /*InsnID*/0,
1768
        // GIR_Coverage, 5734,
1769
0
        GIR_Done,
1770
      // Label 117: @3602
1771
0
      GIM_Try, /*On fail goto*//*Label 118*/ GIMT_Encode4(3685), // Rule ID 1200 //
1772
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
1773
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1774
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1775
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
1776
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1777
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
1778
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1779
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1780
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1781
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1782
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1783
        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 3062:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1784
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAsv2i32),
1785
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
1786
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1787
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1788
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1789
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1790
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1791
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1792
0
        GIR_EraseFromParent, /*InsnID*/0,
1793
        // GIR_Coverage, 1200,
1794
0
        GIR_Done,
1795
      // Label 118: @3685
1796
0
      GIM_Try, /*On fail goto*//*Label 119*/ GIMT_Encode4(3768), // Rule ID 1206 //
1797
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
1798
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1799
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1800
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
1801
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1802
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
1803
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1804
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1805
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1806
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1807
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1808
        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 3063:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1809
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAuv2i32),
1810
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
1811
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1812
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1813
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1814
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1815
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1816
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1817
0
        GIR_EraseFromParent, /*InsnID*/0,
1818
        // GIR_Coverage, 1206,
1819
0
        GIR_Done,
1820
      // Label 119: @3768
1821
0
      GIM_Try, /*On fail goto*//*Label 120*/ GIMT_Encode4(3843), // Rule ID 5658 //
1822
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
1823
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1824
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1825
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1826
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1827
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1828
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1829
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1830
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1831
        // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1)  =>  (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1832
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMLAv2i32),
1833
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
1834
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1835
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1836
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
1837
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1838
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1839
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1840
0
        GIR_EraseFromParent, /*InsnID*/0,
1841
        // GIR_Coverage, 5658,
1842
0
        GIR_Done,
1843
      // Label 120: @3843
1844
0
      GIM_Try, /*On fail goto*//*Label 121*/ GIMT_Encode4(3918), // Rule ID 906 //
1845
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
1846
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1847
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1848
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1849
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1850
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1851
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1852
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1853
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1854
        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1855
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMLAv2i32),
1856
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
1857
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1858
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1859
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
1860
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1861
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1862
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1863
0
        GIR_EraseFromParent, /*InsnID*/0,
1864
        // GIR_Coverage, 906,
1865
0
        GIR_Done,
1866
      // Label 121: @3918
1867
0
      GIM_Try, /*On fail goto*//*Label 122*/ GIMT_Encode4(3966), // Rule ID 775 //
1868
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
1869
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1870
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1871
        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VADDv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1872
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDv2i32),
1873
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
1874
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1875
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
1876
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1877
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1878
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1879
0
        GIR_EraseFromParent, /*InsnID*/0,
1880
        // GIR_Coverage, 775,
1881
0
        GIR_Done,
1882
      // Label 122: @3966
1883
0
      GIM_Reject,
1884
    // Label 115: @3967
1885
0
    GIM_Reject,
1886
    // Label 78: @3968
1887
0
    GIM_Try, /*On fail goto*//*Label 123*/ GIMT_Encode4(5175),
1888
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1889
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1890
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
1891
0
      GIM_Try, /*On fail goto*//*Label 124*/ GIMT_Encode4(4083), // Rule ID 5740 //
1892
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
1893
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1894
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
1895
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1896
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1897
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
1898
0
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1899
0
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
1900
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1901
0
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1902
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1903
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1904
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
1905
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1906
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1907
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 3062:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1)  =>  (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1908
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABALsv2i64),
1909
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
1910
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1911
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1912
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1913
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1914
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1915
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1916
0
        GIR_EraseFromParent, /*InsnID*/0,
1917
        // GIR_Coverage, 5740,
1918
0
        GIR_Done,
1919
      // Label 124: @4083
1920
0
      GIM_Try, /*On fail goto*//*Label 125*/ GIMT_Encode4(4180), // Rule ID 5743 //
1921
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
1922
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1923
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
1924
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1925
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1926
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
1927
0
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1928
0
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
1929
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1930
0
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1931
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1932
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1933
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
1934
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1935
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1936
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 3063:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1)  =>  (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1937
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABALuv2i64),
1938
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
1939
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1940
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1941
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1942
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1943
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1944
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1945
0
        GIR_EraseFromParent, /*InsnID*/0,
1946
        // GIR_Coverage, 5743,
1947
0
        GIR_Done,
1948
      // Label 125: @4180
1949
0
      GIM_Try, /*On fail goto*//*Label 126*/ GIMT_Encode4(4277), // Rule ID 1212 //
1950
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
1951
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
1952
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1953
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
1954
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1955
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1956
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
1957
0
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1958
0
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
1959
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1960
0
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1961
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1962
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1963
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1964
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1965
        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 3062:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)))  =>  (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1966
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABALsv2i64),
1967
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
1968
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1969
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1970
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1971
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1972
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1973
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1974
0
        GIR_EraseFromParent, /*InsnID*/0,
1975
        // GIR_Coverage, 1212,
1976
0
        GIR_Done,
1977
      // Label 126: @4277
1978
0
      GIM_Try, /*On fail goto*//*Label 127*/ GIMT_Encode4(4374), // Rule ID 1215 //
1979
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
1980
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
1981
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1982
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
1983
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1984
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1985
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
1986
0
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1987
0
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
1988
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1989
0
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1990
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1991
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
1992
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1993
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
1994
        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 3063:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)))  =>  (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1995
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABALuv2i64),
1996
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
1997
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1998
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1999
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2000
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2001
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2002
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2003
0
        GIR_EraseFromParent, /*InsnID*/0,
2004
        // GIR_Coverage, 1215,
2005
0
        GIR_Done,
2006
      // Label 127: @4374
2007
0
      GIM_Try, /*On fail goto*//*Label 128*/ GIMT_Encode4(4450), // Rule ID 799 //
2008
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2009
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2010
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
2011
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2012
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2013
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2014
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
2015
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
2016
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2017
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2018
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2019
        // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2020
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64),
2021
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2022
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2023
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2024
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2025
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2026
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2027
0
        GIR_EraseFromParent, /*InsnID*/0,
2028
        // GIR_Coverage, 799,
2029
0
        GIR_Done,
2030
      // Label 128: @4450
2031
0
      GIM_Try, /*On fail goto*//*Label 129*/ GIMT_Encode4(4526), // Rule ID 798 //
2032
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2033
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2034
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
2035
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2036
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2037
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2038
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
2039
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
2040
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2041
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2042
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2043
        // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2044
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64),
2045
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2046
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2047
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2048
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2049
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2050
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2051
0
        GIR_EraseFromParent, /*InsnID*/0,
2052
        // GIR_Coverage, 798,
2053
0
        GIR_Done,
2054
      // Label 129: @4526
2055
0
      GIM_Try, /*On fail goto*//*Label 130*/ GIMT_Encode4(4602), // Rule ID 787 //
2056
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2057
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2058
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
2059
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2060
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2061
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2062
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
2063
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
2064
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2065
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2066
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2067
        // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2068
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDLsv2i64),
2069
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2070
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2071
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2072
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2073
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2074
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2075
0
        GIR_EraseFromParent, /*InsnID*/0,
2076
        // GIR_Coverage, 787,
2077
0
        GIR_Done,
2078
      // Label 130: @4602
2079
0
      GIM_Try, /*On fail goto*//*Label 131*/ GIMT_Encode4(4678), // Rule ID 797 //
2080
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2081
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2082
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
2083
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2084
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2085
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2086
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
2087
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
2088
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2089
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2090
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2091
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2092
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64),
2093
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2094
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2095
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2096
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2097
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2098
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2099
0
        GIR_EraseFromParent, /*InsnID*/0,
2100
        // GIR_Coverage, 797,
2101
0
        GIR_Done,
2102
      // Label 131: @4678
2103
0
      GIM_Try, /*On fail goto*//*Label 132*/ GIMT_Encode4(4754), // Rule ID 796 //
2104
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2105
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2106
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
2107
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2108
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2109
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2110
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
2111
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
2112
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2113
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2114
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2115
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2116
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64),
2117
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2118
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2119
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2120
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2121
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2122
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2123
0
        GIR_EraseFromParent, /*InsnID*/0,
2124
        // GIR_Coverage, 796,
2125
0
        GIR_Done,
2126
      // Label 132: @4754
2127
0
      GIM_Try, /*On fail goto*//*Label 133*/ GIMT_Encode4(4816), // Rule ID 5637 //
2128
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2129
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2130
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
2131
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2132
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2133
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2134
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2135
        // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn)  =>  (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2136
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64),
2137
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2138
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2139
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2140
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2141
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2142
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2143
0
        GIR_EraseFromParent, /*InsnID*/0,
2144
        // GIR_Coverage, 5637,
2145
0
        GIR_Done,
2146
      // Label 133: @4816
2147
0
      GIM_Try, /*On fail goto*//*Label 134*/ GIMT_Encode4(4878), // Rule ID 5631 //
2148
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2149
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2150
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
2151
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2152
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2153
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2154
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2155
        // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn)  =>  (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2156
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDWsv2i64),
2157
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2158
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2159
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2160
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2161
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2162
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2163
0
        GIR_EraseFromParent, /*InsnID*/0,
2164
        // GIR_Coverage, 5631,
2165
0
        GIR_Done,
2166
      // Label 134: @4878
2167
0
      GIM_Try, /*On fail goto*//*Label 135*/ GIMT_Encode4(4940), // Rule ID 5636 //
2168
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2169
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2170
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
2171
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2172
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2173
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2174
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2175
        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn)  =>  (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2176
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64),
2177
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2178
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2179
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2180
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2181
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2182
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2183
0
        GIR_EraseFromParent, /*InsnID*/0,
2184
        // GIR_Coverage, 5636,
2185
0
        GIR_Done,
2186
      // Label 135: @4940
2187
0
      GIM_Try, /*On fail goto*//*Label 136*/ GIMT_Encode4(5002), // Rule ID 808 //
2188
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2189
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2190
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2191
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
2192
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2193
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2194
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2195
        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2196
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64),
2197
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2198
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2199
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2200
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2201
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2202
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2203
0
        GIR_EraseFromParent, /*InsnID*/0,
2204
        // GIR_Coverage, 808,
2205
0
        GIR_Done,
2206
      // Label 136: @5002
2207
0
      GIM_Try, /*On fail goto*//*Label 137*/ GIMT_Encode4(5064), // Rule ID 802 //
2208
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2209
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2210
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2211
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
2212
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2213
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2214
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2215
        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2216
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDWsv2i64),
2217
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2218
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2219
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2220
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2221
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2222
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2223
0
        GIR_EraseFromParent, /*InsnID*/0,
2224
        // GIR_Coverage, 802,
2225
0
        GIR_Done,
2226
      // Label 137: @5064
2227
0
      GIM_Try, /*On fail goto*//*Label 138*/ GIMT_Encode4(5126), // Rule ID 807 //
2228
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2229
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2230
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2231
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
2232
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2233
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2234
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2235
        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2236
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64),
2237
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2238
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2239
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2240
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2241
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2242
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2243
0
        GIR_EraseFromParent, /*InsnID*/0,
2244
        // GIR_Coverage, 807,
2245
0
        GIR_Done,
2246
      // Label 138: @5126
2247
0
      GIM_Try, /*On fail goto*//*Label 139*/ GIMT_Encode4(5174), // Rule ID 780 //
2248
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2249
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2250
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2251
        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VADDv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
2252
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDv2i64),
2253
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2254
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2255
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2256
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2257
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2258
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2259
0
        GIR_EraseFromParent, /*InsnID*/0,
2260
        // GIR_Coverage, 780,
2261
0
        GIR_Done,
2262
      // Label 139: @5174
2263
0
      GIM_Reject,
2264
    // Label 123: @5175
2265
0
    GIM_Reject,
2266
    // Label 79: @5176
2267
0
    GIM_Try, /*On fail goto*//*Label 140*/ GIMT_Encode4(5725),
2268
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
2269
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
2270
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2271
0
      GIM_Try, /*On fail goto*//*Label 141*/ GIMT_Encode4(5277), // Rule ID 5727 //
2272
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2273
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2274
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2275
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2276
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
2277
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2278
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2279
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2280
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2281
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2282
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2283
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 3062:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1)  =>  (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2284
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i16),
2285
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2286
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2287
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2288
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2289
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2290
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2291
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2292
0
        GIR_EraseFromParent, /*InsnID*/0,
2293
        // GIR_Coverage, 5727,
2294
0
        GIR_Done,
2295
      // Label 141: @5277
2296
0
      GIM_Try, /*On fail goto*//*Label 142*/ GIMT_Encode4(5360), // Rule ID 5733 //
2297
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2298
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2299
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2300
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2301
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
2302
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2303
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2304
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2305
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2306
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2307
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2308
        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 3063:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1)  =>  (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2309
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i16),
2310
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2311
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2312
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2313
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2314
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2315
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2316
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2317
0
        GIR_EraseFromParent, /*InsnID*/0,
2318
        // GIR_Coverage, 5733,
2319
0
        GIR_Done,
2320
      // Label 142: @5360
2321
0
      GIM_Try, /*On fail goto*//*Label 143*/ GIMT_Encode4(5443), // Rule ID 1199 //
2322
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2323
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2324
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2325
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2326
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2327
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
2328
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2329
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2330
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2331
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2332
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2333
        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (intrinsic_wo_chain:{ *:[v4i16] } 3062:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2334
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i16),
2335
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2336
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2337
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2338
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2339
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2340
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2341
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2342
0
        GIR_EraseFromParent, /*InsnID*/0,
2343
        // GIR_Coverage, 1199,
2344
0
        GIR_Done,
2345
      // Label 143: @5443
2346
0
      GIM_Try, /*On fail goto*//*Label 144*/ GIMT_Encode4(5526), // Rule ID 1205 //
2347
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2348
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2349
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2350
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2351
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2352
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
2353
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2354
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2355
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2356
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2357
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2358
        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (intrinsic_wo_chain:{ *:[v4i16] } 3063:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2359
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i16),
2360
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2361
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2362
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2363
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2364
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2365
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2366
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2367
0
        GIR_EraseFromParent, /*InsnID*/0,
2368
        // GIR_Coverage, 1205,
2369
0
        GIR_Done,
2370
      // Label 144: @5526
2371
0
      GIM_Try, /*On fail goto*//*Label 145*/ GIMT_Encode4(5601), // Rule ID 5657 //
2372
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2373
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2374
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2375
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2376
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2377
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2378
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2379
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2380
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2381
        // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1)  =>  (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2382
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i16),
2383
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2384
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2385
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2386
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2387
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2388
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2389
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2390
0
        GIR_EraseFromParent, /*InsnID*/0,
2391
        // GIR_Coverage, 5657,
2392
0
        GIR_Done,
2393
      // Label 145: @5601
2394
0
      GIM_Try, /*On fail goto*//*Label 146*/ GIMT_Encode4(5676), // Rule ID 905 //
2395
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2396
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2397
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2398
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2399
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2400
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2401
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2402
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2403
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2404
        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2405
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i16),
2406
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2407
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2408
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2409
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2410
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2411
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2412
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2413
0
        GIR_EraseFromParent, /*InsnID*/0,
2414
        // GIR_Coverage, 905,
2415
0
        GIR_Done,
2416
      // Label 146: @5676
2417
0
      GIM_Try, /*On fail goto*//*Label 147*/ GIMT_Encode4(5724), // Rule ID 774 //
2418
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2419
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2420
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2421
        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VADDv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2422
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDv4i16),
2423
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2424
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2425
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2426
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2427
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2428
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2429
0
        GIR_EraseFromParent, /*InsnID*/0,
2430
        // GIR_Coverage, 774,
2431
0
        GIR_Done,
2432
      // Label 147: @5724
2433
0
      GIM_Reject,
2434
    // Label 140: @5725
2435
0
    GIM_Reject,
2436
    // Label 80: @5726
2437
0
    GIM_Try, /*On fail goto*//*Label 148*/ GIMT_Encode4(7592),
2438
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2439
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2440
0
      GIM_Try, /*On fail goto*//*Label 149*/ GIMT_Encode4(5841), // Rule ID 5739 //
2441
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2442
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2443
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2444
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
2445
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2446
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2447
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2448
0
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2449
0
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
2450
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2451
0
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2452
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2453
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2454
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2455
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2456
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2457
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 3062:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1)  =>  (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2458
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABALsv4i32),
2459
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2460
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2461
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2462
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2463
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2464
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2465
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2466
0
        GIR_EraseFromParent, /*InsnID*/0,
2467
        // GIR_Coverage, 5739,
2468
0
        GIR_Done,
2469
      // Label 149: @5841
2470
0
      GIM_Try, /*On fail goto*//*Label 150*/ GIMT_Encode4(5943), // Rule ID 5742 //
2471
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2472
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2473
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2474
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
2475
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2476
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2477
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2478
0
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2479
0
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
2480
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2481
0
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2482
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2483
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2484
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2485
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2486
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2487
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 3063:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1)  =>  (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2488
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABALuv4i32),
2489
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2490
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2491
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2492
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2493
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2494
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2495
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2496
0
        GIR_EraseFromParent, /*InsnID*/0,
2497
        // GIR_Coverage, 5742,
2498
0
        GIR_Done,
2499
      // Label 150: @5943
2500
0
      GIM_Try, /*On fail goto*//*Label 151*/ GIMT_Encode4(6045), // Rule ID 1211 //
2501
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2502
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2503
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2504
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2505
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
2506
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2507
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2508
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2509
0
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2510
0
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
2511
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2512
0
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2513
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2514
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2515
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2516
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2517
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 3062:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)))  =>  (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2518
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABALsv4i32),
2519
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2520
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2521
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2522
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2523
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2524
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2525
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2526
0
        GIR_EraseFromParent, /*InsnID*/0,
2527
        // GIR_Coverage, 1211,
2528
0
        GIR_Done,
2529
      // Label 151: @6045
2530
0
      GIM_Try, /*On fail goto*//*Label 152*/ GIMT_Encode4(6147), // Rule ID 1214 //
2531
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2532
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2533
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2534
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2535
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
2536
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2537
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2538
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2539
0
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2540
0
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
2541
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2542
0
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2543
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2544
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2545
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2546
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2547
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 3063:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)))  =>  (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2548
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABALuv4i32),
2549
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2550
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2551
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2552
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2553
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2554
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2555
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2556
0
        GIR_EraseFromParent, /*InsnID*/0,
2557
        // GIR_Coverage, 1214,
2558
0
        GIR_Done,
2559
      // Label 152: @6147
2560
0
      GIM_Try, /*On fail goto*//*Label 153*/ GIMT_Encode4(6235), // Rule ID 5731 //
2561
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2562
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2563
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2564
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2565
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2566
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
2567
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2568
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2569
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2570
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2571
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2572
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2573
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 3062:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2574
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i32),
2575
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2576
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2577
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2578
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2579
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2580
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2581
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2582
0
        GIR_EraseFromParent, /*InsnID*/0,
2583
        // GIR_Coverage, 5731,
2584
0
        GIR_Done,
2585
      // Label 153: @6235
2586
0
      GIM_Try, /*On fail goto*//*Label 154*/ GIMT_Encode4(6323), // Rule ID 5737 //
2587
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2588
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2589
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2590
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2591
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2592
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
2593
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2594
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2595
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2596
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2597
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2598
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2599
        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 3063:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2600
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i32),
2601
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2602
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2603
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2604
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2605
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2606
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2607
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2608
0
        GIR_EraseFromParent, /*InsnID*/0,
2609
        // GIR_Coverage, 5737,
2610
0
        GIR_Done,
2611
      // Label 154: @6323
2612
0
      GIM_Try, /*On fail goto*//*Label 155*/ GIMT_Encode4(6411), // Rule ID 1203 //
2613
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2614
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2615
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2616
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2617
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2618
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2619
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
2620
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2621
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2622
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2623
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2624
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2625
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 3062:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2626
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i32),
2627
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2628
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2629
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2630
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2631
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2632
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2633
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2634
0
        GIR_EraseFromParent, /*InsnID*/0,
2635
        // GIR_Coverage, 1203,
2636
0
        GIR_Done,
2637
      // Label 155: @6411
2638
0
      GIM_Try, /*On fail goto*//*Label 156*/ GIMT_Encode4(6499), // Rule ID 1209 //
2639
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2640
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2641
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2642
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2643
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2644
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2645
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
2646
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2647
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2648
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2649
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2650
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2651
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 3063:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2652
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i32),
2653
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2654
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2655
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2656
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2657
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2658
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2659
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2660
0
        GIR_EraseFromParent, /*InsnID*/0,
2661
        // GIR_Coverage, 1209,
2662
0
        GIR_Done,
2663
      // Label 156: @6499
2664
0
      GIM_Try, /*On fail goto*//*Label 157*/ GIMT_Encode4(6580), // Rule ID 795 //
2665
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2666
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2667
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2668
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
2669
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2670
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2671
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2672
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
2673
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2674
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2675
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2676
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2677
        // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2678
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32),
2679
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2680
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2681
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2682
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2683
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2684
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2685
0
        GIR_EraseFromParent, /*InsnID*/0,
2686
        // GIR_Coverage, 795,
2687
0
        GIR_Done,
2688
      // Label 157: @6580
2689
0
      GIM_Try, /*On fail goto*//*Label 158*/ GIMT_Encode4(6661), // Rule ID 794 //
2690
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2691
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2692
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2693
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
2694
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2695
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2696
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2697
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
2698
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2699
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2700
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2701
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2702
        // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2703
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32),
2704
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2705
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2706
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2707
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2708
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2709
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2710
0
        GIR_EraseFromParent, /*InsnID*/0,
2711
        // GIR_Coverage, 794,
2712
0
        GIR_Done,
2713
      // Label 158: @6661
2714
0
      GIM_Try, /*On fail goto*//*Label 159*/ GIMT_Encode4(6742), // Rule ID 786 //
2715
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2716
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2717
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2718
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
2719
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2720
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2721
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2722
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
2723
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2724
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2725
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2726
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2727
        // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2728
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDLsv4i32),
2729
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2730
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2731
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2732
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2733
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2734
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2735
0
        GIR_EraseFromParent, /*InsnID*/0,
2736
        // GIR_Coverage, 786,
2737
0
        GIR_Done,
2738
      // Label 159: @6742
2739
0
      GIM_Try, /*On fail goto*//*Label 160*/ GIMT_Encode4(6823), // Rule ID 793 //
2740
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2741
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2742
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2743
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
2744
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2745
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2746
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2747
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
2748
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2749
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2750
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2751
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2752
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2753
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32),
2754
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2755
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2756
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2757
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2758
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2759
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2760
0
        GIR_EraseFromParent, /*InsnID*/0,
2761
        // GIR_Coverage, 793,
2762
0
        GIR_Done,
2763
      // Label 160: @6823
2764
0
      GIM_Try, /*On fail goto*//*Label 161*/ GIMT_Encode4(6904), // Rule ID 792 //
2765
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2766
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2767
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2768
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
2769
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2770
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2771
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2772
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
2773
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2774
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2775
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2776
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2777
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2778
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32),
2779
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2780
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2781
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2782
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2783
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2784
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2785
0
        GIR_EraseFromParent, /*InsnID*/0,
2786
        // GIR_Coverage, 792,
2787
0
        GIR_Done,
2788
      // Label 161: @6904
2789
0
      GIM_Try, /*On fail goto*//*Label 162*/ GIMT_Encode4(6984), // Rule ID 5661 //
2790
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2791
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2792
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2793
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2794
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2795
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2796
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2797
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2798
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2799
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2800
        // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2801
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i32),
2802
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2803
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2804
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2805
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2806
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2807
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2808
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2809
0
        GIR_EraseFromParent, /*InsnID*/0,
2810
        // GIR_Coverage, 5661,
2811
0
        GIR_Done,
2812
      // Label 162: @6984
2813
0
      GIM_Try, /*On fail goto*//*Label 163*/ GIMT_Encode4(7051), // Rule ID 5635 //
2814
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2815
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2816
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2817
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
2818
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2819
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2820
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2821
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2822
        // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn)  =>  (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2823
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32),
2824
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2825
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2826
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2827
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2828
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2829
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2830
0
        GIR_EraseFromParent, /*InsnID*/0,
2831
        // GIR_Coverage, 5635,
2832
0
        GIR_Done,
2833
      // Label 163: @7051
2834
0
      GIM_Try, /*On fail goto*//*Label 164*/ GIMT_Encode4(7118), // Rule ID 5630 //
2835
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2836
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2837
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2838
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
2839
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2840
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2841
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2842
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2843
        // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn)  =>  (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2844
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDWsv4i32),
2845
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2846
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2847
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2848
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2849
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2850
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2851
0
        GIR_EraseFromParent, /*InsnID*/0,
2852
        // GIR_Coverage, 5630,
2853
0
        GIR_Done,
2854
      // Label 164: @7118
2855
0
      GIM_Try, /*On fail goto*//*Label 165*/ GIMT_Encode4(7185), // Rule ID 5634 //
2856
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2857
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2858
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2859
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
2860
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2861
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2862
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2863
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2864
        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn)  =>  (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2865
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32),
2866
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2867
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2868
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2869
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2870
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2871
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2872
0
        GIR_EraseFromParent, /*InsnID*/0,
2873
        // GIR_Coverage, 5634,
2874
0
        GIR_Done,
2875
      // Label 165: @7185
2876
0
      GIM_Try, /*On fail goto*//*Label 166*/ GIMT_Encode4(7265), // Rule ID 909 //
2877
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2878
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2879
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2880
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2881
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2882
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2883
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2884
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2885
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2886
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2887
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2888
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i32),
2889
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2890
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2891
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2892
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2893
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2894
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2895
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2896
0
        GIR_EraseFromParent, /*InsnID*/0,
2897
        // GIR_Coverage, 909,
2898
0
        GIR_Done,
2899
      // Label 166: @7265
2900
0
      GIM_Try, /*On fail goto*//*Label 167*/ GIMT_Encode4(7332), // Rule ID 806 //
2901
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2902
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2903
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2904
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2905
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
2906
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2907
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2908
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2909
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2910
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32),
2911
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2912
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2913
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2914
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2915
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2916
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2917
0
        GIR_EraseFromParent, /*InsnID*/0,
2918
        // GIR_Coverage, 806,
2919
0
        GIR_Done,
2920
      // Label 167: @7332
2921
0
      GIM_Try, /*On fail goto*//*Label 168*/ GIMT_Encode4(7399), // Rule ID 801 //
2922
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2923
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2924
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2925
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2926
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
2927
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2928
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2929
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2930
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2931
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDWsv4i32),
2932
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2933
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2934
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2935
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2936
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2937
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2938
0
        GIR_EraseFromParent, /*InsnID*/0,
2939
        // GIR_Coverage, 801,
2940
0
        GIR_Done,
2941
      // Label 168: @7399
2942
0
      GIM_Try, /*On fail goto*//*Label 169*/ GIMT_Encode4(7466), // Rule ID 805 //
2943
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2944
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2945
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2946
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2947
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
2948
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2949
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2950
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2951
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2952
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32),
2953
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2954
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2955
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2956
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2957
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2958
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2959
0
        GIR_EraseFromParent, /*InsnID*/0,
2960
        // GIR_Coverage, 805,
2961
0
        GIR_Done,
2962
      // Label 169: @7466
2963
0
      GIM_Try, /*On fail goto*//*Label 170*/ GIMT_Encode4(7519), // Rule ID 778 //
2964
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2965
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2966
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2967
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
2968
        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VADDv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2969
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDv4i32),
2970
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
2971
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2972
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2973
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2974
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2975
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2976
0
        GIR_EraseFromParent, /*InsnID*/0,
2977
        // GIR_Coverage, 778,
2978
0
        GIR_Done,
2979
      // Label 170: @7519
2980
0
      GIM_Try, /*On fail goto*//*Label 171*/ GIMT_Encode4(7591), // Rule ID 3602 //
2981
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
2982
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2983
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2984
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2985
        // (add:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
2986
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
2987
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
2988
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
2989
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi32),
2990
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
2991
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
2992
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
2993
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2994
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2995
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2996
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
2997
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2998
0
        GIR_EraseFromParent, /*InsnID*/0,
2999
        // GIR_Coverage, 3602,
3000
0
        GIR_Done,
3001
      // Label 171: @7591
3002
0
      GIM_Reject,
3003
    // Label 148: @7592
3004
0
    GIM_Reject,
3005
    // Label 81: @7593
3006
0
    GIM_Try, /*On fail goto*//*Label 172*/ GIMT_Encode4(8142),
3007
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
3008
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
3009
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3010
0
      GIM_Try, /*On fail goto*//*Label 173*/ GIMT_Encode4(7694), // Rule ID 5726 //
3011
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3012
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3013
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3014
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3015
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
3016
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3017
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3018
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3019
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3020
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3021
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3022
        // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 3062:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1)  =>  (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3023
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i8),
3024
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3025
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3026
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3027
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3028
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3029
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3030
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3031
0
        GIR_EraseFromParent, /*InsnID*/0,
3032
        // GIR_Coverage, 5726,
3033
0
        GIR_Done,
3034
      // Label 173: @7694
3035
0
      GIM_Try, /*On fail goto*//*Label 174*/ GIMT_Encode4(7777), // Rule ID 5732 //
3036
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3037
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3038
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3039
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3040
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
3041
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3042
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3043
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3044
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3045
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3046
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3047
        // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 3063:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1)  =>  (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3048
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i8),
3049
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3050
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3051
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3052
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3053
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3054
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3055
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3056
0
        GIR_EraseFromParent, /*InsnID*/0,
3057
        // GIR_Coverage, 5732,
3058
0
        GIR_Done,
3059
      // Label 174: @7777
3060
0
      GIM_Try, /*On fail goto*//*Label 175*/ GIMT_Encode4(7860), // Rule ID 1198 //
3061
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3062
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3063
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3064
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3065
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3066
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
3067
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3068
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3069
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3070
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3071
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3072
        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (intrinsic_wo_chain:{ *:[v8i8] } 3062:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3073
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i8),
3074
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3075
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3076
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3077
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3078
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3079
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3080
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3081
0
        GIR_EraseFromParent, /*InsnID*/0,
3082
        // GIR_Coverage, 1198,
3083
0
        GIR_Done,
3084
      // Label 175: @7860
3085
0
      GIM_Try, /*On fail goto*//*Label 176*/ GIMT_Encode4(7943), // Rule ID 1204 //
3086
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3087
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3088
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3089
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3090
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3091
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
3092
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3093
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3094
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3095
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3096
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3097
        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (intrinsic_wo_chain:{ *:[v8i8] } 3063:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3098
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i8),
3099
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3100
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3101
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3102
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3103
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3104
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3105
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3106
0
        GIR_EraseFromParent, /*InsnID*/0,
3107
        // GIR_Coverage, 1204,
3108
0
        GIR_Done,
3109
      // Label 176: @7943
3110
0
      GIM_Try, /*On fail goto*//*Label 177*/ GIMT_Encode4(8018), // Rule ID 5656 //
3111
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3112
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3113
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3114
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3115
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3116
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3117
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3118
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3119
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3120
        // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1)  =>  (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3121
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i8),
3122
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3123
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3124
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3125
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3126
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3127
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3128
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3129
0
        GIR_EraseFromParent, /*InsnID*/0,
3130
        // GIR_Coverage, 5656,
3131
0
        GIR_Done,
3132
      // Label 177: @8018
3133
0
      GIM_Try, /*On fail goto*//*Label 178*/ GIMT_Encode4(8093), // Rule ID 904 //
3134
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3135
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3136
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3137
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3138
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3139
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3140
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3141
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3142
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3143
        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3144
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i8),
3145
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3146
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3147
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3148
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3149
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3150
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3151
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3152
0
        GIR_EraseFromParent, /*InsnID*/0,
3153
        // GIR_Coverage, 904,
3154
0
        GIR_Done,
3155
      // Label 178: @8093
3156
0
      GIM_Try, /*On fail goto*//*Label 179*/ GIMT_Encode4(8141), // Rule ID 773 //
3157
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3158
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3159
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3160
        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VADDv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3161
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDv8i8),
3162
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3163
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3164
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3165
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3166
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3167
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3168
0
        GIR_EraseFromParent, /*InsnID*/0,
3169
        // GIR_Coverage, 773,
3170
0
        GIR_Done,
3171
      // Label 179: @8141
3172
0
      GIM_Reject,
3173
    // Label 172: @8142
3174
0
    GIM_Reject,
3175
    // Label 82: @8143
3176
0
    GIM_Try, /*On fail goto*//*Label 180*/ GIMT_Encode4(10009),
3177
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3178
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
3179
0
      GIM_Try, /*On fail goto*//*Label 181*/ GIMT_Encode4(8258), // Rule ID 5738 //
3180
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3181
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3182
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3183
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3184
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3185
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3186
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3187
0
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3188
0
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
3189
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3190
0
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
3191
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3192
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3193
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3194
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3195
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3196
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 3062:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1)  =>  (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3197
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABALsv8i16),
3198
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3199
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3200
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
3201
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
3202
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3203
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3204
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3205
0
        GIR_EraseFromParent, /*InsnID*/0,
3206
        // GIR_Coverage, 5738,
3207
0
        GIR_Done,
3208
      // Label 181: @8258
3209
0
      GIM_Try, /*On fail goto*//*Label 182*/ GIMT_Encode4(8360), // Rule ID 5741 //
3210
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3211
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3212
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3213
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3214
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3215
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3216
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3217
0
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3218
0
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
3219
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3220
0
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
3221
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3222
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3223
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3224
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3225
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3226
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 3063:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1)  =>  (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3227
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABALuv8i16),
3228
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3229
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3230
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
3231
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
3232
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3233
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3234
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3235
0
        GIR_EraseFromParent, /*InsnID*/0,
3236
        // GIR_Coverage, 5741,
3237
0
        GIR_Done,
3238
      // Label 182: @8360
3239
0
      GIM_Try, /*On fail goto*//*Label 183*/ GIMT_Encode4(8462), // Rule ID 1210 //
3240
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3241
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3242
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3243
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3244
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3245
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3246
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3247
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3248
0
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3249
0
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
3250
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3251
0
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
3252
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3253
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3254
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3255
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3256
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 3062:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)))  =>  (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3257
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABALsv8i16),
3258
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3259
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3260
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
3261
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
3262
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3263
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3264
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3265
0
        GIR_EraseFromParent, /*InsnID*/0,
3266
        // GIR_Coverage, 1210,
3267
0
        GIR_Done,
3268
      // Label 183: @8462
3269
0
      GIM_Try, /*On fail goto*//*Label 184*/ GIMT_Encode4(8564), // Rule ID 1213 //
3270
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3271
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3272
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3273
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3274
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3275
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3276
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3277
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3278
0
        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3279
0
        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
3280
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3281
0
        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
3282
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3283
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3284
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3285
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3286
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 3063:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)))  =>  (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3287
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABALuv8i16),
3288
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3289
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3290
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
3291
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
3292
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3293
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3294
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3295
0
        GIR_EraseFromParent, /*InsnID*/0,
3296
        // GIR_Coverage, 1213,
3297
0
        GIR_Done,
3298
      // Label 184: @8564
3299
0
      GIM_Try, /*On fail goto*//*Label 185*/ GIMT_Encode4(8652), // Rule ID 5730 //
3300
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3301
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3302
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3303
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3304
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3305
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
3306
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3307
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3308
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3309
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3310
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3311
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3312
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 3062:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1)  =>  (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3313
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i16),
3314
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3315
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3316
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3317
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3318
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3319
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3320
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3321
0
        GIR_EraseFromParent, /*InsnID*/0,
3322
        // GIR_Coverage, 5730,
3323
0
        GIR_Done,
3324
      // Label 185: @8652
3325
0
      GIM_Try, /*On fail goto*//*Label 186*/ GIMT_Encode4(8740), // Rule ID 5736 //
3326
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3327
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3328
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3329
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3330
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3331
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
3332
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3333
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3334
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3335
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3336
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3337
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3338
        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 3063:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1)  =>  (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3339
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i16),
3340
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3341
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3342
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3343
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3344
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3345
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3346
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3347
0
        GIR_EraseFromParent, /*InsnID*/0,
3348
        // GIR_Coverage, 5736,
3349
0
        GIR_Done,
3350
      // Label 186: @8740
3351
0
      GIM_Try, /*On fail goto*//*Label 187*/ GIMT_Encode4(8828), // Rule ID 1202 //
3352
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3353
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3354
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3355
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3356
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3357
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3358
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
3359
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3360
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3361
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3362
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3363
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3364
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (intrinsic_wo_chain:{ *:[v8i16] } 3062:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3365
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i16),
3366
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3367
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3368
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3369
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3370
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3371
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3372
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3373
0
        GIR_EraseFromParent, /*InsnID*/0,
3374
        // GIR_Coverage, 1202,
3375
0
        GIR_Done,
3376
      // Label 187: @8828
3377
0
      GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(8916), // Rule ID 1208 //
3378
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3379
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3380
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3381
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3382
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3383
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3384
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
3385
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3386
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3387
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3388
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3389
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3390
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (intrinsic_wo_chain:{ *:[v8i16] } 3063:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3391
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i16),
3392
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3393
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3394
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3395
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3396
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3397
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3398
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3399
0
        GIR_EraseFromParent, /*InsnID*/0,
3400
        // GIR_Coverage, 1208,
3401
0
        GIR_Done,
3402
      // Label 188: @8916
3403
0
      GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(8997), // Rule ID 791 //
3404
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3405
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3406
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3407
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3408
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3409
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3410
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3411
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3412
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3413
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3414
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3415
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3416
        // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3417
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16),
3418
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3419
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3420
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3421
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3422
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3423
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3424
0
        GIR_EraseFromParent, /*InsnID*/0,
3425
        // GIR_Coverage, 791,
3426
0
        GIR_Done,
3427
      // Label 189: @8997
3428
0
      GIM_Try, /*On fail goto*//*Label 190*/ GIMT_Encode4(9078), // Rule ID 790 //
3429
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3430
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3431
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3432
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3433
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3434
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3435
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3436
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
3437
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3438
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3439
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3440
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3441
        // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3442
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16),
3443
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3444
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3445
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3446
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3447
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3448
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3449
0
        GIR_EraseFromParent, /*InsnID*/0,
3450
        // GIR_Coverage, 790,
3451
0
        GIR_Done,
3452
      // Label 190: @9078
3453
0
      GIM_Try, /*On fail goto*//*Label 191*/ GIMT_Encode4(9159), // Rule ID 785 //
3454
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3455
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3456
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3457
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
3458
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3459
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3460
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3461
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
3462
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3463
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3464
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3465
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3466
        // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3467
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDLsv8i16),
3468
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3469
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3470
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3471
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3472
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3473
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3474
0
        GIR_EraseFromParent, /*InsnID*/0,
3475
        // GIR_Coverage, 785,
3476
0
        GIR_Done,
3477
      // Label 191: @9159
3478
0
      GIM_Try, /*On fail goto*//*Label 192*/ GIMT_Encode4(9240), // Rule ID 789 //
3479
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3480
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3481
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3482
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3483
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3484
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3485
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3486
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3487
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3488
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3489
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3490
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3491
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3492
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16),
3493
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3494
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3495
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3496
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3497
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3498
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3499
0
        GIR_EraseFromParent, /*InsnID*/0,
3500
        // GIR_Coverage, 789,
3501
0
        GIR_Done,
3502
      // Label 192: @9240
3503
0
      GIM_Try, /*On fail goto*//*Label 193*/ GIMT_Encode4(9321), // Rule ID 788 //
3504
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3505
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3506
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3507
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3508
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3509
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3510
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3511
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
3512
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3513
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3514
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3515
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3516
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3517
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16),
3518
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3519
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3520
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3521
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3522
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3523
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3524
0
        GIR_EraseFromParent, /*InsnID*/0,
3525
        // GIR_Coverage, 788,
3526
0
        GIR_Done,
3527
      // Label 193: @9321
3528
0
      GIM_Try, /*On fail goto*//*Label 194*/ GIMT_Encode4(9401), // Rule ID 5660 //
3529
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3530
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3531
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3532
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3533
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3534
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3535
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3536
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3537
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3538
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3539
        // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1)  =>  (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3540
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i16),
3541
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3542
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3543
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3544
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3545
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3546
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3547
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3548
0
        GIR_EraseFromParent, /*InsnID*/0,
3549
        // GIR_Coverage, 5660,
3550
0
        GIR_Done,
3551
      // Label 194: @9401
3552
0
      GIM_Try, /*On fail goto*//*Label 195*/ GIMT_Encode4(9468), // Rule ID 5633 //
3553
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3554
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3555
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3556
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3557
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3558
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3559
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3560
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3561
        // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn)  =>  (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3562
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16),
3563
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3564
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
3565
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3566
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3567
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3568
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3569
0
        GIR_EraseFromParent, /*InsnID*/0,
3570
        // GIR_Coverage, 5633,
3571
0
        GIR_Done,
3572
      // Label 195: @9468
3573
0
      GIM_Try, /*On fail goto*//*Label 196*/ GIMT_Encode4(9535), // Rule ID 5629 //
3574
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3575
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3576
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3577
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
3578
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3579
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3580
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3581
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3582
        // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn)  =>  (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3583
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDWsv8i16),
3584
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3585
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
3586
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3587
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3588
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3589
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3590
0
        GIR_EraseFromParent, /*InsnID*/0,
3591
        // GIR_Coverage, 5629,
3592
0
        GIR_Done,
3593
      // Label 196: @9535
3594
0
      GIM_Try, /*On fail goto*//*Label 197*/ GIMT_Encode4(9602), // Rule ID 5632 //
3595
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3596
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3597
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3598
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3599
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3600
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3601
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3602
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3603
        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn)  =>  (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3604
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16),
3605
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3606
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
3607
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3608
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3609
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3610
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3611
0
        GIR_EraseFromParent, /*InsnID*/0,
3612
        // GIR_Coverage, 5632,
3613
0
        GIR_Done,
3614
      // Label 197: @9602
3615
0
      GIM_Try, /*On fail goto*//*Label 198*/ GIMT_Encode4(9682), // Rule ID 908 //
3616
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3617
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3618
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3619
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3620
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3621
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3622
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3623
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3624
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3625
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3626
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3627
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i16),
3628
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3629
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3630
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3631
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3632
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3633
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3634
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3635
0
        GIR_EraseFromParent, /*InsnID*/0,
3636
        // GIR_Coverage, 908,
3637
0
        GIR_Done,
3638
      // Label 198: @9682
3639
0
      GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(9749), // Rule ID 804 //
3640
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3641
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3642
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3643
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3644
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3645
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3646
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3647
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3648
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3649
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16),
3650
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3651
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3652
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3653
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3654
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3655
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3656
0
        GIR_EraseFromParent, /*InsnID*/0,
3657
        // GIR_Coverage, 804,
3658
0
        GIR_Done,
3659
      // Label 199: @9749
3660
0
      GIM_Try, /*On fail goto*//*Label 200*/ GIMT_Encode4(9816), // Rule ID 800 //
3661
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3662
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3663
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3664
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3665
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
3666
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3667
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3668
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3669
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3670
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDWsv8i16),
3671
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3672
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3673
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3674
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3675
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3676
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3677
0
        GIR_EraseFromParent, /*InsnID*/0,
3678
        // GIR_Coverage, 800,
3679
0
        GIR_Done,
3680
      // Label 200: @9816
3681
0
      GIM_Try, /*On fail goto*//*Label 201*/ GIMT_Encode4(9883), // Rule ID 803 //
3682
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3683
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3684
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3685
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3686
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3687
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3688
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3689
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3690
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3691
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16),
3692
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3693
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3694
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3695
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3696
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3697
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3698
0
        GIR_EraseFromParent, /*InsnID*/0,
3699
        // GIR_Coverage, 803,
3700
0
        GIR_Done,
3701
      // Label 201: @9883
3702
0
      GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(9936), // Rule ID 777 //
3703
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3704
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3705
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3706
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3707
        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VADDv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3708
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDv8i16),
3709
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3710
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3711
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3712
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3713
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3714
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3715
0
        GIR_EraseFromParent, /*InsnID*/0,
3716
        // GIR_Coverage, 777,
3717
0
        GIR_Done,
3718
      // Label 202: @9936
3719
0
      GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(10008), // Rule ID 3598 //
3720
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
3721
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3722
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3723
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3724
        // (add:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
3725
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3726
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
3727
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
3728
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi16),
3729
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
3730
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
3731
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
3732
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
3733
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3734
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3735
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3736
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3737
0
        GIR_EraseFromParent, /*InsnID*/0,
3738
        // GIR_Coverage, 3598,
3739
0
        GIR_Done,
3740
      // Label 203: @10008
3741
0
      GIM_Reject,
3742
    // Label 180: @10009
3743
0
    GIM_Reject,
3744
    // Label 83: @10010
3745
0
    GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(10661),
3746
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3747
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
3748
0
      GIM_Try, /*On fail goto*//*Label 205*/ GIMT_Encode4(10111), // Rule ID 5729 //
3749
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3750
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3751
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3752
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3753
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3754
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
3755
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3756
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3757
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3758
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3759
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3760
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3761
        // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 3062:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1)  =>  (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3762
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAsv16i8),
3763
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3764
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3765
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3766
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3767
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3768
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3769
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3770
0
        GIR_EraseFromParent, /*InsnID*/0,
3771
        // GIR_Coverage, 5729,
3772
0
        GIR_Done,
3773
      // Label 205: @10111
3774
0
      GIM_Try, /*On fail goto*//*Label 206*/ GIMT_Encode4(10199), // Rule ID 5735 //
3775
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3776
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3777
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3778
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3779
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3780
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
3781
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3782
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3783
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3784
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3785
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3786
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3787
        // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 3063:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1)  =>  (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3788
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAuv16i8),
3789
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3790
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3791
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3792
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3793
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3794
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3795
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3796
0
        GIR_EraseFromParent, /*InsnID*/0,
3797
        // GIR_Coverage, 5735,
3798
0
        GIR_Done,
3799
      // Label 206: @10199
3800
0
      GIM_Try, /*On fail goto*//*Label 207*/ GIMT_Encode4(10287), // Rule ID 1201 //
3801
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3802
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3803
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3804
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3805
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3806
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3807
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
3808
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3809
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3810
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3811
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3812
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3813
        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (intrinsic_wo_chain:{ *:[v16i8] } 3062:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3814
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAsv16i8),
3815
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3816
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3817
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3818
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3819
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3820
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3821
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3822
0
        GIR_EraseFromParent, /*InsnID*/0,
3823
        // GIR_Coverage, 1201,
3824
0
        GIR_Done,
3825
      // Label 207: @10287
3826
0
      GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(10375), // Rule ID 1207 //
3827
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3828
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3829
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3830
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3831
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3832
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3833
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
3834
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3835
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3836
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3837
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3838
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3839
        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (intrinsic_wo_chain:{ *:[v16i8] } 3063:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3840
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABAuv16i8),
3841
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3842
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3843
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3844
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3845
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3846
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3847
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3848
0
        GIR_EraseFromParent, /*InsnID*/0,
3849
        // GIR_Coverage, 1207,
3850
0
        GIR_Done,
3851
      // Label 208: @10375
3852
0
      GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(10455), // Rule ID 5659 //
3853
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3854
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3855
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3856
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3857
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3858
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3859
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3860
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3861
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3862
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3863
        // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1)  =>  (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3864
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMLAv16i8),
3865
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3866
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3867
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3868
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3869
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3870
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3871
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3872
0
        GIR_EraseFromParent, /*InsnID*/0,
3873
        // GIR_Coverage, 5659,
3874
0
        GIR_Done,
3875
      // Label 209: @10455
3876
0
      GIM_Try, /*On fail goto*//*Label 210*/ GIMT_Encode4(10535), // Rule ID 907 //
3877
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3878
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3879
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3880
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3881
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3882
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3883
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3884
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3885
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3886
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3887
        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3888
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMLAv16i8),
3889
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3890
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3891
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3892
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3893
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3894
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3895
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3896
0
        GIR_EraseFromParent, /*InsnID*/0,
3897
        // GIR_Coverage, 907,
3898
0
        GIR_Done,
3899
      // Label 210: @10535
3900
0
      GIM_Try, /*On fail goto*//*Label 211*/ GIMT_Encode4(10588), // Rule ID 776 //
3901
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3902
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3903
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3904
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3905
        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VADDv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3906
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDv16i8),
3907
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
3908
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3909
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3910
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3911
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3912
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3913
0
        GIR_EraseFromParent, /*InsnID*/0,
3914
        // GIR_Coverage, 776,
3915
0
        GIR_Done,
3916
      // Label 211: @10588
3917
0
      GIM_Try, /*On fail goto*//*Label 212*/ GIMT_Encode4(10660), // Rule ID 3594 //
3918
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
3919
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3920
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3921
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3922
        // (add:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
3923
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3924
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
3925
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
3926
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi8),
3927
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
3928
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
3929
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
3930
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
3931
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3932
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3933
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3934
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3935
0
        GIR_EraseFromParent, /*InsnID*/0,
3936
        // GIR_Coverage, 3594,
3937
0
        GIR_Done,
3938
      // Label 212: @10660
3939
0
      GIM_Reject,
3940
    // Label 204: @10661
3941
0
    GIM_Reject,
3942
    // Label 84: @10662
3943
0
    GIM_Reject,
3944
    // Label 1: @10663
3945
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 222*/ GIMT_Encode4(14338),
3946
0
    /*GILLT_s32*//*Label 213*/ GIMT_Encode4(10734),
3947
0
    /*GILLT_s64*//*Label 214*/ GIMT_Encode4(11356), GIMT_Encode4(0),
3948
0
    /*GILLT_v2s32*//*Label 215*/ GIMT_Encode4(11418),
3949
0
    /*GILLT_v2s64*//*Label 216*/ GIMT_Encode4(11556), GIMT_Encode4(0),
3950
0
    /*GILLT_v4s16*//*Label 217*/ GIMT_Encode4(12190),
3951
0
    /*GILLT_v4s32*//*Label 218*/ GIMT_Encode4(12328), GIMT_Encode4(0), GIMT_Encode4(0),
3952
0
    /*GILLT_v8s8*//*Label 219*/ GIMT_Encode4(13154),
3953
0
    /*GILLT_v8s16*//*Label 220*/ GIMT_Encode4(13292), GIMT_Encode4(0), GIMT_Encode4(0),
3954
0
    /*GILLT_v16s8*//*Label 221*/ GIMT_Encode4(14118),
3955
    // Label 213: @10734
3956
0
    GIM_Try, /*On fail goto*//*Label 223*/ GIMT_Encode4(11355),
3957
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3958
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3959
0
      GIM_Try, /*On fail goto*//*Label 224*/ GIMT_Encode4(10814), // Rule ID 96 //
3960
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
3961
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
3962
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3963
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
3964
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
3965
        // MIs[1] Operand 1
3966
        // No operand predicates
3967
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
3968
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3969
        // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, GPR:{ *:[i32] }:$Rn)  =>  (RSBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3970
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::RSBri),
3971
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
3972
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
3973
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3974
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3975
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3976
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3977
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3978
0
        GIR_EraseFromParent, /*InsnID*/0,
3979
        // GIR_Coverage, 96,
3980
0
        GIR_Done,
3981
      // Label 224: @10814
3982
0
      GIM_Try, /*On fail goto*//*Label 225*/ GIMT_Encode4(10881), // Rule ID 435 //
3983
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
3984
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
3985
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3986
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
3987
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
3988
        // MIs[1] Operand 1
3989
        // No operand predicates
3990
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
3991
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3992
        // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, rGPR:{ *:[i32] }:$Rn)  =>  (t2RSBri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3993
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2RSBri),
3994
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
3995
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
3996
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3997
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3998
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3999
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4000
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4001
0
        GIR_EraseFromParent, /*InsnID*/0,
4002
        // GIR_Coverage, 435,
4003
0
        GIR_Done,
4004
      // Label 225: @10881
4005
0
      GIM_Try, /*On fail goto*//*Label 226*/ GIMT_Encode4(10948), // Rule ID 76 //
4006
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
4007
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4008
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4009
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4010
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4011
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
4012
        // MIs[1] Operand 1
4013
        // No operand predicates
4014
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4015
        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (SUBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4016
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SUBri),
4017
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
4018
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4019
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4020
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4021
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4022
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4023
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4024
0
        GIR_EraseFromParent, /*InsnID*/0,
4025
        // GIR_Coverage, 76,
4026
0
        GIR_Done,
4027
      // Label 226: @10948
4028
0
      GIM_Try, /*On fail goto*//*Label 227*/ GIMT_Encode4(11015), // Rule ID 419 //
4029
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
4030
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4031
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
4032
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4033
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4034
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
4035
        // MIs[1] Operand 1
4036
        // No operand predicates
4037
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4038
        // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2SUBri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4039
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SUBri),
4040
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
4041
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4042
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4043
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4044
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4045
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4046
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4047
0
        GIR_EraseFromParent, /*InsnID*/0,
4048
        // GIR_Coverage, 419,
4049
0
        GIR_Done,
4050
      // Label 227: @11015
4051
0
      GIM_Try, /*On fail goto*//*Label 228*/ GIMT_Encode4(11076), // Rule ID 420 //
4052
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
4053
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4054
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4055
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4056
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4057
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_4095),
4058
        // MIs[1] Operand 1
4059
        // No operand predicates
4060
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4061
        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm)  =>  (t2SUBri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4062
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SUBri12),
4063
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
4064
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4065
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4066
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4067
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4068
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4069
0
        GIR_EraseFromParent, /*InsnID*/0,
4070
        // GIR_Coverage, 420,
4071
0
        GIR_Done,
4072
      // Label 228: @11076
4073
0
      GIM_Try, /*On fail goto*//*Label 229*/ GIMT_Encode4(11156), // Rule ID 173 //
4074
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM_UseMulOps),
4075
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4076
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4077
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4078
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4079
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4080
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4081
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4082
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4083
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4084
        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm))  =>  (MLS:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
4085
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MLS),
4086
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
4087
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4088
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4089
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
4090
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4091
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4092
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4093
0
        GIR_EraseFromParent, /*InsnID*/0,
4094
        // GIR_Coverage, 173,
4095
0
        GIR_Done,
4096
      // Label 229: @11156
4097
0
      GIM_Try, /*On fail goto*//*Label 230*/ GIMT_Encode4(11236), // Rule ID 512 //
4098
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_UseMulOps),
4099
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4100
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4101
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4102
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4103
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4104
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4105
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4106
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4107
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4108
        // (sub:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm))  =>  (t2MLS:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
4109
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2MLS),
4110
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
4111
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4112
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4113
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
4114
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4115
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4116
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4117
0
        GIR_EraseFromParent, /*InsnID*/0,
4118
        // GIR_Coverage, 512,
4119
0
        GIR_Done,
4120
      // Label 230: @11236
4121
0
      GIM_Try, /*On fail goto*//*Label 231*/ GIMT_Encode4(11295), // Rule ID 77 //
4122
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
4123
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4124
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4125
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4126
        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (SUBrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4127
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SUBrr),
4128
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
4129
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4130
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4131
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4132
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4133
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4134
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4135
0
        GIR_EraseFromParent, /*InsnID*/0,
4136
        // GIR_Coverage, 77,
4137
0
        GIR_Done,
4138
      // Label 231: @11295
4139
0
      GIM_Try, /*On fail goto*//*Label 232*/ GIMT_Encode4(11354), // Rule ID 421 //
4140
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
4141
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
4142
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
4143
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4144
        // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SUBrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4145
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SUBrr),
4146
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
4147
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4148
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4149
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4150
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4151
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4152
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4153
0
        GIR_EraseFromParent, /*InsnID*/0,
4154
        // GIR_Coverage, 421,
4155
0
        GIR_Done,
4156
      // Label 232: @11354
4157
0
      GIM_Reject,
4158
    // Label 223: @11355
4159
0
    GIM_Reject,
4160
    // Label 214: @11356
4161
0
    GIM_Try, /*On fail goto*//*Label 233*/ GIMT_Encode4(11417), // Rule ID 983 //
4162
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4163
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
4164
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4165
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4166
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4167
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4168
      // (sub:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VSUBv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
4169
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBv1i64),
4170
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4171
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4172
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4173
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4174
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4175
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4176
0
      GIR_EraseFromParent, /*InsnID*/0,
4177
      // GIR_Coverage, 983,
4178
0
      GIR_Done,
4179
    // Label 233: @11417
4180
0
    GIM_Reject,
4181
    // Label 215: @11418
4182
0
    GIM_Try, /*On fail goto*//*Label 234*/ GIMT_Encode4(11555),
4183
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
4184
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
4185
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4186
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4187
0
      GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(11511), // Rule ID 934 //
4188
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4189
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4190
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4191
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4192
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
4193
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4194
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4195
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4196
        // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VMLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4197
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMLSv2i32),
4198
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4199
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4200
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4201
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4202
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4203
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4204
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4205
0
        GIR_EraseFromParent, /*InsnID*/0,
4206
        // GIR_Coverage, 934,
4207
0
        GIR_Done,
4208
      // Label 235: @11511
4209
0
      GIM_Try, /*On fail goto*//*Label 236*/ GIMT_Encode4(11554), // Rule ID 979 //
4210
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4211
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4212
        // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VSUBv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4213
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBv2i32),
4214
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4215
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4216
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4217
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4218
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4219
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4220
0
        GIR_EraseFromParent, /*InsnID*/0,
4221
        // GIR_Coverage, 979,
4222
0
        GIR_Done,
4223
      // Label 236: @11554
4224
0
      GIM_Reject,
4225
    // Label 234: @11555
4226
0
    GIM_Reject,
4227
    // Label 216: @11556
4228
0
    GIM_Try, /*On fail goto*//*Label 237*/ GIMT_Encode4(12189),
4229
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4230
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4231
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4232
0
      GIM_Try, /*On fail goto*//*Label 238*/ GIMT_Encode4(11650), // Rule ID 1003 //
4233
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4234
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4235
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4236
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4237
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4238
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4239
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4240
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4241
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4242
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4243
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4244
        // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4245
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64),
4246
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4247
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4248
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4249
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4250
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4251
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4252
0
        GIR_EraseFromParent, /*InsnID*/0,
4253
        // GIR_Coverage, 1003,
4254
0
        GIR_Done,
4255
      // Label 238: @11650
4256
0
      GIM_Try, /*On fail goto*//*Label 239*/ GIMT_Encode4(11726), // Rule ID 1002 //
4257
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4258
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4259
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4260
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4261
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4262
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4263
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
4264
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4265
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4266
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4267
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4268
        // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4269
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64),
4270
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4271
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4272
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4273
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4274
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4275
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4276
0
        GIR_EraseFromParent, /*InsnID*/0,
4277
        // GIR_Coverage, 1002,
4278
0
        GIR_Done,
4279
      // Label 239: @11726
4280
0
      GIM_Try, /*On fail goto*//*Label 240*/ GIMT_Encode4(11802), // Rule ID 991 //
4281
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4282
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4283
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4284
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4285
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4286
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4287
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
4288
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4289
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4290
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4291
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4292
        // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4293
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv2i64),
4294
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4295
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4296
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4297
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4298
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4299
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4300
0
        GIR_EraseFromParent, /*InsnID*/0,
4301
        // GIR_Coverage, 991,
4302
0
        GIR_Done,
4303
      // Label 240: @11802
4304
0
      GIM_Try, /*On fail goto*//*Label 241*/ GIMT_Encode4(11878), // Rule ID 1001 //
4305
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4306
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4307
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4308
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4309
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4310
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4311
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4312
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4313
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4314
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4315
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4316
        // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4317
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64),
4318
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4319
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4320
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4321
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4322
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4323
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4324
0
        GIR_EraseFromParent, /*InsnID*/0,
4325
        // GIR_Coverage, 1001,
4326
0
        GIR_Done,
4327
      // Label 241: @11878
4328
0
      GIM_Try, /*On fail goto*//*Label 242*/ GIMT_Encode4(11954), // Rule ID 1000 //
4329
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4330
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4331
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4332
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4333
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4334
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4335
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
4336
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4337
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4338
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4339
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4340
        // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4341
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64),
4342
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4343
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4344
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4345
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4346
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4347
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4348
0
        GIR_EraseFromParent, /*InsnID*/0,
4349
        // GIR_Coverage, 1000,
4350
0
        GIR_Done,
4351
      // Label 242: @11954
4352
0
      GIM_Try, /*On fail goto*//*Label 243*/ GIMT_Encode4(12016), // Rule ID 1012 //
4353
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4354
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4355
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4356
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4357
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4358
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4359
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4360
        // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4361
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv2i64),
4362
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4363
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4364
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4365
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4366
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4367
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4368
0
        GIR_EraseFromParent, /*InsnID*/0,
4369
        // GIR_Coverage, 1012,
4370
0
        GIR_Done,
4371
      // Label 243: @12016
4372
0
      GIM_Try, /*On fail goto*//*Label 244*/ GIMT_Encode4(12078), // Rule ID 1006 //
4373
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4374
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4375
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4376
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4377
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4378
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4379
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4380
        // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4381
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv2i64),
4382
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4383
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4384
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4385
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4386
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4387
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4388
0
        GIR_EraseFromParent, /*InsnID*/0,
4389
        // GIR_Coverage, 1006,
4390
0
        GIR_Done,
4391
      // Label 244: @12078
4392
0
      GIM_Try, /*On fail goto*//*Label 245*/ GIMT_Encode4(12140), // Rule ID 1011 //
4393
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4394
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4395
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4396
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4397
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4398
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4399
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4400
        // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4401
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv2i64),
4402
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4403
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4404
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4405
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4406
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4407
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4408
0
        GIR_EraseFromParent, /*InsnID*/0,
4409
        // GIR_Coverage, 1011,
4410
0
        GIR_Done,
4411
      // Label 245: @12140
4412
0
      GIM_Try, /*On fail goto*//*Label 246*/ GIMT_Encode4(12188), // Rule ID 984 //
4413
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4414
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4415
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4416
        // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VSUBv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
4417
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBv2i64),
4418
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4419
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4420
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4421
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4422
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4423
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4424
0
        GIR_EraseFromParent, /*InsnID*/0,
4425
        // GIR_Coverage, 984,
4426
0
        GIR_Done,
4427
      // Label 246: @12188
4428
0
      GIM_Reject,
4429
    // Label 237: @12189
4430
0
    GIM_Reject,
4431
    // Label 217: @12190
4432
0
    GIM_Try, /*On fail goto*//*Label 247*/ GIMT_Encode4(12327),
4433
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
4434
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
4435
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4436
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4437
0
      GIM_Try, /*On fail goto*//*Label 248*/ GIMT_Encode4(12283), // Rule ID 933 //
4438
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4439
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4440
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4441
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4442
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
4443
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4444
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4445
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4446
        // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VMLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4447
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMLSv4i16),
4448
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4449
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4450
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4451
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4452
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4453
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4454
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4455
0
        GIR_EraseFromParent, /*InsnID*/0,
4456
        // GIR_Coverage, 933,
4457
0
        GIR_Done,
4458
      // Label 248: @12283
4459
0
      GIM_Try, /*On fail goto*//*Label 249*/ GIMT_Encode4(12326), // Rule ID 978 //
4460
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4461
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4462
        // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VSUBv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4463
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBv4i16),
4464
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4465
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4466
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4467
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4468
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4469
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4470
0
        GIR_EraseFromParent, /*InsnID*/0,
4471
        // GIR_Coverage, 978,
4472
0
        GIR_Done,
4473
      // Label 249: @12326
4474
0
      GIM_Reject,
4475
    // Label 247: @12327
4476
0
    GIM_Reject,
4477
    // Label 218: @12328
4478
0
    GIM_Try, /*On fail goto*//*Label 250*/ GIMT_Encode4(13153),
4479
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4480
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4481
0
      GIM_Try, /*On fail goto*//*Label 251*/ GIMT_Encode4(12422), // Rule ID 999 //
4482
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4483
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4484
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4485
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4486
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4487
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4488
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4489
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4490
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4491
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4492
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4493
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4494
        // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4495
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32),
4496
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4497
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4498
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4499
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4500
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4501
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4502
0
        GIR_EraseFromParent, /*InsnID*/0,
4503
        // GIR_Coverage, 999,
4504
0
        GIR_Done,
4505
      // Label 251: @12422
4506
0
      GIM_Try, /*On fail goto*//*Label 252*/ GIMT_Encode4(12503), // Rule ID 998 //
4507
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4508
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4509
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4510
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4511
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4512
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4513
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4514
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
4515
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4516
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4517
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4518
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4519
        // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4520
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32),
4521
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4522
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4523
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4524
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4525
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4526
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4527
0
        GIR_EraseFromParent, /*InsnID*/0,
4528
        // GIR_Coverage, 998,
4529
0
        GIR_Done,
4530
      // Label 252: @12503
4531
0
      GIM_Try, /*On fail goto*//*Label 253*/ GIMT_Encode4(12584), // Rule ID 990 //
4532
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4533
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4534
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4535
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4536
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4537
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4538
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4539
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
4540
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4541
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4542
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4543
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4544
        // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4545
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv4i32),
4546
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4547
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4548
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4549
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4550
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4551
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4552
0
        GIR_EraseFromParent, /*InsnID*/0,
4553
        // GIR_Coverage, 990,
4554
0
        GIR_Done,
4555
      // Label 253: @12584
4556
0
      GIM_Try, /*On fail goto*//*Label 254*/ GIMT_Encode4(12665), // Rule ID 997 //
4557
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4558
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4559
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4560
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4561
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4562
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4563
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4564
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4565
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4566
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4567
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4568
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4569
        // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4570
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32),
4571
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4572
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4573
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4574
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4575
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4576
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4577
0
        GIR_EraseFromParent, /*InsnID*/0,
4578
        // GIR_Coverage, 997,
4579
0
        GIR_Done,
4580
      // Label 254: @12665
4581
0
      GIM_Try, /*On fail goto*//*Label 255*/ GIMT_Encode4(12746), // Rule ID 996 //
4582
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4583
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4584
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4585
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4586
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4587
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4588
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4589
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
4590
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4591
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4592
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4593
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4594
        // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4595
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32),
4596
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4597
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4598
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4599
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4600
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4601
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4602
0
        GIR_EraseFromParent, /*InsnID*/0,
4603
        // GIR_Coverage, 996,
4604
0
        GIR_Done,
4605
      // Label 255: @12746
4606
0
      GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(12826), // Rule ID 937 //
4607
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4608
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4609
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4610
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4611
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4612
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4613
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4614
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4615
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4616
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4617
        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VMLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4618
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMLSv4i32),
4619
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4620
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4621
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4622
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4623
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4624
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4625
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4626
0
        GIR_EraseFromParent, /*InsnID*/0,
4627
        // GIR_Coverage, 937,
4628
0
        GIR_Done,
4629
      // Label 256: @12826
4630
0
      GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(12893), // Rule ID 1010 //
4631
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4632
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4633
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4634
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4635
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4636
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4637
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4638
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4639
        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4640
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv4i32),
4641
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4642
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4643
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4644
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4645
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4646
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4647
0
        GIR_EraseFromParent, /*InsnID*/0,
4648
        // GIR_Coverage, 1010,
4649
0
        GIR_Done,
4650
      // Label 257: @12893
4651
0
      GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(12960), // Rule ID 1005 //
4652
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4653
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4654
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4655
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4656
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4657
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4658
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4659
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4660
        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4661
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv4i32),
4662
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4663
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4664
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4665
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4666
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4667
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4668
0
        GIR_EraseFromParent, /*InsnID*/0,
4669
        // GIR_Coverage, 1005,
4670
0
        GIR_Done,
4671
      // Label 258: @12960
4672
0
      GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(13027), // Rule ID 1009 //
4673
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4674
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4675
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4676
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4677
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4678
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4679
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4680
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4681
        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4682
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv4i32),
4683
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4684
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4685
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4686
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4687
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4688
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4689
0
        GIR_EraseFromParent, /*InsnID*/0,
4690
        // GIR_Coverage, 1009,
4691
0
        GIR_Done,
4692
      // Label 259: @13027
4693
0
      GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(13080), // Rule ID 982 //
4694
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4695
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4696
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4697
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4698
        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VSUBv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4699
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBv4i32),
4700
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4701
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4702
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4703
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4704
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4705
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4706
0
        GIR_EraseFromParent, /*InsnID*/0,
4707
        // GIR_Coverage, 982,
4708
0
        GIR_Done,
4709
      // Label 260: @13080
4710
0
      GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(13152), // Rule ID 3614 //
4711
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
4712
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
4713
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
4714
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
4715
        // (sub:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VSUBi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
4716
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4717
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
4718
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
4719
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi32),
4720
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
4721
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
4722
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
4723
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
4724
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4725
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4726
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4727
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4728
0
        GIR_EraseFromParent, /*InsnID*/0,
4729
        // GIR_Coverage, 3614,
4730
0
        GIR_Done,
4731
      // Label 261: @13152
4732
0
      GIM_Reject,
4733
    // Label 250: @13153
4734
0
    GIM_Reject,
4735
    // Label 219: @13154
4736
0
    GIM_Try, /*On fail goto*//*Label 262*/ GIMT_Encode4(13291),
4737
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
4738
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
4739
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4740
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4741
0
      GIM_Try, /*On fail goto*//*Label 263*/ GIMT_Encode4(13247), // Rule ID 932 //
4742
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4743
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4744
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4745
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4746
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4747
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4748
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4749
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4750
        // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VMLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4751
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMLSv8i8),
4752
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4753
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4754
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4755
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4756
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4757
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4758
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4759
0
        GIR_EraseFromParent, /*InsnID*/0,
4760
        // GIR_Coverage, 932,
4761
0
        GIR_Done,
4762
      // Label 263: @13247
4763
0
      GIM_Try, /*On fail goto*//*Label 264*/ GIMT_Encode4(13290), // Rule ID 977 //
4764
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4765
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4766
        // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VSUBv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4767
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBv8i8),
4768
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4769
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4770
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4771
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4772
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4773
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4774
0
        GIR_EraseFromParent, /*InsnID*/0,
4775
        // GIR_Coverage, 977,
4776
0
        GIR_Done,
4777
      // Label 264: @13290
4778
0
      GIM_Reject,
4779
    // Label 262: @13291
4780
0
    GIM_Reject,
4781
    // Label 220: @13292
4782
0
    GIM_Try, /*On fail goto*//*Label 265*/ GIMT_Encode4(14117),
4783
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4784
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4785
0
      GIM_Try, /*On fail goto*//*Label 266*/ GIMT_Encode4(13386), // Rule ID 995 //
4786
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4787
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4788
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4789
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4790
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4791
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4792
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4793
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4794
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4795
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4796
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4797
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4798
        // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4799
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16),
4800
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4801
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4802
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4803
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4804
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4805
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4806
0
        GIR_EraseFromParent, /*InsnID*/0,
4807
        // GIR_Coverage, 995,
4808
0
        GIR_Done,
4809
      // Label 266: @13386
4810
0
      GIM_Try, /*On fail goto*//*Label 267*/ GIMT_Encode4(13467), // Rule ID 994 //
4811
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4812
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4813
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4814
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4815
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4816
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4817
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4818
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
4819
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4820
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4821
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4822
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4823
        // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4824
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16),
4825
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4826
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4827
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4828
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4829
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4830
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4831
0
        GIR_EraseFromParent, /*InsnID*/0,
4832
        // GIR_Coverage, 994,
4833
0
        GIR_Done,
4834
      // Label 267: @13467
4835
0
      GIM_Try, /*On fail goto*//*Label 268*/ GIMT_Encode4(13548), // Rule ID 989 //
4836
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4837
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4838
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4839
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4840
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4841
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4842
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4843
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
4844
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4845
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4846
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4847
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4848
        // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4849
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv8i16),
4850
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4851
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4852
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4853
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4854
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4855
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4856
0
        GIR_EraseFromParent, /*InsnID*/0,
4857
        // GIR_Coverage, 989,
4858
0
        GIR_Done,
4859
      // Label 268: @13548
4860
0
      GIM_Try, /*On fail goto*//*Label 269*/ GIMT_Encode4(13629), // Rule ID 993 //
4861
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4862
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4863
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4864
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4865
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4866
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4867
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4868
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4869
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4870
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4871
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4872
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4873
        // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4874
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16),
4875
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4876
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4877
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4878
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4879
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4880
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4881
0
        GIR_EraseFromParent, /*InsnID*/0,
4882
        // GIR_Coverage, 993,
4883
0
        GIR_Done,
4884
      // Label 269: @13629
4885
0
      GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(13710), // Rule ID 992 //
4886
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4887
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4888
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4889
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4890
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4891
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4892
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4893
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
4894
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4895
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4896
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4897
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4898
        // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4899
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16),
4900
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4901
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4902
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4903
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4904
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4905
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4906
0
        GIR_EraseFromParent, /*InsnID*/0,
4907
        // GIR_Coverage, 992,
4908
0
        GIR_Done,
4909
      // Label 270: @13710
4910
0
      GIM_Try, /*On fail goto*//*Label 271*/ GIMT_Encode4(13790), // Rule ID 936 //
4911
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4912
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4913
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4914
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4915
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4916
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
4917
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
4918
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4919
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4920
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4921
        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VMLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
4922
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMLSv8i16),
4923
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4924
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4925
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4926
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4927
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4928
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4929
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4930
0
        GIR_EraseFromParent, /*InsnID*/0,
4931
        // GIR_Coverage, 936,
4932
0
        GIR_Done,
4933
      // Label 271: @13790
4934
0
      GIM_Try, /*On fail goto*//*Label 272*/ GIMT_Encode4(13857), // Rule ID 1008 //
4935
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4936
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4937
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4938
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4939
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4940
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4941
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4942
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4943
        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4944
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv8i16),
4945
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4946
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4947
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4948
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4949
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4950
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4951
0
        GIR_EraseFromParent, /*InsnID*/0,
4952
        // GIR_Coverage, 1008,
4953
0
        GIR_Done,
4954
      // Label 272: @13857
4955
0
      GIM_Try, /*On fail goto*//*Label 273*/ GIMT_Encode4(13924), // Rule ID 1004 //
4956
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4957
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4958
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4959
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4960
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4961
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4962
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4963
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4964
        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4965
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv8i16),
4966
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4967
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4968
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4969
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4970
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4971
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4972
0
        GIR_EraseFromParent, /*InsnID*/0,
4973
        // GIR_Coverage, 1004,
4974
0
        GIR_Done,
4975
      // Label 273: @13924
4976
0
      GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(13991), // Rule ID 1007 //
4977
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4978
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4979
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4980
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4981
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4982
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4983
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4984
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4985
        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4986
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv8i16),
4987
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
4988
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4989
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4990
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4991
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4992
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4993
0
        GIR_EraseFromParent, /*InsnID*/0,
4994
        // GIR_Coverage, 1007,
4995
0
        GIR_Done,
4996
      // Label 274: @13991
4997
0
      GIM_Try, /*On fail goto*//*Label 275*/ GIMT_Encode4(14044), // Rule ID 981 //
4998
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4999
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5000
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5001
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5002
        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VSUBv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
5003
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBv8i16),
5004
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
5005
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5006
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5007
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5008
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5009
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5010
0
        GIR_EraseFromParent, /*InsnID*/0,
5011
        // GIR_Coverage, 981,
5012
0
        GIR_Done,
5013
      // Label 275: @14044
5014
0
      GIM_Try, /*On fail goto*//*Label 276*/ GIMT_Encode4(14116), // Rule ID 3610 //
5015
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
5016
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5017
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5018
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5019
        // (sub:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VSUBi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
5020
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5021
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
5022
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
5023
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi16),
5024
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
5025
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
5026
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
5027
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
5028
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5029
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5030
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5031
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5032
0
        GIR_EraseFromParent, /*InsnID*/0,
5033
        // GIR_Coverage, 3610,
5034
0
        GIR_Done,
5035
      // Label 276: @14116
5036
0
      GIM_Reject,
5037
    // Label 265: @14117
5038
0
    GIM_Reject,
5039
    // Label 221: @14118
5040
0
    GIM_Try, /*On fail goto*//*Label 277*/ GIMT_Encode4(14337),
5041
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
5042
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5043
0
      GIM_Try, /*On fail goto*//*Label 278*/ GIMT_Encode4(14211), // Rule ID 935 //
5044
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5045
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5046
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5047
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5048
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5049
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
5050
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
5051
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5052
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5053
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
5054
        // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VMLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
5055
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMLSv16i8),
5056
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
5057
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
5058
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5059
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5060
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5061
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5062
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5063
0
        GIR_EraseFromParent, /*InsnID*/0,
5064
        // GIR_Coverage, 935,
5065
0
        GIR_Done,
5066
      // Label 278: @14211
5067
0
      GIM_Try, /*On fail goto*//*Label 279*/ GIMT_Encode4(14264), // Rule ID 980 //
5068
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5069
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5070
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5071
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5072
        // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VSUBv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
5073
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBv16i8),
5074
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
5075
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5076
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5077
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5078
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5079
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5080
0
        GIR_EraseFromParent, /*InsnID*/0,
5081
        // GIR_Coverage, 980,
5082
0
        GIR_Done,
5083
      // Label 279: @14264
5084
0
      GIM_Try, /*On fail goto*//*Label 280*/ GIMT_Encode4(14336), // Rule ID 3606 //
5085
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
5086
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5087
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5088
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5089
        // (sub:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VSUBi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
5090
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5091
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
5092
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
5093
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi8),
5094
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
5095
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
5096
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
5097
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
5098
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5099
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5100
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5101
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5102
0
        GIR_EraseFromParent, /*InsnID*/0,
5103
        // GIR_Coverage, 3606,
5104
0
        GIR_Done,
5105
      // Label 280: @14336
5106
0
      GIM_Reject,
5107
    // Label 277: @14337
5108
0
    GIM_Reject,
5109
    // Label 222: @14338
5110
0
    GIM_Reject,
5111
    // Label 2: @14339
5112
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 288*/ GIMT_Encode4(15396),
5113
0
    /*GILLT_s32*//*Label 281*/ GIMT_Encode4(14410), GIMT_Encode4(0), GIMT_Encode4(0),
5114
0
    /*GILLT_v2s32*//*Label 282*/ GIMT_Encode4(14790), GIMT_Encode4(0), GIMT_Encode4(0),
5115
0
    /*GILLT_v4s16*//*Label 283*/ GIMT_Encode4(14852),
5116
0
    /*GILLT_v4s32*//*Label 284*/ GIMT_Encode4(14914), GIMT_Encode4(0), GIMT_Encode4(0),
5117
0
    /*GILLT_v8s8*//*Label 285*/ GIMT_Encode4(15054),
5118
0
    /*GILLT_v8s16*//*Label 286*/ GIMT_Encode4(15116), GIMT_Encode4(0), GIMT_Encode4(0),
5119
0
    /*GILLT_v16s8*//*Label 287*/ GIMT_Encode4(15256),
5120
    // Label 281: @14410
5121
0
    GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(14789),
5122
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
5123
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5124
0
      GIM_Try, /*On fail goto*//*Label 290*/ GIMT_Encode4(14520), // Rule ID 186 //
5125
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
5126
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5127
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5128
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
5129
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5130
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5131
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5132
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
5133
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5134
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
5135
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5136
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5137
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5138
0
        GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
5139
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
5140
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
5141
        // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))  =>  (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5142
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMULTT),
5143
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5144
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5145
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5146
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5147
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5148
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5149
0
        GIR_EraseFromParent, /*InsnID*/0,
5150
        // GIR_Coverage, 186,
5151
0
        GIR_Done,
5152
      // Label 290: @14520
5153
0
      GIM_Try, /*On fail goto*//*Label 291*/ GIMT_Encode4(14617), // Rule ID 523 //
5154
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
5155
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5156
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5157
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
5158
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5159
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5160
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5161
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
5162
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5163
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
5164
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5165
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5166
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5167
0
        GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
5168
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
5169
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
5170
        // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))  =>  (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5171
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMULTT),
5172
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5173
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5174
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5175
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5176
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5177
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5178
0
        GIR_EraseFromParent, /*InsnID*/0,
5179
        // GIR_Coverage, 523,
5180
0
        GIR_Done,
5181
      // Label 291: @14617
5182
0
      GIM_Try, /*On fail goto*//*Label 292*/ GIMT_Encode4(14676), // Rule ID 169 //
5183
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
5184
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
5185
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
5186
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
5187
        // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (MUL:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
5188
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MUL),
5189
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5190
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5191
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
5192
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5193
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5194
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5195
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5196
0
        GIR_EraseFromParent, /*InsnID*/0,
5197
        // GIR_Coverage, 169,
5198
0
        GIR_Done,
5199
      // Label 292: @14676
5200
0
      GIM_Try, /*On fail goto*//*Label 293*/ GIMT_Encode4(14735), // Rule ID 170 //
5201
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV6_UseMulOps),
5202
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
5203
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
5204
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
5205
        // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (MULv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
5206
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MULv5),
5207
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5208
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5209
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
5210
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5211
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5212
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5213
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5214
0
        GIR_EraseFromParent, /*InsnID*/0,
5215
        // GIR_Coverage, 170,
5216
0
        GIR_Done,
5217
      // Label 293: @14735
5218
0
      GIM_Try, /*On fail goto*//*Label 294*/ GIMT_Encode4(14788), // Rule ID 510 //
5219
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
5220
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5221
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5222
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5223
        // (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2MUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5224
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2MUL),
5225
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5226
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5227
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
5228
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5229
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5230
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5231
0
        GIR_EraseFromParent, /*InsnID*/0,
5232
        // GIR_Coverage, 510,
5233
0
        GIR_Done,
5234
      // Label 294: @14788
5235
0
      GIM_Reject,
5236
    // Label 289: @14789
5237
0
    GIM_Reject,
5238
    // Label 282: @14790
5239
0
    GIM_Try, /*On fail goto*//*Label 295*/ GIMT_Encode4(14851), // Rule ID 854 //
5240
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5241
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
5242
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
5243
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5244
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5245
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5246
      // (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VMULv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5247
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMULv2i32),
5248
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
5249
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5250
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5251
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5252
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5253
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5254
0
      GIR_EraseFromParent, /*InsnID*/0,
5255
      // GIR_Coverage, 854,
5256
0
      GIR_Done,
5257
    // Label 295: @14851
5258
0
    GIM_Reject,
5259
    // Label 283: @14852
5260
0
    GIM_Try, /*On fail goto*//*Label 296*/ GIMT_Encode4(14913), // Rule ID 853 //
5261
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5262
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
5263
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
5264
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5265
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5266
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5267
      // (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VMULv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5268
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMULv4i16),
5269
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
5270
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5271
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5272
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5273
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5274
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5275
0
      GIR_EraseFromParent, /*InsnID*/0,
5276
      // GIR_Coverage, 853,
5277
0
      GIR_Done,
5278
    // Label 296: @14913
5279
0
    GIM_Reject,
5280
    // Label 284: @14914
5281
0
    GIM_Try, /*On fail goto*//*Label 297*/ GIMT_Encode4(15053),
5282
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
5283
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5284
0
      GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(14980), // Rule ID 857 //
5285
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5286
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5287
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5288
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5289
        // (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VMULv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
5290
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMULv4i32),
5291
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
5292
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5293
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5294
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5295
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5296
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5297
0
        GIR_EraseFromParent, /*InsnID*/0,
5298
        // GIR_Coverage, 857,
5299
0
        GIR_Done,
5300
      // Label 298: @14980
5301
0
      GIM_Try, /*On fail goto*//*Label 299*/ GIMT_Encode4(15052), // Rule ID 3572 //
5302
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
5303
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5304
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5305
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5306
        // (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VMULi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
5307
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5308
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
5309
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
5310
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi32),
5311
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
5312
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
5313
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
5314
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
5315
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5316
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5317
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5318
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5319
0
        GIR_EraseFromParent, /*InsnID*/0,
5320
        // GIR_Coverage, 3572,
5321
0
        GIR_Done,
5322
      // Label 299: @15052
5323
0
      GIM_Reject,
5324
    // Label 297: @15053
5325
0
    GIM_Reject,
5326
    // Label 285: @15054
5327
0
    GIM_Try, /*On fail goto*//*Label 300*/ GIMT_Encode4(15115), // Rule ID 852 //
5328
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5329
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
5330
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
5331
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5332
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5333
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5334
      // (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMULv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5335
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMULv8i8),
5336
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
5337
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5338
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5339
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5340
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5341
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5342
0
      GIR_EraseFromParent, /*InsnID*/0,
5343
      // GIR_Coverage, 852,
5344
0
      GIR_Done,
5345
    // Label 300: @15115
5346
0
    GIM_Reject,
5347
    // Label 286: @15116
5348
0
    GIM_Try, /*On fail goto*//*Label 301*/ GIMT_Encode4(15255),
5349
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
5350
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5351
0
      GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(15182), // Rule ID 856 //
5352
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5353
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5354
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5355
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5356
        // (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VMULv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
5357
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMULv8i16),
5358
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
5359
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5360
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5361
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5362
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5363
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5364
0
        GIR_EraseFromParent, /*InsnID*/0,
5365
        // GIR_Coverage, 856,
5366
0
        GIR_Done,
5367
      // Label 302: @15182
5368
0
      GIM_Try, /*On fail goto*//*Label 303*/ GIMT_Encode4(15254), // Rule ID 3568 //
5369
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
5370
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5371
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5372
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5373
        // (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VMULi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
5374
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5375
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
5376
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
5377
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi16),
5378
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
5379
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
5380
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
5381
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
5382
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5383
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5384
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5385
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5386
0
        GIR_EraseFromParent, /*InsnID*/0,
5387
        // GIR_Coverage, 3568,
5388
0
        GIR_Done,
5389
      // Label 303: @15254
5390
0
      GIM_Reject,
5391
    // Label 301: @15255
5392
0
    GIM_Reject,
5393
    // Label 287: @15256
5394
0
    GIM_Try, /*On fail goto*//*Label 304*/ GIMT_Encode4(15395),
5395
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
5396
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5397
0
      GIM_Try, /*On fail goto*//*Label 305*/ GIMT_Encode4(15322), // Rule ID 855 //
5398
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5399
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5400
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5401
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5402
        // (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VMULv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
5403
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMULv16i8),
5404
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
5405
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5406
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5407
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5408
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5409
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5410
0
        GIR_EraseFromParent, /*InsnID*/0,
5411
        // GIR_Coverage, 855,
5412
0
        GIR_Done,
5413
      // Label 305: @15322
5414
0
      GIM_Try, /*On fail goto*//*Label 306*/ GIMT_Encode4(15394), // Rule ID 3564 //
5415
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
5416
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5417
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5418
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5419
        // (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VMULi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
5420
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5421
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
5422
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
5423
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi8),
5424
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
5425
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
5426
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
5427
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
5428
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5429
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5430
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5431
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5432
0
        GIR_EraseFromParent, /*InsnID*/0,
5433
        // GIR_Coverage, 3564,
5434
0
        GIR_Done,
5435
      // Label 306: @15394
5436
0
      GIM_Reject,
5437
    // Label 304: @15395
5438
0
    GIM_Reject,
5439
    // Label 288: @15396
5440
0
    GIM_Reject,
5441
    // Label 3: @15397
5442
0
    GIM_Try, /*On fail goto*//*Label 307*/ GIMT_Encode4(15521),
5443
0
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5444
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
5445
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5446
0
      GIM_Try, /*On fail goto*//*Label 308*/ GIMT_Encode4(15467), // Rule ID 195 //
5447
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInARM_IsARM),
5448
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5449
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5450
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5451
        // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (SDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5452
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SDIV),
5453
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5454
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5455
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
5456
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5457
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5458
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5459
0
        GIR_EraseFromParent, /*InsnID*/0,
5460
        // GIR_Coverage, 195,
5461
0
        GIR_Done,
5462
      // Label 308: @15467
5463
0
      GIM_Try, /*On fail goto*//*Label 309*/ GIMT_Encode4(15520), // Rule ID 540 //
5464
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb),
5465
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5466
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5467
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5468
        // (sdiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5469
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SDIV),
5470
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5471
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5472
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
5473
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5474
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5475
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5476
0
        GIR_EraseFromParent, /*InsnID*/0,
5477
        // GIR_Coverage, 540,
5478
0
        GIR_Done,
5479
      // Label 309: @15520
5480
0
      GIM_Reject,
5481
    // Label 307: @15521
5482
0
    GIM_Reject,
5483
    // Label 4: @15522
5484
0
    GIM_Try, /*On fail goto*//*Label 310*/ GIMT_Encode4(15646),
5485
0
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5486
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
5487
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5488
0
      GIM_Try, /*On fail goto*//*Label 311*/ GIMT_Encode4(15592), // Rule ID 196 //
5489
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInARM_IsARM),
5490
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5491
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5492
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5493
        // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (UDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5494
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UDIV),
5495
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5496
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5497
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
5498
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5499
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5500
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5501
0
        GIR_EraseFromParent, /*InsnID*/0,
5502
        // GIR_Coverage, 196,
5503
0
        GIR_Done,
5504
      // Label 311: @15592
5505
0
      GIM_Try, /*On fail goto*//*Label 312*/ GIMT_Encode4(15645), // Rule ID 541 //
5506
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb),
5507
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5508
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5509
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5510
        // (udiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5511
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UDIV),
5512
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5513
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5514
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
5515
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5516
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5517
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5518
0
        GIR_EraseFromParent, /*InsnID*/0,
5519
        // GIR_Coverage, 541,
5520
0
        GIR_Done,
5521
      // Label 312: @15645
5522
0
      GIM_Reject,
5523
    // Label 310: @15646
5524
0
    GIM_Reject,
5525
    // Label 5: @15647
5526
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 326*/ GIMT_Encode4(19057),
5527
0
    /*GILLT_s32*//*Label 313*/ GIMT_Encode4(15718),
5528
0
    /*GILLT_s64*//*Label 314*/ GIMT_Encode4(17761),
5529
0
    /*GILLT_v2s1*//*Label 315*/ GIMT_Encode4(17823),
5530
0
    /*GILLT_v2s32*//*Label 316*/ GIMT_Encode4(17945),
5531
0
    /*GILLT_v2s64*//*Label 317*/ GIMT_Encode4(18007),
5532
0
    /*GILLT_v4s1*//*Label 318*/ GIMT_Encode4(18147),
5533
0
    /*GILLT_v4s16*//*Label 319*/ GIMT_Encode4(18269),
5534
0
    /*GILLT_v4s32*//*Label 320*/ GIMT_Encode4(18331), GIMT_Encode4(0),
5535
0
    /*GILLT_v8s1*//*Label 321*/ GIMT_Encode4(18471),
5536
0
    /*GILLT_v8s8*//*Label 322*/ GIMT_Encode4(18593),
5537
0
    /*GILLT_v8s16*//*Label 323*/ GIMT_Encode4(18655), GIMT_Encode4(0),
5538
0
    /*GILLT_v16s1*//*Label 324*/ GIMT_Encode4(18795),
5539
0
    /*GILLT_v16s8*//*Label 325*/ GIMT_Encode4(18917),
5540
    // Label 313: @15718
5541
0
    GIM_Try, /*On fail goto*//*Label 327*/ GIMT_Encode4(17760),
5542
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
5543
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5544
0
      GIM_Try, /*On fail goto*//*Label 328*/ GIMT_Encode4(15811), // Rule ID 1879 //
5545
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
5546
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
5547
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5548
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
5549
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5550
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5551
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5552
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8,
5553
0
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935),
5554
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
5555
        // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] })  =>  (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
5556
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UXTB16),
5557
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5558
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
5559
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
5560
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5561
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5562
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5563
0
        GIR_EraseFromParent, /*InsnID*/0,
5564
        // GIR_Coverage, 1879,
5565
0
        GIR_Done,
5566
      // Label 328: @15811
5567
0
      GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(15891), // Rule ID 2125 //
5568
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
5569
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5570
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5571
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
5572
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5573
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5574
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5575
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8,
5576
0
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935),
5577
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
5578
        // (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] })  =>  (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
5579
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16),
5580
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5581
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
5582
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
5583
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5584
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5585
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5586
0
        GIR_EraseFromParent, /*InsnID*/0,
5587
        // GIR_Coverage, 2125,
5588
0
        GIR_Done,
5589
      // Label 329: @15891
5590
0
      GIM_Try, /*On fail goto*//*Label 330*/ GIMT_Encode4(15949), // Rule ID 2015 //
5591
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
5592
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
5593
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5594
0
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
5595
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 255:{ *:[i32] })  =>  (UXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
5596
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UXTB),
5597
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5598
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
5599
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
5600
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5601
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5602
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5603
0
        GIR_EraseFromParent, /*InsnID*/0,
5604
        // GIR_Coverage, 2015,
5605
0
        GIR_Done,
5606
      // Label 330: @15949
5607
0
      GIM_Try, /*On fail goto*//*Label 331*/ GIMT_Encode4(16007), // Rule ID 2016 //
5608
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
5609
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
5610
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5611
0
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
5612
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 65535:{ *:[i32] })  =>  (UXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
5613
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UXTH),
5614
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5615
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
5616
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
5617
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5618
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5619
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5620
0
        GIR_EraseFromParent, /*InsnID*/0,
5621
        // GIR_Coverage, 2016,
5622
0
        GIR_Done,
5623
      // Label 331: @16007
5624
0
      GIM_Try, /*On fail goto*//*Label 332*/ GIMT_Encode4(16065), // Rule ID 2017 //
5625
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
5626
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
5627
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5628
0
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935),
5629
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 16711935:{ *:[i32] })  =>  (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
5630
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UXTB16),
5631
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5632
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
5633
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
5634
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5635
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5636
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5637
0
        GIR_EraseFromParent, /*InsnID*/0,
5638
        // GIR_Coverage, 2017,
5639
0
        GIR_Done,
5640
      // Label 332: @16065
5641
0
      GIM_Try, /*On fail goto*//*Label 333*/ GIMT_Encode4(16123), // Rule ID 2243 //
5642
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
5643
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5644
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5645
0
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
5646
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })  =>  (t2UXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
5647
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UXTB),
5648
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5649
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
5650
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
5651
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5652
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5653
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5654
0
        GIR_EraseFromParent, /*InsnID*/0,
5655
        // GIR_Coverage, 2243,
5656
0
        GIR_Done,
5657
      // Label 333: @16123
5658
0
      GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(16181), // Rule ID 2244 //
5659
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
5660
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5661
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5662
0
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
5663
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })  =>  (t2UXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
5664
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UXTH),
5665
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5666
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
5667
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
5668
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5669
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5670
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5671
0
        GIR_EraseFromParent, /*InsnID*/0,
5672
        // GIR_Coverage, 2244,
5673
0
        GIR_Done,
5674
      // Label 334: @16181
5675
0
      GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(16239), // Rule ID 2245 //
5676
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
5677
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5678
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5679
0
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935),
5680
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16711935:{ *:[i32] })  =>  (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
5681
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16),
5682
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5683
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
5684
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
5685
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5686
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5687
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5688
0
        GIR_EraseFromParent, /*InsnID*/0,
5689
        // GIR_Coverage, 2245,
5690
0
        GIR_Done,
5691
      // Label 335: @16239
5692
0
      GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(16328), // Rule ID 5565 //
5693
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
5694
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5695
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5696
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
5697
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5698
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5699
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1),
5700
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5701
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5702
0
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
5703
        // MIs[2] Operand 1
5704
        // No operand predicates
5705
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5706
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
5707
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
5708
        // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm), GPR:{ *:[i32] }:$Rn)  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5709
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::BICri),
5710
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5711
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
5712
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5713
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5714
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5715
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5716
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5717
0
        GIR_EraseFromParent, /*InsnID*/0,
5718
        // GIR_Coverage, 5565,
5719
0
        GIR_Done,
5720
      // Label 336: @16328
5721
0
      GIM_Try, /*On fail goto*//*Label 337*/ GIMT_Encode4(16417), // Rule ID 5598 //
5722
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
5723
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5724
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5725
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
5726
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5727
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5728
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1),
5729
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5730
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5731
0
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
5732
        // MIs[2] Operand 1
5733
        // No operand predicates
5734
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5735
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
5736
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
5737
        // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn)  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5738
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2BICri),
5739
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5740
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
5741
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5742
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5743
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5744
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5745
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5746
0
        GIR_EraseFromParent, /*InsnID*/0,
5747
        // GIR_Coverage, 5598,
5748
0
        GIR_Done,
5749
      // Label 337: @16417
5750
0
      GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(16506), // Rule ID 5564 //
5751
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
5752
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5753
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5754
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
5755
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5756
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5757
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5758
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5759
0
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
5760
        // MIs[2] Operand 1
5761
        // No operand predicates
5762
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
5763
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5764
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
5765
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
5766
        // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5767
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::BICri),
5768
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5769
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
5770
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5771
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5772
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5773
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5774
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5775
0
        GIR_EraseFromParent, /*InsnID*/0,
5776
        // GIR_Coverage, 5564,
5777
0
        GIR_Done,
5778
      // Label 338: @16506
5779
0
      GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(16595), // Rule ID 5597 //
5780
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
5781
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5782
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5783
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
5784
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5785
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5786
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5787
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5788
0
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
5789
        // MIs[2] Operand 1
5790
        // No operand predicates
5791
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
5792
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5793
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
5794
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
5795
        // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5796
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2BICri),
5797
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5798
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
5799
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5800
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5801
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5802
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5803
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5804
0
        GIR_EraseFromParent, /*InsnID*/0,
5805
        // GIR_Coverage, 5597,
5806
0
        GIR_Done,
5807
      // Label 339: @16595
5808
0
      GIM_Try, /*On fail goto*//*Label 340*/ GIMT_Encode4(16684), // Rule ID 5563 //
5809
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
5810
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5811
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5812
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5813
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
5814
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5815
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5816
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1),
5817
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5818
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5819
0
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
5820
        // MIs[2] Operand 1
5821
        // No operand predicates
5822
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
5823
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
5824
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm))  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5825
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::BICri),
5826
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5827
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5828
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5829
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5830
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5831
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5832
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5833
0
        GIR_EraseFromParent, /*InsnID*/0,
5834
        // GIR_Coverage, 5563,
5835
0
        GIR_Done,
5836
      // Label 340: @16684
5837
0
      GIM_Try, /*On fail goto*//*Label 341*/ GIMT_Encode4(16773), // Rule ID 5596 //
5838
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
5839
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5840
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5841
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5842
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
5843
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5844
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5845
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1),
5846
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5847
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5848
0
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
5849
        // MIs[2] Operand 1
5850
        // No operand predicates
5851
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
5852
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
5853
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm))  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5854
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2BICri),
5855
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5856
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5857
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5858
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5859
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5860
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5861
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5862
0
        GIR_EraseFromParent, /*InsnID*/0,
5863
        // GIR_Coverage, 5596,
5864
0
        GIR_Done,
5865
      // Label 341: @16773
5866
0
      GIM_Try, /*On fail goto*//*Label 342*/ GIMT_Encode4(16862), // Rule ID 159 //
5867
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
5868
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5869
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5870
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5871
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
5872
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5873
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5874
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5875
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5876
0
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
5877
        // MIs[2] Operand 1
5878
        // No operand predicates
5879
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
5880
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
5881
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
5882
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }))  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5883
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::BICri),
5884
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5885
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5886
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5887
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5888
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5889
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5890
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5891
0
        GIR_EraseFromParent, /*InsnID*/0,
5892
        // GIR_Coverage, 159,
5893
0
        GIR_Done,
5894
      // Label 342: @16862
5895
0
      GIM_Try, /*On fail goto*//*Label 343*/ GIMT_Encode4(16951), // Rule ID 498 //
5896
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
5897
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5898
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5899
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5900
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
5901
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5902
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5903
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5904
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5905
0
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
5906
        // MIs[2] Operand 1
5907
        // No operand predicates
5908
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
5909
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
5910
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
5911
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }))  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5912
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2BICri),
5913
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5914
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5915
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5916
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5917
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5918
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5919
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5920
0
        GIR_EraseFromParent, /*InsnID*/0,
5921
        // GIR_Coverage, 498,
5922
0
        GIR_Done,
5923
      // Label 343: @16951
5924
0
      GIM_Try, /*On fail goto*//*Label 344*/ GIMT_Encode4(17032), // Rule ID 5566 //
5925
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
5926
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5927
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5928
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
5929
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5930
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5931
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5932
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
5933
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5934
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
5935
        // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5936
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::BICrr),
5937
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5938
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
5939
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
5940
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5941
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5942
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5943
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5944
0
        GIR_EraseFromParent, /*InsnID*/0,
5945
        // GIR_Coverage, 5566,
5946
0
        GIR_Done,
5947
      // Label 344: @17032
5948
0
      GIM_Try, /*On fail goto*//*Label 345*/ GIMT_Encode4(17113), // Rule ID 5599 //
5949
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
5950
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5951
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5952
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
5953
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5954
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5955
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5956
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
5957
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5958
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
5959
        // (and:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5960
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2BICrr),
5961
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5962
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
5963
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
5964
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5965
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5966
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5967
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5968
0
        GIR_EraseFromParent, /*InsnID*/0,
5969
        // GIR_Coverage, 5599,
5970
0
        GIR_Done,
5971
      // Label 345: @17113
5972
0
      GIM_Try, /*On fail goto*//*Label 346*/ GIMT_Encode4(17194), // Rule ID 160 //
5973
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
5974
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5975
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5976
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5977
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
5978
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5979
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5980
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5981
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
5982
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
5983
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }))  =>  (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5984
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::BICrr),
5985
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
5986
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5987
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
5988
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5989
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5990
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5991
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5992
0
        GIR_EraseFromParent, /*InsnID*/0,
5993
        // GIR_Coverage, 160,
5994
0
        GIR_Done,
5995
      // Label 346: @17194
5996
0
      GIM_Try, /*On fail goto*//*Label 347*/ GIMT_Encode4(17275), // Rule ID 499 //
5997
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
5998
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5999
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6000
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6001
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6002
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6003
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6004
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6005
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
6006
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
6007
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }))  =>  (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6008
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2BICrr),
6009
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
6010
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6011
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6012
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6013
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6014
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6015
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6016
0
        GIR_EraseFromParent, /*InsnID*/0,
6017
        // GIR_Coverage, 499,
6018
0
        GIR_Done,
6019
      // Label 347: @17275
6020
0
      GIM_Try, /*On fail goto*//*Label 348*/ GIMT_Encode4(17330), // Rule ID 352 //
6021
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
6022
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6023
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6024
0
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
6025
        // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })  =>  (tUXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
6026
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::tUXTB),
6027
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
6028
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
6029
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6030
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6031
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6032
0
        GIR_EraseFromParent, /*InsnID*/0,
6033
        // GIR_Coverage, 352,
6034
0
        GIR_Done,
6035
      // Label 348: @17330
6036
0
      GIM_Try, /*On fail goto*//*Label 349*/ GIMT_Encode4(17385), // Rule ID 353 //
6037
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
6038
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6039
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6040
0
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
6041
        // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })  =>  (tUXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
6042
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::tUXTH),
6043
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
6044
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
6045
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6046
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6047
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6048
0
        GIR_EraseFromParent, /*InsnID*/0,
6049
        // GIR_Coverage, 353,
6050
0
        GIR_Done,
6051
      // Label 349: @17385
6052
0
      GIM_Try, /*On fail goto*//*Label 350*/ GIMT_Encode4(17452), // Rule ID 147 //
6053
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
6054
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6055
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6056
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6057
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6058
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
6059
        // MIs[1] Operand 1
6060
        // No operand predicates
6061
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
6062
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (ANDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6063
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::ANDri),
6064
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
6065
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6066
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
6067
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6068
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6069
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6070
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6071
0
        GIR_EraseFromParent, /*InsnID*/0,
6072
        // GIR_Coverage, 147,
6073
0
        GIR_Done,
6074
      // Label 350: @17452
6075
0
      GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(17519), // Rule ID 489 //
6076
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
6077
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6078
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6079
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6080
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6081
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
6082
        // MIs[1] Operand 1
6083
        // No operand predicates
6084
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
6085
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2ANDri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6086
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2ANDri),
6087
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
6088
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6089
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
6090
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6091
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6092
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6093
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6094
0
        GIR_EraseFromParent, /*InsnID*/0,
6095
        // GIR_Coverage, 489,
6096
0
        GIR_Done,
6097
      // Label 351: @17519
6098
0
      GIM_Try, /*On fail goto*//*Label 352*/ GIMT_Encode4(17580), // Rule ID 163 //
6099
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM),
6100
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6101
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6102
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6103
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6104
        // MIs[1] Operand 1
6105
        // No operand predicates
6106
0
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_bf_inv_mask_imm),
6107
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
6108
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm)  =>  (BFC:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm)
6109
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::BFC),
6110
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
6111
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
6112
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
6113
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6114
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6115
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6116
0
        GIR_EraseFromParent, /*InsnID*/0,
6117
        // GIR_Coverage, 163,
6118
0
        GIR_Done,
6119
      // Label 352: @17580
6120
0
      GIM_Try, /*On fail goto*//*Label 353*/ GIMT_Encode4(17641), // Rule ID 501 //
6121
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
6122
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6123
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6124
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6125
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6126
        // MIs[1] Operand 1
6127
        // No operand predicates
6128
0
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_bf_inv_mask_imm),
6129
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
6130
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm)  =>  (t2BFC:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm)
6131
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2BFC),
6132
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
6133
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
6134
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
6135
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6136
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6137
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6138
0
        GIR_EraseFromParent, /*InsnID*/0,
6139
        // GIR_Coverage, 501,
6140
0
        GIR_Done,
6141
      // Label 353: @17641
6142
0
      GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(17700), // Rule ID 148 //
6143
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
6144
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6145
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6146
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6147
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (ANDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6148
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::ANDrr),
6149
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
6150
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6151
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
6152
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6153
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6154
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6155
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6156
0
        GIR_EraseFromParent, /*InsnID*/0,
6157
        // GIR_Coverage, 148,
6158
0
        GIR_Done,
6159
      // Label 354: @17700
6160
0
      GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(17759), // Rule ID 490 //
6161
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
6162
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6163
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6164
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6165
        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2ANDrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6166
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
6167
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
6168
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6169
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
6170
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6171
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6172
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6173
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6174
0
        GIR_EraseFromParent, /*InsnID*/0,
6175
        // GIR_Coverage, 490,
6176
0
        GIR_Done,
6177
      // Label 355: @17759
6178
0
      GIM_Reject,
6179
    // Label 327: @17760
6180
0
    GIM_Reject,
6181
    // Label 314: @17761
6182
0
    GIM_Try, /*On fail goto*//*Label 356*/ GIMT_Encode4(17822), // Rule ID 2532 //
6183
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6184
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
6185
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
6186
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6187
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6188
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6189
      // (and:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)  =>  (VANDd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)
6190
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VANDd),
6191
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
6192
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
6193
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
6194
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6195
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6196
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6197
0
      GIR_EraseFromParent, /*InsnID*/0,
6198
      // GIR_Coverage, 2532,
6199
0
      GIR_Done,
6200
    // Label 356: @17822
6201
0
    GIM_Reject,
6202
    // Label 315: @17823
6203
0
    GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(17944), // Rule ID 1850 //
6204
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
6205
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s1,
6206
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s1,
6207
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
6208
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
6209
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
6210
      // (and:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
6211
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6212
0
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
6213
0
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
6214
0
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
6215
0
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6216
0
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
6217
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
6218
0
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
6219
0
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6220
0
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
6221
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
6222
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
6223
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6224
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
6225
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
6226
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
6227
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6228
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6229
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6230
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
6231
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
6232
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6233
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
6234
0
      GIR_EraseFromParent, /*InsnID*/0,
6235
      // GIR_Coverage, 1850,
6236
0
      GIR_Done,
6237
    // Label 357: @17944
6238
0
    GIM_Reject,
6239
    // Label 316: @17945
6240
0
    GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(18006), // Rule ID 1150 //
6241
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6242
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
6243
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
6244
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6245
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6246
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6247
      // (and:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VANDd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
6248
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VANDd),
6249
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
6250
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
6251
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
6252
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6253
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6254
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6255
0
      GIR_EraseFromParent, /*InsnID*/0,
6256
      // GIR_Coverage, 1150,
6257
0
      GIR_Done,
6258
    // Label 358: @18006
6259
0
    GIM_Reject,
6260
    // Label 317: @18007
6261
0
    GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(18146),
6262
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
6263
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6264
0
      GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(18073), // Rule ID 2535 //
6265
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6266
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6267
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6268
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6269
        // (and:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)  =>  (VANDq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)
6270
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VANDq),
6271
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
6272
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
6273
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
6274
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6275
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6276
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6277
0
        GIR_EraseFromParent, /*InsnID*/0,
6278
        // GIR_Coverage, 2535,
6279
0
        GIR_Done,
6280
      // Label 360: @18073
6281
0
      GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(18145), // Rule ID 3476 //
6282
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
6283
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6284
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6285
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6286
        // (and:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)  =>  (MVE_VAND:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
6287
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6288
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6289
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
6290
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND),
6291
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
6292
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
6293
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
6294
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6295
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6296
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6297
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6298
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6299
0
        GIR_EraseFromParent, /*InsnID*/0,
6300
        // GIR_Coverage, 3476,
6301
0
        GIR_Done,
6302
      // Label 361: @18145
6303
0
      GIM_Reject,
6304
    // Label 359: @18146
6305
0
    GIM_Reject,
6306
    // Label 318: @18147
6307
0
    GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(18268), // Rule ID 1851 //
6308
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
6309
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1,
6310
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1,
6311
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
6312
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
6313
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
6314
      // (and:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
6315
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6316
0
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
6317
0
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
6318
0
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
6319
0
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6320
0
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
6321
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
6322
0
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
6323
0
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6324
0
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
6325
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
6326
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
6327
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6328
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
6329
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
6330
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
6331
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6332
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6333
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6334
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
6335
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
6336
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6337
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
6338
0
      GIR_EraseFromParent, /*InsnID*/0,
6339
      // GIR_Coverage, 1851,
6340
0
      GIR_Done,
6341
    // Label 362: @18268
6342
0
    GIM_Reject,
6343
    // Label 319: @18269
6344
0
    GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(18330), // Rule ID 2531 //
6345
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6346
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
6347
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
6348
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6349
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6350
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6351
      // (and:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)  =>  (VANDd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)
6352
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VANDd),
6353
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
6354
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
6355
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
6356
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6357
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6358
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6359
0
      GIR_EraseFromParent, /*InsnID*/0,
6360
      // GIR_Coverage, 2531,
6361
0
      GIR_Done,
6362
    // Label 363: @18330
6363
0
    GIM_Reject,
6364
    // Label 320: @18331
6365
0
    GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(18470),
6366
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
6367
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6368
0
      GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(18397), // Rule ID 1151 //
6369
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6370
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6371
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6372
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6373
        // (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VANDq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
6374
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VANDq),
6375
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
6376
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
6377
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
6378
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6379
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6380
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6381
0
        GIR_EraseFromParent, /*InsnID*/0,
6382
        // GIR_Coverage, 1151,
6383
0
        GIR_Done,
6384
      // Label 365: @18397
6385
0
      GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(18469), // Rule ID 3472 //
6386
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
6387
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6388
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6389
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6390
        // (and:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VAND:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
6391
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6392
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6393
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
6394
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND),
6395
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
6396
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
6397
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
6398
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6399
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6400
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6401
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6402
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6403
0
        GIR_EraseFromParent, /*InsnID*/0,
6404
        // GIR_Coverage, 3472,
6405
0
        GIR_Done,
6406
      // Label 366: @18469
6407
0
      GIM_Reject,
6408
    // Label 364: @18470
6409
0
    GIM_Reject,
6410
    // Label 321: @18471
6411
0
    GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(18592), // Rule ID 1852 //
6412
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
6413
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1,
6414
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1,
6415
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
6416
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
6417
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
6418
      // (and:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
6419
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6420
0
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
6421
0
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
6422
0
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
6423
0
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6424
0
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
6425
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
6426
0
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
6427
0
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6428
0
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
6429
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
6430
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
6431
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6432
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
6433
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
6434
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
6435
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6436
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6437
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6438
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
6439
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
6440
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6441
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
6442
0
      GIR_EraseFromParent, /*InsnID*/0,
6443
      // GIR_Coverage, 1852,
6444
0
      GIR_Done,
6445
    // Label 367: @18592
6446
0
    GIM_Reject,
6447
    // Label 322: @18593
6448
0
    GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(18654), // Rule ID 2530 //
6449
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6450
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
6451
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
6452
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6453
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6454
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6455
      // (and:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)  =>  (VANDd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)
6456
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VANDd),
6457
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
6458
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
6459
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
6460
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6461
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6462
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6463
0
      GIR_EraseFromParent, /*InsnID*/0,
6464
      // GIR_Coverage, 2530,
6465
0
      GIR_Done,
6466
    // Label 368: @18654
6467
0
    GIM_Reject,
6468
    // Label 323: @18655
6469
0
    GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(18794),
6470
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
6471
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6472
0
      GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(18721), // Rule ID 2534 //
6473
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6474
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6475
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6476
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6477
        // (and:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)  =>  (VANDq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)
6478
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VANDq),
6479
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
6480
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
6481
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
6482
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6483
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6484
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6485
0
        GIR_EraseFromParent, /*InsnID*/0,
6486
        // GIR_Coverage, 2534,
6487
0
        GIR_Done,
6488
      // Label 370: @18721
6489
0
      GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(18793), // Rule ID 3468 //
6490
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
6491
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6492
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6493
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6494
        // (and:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VAND:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
6495
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6496
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6497
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
6498
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND),
6499
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
6500
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
6501
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
6502
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6503
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6504
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6505
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6506
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6507
0
        GIR_EraseFromParent, /*InsnID*/0,
6508
        // GIR_Coverage, 3468,
6509
0
        GIR_Done,
6510
      // Label 371: @18793
6511
0
      GIM_Reject,
6512
    // Label 369: @18794
6513
0
    GIM_Reject,
6514
    // Label 324: @18795
6515
0
    GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(18916), // Rule ID 1853 //
6516
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
6517
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1,
6518
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1,
6519
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
6520
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
6521
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
6522
      // (and:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
6523
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6524
0
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
6525
0
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
6526
0
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
6527
0
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6528
0
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
6529
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
6530
0
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
6531
0
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6532
0
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
6533
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
6534
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
6535
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6536
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
6537
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
6538
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
6539
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6540
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6541
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6542
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
6543
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
6544
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6545
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
6546
0
      GIR_EraseFromParent, /*InsnID*/0,
6547
      // GIR_Coverage, 1853,
6548
0
      GIR_Done,
6549
    // Label 372: @18916
6550
0
    GIM_Reject,
6551
    // Label 325: @18917
6552
0
    GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(19056),
6553
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
6554
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6555
0
      GIM_Try, /*On fail goto*//*Label 374*/ GIMT_Encode4(18983), // Rule ID 2533 //
6556
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6557
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6558
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6559
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6560
        // (and:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)  =>  (VANDq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)
6561
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VANDq),
6562
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
6563
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
6564
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
6565
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6566
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6567
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6568
0
        GIR_EraseFromParent, /*InsnID*/0,
6569
        // GIR_Coverage, 2533,
6570
0
        GIR_Done,
6571
      // Label 374: @18983
6572
0
      GIM_Try, /*On fail goto*//*Label 375*/ GIMT_Encode4(19055), // Rule ID 3464 //
6573
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
6574
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6575
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6576
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6577
        // (and:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VAND:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
6578
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6579
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6580
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
6581
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND),
6582
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
6583
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
6584
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
6585
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6586
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6587
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6588
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6589
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6590
0
        GIR_EraseFromParent, /*InsnID*/0,
6591
        // GIR_Coverage, 3464,
6592
0
        GIR_Done,
6593
      // Label 375: @19055
6594
0
      GIM_Reject,
6595
    // Label 373: @19056
6596
0
    GIM_Reject,
6597
    // Label 326: @19057
6598
0
    GIM_Reject,
6599
    // Label 6: @19058
6600
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 389*/ GIMT_Encode4(25512),
6601
0
    /*GILLT_s32*//*Label 376*/ GIMT_Encode4(19129),
6602
0
    /*GILLT_s64*//*Label 377*/ GIMT_Encode4(24216),
6603
0
    /*GILLT_v2s1*//*Label 378*/ GIMT_Encode4(24278),
6604
0
    /*GILLT_v2s32*//*Label 379*/ GIMT_Encode4(24400),
6605
0
    /*GILLT_v2s64*//*Label 380*/ GIMT_Encode4(24462),
6606
0
    /*GILLT_v4s1*//*Label 381*/ GIMT_Encode4(24602),
6607
0
    /*GILLT_v4s16*//*Label 382*/ GIMT_Encode4(24724),
6608
0
    /*GILLT_v4s32*//*Label 383*/ GIMT_Encode4(24786), GIMT_Encode4(0),
6609
0
    /*GILLT_v8s1*//*Label 384*/ GIMT_Encode4(24926),
6610
0
    /*GILLT_v8s8*//*Label 385*/ GIMT_Encode4(25048),
6611
0
    /*GILLT_v8s16*//*Label 386*/ GIMT_Encode4(25110), GIMT_Encode4(0),
6612
0
    /*GILLT_v16s1*//*Label 387*/ GIMT_Encode4(25250),
6613
0
    /*GILLT_v16s8*//*Label 388*/ GIMT_Encode4(25372),
6614
    // Label 376: @19129
6615
0
    GIM_Try, /*On fail goto*//*Label 390*/ GIMT_Encode4(24215),
6616
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
6617
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6618
0
      GIM_Try, /*On fail goto*//*Label 391*/ GIMT_Encode4(19282), // Rule ID 5781 //
6619
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
6620
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6621
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6622
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6623
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6624
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6625
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6626
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
6627
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6628
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6629
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6630
0
        GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8,
6631
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
6632
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6633
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
6634
0
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6635
0
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6636
0
        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6637
0
        GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL),
6638
0
        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6639
        // MIs[4] Rm
6640
0
        GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
6641
0
        GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24,
6642
0
        GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
6643
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
6644
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
6645
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
6646
0
        GIM_CheckIsSafeToFold, /*InsnID*/4,
6647
        // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }))  =>  (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
6648
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::REVSH),
6649
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
6650
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6651
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6652
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6653
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6654
0
        GIR_EraseFromParent, /*InsnID*/0,
6655
        // GIR_Coverage, 5781,
6656
0
        GIR_Done,
6657
      // Label 391: @19282
6658
0
      GIM_Try, /*On fail goto*//*Label 392*/ GIMT_Encode4(19422), // Rule ID 5823 //
6659
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
6660
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6661
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6662
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6663
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6664
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6665
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6666
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
6667
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6668
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6669
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6670
0
        GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8,
6671
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
6672
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6673
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
6674
0
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6675
0
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6676
0
        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6677
0
        GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL),
6678
0
        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6679
        // MIs[4] Rm
6680
0
        GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
6681
0
        GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24,
6682
0
        GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
6683
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
6684
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
6685
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
6686
0
        GIM_CheckIsSafeToFold, /*InsnID*/4,
6687
        // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }))  =>  (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
6688
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2REVSH),
6689
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
6690
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6691
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6692
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6693
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6694
0
        GIR_EraseFromParent, /*InsnID*/0,
6695
        // GIR_Coverage, 5823,
6696
0
        GIR_Done,
6697
      // Label 392: @19422
6698
0
      GIM_Try, /*On fail goto*//*Label 393*/ GIMT_Encode4(19562), // Rule ID 1942 //
6699
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
6700
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6701
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6702
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
6703
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6704
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6705
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6706
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
6707
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6708
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6709
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6710
0
        GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
6711
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
6712
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6713
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
6714
0
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6715
0
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6716
0
        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6717
0
        GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
6718
0
        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6719
        // MIs[4] Rm
6720
0
        GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
6721
0
        GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
6722
0
        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255),
6723
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
6724
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
6725
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
6726
0
        GIM_CheckIsSafeToFold, /*InsnID*/4,
6727
        // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }))  =>  (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
6728
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::REVSH),
6729
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
6730
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6731
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6732
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6733
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6734
0
        GIR_EraseFromParent, /*InsnID*/0,
6735
        // GIR_Coverage, 1942,
6736
0
        GIR_Done,
6737
      // Label 393: @19562
6738
0
      GIM_Try, /*On fail goto*//*Label 394*/ GIMT_Encode4(19702), // Rule ID 2212 //
6739
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
6740
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6741
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6742
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
6743
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6744
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6745
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6746
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
6747
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6748
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6749
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6750
0
        GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
6751
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
6752
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6753
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
6754
0
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6755
0
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6756
0
        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6757
0
        GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
6758
0
        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6759
        // MIs[4] Rm
6760
0
        GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
6761
0
        GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
6762
0
        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255),
6763
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
6764
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
6765
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
6766
0
        GIM_CheckIsSafeToFold, /*InsnID*/4,
6767
        // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }))  =>  (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
6768
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2REVSH),
6769
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
6770
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6771
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6772
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6773
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6774
0
        GIR_EraseFromParent, /*InsnID*/0,
6775
        // GIR_Coverage, 2212,
6776
0
        GIR_Done,
6777
      // Label 394: @19702
6778
0
      GIM_Try, /*On fail goto*//*Label 395*/ GIMT_Encode4(19848), // Rule ID 5579 //
6779
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
6780
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6781
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6782
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6783
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6784
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6785
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6786
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
6787
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6788
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6789
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6790
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6791
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6792
0
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt),
6793
        // MIs[3] Operand 1
6794
        // No operand predicates
6795
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
6796
0
        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
6797
0
        GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
6798
0
        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
6799
0
        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6800
0
        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6801
0
        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760),
6802
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
6803
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
6804
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
6805
0
        GIM_CheckIsSafeToFold, /*InsnID*/4,
6806
        // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
6807
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
6808
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
6809
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
6810
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6811
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6812
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6813
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6814
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6815
0
        GIR_EraseFromParent, /*InsnID*/0,
6816
        // GIR_Coverage, 5579,
6817
0
        GIR_Done,
6818
      // Label 395: @19848
6819
0
      GIM_Try, /*On fail goto*//*Label 396*/ GIMT_Encode4(19994), // Rule ID 5616 //
6820
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
6821
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6822
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6823
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6824
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6825
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6826
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6827
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
6828
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6829
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6830
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6831
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6832
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6833
0
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt),
6834
        // MIs[3] Operand 1
6835
        // No operand predicates
6836
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
6837
0
        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
6838
0
        GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
6839
0
        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
6840
0
        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6841
0
        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6842
0
        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760),
6843
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
6844
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
6845
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
6846
0
        GIM_CheckIsSafeToFold, /*InsnID*/4,
6847
        // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
6848
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
6849
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
6850
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
6851
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6852
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6853
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6854
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6855
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6856
0
        GIR_EraseFromParent, /*InsnID*/0,
6857
        // GIR_Coverage, 5616,
6858
0
        GIR_Done,
6859
      // Label 396: @19994
6860
0
      GIM_Try, /*On fail goto*//*Label 397*/ GIMT_Encode4(20140), // Rule ID 5786 //
6861
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
6862
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6863
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6864
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6865
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6866
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6867
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6868
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
6869
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6870
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6871
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6872
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6873
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6874
0
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15),
6875
        // MIs[3] Operand 1
6876
        // No operand predicates
6877
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
6878
0
        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
6879
0
        GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
6880
0
        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
6881
0
        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6882
0
        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6883
0
        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760),
6884
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
6885
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
6886
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
6887
0
        GIM_CheckIsSafeToFold, /*InsnID*/4,
6888
        // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
6889
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
6890
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
6891
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
6892
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
6893
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6894
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6895
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6896
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6897
0
        GIR_EraseFromParent, /*InsnID*/0,
6898
        // GIR_Coverage, 5786,
6899
0
        GIR_Done,
6900
      // Label 397: @20140
6901
0
      GIM_Try, /*On fail goto*//*Label 398*/ GIMT_Encode4(20286), // Rule ID 5828 //
6902
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
6903
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6904
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6905
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6906
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6907
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6908
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6909
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
6910
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6911
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6912
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6913
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6914
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6915
0
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15),
6916
        // MIs[3] Operand 1
6917
        // No operand predicates
6918
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
6919
0
        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
6920
0
        GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
6921
0
        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
6922
0
        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6923
0
        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6924
0
        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760),
6925
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
6926
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
6927
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
6928
0
        GIM_CheckIsSafeToFold, /*InsnID*/4,
6929
        // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
6930
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
6931
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
6932
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
6933
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
6934
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6935
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6936
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6937
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6938
0
        GIR_EraseFromParent, /*InsnID*/0,
6939
        // GIR_Coverage, 5828,
6940
0
        GIR_Done,
6941
      // Label 398: @20286
6942
0
      GIM_Try, /*On fail goto*//*Label 399*/ GIMT_Encode4(20432), // Rule ID 5578 //
6943
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
6944
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6945
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6946
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6947
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6948
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6949
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6950
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
6951
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6952
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6953
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6954
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6955
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6956
0
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt),
6957
        // MIs[3] Operand 1
6958
        // No operand predicates
6959
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
6960
0
        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
6961
0
        GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
6962
0
        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
6963
0
        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6964
0
        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6965
0
        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(65535),
6966
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
6967
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
6968
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
6969
0
        GIM_CheckIsSafeToFold, /*InsnID*/4,
6970
        // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
6971
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
6972
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
6973
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
6974
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6975
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6976
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6977
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6978
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6979
0
        GIR_EraseFromParent, /*InsnID*/0,
6980
        // GIR_Coverage, 5578,
6981
0
        GIR_Done,
6982
      // Label 399: @20432
6983
0
      GIM_Try, /*On fail goto*//*Label 400*/ GIMT_Encode4(20578), // Rule ID 5615 //
6984
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
6985
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6986
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6987
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6988
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6989
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6990
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6991
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
6992
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6993
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6994
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6995
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6996
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6997
0
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt),
6998
        // MIs[3] Operand 1
6999
        // No operand predicates
7000
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
7001
0
        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
7002
0
        GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
7003
0
        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
7004
0
        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7005
0
        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7006
0
        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(65535),
7007
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7008
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7009
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
7010
0
        GIM_CheckIsSafeToFold, /*InsnID*/4,
7011
        // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] }))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7012
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
7013
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7014
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
7015
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7016
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7017
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7018
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7019
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7020
0
        GIR_EraseFromParent, /*InsnID*/0,
7021
        // GIR_Coverage, 5615,
7022
0
        GIR_Done,
7023
      // Label 400: @20578
7024
0
      GIM_Try, /*On fail goto*//*Label 401*/ GIMT_Encode4(20724), // Rule ID 203 //
7025
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
7026
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7027
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7028
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7029
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7030
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7031
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7032
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
7033
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7034
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7035
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7036
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7037
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
7038
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
7039
0
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7040
0
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7041
0
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7042
0
        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
7043
0
        GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7044
0
        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt),
7045
        // MIs[4] Operand 1
7046
        // No operand predicates
7047
0
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
7048
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7049
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7050
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
7051
0
        GIM_CheckIsSafeToFold, /*InsnID*/4,
7052
        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7053
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
7054
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7055
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7056
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
7057
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
7058
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7059
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7060
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7061
0
        GIR_EraseFromParent, /*InsnID*/0,
7062
        // GIR_Coverage, 203,
7063
0
        GIR_Done,
7064
      // Label 401: @20724
7065
0
      GIM_Try, /*On fail goto*//*Label 402*/ GIMT_Encode4(20870), // Rule ID 548 //
7066
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
7067
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7068
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7069
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7070
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7071
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7072
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7073
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
7074
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7075
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7076
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7077
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7078
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
7079
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
7080
0
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7081
0
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7082
0
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7083
0
        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
7084
0
        GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7085
0
        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt),
7086
        // MIs[4] Operand 1
7087
        // No operand predicates
7088
0
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
7089
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7090
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7091
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
7092
0
        GIM_CheckIsSafeToFold, /*InsnID*/4,
7093
        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7094
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
7095
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7096
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7097
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
7098
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
7099
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7100
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7101
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7102
0
        GIR_EraseFromParent, /*InsnID*/0,
7103
        // GIR_Coverage, 548,
7104
0
        GIR_Done,
7105
      // Label 402: @20870
7106
0
      GIM_Try, /*On fail goto*//*Label 403*/ GIMT_Encode4(21016), // Rule ID 1947 //
7107
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
7108
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7109
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7110
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7111
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7112
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7113
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7114
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
7115
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7116
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7117
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7118
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7119
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
7120
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
7121
0
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7122
0
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7123
0
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7124
0
        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
7125
0
        GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7126
0
        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15),
7127
        // MIs[4] Operand 1
7128
        // No operand predicates
7129
0
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
7130
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7131
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7132
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
7133
0
        GIM_CheckIsSafeToFold, /*InsnID*/4,
7134
        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
7135
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
7136
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7137
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7138
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2
7139
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
7140
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7141
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7142
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7143
0
        GIR_EraseFromParent, /*InsnID*/0,
7144
        // GIR_Coverage, 1947,
7145
0
        GIR_Done,
7146
      // Label 403: @21016
7147
0
      GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(21162), // Rule ID 2217 //
7148
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
7149
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7150
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7151
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7152
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7153
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7154
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7155
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
7156
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7157
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7158
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7159
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7160
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
7161
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
7162
0
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7163
0
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7164
0
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7165
0
        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
7166
0
        GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7167
0
        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15),
7168
        // MIs[4] Operand 1
7169
        // No operand predicates
7170
0
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
7171
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7172
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7173
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
7174
0
        GIM_CheckIsSafeToFold, /*InsnID*/4,
7175
        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
7176
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
7177
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7178
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7179
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2
7180
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
7181
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7182
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7183
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7184
0
        GIR_EraseFromParent, /*InsnID*/0,
7185
        // GIR_Coverage, 2217,
7186
0
        GIR_Done,
7187
      // Label 404: @21162
7188
0
      GIM_Try, /*On fail goto*//*Label 405*/ GIMT_Encode4(21308), // Rule ID 202 //
7189
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
7190
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7191
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7192
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7193
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7194
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7195
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7196
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
7197
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7198
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7199
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7200
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7201
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
7202
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
7203
0
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7204
0
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7205
0
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7206
0
        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
7207
0
        GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7208
0
        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt),
7209
        // MIs[4] Operand 1
7210
        // No operand predicates
7211
0
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760),
7212
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7213
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7214
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
7215
0
        GIM_CheckIsSafeToFold, /*InsnID*/4,
7216
        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7217
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
7218
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7219
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7220
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
7221
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
7222
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7223
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7224
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7225
0
        GIR_EraseFromParent, /*InsnID*/0,
7226
        // GIR_Coverage, 202,
7227
0
        GIR_Done,
7228
      // Label 405: @21308
7229
0
      GIM_Try, /*On fail goto*//*Label 406*/ GIMT_Encode4(21454), // Rule ID 547 //
7230
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
7231
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7232
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7233
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7234
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7235
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7236
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7237
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
7238
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7239
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7240
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7241
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7242
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
7243
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
7244
0
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7245
0
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7246
0
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7247
0
        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
7248
0
        GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7249
0
        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt),
7250
        // MIs[4] Operand 1
7251
        // No operand predicates
7252
0
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760),
7253
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7254
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7255
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
7256
0
        GIM_CheckIsSafeToFold, /*InsnID*/4,
7257
        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7258
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
7259
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7260
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7261
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
7262
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
7263
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7264
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7265
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7266
0
        GIR_EraseFromParent, /*InsnID*/0,
7267
        // GIR_Coverage, 547,
7268
0
        GIR_Done,
7269
      // Label 406: @21454
7270
0
      GIM_Try, /*On fail goto*//*Label 407*/ GIMT_Encode4(21568), // Rule ID 1943 //
7271
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
7272
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7273
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7274
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7275
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7276
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7277
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7278
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
7279
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7280
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7281
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7282
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7283
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7284
0
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760),
7285
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7286
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7287
        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] }))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
7288
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
7289
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7290
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7291
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7292
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
7293
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7294
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7295
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7296
0
        GIR_EraseFromParent, /*InsnID*/0,
7297
        // GIR_Coverage, 1943,
7298
0
        GIR_Done,
7299
      // Label 407: @21568
7300
0
      GIM_Try, /*On fail goto*//*Label 408*/ GIMT_Encode4(21682), // Rule ID 2213 //
7301
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
7302
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7303
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7304
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7305
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7306
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7307
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7308
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
7309
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7310
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7311
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7312
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7313
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7314
0
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760),
7315
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7316
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7317
        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] }))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] })
7318
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
7319
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7320
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7321
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
7322
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
7323
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7324
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7325
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7326
0
        GIR_EraseFromParent, /*InsnID*/0,
7327
        // GIR_Coverage, 2213,
7328
0
        GIR_Done,
7329
      // Label 408: @21682
7330
0
      GIM_Try, /*On fail goto*//*Label 409*/ GIMT_Encode4(21796), // Rule ID 5782 //
7331
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
7332
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7333
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7334
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7335
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7336
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7337
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7338
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
7339
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7340
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7341
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7342
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7343
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7344
0
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
7345
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7346
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7347
        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
7348
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
7349
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7350
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
7351
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7352
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
7353
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7354
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7355
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7356
0
        GIR_EraseFromParent, /*InsnID*/0,
7357
        // GIR_Coverage, 5782,
7358
0
        GIR_Done,
7359
      // Label 409: @21796
7360
0
      GIM_Try, /*On fail goto*//*Label 410*/ GIMT_Encode4(21910), // Rule ID 5824 //
7361
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
7362
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7363
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7364
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7365
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7366
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7367
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7368
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
7369
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7370
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7371
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7372
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7373
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7374
0
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
7375
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7376
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7377
        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] })
7378
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
7379
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7380
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
7381
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
7382
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
7383
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7384
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7385
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7386
0
        GIR_EraseFromParent, /*InsnID*/0,
7387
        // GIR_Coverage, 5824,
7388
0
        GIR_Done,
7389
      // Label 410: @21910
7390
0
      GIM_Try, /*On fail goto*//*Label 411*/ GIMT_Encode4(22027), // Rule ID 1946 //
7391
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
7392
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7393
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7394
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7395
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7396
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7397
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7398
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
7399
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7400
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
7401
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7402
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7403
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7404
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7405
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7406
0
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
7407
        // MIs[3] Operand 1
7408
        // No operand predicates
7409
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7410
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7411
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
7412
        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7413
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
7414
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7415
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7416
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
7417
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7418
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7419
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7420
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7421
0
        GIR_EraseFromParent, /*InsnID*/0,
7422
        // GIR_Coverage, 1946,
7423
0
        GIR_Done,
7424
      // Label 411: @22027
7425
0
      GIM_Try, /*On fail goto*//*Label 412*/ GIMT_Encode4(22144), // Rule ID 2216 //
7426
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
7427
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7428
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7429
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7430
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7431
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7432
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7433
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
7434
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7435
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
7436
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7437
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7438
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7439
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7440
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7441
0
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
7442
        // MIs[3] Operand 1
7443
        // No operand predicates
7444
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7445
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7446
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
7447
        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7448
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
7449
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7450
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7451
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
7452
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7453
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7454
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7455
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7456
0
        GIR_EraseFromParent, /*InsnID*/0,
7457
        // GIR_Coverage, 2216,
7458
0
        GIR_Done,
7459
      // Label 412: @22144
7460
0
      GIM_Try, /*On fail goto*//*Label 413*/ GIMT_Encode4(22261), // Rule ID 1945 //
7461
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
7462
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7463
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7464
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7465
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7466
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7467
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7468
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
7469
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7470
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
7471
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7472
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7473
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7474
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7475
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7476
0
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16),
7477
        // MIs[3] Operand 1
7478
        // No operand predicates
7479
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7480
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7481
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
7482
        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
7483
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
7484
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7485
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7486
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
7487
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7488
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7489
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7490
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7491
0
        GIR_EraseFromParent, /*InsnID*/0,
7492
        // GIR_Coverage, 1945,
7493
0
        GIR_Done,
7494
      // Label 413: @22261
7495
0
      GIM_Try, /*On fail goto*//*Label 414*/ GIMT_Encode4(22378), // Rule ID 2215 //
7496
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
7497
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7498
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7499
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7500
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7501
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7502
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7503
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
7504
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7505
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
7506
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7507
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7508
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7509
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7510
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7511
0
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16),
7512
        // MIs[3] Operand 1
7513
        // No operand predicates
7514
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7515
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7516
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
7517
        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
7518
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
7519
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7520
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7521
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
7522
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7523
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7524
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7525
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7526
0
        GIR_EraseFromParent, /*InsnID*/0,
7527
        // GIR_Coverage, 2215,
7528
0
        GIR_Done,
7529
      // Label 414: @22378
7530
0
      GIM_Try, /*On fail goto*//*Label 415*/ GIMT_Encode4(22495), // Rule ID 1944 //
7531
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
7532
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7533
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7534
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7535
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7536
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7537
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7538
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
7539
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7540
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
7541
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7542
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7543
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7544
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7545
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7546
0
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
7547
        // MIs[3] Operand 1
7548
        // No operand predicates
7549
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7550
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7551
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
7552
        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7553
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
7554
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7555
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7556
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7557
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7558
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7559
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7560
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7561
0
        GIR_EraseFromParent, /*InsnID*/0,
7562
        // GIR_Coverage, 1944,
7563
0
        GIR_Done,
7564
      // Label 415: @22495
7565
0
      GIM_Try, /*On fail goto*//*Label 416*/ GIMT_Encode4(22612), // Rule ID 2214 //
7566
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
7567
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7568
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7569
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7570
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7571
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7572
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7573
0
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
7574
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7575
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
7576
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7577
0
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7578
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7579
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7580
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7581
0
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
7582
        // MIs[3] Operand 1
7583
        // No operand predicates
7584
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7585
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7586
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
7587
        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7588
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
7589
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7590
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7591
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
7592
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7593
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7594
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7595
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7596
0
        GIR_EraseFromParent, /*InsnID*/0,
7597
        // GIR_Coverage, 2214,
7598
0
        GIR_Done,
7599
      // Label 416: @22612
7600
0
      GIM_Try, /*On fail goto*//*Label 417*/ GIMT_Encode4(22729), // Rule ID 5785 //
7601
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
7602
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7603
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7604
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
7605
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7606
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7607
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7608
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7609
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7610
0
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
7611
        // MIs[2] Operand 1
7612
        // No operand predicates
7613
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7614
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
7615
0
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7616
0
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7617
0
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7618
0
        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760),
7619
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7620
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7621
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
7622
        // (or:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7623
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
7624
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7625
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
7626
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
7627
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
7628
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7629
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7630
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7631
0
        GIR_EraseFromParent, /*InsnID*/0,
7632
        // GIR_Coverage, 5785,
7633
0
        GIR_Done,
7634
      // Label 417: @22729
7635
0
      GIM_Try, /*On fail goto*//*Label 418*/ GIMT_Encode4(22846), // Rule ID 5827 //
7636
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
7637
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7638
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7639
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
7640
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7641
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7642
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7643
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7644
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7645
0
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
7646
        // MIs[2] Operand 1
7647
        // No operand predicates
7648
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7649
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
7650
0
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7651
0
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7652
0
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7653
0
        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760),
7654
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7655
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7656
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
7657
        // (or:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7658
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
7659
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7660
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
7661
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
7662
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
7663
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7664
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7665
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7666
0
        GIR_EraseFromParent, /*InsnID*/0,
7667
        // GIR_Coverage, 5827,
7668
0
        GIR_Done,
7669
      // Label 418: @22846
7670
0
      GIM_Try, /*On fail goto*//*Label 419*/ GIMT_Encode4(22963), // Rule ID 5784 //
7671
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
7672
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7673
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7674
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
7675
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7676
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7677
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7678
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7679
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7680
0
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16),
7681
        // MIs[2] Operand 1
7682
        // No operand predicates
7683
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7684
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
7685
0
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7686
0
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7687
0
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7688
0
        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760),
7689
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7690
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7691
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
7692
        // (or:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
7693
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
7694
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7695
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
7696
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
7697
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
7698
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7699
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7700
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7701
0
        GIR_EraseFromParent, /*InsnID*/0,
7702
        // GIR_Coverage, 5784,
7703
0
        GIR_Done,
7704
      // Label 419: @22963
7705
0
      GIM_Try, /*On fail goto*//*Label 420*/ GIMT_Encode4(23080), // Rule ID 5826 //
7706
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
7707
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7708
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7709
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
7710
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7711
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7712
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7713
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7714
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7715
0
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16),
7716
        // MIs[2] Operand 1
7717
        // No operand predicates
7718
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7719
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
7720
0
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7721
0
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7722
0
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7723
0
        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760),
7724
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7725
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7726
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
7727
        // (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
7728
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
7729
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7730
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
7731
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
7732
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
7733
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7734
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7735
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7736
0
        GIR_EraseFromParent, /*InsnID*/0,
7737
        // GIR_Coverage, 5826,
7738
0
        GIR_Done,
7739
      // Label 420: @23080
7740
0
      GIM_Try, /*On fail goto*//*Label 421*/ GIMT_Encode4(23197), // Rule ID 5783 //
7741
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
7742
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7743
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7744
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
7745
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7746
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7747
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7748
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7749
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7750
0
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
7751
        // MIs[2] Operand 1
7752
        // No operand predicates
7753
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7754
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
7755
0
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7756
0
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7757
0
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7758
0
        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535),
7759
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7760
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7761
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
7762
        // (or:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7763
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
7764
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7765
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
7766
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7767
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
7768
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7769
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7770
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7771
0
        GIR_EraseFromParent, /*InsnID*/0,
7772
        // GIR_Coverage, 5783,
7773
0
        GIR_Done,
7774
      // Label 421: @23197
7775
0
      GIM_Try, /*On fail goto*//*Label 422*/ GIMT_Encode4(23314), // Rule ID 5825 //
7776
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
7777
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7778
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7779
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
7780
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7781
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7782
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7783
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7784
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7785
0
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
7786
        // MIs[2] Operand 1
7787
        // No operand predicates
7788
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7789
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
7790
0
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7791
0
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7792
0
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7793
0
        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535),
7794
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7795
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7796
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
7797
        // (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7798
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
7799
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7800
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
7801
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
7802
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
7803
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7804
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7805
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7806
0
        GIR_EraseFromParent, /*InsnID*/0,
7807
        // GIR_Coverage, 5825,
7808
0
        GIR_Done,
7809
      // Label 422: @23314
7810
0
      GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(23403), // Rule ID 5603 //
7811
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
7812
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7813
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7814
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
7815
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7816
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7817
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1),
7818
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7819
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7820
0
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
7821
        // MIs[2] Operand 1
7822
        // No operand predicates
7823
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7824
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7825
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7826
        // (or:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn)  =>  (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7827
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2ORNri),
7828
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7829
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
7830
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
7831
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7832
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7833
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7834
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7835
0
        GIR_EraseFromParent, /*InsnID*/0,
7836
        // GIR_Coverage, 5603,
7837
0
        GIR_Done,
7838
      // Label 423: @23403
7839
0
      GIM_Try, /*On fail goto*//*Label 424*/ GIMT_Encode4(23492), // Rule ID 5602 //
7840
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
7841
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7842
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7843
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
7844
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7845
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7846
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7847
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7848
0
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
7849
        // MIs[2] Operand 1
7850
        // No operand predicates
7851
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
7852
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7853
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7854
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7855
        // (or:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7856
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2ORNri),
7857
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7858
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
7859
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
7860
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7861
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7862
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7863
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7864
0
        GIR_EraseFromParent, /*InsnID*/0,
7865
        // GIR_Coverage, 5602,
7866
0
        GIR_Done,
7867
      // Label 424: @23492
7868
0
      GIM_Try, /*On fail goto*//*Label 425*/ GIMT_Encode4(23581), // Rule ID 5601 //
7869
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
7870
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7871
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7872
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7873
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
7874
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7875
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7876
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1),
7877
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7878
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7879
0
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
7880
        // MIs[2] Operand 1
7881
        // No operand predicates
7882
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7883
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7884
        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm))  =>  (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7885
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2ORNri),
7886
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7887
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
7888
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
7889
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7890
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7891
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7892
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7893
0
        GIR_EraseFromParent, /*InsnID*/0,
7894
        // GIR_Coverage, 5601,
7895
0
        GIR_Done,
7896
      // Label 425: @23581
7897
0
      GIM_Try, /*On fail goto*//*Label 426*/ GIMT_Encode4(23670), // Rule ID 504 //
7898
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
7899
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7900
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7901
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7902
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
7903
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7904
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7905
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7906
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7907
0
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
7908
        // MIs[2] Operand 1
7909
        // No operand predicates
7910
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
7911
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7912
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
7913
        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }))  =>  (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7914
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2ORNri),
7915
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7916
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
7917
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
7918
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7919
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7920
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7921
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7922
0
        GIR_EraseFromParent, /*InsnID*/0,
7923
        // GIR_Coverage, 504,
7924
0
        GIR_Done,
7925
      // Label 426: @23670
7926
0
      GIM_Try, /*On fail goto*//*Label 427*/ GIMT_Encode4(23751), // Rule ID 5604 //
7927
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
7928
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7929
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7930
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
7931
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7932
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7933
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7934
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
7935
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7936
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7937
        // (or:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
7938
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2ORNrr),
7939
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7940
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
7941
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7942
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7943
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7944
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7945
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7946
0
        GIR_EraseFromParent, /*InsnID*/0,
7947
        // GIR_Coverage, 5604,
7948
0
        GIR_Done,
7949
      // Label 427: @23751
7950
0
      GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(23832), // Rule ID 505 //
7951
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
7952
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7953
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7954
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7955
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
7956
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7957
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7958
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7959
0
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
7960
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
7961
        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }))  =>  (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
7962
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2ORNrr),
7963
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7964
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
7965
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7966
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7967
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7968
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7969
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7970
0
        GIR_EraseFromParent, /*InsnID*/0,
7971
        // GIR_Coverage, 505,
7972
0
        GIR_Done,
7973
      // Label 428: @23832
7974
0
      GIM_Try, /*On fail goto*//*Label 429*/ GIMT_Encode4(23897), // Rule ID 1872 //
7975
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM),
7976
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7977
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7978
0
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294901760),
7979
        // (or:{ *:[i32] } GPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] })  =>  (MOVTi16:{ *:[i32] } GPR:{ *:[i32] }:$src, 65535:{ *:[i32] })
7980
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MOVTi16),
7981
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7982
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7983
0
        GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(65535),
7984
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7985
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7986
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7987
0
        GIR_EraseFromParent, /*InsnID*/0,
7988
        // GIR_Coverage, 1872,
7989
0
        GIR_Done,
7990
      // Label 429: @23897
7991
0
      GIM_Try, /*On fail goto*//*Label 430*/ GIMT_Encode4(23962), // Rule ID 2107 //
7992
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
7993
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7994
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7995
0
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294901760),
7996
        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] })  =>  (t2MOVTi16:{ *:[i32] } rGPR:{ *:[i32] }:$src, 65535:{ *:[i32] })
7997
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2MOVTi16),
7998
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
7999
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8000
0
        GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(65535),
8001
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8002
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8003
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8004
0
        GIR_EraseFromParent, /*InsnID*/0,
8005
        // GIR_Coverage, 2107,
8006
0
        GIR_Done,
8007
      // Label 430: @23962
8008
0
      GIM_Try, /*On fail goto*//*Label 431*/ GIMT_Encode4(24029), // Rule ID 151 //
8009
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
8010
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8011
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8012
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8013
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8014
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
8015
        // MIs[1] Operand 1
8016
        // No operand predicates
8017
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
8018
        // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (ORRri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8019
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::ORRri),
8020
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
8021
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
8022
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
8023
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8024
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8025
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8026
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8027
0
        GIR_EraseFromParent, /*InsnID*/0,
8028
        // GIR_Coverage, 151,
8029
0
        GIR_Done,
8030
      // Label 431: @24029
8031
0
      GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(24096), // Rule ID 492 //
8032
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
8033
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8034
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8035
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8036
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8037
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
8038
        // MIs[1] Operand 1
8039
        // No operand predicates
8040
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
8041
        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2ORRri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8042
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2ORRri),
8043
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
8044
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
8045
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
8046
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8047
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8048
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8049
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8050
0
        GIR_EraseFromParent, /*InsnID*/0,
8051
        // GIR_Coverage, 492,
8052
0
        GIR_Done,
8053
      // Label 432: @24096
8054
0
      GIM_Try, /*On fail goto*//*Label 433*/ GIMT_Encode4(24155), // Rule ID 152 //
8055
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
8056
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8057
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8058
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8059
        // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (ORRrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
8060
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::ORRrr),
8061
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
8062
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
8063
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
8064
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8065
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8066
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8067
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8068
0
        GIR_EraseFromParent, /*InsnID*/0,
8069
        // GIR_Coverage, 152,
8070
0
        GIR_Done,
8071
      // Label 433: @24155
8072
0
      GIM_Try, /*On fail goto*//*Label 434*/ GIMT_Encode4(24214), // Rule ID 493 //
8073
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
8074
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8075
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8076
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8077
        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2ORRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
8078
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
8079
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
8080
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
8081
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
8082
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8083
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8084
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8085
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8086
0
        GIR_EraseFromParent, /*InsnID*/0,
8087
        // GIR_Coverage, 493,
8088
0
        GIR_Done,
8089
      // Label 434: @24214
8090
0
      GIM_Reject,
8091
    // Label 390: @24215
8092
0
    GIM_Reject,
8093
    // Label 377: @24216
8094
0
    GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(24277), // Rule ID 2538 //
8095
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8096
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
8097
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
8098
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8099
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8100
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8101
      // (or:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)  =>  (VORRd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)
8102
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VORRd),
8103
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
8104
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
8105
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
8106
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8107
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8108
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8109
0
      GIR_EraseFromParent, /*InsnID*/0,
8110
      // GIR_Coverage, 2538,
8111
0
      GIR_Done,
8112
    // Label 435: @24277
8113
0
    GIM_Reject,
8114
    // Label 378: @24278
8115
0
    GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(24399), // Rule ID 1858 //
8116
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
8117
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s1,
8118
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s1,
8119
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8120
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8121
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8122
      // (or:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8123
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8124
0
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8125
0
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8126
0
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8127
0
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8128
0
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8129
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
8130
0
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8131
0
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8132
0
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8133
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
8134
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
8135
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8136
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
8137
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
8138
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
8139
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8140
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8141
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8142
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8143
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
8144
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
8145
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
8146
0
      GIR_EraseFromParent, /*InsnID*/0,
8147
      // GIR_Coverage, 1858,
8148
0
      GIR_Done,
8149
    // Label 436: @24399
8150
0
    GIM_Reject,
8151
    // Label 379: @24400
8152
0
    GIM_Try, /*On fail goto*//*Label 437*/ GIMT_Encode4(24461), // Rule ID 1154 //
8153
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8154
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8155
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
8156
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8157
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8158
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8159
      // (or:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VORRd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
8160
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VORRd),
8161
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
8162
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
8163
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8164
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8165
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8166
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8167
0
      GIR_EraseFromParent, /*InsnID*/0,
8168
      // GIR_Coverage, 1154,
8169
0
      GIR_Done,
8170
    // Label 437: @24461
8171
0
    GIM_Reject,
8172
    // Label 380: @24462
8173
0
    GIM_Try, /*On fail goto*//*Label 438*/ GIMT_Encode4(24601),
8174
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
8175
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8176
0
      GIM_Try, /*On fail goto*//*Label 439*/ GIMT_Encode4(24528), // Rule ID 2541 //
8177
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8178
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
8179
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
8180
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
8181
        // (or:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)  =>  (VORRq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)
8182
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VORRq),
8183
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
8184
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
8185
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
8186
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8187
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8188
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8189
0
        GIR_EraseFromParent, /*InsnID*/0,
8190
        // GIR_Coverage, 2541,
8191
0
        GIR_Done,
8192
      // Label 439: @24528
8193
0
      GIM_Try, /*On fail goto*//*Label 440*/ GIMT_Encode4(24600), // Rule ID 3490 //
8194
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
8195
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
8196
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
8197
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
8198
        // (or:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)  =>  (MVE_VORR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
8199
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
8200
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
8201
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
8202
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR),
8203
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
8204
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
8205
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
8206
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
8207
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8208
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8209
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
8210
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8211
0
        GIR_EraseFromParent, /*InsnID*/0,
8212
        // GIR_Coverage, 3490,
8213
0
        GIR_Done,
8214
      // Label 440: @24600
8215
0
      GIM_Reject,
8216
    // Label 438: @24601
8217
0
    GIM_Reject,
8218
    // Label 381: @24602
8219
0
    GIM_Try, /*On fail goto*//*Label 441*/ GIMT_Encode4(24723), // Rule ID 1859 //
8220
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
8221
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1,
8222
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1,
8223
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8224
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8225
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8226
      // (or:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8227
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8228
0
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8229
0
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8230
0
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8231
0
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8232
0
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8233
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
8234
0
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8235
0
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8236
0
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8237
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
8238
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
8239
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8240
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
8241
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
8242
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
8243
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8244
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8245
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8246
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8247
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
8248
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
8249
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
8250
0
      GIR_EraseFromParent, /*InsnID*/0,
8251
      // GIR_Coverage, 1859,
8252
0
      GIR_Done,
8253
    // Label 441: @24723
8254
0
    GIM_Reject,
8255
    // Label 382: @24724
8256
0
    GIM_Try, /*On fail goto*//*Label 442*/ GIMT_Encode4(24785), // Rule ID 2537 //
8257
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8258
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8259
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
8260
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8261
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8262
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8263
      // (or:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)  =>  (VORRd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)
8264
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VORRd),
8265
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
8266
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
8267
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
8268
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8269
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8270
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8271
0
      GIR_EraseFromParent, /*InsnID*/0,
8272
      // GIR_Coverage, 2537,
8273
0
      GIR_Done,
8274
    // Label 442: @24785
8275
0
    GIM_Reject,
8276
    // Label 383: @24786
8277
0
    GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(24925),
8278
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
8279
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8280
0
      GIM_Try, /*On fail goto*//*Label 444*/ GIMT_Encode4(24852), // Rule ID 1155 //
8281
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8282
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
8283
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
8284
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
8285
        // (or:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VORRq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
8286
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VORRq),
8287
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
8288
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
8289
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8290
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8291
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8292
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8293
0
        GIR_EraseFromParent, /*InsnID*/0,
8294
        // GIR_Coverage, 1155,
8295
0
        GIR_Done,
8296
      // Label 444: @24852
8297
0
      GIM_Try, /*On fail goto*//*Label 445*/ GIMT_Encode4(24924), // Rule ID 3486 //
8298
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
8299
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
8300
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
8301
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
8302
        // (or:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VORR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
8303
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
8304
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
8305
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
8306
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR),
8307
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
8308
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
8309
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
8310
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
8311
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8312
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8313
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
8314
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8315
0
        GIR_EraseFromParent, /*InsnID*/0,
8316
        // GIR_Coverage, 3486,
8317
0
        GIR_Done,
8318
      // Label 445: @24924
8319
0
      GIM_Reject,
8320
    // Label 443: @24925
8321
0
    GIM_Reject,
8322
    // Label 384: @24926
8323
0
    GIM_Try, /*On fail goto*//*Label 446*/ GIMT_Encode4(25047), // Rule ID 1860 //
8324
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
8325
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1,
8326
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1,
8327
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8328
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8329
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8330
      // (or:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8331
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8332
0
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8333
0
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8334
0
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8335
0
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8336
0
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8337
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
8338
0
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8339
0
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8340
0
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8341
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
8342
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
8343
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8344
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
8345
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
8346
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
8347
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8348
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8349
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8350
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8351
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
8352
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
8353
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
8354
0
      GIR_EraseFromParent, /*InsnID*/0,
8355
      // GIR_Coverage, 1860,
8356
0
      GIR_Done,
8357
    // Label 446: @25047
8358
0
    GIM_Reject,
8359
    // Label 385: @25048
8360
0
    GIM_Try, /*On fail goto*//*Label 447*/ GIMT_Encode4(25109), // Rule ID 2536 //
8361
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8362
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
8363
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
8364
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8365
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8366
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8367
      // (or:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)  =>  (VORRd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)
8368
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VORRd),
8369
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
8370
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
8371
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
8372
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8373
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8374
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8375
0
      GIR_EraseFromParent, /*InsnID*/0,
8376
      // GIR_Coverage, 2536,
8377
0
      GIR_Done,
8378
    // Label 447: @25109
8379
0
    GIM_Reject,
8380
    // Label 386: @25110
8381
0
    GIM_Try, /*On fail goto*//*Label 448*/ GIMT_Encode4(25249),
8382
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
8383
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8384
0
      GIM_Try, /*On fail goto*//*Label 449*/ GIMT_Encode4(25176), // Rule ID 2540 //
8385
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8386
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
8387
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
8388
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
8389
        // (or:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)  =>  (VORRq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)
8390
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VORRq),
8391
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
8392
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
8393
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
8394
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8395
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8396
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8397
0
        GIR_EraseFromParent, /*InsnID*/0,
8398
        // GIR_Coverage, 2540,
8399
0
        GIR_Done,
8400
      // Label 449: @25176
8401
0
      GIM_Try, /*On fail goto*//*Label 450*/ GIMT_Encode4(25248), // Rule ID 3482 //
8402
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
8403
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
8404
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
8405
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
8406
        // (or:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VORR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
8407
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
8408
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
8409
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
8410
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR),
8411
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
8412
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
8413
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
8414
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
8415
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8416
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8417
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
8418
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8419
0
        GIR_EraseFromParent, /*InsnID*/0,
8420
        // GIR_Coverage, 3482,
8421
0
        GIR_Done,
8422
      // Label 450: @25248
8423
0
      GIM_Reject,
8424
    // Label 448: @25249
8425
0
    GIM_Reject,
8426
    // Label 387: @25250
8427
0
    GIM_Try, /*On fail goto*//*Label 451*/ GIMT_Encode4(25371), // Rule ID 1861 //
8428
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
8429
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1,
8430
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1,
8431
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8432
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8433
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8434
      // (or:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8435
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8436
0
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8437
0
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8438
0
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8439
0
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8440
0
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8441
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
8442
0
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8443
0
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8444
0
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8445
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
8446
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
8447
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8448
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
8449
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
8450
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
8451
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8452
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8453
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8454
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8455
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
8456
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
8457
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
8458
0
      GIR_EraseFromParent, /*InsnID*/0,
8459
      // GIR_Coverage, 1861,
8460
0
      GIR_Done,
8461
    // Label 451: @25371
8462
0
    GIM_Reject,
8463
    // Label 388: @25372
8464
0
    GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(25511),
8465
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
8466
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8467
0
      GIM_Try, /*On fail goto*//*Label 453*/ GIMT_Encode4(25438), // Rule ID 2539 //
8468
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8469
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
8470
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
8471
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
8472
        // (or:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)  =>  (VORRq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)
8473
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VORRq),
8474
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
8475
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
8476
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
8477
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8478
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8479
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8480
0
        GIR_EraseFromParent, /*InsnID*/0,
8481
        // GIR_Coverage, 2539,
8482
0
        GIR_Done,
8483
      // Label 453: @25438
8484
0
      GIM_Try, /*On fail goto*//*Label 454*/ GIMT_Encode4(25510), // Rule ID 3478 //
8485
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
8486
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
8487
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
8488
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
8489
        // (or:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VORR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
8490
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
8491
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
8492
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
8493
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR),
8494
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
8495
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
8496
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
8497
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
8498
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8499
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8500
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
8501
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8502
0
        GIR_EraseFromParent, /*InsnID*/0,
8503
        // GIR_Coverage, 3478,
8504
0
        GIR_Done,
8505
      // Label 454: @25510
8506
0
      GIM_Reject,
8507
    // Label 452: @25511
8508
0
    GIM_Reject,
8509
    // Label 389: @25512
8510
0
    GIM_Reject,
8511
    // Label 7: @25513
8512
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 468*/ GIMT_Encode4(27379),
8513
0
    /*GILLT_s32*//*Label 455*/ GIMT_Encode4(25584),
8514
0
    /*GILLT_s64*//*Label 456*/ GIMT_Encode4(26083),
8515
0
    /*GILLT_v2s1*//*Label 457*/ GIMT_Encode4(26145),
8516
0
    /*GILLT_v2s32*//*Label 458*/ GIMT_Encode4(26267),
8517
0
    /*GILLT_v2s64*//*Label 459*/ GIMT_Encode4(26329),
8518
0
    /*GILLT_v4s1*//*Label 460*/ GIMT_Encode4(26469),
8519
0
    /*GILLT_v4s16*//*Label 461*/ GIMT_Encode4(26591),
8520
0
    /*GILLT_v4s32*//*Label 462*/ GIMT_Encode4(26653), GIMT_Encode4(0),
8521
0
    /*GILLT_v8s1*//*Label 463*/ GIMT_Encode4(26793),
8522
0
    /*GILLT_v8s8*//*Label 464*/ GIMT_Encode4(26915),
8523
0
    /*GILLT_v8s16*//*Label 465*/ GIMT_Encode4(26977), GIMT_Encode4(0),
8524
0
    /*GILLT_v16s1*//*Label 466*/ GIMT_Encode4(27117),
8525
0
    /*GILLT_v16s8*//*Label 467*/ GIMT_Encode4(27239),
8526
    // Label 455: @25584
8527
0
    GIM_Try, /*On fail goto*//*Label 469*/ GIMT_Encode4(26082),
8528
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
8529
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
8530
0
      GIM_Try, /*On fail goto*//*Label 470*/ GIMT_Encode4(25659), // Rule ID 5606 //
8531
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
8532
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8533
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, uint8_t(-1),
8534
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8535
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8536
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
8537
        // MIs[1] Operand 1
8538
        // No operand predicates
8539
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
8540
        // (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
8541
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2MVNi),
8542
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
8543
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
8544
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8545
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8546
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8547
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8548
0
        GIR_EraseFromParent, /*InsnID*/0,
8549
        // GIR_Coverage, 5606,
8550
0
        GIR_Done,
8551
      // Label 470: @25659
8552
0
      GIM_Try, /*On fail goto*//*Label 471*/ GIMT_Encode4(25721), // Rule ID 507 //
8553
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
8554
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8555
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8556
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8557
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
8558
        // MIs[1] Operand 1
8559
        // No operand predicates
8560
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
8561
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
8562
        // (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })  =>  (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
8563
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2MVNi),
8564
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
8565
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
8566
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8567
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8568
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8569
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8570
0
        GIR_EraseFromParent, /*InsnID*/0,
8571
        // GIR_Coverage, 507,
8572
0
        GIR_Done,
8573
      // Label 471: @25721
8574
0
      GIM_Try, /*On fail goto*//*Label 472*/ GIMT_Encode4(25775), // Rule ID 508 //
8575
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
8576
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8577
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8578
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
8579
        // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })  =>  (t2MVNr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
8580
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2MVNr),
8581
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
8582
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
8583
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8584
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8585
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8586
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8587
0
        GIR_EraseFromParent, /*InsnID*/0,
8588
        // GIR_Coverage, 508,
8589
0
        GIR_Done,
8590
      // Label 472: @25775
8591
0
      GIM_Try, /*On fail goto*//*Label 473*/ GIMT_Encode4(25829), // Rule ID 165 //
8592
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
8593
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8594
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8595
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
8596
        // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })  =>  (MVNr:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
8597
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVNr),
8598
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
8599
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
8600
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8601
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8602
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8603
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8604
0
        GIR_EraseFromParent, /*InsnID*/0,
8605
        // GIR_Coverage, 165,
8606
0
        GIR_Done,
8607
      // Label 473: @25829
8608
0
      GIM_Try, /*On fail goto*//*Label 474*/ GIMT_Encode4(25896), // Rule ID 155 //
8609
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
8610
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8611
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8612
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8613
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8614
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
8615
        // MIs[1] Operand 1
8616
        // No operand predicates
8617
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
8618
        // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (EORri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8619
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::EORri),
8620
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
8621
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
8622
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
8623
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8624
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8625
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8626
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8627
0
        GIR_EraseFromParent, /*InsnID*/0,
8628
        // GIR_Coverage, 155,
8629
0
        GIR_Done,
8630
      // Label 474: @25896
8631
0
      GIM_Try, /*On fail goto*//*Label 475*/ GIMT_Encode4(25963), // Rule ID 495 //
8632
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
8633
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8634
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8635
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8636
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8637
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
8638
        // MIs[1] Operand 1
8639
        // No operand predicates
8640
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
8641
        // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2EORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8642
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2EORri),
8643
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
8644
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
8645
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
8646
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8647
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8648
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8649
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8650
0
        GIR_EraseFromParent, /*InsnID*/0,
8651
        // GIR_Coverage, 495,
8652
0
        GIR_Done,
8653
      // Label 475: @25963
8654
0
      GIM_Try, /*On fail goto*//*Label 476*/ GIMT_Encode4(26022), // Rule ID 156 //
8655
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
8656
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8657
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8658
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8659
        // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (EORrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
8660
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::EORrr),
8661
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
8662
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
8663
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
8664
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8665
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8666
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8667
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8668
0
        GIR_EraseFromParent, /*InsnID*/0,
8669
        // GIR_Coverage, 156,
8670
0
        GIR_Done,
8671
      // Label 476: @26022
8672
0
      GIM_Try, /*On fail goto*//*Label 477*/ GIMT_Encode4(26081), // Rule ID 496 //
8673
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
8674
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8675
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8676
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8677
        // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2EORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
8678
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
8679
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
8680
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
8681
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
8682
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8683
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8684
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8685
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8686
0
        GIR_EraseFromParent, /*InsnID*/0,
8687
        // GIR_Coverage, 496,
8688
0
        GIR_Done,
8689
      // Label 477: @26081
8690
0
      GIM_Reject,
8691
    // Label 469: @26082
8692
0
    GIM_Reject,
8693
    // Label 456: @26083
8694
0
    GIM_Try, /*On fail goto*//*Label 478*/ GIMT_Encode4(26144), // Rule ID 2544 //
8695
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8696
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
8697
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
8698
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8699
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8700
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8701
      // (xor:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)  =>  (VEORd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)
8702
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VEORd),
8703
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
8704
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
8705
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
8706
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8707
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8708
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8709
0
      GIR_EraseFromParent, /*InsnID*/0,
8710
      // GIR_Coverage, 2544,
8711
0
      GIR_Done,
8712
    // Label 478: @26144
8713
0
    GIM_Reject,
8714
    // Label 457: @26145
8715
0
    GIM_Try, /*On fail goto*//*Label 479*/ GIMT_Encode4(26266), // Rule ID 1854 //
8716
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
8717
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s1,
8718
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s1,
8719
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8720
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8721
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8722
      // (xor:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v2i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8723
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8724
0
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8725
0
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8726
0
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8727
0
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8728
0
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8729
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
8730
0
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8731
0
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8732
0
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8733
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
8734
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
8735
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8736
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
8737
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
8738
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
8739
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8740
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8741
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8742
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8743
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
8744
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
8745
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
8746
0
      GIR_EraseFromParent, /*InsnID*/0,
8747
      // GIR_Coverage, 1854,
8748
0
      GIR_Done,
8749
    // Label 479: @26266
8750
0
    GIM_Reject,
8751
    // Label 458: @26267
8752
0
    GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(26328), // Rule ID 1152 //
8753
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8754
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8755
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
8756
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8757
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8758
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8759
      // (xor:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VEORd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
8760
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VEORd),
8761
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
8762
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
8763
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8764
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8765
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8766
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8767
0
      GIR_EraseFromParent, /*InsnID*/0,
8768
      // GIR_Coverage, 1152,
8769
0
      GIR_Done,
8770
    // Label 480: @26328
8771
0
    GIM_Reject,
8772
    // Label 459: @26329
8773
0
    GIM_Try, /*On fail goto*//*Label 481*/ GIMT_Encode4(26468),
8774
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
8775
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8776
0
      GIM_Try, /*On fail goto*//*Label 482*/ GIMT_Encode4(26395), // Rule ID 2547 //
8777
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8778
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
8779
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
8780
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
8781
        // (xor:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)  =>  (VEORq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)
8782
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VEORq),
8783
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
8784
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
8785
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
8786
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8787
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8788
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8789
0
        GIR_EraseFromParent, /*InsnID*/0,
8790
        // GIR_Coverage, 2547,
8791
0
        GIR_Done,
8792
      // Label 482: @26395
8793
0
      GIM_Try, /*On fail goto*//*Label 483*/ GIMT_Encode4(26467), // Rule ID 3504 //
8794
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
8795
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
8796
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
8797
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
8798
        // (xor:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)  =>  (MVE_VEOR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
8799
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
8800
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
8801
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
8802
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR),
8803
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
8804
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
8805
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
8806
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
8807
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8808
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8809
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
8810
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8811
0
        GIR_EraseFromParent, /*InsnID*/0,
8812
        // GIR_Coverage, 3504,
8813
0
        GIR_Done,
8814
      // Label 483: @26467
8815
0
      GIM_Reject,
8816
    // Label 481: @26468
8817
0
    GIM_Reject,
8818
    // Label 460: @26469
8819
0
    GIM_Try, /*On fail goto*//*Label 484*/ GIMT_Encode4(26590), // Rule ID 1855 //
8820
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
8821
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1,
8822
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1,
8823
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8824
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8825
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8826
      // (xor:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v4i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8827
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8828
0
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8829
0
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8830
0
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8831
0
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8832
0
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8833
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
8834
0
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8835
0
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8836
0
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8837
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
8838
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
8839
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8840
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
8841
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
8842
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
8843
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8844
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8845
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8846
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8847
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
8848
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
8849
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
8850
0
      GIR_EraseFromParent, /*InsnID*/0,
8851
      // GIR_Coverage, 1855,
8852
0
      GIR_Done,
8853
    // Label 484: @26590
8854
0
    GIM_Reject,
8855
    // Label 461: @26591
8856
0
    GIM_Try, /*On fail goto*//*Label 485*/ GIMT_Encode4(26652), // Rule ID 2543 //
8857
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8858
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8859
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
8860
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8861
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8862
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8863
      // (xor:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)  =>  (VEORd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)
8864
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VEORd),
8865
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
8866
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
8867
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
8868
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8869
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8870
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8871
0
      GIR_EraseFromParent, /*InsnID*/0,
8872
      // GIR_Coverage, 2543,
8873
0
      GIR_Done,
8874
    // Label 485: @26652
8875
0
    GIM_Reject,
8876
    // Label 462: @26653
8877
0
    GIM_Try, /*On fail goto*//*Label 486*/ GIMT_Encode4(26792),
8878
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
8879
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8880
0
      GIM_Try, /*On fail goto*//*Label 487*/ GIMT_Encode4(26719), // Rule ID 1153 //
8881
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8882
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
8883
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
8884
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
8885
        // (xor:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VEORq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
8886
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VEORq),
8887
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
8888
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
8889
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8890
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8891
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8892
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8893
0
        GIR_EraseFromParent, /*InsnID*/0,
8894
        // GIR_Coverage, 1153,
8895
0
        GIR_Done,
8896
      // Label 487: @26719
8897
0
      GIM_Try, /*On fail goto*//*Label 488*/ GIMT_Encode4(26791), // Rule ID 3500 //
8898
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
8899
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
8900
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
8901
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
8902
        // (xor:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VEOR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
8903
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
8904
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
8905
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
8906
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR),
8907
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
8908
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
8909
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
8910
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
8911
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8912
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8913
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
8914
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8915
0
        GIR_EraseFromParent, /*InsnID*/0,
8916
        // GIR_Coverage, 3500,
8917
0
        GIR_Done,
8918
      // Label 488: @26791
8919
0
      GIM_Reject,
8920
    // Label 486: @26792
8921
0
    GIM_Reject,
8922
    // Label 463: @26793
8923
0
    GIM_Try, /*On fail goto*//*Label 489*/ GIMT_Encode4(26914), // Rule ID 1856 //
8924
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
8925
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1,
8926
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1,
8927
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8928
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8929
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8930
      // (xor:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v8i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8931
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8932
0
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8933
0
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8934
0
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8935
0
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8936
0
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8937
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
8938
0
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8939
0
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8940
0
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8941
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
8942
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
8943
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8944
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
8945
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
8946
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
8947
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8948
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8949
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8950
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8951
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
8952
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
8953
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
8954
0
      GIR_EraseFromParent, /*InsnID*/0,
8955
      // GIR_Coverage, 1856,
8956
0
      GIR_Done,
8957
    // Label 489: @26914
8958
0
    GIM_Reject,
8959
    // Label 464: @26915
8960
0
    GIM_Try, /*On fail goto*//*Label 490*/ GIMT_Encode4(26976), // Rule ID 2542 //
8961
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8962
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
8963
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
8964
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8965
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8966
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8967
      // (xor:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)  =>  (VEORd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)
8968
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VEORd),
8969
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
8970
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
8971
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
8972
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8973
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8974
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8975
0
      GIR_EraseFromParent, /*InsnID*/0,
8976
      // GIR_Coverage, 2542,
8977
0
      GIR_Done,
8978
    // Label 490: @26976
8979
0
    GIM_Reject,
8980
    // Label 465: @26977
8981
0
    GIM_Try, /*On fail goto*//*Label 491*/ GIMT_Encode4(27116),
8982
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
8983
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8984
0
      GIM_Try, /*On fail goto*//*Label 492*/ GIMT_Encode4(27043), // Rule ID 2546 //
8985
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8986
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
8987
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
8988
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
8989
        // (xor:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)  =>  (VEORq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)
8990
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VEORq),
8991
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
8992
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
8993
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
8994
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8995
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8996
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8997
0
        GIR_EraseFromParent, /*InsnID*/0,
8998
        // GIR_Coverage, 2546,
8999
0
        GIR_Done,
9000
      // Label 492: @27043
9001
0
      GIM_Try, /*On fail goto*//*Label 493*/ GIMT_Encode4(27115), // Rule ID 3496 //
9002
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9003
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9004
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9005
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9006
        // (xor:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VEOR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
9007
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9008
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9009
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
9010
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR),
9011
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
9012
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
9013
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
9014
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9015
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9016
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9017
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9018
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9019
0
        GIR_EraseFromParent, /*InsnID*/0,
9020
        // GIR_Coverage, 3496,
9021
0
        GIR_Done,
9022
      // Label 493: @27115
9023
0
      GIM_Reject,
9024
    // Label 491: @27116
9025
0
    GIM_Reject,
9026
    // Label 466: @27117
9027
0
    GIM_Try, /*On fail goto*//*Label 494*/ GIMT_Encode4(27238), // Rule ID 1857 //
9028
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9029
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1,
9030
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1,
9031
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9032
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9033
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9034
      // (xor:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v16i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9035
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9036
0
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9037
0
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9038
0
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9039
0
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
9040
0
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9041
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
9042
0
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9043
0
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
9044
0
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9045
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
9046
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
9047
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
9048
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9049
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9050
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9051
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9052
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9053
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9054
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9055
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
9056
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9057
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9058
0
      GIR_EraseFromParent, /*InsnID*/0,
9059
      // GIR_Coverage, 1857,
9060
0
      GIR_Done,
9061
    // Label 494: @27238
9062
0
    GIM_Reject,
9063
    // Label 467: @27239
9064
0
    GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(27378),
9065
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
9066
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
9067
0
      GIM_Try, /*On fail goto*//*Label 496*/ GIMT_Encode4(27305), // Rule ID 2545 //
9068
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9069
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9070
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9071
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9072
        // (xor:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)  =>  (VEORq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)
9073
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VEORq),
9074
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
9075
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
9076
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
9077
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9078
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9079
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9080
0
        GIR_EraseFromParent, /*InsnID*/0,
9081
        // GIR_Coverage, 2545,
9082
0
        GIR_Done,
9083
      // Label 496: @27305
9084
0
      GIM_Try, /*On fail goto*//*Label 497*/ GIMT_Encode4(27377), // Rule ID 3492 //
9085
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9086
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9087
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9088
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9089
        // (xor:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VEOR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
9090
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9091
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9092
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
9093
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR),
9094
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
9095
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
9096
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
9097
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9098
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9099
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9100
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9101
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9102
0
        GIR_EraseFromParent, /*InsnID*/0,
9103
        // GIR_Coverage, 3492,
9104
0
        GIR_Done,
9105
      // Label 497: @27377
9106
0
      GIM_Reject,
9107
    // Label 495: @27378
9108
0
    GIM_Reject,
9109
    // Label 468: @27379
9110
0
    GIM_Reject,
9111
    // Label 8: @27380
9112
0
    GIM_Try, /*On fail goto*//*Label 498*/ GIMT_Encode4(27888),
9113
0
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
9114
0
      GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(16), /*)*//*default:*//*Label 503*/ GIMT_Encode4(27887),
9115
0
      /*GILLT_v2s64*//*Label 499*/ GIMT_Encode4(27443), GIMT_Encode4(0), GIMT_Encode4(0),
9116
0
      /*GILLT_v4s32*//*Label 500*/ GIMT_Encode4(27515), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
9117
0
      /*GILLT_v8s16*//*Label 501*/ GIMT_Encode4(27641), GIMT_Encode4(0), GIMT_Encode4(0),
9118
0
      /*GILLT_v16s8*//*Label 502*/ GIMT_Encode4(27815),
9119
      // Label 499: @27443
9120
0
      GIM_Try, /*On fail goto*//*Label 504*/ GIMT_Encode4(27514), // Rule ID 3125 //
9121
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9122
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9123
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
9124
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9125
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9126
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9127
        // (concat_vectors:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Dn, DPR:{ *:[v1i64] }:$Dm)  =>  (REG_SEQUENCE:{ *:[v2i64] } QPR:{ *:[i32] }, DPR:{ *:[v1i64] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v1i64] }:$Dm, dsub_1:{ *:[i32] })
9128
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
9129
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
9130
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
9131
0
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
9132
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
9133
0
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
9134
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
9135
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
9136
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
9137
0
        GIR_EraseFromParent, /*InsnID*/0,
9138
        // GIR_Coverage, 3125,
9139
0
        GIR_Done,
9140
      // Label 504: @27514
9141
0
      GIM_Reject,
9142
      // Label 500: @27515
9143
0
      GIM_Try, /*On fail goto*//*Label 505*/ GIMT_Encode4(27640),
9144
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9145
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
9146
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9147
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9148
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9149
0
        GIM_Try, /*On fail goto*//*Label 506*/ GIMT_Encode4(27591), // Rule ID 3126 //
9150
0
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9151
          // (concat_vectors:{ *:[v4i32] } DPR:{ *:[v2i32] }:$Dn, DPR:{ *:[v2i32] }:$Dm)  =>  (REG_SEQUENCE:{ *:[v4i32] } QPR:{ *:[i32] }, DPR:{ *:[v2i32] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v2i32] }:$Dm, dsub_1:{ *:[i32] })
9152
0
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
9153
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
9154
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
9155
0
          GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
9156
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
9157
0
          GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
9158
0
          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
9159
0
          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
9160
0
          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
9161
0
          GIR_EraseFromParent, /*InsnID*/0,
9162
          // GIR_Coverage, 3126,
9163
0
          GIR_Done,
9164
        // Label 506: @27591
9165
0
        GIM_Try, /*On fail goto*//*Label 507*/ GIMT_Encode4(27639), // Rule ID 3129 //
9166
0
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9167
          // (concat_vectors:{ *:[v4f32] } DPR:{ *:[v2f32] }:$Dn, DPR:{ *:[v2f32] }:$Dm)  =>  (REG_SEQUENCE:{ *:[v4f32] } QPR:{ *:[i32] }, DPR:{ *:[v2f32] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v2f32] }:$Dm, dsub_1:{ *:[i32] })
9168
0
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
9169
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
9170
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
9171
0
          GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
9172
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
9173
0
          GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
9174
0
          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
9175
0
          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
9176
0
          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
9177
0
          GIR_EraseFromParent, /*InsnID*/0,
9178
          // GIR_Coverage, 3129,
9179
0
          GIR_Done,
9180
        // Label 507: @27639
9181
0
        GIM_Reject,
9182
      // Label 505: @27640
9183
0
      GIM_Reject,
9184
      // Label 501: @27641
9185
0
      GIM_Try, /*On fail goto*//*Label 508*/ GIMT_Encode4(27814),
9186
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9187
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
9188
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9189
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9190
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9191
0
        GIM_Try, /*On fail goto*//*Label 509*/ GIMT_Encode4(27717), // Rule ID 3127 //
9192
0
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9193
          // (concat_vectors:{ *:[v8i16] } DPR:{ *:[v4i16] }:$Dn, DPR:{ *:[v4i16] }:$Dm)  =>  (REG_SEQUENCE:{ *:[v8i16] } QPR:{ *:[i32] }, DPR:{ *:[v4i16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4i16] }:$Dm, dsub_1:{ *:[i32] })
9194
0
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
9195
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
9196
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
9197
0
          GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
9198
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
9199
0
          GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
9200
0
          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
9201
0
          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
9202
0
          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
9203
0
          GIR_EraseFromParent, /*InsnID*/0,
9204
          // GIR_Coverage, 3127,
9205
0
          GIR_Done,
9206
        // Label 509: @27717
9207
0
        GIM_Try, /*On fail goto*//*Label 510*/ GIMT_Encode4(27765), // Rule ID 3130 //
9208
0
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9209
          // (concat_vectors:{ *:[v8f16] } DPR:{ *:[v4f16] }:$Dn, DPR:{ *:[v4f16] }:$Dm)  =>  (REG_SEQUENCE:{ *:[v8f16] } QPR:{ *:[i32] }, DPR:{ *:[v4f16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4f16] }:$Dm, dsub_1:{ *:[i32] })
9210
0
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
9211
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
9212
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
9213
0
          GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
9214
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
9215
0
          GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
9216
0
          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
9217
0
          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
9218
0
          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
9219
0
          GIR_EraseFromParent, /*InsnID*/0,
9220
          // GIR_Coverage, 3130,
9221
0
          GIR_Done,
9222
        // Label 510: @27765
9223
0
        GIM_Try, /*On fail goto*//*Label 511*/ GIMT_Encode4(27813), // Rule ID 3131 //
9224
0
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9225
          // (concat_vectors:{ *:[v8bf16] } DPR:{ *:[v4bf16] }:$Dn, DPR:{ *:[v4bf16] }:$Dm)  =>  (REG_SEQUENCE:{ *:[v8bf16] } QPR:{ *:[i32] }, DPR:{ *:[v4bf16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4bf16] }:$Dm, dsub_1:{ *:[i32] })
9226
0
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
9227
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
9228
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
9229
0
          GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
9230
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
9231
0
          GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
9232
0
          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
9233
0
          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
9234
0
          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
9235
0
          GIR_EraseFromParent, /*InsnID*/0,
9236
          // GIR_Coverage, 3131,
9237
0
          GIR_Done,
9238
        // Label 511: @27813
9239
0
        GIM_Reject,
9240
      // Label 508: @27814
9241
0
      GIM_Reject,
9242
      // Label 502: @27815
9243
0
      GIM_Try, /*On fail goto*//*Label 512*/ GIMT_Encode4(27886), // Rule ID 3128 //
9244
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9245
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9246
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
9247
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9248
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9249
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9250
        // (concat_vectors:{ *:[v16i8] } DPR:{ *:[v8i8] }:$Dn, DPR:{ *:[v8i8] }:$Dm)  =>  (REG_SEQUENCE:{ *:[v16i8] } QPR:{ *:[i32] }, DPR:{ *:[v8i8] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v8i8] }:$Dm, dsub_1:{ *:[i32] })
9251
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
9252
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
9253
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
9254
0
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
9255
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
9256
0
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
9257
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
9258
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
9259
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
9260
0
        GIR_EraseFromParent, /*InsnID*/0,
9261
        // GIR_Coverage, 3128,
9262
0
        GIR_Done,
9263
      // Label 512: @27886
9264
0
      GIM_Reject,
9265
      // Label 503: @27887
9266
0
      GIM_Reject,
9267
    // Label 498: @27888
9268
0
    GIM_Reject,
9269
    // Label 9: @27889
9270
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 522*/ GIMT_Encode4(41272),
9271
0
    /*GILLT_s32*//*Label 513*/ GIMT_Encode4(27960),
9272
0
    /*GILLT_s64*//*Label 514*/ GIMT_Encode4(28136), GIMT_Encode4(0),
9273
0
    /*GILLT_v2s32*//*Label 515*/ GIMT_Encode4(29301),
9274
0
    /*GILLT_v2s64*//*Label 516*/ GIMT_Encode4(30466), GIMT_Encode4(0),
9275
0
    /*GILLT_v4s16*//*Label 517*/ GIMT_Encode4(32805),
9276
0
    /*GILLT_v4s32*//*Label 518*/ GIMT_Encode4(34324), GIMT_Encode4(0), GIMT_Encode4(0),
9277
0
    /*GILLT_v8s8*//*Label 519*/ GIMT_Encode4(36663),
9278
0
    /*GILLT_v8s16*//*Label 520*/ GIMT_Encode4(37294), GIMT_Encode4(0), GIMT_Encode4(0),
9279
0
    /*GILLT_v16s8*//*Label 521*/ GIMT_Encode4(39987),
9280
    // Label 513: @27960
9281
0
    GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(28135),
9282
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
9283
0
      GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(28013), // Rule ID 706 //
9284
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs),
9285
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9286
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
9287
        // (bitconvert:{ *:[i32] } SPR:{ *:[f32] }:$Sn)  =>  (VMOVRS:{ *:[i32] } SPR:{ *:[f32] }:$Sn)
9288
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMOVRS),
9289
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rt]
9290
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
9291
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9292
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9293
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9294
0
        GIR_EraseFromParent, /*InsnID*/0,
9295
        // GIR_Coverage, 706,
9296
0
        GIR_Done,
9297
      // Label 524: @28013
9298
0
      GIM_Try, /*On fail goto*//*Label 525*/ GIMT_Encode4(28057), // Rule ID 707 //
9299
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs_UseVMOVSR),
9300
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
9301
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9302
        // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$Rt)  =>  (VMOVSR:{ *:[f32] } GPR:{ *:[i32] }:$Rt)
9303
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMOVSR),
9304
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sn]
9305
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rt
9306
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9307
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9308
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9309
0
        GIR_EraseFromParent, /*InsnID*/0,
9310
        // GIR_Coverage, 707,
9311
0
        GIR_Done,
9312
      // Label 525: @28057
9313
0
      GIM_Try, /*On fail goto*//*Label 526*/ GIMT_Encode4(28134), // Rule ID 2745 //
9314
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseVMOVSR_HasNEON),
9315
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9316
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9317
        // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$a)  =>  (EXTRACT_SUBREG:{ *:[f32] } (VMOVDRR:{ *:[f64] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$a), ssub_0:{ *:[i32] })
9318
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
9319
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VMOVDRR),
9320
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
9321
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
9322
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
9323
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9324
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9325
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9326
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9327
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
9328
0
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
9329
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
9330
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
9331
0
        GIR_EraseFromParent, /*InsnID*/0,
9332
        // GIR_Coverage, 2745,
9333
0
        GIR_Done,
9334
      // Label 526: @28134
9335
0
      GIM_Reject,
9336
    // Label 523: @28135
9337
0
    GIM_Reject,
9338
    // Label 514: @28136
9339
0
    GIM_Try, /*On fail goto*//*Label 527*/ GIMT_Encode4(28178), // Rule ID 2747 //
9340
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9341
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9342
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9343
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9344
      // (bitconvert:{ *:[f64] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[f64] }:$src
9345
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9346
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9347
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9348
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9349
0
      GIR_EraseFromParent, /*InsnID*/0,
9350
      // GIR_Coverage, 2747,
9351
0
      GIR_Done,
9352
    // Label 527: @28178
9353
0
    GIM_Try, /*On fail goto*//*Label 528*/ GIMT_Encode4(28220), // Rule ID 2748 //
9354
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9355
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9356
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9357
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9358
      // (bitconvert:{ *:[v1i64] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v1i64] }:$src
9359
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9360
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9361
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9362
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9363
0
      GIR_EraseFromParent, /*InsnID*/0,
9364
      // GIR_Coverage, 2748,
9365
0
      GIR_Done,
9366
    // Label 528: @28220
9367
0
    GIM_Try, /*On fail goto*//*Label 529*/ GIMT_Encode4(28262), // Rule ID 2763 //
9368
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9369
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9370
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9371
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9372
      // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[f64] }:$src
9373
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9374
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9375
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9376
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9377
0
      GIR_EraseFromParent, /*InsnID*/0,
9378
      // GIR_Coverage, 2763,
9379
0
      GIR_Done,
9380
    // Label 529: @28262
9381
0
    GIM_Try, /*On fail goto*//*Label 530*/ GIMT_Encode4(28304), // Rule ID 2764 //
9382
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9383
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9384
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9385
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9386
      // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[f64] }:$src
9387
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9388
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9389
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9390
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9391
0
      GIR_EraseFromParent, /*InsnID*/0,
9392
      // GIR_Coverage, 2764,
9393
0
      GIR_Done,
9394
    // Label 530: @28304
9395
0
    GIM_Try, /*On fail goto*//*Label 531*/ GIMT_Encode4(28346), // Rule ID 2765 //
9396
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9397
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9398
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9399
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9400
      // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src)  =>  DPR:{ *:[f64] }:$src
9401
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9402
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9403
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9404
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9405
0
      GIR_EraseFromParent, /*InsnID*/0,
9406
      // GIR_Coverage, 2765,
9407
0
      GIR_Done,
9408
    // Label 531: @28346
9409
0
    GIM_Try, /*On fail goto*//*Label 532*/ GIMT_Encode4(28388), // Rule ID 2766 //
9410
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9411
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9412
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9413
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9414
      // (bitconvert:{ *:[f64] } DPR:{ *:[v4bf16] }:$src)  =>  DPR:{ *:[f64] }:$src
9415
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9416
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9417
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9418
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9419
0
      GIR_EraseFromParent, /*InsnID*/0,
9420
      // GIR_Coverage, 2766,
9421
0
      GIR_Done,
9422
    // Label 532: @28388
9423
0
    GIM_Try, /*On fail goto*//*Label 533*/ GIMT_Encode4(28430), // Rule ID 2767 //
9424
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9425
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9426
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9427
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9428
      // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[f64] }:$src
9429
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9430
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9431
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9432
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9433
0
      GIR_EraseFromParent, /*InsnID*/0,
9434
      // GIR_Coverage, 2767,
9435
0
      GIR_Done,
9436
    // Label 533: @28430
9437
0
    GIM_Try, /*On fail goto*//*Label 534*/ GIMT_Encode4(28472), // Rule ID 2768 //
9438
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9439
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9440
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9441
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9442
      // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[f64] }:$src
9443
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9444
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9445
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9446
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9447
0
      GIR_EraseFromParent, /*InsnID*/0,
9448
      // GIR_Coverage, 2768,
9449
0
      GIR_Done,
9450
    // Label 534: @28472
9451
0
    GIM_Try, /*On fail goto*//*Label 535*/ GIMT_Encode4(28514), // Rule ID 2769 //
9452
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9453
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9454
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9455
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9456
      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[v1i64] }:$src
9457
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9458
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9459
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9460
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9461
0
      GIR_EraseFromParent, /*InsnID*/0,
9462
      // GIR_Coverage, 2769,
9463
0
      GIR_Done,
9464
    // Label 535: @28514
9465
0
    GIM_Try, /*On fail goto*//*Label 536*/ GIMT_Encode4(28556), // Rule ID 2770 //
9466
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9467
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9468
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9469
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9470
      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[v1i64] }:$src
9471
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9472
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9473
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9474
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9475
0
      GIR_EraseFromParent, /*InsnID*/0,
9476
      // GIR_Coverage, 2770,
9477
0
      GIR_Done,
9478
    // Label 536: @28556
9479
0
    GIM_Try, /*On fail goto*//*Label 537*/ GIMT_Encode4(28598), // Rule ID 2771 //
9480
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9481
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9482
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9483
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9484
      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src)  =>  DPR:{ *:[v1i64] }:$src
9485
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9486
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9487
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9488
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9489
0
      GIR_EraseFromParent, /*InsnID*/0,
9490
      // GIR_Coverage, 2771,
9491
0
      GIR_Done,
9492
    // Label 537: @28598
9493
0
    GIM_Try, /*On fail goto*//*Label 538*/ GIMT_Encode4(28640), // Rule ID 2772 //
9494
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9495
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9496
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9497
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9498
      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4bf16] }:$src)  =>  DPR:{ *:[v1i64] }:$src
9499
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9500
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9501
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9502
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9503
0
      GIR_EraseFromParent, /*InsnID*/0,
9504
      // GIR_Coverage, 2772,
9505
0
      GIR_Done,
9506
    // Label 538: @28640
9507
0
    GIM_Try, /*On fail goto*//*Label 539*/ GIMT_Encode4(28682), // Rule ID 2773 //
9508
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9509
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9510
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9511
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9512
      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[v1i64] }:$src
9513
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9514
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9515
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9516
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9517
0
      GIR_EraseFromParent, /*InsnID*/0,
9518
      // GIR_Coverage, 2773,
9519
0
      GIR_Done,
9520
    // Label 539: @28682
9521
0
    GIM_Try, /*On fail goto*//*Label 540*/ GIMT_Encode4(28724), // Rule ID 2774 //
9522
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9523
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9524
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9525
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9526
      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[v1i64] }:$src
9527
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9528
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9529
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9530
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9531
0
      GIR_EraseFromParent, /*InsnID*/0,
9532
      // GIR_Coverage, 2774,
9533
0
      GIR_Done,
9534
    // Label 540: @28724
9535
0
    GIM_Try, /*On fail goto*//*Label 541*/ GIMT_Encode4(28772), // Rule ID 2855 //
9536
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
9537
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9538
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9539
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9540
      // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src)  =>  (VREV64d32:{ *:[f64] } DPR:{ *:[v2f32] }:$src)
9541
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
9542
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
9543
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9544
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9545
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9546
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9547
0
      GIR_EraseFromParent, /*InsnID*/0,
9548
      // GIR_Coverage, 2855,
9549
0
      GIR_Done,
9550
    // Label 541: @28772
9551
0
    GIM_Try, /*On fail goto*//*Label 542*/ GIMT_Encode4(28820), // Rule ID 2856 //
9552
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
9553
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9554
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9555
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9556
      // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src)  =>  (VREV64d32:{ *:[f64] } DPR:{ *:[v2i32] }:$src)
9557
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
9558
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
9559
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9560
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9561
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9562
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9563
0
      GIR_EraseFromParent, /*InsnID*/0,
9564
      // GIR_Coverage, 2856,
9565
0
      GIR_Done,
9566
    // Label 542: @28820
9567
0
    GIM_Try, /*On fail goto*//*Label 543*/ GIMT_Encode4(28868), // Rule ID 2857 //
9568
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
9569
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9570
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9571
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9572
      // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src)  =>  (VREV64d16:{ *:[f64] } DPR:{ *:[v4f16] }:$src)
9573
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
9574
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
9575
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9576
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9577
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9578
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9579
0
      GIR_EraseFromParent, /*InsnID*/0,
9580
      // GIR_Coverage, 2857,
9581
0
      GIR_Done,
9582
    // Label 543: @28868
9583
0
    GIM_Try, /*On fail goto*//*Label 544*/ GIMT_Encode4(28916), // Rule ID 2858 //
9584
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
9585
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9586
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9587
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9588
      // (bitconvert:{ *:[f64] } DPR:{ *:[v4bf16] }:$src)  =>  (VREV64d16:{ *:[f64] } DPR:{ *:[v4bf16] }:$src)
9589
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
9590
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
9591
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9592
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9593
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9594
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9595
0
      GIR_EraseFromParent, /*InsnID*/0,
9596
      // GIR_Coverage, 2858,
9597
0
      GIR_Done,
9598
    // Label 544: @28916
9599
0
    GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(28964), // Rule ID 2859 //
9600
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
9601
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9602
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9603
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9604
      // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src)  =>  (VREV64d16:{ *:[f64] } DPR:{ *:[v4i16] }:$src)
9605
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
9606
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
9607
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9608
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9609
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9610
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9611
0
      GIR_EraseFromParent, /*InsnID*/0,
9612
      // GIR_Coverage, 2859,
9613
0
      GIR_Done,
9614
    // Label 545: @28964
9615
0
    GIM_Try, /*On fail goto*//*Label 546*/ GIMT_Encode4(29012), // Rule ID 2860 //
9616
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
9617
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9618
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9619
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9620
      // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src)  =>  (VREV64d8:{ *:[f64] } DPR:{ *:[v8i8] }:$src)
9621
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d8),
9622
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
9623
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9624
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9625
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9626
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9627
0
      GIR_EraseFromParent, /*InsnID*/0,
9628
      // GIR_Coverage, 2860,
9629
0
      GIR_Done,
9630
    // Label 546: @29012
9631
0
    GIM_Try, /*On fail goto*//*Label 547*/ GIMT_Encode4(29060), // Rule ID 2861 //
9632
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
9633
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9634
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9635
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9636
      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src)  =>  (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src)
9637
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
9638
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
9639
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9640
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9641
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9642
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9643
0
      GIR_EraseFromParent, /*InsnID*/0,
9644
      // GIR_Coverage, 2861,
9645
0
      GIR_Done,
9646
    // Label 547: @29060
9647
0
    GIM_Try, /*On fail goto*//*Label 548*/ GIMT_Encode4(29108), // Rule ID 2862 //
9648
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
9649
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9650
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9651
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9652
      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src)  =>  (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src)
9653
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
9654
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
9655
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9656
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9657
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9658
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9659
0
      GIR_EraseFromParent, /*InsnID*/0,
9660
      // GIR_Coverage, 2862,
9661
0
      GIR_Done,
9662
    // Label 548: @29108
9663
0
    GIM_Try, /*On fail goto*//*Label 549*/ GIMT_Encode4(29156), // Rule ID 2863 //
9664
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
9665
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9666
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9667
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9668
      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src)  =>  (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src)
9669
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
9670
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
9671
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9672
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9673
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9674
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9675
0
      GIR_EraseFromParent, /*InsnID*/0,
9676
      // GIR_Coverage, 2863,
9677
0
      GIR_Done,
9678
    // Label 549: @29156
9679
0
    GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(29204), // Rule ID 2864 //
9680
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
9681
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9682
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9683
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9684
      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4bf16] }:$src)  =>  (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4bf16] }:$src)
9685
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
9686
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
9687
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9688
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9689
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9690
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9691
0
      GIR_EraseFromParent, /*InsnID*/0,
9692
      // GIR_Coverage, 2864,
9693
0
      GIR_Done,
9694
    // Label 550: @29204
9695
0
    GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(29252), // Rule ID 2865 //
9696
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
9697
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9698
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9699
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9700
      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src)  =>  (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src)
9701
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
9702
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
9703
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9704
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9705
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9706
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9707
0
      GIR_EraseFromParent, /*InsnID*/0,
9708
      // GIR_Coverage, 2865,
9709
0
      GIR_Done,
9710
    // Label 551: @29252
9711
0
    GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(29300), // Rule ID 2866 //
9712
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
9713
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9714
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9715
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9716
      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src)  =>  (VREV64d8:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src)
9717
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d8),
9718
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
9719
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9720
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9721
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9722
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9723
0
      GIR_EraseFromParent, /*InsnID*/0,
9724
      // GIR_Coverage, 2866,
9725
0
      GIR_Done,
9726
    // Label 552: @29300
9727
0
    GIM_Reject,
9728
    // Label 515: @29301
9729
0
    GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(29343), // Rule ID 2749 //
9730
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9731
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9732
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9733
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9734
      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[v2f32] }:$src
9735
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9736
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9737
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9738
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9739
0
      GIR_EraseFromParent, /*InsnID*/0,
9740
      // GIR_Coverage, 2749,
9741
0
      GIR_Done,
9742
    // Label 553: @29343
9743
0
    GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(29385), // Rule ID 2750 //
9744
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9745
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9746
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9747
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9748
      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[v2i32] }:$src
9749
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9750
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9751
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9752
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9753
0
      GIR_EraseFromParent, /*InsnID*/0,
9754
      // GIR_Coverage, 2750,
9755
0
      GIR_Done,
9756
    // Label 554: @29385
9757
0
    GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(29427), // Rule ID 2775 //
9758
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9759
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9760
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9761
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9762
      // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v2f32] }:$src
9763
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9764
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9765
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9766
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9767
0
      GIR_EraseFromParent, /*InsnID*/0,
9768
      // GIR_Coverage, 2775,
9769
0
      GIR_Done,
9770
    // Label 555: @29427
9771
0
    GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(29469), // Rule ID 2776 //
9772
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9773
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9774
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9775
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9776
      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[v2f32] }:$src
9777
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9778
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9779
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9780
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9781
0
      GIR_EraseFromParent, /*InsnID*/0,
9782
      // GIR_Coverage, 2776,
9783
0
      GIR_Done,
9784
    // Label 556: @29469
9785
0
    GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(29511), // Rule ID 2777 //
9786
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9787
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9788
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9789
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9790
      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src)  =>  DPR:{ *:[v2f32] }:$src
9791
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9792
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9793
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9794
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9795
0
      GIR_EraseFromParent, /*InsnID*/0,
9796
      // GIR_Coverage, 2777,
9797
0
      GIR_Done,
9798
    // Label 557: @29511
9799
0
    GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(29553), // Rule ID 2778 //
9800
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9801
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9802
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9803
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9804
      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4bf16] }:$src)  =>  DPR:{ *:[v2f32] }:$src
9805
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9806
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9807
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9808
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9809
0
      GIR_EraseFromParent, /*InsnID*/0,
9810
      // GIR_Coverage, 2778,
9811
0
      GIR_Done,
9812
    // Label 558: @29553
9813
0
    GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(29595), // Rule ID 2779 //
9814
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9815
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9816
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9817
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9818
      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[v2f32] }:$src
9819
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9820
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9821
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9822
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9823
0
      GIR_EraseFromParent, /*InsnID*/0,
9824
      // GIR_Coverage, 2779,
9825
0
      GIR_Done,
9826
    // Label 559: @29595
9827
0
    GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(29637), // Rule ID 2780 //
9828
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9829
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9830
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9831
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9832
      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[v2f32] }:$src
9833
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9834
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9835
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9836
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9837
0
      GIR_EraseFromParent, /*InsnID*/0,
9838
      // GIR_Coverage, 2780,
9839
0
      GIR_Done,
9840
    // Label 560: @29637
9841
0
    GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(29679), // Rule ID 2781 //
9842
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9843
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9844
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9845
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9846
      // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v2i32] }:$src
9847
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9848
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9849
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9850
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9851
0
      GIR_EraseFromParent, /*InsnID*/0,
9852
      // GIR_Coverage, 2781,
9853
0
      GIR_Done,
9854
    // Label 561: @29679
9855
0
    GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(29721), // Rule ID 2782 //
9856
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9857
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9858
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9859
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9860
      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[v2i32] }:$src
9861
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9862
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9863
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9864
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9865
0
      GIR_EraseFromParent, /*InsnID*/0,
9866
      // GIR_Coverage, 2782,
9867
0
      GIR_Done,
9868
    // Label 562: @29721
9869
0
    GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(29763), // Rule ID 2783 //
9870
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9871
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9872
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9873
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9874
      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src)  =>  DPR:{ *:[v2i32] }:$src
9875
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9876
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9877
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9878
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9879
0
      GIR_EraseFromParent, /*InsnID*/0,
9880
      // GIR_Coverage, 2783,
9881
0
      GIR_Done,
9882
    // Label 563: @29763
9883
0
    GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(29805), // Rule ID 2784 //
9884
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9885
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9886
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9887
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9888
      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4bf16] }:$src)  =>  DPR:{ *:[v2i32] }:$src
9889
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9890
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9891
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9892
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9893
0
      GIR_EraseFromParent, /*InsnID*/0,
9894
      // GIR_Coverage, 2784,
9895
0
      GIR_Done,
9896
    // Label 564: @29805
9897
0
    GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(29847), // Rule ID 2785 //
9898
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9899
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9900
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9901
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9902
      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[v2i32] }:$src
9903
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9904
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9905
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9906
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9907
0
      GIR_EraseFromParent, /*InsnID*/0,
9908
      // GIR_Coverage, 2785,
9909
0
      GIR_Done,
9910
    // Label 565: @29847
9911
0
    GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(29889), // Rule ID 2786 //
9912
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
9913
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9914
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9915
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9916
      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[v2i32] }:$src
9917
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9918
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9919
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9920
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
9921
0
      GIR_EraseFromParent, /*InsnID*/0,
9922
      // GIR_Coverage, 2786,
9923
0
      GIR_Done,
9924
    // Label 566: @29889
9925
0
    GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(29937), // Rule ID 2867 //
9926
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
9927
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9928
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9929
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9930
      // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src)  =>  (VREV64d32:{ *:[v2f32] } DPR:{ *:[f64] }:$src)
9931
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
9932
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
9933
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9934
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9935
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9936
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9937
0
      GIR_EraseFromParent, /*InsnID*/0,
9938
      // GIR_Coverage, 2867,
9939
0
      GIR_Done,
9940
    // Label 567: @29937
9941
0
    GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(29985), // Rule ID 2868 //
9942
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
9943
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9944
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9945
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9946
      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src)  =>  (VREV64d32:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src)
9947
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
9948
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
9949
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9950
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9951
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9952
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9953
0
      GIR_EraseFromParent, /*InsnID*/0,
9954
      // GIR_Coverage, 2868,
9955
0
      GIR_Done,
9956
    // Label 568: @29985
9957
0
    GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(30033), // Rule ID 2869 //
9958
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
9959
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9960
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9961
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9962
      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src)  =>  (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src)
9963
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
9964
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
9965
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9966
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9967
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9968
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9969
0
      GIR_EraseFromParent, /*InsnID*/0,
9970
      // GIR_Coverage, 2869,
9971
0
      GIR_Done,
9972
    // Label 569: @30033
9973
0
    GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(30081), // Rule ID 2870 //
9974
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
9975
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9976
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9977
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9978
      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4bf16] }:$src)  =>  (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4bf16] }:$src)
9979
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
9980
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
9981
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9982
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9983
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9984
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9985
0
      GIR_EraseFromParent, /*InsnID*/0,
9986
      // GIR_Coverage, 2870,
9987
0
      GIR_Done,
9988
    // Label 570: @30081
9989
0
    GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(30129), // Rule ID 2871 //
9990
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
9991
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9992
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9993
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9994
      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src)  =>  (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src)
9995
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
9996
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
9997
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9998
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9999
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10000
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10001
0
      GIR_EraseFromParent, /*InsnID*/0,
10002
      // GIR_Coverage, 2871,
10003
0
      GIR_Done,
10004
    // Label 571: @30129
10005
0
    GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(30177), // Rule ID 2872 //
10006
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
10007
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
10008
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10009
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10010
      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src)  =>  (VREV32d8:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src)
10011
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32d8),
10012
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
10013
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10014
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10015
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10016
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10017
0
      GIR_EraseFromParent, /*InsnID*/0,
10018
      // GIR_Coverage, 2872,
10019
0
      GIR_Done,
10020
    // Label 572: @30177
10021
0
    GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(30225), // Rule ID 2873 //
10022
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
10023
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10024
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10025
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10026
      // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src)  =>  (VREV64d32:{ *:[v2i32] } DPR:{ *:[f64] }:$src)
10027
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
10028
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
10029
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10030
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10031
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10032
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10033
0
      GIR_EraseFromParent, /*InsnID*/0,
10034
      // GIR_Coverage, 2873,
10035
0
      GIR_Done,
10036
    // Label 573: @30225
10037
0
    GIM_Try, /*On fail goto*//*Label 574*/ GIMT_Encode4(30273), // Rule ID 2874 //
10038
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
10039
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10040
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10041
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10042
      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src)  =>  (VREV64d32:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src)
10043
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
10044
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
10045
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10046
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10047
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10048
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10049
0
      GIR_EraseFromParent, /*InsnID*/0,
10050
      // GIR_Coverage, 2874,
10051
0
      GIR_Done,
10052
    // Label 574: @30273
10053
0
    GIM_Try, /*On fail goto*//*Label 575*/ GIMT_Encode4(30321), // Rule ID 2875 //
10054
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
10055
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10056
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10057
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10058
      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src)  =>  (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src)
10059
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
10060
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
10061
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10062
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10063
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10064
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10065
0
      GIR_EraseFromParent, /*InsnID*/0,
10066
      // GIR_Coverage, 2875,
10067
0
      GIR_Done,
10068
    // Label 575: @30321
10069
0
    GIM_Try, /*On fail goto*//*Label 576*/ GIMT_Encode4(30369), // Rule ID 2876 //
10070
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
10071
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10072
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10073
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10074
      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4bf16] }:$src)  =>  (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4bf16] }:$src)
10075
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
10076
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
10077
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10078
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10079
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10080
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10081
0
      GIR_EraseFromParent, /*InsnID*/0,
10082
      // GIR_Coverage, 2876,
10083
0
      GIR_Done,
10084
    // Label 576: @30369
10085
0
    GIM_Try, /*On fail goto*//*Label 577*/ GIMT_Encode4(30417), // Rule ID 2877 //
10086
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
10087
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10088
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10089
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10090
      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src)  =>  (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src)
10091
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
10092
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
10093
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10094
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10095
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10096
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10097
0
      GIR_EraseFromParent, /*InsnID*/0,
10098
      // GIR_Coverage, 2877,
10099
0
      GIR_Done,
10100
    // Label 577: @30417
10101
0
    GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(30465), // Rule ID 2878 //
10102
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
10103
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
10104
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10105
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10106
      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src)  =>  (VREV32d8:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src)
10107
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32d8),
10108
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
10109
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10110
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10111
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10112
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10113
0
      GIR_EraseFromParent, /*InsnID*/0,
10114
      // GIR_Coverage, 2878,
10115
0
      GIR_Done,
10116
    // Label 578: @30465
10117
0
    GIM_Reject,
10118
    // Label 516: @30466
10119
0
    GIM_Try, /*On fail goto*//*Label 579*/ GIMT_Encode4(30508), // Rule ID 2755 //
10120
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10121
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10122
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10123
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10124
      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v2f64] }:$src
10125
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10126
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10127
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10128
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10129
0
      GIR_EraseFromParent, /*InsnID*/0,
10130
      // GIR_Coverage, 2755,
10131
0
      GIR_Done,
10132
    // Label 579: @30508
10133
0
    GIM_Try, /*On fail goto*//*Label 580*/ GIMT_Encode4(30550), // Rule ID 2756 //
10134
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10135
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10136
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10137
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10138
      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v2i64] }:$src
10139
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10140
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10141
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10142
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10143
0
      GIR_EraseFromParent, /*InsnID*/0,
10144
      // GIR_Coverage, 2756,
10145
0
      GIR_Done,
10146
    // Label 580: @30550
10147
0
    GIM_Try, /*On fail goto*//*Label 581*/ GIMT_Encode4(30592), // Rule ID 2809 //
10148
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
10149
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10150
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10151
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10152
      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v2f64] }:$src
10153
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10154
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10155
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10156
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10157
0
      GIR_EraseFromParent, /*InsnID*/0,
10158
      // GIR_Coverage, 2809,
10159
0
      GIR_Done,
10160
    // Label 581: @30592
10161
0
    GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(30634), // Rule ID 2810 //
10162
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
10163
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10164
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10165
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10166
      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v2f64] }:$src
10167
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10168
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10169
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10170
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10171
0
      GIR_EraseFromParent, /*InsnID*/0,
10172
      // GIR_Coverage, 2810,
10173
0
      GIR_Done,
10174
    // Label 582: @30634
10175
0
    GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(30676), // Rule ID 2811 //
10176
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
10177
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10178
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10179
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10180
      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src)  =>  QPR:{ *:[v2f64] }:$src
10181
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10182
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10183
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10184
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10185
0
      GIR_EraseFromParent, /*InsnID*/0,
10186
      // GIR_Coverage, 2811,
10187
0
      GIR_Done,
10188
    // Label 583: @30676
10189
0
    GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(30718), // Rule ID 2812 //
10190
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
10191
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10192
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10193
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10194
      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8bf16] }:$src)  =>  QPR:{ *:[v2f64] }:$src
10195
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10196
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10197
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10198
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10199
0
      GIR_EraseFromParent, /*InsnID*/0,
10200
      // GIR_Coverage, 2812,
10201
0
      GIR_Done,
10202
    // Label 584: @30718
10203
0
    GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(30760), // Rule ID 2813 //
10204
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
10205
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10206
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10207
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10208
      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v2f64] }:$src
10209
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10210
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10211
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10212
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10213
0
      GIR_EraseFromParent, /*InsnID*/0,
10214
      // GIR_Coverage, 2813,
10215
0
      GIR_Done,
10216
    // Label 585: @30760
10217
0
    GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(30802), // Rule ID 2814 //
10218
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
10219
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10220
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10221
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10222
      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v2f64] }:$src
10223
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10224
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10225
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10226
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10227
0
      GIR_EraseFromParent, /*InsnID*/0,
10228
      // GIR_Coverage, 2814,
10229
0
      GIR_Done,
10230
    // Label 586: @30802
10231
0
    GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(30844), // Rule ID 2815 //
10232
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
10233
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10234
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10235
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10236
      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v2i64] }:$src
10237
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10238
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10239
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10240
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10241
0
      GIR_EraseFromParent, /*InsnID*/0,
10242
      // GIR_Coverage, 2815,
10243
0
      GIR_Done,
10244
    // Label 587: @30844
10245
0
    GIM_Try, /*On fail goto*//*Label 588*/ GIMT_Encode4(30886), // Rule ID 2816 //
10246
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
10247
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10248
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10249
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10250
      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v2i64] }:$src
10251
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10252
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10253
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10254
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10255
0
      GIR_EraseFromParent, /*InsnID*/0,
10256
      // GIR_Coverage, 2816,
10257
0
      GIR_Done,
10258
    // Label 588: @30886
10259
0
    GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(30928), // Rule ID 2817 //
10260
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
10261
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10262
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10263
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10264
      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src)  =>  QPR:{ *:[v2i64] }:$src
10265
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10266
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10267
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10268
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10269
0
      GIR_EraseFromParent, /*InsnID*/0,
10270
      // GIR_Coverage, 2817,
10271
0
      GIR_Done,
10272
    // Label 589: @30928
10273
0
    GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(30970), // Rule ID 2818 //
10274
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
10275
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10276
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10277
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10278
      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8bf16] }:$src)  =>  QPR:{ *:[v2i64] }:$src
10279
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10280
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10281
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10282
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10283
0
      GIR_EraseFromParent, /*InsnID*/0,
10284
      // GIR_Coverage, 2818,
10285
0
      GIR_Done,
10286
    // Label 590: @30970
10287
0
    GIM_Try, /*On fail goto*//*Label 591*/ GIMT_Encode4(31012), // Rule ID 2819 //
10288
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
10289
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10290
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10291
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10292
      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v2i64] }:$src
10293
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10294
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10295
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10296
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10297
0
      GIR_EraseFromParent, /*InsnID*/0,
10298
      // GIR_Coverage, 2819,
10299
0
      GIR_Done,
10300
    // Label 591: @31012
10301
0
    GIM_Try, /*On fail goto*//*Label 592*/ GIMT_Encode4(31054), // Rule ID 2820 //
10302
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
10303
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10304
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10305
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10306
      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v2i64] }:$src
10307
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10308
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10309
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10310
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10311
0
      GIR_EraseFromParent, /*InsnID*/0,
10312
      // GIR_Coverage, 2820,
10313
0
      GIR_Done,
10314
    // Label 592: @31054
10315
0
    GIM_Try, /*On fail goto*//*Label 593*/ GIMT_Encode4(31102), // Rule ID 2901 //
10316
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
10317
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10318
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10319
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10320
      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src)  =>  (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src)
10321
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
10322
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
10323
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10324
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10325
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10326
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10327
0
      GIR_EraseFromParent, /*InsnID*/0,
10328
      // GIR_Coverage, 2901,
10329
0
      GIR_Done,
10330
    // Label 593: @31102
10331
0
    GIM_Try, /*On fail goto*//*Label 594*/ GIMT_Encode4(31150), // Rule ID 2902 //
10332
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
10333
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10334
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10335
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10336
      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src)  =>  (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src)
10337
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
10338
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
10339
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10340
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10341
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10342
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10343
0
      GIR_EraseFromParent, /*InsnID*/0,
10344
      // GIR_Coverage, 2902,
10345
0
      GIR_Done,
10346
    // Label 594: @31150
10347
0
    GIM_Try, /*On fail goto*//*Label 595*/ GIMT_Encode4(31198), // Rule ID 2903 //
10348
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
10349
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10350
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10351
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10352
      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src)  =>  (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src)
10353
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
10354
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
10355
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10356
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10357
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10358
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10359
0
      GIR_EraseFromParent, /*InsnID*/0,
10360
      // GIR_Coverage, 2903,
10361
0
      GIR_Done,
10362
    // Label 595: @31198
10363
0
    GIM_Try, /*On fail goto*//*Label 596*/ GIMT_Encode4(31246), // Rule ID 2904 //
10364
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
10365
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10366
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10367
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10368
      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8bf16] }:$src)  =>  (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8bf16] }:$src)
10369
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
10370
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
10371
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10372
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10373
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10374
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10375
0
      GIR_EraseFromParent, /*InsnID*/0,
10376
      // GIR_Coverage, 2904,
10377
0
      GIR_Done,
10378
    // Label 596: @31246
10379
0
    GIM_Try, /*On fail goto*//*Label 597*/ GIMT_Encode4(31294), // Rule ID 2905 //
10380
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
10381
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10382
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10383
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10384
      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src)  =>  (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src)
10385
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
10386
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
10387
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10388
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10389
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10390
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10391
0
      GIR_EraseFromParent, /*InsnID*/0,
10392
      // GIR_Coverage, 2905,
10393
0
      GIR_Done,
10394
    // Label 597: @31294
10395
0
    GIM_Try, /*On fail goto*//*Label 598*/ GIMT_Encode4(31342), // Rule ID 2906 //
10396
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
10397
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10398
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10399
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10400
      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src)  =>  (VREV64q8:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src)
10401
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q8),
10402
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
10403
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10404
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10405
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10406
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10407
0
      GIR_EraseFromParent, /*InsnID*/0,
10408
      // GIR_Coverage, 2906,
10409
0
      GIR_Done,
10410
    // Label 598: @31342
10411
0
    GIM_Try, /*On fail goto*//*Label 599*/ GIMT_Encode4(31390), // Rule ID 2907 //
10412
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
10413
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10414
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10415
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10416
      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src)  =>  (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src)
10417
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
10418
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
10419
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10420
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10421
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10422
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10423
0
      GIR_EraseFromParent, /*InsnID*/0,
10424
      // GIR_Coverage, 2907,
10425
0
      GIR_Done,
10426
    // Label 599: @31390
10427
0
    GIM_Try, /*On fail goto*//*Label 600*/ GIMT_Encode4(31438), // Rule ID 2908 //
10428
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
10429
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10430
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10431
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10432
      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src)  =>  (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src)
10433
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
10434
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
10435
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10436
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10437
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10438
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10439
0
      GIR_EraseFromParent, /*InsnID*/0,
10440
      // GIR_Coverage, 2908,
10441
0
      GIR_Done,
10442
    // Label 600: @31438
10443
0
    GIM_Try, /*On fail goto*//*Label 601*/ GIMT_Encode4(31486), // Rule ID 2909 //
10444
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
10445
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10446
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10447
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10448
      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src)  =>  (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src)
10449
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
10450
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
10451
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10452
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10453
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10454
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10455
0
      GIR_EraseFromParent, /*InsnID*/0,
10456
      // GIR_Coverage, 2909,
10457
0
      GIR_Done,
10458
    // Label 601: @31486
10459
0
    GIM_Try, /*On fail goto*//*Label 602*/ GIMT_Encode4(31534), // Rule ID 2910 //
10460
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
10461
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10462
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10463
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10464
      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8bf16] }:$src)  =>  (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8bf16] }:$src)
10465
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
10466
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
10467
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10468
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10469
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10470
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10471
0
      GIR_EraseFromParent, /*InsnID*/0,
10472
      // GIR_Coverage, 2910,
10473
0
      GIR_Done,
10474
    // Label 602: @31534
10475
0
    GIM_Try, /*On fail goto*//*Label 603*/ GIMT_Encode4(31582), // Rule ID 2911 //
10476
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
10477
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10478
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10479
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10480
      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src)  =>  (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src)
10481
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
10482
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
10483
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10484
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10485
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10486
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10487
0
      GIR_EraseFromParent, /*InsnID*/0,
10488
      // GIR_Coverage, 2911,
10489
0
      GIR_Done,
10490
    // Label 603: @31582
10491
0
    GIM_Try, /*On fail goto*//*Label 604*/ GIMT_Encode4(31630), // Rule ID 2912 //
10492
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
10493
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10494
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10495
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10496
      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src)  =>  (VREV64q8:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src)
10497
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q8),
10498
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
10499
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10500
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10501
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10502
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10503
0
      GIR_EraseFromParent, /*InsnID*/0,
10504
      // GIR_Coverage, 2912,
10505
0
      GIR_Done,
10506
    // Label 604: @31630
10507
0
    GIM_Try, /*On fail goto*//*Label 605*/ GIMT_Encode4(31672), // Rule ID 5409 //
10508
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
10509
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10510
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10511
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10512
      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$src)  =>  MQPR:{ *:[v2f64] }:$src
10513
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10514
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10515
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10516
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
10517
0
      GIR_EraseFromParent, /*InsnID*/0,
10518
      // GIR_Coverage, 5409,
10519
0
      GIR_Done,
10520
    // Label 605: @31672
10521
0
    GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(31714), // Rule ID 5410 //
10522
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
10523
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10524
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10525
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10526
      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$src)  =>  MQPR:{ *:[v2i64] }:$src
10527
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10528
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10529
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10530
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
10531
0
      GIR_EraseFromParent, /*InsnID*/0,
10532
      // GIR_Coverage, 5410,
10533
0
      GIR_Done,
10534
    // Label 606: @31714
10535
0
    GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(31756), // Rule ID 5415 //
10536
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
10537
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10538
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10539
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10540
      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src)  =>  MQPR:{ *:[v2f64] }:$src
10541
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10542
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10543
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10544
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
10545
0
      GIR_EraseFromParent, /*InsnID*/0,
10546
      // GIR_Coverage, 5415,
10547
0
      GIR_Done,
10548
    // Label 607: @31756
10549
0
    GIM_Try, /*On fail goto*//*Label 608*/ GIMT_Encode4(31798), // Rule ID 5416 //
10550
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
10551
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10552
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10553
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10554
      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src)  =>  MQPR:{ *:[v2f64] }:$src
10555
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10556
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10557
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10558
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
10559
0
      GIR_EraseFromParent, /*InsnID*/0,
10560
      // GIR_Coverage, 5416,
10561
0
      GIR_Done,
10562
    // Label 608: @31798
10563
0
    GIM_Try, /*On fail goto*//*Label 609*/ GIMT_Encode4(31840), // Rule ID 5417 //
10564
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
10565
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10566
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10567
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10568
      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src)  =>  MQPR:{ *:[v2f64] }:$src
10569
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10570
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10571
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10572
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
10573
0
      GIR_EraseFromParent, /*InsnID*/0,
10574
      // GIR_Coverage, 5417,
10575
0
      GIR_Done,
10576
    // Label 609: @31840
10577
0
    GIM_Try, /*On fail goto*//*Label 610*/ GIMT_Encode4(31882), // Rule ID 5418 //
10578
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
10579
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10580
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10581
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10582
      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src)  =>  MQPR:{ *:[v2f64] }:$src
10583
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10584
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10585
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10586
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
10587
0
      GIR_EraseFromParent, /*InsnID*/0,
10588
      // GIR_Coverage, 5418,
10589
0
      GIR_Done,
10590
    // Label 610: @31882
10591
0
    GIM_Try, /*On fail goto*//*Label 611*/ GIMT_Encode4(31924), // Rule ID 5419 //
10592
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
10593
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10594
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10595
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10596
      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src)  =>  MQPR:{ *:[v2f64] }:$src
10597
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10598
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10599
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10600
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
10601
0
      GIR_EraseFromParent, /*InsnID*/0,
10602
      // GIR_Coverage, 5419,
10603
0
      GIR_Done,
10604
    // Label 611: @31924
10605
0
    GIM_Try, /*On fail goto*//*Label 612*/ GIMT_Encode4(31966), // Rule ID 5420 //
10606
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
10607
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10608
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10609
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10610
      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src)  =>  MQPR:{ *:[v2i64] }:$src
10611
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10612
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10613
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10614
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
10615
0
      GIR_EraseFromParent, /*InsnID*/0,
10616
      // GIR_Coverage, 5420,
10617
0
      GIR_Done,
10618
    // Label 612: @31966
10619
0
    GIM_Try, /*On fail goto*//*Label 613*/ GIMT_Encode4(32008), // Rule ID 5421 //
10620
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
10621
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10622
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10623
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10624
      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src)  =>  MQPR:{ *:[v2i64] }:$src
10625
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10626
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10627
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10628
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
10629
0
      GIR_EraseFromParent, /*InsnID*/0,
10630
      // GIR_Coverage, 5421,
10631
0
      GIR_Done,
10632
    // Label 613: @32008
10633
0
    GIM_Try, /*On fail goto*//*Label 614*/ GIMT_Encode4(32050), // Rule ID 5422 //
10634
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
10635
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10636
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10637
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10638
      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src)  =>  MQPR:{ *:[v2i64] }:$src
10639
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10640
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10641
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10642
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
10643
0
      GIR_EraseFromParent, /*InsnID*/0,
10644
      // GIR_Coverage, 5422,
10645
0
      GIR_Done,
10646
    // Label 614: @32050
10647
0
    GIM_Try, /*On fail goto*//*Label 615*/ GIMT_Encode4(32092), // Rule ID 5423 //
10648
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
10649
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10650
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10651
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10652
      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src)  =>  MQPR:{ *:[v2i64] }:$src
10653
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10654
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10655
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10656
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
10657
0
      GIR_EraseFromParent, /*InsnID*/0,
10658
      // GIR_Coverage, 5423,
10659
0
      GIR_Done,
10660
    // Label 615: @32092
10661
0
    GIM_Try, /*On fail goto*//*Label 616*/ GIMT_Encode4(32134), // Rule ID 5424 //
10662
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
10663
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10664
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10665
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10666
      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src)  =>  MQPR:{ *:[v2i64] }:$src
10667
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10668
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10669
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10670
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
10671
0
      GIR_EraseFromParent, /*InsnID*/0,
10672
      // GIR_Coverage, 5424,
10673
0
      GIR_Done,
10674
    // Label 616: @32134
10675
0
    GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(32201), // Rule ID 5451 //
10676
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
10677
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10678
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10679
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10680
      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src)  =>  (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src)
10681
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10682
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10683
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
10684
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
10685
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
10686
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10687
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10688
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10689
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10690
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10691
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10692
0
      GIR_EraseFromParent, /*InsnID*/0,
10693
      // GIR_Coverage, 5451,
10694
0
      GIR_Done,
10695
    // Label 617: @32201
10696
0
    GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(32268), // Rule ID 5452 //
10697
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
10698
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10699
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10700
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10701
      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src)
10702
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10703
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10704
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
10705
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
10706
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
10707
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10708
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10709
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10710
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10711
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10712
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10713
0
      GIR_EraseFromParent, /*InsnID*/0,
10714
      // GIR_Coverage, 5452,
10715
0
      GIR_Done,
10716
    // Label 618: @32268
10717
0
    GIM_Try, /*On fail goto*//*Label 619*/ GIMT_Encode4(32335), // Rule ID 5453 //
10718
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
10719
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10720
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10721
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10722
      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src)  =>  (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src)
10723
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10724
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10725
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
10726
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
10727
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
10728
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10729
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10730
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10731
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10732
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10733
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10734
0
      GIR_EraseFromParent, /*InsnID*/0,
10735
      // GIR_Coverage, 5453,
10736
0
      GIR_Done,
10737
    // Label 619: @32335
10738
0
    GIM_Try, /*On fail goto*//*Label 620*/ GIMT_Encode4(32402), // Rule ID 5454 //
10739
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
10740
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10741
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10742
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10743
      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src)
10744
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10745
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10746
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
10747
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
10748
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
10749
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10750
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10751
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10752
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10753
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10754
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10755
0
      GIR_EraseFromParent, /*InsnID*/0,
10756
      // GIR_Coverage, 5454,
10757
0
      GIR_Done,
10758
    // Label 620: @32402
10759
0
    GIM_Try, /*On fail goto*//*Label 621*/ GIMT_Encode4(32469), // Rule ID 5455 //
10760
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
10761
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10762
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10763
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10764
      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src)  =>  (MVE_VREV64_8:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src)
10765
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10766
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10767
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
10768
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8),
10769
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
10770
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10771
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10772
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10773
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10774
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10775
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10776
0
      GIR_EraseFromParent, /*InsnID*/0,
10777
      // GIR_Coverage, 5455,
10778
0
      GIR_Done,
10779
    // Label 621: @32469
10780
0
    GIM_Try, /*On fail goto*//*Label 622*/ GIMT_Encode4(32536), // Rule ID 5456 //
10781
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
10782
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10783
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10784
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10785
      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src)  =>  (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src)
10786
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10787
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10788
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
10789
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
10790
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
10791
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10792
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10793
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10794
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10795
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10796
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10797
0
      GIR_EraseFromParent, /*InsnID*/0,
10798
      // GIR_Coverage, 5456,
10799
0
      GIR_Done,
10800
    // Label 622: @32536
10801
0
    GIM_Try, /*On fail goto*//*Label 623*/ GIMT_Encode4(32603), // Rule ID 5457 //
10802
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
10803
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10804
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10805
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10806
      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src)
10807
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10808
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10809
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
10810
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
10811
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
10812
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10813
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10814
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10815
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10816
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10817
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10818
0
      GIR_EraseFromParent, /*InsnID*/0,
10819
      // GIR_Coverage, 5457,
10820
0
      GIR_Done,
10821
    // Label 623: @32603
10822
0
    GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(32670), // Rule ID 5458 //
10823
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
10824
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10825
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10826
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10827
      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src)  =>  (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src)
10828
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10829
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10830
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
10831
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
10832
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
10833
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10834
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10835
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10836
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10837
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10838
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10839
0
      GIR_EraseFromParent, /*InsnID*/0,
10840
      // GIR_Coverage, 5458,
10841
0
      GIR_Done,
10842
    // Label 624: @32670
10843
0
    GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(32737), // Rule ID 5459 //
10844
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
10845
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10846
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10847
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10848
      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src)
10849
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10850
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10851
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
10852
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
10853
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
10854
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10855
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10856
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10857
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10858
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10859
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10860
0
      GIR_EraseFromParent, /*InsnID*/0,
10861
      // GIR_Coverage, 5459,
10862
0
      GIR_Done,
10863
    // Label 625: @32737
10864
0
    GIM_Try, /*On fail goto*//*Label 626*/ GIMT_Encode4(32804), // Rule ID 5460 //
10865
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
10866
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10867
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10868
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10869
      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src)  =>  (MVE_VREV64_8:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src)
10870
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10871
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10872
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
10873
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8),
10874
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
10875
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10876
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10877
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10878
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10879
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10880
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10881
0
      GIR_EraseFromParent, /*InsnID*/0,
10882
      // GIR_Coverage, 5460,
10883
0
      GIR_Done,
10884
    // Label 626: @32804
10885
0
    GIM_Reject,
10886
    // Label 517: @32805
10887
0
    GIM_Try, /*On fail goto*//*Label 627*/ GIMT_Encode4(32847), // Rule ID 2751 //
10888
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10889
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10890
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10891
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10892
      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v4f16] }:$src)  =>  DPR:{ *:[v4i16] }:$src
10893
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10894
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10895
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10896
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10897
0
      GIR_EraseFromParent, /*InsnID*/0,
10898
      // GIR_Coverage, 2751,
10899
0
      GIR_Done,
10900
    // Label 627: @32847
10901
0
    GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(32889), // Rule ID 2752 //
10902
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10903
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10904
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10905
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10906
      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[v4f16] }:$src
10907
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10908
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10909
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10910
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10911
0
      GIR_EraseFromParent, /*InsnID*/0,
10912
      // GIR_Coverage, 2752,
10913
0
      GIR_Done,
10914
    // Label 628: @32889
10915
0
    GIM_Try, /*On fail goto*//*Label 629*/ GIMT_Encode4(32931), // Rule ID 2753 //
10916
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10917
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10918
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10919
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10920
      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v4bf16] }:$src)  =>  DPR:{ *:[v4i16] }:$src
10921
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10922
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10923
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10924
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10925
0
      GIR_EraseFromParent, /*InsnID*/0,
10926
      // GIR_Coverage, 2753,
10927
0
      GIR_Done,
10928
    // Label 629: @32931
10929
0
    GIM_Try, /*On fail goto*//*Label 630*/ GIMT_Encode4(32973), // Rule ID 2754 //
10930
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10931
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10932
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10933
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10934
      // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[v4bf16] }:$src
10935
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10936
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10937
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10938
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10939
0
      GIR_EraseFromParent, /*InsnID*/0,
10940
      // GIR_Coverage, 2754,
10941
0
      GIR_Done,
10942
    // Label 630: @32973
10943
0
    GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(33015), // Rule ID 2787 //
10944
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
10945
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10946
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10947
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10948
      // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v4f16] }:$src
10949
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10950
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10951
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10952
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10953
0
      GIR_EraseFromParent, /*InsnID*/0,
10954
      // GIR_Coverage, 2787,
10955
0
      GIR_Done,
10956
    // Label 631: @33015
10957
0
    GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(33057), // Rule ID 2788 //
10958
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
10959
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10960
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10961
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10962
      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[v4f16] }:$src
10963
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10964
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10965
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10966
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10967
0
      GIR_EraseFromParent, /*InsnID*/0,
10968
      // GIR_Coverage, 2788,
10969
0
      GIR_Done,
10970
    // Label 632: @33057
10971
0
    GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(33099), // Rule ID 2789 //
10972
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
10973
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
10974
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10975
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10976
      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[v4f16] }:$src
10977
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10978
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10979
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10980
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10981
0
      GIR_EraseFromParent, /*InsnID*/0,
10982
      // GIR_Coverage, 2789,
10983
0
      GIR_Done,
10984
    // Label 633: @33099
10985
0
    GIM_Try, /*On fail goto*//*Label 634*/ GIMT_Encode4(33141), // Rule ID 2790 //
10986
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
10987
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
10988
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10989
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10990
      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[v4f16] }:$src
10991
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10992
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10993
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10994
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10995
0
      GIR_EraseFromParent, /*InsnID*/0,
10996
      // GIR_Coverage, 2790,
10997
0
      GIR_Done,
10998
    // Label 634: @33141
10999
0
    GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(33183), // Rule ID 2791 //
11000
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11001
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
11002
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11003
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11004
      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[v4f16] }:$src
11005
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11006
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11007
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11008
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11009
0
      GIR_EraseFromParent, /*InsnID*/0,
11010
      // GIR_Coverage, 2791,
11011
0
      GIR_Done,
11012
    // Label 635: @33183
11013
0
    GIM_Try, /*On fail goto*//*Label 636*/ GIMT_Encode4(33225), // Rule ID 2792 //
11014
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11015
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11016
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11017
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11018
      // (bitconvert:{ *:[v4bf16] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v4bf16] }:$src
11019
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11020
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11021
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11022
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11023
0
      GIR_EraseFromParent, /*InsnID*/0,
11024
      // GIR_Coverage, 2792,
11025
0
      GIR_Done,
11026
    // Label 636: @33225
11027
0
    GIM_Try, /*On fail goto*//*Label 637*/ GIMT_Encode4(33267), // Rule ID 2793 //
11028
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11029
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11030
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11031
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11032
      // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[v4bf16] }:$src
11033
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11034
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11035
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11036
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11037
0
      GIR_EraseFromParent, /*InsnID*/0,
11038
      // GIR_Coverage, 2793,
11039
0
      GIR_Done,
11040
    // Label 637: @33267
11041
0
    GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(33309), // Rule ID 2794 //
11042
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11043
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11044
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11045
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11046
      // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[v4bf16] }:$src
11047
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11048
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11049
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11050
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11051
0
      GIR_EraseFromParent, /*InsnID*/0,
11052
      // GIR_Coverage, 2794,
11053
0
      GIR_Done,
11054
    // Label 638: @33309
11055
0
    GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(33351), // Rule ID 2795 //
11056
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11057
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11058
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11059
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11060
      // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[v4bf16] }:$src
11061
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11062
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11063
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11064
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11065
0
      GIR_EraseFromParent, /*InsnID*/0,
11066
      // GIR_Coverage, 2795,
11067
0
      GIR_Done,
11068
    // Label 639: @33351
11069
0
    GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(33393), // Rule ID 2796 //
11070
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11071
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
11072
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11073
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11074
      // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[v4bf16] }:$src
11075
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11076
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11077
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11078
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11079
0
      GIR_EraseFromParent, /*InsnID*/0,
11080
      // GIR_Coverage, 2796,
11081
0
      GIR_Done,
11082
    // Label 640: @33393
11083
0
    GIM_Try, /*On fail goto*//*Label 641*/ GIMT_Encode4(33435), // Rule ID 2797 //
11084
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11085
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11086
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11087
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11088
      // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v4i16] }:$src
11089
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11090
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11091
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11092
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11093
0
      GIR_EraseFromParent, /*InsnID*/0,
11094
      // GIR_Coverage, 2797,
11095
0
      GIR_Done,
11096
    // Label 641: @33435
11097
0
    GIM_Try, /*On fail goto*//*Label 642*/ GIMT_Encode4(33477), // Rule ID 2798 //
11098
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11099
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11100
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11101
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11102
      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[v4i16] }:$src
11103
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11104
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11105
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11106
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11107
0
      GIR_EraseFromParent, /*InsnID*/0,
11108
      // GIR_Coverage, 2798,
11109
0
      GIR_Done,
11110
    // Label 642: @33477
11111
0
    GIM_Try, /*On fail goto*//*Label 643*/ GIMT_Encode4(33519), // Rule ID 2799 //
11112
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11113
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11114
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11115
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11116
      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[v4i16] }:$src
11117
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11118
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11119
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11120
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11121
0
      GIR_EraseFromParent, /*InsnID*/0,
11122
      // GIR_Coverage, 2799,
11123
0
      GIR_Done,
11124
    // Label 643: @33519
11125
0
    GIM_Try, /*On fail goto*//*Label 644*/ GIMT_Encode4(33561), // Rule ID 2800 //
11126
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11127
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11128
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11129
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11130
      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[v4i16] }:$src
11131
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11132
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11133
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11134
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11135
0
      GIR_EraseFromParent, /*InsnID*/0,
11136
      // GIR_Coverage, 2800,
11137
0
      GIR_Done,
11138
    // Label 644: @33561
11139
0
    GIM_Try, /*On fail goto*//*Label 645*/ GIMT_Encode4(33603), // Rule ID 2801 //
11140
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11141
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
11142
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11143
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11144
      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[v4i16] }:$src
11145
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11146
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11147
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11148
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11149
0
      GIR_EraseFromParent, /*InsnID*/0,
11150
      // GIR_Coverage, 2801,
11151
0
      GIR_Done,
11152
    // Label 645: @33603
11153
0
    GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(33651), // Rule ID 2879 //
11154
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11155
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11156
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11157
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11158
      // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src)  =>  (VREV64d16:{ *:[v4f16] } DPR:{ *:[f64] }:$src)
11159
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
11160
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11161
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11162
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11163
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11164
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11165
0
      GIR_EraseFromParent, /*InsnID*/0,
11166
      // GIR_Coverage, 2879,
11167
0
      GIR_Done,
11168
    // Label 646: @33651
11169
0
    GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(33699), // Rule ID 2880 //
11170
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11171
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11172
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11173
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11174
      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src)  =>  (VREV64d16:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src)
11175
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
11176
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11177
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11178
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11179
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11180
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11181
0
      GIR_EraseFromParent, /*InsnID*/0,
11182
      // GIR_Coverage, 2880,
11183
0
      GIR_Done,
11184
    // Label 647: @33699
11185
0
    GIM_Try, /*On fail goto*//*Label 648*/ GIMT_Encode4(33747), // Rule ID 2881 //
11186
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11187
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11188
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11189
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11190
      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src)  =>  (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src)
11191
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
11192
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11193
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11194
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11195
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11196
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11197
0
      GIR_EraseFromParent, /*InsnID*/0,
11198
      // GIR_Coverage, 2881,
11199
0
      GIR_Done,
11200
    // Label 648: @33747
11201
0
    GIM_Try, /*On fail goto*//*Label 649*/ GIMT_Encode4(33795), // Rule ID 2882 //
11202
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11203
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11204
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11205
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11206
      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src)  =>  (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src)
11207
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
11208
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11209
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11210
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11211
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11212
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11213
0
      GIR_EraseFromParent, /*InsnID*/0,
11214
      // GIR_Coverage, 2882,
11215
0
      GIR_Done,
11216
    // Label 649: @33795
11217
0
    GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(33843), // Rule ID 2883 //
11218
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11219
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
11220
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11221
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11222
      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src)  =>  (VREV16d8:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src)
11223
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV16d8),
11224
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11225
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11226
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11227
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11228
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11229
0
      GIR_EraseFromParent, /*InsnID*/0,
11230
      // GIR_Coverage, 2883,
11231
0
      GIR_Done,
11232
    // Label 650: @33843
11233
0
    GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(33891), // Rule ID 2884 //
11234
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11235
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11236
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11237
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11238
      // (bitconvert:{ *:[v4bf16] } DPR:{ *:[f64] }:$src)  =>  (VREV64d16:{ *:[v4bf16] } DPR:{ *:[f64] }:$src)
11239
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
11240
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11241
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11242
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11243
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11244
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11245
0
      GIR_EraseFromParent, /*InsnID*/0,
11246
      // GIR_Coverage, 2884,
11247
0
      GIR_Done,
11248
    // Label 651: @33891
11249
0
    GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(33939), // Rule ID 2885 //
11250
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11251
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11252
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11253
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11254
      // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v1i64] }:$src)  =>  (VREV64d16:{ *:[v4bf16] } DPR:{ *:[v1i64] }:$src)
11255
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
11256
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11257
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11258
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11259
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11260
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11261
0
      GIR_EraseFromParent, /*InsnID*/0,
11262
      // GIR_Coverage, 2885,
11263
0
      GIR_Done,
11264
    // Label 652: @33939
11265
0
    GIM_Try, /*On fail goto*//*Label 653*/ GIMT_Encode4(33987), // Rule ID 2886 //
11266
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11267
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11268
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11269
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11270
      // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v2f32] }:$src)  =>  (VREV32d16:{ *:[v4bf16] } DPR:{ *:[v2f32] }:$src)
11271
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
11272
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11273
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11274
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11275
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11276
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11277
0
      GIR_EraseFromParent, /*InsnID*/0,
11278
      // GIR_Coverage, 2886,
11279
0
      GIR_Done,
11280
    // Label 653: @33987
11281
0
    GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(34035), // Rule ID 2887 //
11282
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11283
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11284
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11285
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11286
      // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v2i32] }:$src)  =>  (VREV32d16:{ *:[v4bf16] } DPR:{ *:[v2i32] }:$src)
11287
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
11288
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11289
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11290
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11291
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11292
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11293
0
      GIR_EraseFromParent, /*InsnID*/0,
11294
      // GIR_Coverage, 2887,
11295
0
      GIR_Done,
11296
    // Label 654: @34035
11297
0
    GIM_Try, /*On fail goto*//*Label 655*/ GIMT_Encode4(34083), // Rule ID 2888 //
11298
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11299
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
11300
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11301
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11302
      // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v8i8] }:$src)  =>  (VREV16d8:{ *:[v4bf16] } DPR:{ *:[v8i8] }:$src)
11303
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV16d8),
11304
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11305
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11306
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11307
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11308
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11309
0
      GIR_EraseFromParent, /*InsnID*/0,
11310
      // GIR_Coverage, 2888,
11311
0
      GIR_Done,
11312
    // Label 655: @34083
11313
0
    GIM_Try, /*On fail goto*//*Label 656*/ GIMT_Encode4(34131), // Rule ID 2889 //
11314
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11315
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11316
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11317
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11318
      // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src)  =>  (VREV64d16:{ *:[v4i16] } DPR:{ *:[f64] }:$src)
11319
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
11320
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11321
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11322
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11323
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11324
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11325
0
      GIR_EraseFromParent, /*InsnID*/0,
11326
      // GIR_Coverage, 2889,
11327
0
      GIR_Done,
11328
    // Label 656: @34131
11329
0
    GIM_Try, /*On fail goto*//*Label 657*/ GIMT_Encode4(34179), // Rule ID 2890 //
11330
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11331
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11332
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11333
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11334
      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src)  =>  (VREV64d16:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src)
11335
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
11336
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11337
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11338
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11339
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11340
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11341
0
      GIR_EraseFromParent, /*InsnID*/0,
11342
      // GIR_Coverage, 2890,
11343
0
      GIR_Done,
11344
    // Label 657: @34179
11345
0
    GIM_Try, /*On fail goto*//*Label 658*/ GIMT_Encode4(34227), // Rule ID 2891 //
11346
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11347
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11348
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11349
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11350
      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src)  =>  (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src)
11351
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
11352
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11353
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11354
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11355
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11356
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11357
0
      GIR_EraseFromParent, /*InsnID*/0,
11358
      // GIR_Coverage, 2891,
11359
0
      GIR_Done,
11360
    // Label 658: @34227
11361
0
    GIM_Try, /*On fail goto*//*Label 659*/ GIMT_Encode4(34275), // Rule ID 2892 //
11362
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11363
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11364
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11365
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11366
      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src)  =>  (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src)
11367
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
11368
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11369
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11370
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11371
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11372
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11373
0
      GIR_EraseFromParent, /*InsnID*/0,
11374
      // GIR_Coverage, 2892,
11375
0
      GIR_Done,
11376
    // Label 659: @34275
11377
0
    GIM_Try, /*On fail goto*//*Label 660*/ GIMT_Encode4(34323), // Rule ID 2893 //
11378
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11379
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
11380
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11381
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11382
      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src)  =>  (VREV16d8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src)
11383
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV16d8),
11384
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11385
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11386
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11387
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11388
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11389
0
      GIR_EraseFromParent, /*InsnID*/0,
11390
      // GIR_Coverage, 2893,
11391
0
      GIR_Done,
11392
    // Label 660: @34323
11393
0
    GIM_Reject,
11394
    // Label 518: @34324
11395
0
    GIM_Try, /*On fail goto*//*Label 661*/ GIMT_Encode4(34366), // Rule ID 2757 //
11396
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11397
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11398
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11399
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11400
      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v4i32] }:$src
11401
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11402
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11403
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11404
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11405
0
      GIR_EraseFromParent, /*InsnID*/0,
11406
      // GIR_Coverage, 2757,
11407
0
      GIR_Done,
11408
    // Label 661: @34366
11409
0
    GIM_Try, /*On fail goto*//*Label 662*/ GIMT_Encode4(34408), // Rule ID 2758 //
11410
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11411
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11412
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11413
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11414
      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v4f32] }:$src
11415
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11416
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11417
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11418
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11419
0
      GIR_EraseFromParent, /*InsnID*/0,
11420
      // GIR_Coverage, 2758,
11421
0
      GIR_Done,
11422
    // Label 662: @34408
11423
0
    GIM_Try, /*On fail goto*//*Label 663*/ GIMT_Encode4(34450), // Rule ID 2821 //
11424
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11425
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11426
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11427
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11428
      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v4f32] }:$src
11429
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11430
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11431
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11432
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11433
0
      GIR_EraseFromParent, /*InsnID*/0,
11434
      // GIR_Coverage, 2821,
11435
0
      GIR_Done,
11436
    // Label 663: @34450
11437
0
    GIM_Try, /*On fail goto*//*Label 664*/ GIMT_Encode4(34492), // Rule ID 2822 //
11438
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11439
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11440
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11441
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11442
      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v4f32] }:$src
11443
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11444
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11445
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11446
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11447
0
      GIR_EraseFromParent, /*InsnID*/0,
11448
      // GIR_Coverage, 2822,
11449
0
      GIR_Done,
11450
    // Label 664: @34492
11451
0
    GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(34534), // Rule ID 2823 //
11452
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11453
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11454
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11455
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11456
      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src)  =>  QPR:{ *:[v4f32] }:$src
11457
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11458
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11459
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11460
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11461
0
      GIR_EraseFromParent, /*InsnID*/0,
11462
      // GIR_Coverage, 2823,
11463
0
      GIR_Done,
11464
    // Label 665: @34534
11465
0
    GIM_Try, /*On fail goto*//*Label 666*/ GIMT_Encode4(34576), // Rule ID 2824 //
11466
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11467
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11468
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11469
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11470
      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8bf16] }:$src)  =>  QPR:{ *:[v4f32] }:$src
11471
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11472
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11473
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11474
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11475
0
      GIR_EraseFromParent, /*InsnID*/0,
11476
      // GIR_Coverage, 2824,
11477
0
      GIR_Done,
11478
    // Label 666: @34576
11479
0
    GIM_Try, /*On fail goto*//*Label 667*/ GIMT_Encode4(34618), // Rule ID 2825 //
11480
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11481
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11482
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11483
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11484
      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v4f32] }:$src
11485
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11486
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11487
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11488
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11489
0
      GIR_EraseFromParent, /*InsnID*/0,
11490
      // GIR_Coverage, 2825,
11491
0
      GIR_Done,
11492
    // Label 667: @34618
11493
0
    GIM_Try, /*On fail goto*//*Label 668*/ GIMT_Encode4(34660), // Rule ID 2826 //
11494
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11495
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11496
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11497
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11498
      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v4f32] }:$src
11499
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11500
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11501
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11502
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11503
0
      GIR_EraseFromParent, /*InsnID*/0,
11504
      // GIR_Coverage, 2826,
11505
0
      GIR_Done,
11506
    // Label 668: @34660
11507
0
    GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(34702), // Rule ID 2827 //
11508
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11509
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11510
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11511
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11512
      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v4i32] }:$src
11513
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11514
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11515
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11516
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11517
0
      GIR_EraseFromParent, /*InsnID*/0,
11518
      // GIR_Coverage, 2827,
11519
0
      GIR_Done,
11520
    // Label 669: @34702
11521
0
    GIM_Try, /*On fail goto*//*Label 670*/ GIMT_Encode4(34744), // Rule ID 2828 //
11522
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11523
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11524
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11525
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11526
      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v4i32] }:$src
11527
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11528
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11529
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11530
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11531
0
      GIR_EraseFromParent, /*InsnID*/0,
11532
      // GIR_Coverage, 2828,
11533
0
      GIR_Done,
11534
    // Label 670: @34744
11535
0
    GIM_Try, /*On fail goto*//*Label 671*/ GIMT_Encode4(34786), // Rule ID 2829 //
11536
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11537
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11538
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11539
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11540
      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src)  =>  QPR:{ *:[v4i32] }:$src
11541
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11542
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11543
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11544
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11545
0
      GIR_EraseFromParent, /*InsnID*/0,
11546
      // GIR_Coverage, 2829,
11547
0
      GIR_Done,
11548
    // Label 671: @34786
11549
0
    GIM_Try, /*On fail goto*//*Label 672*/ GIMT_Encode4(34828), // Rule ID 2830 //
11550
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11551
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11552
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11553
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11554
      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8bf16] }:$src)  =>  QPR:{ *:[v4i32] }:$src
11555
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11556
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11557
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11558
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11559
0
      GIR_EraseFromParent, /*InsnID*/0,
11560
      // GIR_Coverage, 2830,
11561
0
      GIR_Done,
11562
    // Label 672: @34828
11563
0
    GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(34870), // Rule ID 2831 //
11564
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11565
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11566
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11567
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11568
      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v4i32] }:$src
11569
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11570
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11571
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11572
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11573
0
      GIR_EraseFromParent, /*InsnID*/0,
11574
      // GIR_Coverage, 2831,
11575
0
      GIR_Done,
11576
    // Label 673: @34870
11577
0
    GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(34912), // Rule ID 2832 //
11578
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11579
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11580
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11581
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11582
      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v4i32] }:$src
11583
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11584
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11585
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11586
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11587
0
      GIR_EraseFromParent, /*InsnID*/0,
11588
      // GIR_Coverage, 2832,
11589
0
      GIR_Done,
11590
    // Label 674: @34912
11591
0
    GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(34960), // Rule ID 2913 //
11592
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11593
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11594
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11595
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11596
      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src)  =>  (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src)
11597
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
11598
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11599
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11600
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11601
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11602
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11603
0
      GIR_EraseFromParent, /*InsnID*/0,
11604
      // GIR_Coverage, 2913,
11605
0
      GIR_Done,
11606
    // Label 675: @34960
11607
0
    GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(35008), // Rule ID 2914 //
11608
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11609
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11610
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11611
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11612
      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src)  =>  (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src)
11613
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
11614
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11615
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11616
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11617
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11618
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11619
0
      GIR_EraseFromParent, /*InsnID*/0,
11620
      // GIR_Coverage, 2914,
11621
0
      GIR_Done,
11622
    // Label 676: @35008
11623
0
    GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(35056), // Rule ID 2915 //
11624
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11625
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11626
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11627
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11628
      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src)  =>  (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src)
11629
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
11630
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11631
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11632
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11633
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11634
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11635
0
      GIR_EraseFromParent, /*InsnID*/0,
11636
      // GIR_Coverage, 2915,
11637
0
      GIR_Done,
11638
    // Label 677: @35056
11639
0
    GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(35104), // Rule ID 2916 //
11640
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11641
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11642
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11643
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11644
      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8bf16] }:$src)  =>  (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8bf16] }:$src)
11645
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
11646
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11647
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11648
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11649
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11650
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11651
0
      GIR_EraseFromParent, /*InsnID*/0,
11652
      // GIR_Coverage, 2916,
11653
0
      GIR_Done,
11654
    // Label 678: @35104
11655
0
    GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(35152), // Rule ID 2917 //
11656
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11657
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11658
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11659
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11660
      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src)  =>  (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src)
11661
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
11662
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11663
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11664
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11665
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11666
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11667
0
      GIR_EraseFromParent, /*InsnID*/0,
11668
      // GIR_Coverage, 2917,
11669
0
      GIR_Done,
11670
    // Label 679: @35152
11671
0
    GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(35200), // Rule ID 2918 //
11672
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11673
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11674
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11675
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11676
      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src)  =>  (VREV32q8:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src)
11677
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32q8),
11678
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11679
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11680
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11681
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11682
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11683
0
      GIR_EraseFromParent, /*InsnID*/0,
11684
      // GIR_Coverage, 2918,
11685
0
      GIR_Done,
11686
    // Label 680: @35200
11687
0
    GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(35248), // Rule ID 2919 //
11688
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11689
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11690
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11691
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11692
      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src)  =>  (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src)
11693
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
11694
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11695
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11696
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11697
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11698
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11699
0
      GIR_EraseFromParent, /*InsnID*/0,
11700
      // GIR_Coverage, 2919,
11701
0
      GIR_Done,
11702
    // Label 681: @35248
11703
0
    GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(35296), // Rule ID 2920 //
11704
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11705
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11706
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11707
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11708
      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src)  =>  (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src)
11709
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
11710
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11711
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11712
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11713
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11714
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11715
0
      GIR_EraseFromParent, /*InsnID*/0,
11716
      // GIR_Coverage, 2920,
11717
0
      GIR_Done,
11718
    // Label 682: @35296
11719
0
    GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(35344), // Rule ID 2921 //
11720
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11721
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11722
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11723
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11724
      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src)  =>  (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src)
11725
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
11726
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11727
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11728
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11729
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11730
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11731
0
      GIR_EraseFromParent, /*InsnID*/0,
11732
      // GIR_Coverage, 2921,
11733
0
      GIR_Done,
11734
    // Label 683: @35344
11735
0
    GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(35392), // Rule ID 2922 //
11736
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11737
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11738
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11739
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11740
      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8bf16] }:$src)  =>  (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8bf16] }:$src)
11741
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
11742
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11743
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11744
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11745
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11746
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11747
0
      GIR_EraseFromParent, /*InsnID*/0,
11748
      // GIR_Coverage, 2922,
11749
0
      GIR_Done,
11750
    // Label 684: @35392
11751
0
    GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(35440), // Rule ID 2923 //
11752
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11753
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11754
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11755
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11756
      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src)  =>  (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src)
11757
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
11758
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11759
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11760
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11761
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11762
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11763
0
      GIR_EraseFromParent, /*InsnID*/0,
11764
      // GIR_Coverage, 2923,
11765
0
      GIR_Done,
11766
    // Label 685: @35440
11767
0
    GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(35488), // Rule ID 2924 //
11768
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11769
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11770
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11771
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11772
      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src)  =>  (VREV32q8:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src)
11773
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32q8),
11774
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
11775
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11776
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11777
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11778
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11779
0
      GIR_EraseFromParent, /*InsnID*/0,
11780
      // GIR_Coverage, 2924,
11781
0
      GIR_Done,
11782
    // Label 686: @35488
11783
0
    GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(35530), // Rule ID 5411 //
11784
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
11785
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11786
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11787
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11788
      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)  =>  MQPR:{ *:[v4i32] }:$src
11789
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11790
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11791
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11792
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11793
0
      GIR_EraseFromParent, /*InsnID*/0,
11794
      // GIR_Coverage, 5411,
11795
0
      GIR_Done,
11796
    // Label 687: @35530
11797
0
    GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(35572), // Rule ID 5412 //
11798
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
11799
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11800
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11801
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11802
      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)  =>  MQPR:{ *:[v4f32] }:$src
11803
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11804
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11805
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11806
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11807
0
      GIR_EraseFromParent, /*InsnID*/0,
11808
      // GIR_Coverage, 5412,
11809
0
      GIR_Done,
11810
    // Label 688: @35572
11811
0
    GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(35614), // Rule ID 5425 //
11812
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
11813
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11814
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11815
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11816
      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src)  =>  MQPR:{ *:[v4f32] }:$src
11817
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11818
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11819
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11820
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11821
0
      GIR_EraseFromParent, /*InsnID*/0,
11822
      // GIR_Coverage, 5425,
11823
0
      GIR_Done,
11824
    // Label 689: @35614
11825
0
    GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(35656), // Rule ID 5426 //
11826
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
11827
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11828
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11829
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11830
      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src)  =>  MQPR:{ *:[v4f32] }:$src
11831
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11832
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11833
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11834
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11835
0
      GIR_EraseFromParent, /*InsnID*/0,
11836
      // GIR_Coverage, 5426,
11837
0
      GIR_Done,
11838
    // Label 690: @35656
11839
0
    GIM_Try, /*On fail goto*//*Label 691*/ GIMT_Encode4(35698), // Rule ID 5427 //
11840
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
11841
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11842
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11843
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11844
      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src)  =>  MQPR:{ *:[v4f32] }:$src
11845
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11846
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11847
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11848
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11849
0
      GIR_EraseFromParent, /*InsnID*/0,
11850
      // GIR_Coverage, 5427,
11851
0
      GIR_Done,
11852
    // Label 691: @35698
11853
0
    GIM_Try, /*On fail goto*//*Label 692*/ GIMT_Encode4(35740), // Rule ID 5428 //
11854
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
11855
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11856
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11857
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11858
      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src)  =>  MQPR:{ *:[v4f32] }:$src
11859
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11860
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11861
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11862
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11863
0
      GIR_EraseFromParent, /*InsnID*/0,
11864
      // GIR_Coverage, 5428,
11865
0
      GIR_Done,
11866
    // Label 692: @35740
11867
0
    GIM_Try, /*On fail goto*//*Label 693*/ GIMT_Encode4(35782), // Rule ID 5429 //
11868
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
11869
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11870
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11871
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11872
      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src)  =>  MQPR:{ *:[v4f32] }:$src
11873
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11874
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11875
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11876
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11877
0
      GIR_EraseFromParent, /*InsnID*/0,
11878
      // GIR_Coverage, 5429,
11879
0
      GIR_Done,
11880
    // Label 693: @35782
11881
0
    GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(35824), // Rule ID 5430 //
11882
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
11883
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11884
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11885
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11886
      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src)  =>  MQPR:{ *:[v4i32] }:$src
11887
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11888
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11889
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11890
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11891
0
      GIR_EraseFromParent, /*InsnID*/0,
11892
      // GIR_Coverage, 5430,
11893
0
      GIR_Done,
11894
    // Label 694: @35824
11895
0
    GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(35866), // Rule ID 5431 //
11896
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
11897
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11898
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11899
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11900
      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src)  =>  MQPR:{ *:[v4i32] }:$src
11901
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11902
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11903
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11904
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11905
0
      GIR_EraseFromParent, /*InsnID*/0,
11906
      // GIR_Coverage, 5431,
11907
0
      GIR_Done,
11908
    // Label 695: @35866
11909
0
    GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(35908), // Rule ID 5432 //
11910
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
11911
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11912
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11913
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11914
      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src)  =>  MQPR:{ *:[v4i32] }:$src
11915
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11916
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11917
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11918
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11919
0
      GIR_EraseFromParent, /*InsnID*/0,
11920
      // GIR_Coverage, 5432,
11921
0
      GIR_Done,
11922
    // Label 696: @35908
11923
0
    GIM_Try, /*On fail goto*//*Label 697*/ GIMT_Encode4(35950), // Rule ID 5433 //
11924
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
11925
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11926
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11927
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11928
      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)  =>  MQPR:{ *:[v4i32] }:$src
11929
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11930
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11931
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11932
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11933
0
      GIR_EraseFromParent, /*InsnID*/0,
11934
      // GIR_Coverage, 5433,
11935
0
      GIR_Done,
11936
    // Label 697: @35950
11937
0
    GIM_Try, /*On fail goto*//*Label 698*/ GIMT_Encode4(35992), // Rule ID 5434 //
11938
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
11939
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11940
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11941
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11942
      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src)  =>  MQPR:{ *:[v4i32] }:$src
11943
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11944
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11945
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11946
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11947
0
      GIR_EraseFromParent, /*InsnID*/0,
11948
      // GIR_Coverage, 5434,
11949
0
      GIR_Done,
11950
    // Label 698: @35992
11951
0
    GIM_Try, /*On fail goto*//*Label 699*/ GIMT_Encode4(36059), // Rule ID 5461 //
11952
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
11953
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11954
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11955
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11956
      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src)  =>  (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src)
11957
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11958
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11959
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
11960
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
11961
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
11962
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11963
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11964
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11965
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11966
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11967
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11968
0
      GIR_EraseFromParent, /*InsnID*/0,
11969
      // GIR_Coverage, 5461,
11970
0
      GIR_Done,
11971
    // Label 699: @36059
11972
0
    GIM_Try, /*On fail goto*//*Label 700*/ GIMT_Encode4(36126), // Rule ID 5462 //
11973
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
11974
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11975
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11976
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11977
      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src)  =>  (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src)
11978
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11979
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11980
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
11981
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
11982
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
11983
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11984
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11985
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11986
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11987
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11988
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11989
0
      GIR_EraseFromParent, /*InsnID*/0,
11990
      // GIR_Coverage, 5462,
11991
0
      GIR_Done,
11992
    // Label 700: @36126
11993
0
    GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(36193), // Rule ID 5463 //
11994
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
11995
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11996
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11997
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11998
      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src)  =>  (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src)
11999
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12000
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12001
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
12002
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12003
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
12004
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12005
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12006
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12007
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12008
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12009
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12010
0
      GIR_EraseFromParent, /*InsnID*/0,
12011
      // GIR_Coverage, 5463,
12012
0
      GIR_Done,
12013
    // Label 701: @36193
12014
0
    GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(36260), // Rule ID 5464 //
12015
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12016
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12017
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12018
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12019
      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src)
12020
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12021
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12022
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
12023
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12024
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
12025
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12026
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12027
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12028
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12029
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12030
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12031
0
      GIR_EraseFromParent, /*InsnID*/0,
12032
      // GIR_Coverage, 5464,
12033
0
      GIR_Done,
12034
    // Label 702: @36260
12035
0
    GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(36327), // Rule ID 5465 //
12036
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12037
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12038
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12039
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12040
      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src)  =>  (MVE_VREV32_8:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src)
12041
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12042
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12043
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
12044
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
12045
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
12046
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12047
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12048
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12049
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12050
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12051
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12052
0
      GIR_EraseFromParent, /*InsnID*/0,
12053
      // GIR_Coverage, 5465,
12054
0
      GIR_Done,
12055
    // Label 703: @36327
12056
0
    GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(36394), // Rule ID 5466 //
12057
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12058
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12059
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12060
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12061
      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src)  =>  (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src)
12062
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12063
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12064
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
12065
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
12066
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
12067
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12068
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12069
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12070
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12071
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12072
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12073
0
      GIR_EraseFromParent, /*InsnID*/0,
12074
      // GIR_Coverage, 5466,
12075
0
      GIR_Done,
12076
    // Label 704: @36394
12077
0
    GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(36461), // Rule ID 5467 //
12078
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12079
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12080
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12081
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12082
      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src)  =>  (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src)
12083
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12084
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12085
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
12086
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
12087
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
12088
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12089
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12090
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12091
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12092
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12093
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12094
0
      GIR_EraseFromParent, /*InsnID*/0,
12095
      // GIR_Coverage, 5467,
12096
0
      GIR_Done,
12097
    // Label 705: @36461
12098
0
    GIM_Try, /*On fail goto*//*Label 706*/ GIMT_Encode4(36528), // Rule ID 5468 //
12099
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12100
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12101
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12102
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12103
      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src)  =>  (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src)
12104
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12105
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12106
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
12107
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12108
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
12109
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12110
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12111
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12112
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12113
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12114
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12115
0
      GIR_EraseFromParent, /*InsnID*/0,
12116
      // GIR_Coverage, 5468,
12117
0
      GIR_Done,
12118
    // Label 706: @36528
12119
0
    GIM_Try, /*On fail goto*//*Label 707*/ GIMT_Encode4(36595), // Rule ID 5469 //
12120
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12121
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12122
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12123
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12124
      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
12125
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12126
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12127
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
12128
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12129
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
12130
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12131
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12132
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12133
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12134
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12135
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12136
0
      GIR_EraseFromParent, /*InsnID*/0,
12137
      // GIR_Coverage, 5469,
12138
0
      GIR_Done,
12139
    // Label 707: @36595
12140
0
    GIM_Try, /*On fail goto*//*Label 708*/ GIMT_Encode4(36662), // Rule ID 5470 //
12141
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12142
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12143
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12144
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12145
      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src)  =>  (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src)
12146
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12147
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12148
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
12149
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
12150
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
12151
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12152
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12153
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12154
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12155
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12156
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12157
0
      GIR_EraseFromParent, /*InsnID*/0,
12158
      // GIR_Coverage, 5470,
12159
0
      GIR_Done,
12160
    // Label 708: @36662
12161
0
    GIM_Reject,
12162
    // Label 519: @36663
12163
0
    GIM_Try, /*On fail goto*//*Label 709*/ GIMT_Encode4(36705), // Rule ID 2802 //
12164
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12165
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
12166
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12167
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12168
      // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v8i8] }:$src
12169
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12170
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12171
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12172
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12173
0
      GIR_EraseFromParent, /*InsnID*/0,
12174
      // GIR_Coverage, 2802,
12175
0
      GIR_Done,
12176
    // Label 709: @36705
12177
0
    GIM_Try, /*On fail goto*//*Label 710*/ GIMT_Encode4(36747), // Rule ID 2803 //
12178
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12179
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
12180
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12181
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12182
      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[v8i8] }:$src
12183
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12184
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12185
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12186
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12187
0
      GIR_EraseFromParent, /*InsnID*/0,
12188
      // GIR_Coverage, 2803,
12189
0
      GIR_Done,
12190
    // Label 710: @36747
12191
0
    GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(36789), // Rule ID 2804 //
12192
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12193
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
12194
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12195
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12196
      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[v8i8] }:$src
12197
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12198
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12199
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12200
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12201
0
      GIR_EraseFromParent, /*InsnID*/0,
12202
      // GIR_Coverage, 2804,
12203
0
      GIR_Done,
12204
    // Label 711: @36789
12205
0
    GIM_Try, /*On fail goto*//*Label 712*/ GIMT_Encode4(36831), // Rule ID 2805 //
12206
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12207
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
12208
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12209
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12210
      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[v8i8] }:$src
12211
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12212
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12213
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12214
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12215
0
      GIR_EraseFromParent, /*InsnID*/0,
12216
      // GIR_Coverage, 2805,
12217
0
      GIR_Done,
12218
    // Label 712: @36831
12219
0
    GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(36873), // Rule ID 2806 //
12220
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12221
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
12222
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12223
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12224
      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src)  =>  DPR:{ *:[v8i8] }:$src
12225
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12226
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12227
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12228
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12229
0
      GIR_EraseFromParent, /*InsnID*/0,
12230
      // GIR_Coverage, 2806,
12231
0
      GIR_Done,
12232
    // Label 713: @36873
12233
0
    GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(36915), // Rule ID 2807 //
12234
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12235
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
12236
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12237
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12238
      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4bf16] }:$src)  =>  DPR:{ *:[v8i8] }:$src
12239
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12240
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12241
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12242
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12243
0
      GIR_EraseFromParent, /*InsnID*/0,
12244
      // GIR_Coverage, 2807,
12245
0
      GIR_Done,
12246
    // Label 714: @36915
12247
0
    GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(36957), // Rule ID 2808 //
12248
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12249
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
12250
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12251
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12252
      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[v8i8] }:$src
12253
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12254
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12255
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12256
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12257
0
      GIR_EraseFromParent, /*InsnID*/0,
12258
      // GIR_Coverage, 2808,
12259
0
      GIR_Done,
12260
    // Label 715: @36957
12261
0
    GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(37005), // Rule ID 2894 //
12262
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12263
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
12264
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12265
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12266
      // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src)  =>  (VREV64d8:{ *:[v8i8] } DPR:{ *:[f64] }:$src)
12267
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d8),
12268
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
12269
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12270
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12271
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12272
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12273
0
      GIR_EraseFromParent, /*InsnID*/0,
12274
      // GIR_Coverage, 2894,
12275
0
      GIR_Done,
12276
    // Label 716: @37005
12277
0
    GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(37053), // Rule ID 2895 //
12278
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12279
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
12280
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12281
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12282
      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src)  =>  (VREV64d8:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src)
12283
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64d8),
12284
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
12285
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12286
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12287
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12288
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12289
0
      GIR_EraseFromParent, /*InsnID*/0,
12290
      // GIR_Coverage, 2895,
12291
0
      GIR_Done,
12292
    // Label 717: @37053
12293
0
    GIM_Try, /*On fail goto*//*Label 718*/ GIMT_Encode4(37101), // Rule ID 2896 //
12294
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12295
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
12296
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12297
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12298
      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src)  =>  (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src)
12299
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32d8),
12300
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
12301
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12302
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12303
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12304
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12305
0
      GIR_EraseFromParent, /*InsnID*/0,
12306
      // GIR_Coverage, 2896,
12307
0
      GIR_Done,
12308
    // Label 718: @37101
12309
0
    GIM_Try, /*On fail goto*//*Label 719*/ GIMT_Encode4(37149), // Rule ID 2897 //
12310
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12311
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
12312
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12313
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12314
      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src)  =>  (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src)
12315
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32d8),
12316
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
12317
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12318
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12319
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12320
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12321
0
      GIR_EraseFromParent, /*InsnID*/0,
12322
      // GIR_Coverage, 2897,
12323
0
      GIR_Done,
12324
    // Label 719: @37149
12325
0
    GIM_Try, /*On fail goto*//*Label 720*/ GIMT_Encode4(37197), // Rule ID 2898 //
12326
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12327
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
12328
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12329
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12330
      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src)  =>  (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src)
12331
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV16d8),
12332
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
12333
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12334
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12335
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12336
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12337
0
      GIR_EraseFromParent, /*InsnID*/0,
12338
      // GIR_Coverage, 2898,
12339
0
      GIR_Done,
12340
    // Label 720: @37197
12341
0
    GIM_Try, /*On fail goto*//*Label 721*/ GIMT_Encode4(37245), // Rule ID 2899 //
12342
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12343
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
12344
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12345
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12346
      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4bf16] }:$src)  =>  (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4bf16] }:$src)
12347
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV16d8),
12348
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
12349
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12350
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12351
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12352
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12353
0
      GIR_EraseFromParent, /*InsnID*/0,
12354
      // GIR_Coverage, 2899,
12355
0
      GIR_Done,
12356
    // Label 721: @37245
12357
0
    GIM_Try, /*On fail goto*//*Label 722*/ GIMT_Encode4(37293), // Rule ID 2900 //
12358
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12359
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
12360
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12361
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12362
      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src)  =>  (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src)
12363
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV16d8),
12364
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
12365
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12366
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12367
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12368
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12369
0
      GIR_EraseFromParent, /*InsnID*/0,
12370
      // GIR_Coverage, 2900,
12371
0
      GIR_Done,
12372
    // Label 722: @37293
12373
0
    GIM_Reject,
12374
    // Label 520: @37294
12375
0
    GIM_Try, /*On fail goto*//*Label 723*/ GIMT_Encode4(37336), // Rule ID 2759 //
12376
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12377
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12378
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12379
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12380
      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v8f16] }:$src)  =>  QPR:{ *:[v8i16] }:$src
12381
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12382
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12383
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12384
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12385
0
      GIR_EraseFromParent, /*InsnID*/0,
12386
      // GIR_Coverage, 2759,
12387
0
      GIR_Done,
12388
    // Label 723: @37336
12389
0
    GIM_Try, /*On fail goto*//*Label 724*/ GIMT_Encode4(37378), // Rule ID 2760 //
12390
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12391
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12392
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12393
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12394
      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v8f16] }:$src
12395
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12396
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12397
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12398
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12399
0
      GIR_EraseFromParent, /*InsnID*/0,
12400
      // GIR_Coverage, 2760,
12401
0
      GIR_Done,
12402
    // Label 724: @37378
12403
0
    GIM_Try, /*On fail goto*//*Label 725*/ GIMT_Encode4(37420), // Rule ID 2761 //
12404
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12405
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12406
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12407
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12408
      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v8bf16] }:$src)  =>  QPR:{ *:[v8i16] }:$src
12409
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12410
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12411
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12412
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12413
0
      GIR_EraseFromParent, /*InsnID*/0,
12414
      // GIR_Coverage, 2761,
12415
0
      GIR_Done,
12416
    // Label 725: @37420
12417
0
    GIM_Try, /*On fail goto*//*Label 726*/ GIMT_Encode4(37462), // Rule ID 2762 //
12418
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12419
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12420
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12421
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12422
      // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v8bf16] }:$src
12423
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12424
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12425
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12426
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12427
0
      GIR_EraseFromParent, /*InsnID*/0,
12428
      // GIR_Coverage, 2762,
12429
0
      GIR_Done,
12430
    // Label 726: @37462
12431
0
    GIM_Try, /*On fail goto*//*Label 727*/ GIMT_Encode4(37504), // Rule ID 2833 //
12432
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12433
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12434
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12435
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12436
      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v8f16] }:$src
12437
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12438
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12439
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12440
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12441
0
      GIR_EraseFromParent, /*InsnID*/0,
12442
      // GIR_Coverage, 2833,
12443
0
      GIR_Done,
12444
    // Label 727: @37504
12445
0
    GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(37546), // Rule ID 2834 //
12446
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12447
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12448
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12449
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12450
      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v8f16] }:$src
12451
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12452
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12453
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12454
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12455
0
      GIR_EraseFromParent, /*InsnID*/0,
12456
      // GIR_Coverage, 2834,
12457
0
      GIR_Done,
12458
    // Label 728: @37546
12459
0
    GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(37588), // Rule ID 2835 //
12460
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12461
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12462
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12463
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12464
      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v8f16] }:$src
12465
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12466
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12467
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12468
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12469
0
      GIR_EraseFromParent, /*InsnID*/0,
12470
      // GIR_Coverage, 2835,
12471
0
      GIR_Done,
12472
    // Label 729: @37588
12473
0
    GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(37630), // Rule ID 2836 //
12474
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12475
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12476
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12477
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12478
      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v8f16] }:$src
12479
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12480
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12481
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12482
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12483
0
      GIR_EraseFromParent, /*InsnID*/0,
12484
      // GIR_Coverage, 2836,
12485
0
      GIR_Done,
12486
    // Label 730: @37630
12487
0
    GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(37672), // Rule ID 2837 //
12488
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12489
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12490
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12491
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12492
      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v8f16] }:$src
12493
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12494
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12495
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12496
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12497
0
      GIR_EraseFromParent, /*InsnID*/0,
12498
      // GIR_Coverage, 2837,
12499
0
      GIR_Done,
12500
    // Label 731: @37672
12501
0
    GIM_Try, /*On fail goto*//*Label 732*/ GIMT_Encode4(37714), // Rule ID 2838 //
12502
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12503
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12504
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12505
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12506
      // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v8bf16] }:$src
12507
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12508
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12509
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12510
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12511
0
      GIR_EraseFromParent, /*InsnID*/0,
12512
      // GIR_Coverage, 2838,
12513
0
      GIR_Done,
12514
    // Label 732: @37714
12515
0
    GIM_Try, /*On fail goto*//*Label 733*/ GIMT_Encode4(37756), // Rule ID 2839 //
12516
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12517
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12518
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12519
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12520
      // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v8bf16] }:$src
12521
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12522
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12523
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12524
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12525
0
      GIR_EraseFromParent, /*InsnID*/0,
12526
      // GIR_Coverage, 2839,
12527
0
      GIR_Done,
12528
    // Label 733: @37756
12529
0
    GIM_Try, /*On fail goto*//*Label 734*/ GIMT_Encode4(37798), // Rule ID 2840 //
12530
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12531
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12532
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12533
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12534
      // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v8bf16] }:$src
12535
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12536
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12537
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12538
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12539
0
      GIR_EraseFromParent, /*InsnID*/0,
12540
      // GIR_Coverage, 2840,
12541
0
      GIR_Done,
12542
    // Label 734: @37798
12543
0
    GIM_Try, /*On fail goto*//*Label 735*/ GIMT_Encode4(37840), // Rule ID 2841 //
12544
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12545
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12546
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12547
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12548
      // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v8bf16] }:$src
12549
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12550
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12551
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12552
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12553
0
      GIR_EraseFromParent, /*InsnID*/0,
12554
      // GIR_Coverage, 2841,
12555
0
      GIR_Done,
12556
    // Label 735: @37840
12557
0
    GIM_Try, /*On fail goto*//*Label 736*/ GIMT_Encode4(37882), // Rule ID 2842 //
12558
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12559
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12560
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12561
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12562
      // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v8bf16] }:$src
12563
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12564
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12565
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12566
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12567
0
      GIR_EraseFromParent, /*InsnID*/0,
12568
      // GIR_Coverage, 2842,
12569
0
      GIR_Done,
12570
    // Label 736: @37882
12571
0
    GIM_Try, /*On fail goto*//*Label 737*/ GIMT_Encode4(37924), // Rule ID 2843 //
12572
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12573
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12574
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12575
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12576
      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v8i16] }:$src
12577
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12578
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12579
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12580
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12581
0
      GIR_EraseFromParent, /*InsnID*/0,
12582
      // GIR_Coverage, 2843,
12583
0
      GIR_Done,
12584
    // Label 737: @37924
12585
0
    GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(37966), // Rule ID 2844 //
12586
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12587
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12588
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12589
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12590
      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v8i16] }:$src
12591
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12592
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12593
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12594
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12595
0
      GIR_EraseFromParent, /*InsnID*/0,
12596
      // GIR_Coverage, 2844,
12597
0
      GIR_Done,
12598
    // Label 738: @37966
12599
0
    GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(38008), // Rule ID 2845 //
12600
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12601
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12602
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12603
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12604
      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v8i16] }:$src
12605
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12606
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12607
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12608
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12609
0
      GIR_EraseFromParent, /*InsnID*/0,
12610
      // GIR_Coverage, 2845,
12611
0
      GIR_Done,
12612
    // Label 739: @38008
12613
0
    GIM_Try, /*On fail goto*//*Label 740*/ GIMT_Encode4(38050), // Rule ID 2846 //
12614
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12615
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12616
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12617
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12618
      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v8i16] }:$src
12619
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12620
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12621
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12622
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12623
0
      GIR_EraseFromParent, /*InsnID*/0,
12624
      // GIR_Coverage, 2846,
12625
0
      GIR_Done,
12626
    // Label 740: @38050
12627
0
    GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(38092), // Rule ID 2847 //
12628
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12629
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12630
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12631
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12632
      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v8i16] }:$src
12633
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12634
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12635
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12636
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12637
0
      GIR_EraseFromParent, /*InsnID*/0,
12638
      // GIR_Coverage, 2847,
12639
0
      GIR_Done,
12640
    // Label 741: @38092
12641
0
    GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(38140), // Rule ID 2925 //
12642
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12643
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12644
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12645
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12646
      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src)  =>  (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src)
12647
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
12648
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
12649
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12650
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12651
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12652
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12653
0
      GIR_EraseFromParent, /*InsnID*/0,
12654
      // GIR_Coverage, 2925,
12655
0
      GIR_Done,
12656
    // Label 742: @38140
12657
0
    GIM_Try, /*On fail goto*//*Label 743*/ GIMT_Encode4(38188), // Rule ID 2926 //
12658
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12659
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12660
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12661
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12662
      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src)  =>  (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src)
12663
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
12664
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
12665
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12666
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12667
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12668
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12669
0
      GIR_EraseFromParent, /*InsnID*/0,
12670
      // GIR_Coverage, 2926,
12671
0
      GIR_Done,
12672
    // Label 743: @38188
12673
0
    GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(38236), // Rule ID 2927 //
12674
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12675
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12676
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12677
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12678
      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src)  =>  (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src)
12679
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
12680
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
12681
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12682
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12683
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12684
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12685
0
      GIR_EraseFromParent, /*InsnID*/0,
12686
      // GIR_Coverage, 2927,
12687
0
      GIR_Done,
12688
    // Label 744: @38236
12689
0
    GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(38284), // Rule ID 2928 //
12690
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12691
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12692
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12693
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12694
      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src)  =>  (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src)
12695
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
12696
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
12697
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12698
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12699
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12700
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12701
0
      GIR_EraseFromParent, /*InsnID*/0,
12702
      // GIR_Coverage, 2928,
12703
0
      GIR_Done,
12704
    // Label 745: @38284
12705
0
    GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(38332), // Rule ID 2929 //
12706
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12707
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12708
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12709
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12710
      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src)  =>  (VREV16q8:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src)
12711
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV16q8),
12712
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
12713
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12714
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12715
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12716
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12717
0
      GIR_EraseFromParent, /*InsnID*/0,
12718
      // GIR_Coverage, 2929,
12719
0
      GIR_Done,
12720
    // Label 746: @38332
12721
0
    GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(38380), // Rule ID 2930 //
12722
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12723
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12724
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12725
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12726
      // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v2f64] }:$src)  =>  (VREV64q16:{ *:[v8bf16] } QPR:{ *:[v2f64] }:$src)
12727
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
12728
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
12729
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12730
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12731
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12732
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12733
0
      GIR_EraseFromParent, /*InsnID*/0,
12734
      // GIR_Coverage, 2930,
12735
0
      GIR_Done,
12736
    // Label 747: @38380
12737
0
    GIM_Try, /*On fail goto*//*Label 748*/ GIMT_Encode4(38428), // Rule ID 2931 //
12738
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12739
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12740
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12741
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12742
      // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v2i64] }:$src)  =>  (VREV64q16:{ *:[v8bf16] } QPR:{ *:[v2i64] }:$src)
12743
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
12744
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
12745
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12746
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12747
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12748
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12749
0
      GIR_EraseFromParent, /*InsnID*/0,
12750
      // GIR_Coverage, 2931,
12751
0
      GIR_Done,
12752
    // Label 748: @38428
12753
0
    GIM_Try, /*On fail goto*//*Label 749*/ GIMT_Encode4(38476), // Rule ID 2932 //
12754
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12755
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12756
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12757
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12758
      // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v4f32] }:$src)  =>  (VREV32q16:{ *:[v8bf16] } QPR:{ *:[v4f32] }:$src)
12759
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
12760
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
12761
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12762
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12763
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12764
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12765
0
      GIR_EraseFromParent, /*InsnID*/0,
12766
      // GIR_Coverage, 2932,
12767
0
      GIR_Done,
12768
    // Label 749: @38476
12769
0
    GIM_Try, /*On fail goto*//*Label 750*/ GIMT_Encode4(38524), // Rule ID 2933 //
12770
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12771
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12772
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12773
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12774
      // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v4i32] }:$src)  =>  (VREV32q16:{ *:[v8bf16] } QPR:{ *:[v4i32] }:$src)
12775
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
12776
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
12777
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12778
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12779
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12780
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12781
0
      GIR_EraseFromParent, /*InsnID*/0,
12782
      // GIR_Coverage, 2933,
12783
0
      GIR_Done,
12784
    // Label 750: @38524
12785
0
    GIM_Try, /*On fail goto*//*Label 751*/ GIMT_Encode4(38572), // Rule ID 2934 //
12786
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12787
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12788
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12789
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12790
      // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v16i8] }:$src)  =>  (VREV16q8:{ *:[v8bf16] } QPR:{ *:[v16i8] }:$src)
12791
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV16q8),
12792
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
12793
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12794
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12795
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12796
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12797
0
      GIR_EraseFromParent, /*InsnID*/0,
12798
      // GIR_Coverage, 2934,
12799
0
      GIR_Done,
12800
    // Label 751: @38572
12801
0
    GIM_Try, /*On fail goto*//*Label 752*/ GIMT_Encode4(38620), // Rule ID 2935 //
12802
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12803
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12804
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12805
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12806
      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src)  =>  (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src)
12807
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
12808
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
12809
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12810
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12811
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12812
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12813
0
      GIR_EraseFromParent, /*InsnID*/0,
12814
      // GIR_Coverage, 2935,
12815
0
      GIR_Done,
12816
    // Label 752: @38620
12817
0
    GIM_Try, /*On fail goto*//*Label 753*/ GIMT_Encode4(38668), // Rule ID 2936 //
12818
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12819
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12820
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12821
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12822
      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src)  =>  (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src)
12823
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
12824
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
12825
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12826
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12827
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12828
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12829
0
      GIR_EraseFromParent, /*InsnID*/0,
12830
      // GIR_Coverage, 2936,
12831
0
      GIR_Done,
12832
    // Label 753: @38668
12833
0
    GIM_Try, /*On fail goto*//*Label 754*/ GIMT_Encode4(38716), // Rule ID 2937 //
12834
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12835
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12836
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12837
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12838
      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src)  =>  (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src)
12839
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
12840
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
12841
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12842
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12843
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12844
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12845
0
      GIR_EraseFromParent, /*InsnID*/0,
12846
      // GIR_Coverage, 2937,
12847
0
      GIR_Done,
12848
    // Label 754: @38716
12849
0
    GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(38764), // Rule ID 2938 //
12850
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12851
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12852
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12853
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12854
      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src)  =>  (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src)
12855
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
12856
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
12857
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12858
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12859
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12860
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12861
0
      GIR_EraseFromParent, /*InsnID*/0,
12862
      // GIR_Coverage, 2938,
12863
0
      GIR_Done,
12864
    // Label 755: @38764
12865
0
    GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(38812), // Rule ID 2939 //
12866
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12867
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12868
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12869
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12870
      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src)  =>  (VREV16q8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src)
12871
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV16q8),
12872
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
12873
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12874
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12875
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12876
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12877
0
      GIR_EraseFromParent, /*InsnID*/0,
12878
      // GIR_Coverage, 2939,
12879
0
      GIR_Done,
12880
    // Label 756: @38812
12881
0
    GIM_Try, /*On fail goto*//*Label 757*/ GIMT_Encode4(38854), // Rule ID 5413 //
12882
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
12883
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12884
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12885
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12886
      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)  =>  MQPR:{ *:[v8i16] }:$src
12887
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12888
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12889
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12890
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12891
0
      GIR_EraseFromParent, /*InsnID*/0,
12892
      // GIR_Coverage, 5413,
12893
0
      GIR_Done,
12894
    // Label 757: @38854
12895
0
    GIM_Try, /*On fail goto*//*Label 758*/ GIMT_Encode4(38896), // Rule ID 5414 //
12896
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
12897
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12898
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12899
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12900
      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)  =>  MQPR:{ *:[v8f16] }:$src
12901
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12902
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12903
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12904
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12905
0
      GIR_EraseFromParent, /*InsnID*/0,
12906
      // GIR_Coverage, 5414,
12907
0
      GIR_Done,
12908
    // Label 758: @38896
12909
0
    GIM_Try, /*On fail goto*//*Label 759*/ GIMT_Encode4(38938), // Rule ID 5435 //
12910
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12911
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12912
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12913
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12914
      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src)  =>  MQPR:{ *:[v8f16] }:$src
12915
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12916
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12917
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12918
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12919
0
      GIR_EraseFromParent, /*InsnID*/0,
12920
      // GIR_Coverage, 5435,
12921
0
      GIR_Done,
12922
    // Label 759: @38938
12923
0
    GIM_Try, /*On fail goto*//*Label 760*/ GIMT_Encode4(38980), // Rule ID 5436 //
12924
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12925
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12926
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12927
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12928
      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src)  =>  MQPR:{ *:[v8f16] }:$src
12929
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12930
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12931
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12932
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12933
0
      GIR_EraseFromParent, /*InsnID*/0,
12934
      // GIR_Coverage, 5436,
12935
0
      GIR_Done,
12936
    // Label 760: @38980
12937
0
    GIM_Try, /*On fail goto*//*Label 761*/ GIMT_Encode4(39022), // Rule ID 5437 //
12938
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12939
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12940
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12941
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12942
      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src)  =>  MQPR:{ *:[v8f16] }:$src
12943
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12944
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12945
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12946
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12947
0
      GIR_EraseFromParent, /*InsnID*/0,
12948
      // GIR_Coverage, 5437,
12949
0
      GIR_Done,
12950
    // Label 761: @39022
12951
0
    GIM_Try, /*On fail goto*//*Label 762*/ GIMT_Encode4(39064), // Rule ID 5438 //
12952
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12953
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12954
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12955
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12956
      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src)  =>  MQPR:{ *:[v8f16] }:$src
12957
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12958
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12959
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12960
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12961
0
      GIR_EraseFromParent, /*InsnID*/0,
12962
      // GIR_Coverage, 5438,
12963
0
      GIR_Done,
12964
    // Label 762: @39064
12965
0
    GIM_Try, /*On fail goto*//*Label 763*/ GIMT_Encode4(39106), // Rule ID 5439 //
12966
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12967
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12968
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12969
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12970
      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src)  =>  MQPR:{ *:[v8f16] }:$src
12971
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12972
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12973
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12974
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12975
0
      GIR_EraseFromParent, /*InsnID*/0,
12976
      // GIR_Coverage, 5439,
12977
0
      GIR_Done,
12978
    // Label 763: @39106
12979
0
    GIM_Try, /*On fail goto*//*Label 764*/ GIMT_Encode4(39148), // Rule ID 5440 //
12980
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12981
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12982
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12983
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12984
      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src)  =>  MQPR:{ *:[v8i16] }:$src
12985
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12986
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12987
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12988
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12989
0
      GIR_EraseFromParent, /*InsnID*/0,
12990
      // GIR_Coverage, 5440,
12991
0
      GIR_Done,
12992
    // Label 764: @39148
12993
0
    GIM_Try, /*On fail goto*//*Label 765*/ GIMT_Encode4(39190), // Rule ID 5441 //
12994
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12995
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12996
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12997
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12998
      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src)  =>  MQPR:{ *:[v8i16] }:$src
12999
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13000
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13001
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13002
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13003
0
      GIR_EraseFromParent, /*InsnID*/0,
13004
      // GIR_Coverage, 5441,
13005
0
      GIR_Done,
13006
    // Label 765: @39190
13007
0
    GIM_Try, /*On fail goto*//*Label 766*/ GIMT_Encode4(39232), // Rule ID 5442 //
13008
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13009
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13010
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13011
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13012
      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src)  =>  MQPR:{ *:[v8i16] }:$src
13013
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13014
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13015
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13016
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13017
0
      GIR_EraseFromParent, /*InsnID*/0,
13018
      // GIR_Coverage, 5442,
13019
0
      GIR_Done,
13020
    // Label 766: @39232
13021
0
    GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(39274), // Rule ID 5443 //
13022
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13023
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13024
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13025
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13026
      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src)  =>  MQPR:{ *:[v8i16] }:$src
13027
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13028
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13029
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13030
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13031
0
      GIR_EraseFromParent, /*InsnID*/0,
13032
      // GIR_Coverage, 5443,
13033
0
      GIR_Done,
13034
    // Label 767: @39274
13035
0
    GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(39316), // Rule ID 5444 //
13036
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13037
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
13038
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13039
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13040
      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)  =>  MQPR:{ *:[v8i16] }:$src
13041
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13042
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13043
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13044
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13045
0
      GIR_EraseFromParent, /*InsnID*/0,
13046
      // GIR_Coverage, 5444,
13047
0
      GIR_Done,
13048
    // Label 768: @39316
13049
0
    GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(39383), // Rule ID 5471 //
13050
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13051
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13052
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13053
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13054
      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src)  =>  (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src)
13055
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13056
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13057
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
13058
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
13059
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
13060
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13061
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13062
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13063
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13064
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13065
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13066
0
      GIR_EraseFromParent, /*InsnID*/0,
13067
      // GIR_Coverage, 5471,
13068
0
      GIR_Done,
13069
    // Label 769: @39383
13070
0
    GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(39450), // Rule ID 5472 //
13071
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13072
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13073
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13074
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13075
      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src)  =>  (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src)
13076
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13077
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13078
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
13079
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
13080
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
13081
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13082
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13083
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13084
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13085
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13086
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13087
0
      GIR_EraseFromParent, /*InsnID*/0,
13088
      // GIR_Coverage, 5472,
13089
0
      GIR_Done,
13090
    // Label 770: @39450
13091
0
    GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(39517), // Rule ID 5473 //
13092
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13093
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13094
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13095
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13096
      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src)  =>  (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src)
13097
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13098
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13099
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
13100
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
13101
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
13102
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13103
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13104
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13105
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13106
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13107
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13108
0
      GIR_EraseFromParent, /*InsnID*/0,
13109
      // GIR_Coverage, 5473,
13110
0
      GIR_Done,
13111
    // Label 771: @39517
13112
0
    GIM_Try, /*On fail goto*//*Label 772*/ GIMT_Encode4(39584), // Rule ID 5474 //
13113
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13114
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13115
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13116
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13117
      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src)
13118
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13119
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13120
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
13121
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
13122
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
13123
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13124
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13125
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13126
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13127
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13128
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13129
0
      GIR_EraseFromParent, /*InsnID*/0,
13130
      // GIR_Coverage, 5474,
13131
0
      GIR_Done,
13132
    // Label 772: @39584
13133
0
    GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(39651), // Rule ID 5475 //
13134
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13135
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
13136
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13137
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13138
      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src)  =>  (MVE_VREV16_8:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src)
13139
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13140
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13141
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
13142
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
13143
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
13144
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13145
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13146
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13147
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13148
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13149
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13150
0
      GIR_EraseFromParent, /*InsnID*/0,
13151
      // GIR_Coverage, 5475,
13152
0
      GIR_Done,
13153
    // Label 773: @39651
13154
0
    GIM_Try, /*On fail goto*//*Label 774*/ GIMT_Encode4(39718), // Rule ID 5476 //
13155
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13156
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13157
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13158
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13159
      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src)  =>  (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src)
13160
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13161
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13162
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
13163
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
13164
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
13165
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13166
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13167
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13168
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13169
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13170
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13171
0
      GIR_EraseFromParent, /*InsnID*/0,
13172
      // GIR_Coverage, 5476,
13173
0
      GIR_Done,
13174
    // Label 774: @39718
13175
0
    GIM_Try, /*On fail goto*//*Label 775*/ GIMT_Encode4(39785), // Rule ID 5477 //
13176
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13177
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13178
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13179
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13180
      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src)  =>  (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src)
13181
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13182
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13183
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
13184
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
13185
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
13186
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13187
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13188
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13189
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13190
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13191
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13192
0
      GIR_EraseFromParent, /*InsnID*/0,
13193
      // GIR_Coverage, 5477,
13194
0
      GIR_Done,
13195
    // Label 775: @39785
13196
0
    GIM_Try, /*On fail goto*//*Label 776*/ GIMT_Encode4(39852), // Rule ID 5478 //
13197
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13198
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13199
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13200
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13201
      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src)  =>  (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src)
13202
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13203
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13204
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
13205
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
13206
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
13207
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13208
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13209
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13210
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13211
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13212
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13213
0
      GIR_EraseFromParent, /*InsnID*/0,
13214
      // GIR_Coverage, 5478,
13215
0
      GIR_Done,
13216
    // Label 776: @39852
13217
0
    GIM_Try, /*On fail goto*//*Label 777*/ GIMT_Encode4(39919), // Rule ID 5479 //
13218
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13219
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13220
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13221
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13222
      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src)
13223
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13224
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13225
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
13226
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
13227
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
13228
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13229
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13230
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13231
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13232
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13233
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13234
0
      GIR_EraseFromParent, /*InsnID*/0,
13235
      // GIR_Coverage, 5479,
13236
0
      GIR_Done,
13237
    // Label 777: @39919
13238
0
    GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(39986), // Rule ID 5480 //
13239
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13240
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
13241
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13242
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13243
      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)  =>  (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
13244
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13245
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13246
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
13247
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
13248
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
13249
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13250
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13251
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13252
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13253
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13254
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13255
0
      GIR_EraseFromParent, /*InsnID*/0,
13256
      // GIR_Coverage, 5480,
13257
0
      GIR_Done,
13258
    // Label 778: @39986
13259
0
    GIM_Reject,
13260
    // Label 521: @39987
13261
0
    GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(40029), // Rule ID 2848 //
13262
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13263
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13264
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13265
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13266
      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v16i8] }:$src
13267
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13268
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13269
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13270
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13271
0
      GIR_EraseFromParent, /*InsnID*/0,
13272
      // GIR_Coverage, 2848,
13273
0
      GIR_Done,
13274
    // Label 779: @40029
13275
0
    GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(40071), // Rule ID 2849 //
13276
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13277
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13278
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13279
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13280
      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v16i8] }:$src
13281
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13282
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13283
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13284
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13285
0
      GIR_EraseFromParent, /*InsnID*/0,
13286
      // GIR_Coverage, 2849,
13287
0
      GIR_Done,
13288
    // Label 780: @40071
13289
0
    GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(40113), // Rule ID 2850 //
13290
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13291
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13292
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13293
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13294
      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v16i8] }:$src
13295
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13296
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13297
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13298
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13299
0
      GIR_EraseFromParent, /*InsnID*/0,
13300
      // GIR_Coverage, 2850,
13301
0
      GIR_Done,
13302
    // Label 781: @40113
13303
0
    GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(40155), // Rule ID 2851 //
13304
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13305
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13306
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13307
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13308
      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v16i8] }:$src
13309
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13310
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13311
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13312
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13313
0
      GIR_EraseFromParent, /*InsnID*/0,
13314
      // GIR_Coverage, 2851,
13315
0
      GIR_Done,
13316
    // Label 782: @40155
13317
0
    GIM_Try, /*On fail goto*//*Label 783*/ GIMT_Encode4(40197), // Rule ID 2852 //
13318
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13319
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13320
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13321
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13322
      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src)  =>  QPR:{ *:[v16i8] }:$src
13323
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13324
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13325
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13326
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13327
0
      GIR_EraseFromParent, /*InsnID*/0,
13328
      // GIR_Coverage, 2852,
13329
0
      GIR_Done,
13330
    // Label 783: @40197
13331
0
    GIM_Try, /*On fail goto*//*Label 784*/ GIMT_Encode4(40239), // Rule ID 2853 //
13332
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13333
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13334
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13335
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13336
      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8bf16] }:$src)  =>  QPR:{ *:[v16i8] }:$src
13337
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13338
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13339
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13340
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13341
0
      GIR_EraseFromParent, /*InsnID*/0,
13342
      // GIR_Coverage, 2853,
13343
0
      GIR_Done,
13344
    // Label 784: @40239
13345
0
    GIM_Try, /*On fail goto*//*Label 785*/ GIMT_Encode4(40281), // Rule ID 2854 //
13346
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13347
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13348
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13349
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13350
      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v16i8] }:$src
13351
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13352
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13353
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13354
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13355
0
      GIR_EraseFromParent, /*InsnID*/0,
13356
      // GIR_Coverage, 2854,
13357
0
      GIR_Done,
13358
    // Label 785: @40281
13359
0
    GIM_Try, /*On fail goto*//*Label 786*/ GIMT_Encode4(40329), // Rule ID 2940 //
13360
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13361
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13362
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13363
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13364
      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src)  =>  (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src)
13365
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q8),
13366
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
13367
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13368
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13369
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13370
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13371
0
      GIR_EraseFromParent, /*InsnID*/0,
13372
      // GIR_Coverage, 2940,
13373
0
      GIR_Done,
13374
    // Label 786: @40329
13375
0
    GIM_Try, /*On fail goto*//*Label 787*/ GIMT_Encode4(40377), // Rule ID 2941 //
13376
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13377
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13378
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13379
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13380
      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src)  =>  (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src)
13381
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV64q8),
13382
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
13383
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13384
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13385
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13386
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13387
0
      GIR_EraseFromParent, /*InsnID*/0,
13388
      // GIR_Coverage, 2941,
13389
0
      GIR_Done,
13390
    // Label 787: @40377
13391
0
    GIM_Try, /*On fail goto*//*Label 788*/ GIMT_Encode4(40425), // Rule ID 2942 //
13392
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13393
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13394
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13395
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13396
      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src)  =>  (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src)
13397
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32q8),
13398
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
13399
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13400
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13401
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13402
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13403
0
      GIR_EraseFromParent, /*InsnID*/0,
13404
      // GIR_Coverage, 2942,
13405
0
      GIR_Done,
13406
    // Label 788: @40425
13407
0
    GIM_Try, /*On fail goto*//*Label 789*/ GIMT_Encode4(40473), // Rule ID 2943 //
13408
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13409
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13410
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13411
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13412
      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src)  =>  (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src)
13413
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV32q8),
13414
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
13415
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13416
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13417
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13418
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13419
0
      GIR_EraseFromParent, /*InsnID*/0,
13420
      // GIR_Coverage, 2943,
13421
0
      GIR_Done,
13422
    // Label 789: @40473
13423
0
    GIM_Try, /*On fail goto*//*Label 790*/ GIMT_Encode4(40521), // Rule ID 2944 //
13424
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13425
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13426
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13427
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13428
      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src)  =>  (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src)
13429
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV16q8),
13430
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
13431
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13432
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13433
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13434
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13435
0
      GIR_EraseFromParent, /*InsnID*/0,
13436
      // GIR_Coverage, 2944,
13437
0
      GIR_Done,
13438
    // Label 790: @40521
13439
0
    GIM_Try, /*On fail goto*//*Label 791*/ GIMT_Encode4(40569), // Rule ID 2945 //
13440
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13441
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13442
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13443
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13444
      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8bf16] }:$src)  =>  (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8bf16] }:$src)
13445
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV16q8),
13446
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
13447
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13448
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13449
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13450
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13451
0
      GIR_EraseFromParent, /*InsnID*/0,
13452
      // GIR_Coverage, 2945,
13453
0
      GIR_Done,
13454
    // Label 791: @40569
13455
0
    GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(40617), // Rule ID 2946 //
13456
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13457
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13458
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13459
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13460
      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src)  =>  (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src)
13461
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VREV16q8),
13462
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
13463
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13464
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13465
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13466
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13467
0
      GIR_EraseFromParent, /*InsnID*/0,
13468
      // GIR_Coverage, 2946,
13469
0
      GIR_Done,
13470
    // Label 792: @40617
13471
0
    GIM_Try, /*On fail goto*//*Label 793*/ GIMT_Encode4(40659), // Rule ID 5445 //
13472
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13473
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13474
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13475
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13476
      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src)  =>  MQPR:{ *:[v16i8] }:$src
13477
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13478
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13479
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13480
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13481
0
      GIR_EraseFromParent, /*InsnID*/0,
13482
      // GIR_Coverage, 5445,
13483
0
      GIR_Done,
13484
    // Label 793: @40659
13485
0
    GIM_Try, /*On fail goto*//*Label 794*/ GIMT_Encode4(40701), // Rule ID 5446 //
13486
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13487
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13488
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13489
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13490
      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src)  =>  MQPR:{ *:[v16i8] }:$src
13491
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13492
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13493
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13494
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13495
0
      GIR_EraseFromParent, /*InsnID*/0,
13496
      // GIR_Coverage, 5446,
13497
0
      GIR_Done,
13498
    // Label 794: @40701
13499
0
    GIM_Try, /*On fail goto*//*Label 795*/ GIMT_Encode4(40743), // Rule ID 5447 //
13500
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13501
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13502
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13503
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13504
      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src)  =>  MQPR:{ *:[v16i8] }:$src
13505
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13506
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13507
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13508
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13509
0
      GIR_EraseFromParent, /*InsnID*/0,
13510
      // GIR_Coverage, 5447,
13511
0
      GIR_Done,
13512
    // Label 795: @40743
13513
0
    GIM_Try, /*On fail goto*//*Label 796*/ GIMT_Encode4(40785), // Rule ID 5448 //
13514
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13515
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13516
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13517
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13518
      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src)  =>  MQPR:{ *:[v16i8] }:$src
13519
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13520
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13521
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13522
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13523
0
      GIR_EraseFromParent, /*InsnID*/0,
13524
      // GIR_Coverage, 5448,
13525
0
      GIR_Done,
13526
    // Label 796: @40785
13527
0
    GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(40827), // Rule ID 5449 //
13528
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13529
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13530
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13531
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13532
      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src)  =>  MQPR:{ *:[v16i8] }:$src
13533
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13534
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13535
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13536
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13537
0
      GIR_EraseFromParent, /*InsnID*/0,
13538
      // GIR_Coverage, 5449,
13539
0
      GIR_Done,
13540
    // Label 797: @40827
13541
0
    GIM_Try, /*On fail goto*//*Label 798*/ GIMT_Encode4(40869), // Rule ID 5450 //
13542
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13543
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13544
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13545
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13546
      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src)  =>  MQPR:{ *:[v16i8] }:$src
13547
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13548
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13549
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13550
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13551
0
      GIR_EraseFromParent, /*InsnID*/0,
13552
      // GIR_Coverage, 5450,
13553
0
      GIR_Done,
13554
    // Label 798: @40869
13555
0
    GIM_Try, /*On fail goto*//*Label 799*/ GIMT_Encode4(40936), // Rule ID 5481 //
13556
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13557
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13558
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13559
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13560
      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src)  =>  (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src)
13561
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13562
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13563
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
13564
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8),
13565
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
13566
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13567
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13568
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13569
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13570
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13571
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13572
0
      GIR_EraseFromParent, /*InsnID*/0,
13573
      // GIR_Coverage, 5481,
13574
0
      GIR_Done,
13575
    // Label 799: @40936
13576
0
    GIM_Try, /*On fail goto*//*Label 800*/ GIMT_Encode4(41003), // Rule ID 5482 //
13577
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13578
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13579
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13580
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13581
      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src)  =>  (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src)
13582
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13583
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13584
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
13585
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8),
13586
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
13587
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13588
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13589
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13590
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13591
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13592
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13593
0
      GIR_EraseFromParent, /*InsnID*/0,
13594
      // GIR_Coverage, 5482,
13595
0
      GIR_Done,
13596
    // Label 800: @41003
13597
0
    GIM_Try, /*On fail goto*//*Label 801*/ GIMT_Encode4(41070), // Rule ID 5483 //
13598
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13599
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13600
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13601
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13602
      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src)  =>  (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src)
13603
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13604
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13605
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
13606
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
13607
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
13608
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13609
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13610
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13611
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13612
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13613
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13614
0
      GIR_EraseFromParent, /*InsnID*/0,
13615
      // GIR_Coverage, 5483,
13616
0
      GIR_Done,
13617
    // Label 801: @41070
13618
0
    GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(41137), // Rule ID 5484 //
13619
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13620
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13621
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13622
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13623
      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src)
13624
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13625
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13626
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
13627
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
13628
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
13629
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13630
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13631
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13632
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13633
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13634
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13635
0
      GIR_EraseFromParent, /*InsnID*/0,
13636
      // GIR_Coverage, 5484,
13637
0
      GIR_Done,
13638
    // Label 802: @41137
13639
0
    GIM_Try, /*On fail goto*//*Label 803*/ GIMT_Encode4(41204), // Rule ID 5485 //
13640
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13641
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13642
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13643
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13644
      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src)  =>  (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src)
13645
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13646
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13647
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
13648
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
13649
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
13650
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13651
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13652
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13653
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13654
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13655
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13656
0
      GIR_EraseFromParent, /*InsnID*/0,
13657
      // GIR_Coverage, 5485,
13658
0
      GIR_Done,
13659
    // Label 803: @41204
13660
0
    GIM_Try, /*On fail goto*//*Label 804*/ GIMT_Encode4(41271), // Rule ID 5486 //
13661
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13662
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13663
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13664
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13665
      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src)
13666
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13667
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13668
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
13669
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
13670
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
13671
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13672
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13673
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13674
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13675
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13676
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13677
0
      GIR_EraseFromParent, /*InsnID*/0,
13678
      // GIR_Coverage, 5486,
13679
0
      GIR_Done,
13680
    // Label 804: @41271
13681
0
    GIM_Reject,
13682
    // Label 522: @41272
13683
0
    GIM_Reject,
13684
    // Label 10: @41273
13685
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 810*/ GIMT_Encode4(41619),
13686
0
    /*GILLT_s16*//*Label 805*/ GIMT_Encode4(41336),
13687
0
    /*GILLT_s32*//*Label 806*/ GIMT_Encode4(41385),
13688
0
    /*GILLT_s64*//*Label 807*/ GIMT_Encode4(41434), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
13689
0
    /*GILLT_v4s32*//*Label 808*/ GIMT_Encode4(41483), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
13690
0
    /*GILLT_v8s16*//*Label 809*/ GIMT_Encode4(41551),
13691
    // Label 805: @41336
13692
0
    GIM_Try, /*On fail goto*//*Label 811*/ GIMT_Encode4(41384), // Rule ID 682 //
13693
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
13694
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
13695
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
13696
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
13697
      // (ftrunc:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VRINTZH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
13698
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZH),
13699
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
13700
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
13701
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13702
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13703
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13704
0
      GIR_EraseFromParent, /*InsnID*/0,
13705
      // GIR_Coverage, 682,
13706
0
      GIR_Done,
13707
    // Label 811: @41384
13708
0
    GIM_Reject,
13709
    // Label 806: @41385
13710
0
    GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(41433), // Rule ID 683 //
13711
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
13712
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13713
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
13714
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
13715
      // (ftrunc:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VRINTZS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
13716
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZS),
13717
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
13718
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
13719
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13720
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13721
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13722
0
      GIR_EraseFromParent, /*InsnID*/0,
13723
      // GIR_Coverage, 683,
13724
0
      GIR_Done,
13725
    // Label 812: @41433
13726
0
    GIM_Reject,
13727
    // Label 807: @41434
13728
0
    GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(41482), // Rule ID 684 //
13729
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
13730
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
13731
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13732
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13733
      // (ftrunc:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VRINTZD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
13734
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZD),
13735
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
13736
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
13737
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13738
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13739
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13740
0
      GIR_EraseFromParent, /*InsnID*/0,
13741
      // GIR_Coverage, 684,
13742
0
      GIR_Done,
13743
    // Label 813: @41482
13744
0
    GIM_Reject,
13745
    // Label 808: @41483
13746
0
    GIM_Try, /*On fail goto*//*Label 814*/ GIMT_Encode4(41550), // Rule ID 4106 //
13747
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
13748
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13749
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13750
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13751
      // (ftrunc:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)  =>  (MVE_VRINTf32Z:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
13752
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13753
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13754
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
13755
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32Z),
13756
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
13757
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
13758
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13759
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13760
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13761
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13762
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13763
0
      GIR_EraseFromParent, /*InsnID*/0,
13764
      // GIR_Coverage, 4106,
13765
0
      GIR_Done,
13766
    // Label 814: @41550
13767
0
    GIM_Reject,
13768
    // Label 809: @41551
13769
0
    GIM_Try, /*On fail goto*//*Label 815*/ GIMT_Encode4(41618), // Rule ID 4094 //
13770
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
13771
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13772
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13773
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13774
      // (ftrunc:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)  =>  (MVE_VRINTf16Z:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
13775
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13776
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13777
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
13778
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16Z),
13779
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
13780
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
13781
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13782
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13783
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13784
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13785
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13786
0
      GIR_EraseFromParent, /*InsnID*/0,
13787
      // GIR_Coverage, 4094,
13788
0
      GIR_Done,
13789
    // Label 815: @41618
13790
0
    GIM_Reject,
13791
    // Label 810: @41619
13792
0
    GIM_Reject,
13793
    // Label 11: @41620
13794
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 821*/ GIMT_Encode4(41912),
13795
0
    /*GILLT_s16*//*Label 816*/ GIMT_Encode4(41683),
13796
0
    /*GILLT_s32*//*Label 817*/ GIMT_Encode4(41714),
13797
0
    /*GILLT_s64*//*Label 818*/ GIMT_Encode4(41745), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
13798
0
    /*GILLT_v4s32*//*Label 819*/ GIMT_Encode4(41776), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
13799
0
    /*GILLT_v8s16*//*Label 820*/ GIMT_Encode4(41844),
13800
    // Label 816: @41683
13801
0
    GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(41713), // Rule ID 691 //
13802
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
13803
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
13804
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
13805
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
13806
      // (fround:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VRINTAH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
13807
0
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAH),
13808
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13809
      // GIR_Coverage, 691,
13810
0
      GIR_Done,
13811
    // Label 822: @41713
13812
0
    GIM_Reject,
13813
    // Label 817: @41714
13814
0
    GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(41744), // Rule ID 692 //
13815
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
13816
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13817
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
13818
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
13819
      // (fround:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VRINTAS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
13820
0
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAS),
13821
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13822
      // GIR_Coverage, 692,
13823
0
      GIR_Done,
13824
    // Label 823: @41744
13825
0
    GIM_Reject,
13826
    // Label 818: @41745
13827
0
    GIM_Try, /*On fail goto*//*Label 824*/ GIMT_Encode4(41775), // Rule ID 693 //
13828
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
13829
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
13830
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13831
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13832
      // (fround:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VRINTAD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
13833
0
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAD),
13834
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13835
      // GIR_Coverage, 693,
13836
0
      GIR_Done,
13837
    // Label 824: @41775
13838
0
    GIM_Reject,
13839
    // Label 819: @41776
13840
0
    GIM_Try, /*On fail goto*//*Label 825*/ GIMT_Encode4(41843), // Rule ID 4104 //
13841
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
13842
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13843
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13844
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13845
      // (fround:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)  =>  (MVE_VRINTf32A:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
13846
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13847
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13848
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
13849
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32A),
13850
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
13851
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
13852
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13853
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13854
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13855
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13856
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13857
0
      GIR_EraseFromParent, /*InsnID*/0,
13858
      // GIR_Coverage, 4104,
13859
0
      GIR_Done,
13860
    // Label 825: @41843
13861
0
    GIM_Reject,
13862
    // Label 820: @41844
13863
0
    GIM_Try, /*On fail goto*//*Label 826*/ GIMT_Encode4(41911), // Rule ID 4092 //
13864
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
13865
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13866
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13867
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13868
      // (fround:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)  =>  (MVE_VRINTf16A:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
13869
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13870
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13871
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
13872
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16A),
13873
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
13874
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
13875
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13876
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13877
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13878
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13879
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13880
0
      GIR_EraseFromParent, /*InsnID*/0,
13881
      // GIR_Coverage, 4092,
13882
0
      GIR_Done,
13883
    // Label 826: @41911
13884
0
    GIM_Reject,
13885
    // Label 821: @41912
13886
0
    GIM_Reject,
13887
    // Label 12: @41913
13888
0
    GIM_Try, /*On fail goto*//*Label 827*/ GIMT_Encode4(42087),
13889
0
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13890
0
      GIM_Try, /*On fail goto*//*Label 828*/ GIMT_Encode4(42004), // Rule ID 2070 //
13891
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
13892
0
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
13893
0
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
13894
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
13895
        // MIs[0] Rn
13896
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
13897
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
13898
        // (ld:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>  =>  (tLDRSB:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (tMOVi8:{ *:[i32] } 0:{ *:[i32] }))
13899
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
13900
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8),
13901
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
13902
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
13903
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
13904
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13905
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
13906
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::tLDRSB),
13907
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rt]
13908
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
13909
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13910
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13911
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13912
0
        GIR_EraseFromParent, /*InsnID*/0,
13913
        // GIR_Coverage, 2070,
13914
0
        GIR_Done,
13915
      // Label 828: @42004
13916
0
      GIM_Try, /*On fail goto*//*Label 829*/ GIMT_Encode4(42086), // Rule ID 2071 //
13917
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
13918
0
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
13919
0
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
13920
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
13921
        // MIs[0] Rn
13922
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
13923
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
13924
        // (ld:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (tLDRSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (tMOVi8:{ *:[i32] } 0:{ *:[i32] }))
13925
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
13926
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8),
13927
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
13928
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
13929
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
13930
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13931
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
13932
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::tLDRSH),
13933
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rt]
13934
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
13935
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13936
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13937
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13938
0
        GIR_EraseFromParent, /*InsnID*/0,
13939
        // GIR_Coverage, 2071,
13940
0
        GIR_Done,
13941
      // Label 829: @42086
13942
0
      GIM_Reject,
13943
    // Label 827: @42087
13944
0
    GIM_Reject,
13945
    // Label 13: @42088
13946
0
    GIM_Try, /*On fail goto*//*Label 830*/ GIMT_Encode4(42113), // Rule ID 5547 //
13947
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13948
      // MIs[0] Operand 0
13949
0
      GIM_CheckIsImm, /*MI*/0, /*Op*/0,
13950
0
      GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
13951
      // (atomic_fence (timm:{ *:[i32] }), 0:{ *:[i32] })  =>  (MEMBARRIER)
13952
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::MEMBARRIER),
13953
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13954
0
      GIR_EraseFromParent, /*InsnID*/0,
13955
      // GIR_Coverage, 5547,
13956
0
      GIR_Done,
13957
    // Label 830: @42113
13958
0
    GIM_Reject,
13959
    // Label 14: @42114
13960
0
    GIM_Try, /*On fail goto*//*Label 831*/ GIMT_Encode4(49540),
13961
0
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
13962
0
      GIM_Try, /*On fail goto*//*Label 832*/ GIMT_Encode4(42182), // Rule ID 1880 //
13963
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
13964
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtb16),
13965
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13966
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13967
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
13968
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
13969
        // (intrinsic_wo_chain:{ *:[i32] } 3265:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src)  =>  (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
13970
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UXTB16),
13971
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
13972
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Src
13973
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13974
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13975
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13976
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13977
0
        GIR_EraseFromParent, /*InsnID*/0,
13978
        // GIR_Coverage, 1880,
13979
0
        GIR_Done,
13980
      // Label 832: @42182
13981
0
      GIM_Try, /*On fail goto*//*Label 833*/ GIMT_Encode4(42242), // Rule ID 2123 //
13982
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
13983
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtb16),
13984
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13985
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13986
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
13987
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
13988
        // (intrinsic_wo_chain:{ *:[i32] } 3265:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm)  =>  (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
13989
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16),
13990
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
13991
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
13992
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13993
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13994
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13995
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13996
0
        GIR_EraseFromParent, /*InsnID*/0,
13997
        // GIR_Coverage, 2123,
13998
0
        GIR_Done,
13999
      // Label 833: @42242
14000
0
      GIM_Try, /*On fail goto*//*Label 834*/ GIMT_Encode4(42290), // Rule ID 694 //
14001
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
14002
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn),
14003
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
14004
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
14005
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
14006
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
14007
        // (intrinsic_wo_chain:{ *:[f16] } 3151:{ *:[iPTR] }, HPR:{ *:[f16] }:$Sm)  =>  (VRINTNH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
14008
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNH),
14009
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
14010
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
14011
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14012
0
        GIR_EraseFromParent, /*InsnID*/0,
14013
        // GIR_Coverage, 694,
14014
0
        GIR_Done,
14015
      // Label 834: @42290
14016
0
      GIM_Try, /*On fail goto*//*Label 835*/ GIMT_Encode4(42338), // Rule ID 695 //
14017
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
14018
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn),
14019
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14020
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14021
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14022
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14023
        // (intrinsic_wo_chain:{ *:[f32] } 3151:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm)  =>  (VRINTNS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
14024
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNS),
14025
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
14026
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
14027
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14028
0
        GIR_EraseFromParent, /*InsnID*/0,
14029
        // GIR_Coverage, 695,
14030
0
        GIR_Done,
14031
      // Label 835: @42338
14032
0
      GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(42386), // Rule ID 696 //
14033
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
14034
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn),
14035
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
14036
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
14037
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14038
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14039
        // (intrinsic_wo_chain:{ *:[f64] } 3151:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm)  =>  (VRINTND:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
14040
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTND),
14041
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
14042
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
14043
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14044
0
        GIR_EraseFromParent, /*InsnID*/0,
14045
        // GIR_Coverage, 696,
14046
0
        GIR_Done,
14047
      // Label 836: @42386
14048
0
      GIM_Try, /*On fail goto*//*Label 837*/ GIMT_Encode4(42443), // Rule ID 710 //
14049
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
14050
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtr),
14051
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14052
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
14053
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14054
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14055
        // (intrinsic_wo_chain:{ *:[f32] } 3266:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm)  =>  (VTOSIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
14056
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VTOSIRD),
14057
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
14058
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
14059
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14060
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14061
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14062
0
        GIR_EraseFromParent, /*InsnID*/0,
14063
        // GIR_Coverage, 710,
14064
0
        GIR_Done,
14065
      // Label 837: @42443
14066
0
      GIM_Try, /*On fail goto*//*Label 838*/ GIMT_Encode4(42500), // Rule ID 711 //
14067
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
14068
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtr),
14069
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14070
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14071
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14072
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14073
        // (intrinsic_wo_chain:{ *:[f32] } 3266:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm)  =>  (VTOSIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
14074
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VTOSIRS),
14075
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
14076
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
14077
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14078
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14079
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14080
0
        GIR_EraseFromParent, /*InsnID*/0,
14081
        // GIR_Coverage, 711,
14082
0
        GIR_Done,
14083
      // Label 838: @42500
14084
0
      GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(42557), // Rule ID 712 //
14085
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
14086
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtru),
14087
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14088
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
14089
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14090
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14091
        // (intrinsic_wo_chain:{ *:[f32] } 3267:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm)  =>  (VTOUIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
14092
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VTOUIRD),
14093
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
14094
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
14095
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14096
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14097
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14098
0
        GIR_EraseFromParent, /*InsnID*/0,
14099
        // GIR_Coverage, 712,
14100
0
        GIR_Done,
14101
      // Label 839: @42557
14102
0
      GIM_Try, /*On fail goto*//*Label 840*/ GIMT_Encode4(42614), // Rule ID 713 //
14103
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
14104
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtru),
14105
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14106
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14107
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14108
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14109
        // (intrinsic_wo_chain:{ *:[f32] } 3267:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm)  =>  (VTOUIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
14110
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VTOUIRS),
14111
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
14112
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
14113
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14114
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14115
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14116
0
        GIR_EraseFromParent, /*InsnID*/0,
14117
        // GIR_Coverage, 713,
14118
0
        GIR_Done,
14119
      // Label 840: @42614
14120
0
      GIM_Try, /*On fail goto*//*Label 841*/ GIMT_Encode4(42671), // Rule ID 1261 //
14121
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14122
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls),
14123
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14124
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
14125
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14126
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14127
        // (intrinsic_wo_chain:{ *:[v4i16] } 3117:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm)  =>  (VPADDLsv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm)
14128
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv8i8),
14129
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14130
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14131
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14132
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14133
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14134
0
        GIR_EraseFromParent, /*InsnID*/0,
14135
        // GIR_Coverage, 1261,
14136
0
        GIR_Done,
14137
      // Label 841: @42671
14138
0
      GIM_Try, /*On fail goto*//*Label 842*/ GIMT_Encode4(42728), // Rule ID 1262 //
14139
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14140
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls),
14141
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14142
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14143
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14144
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14145
        // (intrinsic_wo_chain:{ *:[v2i32] } 3117:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VPADDLsv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm)
14146
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv4i16),
14147
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14148
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14149
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14150
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14151
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14152
0
        GIR_EraseFromParent, /*InsnID*/0,
14153
        // GIR_Coverage, 1262,
14154
0
        GIR_Done,
14155
      // Label 842: @42728
14156
0
      GIM_Try, /*On fail goto*//*Label 843*/ GIMT_Encode4(42785), // Rule ID 1263 //
14157
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14158
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls),
14159
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
14160
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14161
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14162
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14163
        // (intrinsic_wo_chain:{ *:[v1i64] } 3117:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VPADDLsv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm)
14164
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv2i32),
14165
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14166
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14167
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14168
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14169
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14170
0
        GIR_EraseFromParent, /*InsnID*/0,
14171
        // GIR_Coverage, 1263,
14172
0
        GIR_Done,
14173
      // Label 843: @42785
14174
0
      GIM_Try, /*On fail goto*//*Label 844*/ GIMT_Encode4(42842), // Rule ID 1264 //
14175
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14176
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls),
14177
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14178
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
14179
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14180
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14181
        // (intrinsic_wo_chain:{ *:[v8i16] } 3117:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (VPADDLsv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm)
14182
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv16i8),
14183
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14184
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14185
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14186
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14187
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14188
0
        GIR_EraseFromParent, /*InsnID*/0,
14189
        // GIR_Coverage, 1264,
14190
0
        GIR_Done,
14191
      // Label 844: @42842
14192
0
      GIM_Try, /*On fail goto*//*Label 845*/ GIMT_Encode4(42899), // Rule ID 1265 //
14193
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14194
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls),
14195
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14196
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14197
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14198
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14199
        // (intrinsic_wo_chain:{ *:[v4i32] } 3117:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VPADDLsv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm)
14200
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv8i16),
14201
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14202
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14203
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14204
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14205
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14206
0
        GIR_EraseFromParent, /*InsnID*/0,
14207
        // GIR_Coverage, 1265,
14208
0
        GIR_Done,
14209
      // Label 845: @42899
14210
0
      GIM_Try, /*On fail goto*//*Label 846*/ GIMT_Encode4(42956), // Rule ID 1266 //
14211
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14212
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls),
14213
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
14214
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14215
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14216
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14217
        // (intrinsic_wo_chain:{ *:[v2i64] } 3117:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VPADDLsv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm)
14218
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv4i32),
14219
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14220
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14221
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14222
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14223
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14224
0
        GIR_EraseFromParent, /*InsnID*/0,
14225
        // GIR_Coverage, 1266,
14226
0
        GIR_Done,
14227
      // Label 846: @42956
14228
0
      GIM_Try, /*On fail goto*//*Label 847*/ GIMT_Encode4(43013), // Rule ID 1267 //
14229
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14230
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu),
14231
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14232
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
14233
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14234
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14235
        // (intrinsic_wo_chain:{ *:[v4i16] } 3118:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm)  =>  (VPADDLuv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm)
14236
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv8i8),
14237
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14238
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14239
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14240
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14241
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14242
0
        GIR_EraseFromParent, /*InsnID*/0,
14243
        // GIR_Coverage, 1267,
14244
0
        GIR_Done,
14245
      // Label 847: @43013
14246
0
      GIM_Try, /*On fail goto*//*Label 848*/ GIMT_Encode4(43070), // Rule ID 1268 //
14247
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14248
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu),
14249
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14250
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14251
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14252
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14253
        // (intrinsic_wo_chain:{ *:[v2i32] } 3118:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VPADDLuv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm)
14254
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv4i16),
14255
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14256
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14257
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14258
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14259
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14260
0
        GIR_EraseFromParent, /*InsnID*/0,
14261
        // GIR_Coverage, 1268,
14262
0
        GIR_Done,
14263
      // Label 848: @43070
14264
0
      GIM_Try, /*On fail goto*//*Label 849*/ GIMT_Encode4(43127), // Rule ID 1269 //
14265
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14266
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu),
14267
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
14268
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14269
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14270
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14271
        // (intrinsic_wo_chain:{ *:[v1i64] } 3118:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VPADDLuv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm)
14272
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv2i32),
14273
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14274
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14275
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14276
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14277
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14278
0
        GIR_EraseFromParent, /*InsnID*/0,
14279
        // GIR_Coverage, 1269,
14280
0
        GIR_Done,
14281
      // Label 849: @43127
14282
0
      GIM_Try, /*On fail goto*//*Label 850*/ GIMT_Encode4(43184), // Rule ID 1270 //
14283
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14284
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu),
14285
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14286
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
14287
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14288
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14289
        // (intrinsic_wo_chain:{ *:[v8i16] } 3118:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (VPADDLuv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm)
14290
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv16i8),
14291
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14292
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14293
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14294
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14295
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14296
0
        GIR_EraseFromParent, /*InsnID*/0,
14297
        // GIR_Coverage, 1270,
14298
0
        GIR_Done,
14299
      // Label 850: @43184
14300
0
      GIM_Try, /*On fail goto*//*Label 851*/ GIMT_Encode4(43241), // Rule ID 1271 //
14301
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14302
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu),
14303
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14304
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14305
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14306
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14307
        // (intrinsic_wo_chain:{ *:[v4i32] } 3118:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VPADDLuv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm)
14308
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv8i16),
14309
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14310
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14311
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14312
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14313
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14314
0
        GIR_EraseFromParent, /*InsnID*/0,
14315
        // GIR_Coverage, 1271,
14316
0
        GIR_Done,
14317
      // Label 851: @43241
14318
0
      GIM_Try, /*On fail goto*//*Label 852*/ GIMT_Encode4(43298), // Rule ID 1272 //
14319
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14320
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu),
14321
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
14322
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14323
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14324
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14325
        // (intrinsic_wo_chain:{ *:[v2i64] } 3118:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VPADDLuv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm)
14326
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv4i32),
14327
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14328
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14329
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14330
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14331
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14332
0
        GIR_EraseFromParent, /*InsnID*/0,
14333
        // GIR_Coverage, 1272,
14334
0
        GIR_Done,
14335
      // Label 852: @43298
14336
0
      GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(43355), // Rule ID 1301 //
14337
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14338
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe),
14339
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14340
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14341
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14342
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14343
        // (intrinsic_wo_chain:{ *:[v2i32] } 3145:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VRECPEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
14344
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRECPEd),
14345
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14346
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14347
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14348
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14349
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14350
0
        GIR_EraseFromParent, /*InsnID*/0,
14351
        // GIR_Coverage, 1301,
14352
0
        GIR_Done,
14353
      // Label 853: @43355
14354
0
      GIM_Try, /*On fail goto*//*Label 854*/ GIMT_Encode4(43412), // Rule ID 1302 //
14355
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14356
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe),
14357
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14358
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14359
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14360
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14361
        // (intrinsic_wo_chain:{ *:[v4i32] } 3145:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VRECPEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
14362
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRECPEq),
14363
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14364
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14365
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14366
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14367
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14368
0
        GIR_EraseFromParent, /*InsnID*/0,
14369
        // GIR_Coverage, 1302,
14370
0
        GIR_Done,
14371
      // Label 854: @43412
14372
0
      GIM_Try, /*On fail goto*//*Label 855*/ GIMT_Encode4(43469), // Rule ID 1303 //
14373
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14374
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe),
14375
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14376
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14377
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14378
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14379
        // (intrinsic_wo_chain:{ *:[v2f32] } 3145:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRECPEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
14380
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRECPEfd),
14381
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14382
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14383
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14384
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14385
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14386
0
        GIR_EraseFromParent, /*InsnID*/0,
14387
        // GIR_Coverage, 1303,
14388
0
        GIR_Done,
14389
      // Label 855: @43469
14390
0
      GIM_Try, /*On fail goto*//*Label 856*/ GIMT_Encode4(43526), // Rule ID 1304 //
14391
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14392
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe),
14393
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14394
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14395
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14396
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14397
        // (intrinsic_wo_chain:{ *:[v4f32] } 3145:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRECPEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
14398
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRECPEfq),
14399
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14400
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14401
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14402
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14403
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14404
0
        GIR_EraseFromParent, /*InsnID*/0,
14405
        // GIR_Coverage, 1304,
14406
0
        GIR_Done,
14407
      // Label 856: @43526
14408
0
      GIM_Try, /*On fail goto*//*Label 857*/ GIMT_Encode4(43583), // Rule ID 1305 //
14409
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
14410
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe),
14411
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14412
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14413
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14414
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14415
        // (intrinsic_wo_chain:{ *:[v4f16] } 3145:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRECPEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
14416
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRECPEhd),
14417
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14418
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14419
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14420
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14421
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14422
0
        GIR_EraseFromParent, /*InsnID*/0,
14423
        // GIR_Coverage, 1305,
14424
0
        GIR_Done,
14425
      // Label 857: @43583
14426
0
      GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(43640), // Rule ID 1306 //
14427
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
14428
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe),
14429
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14430
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14431
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14432
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14433
        // (intrinsic_wo_chain:{ *:[v8f16] } 3145:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRECPEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
14434
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRECPEhq),
14435
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14436
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14437
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14438
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14439
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14440
0
        GIR_EraseFromParent, /*InsnID*/0,
14441
        // GIR_Coverage, 1306,
14442
0
        GIR_Done,
14443
      // Label 858: @43640
14444
0
      GIM_Try, /*On fail goto*//*Label 859*/ GIMT_Encode4(43697), // Rule ID 1311 //
14445
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14446
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte),
14447
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14448
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14449
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14450
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14451
        // (intrinsic_wo_chain:{ *:[v2i32] } 3158:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VRSQRTEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
14452
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEd),
14453
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14454
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14455
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14456
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14457
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14458
0
        GIR_EraseFromParent, /*InsnID*/0,
14459
        // GIR_Coverage, 1311,
14460
0
        GIR_Done,
14461
      // Label 859: @43697
14462
0
      GIM_Try, /*On fail goto*//*Label 860*/ GIMT_Encode4(43754), // Rule ID 1312 //
14463
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14464
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte),
14465
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14466
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14467
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14468
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14469
        // (intrinsic_wo_chain:{ *:[v4i32] } 3158:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VRSQRTEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
14470
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEq),
14471
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14472
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14473
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14474
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14475
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14476
0
        GIR_EraseFromParent, /*InsnID*/0,
14477
        // GIR_Coverage, 1312,
14478
0
        GIR_Done,
14479
      // Label 860: @43754
14480
0
      GIM_Try, /*On fail goto*//*Label 861*/ GIMT_Encode4(43811), // Rule ID 1313 //
14481
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14482
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte),
14483
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14484
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14485
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14486
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14487
        // (intrinsic_wo_chain:{ *:[v2f32] } 3158:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRSQRTEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
14488
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEfd),
14489
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14490
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14491
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14492
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14493
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14494
0
        GIR_EraseFromParent, /*InsnID*/0,
14495
        // GIR_Coverage, 1313,
14496
0
        GIR_Done,
14497
      // Label 861: @43811
14498
0
      GIM_Try, /*On fail goto*//*Label 862*/ GIMT_Encode4(43868), // Rule ID 1314 //
14499
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14500
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte),
14501
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14502
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14503
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14504
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14505
        // (intrinsic_wo_chain:{ *:[v4f32] } 3158:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRSQRTEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
14506
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEfq),
14507
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14508
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14509
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14510
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14511
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14512
0
        GIR_EraseFromParent, /*InsnID*/0,
14513
        // GIR_Coverage, 1314,
14514
0
        GIR_Done,
14515
      // Label 862: @43868
14516
0
      GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(43925), // Rule ID 1315 //
14517
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
14518
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte),
14519
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14520
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14521
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14522
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14523
        // (intrinsic_wo_chain:{ *:[v4f16] } 3158:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRSQRTEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
14524
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEhd),
14525
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14526
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14527
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14528
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14529
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14530
0
        GIR_EraseFromParent, /*InsnID*/0,
14531
        // GIR_Coverage, 1315,
14532
0
        GIR_Done,
14533
      // Label 863: @43925
14534
0
      GIM_Try, /*On fail goto*//*Label 864*/ GIMT_Encode4(43982), // Rule ID 1316 //
14535
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
14536
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte),
14537
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14538
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14539
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14540
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14541
        // (intrinsic_wo_chain:{ *:[v8f16] } 3158:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRSQRTEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
14542
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEhq),
14543
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14544
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14545
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14546
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14547
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14548
0
        GIR_EraseFromParent, /*InsnID*/0,
14549
        // GIR_Coverage, 1316,
14550
0
        GIR_Done,
14551
      // Label 864: @43982
14552
0
      GIM_Try, /*On fail goto*//*Label 865*/ GIMT_Encode4(44039), // Rule ID 1537 //
14553
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14554
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs),
14555
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
14556
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
14557
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14558
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14559
        // (intrinsic_wo_chain:{ *:[v8i8] } 3123:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm)  =>  (VQABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
14560
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQABSv8i8),
14561
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14562
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14563
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14564
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14565
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14566
0
        GIR_EraseFromParent, /*InsnID*/0,
14567
        // GIR_Coverage, 1537,
14568
0
        GIR_Done,
14569
      // Label 865: @44039
14570
0
      GIM_Try, /*On fail goto*//*Label 866*/ GIMT_Encode4(44096), // Rule ID 1538 //
14571
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14572
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs),
14573
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14574
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14575
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14576
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14577
        // (intrinsic_wo_chain:{ *:[v4i16] } 3123:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VQABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
14578
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQABSv4i16),
14579
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14580
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14581
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14582
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14583
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14584
0
        GIR_EraseFromParent, /*InsnID*/0,
14585
        // GIR_Coverage, 1538,
14586
0
        GIR_Done,
14587
      // Label 866: @44096
14588
0
      GIM_Try, /*On fail goto*//*Label 867*/ GIMT_Encode4(44153), // Rule ID 1539 //
14589
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14590
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs),
14591
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14592
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14593
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14594
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14595
        // (intrinsic_wo_chain:{ *:[v2i32] } 3123:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VQABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
14596
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQABSv2i32),
14597
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14598
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14599
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14600
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14601
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14602
0
        GIR_EraseFromParent, /*InsnID*/0,
14603
        // GIR_Coverage, 1539,
14604
0
        GIR_Done,
14605
      // Label 867: @44153
14606
0
      GIM_Try, /*On fail goto*//*Label 868*/ GIMT_Encode4(44210), // Rule ID 1540 //
14607
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14608
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs),
14609
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
14610
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
14611
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14612
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14613
        // (intrinsic_wo_chain:{ *:[v16i8] } 3123:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (VQABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
14614
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQABSv16i8),
14615
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14616
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14617
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14618
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14619
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14620
0
        GIR_EraseFromParent, /*InsnID*/0,
14621
        // GIR_Coverage, 1540,
14622
0
        GIR_Done,
14623
      // Label 868: @44210
14624
0
      GIM_Try, /*On fail goto*//*Label 869*/ GIMT_Encode4(44267), // Rule ID 1541 //
14625
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14626
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs),
14627
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14628
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14629
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14630
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14631
        // (intrinsic_wo_chain:{ *:[v8i16] } 3123:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VQABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
14632
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQABSv8i16),
14633
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14634
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14635
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14636
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14637
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14638
0
        GIR_EraseFromParent, /*InsnID*/0,
14639
        // GIR_Coverage, 1541,
14640
0
        GIR_Done,
14641
      // Label 869: @44267
14642
0
      GIM_Try, /*On fail goto*//*Label 870*/ GIMT_Encode4(44324), // Rule ID 1542 //
14643
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14644
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs),
14645
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14646
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14647
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14648
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14649
        // (intrinsic_wo_chain:{ *:[v4i32] } 3123:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VQABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
14650
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQABSv4i32),
14651
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14652
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14653
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14654
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14655
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14656
0
        GIR_EraseFromParent, /*InsnID*/0,
14657
        // GIR_Coverage, 1542,
14658
0
        GIR_Done,
14659
      // Label 870: @44324
14660
0
      GIM_Try, /*On fail goto*//*Label 871*/ GIMT_Encode4(44381), // Rule ID 1553 //
14661
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14662
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg),
14663
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
14664
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
14665
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14666
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14667
        // (intrinsic_wo_chain:{ *:[v8i8] } 3129:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm)  =>  (VQNEGv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
14668
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQNEGv8i8),
14669
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14670
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14671
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14672
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14673
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14674
0
        GIR_EraseFromParent, /*InsnID*/0,
14675
        // GIR_Coverage, 1553,
14676
0
        GIR_Done,
14677
      // Label 871: @44381
14678
0
      GIM_Try, /*On fail goto*//*Label 872*/ GIMT_Encode4(44438), // Rule ID 1554 //
14679
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14680
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg),
14681
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14682
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14683
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14684
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14685
        // (intrinsic_wo_chain:{ *:[v4i16] } 3129:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VQNEGv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
14686
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQNEGv4i16),
14687
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14688
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14689
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14690
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14691
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14692
0
        GIR_EraseFromParent, /*InsnID*/0,
14693
        // GIR_Coverage, 1554,
14694
0
        GIR_Done,
14695
      // Label 872: @44438
14696
0
      GIM_Try, /*On fail goto*//*Label 873*/ GIMT_Encode4(44495), // Rule ID 1555 //
14697
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14698
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg),
14699
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14700
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14701
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14702
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14703
        // (intrinsic_wo_chain:{ *:[v2i32] } 3129:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VQNEGv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
14704
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQNEGv2i32),
14705
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14706
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14707
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14708
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14709
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14710
0
        GIR_EraseFromParent, /*InsnID*/0,
14711
        // GIR_Coverage, 1555,
14712
0
        GIR_Done,
14713
      // Label 873: @44495
14714
0
      GIM_Try, /*On fail goto*//*Label 874*/ GIMT_Encode4(44552), // Rule ID 1556 //
14715
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14716
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg),
14717
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
14718
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
14719
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14720
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14721
        // (intrinsic_wo_chain:{ *:[v16i8] } 3129:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (VQNEGv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
14722
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQNEGv16i8),
14723
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14724
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14725
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14726
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14727
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14728
0
        GIR_EraseFromParent, /*InsnID*/0,
14729
        // GIR_Coverage, 1556,
14730
0
        GIR_Done,
14731
      // Label 874: @44552
14732
0
      GIM_Try, /*On fail goto*//*Label 875*/ GIMT_Encode4(44609), // Rule ID 1557 //
14733
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14734
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg),
14735
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14736
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14737
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14738
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14739
        // (intrinsic_wo_chain:{ *:[v8i16] } 3129:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VQNEGv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
14740
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQNEGv8i16),
14741
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14742
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14743
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14744
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14745
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14746
0
        GIR_EraseFromParent, /*InsnID*/0,
14747
        // GIR_Coverage, 1557,
14748
0
        GIR_Done,
14749
      // Label 875: @44609
14750
0
      GIM_Try, /*On fail goto*//*Label 876*/ GIMT_Encode4(44666), // Rule ID 1558 //
14751
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14752
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg),
14753
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14754
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14755
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14756
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14757
        // (intrinsic_wo_chain:{ *:[v4i32] } 3129:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VQNEGv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
14758
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQNEGv4i32),
14759
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14760
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14761
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14762
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14763
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14764
0
        GIR_EraseFromParent, /*InsnID*/0,
14765
        // GIR_Coverage, 1558,
14766
0
        GIR_Done,
14767
      // Label 876: @44666
14768
0
      GIM_Try, /*On fail goto*//*Label 877*/ GIMT_Encode4(44723), // Rule ID 1559 //
14769
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14770
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls),
14771
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
14772
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
14773
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14774
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14775
        // (intrinsic_wo_chain:{ *:[v8i8] } 3070:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm)  =>  (VCLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
14776
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCLSv8i8),
14777
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14778
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14779
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14780
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14781
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14782
0
        GIR_EraseFromParent, /*InsnID*/0,
14783
        // GIR_Coverage, 1559,
14784
0
        GIR_Done,
14785
      // Label 877: @44723
14786
0
      GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(44780), // Rule ID 1560 //
14787
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14788
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls),
14789
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14790
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14791
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14792
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14793
        // (intrinsic_wo_chain:{ *:[v4i16] } 3070:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VCLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
14794
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCLSv4i16),
14795
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14796
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14797
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14798
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14799
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14800
0
        GIR_EraseFromParent, /*InsnID*/0,
14801
        // GIR_Coverage, 1560,
14802
0
        GIR_Done,
14803
      // Label 878: @44780
14804
0
      GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(44837), // Rule ID 1561 //
14805
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14806
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls),
14807
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14808
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14809
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14810
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14811
        // (intrinsic_wo_chain:{ *:[v2i32] } 3070:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VCLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
14812
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCLSv2i32),
14813
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14814
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14815
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14816
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14817
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14818
0
        GIR_EraseFromParent, /*InsnID*/0,
14819
        // GIR_Coverage, 1561,
14820
0
        GIR_Done,
14821
      // Label 879: @44837
14822
0
      GIM_Try, /*On fail goto*//*Label 880*/ GIMT_Encode4(44894), // Rule ID 1562 //
14823
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14824
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls),
14825
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
14826
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
14827
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14828
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14829
        // (intrinsic_wo_chain:{ *:[v16i8] } 3070:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (VCLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
14830
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCLSv16i8),
14831
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14832
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14833
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14834
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14835
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14836
0
        GIR_EraseFromParent, /*InsnID*/0,
14837
        // GIR_Coverage, 1562,
14838
0
        GIR_Done,
14839
      // Label 880: @44894
14840
0
      GIM_Try, /*On fail goto*//*Label 881*/ GIMT_Encode4(44951), // Rule ID 1563 //
14841
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14842
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls),
14843
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14844
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14845
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14846
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14847
        // (intrinsic_wo_chain:{ *:[v8i16] } 3070:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VCLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
14848
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCLSv8i16),
14849
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14850
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14851
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14852
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14853
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14854
0
        GIR_EraseFromParent, /*InsnID*/0,
14855
        // GIR_Coverage, 1563,
14856
0
        GIR_Done,
14857
      // Label 881: @44951
14858
0
      GIM_Try, /*On fail goto*//*Label 882*/ GIMT_Encode4(45008), // Rule ID 1564 //
14859
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14860
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls),
14861
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14862
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14863
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14864
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14865
        // (intrinsic_wo_chain:{ *:[v4i32] } 3070:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VCLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
14866
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCLSv4i32),
14867
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14868
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14869
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14870
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14871
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14872
0
        GIR_EraseFromParent, /*InsnID*/0,
14873
        // GIR_Coverage, 1564,
14874
0
        GIR_Done,
14875
      // Label 882: @45008
14876
0
      GIM_Try, /*On fail goto*//*Label 883*/ GIMT_Encode4(45065), // Rule ID 1608 //
14877
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14878
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovns),
14879
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
14880
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14881
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14882
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14883
        // (intrinsic_wo_chain:{ *:[v8i8] } 3126:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VQMOVNsv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
14884
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv8i8),
14885
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14886
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14887
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14888
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14889
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14890
0
        GIR_EraseFromParent, /*InsnID*/0,
14891
        // GIR_Coverage, 1608,
14892
0
        GIR_Done,
14893
      // Label 883: @45065
14894
0
      GIM_Try, /*On fail goto*//*Label 884*/ GIMT_Encode4(45122), // Rule ID 1609 //
14895
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14896
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovns),
14897
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14898
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14899
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14900
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14901
        // (intrinsic_wo_chain:{ *:[v4i16] } 3126:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VQMOVNsv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
14902
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv4i16),
14903
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14904
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14905
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14906
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14907
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14908
0
        GIR_EraseFromParent, /*InsnID*/0,
14909
        // GIR_Coverage, 1609,
14910
0
        GIR_Done,
14911
      // Label 884: @45122
14912
0
      GIM_Try, /*On fail goto*//*Label 885*/ GIMT_Encode4(45179), // Rule ID 1610 //
14913
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14914
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovns),
14915
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14916
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
14917
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14918
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14919
        // (intrinsic_wo_chain:{ *:[v2i32] } 3126:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm)  =>  (VQMOVNsv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
14920
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv2i32),
14921
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14922
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14923
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14924
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14925
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14926
0
        GIR_EraseFromParent, /*InsnID*/0,
14927
        // GIR_Coverage, 1610,
14928
0
        GIR_Done,
14929
      // Label 885: @45179
14930
0
      GIM_Try, /*On fail goto*//*Label 886*/ GIMT_Encode4(45236), // Rule ID 1611 //
14931
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14932
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnu),
14933
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
14934
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14935
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14936
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14937
        // (intrinsic_wo_chain:{ *:[v8i8] } 3128:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VQMOVNuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
14938
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv8i8),
14939
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14940
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14941
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14942
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14943
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14944
0
        GIR_EraseFromParent, /*InsnID*/0,
14945
        // GIR_Coverage, 1611,
14946
0
        GIR_Done,
14947
      // Label 886: @45236
14948
0
      GIM_Try, /*On fail goto*//*Label 887*/ GIMT_Encode4(45293), // Rule ID 1612 //
14949
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14950
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnu),
14951
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14952
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14953
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14954
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14955
        // (intrinsic_wo_chain:{ *:[v4i16] } 3128:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VQMOVNuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
14956
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv4i16),
14957
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14958
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14959
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14960
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14961
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14962
0
        GIR_EraseFromParent, /*InsnID*/0,
14963
        // GIR_Coverage, 1612,
14964
0
        GIR_Done,
14965
      // Label 887: @45293
14966
0
      GIM_Try, /*On fail goto*//*Label 888*/ GIMT_Encode4(45350), // Rule ID 1613 //
14967
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14968
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnu),
14969
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14970
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
14971
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14972
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14973
        // (intrinsic_wo_chain:{ *:[v2i32] } 3128:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm)  =>  (VQMOVNuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
14974
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv2i32),
14975
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14976
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14977
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14978
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14979
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14980
0
        GIR_EraseFromParent, /*InsnID*/0,
14981
        // GIR_Coverage, 1613,
14982
0
        GIR_Done,
14983
      // Label 888: @45350
14984
0
      GIM_Try, /*On fail goto*//*Label 889*/ GIMT_Encode4(45407), // Rule ID 1614 //
14985
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14986
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnsu),
14987
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
14988
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14989
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14990
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14991
        // (intrinsic_wo_chain:{ *:[v8i8] } 3127:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VQMOVNsuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
14992
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv8i8),
14993
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
14994
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14995
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14996
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14997
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14998
0
        GIR_EraseFromParent, /*InsnID*/0,
14999
        // GIR_Coverage, 1614,
15000
0
        GIR_Done,
15001
      // Label 889: @45407
15002
0
      GIM_Try, /*On fail goto*//*Label 890*/ GIMT_Encode4(45464), // Rule ID 1615 //
15003
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15004
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnsu),
15005
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15006
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15007
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15008
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15009
        // (intrinsic_wo_chain:{ *:[v4i16] } 3127:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VQMOVNsuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
15010
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv4i16),
15011
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15012
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15013
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15014
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15015
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15016
0
        GIR_EraseFromParent, /*InsnID*/0,
15017
        // GIR_Coverage, 1615,
15018
0
        GIR_Done,
15019
      // Label 890: @45464
15020
0
      GIM_Try, /*On fail goto*//*Label 891*/ GIMT_Encode4(45521), // Rule ID 1616 //
15021
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15022
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnsu),
15023
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15024
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
15025
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15026
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15027
        // (intrinsic_wo_chain:{ *:[v2i32] } 3127:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm)  =>  (VQMOVNsuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
15028
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv2i32),
15029
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15030
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15031
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15032
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15033
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15034
0
        GIR_EraseFromParent, /*InsnID*/0,
15035
        // GIR_Coverage, 1616,
15036
0
        GIR_Done,
15037
      // Label 891: @45521
15038
0
      GIM_Try, /*On fail goto*//*Label 892*/ GIMT_Encode4(45569), // Rule ID 1639 //
15039
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15040
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas),
15041
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15042
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15043
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15044
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15045
        // (intrinsic_wo_chain:{ *:[v2i32] } 3071:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTANSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15046
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTANSDf),
15047
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15048
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15049
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15050
0
        GIR_EraseFromParent, /*InsnID*/0,
15051
        // GIR_Coverage, 1639,
15052
0
        GIR_Done,
15053
      // Label 892: @45569
15054
0
      GIM_Try, /*On fail goto*//*Label 893*/ GIMT_Encode4(45617), // Rule ID 1640 //
15055
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15056
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas),
15057
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15058
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15059
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15060
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15061
        // (intrinsic_wo_chain:{ *:[v4i32] } 3071:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTANSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15062
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTANSQf),
15063
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15064
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15065
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15066
0
        GIR_EraseFromParent, /*InsnID*/0,
15067
        // GIR_Coverage, 1640,
15068
0
        GIR_Done,
15069
      // Label 893: @45617
15070
0
      GIM_Try, /*On fail goto*//*Label 894*/ GIMT_Encode4(45665), // Rule ID 1641 //
15071
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15072
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau),
15073
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15074
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15075
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15076
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15077
        // (intrinsic_wo_chain:{ *:[v2i32] } 3072:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTANUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15078
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTANUDf),
15079
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15080
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15081
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15082
0
        GIR_EraseFromParent, /*InsnID*/0,
15083
        // GIR_Coverage, 1641,
15084
0
        GIR_Done,
15085
      // Label 894: @45665
15086
0
      GIM_Try, /*On fail goto*//*Label 895*/ GIMT_Encode4(45713), // Rule ID 1642 //
15087
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15088
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau),
15089
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15090
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15091
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15092
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15093
        // (intrinsic_wo_chain:{ *:[v4i32] } 3072:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTANUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15094
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTANUQf),
15095
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15096
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15097
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15098
0
        GIR_EraseFromParent, /*InsnID*/0,
15099
        // GIR_Coverage, 1642,
15100
0
        GIR_Done,
15101
      // Label 895: @45713
15102
0
      GIM_Try, /*On fail goto*//*Label 896*/ GIMT_Encode4(45761), // Rule ID 1643 //
15103
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15104
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas),
15105
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15106
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15107
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15108
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15109
        // (intrinsic_wo_chain:{ *:[v4i16] } 3071:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTANSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15110
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTANSDh),
15111
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15112
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15113
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15114
0
        GIR_EraseFromParent, /*InsnID*/0,
15115
        // GIR_Coverage, 1643,
15116
0
        GIR_Done,
15117
      // Label 896: @45761
15118
0
      GIM_Try, /*On fail goto*//*Label 897*/ GIMT_Encode4(45809), // Rule ID 1644 //
15119
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15120
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas),
15121
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15122
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15123
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15124
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15125
        // (intrinsic_wo_chain:{ *:[v8i16] } 3071:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTANSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15126
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTANSQh),
15127
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15128
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15129
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15130
0
        GIR_EraseFromParent, /*InsnID*/0,
15131
        // GIR_Coverage, 1644,
15132
0
        GIR_Done,
15133
      // Label 897: @45809
15134
0
      GIM_Try, /*On fail goto*//*Label 898*/ GIMT_Encode4(45857), // Rule ID 1645 //
15135
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15136
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau),
15137
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15138
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15139
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15140
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15141
        // (intrinsic_wo_chain:{ *:[v4i16] } 3072:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTANUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15142
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTANUDh),
15143
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15144
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15145
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15146
0
        GIR_EraseFromParent, /*InsnID*/0,
15147
        // GIR_Coverage, 1645,
15148
0
        GIR_Done,
15149
      // Label 898: @45857
15150
0
      GIM_Try, /*On fail goto*//*Label 899*/ GIMT_Encode4(45905), // Rule ID 1646 //
15151
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15152
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau),
15153
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15154
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15155
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15156
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15157
        // (intrinsic_wo_chain:{ *:[v8i16] } 3072:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTANUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15158
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTANUQh),
15159
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15160
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15161
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15162
0
        GIR_EraseFromParent, /*InsnID*/0,
15163
        // GIR_Coverage, 1646,
15164
0
        GIR_Done,
15165
      // Label 899: @45905
15166
0
      GIM_Try, /*On fail goto*//*Label 900*/ GIMT_Encode4(45953), // Rule ID 1647 //
15167
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15168
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns),
15169
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15170
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15171
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15172
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15173
        // (intrinsic_wo_chain:{ *:[v2i32] } 3083:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTNNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15174
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSDf),
15175
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15176
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15177
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15178
0
        GIR_EraseFromParent, /*InsnID*/0,
15179
        // GIR_Coverage, 1647,
15180
0
        GIR_Done,
15181
      // Label 900: @45953
15182
0
      GIM_Try, /*On fail goto*//*Label 901*/ GIMT_Encode4(46001), // Rule ID 1648 //
15183
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15184
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns),
15185
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15186
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15187
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15188
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15189
        // (intrinsic_wo_chain:{ *:[v4i32] } 3083:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTNNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15190
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSQf),
15191
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15192
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15193
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15194
0
        GIR_EraseFromParent, /*InsnID*/0,
15195
        // GIR_Coverage, 1648,
15196
0
        GIR_Done,
15197
      // Label 901: @46001
15198
0
      GIM_Try, /*On fail goto*//*Label 902*/ GIMT_Encode4(46049), // Rule ID 1649 //
15199
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15200
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu),
15201
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15202
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15203
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15204
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15205
        // (intrinsic_wo_chain:{ *:[v2i32] } 3084:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTNNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15206
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUDf),
15207
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15208
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15209
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15210
0
        GIR_EraseFromParent, /*InsnID*/0,
15211
        // GIR_Coverage, 1649,
15212
0
        GIR_Done,
15213
      // Label 902: @46049
15214
0
      GIM_Try, /*On fail goto*//*Label 903*/ GIMT_Encode4(46097), // Rule ID 1650 //
15215
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15216
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu),
15217
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15218
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15219
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15220
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15221
        // (intrinsic_wo_chain:{ *:[v4i32] } 3084:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTNNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15222
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUQf),
15223
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15224
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15225
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15226
0
        GIR_EraseFromParent, /*InsnID*/0,
15227
        // GIR_Coverage, 1650,
15228
0
        GIR_Done,
15229
      // Label 903: @46097
15230
0
      GIM_Try, /*On fail goto*//*Label 904*/ GIMT_Encode4(46145), // Rule ID 1651 //
15231
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15232
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns),
15233
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15234
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15235
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15236
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15237
        // (intrinsic_wo_chain:{ *:[v4i16] } 3083:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTNNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15238
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSDh),
15239
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15240
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15241
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15242
0
        GIR_EraseFromParent, /*InsnID*/0,
15243
        // GIR_Coverage, 1651,
15244
0
        GIR_Done,
15245
      // Label 904: @46145
15246
0
      GIM_Try, /*On fail goto*//*Label 905*/ GIMT_Encode4(46193), // Rule ID 1652 //
15247
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15248
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns),
15249
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15250
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15251
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15252
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15253
        // (intrinsic_wo_chain:{ *:[v8i16] } 3083:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTNNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15254
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSQh),
15255
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15256
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15257
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15258
0
        GIR_EraseFromParent, /*InsnID*/0,
15259
        // GIR_Coverage, 1652,
15260
0
        GIR_Done,
15261
      // Label 905: @46193
15262
0
      GIM_Try, /*On fail goto*//*Label 906*/ GIMT_Encode4(46241), // Rule ID 1653 //
15263
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15264
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu),
15265
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15266
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15267
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15268
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15269
        // (intrinsic_wo_chain:{ *:[v4i16] } 3084:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTNNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15270
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUDh),
15271
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15272
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15273
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15274
0
        GIR_EraseFromParent, /*InsnID*/0,
15275
        // GIR_Coverage, 1653,
15276
0
        GIR_Done,
15277
      // Label 906: @46241
15278
0
      GIM_Try, /*On fail goto*//*Label 907*/ GIMT_Encode4(46289), // Rule ID 1654 //
15279
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15280
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu),
15281
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15282
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15283
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15284
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15285
        // (intrinsic_wo_chain:{ *:[v8i16] } 3084:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTNNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15286
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUQh),
15287
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15288
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15289
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15290
0
        GIR_EraseFromParent, /*InsnID*/0,
15291
        // GIR_Coverage, 1654,
15292
0
        GIR_Done,
15293
      // Label 907: @46289
15294
0
      GIM_Try, /*On fail goto*//*Label 908*/ GIMT_Encode4(46337), // Rule ID 1655 //
15295
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15296
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps),
15297
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15298
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15299
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15300
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15301
        // (intrinsic_wo_chain:{ *:[v2i32] } 3085:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTPNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15302
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSDf),
15303
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15304
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15305
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15306
0
        GIR_EraseFromParent, /*InsnID*/0,
15307
        // GIR_Coverage, 1655,
15308
0
        GIR_Done,
15309
      // Label 908: @46337
15310
0
      GIM_Try, /*On fail goto*//*Label 909*/ GIMT_Encode4(46385), // Rule ID 1656 //
15311
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15312
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps),
15313
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15314
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15315
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15316
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15317
        // (intrinsic_wo_chain:{ *:[v4i32] } 3085:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTPNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15318
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSQf),
15319
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15320
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15321
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15322
0
        GIR_EraseFromParent, /*InsnID*/0,
15323
        // GIR_Coverage, 1656,
15324
0
        GIR_Done,
15325
      // Label 909: @46385
15326
0
      GIM_Try, /*On fail goto*//*Label 910*/ GIMT_Encode4(46433), // Rule ID 1657 //
15327
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15328
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu),
15329
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15330
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15331
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15332
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15333
        // (intrinsic_wo_chain:{ *:[v2i32] } 3086:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTPNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15334
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUDf),
15335
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15336
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15337
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15338
0
        GIR_EraseFromParent, /*InsnID*/0,
15339
        // GIR_Coverage, 1657,
15340
0
        GIR_Done,
15341
      // Label 910: @46433
15342
0
      GIM_Try, /*On fail goto*//*Label 911*/ GIMT_Encode4(46481), // Rule ID 1658 //
15343
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15344
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu),
15345
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15346
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15347
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15348
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15349
        // (intrinsic_wo_chain:{ *:[v4i32] } 3086:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTPNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15350
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUQf),
15351
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15352
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15353
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15354
0
        GIR_EraseFromParent, /*InsnID*/0,
15355
        // GIR_Coverage, 1658,
15356
0
        GIR_Done,
15357
      // Label 911: @46481
15358
0
      GIM_Try, /*On fail goto*//*Label 912*/ GIMT_Encode4(46529), // Rule ID 1659 //
15359
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15360
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps),
15361
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15362
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15363
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15364
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15365
        // (intrinsic_wo_chain:{ *:[v4i16] } 3085:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTPNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15366
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSDh),
15367
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15368
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15369
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15370
0
        GIR_EraseFromParent, /*InsnID*/0,
15371
        // GIR_Coverage, 1659,
15372
0
        GIR_Done,
15373
      // Label 912: @46529
15374
0
      GIM_Try, /*On fail goto*//*Label 913*/ GIMT_Encode4(46577), // Rule ID 1660 //
15375
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15376
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps),
15377
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15378
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15379
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15380
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15381
        // (intrinsic_wo_chain:{ *:[v8i16] } 3085:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTPNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15382
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSQh),
15383
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15384
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15385
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15386
0
        GIR_EraseFromParent, /*InsnID*/0,
15387
        // GIR_Coverage, 1660,
15388
0
        GIR_Done,
15389
      // Label 913: @46577
15390
0
      GIM_Try, /*On fail goto*//*Label 914*/ GIMT_Encode4(46625), // Rule ID 1661 //
15391
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15392
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu),
15393
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15394
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15395
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15396
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15397
        // (intrinsic_wo_chain:{ *:[v4i16] } 3086:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTPNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15398
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUDh),
15399
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15400
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15401
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15402
0
        GIR_EraseFromParent, /*InsnID*/0,
15403
        // GIR_Coverage, 1661,
15404
0
        GIR_Done,
15405
      // Label 914: @46625
15406
0
      GIM_Try, /*On fail goto*//*Label 915*/ GIMT_Encode4(46673), // Rule ID 1662 //
15407
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15408
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu),
15409
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15410
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15411
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15412
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15413
        // (intrinsic_wo_chain:{ *:[v8i16] } 3086:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTPNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15414
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUQh),
15415
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15416
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15417
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15418
0
        GIR_EraseFromParent, /*InsnID*/0,
15419
        // GIR_Coverage, 1662,
15420
0
        GIR_Done,
15421
      // Label 915: @46673
15422
0
      GIM_Try, /*On fail goto*//*Label 916*/ GIMT_Encode4(46721), // Rule ID 1663 //
15423
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15424
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms),
15425
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15426
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15427
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15428
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15429
        // (intrinsic_wo_chain:{ *:[v2i32] } 3081:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTMNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15430
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSDf),
15431
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15432
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15433
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15434
0
        GIR_EraseFromParent, /*InsnID*/0,
15435
        // GIR_Coverage, 1663,
15436
0
        GIR_Done,
15437
      // Label 916: @46721
15438
0
      GIM_Try, /*On fail goto*//*Label 917*/ GIMT_Encode4(46769), // Rule ID 1664 //
15439
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15440
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms),
15441
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15442
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15443
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15444
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15445
        // (intrinsic_wo_chain:{ *:[v4i32] } 3081:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTMNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15446
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSQf),
15447
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15448
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15449
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15450
0
        GIR_EraseFromParent, /*InsnID*/0,
15451
        // GIR_Coverage, 1664,
15452
0
        GIR_Done,
15453
      // Label 917: @46769
15454
0
      GIM_Try, /*On fail goto*//*Label 918*/ GIMT_Encode4(46817), // Rule ID 1665 //
15455
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15456
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu),
15457
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15458
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15459
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15460
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15461
        // (intrinsic_wo_chain:{ *:[v2i32] } 3082:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTMNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15462
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUDf),
15463
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15464
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15465
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15466
0
        GIR_EraseFromParent, /*InsnID*/0,
15467
        // GIR_Coverage, 1665,
15468
0
        GIR_Done,
15469
      // Label 918: @46817
15470
0
      GIM_Try, /*On fail goto*//*Label 919*/ GIMT_Encode4(46865), // Rule ID 1666 //
15471
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15472
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu),
15473
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15474
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15475
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15476
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15477
        // (intrinsic_wo_chain:{ *:[v4i32] } 3082:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTMNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15478
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUQf),
15479
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15480
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15481
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15482
0
        GIR_EraseFromParent, /*InsnID*/0,
15483
        // GIR_Coverage, 1666,
15484
0
        GIR_Done,
15485
      // Label 919: @46865
15486
0
      GIM_Try, /*On fail goto*//*Label 920*/ GIMT_Encode4(46913), // Rule ID 1667 //
15487
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15488
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms),
15489
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15490
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15491
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15492
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15493
        // (intrinsic_wo_chain:{ *:[v4i16] } 3081:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTMNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15494
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSDh),
15495
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15496
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15497
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15498
0
        GIR_EraseFromParent, /*InsnID*/0,
15499
        // GIR_Coverage, 1667,
15500
0
        GIR_Done,
15501
      // Label 920: @46913
15502
0
      GIM_Try, /*On fail goto*//*Label 921*/ GIMT_Encode4(46961), // Rule ID 1668 //
15503
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15504
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms),
15505
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15506
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15507
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15508
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15509
        // (intrinsic_wo_chain:{ *:[v8i16] } 3081:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTMNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15510
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSQh),
15511
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15512
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15513
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15514
0
        GIR_EraseFromParent, /*InsnID*/0,
15515
        // GIR_Coverage, 1668,
15516
0
        GIR_Done,
15517
      // Label 921: @46961
15518
0
      GIM_Try, /*On fail goto*//*Label 922*/ GIMT_Encode4(47009), // Rule ID 1669 //
15519
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15520
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu),
15521
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15522
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15523
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15524
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15525
        // (intrinsic_wo_chain:{ *:[v4i16] } 3082:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTMNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15526
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUDh),
15527
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15528
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15529
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15530
0
        GIR_EraseFromParent, /*InsnID*/0,
15531
        // GIR_Coverage, 1669,
15532
0
        GIR_Done,
15533
      // Label 922: @47009
15534
0
      GIM_Try, /*On fail goto*//*Label 923*/ GIMT_Encode4(47057), // Rule ID 1670 //
15535
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15536
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu),
15537
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15538
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15539
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15540
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15541
        // (intrinsic_wo_chain:{ *:[v8i16] } 3082:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTMNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15542
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUQh),
15543
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15544
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15545
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15546
0
        GIR_EraseFromParent, /*InsnID*/0,
15547
        // GIR_Coverage, 1670,
15548
0
        GIR_Done,
15549
      // Label 923: @47057
15550
0
      GIM_Try, /*On fail goto*//*Label 924*/ GIMT_Encode4(47114), // Rule ID 1687 //
15551
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16_HasNEON),
15552
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2hf),
15553
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15554
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15555
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15556
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15557
        // (intrinsic_wo_chain:{ *:[v4i16] } 3077:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTf2h:{ *:[v4i16] } QPR:{ *:[v4f32] }:$Vm)
15558
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTf2h),
15559
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15560
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15561
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15562
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15563
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15564
0
        GIR_EraseFromParent, /*InsnID*/0,
15565
        // GIR_Coverage, 1687,
15566
0
        GIR_Done,
15567
      // Label 924: @47114
15568
0
      GIM_Try, /*On fail goto*//*Label 925*/ GIMT_Encode4(47171), // Rule ID 1688 //
15569
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16_HasNEON),
15570
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvthf2fp),
15571
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15572
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15573
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15574
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15575
        // (intrinsic_wo_chain:{ *:[v4f32] } 3080:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4i16] }:$Vm)
15576
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTh2f),
15577
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15578
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15579
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15580
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15581
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15582
0
        GIR_EraseFromParent, /*InsnID*/0,
15583
        // GIR_Coverage, 1688,
15584
0
        GIR_Done,
15585
      // Label 925: @47171
15586
0
      GIM_Try, /*On fail goto*//*Label 926*/ GIMT_Encode4(47219), // Rule ID 1710 //
15587
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15588
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn),
15589
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15590
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15591
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15592
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15593
        // (intrinsic_wo_chain:{ *:[v2f32] } 3151:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTNNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
15594
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNDf),
15595
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15596
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15597
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15598
0
        GIR_EraseFromParent, /*InsnID*/0,
15599
        // GIR_Coverage, 1710,
15600
0
        GIR_Done,
15601
      // Label 926: @47219
15602
0
      GIM_Try, /*On fail goto*//*Label 927*/ GIMT_Encode4(47267), // Rule ID 1711 //
15603
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15604
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn),
15605
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15606
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15607
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15608
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15609
        // (intrinsic_wo_chain:{ *:[v4f32] } 3151:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTNNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
15610
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNQf),
15611
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15612
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15613
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15614
0
        GIR_EraseFromParent, /*InsnID*/0,
15615
        // GIR_Coverage, 1711,
15616
0
        GIR_Done,
15617
      // Label 927: @47267
15618
0
      GIM_Try, /*On fail goto*//*Label 928*/ GIMT_Encode4(47315), // Rule ID 1712 //
15619
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15620
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn),
15621
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15622
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15623
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15624
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15625
        // (intrinsic_wo_chain:{ *:[v4f16] } 3151:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTNNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
15626
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNDh),
15627
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15628
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15629
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15630
0
        GIR_EraseFromParent, /*InsnID*/0,
15631
        // GIR_Coverage, 1712,
15632
0
        GIR_Done,
15633
      // Label 928: @47315
15634
0
      GIM_Try, /*On fail goto*//*Label 929*/ GIMT_Encode4(47363), // Rule ID 1713 //
15635
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15636
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn),
15637
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15638
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15639
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15640
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15641
        // (intrinsic_wo_chain:{ *:[v8f16] } 3151:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTNNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
15642
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNQh),
15643
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15644
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15645
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15646
0
        GIR_EraseFromParent, /*InsnID*/0,
15647
        // GIR_Coverage, 1713,
15648
0
        GIR_Done,
15649
      // Label 929: @47363
15650
0
      GIM_Try, /*On fail goto*//*Label 930*/ GIMT_Encode4(47411), // Rule ID 1714 //
15651
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15652
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintx),
15653
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15654
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15655
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15656
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15657
        // (intrinsic_wo_chain:{ *:[v2f32] } 3153:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTXNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
15658
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNDf),
15659
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15660
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15661
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15662
0
        GIR_EraseFromParent, /*InsnID*/0,
15663
        // GIR_Coverage, 1714,
15664
0
        GIR_Done,
15665
      // Label 930: @47411
15666
0
      GIM_Try, /*On fail goto*//*Label 931*/ GIMT_Encode4(47459), // Rule ID 1715 //
15667
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15668
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintx),
15669
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15670
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15671
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15672
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15673
        // (intrinsic_wo_chain:{ *:[v4f32] } 3153:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTXNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
15674
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNQf),
15675
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15676
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15677
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15678
0
        GIR_EraseFromParent, /*InsnID*/0,
15679
        // GIR_Coverage, 1715,
15680
0
        GIR_Done,
15681
      // Label 931: @47459
15682
0
      GIM_Try, /*On fail goto*//*Label 932*/ GIMT_Encode4(47507), // Rule ID 1716 //
15683
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15684
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintx),
15685
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15686
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15687
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15688
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15689
        // (intrinsic_wo_chain:{ *:[v4f16] } 3153:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTXNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
15690
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNDh),
15691
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15692
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15693
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15694
0
        GIR_EraseFromParent, /*InsnID*/0,
15695
        // GIR_Coverage, 1716,
15696
0
        GIR_Done,
15697
      // Label 932: @47507
15698
0
      GIM_Try, /*On fail goto*//*Label 933*/ GIMT_Encode4(47555), // Rule ID 1717 //
15699
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15700
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintx),
15701
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15702
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15703
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15704
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15705
        // (intrinsic_wo_chain:{ *:[v8f16] } 3153:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTXNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
15706
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNQh),
15707
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15708
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15709
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15710
0
        GIR_EraseFromParent, /*InsnID*/0,
15711
        // GIR_Coverage, 1717,
15712
0
        GIR_Done,
15713
      // Label 933: @47555
15714
0
      GIM_Try, /*On fail goto*//*Label 934*/ GIMT_Encode4(47603), // Rule ID 1718 //
15715
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15716
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrinta),
15717
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15718
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15719
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15720
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15721
        // (intrinsic_wo_chain:{ *:[v2f32] } 3149:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTANDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
15722
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANDf),
15723
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15724
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15725
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15726
0
        GIR_EraseFromParent, /*InsnID*/0,
15727
        // GIR_Coverage, 1718,
15728
0
        GIR_Done,
15729
      // Label 934: @47603
15730
0
      GIM_Try, /*On fail goto*//*Label 935*/ GIMT_Encode4(47651), // Rule ID 1719 //
15731
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15732
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrinta),
15733
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15734
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15735
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15736
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15737
        // (intrinsic_wo_chain:{ *:[v4f32] } 3149:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTANQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
15738
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANQf),
15739
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15740
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15741
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15742
0
        GIR_EraseFromParent, /*InsnID*/0,
15743
        // GIR_Coverage, 1719,
15744
0
        GIR_Done,
15745
      // Label 935: @47651
15746
0
      GIM_Try, /*On fail goto*//*Label 936*/ GIMT_Encode4(47699), // Rule ID 1720 //
15747
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15748
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrinta),
15749
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15750
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15751
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15752
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15753
        // (intrinsic_wo_chain:{ *:[v4f16] } 3149:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTANDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
15754
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANDh),
15755
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15756
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15757
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15758
0
        GIR_EraseFromParent, /*InsnID*/0,
15759
        // GIR_Coverage, 1720,
15760
0
        GIR_Done,
15761
      // Label 936: @47699
15762
0
      GIM_Try, /*On fail goto*//*Label 937*/ GIMT_Encode4(47747), // Rule ID 1721 //
15763
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15764
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrinta),
15765
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15766
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15767
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15768
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15769
        // (intrinsic_wo_chain:{ *:[v8f16] } 3149:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTANQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
15770
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANQh),
15771
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15772
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15773
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15774
0
        GIR_EraseFromParent, /*InsnID*/0,
15775
        // GIR_Coverage, 1721,
15776
0
        GIR_Done,
15777
      // Label 937: @47747
15778
0
      GIM_Try, /*On fail goto*//*Label 938*/ GIMT_Encode4(47795), // Rule ID 1722 //
15779
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15780
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintz),
15781
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15782
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15783
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15784
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15785
        // (intrinsic_wo_chain:{ *:[v2f32] } 3154:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTZNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
15786
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNDf),
15787
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15788
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15789
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15790
0
        GIR_EraseFromParent, /*InsnID*/0,
15791
        // GIR_Coverage, 1722,
15792
0
        GIR_Done,
15793
      // Label 938: @47795
15794
0
      GIM_Try, /*On fail goto*//*Label 939*/ GIMT_Encode4(47843), // Rule ID 1723 //
15795
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15796
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintz),
15797
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15798
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15799
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15800
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15801
        // (intrinsic_wo_chain:{ *:[v4f32] } 3154:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTZNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
15802
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNQf),
15803
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15804
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15805
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15806
0
        GIR_EraseFromParent, /*InsnID*/0,
15807
        // GIR_Coverage, 1723,
15808
0
        GIR_Done,
15809
      // Label 939: @47843
15810
0
      GIM_Try, /*On fail goto*//*Label 940*/ GIMT_Encode4(47891), // Rule ID 1724 //
15811
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15812
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintz),
15813
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15814
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15815
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15816
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15817
        // (intrinsic_wo_chain:{ *:[v4f16] } 3154:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTZNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
15818
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNDh),
15819
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15820
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15821
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15822
0
        GIR_EraseFromParent, /*InsnID*/0,
15823
        // GIR_Coverage, 1724,
15824
0
        GIR_Done,
15825
      // Label 940: @47891
15826
0
      GIM_Try, /*On fail goto*//*Label 941*/ GIMT_Encode4(47939), // Rule ID 1725 //
15827
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15828
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintz),
15829
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15830
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15831
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15832
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15833
        // (intrinsic_wo_chain:{ *:[v8f16] } 3154:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTZNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
15834
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNQh),
15835
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15836
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15837
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15838
0
        GIR_EraseFromParent, /*InsnID*/0,
15839
        // GIR_Coverage, 1725,
15840
0
        GIR_Done,
15841
      // Label 941: @47939
15842
0
      GIM_Try, /*On fail goto*//*Label 942*/ GIMT_Encode4(47987), // Rule ID 1726 //
15843
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15844
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintm),
15845
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15846
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15847
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15848
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15849
        // (intrinsic_wo_chain:{ *:[v2f32] } 3150:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
15850
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNDf),
15851
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15852
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15853
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15854
0
        GIR_EraseFromParent, /*InsnID*/0,
15855
        // GIR_Coverage, 1726,
15856
0
        GIR_Done,
15857
      // Label 942: @47987
15858
0
      GIM_Try, /*On fail goto*//*Label 943*/ GIMT_Encode4(48035), // Rule ID 1727 //
15859
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15860
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintm),
15861
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15862
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15863
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15864
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15865
        // (intrinsic_wo_chain:{ *:[v4f32] } 3150:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
15866
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNQf),
15867
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15868
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15869
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15870
0
        GIR_EraseFromParent, /*InsnID*/0,
15871
        // GIR_Coverage, 1727,
15872
0
        GIR_Done,
15873
      // Label 943: @48035
15874
0
      GIM_Try, /*On fail goto*//*Label 944*/ GIMT_Encode4(48083), // Rule ID 1728 //
15875
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15876
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintm),
15877
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15878
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15879
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15880
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15881
        // (intrinsic_wo_chain:{ *:[v4f16] } 3150:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
15882
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNDh),
15883
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15884
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15885
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15886
0
        GIR_EraseFromParent, /*InsnID*/0,
15887
        // GIR_Coverage, 1728,
15888
0
        GIR_Done,
15889
      // Label 944: @48083
15890
0
      GIM_Try, /*On fail goto*//*Label 945*/ GIMT_Encode4(48131), // Rule ID 1729 //
15891
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15892
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintm),
15893
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15894
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15895
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15896
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15897
        // (intrinsic_wo_chain:{ *:[v8f16] } 3150:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
15898
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNQh),
15899
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15900
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15901
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15902
0
        GIR_EraseFromParent, /*InsnID*/0,
15903
        // GIR_Coverage, 1729,
15904
0
        GIR_Done,
15905
      // Label 945: @48131
15906
0
      GIM_Try, /*On fail goto*//*Label 946*/ GIMT_Encode4(48179), // Rule ID 1730 //
15907
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15908
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintp),
15909
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15910
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15911
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15912
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15913
        // (intrinsic_wo_chain:{ *:[v2f32] } 3152:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTPNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
15914
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNDf),
15915
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15916
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15917
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15918
0
        GIR_EraseFromParent, /*InsnID*/0,
15919
        // GIR_Coverage, 1730,
15920
0
        GIR_Done,
15921
      // Label 946: @48179
15922
0
      GIM_Try, /*On fail goto*//*Label 947*/ GIMT_Encode4(48227), // Rule ID 1731 //
15923
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15924
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintp),
15925
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15926
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15927
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15928
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15929
        // (intrinsic_wo_chain:{ *:[v4f32] } 3152:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTPNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
15930
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNQf),
15931
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15932
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15933
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15934
0
        GIR_EraseFromParent, /*InsnID*/0,
15935
        // GIR_Coverage, 1731,
15936
0
        GIR_Done,
15937
      // Label 947: @48227
15938
0
      GIM_Try, /*On fail goto*//*Label 948*/ GIMT_Encode4(48275), // Rule ID 1732 //
15939
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15940
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintp),
15941
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15942
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15943
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15944
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15945
        // (intrinsic_wo_chain:{ *:[v4f16] } 3152:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTPNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
15946
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNDh),
15947
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15948
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15949
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15950
0
        GIR_EraseFromParent, /*InsnID*/0,
15951
        // GIR_Coverage, 1732,
15952
0
        GIR_Done,
15953
      // Label 948: @48275
15954
0
      GIM_Try, /*On fail goto*//*Label 949*/ GIMT_Encode4(48323), // Rule ID 1733 //
15955
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
15956
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintp),
15957
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15958
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15959
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15960
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15961
        // (intrinsic_wo_chain:{ *:[v8f16] } 3152:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTPNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
15962
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNQh),
15963
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15964
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15965
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15966
0
        GIR_EraseFromParent, /*InsnID*/0,
15967
        // GIR_Coverage, 1733,
15968
0
        GIR_Done,
15969
      // Label 949: @48323
15970
0
      GIM_Try, /*On fail goto*//*Label 950*/ GIMT_Encode4(48371), // Rule ID 1736 //
15971
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8),
15972
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesimc),
15973
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
15974
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
15975
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15976
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15977
        // (intrinsic_wo_chain:{ *:[v16i8] } 3040:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (AESIMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
15978
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::AESIMC),
15979
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15980
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15981
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15982
0
        GIR_EraseFromParent, /*InsnID*/0,
15983
        // GIR_Coverage, 1736,
15984
0
        GIR_Done,
15985
      // Label 950: @48371
15986
0
      GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(48419), // Rule ID 1737 //
15987
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8),
15988
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesmc),
15989
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
15990
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
15991
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15992
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15993
        // (intrinsic_wo_chain:{ *:[v16i8] } 3041:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (AESMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
15994
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::AESMC),
15995
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
15996
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15997
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15998
0
        GIR_EraseFromParent, /*InsnID*/0,
15999
        // GIR_Coverage, 1737,
16000
0
        GIR_Done,
16001
      // Label 951: @48419
16002
0
      GIM_Try, /*On fail goto*//*Label 952*/ GIMT_Encode4(48479), // Rule ID 1875 //
16003
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
16004
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtb16),
16005
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16006
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16007
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16008
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
16009
        // (intrinsic_wo_chain:{ *:[i32] } 3240:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src)  =>  (SXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
16010
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SXTB16),
16011
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
16012
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Src
16013
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16014
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16015
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16016
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16017
0
        GIR_EraseFromParent, /*InsnID*/0,
16018
        // GIR_Coverage, 1875,
16019
0
        GIR_Done,
16020
      // Label 952: @48479
16021
0
      GIM_Try, /*On fail goto*//*Label 953*/ GIMT_Encode4(48539), // Rule ID 2112 //
16022
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
16023
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtb16),
16024
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16025
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16026
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16027
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16028
        // (intrinsic_wo_chain:{ *:[i32] } 3240:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn)  =>  (t2SXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 0:{ *:[i32] })
16029
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SXTB16),
16030
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
16031
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16032
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16033
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16034
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16035
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16036
0
        GIR_EraseFromParent, /*InsnID*/0,
16037
        // GIR_Coverage, 2112,
16038
0
        GIR_Done,
16039
      // Label 953: @48539
16040
0
      GIM_Try, /*On fail goto*//*Label 954*/ GIMT_Encode4(48615), // Rule ID 3772 //
16041
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
16042
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcls),
16043
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
16044
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
16045
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16046
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16047
        // (intrinsic_wo_chain:{ *:[v16i8] } 2922:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$val)  =>  (MVE_VCLSs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val)
16048
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16049
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16050
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
16051
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs8),
16052
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
16053
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val
16054
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16055
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16056
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16057
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16058
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16059
0
        GIR_EraseFromParent, /*InsnID*/0,
16060
        // GIR_Coverage, 3772,
16061
0
        GIR_Done,
16062
      // Label 954: @48615
16063
0
      GIM_Try, /*On fail goto*//*Label 955*/ GIMT_Encode4(48691), // Rule ID 3774 //
16064
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
16065
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcls),
16066
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16067
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
16068
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16069
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16070
        // (intrinsic_wo_chain:{ *:[v8i16] } 2922:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$val)  =>  (MVE_VCLSs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val)
16071
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16072
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16073
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
16074
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs16),
16075
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
16076
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val
16077
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16078
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16079
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16080
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16081
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16082
0
        GIR_EraseFromParent, /*InsnID*/0,
16083
        // GIR_Coverage, 3774,
16084
0
        GIR_Done,
16085
      // Label 955: @48691
16086
0
      GIM_Try, /*On fail goto*//*Label 956*/ GIMT_Encode4(48767), // Rule ID 3776 //
16087
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
16088
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcls),
16089
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16090
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
16091
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16092
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16093
        // (intrinsic_wo_chain:{ *:[v4i32] } 2922:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$val)  =>  (MVE_VCLSs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val)
16094
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16095
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16096
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
16097
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs32),
16098
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
16099
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val
16100
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16101
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16102
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16103
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16104
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16105
0
        GIR_EraseFromParent, /*InsnID*/0,
16106
        // GIR_Coverage, 3776,
16107
0
        GIR_Done,
16108
      // Label 956: @48767
16109
0
      GIM_Try, /*On fail goto*//*Label 957*/ GIMT_Encode4(48843), // Rule ID 4088 //
16110
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16111
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintn),
16112
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16113
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
16114
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16115
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16116
        // (intrinsic_wo_chain:{ *:[v8f16] } 3004:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val)  =>  (MVE_VRINTf16N:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
16117
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16118
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16119
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
16120
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16N),
16121
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
16122
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val
16123
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16124
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16125
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16126
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16127
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16128
0
        GIR_EraseFromParent, /*InsnID*/0,
16129
        // GIR_Coverage, 4088,
16130
0
        GIR_Done,
16131
      // Label 957: @48843
16132
0
      GIM_Try, /*On fail goto*//*Label 958*/ GIMT_Encode4(48919), // Rule ID 4100 //
16133
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16134
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintn),
16135
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16136
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
16137
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16138
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16139
        // (intrinsic_wo_chain:{ *:[v4f32] } 3004:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val)  =>  (MVE_VRINTf32N:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
16140
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16141
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16142
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
16143
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32N),
16144
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
16145
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val
16146
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16147
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16148
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16149
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16150
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16151
0
        GIR_EraseFromParent, /*InsnID*/0,
16152
        // GIR_Coverage, 4100,
16153
0
        GIR_Done,
16154
      // Label 958: @48919
16155
0
      GIM_Try, /*On fail goto*//*Label 959*/ GIMT_Encode4(48982), // Rule ID 4990 //
16156
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
16157
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp8),
16158
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s1,
16159
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16160
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
16161
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16162
        // (intrinsic_wo_chain:{ *:[v16i1] } 2930:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn)  =>  (MVE_VCTP8:{ *:[v16i1] } rGPR:{ *:[i32] }:$Rn)
16163
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP8),
16164
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[P0]
16165
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16166
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16167
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16168
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16169
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16170
0
        GIR_EraseFromParent, /*InsnID*/0,
16171
        // GIR_Coverage, 4990,
16172
0
        GIR_Done,
16173
      // Label 959: @48982
16174
0
      GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(49045), // Rule ID 4992 //
16175
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
16176
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp16),
16177
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s1,
16178
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16179
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
16180
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16181
        // (intrinsic_wo_chain:{ *:[v8i1] } 2927:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn)  =>  (MVE_VCTP16:{ *:[v8i1] } rGPR:{ *:[i32] }:$Rn)
16182
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP16),
16183
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[P0]
16184
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16185
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16186
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16187
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16188
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16189
0
        GIR_EraseFromParent, /*InsnID*/0,
16190
        // GIR_Coverage, 4992,
16191
0
        GIR_Done,
16192
      // Label 960: @49045
16193
0
      GIM_Try, /*On fail goto*//*Label 961*/ GIMT_Encode4(49108), // Rule ID 4994 //
16194
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
16195
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp32),
16196
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s1,
16197
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16198
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
16199
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16200
        // (intrinsic_wo_chain:{ *:[v4i1] } 2928:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn)  =>  (MVE_VCTP32:{ *:[v4i1] } rGPR:{ *:[i32] }:$Rn)
16201
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP32),
16202
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[P0]
16203
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16204
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16205
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16206
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16207
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16208
0
        GIR_EraseFromParent, /*InsnID*/0,
16209
        // GIR_Coverage, 4994,
16210
0
        GIR_Done,
16211
      // Label 961: @49108
16212
0
      GIM_Try, /*On fail goto*//*Label 962*/ GIMT_Encode4(49171), // Rule ID 4996 //
16213
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
16214
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp64),
16215
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s1,
16216
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16217
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
16218
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16219
        // (intrinsic_wo_chain:{ *:[v2i1] } 2929:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn)  =>  (MVE_VCTP64:{ *:[v2i1] } rGPR:{ *:[i32] }:$Rn)
16220
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP64),
16221
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[P0]
16222
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16223
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16224
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16225
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16226
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16227
0
        GIR_EraseFromParent, /*InsnID*/0,
16228
        // GIR_Coverage, 4996,
16229
0
        GIR_Done,
16230
      // Label 962: @49171
16231
0
      GIM_Try, /*On fail goto*//*Label 963*/ GIMT_Encode4(49228), // Rule ID 617 //
16232
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb),
16233
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_tt),
16234
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16235
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16236
        // MIs[0] Rn
16237
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
16238
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16239
        // (intrinsic_wo_chain:{ *:[i32] } 2812:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn)  =>  (t2TT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
16240
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2TT),
16241
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rt]
16242
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16243
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16244
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16245
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16246
0
        GIR_EraseFromParent, /*InsnID*/0,
16247
        // GIR_Coverage, 617,
16248
0
        GIR_Done,
16249
      // Label 963: @49228
16250
0
      GIM_Try, /*On fail goto*//*Label 964*/ GIMT_Encode4(49285), // Rule ID 618 //
16251
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb),
16252
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_ttt),
16253
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16254
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16255
        // MIs[0] Rn
16256
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
16257
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16258
        // (intrinsic_wo_chain:{ *:[i32] } 2815:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn)  =>  (t2TTT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
16259
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2TTT),
16260
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rt]
16261
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16262
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16263
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16264
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16265
0
        GIR_EraseFromParent, /*InsnID*/0,
16266
        // GIR_Coverage, 618,
16267
0
        GIR_Done,
16268
      // Label 964: @49285
16269
0
      GIM_Try, /*On fail goto*//*Label 965*/ GIMT_Encode4(49342), // Rule ID 619 //
16270
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb),
16271
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_tta),
16272
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16273
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16274
        // MIs[0] Rn
16275
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
16276
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16277
        // (intrinsic_wo_chain:{ *:[i32] } 2813:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn)  =>  (t2TTA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
16278
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2TTA),
16279
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rt]
16280
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16281
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16282
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16283
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16284
0
        GIR_EraseFromParent, /*InsnID*/0,
16285
        // GIR_Coverage, 619,
16286
0
        GIR_Done,
16287
      // Label 965: @49342
16288
0
      GIM_Try, /*On fail goto*//*Label 966*/ GIMT_Encode4(49399), // Rule ID 620 //
16289
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb),
16290
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_ttat),
16291
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16292
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16293
        // MIs[0] Rn
16294
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
16295
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16296
        // (intrinsic_wo_chain:{ *:[i32] } 2814:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn)  =>  (t2TTAT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
16297
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2TTAT),
16298
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rt]
16299
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16300
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16301
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16302
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16303
0
        GIR_EraseFromParent, /*InsnID*/0,
16304
        // GIR_Coverage, 620,
16305
0
        GIR_Done,
16306
      // Label 966: @49399
16307
0
      GIM_Try, /*On fail goto*//*Label 967*/ GIMT_Encode4(49539), // Rule ID 2720 //
16308
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
16309
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1h),
16310
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16311
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16312
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
16313
        // (intrinsic_wo_chain:{ *:[i32] } 3048:{ *:[iPTR] }, i32:{ *:[i32] }:$Rn)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[f32] } (SHA1H:{ *:[v16i8] } (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$Rn, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }), GPR:{ *:[i32] })
16314
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16315
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
16316
0
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
16317
0
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
16318
0
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16319
0
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16320
0
        GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16321
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
16322
0
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
16323
0
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16324
0
        GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
16325
0
        GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
16326
0
        GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
16327
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
16328
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
16329
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::SHA1H),
16330
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16331
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
16332
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
16333
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16334
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16335
0
        GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
16336
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
16337
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::MQPRRegClassID),
16338
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16339
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
16340
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16341
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
16342
0
        GIR_EraseFromParent, /*InsnID*/0,
16343
        // GIR_Coverage, 2720,
16344
0
        GIR_Done,
16345
      // Label 967: @49539
16346
0
      GIM_Reject,
16347
    // Label 831: @49540
16348
0
    GIM_Try, /*On fail goto*//*Label 968*/ GIMT_Encode4(76329),
16349
0
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
16350
0
      GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(49621), // Rule ID 2130 //
16351
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
16352
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtab16),
16353
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16354
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16355
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16356
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16357
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16358
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16359
        // (intrinsic_wo_chain:{ *:[i32] } 3264:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
16360
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB16),
16361
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
16362
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16363
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16364
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16365
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16366
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16367
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16368
0
        GIR_EraseFromParent, /*InsnID*/0,
16369
        // GIR_Coverage, 2130,
16370
0
        GIR_Done,
16371
      // Label 969: @49621
16372
0
      GIM_Try, /*On fail goto*//*Label 970*/ GIMT_Encode4(49734), // Rule ID 1916 //
16373
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
16374
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat),
16375
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16376
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16377
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16378
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16379
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16380
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
16381
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16382
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16383
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16384
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16385
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16386
0
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
16387
        // MIs[2] Operand 1
16388
        // No operand predicates
16389
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
16390
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16391
0
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
16392
        // MIs[3] Operand 1
16393
        // No operand predicates
16394
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
16395
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
16396
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
16397
        // (intrinsic_wo_chain:{ *:[i32] } 3259:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos)  =>  (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft)
16398
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::USAT),
16399
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
16400
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos
16401
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
16402
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft
16403
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16404
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16405
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16406
0
        GIR_EraseFromParent, /*InsnID*/0,
16407
        // GIR_Coverage, 1916,
16408
0
        GIR_Done,
16409
      // Label 970: @49734
16410
0
      GIM_Try, /*On fail goto*//*Label 971*/ GIMT_Encode4(49847), // Rule ID 2170 //
16411
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
16412
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat),
16413
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16414
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16415
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16416
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16417
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16418
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
16419
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16420
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16421
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16422
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16423
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16424
0
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
16425
        // MIs[2] Operand 1
16426
        // No operand predicates
16427
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
16428
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16429
0
        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
16430
        // MIs[3] Operand 1
16431
        // No operand predicates
16432
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
16433
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
16434
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
16435
        // (intrinsic_wo_chain:{ *:[i32] } 3259:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos)  =>  (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft)
16436
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2USAT),
16437
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
16438
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos
16439
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
16440
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft
16441
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16442
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16443
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16444
0
        GIR_EraseFromParent, /*InsnID*/0,
16445
        // GIR_Coverage, 2170,
16446
0
        GIR_Done,
16447
      // Label 971: @49847
16448
0
      GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(49944), // Rule ID 5556 //
16449
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
16450
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16451
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16452
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16453
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16454
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16455
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16456
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
16457
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16458
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16459
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16460
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16461
        // MIs[1] Rn
16462
0
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16463
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16464
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
16465
        // (intrinsic_wo_chain:{ *:[i32] } 3182:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 3182:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn), GPRnopc:{ *:[i32] }:$Rm)  =>  (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
16466
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::QDADD),
16467
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
16468
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16469
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16470
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16471
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16472
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16473
0
        GIR_EraseFromParent, /*InsnID*/0,
16474
        // GIR_Coverage, 5556,
16475
0
        GIR_Done,
16476
      // Label 972: @49944
16477
0
      GIM_Try, /*On fail goto*//*Label 973*/ GIMT_Encode4(50041), // Rule ID 5813 //
16478
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
16479
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16480
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16481
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16482
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16483
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16484
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16485
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
16486
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16487
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16488
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16489
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16490
        // MIs[1] Rn
16491
0
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16492
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16493
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
16494
        // (intrinsic_wo_chain:{ *:[i32] } 3182:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 3182:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm)  =>  (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
16495
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2QDADD),
16496
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
16497
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16498
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16499
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16500
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16501
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16502
0
        GIR_EraseFromParent, /*InsnID*/0,
16503
        // GIR_Coverage, 5813,
16504
0
        GIR_Done,
16505
      // Label 973: @50041
16506
0
      GIM_Try, /*On fail goto*//*Label 974*/ GIMT_Encode4(50138), // Rule ID 109 //
16507
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
16508
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16509
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16510
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16511
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16512
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16513
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16514
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16515
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
16516
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16517
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16518
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16519
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16520
        // MIs[1] Rn
16521
0
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16522
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
16523
        // (intrinsic_wo_chain:{ *:[i32] } 3182:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 3182:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn))  =>  (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
16524
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::QDADD),
16525
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
16526
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
16527
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16528
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16529
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16530
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16531
0
        GIR_EraseFromParent, /*InsnID*/0,
16532
        // GIR_Coverage, 109,
16533
0
        GIR_Done,
16534
      // Label 974: @50138
16535
0
      GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(50235), // Rule ID 110 //
16536
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
16537
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub),
16538
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16539
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16540
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16541
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16542
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16543
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16544
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
16545
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16546
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16547
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16548
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16549
        // MIs[1] Rn
16550
0
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16551
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
16552
        // (intrinsic_wo_chain:{ *:[i32] } 3187:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 3182:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn))  =>  (QDSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
16553
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::QDSUB),
16554
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
16555
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
16556
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16557
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16558
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16559
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16560
0
        GIR_EraseFromParent, /*InsnID*/0,
16561
        // GIR_Coverage, 110,
16562
0
        GIR_Done,
16563
      // Label 975: @50235
16564
0
      GIM_Try, /*On fail goto*//*Label 976*/ GIMT_Encode4(50332), // Rule ID 2148 //
16565
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
16566
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16567
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16568
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16569
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16570
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16571
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16572
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16573
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
16574
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16575
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16576
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16577
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16578
        // MIs[1] Rn
16579
0
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16580
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
16581
        // (intrinsic_wo_chain:{ *:[i32] } 3182:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 3182:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn))  =>  (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
16582
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2QDADD),
16583
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
16584
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
16585
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16586
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16587
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16588
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16589
0
        GIR_EraseFromParent, /*InsnID*/0,
16590
        // GIR_Coverage, 2148,
16591
0
        GIR_Done,
16592
      // Label 976: @50332
16593
0
      GIM_Try, /*On fail goto*//*Label 977*/ GIMT_Encode4(50429), // Rule ID 2149 //
16594
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
16595
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub),
16596
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16597
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16598
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16599
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16600
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16601
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16602
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
16603
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16604
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16605
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16606
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16607
        // MIs[1] Rn
16608
0
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16609
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
16610
        // (intrinsic_wo_chain:{ *:[i32] } 3187:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 3182:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn))  =>  (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
16611
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2QDSUB),
16612
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
16613
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
16614
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16615
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16616
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16617
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16618
0
        GIR_EraseFromParent, /*InsnID*/0,
16619
        // GIR_Coverage, 2149,
16620
0
        GIR_Done,
16621
      // Label 977: @50429
16622
0
      GIM_Try, /*On fail goto*//*Label 978*/ GIMT_Encode4(50513), // Rule ID 4182 //
16623
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16624
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta),
16625
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16626
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16627
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16628
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16629
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16630
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16631
        // (intrinsic_wo_chain:{ *:[v8i16] } 2938:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in)  =>  (MVE_VCVTs16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16632
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16633
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16634
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
16635
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16a),
16636
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
16637
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16638
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16639
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16640
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16641
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16642
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16643
0
        GIR_EraseFromParent, /*InsnID*/0,
16644
        // GIR_Coverage, 4182,
16645
0
        GIR_Done,
16646
      // Label 978: @50513
16647
0
      GIM_Try, /*On fail goto*//*Label 979*/ GIMT_Encode4(50597), // Rule ID 4184 //
16648
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16649
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn),
16650
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16651
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16652
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16653
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16654
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16655
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16656
        // (intrinsic_wo_chain:{ *:[v8i16] } 2942:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in)  =>  (MVE_VCVTs16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16657
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16658
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16659
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
16660
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16n),
16661
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
16662
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16663
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16664
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16665
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16666
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16667
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16668
0
        GIR_EraseFromParent, /*InsnID*/0,
16669
        // GIR_Coverage, 4184,
16670
0
        GIR_Done,
16671
      // Label 979: @50597
16672
0
      GIM_Try, /*On fail goto*//*Label 980*/ GIMT_Encode4(50681), // Rule ID 4186 //
16673
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16674
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp),
16675
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16676
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16677
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16678
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16679
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16680
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16681
        // (intrinsic_wo_chain:{ *:[v8i16] } 2944:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in)  =>  (MVE_VCVTs16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16682
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16683
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16684
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
16685
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16p),
16686
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
16687
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16688
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16689
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16690
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16691
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16692
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16693
0
        GIR_EraseFromParent, /*InsnID*/0,
16694
        // GIR_Coverage, 4186,
16695
0
        GIR_Done,
16696
      // Label 980: @50681
16697
0
      GIM_Try, /*On fail goto*//*Label 981*/ GIMT_Encode4(50765), // Rule ID 4188 //
16698
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16699
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm),
16700
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16701
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16702
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16703
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16704
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16705
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16706
        // (intrinsic_wo_chain:{ *:[v8i16] } 2940:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in)  =>  (MVE_VCVTs16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16707
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16708
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16709
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
16710
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16m),
16711
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
16712
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16713
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16714
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16715
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16716
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16717
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16718
0
        GIR_EraseFromParent, /*InsnID*/0,
16719
        // GIR_Coverage, 4188,
16720
0
        GIR_Done,
16721
      // Label 981: @50765
16722
0
      GIM_Try, /*On fail goto*//*Label 982*/ GIMT_Encode4(50849), // Rule ID 4190 //
16723
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16724
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta),
16725
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16726
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16727
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16728
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16729
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
16730
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16731
        // (intrinsic_wo_chain:{ *:[v8i16] } 2938:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in)  =>  (MVE_VCVTu16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16732
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16733
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16734
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
16735
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16a),
16736
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
16737
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16738
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16739
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16740
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16741
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16742
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16743
0
        GIR_EraseFromParent, /*InsnID*/0,
16744
        // GIR_Coverage, 4190,
16745
0
        GIR_Done,
16746
      // Label 982: @50849
16747
0
      GIM_Try, /*On fail goto*//*Label 983*/ GIMT_Encode4(50933), // Rule ID 4192 //
16748
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16749
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn),
16750
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16751
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16752
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16753
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16754
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
16755
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16756
        // (intrinsic_wo_chain:{ *:[v8i16] } 2942:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in)  =>  (MVE_VCVTu16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16757
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16758
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16759
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
16760
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16n),
16761
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
16762
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16763
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16764
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16765
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16766
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16767
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16768
0
        GIR_EraseFromParent, /*InsnID*/0,
16769
        // GIR_Coverage, 4192,
16770
0
        GIR_Done,
16771
      // Label 983: @50933
16772
0
      GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(51017), // Rule ID 4194 //
16773
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16774
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp),
16775
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16776
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16777
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16778
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16779
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
16780
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16781
        // (intrinsic_wo_chain:{ *:[v8i16] } 2944:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in)  =>  (MVE_VCVTu16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16782
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16783
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16784
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
16785
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16p),
16786
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
16787
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16788
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16789
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16790
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16791
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16792
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16793
0
        GIR_EraseFromParent, /*InsnID*/0,
16794
        // GIR_Coverage, 4194,
16795
0
        GIR_Done,
16796
      // Label 984: @51017
16797
0
      GIM_Try, /*On fail goto*//*Label 985*/ GIMT_Encode4(51101), // Rule ID 4196 //
16798
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16799
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm),
16800
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16801
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16802
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16803
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16804
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
16805
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16806
        // (intrinsic_wo_chain:{ *:[v8i16] } 2940:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in)  =>  (MVE_VCVTu16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16807
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16808
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16809
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
16810
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16m),
16811
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
16812
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16813
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16814
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16815
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16816
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16817
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16818
0
        GIR_EraseFromParent, /*InsnID*/0,
16819
        // GIR_Coverage, 4196,
16820
0
        GIR_Done,
16821
      // Label 985: @51101
16822
0
      GIM_Try, /*On fail goto*//*Label 986*/ GIMT_Encode4(51185), // Rule ID 4198 //
16823
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16824
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta),
16825
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16826
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16827
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16828
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16829
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16830
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16831
        // (intrinsic_wo_chain:{ *:[v4i32] } 2938:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in)  =>  (MVE_VCVTs32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16832
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16833
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16834
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
16835
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32a),
16836
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
16837
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16838
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16839
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16840
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16841
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16842
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16843
0
        GIR_EraseFromParent, /*InsnID*/0,
16844
        // GIR_Coverage, 4198,
16845
0
        GIR_Done,
16846
      // Label 986: @51185
16847
0
      GIM_Try, /*On fail goto*//*Label 987*/ GIMT_Encode4(51269), // Rule ID 4200 //
16848
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16849
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn),
16850
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16851
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16852
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16853
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16854
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16855
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16856
        // (intrinsic_wo_chain:{ *:[v4i32] } 2942:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in)  =>  (MVE_VCVTs32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16857
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16858
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16859
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
16860
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32n),
16861
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
16862
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16863
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16864
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16865
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16866
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16867
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16868
0
        GIR_EraseFromParent, /*InsnID*/0,
16869
        // GIR_Coverage, 4200,
16870
0
        GIR_Done,
16871
      // Label 987: @51269
16872
0
      GIM_Try, /*On fail goto*//*Label 988*/ GIMT_Encode4(51353), // Rule ID 4202 //
16873
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16874
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp),
16875
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16876
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16877
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16878
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16879
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16880
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16881
        // (intrinsic_wo_chain:{ *:[v4i32] } 2944:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in)  =>  (MVE_VCVTs32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16882
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16883
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16884
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
16885
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32p),
16886
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
16887
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16888
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16889
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16890
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16891
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16892
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16893
0
        GIR_EraseFromParent, /*InsnID*/0,
16894
        // GIR_Coverage, 4202,
16895
0
        GIR_Done,
16896
      // Label 988: @51353
16897
0
      GIM_Try, /*On fail goto*//*Label 989*/ GIMT_Encode4(51437), // Rule ID 4204 //
16898
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16899
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm),
16900
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16901
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16902
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16903
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16904
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16905
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16906
        // (intrinsic_wo_chain:{ *:[v4i32] } 2940:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in)  =>  (MVE_VCVTs32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16907
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16908
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16909
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
16910
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32m),
16911
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
16912
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16913
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16914
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16915
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16916
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16917
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16918
0
        GIR_EraseFromParent, /*InsnID*/0,
16919
        // GIR_Coverage, 4204,
16920
0
        GIR_Done,
16921
      // Label 989: @51437
16922
0
      GIM_Try, /*On fail goto*//*Label 990*/ GIMT_Encode4(51521), // Rule ID 4206 //
16923
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16924
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta),
16925
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16926
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16927
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16928
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16929
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
16930
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16931
        // (intrinsic_wo_chain:{ *:[v4i32] } 2938:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in)  =>  (MVE_VCVTu32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16932
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16933
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16934
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
16935
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32a),
16936
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
16937
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16938
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16939
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16940
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16941
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16942
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16943
0
        GIR_EraseFromParent, /*InsnID*/0,
16944
        // GIR_Coverage, 4206,
16945
0
        GIR_Done,
16946
      // Label 990: @51521
16947
0
      GIM_Try, /*On fail goto*//*Label 991*/ GIMT_Encode4(51605), // Rule ID 4208 //
16948
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16949
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn),
16950
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16951
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16952
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16953
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16954
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
16955
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16956
        // (intrinsic_wo_chain:{ *:[v4i32] } 2942:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in)  =>  (MVE_VCVTu32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16957
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16958
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16959
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
16960
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32n),
16961
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
16962
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16963
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16964
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16965
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16966
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16967
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16968
0
        GIR_EraseFromParent, /*InsnID*/0,
16969
        // GIR_Coverage, 4208,
16970
0
        GIR_Done,
16971
      // Label 991: @51605
16972
0
      GIM_Try, /*On fail goto*//*Label 992*/ GIMT_Encode4(51689), // Rule ID 4210 //
16973
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16974
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp),
16975
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16976
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16977
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16978
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16979
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
16980
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16981
        // (intrinsic_wo_chain:{ *:[v4i32] } 2944:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in)  =>  (MVE_VCVTu32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16982
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16983
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16984
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
16985
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32p),
16986
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
16987
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16988
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16989
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16990
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16991
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16992
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16993
0
        GIR_EraseFromParent, /*InsnID*/0,
16994
        // GIR_Coverage, 4210,
16995
0
        GIR_Done,
16996
      // Label 992: @51689
16997
0
      GIM_Try, /*On fail goto*//*Label 993*/ GIMT_Encode4(51773), // Rule ID 4212 //
16998
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16999
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm),
17000
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17001
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17002
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
17003
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17004
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
17005
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17006
        // (intrinsic_wo_chain:{ *:[v4i32] } 2940:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in)  =>  (MVE_VCVTu32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
17007
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17008
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17009
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
17010
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32m),
17011
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
17012
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
17013
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17014
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17015
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17016
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17017
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17018
0
        GIR_EraseFromParent, /*InsnID*/0,
17019
        // GIR_Coverage, 4212,
17020
0
        GIR_Done,
17021
      // Label 993: @51773
17022
0
      GIM_Try, /*On fail goto*//*Label 994*/ GIMT_Encode4(51857), // Rule ID 4656 //
17023
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17024
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_widen),
17025
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17026
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17027
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17028
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17029
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17030
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17031
        // (intrinsic_wo_chain:{ *:[v4f32] } 2936:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 0:{ *:[i32] })  =>  (MVE_VCVTf32f16bh:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm)
17032
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17033
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17034
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
17035
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32f16bh),
17036
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
17037
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
17038
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17039
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17040
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17041
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17042
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17043
0
        GIR_EraseFromParent, /*InsnID*/0,
17044
        // GIR_Coverage, 4656,
17045
0
        GIR_Done,
17046
      // Label 994: @51857
17047
0
      GIM_Try, /*On fail goto*//*Label 995*/ GIMT_Encode4(51941), // Rule ID 4662 //
17048
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17049
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_widen),
17050
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17051
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17052
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17053
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17054
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17055
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
17056
        // (intrinsic_wo_chain:{ *:[v4f32] } 2936:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 1:{ *:[i32] })  =>  (MVE_VCVTf32f16th:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm)
17057
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17058
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17059
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
17060
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32f16th),
17061
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
17062
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
17063
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17064
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17065
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17066
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17067
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17068
0
        GIR_EraseFromParent, /*InsnID*/0,
17069
        // GIR_Coverage, 4662,
17070
0
        GIR_Done,
17071
      // Label 995: @51941
17072
0
      GIM_Try, /*On fail goto*//*Label 996*/ GIMT_Encode4(52022), // Rule ID 1909 //
17073
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
17074
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat),
17075
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17076
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17077
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17078
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17079
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17080
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17081
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17082
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
17083
        // MIs[1] Operand 1
17084
        // No operand predicates
17085
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17086
        // (intrinsic_wo_chain:{ *:[i32] } 3259:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos)  =>  (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, 0:{ *:[i32] })
17087
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::USAT),
17088
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
17089
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
17090
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
17091
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17092
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17093
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17094
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17095
0
        GIR_EraseFromParent, /*InsnID*/0,
17096
        // GIR_Coverage, 1909,
17097
0
        GIR_Done,
17098
      // Label 996: @52022
17099
0
      GIM_Try, /*On fail goto*//*Label 997*/ GIMT_Encode4(52100), // Rule ID 1913 //
17100
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
17101
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat16),
17102
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17103
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17104
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17105
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17106
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17107
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17108
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17109
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
17110
        // MIs[1] Operand 1
17111
        // No operand predicates
17112
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17113
        // (intrinsic_wo_chain:{ *:[i32] } 3260:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos)  =>  (USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPRnopc:{ *:[i32] }:$a)
17114
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::USAT16),
17115
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
17116
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
17117
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
17118
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17119
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17120
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17121
0
        GIR_EraseFromParent, /*InsnID*/0,
17122
        // GIR_Coverage, 1913,
17123
0
        GIR_Done,
17124
      // Label 997: @52100
17125
0
      GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(52181), // Rule ID 2165 //
17126
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
17127
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat),
17128
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17129
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17130
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17131
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17132
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
17133
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17134
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17135
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
17136
        // MIs[1] Operand 1
17137
        // No operand predicates
17138
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17139
        // (intrinsic_wo_chain:{ *:[i32] } 3259:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos)  =>  (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPR:{ *:[i32] }:$a, 0:{ *:[i32] })
17140
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2USAT),
17141
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
17142
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
17143
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
17144
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17145
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17146
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17147
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17148
0
        GIR_EraseFromParent, /*InsnID*/0,
17149
        // GIR_Coverage, 2165,
17150
0
        GIR_Done,
17151
      // Label 998: @52181
17152
0
      GIM_Try, /*On fail goto*//*Label 999*/ GIMT_Encode4(52259), // Rule ID 2167 //
17153
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
17154
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat16),
17155
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17156
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17157
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17158
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17159
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
17160
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17161
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17162
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
17163
        // MIs[1] Operand 1
17164
        // No operand predicates
17165
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17166
        // (intrinsic_wo_chain:{ *:[i32] } 3260:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos)  =>  (t2USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPR:{ *:[i32] }:$a)
17167
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2USAT16),
17168
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
17169
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
17170
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
17171
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17172
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17173
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17174
0
        GIR_EraseFromParent, /*InsnID*/0,
17175
        // GIR_Coverage, 2167,
17176
0
        GIR_Done,
17177
      // Label 999: @52259
17178
0
      GIM_Try, /*On fail goto*//*Label 1000*/ GIMT_Encode4(52353), // Rule ID 4052 //
17179
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshlu_imm),
17180
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
17181
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
17182
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17183
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17184
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17185
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17186
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17187
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
17188
        // MIs[1] Operand 1
17189
        // No operand predicates
17190
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17191
        // (intrinsic_wo_chain:{ *:[v16i8] } 2997:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)  =>  (MVE_VQSHLU_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
17192
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17193
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17194
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
17195
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms8),
17196
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
17197
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
17198
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17199
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17200
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17201
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17202
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17203
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17204
0
        GIR_EraseFromParent, /*InsnID*/0,
17205
        // GIR_Coverage, 4052,
17206
0
        GIR_Done,
17207
      // Label 1000: @52353
17208
0
      GIM_Try, /*On fail goto*//*Label 1001*/ GIMT_Encode4(52447), // Rule ID 4054 //
17209
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshlu_imm),
17210
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17211
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17212
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17213
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17214
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17215
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17216
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17217
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
17218
        // MIs[1] Operand 1
17219
        // No operand predicates
17220
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17221
        // (intrinsic_wo_chain:{ *:[v8i16] } 2997:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)  =>  (MVE_VQSHLU_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
17222
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17223
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17224
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
17225
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms16),
17226
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
17227
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
17228
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17229
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17230
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17231
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17232
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17233
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17234
0
        GIR_EraseFromParent, /*InsnID*/0,
17235
        // GIR_Coverage, 4054,
17236
0
        GIR_Done,
17237
      // Label 1001: @52447
17238
0
      GIM_Try, /*On fail goto*//*Label 1002*/ GIMT_Encode4(52541), // Rule ID 4056 //
17239
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshlu_imm),
17240
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17241
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17242
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17243
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17244
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17245
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17246
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17247
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
17248
        // MIs[1] Operand 1
17249
        // No operand predicates
17250
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17251
        // (intrinsic_wo_chain:{ *:[v4i32] } 2997:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)  =>  (MVE_VQSHLU_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
17252
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17253
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17254
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
17255
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms32),
17256
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
17257
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
17258
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17259
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17260
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17261
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17262
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17263
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17264
0
        GIR_EraseFromParent, /*InsnID*/0,
17265
        // GIR_Coverage, 4056,
17266
0
        GIR_Done,
17267
      // Label 1002: @52541
17268
0
      GIM_Try, /*On fail goto*//*Label 1003*/ GIMT_Encode4(52615), // Rule ID 1671 //
17269
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
17270
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs),
17271
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
17272
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
17273
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17274
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17275
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17276
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17277
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17278
        // MIs[1] Operand 1
17279
        // No operand predicates
17280
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17281
        // (intrinsic_wo_chain:{ *:[v2i32] } 3075:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTf2xsd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17282
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xsd),
17283
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
17284
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17285
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17286
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17287
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17288
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17289
0
        GIR_EraseFromParent, /*InsnID*/0,
17290
        // GIR_Coverage, 1671,
17291
0
        GIR_Done,
17292
      // Label 1003: @52615
17293
0
      GIM_Try, /*On fail goto*//*Label 1004*/ GIMT_Encode4(52689), // Rule ID 1672 //
17294
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
17295
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu),
17296
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
17297
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
17298
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17299
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17300
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17301
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17302
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17303
        // MIs[1] Operand 1
17304
        // No operand predicates
17305
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17306
        // (intrinsic_wo_chain:{ *:[v2i32] } 3076:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTf2xud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17307
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xud),
17308
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
17309
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17310
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17311
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17312
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17313
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17314
0
        GIR_EraseFromParent, /*InsnID*/0,
17315
        // GIR_Coverage, 1672,
17316
0
        GIR_Done,
17317
      // Label 1004: @52689
17318
0
      GIM_Try, /*On fail goto*//*Label 1005*/ GIMT_Encode4(52763), // Rule ID 1673 //
17319
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
17320
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp),
17321
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
17322
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
17323
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17324
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17325
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17326
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17327
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17328
        // MIs[1] Operand 1
17329
        // No operand predicates
17330
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17331
        // (intrinsic_wo_chain:{ *:[v2f32] } 3078:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17332
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2fd),
17333
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
17334
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17335
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17336
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17337
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17338
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17339
0
        GIR_EraseFromParent, /*InsnID*/0,
17340
        // GIR_Coverage, 1673,
17341
0
        GIR_Done,
17342
      // Label 1005: @52763
17343
0
      GIM_Try, /*On fail goto*//*Label 1006*/ GIMT_Encode4(52837), // Rule ID 1674 //
17344
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
17345
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp),
17346
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
17347
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
17348
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17349
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17350
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17351
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17352
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17353
        // MIs[1] Operand 1
17354
        // No operand predicates
17355
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17356
        // (intrinsic_wo_chain:{ *:[v2f32] } 3079:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17357
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2fd),
17358
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
17359
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17360
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17361
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17362
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17363
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17364
0
        GIR_EraseFromParent, /*InsnID*/0,
17365
        // GIR_Coverage, 1674,
17366
0
        GIR_Done,
17367
      // Label 1006: @52837
17368
0
      GIM_Try, /*On fail goto*//*Label 1007*/ GIMT_Encode4(52911), // Rule ID 1675 //
17369
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
17370
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs),
17371
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
17372
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
17373
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17374
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17375
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17376
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17377
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17378
        // MIs[1] Operand 1
17379
        // No operand predicates
17380
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17381
        // (intrinsic_wo_chain:{ *:[v4i16] } 3075:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTh2xsd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17382
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xsd),
17383
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
17384
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17385
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17386
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17387
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17388
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17389
0
        GIR_EraseFromParent, /*InsnID*/0,
17390
        // GIR_Coverage, 1675,
17391
0
        GIR_Done,
17392
      // Label 1007: @52911
17393
0
      GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(52985), // Rule ID 1676 //
17394
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
17395
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu),
17396
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
17397
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
17398
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17399
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17400
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17401
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17402
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17403
        // MIs[1] Operand 1
17404
        // No operand predicates
17405
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17406
        // (intrinsic_wo_chain:{ *:[v4i16] } 3076:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTh2xud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17407
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xud),
17408
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
17409
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17410
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17411
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17412
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17413
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17414
0
        GIR_EraseFromParent, /*InsnID*/0,
17415
        // GIR_Coverage, 1676,
17416
0
        GIR_Done,
17417
      // Label 1008: @52985
17418
0
      GIM_Try, /*On fail goto*//*Label 1009*/ GIMT_Encode4(53059), // Rule ID 1677 //
17419
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
17420
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp),
17421
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
17422
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
17423
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17424
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17425
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17426
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17427
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17428
        // MIs[1] Operand 1
17429
        // No operand predicates
17430
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17431
        // (intrinsic_wo_chain:{ *:[v4f16] } 3078:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17432
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2hd),
17433
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
17434
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17435
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17436
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17437
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17438
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17439
0
        GIR_EraseFromParent, /*InsnID*/0,
17440
        // GIR_Coverage, 1677,
17441
0
        GIR_Done,
17442
      // Label 1009: @53059
17443
0
      GIM_Try, /*On fail goto*//*Label 1010*/ GIMT_Encode4(53133), // Rule ID 1678 //
17444
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
17445
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp),
17446
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
17447
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
17448
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17449
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17450
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17451
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17452
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17453
        // MIs[1] Operand 1
17454
        // No operand predicates
17455
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17456
        // (intrinsic_wo_chain:{ *:[v4f16] } 3079:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17457
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2hd),
17458
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
17459
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17460
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17461
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17462
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17463
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17464
0
        GIR_EraseFromParent, /*InsnID*/0,
17465
        // GIR_Coverage, 1678,
17466
0
        GIR_Done,
17467
      // Label 1010: @53133
17468
0
      GIM_Try, /*On fail goto*//*Label 1011*/ GIMT_Encode4(53207), // Rule ID 1679 //
17469
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
17470
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs),
17471
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17472
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17473
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17474
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17475
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17476
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17477
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17478
        // MIs[1] Operand 1
17479
        // No operand predicates
17480
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17481
        // (intrinsic_wo_chain:{ *:[v4i32] } 3075:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTf2xsq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17482
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xsq),
17483
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
17484
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17485
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17486
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17487
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17488
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17489
0
        GIR_EraseFromParent, /*InsnID*/0,
17490
        // GIR_Coverage, 1679,
17491
0
        GIR_Done,
17492
      // Label 1011: @53207
17493
0
      GIM_Try, /*On fail goto*//*Label 1012*/ GIMT_Encode4(53281), // Rule ID 1680 //
17494
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
17495
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu),
17496
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17497
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17498
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17499
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17500
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17501
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17502
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17503
        // MIs[1] Operand 1
17504
        // No operand predicates
17505
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17506
        // (intrinsic_wo_chain:{ *:[v4i32] } 3076:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTf2xuq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17507
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xuq),
17508
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
17509
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17510
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17511
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17512
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17513
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17514
0
        GIR_EraseFromParent, /*InsnID*/0,
17515
        // GIR_Coverage, 1680,
17516
0
        GIR_Done,
17517
      // Label 1012: @53281
17518
0
      GIM_Try, /*On fail goto*//*Label 1013*/ GIMT_Encode4(53355), // Rule ID 1681 //
17519
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
17520
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp),
17521
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17522
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17523
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17524
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17525
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17526
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17527
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17528
        // MIs[1] Operand 1
17529
        // No operand predicates
17530
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17531
        // (intrinsic_wo_chain:{ *:[v4f32] } 3078:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17532
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2fq),
17533
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
17534
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17535
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17536
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17537
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17538
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17539
0
        GIR_EraseFromParent, /*InsnID*/0,
17540
        // GIR_Coverage, 1681,
17541
0
        GIR_Done,
17542
      // Label 1013: @53355
17543
0
      GIM_Try, /*On fail goto*//*Label 1014*/ GIMT_Encode4(53429), // Rule ID 1682 //
17544
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
17545
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp),
17546
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17547
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17548
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17549
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17550
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17551
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17552
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17553
        // MIs[1] Operand 1
17554
        // No operand predicates
17555
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17556
        // (intrinsic_wo_chain:{ *:[v4f32] } 3079:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17557
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2fq),
17558
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
17559
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17560
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17561
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17562
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17563
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17564
0
        GIR_EraseFromParent, /*InsnID*/0,
17565
        // GIR_Coverage, 1682,
17566
0
        GIR_Done,
17567
      // Label 1014: @53429
17568
0
      GIM_Try, /*On fail goto*//*Label 1015*/ GIMT_Encode4(53503), // Rule ID 1683 //
17569
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
17570
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs),
17571
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17572
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17573
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17574
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17575
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17576
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17577
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17578
        // MIs[1] Operand 1
17579
        // No operand predicates
17580
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17581
        // (intrinsic_wo_chain:{ *:[v8i16] } 3075:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTh2xsq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17582
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xsq),
17583
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
17584
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17585
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17586
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17587
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17588
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17589
0
        GIR_EraseFromParent, /*InsnID*/0,
17590
        // GIR_Coverage, 1683,
17591
0
        GIR_Done,
17592
      // Label 1015: @53503
17593
0
      GIM_Try, /*On fail goto*//*Label 1016*/ GIMT_Encode4(53577), // Rule ID 1684 //
17594
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
17595
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu),
17596
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17597
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17598
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17599
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17600
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17601
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17602
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17603
        // MIs[1] Operand 1
17604
        // No operand predicates
17605
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17606
        // (intrinsic_wo_chain:{ *:[v8i16] } 3076:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTh2xuq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17607
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xuq),
17608
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
17609
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17610
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17611
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17612
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17613
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17614
0
        GIR_EraseFromParent, /*InsnID*/0,
17615
        // GIR_Coverage, 1684,
17616
0
        GIR_Done,
17617
      // Label 1016: @53577
17618
0
      GIM_Try, /*On fail goto*//*Label 1017*/ GIMT_Encode4(53651), // Rule ID 1685 //
17619
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
17620
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp),
17621
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17622
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17623
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17624
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17625
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17626
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17627
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17628
        // MIs[1] Operand 1
17629
        // No operand predicates
17630
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17631
        // (intrinsic_wo_chain:{ *:[v8f16] } 3078:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17632
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2hq),
17633
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
17634
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17635
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17636
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17637
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17638
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17639
0
        GIR_EraseFromParent, /*InsnID*/0,
17640
        // GIR_Coverage, 1685,
17641
0
        GIR_Done,
17642
      // Label 1017: @53651
17643
0
      GIM_Try, /*On fail goto*//*Label 1018*/ GIMT_Encode4(53725), // Rule ID 1686 //
17644
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
17645
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp),
17646
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17647
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17648
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17649
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17650
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17651
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17652
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17653
        // MIs[1] Operand 1
17654
        // No operand predicates
17655
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17656
        // (intrinsic_wo_chain:{ *:[v8f16] } 3079:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17657
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2hq),
17658
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
17659
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17660
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17661
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17662
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17663
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17664
0
        GIR_EraseFromParent, /*InsnID*/0,
17665
        // GIR_Coverage, 1686,
17666
0
        GIR_Done,
17667
      // Label 1018: @53725
17668
0
      GIM_Try, /*On fail goto*//*Label 1019*/ GIMT_Encode4(53799), // Rule ID 1749 //
17669
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline),
17670
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_sqshl),
17671
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17672
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17673
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17674
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17675
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17676
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17677
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17678
        // MIs[1] Operand 1
17679
        // No operand predicates
17680
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17681
        // (intrinsic_wo_chain:{ *:[i32] } 2902:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)  =>  (MVE_SQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
17682
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_SQSHL),
17683
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
17684
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
17685
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17686
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17687
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17688
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17689
0
        GIR_EraseFromParent, /*InsnID*/0,
17690
        // GIR_Coverage, 1749,
17691
0
        GIR_Done,
17692
      // Label 1019: @53799
17693
0
      GIM_Try, /*On fail goto*//*Label 1020*/ GIMT_Encode4(53873), // Rule ID 1750 //
17694
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline),
17695
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_srshr),
17696
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17697
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17698
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17699
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17700
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17701
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17702
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17703
        // MIs[1] Operand 1
17704
        // No operand predicates
17705
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17706
        // (intrinsic_wo_chain:{ *:[i32] } 2904:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)  =>  (MVE_SRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
17707
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_SRSHR),
17708
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
17709
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
17710
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17711
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17712
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17713
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17714
0
        GIR_EraseFromParent, /*InsnID*/0,
17715
        // GIR_Coverage, 1750,
17716
0
        GIR_Done,
17717
      // Label 1020: @53873
17718
0
      GIM_Try, /*On fail goto*//*Label 1021*/ GIMT_Encode4(53947), // Rule ID 1751 //
17719
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline),
17720
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_uqshl),
17721
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17722
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17723
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17724
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17725
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17726
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17727
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17728
        // MIs[1] Operand 1
17729
        // No operand predicates
17730
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17731
        // (intrinsic_wo_chain:{ *:[i32] } 2909:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)  =>  (MVE_UQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
17732
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_UQSHL),
17733
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
17734
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
17735
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17736
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17737
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17738
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17739
0
        GIR_EraseFromParent, /*InsnID*/0,
17740
        // GIR_Coverage, 1751,
17741
0
        GIR_Done,
17742
      // Label 1021: @53947
17743
0
      GIM_Try, /*On fail goto*//*Label 1022*/ GIMT_Encode4(54021), // Rule ID 1752 //
17744
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline),
17745
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_urshr),
17746
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17747
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17748
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17749
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17750
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17751
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17752
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17753
        // MIs[1] Operand 1
17754
        // No operand predicates
17755
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
17756
        // (intrinsic_wo_chain:{ *:[i32] } 2911:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)  =>  (MVE_URSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
17757
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_URSHR),
17758
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
17759
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
17760
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17761
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17762
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17763
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17764
0
        GIR_EraseFromParent, /*InsnID*/0,
17765
        // GIR_Coverage, 1752,
17766
0
        GIR_Done,
17767
      // Label 1022: @54021
17768
0
      GIM_Try, /*On fail goto*//*Label 1023*/ GIMT_Encode4(54091), // Rule ID 105 //
17769
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
17770
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd8),
17771
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17772
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17773
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17774
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17775
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17776
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17777
        // (intrinsic_wo_chain:{ *:[i32] } 3184:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17778
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::QADD8),
17779
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
17780
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17781
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17782
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17783
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17784
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17785
0
        GIR_EraseFromParent, /*InsnID*/0,
17786
        // GIR_Coverage, 105,
17787
0
        GIR_Done,
17788
      // Label 1023: @54091
17789
0
      GIM_Try, /*On fail goto*//*Label 1024*/ GIMT_Encode4(54161), // Rule ID 106 //
17790
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
17791
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd16),
17792
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17793
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17794
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17795
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17796
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17797
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17798
        // (intrinsic_wo_chain:{ *:[i32] } 3183:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17799
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::QADD16),
17800
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
17801
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17802
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17803
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17804
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17805
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17806
0
        GIR_EraseFromParent, /*InsnID*/0,
17807
        // GIR_Coverage, 106,
17808
0
        GIR_Done,
17809
      // Label 1024: @54161
17810
0
      GIM_Try, /*On fail goto*//*Label 1025*/ GIMT_Encode4(54231), // Rule ID 107 //
17811
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
17812
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub16),
17813
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17814
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17815
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17816
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17817
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17818
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17819
        // (intrinsic_wo_chain:{ *:[i32] } 3188:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17820
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::QSUB16),
17821
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
17822
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17823
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17824
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17825
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17826
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17827
0
        GIR_EraseFromParent, /*InsnID*/0,
17828
        // GIR_Coverage, 107,
17829
0
        GIR_Done,
17830
      // Label 1025: @54231
17831
0
      GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(54301), // Rule ID 108 //
17832
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
17833
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub8),
17834
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17835
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17836
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17837
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17838
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17839
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17840
        // (intrinsic_wo_chain:{ *:[i32] } 3189:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17841
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::QSUB8),
17842
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
17843
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17844
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17845
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17846
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17847
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17848
0
        GIR_EraseFromParent, /*InsnID*/0,
17849
        // GIR_Coverage, 108,
17850
0
        GIR_Done,
17851
      // Label 1026: @54301
17852
0
      GIM_Try, /*On fail goto*//*Label 1027*/ GIMT_Encode4(54371), // Rule ID 111 //
17853
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
17854
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub),
17855
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17856
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17857
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17858
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17859
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17860
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17861
        // (intrinsic_wo_chain:{ *:[i32] } 3187:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)  =>  (QSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
17862
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::QSUB),
17863
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
17864
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
17865
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
17866
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17867
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17868
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17869
0
        GIR_EraseFromParent, /*InsnID*/0,
17870
        // GIR_Coverage, 111,
17871
0
        GIR_Done,
17872
      // Label 1027: @54371
17873
0
      GIM_Try, /*On fail goto*//*Label 1028*/ GIMT_Encode4(54441), // Rule ID 112 //
17874
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
17875
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
17876
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17877
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17878
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17879
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17880
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17881
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17882
        // (intrinsic_wo_chain:{ *:[i32] } 3182:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)  =>  (QADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
17883
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::QADD),
17884
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
17885
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
17886
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
17887
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17888
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17889
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17890
0
        GIR_EraseFromParent, /*InsnID*/0,
17891
        // GIR_Coverage, 112,
17892
0
        GIR_Done,
17893
      // Label 1028: @54441
17894
0
      GIM_Try, /*On fail goto*//*Label 1029*/ GIMT_Encode4(54511), // Rule ID 113 //
17895
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
17896
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd16),
17897
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17898
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17899
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17900
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17901
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17902
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17903
        // (intrinsic_wo_chain:{ *:[i32] } 3251:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17904
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UQADD16),
17905
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
17906
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17907
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17908
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17909
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17910
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17911
0
        GIR_EraseFromParent, /*InsnID*/0,
17912
        // GIR_Coverage, 113,
17913
0
        GIR_Done,
17914
      // Label 1029: @54511
17915
0
      GIM_Try, /*On fail goto*//*Label 1030*/ GIMT_Encode4(54581), // Rule ID 114 //
17916
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
17917
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd8),
17918
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17919
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17920
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17921
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17922
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17923
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17924
        // (intrinsic_wo_chain:{ *:[i32] } 3252:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17925
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UQADD8),
17926
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
17927
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17928
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17929
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17930
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17931
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17932
0
        GIR_EraseFromParent, /*InsnID*/0,
17933
        // GIR_Coverage, 114,
17934
0
        GIR_Done,
17935
      // Label 1030: @54581
17936
0
      GIM_Try, /*On fail goto*//*Label 1031*/ GIMT_Encode4(54651), // Rule ID 115 //
17937
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
17938
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub16),
17939
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17940
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17941
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17942
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17943
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17944
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17945
        // (intrinsic_wo_chain:{ *:[i32] } 3255:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17946
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UQSUB16),
17947
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
17948
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17949
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17950
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17951
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17952
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17953
0
        GIR_EraseFromParent, /*InsnID*/0,
17954
        // GIR_Coverage, 115,
17955
0
        GIR_Done,
17956
      // Label 1031: @54651
17957
0
      GIM_Try, /*On fail goto*//*Label 1032*/ GIMT_Encode4(54721), // Rule ID 116 //
17958
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
17959
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub8),
17960
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17961
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17962
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17963
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17964
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17965
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17966
        // (intrinsic_wo_chain:{ *:[i32] } 3256:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17967
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UQSUB8),
17968
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
17969
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17970
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17971
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17972
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17973
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17974
0
        GIR_EraseFromParent, /*InsnID*/0,
17975
        // GIR_Coverage, 116,
17976
0
        GIR_Done,
17977
      // Label 1032: @54721
17978
0
      GIM_Try, /*On fail goto*//*Label 1033*/ GIMT_Encode4(54791), // Rule ID 117 //
17979
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
17980
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qasx),
17981
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17982
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17983
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17984
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17985
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17986
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17987
        // (intrinsic_wo_chain:{ *:[i32] } 3185:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17988
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::QASX),
17989
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
17990
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17991
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17992
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17993
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17994
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17995
0
        GIR_EraseFromParent, /*InsnID*/0,
17996
        // GIR_Coverage, 117,
17997
0
        GIR_Done,
17998
      // Label 1033: @54791
17999
0
      GIM_Try, /*On fail goto*//*Label 1034*/ GIMT_Encode4(54861), // Rule ID 118 //
18000
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18001
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsax),
18002
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18003
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18004
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18005
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18006
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18007
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18008
        // (intrinsic_wo_chain:{ *:[i32] } 3186:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18009
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::QSAX),
18010
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18011
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18012
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18013
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18014
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18015
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18016
0
        GIR_EraseFromParent, /*InsnID*/0,
18017
        // GIR_Coverage, 118,
18018
0
        GIR_Done,
18019
      // Label 1034: @54861
18020
0
      GIM_Try, /*On fail goto*//*Label 1035*/ GIMT_Encode4(54931), // Rule ID 119 //
18021
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18022
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqasx),
18023
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18024
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18025
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18026
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18027
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18028
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18029
        // (intrinsic_wo_chain:{ *:[i32] } 3253:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18030
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UQASX),
18031
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18032
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18033
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18034
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18035
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18036
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18037
0
        GIR_EraseFromParent, /*InsnID*/0,
18038
        // GIR_Coverage, 119,
18039
0
        GIR_Done,
18040
      // Label 1035: @54931
18041
0
      GIM_Try, /*On fail goto*//*Label 1036*/ GIMT_Encode4(55001), // Rule ID 120 //
18042
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18043
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsax),
18044
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18045
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18046
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18047
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18048
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18049
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18050
        // (intrinsic_wo_chain:{ *:[i32] } 3254:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18051
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UQSAX),
18052
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18053
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18054
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18055
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18056
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18057
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18058
0
        GIR_EraseFromParent, /*InsnID*/0,
18059
        // GIR_Coverage, 120,
18060
0
        GIR_Done,
18061
      // Label 1036: @55001
18062
0
      GIM_Try, /*On fail goto*//*Label 1037*/ GIMT_Encode4(55071), // Rule ID 133 //
18063
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18064
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shasx),
18065
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18066
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18067
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18068
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18069
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18070
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18071
        // (intrinsic_wo_chain:{ *:[i32] } 3197:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18072
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SHASX),
18073
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18074
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18075
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18076
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18077
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18078
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18079
0
        GIR_EraseFromParent, /*InsnID*/0,
18080
        // GIR_Coverage, 133,
18081
0
        GIR_Done,
18082
      // Label 1037: @55071
18083
0
      GIM_Try, /*On fail goto*//*Label 1038*/ GIMT_Encode4(55141), // Rule ID 134 //
18084
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18085
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd16),
18086
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18087
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18088
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18089
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18090
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18091
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18092
        // (intrinsic_wo_chain:{ *:[i32] } 3195:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18093
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SHADD16),
18094
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18095
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18096
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18097
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18098
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18099
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18100
0
        GIR_EraseFromParent, /*InsnID*/0,
18101
        // GIR_Coverage, 134,
18102
0
        GIR_Done,
18103
      // Label 1038: @55141
18104
0
      GIM_Try, /*On fail goto*//*Label 1039*/ GIMT_Encode4(55211), // Rule ID 135 //
18105
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18106
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd8),
18107
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18108
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18109
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18110
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18111
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18112
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18113
        // (intrinsic_wo_chain:{ *:[i32] } 3196:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18114
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SHADD8),
18115
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18116
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18117
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18118
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18119
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18120
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18121
0
        GIR_EraseFromParent, /*InsnID*/0,
18122
        // GIR_Coverage, 135,
18123
0
        GIR_Done,
18124
      // Label 1039: @55211
18125
0
      GIM_Try, /*On fail goto*//*Label 1040*/ GIMT_Encode4(55281), // Rule ID 136 //
18126
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18127
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsax),
18128
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18129
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18130
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18131
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18132
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18133
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18134
        // (intrinsic_wo_chain:{ *:[i32] } 3198:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18135
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SHSAX),
18136
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18137
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18138
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18139
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18140
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18141
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18142
0
        GIR_EraseFromParent, /*InsnID*/0,
18143
        // GIR_Coverage, 136,
18144
0
        GIR_Done,
18145
      // Label 1040: @55281
18146
0
      GIM_Try, /*On fail goto*//*Label 1041*/ GIMT_Encode4(55351), // Rule ID 137 //
18147
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18148
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub16),
18149
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18150
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18151
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18152
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18153
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18154
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18155
        // (intrinsic_wo_chain:{ *:[i32] } 3199:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18156
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SHSUB16),
18157
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18158
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18159
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18160
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18161
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18162
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18163
0
        GIR_EraseFromParent, /*InsnID*/0,
18164
        // GIR_Coverage, 137,
18165
0
        GIR_Done,
18166
      // Label 1041: @55351
18167
0
      GIM_Try, /*On fail goto*//*Label 1042*/ GIMT_Encode4(55421), // Rule ID 138 //
18168
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18169
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub8),
18170
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18171
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18172
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18173
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18174
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18175
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18176
        // (intrinsic_wo_chain:{ *:[i32] } 3200:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18177
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SHSUB8),
18178
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18179
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18180
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18181
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18182
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18183
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18184
0
        GIR_EraseFromParent, /*InsnID*/0,
18185
        // GIR_Coverage, 138,
18186
0
        GIR_Done,
18187
      // Label 1042: @55421
18188
0
      GIM_Try, /*On fail goto*//*Label 1043*/ GIMT_Encode4(55491), // Rule ID 139 //
18189
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18190
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhasx),
18191
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18192
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18193
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18194
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18195
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18196
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18197
        // (intrinsic_wo_chain:{ *:[i32] } 3246:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18198
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UHASX),
18199
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18200
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18201
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18202
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18203
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18204
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18205
0
        GIR_EraseFromParent, /*InsnID*/0,
18206
        // GIR_Coverage, 139,
18207
0
        GIR_Done,
18208
      // Label 1043: @55491
18209
0
      GIM_Try, /*On fail goto*//*Label 1044*/ GIMT_Encode4(55561), // Rule ID 140 //
18210
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18211
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd16),
18212
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18213
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18214
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18215
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18216
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18217
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18218
        // (intrinsic_wo_chain:{ *:[i32] } 3244:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18219
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UHADD16),
18220
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18221
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18222
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18223
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18224
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18225
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18226
0
        GIR_EraseFromParent, /*InsnID*/0,
18227
        // GIR_Coverage, 140,
18228
0
        GIR_Done,
18229
      // Label 1044: @55561
18230
0
      GIM_Try, /*On fail goto*//*Label 1045*/ GIMT_Encode4(55631), // Rule ID 141 //
18231
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18232
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd8),
18233
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18234
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18235
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18236
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18237
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18238
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18239
        // (intrinsic_wo_chain:{ *:[i32] } 3245:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18240
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UHADD8),
18241
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18242
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18243
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18244
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18245
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18246
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18247
0
        GIR_EraseFromParent, /*InsnID*/0,
18248
        // GIR_Coverage, 141,
18249
0
        GIR_Done,
18250
      // Label 1045: @55631
18251
0
      GIM_Try, /*On fail goto*//*Label 1046*/ GIMT_Encode4(55701), // Rule ID 142 //
18252
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18253
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsax),
18254
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18255
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18256
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18257
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18258
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18259
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18260
        // (intrinsic_wo_chain:{ *:[i32] } 3247:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18261
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UHSAX),
18262
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18263
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18264
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18265
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18266
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18267
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18268
0
        GIR_EraseFromParent, /*InsnID*/0,
18269
        // GIR_Coverage, 142,
18270
0
        GIR_Done,
18271
      // Label 1046: @55701
18272
0
      GIM_Try, /*On fail goto*//*Label 1047*/ GIMT_Encode4(55771), // Rule ID 143 //
18273
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18274
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub16),
18275
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18276
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18277
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18278
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18279
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18280
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18281
        // (intrinsic_wo_chain:{ *:[i32] } 3248:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18282
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UHSUB16),
18283
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18284
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18285
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18286
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18287
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18288
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18289
0
        GIR_EraseFromParent, /*InsnID*/0,
18290
        // GIR_Coverage, 143,
18291
0
        GIR_Done,
18292
      // Label 1047: @55771
18293
0
      GIM_Try, /*On fail goto*//*Label 1048*/ GIMT_Encode4(55841), // Rule ID 144 //
18294
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18295
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub8),
18296
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18297
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18298
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18299
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18300
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18301
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18302
        // (intrinsic_wo_chain:{ *:[i32] } 3249:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18303
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UHSUB8),
18304
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18305
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18306
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18307
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18308
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18309
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18310
0
        GIR_EraseFromParent, /*InsnID*/0,
18311
        // GIR_Coverage, 144,
18312
0
        GIR_Done,
18313
      // Label 1048: @55841
18314
0
      GIM_Try, /*On fail goto*//*Label 1049*/ GIMT_Encode4(55911), // Rule ID 145 //
18315
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
18316
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usad8),
18317
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18318
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18319
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18320
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
18321
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
18322
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
18323
        // (intrinsic_wo_chain:{ *:[i32] } 3257:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (USAD8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
18324
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::USAD8),
18325
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18326
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18327
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18328
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18329
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18330
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18331
0
        GIR_EraseFromParent, /*InsnID*/0,
18332
        // GIR_Coverage, 145,
18333
0
        GIR_Done,
18334
      // Label 1049: @55911
18335
0
      GIM_Try, /*On fail goto*//*Label 1050*/ GIMT_Encode4(55972), // Rule ID 204 //
18336
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM),
18337
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32b),
18338
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18339
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18340
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18341
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18342
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18343
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18344
        // (intrinsic_wo_chain:{ *:[i32] } 2816:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32B:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18345
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::CRC32B),
18346
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18347
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18348
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18349
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18350
0
        GIR_EraseFromParent, /*InsnID*/0,
18351
        // GIR_Coverage, 204,
18352
0
        GIR_Done,
18353
      // Label 1050: @55972
18354
0
      GIM_Try, /*On fail goto*//*Label 1051*/ GIMT_Encode4(56033), // Rule ID 205 //
18355
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM),
18356
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cb),
18357
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18358
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18359
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18360
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18361
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18362
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18363
        // (intrinsic_wo_chain:{ *:[i32] } 2817:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32CB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18364
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::CRC32CB),
18365
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18366
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18367
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18368
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18369
0
        GIR_EraseFromParent, /*InsnID*/0,
18370
        // GIR_Coverage, 205,
18371
0
        GIR_Done,
18372
      // Label 1051: @56033
18373
0
      GIM_Try, /*On fail goto*//*Label 1052*/ GIMT_Encode4(56094), // Rule ID 206 //
18374
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM),
18375
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32h),
18376
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18377
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18378
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18379
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18380
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18381
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18382
        // (intrinsic_wo_chain:{ *:[i32] } 2820:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32H:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18383
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::CRC32H),
18384
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18385
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18386
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18387
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18388
0
        GIR_EraseFromParent, /*InsnID*/0,
18389
        // GIR_Coverage, 206,
18390
0
        GIR_Done,
18391
      // Label 1052: @56094
18392
0
      GIM_Try, /*On fail goto*//*Label 1053*/ GIMT_Encode4(56155), // Rule ID 207 //
18393
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM),
18394
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32ch),
18395
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18396
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18397
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18398
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18399
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18400
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18401
        // (intrinsic_wo_chain:{ *:[i32] } 2818:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32CH:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18402
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::CRC32CH),
18403
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18404
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18405
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18406
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18407
0
        GIR_EraseFromParent, /*InsnID*/0,
18408
        // GIR_Coverage, 207,
18409
0
        GIR_Done,
18410
      // Label 1053: @56155
18411
0
      GIM_Try, /*On fail goto*//*Label 1054*/ GIMT_Encode4(56216), // Rule ID 208 //
18412
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM),
18413
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32w),
18414
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18415
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18416
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18417
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18418
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18419
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18420
        // (intrinsic_wo_chain:{ *:[i32] } 2821:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32W:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18421
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::CRC32W),
18422
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18423
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18424
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18425
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18426
0
        GIR_EraseFromParent, /*InsnID*/0,
18427
        // GIR_Coverage, 208,
18428
0
        GIR_Done,
18429
      // Label 1054: @56216
18430
0
      GIM_Try, /*On fail goto*//*Label 1055*/ GIMT_Encode4(56277), // Rule ID 209 //
18431
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM),
18432
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cw),
18433
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18434
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18435
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18436
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18437
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18438
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18439
        // (intrinsic_wo_chain:{ *:[i32] } 2819:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32CW:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18440
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::CRC32CW),
18441
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18442
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18443
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18444
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18445
0
        GIR_EraseFromParent, /*InsnID*/0,
18446
        // GIR_Coverage, 209,
18447
0
        GIR_Done,
18448
      // Label 1055: @56277
18449
0
      GIM_Try, /*On fail goto*//*Label 1056*/ GIMT_Encode4(56347), // Rule ID 440 //
18450
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18451
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd16),
18452
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18453
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18454
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18455
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18456
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18457
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18458
        // (intrinsic_wo_chain:{ *:[i32] } 3183:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18459
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2QADD16),
18460
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18461
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18462
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18463
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18464
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18465
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18466
0
        GIR_EraseFromParent, /*InsnID*/0,
18467
        // GIR_Coverage, 440,
18468
0
        GIR_Done,
18469
      // Label 1056: @56347
18470
0
      GIM_Try, /*On fail goto*//*Label 1057*/ GIMT_Encode4(56417), // Rule ID 441 //
18471
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18472
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd8),
18473
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18474
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18475
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18476
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18477
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18478
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18479
        // (intrinsic_wo_chain:{ *:[i32] } 3184:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18480
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2QADD8),
18481
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18482
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18483
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18484
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18485
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18486
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18487
0
        GIR_EraseFromParent, /*InsnID*/0,
18488
        // GIR_Coverage, 441,
18489
0
        GIR_Done,
18490
      // Label 1057: @56417
18491
0
      GIM_Try, /*On fail goto*//*Label 1058*/ GIMT_Encode4(56487), // Rule ID 442 //
18492
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18493
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qasx),
18494
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18495
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18496
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18497
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18498
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18499
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18500
        // (intrinsic_wo_chain:{ *:[i32] } 3185:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18501
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2QASX),
18502
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18503
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18504
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18505
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18506
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18507
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18508
0
        GIR_EraseFromParent, /*InsnID*/0,
18509
        // GIR_Coverage, 442,
18510
0
        GIR_Done,
18511
      // Label 1058: @56487
18512
0
      GIM_Try, /*On fail goto*//*Label 1059*/ GIMT_Encode4(56557), // Rule ID 443 //
18513
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18514
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub8),
18515
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18516
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18517
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18518
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18519
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18520
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18521
        // (intrinsic_wo_chain:{ *:[i32] } 3256:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18522
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UQSUB8),
18523
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18524
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18525
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18526
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18527
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18528
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18529
0
        GIR_EraseFromParent, /*InsnID*/0,
18530
        // GIR_Coverage, 443,
18531
0
        GIR_Done,
18532
      // Label 1059: @56557
18533
0
      GIM_Try, /*On fail goto*//*Label 1060*/ GIMT_Encode4(56627), // Rule ID 444 //
18534
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18535
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsax),
18536
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18537
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18538
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18539
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18540
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18541
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18542
        // (intrinsic_wo_chain:{ *:[i32] } 3186:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18543
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2QSAX),
18544
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18545
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18546
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18547
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18548
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18549
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18550
0
        GIR_EraseFromParent, /*InsnID*/0,
18551
        // GIR_Coverage, 444,
18552
0
        GIR_Done,
18553
      // Label 1060: @56627
18554
0
      GIM_Try, /*On fail goto*//*Label 1061*/ GIMT_Encode4(56697), // Rule ID 445 //
18555
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18556
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub16),
18557
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18558
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18559
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18560
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18561
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18562
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18563
        // (intrinsic_wo_chain:{ *:[i32] } 3188:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18564
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2QSUB16),
18565
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18566
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18567
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18568
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18569
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18570
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18571
0
        GIR_EraseFromParent, /*InsnID*/0,
18572
        // GIR_Coverage, 445,
18573
0
        GIR_Done,
18574
      // Label 1061: @56697
18575
0
      GIM_Try, /*On fail goto*//*Label 1062*/ GIMT_Encode4(56767), // Rule ID 446 //
18576
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18577
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub8),
18578
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18579
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18580
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18581
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18582
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18583
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18584
        // (intrinsic_wo_chain:{ *:[i32] } 3189:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18585
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2QSUB8),
18586
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18587
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18588
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18589
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18590
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18591
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18592
0
        GIR_EraseFromParent, /*InsnID*/0,
18593
        // GIR_Coverage, 446,
18594
0
        GIR_Done,
18595
      // Label 1062: @56767
18596
0
      GIM_Try, /*On fail goto*//*Label 1063*/ GIMT_Encode4(56837), // Rule ID 447 //
18597
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18598
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd16),
18599
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18600
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18601
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18602
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18603
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18604
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18605
        // (intrinsic_wo_chain:{ *:[i32] } 3251:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18606
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UQADD16),
18607
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18608
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18609
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18610
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18611
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18612
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18613
0
        GIR_EraseFromParent, /*InsnID*/0,
18614
        // GIR_Coverage, 447,
18615
0
        GIR_Done,
18616
      // Label 1063: @56837
18617
0
      GIM_Try, /*On fail goto*//*Label 1064*/ GIMT_Encode4(56907), // Rule ID 448 //
18618
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18619
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd8),
18620
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18621
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18622
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18623
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18624
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18625
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18626
        // (intrinsic_wo_chain:{ *:[i32] } 3252:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18627
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UQADD8),
18628
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18629
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18630
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18631
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18632
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18633
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18634
0
        GIR_EraseFromParent, /*InsnID*/0,
18635
        // GIR_Coverage, 448,
18636
0
        GIR_Done,
18637
      // Label 1064: @56907
18638
0
      GIM_Try, /*On fail goto*//*Label 1065*/ GIMT_Encode4(56977), // Rule ID 449 //
18639
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18640
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqasx),
18641
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18642
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18643
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18644
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18645
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18646
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18647
        // (intrinsic_wo_chain:{ *:[i32] } 3253:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18648
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UQASX),
18649
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18650
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18651
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18652
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18653
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18654
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18655
0
        GIR_EraseFromParent, /*InsnID*/0,
18656
        // GIR_Coverage, 449,
18657
0
        GIR_Done,
18658
      // Label 1065: @56977
18659
0
      GIM_Try, /*On fail goto*//*Label 1066*/ GIMT_Encode4(57047), // Rule ID 450 //
18660
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18661
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsax),
18662
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18663
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18664
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18665
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18666
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18667
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18668
        // (intrinsic_wo_chain:{ *:[i32] } 3254:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18669
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UQSAX),
18670
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18671
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18672
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18673
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18674
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18675
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18676
0
        GIR_EraseFromParent, /*InsnID*/0,
18677
        // GIR_Coverage, 450,
18678
0
        GIR_Done,
18679
      // Label 1066: @57047
18680
0
      GIM_Try, /*On fail goto*//*Label 1067*/ GIMT_Encode4(57117), // Rule ID 451 //
18681
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18682
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub16),
18683
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18684
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18685
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18686
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18687
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18688
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18689
        // (intrinsic_wo_chain:{ *:[i32] } 3255:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18690
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UQSUB16),
18691
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18692
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18693
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18694
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18695
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18696
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18697
0
        GIR_EraseFromParent, /*InsnID*/0,
18698
        // GIR_Coverage, 451,
18699
0
        GIR_Done,
18700
      // Label 1067: @57117
18701
0
      GIM_Try, /*On fail goto*//*Label 1068*/ GIMT_Encode4(57187), // Rule ID 464 //
18702
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18703
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shasx),
18704
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18705
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18706
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18707
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18708
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18709
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18710
        // (intrinsic_wo_chain:{ *:[i32] } 3197:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18711
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SHASX),
18712
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18713
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18714
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18715
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18716
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18717
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18718
0
        GIR_EraseFromParent, /*InsnID*/0,
18719
        // GIR_Coverage, 464,
18720
0
        GIR_Done,
18721
      // Label 1068: @57187
18722
0
      GIM_Try, /*On fail goto*//*Label 1069*/ GIMT_Encode4(57257), // Rule ID 465 //
18723
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18724
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd16),
18725
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18726
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18727
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18728
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18729
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18730
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18731
        // (intrinsic_wo_chain:{ *:[i32] } 3195:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18732
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SHADD16),
18733
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18734
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18735
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18736
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18737
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18738
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18739
0
        GIR_EraseFromParent, /*InsnID*/0,
18740
        // GIR_Coverage, 465,
18741
0
        GIR_Done,
18742
      // Label 1069: @57257
18743
0
      GIM_Try, /*On fail goto*//*Label 1070*/ GIMT_Encode4(57327), // Rule ID 466 //
18744
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18745
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd8),
18746
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18747
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18748
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18749
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18750
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18751
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18752
        // (intrinsic_wo_chain:{ *:[i32] } 3196:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18753
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SHADD8),
18754
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18755
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18756
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18757
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18758
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18759
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18760
0
        GIR_EraseFromParent, /*InsnID*/0,
18761
        // GIR_Coverage, 466,
18762
0
        GIR_Done,
18763
      // Label 1070: @57327
18764
0
      GIM_Try, /*On fail goto*//*Label 1071*/ GIMT_Encode4(57397), // Rule ID 467 //
18765
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18766
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsax),
18767
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18768
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18769
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18770
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18771
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18772
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18773
        // (intrinsic_wo_chain:{ *:[i32] } 3198:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18774
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SHSAX),
18775
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18776
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18777
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18778
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18779
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18780
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18781
0
        GIR_EraseFromParent, /*InsnID*/0,
18782
        // GIR_Coverage, 467,
18783
0
        GIR_Done,
18784
      // Label 1071: @57397
18785
0
      GIM_Try, /*On fail goto*//*Label 1072*/ GIMT_Encode4(57467), // Rule ID 468 //
18786
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18787
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub16),
18788
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18789
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18790
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18791
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18792
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18793
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18794
        // (intrinsic_wo_chain:{ *:[i32] } 3199:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18795
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SHSUB16),
18796
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18797
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18798
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18799
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18800
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18801
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18802
0
        GIR_EraseFromParent, /*InsnID*/0,
18803
        // GIR_Coverage, 468,
18804
0
        GIR_Done,
18805
      // Label 1072: @57467
18806
0
      GIM_Try, /*On fail goto*//*Label 1073*/ GIMT_Encode4(57537), // Rule ID 469 //
18807
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18808
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub8),
18809
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18810
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18811
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18812
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18813
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18814
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18815
        // (intrinsic_wo_chain:{ *:[i32] } 3200:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18816
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SHSUB8),
18817
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18818
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18819
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18820
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18821
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18822
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18823
0
        GIR_EraseFromParent, /*InsnID*/0,
18824
        // GIR_Coverage, 469,
18825
0
        GIR_Done,
18826
      // Label 1073: @57537
18827
0
      GIM_Try, /*On fail goto*//*Label 1074*/ GIMT_Encode4(57607), // Rule ID 470 //
18828
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18829
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhasx),
18830
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18831
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18832
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18833
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18834
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18835
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18836
        // (intrinsic_wo_chain:{ *:[i32] } 3246:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18837
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UHASX),
18838
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18839
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18840
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18841
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18842
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18843
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18844
0
        GIR_EraseFromParent, /*InsnID*/0,
18845
        // GIR_Coverage, 470,
18846
0
        GIR_Done,
18847
      // Label 1074: @57607
18848
0
      GIM_Try, /*On fail goto*//*Label 1075*/ GIMT_Encode4(57677), // Rule ID 471 //
18849
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18850
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd16),
18851
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18852
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18853
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18854
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18855
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18856
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18857
        // (intrinsic_wo_chain:{ *:[i32] } 3244:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18858
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UHADD16),
18859
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18860
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18861
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18862
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18863
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18864
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18865
0
        GIR_EraseFromParent, /*InsnID*/0,
18866
        // GIR_Coverage, 471,
18867
0
        GIR_Done,
18868
      // Label 1075: @57677
18869
0
      GIM_Try, /*On fail goto*//*Label 1076*/ GIMT_Encode4(57747), // Rule ID 472 //
18870
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18871
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd8),
18872
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18873
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18874
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18875
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18876
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18877
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18878
        // (intrinsic_wo_chain:{ *:[i32] } 3245:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18879
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UHADD8),
18880
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18881
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18882
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18883
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18884
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18885
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18886
0
        GIR_EraseFromParent, /*InsnID*/0,
18887
        // GIR_Coverage, 472,
18888
0
        GIR_Done,
18889
      // Label 1076: @57747
18890
0
      GIM_Try, /*On fail goto*//*Label 1077*/ GIMT_Encode4(57817), // Rule ID 473 //
18891
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18892
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsax),
18893
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18894
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18895
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18896
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18897
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18898
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18899
        // (intrinsic_wo_chain:{ *:[i32] } 3247:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18900
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UHSAX),
18901
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18902
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18903
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18904
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18905
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18906
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18907
0
        GIR_EraseFromParent, /*InsnID*/0,
18908
        // GIR_Coverage, 473,
18909
0
        GIR_Done,
18910
      // Label 1077: @57817
18911
0
      GIM_Try, /*On fail goto*//*Label 1078*/ GIMT_Encode4(57887), // Rule ID 474 //
18912
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18913
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub16),
18914
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18915
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18916
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18917
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18918
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18919
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18920
        // (intrinsic_wo_chain:{ *:[i32] } 3248:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18921
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UHSUB16),
18922
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18923
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18924
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18925
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18926
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18927
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18928
0
        GIR_EraseFromParent, /*InsnID*/0,
18929
        // GIR_Coverage, 474,
18930
0
        GIR_Done,
18931
      // Label 1078: @57887
18932
0
      GIM_Try, /*On fail goto*//*Label 1079*/ GIMT_Encode4(57957), // Rule ID 475 //
18933
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18934
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub8),
18935
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18936
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18937
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18938
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18939
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18940
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18941
        // (intrinsic_wo_chain:{ *:[i32] } 3249:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18942
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UHSUB8),
18943
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18944
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18945
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18946
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18947
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18948
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18949
0
        GIR_EraseFromParent, /*InsnID*/0,
18950
        // GIR_Coverage, 475,
18951
0
        GIR_Done,
18952
      // Label 1079: @57957
18953
0
      GIM_Try, /*On fail goto*//*Label 1080*/ GIMT_Encode4(58027), // Rule ID 476 //
18954
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18955
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usad8),
18956
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18957
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18958
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18959
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18960
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18961
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18962
        // (intrinsic_wo_chain:{ *:[i32] } 3257:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2USAD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18963
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2USAD8),
18964
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18965
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18966
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18967
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18968
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18969
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18970
0
        GIR_EraseFromParent, /*InsnID*/0,
18971
        // GIR_Coverage, 476,
18972
0
        GIR_Done,
18973
      // Label 1080: @58027
18974
0
      GIM_Try, /*On fail goto*//*Label 1081*/ GIMT_Encode4(58097), // Rule ID 532 //
18975
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18976
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuad),
18977
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18978
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18979
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18980
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18981
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18982
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18983
        // (intrinsic_wo_chain:{ *:[i32] } 3215:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMUAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18984
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMUAD),
18985
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
18986
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18987
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18988
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18989
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18990
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18991
0
        GIR_EraseFromParent, /*InsnID*/0,
18992
        // GIR_Coverage, 532,
18993
0
        GIR_Done,
18994
      // Label 1081: @58097
18995
0
      GIM_Try, /*On fail goto*//*Label 1082*/ GIMT_Encode4(58167), // Rule ID 533 //
18996
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
18997
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuadx),
18998
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18999
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19000
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19001
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19002
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19003
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19004
        // (intrinsic_wo_chain:{ *:[i32] } 3216:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMUADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19005
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMUADX),
19006
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
19007
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19008
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19009
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19010
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19011
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19012
0
        GIR_EraseFromParent, /*InsnID*/0,
19013
        // GIR_Coverage, 533,
19014
0
        GIR_Done,
19015
      // Label 1082: @58167
19016
0
      GIM_Try, /*On fail goto*//*Label 1083*/ GIMT_Encode4(58237), // Rule ID 534 //
19017
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19018
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusd),
19019
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19020
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19021
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19022
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19023
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19024
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19025
        // (intrinsic_wo_chain:{ *:[i32] } 3223:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMUSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19026
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMUSD),
19027
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
19028
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19029
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19030
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19031
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19032
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19033
0
        GIR_EraseFromParent, /*InsnID*/0,
19034
        // GIR_Coverage, 534,
19035
0
        GIR_Done,
19036
      // Label 1083: @58237
19037
0
      GIM_Try, /*On fail goto*//*Label 1084*/ GIMT_Encode4(58307), // Rule ID 535 //
19038
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19039
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusdx),
19040
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19041
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19042
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19043
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19044
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19045
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19046
        // (intrinsic_wo_chain:{ *:[i32] } 3224:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMUSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19047
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMUSDX),
19048
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
19049
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19050
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19051
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19052
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19053
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19054
0
        GIR_EraseFromParent, /*InsnID*/0,
19055
        // GIR_Coverage, 535,
19056
0
        GIR_Done,
19057
      // Label 1084: @58307
19058
0
      GIM_Try, /*On fail goto*//*Label 1085*/ GIMT_Encode4(58368), // Rule ID 549 //
19059
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2),
19060
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32b),
19061
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19062
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19063
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19064
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19065
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19066
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19067
        // (intrinsic_wo_chain:{ *:[i32] } 2816:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32B:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19068
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2CRC32B),
19069
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
19070
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19071
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19072
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19073
0
        GIR_EraseFromParent, /*InsnID*/0,
19074
        // GIR_Coverage, 549,
19075
0
        GIR_Done,
19076
      // Label 1085: @58368
19077
0
      GIM_Try, /*On fail goto*//*Label 1086*/ GIMT_Encode4(58429), // Rule ID 550 //
19078
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2),
19079
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cb),
19080
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19081
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19082
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19083
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19084
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19085
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19086
        // (intrinsic_wo_chain:{ *:[i32] } 2817:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32CB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19087
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CB),
19088
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
19089
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19090
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19091
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19092
0
        GIR_EraseFromParent, /*InsnID*/0,
19093
        // GIR_Coverage, 550,
19094
0
        GIR_Done,
19095
      // Label 1086: @58429
19096
0
      GIM_Try, /*On fail goto*//*Label 1087*/ GIMT_Encode4(58490), // Rule ID 551 //
19097
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2),
19098
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32h),
19099
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19100
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19101
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19102
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19103
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19104
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19105
        // (intrinsic_wo_chain:{ *:[i32] } 2820:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32H:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19106
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2CRC32H),
19107
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
19108
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19109
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19110
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19111
0
        GIR_EraseFromParent, /*InsnID*/0,
19112
        // GIR_Coverage, 551,
19113
0
        GIR_Done,
19114
      // Label 1087: @58490
19115
0
      GIM_Try, /*On fail goto*//*Label 1088*/ GIMT_Encode4(58551), // Rule ID 552 //
19116
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2),
19117
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32ch),
19118
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19119
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19120
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19121
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19122
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19123
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19124
        // (intrinsic_wo_chain:{ *:[i32] } 2818:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32CH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19125
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CH),
19126
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
19127
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19128
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19129
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19130
0
        GIR_EraseFromParent, /*InsnID*/0,
19131
        // GIR_Coverage, 552,
19132
0
        GIR_Done,
19133
      // Label 1088: @58551
19134
0
      GIM_Try, /*On fail goto*//*Label 1089*/ GIMT_Encode4(58612), // Rule ID 553 //
19135
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2),
19136
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32w),
19137
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19138
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19139
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19140
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19141
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19142
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19143
        // (intrinsic_wo_chain:{ *:[i32] } 2821:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32W:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19144
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2CRC32W),
19145
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
19146
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19147
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19148
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19149
0
        GIR_EraseFromParent, /*InsnID*/0,
19150
        // GIR_Coverage, 553,
19151
0
        GIR_Done,
19152
      // Label 1089: @58612
19153
0
      GIM_Try, /*On fail goto*//*Label 1090*/ GIMT_Encode4(58673), // Rule ID 554 //
19154
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2),
19155
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cw),
19156
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19157
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19158
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19159
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19160
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19161
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19162
        // (intrinsic_wo_chain:{ *:[i32] } 2819:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32CW:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19163
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CW),
19164
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
19165
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19166
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19167
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19168
0
        GIR_EraseFromParent, /*InsnID*/0,
19169
        // GIR_Coverage, 554,
19170
0
        GIR_Done,
19171
      // Label 1090: @58673
19172
0
      GIM_Try, /*On fail goto*//*Label 1091*/ GIMT_Encode4(58743), // Rule ID 809 //
19173
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19174
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds),
19175
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19176
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19177
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19178
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19179
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19180
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19181
        // (intrinsic_wo_chain:{ *:[v4i16] } 3087:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19182
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHADDsv4i16),
19183
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19184
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19185
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19186
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19187
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19188
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19189
0
        GIR_EraseFromParent, /*InsnID*/0,
19190
        // GIR_Coverage, 809,
19191
0
        GIR_Done,
19192
      // Label 1091: @58743
19193
0
      GIM_Try, /*On fail goto*//*Label 1092*/ GIMT_Encode4(58813), // Rule ID 810 //
19194
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19195
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds),
19196
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19197
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19198
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19199
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19200
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19201
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19202
        // (intrinsic_wo_chain:{ *:[v2i32] } 3087:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19203
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHADDsv2i32),
19204
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19205
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19206
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19207
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19208
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19209
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19210
0
        GIR_EraseFromParent, /*InsnID*/0,
19211
        // GIR_Coverage, 810,
19212
0
        GIR_Done,
19213
      // Label 1092: @58813
19214
0
      GIM_Try, /*On fail goto*//*Label 1093*/ GIMT_Encode4(58883), // Rule ID 811 //
19215
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19216
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds),
19217
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19218
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19219
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19220
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19221
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19222
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19223
        // (intrinsic_wo_chain:{ *:[v8i16] } 3087:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19224
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHADDsv8i16),
19225
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19226
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19227
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19228
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19229
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19230
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19231
0
        GIR_EraseFromParent, /*InsnID*/0,
19232
        // GIR_Coverage, 811,
19233
0
        GIR_Done,
19234
      // Label 1093: @58883
19235
0
      GIM_Try, /*On fail goto*//*Label 1094*/ GIMT_Encode4(58953), // Rule ID 812 //
19236
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19237
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds),
19238
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19239
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19240
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19241
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19242
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19243
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19244
        // (intrinsic_wo_chain:{ *:[v4i32] } 3087:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19245
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHADDsv4i32),
19246
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19247
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19248
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19249
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19250
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19251
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19252
0
        GIR_EraseFromParent, /*InsnID*/0,
19253
        // GIR_Coverage, 812,
19254
0
        GIR_Done,
19255
      // Label 1094: @58953
19256
0
      GIM_Try, /*On fail goto*//*Label 1095*/ GIMT_Encode4(59023), // Rule ID 813 //
19257
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19258
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds),
19259
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19260
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19261
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19262
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19263
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19264
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19265
        // (intrinsic_wo_chain:{ *:[v8i8] } 3087:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19266
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHADDsv8i8),
19267
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19268
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19269
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19270
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19271
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19272
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19273
0
        GIR_EraseFromParent, /*InsnID*/0,
19274
        // GIR_Coverage, 813,
19275
0
        GIR_Done,
19276
      // Label 1095: @59023
19277
0
      GIM_Try, /*On fail goto*//*Label 1096*/ GIMT_Encode4(59093), // Rule ID 814 //
19278
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19279
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds),
19280
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
19281
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
19282
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
19283
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19284
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19285
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19286
        // (intrinsic_wo_chain:{ *:[v16i8] } 3087:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19287
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHADDsv16i8),
19288
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19289
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19290
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19291
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19292
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19293
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19294
0
        GIR_EraseFromParent, /*InsnID*/0,
19295
        // GIR_Coverage, 814,
19296
0
        GIR_Done,
19297
      // Label 1096: @59093
19298
0
      GIM_Try, /*On fail goto*//*Label 1097*/ GIMT_Encode4(59163), // Rule ID 815 //
19299
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19300
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu),
19301
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19302
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19303
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19304
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19305
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19306
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19307
        // (intrinsic_wo_chain:{ *:[v4i16] } 3088:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19308
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHADDuv4i16),
19309
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19310
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19311
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19312
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19313
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19314
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19315
0
        GIR_EraseFromParent, /*InsnID*/0,
19316
        // GIR_Coverage, 815,
19317
0
        GIR_Done,
19318
      // Label 1097: @59163
19319
0
      GIM_Try, /*On fail goto*//*Label 1098*/ GIMT_Encode4(59233), // Rule ID 816 //
19320
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19321
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu),
19322
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19323
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19324
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19325
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19326
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19327
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19328
        // (intrinsic_wo_chain:{ *:[v2i32] } 3088:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19329
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHADDuv2i32),
19330
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19331
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19332
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19333
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19334
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19335
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19336
0
        GIR_EraseFromParent, /*InsnID*/0,
19337
        // GIR_Coverage, 816,
19338
0
        GIR_Done,
19339
      // Label 1098: @59233
19340
0
      GIM_Try, /*On fail goto*//*Label 1099*/ GIMT_Encode4(59303), // Rule ID 817 //
19341
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19342
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu),
19343
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19344
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19345
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19346
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19347
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19348
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19349
        // (intrinsic_wo_chain:{ *:[v8i16] } 3088:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19350
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHADDuv8i16),
19351
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19352
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19353
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19354
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19355
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19356
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19357
0
        GIR_EraseFromParent, /*InsnID*/0,
19358
        // GIR_Coverage, 817,
19359
0
        GIR_Done,
19360
      // Label 1099: @59303
19361
0
      GIM_Try, /*On fail goto*//*Label 1100*/ GIMT_Encode4(59373), // Rule ID 818 //
19362
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19363
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu),
19364
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19365
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19366
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19367
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19368
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19369
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19370
        // (intrinsic_wo_chain:{ *:[v4i32] } 3088:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19371
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHADDuv4i32),
19372
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19373
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19374
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19375
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19376
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19377
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19378
0
        GIR_EraseFromParent, /*InsnID*/0,
19379
        // GIR_Coverage, 818,
19380
0
        GIR_Done,
19381
      // Label 1100: @59373
19382
0
      GIM_Try, /*On fail goto*//*Label 1101*/ GIMT_Encode4(59443), // Rule ID 819 //
19383
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19384
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu),
19385
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19386
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19387
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19388
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19389
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19390
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19391
        // (intrinsic_wo_chain:{ *:[v8i8] } 3088:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19392
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHADDuv8i8),
19393
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19394
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19395
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19396
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19397
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19398
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19399
0
        GIR_EraseFromParent, /*InsnID*/0,
19400
        // GIR_Coverage, 819,
19401
0
        GIR_Done,
19402
      // Label 1101: @59443
19403
0
      GIM_Try, /*On fail goto*//*Label 1102*/ GIMT_Encode4(59513), // Rule ID 820 //
19404
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19405
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu),
19406
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
19407
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
19408
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
19409
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19410
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19411
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19412
        // (intrinsic_wo_chain:{ *:[v16i8] } 3088:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19413
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHADDuv16i8),
19414
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19415
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19416
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19417
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19418
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19419
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19420
0
        GIR_EraseFromParent, /*InsnID*/0,
19421
        // GIR_Coverage, 820,
19422
0
        GIR_Done,
19423
      // Label 1102: @59513
19424
0
      GIM_Try, /*On fail goto*//*Label 1103*/ GIMT_Encode4(59583), // Rule ID 821 //
19425
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19426
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds),
19427
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19428
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19429
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19430
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19431
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19432
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19433
        // (intrinsic_wo_chain:{ *:[v4i16] } 3147:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VRHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19434
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv4i16),
19435
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19436
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19437
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19438
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19439
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19440
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19441
0
        GIR_EraseFromParent, /*InsnID*/0,
19442
        // GIR_Coverage, 821,
19443
0
        GIR_Done,
19444
      // Label 1103: @59583
19445
0
      GIM_Try, /*On fail goto*//*Label 1104*/ GIMT_Encode4(59653), // Rule ID 822 //
19446
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19447
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds),
19448
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19449
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19450
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19451
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19452
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19453
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19454
        // (intrinsic_wo_chain:{ *:[v2i32] } 3147:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VRHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19455
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv2i32),
19456
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19457
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19458
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19459
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19460
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19461
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19462
0
        GIR_EraseFromParent, /*InsnID*/0,
19463
        // GIR_Coverage, 822,
19464
0
        GIR_Done,
19465
      // Label 1104: @59653
19466
0
      GIM_Try, /*On fail goto*//*Label 1105*/ GIMT_Encode4(59723), // Rule ID 823 //
19467
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19468
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds),
19469
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19470
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19471
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19472
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19473
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19474
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19475
        // (intrinsic_wo_chain:{ *:[v8i16] } 3147:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VRHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19476
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv8i16),
19477
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19478
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19479
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19480
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19481
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19482
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19483
0
        GIR_EraseFromParent, /*InsnID*/0,
19484
        // GIR_Coverage, 823,
19485
0
        GIR_Done,
19486
      // Label 1105: @59723
19487
0
      GIM_Try, /*On fail goto*//*Label 1106*/ GIMT_Encode4(59793), // Rule ID 824 //
19488
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19489
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds),
19490
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19491
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19492
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19493
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19494
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19495
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19496
        // (intrinsic_wo_chain:{ *:[v4i32] } 3147:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VRHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19497
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv4i32),
19498
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19499
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19500
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19501
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19502
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19503
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19504
0
        GIR_EraseFromParent, /*InsnID*/0,
19505
        // GIR_Coverage, 824,
19506
0
        GIR_Done,
19507
      // Label 1106: @59793
19508
0
      GIM_Try, /*On fail goto*//*Label 1107*/ GIMT_Encode4(59863), // Rule ID 825 //
19509
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19510
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds),
19511
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19512
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19513
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19514
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19515
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19516
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19517
        // (intrinsic_wo_chain:{ *:[v8i8] } 3147:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VRHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19518
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv8i8),
19519
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19520
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19521
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19522
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19523
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19524
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19525
0
        GIR_EraseFromParent, /*InsnID*/0,
19526
        // GIR_Coverage, 825,
19527
0
        GIR_Done,
19528
      // Label 1107: @59863
19529
0
      GIM_Try, /*On fail goto*//*Label 1108*/ GIMT_Encode4(59933), // Rule ID 826 //
19530
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19531
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds),
19532
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
19533
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
19534
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
19535
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19536
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19537
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19538
        // (intrinsic_wo_chain:{ *:[v16i8] } 3147:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VRHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19539
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv16i8),
19540
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19541
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19542
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19543
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19544
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19545
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19546
0
        GIR_EraseFromParent, /*InsnID*/0,
19547
        // GIR_Coverage, 826,
19548
0
        GIR_Done,
19549
      // Label 1108: @59933
19550
0
      GIM_Try, /*On fail goto*//*Label 1109*/ GIMT_Encode4(60003), // Rule ID 827 //
19551
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19552
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu),
19553
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19554
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19555
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19556
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19557
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19558
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19559
        // (intrinsic_wo_chain:{ *:[v4i16] } 3148:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VRHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19560
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv4i16),
19561
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19562
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19563
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19564
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19565
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19566
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19567
0
        GIR_EraseFromParent, /*InsnID*/0,
19568
        // GIR_Coverage, 827,
19569
0
        GIR_Done,
19570
      // Label 1109: @60003
19571
0
      GIM_Try, /*On fail goto*//*Label 1110*/ GIMT_Encode4(60073), // Rule ID 828 //
19572
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19573
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu),
19574
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19575
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19576
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19577
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19578
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19579
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19580
        // (intrinsic_wo_chain:{ *:[v2i32] } 3148:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VRHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19581
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv2i32),
19582
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19583
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19584
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19585
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19586
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19587
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19588
0
        GIR_EraseFromParent, /*InsnID*/0,
19589
        // GIR_Coverage, 828,
19590
0
        GIR_Done,
19591
      // Label 1110: @60073
19592
0
      GIM_Try, /*On fail goto*//*Label 1111*/ GIMT_Encode4(60143), // Rule ID 829 //
19593
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19594
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu),
19595
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19596
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19597
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19598
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19599
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19600
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19601
        // (intrinsic_wo_chain:{ *:[v8i16] } 3148:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VRHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19602
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv8i16),
19603
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19604
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19605
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19606
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19607
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19608
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19609
0
        GIR_EraseFromParent, /*InsnID*/0,
19610
        // GIR_Coverage, 829,
19611
0
        GIR_Done,
19612
      // Label 1111: @60143
19613
0
      GIM_Try, /*On fail goto*//*Label 1112*/ GIMT_Encode4(60213), // Rule ID 830 //
19614
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19615
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu),
19616
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19617
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19618
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19619
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19620
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19621
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19622
        // (intrinsic_wo_chain:{ *:[v4i32] } 3148:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VRHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19623
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv4i32),
19624
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19625
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19626
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19627
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19628
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19629
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19630
0
        GIR_EraseFromParent, /*InsnID*/0,
19631
        // GIR_Coverage, 830,
19632
0
        GIR_Done,
19633
      // Label 1112: @60213
19634
0
      GIM_Try, /*On fail goto*//*Label 1113*/ GIMT_Encode4(60283), // Rule ID 831 //
19635
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19636
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu),
19637
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19638
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19639
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19640
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19641
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19642
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19643
        // (intrinsic_wo_chain:{ *:[v8i8] } 3148:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VRHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19644
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv8i8),
19645
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19646
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19647
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19648
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19649
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19650
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19651
0
        GIR_EraseFromParent, /*InsnID*/0,
19652
        // GIR_Coverage, 831,
19653
0
        GIR_Done,
19654
      // Label 1113: @60283
19655
0
      GIM_Try, /*On fail goto*//*Label 1114*/ GIMT_Encode4(60353), // Rule ID 832 //
19656
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19657
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu),
19658
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
19659
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
19660
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
19661
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19662
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19663
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19664
        // (intrinsic_wo_chain:{ *:[v16i8] } 3148:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VRHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19665
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv16i8),
19666
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19667
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19668
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19669
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19670
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19671
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19672
0
        GIR_EraseFromParent, /*InsnID*/0,
19673
        // GIR_Coverage, 832,
19674
0
        GIR_Done,
19675
      // Label 1114: @60353
19676
0
      GIM_Try, /*On fail goto*//*Label 1115*/ GIMT_Encode4(60423), // Rule ID 849 //
19677
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19678
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vraddhn),
19679
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19680
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19681
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19682
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19683
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19684
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19685
        // (intrinsic_wo_chain:{ *:[v8i8] } 3144:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VRADDHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19686
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv8i8),
19687
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19688
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19689
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19690
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19691
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19692
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19693
0
        GIR_EraseFromParent, /*InsnID*/0,
19694
        // GIR_Coverage, 849,
19695
0
        GIR_Done,
19696
      // Label 1115: @60423
19697
0
      GIM_Try, /*On fail goto*//*Label 1116*/ GIMT_Encode4(60493), // Rule ID 850 //
19698
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19699
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vraddhn),
19700
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19701
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19702
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19703
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19704
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19705
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19706
        // (intrinsic_wo_chain:{ *:[v4i16] } 3144:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VRADDHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19707
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv4i16),
19708
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19709
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19710
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19711
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19712
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19713
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19714
0
        GIR_EraseFromParent, /*InsnID*/0,
19715
        // GIR_Coverage, 850,
19716
0
        GIR_Done,
19717
      // Label 1116: @60493
19718
0
      GIM_Try, /*On fail goto*//*Label 1117*/ GIMT_Encode4(60563), // Rule ID 851 //
19719
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19720
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vraddhn),
19721
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19722
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
19723
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
19724
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19725
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19726
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19727
        // (intrinsic_wo_chain:{ *:[v2i32] } 3144:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VRADDHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
19728
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv2i32),
19729
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19730
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19731
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19732
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19733
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19734
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19735
0
        GIR_EraseFromParent, /*InsnID*/0,
19736
        // GIR_Coverage, 851,
19737
0
        GIR_Done,
19738
      // Label 1117: @60563
19739
0
      GIM_Try, /*On fail goto*//*Label 1118*/ GIMT_Encode4(60633), // Rule ID 858 //
19740
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19741
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmulp),
19742
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19743
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19744
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19745
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19746
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19747
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19748
        // (intrinsic_wo_chain:{ *:[v8i8] } 3113:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMULpd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19749
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMULpd),
19750
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19751
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19752
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19753
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19754
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19755
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19756
0
        GIR_EraseFromParent, /*InsnID*/0,
19757
        // GIR_Coverage, 858,
19758
0
        GIR_Done,
19759
      // Label 1118: @60633
19760
0
      GIM_Try, /*On fail goto*//*Label 1119*/ GIMT_Encode4(60703), // Rule ID 859 //
19761
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19762
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmulp),
19763
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
19764
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
19765
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
19766
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19767
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19768
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19769
        // (intrinsic_wo_chain:{ *:[v16i8] } 3113:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VMULpq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19770
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMULpq),
19771
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19772
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19773
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19774
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19775
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19776
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19777
0
        GIR_EraseFromParent, /*InsnID*/0,
19778
        // GIR_Coverage, 859,
19779
0
        GIR_Done,
19780
      // Label 1119: @60703
19781
0
      GIM_Try, /*On fail goto*//*Label 1120*/ GIMT_Encode4(60773), // Rule ID 872 //
19782
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19783
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh),
19784
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19785
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19786
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19787
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19788
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19789
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19790
        // (intrinsic_wo_chain:{ *:[v4i16] } 3124:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19791
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv4i16),
19792
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19793
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19794
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19795
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19796
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19797
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19798
0
        GIR_EraseFromParent, /*InsnID*/0,
19799
        // GIR_Coverage, 872,
19800
0
        GIR_Done,
19801
      // Label 1120: @60773
19802
0
      GIM_Try, /*On fail goto*//*Label 1121*/ GIMT_Encode4(60843), // Rule ID 873 //
19803
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19804
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh),
19805
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19806
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19807
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19808
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19809
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19810
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19811
        // (intrinsic_wo_chain:{ *:[v2i32] } 3124:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19812
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv2i32),
19813
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19814
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19815
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19816
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19817
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19818
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19819
0
        GIR_EraseFromParent, /*InsnID*/0,
19820
        // GIR_Coverage, 873,
19821
0
        GIR_Done,
19822
      // Label 1121: @60843
19823
0
      GIM_Try, /*On fail goto*//*Label 1122*/ GIMT_Encode4(60913), // Rule ID 874 //
19824
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19825
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh),
19826
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19827
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19828
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19829
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19830
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19831
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19832
        // (intrinsic_wo_chain:{ *:[v8i16] } 3124:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19833
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv8i16),
19834
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19835
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19836
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19837
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19838
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19839
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19840
0
        GIR_EraseFromParent, /*InsnID*/0,
19841
        // GIR_Coverage, 874,
19842
0
        GIR_Done,
19843
      // Label 1122: @60913
19844
0
      GIM_Try, /*On fail goto*//*Label 1123*/ GIMT_Encode4(60983), // Rule ID 875 //
19845
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19846
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh),
19847
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19848
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19849
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19850
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19851
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19852
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19853
        // (intrinsic_wo_chain:{ *:[v4i32] } 3124:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19854
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv4i32),
19855
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19856
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19857
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19858
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19859
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19860
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19861
0
        GIR_EraseFromParent, /*InsnID*/0,
19862
        // GIR_Coverage, 875,
19863
0
        GIR_Done,
19864
      // Label 1123: @60983
19865
0
      GIM_Try, /*On fail goto*//*Label 1124*/ GIMT_Encode4(61053), // Rule ID 880 //
19866
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19867
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh),
19868
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19869
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19870
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19871
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19872
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19873
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19874
        // (intrinsic_wo_chain:{ *:[v4i16] } 3132:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQRDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19875
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv4i16),
19876
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19877
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19878
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19879
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19880
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19881
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19882
0
        GIR_EraseFromParent, /*InsnID*/0,
19883
        // GIR_Coverage, 880,
19884
0
        GIR_Done,
19885
      // Label 1124: @61053
19886
0
      GIM_Try, /*On fail goto*//*Label 1125*/ GIMT_Encode4(61123), // Rule ID 881 //
19887
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19888
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh),
19889
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19890
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19891
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19892
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19893
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19894
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19895
        // (intrinsic_wo_chain:{ *:[v2i32] } 3132:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQRDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19896
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv2i32),
19897
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19898
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19899
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19900
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19901
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19902
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19903
0
        GIR_EraseFromParent, /*InsnID*/0,
19904
        // GIR_Coverage, 881,
19905
0
        GIR_Done,
19906
      // Label 1125: @61123
19907
0
      GIM_Try, /*On fail goto*//*Label 1126*/ GIMT_Encode4(61193), // Rule ID 882 //
19908
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19909
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh),
19910
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19911
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19912
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19913
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19914
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19915
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19916
        // (intrinsic_wo_chain:{ *:[v8i16] } 3132:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQRDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19917
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv8i16),
19918
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19919
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19920
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19921
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19922
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19923
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19924
0
        GIR_EraseFromParent, /*InsnID*/0,
19925
        // GIR_Coverage, 882,
19926
0
        GIR_Done,
19927
      // Label 1126: @61193
19928
0
      GIM_Try, /*On fail goto*//*Label 1127*/ GIMT_Encode4(61263), // Rule ID 883 //
19929
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19930
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh),
19931
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19932
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19933
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19934
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19935
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19936
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19937
        // (intrinsic_wo_chain:{ *:[v4i32] } 3132:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQRDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19938
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv4i32),
19939
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19940
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19941
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19942
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19943
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19944
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19945
0
        GIR_EraseFromParent, /*InsnID*/0,
19946
        // GIR_Coverage, 883,
19947
0
        GIR_Done,
19948
      // Label 1127: @61263
19949
0
      GIM_Try, /*On fail goto*//*Label 1128*/ GIMT_Encode4(61333), // Rule ID 894 //
19950
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19951
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmullp),
19952
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19953
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19954
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19955
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19956
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19957
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19958
        // (intrinsic_wo_chain:{ *:[v8i16] } 3110:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMULLp8:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19959
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMULLp8),
19960
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19961
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19962
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19963
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19964
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19965
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19966
0
        GIR_EraseFromParent, /*InsnID*/0,
19967
        // GIR_Coverage, 894,
19968
0
        GIR_Done,
19969
      // Label 1128: @61333
19970
0
      GIM_Try, /*On fail goto*//*Label 1129*/ GIMT_Encode4(61394), // Rule ID 895 //
19971
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8),
19972
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmullp),
19973
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
19974
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19975
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19976
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19977
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19978
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19979
        // (intrinsic_wo_chain:{ *:[v2i64] } 3110:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VMULLp64:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
19980
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMULLp64),
19981
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
19982
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19983
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19984
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19985
0
        GIR_EraseFromParent, /*InsnID*/0,
19986
        // GIR_Coverage, 895,
19987
0
        GIR_Done,
19988
      // Label 1129: @61394
19989
0
      GIM_Try, /*On fail goto*//*Label 1130*/ GIMT_Encode4(61464), // Rule ID 900 //
19990
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19991
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
19992
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19993
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19994
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19995
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19996
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19997
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19998
        // (intrinsic_wo_chain:{ *:[v4i32] } 3125:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQDMULLv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19999
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQDMULLv4i32),
20000
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20001
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20002
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20003
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20004
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20005
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20006
0
        GIR_EraseFromParent, /*InsnID*/0,
20007
        // GIR_Coverage, 900,
20008
0
        GIR_Done,
20009
      // Label 1130: @61464
20010
0
      GIM_Try, /*On fail goto*//*Label 1131*/ GIMT_Encode4(61534), // Rule ID 901 //
20011
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20012
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
20013
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
20014
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20015
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20016
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20017
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20018
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20019
        // (intrinsic_wo_chain:{ *:[v2i64] } 3125:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQDMULLv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20020
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQDMULLv2i64),
20021
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20022
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20023
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20024
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20025
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20026
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20027
0
        GIR_EraseFromParent, /*InsnID*/0,
20028
        // GIR_Coverage, 901,
20029
0
        GIR_Done,
20030
      // Label 1131: @61534
20031
0
      GIM_Try, /*On fail goto*//*Label 1132*/ GIMT_Encode4(61604), // Rule ID 1013 //
20032
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20033
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs),
20034
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20035
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20036
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20037
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20038
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20039
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20040
        // (intrinsic_wo_chain:{ *:[v4i16] } 3089:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VHSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20041
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv4i16),
20042
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20043
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20044
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20045
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20046
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20047
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20048
0
        GIR_EraseFromParent, /*InsnID*/0,
20049
        // GIR_Coverage, 1013,
20050
0
        GIR_Done,
20051
      // Label 1132: @61604
20052
0
      GIM_Try, /*On fail goto*//*Label 1133*/ GIMT_Encode4(61674), // Rule ID 1014 //
20053
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20054
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs),
20055
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20056
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20057
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20058
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20059
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20060
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20061
        // (intrinsic_wo_chain:{ *:[v2i32] } 3089:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VHSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20062
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv2i32),
20063
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20064
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20065
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20066
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20067
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20068
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20069
0
        GIR_EraseFromParent, /*InsnID*/0,
20070
        // GIR_Coverage, 1014,
20071
0
        GIR_Done,
20072
      // Label 1133: @61674
20073
0
      GIM_Try, /*On fail goto*//*Label 1134*/ GIMT_Encode4(61744), // Rule ID 1015 //
20074
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20075
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs),
20076
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
20077
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
20078
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20079
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20080
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20081
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20082
        // (intrinsic_wo_chain:{ *:[v8i16] } 3089:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VHSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20083
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv8i16),
20084
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20085
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20086
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20087
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20088
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20089
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20090
0
        GIR_EraseFromParent, /*InsnID*/0,
20091
        // GIR_Coverage, 1015,
20092
0
        GIR_Done,
20093
      // Label 1134: @61744
20094
0
      GIM_Try, /*On fail goto*//*Label 1135*/ GIMT_Encode4(61814), // Rule ID 1016 //
20095
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20096
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs),
20097
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20098
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20099
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20100
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20101
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20102
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20103
        // (intrinsic_wo_chain:{ *:[v4i32] } 3089:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VHSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20104
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv4i32),
20105
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20106
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20107
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20108
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20109
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20110
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20111
0
        GIR_EraseFromParent, /*InsnID*/0,
20112
        // GIR_Coverage, 1016,
20113
0
        GIR_Done,
20114
      // Label 1135: @61814
20115
0
      GIM_Try, /*On fail goto*//*Label 1136*/ GIMT_Encode4(61884), // Rule ID 1017 //
20116
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20117
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs),
20118
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
20119
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
20120
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
20121
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20122
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20123
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20124
        // (intrinsic_wo_chain:{ *:[v8i8] } 3089:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VHSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20125
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv8i8),
20126
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20127
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20128
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20129
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20130
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20131
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20132
0
        GIR_EraseFromParent, /*InsnID*/0,
20133
        // GIR_Coverage, 1017,
20134
0
        GIR_Done,
20135
      // Label 1136: @61884
20136
0
      GIM_Try, /*On fail goto*//*Label 1137*/ GIMT_Encode4(61954), // Rule ID 1018 //
20137
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20138
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs),
20139
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
20140
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
20141
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
20142
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20143
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20144
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20145
        // (intrinsic_wo_chain:{ *:[v16i8] } 3089:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VHSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
20146
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv16i8),
20147
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20148
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20149
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20150
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20151
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20152
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20153
0
        GIR_EraseFromParent, /*InsnID*/0,
20154
        // GIR_Coverage, 1018,
20155
0
        GIR_Done,
20156
      // Label 1137: @61954
20157
0
      GIM_Try, /*On fail goto*//*Label 1138*/ GIMT_Encode4(62024), // Rule ID 1019 //
20158
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20159
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu),
20160
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20161
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20162
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20163
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20164
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20165
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20166
        // (intrinsic_wo_chain:{ *:[v4i16] } 3090:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VHSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20167
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv4i16),
20168
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20169
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20170
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20171
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20172
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20173
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20174
0
        GIR_EraseFromParent, /*InsnID*/0,
20175
        // GIR_Coverage, 1019,
20176
0
        GIR_Done,
20177
      // Label 1138: @62024
20178
0
      GIM_Try, /*On fail goto*//*Label 1139*/ GIMT_Encode4(62094), // Rule ID 1020 //
20179
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20180
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu),
20181
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20182
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20183
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20184
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20185
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20186
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20187
        // (intrinsic_wo_chain:{ *:[v2i32] } 3090:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VHSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20188
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv2i32),
20189
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20190
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20191
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20192
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20193
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20194
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20195
0
        GIR_EraseFromParent, /*InsnID*/0,
20196
        // GIR_Coverage, 1020,
20197
0
        GIR_Done,
20198
      // Label 1139: @62094
20199
0
      GIM_Try, /*On fail goto*//*Label 1140*/ GIMT_Encode4(62164), // Rule ID 1021 //
20200
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20201
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu),
20202
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
20203
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
20204
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20205
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20206
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20207
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20208
        // (intrinsic_wo_chain:{ *:[v8i16] } 3090:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VHSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20209
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv8i16),
20210
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20211
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20212
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20213
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20214
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20215
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20216
0
        GIR_EraseFromParent, /*InsnID*/0,
20217
        // GIR_Coverage, 1021,
20218
0
        GIR_Done,
20219
      // Label 1140: @62164
20220
0
      GIM_Try, /*On fail goto*//*Label 1141*/ GIMT_Encode4(62234), // Rule ID 1022 //
20221
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20222
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu),
20223
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20224
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20225
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20226
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20227
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20228
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20229
        // (intrinsic_wo_chain:{ *:[v4i32] } 3090:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VHSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20230
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv4i32),
20231
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20232
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20233
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20234
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20235
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20236
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20237
0
        GIR_EraseFromParent, /*InsnID*/0,
20238
        // GIR_Coverage, 1022,
20239
0
        GIR_Done,
20240
      // Label 1141: @62234
20241
0
      GIM_Try, /*On fail goto*//*Label 1142*/ GIMT_Encode4(62304), // Rule ID 1023 //
20242
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20243
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu),
20244
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
20245
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
20246
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
20247
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20248
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20249
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20250
        // (intrinsic_wo_chain:{ *:[v8i8] } 3090:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VHSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20251
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv8i8),
20252
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20253
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20254
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20255
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20256
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20257
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20258
0
        GIR_EraseFromParent, /*InsnID*/0,
20259
        // GIR_Coverage, 1023,
20260
0
        GIR_Done,
20261
      // Label 1142: @62304
20262
0
      GIM_Try, /*On fail goto*//*Label 1143*/ GIMT_Encode4(62374), // Rule ID 1024 //
20263
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20264
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu),
20265
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
20266
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
20267
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
20268
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20269
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20270
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20271
        // (intrinsic_wo_chain:{ *:[v16i8] } 3090:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VHSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
20272
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv16i8),
20273
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20274
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20275
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20276
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20277
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20278
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20279
0
        GIR_EraseFromParent, /*InsnID*/0,
20280
        // GIR_Coverage, 1024,
20281
0
        GIR_Done,
20282
      // Label 1143: @62374
20283
0
      GIM_Try, /*On fail goto*//*Label 1144*/ GIMT_Encode4(62444), // Rule ID 1041 //
20284
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20285
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsubhn),
20286
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
20287
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
20288
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20289
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20290
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20291
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20292
        // (intrinsic_wo_chain:{ *:[v8i8] } 3160:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VRSUBHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20293
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv8i8),
20294
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20295
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20296
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20297
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20298
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20299
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20300
0
        GIR_EraseFromParent, /*InsnID*/0,
20301
        // GIR_Coverage, 1041,
20302
0
        GIR_Done,
20303
      // Label 1144: @62444
20304
0
      GIM_Try, /*On fail goto*//*Label 1145*/ GIMT_Encode4(62514), // Rule ID 1042 //
20305
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20306
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsubhn),
20307
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20308
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20309
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20310
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20311
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20312
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20313
        // (intrinsic_wo_chain:{ *:[v4i16] } 3160:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VRSUBHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20314
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv4i16),
20315
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20316
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20317
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20318
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20319
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20320
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20321
0
        GIR_EraseFromParent, /*InsnID*/0,
20322
        // GIR_Coverage, 1042,
20323
0
        GIR_Done,
20324
      // Label 1145: @62514
20325
0
      GIM_Try, /*On fail goto*//*Label 1146*/ GIMT_Encode4(62584), // Rule ID 1043 //
20326
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20327
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsubhn),
20328
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20329
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
20330
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
20331
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20332
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20333
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20334
        // (intrinsic_wo_chain:{ *:[v2i32] } 3160:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VRSUBHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
20335
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv2i32),
20336
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20337
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20338
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20339
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20340
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20341
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20342
0
        GIR_EraseFromParent, /*InsnID*/0,
20343
        // GIR_Coverage, 1043,
20344
0
        GIR_Done,
20345
      // Label 1146: @62584
20346
0
      GIM_Try, /*On fail goto*//*Label 1147*/ GIMT_Encode4(62654), // Rule ID 1136 //
20347
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20348
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge),
20349
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20350
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20351
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20352
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20353
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20354
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20355
        // (intrinsic_wo_chain:{ *:[v2i32] } 3065:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VACGEfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
20356
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VACGEfd),
20357
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20358
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20359
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20360
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20361
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20362
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20363
0
        GIR_EraseFromParent, /*InsnID*/0,
20364
        // GIR_Coverage, 1136,
20365
0
        GIR_Done,
20366
      // Label 1147: @62654
20367
0
      GIM_Try, /*On fail goto*//*Label 1148*/ GIMT_Encode4(62724), // Rule ID 1137 //
20368
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20369
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge),
20370
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20371
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20372
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20373
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20374
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20375
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20376
        // (intrinsic_wo_chain:{ *:[v4i32] } 3065:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VACGEfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
20377
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VACGEfq),
20378
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20379
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20380
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20381
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20382
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20383
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20384
0
        GIR_EraseFromParent, /*InsnID*/0,
20385
        // GIR_Coverage, 1137,
20386
0
        GIR_Done,
20387
      // Label 1148: @62724
20388
0
      GIM_Try, /*On fail goto*//*Label 1149*/ GIMT_Encode4(62794), // Rule ID 1138 //
20389
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
20390
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge),
20391
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20392
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20393
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20394
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20395
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20396
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20397
        // (intrinsic_wo_chain:{ *:[v4i16] } 3065:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VACGEhd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
20398
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VACGEhd),
20399
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20400
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20401
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20402
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20403
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20404
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20405
0
        GIR_EraseFromParent, /*InsnID*/0,
20406
        // GIR_Coverage, 1138,
20407
0
        GIR_Done,
20408
      // Label 1149: @62794
20409
0
      GIM_Try, /*On fail goto*//*Label 1150*/ GIMT_Encode4(62864), // Rule ID 1139 //
20410
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
20411
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge),
20412
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
20413
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
20414
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20415
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20416
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20417
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20418
        // (intrinsic_wo_chain:{ *:[v8i16] } 3065:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VACGEhq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
20419
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VACGEhq),
20420
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20421
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20422
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20423
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20424
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20425
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20426
0
        GIR_EraseFromParent, /*InsnID*/0,
20427
        // GIR_Coverage, 1139,
20428
0
        GIR_Done,
20429
      // Label 1150: @62864
20430
0
      GIM_Try, /*On fail goto*//*Label 1151*/ GIMT_Encode4(62934), // Rule ID 1140 //
20431
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20432
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt),
20433
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20434
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20435
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20436
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20437
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20438
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20439
        // (intrinsic_wo_chain:{ *:[v2i32] } 3066:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VACGTfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
20440
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VACGTfd),
20441
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20442
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20443
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20444
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20445
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20446
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20447
0
        GIR_EraseFromParent, /*InsnID*/0,
20448
        // GIR_Coverage, 1140,
20449
0
        GIR_Done,
20450
      // Label 1151: @62934
20451
0
      GIM_Try, /*On fail goto*//*Label 1152*/ GIMT_Encode4(63004), // Rule ID 1141 //
20452
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20453
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt),
20454
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20455
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20456
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20457
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20458
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20459
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20460
        // (intrinsic_wo_chain:{ *:[v4i32] } 3066:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VACGTfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
20461
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VACGTfq),
20462
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20463
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20464
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20465
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20466
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20467
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20468
0
        GIR_EraseFromParent, /*InsnID*/0,
20469
        // GIR_Coverage, 1141,
20470
0
        GIR_Done,
20471
      // Label 1152: @63004
20472
0
      GIM_Try, /*On fail goto*//*Label 1153*/ GIMT_Encode4(63074), // Rule ID 1142 //
20473
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
20474
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt),
20475
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20476
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20477
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20478
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20479
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20480
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20481
        // (intrinsic_wo_chain:{ *:[v4i16] } 3066:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VACGThd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
20482
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VACGThd),
20483
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20484
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20485
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20486
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20487
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20488
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20489
0
        GIR_EraseFromParent, /*InsnID*/0,
20490
        // GIR_Coverage, 1142,
20491
0
        GIR_Done,
20492
      // Label 1153: @63074
20493
0
      GIM_Try, /*On fail goto*//*Label 1154*/ GIMT_Encode4(63144), // Rule ID 1143 //
20494
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
20495
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt),
20496
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
20497
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
20498
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20499
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20500
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20501
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20502
        // (intrinsic_wo_chain:{ *:[v8i16] } 3066:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VACGThq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
20503
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VACGThq),
20504
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20505
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20506
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20507
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20508
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20509
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20510
0
        GIR_EraseFromParent, /*InsnID*/0,
20511
        // GIR_Coverage, 1143,
20512
0
        GIR_Done,
20513
      // Label 1154: @63144
20514
0
      GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(63214), // Rule ID 1176 //
20515
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20516
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
20517
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20518
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20519
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20520
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20521
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20522
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20523
        // (intrinsic_wo_chain:{ *:[v4i16] } 3062:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VABDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20524
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDsv4i16),
20525
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20526
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20527
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20528
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20529
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20530
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20531
0
        GIR_EraseFromParent, /*InsnID*/0,
20532
        // GIR_Coverage, 1176,
20533
0
        GIR_Done,
20534
      // Label 1155: @63214
20535
0
      GIM_Try, /*On fail goto*//*Label 1156*/ GIMT_Encode4(63284), // Rule ID 1177 //
20536
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20537
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
20538
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20539
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20540
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20541
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20542
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20543
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20544
        // (intrinsic_wo_chain:{ *:[v2i32] } 3062:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VABDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20545
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDsv2i32),
20546
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20547
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20548
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20549
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20550
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20551
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20552
0
        GIR_EraseFromParent, /*InsnID*/0,
20553
        // GIR_Coverage, 1177,
20554
0
        GIR_Done,
20555
      // Label 1156: @63284
20556
0
      GIM_Try, /*On fail goto*//*Label 1157*/ GIMT_Encode4(63354), // Rule ID 1178 //
20557
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20558
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
20559
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
20560
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
20561
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20562
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20563
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20564
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20565
        // (intrinsic_wo_chain:{ *:[v8i16] } 3062:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VABDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20566
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDsv8i16),
20567
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20568
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20569
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20570
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20571
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20572
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20573
0
        GIR_EraseFromParent, /*InsnID*/0,
20574
        // GIR_Coverage, 1178,
20575
0
        GIR_Done,
20576
      // Label 1157: @63354
20577
0
      GIM_Try, /*On fail goto*//*Label 1158*/ GIMT_Encode4(63424), // Rule ID 1179 //
20578
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20579
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
20580
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20581
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20582
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20583
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20584
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20585
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20586
        // (intrinsic_wo_chain:{ *:[v4i32] } 3062:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VABDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20587
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDsv4i32),
20588
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20589
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20590
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20591
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20592
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20593
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20594
0
        GIR_EraseFromParent, /*InsnID*/0,
20595
        // GIR_Coverage, 1179,
20596
0
        GIR_Done,
20597
      // Label 1158: @63424
20598
0
      GIM_Try, /*On fail goto*//*Label 1159*/ GIMT_Encode4(63494), // Rule ID 1180 //
20599
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20600
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
20601
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
20602
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
20603
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
20604
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20605
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20606
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20607
        // (intrinsic_wo_chain:{ *:[v8i8] } 3062:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VABDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20608
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDsv8i8),
20609
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20610
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20611
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20612
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20613
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20614
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20615
0
        GIR_EraseFromParent, /*InsnID*/0,
20616
        // GIR_Coverage, 1180,
20617
0
        GIR_Done,
20618
      // Label 1159: @63494
20619
0
      GIM_Try, /*On fail goto*//*Label 1160*/ GIMT_Encode4(63564), // Rule ID 1181 //
20620
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20621
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
20622
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
20623
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
20624
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
20625
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20626
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20627
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20628
        // (intrinsic_wo_chain:{ *:[v16i8] } 3062:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VABDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
20629
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDsv16i8),
20630
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20631
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20632
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20633
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20634
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20635
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20636
0
        GIR_EraseFromParent, /*InsnID*/0,
20637
        // GIR_Coverage, 1181,
20638
0
        GIR_Done,
20639
      // Label 1160: @63564
20640
0
      GIM_Try, /*On fail goto*//*Label 1161*/ GIMT_Encode4(63634), // Rule ID 1182 //
20641
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20642
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
20643
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20644
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20645
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20646
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20647
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20648
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20649
        // (intrinsic_wo_chain:{ *:[v4i16] } 3063:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VABDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20650
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDuv4i16),
20651
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20652
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20653
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20654
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20655
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20656
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20657
0
        GIR_EraseFromParent, /*InsnID*/0,
20658
        // GIR_Coverage, 1182,
20659
0
        GIR_Done,
20660
      // Label 1161: @63634
20661
0
      GIM_Try, /*On fail goto*//*Label 1162*/ GIMT_Encode4(63704), // Rule ID 1183 //
20662
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20663
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
20664
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20665
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20666
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20667
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20668
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20669
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20670
        // (intrinsic_wo_chain:{ *:[v2i32] } 3063:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VABDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20671
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDuv2i32),
20672
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20673
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20674
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20675
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20676
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20677
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20678
0
        GIR_EraseFromParent, /*InsnID*/0,
20679
        // GIR_Coverage, 1183,
20680
0
        GIR_Done,
20681
      // Label 1162: @63704
20682
0
      GIM_Try, /*On fail goto*//*Label 1163*/ GIMT_Encode4(63774), // Rule ID 1184 //
20683
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20684
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
20685
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
20686
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
20687
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20688
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20689
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20690
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20691
        // (intrinsic_wo_chain:{ *:[v8i16] } 3063:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VABDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20692
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDuv8i16),
20693
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20694
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20695
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20696
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20697
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20698
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20699
0
        GIR_EraseFromParent, /*InsnID*/0,
20700
        // GIR_Coverage, 1184,
20701
0
        GIR_Done,
20702
      // Label 1163: @63774
20703
0
      GIM_Try, /*On fail goto*//*Label 1164*/ GIMT_Encode4(63844), // Rule ID 1185 //
20704
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20705
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
20706
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20707
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20708
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20709
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20710
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20711
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20712
        // (intrinsic_wo_chain:{ *:[v4i32] } 3063:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VABDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20713
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDuv4i32),
20714
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20715
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20716
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20717
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20718
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20719
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20720
0
        GIR_EraseFromParent, /*InsnID*/0,
20721
        // GIR_Coverage, 1185,
20722
0
        GIR_Done,
20723
      // Label 1164: @63844
20724
0
      GIM_Try, /*On fail goto*//*Label 1165*/ GIMT_Encode4(63914), // Rule ID 1186 //
20725
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20726
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
20727
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
20728
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
20729
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
20730
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20731
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20732
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20733
        // (intrinsic_wo_chain:{ *:[v8i8] } 3063:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VABDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20734
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDuv8i8),
20735
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20736
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20737
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20738
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20739
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20740
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20741
0
        GIR_EraseFromParent, /*InsnID*/0,
20742
        // GIR_Coverage, 1186,
20743
0
        GIR_Done,
20744
      // Label 1165: @63914
20745
0
      GIM_Try, /*On fail goto*//*Label 1166*/ GIMT_Encode4(63984), // Rule ID 1187 //
20746
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20747
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
20748
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
20749
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
20750
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
20751
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20752
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20753
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20754
        // (intrinsic_wo_chain:{ *:[v16i8] } 3063:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VABDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
20755
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDuv16i8),
20756
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20757
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20758
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20759
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20760
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20761
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20762
0
        GIR_EraseFromParent, /*InsnID*/0,
20763
        // GIR_Coverage, 1187,
20764
0
        GIR_Done,
20765
      // Label 1166: @63984
20766
0
      GIM_Try, /*On fail goto*//*Label 1167*/ GIMT_Encode4(64054), // Rule ID 1188 //
20767
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20768
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
20769
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20770
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20771
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20772
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20773
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20774
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20775
        // (intrinsic_wo_chain:{ *:[v2f32] } 3062:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VABDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
20776
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDfd),
20777
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20778
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20779
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20780
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20781
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20782
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20783
0
        GIR_EraseFromParent, /*InsnID*/0,
20784
        // GIR_Coverage, 1188,
20785
0
        GIR_Done,
20786
      // Label 1167: @64054
20787
0
      GIM_Try, /*On fail goto*//*Label 1168*/ GIMT_Encode4(64124), // Rule ID 1189 //
20788
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20789
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
20790
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20791
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20792
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20793
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20794
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20795
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20796
        // (intrinsic_wo_chain:{ *:[v4f32] } 3062:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VABDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
20797
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDfq),
20798
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20799
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20800
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20801
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20802
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20803
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20804
0
        GIR_EraseFromParent, /*InsnID*/0,
20805
        // GIR_Coverage, 1189,
20806
0
        GIR_Done,
20807
      // Label 1168: @64124
20808
0
      GIM_Try, /*On fail goto*//*Label 1169*/ GIMT_Encode4(64194), // Rule ID 1190 //
20809
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
20810
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
20811
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20812
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20813
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20814
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20815
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20816
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20817
        // (intrinsic_wo_chain:{ *:[v4f16] } 3062:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VABDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
20818
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDhd),
20819
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20820
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20821
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20822
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20823
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20824
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20825
0
        GIR_EraseFromParent, /*InsnID*/0,
20826
        // GIR_Coverage, 1190,
20827
0
        GIR_Done,
20828
      // Label 1169: @64194
20829
0
      GIM_Try, /*On fail goto*//*Label 1170*/ GIMT_Encode4(64264), // Rule ID 1191 //
20830
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
20831
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
20832
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
20833
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
20834
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20835
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20836
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20837
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20838
        // (intrinsic_wo_chain:{ *:[v8f16] } 3062:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VABDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
20839
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDhq),
20840
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20841
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20842
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20843
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20844
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20845
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20846
0
        GIR_EraseFromParent, /*InsnID*/0,
20847
        // GIR_Coverage, 1191,
20848
0
        GIR_Done,
20849
      // Label 1170: @64264
20850
0
      GIM_Try, /*On fail goto*//*Label 1171*/ GIMT_Encode4(64334), // Rule ID 1256 //
20851
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20852
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd),
20853
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
20854
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
20855
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
20856
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20857
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20858
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20859
        // (intrinsic_wo_chain:{ *:[v8i8] } 3116:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VPADDi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20860
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADDi8),
20861
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20862
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20863
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20864
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20865
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20866
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20867
0
        GIR_EraseFromParent, /*InsnID*/0,
20868
        // GIR_Coverage, 1256,
20869
0
        GIR_Done,
20870
      // Label 1171: @64334
20871
0
      GIM_Try, /*On fail goto*//*Label 1172*/ GIMT_Encode4(64404), // Rule ID 1257 //
20872
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20873
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd),
20874
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20875
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20876
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20877
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20878
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20879
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20880
        // (intrinsic_wo_chain:{ *:[v4i16] } 3116:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VPADDi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20881
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADDi16),
20882
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20883
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20884
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20885
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20886
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20887
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20888
0
        GIR_EraseFromParent, /*InsnID*/0,
20889
        // GIR_Coverage, 1257,
20890
0
        GIR_Done,
20891
      // Label 1172: @64404
20892
0
      GIM_Try, /*On fail goto*//*Label 1173*/ GIMT_Encode4(64474), // Rule ID 1258 //
20893
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20894
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd),
20895
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20896
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20897
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20898
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20899
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20900
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20901
        // (intrinsic_wo_chain:{ *:[v2i32] } 3116:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VPADDi32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20902
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADDi32),
20903
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20904
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20905
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20906
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20907
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20908
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20909
0
        GIR_EraseFromParent, /*InsnID*/0,
20910
        // GIR_Coverage, 1258,
20911
0
        GIR_Done,
20912
      // Label 1173: @64474
20913
0
      GIM_Try, /*On fail goto*//*Label 1174*/ GIMT_Encode4(64544), // Rule ID 1259 //
20914
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20915
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd),
20916
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20917
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20918
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20919
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20920
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20921
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20922
        // (intrinsic_wo_chain:{ *:[v2f32] } 3116:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VPADDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
20923
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADDf),
20924
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20925
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20926
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20927
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20928
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20929
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20930
0
        GIR_EraseFromParent, /*InsnID*/0,
20931
        // GIR_Coverage, 1259,
20932
0
        GIR_Done,
20933
      // Label 1174: @64544
20934
0
      GIM_Try, /*On fail goto*//*Label 1175*/ GIMT_Encode4(64614), // Rule ID 1260 //
20935
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
20936
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd),
20937
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20938
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20939
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20940
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20941
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20942
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20943
        // (intrinsic_wo_chain:{ *:[v4f16] } 3116:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VPADDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
20944
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADDh),
20945
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20946
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20947
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20948
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20949
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20950
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20951
0
        GIR_EraseFromParent, /*InsnID*/0,
20952
        // GIR_Coverage, 1260,
20953
0
        GIR_Done,
20954
      // Label 1175: @64614
20955
0
      GIM_Try, /*On fail goto*//*Label 1176*/ GIMT_Encode4(64684), // Rule ID 1273 //
20956
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20957
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals),
20958
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20959
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20960
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
20961
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20962
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20963
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20964
        // (intrinsic_wo_chain:{ *:[v4i16] } 3114:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)  =>  (VPADALsv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)
20965
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADALsv8i8),
20966
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20967
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
20968
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20969
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20970
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20971
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20972
0
        GIR_EraseFromParent, /*InsnID*/0,
20973
        // GIR_Coverage, 1273,
20974
0
        GIR_Done,
20975
      // Label 1176: @64684
20976
0
      GIM_Try, /*On fail goto*//*Label 1177*/ GIMT_Encode4(64754), // Rule ID 1274 //
20977
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20978
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals),
20979
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20980
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20981
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20982
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20983
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20984
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20985
        // (intrinsic_wo_chain:{ *:[v2i32] } 3114:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)  =>  (VPADALsv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)
20986
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADALsv4i16),
20987
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
20988
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
20989
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20990
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20991
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20992
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20993
0
        GIR_EraseFromParent, /*InsnID*/0,
20994
        // GIR_Coverage, 1274,
20995
0
        GIR_Done,
20996
      // Label 1177: @64754
20997
0
      GIM_Try, /*On fail goto*//*Label 1178*/ GIMT_Encode4(64824), // Rule ID 1275 //
20998
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20999
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals),
21000
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
21001
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21002
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21003
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21004
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21005
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21006
        // (intrinsic_wo_chain:{ *:[v1i64] } 3114:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)  =>  (VPADALsv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)
21007
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADALsv2i32),
21008
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21009
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21010
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21011
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21012
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21013
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21014
0
        GIR_EraseFromParent, /*InsnID*/0,
21015
        // GIR_Coverage, 1275,
21016
0
        GIR_Done,
21017
      // Label 1178: @64824
21018
0
      GIM_Try, /*On fail goto*//*Label 1179*/ GIMT_Encode4(64894), // Rule ID 1276 //
21019
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21020
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals),
21021
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21022
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21023
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
21024
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21025
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21026
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21027
        // (intrinsic_wo_chain:{ *:[v8i16] } 3114:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)  =>  (VPADALsv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)
21028
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADALsv16i8),
21029
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21030
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21031
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21032
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21033
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21034
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21035
0
        GIR_EraseFromParent, /*InsnID*/0,
21036
        // GIR_Coverage, 1276,
21037
0
        GIR_Done,
21038
      // Label 1179: @64894
21039
0
      GIM_Try, /*On fail goto*//*Label 1180*/ GIMT_Encode4(64964), // Rule ID 1277 //
21040
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21041
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals),
21042
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21043
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21044
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21045
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21046
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21047
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21048
        // (intrinsic_wo_chain:{ *:[v4i32] } 3114:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)  =>  (VPADALsv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)
21049
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADALsv8i16),
21050
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21051
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21052
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21053
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21054
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21055
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21056
0
        GIR_EraseFromParent, /*InsnID*/0,
21057
        // GIR_Coverage, 1277,
21058
0
        GIR_Done,
21059
      // Label 1180: @64964
21060
0
      GIM_Try, /*On fail goto*//*Label 1181*/ GIMT_Encode4(65034), // Rule ID 1278 //
21061
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21062
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals),
21063
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
21064
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
21065
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21066
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21067
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21068
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21069
        // (intrinsic_wo_chain:{ *:[v2i64] } 3114:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)  =>  (VPADALsv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)
21070
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADALsv4i32),
21071
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21072
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21073
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21074
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21075
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21076
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21077
0
        GIR_EraseFromParent, /*InsnID*/0,
21078
        // GIR_Coverage, 1278,
21079
0
        GIR_Done,
21080
      // Label 1181: @65034
21081
0
      GIM_Try, /*On fail goto*//*Label 1182*/ GIMT_Encode4(65104), // Rule ID 1279 //
21082
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21083
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu),
21084
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21085
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21086
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
21087
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21088
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21089
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21090
        // (intrinsic_wo_chain:{ *:[v4i16] } 3115:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)  =>  (VPADALuv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)
21091
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADALuv8i8),
21092
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21093
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21094
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21095
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21096
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21097
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21098
0
        GIR_EraseFromParent, /*InsnID*/0,
21099
        // GIR_Coverage, 1279,
21100
0
        GIR_Done,
21101
      // Label 1182: @65104
21102
0
      GIM_Try, /*On fail goto*//*Label 1183*/ GIMT_Encode4(65174), // Rule ID 1280 //
21103
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21104
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu),
21105
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21106
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21107
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21108
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21109
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21110
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21111
        // (intrinsic_wo_chain:{ *:[v2i32] } 3115:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)  =>  (VPADALuv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)
21112
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADALuv4i16),
21113
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21114
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21115
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21116
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21117
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21118
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21119
0
        GIR_EraseFromParent, /*InsnID*/0,
21120
        // GIR_Coverage, 1280,
21121
0
        GIR_Done,
21122
      // Label 1183: @65174
21123
0
      GIM_Try, /*On fail goto*//*Label 1184*/ GIMT_Encode4(65244), // Rule ID 1281 //
21124
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21125
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu),
21126
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
21127
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21128
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21129
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21130
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21131
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21132
        // (intrinsic_wo_chain:{ *:[v1i64] } 3115:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)  =>  (VPADALuv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)
21133
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADALuv2i32),
21134
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21135
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21136
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21137
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21138
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21139
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21140
0
        GIR_EraseFromParent, /*InsnID*/0,
21141
        // GIR_Coverage, 1281,
21142
0
        GIR_Done,
21143
      // Label 1184: @65244
21144
0
      GIM_Try, /*On fail goto*//*Label 1185*/ GIMT_Encode4(65314), // Rule ID 1282 //
21145
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21146
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu),
21147
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21148
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21149
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
21150
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21151
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21152
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21153
        // (intrinsic_wo_chain:{ *:[v8i16] } 3115:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)  =>  (VPADALuv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)
21154
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADALuv16i8),
21155
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21156
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21157
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21158
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21159
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21160
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21161
0
        GIR_EraseFromParent, /*InsnID*/0,
21162
        // GIR_Coverage, 1282,
21163
0
        GIR_Done,
21164
      // Label 1185: @65314
21165
0
      GIM_Try, /*On fail goto*//*Label 1186*/ GIMT_Encode4(65384), // Rule ID 1283 //
21166
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21167
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu),
21168
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21169
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21170
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21171
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21172
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21173
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21174
        // (intrinsic_wo_chain:{ *:[v4i32] } 3115:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)  =>  (VPADALuv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)
21175
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADALuv8i16),
21176
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21177
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21178
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21179
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21180
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21181
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21182
0
        GIR_EraseFromParent, /*InsnID*/0,
21183
        // GIR_Coverage, 1283,
21184
0
        GIR_Done,
21185
      // Label 1186: @65384
21186
0
      GIM_Try, /*On fail goto*//*Label 1187*/ GIMT_Encode4(65454), // Rule ID 1284 //
21187
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21188
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu),
21189
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
21190
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
21191
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21192
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21193
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21194
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21195
        // (intrinsic_wo_chain:{ *:[v2i64] } 3115:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)  =>  (VPADALuv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)
21196
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPADALuv4i32),
21197
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21198
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21199
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21200
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21201
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21202
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21203
0
        GIR_EraseFromParent, /*InsnID*/0,
21204
        // GIR_Coverage, 1284,
21205
0
        GIR_Done,
21206
      // Label 1187: @65454
21207
0
      GIM_Try, /*On fail goto*//*Label 1188*/ GIMT_Encode4(65524), // Rule ID 1285 //
21208
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21209
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs),
21210
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
21211
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
21212
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
21213
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21214
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21215
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21216
        // (intrinsic_wo_chain:{ *:[v8i8] } 3119:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VPMAXs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21217
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPMAXs8),
21218
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21219
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21220
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21221
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21222
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21223
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21224
0
        GIR_EraseFromParent, /*InsnID*/0,
21225
        // GIR_Coverage, 1285,
21226
0
        GIR_Done,
21227
      // Label 1188: @65524
21228
0
      GIM_Try, /*On fail goto*//*Label 1189*/ GIMT_Encode4(65594), // Rule ID 1286 //
21229
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21230
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs),
21231
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21232
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21233
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21234
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21235
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21236
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21237
        // (intrinsic_wo_chain:{ *:[v4i16] } 3119:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VPMAXs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
21238
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPMAXs16),
21239
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21240
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21241
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21242
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21243
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21244
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21245
0
        GIR_EraseFromParent, /*InsnID*/0,
21246
        // GIR_Coverage, 1286,
21247
0
        GIR_Done,
21248
      // Label 1189: @65594
21249
0
      GIM_Try, /*On fail goto*//*Label 1190*/ GIMT_Encode4(65664), // Rule ID 1287 //
21250
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21251
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs),
21252
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21253
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21254
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21255
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21256
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21257
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21258
        // (intrinsic_wo_chain:{ *:[v2i32] } 3119:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VPMAXs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21259
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPMAXs32),
21260
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21261
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21262
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21263
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21264
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21265
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21266
0
        GIR_EraseFromParent, /*InsnID*/0,
21267
        // GIR_Coverage, 1287,
21268
0
        GIR_Done,
21269
      // Label 1190: @65664
21270
0
      GIM_Try, /*On fail goto*//*Label 1191*/ GIMT_Encode4(65734), // Rule ID 1288 //
21271
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21272
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxu),
21273
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
21274
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
21275
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
21276
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21277
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21278
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21279
        // (intrinsic_wo_chain:{ *:[v8i8] } 3120:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VPMAXu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21280
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPMAXu8),
21281
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21282
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21283
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21284
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21285
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21286
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21287
0
        GIR_EraseFromParent, /*InsnID*/0,
21288
        // GIR_Coverage, 1288,
21289
0
        GIR_Done,
21290
      // Label 1191: @65734
21291
0
      GIM_Try, /*On fail goto*//*Label 1192*/ GIMT_Encode4(65804), // Rule ID 1289 //
21292
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21293
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxu),
21294
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21295
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21296
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21297
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21298
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21299
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21300
        // (intrinsic_wo_chain:{ *:[v4i16] } 3120:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VPMAXu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
21301
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPMAXu16),
21302
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21303
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21304
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21305
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21306
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21307
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21308
0
        GIR_EraseFromParent, /*InsnID*/0,
21309
        // GIR_Coverage, 1289,
21310
0
        GIR_Done,
21311
      // Label 1192: @65804
21312
0
      GIM_Try, /*On fail goto*//*Label 1193*/ GIMT_Encode4(65874), // Rule ID 1290 //
21313
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21314
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxu),
21315
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21316
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21317
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21318
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21319
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21320
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21321
        // (intrinsic_wo_chain:{ *:[v2i32] } 3120:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VPMAXu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21322
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPMAXu32),
21323
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21324
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21325
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21326
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21327
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21328
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21329
0
        GIR_EraseFromParent, /*InsnID*/0,
21330
        // GIR_Coverage, 1290,
21331
0
        GIR_Done,
21332
      // Label 1193: @65874
21333
0
      GIM_Try, /*On fail goto*//*Label 1194*/ GIMT_Encode4(65944), // Rule ID 1291 //
21334
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21335
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs),
21336
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21337
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21338
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21339
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21340
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21341
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21342
        // (intrinsic_wo_chain:{ *:[v2f32] } 3119:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VPMAXf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21343
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPMAXf),
21344
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21345
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21346
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21347
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21348
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21349
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21350
0
        GIR_EraseFromParent, /*InsnID*/0,
21351
        // GIR_Coverage, 1291,
21352
0
        GIR_Done,
21353
      // Label 1194: @65944
21354
0
      GIM_Try, /*On fail goto*//*Label 1195*/ GIMT_Encode4(66014), // Rule ID 1292 //
21355
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
21356
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs),
21357
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21358
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21359
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21360
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21361
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21362
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21363
        // (intrinsic_wo_chain:{ *:[v4f16] } 3119:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VPMAXh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21364
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPMAXh),
21365
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21366
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21367
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21368
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21369
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21370
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21371
0
        GIR_EraseFromParent, /*InsnID*/0,
21372
        // GIR_Coverage, 1292,
21373
0
        GIR_Done,
21374
      // Label 1195: @66014
21375
0
      GIM_Try, /*On fail goto*//*Label 1196*/ GIMT_Encode4(66084), // Rule ID 1293 //
21376
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21377
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins),
21378
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
21379
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
21380
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
21381
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21382
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21383
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21384
        // (intrinsic_wo_chain:{ *:[v8i8] } 3121:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VPMINs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21385
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPMINs8),
21386
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21387
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21388
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21389
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21390
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21391
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21392
0
        GIR_EraseFromParent, /*InsnID*/0,
21393
        // GIR_Coverage, 1293,
21394
0
        GIR_Done,
21395
      // Label 1196: @66084
21396
0
      GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(66154), // Rule ID 1294 //
21397
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21398
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins),
21399
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21400
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21401
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21402
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21403
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21404
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21405
        // (intrinsic_wo_chain:{ *:[v4i16] } 3121:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VPMINs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
21406
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPMINs16),
21407
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21408
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21409
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21410
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21411
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21412
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21413
0
        GIR_EraseFromParent, /*InsnID*/0,
21414
        // GIR_Coverage, 1294,
21415
0
        GIR_Done,
21416
      // Label 1197: @66154
21417
0
      GIM_Try, /*On fail goto*//*Label 1198*/ GIMT_Encode4(66224), // Rule ID 1295 //
21418
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21419
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins),
21420
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21421
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21422
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21423
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21424
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21425
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21426
        // (intrinsic_wo_chain:{ *:[v2i32] } 3121:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VPMINs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21427
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPMINs32),
21428
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21429
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21430
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21431
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21432
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21433
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21434
0
        GIR_EraseFromParent, /*InsnID*/0,
21435
        // GIR_Coverage, 1295,
21436
0
        GIR_Done,
21437
      // Label 1198: @66224
21438
0
      GIM_Try, /*On fail goto*//*Label 1199*/ GIMT_Encode4(66294), // Rule ID 1296 //
21439
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21440
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpminu),
21441
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
21442
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
21443
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
21444
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21445
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21446
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21447
        // (intrinsic_wo_chain:{ *:[v8i8] } 3122:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VPMINu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21448
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPMINu8),
21449
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21450
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21451
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21452
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21453
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21454
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21455
0
        GIR_EraseFromParent, /*InsnID*/0,
21456
        // GIR_Coverage, 1296,
21457
0
        GIR_Done,
21458
      // Label 1199: @66294
21459
0
      GIM_Try, /*On fail goto*//*Label 1200*/ GIMT_Encode4(66364), // Rule ID 1297 //
21460
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21461
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpminu),
21462
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21463
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21464
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21465
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21466
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21467
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21468
        // (intrinsic_wo_chain:{ *:[v4i16] } 3122:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VPMINu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
21469
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPMINu16),
21470
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21471
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21472
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21473
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21474
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21475
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21476
0
        GIR_EraseFromParent, /*InsnID*/0,
21477
        // GIR_Coverage, 1297,
21478
0
        GIR_Done,
21479
      // Label 1200: @66364
21480
0
      GIM_Try, /*On fail goto*//*Label 1201*/ GIMT_Encode4(66434), // Rule ID 1298 //
21481
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21482
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpminu),
21483
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21484
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21485
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21486
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21487
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21488
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21489
        // (intrinsic_wo_chain:{ *:[v2i32] } 3122:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VPMINu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21490
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPMINu32),
21491
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21492
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21493
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21494
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21495
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21496
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21497
0
        GIR_EraseFromParent, /*InsnID*/0,
21498
        // GIR_Coverage, 1298,
21499
0
        GIR_Done,
21500
      // Label 1201: @66434
21501
0
      GIM_Try, /*On fail goto*//*Label 1202*/ GIMT_Encode4(66504), // Rule ID 1299 //
21502
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21503
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins),
21504
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21505
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21506
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21507
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21508
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21509
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21510
        // (intrinsic_wo_chain:{ *:[v2f32] } 3121:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VPMINf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21511
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPMINf),
21512
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21513
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21514
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21515
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21516
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21517
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21518
0
        GIR_EraseFromParent, /*InsnID*/0,
21519
        // GIR_Coverage, 1299,
21520
0
        GIR_Done,
21521
      // Label 1202: @66504
21522
0
      GIM_Try, /*On fail goto*//*Label 1203*/ GIMT_Encode4(66574), // Rule ID 1300 //
21523
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
21524
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins),
21525
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21526
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21527
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21528
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21529
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21530
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21531
        // (intrinsic_wo_chain:{ *:[v4f16] } 3121:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VPMINh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21532
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VPMINh),
21533
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21534
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21535
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21536
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21537
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21538
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21539
0
        GIR_EraseFromParent, /*InsnID*/0,
21540
        // GIR_Coverage, 1300,
21541
0
        GIR_Done,
21542
      // Label 1203: @66574
21543
0
      GIM_Try, /*On fail goto*//*Label 1204*/ GIMT_Encode4(66644), // Rule ID 1307 //
21544
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21545
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps),
21546
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21547
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21548
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21549
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21550
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21551
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21552
        // (intrinsic_wo_chain:{ *:[v2f32] } 3146:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VRECPSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21553
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRECPSfd),
21554
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21555
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21556
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21557
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21558
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21559
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21560
0
        GIR_EraseFromParent, /*InsnID*/0,
21561
        // GIR_Coverage, 1307,
21562
0
        GIR_Done,
21563
      // Label 1204: @66644
21564
0
      GIM_Try, /*On fail goto*//*Label 1205*/ GIMT_Encode4(66714), // Rule ID 1308 //
21565
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21566
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps),
21567
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21568
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21569
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21570
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21571
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21572
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21573
        // (intrinsic_wo_chain:{ *:[v4f32] } 3146:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VRECPSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
21574
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRECPSfq),
21575
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21576
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21577
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21578
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21579
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21580
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21581
0
        GIR_EraseFromParent, /*InsnID*/0,
21582
        // GIR_Coverage, 1308,
21583
0
        GIR_Done,
21584
      // Label 1205: @66714
21585
0
      GIM_Try, /*On fail goto*//*Label 1206*/ GIMT_Encode4(66784), // Rule ID 1309 //
21586
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
21587
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps),
21588
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21589
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21590
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21591
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21592
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21593
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21594
        // (intrinsic_wo_chain:{ *:[v4f16] } 3146:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VRECPShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21595
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRECPShd),
21596
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21597
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21598
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21599
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21600
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21601
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21602
0
        GIR_EraseFromParent, /*InsnID*/0,
21603
        // GIR_Coverage, 1309,
21604
0
        GIR_Done,
21605
      // Label 1206: @66784
21606
0
      GIM_Try, /*On fail goto*//*Label 1207*/ GIMT_Encode4(66854), // Rule ID 1310 //
21607
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
21608
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps),
21609
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21610
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21611
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21612
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21613
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21614
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21615
        // (intrinsic_wo_chain:{ *:[v8f16] } 3146:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VRECPShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
21616
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRECPShq),
21617
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21618
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21619
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21620
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21621
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21622
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21623
0
        GIR_EraseFromParent, /*InsnID*/0,
21624
        // GIR_Coverage, 1310,
21625
0
        GIR_Done,
21626
      // Label 1207: @66854
21627
0
      GIM_Try, /*On fail goto*//*Label 1208*/ GIMT_Encode4(66924), // Rule ID 1317 //
21628
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21629
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts),
21630
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21631
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21632
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21633
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21634
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21635
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21636
        // (intrinsic_wo_chain:{ *:[v2f32] } 3159:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VRSQRTSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21637
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSQRTSfd),
21638
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21639
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21640
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21641
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21642
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21643
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21644
0
        GIR_EraseFromParent, /*InsnID*/0,
21645
        // GIR_Coverage, 1317,
21646
0
        GIR_Done,
21647
      // Label 1208: @66924
21648
0
      GIM_Try, /*On fail goto*//*Label 1209*/ GIMT_Encode4(66994), // Rule ID 1318 //
21649
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21650
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts),
21651
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21652
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21653
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21654
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21655
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21656
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21657
        // (intrinsic_wo_chain:{ *:[v4f32] } 3159:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VRSQRTSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
21658
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSQRTSfq),
21659
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21660
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21661
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21662
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21663
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21664
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21665
0
        GIR_EraseFromParent, /*InsnID*/0,
21666
        // GIR_Coverage, 1318,
21667
0
        GIR_Done,
21668
      // Label 1209: @66994
21669
0
      GIM_Try, /*On fail goto*//*Label 1210*/ GIMT_Encode4(67064), // Rule ID 1319 //
21670
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
21671
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts),
21672
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21673
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21674
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21675
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21676
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21677
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21678
        // (intrinsic_wo_chain:{ *:[v4f16] } 3159:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VRSQRTShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21679
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSQRTShd),
21680
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21681
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21682
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21683
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21684
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21685
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21686
0
        GIR_EraseFromParent, /*InsnID*/0,
21687
        // GIR_Coverage, 1319,
21688
0
        GIR_Done,
21689
      // Label 1210: @67064
21690
0
      GIM_Try, /*On fail goto*//*Label 1211*/ GIMT_Encode4(67134), // Rule ID 1320 //
21691
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
21692
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts),
21693
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21694
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21695
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21696
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21697
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21698
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21699
        // (intrinsic_wo_chain:{ *:[v8f16] } 3159:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VRSQRTShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
21700
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSQRTShq),
21701
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21702
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21703
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21704
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21705
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21706
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21707
0
        GIR_EraseFromParent, /*InsnID*/0,
21708
        // GIR_Coverage, 1320,
21709
0
        GIR_Done,
21710
      // Label 1211: @67134
21711
0
      GIM_Try, /*On fail goto*//*Label 1212*/ GIMT_Encode4(67204), // Rule ID 1321 //
21712
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21713
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
21714
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21715
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21716
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21717
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21718
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21719
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21720
        // (intrinsic_wo_chain:{ *:[v4i16] } 3162:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
21721
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSHLsv4i16),
21722
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21723
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21724
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21725
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21726
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21727
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21728
0
        GIR_EraseFromParent, /*InsnID*/0,
21729
        // GIR_Coverage, 1321,
21730
0
        GIR_Done,
21731
      // Label 1212: @67204
21732
0
      GIM_Try, /*On fail goto*//*Label 1213*/ GIMT_Encode4(67274), // Rule ID 1322 //
21733
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21734
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
21735
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21736
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21737
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21738
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21739
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21740
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21741
        // (intrinsic_wo_chain:{ *:[v2i32] } 3162:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
21742
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSHLsv2i32),
21743
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21744
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21745
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21746
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21747
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21748
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21749
0
        GIR_EraseFromParent, /*InsnID*/0,
21750
        // GIR_Coverage, 1322,
21751
0
        GIR_Done,
21752
      // Label 1213: @67274
21753
0
      GIM_Try, /*On fail goto*//*Label 1214*/ GIMT_Encode4(67344), // Rule ID 1323 //
21754
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21755
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
21756
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21757
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21758
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21759
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21760
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21761
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21762
        // (intrinsic_wo_chain:{ *:[v8i16] } 3162:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
21763
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSHLsv8i16),
21764
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21765
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21766
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21767
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21768
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21769
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21770
0
        GIR_EraseFromParent, /*InsnID*/0,
21771
        // GIR_Coverage, 1323,
21772
0
        GIR_Done,
21773
      // Label 1214: @67344
21774
0
      GIM_Try, /*On fail goto*//*Label 1215*/ GIMT_Encode4(67414), // Rule ID 1324 //
21775
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21776
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
21777
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21778
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21779
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21780
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21781
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21782
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21783
        // (intrinsic_wo_chain:{ *:[v4i32] } 3162:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
21784
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSHLsv4i32),
21785
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21786
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21787
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21788
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21789
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21790
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21791
0
        GIR_EraseFromParent, /*InsnID*/0,
21792
        // GIR_Coverage, 1324,
21793
0
        GIR_Done,
21794
      // Label 1215: @67414
21795
0
      GIM_Try, /*On fail goto*//*Label 1216*/ GIMT_Encode4(67484), // Rule ID 1325 //
21796
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21797
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
21798
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
21799
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
21800
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
21801
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21802
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21803
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21804
        // (intrinsic_wo_chain:{ *:[v8i8] } 3162:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
21805
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSHLsv8i8),
21806
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21807
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21808
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21809
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21810
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21811
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21812
0
        GIR_EraseFromParent, /*InsnID*/0,
21813
        // GIR_Coverage, 1325,
21814
0
        GIR_Done,
21815
      // Label 1216: @67484
21816
0
      GIM_Try, /*On fail goto*//*Label 1217*/ GIMT_Encode4(67554), // Rule ID 1326 //
21817
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21818
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
21819
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
21820
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
21821
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
21822
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21823
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21824
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21825
        // (intrinsic_wo_chain:{ *:[v16i8] } 3162:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
21826
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSHLsv16i8),
21827
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21828
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21829
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21830
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21831
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21832
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21833
0
        GIR_EraseFromParent, /*InsnID*/0,
21834
        // GIR_Coverage, 1326,
21835
0
        GIR_Done,
21836
      // Label 1217: @67554
21837
0
      GIM_Try, /*On fail goto*//*Label 1218*/ GIMT_Encode4(67624), // Rule ID 1327 //
21838
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21839
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
21840
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
21841
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21842
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21843
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21844
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21845
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21846
        // (intrinsic_wo_chain:{ *:[v1i64] } 3162:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
21847
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSHLsv1i64),
21848
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21849
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21850
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21851
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21852
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21853
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21854
0
        GIR_EraseFromParent, /*InsnID*/0,
21855
        // GIR_Coverage, 1327,
21856
0
        GIR_Done,
21857
      // Label 1218: @67624
21858
0
      GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(67694), // Rule ID 1328 //
21859
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21860
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
21861
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
21862
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
21863
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
21864
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21865
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21866
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21867
        // (intrinsic_wo_chain:{ *:[v2i64] } 3162:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
21868
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSHLsv2i64),
21869
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21870
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21871
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21872
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21873
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21874
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21875
0
        GIR_EraseFromParent, /*InsnID*/0,
21876
        // GIR_Coverage, 1328,
21877
0
        GIR_Done,
21878
      // Label 1219: @67694
21879
0
      GIM_Try, /*On fail goto*//*Label 1220*/ GIMT_Encode4(67764), // Rule ID 1329 //
21880
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21881
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
21882
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21883
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21884
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21885
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21886
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21887
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21888
        // (intrinsic_wo_chain:{ *:[v4i16] } 3163:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
21889
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSHLuv4i16),
21890
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21891
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21892
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21893
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21894
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21895
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21896
0
        GIR_EraseFromParent, /*InsnID*/0,
21897
        // GIR_Coverage, 1329,
21898
0
        GIR_Done,
21899
      // Label 1220: @67764
21900
0
      GIM_Try, /*On fail goto*//*Label 1221*/ GIMT_Encode4(67834), // Rule ID 1330 //
21901
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21902
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
21903
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21904
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21905
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21906
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21907
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21908
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21909
        // (intrinsic_wo_chain:{ *:[v2i32] } 3163:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
21910
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSHLuv2i32),
21911
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21912
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21913
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21914
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21915
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21916
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21917
0
        GIR_EraseFromParent, /*InsnID*/0,
21918
        // GIR_Coverage, 1330,
21919
0
        GIR_Done,
21920
      // Label 1221: @67834
21921
0
      GIM_Try, /*On fail goto*//*Label 1222*/ GIMT_Encode4(67904), // Rule ID 1331 //
21922
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21923
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
21924
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21925
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21926
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21927
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21928
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21929
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21930
        // (intrinsic_wo_chain:{ *:[v8i16] } 3163:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
21931
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSHLuv8i16),
21932
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21933
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21934
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21935
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21936
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21937
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21938
0
        GIR_EraseFromParent, /*InsnID*/0,
21939
        // GIR_Coverage, 1331,
21940
0
        GIR_Done,
21941
      // Label 1222: @67904
21942
0
      GIM_Try, /*On fail goto*//*Label 1223*/ GIMT_Encode4(67974), // Rule ID 1332 //
21943
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21944
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
21945
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21946
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21947
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21948
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21949
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21950
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21951
        // (intrinsic_wo_chain:{ *:[v4i32] } 3163:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
21952
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSHLuv4i32),
21953
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21954
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21955
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21956
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21957
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21958
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21959
0
        GIR_EraseFromParent, /*InsnID*/0,
21960
        // GIR_Coverage, 1332,
21961
0
        GIR_Done,
21962
      // Label 1223: @67974
21963
0
      GIM_Try, /*On fail goto*//*Label 1224*/ GIMT_Encode4(68044), // Rule ID 1333 //
21964
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21965
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
21966
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
21967
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
21968
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
21969
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21970
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21971
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21972
        // (intrinsic_wo_chain:{ *:[v8i8] } 3163:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
21973
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSHLuv8i8),
21974
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21975
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21976
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21977
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21978
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21979
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21980
0
        GIR_EraseFromParent, /*InsnID*/0,
21981
        // GIR_Coverage, 1333,
21982
0
        GIR_Done,
21983
      // Label 1224: @68044
21984
0
      GIM_Try, /*On fail goto*//*Label 1225*/ GIMT_Encode4(68114), // Rule ID 1334 //
21985
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21986
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
21987
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
21988
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
21989
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
21990
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21991
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21992
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21993
        // (intrinsic_wo_chain:{ *:[v16i8] } 3163:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
21994
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSHLuv16i8),
21995
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
21996
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21997
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21998
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21999
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22000
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22001
0
        GIR_EraseFromParent, /*InsnID*/0,
22002
        // GIR_Coverage, 1334,
22003
0
        GIR_Done,
22004
      // Label 1225: @68114
22005
0
      GIM_Try, /*On fail goto*//*Label 1226*/ GIMT_Encode4(68184), // Rule ID 1335 //
22006
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22007
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
22008
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
22009
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22010
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
22011
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22012
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22013
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22014
        // (intrinsic_wo_chain:{ *:[v1i64] } 3163:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22015
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSHLuv1i64),
22016
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22017
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22018
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22019
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22020
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22021
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22022
0
        GIR_EraseFromParent, /*InsnID*/0,
22023
        // GIR_Coverage, 1335,
22024
0
        GIR_Done,
22025
      // Label 1226: @68184
22026
0
      GIM_Try, /*On fail goto*//*Label 1227*/ GIMT_Encode4(68254), // Rule ID 1336 //
22027
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22028
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
22029
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
22030
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
22031
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
22032
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22033
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22034
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22035
        // (intrinsic_wo_chain:{ *:[v2i64] } 3163:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22036
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSHLuv2i64),
22037
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22038
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22039
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22040
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22041
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22042
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22043
0
        GIR_EraseFromParent, /*InsnID*/0,
22044
        // GIR_Coverage, 1336,
22045
0
        GIR_Done,
22046
      // Label 1227: @68254
22047
0
      GIM_Try, /*On fail goto*//*Label 1228*/ GIMT_Encode4(68324), // Rule ID 1370 //
22048
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22049
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22050
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
22051
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
22052
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
22053
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22054
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22055
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22056
        // (intrinsic_wo_chain:{ *:[v4i16] } 3156:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22057
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv4i16),
22058
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22059
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22060
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22061
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22062
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22063
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22064
0
        GIR_EraseFromParent, /*InsnID*/0,
22065
        // GIR_Coverage, 1370,
22066
0
        GIR_Done,
22067
      // Label 1228: @68324
22068
0
      GIM_Try, /*On fail goto*//*Label 1229*/ GIMT_Encode4(68394), // Rule ID 1371 //
22069
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22070
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22071
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
22072
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
22073
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
22074
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22075
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22076
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22077
        // (intrinsic_wo_chain:{ *:[v2i32] } 3156:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22078
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv2i32),
22079
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22080
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22081
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22082
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22083
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22084
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22085
0
        GIR_EraseFromParent, /*InsnID*/0,
22086
        // GIR_Coverage, 1371,
22087
0
        GIR_Done,
22088
      // Label 1229: @68394
22089
0
      GIM_Try, /*On fail goto*//*Label 1230*/ GIMT_Encode4(68464), // Rule ID 1372 //
22090
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22091
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22092
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22093
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22094
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22095
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22096
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22097
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22098
        // (intrinsic_wo_chain:{ *:[v8i16] } 3156:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22099
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv8i16),
22100
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22101
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22102
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22103
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22104
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22105
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22106
0
        GIR_EraseFromParent, /*InsnID*/0,
22107
        // GIR_Coverage, 1372,
22108
0
        GIR_Done,
22109
      // Label 1230: @68464
22110
0
      GIM_Try, /*On fail goto*//*Label 1231*/ GIMT_Encode4(68534), // Rule ID 1373 //
22111
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22112
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22113
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22114
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22115
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22116
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22117
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22118
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22119
        // (intrinsic_wo_chain:{ *:[v4i32] } 3156:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22120
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv4i32),
22121
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22122
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22123
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22124
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22125
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22126
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22127
0
        GIR_EraseFromParent, /*InsnID*/0,
22128
        // GIR_Coverage, 1373,
22129
0
        GIR_Done,
22130
      // Label 1231: @68534
22131
0
      GIM_Try, /*On fail goto*//*Label 1232*/ GIMT_Encode4(68604), // Rule ID 1374 //
22132
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22133
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22134
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
22135
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
22136
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
22137
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22138
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22139
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22140
        // (intrinsic_wo_chain:{ *:[v8i8] } 3156:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22141
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv8i8),
22142
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22143
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22144
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22145
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22146
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22147
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22148
0
        GIR_EraseFromParent, /*InsnID*/0,
22149
        // GIR_Coverage, 1374,
22150
0
        GIR_Done,
22151
      // Label 1232: @68604
22152
0
      GIM_Try, /*On fail goto*//*Label 1233*/ GIMT_Encode4(68674), // Rule ID 1375 //
22153
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22154
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22155
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22156
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22157
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22158
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22159
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22160
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22161
        // (intrinsic_wo_chain:{ *:[v16i8] } 3156:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22162
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv16i8),
22163
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22164
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22165
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22166
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22167
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22168
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22169
0
        GIR_EraseFromParent, /*InsnID*/0,
22170
        // GIR_Coverage, 1375,
22171
0
        GIR_Done,
22172
      // Label 1233: @68674
22173
0
      GIM_Try, /*On fail goto*//*Label 1234*/ GIMT_Encode4(68744), // Rule ID 1376 //
22174
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22175
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22176
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
22177
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22178
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
22179
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22180
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22181
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22182
        // (intrinsic_wo_chain:{ *:[v1i64] } 3156:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22183
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv1i64),
22184
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22185
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22186
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22187
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22188
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22189
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22190
0
        GIR_EraseFromParent, /*InsnID*/0,
22191
        // GIR_Coverage, 1376,
22192
0
        GIR_Done,
22193
      // Label 1234: @68744
22194
0
      GIM_Try, /*On fail goto*//*Label 1235*/ GIMT_Encode4(68814), // Rule ID 1377 //
22195
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22196
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22197
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
22198
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
22199
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
22200
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22201
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22202
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22203
        // (intrinsic_wo_chain:{ *:[v2i64] } 3156:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22204
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv2i64),
22205
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22206
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22207
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22208
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22209
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22210
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22211
0
        GIR_EraseFromParent, /*InsnID*/0,
22212
        // GIR_Coverage, 1377,
22213
0
        GIR_Done,
22214
      // Label 1235: @68814
22215
0
      GIM_Try, /*On fail goto*//*Label 1236*/ GIMT_Encode4(68884), // Rule ID 1378 //
22216
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22217
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22218
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
22219
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
22220
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
22221
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22222
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22223
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22224
        // (intrinsic_wo_chain:{ *:[v4i16] } 3157:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22225
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv4i16),
22226
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22227
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22228
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22229
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22230
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22231
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22232
0
        GIR_EraseFromParent, /*InsnID*/0,
22233
        // GIR_Coverage, 1378,
22234
0
        GIR_Done,
22235
      // Label 1236: @68884
22236
0
      GIM_Try, /*On fail goto*//*Label 1237*/ GIMT_Encode4(68954), // Rule ID 1379 //
22237
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22238
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22239
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
22240
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
22241
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
22242
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22243
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22244
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22245
        // (intrinsic_wo_chain:{ *:[v2i32] } 3157:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22246
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv2i32),
22247
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22248
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22249
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22250
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22251
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22252
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22253
0
        GIR_EraseFromParent, /*InsnID*/0,
22254
        // GIR_Coverage, 1379,
22255
0
        GIR_Done,
22256
      // Label 1237: @68954
22257
0
      GIM_Try, /*On fail goto*//*Label 1238*/ GIMT_Encode4(69024), // Rule ID 1380 //
22258
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22259
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22260
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22261
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22262
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22263
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22264
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22265
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22266
        // (intrinsic_wo_chain:{ *:[v8i16] } 3157:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22267
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv8i16),
22268
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22269
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22270
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22271
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22272
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22273
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22274
0
        GIR_EraseFromParent, /*InsnID*/0,
22275
        // GIR_Coverage, 1380,
22276
0
        GIR_Done,
22277
      // Label 1238: @69024
22278
0
      GIM_Try, /*On fail goto*//*Label 1239*/ GIMT_Encode4(69094), // Rule ID 1381 //
22279
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22280
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22281
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22282
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22283
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22284
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22285
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22286
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22287
        // (intrinsic_wo_chain:{ *:[v4i32] } 3157:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22288
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv4i32),
22289
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22290
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22291
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22292
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22293
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22294
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22295
0
        GIR_EraseFromParent, /*InsnID*/0,
22296
        // GIR_Coverage, 1381,
22297
0
        GIR_Done,
22298
      // Label 1239: @69094
22299
0
      GIM_Try, /*On fail goto*//*Label 1240*/ GIMT_Encode4(69164), // Rule ID 1382 //
22300
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22301
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22302
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
22303
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
22304
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
22305
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22306
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22307
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22308
        // (intrinsic_wo_chain:{ *:[v8i8] } 3157:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22309
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv8i8),
22310
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22311
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22312
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22313
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22314
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22315
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22316
0
        GIR_EraseFromParent, /*InsnID*/0,
22317
        // GIR_Coverage, 1382,
22318
0
        GIR_Done,
22319
      // Label 1240: @69164
22320
0
      GIM_Try, /*On fail goto*//*Label 1241*/ GIMT_Encode4(69234), // Rule ID 1383 //
22321
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22322
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22323
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22324
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22325
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22326
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22327
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22328
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22329
        // (intrinsic_wo_chain:{ *:[v16i8] } 3157:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22330
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv16i8),
22331
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22332
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22333
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22334
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22335
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22336
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22337
0
        GIR_EraseFromParent, /*InsnID*/0,
22338
        // GIR_Coverage, 1383,
22339
0
        GIR_Done,
22340
      // Label 1241: @69234
22341
0
      GIM_Try, /*On fail goto*//*Label 1242*/ GIMT_Encode4(69304), // Rule ID 1384 //
22342
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22343
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22344
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
22345
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22346
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
22347
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22348
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22349
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22350
        // (intrinsic_wo_chain:{ *:[v1i64] } 3157:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22351
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv1i64),
22352
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22353
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22354
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22355
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22356
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22357
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22358
0
        GIR_EraseFromParent, /*InsnID*/0,
22359
        // GIR_Coverage, 1384,
22360
0
        GIR_Done,
22361
      // Label 1242: @69304
22362
0
      GIM_Try, /*On fail goto*//*Label 1243*/ GIMT_Encode4(69374), // Rule ID 1385 //
22363
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22364
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22365
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
22366
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
22367
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
22368
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22369
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22370
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22371
        // (intrinsic_wo_chain:{ *:[v2i64] } 3157:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22372
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv2i64),
22373
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22374
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22375
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22376
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22377
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22378
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22379
0
        GIR_EraseFromParent, /*InsnID*/0,
22380
        // GIR_Coverage, 1385,
22381
0
        GIR_Done,
22382
      // Label 1243: @69374
22383
0
      GIM_Try, /*On fail goto*//*Label 1244*/ GIMT_Encode4(69444), // Rule ID 1405 //
22384
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22385
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
22386
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
22387
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
22388
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
22389
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22390
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22391
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22392
        // (intrinsic_wo_chain:{ *:[v4i16] } 3141:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VQSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22393
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv4i16),
22394
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22395
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22396
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22397
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22398
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22399
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22400
0
        GIR_EraseFromParent, /*InsnID*/0,
22401
        // GIR_Coverage, 1405,
22402
0
        GIR_Done,
22403
      // Label 1244: @69444
22404
0
      GIM_Try, /*On fail goto*//*Label 1245*/ GIMT_Encode4(69514), // Rule ID 1406 //
22405
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22406
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
22407
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
22408
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
22409
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
22410
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22411
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22412
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22413
        // (intrinsic_wo_chain:{ *:[v2i32] } 3141:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VQSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22414
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv2i32),
22415
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22416
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22417
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22418
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22419
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22420
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22421
0
        GIR_EraseFromParent, /*InsnID*/0,
22422
        // GIR_Coverage, 1406,
22423
0
        GIR_Done,
22424
      // Label 1245: @69514
22425
0
      GIM_Try, /*On fail goto*//*Label 1246*/ GIMT_Encode4(69584), // Rule ID 1407 //
22426
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22427
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
22428
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22429
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22430
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22431
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22432
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22433
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22434
        // (intrinsic_wo_chain:{ *:[v8i16] } 3141:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VQSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22435
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv8i16),
22436
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22437
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22438
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22439
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22440
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22441
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22442
0
        GIR_EraseFromParent, /*InsnID*/0,
22443
        // GIR_Coverage, 1407,
22444
0
        GIR_Done,
22445
      // Label 1246: @69584
22446
0
      GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(69654), // Rule ID 1408 //
22447
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22448
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
22449
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22450
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22451
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22452
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22453
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22454
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22455
        // (intrinsic_wo_chain:{ *:[v4i32] } 3141:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VQSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22456
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv4i32),
22457
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22458
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22459
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22460
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22461
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22462
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22463
0
        GIR_EraseFromParent, /*InsnID*/0,
22464
        // GIR_Coverage, 1408,
22465
0
        GIR_Done,
22466
      // Label 1247: @69654
22467
0
      GIM_Try, /*On fail goto*//*Label 1248*/ GIMT_Encode4(69724), // Rule ID 1409 //
22468
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22469
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
22470
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
22471
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
22472
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
22473
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22474
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22475
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22476
        // (intrinsic_wo_chain:{ *:[v8i8] } 3141:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VQSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22477
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv8i8),
22478
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22479
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22480
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22481
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22482
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22483
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22484
0
        GIR_EraseFromParent, /*InsnID*/0,
22485
        // GIR_Coverage, 1409,
22486
0
        GIR_Done,
22487
      // Label 1248: @69724
22488
0
      GIM_Try, /*On fail goto*//*Label 1249*/ GIMT_Encode4(69794), // Rule ID 1410 //
22489
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22490
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
22491
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22492
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22493
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22494
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22495
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22496
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22497
        // (intrinsic_wo_chain:{ *:[v16i8] } 3141:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VQSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22498
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv16i8),
22499
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22500
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22501
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22502
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22503
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22504
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22505
0
        GIR_EraseFromParent, /*InsnID*/0,
22506
        // GIR_Coverage, 1410,
22507
0
        GIR_Done,
22508
      // Label 1249: @69794
22509
0
      GIM_Try, /*On fail goto*//*Label 1250*/ GIMT_Encode4(69864), // Rule ID 1411 //
22510
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22511
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
22512
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
22513
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22514
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
22515
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22516
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22517
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22518
        // (intrinsic_wo_chain:{ *:[v1i64] } 3141:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VQSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22519
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv1i64),
22520
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22521
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22522
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22523
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22524
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22525
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22526
0
        GIR_EraseFromParent, /*InsnID*/0,
22527
        // GIR_Coverage, 1411,
22528
0
        GIR_Done,
22529
      // Label 1250: @69864
22530
0
      GIM_Try, /*On fail goto*//*Label 1251*/ GIMT_Encode4(69934), // Rule ID 1412 //
22531
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22532
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
22533
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
22534
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
22535
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
22536
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22537
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22538
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22539
        // (intrinsic_wo_chain:{ *:[v2i64] } 3141:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VQSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22540
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv2i64),
22541
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22542
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22543
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22544
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22545
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22546
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22547
0
        GIR_EraseFromParent, /*InsnID*/0,
22548
        // GIR_Coverage, 1412,
22549
0
        GIR_Done,
22550
      // Label 1251: @69934
22551
0
      GIM_Try, /*On fail goto*//*Label 1252*/ GIMT_Encode4(70004), // Rule ID 1413 //
22552
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22553
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
22554
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
22555
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
22556
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
22557
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22558
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22559
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22560
        // (intrinsic_wo_chain:{ *:[v4i16] } 3143:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VQSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22561
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv4i16),
22562
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22563
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22564
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22565
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22566
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22567
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22568
0
        GIR_EraseFromParent, /*InsnID*/0,
22569
        // GIR_Coverage, 1413,
22570
0
        GIR_Done,
22571
      // Label 1252: @70004
22572
0
      GIM_Try, /*On fail goto*//*Label 1253*/ GIMT_Encode4(70074), // Rule ID 1414 //
22573
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22574
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
22575
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
22576
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
22577
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
22578
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22579
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22580
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22581
        // (intrinsic_wo_chain:{ *:[v2i32] } 3143:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VQSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22582
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv2i32),
22583
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22584
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22585
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22586
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22587
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22588
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22589
0
        GIR_EraseFromParent, /*InsnID*/0,
22590
        // GIR_Coverage, 1414,
22591
0
        GIR_Done,
22592
      // Label 1253: @70074
22593
0
      GIM_Try, /*On fail goto*//*Label 1254*/ GIMT_Encode4(70144), // Rule ID 1415 //
22594
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22595
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
22596
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22597
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22598
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22599
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22600
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22601
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22602
        // (intrinsic_wo_chain:{ *:[v8i16] } 3143:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VQSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22603
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv8i16),
22604
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22605
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22606
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22607
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22608
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22609
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22610
0
        GIR_EraseFromParent, /*InsnID*/0,
22611
        // GIR_Coverage, 1415,
22612
0
        GIR_Done,
22613
      // Label 1254: @70144
22614
0
      GIM_Try, /*On fail goto*//*Label 1255*/ GIMT_Encode4(70214), // Rule ID 1416 //
22615
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22616
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
22617
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22618
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22619
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22620
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22621
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22622
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22623
        // (intrinsic_wo_chain:{ *:[v4i32] } 3143:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VQSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22624
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv4i32),
22625
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22626
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22627
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22628
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22629
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22630
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22631
0
        GIR_EraseFromParent, /*InsnID*/0,
22632
        // GIR_Coverage, 1416,
22633
0
        GIR_Done,
22634
      // Label 1255: @70214
22635
0
      GIM_Try, /*On fail goto*//*Label 1256*/ GIMT_Encode4(70284), // Rule ID 1417 //
22636
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22637
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
22638
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
22639
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
22640
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
22641
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22642
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22643
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22644
        // (intrinsic_wo_chain:{ *:[v8i8] } 3143:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VQSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22645
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv8i8),
22646
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22647
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22648
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22649
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22650
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22651
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22652
0
        GIR_EraseFromParent, /*InsnID*/0,
22653
        // GIR_Coverage, 1417,
22654
0
        GIR_Done,
22655
      // Label 1256: @70284
22656
0
      GIM_Try, /*On fail goto*//*Label 1257*/ GIMT_Encode4(70354), // Rule ID 1418 //
22657
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22658
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
22659
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22660
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22661
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22662
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22663
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22664
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22665
        // (intrinsic_wo_chain:{ *:[v16i8] } 3143:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VQSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22666
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv16i8),
22667
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22668
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22669
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22670
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22671
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22672
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22673
0
        GIR_EraseFromParent, /*InsnID*/0,
22674
        // GIR_Coverage, 1418,
22675
0
        GIR_Done,
22676
      // Label 1257: @70354
22677
0
      GIM_Try, /*On fail goto*//*Label 1258*/ GIMT_Encode4(70424), // Rule ID 1419 //
22678
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22679
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
22680
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
22681
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22682
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
22683
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22684
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22685
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22686
        // (intrinsic_wo_chain:{ *:[v1i64] } 3143:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VQSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22687
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv1i64),
22688
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22689
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22690
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22691
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22692
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22693
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22694
0
        GIR_EraseFromParent, /*InsnID*/0,
22695
        // GIR_Coverage, 1419,
22696
0
        GIR_Done,
22697
      // Label 1258: @70424
22698
0
      GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(70494), // Rule ID 1420 //
22699
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22700
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
22701
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
22702
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
22703
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
22704
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22705
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22706
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22707
        // (intrinsic_wo_chain:{ *:[v2i64] } 3143:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VQSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22708
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv2i64),
22709
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22710
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22711
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22712
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22713
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22714
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22715
0
        GIR_EraseFromParent, /*InsnID*/0,
22716
        // GIR_Coverage, 1420,
22717
0
        GIR_Done,
22718
      // Label 1259: @70494
22719
0
      GIM_Try, /*On fail goto*//*Label 1260*/ GIMT_Encode4(70564), // Rule ID 1454 //
22720
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22721
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
22722
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
22723
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
22724
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
22725
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22726
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22727
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22728
        // (intrinsic_wo_chain:{ *:[v4i16] } 3136:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VQRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22729
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv4i16),
22730
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22731
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22732
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22733
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22734
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22735
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22736
0
        GIR_EraseFromParent, /*InsnID*/0,
22737
        // GIR_Coverage, 1454,
22738
0
        GIR_Done,
22739
      // Label 1260: @70564
22740
0
      GIM_Try, /*On fail goto*//*Label 1261*/ GIMT_Encode4(70634), // Rule ID 1455 //
22741
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22742
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
22743
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
22744
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
22745
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
22746
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22747
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22748
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22749
        // (intrinsic_wo_chain:{ *:[v2i32] } 3136:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VQRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22750
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv2i32),
22751
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22752
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22753
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22754
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22755
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22756
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22757
0
        GIR_EraseFromParent, /*InsnID*/0,
22758
        // GIR_Coverage, 1455,
22759
0
        GIR_Done,
22760
      // Label 1261: @70634
22761
0
      GIM_Try, /*On fail goto*//*Label 1262*/ GIMT_Encode4(70704), // Rule ID 1456 //
22762
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22763
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
22764
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22765
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22766
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22767
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22768
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22769
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22770
        // (intrinsic_wo_chain:{ *:[v8i16] } 3136:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VQRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22771
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv8i16),
22772
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22773
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22774
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22775
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22776
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22777
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22778
0
        GIR_EraseFromParent, /*InsnID*/0,
22779
        // GIR_Coverage, 1456,
22780
0
        GIR_Done,
22781
      // Label 1262: @70704
22782
0
      GIM_Try, /*On fail goto*//*Label 1263*/ GIMT_Encode4(70774), // Rule ID 1457 //
22783
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22784
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
22785
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22786
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22787
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22788
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22789
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22790
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22791
        // (intrinsic_wo_chain:{ *:[v4i32] } 3136:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VQRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22792
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv4i32),
22793
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22794
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22795
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22796
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22797
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22798
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22799
0
        GIR_EraseFromParent, /*InsnID*/0,
22800
        // GIR_Coverage, 1457,
22801
0
        GIR_Done,
22802
      // Label 1263: @70774
22803
0
      GIM_Try, /*On fail goto*//*Label 1264*/ GIMT_Encode4(70844), // Rule ID 1458 //
22804
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22805
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
22806
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
22807
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
22808
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
22809
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22810
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22811
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22812
        // (intrinsic_wo_chain:{ *:[v8i8] } 3136:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VQRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22813
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv8i8),
22814
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22815
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22816
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22817
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22818
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22819
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22820
0
        GIR_EraseFromParent, /*InsnID*/0,
22821
        // GIR_Coverage, 1458,
22822
0
        GIR_Done,
22823
      // Label 1264: @70844
22824
0
      GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(70914), // Rule ID 1459 //
22825
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22826
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
22827
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22828
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22829
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22830
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22831
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22832
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22833
        // (intrinsic_wo_chain:{ *:[v16i8] } 3136:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VQRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22834
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv16i8),
22835
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22836
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22837
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22838
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22839
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22840
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22841
0
        GIR_EraseFromParent, /*InsnID*/0,
22842
        // GIR_Coverage, 1459,
22843
0
        GIR_Done,
22844
      // Label 1265: @70914
22845
0
      GIM_Try, /*On fail goto*//*Label 1266*/ GIMT_Encode4(70984), // Rule ID 1460 //
22846
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22847
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
22848
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
22849
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22850
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
22851
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22852
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22853
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22854
        // (intrinsic_wo_chain:{ *:[v1i64] } 3136:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VQRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22855
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv1i64),
22856
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22857
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22858
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22859
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22860
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22861
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22862
0
        GIR_EraseFromParent, /*InsnID*/0,
22863
        // GIR_Coverage, 1460,
22864
0
        GIR_Done,
22865
      // Label 1266: @70984
22866
0
      GIM_Try, /*On fail goto*//*Label 1267*/ GIMT_Encode4(71054), // Rule ID 1461 //
22867
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22868
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
22869
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
22870
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
22871
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
22872
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22873
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22874
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22875
        // (intrinsic_wo_chain:{ *:[v2i64] } 3136:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VQRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22876
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv2i64),
22877
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22878
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22879
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22880
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22881
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22882
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22883
0
        GIR_EraseFromParent, /*InsnID*/0,
22884
        // GIR_Coverage, 1461,
22885
0
        GIR_Done,
22886
      // Label 1267: @71054
22887
0
      GIM_Try, /*On fail goto*//*Label 1268*/ GIMT_Encode4(71124), // Rule ID 1462 //
22888
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22889
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
22890
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
22891
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
22892
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
22893
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22894
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22895
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22896
        // (intrinsic_wo_chain:{ *:[v4i16] } 3137:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VQRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22897
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv4i16),
22898
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22899
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22900
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22901
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22902
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22903
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22904
0
        GIR_EraseFromParent, /*InsnID*/0,
22905
        // GIR_Coverage, 1462,
22906
0
        GIR_Done,
22907
      // Label 1268: @71124
22908
0
      GIM_Try, /*On fail goto*//*Label 1269*/ GIMT_Encode4(71194), // Rule ID 1463 //
22909
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22910
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
22911
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
22912
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
22913
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
22914
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22915
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22916
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22917
        // (intrinsic_wo_chain:{ *:[v2i32] } 3137:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VQRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22918
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv2i32),
22919
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22920
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22921
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22922
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22923
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22924
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22925
0
        GIR_EraseFromParent, /*InsnID*/0,
22926
        // GIR_Coverage, 1463,
22927
0
        GIR_Done,
22928
      // Label 1269: @71194
22929
0
      GIM_Try, /*On fail goto*//*Label 1270*/ GIMT_Encode4(71264), // Rule ID 1464 //
22930
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22931
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
22932
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22933
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22934
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22935
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22936
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22937
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22938
        // (intrinsic_wo_chain:{ *:[v8i16] } 3137:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VQRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22939
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv8i16),
22940
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22941
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22942
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22943
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22944
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22945
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22946
0
        GIR_EraseFromParent, /*InsnID*/0,
22947
        // GIR_Coverage, 1464,
22948
0
        GIR_Done,
22949
      // Label 1270: @71264
22950
0
      GIM_Try, /*On fail goto*//*Label 1271*/ GIMT_Encode4(71334), // Rule ID 1465 //
22951
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22952
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
22953
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22954
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22955
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22956
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22957
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22958
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22959
        // (intrinsic_wo_chain:{ *:[v4i32] } 3137:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VQRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22960
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv4i32),
22961
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22962
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22963
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22964
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22965
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22966
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22967
0
        GIR_EraseFromParent, /*InsnID*/0,
22968
        // GIR_Coverage, 1465,
22969
0
        GIR_Done,
22970
      // Label 1271: @71334
22971
0
      GIM_Try, /*On fail goto*//*Label 1272*/ GIMT_Encode4(71404), // Rule ID 1466 //
22972
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22973
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
22974
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
22975
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
22976
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
22977
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22978
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22979
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22980
        // (intrinsic_wo_chain:{ *:[v8i8] } 3137:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VQRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22981
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv8i8),
22982
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
22983
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22984
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22985
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22986
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22987
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22988
0
        GIR_EraseFromParent, /*InsnID*/0,
22989
        // GIR_Coverage, 1466,
22990
0
        GIR_Done,
22991
      // Label 1272: @71404
22992
0
      GIM_Try, /*On fail goto*//*Label 1273*/ GIMT_Encode4(71474), // Rule ID 1467 //
22993
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22994
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
22995
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22996
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22997
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22998
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22999
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23000
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23001
        // (intrinsic_wo_chain:{ *:[v16i8] } 3137:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VQRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
23002
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv16i8),
23003
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
23004
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
23005
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
23006
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23007
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23008
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23009
0
        GIR_EraseFromParent, /*InsnID*/0,
23010
        // GIR_Coverage, 1467,
23011
0
        GIR_Done,
23012
      // Label 1273: @71474
23013
0
      GIM_Try, /*On fail goto*//*Label 1274*/ GIMT_Encode4(71544), // Rule ID 1468 //
23014
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23015
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
23016
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
23017
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
23018
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
23019
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23020
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23021
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23022
        // (intrinsic_wo_chain:{ *:[v1i64] } 3137:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VQRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
23023
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv1i64),
23024
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
23025
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
23026
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
23027
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23028
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23029
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23030
0
        GIR_EraseFromParent, /*InsnID*/0,
23031
        // GIR_Coverage, 1468,
23032
0
        GIR_Done,
23033
      // Label 1274: @71544
23034
0
      GIM_Try, /*On fail goto*//*Label 1275*/ GIMT_Encode4(71614), // Rule ID 1469 //
23035
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23036
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
23037
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
23038
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
23039
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
23040
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23041
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23042
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23043
        // (intrinsic_wo_chain:{ *:[v2i64] } 3137:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VQRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
23044
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv2i64),
23045
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
23046
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
23047
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
23048
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23049
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23050
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23051
0
        GIR_EraseFromParent, /*InsnID*/0,
23052
        // GIR_Coverage, 1469,
23053
0
        GIR_Done,
23054
      // Label 1275: @71614
23055
0
      GIM_Try, /*On fail goto*//*Label 1276*/ GIMT_Encode4(71675), // Rule ID 1734 //
23056
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8),
23057
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesd),
23058
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
23059
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
23060
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
23061
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23062
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23063
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23064
        // (intrinsic_wo_chain:{ *:[v16i8] } 3038:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)  =>  (AESD:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)
23065
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::AESD),
23066
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
23067
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
23068
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
23069
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23070
0
        GIR_EraseFromParent, /*InsnID*/0,
23071
        // GIR_Coverage, 1734,
23072
0
        GIR_Done,
23073
      // Label 1276: @71675
23074
0
      GIM_Try, /*On fail goto*//*Label 1277*/ GIMT_Encode4(71736), // Rule ID 1735 //
23075
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8),
23076
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aese),
23077
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
23078
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
23079
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
23080
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23081
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23082
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23083
        // (intrinsic_wo_chain:{ *:[v16i8] } 3039:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)  =>  (AESE:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)
23084
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::AESE),
23085
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
23086
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
23087
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
23088
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23089
0
        GIR_EraseFromParent, /*InsnID*/0,
23090
        // GIR_Coverage, 1735,
23091
0
        GIR_Done,
23092
      // Label 1277: @71736
23093
0
      GIM_Try, /*On fail goto*//*Label 1278*/ GIMT_Encode4(71797), // Rule ID 1738 //
23094
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8),
23095
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1su1),
23096
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23097
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23098
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23099
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23100
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23101
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23102
        // (intrinsic_wo_chain:{ *:[v4i32] } 3052:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA1SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)
23103
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SHA1SU1),
23104
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
23105
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
23106
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
23107
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23108
0
        GIR_EraseFromParent, /*InsnID*/0,
23109
        // GIR_Coverage, 1738,
23110
0
        GIR_Done,
23111
      // Label 1278: @71797
23112
0
      GIM_Try, /*On fail goto*//*Label 1279*/ GIMT_Encode4(71858), // Rule ID 1739 //
23113
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8),
23114
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256su0),
23115
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23116
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23117
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23118
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23119
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23120
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23121
        // (intrinsic_wo_chain:{ *:[v4i32] } 3055:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA256SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)
23122
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SHA256SU0),
23123
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
23124
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
23125
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
23126
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23127
0
        GIR_EraseFromParent, /*InsnID*/0,
23128
        // GIR_Coverage, 1739,
23129
0
        GIR_Done,
23130
      // Label 1279: @71858
23131
0
      GIM_Try, /*On fail goto*//*Label 1280*/ GIMT_Encode4(71928), // Rule ID 1753 //
23132
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline),
23133
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_sqrshr),
23134
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23135
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23136
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23137
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23138
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23139
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23140
        // (intrinsic_wo_chain:{ *:[i32] } 2900:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm)  =>  (MVE_SQRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm)
23141
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_SQRSHR),
23142
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
23143
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
23144
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23145
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23146
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23147
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23148
0
        GIR_EraseFromParent, /*InsnID*/0,
23149
        // GIR_Coverage, 1753,
23150
0
        GIR_Done,
23151
      // Label 1280: @71928
23152
0
      GIM_Try, /*On fail goto*//*Label 1281*/ GIMT_Encode4(71998), // Rule ID 1754 //
23153
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline),
23154
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_uqrshl),
23155
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23156
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23157
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23158
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23159
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23160
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23161
        // (intrinsic_wo_chain:{ *:[i32] } 2907:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm)  =>  (MVE_UQRSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm)
23162
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_UQRSHL),
23163
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
23164
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
23165
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23166
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23167
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23168
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23169
0
        GIR_EraseFromParent, /*InsnID*/0,
23170
        // GIR_Coverage, 1754,
23171
0
        GIR_Done,
23172
      // Label 1281: @71998
23173
0
      GIM_Try, /*On fail goto*//*Label 1282*/ GIMT_Encode4(72071), // Rule ID 1877 //
23174
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
23175
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtab16),
23176
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23177
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23178
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23179
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23180
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23181
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23182
        // (intrinsic_wo_chain:{ *:[i32] } 3239:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS)  =>  (SXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] })
23183
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SXTAB16),
23184
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
23185
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS
23186
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // RHS
23187
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23188
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23189
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23190
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23191
0
        GIR_EraseFromParent, /*InsnID*/0,
23192
        // GIR_Coverage, 1877,
23193
0
        GIR_Done,
23194
      // Label 1282: @72071
23195
0
      GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(72144), // Rule ID 1884 //
23196
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
23197
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtab16),
23198
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23199
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23200
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23201
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23202
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23203
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23204
        // (intrinsic_wo_chain:{ *:[i32] } 3264:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS)  =>  (UXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] })
23205
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UXTAB16),
23206
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
23207
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS
23208
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // RHS
23209
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23210
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23211
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23212
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23213
0
        GIR_EraseFromParent, /*InsnID*/0,
23214
        // GIR_Coverage, 1884,
23215
0
        GIR_Done,
23216
      // Label 1283: @72144
23217
0
      GIM_Try, /*On fail goto*//*Label 1284*/ GIMT_Encode4(72214), // Rule ID 1935 //
23218
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
23219
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuad),
23220
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23221
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23222
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23223
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23224
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23225
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23226
        // (intrinsic_wo_chain:{ *:[i32] } 3215:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SMUAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
23227
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMUAD),
23228
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
23229
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23230
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23231
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23232
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23233
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23234
0
        GIR_EraseFromParent, /*InsnID*/0,
23235
        // GIR_Coverage, 1935,
23236
0
        GIR_Done,
23237
      // Label 1284: @72214
23238
0
      GIM_Try, /*On fail goto*//*Label 1285*/ GIMT_Encode4(72284), // Rule ID 1936 //
23239
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
23240
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuadx),
23241
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23242
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23243
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23244
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23245
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23246
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23247
        // (intrinsic_wo_chain:{ *:[i32] } 3216:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SMUADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
23248
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMUADX),
23249
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
23250
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23251
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23252
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23253
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23254
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23255
0
        GIR_EraseFromParent, /*InsnID*/0,
23256
        // GIR_Coverage, 1936,
23257
0
        GIR_Done,
23258
      // Label 1285: @72284
23259
0
      GIM_Try, /*On fail goto*//*Label 1286*/ GIMT_Encode4(72354), // Rule ID 1937 //
23260
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
23261
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusd),
23262
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23263
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23264
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23265
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23266
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23267
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23268
        // (intrinsic_wo_chain:{ *:[i32] } 3223:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SMUSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
23269
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMUSD),
23270
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
23271
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23272
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23273
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23274
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23275
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23276
0
        GIR_EraseFromParent, /*InsnID*/0,
23277
        // GIR_Coverage, 1937,
23278
0
        GIR_Done,
23279
      // Label 1286: @72354
23280
0
      GIM_Try, /*On fail goto*//*Label 1287*/ GIMT_Encode4(72424), // Rule ID 1938 //
23281
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
23282
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusdx),
23283
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23284
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23285
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23286
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23287
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23288
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23289
        // (intrinsic_wo_chain:{ *:[i32] } 3224:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SMUSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
23290
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMUSDX),
23291
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
23292
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23293
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23294
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23295
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23296
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23297
0
        GIR_EraseFromParent, /*InsnID*/0,
23298
        // GIR_Coverage, 1938,
23299
0
        GIR_Done,
23300
      // Label 1287: @72424
23301
0
      GIM_Try, /*On fail goto*//*Label 1288*/ GIMT_Encode4(72494), // Rule ID 2002 //
23302
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
23303
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbb),
23304
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23305
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23306
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23307
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23308
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23309
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23310
        // (intrinsic_wo_chain:{ *:[i32] } 3217:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULBB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23311
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMULBB),
23312
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
23313
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23314
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23315
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23316
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23317
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23318
0
        GIR_EraseFromParent, /*InsnID*/0,
23319
        // GIR_Coverage, 2002,
23320
0
        GIR_Done,
23321
      // Label 1288: @72494
23322
0
      GIM_Try, /*On fail goto*//*Label 1289*/ GIMT_Encode4(72564), // Rule ID 2003 //
23323
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
23324
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbt),
23325
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23326
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23327
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23328
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23329
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23330
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23331
        // (intrinsic_wo_chain:{ *:[i32] } 3218:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULBT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23332
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMULBT),
23333
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
23334
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23335
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23336
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23337
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23338
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23339
0
        GIR_EraseFromParent, /*InsnID*/0,
23340
        // GIR_Coverage, 2003,
23341
0
        GIR_Done,
23342
      // Label 1289: @72564
23343
0
      GIM_Try, /*On fail goto*//*Label 1290*/ GIMT_Encode4(72634), // Rule ID 2004 //
23344
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
23345
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultb),
23346
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23347
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23348
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23349
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23350
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23351
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23352
        // (intrinsic_wo_chain:{ *:[i32] } 3219:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULTB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23353
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMULTB),
23354
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
23355
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23356
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23357
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23358
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23359
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23360
0
        GIR_EraseFromParent, /*InsnID*/0,
23361
        // GIR_Coverage, 2004,
23362
0
        GIR_Done,
23363
      // Label 1290: @72634
23364
0
      GIM_Try, /*On fail goto*//*Label 1291*/ GIMT_Encode4(72704), // Rule ID 2005 //
23365
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
23366
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultt),
23367
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23368
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23369
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23370
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23371
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23372
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23373
        // (intrinsic_wo_chain:{ *:[i32] } 3220:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23374
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMULTT),
23375
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
23376
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23377
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23378
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23379
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23380
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23381
0
        GIR_EraseFromParent, /*InsnID*/0,
23382
        // GIR_Coverage, 2005,
23383
0
        GIR_Done,
23384
      // Label 1291: @72704
23385
0
      GIM_Try, /*On fail goto*//*Label 1292*/ GIMT_Encode4(72774), // Rule ID 2006 //
23386
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
23387
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwb),
23388
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23389
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23390
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23391
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23392
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23393
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23394
        // (intrinsic_wo_chain:{ *:[i32] } 3221:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23395
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMULWB),
23396
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
23397
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23398
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23399
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23400
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23401
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23402
0
        GIR_EraseFromParent, /*InsnID*/0,
23403
        // GIR_Coverage, 2006,
23404
0
        GIR_Done,
23405
      // Label 1292: @72774
23406
0
      GIM_Try, /*On fail goto*//*Label 1293*/ GIMT_Encode4(72844), // Rule ID 2007 //
23407
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
23408
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwt),
23409
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23410
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23411
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23412
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23413
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23414
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23415
        // (intrinsic_wo_chain:{ *:[i32] } 3222:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23416
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMULWT),
23417
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
23418
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23419
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23420
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23421
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23422
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23423
0
        GIR_EraseFromParent, /*InsnID*/0,
23424
        // GIR_Coverage, 2007,
23425
0
        GIR_Done,
23426
      // Label 1293: @72844
23427
0
      GIM_Try, /*On fail goto*//*Label 1294*/ GIMT_Encode4(72917), // Rule ID 2113 //
23428
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
23429
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtab16),
23430
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23431
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23432
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23433
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23434
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23435
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23436
        // (intrinsic_wo_chain:{ *:[i32] } 3239:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
23437
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB16),
23438
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
23439
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23440
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23441
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23442
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23443
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23444
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23445
0
        GIR_EraseFromParent, /*InsnID*/0,
23446
        // GIR_Coverage, 2113,
23447
0
        GIR_Done,
23448
      // Label 1294: @72917
23449
0
      GIM_Try, /*On fail goto*//*Label 1295*/ GIMT_Encode4(72987), // Rule ID 2146 //
23450
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
23451
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
23452
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23453
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23454
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23455
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23456
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23457
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23458
        // (intrinsic_wo_chain:{ *:[i32] } 3182:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)  =>  (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
23459
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2QADD),
23460
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
23461
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
23462
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
23463
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23464
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23465
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23466
0
        GIR_EraseFromParent, /*InsnID*/0,
23467
        // GIR_Coverage, 2146,
23468
0
        GIR_Done,
23469
      // Label 1295: @72987
23470
0
      GIM_Try, /*On fail goto*//*Label 1296*/ GIMT_Encode4(73057), // Rule ID 2147 //
23471
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
23472
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub),
23473
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23474
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23475
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23476
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23477
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23478
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23479
        // (intrinsic_wo_chain:{ *:[i32] } 3187:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)  =>  (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
23480
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2QSUB),
23481
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
23482
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
23483
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
23484
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23485
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23486
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23487
0
        GIR_EraseFromParent, /*InsnID*/0,
23488
        // GIR_Coverage, 2147,
23489
0
        GIR_Done,
23490
      // Label 1296: @73057
23491
0
      GIM_Try, /*On fail goto*//*Label 1297*/ GIMT_Encode4(73127), // Rule ID 2187 //
23492
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
23493
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbb),
23494
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23495
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23496
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23497
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23498
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23499
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23500
        // (intrinsic_wo_chain:{ *:[i32] } 3217:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULBB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23501
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMULBB),
23502
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
23503
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23504
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23505
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23506
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23507
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23508
0
        GIR_EraseFromParent, /*InsnID*/0,
23509
        // GIR_Coverage, 2187,
23510
0
        GIR_Done,
23511
      // Label 1297: @73127
23512
0
      GIM_Try, /*On fail goto*//*Label 1298*/ GIMT_Encode4(73197), // Rule ID 2188 //
23513
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
23514
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbt),
23515
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23516
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23517
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23518
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23519
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23520
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23521
        // (intrinsic_wo_chain:{ *:[i32] } 3218:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23522
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMULBT),
23523
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
23524
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23525
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23526
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23527
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23528
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23529
0
        GIR_EraseFromParent, /*InsnID*/0,
23530
        // GIR_Coverage, 2188,
23531
0
        GIR_Done,
23532
      // Label 1298: @73197
23533
0
      GIM_Try, /*On fail goto*//*Label 1299*/ GIMT_Encode4(73267), // Rule ID 2189 //
23534
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
23535
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultb),
23536
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23537
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23538
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23539
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23540
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23541
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23542
        // (intrinsic_wo_chain:{ *:[i32] } 3219:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23543
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMULTB),
23544
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
23545
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23546
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23547
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23548
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23549
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23550
0
        GIR_EraseFromParent, /*InsnID*/0,
23551
        // GIR_Coverage, 2189,
23552
0
        GIR_Done,
23553
      // Label 1299: @73267
23554
0
      GIM_Try, /*On fail goto*//*Label 1300*/ GIMT_Encode4(73337), // Rule ID 2190 //
23555
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
23556
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultt),
23557
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23558
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23559
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23560
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23561
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23562
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23563
        // (intrinsic_wo_chain:{ *:[i32] } 3220:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23564
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMULTT),
23565
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
23566
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23567
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23568
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23569
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23570
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23571
0
        GIR_EraseFromParent, /*InsnID*/0,
23572
        // GIR_Coverage, 2190,
23573
0
        GIR_Done,
23574
      // Label 1300: @73337
23575
0
      GIM_Try, /*On fail goto*//*Label 1301*/ GIMT_Encode4(73407), // Rule ID 2191 //
23576
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
23577
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwb),
23578
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23579
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23580
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23581
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23582
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23583
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23584
        // (intrinsic_wo_chain:{ *:[i32] } 3221:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULWB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23585
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMULWB),
23586
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
23587
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23588
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23589
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23590
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23591
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23592
0
        GIR_EraseFromParent, /*InsnID*/0,
23593
        // GIR_Coverage, 2191,
23594
0
        GIR_Done,
23595
      // Label 1301: @73407
23596
0
      GIM_Try, /*On fail goto*//*Label 1302*/ GIMT_Encode4(73477), // Rule ID 2192 //
23597
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
23598
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwt),
23599
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23600
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23601
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23602
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23603
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23604
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23605
        // (intrinsic_wo_chain:{ *:[i32] } 3222:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULWT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23606
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMULWT),
23607
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
23608
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23609
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23610
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23611
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23612
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23613
0
        GIR_EraseFromParent, /*InsnID*/0,
23614
        // GIR_Coverage, 2192,
23615
0
        GIR_Done,
23616
      // Label 1302: @73477
23617
0
      GIM_Try, /*On fail goto*//*Label 1303*/ GIMT_Encode4(73541), // Rule ID 2519 //
23618
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a),
23619
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90),
23620
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
23621
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
23622
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
23623
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23624
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23625
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23626
        // (intrinsic_wo_chain:{ *:[v4f16] } 3069:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm)  =>  (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 0:{ *:[i32] })
23627
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f16),
23628
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
23629
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23630
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23631
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23632
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23633
0
        GIR_EraseFromParent, /*InsnID*/0,
23634
        // GIR_Coverage, 2519,
23635
0
        GIR_Done,
23636
      // Label 1303: @73541
23637
0
      GIM_Try, /*On fail goto*//*Label 1304*/ GIMT_Encode4(73605), // Rule ID 2520 //
23638
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a),
23639
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270),
23640
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
23641
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
23642
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
23643
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23644
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23645
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23646
        // (intrinsic_wo_chain:{ *:[v4f16] } 3068:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm)  =>  (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 1:{ *:[i32] })
23647
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f16),
23648
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
23649
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23650
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23651
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
23652
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23653
0
        GIR_EraseFromParent, /*InsnID*/0,
23654
        // GIR_Coverage, 2520,
23655
0
        GIR_Done,
23656
      // Label 1304: @73605
23657
0
      GIM_Try, /*On fail goto*//*Label 1305*/ GIMT_Encode4(73669), // Rule ID 2521 //
23658
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a),
23659
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90),
23660
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
23661
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
23662
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
23663
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23664
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23665
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23666
        // (intrinsic_wo_chain:{ *:[v8f16] } 3069:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm)  =>  (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 0:{ *:[i32] })
23667
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCADDv8f16),
23668
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
23669
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23670
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23671
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23672
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23673
0
        GIR_EraseFromParent, /*InsnID*/0,
23674
        // GIR_Coverage, 2521,
23675
0
        GIR_Done,
23676
      // Label 1305: @73669
23677
0
      GIM_Try, /*On fail goto*//*Label 1306*/ GIMT_Encode4(73733), // Rule ID 2522 //
23678
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a),
23679
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270),
23680
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
23681
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
23682
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
23683
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23684
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23685
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23686
        // (intrinsic_wo_chain:{ *:[v8f16] } 3068:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm)  =>  (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 1:{ *:[i32] })
23687
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCADDv8f16),
23688
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
23689
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23690
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23691
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
23692
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23693
0
        GIR_EraseFromParent, /*InsnID*/0,
23694
        // GIR_Coverage, 2522,
23695
0
        GIR_Done,
23696
      // Label 1306: @73733
23697
0
      GIM_Try, /*On fail goto*//*Label 1307*/ GIMT_Encode4(73797), // Rule ID 2523 //
23698
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a),
23699
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90),
23700
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
23701
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
23702
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
23703
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23704
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23705
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23706
        // (intrinsic_wo_chain:{ *:[v2f32] } 3069:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm)  =>  (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 0:{ *:[i32] })
23707
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCADDv2f32),
23708
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
23709
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23710
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23711
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23712
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23713
0
        GIR_EraseFromParent, /*InsnID*/0,
23714
        // GIR_Coverage, 2523,
23715
0
        GIR_Done,
23716
      // Label 1307: @73797
23717
0
      GIM_Try, /*On fail goto*//*Label 1308*/ GIMT_Encode4(73861), // Rule ID 2524 //
23718
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a),
23719
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270),
23720
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
23721
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
23722
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
23723
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23724
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23725
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23726
        // (intrinsic_wo_chain:{ *:[v2f32] } 3068:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm)  =>  (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 1:{ *:[i32] })
23727
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCADDv2f32),
23728
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
23729
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23730
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23731
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
23732
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23733
0
        GIR_EraseFromParent, /*InsnID*/0,
23734
        // GIR_Coverage, 2524,
23735
0
        GIR_Done,
23736
      // Label 1308: @73861
23737
0
      GIM_Try, /*On fail goto*//*Label 1309*/ GIMT_Encode4(73925), // Rule ID 2525 //
23738
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a),
23739
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90),
23740
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23741
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23742
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23743
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23744
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23745
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23746
        // (intrinsic_wo_chain:{ *:[v4f32] } 3069:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm)  =>  (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 0:{ *:[i32] })
23747
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f32),
23748
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
23749
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23750
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23751
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23752
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23753
0
        GIR_EraseFromParent, /*InsnID*/0,
23754
        // GIR_Coverage, 2525,
23755
0
        GIR_Done,
23756
      // Label 1309: @73925
23757
0
      GIM_Try, /*On fail goto*//*Label 1310*/ GIMT_Encode4(73989), // Rule ID 2526 //
23758
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a),
23759
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270),
23760
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23761
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23762
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23763
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23764
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23765
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23766
        // (intrinsic_wo_chain:{ *:[v4f32] } 3068:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm)  =>  (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 1:{ *:[i32] })
23767
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f32),
23768
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
23769
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23770
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23771
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
23772
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23773
0
        GIR_EraseFromParent, /*InsnID*/0,
23774
        // GIR_Coverage, 2526,
23775
0
        GIR_Done,
23776
      // Label 1310: @73989
23777
0
      GIM_Try, /*On fail goto*//*Label 1311*/ GIMT_Encode4(74102), // Rule ID 3211 //
23778
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
23779
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmv),
23780
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23781
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23782
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23783
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23784
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23785
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23786
        // (intrinsic_wo_chain:{ *:[f32] } 2876:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec)  =>  (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
23787
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23788
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23789
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23790
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23791
0
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23792
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
23793
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMVf32),
23794
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23795
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23796
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23797
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
23798
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23799
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23800
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23801
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23802
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
23803
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23804
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
23805
0
        GIR_EraseFromParent, /*InsnID*/0,
23806
        // GIR_Coverage, 3211,
23807
0
        GIR_Done,
23808
      // Label 1311: @74102
23809
0
      GIM_Try, /*On fail goto*//*Label 1312*/ GIMT_Encode4(74215), // Rule ID 3213 //
23810
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
23811
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmv),
23812
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
23813
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
23814
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
23815
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
23816
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
23817
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23818
        // (intrinsic_wo_chain:{ *:[f16] } 2876:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec)  =>  (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
23819
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23820
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23821
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23822
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23823
0
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23824
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
23825
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMVf16),
23826
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23827
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23828
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23829
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
23830
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23831
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23832
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23833
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23834
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
23835
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23836
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
23837
0
        GIR_EraseFromParent, /*InsnID*/0,
23838
        // GIR_Coverage, 3213,
23839
0
        GIR_Done,
23840
      // Label 1312: @74215
23841
0
      GIM_Try, /*On fail goto*//*Label 1313*/ GIMT_Encode4(74328), // Rule ID 3215 //
23842
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
23843
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmv),
23844
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23845
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23846
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23847
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23848
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23849
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23850
        // (intrinsic_wo_chain:{ *:[f32] } 2867:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec)  =>  (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
23851
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23852
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23853
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23854
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23855
0
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23856
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
23857
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMVf32),
23858
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23859
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23860
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23861
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
23862
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23863
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23864
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23865
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23866
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
23867
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23868
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
23869
0
        GIR_EraseFromParent, /*InsnID*/0,
23870
        // GIR_Coverage, 3215,
23871
0
        GIR_Done,
23872
      // Label 1313: @74328
23873
0
      GIM_Try, /*On fail goto*//*Label 1314*/ GIMT_Encode4(74441), // Rule ID 3217 //
23874
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
23875
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmv),
23876
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
23877
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
23878
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
23879
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
23880
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
23881
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23882
        // (intrinsic_wo_chain:{ *:[f16] } 2867:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec)  =>  (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
23883
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23884
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23885
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23886
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23887
0
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23888
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
23889
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMVf16),
23890
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23891
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23892
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23893
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
23894
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23895
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23896
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23897
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23898
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
23899
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23900
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
23901
0
        GIR_EraseFromParent, /*InsnID*/0,
23902
        // GIR_Coverage, 3217,
23903
0
        GIR_Done,
23904
      // Label 1314: @74441
23905
0
      GIM_Try, /*On fail goto*//*Label 1315*/ GIMT_Encode4(74554), // Rule ID 3219 //
23906
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
23907
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmav),
23908
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23909
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23910
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23911
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23912
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23913
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23914
        // (intrinsic_wo_chain:{ *:[f32] } 2874:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec)  =>  (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
23915
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23916
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23917
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23918
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23919
0
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23920
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
23921
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAVf32),
23922
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23923
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23924
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23925
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
23926
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23927
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23928
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23929
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23930
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
23931
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23932
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
23933
0
        GIR_EraseFromParent, /*InsnID*/0,
23934
        // GIR_Coverage, 3219,
23935
0
        GIR_Done,
23936
      // Label 1315: @74554
23937
0
      GIM_Try, /*On fail goto*//*Label 1316*/ GIMT_Encode4(74667), // Rule ID 3221 //
23938
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
23939
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmav),
23940
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
23941
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
23942
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
23943
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
23944
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
23945
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23946
        // (intrinsic_wo_chain:{ *:[f16] } 2874:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec)  =>  (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
23947
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23948
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23949
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23950
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23951
0
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23952
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
23953
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAVf16),
23954
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23955
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23956
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23957
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
23958
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23959
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23960
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23961
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23962
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
23963
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23964
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
23965
0
        GIR_EraseFromParent, /*InsnID*/0,
23966
        // GIR_Coverage, 3221,
23967
0
        GIR_Done,
23968
      // Label 1316: @74667
23969
0
      GIM_Try, /*On fail goto*//*Label 1317*/ GIMT_Encode4(74780), // Rule ID 3223 //
23970
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
23971
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmav),
23972
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23973
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23974
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23975
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23976
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23977
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23978
        // (intrinsic_wo_chain:{ *:[f32] } 2865:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec)  =>  (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
23979
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23980
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23981
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23982
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23983
0
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23984
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
23985
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAVf32),
23986
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23987
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23988
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23989
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
23990
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23991
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23992
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23993
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23994
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
23995
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23996
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
23997
0
        GIR_EraseFromParent, /*InsnID*/0,
23998
        // GIR_Coverage, 3223,
23999
0
        GIR_Done,
24000
      // Label 1317: @74780
24001
0
      GIM_Try, /*On fail goto*//*Label 1318*/ GIMT_Encode4(74893), // Rule ID 3225 //
24002
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24003
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmav),
24004
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
24005
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
24006
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24007
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
24008
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
24009
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24010
        // (intrinsic_wo_chain:{ *:[f16] } 2865:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec)  =>  (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
24011
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24012
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
24013
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24014
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24015
0
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
24016
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
24017
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAVf16),
24018
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24019
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
24020
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
24021
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
24022
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24023
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24024
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24025
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24026
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
24027
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24028
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
24029
0
        GIR_EraseFromParent, /*InsnID*/0,
24030
        // GIR_Coverage, 3225,
24031
0
        GIR_Done,
24032
      // Label 1318: @74893
24033
0
      GIM_Try, /*On fail goto*//*Label 1319*/ GIMT_Encode4(74969), // Rule ID 3275 //
24034
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24035
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minav),
24036
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24037
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24038
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
24039
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24040
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24041
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24042
        // (intrinsic_wo_chain:{ *:[i32] } 2872:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)  =>  (MVE_VMINAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
24043
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs8),
24044
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
24045
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24046
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24047
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24048
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24049
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24050
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24051
0
        GIR_EraseFromParent, /*InsnID*/0,
24052
        // GIR_Coverage, 3275,
24053
0
        GIR_Done,
24054
      // Label 1319: @74969
24055
0
      GIM_Try, /*On fail goto*//*Label 1320*/ GIMT_Encode4(75045), // Rule ID 3277 //
24056
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24057
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minav),
24058
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24059
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24060
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24061
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24062
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24063
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24064
        // (intrinsic_wo_chain:{ *:[i32] } 2872:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)  =>  (MVE_VMINAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
24065
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs16),
24066
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
24067
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24068
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24069
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24070
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24071
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24072
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24073
0
        GIR_EraseFromParent, /*InsnID*/0,
24074
        // GIR_Coverage, 3277,
24075
0
        GIR_Done,
24076
      // Label 1320: @75045
24077
0
      GIM_Try, /*On fail goto*//*Label 1321*/ GIMT_Encode4(75121), // Rule ID 3279 //
24078
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24079
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minav),
24080
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24081
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24082
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24083
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24084
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24085
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24086
        // (intrinsic_wo_chain:{ *:[i32] } 2872:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)  =>  (MVE_VMINAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
24087
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs32),
24088
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
24089
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24090
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24091
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24092
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24093
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24094
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24095
0
        GIR_EraseFromParent, /*InsnID*/0,
24096
        // GIR_Coverage, 3279,
24097
0
        GIR_Done,
24098
      // Label 1321: @75121
24099
0
      GIM_Try, /*On fail goto*//*Label 1322*/ GIMT_Encode4(75197), // Rule ID 3281 //
24100
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24101
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxav),
24102
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24103
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24104
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
24105
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24106
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24107
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24108
        // (intrinsic_wo_chain:{ *:[i32] } 2863:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)  =>  (MVE_VMAXAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
24109
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs8),
24110
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
24111
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24112
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24113
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24114
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24115
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24116
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24117
0
        GIR_EraseFromParent, /*InsnID*/0,
24118
        // GIR_Coverage, 3281,
24119
0
        GIR_Done,
24120
      // Label 1322: @75197
24121
0
      GIM_Try, /*On fail goto*//*Label 1323*/ GIMT_Encode4(75273), // Rule ID 3283 //
24122
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24123
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxav),
24124
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24125
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24126
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24127
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24128
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24129
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24130
        // (intrinsic_wo_chain:{ *:[i32] } 2863:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)  =>  (MVE_VMAXAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
24131
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs16),
24132
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
24133
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24134
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24135
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24136
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24137
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24138
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24139
0
        GIR_EraseFromParent, /*InsnID*/0,
24140
        // GIR_Coverage, 3283,
24141
0
        GIR_Done,
24142
      // Label 1323: @75273
24143
0
      GIM_Try, /*On fail goto*//*Label 1324*/ GIMT_Encode4(75349), // Rule ID 3285 //
24144
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24145
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxav),
24146
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24147
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24148
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24149
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24150
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24151
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24152
        // (intrinsic_wo_chain:{ *:[i32] } 2863:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)  =>  (MVE_VMAXAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
24153
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs32),
24154
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
24155
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24156
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24157
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24158
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24159
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24160
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24161
0
        GIR_EraseFromParent, /*InsnID*/0,
24162
        // GIR_Coverage, 3285,
24163
0
        GIR_Done,
24164
      // Label 1324: @75349
24165
0
      GIM_Try, /*On fail goto*//*Label 1325*/ GIMT_Encode4(75438), // Rule ID 3576 //
24166
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24167
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmulh),
24168
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
24169
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24170
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
24171
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24172
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24173
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24174
        // (intrinsic_wo_chain:{ *:[v16i8] } 2985:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VQDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
24175
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24176
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24177
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24178
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi8),
24179
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24180
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24181
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24182
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24183
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24184
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24185
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24186
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24187
0
        GIR_EraseFromParent, /*InsnID*/0,
24188
        // GIR_Coverage, 3576,
24189
0
        GIR_Done,
24190
      // Label 1325: @75438
24191
0
      GIM_Try, /*On fail goto*//*Label 1326*/ GIMT_Encode4(75527), // Rule ID 3583 //
24192
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24193
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmulh),
24194
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24195
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24196
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24197
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24198
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24199
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24200
        // (intrinsic_wo_chain:{ *:[v8i16] } 2985:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VQDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
24201
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24202
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24203
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24204
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi16),
24205
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24206
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24207
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24208
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24209
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24210
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24211
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24212
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24213
0
        GIR_EraseFromParent, /*InsnID*/0,
24214
        // GIR_Coverage, 3583,
24215
0
        GIR_Done,
24216
      // Label 1326: @75527
24217
0
      GIM_Try, /*On fail goto*//*Label 1327*/ GIMT_Encode4(75616), // Rule ID 3587 //
24218
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24219
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmulh),
24220
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24221
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24222
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24223
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24224
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24225
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24226
        // (intrinsic_wo_chain:{ *:[v4i32] } 2985:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VQDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
24227
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24228
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24229
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24230
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi32),
24231
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24232
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24233
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24234
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24235
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24236
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24237
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24238
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24239
0
        GIR_EraseFromParent, /*InsnID*/0,
24240
        // GIR_Coverage, 3587,
24241
0
        GIR_Done,
24242
      // Label 1327: @75616
24243
0
      GIM_Try, /*On fail goto*//*Label 1328*/ GIMT_Encode4(75705), // Rule ID 3589 //
24244
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24245
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmulh),
24246
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
24247
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24248
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
24249
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24250
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24251
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24252
        // (intrinsic_wo_chain:{ *:[v16i8] } 2994:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VQRDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
24253
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24254
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24255
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24256
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi8),
24257
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24258
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24259
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24260
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24261
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24262
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24263
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24264
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24265
0
        GIR_EraseFromParent, /*InsnID*/0,
24266
        // GIR_Coverage, 3589,
24267
0
        GIR_Done,
24268
      // Label 1328: @75705
24269
0
      GIM_Try, /*On fail goto*//*Label 1329*/ GIMT_Encode4(75794), // Rule ID 3591 //
24270
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24271
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmulh),
24272
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24273
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24274
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24275
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24276
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24277
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24278
        // (intrinsic_wo_chain:{ *:[v8i16] } 2994:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VQRDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
24279
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24280
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24281
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24282
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi16),
24283
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24284
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24285
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24286
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24287
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24288
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24289
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24290
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24291
0
        GIR_EraseFromParent, /*InsnID*/0,
24292
        // GIR_Coverage, 3591,
24293
0
        GIR_Done,
24294
      // Label 1329: @75794
24295
0
      GIM_Try, /*On fail goto*//*Label 1330*/ GIMT_Encode4(75883), // Rule ID 3593 //
24296
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24297
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmulh),
24298
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24299
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24300
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24301
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24302
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24303
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24304
        // (intrinsic_wo_chain:{ *:[v4i32] } 2994:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VQRDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
24305
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24306
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24307
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24308
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi32),
24309
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24310
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24311
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24312
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24313
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24314
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24315
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24316
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24317
0
        GIR_EraseFromParent, /*InsnID*/0,
24318
        // GIR_Coverage, 3593,
24319
0
        GIR_Done,
24320
      // Label 1330: @75883
24321
0
      GIM_Try, /*On fail goto*//*Label 1331*/ GIMT_Encode4(75972), // Rule ID 4879 //
24322
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24323
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr),
24324
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
24325
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24326
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24327
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24328
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24329
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24330
        // (intrinsic_wo_chain:{ *:[v16i8] } 2918:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm)  =>  (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm)
24331
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24332
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24333
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24334
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR8),
24335
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24336
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
24337
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
24338
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24339
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24340
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24341
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24342
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24343
0
        GIR_EraseFromParent, /*InsnID*/0,
24344
        // GIR_Coverage, 4879,
24345
0
        GIR_Done,
24346
      // Label 1331: @75972
24347
0
      GIM_Try, /*On fail goto*//*Label 1332*/ GIMT_Encode4(76061), // Rule ID 4884 //
24348
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24349
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr),
24350
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24351
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24352
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24353
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24354
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24355
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24356
        // (intrinsic_wo_chain:{ *:[v8i16] } 2918:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm)  =>  (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm)
24357
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24358
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24359
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24360
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16),
24361
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24362
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
24363
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
24364
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24365
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24366
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24367
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24368
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24369
0
        GIR_EraseFromParent, /*InsnID*/0,
24370
        // GIR_Coverage, 4884,
24371
0
        GIR_Done,
24372
      // Label 1332: @76061
24373
0
      GIM_Try, /*On fail goto*//*Label 1333*/ GIMT_Encode4(76150), // Rule ID 4886 //
24374
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24375
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr),
24376
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24377
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24378
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24379
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24380
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24381
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24382
        // (intrinsic_wo_chain:{ *:[v4i32] } 2918:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm)  =>  (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm)
24383
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24384
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24385
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24386
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32),
24387
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24388
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
24389
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
24390
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24391
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24392
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24393
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24394
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24395
0
        GIR_EraseFromParent, /*InsnID*/0,
24396
        // GIR_Coverage, 4886,
24397
0
        GIR_Done,
24398
      // Label 1333: @76150
24399
0
      GIM_Try, /*On fail goto*//*Label 1334*/ GIMT_Encode4(76239), // Rule ID 4888 //
24400
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24401
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr),
24402
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24403
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24404
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24405
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24406
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24407
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24408
        // (intrinsic_wo_chain:{ *:[v8f16] } 2918:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm)  =>  (MVE_VBRSR16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm)
24409
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24410
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24411
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24412
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16),
24413
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24414
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
24415
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
24416
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24417
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24418
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24419
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24420
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24421
0
        GIR_EraseFromParent, /*InsnID*/0,
24422
        // GIR_Coverage, 4888,
24423
0
        GIR_Done,
24424
      // Label 1334: @76239
24425
0
      GIM_Try, /*On fail goto*//*Label 1335*/ GIMT_Encode4(76328), // Rule ID 4890 //
24426
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24427
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr),
24428
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24429
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24430
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24431
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24432
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24433
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24434
        // (intrinsic_wo_chain:{ *:[v4f32] } 2918:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm)  =>  (MVE_VBRSR32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm)
24435
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24436
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24437
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24438
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32),
24439
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24440
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
24441
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
24442
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24443
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24444
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24445
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24446
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24447
0
        GIR_EraseFromParent, /*InsnID*/0,
24448
        // GIR_Coverage, 4890,
24449
0
        GIR_Done,
24450
      // Label 1335: @76328
24451
0
      GIM_Reject,
24452
    // Label 968: @76329
24453
0
    GIM_Try, /*On fail goto*//*Label 1336*/ GIMT_Encode4(90908),
24454
0
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
24455
0
      GIM_Try, /*On fail goto*//*Label 1337*/ GIMT_Encode4(76439), // Rule ID 4040 //
24456
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm),
24457
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
24458
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24459
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24460
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24461
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24462
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24463
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24464
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24465
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
24466
        // MIs[1] Operand 1
24467
        // No operand predicates
24468
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
24469
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
24470
        // (intrinsic_wo_chain:{ *:[v16i8] } 2995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 0:{ *:[i32] })  =>  (MVE_VQSHLimms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
24471
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24472
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24473
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24474
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms8),
24475
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24476
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24477
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24478
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24479
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24480
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24481
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24482
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24483
0
        GIR_EraseFromParent, /*InsnID*/0,
24484
        // GIR_Coverage, 4040,
24485
0
        GIR_Done,
24486
      // Label 1337: @76439
24487
0
      GIM_Try, /*On fail goto*//*Label 1338*/ GIMT_Encode4(76541), // Rule ID 4042 //
24488
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm),
24489
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
24490
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24491
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24492
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24493
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24494
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24495
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24496
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24497
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
24498
        // MIs[1] Operand 1
24499
        // No operand predicates
24500
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
24501
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
24502
        // (intrinsic_wo_chain:{ *:[v16i8] } 2995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 1:{ *:[i32] })  =>  (MVE_VQSHLimmu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
24503
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24504
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24505
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24506
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu8),
24507
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24508
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24509
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24510
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24511
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24512
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24513
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24514
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24515
0
        GIR_EraseFromParent, /*InsnID*/0,
24516
        // GIR_Coverage, 4042,
24517
0
        GIR_Done,
24518
      // Label 1338: @76541
24519
0
      GIM_Try, /*On fail goto*//*Label 1339*/ GIMT_Encode4(76643), // Rule ID 4044 //
24520
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm),
24521
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24522
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24523
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24524
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24525
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24526
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24527
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24528
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24529
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
24530
        // MIs[1] Operand 1
24531
        // No operand predicates
24532
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
24533
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
24534
        // (intrinsic_wo_chain:{ *:[v8i16] } 2995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 0:{ *:[i32] })  =>  (MVE_VQSHLimms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
24535
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24536
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24537
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24538
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms16),
24539
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24540
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24541
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24542
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24543
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24544
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24545
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24546
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24547
0
        GIR_EraseFromParent, /*InsnID*/0,
24548
        // GIR_Coverage, 4044,
24549
0
        GIR_Done,
24550
      // Label 1339: @76643
24551
0
      GIM_Try, /*On fail goto*//*Label 1340*/ GIMT_Encode4(76745), // Rule ID 4046 //
24552
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm),
24553
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24554
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24555
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24556
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24557
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24558
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24559
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24560
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24561
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
24562
        // MIs[1] Operand 1
24563
        // No operand predicates
24564
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
24565
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
24566
        // (intrinsic_wo_chain:{ *:[v8i16] } 2995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 1:{ *:[i32] })  =>  (MVE_VQSHLimmu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
24567
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24568
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24569
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24570
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu16),
24571
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24572
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24573
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24574
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24575
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24576
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24577
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24578
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24579
0
        GIR_EraseFromParent, /*InsnID*/0,
24580
        // GIR_Coverage, 4046,
24581
0
        GIR_Done,
24582
      // Label 1340: @76745
24583
0
      GIM_Try, /*On fail goto*//*Label 1341*/ GIMT_Encode4(76847), // Rule ID 4048 //
24584
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm),
24585
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24586
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24587
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24588
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24589
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24590
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24591
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24592
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24593
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
24594
        // MIs[1] Operand 1
24595
        // No operand predicates
24596
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
24597
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
24598
        // (intrinsic_wo_chain:{ *:[v4i32] } 2995:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 0:{ *:[i32] })  =>  (MVE_VQSHLimms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
24599
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24600
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24601
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24602
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms32),
24603
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24604
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24605
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24606
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24607
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24608
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24609
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24610
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24611
0
        GIR_EraseFromParent, /*InsnID*/0,
24612
        // GIR_Coverage, 4048,
24613
0
        GIR_Done,
24614
      // Label 1341: @76847
24615
0
      GIM_Try, /*On fail goto*//*Label 1342*/ GIMT_Encode4(76949), // Rule ID 4050 //
24616
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm),
24617
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24618
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24619
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24620
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24621
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24622
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24623
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24624
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24625
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
24626
        // MIs[1] Operand 1
24627
        // No operand predicates
24628
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
24629
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
24630
        // (intrinsic_wo_chain:{ *:[v4i32] } 2995:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 1:{ *:[i32] })  =>  (MVE_VQSHLimmu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
24631
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24632
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24633
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24634
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu32),
24635
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24636
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24637
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24638
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24639
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24640
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24641
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24642
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24643
0
        GIR_EraseFromParent, /*InsnID*/0,
24644
        // GIR_Coverage, 4050,
24645
0
        GIR_Done,
24646
      // Label 1342: @76949
24647
0
      GIM_Try, /*On fail goto*//*Label 1343*/ GIMT_Encode4(77051), // Rule ID 4058 //
24648
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm),
24649
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
24650
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24651
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24652
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24653
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24654
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24655
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24656
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24657
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
24658
        // MIs[1] Operand 1
24659
        // No operand predicates
24660
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
24661
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
24662
        // (intrinsic_wo_chain:{ *:[v16i8] } 3012:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] })  =>  (MVE_VRSHR_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)
24663
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24664
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24665
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24666
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms8),
24667
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24668
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24669
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24670
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24671
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24672
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24673
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24674
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24675
0
        GIR_EraseFromParent, /*InsnID*/0,
24676
        // GIR_Coverage, 4058,
24677
0
        GIR_Done,
24678
      // Label 1343: @77051
24679
0
      GIM_Try, /*On fail goto*//*Label 1344*/ GIMT_Encode4(77153), // Rule ID 4060 //
24680
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm),
24681
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
24682
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24683
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24684
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24685
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24686
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24687
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24688
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24689
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
24690
        // MIs[1] Operand 1
24691
        // No operand predicates
24692
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
24693
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
24694
        // (intrinsic_wo_chain:{ *:[v16i8] } 3012:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] })  =>  (MVE_VRSHR_immu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)
24695
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24696
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24697
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24698
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu8),
24699
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24700
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24701
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24702
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24703
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24704
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24705
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24706
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24707
0
        GIR_EraseFromParent, /*InsnID*/0,
24708
        // GIR_Coverage, 4060,
24709
0
        GIR_Done,
24710
      // Label 1344: @77153
24711
0
      GIM_Try, /*On fail goto*//*Label 1345*/ GIMT_Encode4(77255), // Rule ID 4062 //
24712
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm),
24713
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24714
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24715
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24716
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24717
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24718
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24719
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24720
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24721
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
24722
        // MIs[1] Operand 1
24723
        // No operand predicates
24724
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
24725
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
24726
        // (intrinsic_wo_chain:{ *:[v8i16] } 3012:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] })  =>  (MVE_VRSHR_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)
24727
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24728
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24729
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24730
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms16),
24731
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24732
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24733
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24734
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24735
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24736
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24737
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24738
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24739
0
        GIR_EraseFromParent, /*InsnID*/0,
24740
        // GIR_Coverage, 4062,
24741
0
        GIR_Done,
24742
      // Label 1345: @77255
24743
0
      GIM_Try, /*On fail goto*//*Label 1346*/ GIMT_Encode4(77357), // Rule ID 4064 //
24744
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm),
24745
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24746
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24747
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24748
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24749
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24750
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24751
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24752
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24753
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
24754
        // MIs[1] Operand 1
24755
        // No operand predicates
24756
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
24757
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
24758
        // (intrinsic_wo_chain:{ *:[v8i16] } 3012:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] })  =>  (MVE_VRSHR_immu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)
24759
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24760
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24761
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24762
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu16),
24763
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24764
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24765
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24766
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24767
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24768
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24769
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24770
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24771
0
        GIR_EraseFromParent, /*InsnID*/0,
24772
        // GIR_Coverage, 4064,
24773
0
        GIR_Done,
24774
      // Label 1346: @77357
24775
0
      GIM_Try, /*On fail goto*//*Label 1347*/ GIMT_Encode4(77459), // Rule ID 4066 //
24776
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm),
24777
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24778
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24779
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24780
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24781
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24782
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24783
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24784
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24785
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32),
24786
        // MIs[1] Operand 1
24787
        // No operand predicates
24788
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
24789
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
24790
        // (intrinsic_wo_chain:{ *:[v4i32] } 3012:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 0:{ *:[i32] })  =>  (MVE_VRSHR_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)
24791
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24792
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24793
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24794
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms32),
24795
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24796
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24797
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24798
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24799
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24800
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24801
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24802
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24803
0
        GIR_EraseFromParent, /*InsnID*/0,
24804
        // GIR_Coverage, 4066,
24805
0
        GIR_Done,
24806
      // Label 1347: @77459
24807
0
      GIM_Try, /*On fail goto*//*Label 1348*/ GIMT_Encode4(77561), // Rule ID 4068 //
24808
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm),
24809
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24810
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24811
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24812
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24813
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24814
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24815
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24816
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24817
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32),
24818
        // MIs[1] Operand 1
24819
        // No operand predicates
24820
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
24821
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
24822
        // (intrinsic_wo_chain:{ *:[v4i32] } 3012:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 1:{ *:[i32] })  =>  (MVE_VRSHR_immu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)
24823
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24824
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24825
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24826
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu32),
24827
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24828
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24829
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24830
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24831
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24832
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24833
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24834
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24835
0
        GIR_EraseFromParent, /*InsnID*/0,
24836
        // GIR_Coverage, 4068,
24837
0
        GIR_Done,
24838
      // Label 1348: @77561
24839
0
      GIM_Try, /*On fail goto*//*Label 1349*/ GIMT_Encode4(77662), // Rule ID 4166 //
24840
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24841
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
24842
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24843
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24844
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24845
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24846
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24847
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
24848
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24849
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
24850
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24851
        // MIs[1] Operand 1
24852
        // No operand predicates
24853
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
24854
        // (intrinsic_wo_chain:{ *:[v8f16] } 2931:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale)  =>  (MVE_VCVTf16s16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale)
24855
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24856
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24857
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24858
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16_fix),
24859
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24860
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
24861
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
24862
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24863
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24864
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24865
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24866
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24867
0
        GIR_EraseFromParent, /*InsnID*/0,
24868
        // GIR_Coverage, 4166,
24869
0
        GIR_Done,
24870
      // Label 1349: @77662
24871
0
      GIM_Try, /*On fail goto*//*Label 1350*/ GIMT_Encode4(77763), // Rule ID 4168 //
24872
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24873
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
24874
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24875
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24876
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24877
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24878
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24879
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
24880
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24881
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
24882
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24883
        // MIs[1] Operand 1
24884
        // No operand predicates
24885
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
24886
        // (intrinsic_wo_chain:{ *:[v8i16] } 2931:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale)  =>  (MVE_VCVTs16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale)
24887
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24888
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24889
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24890
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16_fix),
24891
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24892
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
24893
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
24894
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24895
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24896
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24897
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24898
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24899
0
        GIR_EraseFromParent, /*InsnID*/0,
24900
        // GIR_Coverage, 4168,
24901
0
        GIR_Done,
24902
      // Label 1350: @77763
24903
0
      GIM_Try, /*On fail goto*//*Label 1351*/ GIMT_Encode4(77864), // Rule ID 4170 //
24904
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24905
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
24906
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24907
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24908
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24909
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24910
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24911
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
24912
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24913
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
24914
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24915
        // MIs[1] Operand 1
24916
        // No operand predicates
24917
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
24918
        // (intrinsic_wo_chain:{ *:[v8f16] } 2931:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale)  =>  (MVE_VCVTf16u16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale)
24919
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24920
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24921
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24922
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16_fix),
24923
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24924
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
24925
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
24926
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24927
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24928
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24929
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24930
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24931
0
        GIR_EraseFromParent, /*InsnID*/0,
24932
        // GIR_Coverage, 4170,
24933
0
        GIR_Done,
24934
      // Label 1351: @77864
24935
0
      GIM_Try, /*On fail goto*//*Label 1352*/ GIMT_Encode4(77965), // Rule ID 4172 //
24936
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24937
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
24938
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24939
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24940
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24941
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24942
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24943
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
24944
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24945
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
24946
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24947
        // MIs[1] Operand 1
24948
        // No operand predicates
24949
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
24950
        // (intrinsic_wo_chain:{ *:[v8i16] } 2931:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale)  =>  (MVE_VCVTu16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale)
24951
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24952
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24953
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24954
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16_fix),
24955
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24956
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
24957
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
24958
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24959
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24960
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24961
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24962
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24963
0
        GIR_EraseFromParent, /*InsnID*/0,
24964
        // GIR_Coverage, 4172,
24965
0
        GIR_Done,
24966
      // Label 1352: @77965
24967
0
      GIM_Try, /*On fail goto*//*Label 1353*/ GIMT_Encode4(78066), // Rule ID 4174 //
24968
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24969
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
24970
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24971
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24972
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24973
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24974
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24975
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
24976
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24977
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
24978
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24979
        // MIs[1] Operand 1
24980
        // No operand predicates
24981
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
24982
        // (intrinsic_wo_chain:{ *:[v4f32] } 2931:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale)  =>  (MVE_VCVTf32s32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale)
24983
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24984
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24985
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
24986
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32_fix),
24987
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
24988
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
24989
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
24990
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24991
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24992
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24993
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24994
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24995
0
        GIR_EraseFromParent, /*InsnID*/0,
24996
        // GIR_Coverage, 4174,
24997
0
        GIR_Done,
24998
      // Label 1353: @78066
24999
0
      GIM_Try, /*On fail goto*//*Label 1354*/ GIMT_Encode4(78167), // Rule ID 4176 //
25000
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25001
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
25002
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25003
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25004
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25005
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25006
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25007
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
25008
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25009
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25010
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25011
        // MIs[1] Operand 1
25012
        // No operand predicates
25013
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
25014
        // (intrinsic_wo_chain:{ *:[v4i32] } 2931:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale)  =>  (MVE_VCVTs32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale)
25015
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25016
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25017
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25018
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32_fix),
25019
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25020
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
25021
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25022
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25023
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25024
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25025
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25026
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25027
0
        GIR_EraseFromParent, /*InsnID*/0,
25028
        // GIR_Coverage, 4176,
25029
0
        GIR_Done,
25030
      // Label 1354: @78167
25031
0
      GIM_Try, /*On fail goto*//*Label 1355*/ GIMT_Encode4(78268), // Rule ID 4178 //
25032
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25033
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
25034
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25035
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25036
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25037
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25038
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25039
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
25040
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25041
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25042
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25043
        // MIs[1] Operand 1
25044
        // No operand predicates
25045
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
25046
        // (intrinsic_wo_chain:{ *:[v4f32] } 2931:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale)  =>  (MVE_VCVTf32u32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale)
25047
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25048
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25049
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25050
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32_fix),
25051
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25052
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
25053
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25054
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25055
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25056
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25057
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25058
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25059
0
        GIR_EraseFromParent, /*InsnID*/0,
25060
        // GIR_Coverage, 4178,
25061
0
        GIR_Done,
25062
      // Label 1355: @78268
25063
0
      GIM_Try, /*On fail goto*//*Label 1356*/ GIMT_Encode4(78369), // Rule ID 4180 //
25064
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25065
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
25066
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25067
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25068
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25069
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25070
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25071
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
25072
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25073
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25074
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25075
        // MIs[1] Operand 1
25076
        // No operand predicates
25077
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
25078
        // (intrinsic_wo_chain:{ *:[v4i32] } 2931:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale)  =>  (MVE_VCVTu32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale)
25079
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25080
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25081
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25082
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32_fix),
25083
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25084
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
25085
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25086
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25087
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25088
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25089
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25090
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25091
0
        GIR_EraseFromParent, /*InsnID*/0,
25092
        // GIR_Coverage, 4180,
25093
0
        GIR_Done,
25094
      // Label 1356: @78369
25095
0
      GIM_Try, /*On fail goto*//*Label 1357*/ GIMT_Encode4(78453), // Rule ID 3227 //
25096
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25097
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv),
25098
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25099
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25100
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25101
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25102
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25103
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25104
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25105
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25106
        // (intrinsic_wo_chain:{ *:[i32] } 2878:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] })  =>  (MVE_VMINVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
25107
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs8),
25108
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
25109
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25110
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25111
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25112
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25113
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25114
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25115
0
        GIR_EraseFromParent, /*InsnID*/0,
25116
        // GIR_Coverage, 3227,
25117
0
        GIR_Done,
25118
      // Label 1357: @78453
25119
0
      GIM_Try, /*On fail goto*//*Label 1358*/ GIMT_Encode4(78537), // Rule ID 3229 //
25120
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25121
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv),
25122
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25123
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25124
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25125
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25126
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25127
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25128
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25129
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25130
        // (intrinsic_wo_chain:{ *:[i32] } 2878:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] })  =>  (MVE_VMINVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
25131
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs16),
25132
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
25133
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25134
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25135
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25136
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25137
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25138
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25139
0
        GIR_EraseFromParent, /*InsnID*/0,
25140
        // GIR_Coverage, 3229,
25141
0
        GIR_Done,
25142
      // Label 1358: @78537
25143
0
      GIM_Try, /*On fail goto*//*Label 1359*/ GIMT_Encode4(78621), // Rule ID 3231 //
25144
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25145
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv),
25146
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25147
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25148
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25149
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25150
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25151
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25152
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25153
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25154
        // (intrinsic_wo_chain:{ *:[i32] } 2878:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] })  =>  (MVE_VMINVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
25155
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs32),
25156
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
25157
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25158
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25159
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25160
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25161
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25162
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25163
0
        GIR_EraseFromParent, /*InsnID*/0,
25164
        // GIR_Coverage, 3231,
25165
0
        GIR_Done,
25166
      // Label 1359: @78621
25167
0
      GIM_Try, /*On fail goto*//*Label 1360*/ GIMT_Encode4(78705), // Rule ID 3233 //
25168
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25169
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv),
25170
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25171
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25172
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25173
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25174
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25175
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25176
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25177
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25178
        // (intrinsic_wo_chain:{ *:[i32] } 2878:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] })  =>  (MVE_VMINVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
25179
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu8),
25180
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
25181
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25182
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25183
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25184
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25185
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25186
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25187
0
        GIR_EraseFromParent, /*InsnID*/0,
25188
        // GIR_Coverage, 3233,
25189
0
        GIR_Done,
25190
      // Label 1360: @78705
25191
0
      GIM_Try, /*On fail goto*//*Label 1361*/ GIMT_Encode4(78789), // Rule ID 3235 //
25192
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25193
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv),
25194
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25195
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25196
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25197
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25198
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25199
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25200
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25201
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25202
        // (intrinsic_wo_chain:{ *:[i32] } 2878:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] })  =>  (MVE_VMINVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
25203
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu16),
25204
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
25205
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25206
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25207
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25208
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25209
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25210
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25211
0
        GIR_EraseFromParent, /*InsnID*/0,
25212
        // GIR_Coverage, 3235,
25213
0
        GIR_Done,
25214
      // Label 1361: @78789
25215
0
      GIM_Try, /*On fail goto*//*Label 1362*/ GIMT_Encode4(78873), // Rule ID 3237 //
25216
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25217
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv),
25218
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25219
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25220
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25221
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25222
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25223
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25224
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25225
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25226
        // (intrinsic_wo_chain:{ *:[i32] } 2878:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] })  =>  (MVE_VMINVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
25227
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu32),
25228
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
25229
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25230
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25231
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25232
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25233
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25234
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25235
0
        GIR_EraseFromParent, /*InsnID*/0,
25236
        // GIR_Coverage, 3237,
25237
0
        GIR_Done,
25238
      // Label 1362: @78873
25239
0
      GIM_Try, /*On fail goto*//*Label 1363*/ GIMT_Encode4(78957), // Rule ID 3239 //
25240
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25241
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv),
25242
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25243
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25244
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25245
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25246
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25247
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25248
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25249
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25250
        // (intrinsic_wo_chain:{ *:[i32] } 2869:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] })  =>  (MVE_VMAXVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
25251
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs8),
25252
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
25253
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25254
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25255
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25256
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25257
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25258
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25259
0
        GIR_EraseFromParent, /*InsnID*/0,
25260
        // GIR_Coverage, 3239,
25261
0
        GIR_Done,
25262
      // Label 1363: @78957
25263
0
      GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(79041), // Rule ID 3241 //
25264
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25265
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv),
25266
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25267
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25268
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25269
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25270
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25271
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25272
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25273
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25274
        // (intrinsic_wo_chain:{ *:[i32] } 2869:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] })  =>  (MVE_VMAXVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
25275
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs16),
25276
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
25277
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25278
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25279
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25280
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25281
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25282
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25283
0
        GIR_EraseFromParent, /*InsnID*/0,
25284
        // GIR_Coverage, 3241,
25285
0
        GIR_Done,
25286
      // Label 1364: @79041
25287
0
      GIM_Try, /*On fail goto*//*Label 1365*/ GIMT_Encode4(79125), // Rule ID 3243 //
25288
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25289
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv),
25290
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25291
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25292
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25293
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25294
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25295
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25296
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25297
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25298
        // (intrinsic_wo_chain:{ *:[i32] } 2869:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] })  =>  (MVE_VMAXVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
25299
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs32),
25300
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
25301
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25302
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25303
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25304
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25305
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25306
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25307
0
        GIR_EraseFromParent, /*InsnID*/0,
25308
        // GIR_Coverage, 3243,
25309
0
        GIR_Done,
25310
      // Label 1365: @79125
25311
0
      GIM_Try, /*On fail goto*//*Label 1366*/ GIMT_Encode4(79209), // Rule ID 3245 //
25312
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25313
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv),
25314
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25315
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25316
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25317
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25318
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25319
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25320
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25321
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25322
        // (intrinsic_wo_chain:{ *:[i32] } 2869:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] })  =>  (MVE_VMAXVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
25323
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu8),
25324
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
25325
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25326
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25327
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25328
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25329
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25330
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25331
0
        GIR_EraseFromParent, /*InsnID*/0,
25332
        // GIR_Coverage, 3245,
25333
0
        GIR_Done,
25334
      // Label 1366: @79209
25335
0
      GIM_Try, /*On fail goto*//*Label 1367*/ GIMT_Encode4(79293), // Rule ID 3247 //
25336
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25337
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv),
25338
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25339
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25340
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25341
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25342
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25343
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25344
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25345
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25346
        // (intrinsic_wo_chain:{ *:[i32] } 2869:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] })  =>  (MVE_VMAXVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
25347
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu16),
25348
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
25349
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25350
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25351
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25352
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25353
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25354
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25355
0
        GIR_EraseFromParent, /*InsnID*/0,
25356
        // GIR_Coverage, 3247,
25357
0
        GIR_Done,
25358
      // Label 1367: @79293
25359
0
      GIM_Try, /*On fail goto*//*Label 1368*/ GIMT_Encode4(79377), // Rule ID 3249 //
25360
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25361
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv),
25362
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25363
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25364
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25365
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25366
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25367
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25368
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25369
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25370
        // (intrinsic_wo_chain:{ *:[i32] } 2869:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] })  =>  (MVE_VMAXVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
25371
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu32),
25372
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
25373
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25374
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25375
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25376
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25377
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25378
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25379
0
        GIR_EraseFromParent, /*InsnID*/0,
25380
        // GIR_Coverage, 3249,
25381
0
        GIR_Done,
25382
      // Label 1368: @79377
25383
0
      GIM_Try, /*On fail goto*//*Label 1369*/ GIMT_Encode4(79474), // Rule ID 3654 //
25384
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25385
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
25386
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25387
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25388
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25389
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25390
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25391
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25392
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25393
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25394
        // (intrinsic_wo_chain:{ *:[v16i8] } 2915:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VABDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25395
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25396
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25397
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25398
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs8),
25399
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25400
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25401
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25402
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25403
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25404
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25405
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25406
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25407
0
        GIR_EraseFromParent, /*InsnID*/0,
25408
        // GIR_Coverage, 3654,
25409
0
        GIR_Done,
25410
      // Label 1369: @79474
25411
0
      GIM_Try, /*On fail goto*//*Label 1370*/ GIMT_Encode4(79571), // Rule ID 3661 //
25412
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25413
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
25414
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25415
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25416
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25417
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25418
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25419
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25420
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25421
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25422
        // (intrinsic_wo_chain:{ *:[v8i16] } 2915:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VABDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25423
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25424
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25425
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25426
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs16),
25427
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25428
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25429
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25430
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25431
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25432
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25433
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25434
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25435
0
        GIR_EraseFromParent, /*InsnID*/0,
25436
        // GIR_Coverage, 3661,
25437
0
        GIR_Done,
25438
      // Label 1370: @79571
25439
0
      GIM_Try, /*On fail goto*//*Label 1371*/ GIMT_Encode4(79668), // Rule ID 3665 //
25440
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25441
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
25442
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25443
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25444
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25445
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25446
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25447
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25448
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25449
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25450
        // (intrinsic_wo_chain:{ *:[v4i32] } 2915:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VABDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25451
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25452
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25453
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25454
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs32),
25455
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25456
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25457
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25458
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25459
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25460
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25461
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25462
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25463
0
        GIR_EraseFromParent, /*InsnID*/0,
25464
        // GIR_Coverage, 3665,
25465
0
        GIR_Done,
25466
      // Label 1371: @79668
25467
0
      GIM_Try, /*On fail goto*//*Label 1372*/ GIMT_Encode4(79765), // Rule ID 3669 //
25468
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25469
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
25470
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25471
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25472
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25473
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25474
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25475
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25476
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25477
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25478
        // (intrinsic_wo_chain:{ *:[v16i8] } 2915:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VABDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25479
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25480
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25481
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25482
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu8),
25483
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25484
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25485
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25486
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25487
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25488
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25489
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25490
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25491
0
        GIR_EraseFromParent, /*InsnID*/0,
25492
        // GIR_Coverage, 3669,
25493
0
        GIR_Done,
25494
      // Label 1372: @79765
25495
0
      GIM_Try, /*On fail goto*//*Label 1373*/ GIMT_Encode4(79862), // Rule ID 3673 //
25496
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25497
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
25498
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25499
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25500
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25501
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25502
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25503
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25504
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25505
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25506
        // (intrinsic_wo_chain:{ *:[v8i16] } 2915:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VABDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25507
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25508
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25509
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25510
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu16),
25511
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25512
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25513
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25514
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25515
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25516
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25517
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25518
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25519
0
        GIR_EraseFromParent, /*InsnID*/0,
25520
        // GIR_Coverage, 3673,
25521
0
        GIR_Done,
25522
      // Label 1373: @79862
25523
0
      GIM_Try, /*On fail goto*//*Label 1374*/ GIMT_Encode4(79959), // Rule ID 3677 //
25524
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25525
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
25526
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25527
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25528
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25529
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25530
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25531
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25532
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25533
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25534
        // (intrinsic_wo_chain:{ *:[v4i32] } 2915:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VABDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25535
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25536
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25537
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25538
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu32),
25539
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25540
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25541
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25542
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25543
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25544
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25545
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25546
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25547
0
        GIR_EraseFromParent, /*InsnID*/0,
25548
        // GIR_Coverage, 3677,
25549
0
        GIR_Done,
25550
      // Label 1374: @79959
25551
0
      GIM_Try, /*On fail goto*//*Label 1375*/ GIMT_Encode4(80056), // Rule ID 3678 //
25552
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25553
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd),
25554
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25555
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25556
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25557
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25558
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25559
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25560
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25561
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25562
        // (intrinsic_wo_chain:{ *:[v16i8] } 3001:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VRHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25563
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25564
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25565
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25566
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs8),
25567
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25568
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25569
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25570
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25571
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25572
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25573
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25574
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25575
0
        GIR_EraseFromParent, /*InsnID*/0,
25576
        // GIR_Coverage, 3678,
25577
0
        GIR_Done,
25578
      // Label 1375: @80056
25579
0
      GIM_Try, /*On fail goto*//*Label 1376*/ GIMT_Encode4(80153), // Rule ID 3685 //
25580
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25581
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd),
25582
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25583
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25584
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25585
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25586
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25587
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25588
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25589
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25590
        // (intrinsic_wo_chain:{ *:[v8i16] } 3001:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VRHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25591
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25592
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25593
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25594
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs16),
25595
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25596
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25597
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25598
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25599
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25600
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25601
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25602
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25603
0
        GIR_EraseFromParent, /*InsnID*/0,
25604
        // GIR_Coverage, 3685,
25605
0
        GIR_Done,
25606
      // Label 1376: @80153
25607
0
      GIM_Try, /*On fail goto*//*Label 1377*/ GIMT_Encode4(80250), // Rule ID 3689 //
25608
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25609
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd),
25610
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25611
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25612
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25613
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25614
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25615
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25616
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25617
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25618
        // (intrinsic_wo_chain:{ *:[v4i32] } 3001:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VRHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25619
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25620
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25621
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25622
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs32),
25623
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25624
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25625
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25626
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25627
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25628
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25629
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25630
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25631
0
        GIR_EraseFromParent, /*InsnID*/0,
25632
        // GIR_Coverage, 3689,
25633
0
        GIR_Done,
25634
      // Label 1377: @80250
25635
0
      GIM_Try, /*On fail goto*//*Label 1378*/ GIMT_Encode4(80347), // Rule ID 3693 //
25636
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25637
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd),
25638
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25639
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25640
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25641
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25642
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25643
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25644
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25645
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25646
        // (intrinsic_wo_chain:{ *:[v16i8] } 3001:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VRHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25647
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25648
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25649
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25650
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu8),
25651
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25652
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25653
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25654
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25655
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25656
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25657
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25658
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25659
0
        GIR_EraseFromParent, /*InsnID*/0,
25660
        // GIR_Coverage, 3693,
25661
0
        GIR_Done,
25662
      // Label 1378: @80347
25663
0
      GIM_Try, /*On fail goto*//*Label 1379*/ GIMT_Encode4(80444), // Rule ID 3697 //
25664
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25665
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd),
25666
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25667
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25668
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25669
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25670
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25671
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25672
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25673
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25674
        // (intrinsic_wo_chain:{ *:[v8i16] } 3001:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VRHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25675
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25676
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25677
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25678
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu16),
25679
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25680
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25681
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25682
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25683
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25684
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25685
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25686
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25687
0
        GIR_EraseFromParent, /*InsnID*/0,
25688
        // GIR_Coverage, 3697,
25689
0
        GIR_Done,
25690
      // Label 1379: @80444
25691
0
      GIM_Try, /*On fail goto*//*Label 1380*/ GIMT_Encode4(80541), // Rule ID 3701 //
25692
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25693
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd),
25694
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25695
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25696
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25697
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25698
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25699
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25700
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25701
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25702
        // (intrinsic_wo_chain:{ *:[v4i32] } 3001:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VRHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25703
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25704
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25705
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25706
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu32),
25707
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25708
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25709
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25710
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25711
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25712
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25713
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25714
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25715
0
        GIR_EraseFromParent, /*InsnID*/0,
25716
        // GIR_Coverage, 3701,
25717
0
        GIR_Done,
25718
      // Label 1380: @80541
25719
0
      GIM_Try, /*On fail goto*//*Label 1381*/ GIMT_Encode4(80638), // Rule ID 3714 //
25720
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25721
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd),
25722
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25723
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25724
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25725
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25726
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25727
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25728
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25729
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25730
        // (intrinsic_wo_chain:{ *:[v16i8] } 2950:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25731
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25732
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25733
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25734
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs8),
25735
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25736
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25737
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25738
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25739
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25740
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25741
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25742
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25743
0
        GIR_EraseFromParent, /*InsnID*/0,
25744
        // GIR_Coverage, 3714,
25745
0
        GIR_Done,
25746
      // Label 1381: @80638
25747
0
      GIM_Try, /*On fail goto*//*Label 1382*/ GIMT_Encode4(80735), // Rule ID 3722 //
25748
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25749
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd),
25750
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25751
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25752
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25753
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25754
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25755
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25756
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25757
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25758
        // (intrinsic_wo_chain:{ *:[v8i16] } 2950:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25759
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25760
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25761
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25762
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs16),
25763
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25764
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25765
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25766
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25767
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25768
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25769
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25770
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25771
0
        GIR_EraseFromParent, /*InsnID*/0,
25772
        // GIR_Coverage, 3722,
25773
0
        GIR_Done,
25774
      // Label 1382: @80735
25775
0
      GIM_Try, /*On fail goto*//*Label 1383*/ GIMT_Encode4(80832), // Rule ID 3727 //
25776
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25777
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd),
25778
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25779
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25780
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25781
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25782
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25783
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25784
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25785
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25786
        // (intrinsic_wo_chain:{ *:[v4i32] } 2950:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25787
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25788
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25789
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25790
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs32),
25791
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25792
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25793
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25794
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25795
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25796
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25797
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25798
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25799
0
        GIR_EraseFromParent, /*InsnID*/0,
25800
        // GIR_Coverage, 3727,
25801
0
        GIR_Done,
25802
      // Label 1383: @80832
25803
0
      GIM_Try, /*On fail goto*//*Label 1384*/ GIMT_Encode4(80929), // Rule ID 3732 //
25804
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25805
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd),
25806
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25807
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25808
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25809
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25810
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25811
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25812
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25813
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25814
        // (intrinsic_wo_chain:{ *:[v16i8] } 2950:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25815
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25816
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25817
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25818
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu8),
25819
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25820
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25821
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25822
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25823
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25824
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25825
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25826
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25827
0
        GIR_EraseFromParent, /*InsnID*/0,
25828
        // GIR_Coverage, 3732,
25829
0
        GIR_Done,
25830
      // Label 1384: @80929
25831
0
      GIM_Try, /*On fail goto*//*Label 1385*/ GIMT_Encode4(81026), // Rule ID 3737 //
25832
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25833
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd),
25834
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25835
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25836
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25837
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25838
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25839
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25840
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25841
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25842
        // (intrinsic_wo_chain:{ *:[v8i16] } 2950:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25843
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25844
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25845
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25846
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu16),
25847
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25848
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25849
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25850
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25851
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25852
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25853
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25854
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25855
0
        GIR_EraseFromParent, /*InsnID*/0,
25856
        // GIR_Coverage, 3737,
25857
0
        GIR_Done,
25858
      // Label 1385: @81026
25859
0
      GIM_Try, /*On fail goto*//*Label 1386*/ GIMT_Encode4(81123), // Rule ID 3742 //
25860
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25861
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd),
25862
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25863
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25864
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25865
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25866
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25867
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25868
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25869
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25870
        // (intrinsic_wo_chain:{ *:[v4i32] } 2950:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25871
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25872
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25873
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25874
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu32),
25875
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25876
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25877
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25878
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25879
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25880
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25881
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25882
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25883
0
        GIR_EraseFromParent, /*InsnID*/0,
25884
        // GIR_Coverage, 3742,
25885
0
        GIR_Done,
25886
      // Label 1386: @81123
25887
0
      GIM_Try, /*On fail goto*//*Label 1387*/ GIMT_Encode4(81220), // Rule ID 3744 //
25888
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25889
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub),
25890
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25891
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25892
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25893
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25894
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25895
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25896
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25897
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25898
        // (intrinsic_wo_chain:{ *:[v16i8] } 2951:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VHSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25899
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25900
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25901
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25902
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs8),
25903
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25904
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25905
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25906
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25907
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25908
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25909
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25910
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25911
0
        GIR_EraseFromParent, /*InsnID*/0,
25912
        // GIR_Coverage, 3744,
25913
0
        GIR_Done,
25914
      // Label 1387: @81220
25915
0
      GIM_Try, /*On fail goto*//*Label 1388*/ GIMT_Encode4(81317), // Rule ID 3747 //
25916
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25917
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub),
25918
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25919
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25920
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25921
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25922
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25923
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25924
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25925
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25926
        // (intrinsic_wo_chain:{ *:[v8i16] } 2951:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VHSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25927
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25928
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25929
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25930
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs16),
25931
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25932
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25933
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25934
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25935
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25936
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25937
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25938
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25939
0
        GIR_EraseFromParent, /*InsnID*/0,
25940
        // GIR_Coverage, 3747,
25941
0
        GIR_Done,
25942
      // Label 1388: @81317
25943
0
      GIM_Try, /*On fail goto*//*Label 1389*/ GIMT_Encode4(81414), // Rule ID 3750 //
25944
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25945
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub),
25946
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25947
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25948
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25949
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25950
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25951
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25952
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25953
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25954
        // (intrinsic_wo_chain:{ *:[v4i32] } 2951:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VHSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25955
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25956
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25957
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25958
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs32),
25959
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25960
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25961
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25962
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25963
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25964
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25965
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25966
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25967
0
        GIR_EraseFromParent, /*InsnID*/0,
25968
        // GIR_Coverage, 3750,
25969
0
        GIR_Done,
25970
      // Label 1389: @81414
25971
0
      GIM_Try, /*On fail goto*//*Label 1390*/ GIMT_Encode4(81511), // Rule ID 3753 //
25972
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25973
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub),
25974
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25975
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25976
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25977
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25978
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25979
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25980
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25981
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25982
        // (intrinsic_wo_chain:{ *:[v16i8] } 2951:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VHSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25983
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25984
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25985
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
25986
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu8),
25987
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
25988
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25989
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25990
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25991
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25992
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25993
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25994
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25995
0
        GIR_EraseFromParent, /*InsnID*/0,
25996
        // GIR_Coverage, 3753,
25997
0
        GIR_Done,
25998
      // Label 1390: @81511
25999
0
      GIM_Try, /*On fail goto*//*Label 1391*/ GIMT_Encode4(81608), // Rule ID 3756 //
26000
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26001
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub),
26002
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26003
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26004
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26005
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26006
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26007
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26008
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26009
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26010
        // (intrinsic_wo_chain:{ *:[v8i16] } 2951:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VHSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26011
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26012
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26013
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26014
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu16),
26015
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26016
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26017
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26018
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26019
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26020
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26021
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26022
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26023
0
        GIR_EraseFromParent, /*InsnID*/0,
26024
        // GIR_Coverage, 3756,
26025
0
        GIR_Done,
26026
      // Label 1391: @81608
26027
0
      GIM_Try, /*On fail goto*//*Label 1392*/ GIMT_Encode4(81705), // Rule ID 3759 //
26028
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26029
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub),
26030
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26031
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26032
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26033
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26034
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26035
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26036
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26037
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26038
        // (intrinsic_wo_chain:{ *:[v4i32] } 2951:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VHSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26039
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26040
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26041
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26042
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu32),
26043
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26044
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26045
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26046
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26047
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26048
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26049
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26050
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26051
0
        GIR_EraseFromParent, /*InsnID*/0,
26052
        // GIR_Coverage, 3759,
26053
0
        GIR_Done,
26054
      // Label 1392: @81705
26055
0
      GIM_Try, /*On fail goto*//*Label 1393*/ GIMT_Encode4(81802), // Rule ID 4160 //
26056
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
26057
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
26058
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26059
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26060
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26061
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26062
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26063
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26064
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26065
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26066
        // (intrinsic_wo_chain:{ *:[v4f32] } 2915:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
26067
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26068
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26069
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26070
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf32),
26071
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26072
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26073
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26074
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26075
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26076
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26077
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26078
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26079
0
        GIR_EraseFromParent, /*InsnID*/0,
26080
        // GIR_Coverage, 4160,
26081
0
        GIR_Done,
26082
      // Label 1393: @81802
26083
0
      GIM_Try, /*On fail goto*//*Label 1394*/ GIMT_Encode4(81899), // Rule ID 4162 //
26084
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
26085
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
26086
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26087
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26088
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26089
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26090
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26091
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26092
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26093
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26094
        // (intrinsic_wo_chain:{ *:[v8f16] } 2915:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
26095
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26096
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26097
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26098
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf16),
26099
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26100
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26101
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26102
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26103
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26104
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26105
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26106
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26107
0
        GIR_EraseFromParent, /*InsnID*/0,
26108
        // GIR_Coverage, 4162,
26109
0
        GIR_Done,
26110
      // Label 1394: @81899
26111
0
      GIM_Try, /*On fail goto*//*Label 1395*/ GIMT_Encode4(81996), // Rule ID 4535 //
26112
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26113
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly),
26114
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26115
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26116
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26117
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26118
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26119
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26120
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26121
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26122
        // (intrinsic_wo_chain:{ *:[v8i16] } 2978:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VMULLBp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26123
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26124
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26125
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26126
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBp8),
26127
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26128
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26129
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26130
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26131
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26132
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26133
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26134
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26135
0
        GIR_EraseFromParent, /*InsnID*/0,
26136
        // GIR_Coverage, 4535,
26137
0
        GIR_Done,
26138
      // Label 1395: @81996
26139
0
      GIM_Try, /*On fail goto*//*Label 1396*/ GIMT_Encode4(82093), // Rule ID 4537 //
26140
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26141
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly),
26142
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26143
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26144
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26145
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26146
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26147
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26148
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26149
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26150
        // (intrinsic_wo_chain:{ *:[v8i16] } 2978:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VMULLTp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26151
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26152
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26153
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26154
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTp8),
26155
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26156
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26157
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26158
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26159
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26160
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26161
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26162
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26163
0
        GIR_EraseFromParent, /*InsnID*/0,
26164
        // GIR_Coverage, 4537,
26165
0
        GIR_Done,
26166
      // Label 1396: @82093
26167
0
      GIM_Try, /*On fail goto*//*Label 1397*/ GIMT_Encode4(82190), // Rule ID 4539 //
26168
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26169
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly),
26170
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26171
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26172
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26173
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26174
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26175
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26176
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26177
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26178
        // (intrinsic_wo_chain:{ *:[v4i32] } 2978:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VMULLBp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26179
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26180
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26181
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26182
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBp16),
26183
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26184
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26185
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26186
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26187
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26188
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26189
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26190
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26191
0
        GIR_EraseFromParent, /*InsnID*/0,
26192
        // GIR_Coverage, 4539,
26193
0
        GIR_Done,
26194
      // Label 1397: @82190
26195
0
      GIM_Try, /*On fail goto*//*Label 1398*/ GIMT_Encode4(82287), // Rule ID 4541 //
26196
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26197
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly),
26198
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26199
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26200
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26201
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26202
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26203
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26204
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26205
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26206
        // (intrinsic_wo_chain:{ *:[v4i32] } 2978:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VMULLTp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26207
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26208
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26209
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26210
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTp16),
26211
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26212
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26213
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26214
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26215
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26216
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26217
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26218
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26219
0
        GIR_EraseFromParent, /*InsnID*/0,
26220
        // GIR_Coverage, 4541,
26221
0
        GIR_Done,
26222
      // Label 1398: @82287
26223
0
      GIM_Try, /*On fail goto*//*Label 1399*/ GIMT_Encode4(82384), // Rule ID 4568 //
26224
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26225
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh),
26226
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
26227
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26228
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26229
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26230
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26231
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26232
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26233
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26234
        // (intrinsic_wo_chain:{ *:[v16i8] } 2976:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26235
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26236
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26237
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26238
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs8),
26239
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26240
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26241
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26242
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26243
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26244
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26245
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26246
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26247
0
        GIR_EraseFromParent, /*InsnID*/0,
26248
        // GIR_Coverage, 4568,
26249
0
        GIR_Done,
26250
      // Label 1399: @82384
26251
0
      GIM_Try, /*On fail goto*//*Label 1400*/ GIMT_Encode4(82481), // Rule ID 4575 //
26252
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26253
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh),
26254
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26255
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26256
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26257
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26258
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26259
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26260
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26261
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26262
        // (intrinsic_wo_chain:{ *:[v8i16] } 2976:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26263
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26264
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26265
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26266
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs16),
26267
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26268
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26269
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26270
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26271
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26272
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26273
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26274
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26275
0
        GIR_EraseFromParent, /*InsnID*/0,
26276
        // GIR_Coverage, 4575,
26277
0
        GIR_Done,
26278
      // Label 1400: @82481
26279
0
      GIM_Try, /*On fail goto*//*Label 1401*/ GIMT_Encode4(82578), // Rule ID 4579 //
26280
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26281
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh),
26282
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26283
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26284
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26285
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26286
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26287
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26288
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26289
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26290
        // (intrinsic_wo_chain:{ *:[v4i32] } 2976:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26291
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26292
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26293
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26294
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs32),
26295
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26296
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26297
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26298
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26299
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26300
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26301
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26302
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26303
0
        GIR_EraseFromParent, /*InsnID*/0,
26304
        // GIR_Coverage, 4579,
26305
0
        GIR_Done,
26306
      // Label 1401: @82578
26307
0
      GIM_Try, /*On fail goto*//*Label 1402*/ GIMT_Encode4(82675), // Rule ID 4583 //
26308
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26309
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh),
26310
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
26311
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26312
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26313
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26314
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26315
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26316
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26317
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26318
        // (intrinsic_wo_chain:{ *:[v16i8] } 2976:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26319
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26320
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26321
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26322
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu8),
26323
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26324
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26325
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26326
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26327
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26328
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26329
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26330
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26331
0
        GIR_EraseFromParent, /*InsnID*/0,
26332
        // GIR_Coverage, 4583,
26333
0
        GIR_Done,
26334
      // Label 1402: @82675
26335
0
      GIM_Try, /*On fail goto*//*Label 1403*/ GIMT_Encode4(82772), // Rule ID 4587 //
26336
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26337
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh),
26338
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26339
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26340
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26341
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26342
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26343
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26344
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26345
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26346
        // (intrinsic_wo_chain:{ *:[v8i16] } 2976:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26347
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26348
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26349
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26350
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu16),
26351
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26352
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26353
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26354
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26355
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26356
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26357
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26358
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26359
0
        GIR_EraseFromParent, /*InsnID*/0,
26360
        // GIR_Coverage, 4587,
26361
0
        GIR_Done,
26362
      // Label 1403: @82772
26363
0
      GIM_Try, /*On fail goto*//*Label 1404*/ GIMT_Encode4(82869), // Rule ID 4591 //
26364
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26365
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh),
26366
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26367
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26368
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26369
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26370
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26371
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26372
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26373
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26374
        // (intrinsic_wo_chain:{ *:[v4i32] } 2976:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26375
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26376
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26377
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26378
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu32),
26379
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26380
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26381
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26382
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26383
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26384
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26385
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26386
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26387
0
        GIR_EraseFromParent, /*InsnID*/0,
26388
        // GIR_Coverage, 4591,
26389
0
        GIR_Done,
26390
      // Label 1404: @82869
26391
0
      GIM_Try, /*On fail goto*//*Label 1405*/ GIMT_Encode4(82966), // Rule ID 4592 //
26392
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26393
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh),
26394
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
26395
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26396
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26397
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26398
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26399
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26400
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26401
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26402
        // (intrinsic_wo_chain:{ *:[v16i8] } 3011:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VRMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26403
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26404
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26405
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26406
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs8),
26407
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26408
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26409
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26410
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26411
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26412
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26413
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26414
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26415
0
        GIR_EraseFromParent, /*InsnID*/0,
26416
        // GIR_Coverage, 4592,
26417
0
        GIR_Done,
26418
      // Label 1405: @82966
26419
0
      GIM_Try, /*On fail goto*//*Label 1406*/ GIMT_Encode4(83063), // Rule ID 4594 //
26420
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26421
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh),
26422
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26423
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26424
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26425
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26426
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26427
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26428
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26429
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26430
        // (intrinsic_wo_chain:{ *:[v8i16] } 3011:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VRMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26431
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26432
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26433
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26434
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs16),
26435
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26436
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26437
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26438
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26439
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26440
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26441
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26442
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26443
0
        GIR_EraseFromParent, /*InsnID*/0,
26444
        // GIR_Coverage, 4594,
26445
0
        GIR_Done,
26446
      // Label 1406: @83063
26447
0
      GIM_Try, /*On fail goto*//*Label 1407*/ GIMT_Encode4(83160), // Rule ID 4596 //
26448
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26449
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh),
26450
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26451
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26452
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26453
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26454
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26455
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26456
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26457
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26458
        // (intrinsic_wo_chain:{ *:[v4i32] } 3011:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VRMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26459
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26460
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26461
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26462
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs32),
26463
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26464
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26465
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26466
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26467
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26468
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26469
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26470
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26471
0
        GIR_EraseFromParent, /*InsnID*/0,
26472
        // GIR_Coverage, 4596,
26473
0
        GIR_Done,
26474
      // Label 1407: @83160
26475
0
      GIM_Try, /*On fail goto*//*Label 1408*/ GIMT_Encode4(83257), // Rule ID 4598 //
26476
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26477
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh),
26478
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
26479
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26480
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26481
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26482
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26483
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26484
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26485
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26486
        // (intrinsic_wo_chain:{ *:[v16i8] } 3011:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VRMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26487
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26488
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26489
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26490
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu8),
26491
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26492
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26493
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26494
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26495
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26496
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26497
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26498
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26499
0
        GIR_EraseFromParent, /*InsnID*/0,
26500
        // GIR_Coverage, 4598,
26501
0
        GIR_Done,
26502
      // Label 1408: @83257
26503
0
      GIM_Try, /*On fail goto*//*Label 1409*/ GIMT_Encode4(83354), // Rule ID 4600 //
26504
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26505
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh),
26506
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26507
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26508
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26509
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26510
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26511
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26512
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26513
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26514
        // (intrinsic_wo_chain:{ *:[v8i16] } 3011:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VRMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26515
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26516
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26517
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26518
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu16),
26519
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26520
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26521
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26522
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26523
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26524
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26525
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26526
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26527
0
        GIR_EraseFromParent, /*InsnID*/0,
26528
        // GIR_Coverage, 4600,
26529
0
        GIR_Done,
26530
      // Label 1409: @83354
26531
0
      GIM_Try, /*On fail goto*//*Label 1410*/ GIMT_Encode4(83451), // Rule ID 4602 //
26532
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26533
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh),
26534
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26535
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26536
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26537
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26538
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26539
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26540
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26541
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26542
        // (intrinsic_wo_chain:{ *:[v4i32] } 3011:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VRMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26543
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26544
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26545
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26546
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu32),
26547
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26548
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26549
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26550
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26551
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26552
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26553
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26554
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26555
0
        GIR_EraseFromParent, /*InsnID*/0,
26556
        // GIR_Coverage, 4602,
26557
0
        GIR_Done,
26558
      // Label 1410: @83451
26559
0
      GIM_Try, /*On fail goto*//*Label 1411*/ GIMT_Encode4(83535), // Rule ID 4653 //
26560
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
26561
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_narrow),
26562
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26563
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26564
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26565
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26566
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26567
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26568
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26569
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26570
        // (intrinsic_wo_chain:{ *:[v8f16] } 2934:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 0:{ *:[i32] })  =>  (MVE_VCVTf16f32bh:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm)
26571
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16f32bh),
26572
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26573
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
26574
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
26575
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26576
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26577
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26578
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26579
0
        GIR_EraseFromParent, /*InsnID*/0,
26580
        // GIR_Coverage, 4653,
26581
0
        GIR_Done,
26582
      // Label 1411: @83535
26583
0
      GIM_Try, /*On fail goto*//*Label 1412*/ GIMT_Encode4(83619), // Rule ID 4659 //
26584
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
26585
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_narrow),
26586
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26587
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26588
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26589
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26590
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26591
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26592
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26593
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26594
        // (intrinsic_wo_chain:{ *:[v8f16] } 2934:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 1:{ *:[i32] })  =>  (MVE_VCVTf16f32th:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm)
26595
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16f32th),
26596
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26597
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
26598
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
26599
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26600
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26601
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26602
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26603
0
        GIR_EraseFromParent, /*InsnID*/0,
26604
        // GIR_Coverage, 4659,
26605
0
        GIR_Done,
26606
      // Label 1412: @83619
26607
0
      GIM_Try, /*On fail goto*//*Label 1413*/ GIMT_Encode4(83716), // Rule ID 4677 //
26608
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26609
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull),
26610
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26611
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26612
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26613
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26614
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26615
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26616
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26617
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26618
        // (intrinsic_wo_chain:{ *:[v4i32] } 2986:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VQDMULLs16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26619
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26620
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26621
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26622
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs16bh),
26623
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26624
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26625
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26626
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26627
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26628
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26629
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26630
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26631
0
        GIR_EraseFromParent, /*InsnID*/0,
26632
        // GIR_Coverage, 4677,
26633
0
        GIR_Done,
26634
      // Label 1413: @83716
26635
0
      GIM_Try, /*On fail goto*//*Label 1414*/ GIMT_Encode4(83813), // Rule ID 4679 //
26636
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26637
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull),
26638
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26639
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26640
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26641
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26642
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26643
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26644
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26645
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26646
        // (intrinsic_wo_chain:{ *:[v4i32] } 2986:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VQDMULLs16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26647
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26648
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26649
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26650
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs16th),
26651
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26652
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26653
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26654
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26655
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26656
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26657
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26658
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26659
0
        GIR_EraseFromParent, /*InsnID*/0,
26660
        // GIR_Coverage, 4679,
26661
0
        GIR_Done,
26662
      // Label 1414: @83813
26663
0
      GIM_Try, /*On fail goto*//*Label 1415*/ GIMT_Encode4(83910), // Rule ID 4681 //
26664
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26665
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull),
26666
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
26667
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26668
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26669
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26670
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26671
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26672
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26673
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26674
        // (intrinsic_wo_chain:{ *:[v2i64] } 2986:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VQDMULLs32bh:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26675
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26676
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26677
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26678
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs32bh),
26679
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26680
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26681
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26682
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26683
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26684
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26685
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26686
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26687
0
        GIR_EraseFromParent, /*InsnID*/0,
26688
        // GIR_Coverage, 4681,
26689
0
        GIR_Done,
26690
      // Label 1415: @83910
26691
0
      GIM_Try, /*On fail goto*//*Label 1416*/ GIMT_Encode4(84007), // Rule ID 4683 //
26692
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26693
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull),
26694
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
26695
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26696
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26697
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26698
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26699
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26700
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26701
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26702
        // (intrinsic_wo_chain:{ *:[v2i64] } 2986:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VQDMULLs32th:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26703
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26704
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26705
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26706
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs32th),
26707
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26708
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26709
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26710
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26711
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26712
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26713
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26714
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26715
0
        GIR_EraseFromParent, /*InsnID*/0,
26716
        // GIR_Coverage, 4683,
26717
0
        GIR_Done,
26718
      // Label 1416: @84007
26719
0
      GIM_Try, /*On fail goto*//*Label 1417*/ GIMT_Encode4(84101), // Rule ID 4028 //
26720
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsli),
26721
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
26722
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26723
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26724
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26725
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26726
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26727
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26728
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
26729
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
26730
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
26731
        // MIs[1] Operand 1
26732
        // No operand predicates
26733
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
26734
        // (intrinsic_wo_chain:{ *:[v16i8] } 3026:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)  =>  (MVE_VSLIimm8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
26735
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSLIimm8),
26736
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26737
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
26738
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
26739
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
26740
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26741
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26742
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26743
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26744
0
        GIR_EraseFromParent, /*InsnID*/0,
26745
        // GIR_Coverage, 4028,
26746
0
        GIR_Done,
26747
      // Label 1417: @84101
26748
0
      GIM_Try, /*On fail goto*//*Label 1418*/ GIMT_Encode4(84195), // Rule ID 4030 //
26749
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsli),
26750
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26751
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26752
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26753
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26754
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26755
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26756
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26757
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
26758
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
26759
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
26760
        // MIs[1] Operand 1
26761
        // No operand predicates
26762
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
26763
        // (intrinsic_wo_chain:{ *:[v8i16] } 3026:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)  =>  (MVE_VSLIimm16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
26764
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSLIimm16),
26765
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26766
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
26767
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
26768
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
26769
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26770
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26771
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26772
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26773
0
        GIR_EraseFromParent, /*InsnID*/0,
26774
        // GIR_Coverage, 4030,
26775
0
        GIR_Done,
26776
      // Label 1418: @84195
26777
0
      GIM_Try, /*On fail goto*//*Label 1419*/ GIMT_Encode4(84289), // Rule ID 4032 //
26778
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsli),
26779
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26780
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26781
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26782
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26783
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26784
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26785
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26786
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
26787
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
26788
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
26789
        // MIs[1] Operand 1
26790
        // No operand predicates
26791
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
26792
        // (intrinsic_wo_chain:{ *:[v4i32] } 3026:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)  =>  (MVE_VSLIimm32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
26793
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSLIimm32),
26794
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26795
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
26796
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
26797
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
26798
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26799
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26800
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26801
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26802
0
        GIR_EraseFromParent, /*InsnID*/0,
26803
        // GIR_Coverage, 4032,
26804
0
        GIR_Done,
26805
      // Label 1419: @84289
26806
0
      GIM_Try, /*On fail goto*//*Label 1420*/ GIMT_Encode4(84383), // Rule ID 4034 //
26807
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsri),
26808
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
26809
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26810
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26811
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26812
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26813
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26814
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26815
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
26816
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
26817
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
26818
        // MIs[1] Operand 1
26819
        // No operand predicates
26820
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
26821
        // (intrinsic_wo_chain:{ *:[v16i8] } 3028:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)  =>  (MVE_VSRIimm8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)
26822
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSRIimm8),
26823
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26824
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
26825
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
26826
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
26827
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26828
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26829
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26830
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26831
0
        GIR_EraseFromParent, /*InsnID*/0,
26832
        // GIR_Coverage, 4034,
26833
0
        GIR_Done,
26834
      // Label 1420: @84383
26835
0
      GIM_Try, /*On fail goto*//*Label 1421*/ GIMT_Encode4(84477), // Rule ID 4036 //
26836
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsri),
26837
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26838
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26839
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26840
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26841
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26842
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26843
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26844
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
26845
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
26846
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
26847
        // MIs[1] Operand 1
26848
        // No operand predicates
26849
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
26850
        // (intrinsic_wo_chain:{ *:[v8i16] } 3028:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)  =>  (MVE_VSRIimm16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)
26851
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSRIimm16),
26852
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26853
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
26854
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
26855
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
26856
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26857
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26858
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26859
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26860
0
        GIR_EraseFromParent, /*InsnID*/0,
26861
        // GIR_Coverage, 4036,
26862
0
        GIR_Done,
26863
      // Label 1421: @84477
26864
0
      GIM_Try, /*On fail goto*//*Label 1422*/ GIMT_Encode4(84571), // Rule ID 4038 //
26865
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsri),
26866
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26867
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26868
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26869
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26870
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26871
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26872
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26873
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
26874
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
26875
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32),
26876
        // MIs[1] Operand 1
26877
        // No operand predicates
26878
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
26879
        // (intrinsic_wo_chain:{ *:[v4i32] } 3028:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)  =>  (MVE_VSRIimm32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)
26880
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSRIimm32),
26881
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26882
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
26883
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
26884
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
26885
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26886
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26887
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26888
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26889
0
        GIR_EraseFromParent, /*InsnID*/0,
26890
        // GIR_Coverage, 4038,
26891
0
        GIR_Done,
26892
      // Label 1422: @84571
26893
0
      GIM_Try, /*On fail goto*//*Label 1423*/ GIMT_Encode4(84677), // Rule ID 4507 //
26894
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
26895
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq),
26896
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26897
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26898
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26899
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
26900
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26901
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
26902
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
26903
        // MIs[1] Operand 1
26904
        // No operand predicates
26905
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26906
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26907
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
26908
        // (intrinsic_wo_chain:{ *:[v8f16] } 2925:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm)  =>  (MVE_VCMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
26909
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26910
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26911
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26912
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMULf16),
26913
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26914
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26915
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qm
26916
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
26917
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26918
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26919
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26920
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26921
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26922
0
        GIR_EraseFromParent, /*InsnID*/0,
26923
        // GIR_Coverage, 4507,
26924
0
        GIR_Done,
26925
      // Label 1423: @84677
26926
0
      GIM_Try, /*On fail goto*//*Label 1424*/ GIMT_Encode4(84783), // Rule ID 4509 //
26927
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
26928
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq),
26929
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26930
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26931
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26932
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
26933
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26934
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
26935
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
26936
        // MIs[1] Operand 1
26937
        // No operand predicates
26938
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26939
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26940
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
26941
        // (intrinsic_wo_chain:{ *:[v4f32] } 2925:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm)  =>  (MVE_VCMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
26942
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26943
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26944
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
26945
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMULf32),
26946
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
26947
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26948
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qm
26949
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
26950
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26951
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26952
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26953
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26954
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26955
0
        GIR_EraseFromParent, /*InsnID*/0,
26956
        // GIR_Coverage, 4509,
26957
0
        GIR_Done,
26958
      // Label 1424: @84783
26959
0
      GIM_Try, /*On fail goto*//*Label 1425*/ GIMT_Encode4(84866), // Rule ID 146 //
26960
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
26961
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usada8),
26962
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26963
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26964
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26965
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26966
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
26967
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
26968
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
26969
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
26970
        // (intrinsic_wo_chain:{ *:[i32] } 3258:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)  =>  (USADA8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
26971
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::USADA8),
26972
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
26973
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
26974
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
26975
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
26976
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
26977
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26978
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26979
0
        GIR_EraseFromParent, /*InsnID*/0,
26980
        // GIR_Coverage, 146,
26981
0
        GIR_Done,
26982
      // Label 1425: @84866
26983
0
      GIM_Try, /*On fail goto*//*Label 1426*/ GIMT_Encode4(84949), // Rule ID 477 //
26984
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
26985
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usada8),
26986
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26987
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26988
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26989
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26990
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26991
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26992
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26993
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26994
        // (intrinsic_wo_chain:{ *:[i32] } 3258:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)  =>  (t2USADA8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
26995
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2USADA8),
26996
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
26997
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
26998
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
26999
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
27000
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27001
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27002
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27003
0
        GIR_EraseFromParent, /*InsnID*/0,
27004
        // GIR_Coverage, 477,
27005
0
        GIR_Done,
27006
      // Label 1426: @84949
27007
0
      GIM_Try, /*On fail goto*//*Label 1427*/ GIMT_Encode4(85032), // Rule ID 536 //
27008
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
27009
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlad),
27010
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27011
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27012
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27013
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27014
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27015
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27016
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27017
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27018
        // (intrinsic_wo_chain:{ *:[i32] } 3203:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)  =>  (t2SMLAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
27019
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMLAD),
27020
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
27021
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
27022
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
27023
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
27024
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27025
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27026
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27027
0
        GIR_EraseFromParent, /*InsnID*/0,
27028
        // GIR_Coverage, 536,
27029
0
        GIR_Done,
27030
      // Label 1427: @85032
27031
0
      GIM_Try, /*On fail goto*//*Label 1428*/ GIMT_Encode4(85115), // Rule ID 537 //
27032
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
27033
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smladx),
27034
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27035
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27036
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27037
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27038
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27039
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27040
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27041
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27042
        // (intrinsic_wo_chain:{ *:[i32] } 3204:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)  =>  (t2SMLADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
27043
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMLADX),
27044
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
27045
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
27046
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
27047
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
27048
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27049
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27050
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27051
0
        GIR_EraseFromParent, /*InsnID*/0,
27052
        // GIR_Coverage, 537,
27053
0
        GIR_Done,
27054
      // Label 1428: @85115
27055
0
      GIM_Try, /*On fail goto*//*Label 1429*/ GIMT_Encode4(85198), // Rule ID 538 //
27056
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
27057
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsd),
27058
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27059
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27060
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27061
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27062
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27063
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27064
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27065
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27066
        // (intrinsic_wo_chain:{ *:[i32] } 3211:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)  =>  (t2SMLSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
27067
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMLSD),
27068
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
27069
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
27070
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
27071
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
27072
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27073
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27074
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27075
0
        GIR_EraseFromParent, /*InsnID*/0,
27076
        // GIR_Coverage, 538,
27077
0
        GIR_Done,
27078
      // Label 1429: @85198
27079
0
      GIM_Try, /*On fail goto*//*Label 1430*/ GIMT_Encode4(85281), // Rule ID 539 //
27080
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
27081
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsdx),
27082
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27083
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27084
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27085
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27086
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27087
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27088
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27089
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27090
        // (intrinsic_wo_chain:{ *:[i32] } 3212:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)  =>  (t2SMLSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
27091
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMLSDX),
27092
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
27093
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
27094
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
27095
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
27096
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27097
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27098
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27099
0
        GIR_EraseFromParent, /*InsnID*/0,
27100
        // GIR_Coverage, 539,
27101
0
        GIR_Done,
27102
      // Label 1430: @85281
27103
0
      GIM_Try, /*On fail goto*//*Label 1431*/ GIMT_Encode4(85355), // Rule ID 968 //
27104
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
27105
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_udot),
27106
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
27107
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
27108
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
27109
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
27110
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27111
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27112
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27113
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27114
        // (intrinsic_wo_chain:{ *:[v2i32] } 3058:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VUDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
27115
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VUDOTD),
27116
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
27117
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27118
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27119
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27120
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27121
0
        GIR_EraseFromParent, /*InsnID*/0,
27122
        // GIR_Coverage, 968,
27123
0
        GIR_Done,
27124
      // Label 1431: @85355
27125
0
      GIM_Try, /*On fail goto*//*Label 1432*/ GIMT_Encode4(85429), // Rule ID 969 //
27126
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
27127
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sdot),
27128
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
27129
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
27130
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
27131
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
27132
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27133
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27134
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27135
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27136
        // (intrinsic_wo_chain:{ *:[v2i32] } 3046:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
27137
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSDOTD),
27138
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
27139
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27140
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27141
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27142
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27143
0
        GIR_EraseFromParent, /*InsnID*/0,
27144
        // GIR_Coverage, 969,
27145
0
        GIR_Done,
27146
      // Label 1432: @85429
27147
0
      GIM_Try, /*On fail goto*//*Label 1433*/ GIMT_Encode4(85503), // Rule ID 970 //
27148
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
27149
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_udot),
27150
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27151
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27152
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
27153
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
27154
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27155
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27156
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27157
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27158
        // (intrinsic_wo_chain:{ *:[v4i32] } 3058:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VUDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27159
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VUDOTQ),
27160
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
27161
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27162
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27163
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27164
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27165
0
        GIR_EraseFromParent, /*InsnID*/0,
27166
        // GIR_Coverage, 970,
27167
0
        GIR_Done,
27168
      // Label 1433: @85503
27169
0
      GIM_Try, /*On fail goto*//*Label 1434*/ GIMT_Encode4(85577), // Rule ID 971 //
27170
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
27171
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sdot),
27172
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27173
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27174
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
27175
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
27176
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27177
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27178
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27179
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27180
        // (intrinsic_wo_chain:{ *:[v4i32] } 3046:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27181
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSDOTQ),
27182
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
27183
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27184
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27185
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27186
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27187
0
        GIR_EraseFromParent, /*InsnID*/0,
27188
        // GIR_Coverage, 971,
27189
0
        GIR_Done,
27190
      // Label 1434: @85577
27191
0
      GIM_Try, /*On fail goto*//*Label 1435*/ GIMT_Encode4(85651), // Rule ID 972 //
27192
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
27193
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_smmla),
27194
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27195
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27196
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
27197
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
27198
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27199
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27200
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27201
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27202
        // (intrinsic_wo_chain:{ *:[v4i32] } 3057:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27203
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSMMLA),
27204
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
27205
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27206
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27207
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27208
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27209
0
        GIR_EraseFromParent, /*InsnID*/0,
27210
        // GIR_Coverage, 972,
27211
0
        GIR_Done,
27212
      // Label 1435: @85651
27213
0
      GIM_Try, /*On fail goto*//*Label 1436*/ GIMT_Encode4(85725), // Rule ID 973 //
27214
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
27215
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_ummla),
27216
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27217
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27218
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
27219
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
27220
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27221
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27222
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27223
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27224
        // (intrinsic_wo_chain:{ *:[v4i32] } 3059:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VUMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27225
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VUMMLA),
27226
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
27227
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27228
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27229
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27230
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27231
0
        GIR_EraseFromParent, /*InsnID*/0,
27232
        // GIR_Coverage, 973,
27233
0
        GIR_Done,
27234
      // Label 1436: @85725
27235
0
      GIM_Try, /*On fail goto*//*Label 1437*/ GIMT_Encode4(85799), // Rule ID 974 //
27236
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
27237
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usmmla),
27238
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27239
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27240
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
27241
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
27242
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27243
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27244
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27245
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27246
        // (intrinsic_wo_chain:{ *:[v4i32] } 3061:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VUSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27247
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VUSMMLA),
27248
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
27249
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27250
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27251
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27252
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27253
0
        GIR_EraseFromParent, /*InsnID*/0,
27254
        // GIR_Coverage, 974,
27255
0
        GIR_Done,
27256
      // Label 1437: @85799
27257
0
      GIM_Try, /*On fail goto*//*Label 1438*/ GIMT_Encode4(85873), // Rule ID 975 //
27258
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
27259
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usdot),
27260
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
27261
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
27262
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
27263
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
27264
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27265
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27266
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27267
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27268
        // (intrinsic_wo_chain:{ *:[v2i32] } 3060:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VUSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
27269
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VUSDOTD),
27270
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
27271
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27272
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27273
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27274
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27275
0
        GIR_EraseFromParent, /*InsnID*/0,
27276
        // GIR_Coverage, 975,
27277
0
        GIR_Done,
27278
      // Label 1438: @85873
27279
0
      GIM_Try, /*On fail goto*//*Label 1439*/ GIMT_Encode4(85947), // Rule ID 976 //
27280
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
27281
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usdot),
27282
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27283
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27284
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
27285
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
27286
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27287
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27288
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27289
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27290
        // (intrinsic_wo_chain:{ *:[v4i32] } 3060:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VUSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27291
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VUSDOTQ),
27292
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
27293
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27294
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27295
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27296
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27297
0
        GIR_EraseFromParent, /*InsnID*/0,
27298
        // GIR_Coverage, 976,
27299
0
        GIR_Done,
27300
      // Label 1439: @85947
27301
0
      GIM_Try, /*On fail goto*//*Label 1440*/ GIMT_Encode4(86030), // Rule ID 1709 //
27302
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
27303
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx1),
27304
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
27305
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
27306
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
27307
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
27308
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27309
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27310
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27311
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27312
        // (intrinsic_wo_chain:{ *:[v8i8] } 3178:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VTBX1:{ *:[v8i8] } DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
27313
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VTBX1),
27314
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
27315
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // orig
27316
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27317
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27318
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27319
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27320
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27321
0
        GIR_EraseFromParent, /*InsnID*/0,
27322
        // GIR_Coverage, 1709,
27323
0
        GIR_Done,
27324
      // Label 1440: @86030
27325
0
      GIM_Try, /*On fail goto*//*Label 1441*/ GIMT_Encode4(86104), // Rule ID 1740 //
27326
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8),
27327
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1su0),
27328
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27329
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27330
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
27331
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
27332
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27333
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27334
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27335
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27336
        // (intrinsic_wo_chain:{ *:[v4i32] } 3051:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA1SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
27337
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SHA1SU0),
27338
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
27339
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
27340
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27341
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27342
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27343
0
        GIR_EraseFromParent, /*InsnID*/0,
27344
        // GIR_Coverage, 1740,
27345
0
        GIR_Done,
27346
      // Label 1441: @86104
27347
0
      GIM_Try, /*On fail goto*//*Label 1442*/ GIMT_Encode4(86178), // Rule ID 1741 //
27348
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8),
27349
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256h),
27350
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27351
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27352
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
27353
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
27354
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27355
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27356
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27357
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27358
        // (intrinsic_wo_chain:{ *:[v4i32] } 3053:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA256H:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
27359
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SHA256H),
27360
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
27361
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
27362
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27363
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27364
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27365
0
        GIR_EraseFromParent, /*InsnID*/0,
27366
        // GIR_Coverage, 1741,
27367
0
        GIR_Done,
27368
      // Label 1442: @86178
27369
0
      GIM_Try, /*On fail goto*//*Label 1443*/ GIMT_Encode4(86252), // Rule ID 1742 //
27370
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8),
27371
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256h2),
27372
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27373
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27374
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
27375
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
27376
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27377
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27378
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27379
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27380
        // (intrinsic_wo_chain:{ *:[v4i32] } 3054:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA256H2:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
27381
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SHA256H2),
27382
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
27383
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
27384
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27385
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27386
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27387
0
        GIR_EraseFromParent, /*InsnID*/0,
27388
        // GIR_Coverage, 1742,
27389
0
        GIR_Done,
27390
      // Label 1443: @86252
27391
0
      GIM_Try, /*On fail goto*//*Label 1444*/ GIMT_Encode4(86326), // Rule ID 1743 //
27392
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8),
27393
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256su1),
27394
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27395
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27396
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
27397
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
27398
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27399
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27400
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27401
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27402
        // (intrinsic_wo_chain:{ *:[v4i32] } 3056:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA256SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
27403
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SHA256SU1),
27404
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
27405
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
27406
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27407
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27408
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27409
0
        GIR_EraseFromParent, /*InsnID*/0,
27410
        // GIR_Coverage, 1743,
27411
0
        GIR_Done,
27412
      // Label 1444: @86326
27413
0
      GIM_Try, /*On fail goto*//*Label 1445*/ GIMT_Encode4(86400), // Rule ID 1744 //
27414
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON),
27415
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_bfdot),
27416
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
27417
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
27418
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
27419
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16,
27420
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27421
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27422
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27423
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27424
        // (intrinsic_wo_chain:{ *:[v2f32] } 3042:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vd, DPR:{ *:[v4bf16] }:$Vn, DPR:{ *:[v4bf16] }:$Vm)  =>  (BF16VDOTS_VDOTD:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vd, DPR:{ *:[v4bf16] }:$Vn, DPR:{ *:[v4bf16] }:$Vm)
27425
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::BF16VDOTS_VDOTD),
27426
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
27427
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27428
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27429
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27430
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27431
0
        GIR_EraseFromParent, /*InsnID*/0,
27432
        // GIR_Coverage, 1744,
27433
0
        GIR_Done,
27434
      // Label 1445: @86400
27435
0
      GIM_Try, /*On fail goto*//*Label 1446*/ GIMT_Encode4(86474), // Rule ID 1745 //
27436
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON),
27437
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_bfdot),
27438
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27439
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27440
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
27441
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
27442
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27443
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27444
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27445
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27446
        // (intrinsic_wo_chain:{ *:[v4f32] } 3042:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm)  =>  (BF16VDOTS_VDOTQ:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm)
27447
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::BF16VDOTS_VDOTQ),
27448
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
27449
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27450
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27451
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27452
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27453
0
        GIR_EraseFromParent, /*InsnID*/0,
27454
        // GIR_Coverage, 1745,
27455
0
        GIR_Done,
27456
      // Label 1446: @86474
27457
0
      GIM_Try, /*On fail goto*//*Label 1447*/ GIMT_Encode4(86548), // Rule ID 1746 //
27458
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON),
27459
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_bfmmla),
27460
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27461
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27462
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
27463
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
27464
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27465
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27466
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27467
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27468
        // (intrinsic_wo_chain:{ *:[v4f32] } 3045:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm)  =>  (VMMLA:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm)
27469
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMMLA),
27470
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
27471
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27472
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27473
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27474
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27475
0
        GIR_EraseFromParent, /*InsnID*/0,
27476
        // GIR_Coverage, 1746,
27477
0
        GIR_Done,
27478
      // Label 1447: @86548
27479
0
      GIM_Try, /*On fail goto*//*Label 1448*/ GIMT_Encode4(86622), // Rule ID 1747 //
27480
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON),
27481
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_bfmlalt),
27482
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27483
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27484
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
27485
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
27486
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27487
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27488
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27489
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27490
        // (intrinsic_wo_chain:{ *:[v4f32] } 3044:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm)  =>  (VBF16MALTQ:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm)
27491
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VBF16MALTQ),
27492
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
27493
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27494
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27495
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27496
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27497
0
        GIR_EraseFromParent, /*InsnID*/0,
27498
        // GIR_Coverage, 1747,
27499
0
        GIR_Done,
27500
      // Label 1448: @86622
27501
0
      GIM_Try, /*On fail goto*//*Label 1449*/ GIMT_Encode4(86696), // Rule ID 1748 //
27502
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON),
27503
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_bfmlalb),
27504
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27505
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27506
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
27507
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
27508
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27509
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27510
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27511
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27512
        // (intrinsic_wo_chain:{ *:[v4f32] } 3043:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm)  =>  (VBF16MALBQ:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm)
27513
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VBF16MALBQ),
27514
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
27515
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27516
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27517
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27518
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27519
0
        GIR_EraseFromParent, /*InsnID*/0,
27520
        // GIR_Coverage, 1748,
27521
0
        GIR_Done,
27522
      // Label 1449: @86696
27523
0
      GIM_Try, /*On fail goto*//*Label 1450*/ GIMT_Encode4(86779), // Rule ID 1927 //
27524
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
27525
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlad),
27526
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27527
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27528
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27529
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27530
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27531
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27532
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27533
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27534
        // (intrinsic_wo_chain:{ *:[i32] } 3203:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)  =>  (SMLAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
27535
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMLAD),
27536
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
27537
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
27538
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
27539
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
27540
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27541
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27542
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27543
0
        GIR_EraseFromParent, /*InsnID*/0,
27544
        // GIR_Coverage, 1927,
27545
0
        GIR_Done,
27546
      // Label 1450: @86779
27547
0
      GIM_Try, /*On fail goto*//*Label 1451*/ GIMT_Encode4(86862), // Rule ID 1928 //
27548
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
27549
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smladx),
27550
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27551
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27552
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27553
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27554
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27555
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27556
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27557
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27558
        // (intrinsic_wo_chain:{ *:[i32] } 3204:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)  =>  (SMLADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
27559
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMLADX),
27560
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
27561
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
27562
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
27563
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
27564
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27565
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27566
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27567
0
        GIR_EraseFromParent, /*InsnID*/0,
27568
        // GIR_Coverage, 1928,
27569
0
        GIR_Done,
27570
      // Label 1451: @86862
27571
0
      GIM_Try, /*On fail goto*//*Label 1452*/ GIMT_Encode4(86945), // Rule ID 1929 //
27572
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
27573
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsd),
27574
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27575
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27576
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27577
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27578
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27579
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27580
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27581
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27582
        // (intrinsic_wo_chain:{ *:[i32] } 3211:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)  =>  (SMLSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
27583
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMLSD),
27584
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
27585
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
27586
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
27587
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
27588
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27589
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27590
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27591
0
        GIR_EraseFromParent, /*InsnID*/0,
27592
        // GIR_Coverage, 1929,
27593
0
        GIR_Done,
27594
      // Label 1452: @86945
27595
0
      GIM_Try, /*On fail goto*//*Label 1453*/ GIMT_Encode4(87028), // Rule ID 1930 //
27596
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
27597
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsdx),
27598
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27599
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27600
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27601
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27602
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27603
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27604
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27605
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27606
        // (intrinsic_wo_chain:{ *:[i32] } 3212:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)  =>  (SMLSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
27607
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMLSDX),
27608
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
27609
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
27610
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
27611
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
27612
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27613
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27614
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27615
0
        GIR_EraseFromParent, /*InsnID*/0,
27616
        // GIR_Coverage, 1930,
27617
0
        GIR_Done,
27618
      // Label 1453: @87028
27619
0
      GIM_Try, /*On fail goto*//*Label 1454*/ GIMT_Encode4(87111), // Rule ID 2008 //
27620
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
27621
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabb),
27622
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27623
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27624
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27625
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27626
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27627
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27628
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27629
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27630
        // (intrinsic_wo_chain:{ *:[i32] } 3201:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27631
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMLABB),
27632
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
27633
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27634
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27635
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27636
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27637
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27638
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27639
0
        GIR_EraseFromParent, /*InsnID*/0,
27640
        // GIR_Coverage, 2008,
27641
0
        GIR_Done,
27642
      // Label 1454: @87111
27643
0
      GIM_Try, /*On fail goto*//*Label 1455*/ GIMT_Encode4(87194), // Rule ID 2009 //
27644
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
27645
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabt),
27646
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27647
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27648
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27649
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27650
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27651
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27652
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27653
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27654
        // (intrinsic_wo_chain:{ *:[i32] } 3202:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27655
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMLABT),
27656
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
27657
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27658
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27659
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27660
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27661
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27662
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27663
0
        GIR_EraseFromParent, /*InsnID*/0,
27664
        // GIR_Coverage, 2009,
27665
0
        GIR_Done,
27666
      // Label 1455: @87194
27667
0
      GIM_Try, /*On fail goto*//*Label 1456*/ GIMT_Encode4(87277), // Rule ID 2010 //
27668
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
27669
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatb),
27670
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27671
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27672
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27673
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27674
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27675
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27676
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27677
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27678
        // (intrinsic_wo_chain:{ *:[i32] } 3207:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27679
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMLATB),
27680
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
27681
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27682
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27683
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27684
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27685
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27686
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27687
0
        GIR_EraseFromParent, /*InsnID*/0,
27688
        // GIR_Coverage, 2010,
27689
0
        GIR_Done,
27690
      // Label 1456: @87277
27691
0
      GIM_Try, /*On fail goto*//*Label 1457*/ GIMT_Encode4(87360), // Rule ID 2011 //
27692
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
27693
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatt),
27694
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27695
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27696
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27697
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27698
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27699
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27700
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27701
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27702
        // (intrinsic_wo_chain:{ *:[i32] } 3208:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27703
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMLATT),
27704
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
27705
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27706
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27707
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27708
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27709
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27710
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27711
0
        GIR_EraseFromParent, /*InsnID*/0,
27712
        // GIR_Coverage, 2011,
27713
0
        GIR_Done,
27714
      // Label 1457: @87360
27715
0
      GIM_Try, /*On fail goto*//*Label 1458*/ GIMT_Encode4(87443), // Rule ID 2012 //
27716
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
27717
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawb),
27718
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27719
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27720
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27721
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27722
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27723
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27724
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27725
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27726
        // (intrinsic_wo_chain:{ *:[i32] } 3209:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27727
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMLAWB),
27728
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
27729
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27730
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27731
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27732
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27733
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27734
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27735
0
        GIR_EraseFromParent, /*InsnID*/0,
27736
        // GIR_Coverage, 2012,
27737
0
        GIR_Done,
27738
      // Label 1458: @87443
27739
0
      GIM_Try, /*On fail goto*//*Label 1459*/ GIMT_Encode4(87526), // Rule ID 2013 //
27740
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
27741
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawt),
27742
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27743
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27744
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27745
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27746
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27747
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27748
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27749
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27750
        // (intrinsic_wo_chain:{ *:[i32] } 3210:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27751
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMLAWT),
27752
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
27753
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27754
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27755
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27756
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27757
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27758
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27759
0
        GIR_EraseFromParent, /*InsnID*/0,
27760
        // GIR_Coverage, 2013,
27761
0
        GIR_Done,
27762
      // Label 1459: @87526
27763
0
      GIM_Try, /*On fail goto*//*Label 1460*/ GIMT_Encode4(87609), // Rule ID 2197 //
27764
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
27765
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabb),
27766
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27767
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27768
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27769
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27770
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27771
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27772
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27773
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27774
        // (intrinsic_wo_chain:{ *:[i32] } 3201:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27775
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB),
27776
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
27777
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27778
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27779
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27780
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27781
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27782
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27783
0
        GIR_EraseFromParent, /*InsnID*/0,
27784
        // GIR_Coverage, 2197,
27785
0
        GIR_Done,
27786
      // Label 1460: @87609
27787
0
      GIM_Try, /*On fail goto*//*Label 1461*/ GIMT_Encode4(87692), // Rule ID 2198 //
27788
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
27789
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabt),
27790
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27791
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27792
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27793
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27794
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27795
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27796
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27797
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27798
        // (intrinsic_wo_chain:{ *:[i32] } 3202:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27799
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT),
27800
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
27801
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27802
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27803
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27804
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27805
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27806
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27807
0
        GIR_EraseFromParent, /*InsnID*/0,
27808
        // GIR_Coverage, 2198,
27809
0
        GIR_Done,
27810
      // Label 1461: @87692
27811
0
      GIM_Try, /*On fail goto*//*Label 1462*/ GIMT_Encode4(87775), // Rule ID 2199 //
27812
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
27813
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatb),
27814
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27815
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27816
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27817
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27818
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27819
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27820
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27821
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27822
        // (intrinsic_wo_chain:{ *:[i32] } 3207:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27823
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMLATB),
27824
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
27825
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27826
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27827
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27828
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27829
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27830
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27831
0
        GIR_EraseFromParent, /*InsnID*/0,
27832
        // GIR_Coverage, 2199,
27833
0
        GIR_Done,
27834
      // Label 1462: @87775
27835
0
      GIM_Try, /*On fail goto*//*Label 1463*/ GIMT_Encode4(87858), // Rule ID 2200 //
27836
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
27837
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatt),
27838
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27839
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27840
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27841
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27842
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27843
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27844
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27845
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27846
        // (intrinsic_wo_chain:{ *:[i32] } 3208:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27847
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT),
27848
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
27849
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27850
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27851
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27852
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27853
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27854
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27855
0
        GIR_EraseFromParent, /*InsnID*/0,
27856
        // GIR_Coverage, 2200,
27857
0
        GIR_Done,
27858
      // Label 1463: @87858
27859
0
      GIM_Try, /*On fail goto*//*Label 1464*/ GIMT_Encode4(87941), // Rule ID 2201 //
27860
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
27861
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawb),
27862
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27863
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27864
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27865
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27866
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27867
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27868
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27869
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27870
        // (intrinsic_wo_chain:{ *:[i32] } 3209:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27871
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMLAWB),
27872
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
27873
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27874
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27875
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27876
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27877
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27878
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27879
0
        GIR_EraseFromParent, /*InsnID*/0,
27880
        // GIR_Coverage, 2201,
27881
0
        GIR_Done,
27882
      // Label 1464: @87941
27883
0
      GIM_Try, /*On fail goto*//*Label 1465*/ GIMT_Encode4(88024), // Rule ID 2202 //
27884
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
27885
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawt),
27886
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27887
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27888
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27889
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27890
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27891
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27892
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27893
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27894
        // (intrinsic_wo_chain:{ *:[i32] } 3210:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27895
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMLAWT),
27896
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
27897
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27898
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27899
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27900
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27901
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27902
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27903
0
        GIR_EraseFromParent, /*InsnID*/0,
27904
        // GIR_Coverage, 2202,
27905
0
        GIR_Done,
27906
      // Label 1465: @88024
27907
0
      GIM_Try, /*On fail goto*//*Label 1466*/ GIMT_Encode4(88107), // Rule ID 2478 //
27908
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
27909
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah),
27910
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
27911
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
27912
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
27913
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16,
27914
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27915
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27916
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27917
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27918
        // (intrinsic_wo_chain:{ *:[v4i16] } 3130:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQRDMLAHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
27919
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv4i16),
27920
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
27921
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
27922
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27923
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27924
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27925
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27926
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27927
0
        GIR_EraseFromParent, /*InsnID*/0,
27928
        // GIR_Coverage, 2478,
27929
0
        GIR_Done,
27930
      // Label 1466: @88107
27931
0
      GIM_Try, /*On fail goto*//*Label 1467*/ GIMT_Encode4(88190), // Rule ID 2479 //
27932
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
27933
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah),
27934
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
27935
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
27936
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
27937
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s32,
27938
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27939
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27940
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27941
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27942
        // (intrinsic_wo_chain:{ *:[v2i32] } 3130:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQRDMLAHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
27943
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv2i32),
27944
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
27945
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
27946
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27947
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27948
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27949
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27950
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27951
0
        GIR_EraseFromParent, /*InsnID*/0,
27952
        // GIR_Coverage, 2479,
27953
0
        GIR_Done,
27954
      // Label 1467: @88190
27955
0
      GIM_Try, /*On fail goto*//*Label 1468*/ GIMT_Encode4(88273), // Rule ID 2480 //
27956
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
27957
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah),
27958
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
27959
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
27960
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
27961
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
27962
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27963
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27964
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27965
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27966
        // (intrinsic_wo_chain:{ *:[v8i16] } 3130:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQRDMLAHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
27967
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv8i16),
27968
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
27969
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
27970
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27971
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27972
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27973
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27974
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27975
0
        GIR_EraseFromParent, /*InsnID*/0,
27976
        // GIR_Coverage, 2480,
27977
0
        GIR_Done,
27978
      // Label 1468: @88273
27979
0
      GIM_Try, /*On fail goto*//*Label 1469*/ GIMT_Encode4(88356), // Rule ID 2481 //
27980
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
27981
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah),
27982
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27983
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27984
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
27985
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
27986
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27987
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27988
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27989
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27990
        // (intrinsic_wo_chain:{ *:[v4i32] } 3130:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQRDMLAHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
27991
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv4i32),
27992
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
27993
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
27994
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27995
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27996
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27997
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27998
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27999
0
        GIR_EraseFromParent, /*InsnID*/0,
28000
        // GIR_Coverage, 2481,
28001
0
        GIR_Done,
28002
      // Label 1469: @88356
28003
0
      GIM_Try, /*On fail goto*//*Label 1470*/ GIMT_Encode4(88439), // Rule ID 2486 //
28004
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
28005
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh),
28006
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
28007
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
28008
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
28009
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16,
28010
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28011
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28012
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28013
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28014
        // (intrinsic_wo_chain:{ *:[v4i16] } 3131:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQRDMLSHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
28015
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv4i16),
28016
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
28017
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28018
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28019
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28020
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28021
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28022
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28023
0
        GIR_EraseFromParent, /*InsnID*/0,
28024
        // GIR_Coverage, 2486,
28025
0
        GIR_Done,
28026
      // Label 1470: @88439
28027
0
      GIM_Try, /*On fail goto*//*Label 1471*/ GIMT_Encode4(88522), // Rule ID 2487 //
28028
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
28029
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh),
28030
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
28031
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
28032
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
28033
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s32,
28034
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28035
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28036
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28037
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28038
        // (intrinsic_wo_chain:{ *:[v2i32] } 3131:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQRDMLSHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
28039
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv2i32),
28040
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
28041
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28042
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28043
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28044
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28045
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28046
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28047
0
        GIR_EraseFromParent, /*InsnID*/0,
28048
        // GIR_Coverage, 2487,
28049
0
        GIR_Done,
28050
      // Label 1471: @88522
28051
0
      GIM_Try, /*On fail goto*//*Label 1472*/ GIMT_Encode4(88605), // Rule ID 2488 //
28052
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
28053
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh),
28054
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28055
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28056
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28057
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
28058
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28059
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28060
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28061
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28062
        // (intrinsic_wo_chain:{ *:[v8i16] } 3131:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQRDMLSHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
28063
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv8i16),
28064
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
28065
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28066
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28067
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28068
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28069
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28070
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28071
0
        GIR_EraseFromParent, /*InsnID*/0,
28072
        // GIR_Coverage, 2488,
28073
0
        GIR_Done,
28074
      // Label 1472: @88605
28075
0
      GIM_Try, /*On fail goto*//*Label 1473*/ GIMT_Encode4(88688), // Rule ID 2489 //
28076
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
28077
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh),
28078
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28079
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28080
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28081
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
28082
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28083
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28084
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28085
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28086
        // (intrinsic_wo_chain:{ *:[v4i32] } 3131:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQRDMLSHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
28087
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv4i32),
28088
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
28089
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28090
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28091
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28092
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28093
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28094
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28095
0
        GIR_EraseFromParent, /*InsnID*/0,
28096
        // GIR_Coverage, 2489,
28097
0
        GIR_Done,
28098
      // Label 1473: @88688
28099
0
      GIM_Try, /*On fail goto*//*Label 1474*/ GIMT_Encode4(88771), // Rule ID 2566 //
28100
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
28101
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vbsl),
28102
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
28103
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
28104
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
28105
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
28106
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28107
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28108
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28109
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28110
        // (intrinsic_wo_chain:{ *:[v8i8] } 3067:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VBSPd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
28111
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VBSPd),
28112
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
28113
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28114
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28115
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28116
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28117
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28118
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28119
0
        GIR_EraseFromParent, /*InsnID*/0,
28120
        // GIR_Coverage, 2566,
28121
0
        GIR_Done,
28122
      // Label 1474: @88771
28123
0
      GIM_Try, /*On fail goto*//*Label 1475*/ GIMT_Encode4(88854), // Rule ID 2567 //
28124
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
28125
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vbsl),
28126
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
28127
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
28128
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
28129
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16,
28130
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28131
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28132
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28133
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28134
        // (intrinsic_wo_chain:{ *:[v4i16] } 3067:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VBSPd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
28135
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VBSPd),
28136
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
28137
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28138
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28139
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28140
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28141
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28142
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28143
0
        GIR_EraseFromParent, /*InsnID*/0,
28144
        // GIR_Coverage, 2567,
28145
0
        GIR_Done,
28146
      // Label 1475: @88854
28147
0
      GIM_Try, /*On fail goto*//*Label 1476*/ GIMT_Encode4(88937), // Rule ID 2568 //
28148
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
28149
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vbsl),
28150
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
28151
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
28152
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
28153
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s32,
28154
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28155
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28156
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28157
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28158
        // (intrinsic_wo_chain:{ *:[v2i32] } 3067:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VBSPd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
28159
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VBSPd),
28160
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
28161
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28162
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28163
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28164
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28165
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28166
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28167
0
        GIR_EraseFromParent, /*InsnID*/0,
28168
        // GIR_Coverage, 2568,
28169
0
        GIR_Done,
28170
      // Label 1476: @88937
28171
0
      GIM_Try, /*On fail goto*//*Label 1477*/ GIMT_Encode4(89020), // Rule ID 2569 //
28172
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
28173
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vbsl),
28174
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
28175
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
28176
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
28177
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s32,
28178
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28179
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28180
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28181
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28182
        // (intrinsic_wo_chain:{ *:[v2f32] } 3067:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VBSPd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
28183
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VBSPd),
28184
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
28185
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28186
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28187
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28188
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28189
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28190
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28191
0
        GIR_EraseFromParent, /*InsnID*/0,
28192
        // GIR_Coverage, 2569,
28193
0
        GIR_Done,
28194
      // Label 1477: @89020
28195
0
      GIM_Try, /*On fail goto*//*Label 1478*/ GIMT_Encode4(89103), // Rule ID 2570 //
28196
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
28197
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vbsl),
28198
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
28199
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
28200
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
28201
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
28202
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28203
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28204
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28205
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28206
        // (intrinsic_wo_chain:{ *:[v1i64] } 3067:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VBSPd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
28207
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VBSPd),
28208
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
28209
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28210
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28211
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28212
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28213
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28214
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28215
0
        GIR_EraseFromParent, /*InsnID*/0,
28216
        // GIR_Coverage, 2570,
28217
0
        GIR_Done,
28218
      // Label 1478: @89103
28219
0
      GIM_Try, /*On fail goto*//*Label 1479*/ GIMT_Encode4(89186), // Rule ID 2575 //
28220
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
28221
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vbsl),
28222
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28223
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28224
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
28225
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
28226
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28227
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28228
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28229
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28230
        // (intrinsic_wo_chain:{ *:[v16i8] } 3067:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VBSPq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
28231
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VBSPq),
28232
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
28233
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28234
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28235
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28236
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28237
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28238
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28239
0
        GIR_EraseFromParent, /*InsnID*/0,
28240
        // GIR_Coverage, 2575,
28241
0
        GIR_Done,
28242
      // Label 1479: @89186
28243
0
      GIM_Try, /*On fail goto*//*Label 1480*/ GIMT_Encode4(89269), // Rule ID 2576 //
28244
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
28245
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vbsl),
28246
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28247
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28248
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28249
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
28250
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28251
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28252
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28253
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28254
        // (intrinsic_wo_chain:{ *:[v8i16] } 3067:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VBSPq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
28255
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VBSPq),
28256
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
28257
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28258
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28259
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28260
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28261
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28262
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28263
0
        GIR_EraseFromParent, /*InsnID*/0,
28264
        // GIR_Coverage, 2576,
28265
0
        GIR_Done,
28266
      // Label 1480: @89269
28267
0
      GIM_Try, /*On fail goto*//*Label 1481*/ GIMT_Encode4(89352), // Rule ID 2577 //
28268
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
28269
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vbsl),
28270
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28271
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28272
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28273
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
28274
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28275
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28276
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28277
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28278
        // (intrinsic_wo_chain:{ *:[v4i32] } 3067:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VBSPq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
28279
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VBSPq),
28280
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
28281
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28282
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28283
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28284
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28285
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28286
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28287
0
        GIR_EraseFromParent, /*InsnID*/0,
28288
        // GIR_Coverage, 2577,
28289
0
        GIR_Done,
28290
      // Label 1481: @89352
28291
0
      GIM_Try, /*On fail goto*//*Label 1482*/ GIMT_Encode4(89435), // Rule ID 2578 //
28292
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
28293
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vbsl),
28294
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28295
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28296
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28297
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
28298
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28299
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28300
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28301
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28302
        // (intrinsic_wo_chain:{ *:[v4f32] } 3067:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VBSPq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
28303
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VBSPq),
28304
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
28305
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28306
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28307
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28308
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28309
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28310
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28311
0
        GIR_EraseFromParent, /*InsnID*/0,
28312
        // GIR_Coverage, 2578,
28313
0
        GIR_Done,
28314
      // Label 1482: @89435
28315
0
      GIM_Try, /*On fail goto*//*Label 1483*/ GIMT_Encode4(89518), // Rule ID 2579 //
28316
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
28317
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vbsl),
28318
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
28319
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
28320
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
28321
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
28322
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28323
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28324
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28325
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28326
        // (intrinsic_wo_chain:{ *:[v2i64] } 3067:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VBSPq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
28327
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VBSPq),
28328
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
28329
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28330
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28331
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28332
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28333
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28334
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28335
0
        GIR_EraseFromParent, /*InsnID*/0,
28336
        // GIR_Coverage, 2579,
28337
0
        GIR_Done,
28338
      // Label 1483: @89518
28339
0
      GIM_Try, /*On fail goto*//*Label 1484*/ GIMT_Encode4(89607), // Rule ID 4966 //
28340
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28341
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlah),
28342
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28343
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28344
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
28345
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28346
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28347
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28348
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28349
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28350
        // (intrinsic_wo_chain:{ *:[v16i8] } 2981:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
28351
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs8),
28352
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
28353
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28354
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28355
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28356
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28357
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28358
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28359
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28360
0
        GIR_EraseFromParent, /*InsnID*/0,
28361
        // GIR_Coverage, 4966,
28362
0
        GIR_Done,
28363
      // Label 1484: @89607
28364
0
      GIM_Try, /*On fail goto*//*Label 1485*/ GIMT_Encode4(89696), // Rule ID 4968 //
28365
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28366
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlah),
28367
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28368
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28369
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28370
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28371
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28372
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28373
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28374
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28375
        // (intrinsic_wo_chain:{ *:[v8i16] } 2981:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
28376
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs16),
28377
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
28378
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28379
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28380
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28381
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28382
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28383
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28384
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28385
0
        GIR_EraseFromParent, /*InsnID*/0,
28386
        // GIR_Coverage, 4968,
28387
0
        GIR_Done,
28388
      // Label 1485: @89696
28389
0
      GIM_Try, /*On fail goto*//*Label 1486*/ GIMT_Encode4(89785), // Rule ID 4970 //
28390
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28391
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlah),
28392
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28393
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28394
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28395
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28396
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28397
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28398
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28399
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28400
        // (intrinsic_wo_chain:{ *:[v4i32] } 2981:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
28401
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs32),
28402
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
28403
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28404
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28405
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28406
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28407
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28408
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28409
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28410
0
        GIR_EraseFromParent, /*InsnID*/0,
28411
        // GIR_Coverage, 4970,
28412
0
        GIR_Done,
28413
      // Label 1486: @89785
28414
0
      GIM_Try, /*On fail goto*//*Label 1487*/ GIMT_Encode4(89874), // Rule ID 4972 //
28415
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28416
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlah),
28417
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28418
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28419
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
28420
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28421
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28422
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28423
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28424
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28425
        // (intrinsic_wo_chain:{ *:[v16i8] } 2990:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQRDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
28426
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs8),
28427
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
28428
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28429
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28430
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28431
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28432
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28433
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28434
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28435
0
        GIR_EraseFromParent, /*InsnID*/0,
28436
        // GIR_Coverage, 4972,
28437
0
        GIR_Done,
28438
      // Label 1487: @89874
28439
0
      GIM_Try, /*On fail goto*//*Label 1488*/ GIMT_Encode4(89963), // Rule ID 4974 //
28440
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28441
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlah),
28442
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28443
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28444
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28445
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28446
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28447
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28448
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28449
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28450
        // (intrinsic_wo_chain:{ *:[v8i16] } 2990:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQRDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
28451
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs16),
28452
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
28453
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28454
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28455
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28456
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28457
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28458
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28459
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28460
0
        GIR_EraseFromParent, /*InsnID*/0,
28461
        // GIR_Coverage, 4974,
28462
0
        GIR_Done,
28463
      // Label 1488: @89963
28464
0
      GIM_Try, /*On fail goto*//*Label 1489*/ GIMT_Encode4(90052), // Rule ID 4976 //
28465
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28466
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlah),
28467
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28468
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28469
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28470
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28471
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28472
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28473
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28474
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28475
        // (intrinsic_wo_chain:{ *:[v4i32] } 2990:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQRDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
28476
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs32),
28477
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
28478
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28479
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28480
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28481
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28482
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28483
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28484
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28485
0
        GIR_EraseFromParent, /*InsnID*/0,
28486
        // GIR_Coverage, 4976,
28487
0
        GIR_Done,
28488
      // Label 1489: @90052
28489
0
      GIM_Try, /*On fail goto*//*Label 1490*/ GIMT_Encode4(90141), // Rule ID 4978 //
28490
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28491
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlash),
28492
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28493
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28494
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
28495
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28496
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28497
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28498
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28499
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28500
        // (intrinsic_wo_chain:{ *:[v16i8] } 2983:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
28501
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs8),
28502
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
28503
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28504
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28505
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28506
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28507
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28508
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28509
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28510
0
        GIR_EraseFromParent, /*InsnID*/0,
28511
        // GIR_Coverage, 4978,
28512
0
        GIR_Done,
28513
      // Label 1490: @90141
28514
0
      GIM_Try, /*On fail goto*//*Label 1491*/ GIMT_Encode4(90230), // Rule ID 4980 //
28515
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28516
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlash),
28517
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28518
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28519
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28520
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28521
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28522
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28523
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28524
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28525
        // (intrinsic_wo_chain:{ *:[v8i16] } 2983:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
28526
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs16),
28527
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
28528
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28529
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28530
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28531
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28532
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28533
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28534
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28535
0
        GIR_EraseFromParent, /*InsnID*/0,
28536
        // GIR_Coverage, 4980,
28537
0
        GIR_Done,
28538
      // Label 1491: @90230
28539
0
      GIM_Try, /*On fail goto*//*Label 1492*/ GIMT_Encode4(90319), // Rule ID 4982 //
28540
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28541
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlash),
28542
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28543
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28544
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28545
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28546
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28547
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28548
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28549
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28550
        // (intrinsic_wo_chain:{ *:[v4i32] } 2983:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
28551
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs32),
28552
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
28553
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28554
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28555
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28556
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28557
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28558
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28559
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28560
0
        GIR_EraseFromParent, /*InsnID*/0,
28561
        // GIR_Coverage, 4982,
28562
0
        GIR_Done,
28563
      // Label 1492: @90319
28564
0
      GIM_Try, /*On fail goto*//*Label 1493*/ GIMT_Encode4(90408), // Rule ID 4984 //
28565
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28566
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlash),
28567
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28568
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28569
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
28570
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28571
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28572
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28573
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28574
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28575
        // (intrinsic_wo_chain:{ *:[v16i8] } 2992:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQRDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
28576
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs8),
28577
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
28578
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28579
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28580
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28581
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28582
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28583
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28584
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28585
0
        GIR_EraseFromParent, /*InsnID*/0,
28586
        // GIR_Coverage, 4984,
28587
0
        GIR_Done,
28588
      // Label 1493: @90408
28589
0
      GIM_Try, /*On fail goto*//*Label 1494*/ GIMT_Encode4(90497), // Rule ID 4986 //
28590
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28591
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlash),
28592
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28593
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28594
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28595
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28596
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28597
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28598
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28599
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28600
        // (intrinsic_wo_chain:{ *:[v8i16] } 2992:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQRDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
28601
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs16),
28602
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
28603
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28604
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28605
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28606
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28607
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28608
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28609
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28610
0
        GIR_EraseFromParent, /*InsnID*/0,
28611
        // GIR_Coverage, 4986,
28612
0
        GIR_Done,
28613
      // Label 1494: @90497
28614
0
      GIM_Try, /*On fail goto*//*Label 1495*/ GIMT_Encode4(90586), // Rule ID 4988 //
28615
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28616
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlash),
28617
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28618
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28619
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28620
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28621
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28622
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28623
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28624
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28625
        // (intrinsic_wo_chain:{ *:[v4i32] } 2992:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQRDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
28626
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs32),
28627
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
28628
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28629
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28630
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28631
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28632
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28633
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28634
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28635
0
        GIR_EraseFromParent, /*InsnID*/0,
28636
        // GIR_Coverage, 4988,
28637
0
        GIR_Done,
28638
      // Label 1495: @90586
28639
0
      GIM_Try, /*On fail goto*//*Label 1496*/ GIMT_Encode4(90693), // Rule ID 2721 //
28640
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
28641
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1c),
28642
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28643
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28644
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28645
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
28646
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28647
        // (intrinsic_wo_chain:{ *:[v4i32] } 3047:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk)  =>  (SHA1C:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
28648
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
28649
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
28650
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28651
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28652
0
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
28653
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
28654
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
28655
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28656
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
28657
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
28658
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/17,
28659
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
28660
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
28661
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SHA1C),
28662
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
28663
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // hash_abcd
28664
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28665
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wk
28666
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28667
0
        GIR_EraseFromParent, /*InsnID*/0,
28668
        // GIR_Coverage, 2721,
28669
0
        GIR_Done,
28670
      // Label 1496: @90693
28671
0
      GIM_Try, /*On fail goto*//*Label 1497*/ GIMT_Encode4(90800), // Rule ID 2722 //
28672
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
28673
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1m),
28674
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28675
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28676
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28677
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
28678
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28679
        // (intrinsic_wo_chain:{ *:[v4i32] } 3049:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk)  =>  (SHA1M:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
28680
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
28681
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
28682
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28683
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28684
0
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
28685
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
28686
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
28687
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28688
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
28689
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
28690
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/17,
28691
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
28692
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
28693
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SHA1M),
28694
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
28695
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // hash_abcd
28696
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28697
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wk
28698
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28699
0
        GIR_EraseFromParent, /*InsnID*/0,
28700
        // GIR_Coverage, 2722,
28701
0
        GIR_Done,
28702
      // Label 1497: @90800
28703
0
      GIM_Try, /*On fail goto*//*Label 1498*/ GIMT_Encode4(90907), // Rule ID 2723 //
28704
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
28705
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1p),
28706
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28707
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28708
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28709
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
28710
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28711
        // (intrinsic_wo_chain:{ *:[v4i32] } 3050:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk)  =>  (SHA1P:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
28712
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
28713
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
28714
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28715
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28716
0
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
28717
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
28718
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
28719
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28720
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
28721
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
28722
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/17,
28723
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
28724
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
28725
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SHA1P),
28726
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
28727
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // hash_abcd
28728
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28729
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wk
28730
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28731
0
        GIR_EraseFromParent, /*InsnID*/0,
28732
        // GIR_Coverage, 2723,
28733
0
        GIR_Done,
28734
      // Label 1498: @90907
28735
0
      GIM_Reject,
28736
    // Label 1336: @90908
28737
0
    GIM_Try, /*On fail goto*//*Label 1499*/ GIMT_Encode4(94916),
28738
0
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
28739
0
      GIM_Try, /*On fail goto*//*Label 1500*/ GIMT_Encode4(91013), // Rule ID 3851 //
28740
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
28741
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28742
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28743
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28744
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28745
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28746
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28747
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28748
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8,
28749
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
28750
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28751
        // (intrinsic_wo_chain:{ *:[v8i16] } 3022:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHLL_lws8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
28752
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28753
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28754
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
28755
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws8bh),
28756
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
28757
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
28758
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28759
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28760
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28761
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28762
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28763
0
        GIR_EraseFromParent, /*InsnID*/0,
28764
        // GIR_Coverage, 3851,
28765
0
        GIR_Done,
28766
      // Label 1500: @91013
28767
0
      GIM_Try, /*On fail goto*//*Label 1501*/ GIMT_Encode4(91110), // Rule ID 3855 //
28768
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
28769
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28770
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28771
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28772
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28773
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28774
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28775
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28776
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8,
28777
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
28778
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28779
        // (intrinsic_wo_chain:{ *:[v8i16] } 3022:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHLL_lws8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
28780
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28781
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28782
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
28783
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws8th),
28784
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
28785
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
28786
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28787
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28788
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28789
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28790
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28791
0
        GIR_EraseFromParent, /*InsnID*/0,
28792
        // GIR_Coverage, 3855,
28793
0
        GIR_Done,
28794
      // Label 1501: @91110
28795
0
      GIM_Try, /*On fail goto*//*Label 1502*/ GIMT_Encode4(91207), // Rule ID 3859 //
28796
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
28797
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28798
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28799
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28800
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28801
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28802
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28803
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28804
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16,
28805
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
28806
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28807
        // (intrinsic_wo_chain:{ *:[v4i32] } 3022:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHLL_lws16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
28808
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28809
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28810
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
28811
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws16bh),
28812
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
28813
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
28814
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28815
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28816
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28817
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28818
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28819
0
        GIR_EraseFromParent, /*InsnID*/0,
28820
        // GIR_Coverage, 3859,
28821
0
        GIR_Done,
28822
      // Label 1502: @91207
28823
0
      GIM_Try, /*On fail goto*//*Label 1503*/ GIMT_Encode4(91304), // Rule ID 3863 //
28824
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
28825
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28826
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28827
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28828
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28829
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28830
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28831
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28832
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16,
28833
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
28834
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28835
        // (intrinsic_wo_chain:{ *:[v4i32] } 3022:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHLL_lws16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
28836
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28837
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28838
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
28839
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws16th),
28840
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
28841
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
28842
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28843
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28844
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28845
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28846
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28847
0
        GIR_EraseFromParent, /*InsnID*/0,
28848
        // GIR_Coverage, 3863,
28849
0
        GIR_Done,
28850
      // Label 1503: @91304
28851
0
      GIM_Try, /*On fail goto*//*Label 1504*/ GIMT_Encode4(91401), // Rule ID 3867 //
28852
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
28853
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28854
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28855
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28856
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28857
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28858
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28859
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28860
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8,
28861
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
28862
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28863
        // (intrinsic_wo_chain:{ *:[v8i16] } 3022:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHLL_lwu8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
28864
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28865
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28866
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
28867
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu8bh),
28868
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
28869
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
28870
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28871
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28872
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28873
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28874
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28875
0
        GIR_EraseFromParent, /*InsnID*/0,
28876
        // GIR_Coverage, 3867,
28877
0
        GIR_Done,
28878
      // Label 1504: @91401
28879
0
      GIM_Try, /*On fail goto*//*Label 1505*/ GIMT_Encode4(91498), // Rule ID 3871 //
28880
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
28881
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28882
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28883
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28884
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28885
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28886
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28887
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28888
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8,
28889
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
28890
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28891
        // (intrinsic_wo_chain:{ *:[v8i16] } 3022:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHLL_lwu8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
28892
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28893
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28894
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
28895
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu8th),
28896
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
28897
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
28898
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28899
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28900
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28901
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28902
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28903
0
        GIR_EraseFromParent, /*InsnID*/0,
28904
        // GIR_Coverage, 3871,
28905
0
        GIR_Done,
28906
      // Label 1505: @91498
28907
0
      GIM_Try, /*On fail goto*//*Label 1506*/ GIMT_Encode4(91595), // Rule ID 3875 //
28908
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
28909
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28910
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28911
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28912
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28913
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28914
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28915
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28916
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16,
28917
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
28918
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28919
        // (intrinsic_wo_chain:{ *:[v4i32] } 3022:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHLL_lwu16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
28920
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28921
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28922
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
28923
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu16bh),
28924
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
28925
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
28926
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28927
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28928
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28929
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28930
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28931
0
        GIR_EraseFromParent, /*InsnID*/0,
28932
        // GIR_Coverage, 3875,
28933
0
        GIR_Done,
28934
      // Label 1506: @91595
28935
0
      GIM_Try, /*On fail goto*//*Label 1507*/ GIMT_Encode4(91692), // Rule ID 3879 //
28936
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
28937
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28938
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28939
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28940
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28941
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28942
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28943
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28944
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16,
28945
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
28946
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28947
        // (intrinsic_wo_chain:{ *:[v4i32] } 3022:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHLL_lwu16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
28948
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28949
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28950
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
28951
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu16th),
28952
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
28953
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
28954
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28955
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28956
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28957
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28958
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28959
0
        GIR_EraseFromParent, /*InsnID*/0,
28960
        // GIR_Coverage, 3879,
28961
0
        GIR_Done,
28962
      // Label 1507: @91692
28963
0
      GIM_Try, /*On fail goto*//*Label 1508*/ GIMT_Encode4(91797), // Rule ID 4511 //
28964
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28965
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
28966
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28967
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28968
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
28969
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28970
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28971
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28972
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28973
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28974
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
28975
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28976
        // (intrinsic_wo_chain:{ *:[v8i16] } 2977:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VMULLBs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
28977
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28978
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28979
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
28980
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs8),
28981
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
28982
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
28983
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
28984
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28985
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28986
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28987
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28988
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28989
0
        GIR_EraseFromParent, /*InsnID*/0,
28990
        // GIR_Coverage, 4511,
28991
0
        GIR_Done,
28992
      // Label 1508: @91797
28993
0
      GIM_Try, /*On fail goto*//*Label 1509*/ GIMT_Encode4(91902), // Rule ID 4513 //
28994
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28995
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
28996
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28997
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28998
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
28999
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29000
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29001
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29002
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29003
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29004
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29005
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29006
        // (intrinsic_wo_chain:{ *:[v8i16] } 2977:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VMULLTs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
29007
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29008
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29009
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
29010
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs8),
29011
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29012
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
29013
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
29014
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29015
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29016
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29017
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29018
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29019
0
        GIR_EraseFromParent, /*InsnID*/0,
29020
        // GIR_Coverage, 4513,
29021
0
        GIR_Done,
29022
      // Label 1509: @91902
29023
0
      GIM_Try, /*On fail goto*//*Label 1510*/ GIMT_Encode4(92007), // Rule ID 4515 //
29024
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29025
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29026
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29027
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29028
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29029
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29030
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29031
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29032
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29033
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29034
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29035
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29036
        // (intrinsic_wo_chain:{ *:[v4i32] } 2977:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VMULLBs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
29037
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29038
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29039
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
29040
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs16),
29041
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29042
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
29043
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
29044
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29045
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29046
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29047
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29048
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29049
0
        GIR_EraseFromParent, /*InsnID*/0,
29050
        // GIR_Coverage, 4515,
29051
0
        GIR_Done,
29052
      // Label 1510: @92007
29053
0
      GIM_Try, /*On fail goto*//*Label 1511*/ GIMT_Encode4(92112), // Rule ID 4517 //
29054
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29055
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29056
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29057
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29058
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29059
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29060
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29061
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29062
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29063
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29064
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29065
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29066
        // (intrinsic_wo_chain:{ *:[v4i32] } 2977:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VMULLTs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
29067
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29068
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29069
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
29070
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs16),
29071
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29072
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
29073
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
29074
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29075
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29076
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29077
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29078
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29079
0
        GIR_EraseFromParent, /*InsnID*/0,
29080
        // GIR_Coverage, 4517,
29081
0
        GIR_Done,
29082
      // Label 1511: @92112
29083
0
      GIM_Try, /*On fail goto*//*Label 1512*/ GIMT_Encode4(92217), // Rule ID 4519 //
29084
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29085
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29086
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
29087
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
29088
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29089
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29090
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29091
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29092
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29093
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29094
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29095
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29096
        // (intrinsic_wo_chain:{ *:[v2i64] } 2977:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VMULLBs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
29097
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29098
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29099
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
29100
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs32),
29101
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29102
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
29103
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
29104
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29105
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29106
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29107
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29108
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29109
0
        GIR_EraseFromParent, /*InsnID*/0,
29110
        // GIR_Coverage, 4519,
29111
0
        GIR_Done,
29112
      // Label 1512: @92217
29113
0
      GIM_Try, /*On fail goto*//*Label 1513*/ GIMT_Encode4(92322), // Rule ID 4521 //
29114
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29115
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29116
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
29117
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
29118
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29119
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29120
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29121
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29122
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29123
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29124
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29125
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29126
        // (intrinsic_wo_chain:{ *:[v2i64] } 2977:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VMULLTs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
29127
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29128
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29129
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
29130
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs32),
29131
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29132
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
29133
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
29134
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29135
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29136
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29137
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29138
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29139
0
        GIR_EraseFromParent, /*InsnID*/0,
29140
        // GIR_Coverage, 4521,
29141
0
        GIR_Done,
29142
      // Label 1513: @92322
29143
0
      GIM_Try, /*On fail goto*//*Label 1514*/ GIMT_Encode4(92427), // Rule ID 4523 //
29144
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29145
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29146
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29147
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29148
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
29149
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29150
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29151
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29152
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29153
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29154
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29155
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29156
        // (intrinsic_wo_chain:{ *:[v8i16] } 2977:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VMULLBu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
29157
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29158
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29159
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
29160
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu8),
29161
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29162
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
29163
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
29164
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29165
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29166
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29167
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29168
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29169
0
        GIR_EraseFromParent, /*InsnID*/0,
29170
        // GIR_Coverage, 4523,
29171
0
        GIR_Done,
29172
      // Label 1514: @92427
29173
0
      GIM_Try, /*On fail goto*//*Label 1515*/ GIMT_Encode4(92532), // Rule ID 4525 //
29174
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29175
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29176
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29177
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29178
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
29179
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29180
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29181
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29182
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29183
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29184
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29185
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29186
        // (intrinsic_wo_chain:{ *:[v8i16] } 2977:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VMULLTu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
29187
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29188
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29189
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
29190
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu8),
29191
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29192
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
29193
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
29194
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29195
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29196
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29197
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29198
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29199
0
        GIR_EraseFromParent, /*InsnID*/0,
29200
        // GIR_Coverage, 4525,
29201
0
        GIR_Done,
29202
      // Label 1515: @92532
29203
0
      GIM_Try, /*On fail goto*//*Label 1516*/ GIMT_Encode4(92637), // Rule ID 4527 //
29204
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29205
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29206
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29207
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29208
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29209
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29210
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29211
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29212
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29213
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29214
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29215
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29216
        // (intrinsic_wo_chain:{ *:[v4i32] } 2977:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VMULLBu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
29217
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29218
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29219
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
29220
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu16),
29221
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29222
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
29223
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
29224
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29225
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29226
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29227
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29228
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29229
0
        GIR_EraseFromParent, /*InsnID*/0,
29230
        // GIR_Coverage, 4527,
29231
0
        GIR_Done,
29232
      // Label 1516: @92637
29233
0
      GIM_Try, /*On fail goto*//*Label 1517*/ GIMT_Encode4(92742), // Rule ID 4529 //
29234
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29235
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29236
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29237
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29238
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29239
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29240
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29241
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29242
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29243
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29244
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29245
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29246
        // (intrinsic_wo_chain:{ *:[v4i32] } 2977:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VMULLTu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
29247
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29248
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29249
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
29250
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu16),
29251
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29252
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
29253
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
29254
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29255
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29256
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29257
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29258
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29259
0
        GIR_EraseFromParent, /*InsnID*/0,
29260
        // GIR_Coverage, 4529,
29261
0
        GIR_Done,
29262
      // Label 1517: @92742
29263
0
      GIM_Try, /*On fail goto*//*Label 1518*/ GIMT_Encode4(92847), // Rule ID 4531 //
29264
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29265
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29266
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
29267
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
29268
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29269
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29270
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29271
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29272
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29273
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29274
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29275
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29276
        // (intrinsic_wo_chain:{ *:[v2i64] } 2977:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VMULLBu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
29277
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29278
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29279
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
29280
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu32),
29281
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29282
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
29283
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
29284
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29285
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29286
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29287
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29288
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29289
0
        GIR_EraseFromParent, /*InsnID*/0,
29290
        // GIR_Coverage, 4531,
29291
0
        GIR_Done,
29292
      // Label 1518: @92847
29293
0
      GIM_Try, /*On fail goto*//*Label 1519*/ GIMT_Encode4(92952), // Rule ID 4533 //
29294
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29295
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29296
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
29297
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
29298
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29299
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29300
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29301
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29302
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29303
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29304
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29305
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29306
        // (intrinsic_wo_chain:{ *:[v2i64] } 2977:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VMULLTu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
29307
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29308
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29309
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
29310
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu32),
29311
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29312
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
29313
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
29314
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29315
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29316
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29317
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29318
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29319
0
        GIR_EraseFromParent, /*InsnID*/0,
29320
        // GIR_Coverage, 4533,
29321
0
        GIR_Done,
29322
      // Label 1519: @92952
29323
0
      GIM_Try, /*On fail goto*//*Label 1520*/ GIMT_Encode4(93066), // Rule ID 4156 //
29324
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
29325
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
29326
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29327
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29328
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29329
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
29330
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
29331
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29332
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
29333
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29334
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29335
        // MIs[1] Operand 1
29336
        // No operand predicates
29337
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29338
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29339
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
29340
        // (intrinsic_wo_chain:{ *:[v8f16] } 2920:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm)  =>  (MVE_VCADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
29341
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29342
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29343
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
29344
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDf16),
29345
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29346
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29347
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29348
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29349
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29350
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29351
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29352
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29353
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29354
0
        GIR_EraseFromParent, /*InsnID*/0,
29355
        // GIR_Coverage, 4156,
29356
0
        GIR_Done,
29357
      // Label 1520: @93066
29358
0
      GIM_Try, /*On fail goto*//*Label 1521*/ GIMT_Encode4(93180), // Rule ID 4158 //
29359
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
29360
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
29361
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29362
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29363
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29364
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
29365
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
29366
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29367
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
29368
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29369
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29370
        // MIs[1] Operand 1
29371
        // No operand predicates
29372
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29373
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29374
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
29375
        // (intrinsic_wo_chain:{ *:[v4f32] } 2920:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm)  =>  (MVE_VCADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
29376
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29377
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29378
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
29379
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDf32),
29380
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29381
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29382
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29383
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29384
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29385
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29386
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29387
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29388
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29389
0
        GIR_EraseFromParent, /*InsnID*/0,
29390
        // GIR_Coverage, 4158,
29391
0
        GIR_Done,
29392
      // Label 1521: @93180
29393
0
      GIM_Try, /*On fail goto*//*Label 1522*/ GIMT_Encode4(93294), // Rule ID 4665 //
29394
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29395
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
29396
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
29397
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29398
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29399
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
29400
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v16s8,
29401
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29402
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
29403
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29404
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29405
        // MIs[1] Operand 1
29406
        // No operand predicates
29407
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29408
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29409
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
29410
        // (intrinsic_wo_chain:{ *:[v16i8] } 2920:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VCADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot)
29411
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29412
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29413
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
29414
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi8),
29415
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29416
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29417
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29418
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29419
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29420
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29421
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29422
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29423
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29424
0
        GIR_EraseFromParent, /*InsnID*/0,
29425
        // GIR_Coverage, 4665,
29426
0
        GIR_Done,
29427
      // Label 1522: @93294
29428
0
      GIM_Try, /*On fail goto*//*Label 1523*/ GIMT_Encode4(93408), // Rule ID 4667 //
29429
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29430
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
29431
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29432
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29433
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29434
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
29435
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
29436
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29437
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
29438
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29439
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29440
        // MIs[1] Operand 1
29441
        // No operand predicates
29442
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29443
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29444
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
29445
        // (intrinsic_wo_chain:{ *:[v8i16] } 2920:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VCADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot)
29446
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29447
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29448
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
29449
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi16),
29450
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29451
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29452
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29453
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29454
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29455
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29456
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29457
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29458
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29459
0
        GIR_EraseFromParent, /*InsnID*/0,
29460
        // GIR_Coverage, 4667,
29461
0
        GIR_Done,
29462
      // Label 1523: @93408
29463
0
      GIM_Try, /*On fail goto*//*Label 1524*/ GIMT_Encode4(93522), // Rule ID 4669 //
29464
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29465
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
29466
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29467
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29468
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29469
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
29470
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
29471
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29472
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
29473
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29474
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29475
        // MIs[1] Operand 1
29476
        // No operand predicates
29477
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29478
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29479
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
29480
        // (intrinsic_wo_chain:{ *:[v4i32] } 2920:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VCADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot)
29481
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29482
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29483
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
29484
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi32),
29485
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29486
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29487
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29488
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29489
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29490
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29491
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29492
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29493
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29494
0
        GIR_EraseFromParent, /*InsnID*/0,
29495
        // GIR_Coverage, 4669,
29496
0
        GIR_Done,
29497
      // Label 1524: @93522
29498
0
      GIM_Try, /*On fail goto*//*Label 1525*/ GIMT_Encode4(93636), // Rule ID 4671 //
29499
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29500
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
29501
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
29502
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29503
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29504
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
29505
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v16s8,
29506
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29507
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
29508
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29509
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29510
        // MIs[1] Operand 1
29511
        // No operand predicates
29512
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29513
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29514
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
29515
        // (intrinsic_wo_chain:{ *:[v16i8] } 2920:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VHCADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot)
29516
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29517
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29518
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
29519
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs8),
29520
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29521
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29522
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29523
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29524
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29525
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29526
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29527
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29528
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29529
0
        GIR_EraseFromParent, /*InsnID*/0,
29530
        // GIR_Coverage, 4671,
29531
0
        GIR_Done,
29532
      // Label 1525: @93636
29533
0
      GIM_Try, /*On fail goto*//*Label 1526*/ GIMT_Encode4(93750), // Rule ID 4673 //
29534
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29535
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
29536
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29537
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29538
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29539
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
29540
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
29541
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29542
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
29543
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29544
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29545
        // MIs[1] Operand 1
29546
        // No operand predicates
29547
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29548
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29549
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
29550
        // (intrinsic_wo_chain:{ *:[v8i16] } 2920:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VHCADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot)
29551
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29552
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29553
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
29554
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs16),
29555
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29556
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29557
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29558
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29559
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29560
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29561
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29562
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29563
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29564
0
        GIR_EraseFromParent, /*InsnID*/0,
29565
        // GIR_Coverage, 4673,
29566
0
        GIR_Done,
29567
      // Label 1526: @93750
29568
0
      GIM_Try, /*On fail goto*//*Label 1527*/ GIMT_Encode4(93864), // Rule ID 4675 //
29569
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29570
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
29571
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29572
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29573
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29574
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
29575
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
29576
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29577
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
29578
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29579
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29580
        // MIs[1] Operand 1
29581
        // No operand predicates
29582
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29583
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29584
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
29585
        // (intrinsic_wo_chain:{ *:[v4i32] } 2920:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VHCADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot)
29586
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29587
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29588
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
29589
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs32),
29590
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29591
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29592
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29593
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29594
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29595
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29596
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29597
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29598
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29599
0
        GIR_EraseFromParent, /*InsnID*/0,
29600
        // GIR_Coverage, 4675,
29601
0
        GIR_Done,
29602
      // Label 1527: @93864
29603
0
      GIM_Try, /*On fail goto*//*Label 1528*/ GIMT_Encode4(93961), // Rule ID 3143 //
29604
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29605
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav),
29606
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
29607
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29608
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29609
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
29610
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v16s8,
29611
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29612
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
29613
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29614
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29615
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29616
        // (intrinsic_wo_chain:{ *:[i32] } 2913:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VABAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
29617
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs8),
29618
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rda]
29619
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
29620
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29621
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29622
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29623
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29624
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29625
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29626
0
        GIR_EraseFromParent, /*InsnID*/0,
29627
        // GIR_Coverage, 3143,
29628
0
        GIR_Done,
29629
      // Label 1528: @93961
29630
0
      GIM_Try, /*On fail goto*//*Label 1529*/ GIMT_Encode4(94058), // Rule ID 3145 //
29631
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29632
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav),
29633
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
29634
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29635
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29636
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
29637
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
29638
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29639
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
29640
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29641
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29642
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29643
        // (intrinsic_wo_chain:{ *:[i32] } 2913:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VABAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
29644
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs16),
29645
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rda]
29646
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
29647
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29648
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29649
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29650
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29651
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29652
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29653
0
        GIR_EraseFromParent, /*InsnID*/0,
29654
        // GIR_Coverage, 3145,
29655
0
        GIR_Done,
29656
      // Label 1529: @94058
29657
0
      GIM_Try, /*On fail goto*//*Label 1530*/ GIMT_Encode4(94155), // Rule ID 3147 //
29658
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29659
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav),
29660
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
29661
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29662
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29663
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
29664
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
29665
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29666
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
29667
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29668
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29669
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29670
        // (intrinsic_wo_chain:{ *:[i32] } 2913:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VABAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
29671
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs32),
29672
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rda]
29673
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
29674
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29675
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29676
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29677
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29678
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29679
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29680
0
        GIR_EraseFromParent, /*InsnID*/0,
29681
        // GIR_Coverage, 3147,
29682
0
        GIR_Done,
29683
      // Label 1530: @94155
29684
0
      GIM_Try, /*On fail goto*//*Label 1531*/ GIMT_Encode4(94252), // Rule ID 3149 //
29685
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29686
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav),
29687
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
29688
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29689
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29690
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
29691
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v16s8,
29692
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29693
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
29694
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29695
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29696
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29697
        // (intrinsic_wo_chain:{ *:[i32] } 2913:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VABAVu8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
29698
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu8),
29699
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rda]
29700
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
29701
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29702
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29703
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29704
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29705
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29706
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29707
0
        GIR_EraseFromParent, /*InsnID*/0,
29708
        // GIR_Coverage, 3149,
29709
0
        GIR_Done,
29710
      // Label 1531: @94252
29711
0
      GIM_Try, /*On fail goto*//*Label 1532*/ GIMT_Encode4(94349), // Rule ID 3151 //
29712
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29713
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav),
29714
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
29715
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29716
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29717
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
29718
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
29719
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29720
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
29721
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29722
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29723
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29724
        // (intrinsic_wo_chain:{ *:[i32] } 2913:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VABAVu16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
29725
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu16),
29726
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rda]
29727
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
29728
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29729
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29730
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29731
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29732
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29733
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29734
0
        GIR_EraseFromParent, /*InsnID*/0,
29735
        // GIR_Coverage, 3151,
29736
0
        GIR_Done,
29737
      // Label 1532: @94349
29738
0
      GIM_Try, /*On fail goto*//*Label 1533*/ GIMT_Encode4(94446), // Rule ID 3153 //
29739
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29740
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav),
29741
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
29742
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29743
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29744
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
29745
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
29746
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29747
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
29748
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29749
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29750
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29751
        // (intrinsic_wo_chain:{ *:[i32] } 2913:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VABAVu32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
29752
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu32),
29753
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rda]
29754
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
29755
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29756
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29757
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29758
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29759
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29760
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29761
0
        GIR_EraseFromParent, /*InsnID*/0,
29762
        // GIR_Coverage, 3153,
29763
0
        GIR_Done,
29764
      // Label 1533: @94446
29765
0
      GIM_Try, /*On fail goto*//*Label 1534*/ GIMT_Encode4(94552), // Rule ID 4120 //
29766
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
29767
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmlaq),
29768
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29769
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29770
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29771
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
29772
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
29773
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29774
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
29775
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29776
        // MIs[1] Operand 1
29777
        // No operand predicates
29778
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29779
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29780
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29781
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
29782
        // (intrinsic_wo_chain:{ *:[v8f16] } 2923:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm)  =>  (MVE_VCMLAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
29783
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf16),
29784
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29785
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qd_src
29786
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29787
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29788
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29789
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29790
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29791
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29792
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29793
0
        GIR_EraseFromParent, /*InsnID*/0,
29794
        // GIR_Coverage, 4120,
29795
0
        GIR_Done,
29796
      // Label 1534: @94552
29797
0
      GIM_Try, /*On fail goto*//*Label 1535*/ GIMT_Encode4(94658), // Rule ID 4123 //
29798
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
29799
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmlaq),
29800
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29801
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29802
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29803
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
29804
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
29805
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29806
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
29807
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29808
        // MIs[1] Operand 1
29809
        // No operand predicates
29810
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29811
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29812
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29813
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
29814
        // (intrinsic_wo_chain:{ *:[v4f32] } 2923:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm)  =>  (MVE_VCMLAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
29815
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf32),
29816
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29817
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qd_src
29818
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29819
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29820
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29821
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29822
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29823
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29824
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29825
0
        GIR_EraseFromParent, /*InsnID*/0,
29826
        // GIR_Coverage, 4123,
29827
0
        GIR_Done,
29828
      // Label 1535: @94658
29829
0
      GIM_Try, /*On fail goto*//*Label 1536*/ GIMT_Encode4(94770), // Rule ID 2715 //
29830
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
29831
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx2),
29832
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
29833
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
29834
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
29835
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
29836
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8,
29837
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
29838
        // (intrinsic_wo_chain:{ *:[v8i8] } 3179:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vm)  =>  (VTBX2:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v16i8] } DPair:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
29839
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
29840
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
29841
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29842
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
29843
0
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
29844
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
29845
0
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
29846
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
29847
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
29848
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
29849
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VTBX2),
29850
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
29851
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // orig
29852
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29853
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Vm
29854
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
29855
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29856
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29857
0
        GIR_EraseFromParent, /*InsnID*/0,
29858
        // GIR_Coverage, 2715,
29859
0
        GIR_Done,
29860
      // Label 1536: @94770
29861
0
      GIM_Try, /*On fail goto*//*Label 1537*/ GIMT_Encode4(94915), // Rule ID 2716 //
29862
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
29863
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbl3),
29864
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
29865
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
29866
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
29867
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
29868
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8,
29869
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
29870
        // (intrinsic_wo_chain:{ *:[v8i8] } 3176:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm)  =>  (VTBL3Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
29871
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
29872
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8,
29873
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29874
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29875
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
29876
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
29877
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29878
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0
29879
0
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
29880
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1
29881
0
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
29882
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2
29883
0
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
29884
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
29885
0
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
29886
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID),
29887
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
29888
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
29889
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID),
29890
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID),
29891
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VTBL3Pseudo),
29892
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
29893
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29894
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Vm
29895
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
29896
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29897
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29898
0
        GIR_EraseFromParent, /*InsnID*/0,
29899
        // GIR_Coverage, 2716,
29900
0
        GIR_Done,
29901
      // Label 1537: @94915
29902
0
      GIM_Reject,
29903
    // Label 1499: @94916
29904
0
    GIM_Try, /*On fail goto*//*Label 1538*/ GIMT_Encode4(101346),
29905
0
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
29906
0
      GIM_Try, /*On fail goto*//*Label 1539*/ GIMT_Encode4(95034), // Rule ID 3962 //
29907
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
29908
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
29909
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29910
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
29911
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29912
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29913
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29914
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29915
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29916
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29917
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29918
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29919
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29920
        // (intrinsic_wo_chain:{ *:[v16i8] } 3018:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29921
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29922
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29923
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
29924
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs8),
29925
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29926
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29927
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29928
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29929
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29930
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29931
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29932
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29933
0
        GIR_EraseFromParent, /*InsnID*/0,
29934
        // GIR_Coverage, 3962,
29935
0
        GIR_Done,
29936
      // Label 1539: @95034
29937
0
      GIM_Try, /*On fail goto*//*Label 1540*/ GIMT_Encode4(95144), // Rule ID 3964 //
29938
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
29939
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29940
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29941
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29942
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29943
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29944
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29945
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29946
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29947
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29948
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29949
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29950
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29951
        // (intrinsic_wo_chain:{ *:[v8i16] } 3018:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29952
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29953
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29954
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
29955
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs16),
29956
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29957
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29958
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29959
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29960
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29961
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29962
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29963
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29964
0
        GIR_EraseFromParent, /*InsnID*/0,
29965
        // GIR_Coverage, 3964,
29966
0
        GIR_Done,
29967
      // Label 1540: @95144
29968
0
      GIM_Try, /*On fail goto*//*Label 1541*/ GIMT_Encode4(95254), // Rule ID 3966 //
29969
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
29970
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29971
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
29972
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29973
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29974
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29975
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29976
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29977
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29978
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29979
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29980
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29981
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29982
        // (intrinsic_wo_chain:{ *:[v4i32] } 3018:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29983
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29984
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29985
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
29986
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs32),
29987
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
29988
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29989
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29990
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29991
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29992
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29993
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29994
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29995
0
        GIR_EraseFromParent, /*InsnID*/0,
29996
        // GIR_Coverage, 3966,
29997
0
        GIR_Done,
29998
      // Label 1541: @95254
29999
0
      GIM_Try, /*On fail goto*//*Label 1542*/ GIMT_Encode4(95364), // Rule ID 3968 //
30000
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30001
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30002
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30003
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
30004
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30005
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30006
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30007
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30008
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30009
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30010
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30011
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30012
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30013
        // (intrinsic_wo_chain:{ *:[v16i8] } 3018:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30014
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30015
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30016
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
30017
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu8),
30018
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30019
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30020
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30021
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30022
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30023
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30024
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30025
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30026
0
        GIR_EraseFromParent, /*InsnID*/0,
30027
        // GIR_Coverage, 3968,
30028
0
        GIR_Done,
30029
      // Label 1542: @95364
30030
0
      GIM_Try, /*On fail goto*//*Label 1543*/ GIMT_Encode4(95474), // Rule ID 3970 //
30031
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30032
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30033
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30034
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30035
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30036
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30037
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30038
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30039
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30040
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30041
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30042
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30043
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30044
        // (intrinsic_wo_chain:{ *:[v8i16] } 3018:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30045
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30046
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30047
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
30048
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu16),
30049
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30050
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30051
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30052
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30053
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30054
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30055
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30056
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30057
0
        GIR_EraseFromParent, /*InsnID*/0,
30058
        // GIR_Coverage, 3970,
30059
0
        GIR_Done,
30060
      // Label 1543: @95474
30061
0
      GIM_Try, /*On fail goto*//*Label 1544*/ GIMT_Encode4(95584), // Rule ID 3972 //
30062
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30063
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30064
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30065
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30066
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30067
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30068
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30069
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30070
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30071
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30072
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30073
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30074
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30075
        // (intrinsic_wo_chain:{ *:[v4i32] } 3018:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30076
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30077
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30078
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
30079
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu32),
30080
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30081
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30082
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30083
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30084
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30085
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30086
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30087
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30088
0
        GIR_EraseFromParent, /*InsnID*/0,
30089
        // GIR_Coverage, 3972,
30090
0
        GIR_Done,
30091
      // Label 1544: @95584
30092
0
      GIM_Try, /*On fail goto*//*Label 1545*/ GIMT_Encode4(95694), // Rule ID 3974 //
30093
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30094
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30095
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30096
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
30097
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30098
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30099
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30100
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30101
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30102
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30103
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30104
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30105
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30106
        // (intrinsic_wo_chain:{ *:[v16i8] } 3018:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30107
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30108
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30109
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
30110
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs8),
30111
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30112
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30113
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30114
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30115
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30116
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30117
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30118
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30119
0
        GIR_EraseFromParent, /*InsnID*/0,
30120
        // GIR_Coverage, 3974,
30121
0
        GIR_Done,
30122
      // Label 1545: @95694
30123
0
      GIM_Try, /*On fail goto*//*Label 1546*/ GIMT_Encode4(95804), // Rule ID 3976 //
30124
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30125
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30126
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30127
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30128
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30129
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30130
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30131
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30132
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30133
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30134
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30135
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30136
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30137
        // (intrinsic_wo_chain:{ *:[v8i16] } 3018:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30138
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30139
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30140
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
30141
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs16),
30142
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30143
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30144
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30145
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30146
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30147
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30148
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30149
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30150
0
        GIR_EraseFromParent, /*InsnID*/0,
30151
        // GIR_Coverage, 3976,
30152
0
        GIR_Done,
30153
      // Label 1546: @95804
30154
0
      GIM_Try, /*On fail goto*//*Label 1547*/ GIMT_Encode4(95914), // Rule ID 3978 //
30155
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30156
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30157
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30158
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30159
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30160
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30161
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30162
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30163
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30164
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30165
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30166
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30167
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30168
        // (intrinsic_wo_chain:{ *:[v4i32] } 3018:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30169
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30170
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30171
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
30172
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs32),
30173
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30174
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30175
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30176
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30177
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30178
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30179
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30180
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30181
0
        GIR_EraseFromParent, /*InsnID*/0,
30182
        // GIR_Coverage, 3978,
30183
0
        GIR_Done,
30184
      // Label 1547: @95914
30185
0
      GIM_Try, /*On fail goto*//*Label 1548*/ GIMT_Encode4(96024), // Rule ID 3980 //
30186
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30187
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30188
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30189
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
30190
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30191
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30192
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30193
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30194
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30195
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30196
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30197
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30198
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30199
        // (intrinsic_wo_chain:{ *:[v16i8] } 3018:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30200
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30201
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30202
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
30203
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu8),
30204
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30205
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30206
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30207
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30208
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30209
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30210
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30211
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30212
0
        GIR_EraseFromParent, /*InsnID*/0,
30213
        // GIR_Coverage, 3980,
30214
0
        GIR_Done,
30215
      // Label 1548: @96024
30216
0
      GIM_Try, /*On fail goto*//*Label 1549*/ GIMT_Encode4(96134), // Rule ID 3982 //
30217
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30218
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30219
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30220
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30221
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30222
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30223
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30224
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30225
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30226
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30227
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30228
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30229
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30230
        // (intrinsic_wo_chain:{ *:[v8i16] } 3018:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30231
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30232
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30233
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
30234
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu16),
30235
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30236
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30237
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30238
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30239
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30240
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30241
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30242
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30243
0
        GIR_EraseFromParent, /*InsnID*/0,
30244
        // GIR_Coverage, 3982,
30245
0
        GIR_Done,
30246
      // Label 1549: @96134
30247
0
      GIM_Try, /*On fail goto*//*Label 1550*/ GIMT_Encode4(96244), // Rule ID 3984 //
30248
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30249
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30250
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30251
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30252
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30253
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30254
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30255
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30256
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30257
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30258
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30259
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30260
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30261
        // (intrinsic_wo_chain:{ *:[v4i32] } 3018:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30262
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30263
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30264
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
30265
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu32),
30266
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30267
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30268
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30269
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30270
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30271
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30272
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30273
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30274
0
        GIR_EraseFromParent, /*InsnID*/0,
30275
        // GIR_Coverage, 3984,
30276
0
        GIR_Done,
30277
      // Label 1550: @96244
30278
0
      GIM_Try, /*On fail goto*//*Label 1551*/ GIMT_Encode4(96354), // Rule ID 3986 //
30279
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30280
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30281
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30282
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
30283
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30284
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30285
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30286
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30287
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30288
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30289
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30290
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30291
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30292
        // (intrinsic_wo_chain:{ *:[v16i8] } 3018:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30293
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30294
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30295
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
30296
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs8),
30297
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30298
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30299
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30300
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30301
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30302
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30303
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30304
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30305
0
        GIR_EraseFromParent, /*InsnID*/0,
30306
        // GIR_Coverage, 3986,
30307
0
        GIR_Done,
30308
      // Label 1551: @96354
30309
0
      GIM_Try, /*On fail goto*//*Label 1552*/ GIMT_Encode4(96464), // Rule ID 3988 //
30310
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30311
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30312
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30313
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30314
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30315
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30316
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30317
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30318
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30319
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30320
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30321
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30322
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30323
        // (intrinsic_wo_chain:{ *:[v8i16] } 3018:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30324
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30325
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30326
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
30327
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs16),
30328
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30329
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30330
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30331
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30332
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30333
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30334
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30335
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30336
0
        GIR_EraseFromParent, /*InsnID*/0,
30337
        // GIR_Coverage, 3988,
30338
0
        GIR_Done,
30339
      // Label 1552: @96464
30340
0
      GIM_Try, /*On fail goto*//*Label 1553*/ GIMT_Encode4(96574), // Rule ID 3990 //
30341
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30342
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30343
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30344
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30345
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30346
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30347
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30348
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30349
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30350
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30351
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30352
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30353
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30354
        // (intrinsic_wo_chain:{ *:[v4i32] } 3018:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30355
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30356
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30357
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
30358
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs32),
30359
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30360
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30361
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30362
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30363
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30364
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30365
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30366
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30367
0
        GIR_EraseFromParent, /*InsnID*/0,
30368
        // GIR_Coverage, 3990,
30369
0
        GIR_Done,
30370
      // Label 1553: @96574
30371
0
      GIM_Try, /*On fail goto*//*Label 1554*/ GIMT_Encode4(96684), // Rule ID 3992 //
30372
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30373
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30374
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30375
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
30376
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30377
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30378
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30379
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30380
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30381
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30382
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30383
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30384
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30385
        // (intrinsic_wo_chain:{ *:[v16i8] } 3018:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30386
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30387
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30388
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
30389
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu8),
30390
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30391
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30392
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30393
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30394
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30395
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30396
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30397
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30398
0
        GIR_EraseFromParent, /*InsnID*/0,
30399
        // GIR_Coverage, 3992,
30400
0
        GIR_Done,
30401
      // Label 1554: @96684
30402
0
      GIM_Try, /*On fail goto*//*Label 1555*/ GIMT_Encode4(96794), // Rule ID 3994 //
30403
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30404
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30405
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30406
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30407
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30408
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30409
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30410
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30411
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30412
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30413
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30414
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30415
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30416
        // (intrinsic_wo_chain:{ *:[v8i16] } 3018:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30417
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30418
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30419
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
30420
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu16),
30421
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30422
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30423
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30424
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30425
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30426
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30427
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30428
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30429
0
        GIR_EraseFromParent, /*InsnID*/0,
30430
        // GIR_Coverage, 3994,
30431
0
        GIR_Done,
30432
      // Label 1555: @96794
30433
0
      GIM_Try, /*On fail goto*//*Label 1556*/ GIMT_Encode4(96904), // Rule ID 3996 //
30434
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30435
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30436
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30437
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30438
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30439
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30440
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30441
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30442
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30443
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30444
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30445
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30446
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30447
        // (intrinsic_wo_chain:{ *:[v4i32] } 3018:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30448
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30449
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30450
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
30451
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu32),
30452
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30453
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30454
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30455
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30456
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30457
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30458
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30459
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30460
0
        GIR_EraseFromParent, /*InsnID*/0,
30461
        // GIR_Coverage, 3996,
30462
0
        GIR_Done,
30463
      // Label 1556: @96904
30464
0
      GIM_Try, /*On fail goto*//*Label 1557*/ GIMT_Encode4(97014), // Rule ID 3998 //
30465
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30466
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30467
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30468
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
30469
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30470
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30471
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30472
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30473
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30474
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30475
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30476
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30477
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30478
        // (intrinsic_wo_chain:{ *:[v16i8] } 3018:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30479
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30480
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30481
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
30482
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs8),
30483
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30484
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30485
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30486
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30487
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30488
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30489
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30490
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30491
0
        GIR_EraseFromParent, /*InsnID*/0,
30492
        // GIR_Coverage, 3998,
30493
0
        GIR_Done,
30494
      // Label 1557: @97014
30495
0
      GIM_Try, /*On fail goto*//*Label 1558*/ GIMT_Encode4(97124), // Rule ID 4000 //
30496
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30497
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30498
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30499
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30500
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30501
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30502
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30503
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30504
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30505
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30506
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30507
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30508
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30509
        // (intrinsic_wo_chain:{ *:[v8i16] } 3018:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30510
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30511
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30512
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
30513
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs16),
30514
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30515
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30516
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30517
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30518
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30519
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30520
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30521
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30522
0
        GIR_EraseFromParent, /*InsnID*/0,
30523
        // GIR_Coverage, 4000,
30524
0
        GIR_Done,
30525
      // Label 1558: @97124
30526
0
      GIM_Try, /*On fail goto*//*Label 1559*/ GIMT_Encode4(97234), // Rule ID 4002 //
30527
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30528
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30529
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30530
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30531
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30532
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30533
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30534
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30535
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30536
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30537
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30538
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30539
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30540
        // (intrinsic_wo_chain:{ *:[v4i32] } 3018:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30541
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30542
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30543
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
30544
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs32),
30545
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30546
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30547
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30548
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30549
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30550
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30551
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30552
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30553
0
        GIR_EraseFromParent, /*InsnID*/0,
30554
        // GIR_Coverage, 4002,
30555
0
        GIR_Done,
30556
      // Label 1559: @97234
30557
0
      GIM_Try, /*On fail goto*//*Label 1560*/ GIMT_Encode4(97344), // Rule ID 4004 //
30558
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30559
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30560
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30561
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
30562
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30563
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30564
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30565
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30566
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30567
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30568
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30569
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30570
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30571
        // (intrinsic_wo_chain:{ *:[v16i8] } 3018:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30572
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30573
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30574
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
30575
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu8),
30576
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30577
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30578
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30579
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30580
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30581
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30582
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30583
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30584
0
        GIR_EraseFromParent, /*InsnID*/0,
30585
        // GIR_Coverage, 4004,
30586
0
        GIR_Done,
30587
      // Label 1560: @97344
30588
0
      GIM_Try, /*On fail goto*//*Label 1561*/ GIMT_Encode4(97454), // Rule ID 4006 //
30589
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30590
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30591
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30592
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30593
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30594
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30595
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30596
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30597
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30598
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30599
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30600
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30601
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30602
        // (intrinsic_wo_chain:{ *:[v8i16] } 3018:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30603
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30604
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30605
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
30606
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu16),
30607
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30608
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30609
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30610
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30611
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30612
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30613
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30614
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30615
0
        GIR_EraseFromParent, /*InsnID*/0,
30616
        // GIR_Coverage, 4006,
30617
0
        GIR_Done,
30618
      // Label 1561: @97454
30619
0
      GIM_Try, /*On fail goto*//*Label 1562*/ GIMT_Encode4(97564), // Rule ID 4008 //
30620
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30621
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30622
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30623
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30624
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30625
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30626
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30627
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30628
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30629
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30630
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30631
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30632
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30633
        // (intrinsic_wo_chain:{ *:[v4i32] } 3018:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30634
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30635
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30636
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
30637
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu32),
30638
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30639
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30640
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30641
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30642
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30643
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30644
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30645
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30646
0
        GIR_EraseFromParent, /*InsnID*/0,
30647
        // GIR_Coverage, 4008,
30648
0
        GIR_Done,
30649
      // Label 1562: @97564
30650
0
      GIM_Try, /*On fail goto*//*Label 1563*/ GIMT_Encode4(97661), // Rule ID 4613 //
30651
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
30652
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30653
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30654
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30655
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30656
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30657
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30658
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30659
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30660
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30661
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30662
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30663
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30664
        // (intrinsic_wo_chain:{ *:[v8i16] } 2988:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQMOVNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30665
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs32bh),
30666
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30667
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30668
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30669
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30670
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30671
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30672
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30673
0
        GIR_EraseFromParent, /*InsnID*/0,
30674
        // GIR_Coverage, 4613,
30675
0
        GIR_Done,
30676
      // Label 1563: @97661
30677
0
      GIM_Try, /*On fail goto*//*Label 1564*/ GIMT_Encode4(97758), // Rule ID 4615 //
30678
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
30679
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30680
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30681
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30682
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30683
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30684
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30685
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30686
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30687
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30688
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30689
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30690
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30691
        // (intrinsic_wo_chain:{ *:[v8i16] } 2988:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQMOVNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30692
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs32th),
30693
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30694
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30695
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30696
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30697
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30698
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30699
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30700
0
        GIR_EraseFromParent, /*InsnID*/0,
30701
        // GIR_Coverage, 4615,
30702
0
        GIR_Done,
30703
      // Label 1564: @97758
30704
0
      GIM_Try, /*On fail goto*//*Label 1565*/ GIMT_Encode4(97855), // Rule ID 4617 //
30705
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
30706
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30707
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30708
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30709
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30710
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30711
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30712
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30713
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30714
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30715
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30716
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30717
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30718
        // (intrinsic_wo_chain:{ *:[v16i8] } 2988:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQMOVNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
30719
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs16bh),
30720
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30721
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30722
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30723
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30724
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30725
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30726
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30727
0
        GIR_EraseFromParent, /*InsnID*/0,
30728
        // GIR_Coverage, 4617,
30729
0
        GIR_Done,
30730
      // Label 1565: @97855
30731
0
      GIM_Try, /*On fail goto*//*Label 1566*/ GIMT_Encode4(97952), // Rule ID 4619 //
30732
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
30733
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30734
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30735
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30736
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30737
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30738
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30739
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30740
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30741
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30742
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30743
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30744
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30745
        // (intrinsic_wo_chain:{ *:[v16i8] } 2988:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQMOVNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
30746
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs16th),
30747
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30748
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30749
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30750
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30751
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30752
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30753
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30754
0
        GIR_EraseFromParent, /*InsnID*/0,
30755
        // GIR_Coverage, 4619,
30756
0
        GIR_Done,
30757
      // Label 1566: @97952
30758
0
      GIM_Try, /*On fail goto*//*Label 1567*/ GIMT_Encode4(98049), // Rule ID 4621 //
30759
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
30760
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30761
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30762
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30763
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30764
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30765
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30766
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30767
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30768
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30769
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30770
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30771
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30772
        // (intrinsic_wo_chain:{ *:[v8i16] } 2988:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQMOVNu32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30773
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu32bh),
30774
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30775
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30776
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30777
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30778
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30779
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30780
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30781
0
        GIR_EraseFromParent, /*InsnID*/0,
30782
        // GIR_Coverage, 4621,
30783
0
        GIR_Done,
30784
      // Label 1567: @98049
30785
0
      GIM_Try, /*On fail goto*//*Label 1568*/ GIMT_Encode4(98146), // Rule ID 4623 //
30786
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
30787
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30788
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30789
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30790
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30791
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30792
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30793
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30794
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30795
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30796
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30797
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30798
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30799
        // (intrinsic_wo_chain:{ *:[v8i16] } 2988:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQMOVNu32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30800
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu32th),
30801
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30802
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30803
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30804
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30805
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30806
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30807
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30808
0
        GIR_EraseFromParent, /*InsnID*/0,
30809
        // GIR_Coverage, 4623,
30810
0
        GIR_Done,
30811
      // Label 1568: @98146
30812
0
      GIM_Try, /*On fail goto*//*Label 1569*/ GIMT_Encode4(98243), // Rule ID 4625 //
30813
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
30814
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30815
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30816
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30817
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30818
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30819
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30820
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30821
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30822
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30823
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30824
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30825
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30826
        // (intrinsic_wo_chain:{ *:[v16i8] } 2988:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQMOVNu16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
30827
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu16bh),
30828
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30829
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30830
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30831
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30832
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30833
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30834
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30835
0
        GIR_EraseFromParent, /*InsnID*/0,
30836
        // GIR_Coverage, 4625,
30837
0
        GIR_Done,
30838
      // Label 1569: @98243
30839
0
      GIM_Try, /*On fail goto*//*Label 1570*/ GIMT_Encode4(98340), // Rule ID 4627 //
30840
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
30841
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30842
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30843
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30844
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30845
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30846
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30847
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30848
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30849
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30850
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30851
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30852
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30853
        // (intrinsic_wo_chain:{ *:[v16i8] } 2988:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQMOVNu16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
30854
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu16th),
30855
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30856
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30857
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30858
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30859
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30860
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30861
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30862
0
        GIR_EraseFromParent, /*InsnID*/0,
30863
        // GIR_Coverage, 4627,
30864
0
        GIR_Done,
30865
      // Label 1570: @98340
30866
0
      GIM_Try, /*On fail goto*//*Label 1571*/ GIMT_Encode4(98437), // Rule ID 4629 //
30867
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
30868
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30869
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30870
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30871
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30872
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30873
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30874
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30875
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30876
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30877
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30878
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30879
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30880
        // (intrinsic_wo_chain:{ *:[v8i16] } 2988:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQMOVUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30881
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs32bh),
30882
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30883
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30884
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30885
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30886
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30887
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30888
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30889
0
        GIR_EraseFromParent, /*InsnID*/0,
30890
        // GIR_Coverage, 4629,
30891
0
        GIR_Done,
30892
      // Label 1571: @98437
30893
0
      GIM_Try, /*On fail goto*//*Label 1572*/ GIMT_Encode4(98534), // Rule ID 4631 //
30894
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
30895
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30896
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30897
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30898
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30899
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30900
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30901
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30902
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30903
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30904
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30905
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30906
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30907
        // (intrinsic_wo_chain:{ *:[v8i16] } 2988:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQMOVUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30908
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs32th),
30909
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30910
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30911
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30912
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30913
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30914
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30915
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30916
0
        GIR_EraseFromParent, /*InsnID*/0,
30917
        // GIR_Coverage, 4631,
30918
0
        GIR_Done,
30919
      // Label 1572: @98534
30920
0
      GIM_Try, /*On fail goto*//*Label 1573*/ GIMT_Encode4(98631), // Rule ID 4633 //
30921
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
30922
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30923
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30924
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30925
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30926
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30927
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30928
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30929
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30930
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30931
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30932
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30933
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30934
        // (intrinsic_wo_chain:{ *:[v16i8] } 2988:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQMOVUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
30935
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs16bh),
30936
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30937
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30938
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30939
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30940
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30941
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30942
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30943
0
        GIR_EraseFromParent, /*InsnID*/0,
30944
        // GIR_Coverage, 4633,
30945
0
        GIR_Done,
30946
      // Label 1573: @98631
30947
0
      GIM_Try, /*On fail goto*//*Label 1574*/ GIMT_Encode4(98728), // Rule ID 4635 //
30948
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
30949
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30950
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30951
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30952
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30953
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30954
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30955
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30956
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30957
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30958
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30959
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30960
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30961
        // (intrinsic_wo_chain:{ *:[v16i8] } 2988:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQMOVUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
30962
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs16th),
30963
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30964
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30965
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30966
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30967
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30968
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30969
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30970
0
        GIR_EraseFromParent, /*InsnID*/0,
30971
        // GIR_Coverage, 4635,
30972
0
        GIR_Done,
30973
      // Label 1574: @98728
30974
0
      GIM_Try, /*On fail goto*//*Label 1575*/ GIMT_Encode4(98825), // Rule ID 4825 //
30975
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
30976
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30977
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30978
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30979
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30980
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30981
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30982
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30983
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30984
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30985
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30986
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30987
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30988
        // (intrinsic_wo_chain:{ *:[v16i8] } 3016:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30989
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs8),
30990
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
30991
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30992
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30993
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30994
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30995
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30996
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30997
0
        GIR_EraseFromParent, /*InsnID*/0,
30998
        // GIR_Coverage, 4825,
30999
0
        GIR_Done,
31000
      // Label 1575: @98825
31001
0
      GIM_Try, /*On fail goto*//*Label 1576*/ GIMT_Encode4(98922), // Rule ID 4827 //
31002
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31003
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31004
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
31005
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31006
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31007
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31008
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31009
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31010
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31011
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31012
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31013
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31014
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31015
        // (intrinsic_wo_chain:{ *:[v8i16] } 3016:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31016
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs16),
31017
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
31018
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31019
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31020
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31021
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31022
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31023
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31024
0
        GIR_EraseFromParent, /*InsnID*/0,
31025
        // GIR_Coverage, 4827,
31026
0
        GIR_Done,
31027
      // Label 1576: @98922
31028
0
      GIM_Try, /*On fail goto*//*Label 1577*/ GIMT_Encode4(99019), // Rule ID 4829 //
31029
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31030
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31031
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
31032
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31033
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31034
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31035
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31036
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31037
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31038
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31039
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31040
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31041
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31042
        // (intrinsic_wo_chain:{ *:[v4i32] } 3016:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31043
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs32),
31044
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
31045
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31046
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31047
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31048
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31049
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31050
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31051
0
        GIR_EraseFromParent, /*InsnID*/0,
31052
        // GIR_Coverage, 4829,
31053
0
        GIR_Done,
31054
      // Label 1577: @99019
31055
0
      GIM_Try, /*On fail goto*//*Label 1578*/ GIMT_Encode4(99116), // Rule ID 4831 //
31056
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31057
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
31058
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
31059
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31060
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31061
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31062
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31063
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31064
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31065
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31066
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31067
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31068
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31069
        // (intrinsic_wo_chain:{ *:[v16i8] } 3016:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31070
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru8),
31071
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
31072
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31073
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31074
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31075
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31076
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31077
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31078
0
        GIR_EraseFromParent, /*InsnID*/0,
31079
        // GIR_Coverage, 4831,
31080
0
        GIR_Done,
31081
      // Label 1578: @99116
31082
0
      GIM_Try, /*On fail goto*//*Label 1579*/ GIMT_Encode4(99213), // Rule ID 4833 //
31083
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31084
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31085
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
31086
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31087
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31088
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31089
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31090
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31091
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31092
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31093
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31094
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31095
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31096
        // (intrinsic_wo_chain:{ *:[v8i16] } 3016:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31097
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru16),
31098
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
31099
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31100
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31101
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31102
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31103
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31104
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31105
0
        GIR_EraseFromParent, /*InsnID*/0,
31106
        // GIR_Coverage, 4833,
31107
0
        GIR_Done,
31108
      // Label 1579: @99213
31109
0
      GIM_Try, /*On fail goto*//*Label 1580*/ GIMT_Encode4(99310), // Rule ID 4835 //
31110
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31111
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31112
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
31113
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31114
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31115
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31116
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31117
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31118
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31119
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31120
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31121
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31122
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31123
        // (intrinsic_wo_chain:{ *:[v4i32] } 3016:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31124
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru32),
31125
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
31126
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31127
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31128
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31129
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31130
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31131
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31132
0
        GIR_EraseFromParent, /*InsnID*/0,
31133
        // GIR_Coverage, 4835,
31134
0
        GIR_Done,
31135
      // Label 1580: @99310
31136
0
      GIM_Try, /*On fail goto*//*Label 1581*/ GIMT_Encode4(99407), // Rule ID 4837 //
31137
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31138
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
31139
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
31140
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31141
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31142
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31143
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31144
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31145
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31146
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31147
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31148
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31149
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31150
        // (intrinsic_wo_chain:{ *:[v16i8] } 3016:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31151
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs8),
31152
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
31153
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31154
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31155
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31156
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31157
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31158
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31159
0
        GIR_EraseFromParent, /*InsnID*/0,
31160
        // GIR_Coverage, 4837,
31161
0
        GIR_Done,
31162
      // Label 1581: @99407
31163
0
      GIM_Try, /*On fail goto*//*Label 1582*/ GIMT_Encode4(99504), // Rule ID 4839 //
31164
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31165
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31166
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
31167
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31168
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31169
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31170
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31171
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31172
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31173
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31174
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31175
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31176
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31177
        // (intrinsic_wo_chain:{ *:[v8i16] } 3016:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31178
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs16),
31179
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
31180
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31181
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31182
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31183
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31184
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31185
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31186
0
        GIR_EraseFromParent, /*InsnID*/0,
31187
        // GIR_Coverage, 4839,
31188
0
        GIR_Done,
31189
      // Label 1582: @99504
31190
0
      GIM_Try, /*On fail goto*//*Label 1583*/ GIMT_Encode4(99601), // Rule ID 4841 //
31191
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31192
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31193
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
31194
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31195
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31196
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31197
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31198
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31199
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31200
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31201
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31202
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31203
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31204
        // (intrinsic_wo_chain:{ *:[v4i32] } 3016:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31205
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs32),
31206
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
31207
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31208
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31209
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31210
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31211
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31212
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31213
0
        GIR_EraseFromParent, /*InsnID*/0,
31214
        // GIR_Coverage, 4841,
31215
0
        GIR_Done,
31216
      // Label 1583: @99601
31217
0
      GIM_Try, /*On fail goto*//*Label 1584*/ GIMT_Encode4(99698), // Rule ID 4843 //
31218
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31219
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
31220
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
31221
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31222
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31223
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31224
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31225
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31226
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31227
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31228
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31229
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31230
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31231
        // (intrinsic_wo_chain:{ *:[v16i8] } 3016:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31232
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru8),
31233
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
31234
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31235
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31236
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31237
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31238
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31239
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31240
0
        GIR_EraseFromParent, /*InsnID*/0,
31241
        // GIR_Coverage, 4843,
31242
0
        GIR_Done,
31243
      // Label 1584: @99698
31244
0
      GIM_Try, /*On fail goto*//*Label 1585*/ GIMT_Encode4(99795), // Rule ID 4845 //
31245
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31246
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31247
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
31248
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31249
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31250
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31251
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31252
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31253
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31254
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31255
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31256
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31257
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31258
        // (intrinsic_wo_chain:{ *:[v8i16] } 3016:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31259
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru16),
31260
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
31261
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31262
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31263
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31264
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31265
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31266
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31267
0
        GIR_EraseFromParent, /*InsnID*/0,
31268
        // GIR_Coverage, 4845,
31269
0
        GIR_Done,
31270
      // Label 1585: @99795
31271
0
      GIM_Try, /*On fail goto*//*Label 1586*/ GIMT_Encode4(99892), // Rule ID 4847 //
31272
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31273
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31274
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
31275
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31276
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31277
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31278
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31279
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31280
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31281
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31282
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31283
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31284
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31285
        // (intrinsic_wo_chain:{ *:[v4i32] } 3016:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31286
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru32),
31287
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
31288
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31289
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31290
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31291
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31292
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31293
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31294
0
        GIR_EraseFromParent, /*InsnID*/0,
31295
        // GIR_Coverage, 4847,
31296
0
        GIR_Done,
31297
      // Label 1586: @99892
31298
0
      GIM_Try, /*On fail goto*//*Label 1587*/ GIMT_Encode4(99989), // Rule ID 4849 //
31299
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31300
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
31301
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
31302
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31303
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31304
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31305
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31306
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31307
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31308
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31309
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31310
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31311
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31312
        // (intrinsic_wo_chain:{ *:[v16i8] } 3016:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31313
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs8),
31314
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
31315
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31316
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31317
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31318
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31319
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31320
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31321
0
        GIR_EraseFromParent, /*InsnID*/0,
31322
        // GIR_Coverage, 4849,
31323
0
        GIR_Done,
31324
      // Label 1587: @99989
31325
0
      GIM_Try, /*On fail goto*//*Label 1588*/ GIMT_Encode4(100086), // Rule ID 4851 //
31326
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31327
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31328
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
31329
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31330
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31331
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31332
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31333
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31334
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31335
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31336
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31337
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31338
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31339
        // (intrinsic_wo_chain:{ *:[v8i16] } 3016:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31340
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs16),
31341
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
31342
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31343
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31344
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31345
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31346
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31347
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31348
0
        GIR_EraseFromParent, /*InsnID*/0,
31349
        // GIR_Coverage, 4851,
31350
0
        GIR_Done,
31351
      // Label 1588: @100086
31352
0
      GIM_Try, /*On fail goto*//*Label 1589*/ GIMT_Encode4(100183), // Rule ID 4853 //
31353
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31354
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31355
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
31356
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31357
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31358
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31359
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31360
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31361
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31362
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31363
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31364
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31365
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31366
        // (intrinsic_wo_chain:{ *:[v4i32] } 3016:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31367
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs32),
31368
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
31369
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31370
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31371
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31372
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31373
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31374
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31375
0
        GIR_EraseFromParent, /*InsnID*/0,
31376
        // GIR_Coverage, 4853,
31377
0
        GIR_Done,
31378
      // Label 1589: @100183
31379
0
      GIM_Try, /*On fail goto*//*Label 1590*/ GIMT_Encode4(100280), // Rule ID 4855 //
31380
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31381
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
31382
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
31383
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31384
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31385
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31386
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31387
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31388
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31389
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31390
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31391
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31392
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31393
        // (intrinsic_wo_chain:{ *:[v16i8] } 3016:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31394
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru8),
31395
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
31396
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31397
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31398
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31399
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31400
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31401
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31402
0
        GIR_EraseFromParent, /*InsnID*/0,
31403
        // GIR_Coverage, 4855,
31404
0
        GIR_Done,
31405
      // Label 1590: @100280
31406
0
      GIM_Try, /*On fail goto*//*Label 1591*/ GIMT_Encode4(100377), // Rule ID 4857 //
31407
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31408
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31409
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
31410
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31411
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31412
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31413
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31414
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31415
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31416
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31417
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31418
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31419
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31420
        // (intrinsic_wo_chain:{ *:[v8i16] } 3016:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31421
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru16),
31422
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
31423
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31424
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31425
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31426
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31427
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31428
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31429
0
        GIR_EraseFromParent, /*InsnID*/0,
31430
        // GIR_Coverage, 4857,
31431
0
        GIR_Done,
31432
      // Label 1591: @100377
31433
0
      GIM_Try, /*On fail goto*//*Label 1592*/ GIMT_Encode4(100474), // Rule ID 4859 //
31434
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31435
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31436
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
31437
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31438
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31439
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31440
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31441
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31442
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31443
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31444
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31445
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31446
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31447
        // (intrinsic_wo_chain:{ *:[v4i32] } 3016:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31448
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru32),
31449
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
31450
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31451
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31452
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31453
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31454
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31455
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31456
0
        GIR_EraseFromParent, /*InsnID*/0,
31457
        // GIR_Coverage, 4859,
31458
0
        GIR_Done,
31459
      // Label 1592: @100474
31460
0
      GIM_Try, /*On fail goto*//*Label 1593*/ GIMT_Encode4(100571), // Rule ID 4861 //
31461
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31462
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
31463
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
31464
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31465
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31466
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31467
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31468
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31469
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31470
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31471
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31472
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31473
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31474
        // (intrinsic_wo_chain:{ *:[v16i8] } 3016:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31475
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs8),
31476
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
31477
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31478
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31479
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31480
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31481
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31482
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31483
0
        GIR_EraseFromParent, /*InsnID*/0,
31484
        // GIR_Coverage, 4861,
31485
0
        GIR_Done,
31486
      // Label 1593: @100571
31487
0
      GIM_Try, /*On fail goto*//*Label 1594*/ GIMT_Encode4(100668), // Rule ID 4863 //
31488
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31489
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31490
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
31491
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31492
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31493
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31494
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31495
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31496
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31497
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31498
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31499
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31500
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31501
        // (intrinsic_wo_chain:{ *:[v8i16] } 3016:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31502
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs16),
31503
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
31504
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31505
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31506
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31507
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31508
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31509
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31510
0
        GIR_EraseFromParent, /*InsnID*/0,
31511
        // GIR_Coverage, 4863,
31512
0
        GIR_Done,
31513
      // Label 1594: @100668
31514
0
      GIM_Try, /*On fail goto*//*Label 1595*/ GIMT_Encode4(100765), // Rule ID 4865 //
31515
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31516
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31517
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
31518
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31519
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31520
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31521
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31522
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31523
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31524
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31525
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31526
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31527
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31528
        // (intrinsic_wo_chain:{ *:[v4i32] } 3016:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31529
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs32),
31530
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
31531
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31532
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31533
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31534
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31535
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31536
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31537
0
        GIR_EraseFromParent, /*InsnID*/0,
31538
        // GIR_Coverage, 4865,
31539
0
        GIR_Done,
31540
      // Label 1595: @100765
31541
0
      GIM_Try, /*On fail goto*//*Label 1596*/ GIMT_Encode4(100862), // Rule ID 4867 //
31542
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31543
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
31544
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
31545
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31546
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31547
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31548
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31549
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31550
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31551
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31552
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31553
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31554
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31555
        // (intrinsic_wo_chain:{ *:[v16i8] } 3016:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31556
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru8),
31557
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
31558
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31559
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31560
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31561
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31562
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31563
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31564
0
        GIR_EraseFromParent, /*InsnID*/0,
31565
        // GIR_Coverage, 4867,
31566
0
        GIR_Done,
31567
      // Label 1596: @100862
31568
0
      GIM_Try, /*On fail goto*//*Label 1597*/ GIMT_Encode4(100959), // Rule ID 4869 //
31569
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31570
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31571
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
31572
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31573
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31574
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31575
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31576
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31577
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31578
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31579
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31580
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31581
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31582
        // (intrinsic_wo_chain:{ *:[v8i16] } 3016:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31583
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru16),
31584
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
31585
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31586
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31587
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31588
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31589
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31590
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31591
0
        GIR_EraseFromParent, /*InsnID*/0,
31592
        // GIR_Coverage, 4869,
31593
0
        GIR_Done,
31594
      // Label 1597: @100959
31595
0
      GIM_Try, /*On fail goto*//*Label 1598*/ GIMT_Encode4(101056), // Rule ID 4871 //
31596
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31597
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31598
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
31599
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31600
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31601
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31602
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31603
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31604
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31605
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31606
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31607
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31608
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31609
        // (intrinsic_wo_chain:{ *:[v4i32] } 3016:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31610
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru32),
31611
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
31612
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31613
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31614
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31615
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31616
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31617
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31618
0
        GIR_EraseFromParent, /*InsnID*/0,
31619
        // GIR_Coverage, 4871,
31620
0
        GIR_Done,
31621
      // Label 1598: @101056
31622
0
      GIM_Try, /*On fail goto*//*Label 1599*/ GIMT_Encode4(101209), // Rule ID 2717 //
31623
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
31624
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx3),
31625
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
31626
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
31627
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
31628
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
31629
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8,
31630
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s8,
31631
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
31632
        // (intrinsic_wo_chain:{ *:[v8i8] } 3180:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm)  =>  (VTBX3Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
31633
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
31634
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8,
31635
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
31636
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31637
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
31638
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
31639
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31640
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
31641
0
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
31642
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
31643
0
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
31644
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2
31645
0
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
31646
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
31647
0
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
31648
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID),
31649
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
31650
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
31651
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID),
31652
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID),
31653
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VTBX3Pseudo),
31654
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
31655
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // orig
31656
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31657
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Vm
31658
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
31659
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31660
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31661
0
        GIR_EraseFromParent, /*InsnID*/0,
31662
        // GIR_Coverage, 2717,
31663
0
        GIR_Done,
31664
      // Label 1599: @101209
31665
0
      GIM_Try, /*On fail goto*//*Label 1600*/ GIMT_Encode4(101345), // Rule ID 2718 //
31666
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
31667
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbl4),
31668
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
31669
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
31670
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
31671
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
31672
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8,
31673
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s8,
31674
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
31675
        // (intrinsic_wo_chain:{ *:[v8i8] } 3177:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm)  =>  (VTBL4Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
31676
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
31677
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
31678
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31679
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0
31680
0
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
31681
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1
31682
0
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
31683
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2
31684
0
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
31685
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn3
31686
0
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
31687
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID),
31688
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
31689
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
31690
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID),
31691
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID),
31692
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VTBL4Pseudo),
31693
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
31694
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31695
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Vm
31696
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
31697
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31698
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31699
0
        GIR_EraseFromParent, /*InsnID*/0,
31700
        // GIR_Coverage, 2718,
31701
0
        GIR_Done,
31702
      // Label 1600: @101345
31703
0
      GIM_Reject,
31704
    // Label 1538: @101346
31705
0
    GIM_Try, /*On fail goto*//*Label 1601*/ GIMT_Encode4(107454),
31706
0
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/8,
31707
0
      GIM_Try, /*On fail goto*//*Label 1602*/ GIMT_Encode4(101462), // Rule ID 3287 //
31708
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
31709
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
31710
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31711
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31712
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31713
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31714
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31715
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
31716
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
31717
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31718
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
31719
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
31720
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31721
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31722
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31723
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31724
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLADAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
31725
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs8),
31726
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
31727
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31728
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31729
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31730
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31731
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31732
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31733
0
        GIR_EraseFromParent, /*InsnID*/0,
31734
        // GIR_Coverage, 3287,
31735
0
        GIR_Done,
31736
      // Label 1602: @101462
31737
0
      GIM_Try, /*On fail goto*//*Label 1603*/ GIMT_Encode4(101570), // Rule ID 3291 //
31738
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
31739
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
31740
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31741
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31742
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31743
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31744
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31745
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
31746
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
31747
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31748
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
31749
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
31750
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31751
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31752
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31753
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31754
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLADAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
31755
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs8),
31756
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
31757
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31758
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31759
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31760
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31761
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31762
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31763
0
        GIR_EraseFromParent, /*InsnID*/0,
31764
        // GIR_Coverage, 3291,
31765
0
        GIR_Done,
31766
      // Label 1603: @101570
31767
0
      GIM_Try, /*On fail goto*//*Label 1604*/ GIMT_Encode4(101678), // Rule ID 3295 //
31768
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
31769
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
31770
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31771
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31772
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31773
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31774
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31775
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
31776
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
31777
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31778
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
31779
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
31780
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31781
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31782
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31783
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31784
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLADAVu8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
31785
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu8),
31786
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
31787
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31788
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31789
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31790
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31791
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31792
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31793
0
        GIR_EraseFromParent, /*InsnID*/0,
31794
        // GIR_Coverage, 3295,
31795
0
        GIR_Done,
31796
      // Label 1604: @101678
31797
0
      GIM_Try, /*On fail goto*//*Label 1605*/ GIMT_Encode4(101786), // Rule ID 3299 //
31798
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
31799
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
31800
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31801
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31802
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31803
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31804
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31805
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
31806
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
31807
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31808
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
31809
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
31810
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31811
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31812
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31813
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31814
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLADAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
31815
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs16),
31816
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
31817
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31818
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31819
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31820
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31821
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31822
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31823
0
        GIR_EraseFromParent, /*InsnID*/0,
31824
        // GIR_Coverage, 3299,
31825
0
        GIR_Done,
31826
      // Label 1605: @101786
31827
0
      GIM_Try, /*On fail goto*//*Label 1606*/ GIMT_Encode4(101894), // Rule ID 3303 //
31828
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
31829
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
31830
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31831
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31832
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31833
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31834
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31835
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
31836
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
31837
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31838
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
31839
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
31840
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31841
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31842
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31843
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31844
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLADAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
31845
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs16),
31846
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
31847
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31848
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31849
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31850
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31851
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31852
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31853
0
        GIR_EraseFromParent, /*InsnID*/0,
31854
        // GIR_Coverage, 3303,
31855
0
        GIR_Done,
31856
      // Label 1606: @101894
31857
0
      GIM_Try, /*On fail goto*//*Label 1607*/ GIMT_Encode4(102002), // Rule ID 3307 //
31858
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
31859
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
31860
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31861
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31862
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31863
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31864
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31865
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
31866
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
31867
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31868
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
31869
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
31870
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31871
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31872
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31873
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31874
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLADAVu16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
31875
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu16),
31876
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
31877
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31878
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31879
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31880
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31881
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31882
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31883
0
        GIR_EraseFromParent, /*InsnID*/0,
31884
        // GIR_Coverage, 3307,
31885
0
        GIR_Done,
31886
      // Label 1607: @102002
31887
0
      GIM_Try, /*On fail goto*//*Label 1608*/ GIMT_Encode4(102110), // Rule ID 3311 //
31888
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
31889
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
31890
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31891
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31892
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31893
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31894
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31895
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
31896
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
31897
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31898
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
31899
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
31900
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31901
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31902
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31903
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31904
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLADAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31905
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs32),
31906
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
31907
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31908
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31909
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31910
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31911
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31912
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31913
0
        GIR_EraseFromParent, /*InsnID*/0,
31914
        // GIR_Coverage, 3311,
31915
0
        GIR_Done,
31916
      // Label 1608: @102110
31917
0
      GIM_Try, /*On fail goto*//*Label 1609*/ GIMT_Encode4(102218), // Rule ID 3315 //
31918
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
31919
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
31920
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31921
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31922
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31923
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31924
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31925
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
31926
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
31927
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31928
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
31929
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
31930
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31931
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31932
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31933
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31934
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLADAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31935
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs32),
31936
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
31937
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31938
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31939
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31940
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31941
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31942
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31943
0
        GIR_EraseFromParent, /*InsnID*/0,
31944
        // GIR_Coverage, 3315,
31945
0
        GIR_Done,
31946
      // Label 1609: @102218
31947
0
      GIM_Try, /*On fail goto*//*Label 1610*/ GIMT_Encode4(102326), // Rule ID 3319 //
31948
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
31949
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
31950
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31951
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31952
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31953
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31954
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31955
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
31956
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
31957
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31958
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
31959
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
31960
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31961
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31962
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31963
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31964
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLADAVu32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31965
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu32),
31966
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
31967
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31968
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31969
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31970
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31971
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31972
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31973
0
        GIR_EraseFromParent, /*InsnID*/0,
31974
        // GIR_Coverage, 3319,
31975
0
        GIR_Done,
31976
      // Label 1610: @102326
31977
0
      GIM_Try, /*On fail goto*//*Label 1611*/ GIMT_Encode4(102434), // Rule ID 3323 //
31978
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
31979
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
31980
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31981
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31982
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31983
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31984
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31985
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
31986
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
31987
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31988
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
31989
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
31990
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31991
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31992
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31993
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31994
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLSDAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
31995
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs8),
31996
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
31997
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31998
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31999
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32000
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32001
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32002
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32003
0
        GIR_EraseFromParent, /*InsnID*/0,
32004
        // GIR_Coverage, 3323,
32005
0
        GIR_Done,
32006
      // Label 1611: @102434
32007
0
      GIM_Try, /*On fail goto*//*Label 1612*/ GIMT_Encode4(102542), // Rule ID 3327 //
32008
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32009
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32010
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32011
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32012
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32013
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32014
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32015
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
32016
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
32017
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32018
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32019
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32020
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32021
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32022
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32023
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32024
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLSDAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32025
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs8),
32026
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
32027
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32028
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32029
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32030
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32031
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32032
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32033
0
        GIR_EraseFromParent, /*InsnID*/0,
32034
        // GIR_Coverage, 3327,
32035
0
        GIR_Done,
32036
      // Label 1612: @102542
32037
0
      GIM_Try, /*On fail goto*//*Label 1613*/ GIMT_Encode4(102650), // Rule ID 3331 //
32038
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32039
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32040
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32041
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32042
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32043
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32044
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32045
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
32046
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
32047
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32048
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32049
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32050
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32051
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32052
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32053
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32054
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLSDAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32055
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs16),
32056
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
32057
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32058
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32059
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32060
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32061
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32062
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32063
0
        GIR_EraseFromParent, /*InsnID*/0,
32064
        // GIR_Coverage, 3331,
32065
0
        GIR_Done,
32066
      // Label 1613: @102650
32067
0
      GIM_Try, /*On fail goto*//*Label 1614*/ GIMT_Encode4(102758), // Rule ID 3335 //
32068
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32069
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32070
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32071
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32072
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32073
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32074
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32075
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
32076
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
32077
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32078
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32079
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32080
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32081
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32082
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32083
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32084
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLSDAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32085
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs16),
32086
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
32087
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32088
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32089
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32090
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32091
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32092
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32093
0
        GIR_EraseFromParent, /*InsnID*/0,
32094
        // GIR_Coverage, 3335,
32095
0
        GIR_Done,
32096
      // Label 1614: @102758
32097
0
      GIM_Try, /*On fail goto*//*Label 1615*/ GIMT_Encode4(102866), // Rule ID 3339 //
32098
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32099
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32100
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32101
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32102
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32103
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32104
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32105
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
32106
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
32107
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32108
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32109
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32110
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32111
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32112
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32113
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32114
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLSDAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32115
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs32),
32116
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
32117
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32118
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32119
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32120
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32121
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32122
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32123
0
        GIR_EraseFromParent, /*InsnID*/0,
32124
        // GIR_Coverage, 3339,
32125
0
        GIR_Done,
32126
      // Label 1615: @102866
32127
0
      GIM_Try, /*On fail goto*//*Label 1616*/ GIMT_Encode4(102974), // Rule ID 3343 //
32128
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32129
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32130
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32131
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32132
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32133
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32134
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32135
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
32136
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
32137
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32138
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32139
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32140
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32141
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32142
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32143
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32144
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLSDAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32145
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs32),
32146
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
32147
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32148
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32149
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32150
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32151
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32152
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32153
0
        GIR_EraseFromParent, /*InsnID*/0,
32154
        // GIR_Coverage, 3343,
32155
0
        GIR_Done,
32156
      // Label 1616: @102974
32157
0
      GIM_Try, /*On fail goto*//*Label 1617*/ GIMT_Encode4(103087), // Rule ID 3289 //
32158
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32159
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32160
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32161
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32162
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32163
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32164
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32165
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
32166
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
32167
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32168
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32169
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32170
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32171
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32172
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32173
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32174
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLADAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32175
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas8),
32176
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
32177
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32178
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32179
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32180
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32181
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32182
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32183
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32184
0
        GIR_EraseFromParent, /*InsnID*/0,
32185
        // GIR_Coverage, 3289,
32186
0
        GIR_Done,
32187
      // Label 1617: @103087
32188
0
      GIM_Try, /*On fail goto*//*Label 1618*/ GIMT_Encode4(103200), // Rule ID 3293 //
32189
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32190
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32191
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32192
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32193
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32194
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32195
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32196
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
32197
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
32198
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32199
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32200
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32201
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32202
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32203
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32204
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32205
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLADAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32206
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs8),
32207
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
32208
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32209
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32210
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32211
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32212
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32213
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32214
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32215
0
        GIR_EraseFromParent, /*InsnID*/0,
32216
        // GIR_Coverage, 3293,
32217
0
        GIR_Done,
32218
      // Label 1618: @103200
32219
0
      GIM_Try, /*On fail goto*//*Label 1619*/ GIMT_Encode4(103313), // Rule ID 3297 //
32220
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32221
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32222
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32223
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32224
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32225
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32226
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32227
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
32228
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
32229
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32230
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
32231
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32232
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32233
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32234
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32235
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32236
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLADAVau8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32237
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8),
32238
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
32239
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32240
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32241
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32242
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32243
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32244
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32245
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32246
0
        GIR_EraseFromParent, /*InsnID*/0,
32247
        // GIR_Coverage, 3297,
32248
0
        GIR_Done,
32249
      // Label 1619: @103313
32250
0
      GIM_Try, /*On fail goto*//*Label 1620*/ GIMT_Encode4(103426), // Rule ID 3301 //
32251
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32252
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32253
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32254
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32255
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32256
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32257
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32258
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
32259
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
32260
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32261
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32262
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32263
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32264
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32265
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32266
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32267
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLADAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32268
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas16),
32269
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
32270
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32271
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32272
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32273
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32274
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32275
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32276
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32277
0
        GIR_EraseFromParent, /*InsnID*/0,
32278
        // GIR_Coverage, 3301,
32279
0
        GIR_Done,
32280
      // Label 1620: @103426
32281
0
      GIM_Try, /*On fail goto*//*Label 1621*/ GIMT_Encode4(103539), // Rule ID 3305 //
32282
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32283
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32284
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32285
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32286
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32287
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32288
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32289
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
32290
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
32291
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32292
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32293
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32294
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32295
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32296
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32297
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32298
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLADAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32299
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs16),
32300
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
32301
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32302
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32303
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32304
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32305
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32306
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32307
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32308
0
        GIR_EraseFromParent, /*InsnID*/0,
32309
        // GIR_Coverage, 3305,
32310
0
        GIR_Done,
32311
      // Label 1621: @103539
32312
0
      GIM_Try, /*On fail goto*//*Label 1622*/ GIMT_Encode4(103652), // Rule ID 3309 //
32313
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32314
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32315
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32316
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32317
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32318
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32319
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32320
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
32321
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
32322
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32323
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
32324
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32325
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32326
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32327
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32328
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32329
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLADAVau16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32330
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16),
32331
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
32332
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32333
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32334
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32335
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32336
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32337
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32338
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32339
0
        GIR_EraseFromParent, /*InsnID*/0,
32340
        // GIR_Coverage, 3309,
32341
0
        GIR_Done,
32342
      // Label 1622: @103652
32343
0
      GIM_Try, /*On fail goto*//*Label 1623*/ GIMT_Encode4(103765), // Rule ID 3313 //
32344
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32345
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32346
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32347
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32348
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32349
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32350
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32351
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
32352
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
32353
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32354
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32355
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32356
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32357
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32358
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32359
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32360
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLADAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32361
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas32),
32362
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
32363
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32364
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32365
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32366
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32367
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32368
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32369
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32370
0
        GIR_EraseFromParent, /*InsnID*/0,
32371
        // GIR_Coverage, 3313,
32372
0
        GIR_Done,
32373
      // Label 1623: @103765
32374
0
      GIM_Try, /*On fail goto*//*Label 1624*/ GIMT_Encode4(103878), // Rule ID 3317 //
32375
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32376
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32377
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32378
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32379
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32380
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32381
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32382
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
32383
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
32384
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32385
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32386
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32387
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32388
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32389
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32390
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32391
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLADAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32392
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs32),
32393
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
32394
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32395
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32396
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32397
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32398
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32399
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32400
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32401
0
        GIR_EraseFromParent, /*InsnID*/0,
32402
        // GIR_Coverage, 3317,
32403
0
        GIR_Done,
32404
      // Label 1624: @103878
32405
0
      GIM_Try, /*On fail goto*//*Label 1625*/ GIMT_Encode4(103991), // Rule ID 3321 //
32406
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32407
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32408
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32409
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32410
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32411
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32412
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32413
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
32414
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
32415
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32416
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
32417
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32418
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32419
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32420
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32421
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32422
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLADAVau32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32423
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32),
32424
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
32425
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32426
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32427
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32428
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32429
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32430
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32431
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32432
0
        GIR_EraseFromParent, /*InsnID*/0,
32433
        // GIR_Coverage, 3321,
32434
0
        GIR_Done,
32435
      // Label 1625: @103991
32436
0
      GIM_Try, /*On fail goto*//*Label 1626*/ GIMT_Encode4(104104), // Rule ID 3325 //
32437
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32438
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32439
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32440
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32441
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32442
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32443
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32444
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
32445
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
32446
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32447
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32448
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32449
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32450
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32451
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32452
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32453
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLSDAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32454
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas8),
32455
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
32456
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32457
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32458
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32459
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32460
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32461
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32462
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32463
0
        GIR_EraseFromParent, /*InsnID*/0,
32464
        // GIR_Coverage, 3325,
32465
0
        GIR_Done,
32466
      // Label 1626: @104104
32467
0
      GIM_Try, /*On fail goto*//*Label 1627*/ GIMT_Encode4(104217), // Rule ID 3329 //
32468
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32469
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32470
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32471
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32472
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32473
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32474
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32475
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
32476
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
32477
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32478
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32479
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32480
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32481
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32482
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32483
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32484
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLSDAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32485
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs8),
32486
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
32487
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32488
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32489
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32490
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32491
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32492
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32493
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32494
0
        GIR_EraseFromParent, /*InsnID*/0,
32495
        // GIR_Coverage, 3329,
32496
0
        GIR_Done,
32497
      // Label 1627: @104217
32498
0
      GIM_Try, /*On fail goto*//*Label 1628*/ GIMT_Encode4(104330), // Rule ID 3333 //
32499
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32500
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32501
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32502
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32503
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32504
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32505
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32506
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
32507
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
32508
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32509
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32510
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32511
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32512
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32513
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32514
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32515
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLSDAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32516
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas16),
32517
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
32518
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32519
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32520
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32521
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32522
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32523
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32524
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32525
0
        GIR_EraseFromParent, /*InsnID*/0,
32526
        // GIR_Coverage, 3333,
32527
0
        GIR_Done,
32528
      // Label 1628: @104330
32529
0
      GIM_Try, /*On fail goto*//*Label 1629*/ GIMT_Encode4(104443), // Rule ID 3337 //
32530
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32531
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32532
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32533
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32534
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32535
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32536
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32537
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
32538
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
32539
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32540
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32541
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32542
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32543
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32544
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32545
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32546
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLSDAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32547
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs16),
32548
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
32549
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32550
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32551
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32552
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32553
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32554
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32555
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32556
0
        GIR_EraseFromParent, /*InsnID*/0,
32557
        // GIR_Coverage, 3337,
32558
0
        GIR_Done,
32559
      // Label 1629: @104443
32560
0
      GIM_Try, /*On fail goto*//*Label 1630*/ GIMT_Encode4(104556), // Rule ID 3341 //
32561
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32562
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32563
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32564
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32565
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32566
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32567
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32568
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
32569
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
32570
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32571
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32572
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32573
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32574
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32575
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32576
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32577
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLSDAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32578
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas32),
32579
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
32580
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32581
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32582
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32583
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32584
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32585
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32586
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32587
0
        GIR_EraseFromParent, /*InsnID*/0,
32588
        // GIR_Coverage, 3341,
32589
0
        GIR_Done,
32590
      // Label 1630: @104556
32591
0
      GIM_Try, /*On fail goto*//*Label 1631*/ GIMT_Encode4(104669), // Rule ID 3345 //
32592
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32593
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32594
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32595
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32596
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32597
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32598
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32599
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
32600
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
32601
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32602
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32603
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32604
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32605
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32606
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32607
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32608
        // (intrinsic_wo_chain:{ *:[i32] } 2970:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLSDAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32609
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs32),
32610
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
32611
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32612
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32613
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32614
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32615
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32616
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32617
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32618
0
        GIR_EraseFromParent, /*InsnID*/0,
32619
        // GIR_Coverage, 3345,
32620
0
        GIR_Done,
32621
      // Label 1631: @104669
32622
0
      GIM_Try, /*On fail goto*//*Label 1632*/ GIMT_Encode4(104779), // Rule ID 4459 //
32623
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
32624
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
32625
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
32626
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
32627
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
32628
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32629
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32630
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32631
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32632
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32633
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32634
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32635
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32636
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32637
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32638
        // (intrinsic_wo_chain:{ *:[v16i8] } 2979:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
32639
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs8),
32640
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
32641
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32642
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32643
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32644
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32645
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32646
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32647
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32648
0
        GIR_EraseFromParent, /*InsnID*/0,
32649
        // GIR_Coverage, 4459,
32650
0
        GIR_Done,
32651
      // Label 1632: @104779
32652
0
      GIM_Try, /*On fail goto*//*Label 1633*/ GIMT_Encode4(104889), // Rule ID 4461 //
32653
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
32654
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
32655
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
32656
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
32657
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
32658
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32659
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32660
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32661
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32662
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32663
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32664
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32665
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32666
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32667
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32668
        // (intrinsic_wo_chain:{ *:[v8i16] } 2979:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
32669
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs16),
32670
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
32671
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32672
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32673
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32674
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32675
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32676
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32677
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32678
0
        GIR_EraseFromParent, /*InsnID*/0,
32679
        // GIR_Coverage, 4461,
32680
0
        GIR_Done,
32681
      // Label 1633: @104889
32682
0
      GIM_Try, /*On fail goto*//*Label 1634*/ GIMT_Encode4(104999), // Rule ID 4463 //
32683
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
32684
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
32685
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
32686
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
32687
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
32688
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32689
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32690
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32691
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32692
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32693
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32694
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32695
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32696
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32697
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32698
        // (intrinsic_wo_chain:{ *:[v4i32] } 2979:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
32699
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs32),
32700
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
32701
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32702
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32703
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32704
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32705
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32706
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32707
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32708
0
        GIR_EraseFromParent, /*InsnID*/0,
32709
        // GIR_Coverage, 4463,
32710
0
        GIR_Done,
32711
      // Label 1634: @104999
32712
0
      GIM_Try, /*On fail goto*//*Label 1635*/ GIMT_Encode4(105109), // Rule ID 4465 //
32713
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
32714
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
32715
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
32716
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
32717
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
32718
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32719
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32720
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32721
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32722
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32723
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32724
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32725
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
32726
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32727
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32728
        // (intrinsic_wo_chain:{ *:[v16i8] } 2979:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
32729
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs8),
32730
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
32731
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32732
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32733
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32734
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32735
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32736
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32737
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32738
0
        GIR_EraseFromParent, /*InsnID*/0,
32739
        // GIR_Coverage, 4465,
32740
0
        GIR_Done,
32741
      // Label 1635: @105109
32742
0
      GIM_Try, /*On fail goto*//*Label 1636*/ GIMT_Encode4(105219), // Rule ID 4467 //
32743
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
32744
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
32745
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
32746
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
32747
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
32748
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32749
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32750
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32751
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32752
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32753
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32754
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32755
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
32756
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32757
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32758
        // (intrinsic_wo_chain:{ *:[v8i16] } 2979:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
32759
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs16),
32760
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
32761
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32762
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32763
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32764
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32765
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32766
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32767
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32768
0
        GIR_EraseFromParent, /*InsnID*/0,
32769
        // GIR_Coverage, 4467,
32770
0
        GIR_Done,
32771
      // Label 1636: @105219
32772
0
      GIM_Try, /*On fail goto*//*Label 1637*/ GIMT_Encode4(105329), // Rule ID 4469 //
32773
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
32774
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
32775
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
32776
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
32777
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
32778
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32779
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32780
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32781
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32782
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32783
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32784
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32785
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
32786
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32787
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32788
        // (intrinsic_wo_chain:{ *:[v4i32] } 2979:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
32789
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs32),
32790
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
32791
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32792
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32793
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32794
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32795
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32796
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32797
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32798
0
        GIR_EraseFromParent, /*InsnID*/0,
32799
        // GIR_Coverage, 4469,
32800
0
        GIR_Done,
32801
      // Label 1637: @105329
32802
0
      GIM_Try, /*On fail goto*//*Label 1638*/ GIMT_Encode4(105439), // Rule ID 4471 //
32803
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
32804
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
32805
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
32806
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
32807
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
32808
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32809
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32810
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32811
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32812
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32813
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32814
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32815
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32816
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
32817
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32818
        // (intrinsic_wo_chain:{ *:[v16i8] } 2979:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
32819
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs8),
32820
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
32821
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32822
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32823
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32824
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32825
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32826
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32827
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32828
0
        GIR_EraseFromParent, /*InsnID*/0,
32829
        // GIR_Coverage, 4471,
32830
0
        GIR_Done,
32831
      // Label 1638: @105439
32832
0
      GIM_Try, /*On fail goto*//*Label 1639*/ GIMT_Encode4(105549), // Rule ID 4473 //
32833
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
32834
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
32835
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
32836
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
32837
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
32838
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32839
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32840
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32841
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32842
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32843
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32844
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32845
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32846
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
32847
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32848
        // (intrinsic_wo_chain:{ *:[v8i16] } 2979:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
32849
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs16),
32850
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
32851
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32852
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32853
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32854
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32855
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32856
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32857
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32858
0
        GIR_EraseFromParent, /*InsnID*/0,
32859
        // GIR_Coverage, 4473,
32860
0
        GIR_Done,
32861
      // Label 1639: @105549
32862
0
      GIM_Try, /*On fail goto*//*Label 1640*/ GIMT_Encode4(105659), // Rule ID 4475 //
32863
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
32864
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
32865
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
32866
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
32867
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
32868
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32869
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32870
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32871
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32872
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32873
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32874
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32875
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32876
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
32877
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32878
        // (intrinsic_wo_chain:{ *:[v4i32] } 2979:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
32879
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs32),
32880
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
32881
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32882
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32883
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32884
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32885
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32886
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32887
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32888
0
        GIR_EraseFromParent, /*InsnID*/0,
32889
        // GIR_Coverage, 4475,
32890
0
        GIR_Done,
32891
      // Label 1640: @105659
32892
0
      GIM_Try, /*On fail goto*//*Label 1641*/ GIMT_Encode4(105769), // Rule ID 4477 //
32893
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
32894
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
32895
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
32896
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
32897
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
32898
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32899
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32900
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32901
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32902
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32903
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32904
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32905
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
32906
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
32907
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32908
        // (intrinsic_wo_chain:{ *:[v16i8] } 2979:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
32909
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs8),
32910
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
32911
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32912
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32913
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32914
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32915
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32916
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32917
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32918
0
        GIR_EraseFromParent, /*InsnID*/0,
32919
        // GIR_Coverage, 4477,
32920
0
        GIR_Done,
32921
      // Label 1641: @105769
32922
0
      GIM_Try, /*On fail goto*//*Label 1642*/ GIMT_Encode4(105879), // Rule ID 4479 //
32923
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
32924
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
32925
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
32926
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
32927
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
32928
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32929
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32930
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32931
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32932
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32933
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32934
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32935
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
32936
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
32937
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32938
        // (intrinsic_wo_chain:{ *:[v8i16] } 2979:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
32939
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs16),
32940
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
32941
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32942
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32943
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32944
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32945
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32946
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32947
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32948
0
        GIR_EraseFromParent, /*InsnID*/0,
32949
        // GIR_Coverage, 4479,
32950
0
        GIR_Done,
32951
      // Label 1642: @105879
32952
0
      GIM_Try, /*On fail goto*//*Label 1643*/ GIMT_Encode4(105989), // Rule ID 4481 //
32953
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
32954
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
32955
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
32956
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
32957
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
32958
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32959
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32960
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32961
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32962
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32963
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32964
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32965
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
32966
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
32967
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32968
        // (intrinsic_wo_chain:{ *:[v4i32] } 2979:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
32969
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs32),
32970
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
32971
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32972
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32973
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32974
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32975
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32976
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32977
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32978
0
        GIR_EraseFromParent, /*InsnID*/0,
32979
        // GIR_Coverage, 4481,
32980
0
        GIR_Done,
32981
      // Label 1643: @105989
32982
0
      GIM_Try, /*On fail goto*//*Label 1644*/ GIMT_Encode4(106099), // Rule ID 4483 //
32983
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
32984
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
32985
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
32986
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
32987
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
32988
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32989
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32990
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32991
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32992
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32993
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32994
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32995
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32996
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32997
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
32998
        // (intrinsic_wo_chain:{ *:[v16i8] } 2979:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
32999
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs8),
33000
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33001
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33002
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33003
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33004
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33005
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33006
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33007
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33008
0
        GIR_EraseFromParent, /*InsnID*/0,
33009
        // GIR_Coverage, 4483,
33010
0
        GIR_Done,
33011
      // Label 1644: @106099
33012
0
      GIM_Try, /*On fail goto*//*Label 1645*/ GIMT_Encode4(106209), // Rule ID 4485 //
33013
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33014
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33015
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33016
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33017
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
33018
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33019
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33020
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33021
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33022
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33023
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33024
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33025
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33026
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33027
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33028
        // (intrinsic_wo_chain:{ *:[v8i16] } 2979:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
33029
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs16),
33030
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33031
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33032
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33033
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33034
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33035
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33036
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33037
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33038
0
        GIR_EraseFromParent, /*InsnID*/0,
33039
        // GIR_Coverage, 4485,
33040
0
        GIR_Done,
33041
      // Label 1645: @106209
33042
0
      GIM_Try, /*On fail goto*//*Label 1646*/ GIMT_Encode4(106319), // Rule ID 4487 //
33043
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33044
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
33045
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
33046
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33047
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
33048
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33049
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33050
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33051
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33052
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33053
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33054
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33055
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33056
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33057
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33058
        // (intrinsic_wo_chain:{ *:[v4i32] } 2979:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33059
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs32),
33060
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33061
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33062
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33063
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33064
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33065
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33066
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33067
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33068
0
        GIR_EraseFromParent, /*InsnID*/0,
33069
        // GIR_Coverage, 4487,
33070
0
        GIR_Done,
33071
      // Label 1646: @106319
33072
0
      GIM_Try, /*On fail goto*//*Label 1647*/ GIMT_Encode4(106429), // Rule ID 4489 //
33073
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33074
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33075
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33076
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
33077
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
33078
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33079
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33080
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33081
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33082
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33083
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33084
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33085
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33086
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33087
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33088
        // (intrinsic_wo_chain:{ *:[v16i8] } 2979:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
33089
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs8),
33090
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33091
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33092
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33093
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33094
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33095
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33096
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33097
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33098
0
        GIR_EraseFromParent, /*InsnID*/0,
33099
        // GIR_Coverage, 4489,
33100
0
        GIR_Done,
33101
      // Label 1647: @106429
33102
0
      GIM_Try, /*On fail goto*//*Label 1648*/ GIMT_Encode4(106539), // Rule ID 4491 //
33103
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33104
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33105
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33106
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33107
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
33108
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33109
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33110
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33111
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33112
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33113
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33114
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33115
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33116
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33117
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33118
        // (intrinsic_wo_chain:{ *:[v8i16] } 2979:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
33119
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs16),
33120
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33121
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33122
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33123
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33124
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33125
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33126
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33127
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33128
0
        GIR_EraseFromParent, /*InsnID*/0,
33129
        // GIR_Coverage, 4491,
33130
0
        GIR_Done,
33131
      // Label 1648: @106539
33132
0
      GIM_Try, /*On fail goto*//*Label 1649*/ GIMT_Encode4(106649), // Rule ID 4493 //
33133
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33134
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
33135
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
33136
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33137
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
33138
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33139
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33140
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33141
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33142
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33143
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33144
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33145
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33146
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33147
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33148
        // (intrinsic_wo_chain:{ *:[v4i32] } 2979:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33149
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs32),
33150
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33151
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33152
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33153
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33154
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33155
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33156
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33157
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33158
0
        GIR_EraseFromParent, /*InsnID*/0,
33159
        // GIR_Coverage, 4493,
33160
0
        GIR_Done,
33161
      // Label 1649: @106649
33162
0
      GIM_Try, /*On fail goto*//*Label 1650*/ GIMT_Encode4(106759), // Rule ID 4495 //
33163
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33164
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33165
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33166
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
33167
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
33168
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33169
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33170
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33171
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33172
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33173
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33174
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33175
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33176
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33177
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33178
        // (intrinsic_wo_chain:{ *:[v16i8] } 2979:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
33179
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs8),
33180
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33181
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33182
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33183
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33184
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33185
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33186
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33187
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33188
0
        GIR_EraseFromParent, /*InsnID*/0,
33189
        // GIR_Coverage, 4495,
33190
0
        GIR_Done,
33191
      // Label 1650: @106759
33192
0
      GIM_Try, /*On fail goto*//*Label 1651*/ GIMT_Encode4(106869), // Rule ID 4497 //
33193
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33194
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33195
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33196
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33197
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
33198
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33199
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33200
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33201
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33202
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33203
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33204
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33205
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33206
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33207
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33208
        // (intrinsic_wo_chain:{ *:[v8i16] } 2979:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
33209
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs16),
33210
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33211
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33212
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33213
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33214
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33215
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33216
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33217
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33218
0
        GIR_EraseFromParent, /*InsnID*/0,
33219
        // GIR_Coverage, 4497,
33220
0
        GIR_Done,
33221
      // Label 1651: @106869
33222
0
      GIM_Try, /*On fail goto*//*Label 1652*/ GIMT_Encode4(106979), // Rule ID 4499 //
33223
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33224
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
33225
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
33226
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33227
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
33228
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33229
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33230
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33231
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33232
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33233
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33234
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33235
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33236
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33237
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33238
        // (intrinsic_wo_chain:{ *:[v4i32] } 2979:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33239
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs32),
33240
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33241
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33242
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33243
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33244
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33245
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33246
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33247
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33248
0
        GIR_EraseFromParent, /*InsnID*/0,
33249
        // GIR_Coverage, 4499,
33250
0
        GIR_Done,
33251
      // Label 1652: @106979
33252
0
      GIM_Try, /*On fail goto*//*Label 1653*/ GIMT_Encode4(107089), // Rule ID 4501 //
33253
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33254
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33255
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33256
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
33257
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
33258
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33259
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33260
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33261
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33262
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33263
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33264
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33265
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33266
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33267
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33268
        // (intrinsic_wo_chain:{ *:[v16i8] } 2979:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
33269
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs8),
33270
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33271
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33272
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33273
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33274
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33275
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33276
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33277
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33278
0
        GIR_EraseFromParent, /*InsnID*/0,
33279
        // GIR_Coverage, 4501,
33280
0
        GIR_Done,
33281
      // Label 1653: @107089
33282
0
      GIM_Try, /*On fail goto*//*Label 1654*/ GIMT_Encode4(107199), // Rule ID 4503 //
33283
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33284
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33285
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33286
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33287
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
33288
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33289
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33290
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33291
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33292
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33293
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33294
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33295
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33296
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33297
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33298
        // (intrinsic_wo_chain:{ *:[v8i16] } 2979:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
33299
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs16),
33300
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33301
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33302
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33303
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33304
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33305
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33306
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33307
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33308
0
        GIR_EraseFromParent, /*InsnID*/0,
33309
        // GIR_Coverage, 4503,
33310
0
        GIR_Done,
33311
      // Label 1654: @107199
33312
0
      GIM_Try, /*On fail goto*//*Label 1655*/ GIMT_Encode4(107309), // Rule ID 4505 //
33313
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33314
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
33315
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
33316
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33317
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
33318
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33319
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33320
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33321
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33322
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33323
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33324
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33325
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33326
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33327
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33328
        // (intrinsic_wo_chain:{ *:[v4i32] } 2979:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33329
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs32),
33330
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33331
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33332
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33333
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33334
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33335
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33336
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33337
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33338
0
        GIR_EraseFromParent, /*InsnID*/0,
33339
        // GIR_Coverage, 4505,
33340
0
        GIR_Done,
33341
      // Label 1655: @107309
33342
0
      GIM_Try, /*On fail goto*//*Label 1656*/ GIMT_Encode4(107453), // Rule ID 2719 //
33343
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
33344
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx4),
33345
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
33346
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
33347
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
33348
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
33349
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8,
33350
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s8,
33351
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s8,
33352
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
33353
        // (intrinsic_wo_chain:{ *:[v8i8] } 3181:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm)  =>  (VTBX4Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
33354
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
33355
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
33356
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33357
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
33358
0
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
33359
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
33360
0
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
33361
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2
33362
0
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
33363
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/6, // Vn3
33364
0
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
33365
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID),
33366
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
33367
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
33368
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID),
33369
0
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID),
33370
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VTBX4Pseudo),
33371
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
33372
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // orig
33373
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33374
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Vm
33375
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33376
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33377
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33378
0
        GIR_EraseFromParent, /*InsnID*/0,
33379
        // GIR_Coverage, 2719,
33380
0
        GIR_Done,
33381
      // Label 1656: @107453
33382
0
      GIM_Reject,
33383
    // Label 1601: @107454
33384
0
    GIM_Try, /*On fail goto*//*Label 1657*/ GIMT_Encode4(112628),
33385
0
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/10,
33386
0
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshrn),
33387
0
      GIM_Try, /*On fail goto*//*Label 1658*/ GIMT_Encode4(107596), // Rule ID 3882 //
33388
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33389
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33390
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33391
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33392
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33393
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33394
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33395
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33396
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33397
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33398
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33399
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33400
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33401
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33402
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
33403
        // MIs[1] Operand 1
33404
        // No operand predicates
33405
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33406
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33407
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33408
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
33409
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
33410
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
33411
        // (intrinsic_wo_chain:{ *:[v16i8] } 3024:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33412
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16bh),
33413
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33414
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33415
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33416
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33417
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33418
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33419
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33420
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33421
0
        GIR_EraseFromParent, /*InsnID*/0,
33422
        // GIR_Coverage, 3882,
33423
0
        GIR_Done,
33424
      // Label 1658: @107596
33425
0
      GIM_Try, /*On fail goto*//*Label 1659*/ GIMT_Encode4(107725), // Rule ID 3884 //
33426
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33427
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33428
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33429
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33430
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33431
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33432
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33433
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33434
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33435
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33436
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33437
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33438
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33439
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33440
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
33441
        // MIs[1] Operand 1
33442
        // No operand predicates
33443
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33444
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33445
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33446
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
33447
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
33448
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
33449
        // (intrinsic_wo_chain:{ *:[v16i8] } 3024:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33450
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16th),
33451
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33452
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33453
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33454
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33455
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33456
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33457
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33458
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33459
0
        GIR_EraseFromParent, /*InsnID*/0,
33460
        // GIR_Coverage, 3884,
33461
0
        GIR_Done,
33462
      // Label 1659: @107725
33463
0
      GIM_Try, /*On fail goto*//*Label 1660*/ GIMT_Encode4(107854), // Rule ID 3886 //
33464
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33465
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33466
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33467
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33468
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33469
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33470
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33471
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33472
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33473
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33474
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33475
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33476
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33477
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33478
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
33479
        // MIs[1] Operand 1
33480
        // No operand predicates
33481
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33482
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33483
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33484
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
33485
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
33486
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
33487
        // (intrinsic_wo_chain:{ *:[v8i16] } 3024:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33488
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32bh),
33489
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33490
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33491
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33492
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33493
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33494
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33495
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33496
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33497
0
        GIR_EraseFromParent, /*InsnID*/0,
33498
        // GIR_Coverage, 3886,
33499
0
        GIR_Done,
33500
      // Label 1660: @107854
33501
0
      GIM_Try, /*On fail goto*//*Label 1661*/ GIMT_Encode4(107983), // Rule ID 3888 //
33502
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33503
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33504
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33505
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33506
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33507
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33508
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33509
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33510
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33511
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33512
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33513
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33514
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33515
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33516
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
33517
        // MIs[1] Operand 1
33518
        // No operand predicates
33519
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33520
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33521
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33522
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
33523
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
33524
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
33525
        // (intrinsic_wo_chain:{ *:[v8i16] } 3024:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33526
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32th),
33527
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33528
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33529
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33530
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33531
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33532
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33533
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33534
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33535
0
        GIR_EraseFromParent, /*InsnID*/0,
33536
        // GIR_Coverage, 3888,
33537
0
        GIR_Done,
33538
      // Label 1661: @107983
33539
0
      GIM_Try, /*On fail goto*//*Label 1662*/ GIMT_Encode4(108112), // Rule ID 3890 //
33540
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33541
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33542
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33543
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33544
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33545
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33546
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33547
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33548
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33549
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33550
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33551
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33552
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33553
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33554
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
33555
        // MIs[1] Operand 1
33556
        // No operand predicates
33557
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33558
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33559
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33560
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
33561
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
33562
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
33563
        // (intrinsic_wo_chain:{ *:[v16i8] } 3024:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33564
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16bh),
33565
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33566
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33567
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33568
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33569
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33570
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33571
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33572
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33573
0
        GIR_EraseFromParent, /*InsnID*/0,
33574
        // GIR_Coverage, 3890,
33575
0
        GIR_Done,
33576
      // Label 1662: @108112
33577
0
      GIM_Try, /*On fail goto*//*Label 1663*/ GIMT_Encode4(108241), // Rule ID 3892 //
33578
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33579
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33580
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33581
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33582
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33583
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33584
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33585
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33586
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33587
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33588
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33589
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33590
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33591
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33592
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
33593
        // MIs[1] Operand 1
33594
        // No operand predicates
33595
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33596
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33597
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33598
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
33599
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
33600
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
33601
        // (intrinsic_wo_chain:{ *:[v16i8] } 3024:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33602
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16th),
33603
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33604
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33605
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33606
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33607
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33608
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33609
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33610
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33611
0
        GIR_EraseFromParent, /*InsnID*/0,
33612
        // GIR_Coverage, 3892,
33613
0
        GIR_Done,
33614
      // Label 1663: @108241
33615
0
      GIM_Try, /*On fail goto*//*Label 1664*/ GIMT_Encode4(108370), // Rule ID 3894 //
33616
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33617
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33618
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33619
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33620
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33621
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33622
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33623
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33624
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33625
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33626
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33627
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33628
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33629
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33630
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
33631
        // MIs[1] Operand 1
33632
        // No operand predicates
33633
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33634
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33635
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33636
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
33637
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
33638
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
33639
        // (intrinsic_wo_chain:{ *:[v8i16] } 3024:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33640
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32bh),
33641
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33642
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33643
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33644
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33645
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33646
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33647
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33648
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33649
0
        GIR_EraseFromParent, /*InsnID*/0,
33650
        // GIR_Coverage, 3894,
33651
0
        GIR_Done,
33652
      // Label 1664: @108370
33653
0
      GIM_Try, /*On fail goto*//*Label 1665*/ GIMT_Encode4(108499), // Rule ID 3896 //
33654
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33655
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33656
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33657
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33658
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33659
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33660
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33661
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33662
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33663
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33664
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33665
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33666
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33667
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33668
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
33669
        // MIs[1] Operand 1
33670
        // No operand predicates
33671
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33672
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33673
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33674
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
33675
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
33676
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
33677
        // (intrinsic_wo_chain:{ *:[v8i16] } 3024:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33678
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32th),
33679
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33680
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33681
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33682
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33683
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33684
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33685
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33686
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33687
0
        GIR_EraseFromParent, /*InsnID*/0,
33688
        // GIR_Coverage, 3896,
33689
0
        GIR_Done,
33690
      // Label 1665: @108499
33691
0
      GIM_Try, /*On fail goto*//*Label 1666*/ GIMT_Encode4(108628), // Rule ID 3898 //
33692
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33693
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33694
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33695
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33696
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33697
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33698
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33699
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33700
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33701
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33702
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33703
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33704
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33705
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33706
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
33707
        // MIs[1] Operand 1
33708
        // No operand predicates
33709
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33710
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33711
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33712
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
33713
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
33714
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
33715
        // (intrinsic_wo_chain:{ *:[v16i8] } 3024:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33716
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16bh),
33717
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33718
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33719
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33720
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33721
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33722
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33723
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33724
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33725
0
        GIR_EraseFromParent, /*InsnID*/0,
33726
        // GIR_Coverage, 3898,
33727
0
        GIR_Done,
33728
      // Label 1666: @108628
33729
0
      GIM_Try, /*On fail goto*//*Label 1667*/ GIMT_Encode4(108757), // Rule ID 3900 //
33730
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33731
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33732
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33733
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33734
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33735
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33736
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33737
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33738
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33739
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33740
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33741
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33742
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33743
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33744
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
33745
        // MIs[1] Operand 1
33746
        // No operand predicates
33747
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33748
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33749
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33750
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
33751
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
33752
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
33753
        // (intrinsic_wo_chain:{ *:[v16i8] } 3024:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33754
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16th),
33755
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33756
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33757
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33758
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33759
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33760
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33761
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33762
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33763
0
        GIR_EraseFromParent, /*InsnID*/0,
33764
        // GIR_Coverage, 3900,
33765
0
        GIR_Done,
33766
      // Label 1667: @108757
33767
0
      GIM_Try, /*On fail goto*//*Label 1668*/ GIMT_Encode4(108886), // Rule ID 3902 //
33768
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33769
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33770
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33771
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33772
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33773
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33774
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33775
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33776
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33777
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33778
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33779
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33780
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33781
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33782
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
33783
        // MIs[1] Operand 1
33784
        // No operand predicates
33785
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33786
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33787
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33788
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
33789
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
33790
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
33791
        // (intrinsic_wo_chain:{ *:[v8i16] } 3024:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33792
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32bh),
33793
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33794
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33795
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33796
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33797
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33798
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33799
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33800
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33801
0
        GIR_EraseFromParent, /*InsnID*/0,
33802
        // GIR_Coverage, 3902,
33803
0
        GIR_Done,
33804
      // Label 1668: @108886
33805
0
      GIM_Try, /*On fail goto*//*Label 1669*/ GIMT_Encode4(109015), // Rule ID 3904 //
33806
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33807
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33808
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33809
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33810
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33811
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33812
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33813
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33814
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33815
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33816
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33817
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33818
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33819
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33820
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
33821
        // MIs[1] Operand 1
33822
        // No operand predicates
33823
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33824
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33825
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33826
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
33827
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
33828
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
33829
        // (intrinsic_wo_chain:{ *:[v8i16] } 3024:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33830
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32th),
33831
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33832
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33833
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33834
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33835
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33836
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33837
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33838
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33839
0
        GIR_EraseFromParent, /*InsnID*/0,
33840
        // GIR_Coverage, 3904,
33841
0
        GIR_Done,
33842
      // Label 1669: @109015
33843
0
      GIM_Try, /*On fail goto*//*Label 1670*/ GIMT_Encode4(109144), // Rule ID 3906 //
33844
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33845
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33846
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33847
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33848
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33849
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33850
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33851
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33852
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33853
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33854
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33855
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33856
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33857
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33858
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
33859
        // MIs[1] Operand 1
33860
        // No operand predicates
33861
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33862
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33863
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33864
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
33865
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
33866
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
33867
        // (intrinsic_wo_chain:{ *:[v16i8] } 3024:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33868
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16bh),
33869
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33870
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33871
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33872
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33873
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33874
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33875
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33876
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33877
0
        GIR_EraseFromParent, /*InsnID*/0,
33878
        // GIR_Coverage, 3906,
33879
0
        GIR_Done,
33880
      // Label 1670: @109144
33881
0
      GIM_Try, /*On fail goto*//*Label 1671*/ GIMT_Encode4(109273), // Rule ID 3908 //
33882
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33883
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33884
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33885
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33886
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33887
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33888
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33889
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33890
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33891
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33892
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33893
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33894
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33895
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33896
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
33897
        // MIs[1] Operand 1
33898
        // No operand predicates
33899
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33900
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33901
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33902
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
33903
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
33904
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
33905
        // (intrinsic_wo_chain:{ *:[v16i8] } 3024:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33906
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16th),
33907
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33908
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33909
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33910
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33911
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33912
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33913
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33914
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33915
0
        GIR_EraseFromParent, /*InsnID*/0,
33916
        // GIR_Coverage, 3908,
33917
0
        GIR_Done,
33918
      // Label 1671: @109273
33919
0
      GIM_Try, /*On fail goto*//*Label 1672*/ GIMT_Encode4(109402), // Rule ID 3910 //
33920
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33921
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33922
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33923
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33924
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33925
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33926
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33927
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33928
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33929
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33930
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33931
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33932
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33933
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33934
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
33935
        // MIs[1] Operand 1
33936
        // No operand predicates
33937
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33938
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33939
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33940
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
33941
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
33942
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
33943
        // (intrinsic_wo_chain:{ *:[v8i16] } 3024:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33944
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32bh),
33945
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33946
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33947
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33948
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33949
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33950
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33951
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33952
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33953
0
        GIR_EraseFromParent, /*InsnID*/0,
33954
        // GIR_Coverage, 3910,
33955
0
        GIR_Done,
33956
      // Label 1672: @109402
33957
0
      GIM_Try, /*On fail goto*//*Label 1673*/ GIMT_Encode4(109531), // Rule ID 3912 //
33958
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33959
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33960
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33961
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33962
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33963
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33964
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33965
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33966
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33967
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33968
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33969
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33970
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33971
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33972
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
33973
        // MIs[1] Operand 1
33974
        // No operand predicates
33975
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33976
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33977
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33978
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
33979
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
33980
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
33981
        // (intrinsic_wo_chain:{ *:[v8i16] } 3024:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33982
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32th),
33983
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
33984
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33985
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33986
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33987
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33988
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33989
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33990
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33991
0
        GIR_EraseFromParent, /*InsnID*/0,
33992
        // GIR_Coverage, 3912,
33993
0
        GIR_Done,
33994
      // Label 1673: @109531
33995
0
      GIM_Try, /*On fail goto*//*Label 1674*/ GIMT_Encode4(109660), // Rule ID 3914 //
33996
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33997
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33998
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33999
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34000
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34001
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34002
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34003
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34004
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34005
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34006
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34007
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34008
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34009
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34010
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34011
        // MIs[1] Operand 1
34012
        // No operand predicates
34013
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34014
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34015
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34016
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34017
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34018
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34019
        // (intrinsic_wo_chain:{ *:[v16i8] } 3024:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34020
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhs16),
34021
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34022
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34023
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34024
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34025
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34026
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34027
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34028
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34029
0
        GIR_EraseFromParent, /*InsnID*/0,
34030
        // GIR_Coverage, 3914,
34031
0
        GIR_Done,
34032
      // Label 1674: @109660
34033
0
      GIM_Try, /*On fail goto*//*Label 1675*/ GIMT_Encode4(109789), // Rule ID 3916 //
34034
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
34035
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
34036
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34037
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34038
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34039
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34040
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34041
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34042
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34043
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34044
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34045
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34046
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34047
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34048
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34049
        // MIs[1] Operand 1
34050
        // No operand predicates
34051
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34052
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34053
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34054
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34055
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34056
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34057
        // (intrinsic_wo_chain:{ *:[v16i8] } 3024:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34058
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNths16),
34059
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34060
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34061
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34062
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34063
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34064
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34065
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34066
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34067
0
        GIR_EraseFromParent, /*InsnID*/0,
34068
        // GIR_Coverage, 3916,
34069
0
        GIR_Done,
34070
      // Label 1675: @109789
34071
0
      GIM_Try, /*On fail goto*//*Label 1676*/ GIMT_Encode4(109918), // Rule ID 3918 //
34072
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34073
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34074
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34075
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34076
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34077
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34078
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34079
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34080
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34081
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34082
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34083
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34084
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34085
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34086
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34087
        // MIs[1] Operand 1
34088
        // No operand predicates
34089
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34090
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34091
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34092
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34093
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34094
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34095
        // (intrinsic_wo_chain:{ *:[v8i16] } 3024:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34096
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhs32),
34097
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34098
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34099
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34100
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34101
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34102
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34103
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34104
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34105
0
        GIR_EraseFromParent, /*InsnID*/0,
34106
        // GIR_Coverage, 3918,
34107
0
        GIR_Done,
34108
      // Label 1676: @109918
34109
0
      GIM_Try, /*On fail goto*//*Label 1677*/ GIMT_Encode4(110047), // Rule ID 3920 //
34110
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34111
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34112
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34113
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34114
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34115
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34116
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34117
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34118
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34119
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34120
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34121
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34122
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34123
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34124
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34125
        // MIs[1] Operand 1
34126
        // No operand predicates
34127
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34128
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34129
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34130
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34131
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34132
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34133
        // (intrinsic_wo_chain:{ *:[v8i16] } 3024:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34134
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNths32),
34135
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34136
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34137
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34138
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34139
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34140
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34141
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34142
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34143
0
        GIR_EraseFromParent, /*InsnID*/0,
34144
        // GIR_Coverage, 3920,
34145
0
        GIR_Done,
34146
      // Label 1677: @110047
34147
0
      GIM_Try, /*On fail goto*//*Label 1678*/ GIMT_Encode4(110176), // Rule ID 3922 //
34148
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
34149
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
34150
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34151
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34152
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34153
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34154
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34155
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34156
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34157
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34158
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34159
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34160
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34161
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34162
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34163
        // MIs[1] Operand 1
34164
        // No operand predicates
34165
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34166
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34167
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34168
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34169
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34170
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34171
        // (intrinsic_wo_chain:{ *:[v16i8] } 3024:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34172
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhu16),
34173
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34174
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34175
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34176
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34177
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34178
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34179
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34180
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34181
0
        GIR_EraseFromParent, /*InsnID*/0,
34182
        // GIR_Coverage, 3922,
34183
0
        GIR_Done,
34184
      // Label 1678: @110176
34185
0
      GIM_Try, /*On fail goto*//*Label 1679*/ GIMT_Encode4(110305), // Rule ID 3924 //
34186
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
34187
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
34188
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34189
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34190
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34191
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34192
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34193
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34194
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34195
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34196
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34197
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34198
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34199
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34200
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34201
        // MIs[1] Operand 1
34202
        // No operand predicates
34203
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34204
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34205
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34206
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34207
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34208
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34209
        // (intrinsic_wo_chain:{ *:[v16i8] } 3024:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34210
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNthu16),
34211
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34212
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34213
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34214
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34215
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34216
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34217
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34218
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34219
0
        GIR_EraseFromParent, /*InsnID*/0,
34220
        // GIR_Coverage, 3924,
34221
0
        GIR_Done,
34222
      // Label 1679: @110305
34223
0
      GIM_Try, /*On fail goto*//*Label 1680*/ GIMT_Encode4(110434), // Rule ID 3926 //
34224
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34225
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34226
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34227
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34228
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34229
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34230
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34231
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34232
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34233
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34234
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34235
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34236
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34237
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34238
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34239
        // MIs[1] Operand 1
34240
        // No operand predicates
34241
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34242
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34243
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34244
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34245
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34246
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34247
        // (intrinsic_wo_chain:{ *:[v8i16] } 3024:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34248
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhu32),
34249
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34250
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34251
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34252
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34253
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34254
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34255
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34256
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34257
0
        GIR_EraseFromParent, /*InsnID*/0,
34258
        // GIR_Coverage, 3926,
34259
0
        GIR_Done,
34260
      // Label 1680: @110434
34261
0
      GIM_Try, /*On fail goto*//*Label 1681*/ GIMT_Encode4(110563), // Rule ID 3928 //
34262
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34263
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34264
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34265
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34266
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34267
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34268
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34269
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34270
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34271
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34272
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34273
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34274
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34275
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34276
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34277
        // MIs[1] Operand 1
34278
        // No operand predicates
34279
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34280
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34281
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34282
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34283
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34284
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34285
        // (intrinsic_wo_chain:{ *:[v8i16] } 3024:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34286
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNthu32),
34287
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34288
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34289
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34290
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34291
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34292
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34293
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34294
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34295
0
        GIR_EraseFromParent, /*InsnID*/0,
34296
        // GIR_Coverage, 3928,
34297
0
        GIR_Done,
34298
      // Label 1681: @110563
34299
0
      GIM_Try, /*On fail goto*//*Label 1682*/ GIMT_Encode4(110692), // Rule ID 3930 //
34300
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
34301
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
34302
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34303
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34304
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34305
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34306
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34307
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34308
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34309
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34310
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34311
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34312
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34313
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34314
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34315
        // MIs[1] Operand 1
34316
        // No operand predicates
34317
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34318
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34319
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34320
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34321
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34322
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34323
        // (intrinsic_wo_chain:{ *:[v16i8] } 3024:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34324
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhs16),
34325
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34326
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34327
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34328
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34329
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34330
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34331
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34332
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34333
0
        GIR_EraseFromParent, /*InsnID*/0,
34334
        // GIR_Coverage, 3930,
34335
0
        GIR_Done,
34336
      // Label 1682: @110692
34337
0
      GIM_Try, /*On fail goto*//*Label 1683*/ GIMT_Encode4(110821), // Rule ID 3932 //
34338
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
34339
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
34340
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34341
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34342
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34343
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34344
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34345
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34346
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34347
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34348
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34349
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34350
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34351
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34352
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34353
        // MIs[1] Operand 1
34354
        // No operand predicates
34355
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34356
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34357
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34358
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34359
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34360
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34361
        // (intrinsic_wo_chain:{ *:[v16i8] } 3024:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34362
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNths16),
34363
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34364
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34365
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34366
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34367
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34368
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34369
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34370
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34371
0
        GIR_EraseFromParent, /*InsnID*/0,
34372
        // GIR_Coverage, 3932,
34373
0
        GIR_Done,
34374
      // Label 1683: @110821
34375
0
      GIM_Try, /*On fail goto*//*Label 1684*/ GIMT_Encode4(110950), // Rule ID 3934 //
34376
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34377
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34378
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34379
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34380
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34381
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34382
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34383
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34384
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34385
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34386
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34387
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34388
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34389
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34390
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34391
        // MIs[1] Operand 1
34392
        // No operand predicates
34393
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34394
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34395
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34396
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34397
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34398
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34399
        // (intrinsic_wo_chain:{ *:[v8i16] } 3024:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34400
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhs32),
34401
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34402
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34403
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34404
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34405
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34406
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34407
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34408
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34409
0
        GIR_EraseFromParent, /*InsnID*/0,
34410
        // GIR_Coverage, 3934,
34411
0
        GIR_Done,
34412
      // Label 1684: @110950
34413
0
      GIM_Try, /*On fail goto*//*Label 1685*/ GIMT_Encode4(111079), // Rule ID 3936 //
34414
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34415
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34416
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34417
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34418
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34419
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34420
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34421
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34422
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34423
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34424
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34425
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34426
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34427
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34428
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34429
        // MIs[1] Operand 1
34430
        // No operand predicates
34431
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34432
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34433
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34434
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34435
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34436
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34437
        // (intrinsic_wo_chain:{ *:[v8i16] } 3024:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34438
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNths32),
34439
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34440
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34441
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34442
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34443
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34444
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34445
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34446
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34447
0
        GIR_EraseFromParent, /*InsnID*/0,
34448
        // GIR_Coverage, 3936,
34449
0
        GIR_Done,
34450
      // Label 1685: @111079
34451
0
      GIM_Try, /*On fail goto*//*Label 1686*/ GIMT_Encode4(111208), // Rule ID 3938 //
34452
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
34453
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
34454
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34455
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34456
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34457
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34458
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34459
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34460
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34461
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34462
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34463
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34464
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34465
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34466
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34467
        // MIs[1] Operand 1
34468
        // No operand predicates
34469
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34470
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34471
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34472
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34473
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34474
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34475
        // (intrinsic_wo_chain:{ *:[v16i8] } 3024:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34476
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhu16),
34477
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34478
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34479
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34480
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34481
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34482
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34483
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34484
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34485
0
        GIR_EraseFromParent, /*InsnID*/0,
34486
        // GIR_Coverage, 3938,
34487
0
        GIR_Done,
34488
      // Label 1686: @111208
34489
0
      GIM_Try, /*On fail goto*//*Label 1687*/ GIMT_Encode4(111337), // Rule ID 3940 //
34490
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
34491
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
34492
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34493
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34494
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34495
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34496
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34497
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34498
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34499
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34500
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34501
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34502
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34503
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34504
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34505
        // MIs[1] Operand 1
34506
        // No operand predicates
34507
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34508
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34509
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34510
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34511
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34512
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34513
        // (intrinsic_wo_chain:{ *:[v16i8] } 3024:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34514
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNthu16),
34515
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34516
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34517
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34518
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34519
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34520
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34521
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34522
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34523
0
        GIR_EraseFromParent, /*InsnID*/0,
34524
        // GIR_Coverage, 3940,
34525
0
        GIR_Done,
34526
      // Label 1687: @111337
34527
0
      GIM_Try, /*On fail goto*//*Label 1688*/ GIMT_Encode4(111466), // Rule ID 3942 //
34528
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34529
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34530
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34531
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34532
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34533
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34534
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34535
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34536
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34537
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34538
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34539
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34540
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34541
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34542
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34543
        // MIs[1] Operand 1
34544
        // No operand predicates
34545
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34546
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34547
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34548
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34549
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34550
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34551
        // (intrinsic_wo_chain:{ *:[v8i16] } 3024:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34552
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhu32),
34553
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34554
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34555
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34556
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34557
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34558
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34559
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34560
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34561
0
        GIR_EraseFromParent, /*InsnID*/0,
34562
        // GIR_Coverage, 3942,
34563
0
        GIR_Done,
34564
      // Label 1688: @111466
34565
0
      GIM_Try, /*On fail goto*//*Label 1689*/ GIMT_Encode4(111595), // Rule ID 3944 //
34566
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34567
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34568
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34569
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34570
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34571
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34572
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34573
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34574
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34575
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34576
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34577
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34578
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34579
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34580
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34581
        // MIs[1] Operand 1
34582
        // No operand predicates
34583
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34584
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34585
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34586
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34587
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34588
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34589
        // (intrinsic_wo_chain:{ *:[v8i16] } 3024:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34590
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNthu32),
34591
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34592
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34593
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34594
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34595
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34596
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34597
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34598
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34599
0
        GIR_EraseFromParent, /*InsnID*/0,
34600
        // GIR_Coverage, 3944,
34601
0
        GIR_Done,
34602
      // Label 1689: @111595
34603
0
      GIM_Try, /*On fail goto*//*Label 1690*/ GIMT_Encode4(111724), // Rule ID 3946 //
34604
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
34605
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
34606
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34607
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34608
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34609
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34610
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34611
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34612
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34613
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34614
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34615
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34616
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34617
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34618
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34619
        // MIs[1] Operand 1
34620
        // No operand predicates
34621
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34622
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34623
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34624
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34625
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34626
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34627
        // (intrinsic_wo_chain:{ *:[v16i8] } 3024:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34628
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs16bh),
34629
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34630
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34631
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34632
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34633
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34634
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34635
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34636
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34637
0
        GIR_EraseFromParent, /*InsnID*/0,
34638
        // GIR_Coverage, 3946,
34639
0
        GIR_Done,
34640
      // Label 1690: @111724
34641
0
      GIM_Try, /*On fail goto*//*Label 1691*/ GIMT_Encode4(111853), // Rule ID 3948 //
34642
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
34643
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
34644
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34645
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34646
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34647
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34648
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34649
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34650
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34651
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34652
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34653
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34654
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34655
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34656
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34657
        // MIs[1] Operand 1
34658
        // No operand predicates
34659
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34660
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34661
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34662
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34663
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34664
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34665
        // (intrinsic_wo_chain:{ *:[v16i8] } 3024:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34666
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs16th),
34667
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34668
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34669
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34670
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34671
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34672
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34673
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34674
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34675
0
        GIR_EraseFromParent, /*InsnID*/0,
34676
        // GIR_Coverage, 3948,
34677
0
        GIR_Done,
34678
      // Label 1691: @111853
34679
0
      GIM_Try, /*On fail goto*//*Label 1692*/ GIMT_Encode4(111982), // Rule ID 3950 //
34680
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34681
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34682
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34683
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34684
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34685
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34686
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34687
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34688
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34689
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34690
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34691
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34692
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34693
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34694
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34695
        // MIs[1] Operand 1
34696
        // No operand predicates
34697
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34698
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34699
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34700
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34701
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34702
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34703
        // (intrinsic_wo_chain:{ *:[v8i16] } 3024:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34704
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs32bh),
34705
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34706
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34707
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34708
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34709
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34710
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34711
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34712
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34713
0
        GIR_EraseFromParent, /*InsnID*/0,
34714
        // GIR_Coverage, 3950,
34715
0
        GIR_Done,
34716
      // Label 1692: @111982
34717
0
      GIM_Try, /*On fail goto*//*Label 1693*/ GIMT_Encode4(112111), // Rule ID 3952 //
34718
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34719
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34720
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34721
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34722
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34723
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34724
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34725
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34726
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34727
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34728
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34729
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34730
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34731
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34732
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34733
        // MIs[1] Operand 1
34734
        // No operand predicates
34735
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34736
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34737
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34738
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34739
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34740
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34741
        // (intrinsic_wo_chain:{ *:[v8i16] } 3024:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34742
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs32th),
34743
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34744
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34745
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34746
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34747
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34748
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34749
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34750
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34751
0
        GIR_EraseFromParent, /*InsnID*/0,
34752
        // GIR_Coverage, 3952,
34753
0
        GIR_Done,
34754
      // Label 1693: @112111
34755
0
      GIM_Try, /*On fail goto*//*Label 1694*/ GIMT_Encode4(112240), // Rule ID 3954 //
34756
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
34757
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
34758
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34759
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34760
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34761
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34762
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34763
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34764
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34765
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34766
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34767
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34768
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34769
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34770
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34771
        // MIs[1] Operand 1
34772
        // No operand predicates
34773
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34774
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34775
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34776
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34777
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34778
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34779
        // (intrinsic_wo_chain:{ *:[v16i8] } 3024:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34780
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs16bh),
34781
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34782
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34783
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34784
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34785
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34786
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34787
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34788
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34789
0
        GIR_EraseFromParent, /*InsnID*/0,
34790
        // GIR_Coverage, 3954,
34791
0
        GIR_Done,
34792
      // Label 1694: @112240
34793
0
      GIM_Try, /*On fail goto*//*Label 1695*/ GIMT_Encode4(112369), // Rule ID 3956 //
34794
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
34795
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
34796
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34797
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34798
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34799
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34800
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34801
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34802
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34803
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34804
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34805
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34806
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34807
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34808
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34809
        // MIs[1] Operand 1
34810
        // No operand predicates
34811
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34812
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34813
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34814
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34815
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34816
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34817
        // (intrinsic_wo_chain:{ *:[v16i8] } 3024:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34818
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs16th),
34819
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34820
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34821
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34822
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34823
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34824
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34825
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34826
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34827
0
        GIR_EraseFromParent, /*InsnID*/0,
34828
        // GIR_Coverage, 3956,
34829
0
        GIR_Done,
34830
      // Label 1695: @112369
34831
0
      GIM_Try, /*On fail goto*//*Label 1696*/ GIMT_Encode4(112498), // Rule ID 3958 //
34832
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34833
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34834
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34835
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34836
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34837
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34838
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34839
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34840
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34841
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34842
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34843
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34844
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34845
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34846
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34847
        // MIs[1] Operand 1
34848
        // No operand predicates
34849
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34850
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34851
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34852
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34853
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34854
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34855
        // (intrinsic_wo_chain:{ *:[v8i16] } 3024:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34856
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs32bh),
34857
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34858
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34859
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34860
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34861
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34862
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34863
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34864
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34865
0
        GIR_EraseFromParent, /*InsnID*/0,
34866
        // GIR_Coverage, 3958,
34867
0
        GIR_Done,
34868
      // Label 1696: @112498
34869
0
      GIM_Try, /*On fail goto*//*Label 1697*/ GIMT_Encode4(112627), // Rule ID 3960 //
34870
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34871
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34872
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34873
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34874
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34875
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34876
0
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34877
0
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34878
0
        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34879
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34880
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34881
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34882
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34883
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34884
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34885
        // MIs[1] Operand 1
34886
        // No operand predicates
34887
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34888
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34889
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34890
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34891
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34892
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34893
        // (intrinsic_wo_chain:{ *:[v8i16] } 3024:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34894
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs32th),
34895
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
34896
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34897
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34898
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34899
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34900
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34901
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34902
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34903
0
        GIR_EraseFromParent, /*InsnID*/0,
34904
        // GIR_Coverage, 3960,
34905
0
        GIR_Done,
34906
      // Label 1697: @112627
34907
0
      GIM_Reject,
34908
    // Label 1657: @112628
34909
0
    GIM_Reject,
34910
    // Label 15: @112629
34911
0
    GIM_Try, /*On fail goto*//*Label 1698*/ GIMT_Encode4(112694),
34912
0
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/1,
34913
0
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_clrex),
34914
0
      GIM_Try, /*On fail goto*//*Label 1699*/ GIMT_Encode4(112663), // Rule ID 252 //
34915
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6K_IsARM),
34916
        // (intrinsic_void 2809:{ *:[iPTR] })  =>  (CLREX)
34917
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::CLREX),
34918
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34919
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34920
0
        GIR_EraseFromParent, /*InsnID*/0,
34921
        // GIR_Coverage, 252,
34922
0
        GIR_Done,
34923
      // Label 1699: @112663
34924
0
      GIM_Try, /*On fail goto*//*Label 1700*/ GIMT_Encode4(112693), // Rule ID 591 //
34925
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV7Clrex_IsThumb),
34926
        // (intrinsic_void 2809:{ *:[iPTR] })  =>  (t2CLREX)
34927
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2CLREX),
34928
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
34929
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34930
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34931
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34932
0
        GIR_EraseFromParent, /*InsnID*/0,
34933
        // GIR_Coverage, 591,
34934
0
        GIR_Done,
34935
      // Label 1700: @112693
34936
0
      GIM_Reject,
34937
    // Label 1698: @112694
34938
0
    GIM_Try, /*On fail goto*//*Label 1701*/ GIMT_Encode4(113587),
34939
0
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
34940
0
      GIM_Try, /*On fail goto*//*Label 1702*/ GIMT_Encode4(112743), // Rule ID 351 //
34941
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsWindows),
34942
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined),
34943
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
34944
0
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, GIMT_Encode8(249),
34945
        // (intrinsic_void 3250:{ *:[iPTR] }, 249:{ *:[i32] })  =>  (t__brkdiv0)
34946
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t__brkdiv0),
34947
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34948
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34949
0
        GIR_EraseFromParent, /*InsnID*/0,
34950
        // GIR_Coverage, 351,
34951
0
        GIR_Done,
34952
      // Label 1702: @112743
34953
0
      GIM_Try, /*On fail goto*//*Label 1703*/ GIMT_Encode4(112800), // Rule ID 2 //
34954
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
34955
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint),
34956
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
34957
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34958
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34959
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_239),
34960
        // MIs[1] Operand 1
34961
        // No operand predicates
34962
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34963
        // (intrinsic_void 2827:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm)  =>  (HINT (imm:{ *:[i32] }):$imm)
34964
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::HINT),
34965
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34966
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
34967
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34968
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
34969
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34970
0
        GIR_EraseFromParent, /*InsnID*/0,
34971
        // GIR_Coverage, 2,
34972
0
        GIR_Done,
34973
      // Label 1703: @112800
34974
0
      GIM_Try, /*On fail goto*//*Label 1704*/ GIMT_Encode4(112857), // Rule ID 10 //
34975
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV7_IsARM),
34976
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dbg),
34977
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
34978
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34979
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34980
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
34981
        // MIs[1] Operand 1
34982
        // No operand predicates
34983
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
34984
        // (intrinsic_void 2822:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (DBG (imm:{ *:[i32] }):$opt)
34985
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::DBG),
34986
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
34987
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
34988
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34989
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
34990
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34991
0
        GIR_EraseFromParent, /*InsnID*/0,
34992
        // GIR_Coverage, 10,
34993
0
        GIR_Done,
34994
      // Label 1704: @112857
34995
0
      GIM_Try, /*On fail goto*//*Label 1705*/ GIMT_Encode4(112905), // Rule ID 11 //
34996
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
34997
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined),
34998
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
34999
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35000
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35001
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535),
35002
        // MIs[1] Operand 1
35003
        // No operand predicates
35004
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
35005
        // (intrinsic_void 3250:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16)  =>  (UDF (imm:{ *:[i32] }):$imm16)
35006
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UDF),
35007
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
35008
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35009
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35010
0
        GIR_EraseFromParent, /*InsnID*/0,
35011
        // GIR_Coverage, 11,
35012
0
        GIR_Done,
35013
      // Label 1705: @112905
35014
0
      GIM_Try, /*On fail goto*//*Label 1706*/ GIMT_Encode4(112953), // Rule ID 235 //
35015
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsARM),
35016
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dmb),
35017
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35018
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35019
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35020
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35021
        // MIs[1] Operand 1
35022
        // No operand predicates
35023
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
35024
        // (intrinsic_void 2823:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (DMB (imm:{ *:[i32] }):$opt)
35025
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::DMB),
35026
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35027
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35028
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35029
0
        GIR_EraseFromParent, /*InsnID*/0,
35030
        // GIR_Coverage, 235,
35031
0
        GIR_Done,
35032
      // Label 1706: @112953
35033
0
      GIM_Try, /*On fail goto*//*Label 1707*/ GIMT_Encode4(113001), // Rule ID 236 //
35034
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsARM),
35035
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dsb),
35036
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35037
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35038
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35039
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35040
        // MIs[1] Operand 1
35041
        // No operand predicates
35042
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
35043
        // (intrinsic_void 2824:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (DSB (imm:{ *:[i32] }):$opt)
35044
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::DSB),
35045
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35046
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35047
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35048
0
        GIR_EraseFromParent, /*InsnID*/0,
35049
        // GIR_Coverage, 236,
35050
0
        GIR_Done,
35051
      // Label 1707: @113001
35052
0
      GIM_Try, /*On fail goto*//*Label 1708*/ GIMT_Encode4(113049), // Rule ID 237 //
35053
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsARM),
35054
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_isb),
35055
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35056
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35057
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35058
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35059
        // MIs[1] Operand 1
35060
        // No operand predicates
35061
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
35062
        // (intrinsic_void 2828:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (ISB (imm:{ *:[i32] }):$opt)
35063
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::ISB),
35064
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35065
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35066
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35067
0
        GIR_EraseFromParent, /*InsnID*/0,
35068
        // GIR_Coverage, 237,
35069
0
        GIR_Done,
35070
      // Label 1708: @113049
35071
0
      GIM_Try, /*On fail goto*//*Label 1709*/ GIMT_Encode4(113106), // Rule ID 283 //
35072
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6M_IsThumb),
35073
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint),
35074
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35075
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35076
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35077
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35078
        // MIs[1] Operand 1
35079
        // No operand predicates
35080
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
35081
        // (intrinsic_void 2827:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)  =>  (tHINT (imm:{ *:[i32] }):$imm)
35082
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::tHINT),
35083
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35084
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35085
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35086
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35087
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35088
0
        GIR_EraseFromParent, /*InsnID*/0,
35089
        // GIR_Coverage, 283,
35090
0
        GIR_Done,
35091
      // Label 1709: @113106
35092
0
      GIM_Try, /*On fail goto*//*Label 1710*/ GIMT_Encode4(113154), // Rule ID 350 //
35093
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb),
35094
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined),
35095
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35096
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35097
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35098
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255),
35099
        // MIs[1] Operand 1
35100
        // No operand predicates
35101
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
35102
        // (intrinsic_void 3250:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_255>>:$imm8)  =>  (tUDF (imm:{ *:[i32] }):$imm8)
35103
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::tUDF),
35104
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm8
35105
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35106
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35107
0
        GIR_EraseFromParent, /*InsnID*/0,
35108
        // GIR_Coverage, 350,
35109
0
        GIR_Done,
35110
      // Label 1710: @113154
35111
0
      GIM_Try, /*On fail goto*//*Label 1711*/ GIMT_Encode4(113202), // Rule ID 502 //
35112
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
35113
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined),
35114
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35115
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35116
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35117
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535),
35118
        // MIs[1] Operand 1
35119
        // No operand predicates
35120
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
35121
        // (intrinsic_void 3250:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16)  =>  (t2UDF (imm:{ *:[i32] }):$imm16)
35122
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UDF),
35123
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
35124
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35125
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35126
0
        GIR_EraseFromParent, /*InsnID*/0,
35127
        // GIR_Coverage, 502,
35128
0
        GIR_Done,
35129
      // Label 1711: @113202
35130
0
      GIM_Try, /*On fail goto*//*Label 1712*/ GIMT_Encode4(113259), // Rule ID 576 //
35131
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsThumb),
35132
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dmb),
35133
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35134
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35135
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35136
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35137
        // MIs[1] Operand 1
35138
        // No operand predicates
35139
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
35140
        // (intrinsic_void 2823:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (t2DMB (imm:{ *:[i32] }):$opt)
35141
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2DMB),
35142
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35143
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35144
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35145
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35146
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35147
0
        GIR_EraseFromParent, /*InsnID*/0,
35148
        // GIR_Coverage, 576,
35149
0
        GIR_Done,
35150
      // Label 1712: @113259
35151
0
      GIM_Try, /*On fail goto*//*Label 1713*/ GIMT_Encode4(113316), // Rule ID 577 //
35152
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsThumb),
35153
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dsb),
35154
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35155
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35156
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35157
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35158
        // MIs[1] Operand 1
35159
        // No operand predicates
35160
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
35161
        // (intrinsic_void 2824:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (t2DSB (imm:{ *:[i32] }):$opt)
35162
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2DSB),
35163
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35164
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35165
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35166
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35167
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35168
0
        GIR_EraseFromParent, /*InsnID*/0,
35169
        // GIR_Coverage, 577,
35170
0
        GIR_Done,
35171
      // Label 1713: @113316
35172
0
      GIM_Try, /*On fail goto*//*Label 1714*/ GIMT_Encode4(113373), // Rule ID 578 //
35173
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsThumb),
35174
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_isb),
35175
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35176
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35177
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35178
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35179
        // MIs[1] Operand 1
35180
        // No operand predicates
35181
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
35182
        // (intrinsic_void 2828:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (t2ISB (imm:{ *:[i32] }):$opt)
35183
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2ISB),
35184
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35185
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35186
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35187
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35188
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35189
0
        GIR_EraseFromParent, /*InsnID*/0,
35190
        // GIR_Coverage, 578,
35191
0
        GIR_Done,
35192
      // Label 1714: @113373
35193
0
      GIM_Try, /*On fail goto*//*Label 1715*/ GIMT_Encode4(113430), // Rule ID 596 //
35194
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
35195
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint),
35196
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35197
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35198
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35199
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_239),
35200
        // MIs[1] Operand 1
35201
        // No operand predicates
35202
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
35203
        // (intrinsic_void 2827:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm)  =>  (t2HINT (imm:{ *:[i32] }):$imm)
35204
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2HINT),
35205
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35206
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35207
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35208
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35209
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35210
0
        GIR_EraseFromParent, /*InsnID*/0,
35211
        // GIR_Coverage, 596,
35212
0
        GIR_Done,
35213
      // Label 1715: @113430
35214
0
      GIM_Try, /*On fail goto*//*Label 1716*/ GIMT_Encode4(113487), // Rule ID 597 //
35215
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
35216
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dbg),
35217
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35218
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35219
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35220
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35221
        // MIs[1] Operand 1
35222
        // No operand predicates
35223
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
35224
        // (intrinsic_void 2822:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (t2DBG (imm:{ *:[i32] }):$opt)
35225
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2DBG),
35226
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35227
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35228
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35229
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35230
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35231
0
        GIR_EraseFromParent, /*InsnID*/0,
35232
        // GIR_Coverage, 597,
35233
0
        GIR_Done,
35234
      // Label 1716: @113487
35235
0
      GIM_Try, /*On fail goto*//*Label 1717*/ GIMT_Encode4(113535), // Rule ID 742 //
35236
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs),
35237
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_get_fpscr),
35238
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35239
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35240
        // (intrinsic_w_chain:{ *:[i32] } 2825:{ *:[iPTR] })  =>  (VMRS:{ *:[i32] })
35241
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMRS),
35242
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rt]
35243
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35244
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35245
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35246
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35247
0
        GIR_EraseFromParent, /*InsnID*/0,
35248
        // GIR_Coverage, 742,
35249
0
        GIR_Done,
35250
      // Label 1717: @113535
35251
0
      GIM_Try, /*On fail goto*//*Label 1718*/ GIMT_Encode4(113586), // Rule ID 743 //
35252
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs),
35253
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_set_fpscr),
35254
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35255
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35256
        // (intrinsic_void 3194:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rt)  =>  (VMSR GPRnopc:{ *:[i32] }:$Rt)
35257
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMSR),
35258
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rt
35259
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35260
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35261
0
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0,
35262
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35263
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35264
0
        GIR_EraseFromParent, /*InsnID*/0,
35265
        // GIR_Coverage, 743,
35266
0
        GIR_Done,
35267
      // Label 1718: @113586
35268
0
      GIM_Reject,
35269
    // Label 1701: @113587
35270
0
    GIM_Try, /*On fail goto*//*Label 1719*/ GIMT_Encode4(113642), // Rule ID 621 //
35271
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLOB_HasV8_1MMainline_IsThumb2),
35272
0
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
35273
0
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::start_loop_iterations),
35274
0
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35275
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35276
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRlrRegClassID),
35277
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35278
      // (intrinsic_w_chain:{ *:[i32] } 316:{ *:[iPTR] }, rGPR:{ *:[i32] }:$tc)  =>  (t2DoLoopStart:{ *:[i32] } rGPR:{ *:[i32] }:$tc)
35279
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2DoLoopStart),
35280
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[X]
35281
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // tc
35282
0
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35283
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35284
0
      GIR_EraseFromParent, /*InsnID*/0,
35285
      // GIR_Coverage, 621,
35286
0
      GIR_Done,
35287
    // Label 1719: @113642
35288
0
    GIM_Try, /*On fail goto*//*Label 1720*/ GIMT_Encode4(116167),
35289
0
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
35290
0
      GIM_Try, /*On fail goto*//*Label 1721*/ GIMT_Encode4(113717), // Rule ID 5177 //
35291
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base),
35292
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
35293
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
35294
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35295
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35296
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35297
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
35298
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35299
        // MIs[1] Operand 1
35300
        // No operand predicates
35301
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
35302
        // (intrinsic_w_chain:{ *:[v4i32] } 2958:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)  =>  (MVE_VLDRWU32_qi:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
35303
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_qi),
35304
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
35305
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
35306
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35307
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35308
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35309
0
        GIR_EraseFromParent, /*InsnID*/0,
35310
        // GIR_Coverage, 5177,
35311
0
        GIR_Done,
35312
      // Label 1721: @113717
35313
0
      GIM_Try, /*On fail goto*//*Label 1722*/ GIMT_Encode4(113784), // Rule ID 5183 //
35314
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base),
35315
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
35316
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
35317
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35318
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35319
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35320
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
35321
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35322
        // MIs[1] Operand 1
35323
        // No operand predicates
35324
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
35325
        // (intrinsic_w_chain:{ *:[v4f32] } 2958:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)  =>  (MVE_VLDRWU32_qi:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
35326
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_qi),
35327
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
35328
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
35329
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35330
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35331
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35332
0
        GIR_EraseFromParent, /*InsnID*/0,
35333
        // GIR_Coverage, 5183,
35334
0
        GIR_Done,
35335
      // Label 1722: @113784
35336
0
      GIM_Try, /*On fail goto*//*Label 1723*/ GIMT_Encode4(113851), // Rule ID 5185 //
35337
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base),
35338
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
35339
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
35340
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35341
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35342
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35343
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
35344
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35345
        // MIs[1] Operand 1
35346
        // No operand predicates
35347
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
35348
        // (intrinsic_w_chain:{ *:[v2i64] } 2958:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)  =>  (MVE_VLDRDU64_qi:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
35349
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_qi),
35350
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
35351
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
35352
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35353
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35354
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35355
0
        GIR_EraseFromParent, /*InsnID*/0,
35356
        // GIR_Coverage, 5185,
35357
0
        GIR_Done,
35358
      // Label 1723: @113851
35359
0
      GIM_Try, /*On fail goto*//*Label 1724*/ GIMT_Encode4(113918), // Rule ID 5187 //
35360
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base),
35361
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
35362
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
35363
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35364
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35365
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35366
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
35367
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35368
        // MIs[1] Operand 1
35369
        // No operand predicates
35370
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
35371
        // (intrinsic_w_chain:{ *:[v2f64] } 2958:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)  =>  (MVE_VLDRDU64_qi:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
35372
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_qi),
35373
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
35374
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
35375
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35376
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35377
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35378
0
        GIR_EraseFromParent, /*InsnID*/0,
35379
        // GIR_Coverage, 5187,
35380
0
        GIR_Done,
35381
      // Label 1724: @113918
35382
0
      GIM_Try, /*On fail goto*//*Label 1725*/ GIMT_Encode4(113974), // Rule ID 1765 //
35383
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_space),
35384
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35385
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35386
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35387
        // MIs[0] size
35388
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
35389
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35390
        // (intrinsic_w_chain:{ *:[i32] } 3225:{ *:[iPTR] }, (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn)  =>  (SPACE:{ *:[i32] } (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn)
35391
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SPACE),
35392
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35393
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // size
35394
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
35395
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35396
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35397
0
        GIR_EraseFromParent, /*InsnID*/0,
35398
        // GIR_Coverage, 1765,
35399
0
        GIR_Done,
35400
      // Label 1725: @113974
35401
0
      GIM_Try, /*On fail goto*//*Label 1726*/ GIMT_Encode4(114041), // Rule ID 5179 //
35402
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base),
35403
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
35404
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35405
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
35406
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35407
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
35408
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35409
        // MIs[1] Operand 1
35410
        // No operand predicates
35411
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35412
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
35413
        // (intrinsic_void 3032:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data)  =>  (MVE_VSTRW32_qi MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
35414
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi),
35415
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
35416
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
35417
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35418
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35419
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35420
0
        GIR_EraseFromParent, /*InsnID*/0,
35421
        // GIR_Coverage, 5179,
35422
0
        GIR_Done,
35423
      // Label 1726: @114041
35424
0
      GIM_Try, /*On fail goto*//*Label 1727*/ GIMT_Encode4(114108), // Rule ID 5189 //
35425
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base),
35426
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
35427
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35428
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
35429
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35430
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
35431
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35432
        // MIs[1] Operand 1
35433
        // No operand predicates
35434
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35435
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
35436
        // (intrinsic_void 3032:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data)  =>  (MVE_VSTRW32_qi MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
35437
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi),
35438
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
35439
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
35440
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35441
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35442
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35443
0
        GIR_EraseFromParent, /*InsnID*/0,
35444
        // GIR_Coverage, 5189,
35445
0
        GIR_Done,
35446
      // Label 1727: @114108
35447
0
      GIM_Try, /*On fail goto*//*Label 1728*/ GIMT_Encode4(114175), // Rule ID 5193 //
35448
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base),
35449
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
35450
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35451
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
35452
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35453
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
35454
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35455
        // MIs[1] Operand 1
35456
        // No operand predicates
35457
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35458
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
35459
        // (intrinsic_void 3032:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data)  =>  (MVE_VSTRD64_qi MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
35460
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi),
35461
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
35462
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
35463
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35464
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35465
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35466
0
        GIR_EraseFromParent, /*InsnID*/0,
35467
        // GIR_Coverage, 5193,
35468
0
        GIR_Done,
35469
      // Label 1728: @114175
35470
0
      GIM_Try, /*On fail goto*//*Label 1729*/ GIMT_Encode4(114242), // Rule ID 5197 //
35471
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base),
35472
0
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
35473
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35474
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
35475
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35476
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
35477
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35478
        // MIs[1] Operand 1
35479
        // No operand predicates
35480
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35481
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
35482
        // (intrinsic_void 3032:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data)  =>  (MVE_VSTRD64_qi MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
35483
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi),
35484
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
35485
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
35486
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35487
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35488
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35489
0
        GIR_EraseFromParent, /*InsnID*/0,
35490
        // GIR_Coverage, 5197,
35491
0
        GIR_Done,
35492
      // Label 1729: @114242
35493
0
      GIM_Try, /*On fail goto*//*Label 1730*/ GIMT_Encode4(114316), // Rule ID 3 //
35494
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
35495
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sel),
35496
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35497
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35498
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35499
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35500
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35501
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35502
        // (intrinsic_w_chain:{ *:[i32] } 3193:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
35503
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SEL),
35504
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35505
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35506
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35507
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35508
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35509
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35510
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35511
0
        GIR_EraseFromParent, /*InsnID*/0,
35512
        // GIR_Coverage, 3,
35513
0
        GIR_Done,
35514
      // Label 1730: @114316
35515
0
      GIM_Try, /*On fail goto*//*Label 1731*/ GIMT_Encode4(114390), // Rule ID 121 //
35516
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35517
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sasx),
35518
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35519
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35520
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35521
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35522
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35523
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35524
        // (intrinsic_w_chain:{ *:[i32] } 3192:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35525
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SASX),
35526
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35527
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35528
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35529
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35530
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35531
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35532
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35533
0
        GIR_EraseFromParent, /*InsnID*/0,
35534
        // GIR_Coverage, 121,
35535
0
        GIR_Done,
35536
      // Label 1731: @114390
35537
0
      GIM_Try, /*On fail goto*//*Label 1732*/ GIMT_Encode4(114464), // Rule ID 122 //
35538
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35539
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd16),
35540
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35541
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35542
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35543
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35544
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35545
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35546
        // (intrinsic_w_chain:{ *:[i32] } 3190:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35547
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SADD16),
35548
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35549
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35550
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35551
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35552
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35553
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35554
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35555
0
        GIR_EraseFromParent, /*InsnID*/0,
35556
        // GIR_Coverage, 122,
35557
0
        GIR_Done,
35558
      // Label 1732: @114464
35559
0
      GIM_Try, /*On fail goto*//*Label 1733*/ GIMT_Encode4(114538), // Rule ID 123 //
35560
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35561
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd8),
35562
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35563
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35564
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35565
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35566
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35567
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35568
        // (intrinsic_w_chain:{ *:[i32] } 3191:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35569
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SADD8),
35570
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35571
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35572
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35573
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35574
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35575
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35576
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35577
0
        GIR_EraseFromParent, /*InsnID*/0,
35578
        // GIR_Coverage, 123,
35579
0
        GIR_Done,
35580
      // Label 1733: @114538
35581
0
      GIM_Try, /*On fail goto*//*Label 1734*/ GIMT_Encode4(114612), // Rule ID 124 //
35582
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35583
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssax),
35584
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35585
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35586
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35587
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35588
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35589
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35590
        // (intrinsic_w_chain:{ *:[i32] } 3228:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35591
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SSAX),
35592
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35593
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35594
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35595
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35596
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35597
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35598
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35599
0
        GIR_EraseFromParent, /*InsnID*/0,
35600
        // GIR_Coverage, 124,
35601
0
        GIR_Done,
35602
      // Label 1734: @114612
35603
0
      GIM_Try, /*On fail goto*//*Label 1735*/ GIMT_Encode4(114686), // Rule ID 125 //
35604
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35605
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub16),
35606
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35607
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35608
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35609
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35610
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35611
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35612
        // (intrinsic_w_chain:{ *:[i32] } 3229:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35613
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SSUB16),
35614
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35615
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35616
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35617
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35618
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35619
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35620
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35621
0
        GIR_EraseFromParent, /*InsnID*/0,
35622
        // GIR_Coverage, 125,
35623
0
        GIR_Done,
35624
      // Label 1735: @114686
35625
0
      GIM_Try, /*On fail goto*//*Label 1736*/ GIMT_Encode4(114760), // Rule ID 126 //
35626
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35627
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub8),
35628
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35629
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35630
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35631
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35632
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35633
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35634
        // (intrinsic_w_chain:{ *:[i32] } 3230:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35635
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SSUB8),
35636
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35637
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35638
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35639
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35640
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35641
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35642
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35643
0
        GIR_EraseFromParent, /*InsnID*/0,
35644
        // GIR_Coverage, 126,
35645
0
        GIR_Done,
35646
      // Label 1736: @114760
35647
0
      GIM_Try, /*On fail goto*//*Label 1737*/ GIMT_Encode4(114834), // Rule ID 127 //
35648
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35649
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uasx),
35650
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35651
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35652
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35653
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35654
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35655
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35656
        // (intrinsic_w_chain:{ *:[i32] } 3243:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35657
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UASX),
35658
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35659
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35660
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35661
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35662
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35663
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35664
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35665
0
        GIR_EraseFromParent, /*InsnID*/0,
35666
        // GIR_Coverage, 127,
35667
0
        GIR_Done,
35668
      // Label 1737: @114834
35669
0
      GIM_Try, /*On fail goto*//*Label 1738*/ GIMT_Encode4(114908), // Rule ID 128 //
35670
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35671
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd16),
35672
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35673
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35674
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35675
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35676
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35677
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35678
        // (intrinsic_w_chain:{ *:[i32] } 3241:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35679
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UADD16),
35680
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35681
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35682
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35683
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35684
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35685
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35686
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35687
0
        GIR_EraseFromParent, /*InsnID*/0,
35688
        // GIR_Coverage, 128,
35689
0
        GIR_Done,
35690
      // Label 1738: @114908
35691
0
      GIM_Try, /*On fail goto*//*Label 1739*/ GIMT_Encode4(114982), // Rule ID 129 //
35692
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35693
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd8),
35694
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35695
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35696
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35697
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35698
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35699
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35700
        // (intrinsic_w_chain:{ *:[i32] } 3242:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35701
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::UADD8),
35702
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35703
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35704
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35705
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35706
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35707
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35708
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35709
0
        GIR_EraseFromParent, /*InsnID*/0,
35710
        // GIR_Coverage, 129,
35711
0
        GIR_Done,
35712
      // Label 1739: @114982
35713
0
      GIM_Try, /*On fail goto*//*Label 1740*/ GIMT_Encode4(115056), // Rule ID 130 //
35714
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35715
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usax),
35716
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35717
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35718
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35719
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35720
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35721
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35722
        // (intrinsic_w_chain:{ *:[i32] } 3261:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (USAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35723
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::USAX),
35724
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35725
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35726
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35727
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35728
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35729
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35730
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35731
0
        GIR_EraseFromParent, /*InsnID*/0,
35732
        // GIR_Coverage, 130,
35733
0
        GIR_Done,
35734
      // Label 1740: @115056
35735
0
      GIM_Try, /*On fail goto*//*Label 1741*/ GIMT_Encode4(115130), // Rule ID 131 //
35736
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35737
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub16),
35738
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35739
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35740
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35741
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35742
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35743
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35744
        // (intrinsic_w_chain:{ *:[i32] } 3262:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (USUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35745
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::USUB16),
35746
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35747
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35748
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35749
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35750
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35751
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35752
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35753
0
        GIR_EraseFromParent, /*InsnID*/0,
35754
        // GIR_Coverage, 131,
35755
0
        GIR_Done,
35756
      // Label 1741: @115130
35757
0
      GIM_Try, /*On fail goto*//*Label 1742*/ GIMT_Encode4(115204), // Rule ID 132 //
35758
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35759
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub8),
35760
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35761
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35762
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35763
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35764
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35765
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35766
        // (intrinsic_w_chain:{ *:[i32] } 3263:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (USUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35767
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::USUB8),
35768
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35769
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35770
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35771
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35772
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35773
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35774
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35775
0
        GIR_EraseFromParent, /*InsnID*/0,
35776
        // GIR_Coverage, 132,
35777
0
        GIR_Done,
35778
      // Label 1742: @115204
35779
0
      GIM_Try, /*On fail goto*//*Label 1743*/ GIMT_Encode4(115278), // Rule ID 439 //
35780
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
35781
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sel),
35782
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35783
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35784
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35785
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35786
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35787
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35788
        // (intrinsic_w_chain:{ *:[i32] } 3193:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (t2SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
35789
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SEL),
35790
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35791
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35792
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35793
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35794
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35795
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35796
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35797
0
        GIR_EraseFromParent, /*InsnID*/0,
35798
        // GIR_Coverage, 439,
35799
0
        GIR_Done,
35800
      // Label 1743: @115278
35801
0
      GIM_Try, /*On fail goto*//*Label 1744*/ GIMT_Encode4(115352), // Rule ID 452 //
35802
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
35803
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sasx),
35804
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35805
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35806
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35807
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35808
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35809
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35810
        // (intrinsic_w_chain:{ *:[i32] } 3192:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
35811
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SASX),
35812
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35813
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35814
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35815
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35816
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35817
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35818
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35819
0
        GIR_EraseFromParent, /*InsnID*/0,
35820
        // GIR_Coverage, 452,
35821
0
        GIR_Done,
35822
      // Label 1744: @115352
35823
0
      GIM_Try, /*On fail goto*//*Label 1745*/ GIMT_Encode4(115426), // Rule ID 453 //
35824
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
35825
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd16),
35826
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35827
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35828
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35829
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35830
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35831
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35832
        // (intrinsic_w_chain:{ *:[i32] } 3190:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
35833
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SADD16),
35834
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35835
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35836
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35837
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35838
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35839
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35840
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35841
0
        GIR_EraseFromParent, /*InsnID*/0,
35842
        // GIR_Coverage, 453,
35843
0
        GIR_Done,
35844
      // Label 1745: @115426
35845
0
      GIM_Try, /*On fail goto*//*Label 1746*/ GIMT_Encode4(115500), // Rule ID 454 //
35846
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
35847
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd8),
35848
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35849
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35850
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35851
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35852
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35853
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35854
        // (intrinsic_w_chain:{ *:[i32] } 3191:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
35855
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SADD8),
35856
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35857
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35858
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35859
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35860
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35861
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35862
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35863
0
        GIR_EraseFromParent, /*InsnID*/0,
35864
        // GIR_Coverage, 454,
35865
0
        GIR_Done,
35866
      // Label 1746: @115500
35867
0
      GIM_Try, /*On fail goto*//*Label 1747*/ GIMT_Encode4(115574), // Rule ID 455 //
35868
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
35869
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssax),
35870
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35871
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35872
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35873
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35874
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35875
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35876
        // (intrinsic_w_chain:{ *:[i32] } 3228:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
35877
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SSAX),
35878
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35879
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35880
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35881
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35882
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35883
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35884
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35885
0
        GIR_EraseFromParent, /*InsnID*/0,
35886
        // GIR_Coverage, 455,
35887
0
        GIR_Done,
35888
      // Label 1747: @115574
35889
0
      GIM_Try, /*On fail goto*//*Label 1748*/ GIMT_Encode4(115648), // Rule ID 456 //
35890
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
35891
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub16),
35892
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35893
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35894
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35895
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35896
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35897
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35898
        // (intrinsic_w_chain:{ *:[i32] } 3229:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
35899
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SSUB16),
35900
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35901
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35902
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35903
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35904
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35905
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35906
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35907
0
        GIR_EraseFromParent, /*InsnID*/0,
35908
        // GIR_Coverage, 456,
35909
0
        GIR_Done,
35910
      // Label 1748: @115648
35911
0
      GIM_Try, /*On fail goto*//*Label 1749*/ GIMT_Encode4(115722), // Rule ID 457 //
35912
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
35913
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub8),
35914
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35915
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35916
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35917
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35918
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35919
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35920
        // (intrinsic_w_chain:{ *:[i32] } 3230:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
35921
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SSUB8),
35922
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35923
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35924
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35925
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35926
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35927
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35928
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35929
0
        GIR_EraseFromParent, /*InsnID*/0,
35930
        // GIR_Coverage, 457,
35931
0
        GIR_Done,
35932
      // Label 1749: @115722
35933
0
      GIM_Try, /*On fail goto*//*Label 1750*/ GIMT_Encode4(115796), // Rule ID 458 //
35934
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
35935
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uasx),
35936
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35937
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35938
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35939
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35940
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35941
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35942
        // (intrinsic_w_chain:{ *:[i32] } 3243:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
35943
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UASX),
35944
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35945
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35946
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35947
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35948
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35949
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35950
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35951
0
        GIR_EraseFromParent, /*InsnID*/0,
35952
        // GIR_Coverage, 458,
35953
0
        GIR_Done,
35954
      // Label 1750: @115796
35955
0
      GIM_Try, /*On fail goto*//*Label 1751*/ GIMT_Encode4(115870), // Rule ID 459 //
35956
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
35957
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd16),
35958
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35959
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35960
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35961
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35962
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35963
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35964
        // (intrinsic_w_chain:{ *:[i32] } 3241:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
35965
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UADD16),
35966
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35967
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35968
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35969
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35970
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35971
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35972
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35973
0
        GIR_EraseFromParent, /*InsnID*/0,
35974
        // GIR_Coverage, 459,
35975
0
        GIR_Done,
35976
      // Label 1751: @115870
35977
0
      GIM_Try, /*On fail goto*//*Label 1752*/ GIMT_Encode4(115944), // Rule ID 460 //
35978
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
35979
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd8),
35980
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35981
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35982
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35983
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35984
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35985
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35986
        // (intrinsic_w_chain:{ *:[i32] } 3242:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
35987
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2UADD8),
35988
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
35989
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35990
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35991
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35992
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35993
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35994
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35995
0
        GIR_EraseFromParent, /*InsnID*/0,
35996
        // GIR_Coverage, 460,
35997
0
        GIR_Done,
35998
      // Label 1752: @115944
35999
0
      GIM_Try, /*On fail goto*//*Label 1753*/ GIMT_Encode4(116018), // Rule ID 461 //
36000
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36001
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usax),
36002
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
36003
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
36004
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36005
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36006
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36007
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36008
        // (intrinsic_w_chain:{ *:[i32] } 3261:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2USAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36009
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2USAX),
36010
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
36011
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
36012
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
36013
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36014
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36015
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36016
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36017
0
        GIR_EraseFromParent, /*InsnID*/0,
36018
        // GIR_Coverage, 461,
36019
0
        GIR_Done,
36020
      // Label 1753: @116018
36021
0
      GIM_Try, /*On fail goto*//*Label 1754*/ GIMT_Encode4(116092), // Rule ID 462 //
36022
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36023
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub16),
36024
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
36025
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
36026
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36027
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36028
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36029
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36030
        // (intrinsic_w_chain:{ *:[i32] } 3262:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2USUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36031
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2USUB16),
36032
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
36033
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
36034
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
36035
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36036
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36037
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36038
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36039
0
        GIR_EraseFromParent, /*InsnID*/0,
36040
        // GIR_Coverage, 462,
36041
0
        GIR_Done,
36042
      // Label 1754: @116092
36043
0
      GIM_Try, /*On fail goto*//*Label 1755*/ GIMT_Encode4(116166), // Rule ID 463 //
36044
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36045
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub8),
36046
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
36047
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
36048
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36049
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36050
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36051
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36052
        // (intrinsic_w_chain:{ *:[i32] } 3263:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2USUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36053
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2USUB8),
36054
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
36055
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
36056
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
36057
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36058
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36059
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36060
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36061
0
        GIR_EraseFromParent, /*InsnID*/0,
36062
        // GIR_Coverage, 463,
36063
0
        GIR_Done,
36064
      // Label 1755: @116166
36065
0
      GIM_Reject,
36066
    // Label 1720: @116167
36067
0
    GIM_Try, /*On fail goto*//*Label 1756*/ GIMT_Encode4(116481),
36068
0
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
36069
0
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base_wb),
36070
0
      GIM_Try, /*On fail goto*//*Label 1757*/ GIMT_Encode4(116255), // Rule ID 5181 //
36071
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36072
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
36073
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36074
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
36075
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36076
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36077
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
36078
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36079
        // MIs[1] Operand 1
36080
        // No operand predicates
36081
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36082
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
36083
        // (intrinsic_w_chain:{ *:[v4i32] } 3034:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data)  =>  (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
36084
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi_pre),
36085
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[wb]
36086
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // data
36087
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
36088
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
36089
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
36090
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36091
0
        GIR_EraseFromParent, /*InsnID*/0,
36092
        // GIR_Coverage, 5181,
36093
0
        GIR_Done,
36094
      // Label 1757: @116255
36095
0
      GIM_Try, /*On fail goto*//*Label 1758*/ GIMT_Encode4(116330), // Rule ID 5191 //
36096
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36097
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
36098
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36099
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
36100
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36101
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36102
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
36103
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36104
        // MIs[1] Operand 1
36105
        // No operand predicates
36106
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36107
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
36108
        // (intrinsic_w_chain:{ *:[v4i32] } 3034:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data)  =>  (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
36109
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi_pre),
36110
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[wb]
36111
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // data
36112
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
36113
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
36114
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
36115
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36116
0
        GIR_EraseFromParent, /*InsnID*/0,
36117
        // GIR_Coverage, 5191,
36118
0
        GIR_Done,
36119
      // Label 1758: @116330
36120
0
      GIM_Try, /*On fail goto*//*Label 1759*/ GIMT_Encode4(116405), // Rule ID 5195 //
36121
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
36122
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
36123
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36124
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
36125
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36126
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36127
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
36128
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36129
        // MIs[1] Operand 1
36130
        // No operand predicates
36131
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36132
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
36133
        // (intrinsic_w_chain:{ *:[v2i64] } 3034:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data)  =>  (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
36134
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi_pre),
36135
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[wb]
36136
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // data
36137
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
36138
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
36139
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
36140
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36141
0
        GIR_EraseFromParent, /*InsnID*/0,
36142
        // GIR_Coverage, 5195,
36143
0
        GIR_Done,
36144
      // Label 1759: @116405
36145
0
      GIM_Try, /*On fail goto*//*Label 1760*/ GIMT_Encode4(116480), // Rule ID 5199 //
36146
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
36147
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
36148
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36149
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
36150
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36151
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36152
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
36153
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36154
        // MIs[1] Operand 1
36155
        // No operand predicates
36156
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36157
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
36158
        // (intrinsic_w_chain:{ *:[v2i64] } 3034:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data)  =>  (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
36159
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi_pre),
36160
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[wb]
36161
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // data
36162
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
36163
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
36164
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
36165
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36166
0
        GIR_EraseFromParent, /*InsnID*/0,
36167
        // GIR_Coverage, 5199,
36168
0
        GIR_Done,
36169
      // Label 1760: @116480
36170
0
      GIM_Reject,
36171
    // Label 1756: @116481
36172
0
    GIM_Try, /*On fail goto*//*Label 1761*/ GIMT_Encode4(117979),
36173
0
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
36174
0
      GIM_Try, /*On fail goto*//*Label 1762*/ GIMT_Encode4(116567), // Rule ID 5069 //
36175
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36176
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
36177
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
36178
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36179
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36180
        // MIs[0] base
36181
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36182
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36183
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36184
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36185
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
36186
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36187
        // (intrinsic_void 3036:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRH16_rq_u MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36188
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq_u),
36189
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36190
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36191
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36192
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36193
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36194
0
        GIR_EraseFromParent, /*InsnID*/0,
36195
        // GIR_Coverage, 5069,
36196
0
        GIR_Done,
36197
      // Label 1762: @116567
36198
0
      GIM_Try, /*On fail goto*//*Label 1763*/ GIMT_Encode4(116645), // Rule ID 5070 //
36199
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36200
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
36201
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
36202
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36203
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36204
        // MIs[0] base
36205
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36206
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36207
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36208
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36209
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
36210
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
36211
        // (intrinsic_void 3036:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSTRH16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36212
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq),
36213
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36214
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36215
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36216
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36217
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36218
0
        GIR_EraseFromParent, /*InsnID*/0,
36219
        // GIR_Coverage, 5070,
36220
0
        GIR_Done,
36221
      // Label 1763: @116645
36222
0
      GIM_Try, /*On fail goto*//*Label 1764*/ GIMT_Encode4(116723), // Rule ID 5073 //
36223
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36224
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
36225
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
36226
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36227
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36228
        // MIs[0] base
36229
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36230
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36231
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36232
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36233
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
36234
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36235
        // (intrinsic_void 3036:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, MQPR:{ *:[v16i8] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRB8_rq MQPR:{ *:[v16i8] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
36236
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB8_rq),
36237
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36238
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36239
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36240
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36241
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36242
0
        GIR_EraseFromParent, /*InsnID*/0,
36243
        // GIR_Coverage, 5073,
36244
0
        GIR_Done,
36245
      // Label 1764: @116723
36246
0
      GIM_Try, /*On fail goto*//*Label 1765*/ GIMT_Encode4(116801), // Rule ID 5153 //
36247
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36248
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
36249
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
36250
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36251
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36252
        // MIs[0] base
36253
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36254
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36255
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36256
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36257
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
36258
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36259
        // (intrinsic_void 3036:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRB16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36260
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB16_rq),
36261
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36262
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36263
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36264
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36265
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36266
0
        GIR_EraseFromParent, /*InsnID*/0,
36267
        // GIR_Coverage, 5153,
36268
0
        GIR_Done,
36269
      // Label 1765: @116801
36270
0
      GIM_Try, /*On fail goto*//*Label 1766*/ GIMT_Encode4(116879), // Rule ID 5155 //
36271
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36272
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
36273
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36274
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36275
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36276
        // MIs[0] base
36277
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36278
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36279
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36280
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36281
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
36282
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36283
        // (intrinsic_void 3036:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRB32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36284
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB32_rq),
36285
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36286
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36287
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36288
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36289
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36290
0
        GIR_EraseFromParent, /*InsnID*/0,
36291
        // GIR_Coverage, 5155,
36292
0
        GIR_Done,
36293
      // Label 1766: @116879
36294
0
      GIM_Try, /*On fail goto*//*Label 1767*/ GIMT_Encode4(116957), // Rule ID 5157 //
36295
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36296
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
36297
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
36298
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36299
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36300
        // MIs[0] base
36301
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36302
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36303
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36304
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36305
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
36306
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36307
        // (intrinsic_void 3036:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRH16_rq_u MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36308
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq_u),
36309
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36310
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36311
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36312
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36313
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36314
0
        GIR_EraseFromParent, /*InsnID*/0,
36315
        // GIR_Coverage, 5157,
36316
0
        GIR_Done,
36317
      // Label 1767: @116957
36318
0
      GIM_Try, /*On fail goto*//*Label 1768*/ GIMT_Encode4(117035), // Rule ID 5158 //
36319
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36320
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
36321
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
36322
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36323
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36324
        // MIs[0] base
36325
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36326
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36327
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36328
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36329
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
36330
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
36331
        // (intrinsic_void 3036:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSTRH16_rq MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36332
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq),
36333
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36334
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36335
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36336
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36337
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36338
0
        GIR_EraseFromParent, /*InsnID*/0,
36339
        // GIR_Coverage, 5158,
36340
0
        GIR_Done,
36341
      // Label 1768: @117035
36342
0
      GIM_Try, /*On fail goto*//*Label 1769*/ GIMT_Encode4(117113), // Rule ID 5161 //
36343
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36344
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
36345
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36346
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36347
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36348
        // MIs[0] base
36349
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36350
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36351
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36352
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36353
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
36354
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36355
        // (intrinsic_void 3036:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRH32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36356
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH32_rq_u),
36357
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36358
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36359
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36360
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36361
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36362
0
        GIR_EraseFromParent, /*InsnID*/0,
36363
        // GIR_Coverage, 5161,
36364
0
        GIR_Done,
36365
      // Label 1769: @117113
36366
0
      GIM_Try, /*On fail goto*//*Label 1770*/ GIMT_Encode4(117191), // Rule ID 5162 //
36367
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36368
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
36369
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36370
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36371
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36372
        // MIs[0] base
36373
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36374
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36375
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36376
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36377
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
36378
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
36379
        // (intrinsic_void 3036:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSTRH32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36380
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH32_rq),
36381
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36382
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36383
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36384
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36385
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36386
0
        GIR_EraseFromParent, /*InsnID*/0,
36387
        // GIR_Coverage, 5162,
36388
0
        GIR_Done,
36389
      // Label 1770: @117191
36390
0
      GIM_Try, /*On fail goto*//*Label 1771*/ GIMT_Encode4(117269), // Rule ID 5165 //
36391
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36392
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
36393
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36394
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36395
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36396
        // MIs[0] base
36397
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36398
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36399
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36400
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36401
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
36402
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36403
        // (intrinsic_void 3036:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRW32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36404
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq_u),
36405
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36406
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36407
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36408
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36409
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36410
0
        GIR_EraseFromParent, /*InsnID*/0,
36411
        // GIR_Coverage, 5165,
36412
0
        GIR_Done,
36413
      // Label 1771: @117269
36414
0
      GIM_Try, /*On fail goto*//*Label 1772*/ GIMT_Encode4(117347), // Rule ID 5166 //
36415
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36416
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
36417
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36418
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36419
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36420
        // MIs[0] base
36421
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36422
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36423
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36424
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36425
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
36426
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
36427
        // (intrinsic_void 3036:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] })  =>  (MVE_VSTRW32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36428
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq),
36429
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36430
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36431
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36432
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36433
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36434
0
        GIR_EraseFromParent, /*InsnID*/0,
36435
        // GIR_Coverage, 5166,
36436
0
        GIR_Done,
36437
      // Label 1772: @117347
36438
0
      GIM_Try, /*On fail goto*//*Label 1773*/ GIMT_Encode4(117425), // Rule ID 5169 //
36439
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36440
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
36441
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36442
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36443
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36444
        // MIs[0] base
36445
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36446
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36447
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36448
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36449
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
36450
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36451
        // (intrinsic_void 3036:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRW32_rq_u MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36452
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq_u),
36453
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36454
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36455
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36456
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36457
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36458
0
        GIR_EraseFromParent, /*InsnID*/0,
36459
        // GIR_Coverage, 5169,
36460
0
        GIR_Done,
36461
      // Label 1773: @117425
36462
0
      GIM_Try, /*On fail goto*//*Label 1774*/ GIMT_Encode4(117503), // Rule ID 5170 //
36463
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36464
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
36465
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36466
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36467
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36468
        // MIs[0] base
36469
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36470
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36471
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36472
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36473
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
36474
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
36475
        // (intrinsic_void 3036:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] })  =>  (MVE_VSTRW32_rq MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36476
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq),
36477
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36478
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36479
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36480
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36481
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36482
0
        GIR_EraseFromParent, /*InsnID*/0,
36483
        // GIR_Coverage, 5170,
36484
0
        GIR_Done,
36485
      // Label 1774: @117503
36486
0
      GIM_Try, /*On fail goto*//*Label 1775*/ GIMT_Encode4(117581), // Rule ID 5173 //
36487
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36488
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
36489
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
36490
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36491
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36492
        // MIs[0] base
36493
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36494
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36495
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36496
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36497
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
36498
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36499
        // (intrinsic_void 3036:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRD64_rq_u MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
36500
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_rq_u),
36501
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36502
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36503
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36504
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36505
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36506
0
        GIR_EraseFromParent, /*InsnID*/0,
36507
        // GIR_Coverage, 5173,
36508
0
        GIR_Done,
36509
      // Label 1775: @117581
36510
0
      GIM_Try, /*On fail goto*//*Label 1776*/ GIMT_Encode4(117659), // Rule ID 5174 //
36511
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36512
0
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
36513
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
36514
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36515
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36516
        // MIs[0] base
36517
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36518
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36519
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36520
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36521
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
36522
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
36523
        // (intrinsic_void 3036:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 3:{ *:[i32] })  =>  (MVE_VSTRD64_rq MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
36524
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_rq),
36525
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36526
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36527
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36528
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36529
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36530
0
        GIR_EraseFromParent, /*InsnID*/0,
36531
        // GIR_Coverage, 5174,
36532
0
        GIR_Done,
36533
      // Label 1776: @117659
36534
0
      GIM_Try, /*On fail goto*//*Label 1777*/ GIMT_Encode4(117741), // Rule ID 265 //
36535
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
36536
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr),
36537
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36538
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36539
        // MIs[0] cop
36540
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36541
        // MIs[0] opc1
36542
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36543
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36544
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36545
        // MIs[0] CRm
36546
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36547
        // (intrinsic_void 2839:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)  =>  (MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
36548
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MCRR),
36549
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
36550
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
36551
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
36552
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2
36553
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
36554
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36555
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36556
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36557
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36558
0
        GIR_EraseFromParent, /*InsnID*/0,
36559
        // GIR_Coverage, 265,
36560
0
        GIR_Done,
36561
      // Label 1777: @117741
36562
0
      GIM_Try, /*On fail goto*//*Label 1778*/ GIMT_Encode4(117814), // Rule ID 266 //
36563
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8),
36564
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr2),
36565
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36566
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36567
        // MIs[0] cop
36568
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36569
        // MIs[0] opc1
36570
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36571
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36572
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36573
        // MIs[0] CRm
36574
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36575
        // (intrinsic_void 2840:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)  =>  (MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
36576
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MCRR2),
36577
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
36578
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
36579
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
36580
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2
36581
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
36582
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36583
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36584
0
        GIR_EraseFromParent, /*InsnID*/0,
36585
        // GIR_Coverage, 266,
36586
0
        GIR_Done,
36587
      // Label 1778: @117814
36588
0
      GIM_Try, /*On fail goto*//*Label 1779*/ GIMT_Encode4(117896), // Rule ID 613 //
36589
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
36590
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr),
36591
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36592
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36593
        // MIs[0] cop
36594
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36595
        // MIs[0] opc1
36596
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36597
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36598
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36599
        // MIs[0] CRm
36600
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36601
        // (intrinsic_void 2839:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)  =>  (t2MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
36602
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2MCRR),
36603
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
36604
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
36605
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
36606
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2
36607
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
36608
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36609
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36610
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36611
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36612
0
        GIR_EraseFromParent, /*InsnID*/0,
36613
        // GIR_Coverage, 613,
36614
0
        GIR_Done,
36615
      // Label 1779: @117896
36616
0
      GIM_Try, /*On fail goto*//*Label 1780*/ GIMT_Encode4(117978), // Rule ID 614 //
36617
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8),
36618
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr2),
36619
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36620
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36621
        // MIs[0] cop
36622
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36623
        // MIs[0] opc1
36624
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36625
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36626
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36627
        // MIs[0] CRm
36628
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36629
        // (intrinsic_void 2840:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)  =>  (t2MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
36630
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2MCRR2),
36631
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
36632
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
36633
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
36634
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2
36635
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
36636
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36637
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36638
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36639
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36640
0
        GIR_EraseFromParent, /*InsnID*/0,
36641
        // GIR_Coverage, 614,
36642
0
        GIR_Done,
36643
      // Label 1780: @117978
36644
0
      GIM_Reject,
36645
    // Label 1761: @117979
36646
0
    GIM_Try, /*On fail goto*//*Label 1781*/ GIMT_Encode4(122222),
36647
0
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
36648
0
      GIM_Try, /*On fail goto*//*Label 1782*/ GIMT_Encode4(118064), // Rule ID 253 //
36649
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8),
36650
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp),
36651
        // MIs[0] cop
36652
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36653
        // MIs[0] opc1
36654
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36655
        // MIs[0] CRd
36656
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
36657
        // MIs[0] CRn
36658
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
36659
        // MIs[0] CRm
36660
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36661
        // MIs[0] opc2
36662
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
36663
        // (intrinsic_void 2807:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
36664
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::CDP),
36665
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
36666
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
36667
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // CRd
36668
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
36669
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
36670
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
36671
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36672
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36673
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36674
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36675
0
        GIR_EraseFromParent, /*InsnID*/0,
36676
        // GIR_Coverage, 253,
36677
0
        GIR_Done,
36678
      // Label 1782: @118064
36679
0
      GIM_Try, /*On fail goto*//*Label 1783*/ GIMT_Encode4(118132), // Rule ID 254 //
36680
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8),
36681
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp2),
36682
        // MIs[0] cop
36683
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36684
        // MIs[0] opc1
36685
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36686
        // MIs[0] CRd
36687
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
36688
        // MIs[0] CRn
36689
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
36690
        // MIs[0] CRm
36691
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36692
        // MIs[0] opc2
36693
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
36694
        // (intrinsic_void 2808:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
36695
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::CDP2),
36696
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
36697
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
36698
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // CRd
36699
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
36700
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
36701
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
36702
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36703
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36704
0
        GIR_EraseFromParent, /*InsnID*/0,
36705
        // GIR_Coverage, 254,
36706
0
        GIR_Done,
36707
      // Label 1783: @118132
36708
0
      GIM_Try, /*On fail goto*//*Label 1784*/ GIMT_Encode4(118209), // Rule ID 615 //
36709
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8),
36710
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp),
36711
        // MIs[0] cop
36712
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36713
        // MIs[0] opc1
36714
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36715
        // MIs[0] CRd
36716
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
36717
        // MIs[0] CRn
36718
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
36719
        // MIs[0] CRm
36720
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36721
        // MIs[0] opc2
36722
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
36723
        // (intrinsic_void 2807:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (t2CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
36724
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2CDP),
36725
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
36726
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
36727
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // CRd
36728
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
36729
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
36730
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
36731
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36732
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36733
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36734
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36735
0
        GIR_EraseFromParent, /*InsnID*/0,
36736
        // GIR_Coverage, 615,
36737
0
        GIR_Done,
36738
      // Label 1784: @118209
36739
0
      GIM_Try, /*On fail goto*//*Label 1785*/ GIMT_Encode4(118286), // Rule ID 616 //
36740
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8),
36741
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp2),
36742
        // MIs[0] cop
36743
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36744
        // MIs[0] opc1
36745
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36746
        // MIs[0] CRd
36747
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
36748
        // MIs[0] CRn
36749
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
36750
        // MIs[0] CRm
36751
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36752
        // MIs[0] opc2
36753
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
36754
        // (intrinsic_void 2808:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (t2CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
36755
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2CDP2),
36756
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
36757
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
36758
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // CRd
36759
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
36760
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
36761
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
36762
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36763
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36764
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36765
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36766
0
        GIR_EraseFromParent, /*InsnID*/0,
36767
        // GIR_Coverage, 616,
36768
0
        GIR_Done,
36769
      // Label 1785: @118286
36770
0
      GIM_Try, /*On fail goto*//*Label 1786*/ GIMT_Encode4(118372), // Rule ID 5063 //
36771
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
36772
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
36773
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
36774
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36775
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36776
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36777
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36778
        // MIs[0] base
36779
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36780
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36781
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36782
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
36783
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36784
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
36785
        // (intrinsic_w_chain:{ *:[v8i16] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36786
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
36787
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
36788
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36789
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36790
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36791
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36792
0
        GIR_EraseFromParent, /*InsnID*/0,
36793
        // GIR_Coverage, 5063,
36794
0
        GIR_Done,
36795
      // Label 1786: @118372
36796
0
      GIM_Try, /*On fail goto*//*Label 1787*/ GIMT_Encode4(118458), // Rule ID 5064 //
36797
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
36798
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
36799
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
36800
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36801
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36802
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36803
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36804
        // MIs[0] base
36805
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36806
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36807
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36808
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
36809
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
36810
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
36811
        // (intrinsic_w_chain:{ *:[v8i16] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36812
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
36813
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
36814
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36815
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36816
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36817
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36818
0
        GIR_EraseFromParent, /*InsnID*/0,
36819
        // GIR_Coverage, 5064,
36820
0
        GIR_Done,
36821
      // Label 1787: @118458
36822
0
      GIM_Try, /*On fail goto*//*Label 1788*/ GIMT_Encode4(118544), // Rule ID 5067 //
36823
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
36824
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
36825
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
36826
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36827
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36828
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36829
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36830
        // MIs[0] base
36831
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36832
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36833
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36834
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
36835
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36836
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
36837
        // (intrinsic_w_chain:{ *:[v16i8] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
36838
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU8_rq),
36839
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
36840
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36841
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36842
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36843
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36844
0
        GIR_EraseFromParent, /*InsnID*/0,
36845
        // GIR_Coverage, 5067,
36846
0
        GIR_Done,
36847
      // Label 1788: @118544
36848
0
      GIM_Try, /*On fail goto*//*Label 1789*/ GIMT_Encode4(118630), // Rule ID 5075 //
36849
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
36850
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
36851
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
36852
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36853
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36854
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36855
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36856
        // MIs[0] base
36857
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36858
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36859
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36860
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
36861
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36862
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
36863
        // (intrinsic_w_chain:{ *:[v16i8] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
36864
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU8_rq),
36865
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
36866
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36867
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36868
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36869
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36870
0
        GIR_EraseFromParent, /*InsnID*/0,
36871
        // GIR_Coverage, 5075,
36872
0
        GIR_Done,
36873
      // Label 1789: @118630
36874
0
      GIM_Try, /*On fail goto*//*Label 1790*/ GIMT_Encode4(118716), // Rule ID 5077 //
36875
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
36876
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
36877
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
36878
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36879
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36880
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36881
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36882
        // MIs[0] base
36883
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36884
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36885
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36886
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
36887
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36888
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
36889
        // (intrinsic_w_chain:{ *:[v8i16] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRBU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36890
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU16_rq),
36891
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
36892
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36893
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36894
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36895
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36896
0
        GIR_EraseFromParent, /*InsnID*/0,
36897
        // GIR_Coverage, 5077,
36898
0
        GIR_Done,
36899
      // Label 1790: @118716
36900
0
      GIM_Try, /*On fail goto*//*Label 1791*/ GIMT_Encode4(118802), // Rule ID 5079 //
36901
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
36902
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
36903
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
36904
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36905
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36906
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36907
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36908
        // MIs[0] base
36909
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36910
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36911
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36912
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
36913
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36914
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
36915
        // (intrinsic_w_chain:{ *:[v8i16] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRBS16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36916
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBS16_rq),
36917
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
36918
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36919
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36920
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36921
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36922
0
        GIR_EraseFromParent, /*InsnID*/0,
36923
        // GIR_Coverage, 5079,
36924
0
        GIR_Done,
36925
      // Label 1791: @118802
36926
0
      GIM_Try, /*On fail goto*//*Label 1792*/ GIMT_Encode4(118888), // Rule ID 5081 //
36927
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
36928
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36929
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36930
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36931
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36932
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36933
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36934
        // MIs[0] base
36935
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36936
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36937
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36938
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
36939
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36940
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
36941
        // (intrinsic_w_chain:{ *:[v4i32] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRBU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36942
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU32_rq),
36943
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
36944
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36945
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36946
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36947
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36948
0
        GIR_EraseFromParent, /*InsnID*/0,
36949
        // GIR_Coverage, 5081,
36950
0
        GIR_Done,
36951
      // Label 1792: @118888
36952
0
      GIM_Try, /*On fail goto*//*Label 1793*/ GIMT_Encode4(118974), // Rule ID 5083 //
36953
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
36954
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36955
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36956
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36957
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36958
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36959
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36960
        // MIs[0] base
36961
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36962
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36963
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36964
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
36965
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36966
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
36967
        // (intrinsic_w_chain:{ *:[v4i32] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRBS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36968
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBS32_rq),
36969
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
36970
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36971
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36972
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36973
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36974
0
        GIR_EraseFromParent, /*InsnID*/0,
36975
        // GIR_Coverage, 5083,
36976
0
        GIR_Done,
36977
      // Label 1793: @118974
36978
0
      GIM_Try, /*On fail goto*//*Label 1794*/ GIMT_Encode4(119060), // Rule ID 5085 //
36979
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
36980
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
36981
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
36982
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36983
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36984
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36985
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36986
        // MIs[0] base
36987
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36988
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36989
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36990
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
36991
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36992
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
36993
        // (intrinsic_w_chain:{ *:[v8i16] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36994
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
36995
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
36996
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36997
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36998
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36999
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37000
0
        GIR_EraseFromParent, /*InsnID*/0,
37001
        // GIR_Coverage, 5085,
37002
0
        GIR_Done,
37003
      // Label 1794: @119060
37004
0
      GIM_Try, /*On fail goto*//*Label 1795*/ GIMT_Encode4(119146), // Rule ID 5086 //
37005
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37006
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
37007
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
37008
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37009
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37010
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37011
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37012
        // MIs[0] base
37013
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37014
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37015
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37016
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37017
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
37018
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37019
        // (intrinsic_w_chain:{ *:[v8i16] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37020
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
37021
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37022
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37023
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37024
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37025
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37026
0
        GIR_EraseFromParent, /*InsnID*/0,
37027
        // GIR_Coverage, 5086,
37028
0
        GIR_Done,
37029
      // Label 1795: @119146
37030
0
      GIM_Try, /*On fail goto*//*Label 1796*/ GIMT_Encode4(119232), // Rule ID 5089 //
37031
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37032
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
37033
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
37034
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37035
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37036
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37037
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37038
        // MIs[0] base
37039
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37040
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37041
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37042
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37043
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37044
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37045
        // (intrinsic_w_chain:{ *:[v8i16] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37046
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
37047
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37048
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37049
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37050
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37051
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37052
0
        GIR_EraseFromParent, /*InsnID*/0,
37053
        // GIR_Coverage, 5089,
37054
0
        GIR_Done,
37055
      // Label 1796: @119232
37056
0
      GIM_Try, /*On fail goto*//*Label 1797*/ GIMT_Encode4(119318), // Rule ID 5090 //
37057
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37058
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
37059
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
37060
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37061
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37062
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37063
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37064
        // MIs[0] base
37065
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37066
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37067
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37068
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37069
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
37070
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37071
        // (intrinsic_w_chain:{ *:[v8i16] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37072
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
37073
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37074
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37075
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37076
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37077
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37078
0
        GIR_EraseFromParent, /*InsnID*/0,
37079
        // GIR_Coverage, 5090,
37080
0
        GIR_Done,
37081
      // Label 1797: @119318
37082
0
      GIM_Try, /*On fail goto*//*Label 1798*/ GIMT_Encode4(119404), // Rule ID 5093 //
37083
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37084
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
37085
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
37086
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37087
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37088
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37089
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37090
        // MIs[0] base
37091
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37092
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37093
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37094
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37095
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37096
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37097
        // (intrinsic_w_chain:{ *:[v8i16] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37098
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
37099
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37100
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37101
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37102
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37103
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37104
0
        GIR_EraseFromParent, /*InsnID*/0,
37105
        // GIR_Coverage, 5093,
37106
0
        GIR_Done,
37107
      // Label 1798: @119404
37108
0
      GIM_Try, /*On fail goto*//*Label 1799*/ GIMT_Encode4(119490), // Rule ID 5094 //
37109
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37110
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
37111
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
37112
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37113
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37114
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37115
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37116
        // MIs[0] base
37117
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37118
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37119
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37120
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37121
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
37122
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37123
        // (intrinsic_w_chain:{ *:[v8i16] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37124
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
37125
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37126
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37127
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37128
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37129
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37130
0
        GIR_EraseFromParent, /*InsnID*/0,
37131
        // GIR_Coverage, 5094,
37132
0
        GIR_Done,
37133
      // Label 1799: @119490
37134
0
      GIM_Try, /*On fail goto*//*Label 1800*/ GIMT_Encode4(119576), // Rule ID 5097 //
37135
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37136
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
37137
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
37138
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37139
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37140
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37141
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37142
        // MIs[0] base
37143
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37144
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37145
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37146
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37147
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37148
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37149
        // (intrinsic_w_chain:{ *:[v8f16] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37150
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
37151
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37152
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37153
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37154
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37155
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37156
0
        GIR_EraseFromParent, /*InsnID*/0,
37157
        // GIR_Coverage, 5097,
37158
0
        GIR_Done,
37159
      // Label 1800: @119576
37160
0
      GIM_Try, /*On fail goto*//*Label 1801*/ GIMT_Encode4(119662), // Rule ID 5098 //
37161
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37162
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
37163
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
37164
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37165
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37166
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37167
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37168
        // MIs[0] base
37169
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37170
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37171
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37172
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37173
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
37174
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37175
        // (intrinsic_w_chain:{ *:[v8f16] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37176
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
37177
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37178
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37179
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37180
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37181
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37182
0
        GIR_EraseFromParent, /*InsnID*/0,
37183
        // GIR_Coverage, 5098,
37184
0
        GIR_Done,
37185
      // Label 1801: @119662
37186
0
      GIM_Try, /*On fail goto*//*Label 1802*/ GIMT_Encode4(119748), // Rule ID 5101 //
37187
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37188
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
37189
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
37190
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37191
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37192
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37193
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37194
        // MIs[0] base
37195
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37196
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37197
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37198
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37199
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37200
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37201
        // (intrinsic_w_chain:{ *:[v8f16] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37202
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
37203
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37204
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37205
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37206
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37207
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37208
0
        GIR_EraseFromParent, /*InsnID*/0,
37209
        // GIR_Coverage, 5101,
37210
0
        GIR_Done,
37211
      // Label 1802: @119748
37212
0
      GIM_Try, /*On fail goto*//*Label 1803*/ GIMT_Encode4(119834), // Rule ID 5102 //
37213
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37214
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
37215
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
37216
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37217
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37218
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37219
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37220
        // MIs[0] base
37221
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37222
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37223
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37224
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37225
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
37226
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37227
        // (intrinsic_w_chain:{ *:[v8f16] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37228
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
37229
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37230
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37231
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37232
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37233
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37234
0
        GIR_EraseFromParent, /*InsnID*/0,
37235
        // GIR_Coverage, 5102,
37236
0
        GIR_Done,
37237
      // Label 1803: @119834
37238
0
      GIM_Try, /*On fail goto*//*Label 1804*/ GIMT_Encode4(119920), // Rule ID 5105 //
37239
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37240
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37241
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37242
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37243
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37244
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37245
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37246
        // MIs[0] base
37247
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37248
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37249
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37250
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37251
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37252
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37253
        // (intrinsic_w_chain:{ *:[v4i32] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37254
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU32_rq_u),
37255
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37256
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37257
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37258
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37259
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37260
0
        GIR_EraseFromParent, /*InsnID*/0,
37261
        // GIR_Coverage, 5105,
37262
0
        GIR_Done,
37263
      // Label 1804: @119920
37264
0
      GIM_Try, /*On fail goto*//*Label 1805*/ GIMT_Encode4(120006), // Rule ID 5106 //
37265
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37266
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37267
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37268
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37269
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37270
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37271
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37272
        // MIs[0] base
37273
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37274
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37275
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37276
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37277
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
37278
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37279
        // (intrinsic_w_chain:{ *:[v4i32] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37280
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU32_rq),
37281
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37282
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37283
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37284
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37285
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37286
0
        GIR_EraseFromParent, /*InsnID*/0,
37287
        // GIR_Coverage, 5106,
37288
0
        GIR_Done,
37289
      // Label 1805: @120006
37290
0
      GIM_Try, /*On fail goto*//*Label 1806*/ GIMT_Encode4(120092), // Rule ID 5109 //
37291
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37292
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37293
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37294
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37295
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37296
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37297
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37298
        // MIs[0] base
37299
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37300
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37301
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37302
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37303
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37304
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37305
        // (intrinsic_w_chain:{ *:[v4i32] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHS32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37306
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHS32_rq_u),
37307
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37308
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37309
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37310
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37311
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37312
0
        GIR_EraseFromParent, /*InsnID*/0,
37313
        // GIR_Coverage, 5109,
37314
0
        GIR_Done,
37315
      // Label 1806: @120092
37316
0
      GIM_Try, /*On fail goto*//*Label 1807*/ GIMT_Encode4(120178), // Rule ID 5110 //
37317
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37318
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37319
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37320
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37321
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37322
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37323
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37324
        // MIs[0] base
37325
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37326
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37327
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37328
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37329
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
37330
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37331
        // (intrinsic_w_chain:{ *:[v4i32] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37332
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHS32_rq),
37333
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37334
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37335
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37336
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37337
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37338
0
        GIR_EraseFromParent, /*InsnID*/0,
37339
        // GIR_Coverage, 5110,
37340
0
        GIR_Done,
37341
      // Label 1807: @120178
37342
0
      GIM_Try, /*On fail goto*//*Label 1808*/ GIMT_Encode4(120264), // Rule ID 5113 //
37343
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37344
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37345
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37346
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37347
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37348
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37349
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37350
        // MIs[0] base
37351
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37352
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37353
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37354
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37355
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37356
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37357
        // (intrinsic_w_chain:{ *:[v4i32] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37358
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
37359
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37360
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37361
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37362
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37363
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37364
0
        GIR_EraseFromParent, /*InsnID*/0,
37365
        // GIR_Coverage, 5113,
37366
0
        GIR_Done,
37367
      // Label 1808: @120264
37368
0
      GIM_Try, /*On fail goto*//*Label 1809*/ GIMT_Encode4(120350), // Rule ID 5114 //
37369
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37370
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37371
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37372
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37373
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37374
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37375
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37376
        // MIs[0] base
37377
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37378
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37379
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37380
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37381
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
37382
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37383
        // (intrinsic_w_chain:{ *:[v4i32] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37384
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
37385
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37386
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37387
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37388
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37389
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37390
0
        GIR_EraseFromParent, /*InsnID*/0,
37391
        // GIR_Coverage, 5114,
37392
0
        GIR_Done,
37393
      // Label 1809: @120350
37394
0
      GIM_Try, /*On fail goto*//*Label 1810*/ GIMT_Encode4(120436), // Rule ID 5117 //
37395
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37396
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37397
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37398
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37399
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37400
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37401
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37402
        // MIs[0] base
37403
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37404
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37405
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37406
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37407
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37408
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37409
        // (intrinsic_w_chain:{ *:[v4i32] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37410
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
37411
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37412
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37413
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37414
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37415
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37416
0
        GIR_EraseFromParent, /*InsnID*/0,
37417
        // GIR_Coverage, 5117,
37418
0
        GIR_Done,
37419
      // Label 1810: @120436
37420
0
      GIM_Try, /*On fail goto*//*Label 1811*/ GIMT_Encode4(120522), // Rule ID 5118 //
37421
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37422
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37423
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37424
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37425
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37426
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37427
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37428
        // MIs[0] base
37429
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37430
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37431
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37432
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37433
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
37434
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37435
        // (intrinsic_w_chain:{ *:[v4i32] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37436
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
37437
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37438
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37439
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37440
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37441
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37442
0
        GIR_EraseFromParent, /*InsnID*/0,
37443
        // GIR_Coverage, 5118,
37444
0
        GIR_Done,
37445
      // Label 1811: @120522
37446
0
      GIM_Try, /*On fail goto*//*Label 1812*/ GIMT_Encode4(120608), // Rule ID 5121 //
37447
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37448
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37449
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37450
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37451
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37452
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37453
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37454
        // MIs[0] base
37455
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37456
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37457
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37458
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37459
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37460
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37461
        // (intrinsic_w_chain:{ *:[v4i32] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37462
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
37463
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37464
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37465
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37466
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37467
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37468
0
        GIR_EraseFromParent, /*InsnID*/0,
37469
        // GIR_Coverage, 5121,
37470
0
        GIR_Done,
37471
      // Label 1812: @120608
37472
0
      GIM_Try, /*On fail goto*//*Label 1813*/ GIMT_Encode4(120694), // Rule ID 5122 //
37473
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37474
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37475
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37476
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37477
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37478
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37479
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37480
        // MIs[0] base
37481
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37482
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37483
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37484
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37485
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
37486
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37487
        // (intrinsic_w_chain:{ *:[v4i32] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37488
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
37489
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37490
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37491
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37492
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37493
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37494
0
        GIR_EraseFromParent, /*InsnID*/0,
37495
        // GIR_Coverage, 5122,
37496
0
        GIR_Done,
37497
      // Label 1813: @120694
37498
0
      GIM_Try, /*On fail goto*//*Label 1814*/ GIMT_Encode4(120780), // Rule ID 5125 //
37499
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37500
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37501
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37502
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37503
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37504
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37505
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37506
        // MIs[0] base
37507
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37508
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37509
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37510
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37511
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37512
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37513
        // (intrinsic_w_chain:{ *:[v4i32] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37514
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
37515
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37516
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37517
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37518
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37519
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37520
0
        GIR_EraseFromParent, /*InsnID*/0,
37521
        // GIR_Coverage, 5125,
37522
0
        GIR_Done,
37523
      // Label 1814: @120780
37524
0
      GIM_Try, /*On fail goto*//*Label 1815*/ GIMT_Encode4(120866), // Rule ID 5126 //
37525
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37526
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37527
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37528
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37529
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37530
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37531
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37532
        // MIs[0] base
37533
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37534
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37535
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37536
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37537
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
37538
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37539
        // (intrinsic_w_chain:{ *:[v4i32] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37540
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
37541
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37542
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37543
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37544
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37545
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37546
0
        GIR_EraseFromParent, /*InsnID*/0,
37547
        // GIR_Coverage, 5126,
37548
0
        GIR_Done,
37549
      // Label 1815: @120866
37550
0
      GIM_Try, /*On fail goto*//*Label 1816*/ GIMT_Encode4(120952), // Rule ID 5129 //
37551
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37552
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37553
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37554
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37555
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37556
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37557
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37558
        // MIs[0] base
37559
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37560
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37561
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37562
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37563
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37564
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37565
        // (intrinsic_w_chain:{ *:[v4f32] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37566
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
37567
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37568
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37569
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37570
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37571
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37572
0
        GIR_EraseFromParent, /*InsnID*/0,
37573
        // GIR_Coverage, 5129,
37574
0
        GIR_Done,
37575
      // Label 1816: @120952
37576
0
      GIM_Try, /*On fail goto*//*Label 1817*/ GIMT_Encode4(121038), // Rule ID 5130 //
37577
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37578
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37579
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37580
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37581
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37582
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37583
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37584
        // MIs[0] base
37585
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37586
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37587
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37588
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37589
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
37590
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37591
        // (intrinsic_w_chain:{ *:[v4f32] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37592
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
37593
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37594
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37595
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37596
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37597
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37598
0
        GIR_EraseFromParent, /*InsnID*/0,
37599
        // GIR_Coverage, 5130,
37600
0
        GIR_Done,
37601
      // Label 1817: @121038
37602
0
      GIM_Try, /*On fail goto*//*Label 1818*/ GIMT_Encode4(121124), // Rule ID 5133 //
37603
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37604
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37605
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37606
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37607
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37608
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37609
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37610
        // MIs[0] base
37611
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37612
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37613
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37614
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37615
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37616
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37617
        // (intrinsic_w_chain:{ *:[v4f32] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37618
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
37619
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37620
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37621
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37622
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37623
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37624
0
        GIR_EraseFromParent, /*InsnID*/0,
37625
        // GIR_Coverage, 5133,
37626
0
        GIR_Done,
37627
      // Label 1818: @121124
37628
0
      GIM_Try, /*On fail goto*//*Label 1819*/ GIMT_Encode4(121210), // Rule ID 5134 //
37629
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37630
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37631
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37632
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37633
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37634
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37635
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37636
        // MIs[0] base
37637
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37638
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37639
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37640
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37641
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
37642
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37643
        // (intrinsic_w_chain:{ *:[v4f32] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37644
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
37645
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37646
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37647
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37648
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37649
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37650
0
        GIR_EraseFromParent, /*InsnID*/0,
37651
        // GIR_Coverage, 5134,
37652
0
        GIR_Done,
37653
      // Label 1819: @121210
37654
0
      GIM_Try, /*On fail goto*//*Label 1820*/ GIMT_Encode4(121296), // Rule ID 5137 //
37655
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37656
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
37657
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
37658
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37659
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37660
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37661
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37662
        // MIs[0] base
37663
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37664
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37665
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37666
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
37667
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37668
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37669
        // (intrinsic_w_chain:{ *:[v2i64] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37670
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u),
37671
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37672
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37673
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37674
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37675
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37676
0
        GIR_EraseFromParent, /*InsnID*/0,
37677
        // GIR_Coverage, 5137,
37678
0
        GIR_Done,
37679
      // Label 1820: @121296
37680
0
      GIM_Try, /*On fail goto*//*Label 1821*/ GIMT_Encode4(121382), // Rule ID 5138 //
37681
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37682
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
37683
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
37684
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37685
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37686
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37687
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37688
        // MIs[0] base
37689
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37690
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37691
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37692
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
37693
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
37694
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37695
        // (intrinsic_w_chain:{ *:[v2i64] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37696
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq),
37697
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37698
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37699
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37700
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37701
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37702
0
        GIR_EraseFromParent, /*InsnID*/0,
37703
        // GIR_Coverage, 5138,
37704
0
        GIR_Done,
37705
      // Label 1821: @121382
37706
0
      GIM_Try, /*On fail goto*//*Label 1822*/ GIMT_Encode4(121468), // Rule ID 5141 //
37707
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37708
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
37709
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
37710
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37711
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37712
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37713
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37714
        // MIs[0] base
37715
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37716
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37717
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37718
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
37719
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37720
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37721
        // (intrinsic_w_chain:{ *:[v2i64] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37722
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u),
37723
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37724
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37725
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37726
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37727
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37728
0
        GIR_EraseFromParent, /*InsnID*/0,
37729
        // GIR_Coverage, 5141,
37730
0
        GIR_Done,
37731
      // Label 1822: @121468
37732
0
      GIM_Try, /*On fail goto*//*Label 1823*/ GIMT_Encode4(121554), // Rule ID 5142 //
37733
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37734
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
37735
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
37736
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37737
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37738
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37739
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37740
        // MIs[0] base
37741
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37742
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37743
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37744
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
37745
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
37746
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37747
        // (intrinsic_w_chain:{ *:[v2i64] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37748
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq),
37749
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37750
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37751
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37752
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37753
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37754
0
        GIR_EraseFromParent, /*InsnID*/0,
37755
        // GIR_Coverage, 5142,
37756
0
        GIR_Done,
37757
      // Label 1823: @121554
37758
0
      GIM_Try, /*On fail goto*//*Label 1824*/ GIMT_Encode4(121640), // Rule ID 5145 //
37759
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37760
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
37761
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
37762
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37763
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37764
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37765
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37766
        // MIs[0] base
37767
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37768
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37769
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37770
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
37771
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37772
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37773
        // (intrinsic_w_chain:{ *:[v2i64] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37774
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u),
37775
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37776
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37777
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37778
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37779
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37780
0
        GIR_EraseFromParent, /*InsnID*/0,
37781
        // GIR_Coverage, 5145,
37782
0
        GIR_Done,
37783
      // Label 1824: @121640
37784
0
      GIM_Try, /*On fail goto*//*Label 1825*/ GIMT_Encode4(121726), // Rule ID 5146 //
37785
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37786
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
37787
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
37788
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37789
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37790
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37791
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37792
        // MIs[0] base
37793
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37794
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37795
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37796
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
37797
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
37798
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37799
        // (intrinsic_w_chain:{ *:[v2i64] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37800
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq),
37801
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37802
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37803
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37804
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37805
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37806
0
        GIR_EraseFromParent, /*InsnID*/0,
37807
        // GIR_Coverage, 5146,
37808
0
        GIR_Done,
37809
      // Label 1825: @121726
37810
0
      GIM_Try, /*On fail goto*//*Label 1826*/ GIMT_Encode4(121812), // Rule ID 5149 //
37811
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37812
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
37813
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
37814
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37815
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37816
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37817
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37818
        // MIs[0] base
37819
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37820
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37821
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37822
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
37823
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37824
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37825
        // (intrinsic_w_chain:{ *:[v2i64] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37826
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u),
37827
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37828
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37829
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37830
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37831
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37832
0
        GIR_EraseFromParent, /*InsnID*/0,
37833
        // GIR_Coverage, 5149,
37834
0
        GIR_Done,
37835
      // Label 1826: @121812
37836
0
      GIM_Try, /*On fail goto*//*Label 1827*/ GIMT_Encode4(121898), // Rule ID 5150 //
37837
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37838
0
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
37839
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
37840
0
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37841
0
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37842
0
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37843
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37844
        // MIs[0] base
37845
0
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37846
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37847
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37848
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
37849
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
37850
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37851
        // (intrinsic_w_chain:{ *:[v2i64] } 2962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37852
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq),
37853
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
37854
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37855
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37856
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37857
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37858
0
        GIR_EraseFromParent, /*InsnID*/0,
37859
        // GIR_Coverage, 5150,
37860
0
        GIR_Done,
37861
      // Label 1827: @121898
37862
0
      GIM_Try, /*On fail goto*//*Label 1828*/ GIMT_Encode4(121981), // Rule ID 263 //
37863
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
37864
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr),
37865
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
37866
        // MIs[0] cop
37867
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
37868
        // MIs[0] opc1
37869
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
37870
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37871
        // MIs[0] CRn
37872
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
37873
        // MIs[0] CRm
37874
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
37875
        // MIs[0] opc2
37876
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
37877
        // (intrinsic_void 2837:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
37878
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MCR),
37879
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
37880
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
37881
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
37882
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
37883
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
37884
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
37885
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37886
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37887
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37888
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37889
0
        GIR_EraseFromParent, /*InsnID*/0,
37890
        // GIR_Coverage, 263,
37891
0
        GIR_Done,
37892
      // Label 1828: @121981
37893
0
      GIM_Try, /*On fail goto*//*Label 1829*/ GIMT_Encode4(122055), // Rule ID 264 //
37894
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8),
37895
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr2),
37896
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
37897
        // MIs[0] cop
37898
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
37899
        // MIs[0] opc1
37900
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
37901
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37902
        // MIs[0] CRn
37903
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
37904
        // MIs[0] CRm
37905
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
37906
        // MIs[0] opc2
37907
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
37908
        // (intrinsic_void 2838:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
37909
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MCR2),
37910
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
37911
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
37912
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
37913
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
37914
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
37915
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
37916
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37917
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37918
0
        GIR_EraseFromParent, /*InsnID*/0,
37919
        // GIR_Coverage, 264,
37920
0
        GIR_Done,
37921
      // Label 1829: @122055
37922
0
      GIM_Try, /*On fail goto*//*Label 1830*/ GIMT_Encode4(122138), // Rule ID 611 //
37923
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
37924
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr),
37925
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
37926
        // MIs[0] cop
37927
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
37928
        // MIs[0] opc1
37929
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
37930
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37931
        // MIs[0] CRn
37932
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
37933
        // MIs[0] CRm
37934
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
37935
        // MIs[0] opc2
37936
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
37937
        // (intrinsic_void 2837:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (t2MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
37938
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2MCR),
37939
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
37940
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
37941
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
37942
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
37943
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
37944
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
37945
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37946
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37947
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37948
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37949
0
        GIR_EraseFromParent, /*InsnID*/0,
37950
        // GIR_Coverage, 611,
37951
0
        GIR_Done,
37952
      // Label 1830: @122138
37953
0
      GIM_Try, /*On fail goto*//*Label 1831*/ GIMT_Encode4(122221), // Rule ID 612 //
37954
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8),
37955
0
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr2),
37956
0
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
37957
        // MIs[0] cop
37958
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
37959
        // MIs[0] opc1
37960
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
37961
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37962
        // MIs[0] CRn
37963
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
37964
        // MIs[0] CRm
37965
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
37966
        // MIs[0] opc2
37967
0
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
37968
        // (intrinsic_void 2838:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (t2MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
37969
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2MCR2),
37970
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
37971
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
37972
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
37973
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
37974
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
37975
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
37976
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37977
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37978
0
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37979
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37980
0
        GIR_EraseFromParent, /*InsnID*/0,
37981
        // GIR_Coverage, 612,
37982
0
        GIR_Done,
37983
      // Label 1831: @122221
37984
0
      GIM_Reject,
37985
    // Label 1781: @122222
37986
0
    GIM_Reject,
37987
    // Label 16: @122223
37988
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(13), /*)*//*default:*//*Label 1835*/ GIMT_Encode4(122413),
37989
0
    /*GILLT_v2s64*//*Label 1832*/ GIMT_Encode4(122266), GIMT_Encode4(0), GIMT_Encode4(0),
37990
0
    /*GILLT_v4s32*//*Label 1833*/ GIMT_Encode4(122315), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
37991
0
    /*GILLT_v8s16*//*Label 1834*/ GIMT_Encode4(122364),
37992
    // Label 1832: @122266
37993
0
    GIM_Try, /*On fail goto*//*Label 1836*/ GIMT_Encode4(122314), // Rule ID 2688 //
37994
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
37995
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
37996
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37997
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37998
      // (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)  =>  (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
37999
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv2i64),
38000
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
38001
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38002
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38003
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38004
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38005
0
      GIR_EraseFromParent, /*InsnID*/0,
38006
      // GIR_Coverage, 2688,
38007
0
      GIR_Done,
38008
    // Label 1836: @122314
38009
0
    GIM_Reject,
38010
    // Label 1833: @122315
38011
0
    GIM_Try, /*On fail goto*//*Label 1837*/ GIMT_Encode4(122363), // Rule ID 2687 //
38012
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38013
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
38014
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38015
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38016
      // (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)  =>  (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
38017
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv4i32),
38018
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
38019
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38020
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38021
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38022
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38023
0
      GIR_EraseFromParent, /*InsnID*/0,
38024
      // GIR_Coverage, 2687,
38025
0
      GIR_Done,
38026
    // Label 1837: @122363
38027
0
    GIM_Reject,
38028
    // Label 1834: @122364
38029
0
    GIM_Try, /*On fail goto*//*Label 1838*/ GIMT_Encode4(122412), // Rule ID 2686 //
38030
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38031
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
38032
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38033
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38034
      // (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)  =>  (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
38035
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv8i16),
38036
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
38037
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38038
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38039
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38040
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38041
0
      GIR_EraseFromParent, /*InsnID*/0,
38042
      // GIR_Coverage, 2686,
38043
0
      GIR_Done,
38044
    // Label 1838: @122412
38045
0
    GIM_Reject,
38046
    // Label 1835: @122413
38047
0
    GIM_Reject,
38048
    // Label 17: @122414
38049
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(12), /*)*//*default:*//*Label 1842*/ GIMT_Encode4(122604),
38050
0
    /*GILLT_v2s32*//*Label 1839*/ GIMT_Encode4(122457), GIMT_Encode4(0), GIMT_Encode4(0),
38051
0
    /*GILLT_v4s16*//*Label 1840*/ GIMT_Encode4(122506), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
38052
0
    /*GILLT_v8s8*//*Label 1841*/ GIMT_Encode4(122555),
38053
    // Label 1839: @122457
38054
0
    GIM_Try, /*On fail goto*//*Label 1843*/ GIMT_Encode4(122505), // Rule ID 1607 //
38055
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38056
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
38057
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38058
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38059
      // (trunc:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)  =>  (VMOVNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
38060
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMOVNv2i32),
38061
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
38062
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38063
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38064
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38065
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38066
0
      GIR_EraseFromParent, /*InsnID*/0,
38067
      // GIR_Coverage, 1607,
38068
0
      GIR_Done,
38069
    // Label 1843: @122505
38070
0
    GIM_Reject,
38071
    // Label 1840: @122506
38072
0
    GIM_Try, /*On fail goto*//*Label 1844*/ GIMT_Encode4(122554), // Rule ID 1606 //
38073
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38074
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
38075
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38076
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38077
      // (trunc:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)  =>  (VMOVNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
38078
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMOVNv4i16),
38079
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
38080
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38081
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38082
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38083
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38084
0
      GIR_EraseFromParent, /*InsnID*/0,
38085
      // GIR_Coverage, 1606,
38086
0
      GIR_Done,
38087
    // Label 1844: @122554
38088
0
    GIM_Reject,
38089
    // Label 1841: @122555
38090
0
    GIM_Try, /*On fail goto*//*Label 1845*/ GIMT_Encode4(122603), // Rule ID 1605 //
38091
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38092
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
38093
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38094
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38095
      // (trunc:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)  =>  (VMOVNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
38096
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMOVNv8i8),
38097
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
38098
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38099
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38100
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38101
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38102
0
      GIR_EraseFromParent, /*InsnID*/0,
38103
      // GIR_Coverage, 1605,
38104
0
      GIR_Done,
38105
    // Label 1845: @122603
38106
0
    GIM_Reject,
38107
    // Label 1842: @122604
38108
0
    GIM_Reject,
38109
    // Label 18: @122605
38110
0
    GIM_Try, /*On fail goto*//*Label 1846*/ GIMT_Encode4(122890),
38111
0
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
38112
0
      GIM_Try, /*On fail goto*//*Label 1847*/ GIMT_Encode4(122662), // Rule ID 412 //
38113
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
38114
0
        GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
38115
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38116
        // MIs[0] Operand 1
38117
        // No operand predicates
38118
        // (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm  =>  (t2MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
38119
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
38120
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
38121
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
38122
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38123
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38124
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38125
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38126
0
        GIR_EraseFromParent, /*InsnID*/0,
38127
        // GIR_Coverage, 412,
38128
0
        GIR_Done,
38129
      // Label 1847: @122662
38130
0
      GIM_Try, /*On fail goto*//*Label 1848*/ GIMT_Encode4(122710), // Rule ID 57 //
38131
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
38132
0
        GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
38133
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38134
        // MIs[0] Operand 1
38135
        // No operand predicates
38136
        // (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm  =>  (MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
38137
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MOVi),
38138
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
38139
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
38140
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38141
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38142
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38143
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38144
0
        GIR_EraseFromParent, /*InsnID*/0,
38145
        // GIR_Coverage, 57,
38146
0
        GIR_Done,
38147
      // Label 1848: @122710
38148
0
      GIM_Try, /*On fail goto*//*Label 1849*/ GIMT_Encode4(122752), // Rule ID 58 //
38149
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM),
38150
0
        GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535),
38151
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38152
        // MIs[0] Operand 1
38153
        // No operand predicates
38154
        // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm  =>  (MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm)
38155
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MOVi16),
38156
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
38157
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
38158
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38159
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38160
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38161
0
        GIR_EraseFromParent, /*InsnID*/0,
38162
        // GIR_Coverage, 58,
38163
0
        GIR_Done,
38164
      // Label 1849: @122752
38165
0
      GIM_Try, /*On fail goto*//*Label 1850*/ GIMT_Encode4(122785), // Rule ID 275 //
38166
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
38167
0
        GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_arm_i32imm),
38168
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38169
        // MIs[0] Operand 1
38170
        // No operand predicates
38171
        // (imm:{ *:[i32] })<<P:Predicate_arm_i32imm>>:$src  =>  (MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src)
38172
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MOVi32imm),
38173
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
38174
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
38175
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38176
0
        GIR_EraseFromParent, /*InsnID*/0,
38177
        // GIR_Coverage, 275,
38178
0
        GIR_Done,
38179
      // Label 1850: @122785
38180
0
      GIM_Try, /*On fail goto*//*Label 1851*/ GIMT_Encode4(122827), // Rule ID 413 //
38181
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV8MBaseline_IsThumb),
38182
0
        GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535),
38183
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38184
        // MIs[0] Operand 1
38185
        // No operand predicates
38186
        // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm  =>  (t2MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm)
38187
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16),
38188
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
38189
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
38190
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38191
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38192
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38193
0
        GIR_EraseFromParent, /*InsnID*/0,
38194
        // GIR_Coverage, 413,
38195
0
        GIR_Done,
38196
      // Label 1851: @122827
38197
0
      GIM_Try, /*On fail goto*//*Label 1852*/ GIMT_Encode4(122889),
38198
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38199
0
        GIM_Try, /*On fail goto*//*Label 1853*/ GIMT_Encode4(122864), // Rule ID 361 //
38200
0
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseMovt_GenExecuteOnly_IsThumb1Only),
38201
          // MIs[0] Operand 1
38202
          // No operand predicates
38203
          // (imm:{ *:[i32] }):$src  =>  (tMOVi32imm:{ *:[i32] }:{ *:[i32] } (imm:{ *:[i32] }):$src)
38204
0
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::tMOVi32imm),
38205
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
38206
0
          GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
38207
0
          GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::CPSR*/0,
38208
0
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38209
0
          GIR_EraseFromParent, /*InsnID*/0,
38210
          // GIR_Coverage, 361,
38211
0
          GIR_Done,
38212
        // Label 1853: @122864
38213
0
        GIM_Try, /*On fail goto*//*Label 1854*/ GIMT_Encode4(122888), // Rule ID 599 //
38214
0
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_UseMovt),
38215
          // MIs[0] Operand 1
38216
          // No operand predicates
38217
          // (imm:{ *:[i32] }):$src  =>  (t2MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src)
38218
0
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2MOVi32imm),
38219
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
38220
0
          GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
38221
0
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38222
0
          GIR_EraseFromParent, /*InsnID*/0,
38223
          // GIR_Coverage, 599,
38224
0
          GIR_Done,
38225
        // Label 1854: @122888
38226
0
        GIM_Reject,
38227
      // Label 1852: @122889
38228
0
      GIM_Reject,
38229
    // Label 1846: @122890
38230
0
    GIM_Reject,
38231
    // Label 19: @122891
38232
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1857*/ GIMT_Encode4(123000),
38233
0
    /*GILLT_s32*//*Label 1855*/ GIMT_Encode4(122910),
38234
0
    /*GILLT_s64*//*Label 1856*/ GIMT_Encode4(122955),
38235
    // Label 1855: @122910
38236
0
    GIM_Try, /*On fail goto*//*Label 1858*/ GIMT_Encode4(122954), // Rule ID 745 //
38237
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP3),
38238
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38239
      // MIs[0] Operand 1
38240
      // No operand predicates
38241
0
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_vfp_f32imm),
38242
      // (fpimm:{ *:[f32] })<<P:Predicate_vfp_f32imm>><<X:vfp_f32imm_xform>>:$imm  =>  (FCONSTS:{ *:[f32] } (vfp_f32imm_xform:{ *:[f32] } (fpimm:{ *:[f32] }):$imm))
38243
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::FCONSTS),
38244
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
38245
0
      GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderVFPF32Imm), // imm
38246
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38247
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38248
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38249
0
      GIR_EraseFromParent, /*InsnID*/0,
38250
      // GIR_Coverage, 745,
38251
0
      GIR_Done,
38252
    // Label 1858: @122954
38253
0
    GIM_Reject,
38254
    // Label 1856: @122955
38255
0
    GIM_Try, /*On fail goto*//*Label 1859*/ GIMT_Encode4(122999), // Rule ID 744 //
38256
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP3),
38257
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38258
      // MIs[0] Operand 1
38259
      // No operand predicates
38260
0
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_vfp_f64imm),
38261
      // (fpimm:{ *:[f64] })<<P:Predicate_vfp_f64imm>><<X:vfp_f64imm_xform>>:$imm  =>  (FCONSTD:{ *:[f64] } (vfp_f64imm_xform:{ *:[f64] } (fpimm:{ *:[f64] }):$imm))
38262
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::FCONSTD),
38263
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
38264
0
      GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderVFPF64Imm), // imm
38265
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38266
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38267
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38268
0
      GIR_EraseFromParent, /*InsnID*/0,
38269
      // GIR_Coverage, 744,
38270
0
      GIR_Done,
38271
    // Label 1859: @122999
38272
0
    GIM_Reject,
38273
    // Label 1857: @123000
38274
0
    GIM_Reject,
38275
    // Label 20: @123001
38276
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(13), /*)*//*default:*//*Label 1863*/ GIMT_Encode4(123191),
38277
0
    /*GILLT_v2s64*//*Label 1860*/ GIMT_Encode4(123044), GIMT_Encode4(0), GIMT_Encode4(0),
38278
0
    /*GILLT_v4s32*//*Label 1861*/ GIMT_Encode4(123093), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
38279
0
    /*GILLT_v8s16*//*Label 1862*/ GIMT_Encode4(123142),
38280
    // Label 1860: @123044
38281
0
    GIM_Try, /*On fail goto*//*Label 1864*/ GIMT_Encode4(123092), // Rule ID 1619 //
38282
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38283
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
38284
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38285
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38286
      // (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)  =>  (VMOVLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
38287
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv2i64),
38288
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
38289
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38290
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38291
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38292
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38293
0
      GIR_EraseFromParent, /*InsnID*/0,
38294
      // GIR_Coverage, 1619,
38295
0
      GIR_Done,
38296
    // Label 1864: @123092
38297
0
    GIM_Reject,
38298
    // Label 1861: @123093
38299
0
    GIM_Try, /*On fail goto*//*Label 1865*/ GIMT_Encode4(123141), // Rule ID 1618 //
38300
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38301
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
38302
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38303
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38304
      // (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)  =>  (VMOVLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
38305
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv4i32),
38306
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
38307
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38308
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38309
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38310
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38311
0
      GIR_EraseFromParent, /*InsnID*/0,
38312
      // GIR_Coverage, 1618,
38313
0
      GIR_Done,
38314
    // Label 1865: @123141
38315
0
    GIM_Reject,
38316
    // Label 1862: @123142
38317
0
    GIM_Try, /*On fail goto*//*Label 1866*/ GIMT_Encode4(123190), // Rule ID 1617 //
38318
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38319
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
38320
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38321
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38322
      // (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)  =>  (VMOVLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
38323
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv8i16),
38324
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
38325
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38326
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38327
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38328
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38329
0
      GIR_EraseFromParent, /*InsnID*/0,
38330
      // GIR_Coverage, 1617,
38331
0
      GIR_Done,
38332
    // Label 1866: @123190
38333
0
    GIM_Reject,
38334
    // Label 1863: @123191
38335
0
    GIM_Reject,
38336
    // Label 21: @123192
38337
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(13), /*)*//*default:*//*Label 1870*/ GIMT_Encode4(123844),
38338
0
    /*GILLT_v2s64*//*Label 1867*/ GIMT_Encode4(123235), GIMT_Encode4(0), GIMT_Encode4(0),
38339
0
    /*GILLT_v4s32*//*Label 1868*/ GIMT_Encode4(123438), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
38340
0
    /*GILLT_v8s16*//*Label 1869*/ GIMT_Encode4(123641),
38341
    // Label 1867: @123235
38342
0
    GIM_Try, /*On fail goto*//*Label 1871*/ GIMT_Encode4(123437),
38343
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
38344
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38345
0
      GIM_Try, /*On fail goto*//*Label 1872*/ GIMT_Encode4(123323), // Rule ID 1194 //
38346
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38347
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38348
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
38349
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38350
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
38351
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
38352
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
38353
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38354
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38355
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
38356
        // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 3062:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VABDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
38357
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDLsv2i64),
38358
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
38359
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38360
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38361
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38362
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38363
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38364
0
        GIR_EraseFromParent, /*InsnID*/0,
38365
        // GIR_Coverage, 1194,
38366
0
        GIR_Done,
38367
      // Label 1872: @123323
38368
0
      GIM_Try, /*On fail goto*//*Label 1873*/ GIMT_Encode4(123397), // Rule ID 1197 //
38369
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38370
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38371
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
38372
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38373
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
38374
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
38375
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
38376
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38377
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38378
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
38379
        // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 3063:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VABDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
38380
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDLuv2i64),
38381
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
38382
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38383
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38384
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38385
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38386
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38387
0
        GIR_EraseFromParent, /*InsnID*/0,
38388
        // GIR_Coverage, 1197,
38389
0
        GIR_Done,
38390
      // Label 1873: @123397
38391
0
      GIM_Try, /*On fail goto*//*Label 1874*/ GIMT_Encode4(123436), // Rule ID 1622 //
38392
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38393
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38394
        // (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)  =>  (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
38395
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv2i64),
38396
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
38397
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38398
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38399
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38400
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38401
0
        GIR_EraseFromParent, /*InsnID*/0,
38402
        // GIR_Coverage, 1622,
38403
0
        GIR_Done,
38404
      // Label 1874: @123436
38405
0
      GIM_Reject,
38406
    // Label 1871: @123437
38407
0
    GIM_Reject,
38408
    // Label 1868: @123438
38409
0
    GIM_Try, /*On fail goto*//*Label 1875*/ GIMT_Encode4(123640),
38410
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
38411
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38412
0
      GIM_Try, /*On fail goto*//*Label 1876*/ GIMT_Encode4(123526), // Rule ID 1193 //
38413
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38414
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38415
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
38416
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38417
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
38418
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
38419
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
38420
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38421
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38422
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
38423
        // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 3062:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VABDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
38424
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDLsv4i32),
38425
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
38426
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38427
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38428
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38429
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38430
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38431
0
        GIR_EraseFromParent, /*InsnID*/0,
38432
        // GIR_Coverage, 1193,
38433
0
        GIR_Done,
38434
      // Label 1876: @123526
38435
0
      GIM_Try, /*On fail goto*//*Label 1877*/ GIMT_Encode4(123600), // Rule ID 1196 //
38436
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38437
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38438
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
38439
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38440
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
38441
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
38442
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
38443
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38444
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38445
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
38446
        // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 3063:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VABDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
38447
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDLuv4i32),
38448
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
38449
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38450
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38451
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38452
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38453
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38454
0
        GIR_EraseFromParent, /*InsnID*/0,
38455
        // GIR_Coverage, 1196,
38456
0
        GIR_Done,
38457
      // Label 1877: @123600
38458
0
      GIM_Try, /*On fail goto*//*Label 1878*/ GIMT_Encode4(123639), // Rule ID 1621 //
38459
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38460
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38461
        // (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)  =>  (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
38462
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv4i32),
38463
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
38464
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38465
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38466
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38467
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38468
0
        GIR_EraseFromParent, /*InsnID*/0,
38469
        // GIR_Coverage, 1621,
38470
0
        GIR_Done,
38471
      // Label 1878: @123639
38472
0
      GIM_Reject,
38473
    // Label 1875: @123640
38474
0
    GIM_Reject,
38475
    // Label 1869: @123641
38476
0
    GIM_Try, /*On fail goto*//*Label 1879*/ GIMT_Encode4(123843),
38477
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
38478
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38479
0
      GIM_Try, /*On fail goto*//*Label 1880*/ GIMT_Encode4(123729), // Rule ID 1192 //
38480
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38481
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38482
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
38483
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38484
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
38485
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
38486
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
38487
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38488
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38489
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
38490
        // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 3062:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VABDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
38491
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDLsv8i16),
38492
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
38493
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38494
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38495
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38496
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38497
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38498
0
        GIR_EraseFromParent, /*InsnID*/0,
38499
        // GIR_Coverage, 1192,
38500
0
        GIR_Done,
38501
      // Label 1880: @123729
38502
0
      GIM_Try, /*On fail goto*//*Label 1881*/ GIMT_Encode4(123803), // Rule ID 1195 //
38503
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38504
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38505
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
38506
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38507
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabdu),
38508
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
38509
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
38510
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38511
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38512
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
38513
        // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 3063:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VABDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
38514
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDLuv8i16),
38515
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
38516
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38517
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38518
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38519
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38520
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38521
0
        GIR_EraseFromParent, /*InsnID*/0,
38522
        // GIR_Coverage, 1195,
38523
0
        GIR_Done,
38524
      // Label 1881: @123803
38525
0
      GIM_Try, /*On fail goto*//*Label 1882*/ GIMT_Encode4(123842), // Rule ID 1620 //
38526
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38527
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38528
        // (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)  =>  (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
38529
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv8i16),
38530
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
38531
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38532
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38533
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38534
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38535
0
        GIR_EraseFromParent, /*InsnID*/0,
38536
        // GIR_Coverage, 1620,
38537
0
        GIR_Done,
38538
      // Label 1882: @123842
38539
0
      GIM_Reject,
38540
    // Label 1879: @123843
38541
0
    GIM_Reject,
38542
    // Label 1870: @123844
38543
0
    GIM_Reject,
38544
    // Label 22: @123845
38545
0
    GIM_Try, /*On fail goto*//*Label 1883*/ GIMT_Encode4(123979),
38546
0
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
38547
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
38548
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
38549
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38550
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38551
0
      GIM_Try, /*On fail goto*//*Label 1884*/ GIMT_Encode4(123929), // Rule ID 478 //
38552
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
38553
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38554
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
38555
0
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_31),
38556
        // MIs[1] Operand 1
38557
        // No operand predicates
38558
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
38559
        // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm)  =>  (t2LSLri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm)
38560
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2LSLri),
38561
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
38562
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
38563
0
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
38564
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38565
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38566
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38567
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38568
0
        GIR_EraseFromParent, /*InsnID*/0,
38569
        // GIR_Coverage, 478,
38570
0
        GIR_Done,
38571
      // Label 1884: @123929
38572
0
      GIM_Try, /*On fail goto*//*Label 1885*/ GIMT_Encode4(123978), // Rule ID 479 //
38573
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
38574
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38575
        // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2LSLrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
38576
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2LSLrr),
38577
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
38578
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
38579
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38580
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38581
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38582
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38583
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38584
0
        GIR_EraseFromParent, /*InsnID*/0,
38585
        // GIR_Coverage, 479,
38586
0
        GIR_Done,
38587
      // Label 1885: @123978
38588
0
      GIM_Reject,
38589
    // Label 1883: @123979
38590
0
    GIM_Reject,
38591
    // Label 23: @123980
38592
0
    GIM_Try, /*On fail goto*//*Label 1886*/ GIMT_Encode4(124051), // Rule ID 481 //
38593
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
38594
0
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
38595
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
38596
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
38597
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38598
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38599
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38600
      // (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2LSRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
38601
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2LSRrr),
38602
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
38603
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
38604
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38605
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38606
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38607
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38608
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38609
0
      GIR_EraseFromParent, /*InsnID*/0,
38610
      // GIR_Coverage, 481,
38611
0
      GIR_Done,
38612
    // Label 1886: @124051
38613
0
    GIM_Reject,
38614
    // Label 24: @124052
38615
0
    GIM_Try, /*On fail goto*//*Label 1887*/ GIMT_Encode4(124316),
38616
0
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
38617
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
38618
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
38619
0
      GIM_Try, /*On fail goto*//*Label 1888*/ GIMT_Encode4(124131), // Rule ID 201 //
38620
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
38621
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38622
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38623
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
38624
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38625
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38626
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
38627
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
38628
        // (sra:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] })  =>  (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
38629
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::REVSH),
38630
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
38631
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
38632
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38633
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38634
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38635
0
        GIR_EraseFromParent, /*InsnID*/0,
38636
        // GIR_Coverage, 201,
38637
0
        GIR_Done,
38638
      // Label 1888: @124131
38639
0
      GIM_Try, /*On fail goto*//*Label 1889*/ GIMT_Encode4(124193), // Rule ID 335 //
38640
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
38641
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
38642
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38643
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
38644
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38645
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
38646
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
38647
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
38648
        // (sra:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] })  =>  (tREVSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
38649
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::tREVSH),
38650
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
38651
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
38652
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38653
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38654
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38655
0
        GIR_EraseFromParent, /*InsnID*/0,
38656
        // GIR_Coverage, 335,
38657
0
        GIR_Done,
38658
      // Label 1889: @124193
38659
0
      GIM_Try, /*On fail goto*//*Label 1890*/ GIMT_Encode4(124315),
38660
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38661
0
        GIM_Try, /*On fail goto*//*Label 1891*/ GIMT_Encode4(124260), // Rule ID 546 //
38662
0
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
38663
0
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38664
0
          GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
38665
0
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38666
0
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38667
0
          GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
38668
0
          GIM_CheckIsSafeToFold, /*InsnID*/1,
38669
          // (sra:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] })  =>  (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
38670
0
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2REVSH),
38671
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
38672
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
38673
0
          GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38674
0
          GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38675
0
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38676
0
          GIR_EraseFromParent, /*InsnID*/0,
38677
          // GIR_Coverage, 546,
38678
0
          GIR_Done,
38679
        // Label 1891: @124260
38680
0
        GIM_Try, /*On fail goto*//*Label 1892*/ GIMT_Encode4(124314), // Rule ID 483 //
38681
0
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
38682
0
          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38683
0
          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38684
          // (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2ASRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
38685
0
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2ASRrr),
38686
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
38687
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
38688
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38689
0
          GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38690
0
          GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38691
0
          GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38692
0
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38693
0
          GIR_EraseFromParent, /*InsnID*/0,
38694
          // GIR_Coverage, 483,
38695
0
          GIR_Done,
38696
        // Label 1892: @124314
38697
0
        GIM_Reject,
38698
      // Label 1890: @124315
38699
0
      GIM_Reject,
38700
    // Label 1887: @124316
38701
0
    GIM_Reject,
38702
    // Label 25: @124317
38703
0
    GIM_Try, /*On fail goto*//*Label 1893*/ GIMT_Encode4(124643),
38704
0
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
38705
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
38706
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
38707
0
      GIM_Try, /*On fail goto*//*Label 1894*/ GIMT_Encode4(124396), // Rule ID 200 //
38708
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
38709
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38710
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38711
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
38712
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38713
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38714
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
38715
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
38716
        // (rotr:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] })  =>  (REV16:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
38717
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::REV16),
38718
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
38719
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
38720
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38721
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38722
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38723
0
        GIR_EraseFromParent, /*InsnID*/0,
38724
        // GIR_Coverage, 200,
38725
0
        GIR_Done,
38726
      // Label 1894: @124396
38727
0
      GIM_Try, /*On fail goto*//*Label 1895*/ GIMT_Encode4(124458), // Rule ID 334 //
38728
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
38729
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
38730
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38731
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
38732
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38733
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
38734
0
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
38735
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
38736
        // (rotr:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] })  =>  (tREV16:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
38737
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::tREV16),
38738
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
38739
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
38740
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38741
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38742
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38743
0
        GIR_EraseFromParent, /*InsnID*/0,
38744
        // GIR_Coverage, 334,
38745
0
        GIR_Done,
38746
      // Label 1895: @124458
38747
0
      GIM_Try, /*On fail goto*//*Label 1896*/ GIMT_Encode4(124642),
38748
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38749
0
        GIM_Try, /*On fail goto*//*Label 1897*/ GIMT_Encode4(124525), // Rule ID 545 //
38750
0
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
38751
0
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38752
0
          GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
38753
0
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38754
0
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38755
0
          GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
38756
0
          GIM_CheckIsSafeToFold, /*InsnID*/1,
38757
          // (rotr:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] })  =>  (t2REV16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
38758
0
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2REV16),
38759
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
38760
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
38761
0
          GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38762
0
          GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38763
0
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38764
0
          GIR_EraseFromParent, /*InsnID*/0,
38765
          // GIR_Coverage, 545,
38766
0
          GIR_Done,
38767
        // Label 1897: @124525
38768
0
        GIM_Try, /*On fail goto*//*Label 1898*/ GIMT_Encode4(124587), // Rule ID 484 //
38769
0
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
38770
0
          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38771
0
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38772
0
          GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
38773
0
          GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_31),
38774
          // MIs[1] Operand 1
38775
          // No operand predicates
38776
0
          GIM_CheckIsSafeToFold, /*InsnID*/1,
38777
          // (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm)  =>  (t2RORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm)
38778
0
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2RORri),
38779
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
38780
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
38781
0
          GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
38782
0
          GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38783
0
          GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38784
0
          GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38785
0
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38786
0
          GIR_EraseFromParent, /*InsnID*/0,
38787
          // GIR_Coverage, 484,
38788
0
          GIR_Done,
38789
        // Label 1898: @124587
38790
0
        GIM_Try, /*On fail goto*//*Label 1899*/ GIMT_Encode4(124641), // Rule ID 485 //
38791
0
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
38792
0
          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38793
0
          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38794
          // (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2RORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
38795
0
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2RORrr),
38796
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
38797
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
38798
0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38799
0
          GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38800
0
          GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38801
0
          GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38802
0
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38803
0
          GIR_EraseFromParent, /*InsnID*/0,
38804
          // GIR_Coverage, 485,
38805
0
          GIR_Done,
38806
        // Label 1899: @124641
38807
0
        GIM_Reject,
38808
      // Label 1896: @124642
38809
0
      GIM_Reject,
38810
    // Label 1893: @124643
38811
0
    GIM_Reject,
38812
    // Label 26: @124644
38813
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 1903*/ GIMT_Encode4(124930),
38814
0
    /*GILLT_v4s32*//*Label 1900*/ GIMT_Encode4(124687), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
38815
0
    /*GILLT_v8s16*//*Label 1901*/ GIMT_Encode4(124768), GIMT_Encode4(0), GIMT_Encode4(0),
38816
0
    /*GILLT_v16s8*//*Label 1902*/ GIMT_Encode4(124849),
38817
    // Label 1900: @124687
38818
0
    GIM_Try, /*On fail goto*//*Label 1904*/ GIMT_Encode4(124767), // Rule ID 4588 //
38819
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
38820
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
38821
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
38822
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38823
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38824
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38825
      // (mulhu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
38826
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38827
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38828
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
38829
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu32),
38830
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
38831
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
38832
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
38833
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38834
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38835
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38836
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38837
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38838
0
      GIR_EraseFromParent, /*InsnID*/0,
38839
      // GIR_Coverage, 4588,
38840
0
      GIR_Done,
38841
    // Label 1904: @124767
38842
0
    GIM_Reject,
38843
    // Label 1901: @124768
38844
0
    GIM_Try, /*On fail goto*//*Label 1905*/ GIMT_Encode4(124848), // Rule ID 4584 //
38845
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
38846
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
38847
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
38848
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38849
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38850
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38851
      // (mulhu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
38852
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38853
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38854
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
38855
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu16),
38856
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
38857
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
38858
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
38859
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38860
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38861
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38862
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38863
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38864
0
      GIR_EraseFromParent, /*InsnID*/0,
38865
      // GIR_Coverage, 4584,
38866
0
      GIR_Done,
38867
    // Label 1905: @124848
38868
0
    GIM_Reject,
38869
    // Label 1902: @124849
38870
0
    GIM_Try, /*On fail goto*//*Label 1906*/ GIMT_Encode4(124929), // Rule ID 4580 //
38871
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
38872
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
38873
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
38874
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38875
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38876
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38877
      // (mulhu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
38878
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38879
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38880
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
38881
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu8),
38882
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
38883
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
38884
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
38885
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38886
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38887
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38888
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38889
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38890
0
      GIR_EraseFromParent, /*InsnID*/0,
38891
      // GIR_Coverage, 4580,
38892
0
      GIR_Done,
38893
    // Label 1906: @124929
38894
0
    GIM_Reject,
38895
    // Label 1903: @124930
38896
0
    GIM_Reject,
38897
    // Label 27: @124931
38898
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 1911*/ GIMT_Encode4(125366),
38899
0
    /*GILLT_s32*//*Label 1907*/ GIMT_Encode4(125002), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
38900
0
    /*GILLT_v4s32*//*Label 1908*/ GIMT_Encode4(125123), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
38901
0
    /*GILLT_v8s16*//*Label 1909*/ GIMT_Encode4(125204), GIMT_Encode4(0), GIMT_Encode4(0),
38902
0
    /*GILLT_v16s8*//*Label 1910*/ GIMT_Encode4(125285),
38903
    // Label 1907: @125002
38904
0
    GIM_Try, /*On fail goto*//*Label 1912*/ GIMT_Encode4(125122),
38905
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
38906
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
38907
0
      GIM_Try, /*On fail goto*//*Label 1913*/ GIMT_Encode4(125068), // Rule ID 178 //
38908
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
38909
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38910
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38911
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38912
        // (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (SMMUL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
38913
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::SMMUL),
38914
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
38915
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
38916
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38917
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38918
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38919
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38920
0
        GIR_EraseFromParent, /*InsnID*/0,
38921
        // GIR_Coverage, 178,
38922
0
        GIR_Done,
38923
      // Label 1913: @125068
38924
0
      GIM_Try, /*On fail goto*//*Label 1914*/ GIMT_Encode4(125121), // Rule ID 515 //
38925
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
38926
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38927
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38928
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38929
        // (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMMUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
38930
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2SMMUL),
38931
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
38932
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
38933
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38934
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38935
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38936
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38937
0
        GIR_EraseFromParent, /*InsnID*/0,
38938
        // GIR_Coverage, 515,
38939
0
        GIR_Done,
38940
      // Label 1914: @125121
38941
0
      GIM_Reject,
38942
    // Label 1912: @125122
38943
0
    GIM_Reject,
38944
    // Label 1908: @125123
38945
0
    GIM_Try, /*On fail goto*//*Label 1915*/ GIMT_Encode4(125203), // Rule ID 4576 //
38946
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
38947
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
38948
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
38949
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38950
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38951
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38952
      // (mulhs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
38953
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38954
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38955
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
38956
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs32),
38957
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
38958
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
38959
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
38960
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38961
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38962
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38963
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38964
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38965
0
      GIR_EraseFromParent, /*InsnID*/0,
38966
      // GIR_Coverage, 4576,
38967
0
      GIR_Done,
38968
    // Label 1915: @125203
38969
0
    GIM_Reject,
38970
    // Label 1909: @125204
38971
0
    GIM_Try, /*On fail goto*//*Label 1916*/ GIMT_Encode4(125284), // Rule ID 4572 //
38972
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
38973
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
38974
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
38975
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38976
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38977
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38978
      // (mulhs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
38979
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38980
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38981
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
38982
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs16),
38983
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
38984
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
38985
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
38986
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38987
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38988
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38989
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38990
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38991
0
      GIR_EraseFromParent, /*InsnID*/0,
38992
      // GIR_Coverage, 4572,
38993
0
      GIR_Done,
38994
    // Label 1916: @125284
38995
0
    GIM_Reject,
38996
    // Label 1910: @125285
38997
0
    GIM_Try, /*On fail goto*//*Label 1917*/ GIMT_Encode4(125365), // Rule ID 4569 //
38998
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
38999
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
39000
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
39001
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39002
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39003
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39004
      // (mulhs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
39005
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39006
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39007
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
39008
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs8),
39009
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
39010
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
39011
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39012
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39013
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39014
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39015
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39016
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39017
0
      GIR_EraseFromParent, /*InsnID*/0,
39018
      // GIR_Coverage, 4569,
39019
0
      GIR_Done,
39020
    // Label 1917: @125365
39021
0
    GIM_Reject,
39022
    // Label 1911: @125366
39023
0
    GIM_Reject,
39024
    // Label 28: @125367
39025
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(16), /*)*//*default:*//*Label 1926*/ GIMT_Encode4(126164),
39026
0
    /*GILLT_s64*//*Label 1918*/ GIMT_Encode4(125434), GIMT_Encode4(0),
39027
0
    /*GILLT_v2s32*//*Label 1919*/ GIMT_Encode4(125496),
39028
0
    /*GILLT_v2s64*//*Label 1920*/ GIMT_Encode4(125558), GIMT_Encode4(0),
39029
0
    /*GILLT_v4s16*//*Label 1921*/ GIMT_Encode4(125620),
39030
0
    /*GILLT_v4s32*//*Label 1922*/ GIMT_Encode4(125682), GIMT_Encode4(0), GIMT_Encode4(0),
39031
0
    /*GILLT_v8s8*//*Label 1923*/ GIMT_Encode4(125822),
39032
0
    /*GILLT_v8s16*//*Label 1924*/ GIMT_Encode4(125884), GIMT_Encode4(0), GIMT_Encode4(0),
39033
0
    /*GILLT_v16s8*//*Label 1925*/ GIMT_Encode4(126024),
39034
    // Label 1918: @125434
39035
0
    GIM_Try, /*On fail goto*//*Label 1927*/ GIMT_Encode4(125495), // Rule ID 847 //
39036
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39037
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
39038
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
39039
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39040
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39041
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39042
      // (uaddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VQADDuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
39043
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQADDuv1i64),
39044
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39045
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39046
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39047
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39048
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39049
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39050
0
      GIR_EraseFromParent, /*InsnID*/0,
39051
      // GIR_Coverage, 847,
39052
0
      GIR_Done,
39053
    // Label 1927: @125495
39054
0
    GIM_Reject,
39055
    // Label 1919: @125496
39056
0
    GIM_Try, /*On fail goto*//*Label 1928*/ GIMT_Encode4(125557), // Rule ID 842 //
39057
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39058
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
39059
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
39060
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39061
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39062
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39063
      // (uaddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
39064
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQADDuv2i32),
39065
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39066
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39067
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39068
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39069
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39070
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39071
0
      GIR_EraseFromParent, /*InsnID*/0,
39072
      // GIR_Coverage, 842,
39073
0
      GIR_Done,
39074
    // Label 1928: @125557
39075
0
    GIM_Reject,
39076
    // Label 1920: @125558
39077
0
    GIM_Try, /*On fail goto*//*Label 1929*/ GIMT_Encode4(125619), // Rule ID 848 //
39078
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39079
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
39080
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
39081
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39082
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39083
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39084
      // (uaddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VQADDuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
39085
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQADDuv2i64),
39086
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39087
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39088
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39089
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39090
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39091
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39092
0
      GIR_EraseFromParent, /*InsnID*/0,
39093
      // GIR_Coverage, 848,
39094
0
      GIR_Done,
39095
    // Label 1929: @125619
39096
0
    GIM_Reject,
39097
    // Label 1921: @125620
39098
0
    GIM_Try, /*On fail goto*//*Label 1930*/ GIMT_Encode4(125681), // Rule ID 841 //
39099
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39100
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
39101
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
39102
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39103
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39104
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39105
      // (uaddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
39106
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQADDuv4i16),
39107
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39108
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39109
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39110
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39111
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39112
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39113
0
      GIR_EraseFromParent, /*InsnID*/0,
39114
      // GIR_Coverage, 841,
39115
0
      GIR_Done,
39116
    // Label 1930: @125681
39117
0
    GIM_Reject,
39118
    // Label 1922: @125682
39119
0
    GIM_Try, /*On fail goto*//*Label 1931*/ GIMT_Encode4(125821),
39120
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
39121
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
39122
0
      GIM_Try, /*On fail goto*//*Label 1932*/ GIMT_Encode4(125748), // Rule ID 844 //
39123
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39124
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39125
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39126
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39127
        // (uaddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
39128
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQADDuv4i32),
39129
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39130
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39131
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39132
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39133
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39134
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39135
0
        GIR_EraseFromParent, /*InsnID*/0,
39136
        // GIR_Coverage, 844,
39137
0
        GIR_Done,
39138
      // Label 1932: @125748
39139
0
      GIM_Try, /*On fail goto*//*Label 1933*/ GIMT_Encode4(125820), // Rule ID 3633 //
39140
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39141
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39142
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39143
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39144
        // (uaddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VQADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
39145
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39146
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39147
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
39148
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu32),
39149
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
39150
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
39151
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39152
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39153
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39154
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39155
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39156
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39157
0
        GIR_EraseFromParent, /*InsnID*/0,
39158
        // GIR_Coverage, 3633,
39159
0
        GIR_Done,
39160
      // Label 1933: @125820
39161
0
      GIM_Reject,
39162
    // Label 1931: @125821
39163
0
    GIM_Reject,
39164
    // Label 1923: @125822
39165
0
    GIM_Try, /*On fail goto*//*Label 1934*/ GIMT_Encode4(125883), // Rule ID 845 //
39166
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39167
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
39168
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
39169
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39170
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39171
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39172
      // (uaddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VQADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
39173
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQADDuv8i8),
39174
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39175
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39176
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39177
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39178
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39179
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39180
0
      GIR_EraseFromParent, /*InsnID*/0,
39181
      // GIR_Coverage, 845,
39182
0
      GIR_Done,
39183
    // Label 1934: @125883
39184
0
    GIM_Reject,
39185
    // Label 1924: @125884
39186
0
    GIM_Try, /*On fail goto*//*Label 1935*/ GIMT_Encode4(126023),
39187
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
39188
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
39189
0
      GIM_Try, /*On fail goto*//*Label 1936*/ GIMT_Encode4(125950), // Rule ID 843 //
39190
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39191
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39192
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39193
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39194
        // (uaddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
39195
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQADDuv8i16),
39196
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39197
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39198
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39199
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39200
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39201
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39202
0
        GIR_EraseFromParent, /*InsnID*/0,
39203
        // GIR_Coverage, 843,
39204
0
        GIR_Done,
39205
      // Label 1936: @125950
39206
0
      GIM_Try, /*On fail goto*//*Label 1937*/ GIMT_Encode4(126022), // Rule ID 3630 //
39207
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39208
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39209
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39210
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39211
        // (uaddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VQADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
39212
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39213
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39214
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
39215
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu16),
39216
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
39217
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
39218
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39219
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39220
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39221
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39222
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39223
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39224
0
        GIR_EraseFromParent, /*InsnID*/0,
39225
        // GIR_Coverage, 3630,
39226
0
        GIR_Done,
39227
      // Label 1937: @126022
39228
0
      GIM_Reject,
39229
    // Label 1935: @126023
39230
0
    GIM_Reject,
39231
    // Label 1925: @126024
39232
0
    GIM_Try, /*On fail goto*//*Label 1938*/ GIMT_Encode4(126163),
39233
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
39234
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
39235
0
      GIM_Try, /*On fail goto*//*Label 1939*/ GIMT_Encode4(126090), // Rule ID 846 //
39236
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39237
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39238
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39239
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39240
        // (uaddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VQADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
39241
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQADDuv16i8),
39242
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39243
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39244
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39245
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39246
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39247
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39248
0
        GIR_EraseFromParent, /*InsnID*/0,
39249
        // GIR_Coverage, 846,
39250
0
        GIR_Done,
39251
      // Label 1939: @126090
39252
0
      GIM_Try, /*On fail goto*//*Label 1940*/ GIMT_Encode4(126162), // Rule ID 3627 //
39253
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39254
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39255
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39256
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39257
        // (uaddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VQADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
39258
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39259
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39260
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
39261
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu8),
39262
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
39263
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
39264
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39265
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39266
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39267
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39268
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39269
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39270
0
        GIR_EraseFromParent, /*InsnID*/0,
39271
        // GIR_Coverage, 3627,
39272
0
        GIR_Done,
39273
      // Label 1940: @126162
39274
0
      GIM_Reject,
39275
    // Label 1938: @126163
39276
0
    GIM_Reject,
39277
    // Label 1926: @126164
39278
0
    GIM_Reject,
39279
    // Label 29: @126165
39280
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 1950*/ GIMT_Encode4(127723),
39281
0
    /*GILLT_s32*//*Label 1941*/ GIMT_Encode4(126236),
39282
0
    /*GILLT_s64*//*Label 1942*/ GIMT_Encode4(126645), GIMT_Encode4(0),
39283
0
    /*GILLT_v2s32*//*Label 1943*/ GIMT_Encode4(126707),
39284
0
    /*GILLT_v2s64*//*Label 1944*/ GIMT_Encode4(126769), GIMT_Encode4(0),
39285
0
    /*GILLT_v4s16*//*Label 1945*/ GIMT_Encode4(127003),
39286
0
    /*GILLT_v4s32*//*Label 1946*/ GIMT_Encode4(127065), GIMT_Encode4(0), GIMT_Encode4(0),
39287
0
    /*GILLT_v8s8*//*Label 1947*/ GIMT_Encode4(127381),
39288
0
    /*GILLT_v8s16*//*Label 1948*/ GIMT_Encode4(127443), GIMT_Encode4(0), GIMT_Encode4(0),
39289
0
    /*GILLT_v16s8*//*Label 1949*/ GIMT_Encode4(127583),
39290
    // Label 1941: @126236
39291
0
    GIM_Try, /*On fail goto*//*Label 1951*/ GIMT_Encode4(126644),
39292
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
39293
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
39294
0
      GIM_Try, /*On fail goto*//*Label 1952*/ GIMT_Encode4(126321), // Rule ID 5780 //
39295
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
39296
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
39297
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39298
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
39299
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39300
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39301
        // MIs[1] Rn
39302
0
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
39303
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39304
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
39305
        // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm)  =>  (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
39306
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::QDADD),
39307
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
39308
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
39309
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
39310
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39311
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39312
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39313
0
        GIR_EraseFromParent, /*InsnID*/0,
39314
        // GIR_Coverage, 5780,
39315
0
        GIR_Done,
39316
      // Label 1952: @126321
39317
0
      GIM_Try, /*On fail goto*//*Label 1953*/ GIMT_Encode4(126393), // Rule ID 5814 //
39318
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
39319
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39320
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39321
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
39322
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39323
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39324
        // MIs[1] Rn
39325
0
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
39326
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39327
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
39328
        // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm)  =>  (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
39329
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2QDADD),
39330
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
39331
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
39332
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
39333
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39334
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39335
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39336
0
        GIR_EraseFromParent, /*InsnID*/0,
39337
        // GIR_Coverage, 5814,
39338
0
        GIR_Done,
39339
      // Label 1953: @126393
39340
0
      GIM_Try, /*On fail goto*//*Label 1954*/ GIMT_Encode4(126465), // Rule ID 1898 //
39341
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
39342
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
39343
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39344
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39345
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
39346
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39347
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39348
        // MIs[1] Rn
39349
0
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
39350
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
39351
        // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn))  =>  (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
39352
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::QDADD),
39353
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
39354
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
39355
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
39356
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39357
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39358
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39359
0
        GIR_EraseFromParent, /*InsnID*/0,
39360
        // GIR_Coverage, 1898,
39361
0
        GIR_Done,
39362
      // Label 1954: @126465
39363
0
      GIM_Try, /*On fail goto*//*Label 1955*/ GIMT_Encode4(126537), // Rule ID 2152 //
39364
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
39365
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39366
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39367
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39368
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
39369
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39370
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39371
        // MIs[1] Rn
39372
0
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
39373
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
39374
        // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn))  =>  (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
39375
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2QDADD),
39376
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
39377
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
39378
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
39379
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39380
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39381
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39382
0
        GIR_EraseFromParent, /*InsnID*/0,
39383
        // GIR_Coverage, 2152,
39384
0
        GIR_Done,
39385
      // Label 1955: @126537
39386
0
      GIM_Try, /*On fail goto*//*Label 1956*/ GIMT_Encode4(126590), // Rule ID 1896 //
39387
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
39388
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
39389
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
39390
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
39391
        // (saddsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (QADD:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
39392
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::QADD),
39393
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
39394
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // a
39395
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b
39396
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39397
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39398
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39399
0
        GIR_EraseFromParent, /*InsnID*/0,
39400
        // GIR_Coverage, 1896,
39401
0
        GIR_Done,
39402
      // Label 1956: @126590
39403
0
      GIM_Try, /*On fail goto*//*Label 1957*/ GIMT_Encode4(126643), // Rule ID 2150 //
39404
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
39405
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39406
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39407
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39408
        // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)  =>  (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
39409
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2QADD),
39410
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
39411
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
39412
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
39413
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39414
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39415
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39416
0
        GIR_EraseFromParent, /*InsnID*/0,
39417
        // GIR_Coverage, 2150,
39418
0
        GIR_Done,
39419
      // Label 1957: @126643
39420
0
      GIM_Reject,
39421
    // Label 1951: @126644
39422
0
    GIM_Reject,
39423
    // Label 1942: @126645
39424
0
    GIM_Try, /*On fail goto*//*Label 1958*/ GIMT_Encode4(126706), // Rule ID 839 //
39425
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39426
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
39427
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
39428
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39429
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39430
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39431
      // (saddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VQADDsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
39432
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQADDsv1i64),
39433
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39434
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39435
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39436
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39437
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39438
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39439
0
      GIR_EraseFromParent, /*InsnID*/0,
39440
      // GIR_Coverage, 839,
39441
0
      GIR_Done,
39442
    // Label 1958: @126706
39443
0
    GIM_Reject,
39444
    // Label 1943: @126707
39445
0
    GIM_Try, /*On fail goto*//*Label 1959*/ GIMT_Encode4(126768), // Rule ID 834 //
39446
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39447
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
39448
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
39449
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39450
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39451
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39452
      // (saddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
39453
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQADDsv2i32),
39454
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39455
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39456
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39457
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39458
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39459
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39460
0
      GIR_EraseFromParent, /*InsnID*/0,
39461
      // GIR_Coverage, 834,
39462
0
      GIR_Done,
39463
    // Label 1959: @126768
39464
0
    GIM_Reject,
39465
    // Label 1944: @126769
39466
0
    GIM_Try, /*On fail goto*//*Label 1960*/ GIMT_Encode4(127002),
39467
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
39468
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
39469
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39470
0
      GIM_Try, /*On fail goto*//*Label 1961*/ GIMT_Encode4(126870), // Rule ID 5871 //
39471
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39472
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39473
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
39474
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
39475
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
39476
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
39477
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
39478
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39479
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39480
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39481
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
39482
        // (saddsat:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 3125:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$src1)  =>  (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
39483
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv2i64),
39484
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39485
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
39486
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
39487
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
39488
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39489
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39490
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39491
0
        GIR_EraseFromParent, /*InsnID*/0,
39492
        // GIR_Coverage, 5871,
39493
0
        GIR_Done,
39494
      // Label 1961: @126870
39495
0
      GIM_Try, /*On fail goto*//*Label 1962*/ GIMT_Encode4(126953), // Rule ID 2495 //
39496
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39497
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39498
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39499
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
39500
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
39501
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
39502
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
39503
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
39504
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39505
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39506
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
39507
        // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 3125:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
39508
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv2i64),
39509
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39510
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
39511
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
39512
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
39513
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39514
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39515
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39516
0
        GIR_EraseFromParent, /*InsnID*/0,
39517
        // GIR_Coverage, 2495,
39518
0
        GIR_Done,
39519
      // Label 1962: @126953
39520
0
      GIM_Try, /*On fail goto*//*Label 1963*/ GIMT_Encode4(127001), // Rule ID 840 //
39521
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39522
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39523
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39524
        // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VQADDsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
39525
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQADDsv2i64),
39526
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39527
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39528
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39529
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39530
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39531
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39532
0
        GIR_EraseFromParent, /*InsnID*/0,
39533
        // GIR_Coverage, 840,
39534
0
        GIR_Done,
39535
      // Label 1963: @127001
39536
0
      GIM_Reject,
39537
    // Label 1960: @127002
39538
0
    GIM_Reject,
39539
    // Label 1945: @127003
39540
0
    GIM_Try, /*On fail goto*//*Label 1964*/ GIMT_Encode4(127064), // Rule ID 833 //
39541
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39542
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
39543
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
39544
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39545
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39546
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39547
      // (saddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
39548
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQADDsv4i16),
39549
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39550
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39551
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39552
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39553
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39554
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39555
0
      GIR_EraseFromParent, /*InsnID*/0,
39556
      // GIR_Coverage, 833,
39557
0
      GIR_Done,
39558
    // Label 1964: @127064
39559
0
    GIM_Reject,
39560
    // Label 1946: @127065
39561
0
    GIM_Try, /*On fail goto*//*Label 1965*/ GIMT_Encode4(127380),
39562
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
39563
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
39564
0
      GIM_Try, /*On fail goto*//*Label 1966*/ GIMT_Encode4(127166), // Rule ID 5870 //
39565
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39566
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39567
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39568
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
39569
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
39570
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
39571
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
39572
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
39573
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39574
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39575
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39576
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
39577
        // (saddsat:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 3125:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
39578
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv4i32),
39579
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39580
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
39581
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
39582
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
39583
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39584
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39585
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39586
0
        GIR_EraseFromParent, /*InsnID*/0,
39587
        // GIR_Coverage, 5870,
39588
0
        GIR_Done,
39589
      // Label 1966: @127166
39590
0
      GIM_Try, /*On fail goto*//*Label 1967*/ GIMT_Encode4(127254), // Rule ID 2494 //
39591
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39592
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39593
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39594
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39595
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
39596
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
39597
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
39598
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
39599
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
39600
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39601
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39602
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
39603
        // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 3125:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
39604
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv4i32),
39605
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39606
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
39607
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
39608
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
39609
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39610
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39611
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39612
0
        GIR_EraseFromParent, /*InsnID*/0,
39613
        // GIR_Coverage, 2494,
39614
0
        GIR_Done,
39615
      // Label 1967: @127254
39616
0
      GIM_Try, /*On fail goto*//*Label 1968*/ GIMT_Encode4(127307), // Rule ID 836 //
39617
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39618
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39619
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39620
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39621
        // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
39622
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQADDsv4i32),
39623
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39624
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39625
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39626
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39627
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39628
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39629
0
        GIR_EraseFromParent, /*InsnID*/0,
39630
        // GIR_Coverage, 836,
39631
0
        GIR_Done,
39632
      // Label 1968: @127307
39633
0
      GIM_Try, /*On fail goto*//*Label 1969*/ GIMT_Encode4(127379), // Rule ID 3624 //
39634
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39635
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39636
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39637
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39638
        // (saddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VQADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
39639
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39640
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39641
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
39642
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs32),
39643
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
39644
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
39645
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39646
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39647
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39648
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39649
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39650
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39651
0
        GIR_EraseFromParent, /*InsnID*/0,
39652
        // GIR_Coverage, 3624,
39653
0
        GIR_Done,
39654
      // Label 1969: @127379
39655
0
      GIM_Reject,
39656
    // Label 1965: @127380
39657
0
    GIM_Reject,
39658
    // Label 1947: @127381
39659
0
    GIM_Try, /*On fail goto*//*Label 1970*/ GIMT_Encode4(127442), // Rule ID 837 //
39660
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39661
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
39662
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
39663
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39664
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39665
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39666
      // (saddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VQADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
39667
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQADDsv8i8),
39668
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39669
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39670
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39671
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39672
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39673
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39674
0
      GIR_EraseFromParent, /*InsnID*/0,
39675
      // GIR_Coverage, 837,
39676
0
      GIR_Done,
39677
    // Label 1970: @127442
39678
0
    GIM_Reject,
39679
    // Label 1948: @127443
39680
0
    GIM_Try, /*On fail goto*//*Label 1971*/ GIMT_Encode4(127582),
39681
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
39682
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
39683
0
      GIM_Try, /*On fail goto*//*Label 1972*/ GIMT_Encode4(127509), // Rule ID 835 //
39684
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39685
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39686
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39687
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39688
        // (saddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
39689
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQADDsv8i16),
39690
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39691
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39692
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39693
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39694
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39695
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39696
0
        GIR_EraseFromParent, /*InsnID*/0,
39697
        // GIR_Coverage, 835,
39698
0
        GIR_Done,
39699
      // Label 1972: @127509
39700
0
      GIM_Try, /*On fail goto*//*Label 1973*/ GIMT_Encode4(127581), // Rule ID 3621 //
39701
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39702
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39703
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39704
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39705
        // (saddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VQADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
39706
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39707
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39708
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
39709
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs16),
39710
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
39711
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
39712
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39713
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39714
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39715
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39716
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39717
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39718
0
        GIR_EraseFromParent, /*InsnID*/0,
39719
        // GIR_Coverage, 3621,
39720
0
        GIR_Done,
39721
      // Label 1973: @127581
39722
0
      GIM_Reject,
39723
    // Label 1971: @127582
39724
0
    GIM_Reject,
39725
    // Label 1949: @127583
39726
0
    GIM_Try, /*On fail goto*//*Label 1974*/ GIMT_Encode4(127722),
39727
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
39728
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
39729
0
      GIM_Try, /*On fail goto*//*Label 1975*/ GIMT_Encode4(127649), // Rule ID 838 //
39730
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39731
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39732
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39733
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39734
        // (saddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VQADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
39735
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQADDsv16i8),
39736
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39737
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39738
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39739
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39740
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39741
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39742
0
        GIR_EraseFromParent, /*InsnID*/0,
39743
        // GIR_Coverage, 838,
39744
0
        GIR_Done,
39745
      // Label 1975: @127649
39746
0
      GIM_Try, /*On fail goto*//*Label 1976*/ GIMT_Encode4(127721), // Rule ID 3618 //
39747
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39748
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39749
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39750
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39751
        // (saddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VQADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
39752
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39753
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39754
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
39755
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs8),
39756
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
39757
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
39758
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39759
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39760
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39761
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39762
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39763
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39764
0
        GIR_EraseFromParent, /*InsnID*/0,
39765
        // GIR_Coverage, 3618,
39766
0
        GIR_Done,
39767
      // Label 1976: @127721
39768
0
      GIM_Reject,
39769
    // Label 1974: @127722
39770
0
    GIM_Reject,
39771
    // Label 1950: @127723
39772
0
    GIM_Reject,
39773
    // Label 30: @127724
39774
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(16), /*)*//*default:*//*Label 1985*/ GIMT_Encode4(128521),
39775
0
    /*GILLT_s64*//*Label 1977*/ GIMT_Encode4(127791), GIMT_Encode4(0),
39776
0
    /*GILLT_v2s32*//*Label 1978*/ GIMT_Encode4(127853),
39777
0
    /*GILLT_v2s64*//*Label 1979*/ GIMT_Encode4(127915), GIMT_Encode4(0),
39778
0
    /*GILLT_v4s16*//*Label 1980*/ GIMT_Encode4(127977),
39779
0
    /*GILLT_v4s32*//*Label 1981*/ GIMT_Encode4(128039), GIMT_Encode4(0), GIMT_Encode4(0),
39780
0
    /*GILLT_v8s8*//*Label 1982*/ GIMT_Encode4(128179),
39781
0
    /*GILLT_v8s16*//*Label 1983*/ GIMT_Encode4(128241), GIMT_Encode4(0), GIMT_Encode4(0),
39782
0
    /*GILLT_v16s8*//*Label 1984*/ GIMT_Encode4(128381),
39783
    // Label 1977: @127791
39784
0
    GIM_Try, /*On fail goto*//*Label 1986*/ GIMT_Encode4(127852), // Rule ID 1039 //
39785
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39786
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
39787
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
39788
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39789
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39790
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39791
      // (usubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VQSUBuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
39792
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv1i64),
39793
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39794
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39795
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39796
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39797
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39798
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39799
0
      GIR_EraseFromParent, /*InsnID*/0,
39800
      // GIR_Coverage, 1039,
39801
0
      GIR_Done,
39802
    // Label 1986: @127852
39803
0
    GIM_Reject,
39804
    // Label 1978: @127853
39805
0
    GIM_Try, /*On fail goto*//*Label 1987*/ GIMT_Encode4(127914), // Rule ID 1034 //
39806
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39807
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
39808
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
39809
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39810
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39811
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39812
      // (usubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
39813
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv2i32),
39814
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39815
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39816
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39817
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39818
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39819
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39820
0
      GIR_EraseFromParent, /*InsnID*/0,
39821
      // GIR_Coverage, 1034,
39822
0
      GIR_Done,
39823
    // Label 1987: @127914
39824
0
    GIM_Reject,
39825
    // Label 1979: @127915
39826
0
    GIM_Try, /*On fail goto*//*Label 1988*/ GIMT_Encode4(127976), // Rule ID 1040 //
39827
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39828
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
39829
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
39830
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39831
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39832
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39833
      // (usubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VQSUBuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
39834
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv2i64),
39835
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39836
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39837
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39838
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39839
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39840
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39841
0
      GIR_EraseFromParent, /*InsnID*/0,
39842
      // GIR_Coverage, 1040,
39843
0
      GIR_Done,
39844
    // Label 1988: @127976
39845
0
    GIM_Reject,
39846
    // Label 1980: @127977
39847
0
    GIM_Try, /*On fail goto*//*Label 1989*/ GIMT_Encode4(128038), // Rule ID 1033 //
39848
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39849
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
39850
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
39851
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39852
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39853
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39854
      // (usubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
39855
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv4i16),
39856
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39857
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39858
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39859
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39860
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39861
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39862
0
      GIR_EraseFromParent, /*InsnID*/0,
39863
      // GIR_Coverage, 1033,
39864
0
      GIR_Done,
39865
    // Label 1989: @128038
39866
0
    GIM_Reject,
39867
    // Label 1981: @128039
39868
0
    GIM_Try, /*On fail goto*//*Label 1990*/ GIMT_Encode4(128178),
39869
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
39870
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
39871
0
      GIM_Try, /*On fail goto*//*Label 1991*/ GIMT_Encode4(128105), // Rule ID 1036 //
39872
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39873
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39874
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39875
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39876
        // (usubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
39877
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv4i32),
39878
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39879
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39880
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39881
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39882
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39883
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39884
0
        GIR_EraseFromParent, /*InsnID*/0,
39885
        // GIR_Coverage, 1036,
39886
0
        GIR_Done,
39887
      // Label 1991: @128105
39888
0
      GIM_Try, /*On fail goto*//*Label 1992*/ GIMT_Encode4(128177), // Rule ID 3651 //
39889
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39890
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39891
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39892
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39893
        // (usubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VQSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
39894
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39895
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39896
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
39897
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu32),
39898
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
39899
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
39900
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39901
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39902
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39903
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39904
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39905
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39906
0
        GIR_EraseFromParent, /*InsnID*/0,
39907
        // GIR_Coverage, 3651,
39908
0
        GIR_Done,
39909
      // Label 1992: @128177
39910
0
      GIM_Reject,
39911
    // Label 1990: @128178
39912
0
    GIM_Reject,
39913
    // Label 1982: @128179
39914
0
    GIM_Try, /*On fail goto*//*Label 1993*/ GIMT_Encode4(128240), // Rule ID 1037 //
39915
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39916
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
39917
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
39918
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39919
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39920
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39921
      // (usubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VQSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
39922
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv8i8),
39923
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39924
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39925
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39926
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39927
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39928
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39929
0
      GIR_EraseFromParent, /*InsnID*/0,
39930
      // GIR_Coverage, 1037,
39931
0
      GIR_Done,
39932
    // Label 1993: @128240
39933
0
    GIM_Reject,
39934
    // Label 1983: @128241
39935
0
    GIM_Try, /*On fail goto*//*Label 1994*/ GIMT_Encode4(128380),
39936
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
39937
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
39938
0
      GIM_Try, /*On fail goto*//*Label 1995*/ GIMT_Encode4(128307), // Rule ID 1035 //
39939
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39940
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39941
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39942
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39943
        // (usubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
39944
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv8i16),
39945
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39946
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39947
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39948
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39949
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39950
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39951
0
        GIR_EraseFromParent, /*InsnID*/0,
39952
        // GIR_Coverage, 1035,
39953
0
        GIR_Done,
39954
      // Label 1995: @128307
39955
0
      GIM_Try, /*On fail goto*//*Label 1996*/ GIMT_Encode4(128379), // Rule ID 3648 //
39956
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39957
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39958
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39959
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39960
        // (usubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VQSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
39961
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39962
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39963
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
39964
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu16),
39965
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
39966
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
39967
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39968
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39969
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39970
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39971
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39972
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39973
0
        GIR_EraseFromParent, /*InsnID*/0,
39974
        // GIR_Coverage, 3648,
39975
0
        GIR_Done,
39976
      // Label 1996: @128379
39977
0
      GIM_Reject,
39978
    // Label 1994: @128380
39979
0
    GIM_Reject,
39980
    // Label 1984: @128381
39981
0
    GIM_Try, /*On fail goto*//*Label 1997*/ GIMT_Encode4(128520),
39982
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
39983
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
39984
0
      GIM_Try, /*On fail goto*//*Label 1998*/ GIMT_Encode4(128447), // Rule ID 1038 //
39985
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39986
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39987
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39988
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39989
        // (usubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VQSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
39990
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv16i8),
39991
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
39992
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39993
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39994
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39995
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39996
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39997
0
        GIR_EraseFromParent, /*InsnID*/0,
39998
        // GIR_Coverage, 1038,
39999
0
        GIR_Done,
40000
      // Label 1998: @128447
40001
0
      GIM_Try, /*On fail goto*//*Label 1999*/ GIMT_Encode4(128519), // Rule ID 3645 //
40002
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
40003
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40004
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40005
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40006
        // (usubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VQSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
40007
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40008
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40009
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
40010
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu8),
40011
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
40012
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
40013
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
40014
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40015
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40016
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40017
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40018
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40019
0
        GIR_EraseFromParent, /*InsnID*/0,
40020
        // GIR_Coverage, 3645,
40021
0
        GIR_Done,
40022
      // Label 1999: @128519
40023
0
      GIM_Reject,
40024
    // Label 1997: @128520
40025
0
    GIM_Reject,
40026
    // Label 1985: @128521
40027
0
    GIM_Reject,
40028
    // Label 31: @128522
40029
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 2009*/ GIMT_Encode4(129760),
40030
0
    /*GILLT_s32*//*Label 2000*/ GIMT_Encode4(128593),
40031
0
    /*GILLT_s64*//*Label 2001*/ GIMT_Encode4(128858), GIMT_Encode4(0),
40032
0
    /*GILLT_v2s32*//*Label 2002*/ GIMT_Encode4(128920),
40033
0
    /*GILLT_v2s64*//*Label 2003*/ GIMT_Encode4(128982), GIMT_Encode4(0),
40034
0
    /*GILLT_v4s16*//*Label 2004*/ GIMT_Encode4(129128),
40035
0
    /*GILLT_v4s32*//*Label 2005*/ GIMT_Encode4(129190), GIMT_Encode4(0), GIMT_Encode4(0),
40036
0
    /*GILLT_v8s8*//*Label 2006*/ GIMT_Encode4(129418),
40037
0
    /*GILLT_v8s16*//*Label 2007*/ GIMT_Encode4(129480), GIMT_Encode4(0), GIMT_Encode4(0),
40038
0
    /*GILLT_v16s8*//*Label 2008*/ GIMT_Encode4(129620),
40039
    // Label 2000: @128593
40040
0
    GIM_Try, /*On fail goto*//*Label 2010*/ GIMT_Encode4(128857),
40041
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
40042
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
40043
0
      GIM_Try, /*On fail goto*//*Label 2011*/ GIMT_Encode4(128678), // Rule ID 1899 //
40044
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
40045
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
40046
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40047
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40048
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
40049
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40050
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40051
        // MIs[1] Rn
40052
0
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
40053
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
40054
        // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn))  =>  (QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
40055
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::QDSUB),
40056
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
40057
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
40058
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
40059
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40060
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40061
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40062
0
        GIR_EraseFromParent, /*InsnID*/0,
40063
        // GIR_Coverage, 1899,
40064
0
        GIR_Done,
40065
      // Label 2011: @128678
40066
0
      GIM_Try, /*On fail goto*//*Label 2012*/ GIMT_Encode4(128750), // Rule ID 2153 //
40067
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
40068
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40069
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40070
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40071
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
40072
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40073
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40074
        // MIs[1] Rn
40075
0
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
40076
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
40077
        // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn))  =>  (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
40078
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2QDSUB),
40079
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
40080
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
40081
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
40082
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40083
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40084
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40085
0
        GIR_EraseFromParent, /*InsnID*/0,
40086
        // GIR_Coverage, 2153,
40087
0
        GIR_Done,
40088
      // Label 2012: @128750
40089
0
      GIM_Try, /*On fail goto*//*Label 2013*/ GIMT_Encode4(128803), // Rule ID 1897 //
40090
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
40091
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
40092
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
40093
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
40094
        // (ssubsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (QSUB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
40095
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::QSUB),
40096
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
40097
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // a
40098
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b
40099
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40100
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40101
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40102
0
        GIR_EraseFromParent, /*InsnID*/0,
40103
        // GIR_Coverage, 1897,
40104
0
        GIR_Done,
40105
      // Label 2013: @128803
40106
0
      GIM_Try, /*On fail goto*//*Label 2014*/ GIMT_Encode4(128856), // Rule ID 2151 //
40107
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
40108
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40109
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40110
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40111
        // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)  =>  (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
40112
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2QSUB),
40113
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
40114
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
40115
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
40116
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40117
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40118
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40119
0
        GIR_EraseFromParent, /*InsnID*/0,
40120
        // GIR_Coverage, 2151,
40121
0
        GIR_Done,
40122
      // Label 2014: @128856
40123
0
      GIM_Reject,
40124
    // Label 2010: @128857
40125
0
    GIM_Reject,
40126
    // Label 2001: @128858
40127
0
    GIM_Try, /*On fail goto*//*Label 2015*/ GIMT_Encode4(128919), // Rule ID 1031 //
40128
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40129
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
40130
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
40131
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40132
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40133
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40134
      // (ssubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VQSUBsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
40135
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv1i64),
40136
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
40137
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40138
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40139
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40140
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40141
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40142
0
      GIR_EraseFromParent, /*InsnID*/0,
40143
      // GIR_Coverage, 1031,
40144
0
      GIR_Done,
40145
    // Label 2015: @128919
40146
0
    GIM_Reject,
40147
    // Label 2002: @128920
40148
0
    GIM_Try, /*On fail goto*//*Label 2016*/ GIMT_Encode4(128981), // Rule ID 1026 //
40149
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40150
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
40151
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
40152
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40153
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40154
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40155
      // (ssubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
40156
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv2i32),
40157
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
40158
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40159
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40160
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40161
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40162
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40163
0
      GIR_EraseFromParent, /*InsnID*/0,
40164
      // GIR_Coverage, 1026,
40165
0
      GIR_Done,
40166
    // Label 2016: @128981
40167
0
    GIM_Reject,
40168
    // Label 2003: @128982
40169
0
    GIM_Try, /*On fail goto*//*Label 2017*/ GIMT_Encode4(129127),
40170
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
40171
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
40172
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40173
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40174
0
      GIM_Try, /*On fail goto*//*Label 2018*/ GIMT_Encode4(129083), // Rule ID 2502 //
40175
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40176
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40177
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
40178
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
40179
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
40180
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
40181
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
40182
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40183
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40184
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
40185
        // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 3125:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VQDMLSLv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
40186
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQDMLSLv2i64),
40187
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
40188
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
40189
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
40190
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
40191
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40192
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40193
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40194
0
        GIR_EraseFromParent, /*InsnID*/0,
40195
        // GIR_Coverage, 2502,
40196
0
        GIR_Done,
40197
      // Label 2018: @129083
40198
0
      GIM_Try, /*On fail goto*//*Label 2019*/ GIMT_Encode4(129126), // Rule ID 1032 //
40199
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40200
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40201
        // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VQSUBsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
40202
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv2i64),
40203
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
40204
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40205
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40206
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40207
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40208
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40209
0
        GIR_EraseFromParent, /*InsnID*/0,
40210
        // GIR_Coverage, 1032,
40211
0
        GIR_Done,
40212
      // Label 2019: @129126
40213
0
      GIM_Reject,
40214
    // Label 2017: @129127
40215
0
    GIM_Reject,
40216
    // Label 2004: @129128
40217
0
    GIM_Try, /*On fail goto*//*Label 2020*/ GIMT_Encode4(129189), // Rule ID 1025 //
40218
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40219
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
40220
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
40221
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40222
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40223
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40224
      // (ssubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
40225
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv4i16),
40226
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
40227
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40228
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40229
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40230
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40231
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40232
0
      GIR_EraseFromParent, /*InsnID*/0,
40233
      // GIR_Coverage, 1025,
40234
0
      GIR_Done,
40235
    // Label 2020: @129189
40236
0
    GIM_Reject,
40237
    // Label 2005: @129190
40238
0
    GIM_Try, /*On fail goto*//*Label 2021*/ GIMT_Encode4(129417),
40239
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
40240
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
40241
0
      GIM_Try, /*On fail goto*//*Label 2022*/ GIMT_Encode4(129291), // Rule ID 2501 //
40242
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40243
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40244
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40245
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40246
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
40247
0
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
40248
0
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
40249
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
40250
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
40251
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40252
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40253
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
40254
        // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 3125:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VQDMLSLv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
40255
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQDMLSLv4i32),
40256
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
40257
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
40258
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
40259
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
40260
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40261
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40262
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40263
0
        GIR_EraseFromParent, /*InsnID*/0,
40264
        // GIR_Coverage, 2501,
40265
0
        GIR_Done,
40266
      // Label 2022: @129291
40267
0
      GIM_Try, /*On fail goto*//*Label 2023*/ GIMT_Encode4(129344), // Rule ID 1028 //
40268
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40269
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40270
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40271
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40272
        // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
40273
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv4i32),
40274
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
40275
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40276
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40277
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40278
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40279
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40280
0
        GIR_EraseFromParent, /*InsnID*/0,
40281
        // GIR_Coverage, 1028,
40282
0
        GIR_Done,
40283
      // Label 2023: @129344
40284
0
      GIM_Try, /*On fail goto*//*Label 2024*/ GIMT_Encode4(129416), // Rule ID 3642 //
40285
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
40286
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40287
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40288
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40289
        // (ssubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VQSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
40290
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40291
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40292
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
40293
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs32),
40294
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
40295
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
40296
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
40297
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40298
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40299
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40300
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40301
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40302
0
        GIR_EraseFromParent, /*InsnID*/0,
40303
        // GIR_Coverage, 3642,
40304
0
        GIR_Done,
40305
      // Label 2024: @129416
40306
0
      GIM_Reject,
40307
    // Label 2021: @129417
40308
0
    GIM_Reject,
40309
    // Label 2006: @129418
40310
0
    GIM_Try, /*On fail goto*//*Label 2025*/ GIMT_Encode4(129479), // Rule ID 1029 //
40311
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40312
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
40313
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
40314
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40315
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40316
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40317
      // (ssubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VQSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
40318
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv8i8),
40319
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
40320
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40321
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40322
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40323
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40324
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40325
0
      GIR_EraseFromParent, /*InsnID*/0,
40326
      // GIR_Coverage, 1029,
40327
0
      GIR_Done,
40328
    // Label 2025: @129479
40329
0
    GIM_Reject,
40330
    // Label 2007: @129480
40331
0
    GIM_Try, /*On fail goto*//*Label 2026*/ GIMT_Encode4(129619),
40332
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
40333
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
40334
0
      GIM_Try, /*On fail goto*//*Label 2027*/ GIMT_Encode4(129546), // Rule ID 1027 //
40335
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40336
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40337
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40338
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40339
        // (ssubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
40340
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv8i16),
40341
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
40342
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40343
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40344
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40345
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40346
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40347
0
        GIR_EraseFromParent, /*InsnID*/0,
40348
        // GIR_Coverage, 1027,
40349
0
        GIR_Done,
40350
      // Label 2027: @129546
40351
0
      GIM_Try, /*On fail goto*//*Label 2028*/ GIMT_Encode4(129618), // Rule ID 3639 //
40352
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
40353
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40354
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40355
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40356
        // (ssubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VQSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
40357
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40358
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40359
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
40360
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs16),
40361
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
40362
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
40363
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
40364
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40365
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40366
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40367
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40368
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40369
0
        GIR_EraseFromParent, /*InsnID*/0,
40370
        // GIR_Coverage, 3639,
40371
0
        GIR_Done,
40372
      // Label 2028: @129618
40373
0
      GIM_Reject,
40374
    // Label 2026: @129619
40375
0
    GIM_Reject,
40376
    // Label 2008: @129620
40377
0
    GIM_Try, /*On fail goto*//*Label 2029*/ GIMT_Encode4(129759),
40378
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
40379
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
40380
0
      GIM_Try, /*On fail goto*//*Label 2030*/ GIMT_Encode4(129686), // Rule ID 1030 //
40381
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40382
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40383
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40384
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40385
        // (ssubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VQSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
40386
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv16i8),
40387
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
40388
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40389
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40390
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40391
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40392
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40393
0
        GIR_EraseFromParent, /*InsnID*/0,
40394
        // GIR_Coverage, 1030,
40395
0
        GIR_Done,
40396
      // Label 2030: @129686
40397
0
      GIM_Try, /*On fail goto*//*Label 2031*/ GIMT_Encode4(129758), // Rule ID 3636 //
40398
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
40399
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40400
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40401
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40402
        // (ssubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VQSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
40403
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40404
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40405
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
40406
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs8),
40407
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
40408
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
40409
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
40410
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40411
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40412
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40413
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40414
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40415
0
        GIR_EraseFromParent, /*InsnID*/0,
40416
        // GIR_Coverage, 3636,
40417
0
        GIR_Done,
40418
      // Label 2031: @129758
40419
0
      GIM_Reject,
40420
    // Label 2029: @129759
40421
0
    GIM_Reject,
40422
    // Label 2009: @129760
40423
0
    GIM_Reject,
40424
    // Label 32: @129761
40425
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2039*/ GIMT_Encode4(132277),
40426
0
    /*GILLT_s16*//*Label 2032*/ GIMT_Encode4(129824),
40427
0
    /*GILLT_s32*//*Label 2033*/ GIMT_Encode4(129886),
40428
0
    /*GILLT_s64*//*Label 2034*/ GIMT_Encode4(131495), GIMT_Encode4(0),
40429
0
    /*GILLT_v2s32*//*Label 2035*/ GIMT_Encode4(131557), GIMT_Encode4(0), GIMT_Encode4(0),
40430
0
    /*GILLT_v4s16*//*Label 2036*/ GIMT_Encode4(131619),
40431
0
    /*GILLT_v4s32*//*Label 2037*/ GIMT_Encode4(131837), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
40432
0
    /*GILLT_v8s16*//*Label 2038*/ GIMT_Encode4(131977),
40433
    // Label 2032: @129824
40434
0
    GIM_Try, /*On fail goto*//*Label 2040*/ GIMT_Encode4(129885), // Rule ID 631 //
40435
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
40436
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
40437
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
40438
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40439
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40440
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40441
      // (fadd:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)  =>  (VADDH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40442
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDH),
40443
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
40444
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
40445
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
40446
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40447
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40448
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40449
0
      GIR_EraseFromParent, /*InsnID*/0,
40450
      // GIR_Coverage, 631,
40451
0
      GIR_Done,
40452
    // Label 2040: @129885
40453
0
    GIM_Reject,
40454
    // Label 2033: @129886
40455
0
    GIM_Try, /*On fail goto*//*Label 2041*/ GIMT_Encode4(131494),
40456
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
40457
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
40458
0
      GIM_Try, /*On fail goto*//*Label 2042*/ GIMT_Encode4(130226), // Rule ID 6050 //
40459
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP),
40460
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40461
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40462
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
40463
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40464
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40465
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40466
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40467
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40468
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
40469
        // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b), SPR:{ *:[f32] }:$acc)  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
40470
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
40471
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
40472
0
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
40473
0
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
40474
0
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
40475
0
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
40476
0
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
40477
0
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
40478
0
        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
40479
0
        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
40480
0
        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
40481
0
        GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40482
0
        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40483
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
40484
0
        GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40485
0
        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40486
0
        GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
40487
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
40488
0
        GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40489
0
        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40490
0
        GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
40491
0
        GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
40492
0
        GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
40493
0
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40494
0
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40495
0
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40496
0
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40497
0
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40498
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
40499
0
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40500
0
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40501
0
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
40502
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
40503
0
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40504
0
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40505
0
        GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
40506
0
        GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
40507
0
        GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
40508
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40509
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40510
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40511
0
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40512
0
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40513
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
40514
0
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40515
0
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40516
0
        GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
40517
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40518
0
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40519
0
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40520
0
        GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
40521
0
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc
40522
0
        GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
40523
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40524
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40525
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40526
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLAfd),
40527
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40528
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
40529
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
40530
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
40531
0
        GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
40532
0
        GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40533
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40534
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40535
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40536
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
40537
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
40538
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40539
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
40540
0
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
40541
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
40542
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40543
0
        GIR_EraseFromParent, /*InsnID*/0,
40544
        // GIR_Coverage, 6050,
40545
0
        GIR_Done,
40546
      // Label 2042: @130226
40547
0
      GIM_Try, /*On fail goto*//*Label 2043*/ GIMT_Encode4(130553), // Rule ID 6051 //
40548
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP),
40549
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40550
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40551
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
40552
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40553
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40554
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40555
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40556
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40557
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
40558
        // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b), SPR:{ *:[f32] }:$acc)  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
40559
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
40560
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
40561
0
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
40562
0
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
40563
0
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
40564
0
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
40565
0
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
40566
0
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
40567
0
        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
40568
0
        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
40569
0
        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
40570
0
        GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40571
0
        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40572
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
40573
0
        GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40574
0
        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40575
0
        GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
40576
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
40577
0
        GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40578
0
        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40579
0
        GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
40580
0
        GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
40581
0
        GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
40582
0
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40583
0
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40584
0
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40585
0
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40586
0
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40587
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
40588
0
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40589
0
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40590
0
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
40591
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
40592
0
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40593
0
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40594
0
        GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
40595
0
        GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
40596
0
        GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
40597
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40598
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40599
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40600
0
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40601
0
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40602
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
40603
0
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40604
0
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40605
0
        GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
40606
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40607
0
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40608
0
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40609
0
        GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
40610
0
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc
40611
0
        GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
40612
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40613
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40614
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40615
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMAfd),
40616
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40617
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
40618
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
40619
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
40620
0
        GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
40621
0
        GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40622
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40623
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40624
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40625
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
40626
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
40627
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40628
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
40629
0
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
40630
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
40631
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40632
0
        GIR_EraseFromParent, /*InsnID*/0,
40633
        // GIR_Coverage, 6051,
40634
0
        GIR_Done,
40635
      // Label 2043: @130553
40636
0
      GIM_Try, /*On fail goto*//*Label 2044*/ GIMT_Encode4(130880), // Rule ID 2727 //
40637
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP),
40638
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40639
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40640
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40641
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
40642
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40643
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40644
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40645
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40646
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
40647
        // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b))  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
40648
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
40649
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
40650
0
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
40651
0
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
40652
0
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
40653
0
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
40654
0
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
40655
0
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
40656
0
        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
40657
0
        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
40658
0
        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
40659
0
        GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40660
0
        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40661
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
40662
0
        GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40663
0
        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40664
0
        GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
40665
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
40666
0
        GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40667
0
        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40668
0
        GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
40669
0
        GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
40670
0
        GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
40671
0
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40672
0
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40673
0
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40674
0
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40675
0
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40676
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
40677
0
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40678
0
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40679
0
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
40680
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
40681
0
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40682
0
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40683
0
        GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
40684
0
        GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
40685
0
        GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
40686
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40687
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40688
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40689
0
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40690
0
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40691
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
40692
0
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40693
0
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40694
0
        GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
40695
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40696
0
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40697
0
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40698
0
        GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
40699
0
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
40700
0
        GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
40701
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40702
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40703
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40704
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLAfd),
40705
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40706
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
40707
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
40708
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
40709
0
        GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
40710
0
        GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40711
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40712
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40713
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40714
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
40715
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
40716
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40717
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
40718
0
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
40719
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
40720
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40721
0
        GIR_EraseFromParent, /*InsnID*/0,
40722
        // GIR_Coverage, 2727,
40723
0
        GIR_Done,
40724
      // Label 2044: @130880
40725
0
      GIM_Try, /*On fail goto*//*Label 2045*/ GIMT_Encode4(131207), // Rule ID 2729 //
40726
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP),
40727
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40728
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40729
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40730
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
40731
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40732
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40733
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40734
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40735
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
40736
        // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b))  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
40737
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
40738
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
40739
0
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
40740
0
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
40741
0
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
40742
0
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
40743
0
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
40744
0
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
40745
0
        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
40746
0
        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
40747
0
        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
40748
0
        GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40749
0
        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40750
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
40751
0
        GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40752
0
        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40753
0
        GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
40754
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
40755
0
        GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40756
0
        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40757
0
        GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
40758
0
        GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
40759
0
        GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
40760
0
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40761
0
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40762
0
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40763
0
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40764
0
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40765
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
40766
0
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40767
0
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40768
0
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
40769
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
40770
0
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40771
0
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40772
0
        GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
40773
0
        GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
40774
0
        GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
40775
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40776
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40777
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40778
0
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40779
0
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40780
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
40781
0
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40782
0
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40783
0
        GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
40784
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40785
0
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40786
0
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40787
0
        GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
40788
0
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
40789
0
        GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
40790
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40791
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40792
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40793
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMAfd),
40794
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40795
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
40796
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
40797
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
40798
0
        GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
40799
0
        GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40800
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40801
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40802
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40803
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
40804
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
40805
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40806
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
40807
0
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
40808
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
40809
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40810
0
        GIR_EraseFromParent, /*InsnID*/0,
40811
        // GIR_Coverage, 2729,
40812
0
        GIR_Done,
40813
      // Label 2045: @131207
40814
0
      GIM_Try, /*On fail goto*//*Label 2046*/ GIMT_Encode4(131260), // Rule ID 630 //
40815
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
40816
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40817
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40818
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40819
        // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)  =>  (VADDS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
40820
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDS),
40821
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
40822
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
40823
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
40824
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40825
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40826
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40827
0
        GIR_EraseFromParent, /*InsnID*/0,
40828
        // GIR_Coverage, 630,
40829
0
        GIR_Done,
40830
      // Label 2046: @131260
40831
0
      GIM_Try, /*On fail goto*//*Label 2047*/ GIMT_Encode4(131493), // Rule ID 2724 //
40832
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
40833
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40834
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40835
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40836
        // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VADDfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
40837
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
40838
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
40839
0
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
40840
0
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
40841
0
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
40842
0
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
40843
0
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
40844
0
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
40845
0
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40846
0
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40847
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
40848
0
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40849
0
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40850
0
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
40851
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
40852
0
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40853
0
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40854
0
        GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
40855
0
        GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
40856
0
        GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
40857
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40858
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40859
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40860
0
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40861
0
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40862
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
40863
0
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40864
0
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40865
0
        GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
40866
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40867
0
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40868
0
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40869
0
        GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
40870
0
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
40871
0
        GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
40872
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40873
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40874
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40875
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VADDfd),
40876
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40877
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
40878
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
40879
0
        GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
40880
0
        GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40881
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40882
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40883
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40884
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
40885
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
40886
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40887
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
40888
0
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
40889
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
40890
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40891
0
        GIR_EraseFromParent, /*InsnID*/0,
40892
        // GIR_Coverage, 2724,
40893
0
        GIR_Done,
40894
      // Label 2047: @131493
40895
0
      GIM_Reject,
40896
    // Label 2041: @131494
40897
0
    GIM_Reject,
40898
    // Label 2034: @131495
40899
0
    GIM_Try, /*On fail goto*//*Label 2048*/ GIMT_Encode4(131556), // Rule ID 629 //
40900
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
40901
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
40902
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
40903
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40904
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40905
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40906
      // (fadd:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)  =>  (VADDD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
40907
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDD),
40908
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
40909
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
40910
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
40911
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40912
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40913
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40914
0
      GIR_EraseFromParent, /*InsnID*/0,
40915
      // GIR_Coverage, 629,
40916
0
      GIR_Done,
40917
    // Label 2048: @131556
40918
0
    GIM_Reject,
40919
    // Label 2035: @131557
40920
0
    GIM_Try, /*On fail goto*//*Label 2049*/ GIMT_Encode4(131618), // Rule ID 781 //
40921
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40922
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
40923
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
40924
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40925
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40926
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40927
      // (fadd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VADDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
40928
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDfd),
40929
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
40930
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40931
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40932
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40933
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40934
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40935
0
      GIR_EraseFromParent, /*InsnID*/0,
40936
      // GIR_Coverage, 781,
40937
0
      GIR_Done,
40938
    // Label 2049: @131618
40939
0
    GIM_Reject,
40940
    // Label 2036: @131619
40941
0
    GIM_Try, /*On fail goto*//*Label 2050*/ GIMT_Encode4(131836),
40942
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
40943
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
40944
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40945
0
      GIM_Try, /*On fail goto*//*Label 2051*/ GIMT_Encode4(131712), // Rule ID 5710 //
40946
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC),
40947
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40948
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
40949
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
40950
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
40951
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40952
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40953
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40954
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
40955
        // (fadd:{ *:[v4f16] } (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm), DPR:{ *:[v4f16] }:$src1)  =>  (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
40956
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFMAhd),
40957
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
40958
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
40959
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
40960
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
40961
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40962
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40963
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40964
0
        GIR_EraseFromParent, /*InsnID*/0,
40965
        // GIR_Coverage, 5710,
40966
0
        GIR_Done,
40967
      // Label 2051: @131712
40968
0
      GIM_Try, /*On fail goto*//*Label 2052*/ GIMT_Encode4(131787), // Rule ID 962 //
40969
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC),
40970
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40971
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40972
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
40973
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
40974
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
40975
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40976
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40977
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
40978
        // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm))  =>  (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
40979
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFMAhd),
40980
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
40981
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
40982
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
40983
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
40984
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40985
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40986
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40987
0
        GIR_EraseFromParent, /*InsnID*/0,
40988
        // GIR_Coverage, 962,
40989
0
        GIR_Done,
40990
      // Label 2052: @131787
40991
0
      GIM_Try, /*On fail goto*//*Label 2053*/ GIMT_Encode4(131835), // Rule ID 783 //
40992
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
40993
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40994
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40995
        // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VADDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
40996
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDhd),
40997
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
40998
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40999
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41000
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41001
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41002
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41003
0
        GIR_EraseFromParent, /*InsnID*/0,
41004
        // GIR_Coverage, 783,
41005
0
        GIR_Done,
41006
      // Label 2053: @131835
41007
0
      GIM_Reject,
41008
    // Label 2050: @131836
41009
0
    GIM_Reject,
41010
    // Label 2037: @131837
41011
0
    GIM_Try, /*On fail goto*//*Label 2054*/ GIMT_Encode4(131976),
41012
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
41013
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
41014
0
      GIM_Try, /*On fail goto*//*Label 2055*/ GIMT_Encode4(131903), // Rule ID 782 //
41015
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
41016
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41017
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41018
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41019
        // (fadd:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VADDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
41020
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDfq),
41021
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
41022
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
41023
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41024
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41025
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41026
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41027
0
        GIR_EraseFromParent, /*InsnID*/0,
41028
        // GIR_Coverage, 782,
41029
0
        GIR_Done,
41030
      // Label 2055: @131903
41031
0
      GIM_Try, /*On fail goto*//*Label 2056*/ GIMT_Encode4(131975), // Rule ID 4140 //
41032
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
41033
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41034
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41035
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41036
        // (fadd:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)  =>  (MVE_VADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
41037
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
41038
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41039
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
41040
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf32),
41041
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
41042
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
41043
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
41044
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41045
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41046
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41047
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41048
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41049
0
        GIR_EraseFromParent, /*InsnID*/0,
41050
        // GIR_Coverage, 4140,
41051
0
        GIR_Done,
41052
      // Label 2056: @131975
41053
0
      GIM_Reject,
41054
    // Label 2054: @131976
41055
0
    GIM_Reject,
41056
    // Label 2038: @131977
41057
0
    GIM_Try, /*On fail goto*//*Label 2057*/ GIMT_Encode4(132276),
41058
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
41059
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
41060
0
      GIM_Try, /*On fail goto*//*Label 2058*/ GIMT_Encode4(132070), // Rule ID 5711 //
41061
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC),
41062
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41063
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41064
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41065
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
41066
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
41067
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41068
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41069
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41070
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
41071
        // (fadd:{ *:[v8f16] } (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm), QPR:{ *:[v8f16] }:$src1)  =>  (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
41072
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFMAhq),
41073
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
41074
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
41075
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41076
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41077
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41078
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41079
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41080
0
        GIR_EraseFromParent, /*InsnID*/0,
41081
        // GIR_Coverage, 5711,
41082
0
        GIR_Done,
41083
      // Label 2058: @132070
41084
0
      GIM_Try, /*On fail goto*//*Label 2059*/ GIMT_Encode4(132150), // Rule ID 963 //
41085
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC),
41086
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41087
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41088
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41089
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41090
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
41091
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
41092
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41093
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41094
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
41095
        // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm))  =>  (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
41096
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFMAhq),
41097
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
41098
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
41099
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41100
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41101
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41102
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41103
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41104
0
        GIR_EraseFromParent, /*InsnID*/0,
41105
        // GIR_Coverage, 963,
41106
0
        GIR_Done,
41107
      // Label 2059: @132150
41108
0
      GIM_Try, /*On fail goto*//*Label 2060*/ GIMT_Encode4(132203), // Rule ID 784 //
41109
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
41110
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41111
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41112
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41113
        // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VADDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
41114
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VADDhq),
41115
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
41116
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
41117
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41118
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41119
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41120
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41121
0
        GIR_EraseFromParent, /*InsnID*/0,
41122
        // GIR_Coverage, 784,
41123
0
        GIR_Done,
41124
      // Label 2060: @132203
41125
0
      GIM_Try, /*On fail goto*//*Label 2061*/ GIMT_Encode4(132275), // Rule ID 4144 //
41126
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
41127
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41128
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41129
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41130
        // (fadd:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)  =>  (MVE_VADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
41131
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
41132
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41133
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
41134
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf16),
41135
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
41136
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
41137
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
41138
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41139
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41140
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41141
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41142
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41143
0
        GIR_EraseFromParent, /*InsnID*/0,
41144
        // GIR_Coverage, 4144,
41145
0
        GIR_Done,
41146
      // Label 2061: @132275
41147
0
      GIM_Reject,
41148
    // Label 2057: @132276
41149
0
    GIM_Reject,
41150
    // Label 2039: @132277
41151
0
    GIM_Reject,
41152
    // Label 33: @132278
41153
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2069*/ GIMT_Encode4(134130),
41154
0
    /*GILLT_s16*//*Label 2062*/ GIMT_Encode4(132341),
41155
0
    /*GILLT_s32*//*Label 2063*/ GIMT_Encode4(132403),
41156
0
    /*GILLT_s64*//*Label 2064*/ GIMT_Encode4(133358), GIMT_Encode4(0),
41157
0
    /*GILLT_v2s32*//*Label 2065*/ GIMT_Encode4(133420), GIMT_Encode4(0), GIMT_Encode4(0),
41158
0
    /*GILLT_v4s16*//*Label 2066*/ GIMT_Encode4(133482),
41159
0
    /*GILLT_v4s32*//*Label 2067*/ GIMT_Encode4(133690), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
41160
0
    /*GILLT_v8s16*//*Label 2068*/ GIMT_Encode4(133830),
41161
    // Label 2062: @132341
41162
0
    GIM_Try, /*On fail goto*//*Label 2070*/ GIMT_Encode4(132402), // Rule ID 634 //
41163
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
41164
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
41165
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
41166
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41167
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41168
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41169
      // (fsub:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)  =>  (VSUBH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
41170
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBH),
41171
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
41172
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
41173
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
41174
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41175
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41176
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41177
0
      GIR_EraseFromParent, /*InsnID*/0,
41178
      // GIR_Coverage, 634,
41179
0
      GIR_Done,
41180
    // Label 2070: @132402
41181
0
    GIM_Reject,
41182
    // Label 2063: @132403
41183
0
    GIM_Try, /*On fail goto*//*Label 2071*/ GIMT_Encode4(133357),
41184
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
41185
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
41186
0
      GIM_Try, /*On fail goto*//*Label 2072*/ GIMT_Encode4(132743), // Rule ID 2728 //
41187
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP),
41188
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41189
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41190
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41191
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41192
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41193
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41194
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41195
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41196
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
41197
        // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b))  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
41198
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41199
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
41200
0
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41201
0
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
41202
0
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
41203
0
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
41204
0
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
41205
0
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
41206
0
        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
41207
0
        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
41208
0
        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
41209
0
        GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41210
0
        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41211
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
41212
0
        GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41213
0
        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41214
0
        GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
41215
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
41216
0
        GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41217
0
        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41218
0
        GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
41219
0
        GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
41220
0
        GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
41221
0
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41222
0
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41223
0
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41224
0
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41225
0
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41226
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
41227
0
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41228
0
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41229
0
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
41230
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
41231
0
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41232
0
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41233
0
        GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
41234
0
        GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
41235
0
        GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
41236
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41237
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41238
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41239
0
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41240
0
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41241
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
41242
0
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41243
0
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41244
0
        GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
41245
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41246
0
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41247
0
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41248
0
        GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
41249
0
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
41250
0
        GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
41251
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41252
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41253
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41254
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLSfd),
41255
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41256
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
41257
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
41258
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
41259
0
        GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
41260
0
        GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41261
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41262
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41263
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41264
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41265
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41266
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41267
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
41268
0
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
41269
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41270
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41271
0
        GIR_EraseFromParent, /*InsnID*/0,
41272
        // GIR_Coverage, 2728,
41273
0
        GIR_Done,
41274
      // Label 2072: @132743
41275
0
      GIM_Try, /*On fail goto*//*Label 2073*/ GIMT_Encode4(133070), // Rule ID 2730 //
41276
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP),
41277
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41278
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41279
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41280
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41281
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41282
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41283
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41284
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41285
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
41286
        // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b))  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
41287
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41288
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
41289
0
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41290
0
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
41291
0
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
41292
0
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
41293
0
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
41294
0
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
41295
0
        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
41296
0
        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
41297
0
        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
41298
0
        GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41299
0
        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41300
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
41301
0
        GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41302
0
        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41303
0
        GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
41304
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
41305
0
        GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41306
0
        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41307
0
        GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
41308
0
        GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
41309
0
        GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
41310
0
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41311
0
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41312
0
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41313
0
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41314
0
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41315
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
41316
0
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41317
0
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41318
0
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
41319
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
41320
0
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41321
0
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41322
0
        GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
41323
0
        GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
41324
0
        GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
41325
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41326
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41327
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41328
0
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41329
0
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41330
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
41331
0
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41332
0
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41333
0
        GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
41334
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41335
0
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41336
0
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41337
0
        GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
41338
0
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
41339
0
        GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
41340
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41341
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41342
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41343
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMSfd),
41344
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41345
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
41346
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
41347
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
41348
0
        GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
41349
0
        GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41350
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41351
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41352
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41353
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41354
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41355
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41356
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
41357
0
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
41358
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41359
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41360
0
        GIR_EraseFromParent, /*InsnID*/0,
41361
        // GIR_Coverage, 2730,
41362
0
        GIR_Done,
41363
      // Label 2073: @133070
41364
0
      GIM_Try, /*On fail goto*//*Label 2074*/ GIMT_Encode4(133123), // Rule ID 633 //
41365
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
41366
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41367
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41368
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41369
        // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)  =>  (VSUBS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
41370
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBS),
41371
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
41372
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
41373
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
41374
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41375
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41376
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41377
0
        GIR_EraseFromParent, /*InsnID*/0,
41378
        // GIR_Coverage, 633,
41379
0
        GIR_Done,
41380
      // Label 2074: @133123
41381
0
      GIM_Try, /*On fail goto*//*Label 2075*/ GIMT_Encode4(133356), // Rule ID 2725 //
41382
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
41383
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41384
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41385
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41386
        // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VSUBfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
41387
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41388
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
41389
0
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41390
0
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
41391
0
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
41392
0
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
41393
0
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
41394
0
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
41395
0
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41396
0
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41397
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
41398
0
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41399
0
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41400
0
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
41401
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
41402
0
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41403
0
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41404
0
        GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
41405
0
        GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
41406
0
        GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
41407
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41408
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41409
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41410
0
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41411
0
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41412
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
41413
0
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41414
0
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41415
0
        GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
41416
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41417
0
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41418
0
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41419
0
        GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
41420
0
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
41421
0
        GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
41422
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41423
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41424
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41425
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VSUBfd),
41426
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41427
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
41428
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
41429
0
        GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
41430
0
        GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41431
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41432
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41433
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41434
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41435
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41436
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41437
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
41438
0
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
41439
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41440
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41441
0
        GIR_EraseFromParent, /*InsnID*/0,
41442
        // GIR_Coverage, 2725,
41443
0
        GIR_Done,
41444
      // Label 2075: @133356
41445
0
      GIM_Reject,
41446
    // Label 2071: @133357
41447
0
    GIM_Reject,
41448
    // Label 2064: @133358
41449
0
    GIM_Try, /*On fail goto*//*Label 2076*/ GIMT_Encode4(133419), // Rule ID 632 //
41450
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
41451
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
41452
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
41453
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41454
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41455
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41456
      // (fsub:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)  =>  (VSUBD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
41457
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBD),
41458
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
41459
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
41460
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
41461
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41462
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41463
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41464
0
      GIR_EraseFromParent, /*InsnID*/0,
41465
      // GIR_Coverage, 632,
41466
0
      GIR_Done,
41467
    // Label 2076: @133419
41468
0
    GIM_Reject,
41469
    // Label 2065: @133420
41470
0
    GIM_Try, /*On fail goto*//*Label 2077*/ GIMT_Encode4(133481), // Rule ID 985 //
41471
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
41472
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
41473
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
41474
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41475
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41476
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41477
      // (fsub:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VSUBfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
41478
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBfd),
41479
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
41480
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
41481
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41482
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41483
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41484
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41485
0
      GIR_EraseFromParent, /*InsnID*/0,
41486
      // GIR_Coverage, 985,
41487
0
      GIR_Done,
41488
    // Label 2077: @133481
41489
0
    GIM_Reject,
41490
    // Label 2066: @133482
41491
0
    GIM_Try, /*On fail goto*//*Label 2078*/ GIMT_Encode4(133689),
41492
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
41493
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
41494
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41495
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41496
0
      GIM_Try, /*On fail goto*//*Label 2079*/ GIMT_Encode4(133575), // Rule ID 940 //
41497
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFPVMLx),
41498
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41499
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41500
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
41501
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
41502
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41503
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41504
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
41505
        // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm))  =>  (VMLShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
41506
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMLShd),
41507
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
41508
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
41509
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41510
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41511
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41512
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41513
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41514
0
        GIR_EraseFromParent, /*InsnID*/0,
41515
        // GIR_Coverage, 940,
41516
0
        GIR_Done,
41517
      // Label 2079: @133575
41518
0
      GIM_Try, /*On fail goto*//*Label 2080*/ GIMT_Encode4(133645), // Rule ID 966 //
41519
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC),
41520
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41521
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41522
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
41523
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
41524
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41525
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41526
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
41527
        // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm))  =>  (VFMShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
41528
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFMShd),
41529
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
41530
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
41531
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41532
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41533
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41534
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41535
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41536
0
        GIR_EraseFromParent, /*InsnID*/0,
41537
        // GIR_Coverage, 966,
41538
0
        GIR_Done,
41539
      // Label 2080: @133645
41540
0
      GIM_Try, /*On fail goto*//*Label 2081*/ GIMT_Encode4(133688), // Rule ID 987 //
41541
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
41542
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41543
        // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VSUBhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
41544
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBhd),
41545
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
41546
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
41547
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41548
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41549
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41550
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41551
0
        GIR_EraseFromParent, /*InsnID*/0,
41552
        // GIR_Coverage, 987,
41553
0
        GIR_Done,
41554
      // Label 2081: @133688
41555
0
      GIM_Reject,
41556
    // Label 2078: @133689
41557
0
    GIM_Reject,
41558
    // Label 2067: @133690
41559
0
    GIM_Try, /*On fail goto*//*Label 2082*/ GIMT_Encode4(133829),
41560
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
41561
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
41562
0
      GIM_Try, /*On fail goto*//*Label 2083*/ GIMT_Encode4(133756), // Rule ID 986 //
41563
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
41564
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41565
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41566
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41567
        // (fsub:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VSUBfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
41568
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBfq),
41569
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
41570
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
41571
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41572
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41573
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41574
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41575
0
        GIR_EraseFromParent, /*InsnID*/0,
41576
        // GIR_Coverage, 986,
41577
0
        GIR_Done,
41578
      // Label 2083: @133756
41579
0
      GIM_Try, /*On fail goto*//*Label 2084*/ GIMT_Encode4(133828), // Rule ID 4148 //
41580
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
41581
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41582
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41583
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41584
        // (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)  =>  (MVE_VSUBf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
41585
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
41586
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41587
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
41588
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf32),
41589
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
41590
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
41591
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
41592
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41593
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41594
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41595
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41596
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41597
0
        GIR_EraseFromParent, /*InsnID*/0,
41598
        // GIR_Coverage, 4148,
41599
0
        GIR_Done,
41600
      // Label 2084: @133828
41601
0
      GIM_Reject,
41602
    // Label 2082: @133829
41603
0
    GIM_Reject,
41604
    // Label 2068: @133830
41605
0
    GIM_Try, /*On fail goto*//*Label 2085*/ GIMT_Encode4(134129),
41606
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
41607
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
41608
0
      GIM_Try, /*On fail goto*//*Label 2086*/ GIMT_Encode4(133923), // Rule ID 941 //
41609
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFPVMLx),
41610
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41611
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41612
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41613
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41614
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
41615
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
41616
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41617
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41618
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
41619
        // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm))  =>  (VMLShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
41620
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMLShq),
41621
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
41622
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
41623
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41624
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41625
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41626
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41627
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41628
0
        GIR_EraseFromParent, /*InsnID*/0,
41629
        // GIR_Coverage, 941,
41630
0
        GIR_Done,
41631
      // Label 2086: @133923
41632
0
      GIM_Try, /*On fail goto*//*Label 2087*/ GIMT_Encode4(134003), // Rule ID 967 //
41633
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC),
41634
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41635
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41636
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41637
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41638
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
41639
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
41640
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41641
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41642
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
41643
        // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm))  =>  (VFMShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
41644
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFMShq),
41645
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
41646
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
41647
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41648
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41649
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41650
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41651
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41652
0
        GIR_EraseFromParent, /*InsnID*/0,
41653
        // GIR_Coverage, 967,
41654
0
        GIR_Done,
41655
      // Label 2087: @134003
41656
0
      GIM_Try, /*On fail goto*//*Label 2088*/ GIMT_Encode4(134056), // Rule ID 988 //
41657
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
41658
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41659
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41660
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41661
        // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VSUBhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
41662
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSUBhq),
41663
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
41664
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
41665
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41666
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41667
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41668
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41669
0
        GIR_EraseFromParent, /*InsnID*/0,
41670
        // GIR_Coverage, 988,
41671
0
        GIR_Done,
41672
      // Label 2088: @134056
41673
0
      GIM_Try, /*On fail goto*//*Label 2089*/ GIMT_Encode4(134128), // Rule ID 4152 //
41674
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
41675
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41676
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41677
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41678
        // (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)  =>  (MVE_VSUBf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
41679
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
41680
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41681
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
41682
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf16),
41683
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
41684
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
41685
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
41686
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41687
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41688
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41689
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41690
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41691
0
        GIR_EraseFromParent, /*InsnID*/0,
41692
        // GIR_Coverage, 4152,
41693
0
        GIR_Done,
41694
      // Label 2089: @134128
41695
0
      GIM_Reject,
41696
    // Label 2085: @134129
41697
0
    GIM_Reject,
41698
    // Label 2069: @134130
41699
0
    GIM_Reject,
41700
    // Label 34: @134131
41701
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2097*/ GIMT_Encode4(135287),
41702
0
    /*GILLT_s16*//*Label 2090*/ GIMT_Encode4(134194),
41703
0
    /*GILLT_s32*//*Label 2091*/ GIMT_Encode4(134256),
41704
0
    /*GILLT_s64*//*Label 2092*/ GIMT_Encode4(134691), GIMT_Encode4(0),
41705
0
    /*GILLT_v2s32*//*Label 2093*/ GIMT_Encode4(134883), GIMT_Encode4(0), GIMT_Encode4(0),
41706
0
    /*GILLT_v4s16*//*Label 2094*/ GIMT_Encode4(134945),
41707
0
    /*GILLT_v4s32*//*Label 2095*/ GIMT_Encode4(135007), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
41708
0
    /*GILLT_v8s16*//*Label 2096*/ GIMT_Encode4(135147),
41709
    // Label 2090: @134194
41710
0
    GIM_Try, /*On fail goto*//*Label 2098*/ GIMT_Encode4(134255), // Rule ID 640 //
41711
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
41712
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
41713
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
41714
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41715
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41716
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41717
      // (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)  =>  (VMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
41718
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMULH),
41719
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
41720
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
41721
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
41722
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41723
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41724
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41725
0
      GIR_EraseFromParent, /*InsnID*/0,
41726
      // GIR_Coverage, 640,
41727
0
      GIR_Done,
41728
    // Label 2098: @134255
41729
0
    GIM_Reject,
41730
    // Label 2091: @134256
41731
0
    GIM_Try, /*On fail goto*//*Label 2099*/ GIMT_Encode4(134690),
41732
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
41733
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
41734
0
      GIM_Try, /*On fail goto*//*Label 2100*/ GIMT_Encode4(134336), // Rule ID 2307 //
41735
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NoHonorSignDependentRounding),
41736
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41737
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41738
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
41739
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41740
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41741
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41742
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
41743
        // (fmul:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a), SPR:{ *:[f32] }:$b)  =>  (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)
41744
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VNMULS),
41745
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
41746
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
41747
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b
41748
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41749
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41750
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41751
0
        GIR_EraseFromParent, /*InsnID*/0,
41752
        // GIR_Coverage, 2307,
41753
0
        GIR_Done,
41754
      // Label 2100: @134336
41755
0
      GIM_Try, /*On fail goto*//*Label 2101*/ GIMT_Encode4(134403), // Rule ID 5837 //
41756
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NoHonorSignDependentRounding),
41757
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41758
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41759
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41760
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
41761
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41762
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41763
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
41764
        // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$b, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a))  =>  (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)
41765
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VNMULS),
41766
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
41767
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
41768
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // b
41769
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41770
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41771
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41772
0
        GIR_EraseFromParent, /*InsnID*/0,
41773
        // GIR_Coverage, 5837,
41774
0
        GIR_Done,
41775
      // Label 2101: @134403
41776
0
      GIM_Try, /*On fail goto*//*Label 2102*/ GIMT_Encode4(134456), // Rule ID 639 //
41777
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
41778
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41779
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41780
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41781
        // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)  =>  (VMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
41782
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMULS),
41783
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
41784
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
41785
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
41786
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41787
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41788
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41789
0
        GIR_EraseFromParent, /*InsnID*/0,
41790
        // GIR_Coverage, 639,
41791
0
        GIR_Done,
41792
      // Label 2102: @134456
41793
0
      GIM_Try, /*On fail goto*//*Label 2103*/ GIMT_Encode4(134689), // Rule ID 2726 //
41794
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
41795
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41796
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41797
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41798
        // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMULfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
41799
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41800
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
41801
0
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41802
0
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
41803
0
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
41804
0
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
41805
0
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
41806
0
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
41807
0
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41808
0
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41809
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
41810
0
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41811
0
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41812
0
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
41813
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
41814
0
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41815
0
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41816
0
        GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
41817
0
        GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
41818
0
        GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
41819
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41820
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41821
0
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41822
0
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41823
0
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41824
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
41825
0
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41826
0
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41827
0
        GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
41828
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41829
0
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41830
0
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41831
0
        GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
41832
0
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
41833
0
        GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
41834
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41835
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41836
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41837
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMULfd),
41838
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41839
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
41840
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
41841
0
        GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
41842
0
        GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41843
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41844
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41845
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41846
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41847
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41848
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41849
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
41850
0
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
41851
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41852
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41853
0
        GIR_EraseFromParent, /*InsnID*/0,
41854
        // GIR_Coverage, 2726,
41855
0
        GIR_Done,
41856
      // Label 2103: @134689
41857
0
      GIM_Reject,
41858
    // Label 2099: @134690
41859
0
    GIM_Reject,
41860
    // Label 2092: @134691
41861
0
    GIM_Try, /*On fail goto*//*Label 2104*/ GIMT_Encode4(134882),
41862
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
41863
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
41864
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41865
0
      GIM_Try, /*On fail goto*//*Label 2105*/ GIMT_Encode4(134771), // Rule ID 2306 //
41866
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_NoHonorSignDependentRounding),
41867
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41868
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
41869
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41870
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41871
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41872
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
41873
        // (fmul:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a), DPR:{ *:[f64] }:$b)  =>  (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b)
41874
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VNMULD),
41875
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
41876
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
41877
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b
41878
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41879
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41880
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41881
0
        GIR_EraseFromParent, /*InsnID*/0,
41882
        // GIR_Coverage, 2306,
41883
0
        GIR_Done,
41884
      // Label 2105: @134771
41885
0
      GIM_Try, /*On fail goto*//*Label 2106*/ GIMT_Encode4(134833), // Rule ID 5836 //
41886
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_NoHonorSignDependentRounding),
41887
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41888
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41889
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
41890
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41891
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41892
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
41893
        // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$b, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a))  =>  (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b)
41894
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VNMULD),
41895
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
41896
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
41897
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // b
41898
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41899
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41900
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41901
0
        GIR_EraseFromParent, /*InsnID*/0,
41902
        // GIR_Coverage, 5836,
41903
0
        GIR_Done,
41904
      // Label 2106: @134833
41905
0
      GIM_Try, /*On fail goto*//*Label 2107*/ GIMT_Encode4(134881), // Rule ID 638 //
41906
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
41907
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41908
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41909
        // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)  =>  (VMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
41910
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMULD),
41911
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
41912
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
41913
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
41914
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41915
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41916
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41917
0
        GIR_EraseFromParent, /*InsnID*/0,
41918
        // GIR_Coverage, 638,
41919
0
        GIR_Done,
41920
      // Label 2107: @134881
41921
0
      GIM_Reject,
41922
    // Label 2104: @134882
41923
0
    GIM_Reject,
41924
    // Label 2093: @134883
41925
0
    GIM_Try, /*On fail goto*//*Label 2108*/ GIMT_Encode4(134944), // Rule ID 860 //
41926
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
41927
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
41928
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
41929
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41930
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41931
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41932
      // (fmul:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VMULfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
41933
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMULfd),
41934
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
41935
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
41936
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41937
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41938
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41939
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41940
0
      GIR_EraseFromParent, /*InsnID*/0,
41941
      // GIR_Coverage, 860,
41942
0
      GIR_Done,
41943
    // Label 2108: @134944
41944
0
    GIM_Reject,
41945
    // Label 2094: @134945
41946
0
    GIM_Try, /*On fail goto*//*Label 2109*/ GIMT_Encode4(135006), // Rule ID 862 //
41947
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
41948
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
41949
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
41950
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41951
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41952
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41953
      // (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VMULhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
41954
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMULhd),
41955
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
41956
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
41957
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41958
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41959
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41960
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41961
0
      GIR_EraseFromParent, /*InsnID*/0,
41962
      // GIR_Coverage, 862,
41963
0
      GIR_Done,
41964
    // Label 2109: @135006
41965
0
    GIM_Reject,
41966
    // Label 2095: @135007
41967
0
    GIM_Try, /*On fail goto*//*Label 2110*/ GIMT_Encode4(135146),
41968
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
41969
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
41970
0
      GIM_Try, /*On fail goto*//*Label 2111*/ GIMT_Encode4(135073), // Rule ID 861 //
41971
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
41972
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41973
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41974
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41975
        // (fmul:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VMULfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
41976
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMULfq),
41977
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
41978
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
41979
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41980
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41981
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41982
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41983
0
        GIR_EraseFromParent, /*InsnID*/0,
41984
        // GIR_Coverage, 861,
41985
0
        GIR_Done,
41986
      // Label 2111: @135073
41987
0
      GIM_Try, /*On fail goto*//*Label 2112*/ GIMT_Encode4(135145), // Rule ID 4112 //
41988
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
41989
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41990
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41991
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41992
        // (fmul:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)  =>  (MVE_VMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
41993
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
41994
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41995
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
41996
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf32),
41997
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
41998
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
41999
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
42000
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42001
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42002
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42003
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42004
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42005
0
        GIR_EraseFromParent, /*InsnID*/0,
42006
        // GIR_Coverage, 4112,
42007
0
        GIR_Done,
42008
      // Label 2112: @135145
42009
0
      GIM_Reject,
42010
    // Label 2110: @135146
42011
0
    GIM_Reject,
42012
    // Label 2096: @135147
42013
0
    GIM_Try, /*On fail goto*//*Label 2113*/ GIMT_Encode4(135286),
42014
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
42015
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
42016
0
      GIM_Try, /*On fail goto*//*Label 2114*/ GIMT_Encode4(135213), // Rule ID 863 //
42017
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42018
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42019
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42020
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42021
        // (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VMULhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
42022
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMULhq),
42023
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
42024
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
42025
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
42026
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42027
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42028
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42029
0
        GIR_EraseFromParent, /*InsnID*/0,
42030
        // GIR_Coverage, 863,
42031
0
        GIR_Done,
42032
      // Label 2114: @135213
42033
0
      GIM_Try, /*On fail goto*//*Label 2115*/ GIMT_Encode4(135285), // Rule ID 4116 //
42034
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
42035
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42036
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42037
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42038
        // (fmul:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)  =>  (MVE_VMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
42039
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42040
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42041
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
42042
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf16),
42043
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
42044
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
42045
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
42046
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42047
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42048
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42049
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42050
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42051
0
        GIR_EraseFromParent, /*InsnID*/0,
42052
        // GIR_Coverage, 4116,
42053
0
        GIR_Done,
42054
      // Label 2115: @135285
42055
0
      GIM_Reject,
42056
    // Label 2113: @135286
42057
0
    GIM_Reject,
42058
    // Label 2097: @135287
42059
0
    GIM_Reject,
42060
    // Label 35: @135288
42061
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2123*/ GIMT_Encode4(137491),
42062
0
    /*GILLT_s16*//*Label 2116*/ GIMT_Encode4(135351),
42063
0
    /*GILLT_s32*//*Label 2117*/ GIMT_Encode4(135815),
42064
0
    /*GILLT_s64*//*Label 2118*/ GIMT_Encode4(136279), GIMT_Encode4(0),
42065
0
    /*GILLT_v2s32*//*Label 2119*/ GIMT_Encode4(136743), GIMT_Encode4(0), GIMT_Encode4(0),
42066
0
    /*GILLT_v4s16*//*Label 2120*/ GIMT_Encode4(136966),
42067
0
    /*GILLT_v4s32*//*Label 2121*/ GIMT_Encode4(137041), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
42068
0
    /*GILLT_v8s16*//*Label 2122*/ GIMT_Encode4(137342),
42069
    // Label 2116: @135351
42070
0
    GIM_Try, /*On fail goto*//*Label 2124*/ GIMT_Encode4(135814),
42071
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
42072
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
42073
0
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
42074
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42075
0
      GIM_Try, /*On fail goto*//*Label 2125*/ GIMT_Encode4(135458), // Rule ID 2413 //
42076
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42077
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42078
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42079
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42080
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42081
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42082
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42083
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
42084
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
42085
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42086
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42087
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
42088
        // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin))  =>  (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42089
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
42090
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
42091
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
42092
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42093
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
42094
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42095
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42096
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42097
0
        GIR_EraseFromParent, /*InsnID*/0,
42098
        // GIR_Coverage, 2413,
42099
0
        GIR_Done,
42100
      // Label 2125: @135458
42101
0
      GIM_Try, /*On fail goto*//*Label 2126*/ GIMT_Encode4(135543), // Rule ID 5845 //
42102
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42103
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42104
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42105
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42106
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42107
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42108
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42109
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
42110
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
42111
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42112
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42113
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
42114
        // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin))  =>  (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42115
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
42116
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
42117
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
42118
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42119
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
42120
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42121
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42122
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42123
0
        GIR_EraseFromParent, /*InsnID*/0,
42124
        // GIR_Coverage, 5845,
42125
0
        GIR_Done,
42126
      // Label 2126: @135543
42127
0
      GIM_Try, /*On fail goto*//*Label 2127*/ GIMT_Encode4(135614), // Rule ID 2405 //
42128
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42129
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42130
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42131
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42132
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42133
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42134
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42135
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42136
        // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)  =>  (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42137
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFMSH),
42138
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
42139
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
42140
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42141
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
42142
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42143
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42144
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42145
0
        GIR_EraseFromParent, /*InsnID*/0,
42146
        // GIR_Coverage, 2405,
42147
0
        GIR_Done,
42148
      // Label 2127: @135614
42149
0
      GIM_Try, /*On fail goto*//*Label 2128*/ GIMT_Encode4(135685), // Rule ID 5842 //
42150
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42151
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42152
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42153
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42154
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42155
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42156
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42157
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42158
        // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin)  =>  (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42159
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFMSH),
42160
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
42161
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
42162
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42163
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
42164
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42165
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42166
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42167
0
        GIR_EraseFromParent, /*InsnID*/0,
42168
        // GIR_Coverage, 5842,
42169
0
        GIR_Done,
42170
      // Label 2128: @135685
42171
0
      GIM_Try, /*On fail goto*//*Label 2129*/ GIMT_Encode4(135756), // Rule ID 2418 //
42172
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42173
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42174
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42175
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
42176
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42177
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42178
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42179
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42180
        // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin))  =>  (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42181
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
42182
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
42183
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
42184
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
42185
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
42186
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42187
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42188
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42189
0
        GIR_EraseFromParent, /*InsnID*/0,
42190
        // GIR_Coverage, 2418,
42191
0
        GIR_Done,
42192
      // Label 2129: @135756
42193
0
      GIM_Try, /*On fail goto*//*Label 2130*/ GIMT_Encode4(135813), // Rule ID 2399 //
42194
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42195
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42196
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42197
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42198
        // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)  =>  (VFMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42199
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFMAH),
42200
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
42201
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
42202
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
42203
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
42204
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42205
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42206
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42207
0
        GIR_EraseFromParent, /*InsnID*/0,
42208
        // GIR_Coverage, 2399,
42209
0
        GIR_Done,
42210
      // Label 2130: @135813
42211
0
      GIM_Reject,
42212
    // Label 2124: @135814
42213
0
    GIM_Reject,
42214
    // Label 2117: @135815
42215
0
    GIM_Try, /*On fail goto*//*Label 2131*/ GIMT_Encode4(136278),
42216
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
42217
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
42218
0
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
42219
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42220
0
      GIM_Try, /*On fail goto*//*Label 2132*/ GIMT_Encode4(135922), // Rule ID 2412 //
42221
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
42222
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42223
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42224
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42225
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42226
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42227
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42228
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
42229
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
42230
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42231
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42232
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
42233
        // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin))  =>  (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42234
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
42235
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
42236
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
42237
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42238
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
42239
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42240
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42241
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42242
0
        GIR_EraseFromParent, /*InsnID*/0,
42243
        // GIR_Coverage, 2412,
42244
0
        GIR_Done,
42245
      // Label 2132: @135922
42246
0
      GIM_Try, /*On fail goto*//*Label 2133*/ GIMT_Encode4(136007), // Rule ID 5844 //
42247
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
42248
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42249
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42250
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42251
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42252
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42253
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42254
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
42255
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
42256
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42257
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42258
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
42259
        // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin))  =>  (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42260
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
42261
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
42262
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
42263
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42264
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
42265
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42266
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42267
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42268
0
        GIR_EraseFromParent, /*InsnID*/0,
42269
        // GIR_Coverage, 5844,
42270
0
        GIR_Done,
42271
      // Label 2133: @136007
42272
0
      GIM_Try, /*On fail goto*//*Label 2134*/ GIMT_Encode4(136078), // Rule ID 2404 //
42273
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
42274
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42275
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42276
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42277
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42278
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42279
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42280
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42281
        // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)  =>  (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42282
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFMSS),
42283
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
42284
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
42285
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42286
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
42287
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42288
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42289
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42290
0
        GIR_EraseFromParent, /*InsnID*/0,
42291
        // GIR_Coverage, 2404,
42292
0
        GIR_Done,
42293
      // Label 2134: @136078
42294
0
      GIM_Try, /*On fail goto*//*Label 2135*/ GIMT_Encode4(136149), // Rule ID 5841 //
42295
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
42296
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42297
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42298
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42299
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42300
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42301
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42302
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42303
        // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin)  =>  (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42304
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFMSS),
42305
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
42306
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
42307
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42308
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
42309
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42310
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42311
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42312
0
        GIR_EraseFromParent, /*InsnID*/0,
42313
        // GIR_Coverage, 5841,
42314
0
        GIR_Done,
42315
      // Label 2135: @136149
42316
0
      GIM_Try, /*On fail goto*//*Label 2136*/ GIMT_Encode4(136220), // Rule ID 2417 //
42317
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
42318
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42319
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42320
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
42321
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42322
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42323
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42324
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42325
        // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin))  =>  (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42326
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
42327
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
42328
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
42329
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
42330
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
42331
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42332
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42333
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42334
0
        GIR_EraseFromParent, /*InsnID*/0,
42335
        // GIR_Coverage, 2417,
42336
0
        GIR_Done,
42337
      // Label 2136: @136220
42338
0
      GIM_Try, /*On fail goto*//*Label 2137*/ GIMT_Encode4(136277), // Rule ID 2398 //
42339
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
42340
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42341
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42342
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42343
        // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)  =>  (VFMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42344
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFMAS),
42345
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
42346
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
42347
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
42348
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
42349
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42350
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42351
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42352
0
        GIR_EraseFromParent, /*InsnID*/0,
42353
        // GIR_Coverage, 2398,
42354
0
        GIR_Done,
42355
      // Label 2137: @136277
42356
0
      GIM_Reject,
42357
    // Label 2131: @136278
42358
0
    GIM_Reject,
42359
    // Label 2118: @136279
42360
0
    GIM_Try, /*On fail goto*//*Label 2138*/ GIMT_Encode4(136742),
42361
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
42362
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
42363
0
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
42364
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42365
0
      GIM_Try, /*On fail goto*//*Label 2139*/ GIMT_Encode4(136386), // Rule ID 2411 //
42366
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
42367
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42368
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42369
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42370
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42371
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42372
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42373
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
42374
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
42375
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42376
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42377
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
42378
        // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin))  =>  (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42379
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
42380
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
42381
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
42382
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
42383
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
42384
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42385
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42386
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42387
0
        GIR_EraseFromParent, /*InsnID*/0,
42388
        // GIR_Coverage, 2411,
42389
0
        GIR_Done,
42390
      // Label 2139: @136386
42391
0
      GIM_Try, /*On fail goto*//*Label 2140*/ GIMT_Encode4(136471), // Rule ID 5843 //
42392
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
42393
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42394
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42395
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42396
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42397
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42398
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42399
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
42400
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
42401
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42402
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42403
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
42404
        // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin))  =>  (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42405
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
42406
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
42407
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
42408
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
42409
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
42410
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42411
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42412
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42413
0
        GIR_EraseFromParent, /*InsnID*/0,
42414
        // GIR_Coverage, 5843,
42415
0
        GIR_Done,
42416
      // Label 2140: @136471
42417
0
      GIM_Try, /*On fail goto*//*Label 2141*/ GIMT_Encode4(136542), // Rule ID 2403 //
42418
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
42419
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42420
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42421
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42422
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42423
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42424
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42425
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42426
        // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)  =>  (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42427
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFMSD),
42428
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
42429
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ddin
42430
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
42431
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
42432
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42433
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42434
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42435
0
        GIR_EraseFromParent, /*InsnID*/0,
42436
        // GIR_Coverage, 2403,
42437
0
        GIR_Done,
42438
      // Label 2141: @136542
42439
0
      GIM_Try, /*On fail goto*//*Label 2142*/ GIMT_Encode4(136613), // Rule ID 5840 //
42440
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
42441
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42442
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42443
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42444
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42445
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42446
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42447
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42448
        // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin)  =>  (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42449
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFMSD),
42450
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
42451
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ddin
42452
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
42453
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
42454
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42455
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42456
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42457
0
        GIR_EraseFromParent, /*InsnID*/0,
42458
        // GIR_Coverage, 5840,
42459
0
        GIR_Done,
42460
      // Label 2142: @136613
42461
0
      GIM_Try, /*On fail goto*//*Label 2143*/ GIMT_Encode4(136684), // Rule ID 2416 //
42462
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
42463
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42464
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42465
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
42466
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42467
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42468
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42469
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42470
        // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin))  =>  (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42471
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
42472
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
42473
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ddin
42474
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
42475
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
42476
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42477
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42478
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42479
0
        GIR_EraseFromParent, /*InsnID*/0,
42480
        // GIR_Coverage, 2416,
42481
0
        GIR_Done,
42482
      // Label 2143: @136684
42483
0
      GIM_Try, /*On fail goto*//*Label 2144*/ GIMT_Encode4(136741), // Rule ID 2397 //
42484
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
42485
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42486
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42487
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42488
        // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)  =>  (VFMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42489
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFMAD),
42490
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
42491
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ddin
42492
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
42493
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
42494
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42495
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42496
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42497
0
        GIR_EraseFromParent, /*InsnID*/0,
42498
        // GIR_Coverage, 2397,
42499
0
        GIR_Done,
42500
      // Label 2144: @136741
42501
0
      GIM_Reject,
42502
    // Label 2138: @136742
42503
0
    GIM_Reject,
42504
    // Label 2119: @136743
42505
0
    GIM_Try, /*On fail goto*//*Label 2145*/ GIMT_Encode4(136965),
42506
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
42507
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
42508
0
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
42509
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42510
0
      GIM_Try, /*On fail goto*//*Label 2146*/ GIMT_Encode4(136836), // Rule ID 2509 //
42511
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4),
42512
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42513
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42514
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
42515
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42516
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42517
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42518
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42519
        // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1)  =>  (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
42520
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFMSfd),
42521
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
42522
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
42523
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
42524
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
42525
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42526
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42527
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42528
0
        GIR_EraseFromParent, /*InsnID*/0,
42529
        // GIR_Coverage, 2509,
42530
0
        GIR_Done,
42531
      // Label 2146: @136836
42532
0
      GIM_Try, /*On fail goto*//*Label 2147*/ GIMT_Encode4(136907), // Rule ID 5883 //
42533
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4),
42534
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42535
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42536
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42537
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
42538
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42539
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42540
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42541
        // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm, (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$src1)  =>  (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
42542
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFMSfd),
42543
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
42544
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
42545
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
42546
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
42547
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42548
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42549
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42550
0
        GIR_EraseFromParent, /*InsnID*/0,
42551
        // GIR_Coverage, 5883,
42552
0
        GIR_Done,
42553
      // Label 2147: @136907
42554
0
      GIM_Try, /*On fail goto*//*Label 2148*/ GIMT_Encode4(136964), // Rule ID 2507 //
42555
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4),
42556
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42557
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42558
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42559
        // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1)  =>  (VFMAfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
42560
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFMAfd),
42561
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
42562
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
42563
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
42564
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
42565
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42566
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42567
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42568
0
        GIR_EraseFromParent, /*InsnID*/0,
42569
        // GIR_Coverage, 2507,
42570
0
        GIR_Done,
42571
      // Label 2148: @136964
42572
0
      GIM_Reject,
42573
    // Label 2145: @136965
42574
0
    GIM_Reject,
42575
    // Label 2120: @136966
42576
0
    GIM_Try, /*On fail goto*//*Label 2149*/ GIMT_Encode4(137040), // Rule ID 2505 //
42577
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42578
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
42579
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
42580
0
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
42581
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42582
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42583
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42584
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42585
      // (fma:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm, DPR:{ *:[v4f16] }:$src1)  =>  (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
42586
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFMAhd),
42587
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
42588
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
42589
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
42590
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
42591
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42592
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42593
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42594
0
      GIR_EraseFromParent, /*InsnID*/0,
42595
      // GIR_Coverage, 2505,
42596
0
      GIR_Done,
42597
    // Label 2149: @137040
42598
0
    GIM_Reject,
42599
    // Label 2121: @137041
42600
0
    GIM_Try, /*On fail goto*//*Label 2150*/ GIMT_Encode4(137341),
42601
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
42602
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
42603
0
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
42604
0
      GIM_Try, /*On fail goto*//*Label 2151*/ GIMT_Encode4(137134), // Rule ID 2510 //
42605
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4),
42606
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42607
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42608
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42609
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
42610
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42611
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42612
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42613
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42614
        // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1)  =>  (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
42615
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFMSfq),
42616
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
42617
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
42618
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
42619
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
42620
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42621
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42622
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42623
0
        GIR_EraseFromParent, /*InsnID*/0,
42624
        // GIR_Coverage, 2510,
42625
0
        GIR_Done,
42626
      // Label 2151: @137134
42627
0
      GIM_Try, /*On fail goto*//*Label 2152*/ GIMT_Encode4(137210), // Rule ID 5884 //
42628
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4),
42629
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42630
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42631
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42632
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42633
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
42634
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42635
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42636
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42637
        // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm, (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$src1)  =>  (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
42638
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFMSfq),
42639
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
42640
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
42641
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
42642
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
42643
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42644
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42645
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42646
0
        GIR_EraseFromParent, /*InsnID*/0,
42647
        // GIR_Coverage, 5884,
42648
0
        GIR_Done,
42649
      // Label 2152: @137210
42650
0
      GIM_Try, /*On fail goto*//*Label 2153*/ GIMT_Encode4(137272), // Rule ID 2508 //
42651
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4),
42652
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42653
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42654
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42655
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42656
        // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1)  =>  (VFMAfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
42657
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFMAfq),
42658
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
42659
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
42660
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
42661
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
42662
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42663
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42664
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42665
0
        GIR_EraseFromParent, /*InsnID*/0,
42666
        // GIR_Coverage, 2508,
42667
0
        GIR_Done,
42668
      // Label 2153: @137272
42669
0
      GIM_Try, /*On fail goto*//*Label 2154*/ GIMT_Encode4(137340), // Rule ID 4130 //
42670
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
42671
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42672
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42673
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42674
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42675
        // (fma:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1, MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add)  =>  (MVE_VFMAf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
42676
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf32),
42677
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
42678
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // add
42679
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // m1
42680
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // m2
42681
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42682
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42683
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42684
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42685
0
        GIR_EraseFromParent, /*InsnID*/0,
42686
        // GIR_Coverage, 4130,
42687
0
        GIR_Done,
42688
      // Label 2154: @137340
42689
0
      GIM_Reject,
42690
    // Label 2150: @137341
42691
0
    GIM_Reject,
42692
    // Label 2122: @137342
42693
0
    GIM_Try, /*On fail goto*//*Label 2155*/ GIMT_Encode4(137490),
42694
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
42695
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
42696
0
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
42697
0
      GIM_Try, /*On fail goto*//*Label 2156*/ GIMT_Encode4(137421), // Rule ID 2506 //
42698
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42699
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42700
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42701
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42702
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42703
        // (fma:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm, QPR:{ *:[v8f16] }:$src1)  =>  (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
42704
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFMAhq),
42705
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
42706
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
42707
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
42708
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
42709
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42710
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42711
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42712
0
        GIR_EraseFromParent, /*InsnID*/0,
42713
        // GIR_Coverage, 2506,
42714
0
        GIR_Done,
42715
      // Label 2156: @137421
42716
0
      GIM_Try, /*On fail goto*//*Label 2157*/ GIMT_Encode4(137489), // Rule ID 4133 //
42717
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
42718
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42719
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42720
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42721
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42722
        // (fma:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1, MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add)  =>  (MVE_VFMAf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
42723
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf16),
42724
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
42725
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // add
42726
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // m1
42727
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // m2
42728
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42729
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42730
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42731
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42732
0
        GIR_EraseFromParent, /*InsnID*/0,
42733
        // GIR_Coverage, 4133,
42734
0
        GIR_Done,
42735
      // Label 2157: @137489
42736
0
      GIM_Reject,
42737
    // Label 2155: @137490
42738
0
    GIM_Reject,
42739
    // Label 2123: @137491
42740
0
    GIM_Reject,
42741
    // Label 36: @137492
42742
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2161*/ GIMT_Encode4(137701),
42743
0
    /*GILLT_s16*//*Label 2158*/ GIMT_Encode4(137515),
42744
0
    /*GILLT_s32*//*Label 2159*/ GIMT_Encode4(137577),
42745
0
    /*GILLT_s64*//*Label 2160*/ GIMT_Encode4(137639),
42746
    // Label 2158: @137515
42747
0
    GIM_Try, /*On fail goto*//*Label 2162*/ GIMT_Encode4(137576), // Rule ID 637 //
42748
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42749
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
42750
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
42751
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42752
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42753
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42754
      // (fdiv:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)  =>  (VDIVH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42755
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VDIVH),
42756
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
42757
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
42758
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
42759
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42760
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42761
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42762
0
      GIR_EraseFromParent, /*InsnID*/0,
42763
      // GIR_Coverage, 637,
42764
0
      GIR_Done,
42765
    // Label 2162: @137576
42766
0
    GIM_Reject,
42767
    // Label 2159: @137577
42768
0
    GIM_Try, /*On fail goto*//*Label 2163*/ GIMT_Encode4(137638), // Rule ID 636 //
42769
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2),
42770
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
42771
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
42772
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42773
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42774
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42775
      // (fdiv:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)  =>  (VDIVS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42776
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VDIVS),
42777
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
42778
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
42779
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
42780
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42781
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42782
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42783
0
      GIR_EraseFromParent, /*InsnID*/0,
42784
      // GIR_Coverage, 636,
42785
0
      GIR_Done,
42786
    // Label 2163: @137638
42787
0
    GIM_Reject,
42788
    // Label 2160: @137639
42789
0
    GIM_Try, /*On fail goto*//*Label 2164*/ GIMT_Encode4(137700), // Rule ID 635 //
42790
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
42791
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
42792
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
42793
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42794
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42795
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42796
      // (fdiv:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)  =>  (VDIVD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42797
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VDIVD),
42798
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
42799
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
42800
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
42801
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42802
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42803
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42804
0
      GIR_EraseFromParent, /*InsnID*/0,
42805
      // GIR_Coverage, 635,
42806
0
      GIR_Done,
42807
    // Label 2164: @137700
42808
0
    GIM_Reject,
42809
    // Label 2161: @137701
42810
0
    GIM_Reject,
42811
    // Label 37: @137702
42812
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2172*/ GIMT_Encode4(139434),
42813
0
    /*GILLT_s16*//*Label 2165*/ GIMT_Encode4(137765),
42814
0
    /*GILLT_s32*//*Label 2166*/ GIMT_Encode4(138151),
42815
0
    /*GILLT_s64*//*Label 2167*/ GIMT_Encode4(138714), GIMT_Encode4(0),
42816
0
    /*GILLT_v2s32*//*Label 2168*/ GIMT_Encode4(139100), GIMT_Encode4(0), GIMT_Encode4(0),
42817
0
    /*GILLT_v4s16*//*Label 2169*/ GIMT_Encode4(139149),
42818
0
    /*GILLT_v4s32*//*Label 2170*/ GIMT_Encode4(139198), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
42819
0
    /*GILLT_v8s16*//*Label 2171*/ GIMT_Encode4(139316),
42820
    // Label 2165: @137765
42821
0
    GIM_Try, /*On fail goto*//*Label 2173*/ GIMT_Encode4(138150),
42822
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
42823
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42824
0
      GIM_Try, /*On fail goto*//*Label 2174*/ GIMT_Encode4(137872), // Rule ID 2421 //
42825
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42826
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42827
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
42828
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42829
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
42830
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
42831
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
42832
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
42833
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
42834
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42835
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42836
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42837
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42838
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
42839
        // (fneg:{ *:[f16] } (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin))  =>  (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42840
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
42841
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
42842
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
42843
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
42844
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
42845
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42846
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42847
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42848
0
        GIR_EraseFromParent, /*InsnID*/0,
42849
        // GIR_Coverage, 2421,
42850
0
        GIR_Done,
42851
      // Label 2174: @137872
42852
0
      GIM_Try, /*On fail goto*//*Label 2175*/ GIMT_Encode4(137965), // Rule ID 5848 //
42853
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42854
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42855
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
42856
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42857
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
42858
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
42859
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42860
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
42861
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
42862
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
42863
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42864
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42865
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42866
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
42867
        // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin))  =>  (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42868
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
42869
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
42870
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
42871
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
42872
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
42873
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42874
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42875
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42876
0
        GIR_EraseFromParent, /*InsnID*/0,
42877
        // GIR_Coverage, 5848,
42878
0
        GIR_Done,
42879
      // Label 2175: @137965
42880
0
      GIM_Try, /*On fail goto*//*Label 2176*/ GIMT_Encode4(138044), // Rule ID 2410 //
42881
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42882
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42883
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
42884
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42885
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
42886
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
42887
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42888
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42889
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42890
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42891
        // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin))  =>  (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42892
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
42893
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
42894
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
42895
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42896
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
42897
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42898
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42899
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42900
0
        GIR_EraseFromParent, /*InsnID*/0,
42901
        // GIR_Coverage, 2410,
42902
0
        GIR_Done,
42903
      // Label 2176: @138044
42904
0
      GIM_Try, /*On fail goto*//*Label 2177*/ GIMT_Encode4(138110), // Rule ID 643 //
42905
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42906
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42907
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
42908
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42909
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
42910
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42911
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42912
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42913
        // (fneg:{ *:[f16] } (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm))  =>  (VNMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42914
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VNMULH),
42915
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
42916
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42917
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
42918
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42919
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42920
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42921
0
        GIR_EraseFromParent, /*InsnID*/0,
42922
        // GIR_Coverage, 643,
42923
0
        GIR_Done,
42924
      // Label 2177: @138110
42925
0
      GIM_Try, /*On fail goto*//*Label 2178*/ GIMT_Encode4(138149), // Rule ID 681 //
42926
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42927
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42928
        // (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VNEGH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
42929
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VNEGH),
42930
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
42931
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
42932
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42933
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42934
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42935
0
        GIR_EraseFromParent, /*InsnID*/0,
42936
        // GIR_Coverage, 681,
42937
0
        GIR_Done,
42938
      // Label 2178: @138149
42939
0
      GIM_Reject,
42940
    // Label 2173: @138150
42941
0
    GIM_Reject,
42942
    // Label 2166: @138151
42943
0
    GIM_Try, /*On fail goto*//*Label 2179*/ GIMT_Encode4(138713),
42944
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
42945
0
      GIM_Try, /*On fail goto*//*Label 2180*/ GIMT_Encode4(138258), // Rule ID 2420 //
42946
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
42947
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42948
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42949
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
42950
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42951
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
42952
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
42953
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
42954
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
42955
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
42956
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42957
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42958
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42959
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42960
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
42961
        // (fneg:{ *:[f32] } (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin))  =>  (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42962
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
42963
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
42964
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
42965
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
42966
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
42967
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42968
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42969
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42970
0
        GIR_EraseFromParent, /*InsnID*/0,
42971
        // GIR_Coverage, 2420,
42972
0
        GIR_Done,
42973
      // Label 2180: @138258
42974
0
      GIM_Try, /*On fail goto*//*Label 2181*/ GIMT_Encode4(138356), // Rule ID 5847 //
42975
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
42976
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42977
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42978
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
42979
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42980
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
42981
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
42982
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42983
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
42984
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
42985
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
42986
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42987
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42988
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
42989
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
42990
        // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin))  =>  (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42991
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
42992
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
42993
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
42994
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
42995
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
42996
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42997
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42998
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42999
0
        GIR_EraseFromParent, /*InsnID*/0,
43000
        // GIR_Coverage, 5847,
43001
0
        GIR_Done,
43002
      // Label 2181: @138356
43003
0
      GIM_Try, /*On fail goto*//*Label 2182*/ GIMT_Encode4(138440), // Rule ID 2409 //
43004
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
43005
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43006
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43007
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
43008
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43009
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43010
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
43011
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43012
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43013
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43014
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
43015
        // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin))  =>  (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43016
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
43017
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
43018
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43019
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
43020
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43021
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43022
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43023
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43024
0
        GIR_EraseFromParent, /*InsnID*/0,
43025
        // GIR_Coverage, 2409,
43026
0
        GIR_Done,
43027
      // Label 2182: @138440
43028
0
      GIM_Try, /*On fail goto*//*Label 2183*/ GIMT_Encode4(138511), // Rule ID 642 //
43029
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2),
43030
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43031
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43032
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
43033
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43034
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43035
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43036
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43037
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
43038
        // (fneg:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm))  =>  (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43039
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VNMULS),
43040
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
43041
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
43042
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43043
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43044
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43045
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43046
0
        GIR_EraseFromParent, /*InsnID*/0,
43047
        // GIR_Coverage, 642,
43048
0
        GIR_Done,
43049
      // Label 2183: @138511
43050
0
      GIM_Try, /*On fail goto*//*Label 2184*/ GIMT_Encode4(138555), // Rule ID 680 //
43051
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
43052
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43053
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43054
        // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VNEGS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
43055
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VNEGS),
43056
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
43057
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
43058
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43059
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43060
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43061
0
        GIR_EraseFromParent, /*InsnID*/0,
43062
        // GIR_Coverage, 680,
43063
0
        GIR_Done,
43064
      // Label 2184: @138555
43065
0
      GIM_Try, /*On fail goto*//*Label 2185*/ GIMT_Encode4(138712), // Rule ID 2732 //
43066
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
43067
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43068
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43069
        // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a)  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VNEGfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
43070
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
43071
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
43072
0
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
43073
0
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
43074
0
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
43075
0
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43076
0
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43077
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
43078
0
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43079
0
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43080
0
        GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
43081
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
43082
0
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
43083
0
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43084
0
        GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
43085
0
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
43086
0
        GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
43087
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43088
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43089
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
43090
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VNEGfd),
43091
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43092
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
43093
0
        GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
43094
0
        GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43095
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43096
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43097
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43098
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
43099
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43100
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43101
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
43102
0
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
43103
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
43104
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43105
0
        GIR_EraseFromParent, /*InsnID*/0,
43106
        // GIR_Coverage, 2732,
43107
0
        GIR_Done,
43108
      // Label 2185: @138712
43109
0
      GIM_Reject,
43110
    // Label 2179: @138713
43111
0
    GIM_Reject,
43112
    // Label 2167: @138714
43113
0
    GIM_Try, /*On fail goto*//*Label 2186*/ GIMT_Encode4(139099),
43114
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
43115
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43116
0
      GIM_Try, /*On fail goto*//*Label 2187*/ GIMT_Encode4(138821), // Rule ID 2419 //
43117
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
43118
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43119
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
43120
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43121
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43122
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43123
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
43124
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43125
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
43126
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43127
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43128
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43129
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
43130
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
43131
        // (fneg:{ *:[f64] } (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin))  =>  (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43132
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
43133
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
43134
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
43135
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
43136
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
43137
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43138
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43139
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43140
0
        GIR_EraseFromParent, /*InsnID*/0,
43141
        // GIR_Coverage, 2419,
43142
0
        GIR_Done,
43143
      // Label 2187: @138821
43144
0
      GIM_Try, /*On fail goto*//*Label 2188*/ GIMT_Encode4(138914), // Rule ID 5846 //
43145
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
43146
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43147
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
43148
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43149
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43150
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43151
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43152
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
43153
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43154
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
43155
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43156
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43157
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
43158
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
43159
        // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin))  =>  (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43160
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
43161
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
43162
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
43163
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
43164
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dm
43165
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43166
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43167
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43168
0
        GIR_EraseFromParent, /*InsnID*/0,
43169
        // GIR_Coverage, 5846,
43170
0
        GIR_Done,
43171
      // Label 2188: @138914
43172
0
      GIM_Try, /*On fail goto*//*Label 2189*/ GIMT_Encode4(138993), // Rule ID 2408 //
43173
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
43174
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43175
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
43176
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43177
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43178
0
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43179
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43180
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43181
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43182
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
43183
        // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin))  =>  (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43184
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
43185
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
43186
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
43187
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
43188
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
43189
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43190
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43191
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43192
0
        GIR_EraseFromParent, /*InsnID*/0,
43193
        // GIR_Coverage, 2408,
43194
0
        GIR_Done,
43195
      // Label 2189: @138993
43196
0
      GIM_Try, /*On fail goto*//*Label 2190*/ GIMT_Encode4(139059), // Rule ID 641 //
43197
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
43198
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43199
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
43200
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43201
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43202
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43203
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43204
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
43205
        // (fneg:{ *:[f64] } (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm))  =>  (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43206
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VNMULD),
43207
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
43208
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
43209
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
43210
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43211
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43212
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43213
0
        GIR_EraseFromParent, /*InsnID*/0,
43214
        // GIR_Coverage, 641,
43215
0
        GIR_Done,
43216
      // Label 2190: @139059
43217
0
      GIM_Try, /*On fail goto*//*Label 2191*/ GIMT_Encode4(139098), // Rule ID 679 //
43218
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
43219
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43220
        // (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VNEGD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
43221
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VNEGD),
43222
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
43223
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
43224
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43225
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43226
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43227
0
        GIR_EraseFromParent, /*InsnID*/0,
43228
        // GIR_Coverage, 679,
43229
0
        GIR_Done,
43230
      // Label 2191: @139098
43231
0
      GIM_Reject,
43232
    // Label 2186: @139099
43233
0
    GIM_Reject,
43234
    // Label 2168: @139100
43235
0
    GIM_Try, /*On fail goto*//*Label 2192*/ GIMT_Encode4(139148), // Rule ID 1549 //
43236
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43237
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
43238
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43239
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43240
      // (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)  =>  (VNEGfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
43241
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VNEGfd),
43242
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
43243
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43244
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43245
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43246
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43247
0
      GIR_EraseFromParent, /*InsnID*/0,
43248
      // GIR_Coverage, 1549,
43249
0
      GIR_Done,
43250
    // Label 2192: @139148
43251
0
    GIM_Reject,
43252
    // Label 2169: @139149
43253
0
    GIM_Try, /*On fail goto*//*Label 2193*/ GIMT_Encode4(139197), // Rule ID 1551 //
43254
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
43255
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
43256
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43257
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43258
      // (fneg:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)  =>  (VNEGhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
43259
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VNEGhd),
43260
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
43261
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43262
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43263
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43264
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43265
0
      GIR_EraseFromParent, /*InsnID*/0,
43266
      // GIR_Coverage, 1551,
43267
0
      GIR_Done,
43268
    // Label 2193: @139197
43269
0
    GIM_Reject,
43270
    // Label 2170: @139198
43271
0
    GIM_Try, /*On fail goto*//*Label 2194*/ GIMT_Encode4(139315),
43272
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
43273
0
      GIM_Try, /*On fail goto*//*Label 2195*/ GIMT_Encode4(139251), // Rule ID 1550 //
43274
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43275
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43276
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43277
        // (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)  =>  (VNEGf32q:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
43278
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VNEGf32q),
43279
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
43280
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43281
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43282
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43283
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43284
0
        GIR_EraseFromParent, /*InsnID*/0,
43285
        // GIR_Coverage, 1550,
43286
0
        GIR_Done,
43287
      // Label 2195: @139251
43288
0
      GIM_Try, /*On fail goto*//*Label 2196*/ GIMT_Encode4(139314), // Rule ID 4240 //
43289
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
43290
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43291
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43292
        // (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$v)  =>  (MVE_VNEGf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$v)
43293
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43294
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43295
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
43296
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VNEGf32),
43297
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
43298
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v
43299
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43300
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43301
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43302
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43303
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43304
0
        GIR_EraseFromParent, /*InsnID*/0,
43305
        // GIR_Coverage, 4240,
43306
0
        GIR_Done,
43307
      // Label 2196: @139314
43308
0
      GIM_Reject,
43309
    // Label 2194: @139315
43310
0
    GIM_Reject,
43311
    // Label 2171: @139316
43312
0
    GIM_Try, /*On fail goto*//*Label 2197*/ GIMT_Encode4(139433),
43313
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
43314
0
      GIM_Try, /*On fail goto*//*Label 2198*/ GIMT_Encode4(139369), // Rule ID 1552 //
43315
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
43316
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43317
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43318
        // (fneg:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)  =>  (VNEGhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
43319
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VNEGhq),
43320
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
43321
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43322
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43323
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43324
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43325
0
        GIR_EraseFromParent, /*InsnID*/0,
43326
        // GIR_Coverage, 1552,
43327
0
        GIR_Done,
43328
      // Label 2198: @139369
43329
0
      GIM_Try, /*On fail goto*//*Label 2199*/ GIMT_Encode4(139432), // Rule ID 4238 //
43330
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
43331
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43332
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43333
        // (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$v)  =>  (MVE_VNEGf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$v)
43334
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43335
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43336
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
43337
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VNEGf16),
43338
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
43339
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v
43340
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43341
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43342
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43343
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43344
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43345
0
        GIR_EraseFromParent, /*InsnID*/0,
43346
        // GIR_Coverage, 4238,
43347
0
        GIR_Done,
43348
      // Label 2199: @139432
43349
0
      GIM_Reject,
43350
    // Label 2197: @139433
43351
0
    GIM_Reject,
43352
    // Label 2172: @139434
43353
0
    GIM_Reject,
43354
    // Label 38: @139435
43355
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 2203*/ GIMT_Encode4(139704),
43356
0
    /*GILLT_s32*//*Label 2200*/ GIMT_Encode4(139478),
43357
0
    /*GILLT_s64*//*Label 2201*/ GIMT_Encode4(139544), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
43358
0
    /*GILLT_v4s32*//*Label 2202*/ GIMT_Encode4(139658),
43359
    // Label 2200: @139478
43360
0
    GIM_Try, /*On fail goto*//*Label 2204*/ GIMT_Encode4(139543), // Rule ID 2308 //
43361
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16),
43362
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
43363
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43364
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43365
      // (fpextend:{ *:[f32] } HPR:{ *:[f16] }:$Sm)  =>  (VCVTBHS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] }))
43366
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43367
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43368
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43369
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
43370
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43371
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTBHS),
43372
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
43373
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43374
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43375
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43376
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43377
0
      GIR_EraseFromParent, /*InsnID*/0,
43378
      // GIR_Coverage, 2308,
43379
0
      GIR_Done,
43380
    // Label 2204: @139543
43381
0
    GIM_Reject,
43382
    // Label 2201: @139544
43383
0
    GIM_Try, /*On fail goto*//*Label 2205*/ GIMT_Encode4(139592), // Rule ID 677 //
43384
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
43385
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43386
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43387
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43388
      // (fpextend:{ *:[f64] } SPR:{ *:[f32] }:$Sm)  =>  (VCVTDS:{ *:[f64] } SPR:{ *:[f32] }:$Sm)
43389
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTDS),
43390
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
43391
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
43392
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43393
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43394
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43395
0
      GIR_EraseFromParent, /*InsnID*/0,
43396
      // GIR_Coverage, 677,
43397
0
      GIR_Done,
43398
    // Label 2205: @139592
43399
0
    GIM_Try, /*On fail goto*//*Label 2206*/ GIMT_Encode4(139657), // Rule ID 2318 //
43400
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
43401
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
43402
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43403
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43404
      // (fpextend:{ *:[f64] } HPR:{ *:[f16] }:$Sm)  =>  (VCVTBHD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] }))
43405
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43406
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43407
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43408
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
43409
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43410
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTBHD),
43411
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
43412
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43413
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43414
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43415
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43416
0
      GIR_EraseFromParent, /*InsnID*/0,
43417
      // GIR_Coverage, 2318,
43418
0
      GIR_Done,
43419
    // Label 2206: @139657
43420
0
    GIM_Reject,
43421
    // Label 2202: @139658
43422
0
    GIM_Try, /*On fail goto*//*Label 2207*/ GIMT_Encode4(139703), // Rule ID 2690 //
43423
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
43424
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43425
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43426
      // (fpextend:{ *:[v4f32] } DPR:{ *:[v4f16] }:$src)  =>  (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4f16] }:$src)
43427
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTh2f),
43428
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
43429
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
43430
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43431
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43432
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43433
0
      GIR_EraseFromParent, /*InsnID*/0,
43434
      // GIR_Coverage, 2690,
43435
0
      GIR_Done,
43436
    // Label 2207: @139703
43437
0
    GIM_Reject,
43438
    // Label 2203: @139704
43439
0
    GIM_Reject,
43440
    // Label 39: @139705
43441
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 2211*/ GIMT_Encode4(140014),
43442
0
    /*GILLT_s16*//*Label 2208*/ GIMT_Encode4(139748),
43443
0
    /*GILLT_s32*//*Label 2209*/ GIMT_Encode4(139919), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
43444
0
    /*GILLT_v4s16*//*Label 2210*/ GIMT_Encode4(139968),
43445
    // Label 2208: @139748
43446
0
    GIM_Try, /*On fail goto*//*Label 2212*/ GIMT_Encode4(139833), // Rule ID 2310 //
43447
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16),
43448
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43449
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43450
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43451
      // (fpround:{ *:[f16] } SPR:{ *:[f32] }:$Sm)  =>  (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBSH:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), SPR:{ *:[f32] }:$Sm), HPR:{ *:[i32] })
43452
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43453
0
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43454
0
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43455
0
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43456
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43457
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTBSH),
43458
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43459
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
43460
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
43461
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
43462
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43463
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43464
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43465
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
43466
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43467
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
43468
0
      GIR_EraseFromParent, /*InsnID*/0,
43469
      // GIR_Coverage, 2310,
43470
0
      GIR_Done,
43471
    // Label 2212: @139833
43472
0
    GIM_Try, /*On fail goto*//*Label 2213*/ GIMT_Encode4(139918), // Rule ID 2320 //
43473
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
43474
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
43475
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43476
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43477
      // (fpround:{ *:[f16] } DPR:{ *:[f64] }:$Dm)  =>  (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBDH:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), DPR:{ *:[f64] }:$Dm), HPR:{ *:[i32] })
43478
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43479
0
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43480
0
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43481
0
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43482
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43483
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTBDH),
43484
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43485
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
43486
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dm
43487
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
43488
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43489
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43490
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43491
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
43492
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43493
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
43494
0
      GIR_EraseFromParent, /*InsnID*/0,
43495
      // GIR_Coverage, 2320,
43496
0
      GIR_Done,
43497
    // Label 2213: @139918
43498
0
    GIM_Reject,
43499
    // Label 2209: @139919
43500
0
    GIM_Try, /*On fail goto*//*Label 2214*/ GIMT_Encode4(139967), // Rule ID 678 //
43501
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
43502
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
43503
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43504
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43505
      // (fpround:{ *:[f32] } DPR:{ *:[f64] }:$Dm)  =>  (VCVTSD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
43506
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTSD),
43507
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
43508
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
43509
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43510
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43511
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43512
0
      GIR_EraseFromParent, /*InsnID*/0,
43513
      // GIR_Coverage, 678,
43514
0
      GIR_Done,
43515
    // Label 2214: @139967
43516
0
    GIM_Reject,
43517
    // Label 2210: @139968
43518
0
    GIM_Try, /*On fail goto*//*Label 2215*/ GIMT_Encode4(140013), // Rule ID 2689 //
43519
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
43520
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43521
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43522
      // (fpround:{ *:[v4f16] } QPR:{ *:[v4f32] }:$src)  =>  (VCVTf2h:{ *:[v4f16] } QPR:{ *:[v4f32] }:$src)
43523
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTf2h),
43524
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
43525
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
43526
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43527
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43528
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43529
0
      GIR_EraseFromParent, /*InsnID*/0,
43530
      // GIR_Coverage, 2689,
43531
0
      GIR_Done,
43532
    // Label 2215: @140013
43533
0
    GIM_Reject,
43534
    // Label 2211: @140014
43535
0
    GIM_Reject,
43536
    // Label 40: @140015
43537
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 2223*/ GIMT_Encode4(141525),
43538
0
    /*GILLT_s32*//*Label 2216*/ GIMT_Encode4(140074), GIMT_Encode4(0), GIMT_Encode4(0),
43539
0
    /*GILLT_v2s32*//*Label 2217*/ GIMT_Encode4(141063), GIMT_Encode4(0),
43540
0
    /*GILLT_v4s1*//*Label 2218*/ GIMT_Encode4(141112),
43541
0
    /*GILLT_v4s16*//*Label 2219*/ GIMT_Encode4(141176),
43542
0
    /*GILLT_v4s32*//*Label 2220*/ GIMT_Encode4(141225), GIMT_Encode4(0),
43543
0
    /*GILLT_v8s1*//*Label 2221*/ GIMT_Encode4(141343), GIMT_Encode4(0),
43544
0
    /*GILLT_v8s16*//*Label 2222*/ GIMT_Encode4(141407),
43545
    // Label 2216: @140074
43546
0
    GIM_Try, /*On fail goto*//*Label 2224*/ GIMT_Encode4(140147), // Rule ID 2328 //
43547
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
43548
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
43549
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
43550
0
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43551
0
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
43552
0
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
43553
0
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43554
0
      GIM_CheckIsSafeToFold, /*InsnID*/1,
43555
      // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
43556
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43557
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSH),
43558
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43559
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
43560
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43561
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43562
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
43563
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43564
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
43565
0
      GIR_EraseFromParent, /*InsnID*/0,
43566
      // GIR_Coverage, 2328,
43567
0
      GIR_Done,
43568
    // Label 2224: @140147
43569
0
    GIM_Try, /*On fail goto*//*Label 2225*/ GIMT_Encode4(140220), // Rule ID 2330 //
43570
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
43571
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43572
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
43573
0
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43574
0
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
43575
0
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43576
0
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43577
0
      GIM_CheckIsSafeToFold, /*InsnID*/1,
43578
      // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
43579
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43580
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSS),
43581
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43582
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
43583
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43584
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43585
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
43586
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43587
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
43588
0
      GIR_EraseFromParent, /*InsnID*/0,
43589
      // GIR_Coverage, 2330,
43590
0
      GIR_Done,
43591
    // Label 2225: @140220
43592
0
    GIM_Try, /*On fail goto*//*Label 2226*/ GIMT_Encode4(140293), // Rule ID 2332 //
43593
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
43594
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
43595
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
43596
0
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43597
0
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
43598
0
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43599
0
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43600
0
      GIM_CheckIsSafeToFold, /*InsnID*/1,
43601
      // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
43602
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43603
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSD),
43604
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43605
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
43606
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43607
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43608
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
43609
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43610
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
43611
0
      GIR_EraseFromParent, /*InsnID*/0,
43612
      // GIR_Coverage, 2332,
43613
0
      GIR_Done,
43614
    // Label 2226: @140293
43615
0
    GIM_Try, /*On fail goto*//*Label 2227*/ GIMT_Encode4(140366), // Rule ID 2334 //
43616
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
43617
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
43618
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
43619
0
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43620
0
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
43621
0
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
43622
0
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43623
0
      GIM_CheckIsSafeToFold, /*InsnID*/1,
43624
      // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
43625
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43626
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSH),
43627
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43628
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
43629
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43630
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43631
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
43632
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43633
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
43634
0
      GIR_EraseFromParent, /*InsnID*/0,
43635
      // GIR_Coverage, 2334,
43636
0
      GIR_Done,
43637
    // Label 2227: @140366
43638
0
    GIM_Try, /*On fail goto*//*Label 2228*/ GIMT_Encode4(140439), // Rule ID 2336 //
43639
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
43640
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43641
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
43642
0
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43643
0
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
43644
0
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43645
0
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43646
0
      GIM_CheckIsSafeToFold, /*InsnID*/1,
43647
      // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
43648
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43649
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSS),
43650
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43651
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
43652
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43653
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43654
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
43655
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43656
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
43657
0
      GIR_EraseFromParent, /*InsnID*/0,
43658
      // GIR_Coverage, 2336,
43659
0
      GIR_Done,
43660
    // Label 2228: @140439
43661
0
    GIM_Try, /*On fail goto*//*Label 2229*/ GIMT_Encode4(140512), // Rule ID 2338 //
43662
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
43663
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
43664
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
43665
0
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43666
0
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
43667
0
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43668
0
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43669
0
      GIM_CheckIsSafeToFold, /*InsnID*/1,
43670
      // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
43671
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43672
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSD),
43673
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43674
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
43675
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43676
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43677
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
43678
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43679
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
43680
0
      GIR_EraseFromParent, /*InsnID*/0,
43681
      // GIR_Coverage, 2338,
43682
0
      GIR_Done,
43683
    // Label 2229: @140512
43684
0
    GIM_Try, /*On fail goto*//*Label 2230*/ GIMT_Encode4(140585), // Rule ID 2322 //
43685
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
43686
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
43687
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
43688
0
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43689
0
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
43690
0
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
43691
0
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43692
0
      GIM_CheckIsSafeToFold, /*InsnID*/1,
43693
      // (fp_to_sint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
43694
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43695
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASH),
43696
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43697
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
43698
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43699
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43700
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
43701
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43702
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
43703
0
      GIR_EraseFromParent, /*InsnID*/0,
43704
      // GIR_Coverage, 2322,
43705
0
      GIR_Done,
43706
    // Label 2230: @140585
43707
0
    GIM_Try, /*On fail goto*//*Label 2231*/ GIMT_Encode4(140658), // Rule ID 2324 //
43708
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
43709
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43710
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
43711
0
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43712
0
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
43713
0
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43714
0
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43715
0
      GIM_CheckIsSafeToFold, /*InsnID*/1,
43716
      // (fp_to_sint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
43717
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43718
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASS),
43719
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43720
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
43721
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43722
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43723
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
43724
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43725
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
43726
0
      GIR_EraseFromParent, /*InsnID*/0,
43727
      // GIR_Coverage, 2324,
43728
0
      GIR_Done,
43729
    // Label 2231: @140658
43730
0
    GIM_Try, /*On fail goto*//*Label 2232*/ GIMT_Encode4(140731), // Rule ID 2326 //
43731
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
43732
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
43733
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
43734
0
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43735
0
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
43736
0
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43737
0
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43738
0
      GIM_CheckIsSafeToFold, /*InsnID*/1,
43739
      // (fp_to_sint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
43740
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43741
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASD),
43742
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43743
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
43744
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43745
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43746
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
43747
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43748
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
43749
0
      GIR_EraseFromParent, /*InsnID*/0,
43750
      // GIR_Coverage, 2326,
43751
0
      GIR_Done,
43752
    // Label 2232: @140731
43753
0
    GIM_Try, /*On fail goto*//*Label 2233*/ GIMT_Encode4(140799), // Rule ID 2359 //
43754
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
43755
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
43756
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
43757
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43758
      // (fp_to_sint:{ *:[i32] } DPR:{ *:[f64] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
43759
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43760
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZD),
43761
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43762
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
43763
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
43764
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43765
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43766
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43767
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
43768
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43769
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
43770
0
      GIR_EraseFromParent, /*InsnID*/0,
43771
      // GIR_Coverage, 2359,
43772
0
      GIR_Done,
43773
    // Label 2233: @140799
43774
0
    GIM_Try, /*On fail goto*//*Label 2234*/ GIMT_Encode4(140867), // Rule ID 2363 //
43775
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
43776
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43777
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
43778
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43779
      // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
43780
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43781
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZS),
43782
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43783
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
43784
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
43785
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43786
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43787
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43788
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
43789
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43790
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
43791
0
      GIR_EraseFromParent, /*InsnID*/0,
43792
      // GIR_Coverage, 2363,
43793
0
      GIR_Done,
43794
    // Label 2234: @140867
43795
0
    GIM_Try, /*On fail goto*//*Label 2235*/ GIMT_Encode4(140935), // Rule ID 2367 //
43796
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
43797
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
43798
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
43799
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43800
      // (fp_to_sint:{ *:[i32] } HPR:{ *:[f16] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
43801
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43802
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZH),
43803
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43804
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
43805
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
43806
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43807
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43808
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43809
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
43810
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43811
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
43812
0
      GIR_EraseFromParent, /*InsnID*/0,
43813
      // GIR_Coverage, 2367,
43814
0
      GIR_Done,
43815
    // Label 2235: @140935
43816
0
    GIM_Try, /*On fail goto*//*Label 2236*/ GIMT_Encode4(141062), // Rule ID 2737 //
43817
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
43818
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43819
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43820
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43821
      // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a)  =>  (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2sd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
43822
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
43823
0
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
43824
0
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
43825
0
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43826
0
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43827
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
43828
0
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
43829
0
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43830
0
      GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
43831
0
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a
43832
0
      GIR_AddImm8, /*InsnID*/2, /*Imm*/17,
43833
0
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43834
0
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43835
0
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
43836
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sd),
43837
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43838
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
43839
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
43840
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43841
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43842
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43843
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
43844
0
      GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
43845
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
43846
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43847
0
      GIR_EraseFromParent, /*InsnID*/0,
43848
      // GIR_Coverage, 2737,
43849
0
      GIR_Done,
43850
    // Label 2236: @141062
43851
0
    GIM_Reject,
43852
    // Label 2217: @141063
43853
0
    GIM_Try, /*On fail goto*//*Label 2237*/ GIMT_Encode4(141111), // Rule ID 1623 //
43854
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43855
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
43856
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43857
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43858
      // (fp_to_sint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTf2sd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
43859
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sd),
43860
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
43861
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43862
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43863
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43864
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43865
0
      GIR_EraseFromParent, /*InsnID*/0,
43866
      // GIR_Coverage, 1623,
43867
0
      GIR_Done,
43868
    // Label 2237: @141111
43869
0
    GIM_Reject,
43870
    // Label 2218: @141112
43871
0
    GIM_Try, /*On fail goto*//*Label 2238*/ GIMT_Encode4(141175), // Rule ID 5231 //
43872
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
43873
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
43874
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
43875
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43876
      // (fp_to_sint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1)  =>  (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
43877
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32r),
43878
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[P0]
43879
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1
43880
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43881
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
43882
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43883
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43884
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43885
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43886
0
      GIR_EraseFromParent, /*InsnID*/0,
43887
      // GIR_Coverage, 5231,
43888
0
      GIR_Done,
43889
    // Label 2238: @141175
43890
0
    GIM_Reject,
43891
    // Label 2219: @141176
43892
0
    GIM_Try, /*On fail goto*//*Label 2239*/ GIMT_Encode4(141224), // Rule ID 1631 //
43893
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
43894
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
43895
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43896
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43897
      // (fp_to_sint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTh2sd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
43898
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTh2sd),
43899
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
43900
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43901
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43902
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43903
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43904
0
      GIR_EraseFromParent, /*InsnID*/0,
43905
      // GIR_Coverage, 1631,
43906
0
      GIR_Done,
43907
    // Label 2239: @141224
43908
0
    GIM_Reject,
43909
    // Label 2220: @141225
43910
0
    GIM_Try, /*On fail goto*//*Label 2240*/ GIMT_Encode4(141342),
43911
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
43912
0
      GIM_Try, /*On fail goto*//*Label 2241*/ GIMT_Encode4(141278), // Rule ID 1627 //
43913
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43914
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43915
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43916
        // (fp_to_sint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTf2sq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
43917
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sq),
43918
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
43919
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43920
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43921
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43922
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43923
0
        GIR_EraseFromParent, /*InsnID*/0,
43924
        // GIR_Coverage, 1627,
43925
0
        GIR_Done,
43926
      // Label 2241: @141278
43927
0
      GIM_Try, /*On fail goto*//*Label 2242*/ GIMT_Encode4(141341), // Rule ID 4218 //
43928
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
43929
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43930
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43931
        // (fp_to_sint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)  =>  (MVE_VCVTs32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
43932
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43933
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43934
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
43935
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32z),
43936
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
43937
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
43938
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43939
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43940
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43941
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43942
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43943
0
        GIR_EraseFromParent, /*InsnID*/0,
43944
        // GIR_Coverage, 4218,
43945
0
        GIR_Done,
43946
      // Label 2242: @141341
43947
0
      GIM_Reject,
43948
    // Label 2240: @141342
43949
0
    GIM_Reject,
43950
    // Label 2221: @141343
43951
0
    GIM_Try, /*On fail goto*//*Label 2243*/ GIMT_Encode4(141406), // Rule ID 5232 //
43952
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
43953
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
43954
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
43955
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43956
      // (fp_to_sint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1)  =>  (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
43957
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16r),
43958
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[P0]
43959
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1
43960
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43961
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
43962
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43963
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43964
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43965
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43966
0
      GIR_EraseFromParent, /*InsnID*/0,
43967
      // GIR_Coverage, 5232,
43968
0
      GIR_Done,
43969
    // Label 2243: @141406
43970
0
    GIM_Reject,
43971
    // Label 2222: @141407
43972
0
    GIM_Try, /*On fail goto*//*Label 2244*/ GIMT_Encode4(141524),
43973
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
43974
0
      GIM_Try, /*On fail goto*//*Label 2245*/ GIMT_Encode4(141460), // Rule ID 1635 //
43975
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
43976
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43977
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43978
        // (fp_to_sint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTh2sq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
43979
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTh2sq),
43980
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
43981
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43982
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43983
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43984
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43985
0
        GIR_EraseFromParent, /*InsnID*/0,
43986
        // GIR_Coverage, 1635,
43987
0
        GIR_Done,
43988
      // Label 2245: @141460
43989
0
      GIM_Try, /*On fail goto*//*Label 2246*/ GIMT_Encode4(141523), // Rule ID 4214 //
43990
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
43991
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43992
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43993
        // (fp_to_sint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)  =>  (MVE_VCVTs16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
43994
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43995
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43996
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
43997
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16z),
43998
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
43999
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
44000
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44001
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44002
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44003
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44004
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44005
0
        GIR_EraseFromParent, /*InsnID*/0,
44006
        // GIR_Coverage, 4214,
44007
0
        GIR_Done,
44008
      // Label 2246: @141523
44009
0
      GIM_Reject,
44010
    // Label 2244: @141524
44011
0
    GIM_Reject,
44012
    // Label 2223: @141525
44013
0
    GIM_Reject,
44014
    // Label 41: @141526
44015
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 2254*/ GIMT_Encode4(143036),
44016
0
    /*GILLT_s32*//*Label 2247*/ GIMT_Encode4(141585), GIMT_Encode4(0), GIMT_Encode4(0),
44017
0
    /*GILLT_v2s32*//*Label 2248*/ GIMT_Encode4(142574), GIMT_Encode4(0),
44018
0
    /*GILLT_v4s1*//*Label 2249*/ GIMT_Encode4(142623),
44019
0
    /*GILLT_v4s16*//*Label 2250*/ GIMT_Encode4(142687),
44020
0
    /*GILLT_v4s32*//*Label 2251*/ GIMT_Encode4(142736), GIMT_Encode4(0),
44021
0
    /*GILLT_v8s1*//*Label 2252*/ GIMT_Encode4(142854), GIMT_Encode4(0),
44022
0
    /*GILLT_v8s16*//*Label 2253*/ GIMT_Encode4(142918),
44023
    // Label 2247: @141585
44024
0
    GIM_Try, /*On fail goto*//*Label 2255*/ GIMT_Encode4(141658), // Rule ID 2329 //
44025
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
44026
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
44027
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44028
0
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44029
0
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
44030
0
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
44031
0
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44032
0
      GIM_CheckIsSafeToFold, /*InsnID*/1,
44033
      // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
44034
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44035
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUH),
44036
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44037
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44038
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44039
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44040
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
44041
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44042
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44043
0
      GIR_EraseFromParent, /*InsnID*/0,
44044
      // GIR_Coverage, 2329,
44045
0
      GIR_Done,
44046
    // Label 2255: @141658
44047
0
    GIM_Try, /*On fail goto*//*Label 2256*/ GIMT_Encode4(141731), // Rule ID 2331 //
44048
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
44049
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
44050
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44051
0
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44052
0
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
44053
0
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
44054
0
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44055
0
      GIM_CheckIsSafeToFold, /*InsnID*/1,
44056
      // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
44057
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44058
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUS),
44059
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44060
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44061
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44062
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44063
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
44064
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44065
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44066
0
      GIR_EraseFromParent, /*InsnID*/0,
44067
      // GIR_Coverage, 2331,
44068
0
      GIR_Done,
44069
    // Label 2256: @141731
44070
0
    GIM_Try, /*On fail goto*//*Label 2257*/ GIMT_Encode4(141804), // Rule ID 2333 //
44071
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
44072
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
44073
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44074
0
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44075
0
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
44076
0
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
44077
0
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44078
0
      GIM_CheckIsSafeToFold, /*InsnID*/1,
44079
      // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
44080
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44081
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUD),
44082
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44083
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44084
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44085
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44086
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
44087
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44088
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44089
0
      GIR_EraseFromParent, /*InsnID*/0,
44090
      // GIR_Coverage, 2333,
44091
0
      GIR_Done,
44092
    // Label 2257: @141804
44093
0
    GIM_Try, /*On fail goto*//*Label 2258*/ GIMT_Encode4(141877), // Rule ID 2335 //
44094
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
44095
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
44096
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44097
0
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44098
0
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
44099
0
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
44100
0
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44101
0
      GIM_CheckIsSafeToFold, /*InsnID*/1,
44102
      // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
44103
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44104
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUH),
44105
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44106
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44107
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44108
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44109
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
44110
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44111
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44112
0
      GIR_EraseFromParent, /*InsnID*/0,
44113
      // GIR_Coverage, 2335,
44114
0
      GIR_Done,
44115
    // Label 2258: @141877
44116
0
    GIM_Try, /*On fail goto*//*Label 2259*/ GIMT_Encode4(141950), // Rule ID 2337 //
44117
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
44118
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
44119
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44120
0
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44121
0
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
44122
0
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
44123
0
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44124
0
      GIM_CheckIsSafeToFold, /*InsnID*/1,
44125
      // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
44126
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44127
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUS),
44128
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44129
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44130
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44131
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44132
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
44133
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44134
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44135
0
      GIR_EraseFromParent, /*InsnID*/0,
44136
      // GIR_Coverage, 2337,
44137
0
      GIR_Done,
44138
    // Label 2259: @141950
44139
0
    GIM_Try, /*On fail goto*//*Label 2260*/ GIMT_Encode4(142023), // Rule ID 2339 //
44140
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
44141
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
44142
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44143
0
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44144
0
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
44145
0
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
44146
0
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44147
0
      GIM_CheckIsSafeToFold, /*InsnID*/1,
44148
      // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
44149
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44150
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUD),
44151
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44152
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44153
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44154
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44155
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
44156
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44157
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44158
0
      GIR_EraseFromParent, /*InsnID*/0,
44159
      // GIR_Coverage, 2339,
44160
0
      GIR_Done,
44161
    // Label 2260: @142023
44162
0
    GIM_Try, /*On fail goto*//*Label 2261*/ GIMT_Encode4(142096), // Rule ID 2323 //
44163
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
44164
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
44165
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44166
0
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44167
0
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
44168
0
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
44169
0
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44170
0
      GIM_CheckIsSafeToFold, /*InsnID*/1,
44171
      // (fp_to_uint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
44172
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44173
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUH),
44174
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44175
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44176
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44177
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44178
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
44179
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44180
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44181
0
      GIR_EraseFromParent, /*InsnID*/0,
44182
      // GIR_Coverage, 2323,
44183
0
      GIR_Done,
44184
    // Label 2261: @142096
44185
0
    GIM_Try, /*On fail goto*//*Label 2262*/ GIMT_Encode4(142169), // Rule ID 2325 //
44186
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
44187
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
44188
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44189
0
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44190
0
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
44191
0
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
44192
0
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44193
0
      GIM_CheckIsSafeToFold, /*InsnID*/1,
44194
      // (fp_to_uint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
44195
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44196
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUS),
44197
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44198
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44199
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44200
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44201
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
44202
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44203
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44204
0
      GIR_EraseFromParent, /*InsnID*/0,
44205
      // GIR_Coverage, 2325,
44206
0
      GIR_Done,
44207
    // Label 2262: @142169
44208
0
    GIM_Try, /*On fail goto*//*Label 2263*/ GIMT_Encode4(142242), // Rule ID 2327 //
44209
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
44210
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
44211
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44212
0
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44213
0
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
44214
0
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
44215
0
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44216
0
      GIM_CheckIsSafeToFold, /*InsnID*/1,
44217
      // (fp_to_uint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
44218
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44219
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUD),
44220
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44221
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44222
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44223
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44224
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
44225
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44226
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44227
0
      GIR_EraseFromParent, /*InsnID*/0,
44228
      // GIR_Coverage, 2327,
44229
0
      GIR_Done,
44230
    // Label 2263: @142242
44231
0
    GIM_Try, /*On fail goto*//*Label 2264*/ GIMT_Encode4(142310), // Rule ID 2369 //
44232
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
44233
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
44234
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44235
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44236
      // (fp_to_uint:{ *:[i32] } DPR:{ *:[f64] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
44237
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44238
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZD),
44239
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44240
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44241
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
44242
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44243
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44244
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44245
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
44246
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44247
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44248
0
      GIR_EraseFromParent, /*InsnID*/0,
44249
      // GIR_Coverage, 2369,
44250
0
      GIR_Done,
44251
    // Label 2264: @142310
44252
0
    GIM_Try, /*On fail goto*//*Label 2265*/ GIMT_Encode4(142378), // Rule ID 2373 //
44253
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
44254
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
44255
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44256
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44257
      // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
44258
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44259
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZS),
44260
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44261
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44262
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
44263
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44264
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44265
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44266
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
44267
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44268
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44269
0
      GIR_EraseFromParent, /*InsnID*/0,
44270
      // GIR_Coverage, 2373,
44271
0
      GIR_Done,
44272
    // Label 2265: @142378
44273
0
    GIM_Try, /*On fail goto*//*Label 2266*/ GIMT_Encode4(142446), // Rule ID 2377 //
44274
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
44275
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
44276
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44277
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44278
      // (fp_to_uint:{ *:[i32] } HPR:{ *:[f16] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
44279
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44280
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZH),
44281
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44282
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44283
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
44284
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44285
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44286
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44287
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
44288
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44289
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44290
0
      GIR_EraseFromParent, /*InsnID*/0,
44291
      // GIR_Coverage, 2377,
44292
0
      GIR_Done,
44293
    // Label 2266: @142446
44294
0
    GIM_Try, /*On fail goto*//*Label 2267*/ GIMT_Encode4(142573), // Rule ID 2738 //
44295
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
44296
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
44297
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44298
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44299
      // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a)  =>  (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2ud:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
44300
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
44301
0
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
44302
0
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
44303
0
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44304
0
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44305
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
44306
0
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
44307
0
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44308
0
      GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
44309
0
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a
44310
0
      GIR_AddImm8, /*InsnID*/2, /*Imm*/17,
44311
0
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
44312
0
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
44313
0
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
44314
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTf2ud),
44315
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44316
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44317
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
44318
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44319
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44320
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44321
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
44322
0
      GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
44323
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
44324
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
44325
0
      GIR_EraseFromParent, /*InsnID*/0,
44326
      // GIR_Coverage, 2738,
44327
0
      GIR_Done,
44328
    // Label 2267: @142573
44329
0
    GIM_Reject,
44330
    // Label 2248: @142574
44331
0
    GIM_Try, /*On fail goto*//*Label 2268*/ GIMT_Encode4(142622), // Rule ID 1624 //
44332
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
44333
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
44334
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44335
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44336
      // (fp_to_uint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTf2ud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
44337
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTf2ud),
44338
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
44339
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44340
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44341
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44342
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44343
0
      GIR_EraseFromParent, /*InsnID*/0,
44344
      // GIR_Coverage, 1624,
44345
0
      GIR_Done,
44346
    // Label 2268: @142622
44347
0
    GIM_Reject,
44348
    // Label 2249: @142623
44349
0
    GIM_Try, /*On fail goto*//*Label 2269*/ GIMT_Encode4(142686), // Rule ID 5229 //
44350
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
44351
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
44352
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
44353
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44354
      // (fp_to_uint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1)  =>  (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
44355
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32r),
44356
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[P0]
44357
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1
44358
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44359
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
44360
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44361
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44362
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44363
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44364
0
      GIR_EraseFromParent, /*InsnID*/0,
44365
      // GIR_Coverage, 5229,
44366
0
      GIR_Done,
44367
    // Label 2269: @142686
44368
0
    GIM_Reject,
44369
    // Label 2250: @142687
44370
0
    GIM_Try, /*On fail goto*//*Label 2270*/ GIMT_Encode4(142735), // Rule ID 1632 //
44371
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
44372
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
44373
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44374
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44375
      // (fp_to_uint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTh2ud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
44376
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTh2ud),
44377
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
44378
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44379
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44380
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44381
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44382
0
      GIR_EraseFromParent, /*InsnID*/0,
44383
      // GIR_Coverage, 1632,
44384
0
      GIR_Done,
44385
    // Label 2270: @142735
44386
0
    GIM_Reject,
44387
    // Label 2251: @142736
44388
0
    GIM_Try, /*On fail goto*//*Label 2271*/ GIMT_Encode4(142853),
44389
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
44390
0
      GIM_Try, /*On fail goto*//*Label 2272*/ GIMT_Encode4(142789), // Rule ID 1628 //
44391
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
44392
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44393
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44394
        // (fp_to_uint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTf2uq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
44395
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTf2uq),
44396
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
44397
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44398
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44399
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44400
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44401
0
        GIR_EraseFromParent, /*InsnID*/0,
44402
        // GIR_Coverage, 1628,
44403
0
        GIR_Done,
44404
      // Label 2272: @142789
44405
0
      GIM_Try, /*On fail goto*//*Label 2273*/ GIMT_Encode4(142852), // Rule ID 4220 //
44406
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
44407
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44408
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44409
        // (fp_to_uint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)  =>  (MVE_VCVTu32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
44410
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44411
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44412
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
44413
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32z),
44414
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
44415
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
44416
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44417
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44418
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44419
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44420
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44421
0
        GIR_EraseFromParent, /*InsnID*/0,
44422
        // GIR_Coverage, 4220,
44423
0
        GIR_Done,
44424
      // Label 2273: @142852
44425
0
      GIM_Reject,
44426
    // Label 2271: @142853
44427
0
    GIM_Reject,
44428
    // Label 2252: @142854
44429
0
    GIM_Try, /*On fail goto*//*Label 2274*/ GIMT_Encode4(142917), // Rule ID 5230 //
44430
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
44431
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
44432
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
44433
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44434
      // (fp_to_uint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1)  =>  (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
44435
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16r),
44436
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[P0]
44437
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1
44438
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44439
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
44440
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44441
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44442
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44443
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44444
0
      GIR_EraseFromParent, /*InsnID*/0,
44445
      // GIR_Coverage, 5230,
44446
0
      GIR_Done,
44447
    // Label 2274: @142917
44448
0
    GIM_Reject,
44449
    // Label 2253: @142918
44450
0
    GIM_Try, /*On fail goto*//*Label 2275*/ GIMT_Encode4(143035),
44451
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
44452
0
      GIM_Try, /*On fail goto*//*Label 2276*/ GIMT_Encode4(142971), // Rule ID 1636 //
44453
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
44454
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44455
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44456
        // (fp_to_uint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTh2uq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
44457
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTh2uq),
44458
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
44459
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44460
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44461
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44462
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44463
0
        GIR_EraseFromParent, /*InsnID*/0,
44464
        // GIR_Coverage, 1636,
44465
0
        GIR_Done,
44466
      // Label 2276: @142971
44467
0
      GIM_Try, /*On fail goto*//*Label 2277*/ GIMT_Encode4(143034), // Rule ID 4216 //
44468
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
44469
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44470
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44471
        // (fp_to_uint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)  =>  (MVE_VCVTu16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
44472
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44473
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44474
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
44475
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16z),
44476
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
44477
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
44478
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44479
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44480
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44481
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44482
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44483
0
        GIR_EraseFromParent, /*InsnID*/0,
44484
        // GIR_Coverage, 4216,
44485
0
        GIR_Done,
44486
      // Label 2277: @143034
44487
0
      GIM_Reject,
44488
    // Label 2275: @143035
44489
0
    GIM_Reject,
44490
    // Label 2254: @143036
44491
0
    GIM_Reject,
44492
    // Label 42: @143037
44493
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2285*/ GIMT_Encode4(143778),
44494
0
    /*GILLT_s16*//*Label 2278*/ GIMT_Encode4(143100),
44495
0
    /*GILLT_s32*//*Label 2279*/ GIMT_Encode4(143166),
44496
0
    /*GILLT_s64*//*Label 2280*/ GIMT_Encode4(143378), GIMT_Encode4(0),
44497
0
    /*GILLT_v2s32*//*Label 2281*/ GIMT_Encode4(143444), GIMT_Encode4(0), GIMT_Encode4(0),
44498
0
    /*GILLT_v4s16*//*Label 2282*/ GIMT_Encode4(143493),
44499
0
    /*GILLT_v4s32*//*Label 2283*/ GIMT_Encode4(143542), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
44500
0
    /*GILLT_v8s16*//*Label 2284*/ GIMT_Encode4(143660),
44501
    // Label 2278: @143100
44502
0
    GIM_Try, /*On fail goto*//*Label 2286*/ GIMT_Encode4(143165), // Rule ID 2353 //
44503
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
44504
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
44505
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44506
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44507
      // (sint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a)  =>  (VSITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
44508
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44509
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44510
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44511
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44512
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44513
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSITOH),
44514
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
44515
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44516
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44517
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44518
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44519
0
      GIR_EraseFromParent, /*InsnID*/0,
44520
      // GIR_Coverage, 2353,
44521
0
      GIR_Done,
44522
    // Label 2286: @143165
44523
0
    GIM_Reject,
44524
    // Label 2279: @143166
44525
0
    GIM_Try, /*On fail goto*//*Label 2287*/ GIMT_Encode4(143377),
44526
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
44527
0
      GIM_Try, /*On fail goto*//*Label 2288*/ GIMT_Encode4(143236), // Rule ID 2351 //
44528
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
44529
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44530
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44531
        // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a)  =>  (VSITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
44532
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44533
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44534
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44535
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44536
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44537
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSITOS),
44538
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
44539
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44540
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44541
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44542
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44543
0
        GIR_EraseFromParent, /*InsnID*/0,
44544
        // GIR_Coverage, 2351,
44545
0
        GIR_Done,
44546
      // Label 2288: @143236
44547
0
      GIM_Try, /*On fail goto*//*Label 2289*/ GIMT_Encode4(143376), // Rule ID 2739 //
44548
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
44549
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44550
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44551
        // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a)  =>  (EXTRACT_SUBREG:{ *:[f32] } (VCVTs2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
44552
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
44553
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
44554
0
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
44555
0
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
44556
0
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44557
0
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44558
0
        GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a
44559
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
44560
0
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44561
0
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44562
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
44563
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
44564
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44565
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
44566
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
44567
0
        GIR_AddImm8, /*InsnID*/2, /*Imm*/17,
44568
0
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
44569
0
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
44570
0
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
44571
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fd),
44572
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44573
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44574
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
44575
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44576
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44577
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44578
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
44579
0
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
44580
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
44581
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
44582
0
        GIR_EraseFromParent, /*InsnID*/0,
44583
        // GIR_Coverage, 2739,
44584
0
        GIR_Done,
44585
      // Label 2289: @143376
44586
0
      GIM_Reject,
44587
    // Label 2287: @143377
44588
0
    GIM_Reject,
44589
    // Label 2280: @143378
44590
0
    GIM_Try, /*On fail goto*//*Label 2290*/ GIMT_Encode4(143443), // Rule ID 2349 //
44591
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
44592
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
44593
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44594
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44595
      // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a)  =>  (VSITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
44596
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44597
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44598
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44599
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44600
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44601
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSITOD),
44602
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
44603
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44604
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44605
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44606
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44607
0
      GIR_EraseFromParent, /*InsnID*/0,
44608
      // GIR_Coverage, 2349,
44609
0
      GIR_Done,
44610
    // Label 2290: @143443
44611
0
    GIM_Reject,
44612
    // Label 2281: @143444
44613
0
    GIM_Try, /*On fail goto*//*Label 2291*/ GIMT_Encode4(143492), // Rule ID 1625 //
44614
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
44615
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
44616
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44617
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44618
      // (sint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)  =>  (VCVTs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)
44619
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fd),
44620
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
44621
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44622
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44623
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44624
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44625
0
      GIR_EraseFromParent, /*InsnID*/0,
44626
      // GIR_Coverage, 1625,
44627
0
      GIR_Done,
44628
    // Label 2291: @143492
44629
0
    GIM_Reject,
44630
    // Label 2282: @143493
44631
0
    GIM_Try, /*On fail goto*//*Label 2292*/ GIMT_Encode4(143541), // Rule ID 1633 //
44632
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
44633
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
44634
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44635
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44636
      // (sint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)  =>  (VCVTs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)
44637
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTs2hd),
44638
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
44639
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44640
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44641
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44642
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44643
0
      GIR_EraseFromParent, /*InsnID*/0,
44644
      // GIR_Coverage, 1633,
44645
0
      GIR_Done,
44646
    // Label 2292: @143541
44647
0
    GIM_Reject,
44648
    // Label 2283: @143542
44649
0
    GIM_Try, /*On fail goto*//*Label 2293*/ GIMT_Encode4(143659),
44650
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
44651
0
      GIM_Try, /*On fail goto*//*Label 2294*/ GIMT_Encode4(143595), // Rule ID 1629 //
44652
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
44653
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44654
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44655
        // (sint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)  =>  (VCVTs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)
44656
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fq),
44657
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
44658
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44659
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44660
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44661
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44662
0
        GIR_EraseFromParent, /*InsnID*/0,
44663
        // GIR_Coverage, 1629,
44664
0
        GIR_Done,
44665
      // Label 2294: @143595
44666
0
      GIM_Try, /*On fail goto*//*Label 2295*/ GIMT_Encode4(143658), // Rule ID 4226 //
44667
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
44668
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44669
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44670
        // (sint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VCVTf32s32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
44671
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44672
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44673
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
44674
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32n),
44675
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
44676
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
44677
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44678
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44679
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44680
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44681
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44682
0
        GIR_EraseFromParent, /*InsnID*/0,
44683
        // GIR_Coverage, 4226,
44684
0
        GIR_Done,
44685
      // Label 2295: @143658
44686
0
      GIM_Reject,
44687
    // Label 2293: @143659
44688
0
    GIM_Reject,
44689
    // Label 2284: @143660
44690
0
    GIM_Try, /*On fail goto*//*Label 2296*/ GIMT_Encode4(143777),
44691
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
44692
0
      GIM_Try, /*On fail goto*//*Label 2297*/ GIMT_Encode4(143713), // Rule ID 1637 //
44693
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
44694
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44695
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44696
        // (sint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)  =>  (VCVTs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)
44697
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTs2hq),
44698
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
44699
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44700
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44701
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44702
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44703
0
        GIR_EraseFromParent, /*InsnID*/0,
44704
        // GIR_Coverage, 1637,
44705
0
        GIR_Done,
44706
      // Label 2297: @143713
44707
0
      GIM_Try, /*On fail goto*//*Label 2298*/ GIMT_Encode4(143776), // Rule ID 4222 //
44708
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
44709
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44710
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44711
        // (sint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VCVTf16s16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
44712
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44713
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44714
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
44715
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16n),
44716
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
44717
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
44718
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44719
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44720
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44721
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44722
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44723
0
        GIR_EraseFromParent, /*InsnID*/0,
44724
        // GIR_Coverage, 4222,
44725
0
        GIR_Done,
44726
      // Label 2298: @143776
44727
0
      GIM_Reject,
44728
    // Label 2296: @143777
44729
0
    GIM_Reject,
44730
    // Label 2285: @143778
44731
0
    GIM_Reject,
44732
    // Label 43: @143779
44733
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2306*/ GIMT_Encode4(144520),
44734
0
    /*GILLT_s16*//*Label 2299*/ GIMT_Encode4(143842),
44735
0
    /*GILLT_s32*//*Label 2300*/ GIMT_Encode4(143908),
44736
0
    /*GILLT_s64*//*Label 2301*/ GIMT_Encode4(144120), GIMT_Encode4(0),
44737
0
    /*GILLT_v2s32*//*Label 2302*/ GIMT_Encode4(144186), GIMT_Encode4(0), GIMT_Encode4(0),
44738
0
    /*GILLT_v4s16*//*Label 2303*/ GIMT_Encode4(144235),
44739
0
    /*GILLT_v4s32*//*Label 2304*/ GIMT_Encode4(144284), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
44740
0
    /*GILLT_v8s16*//*Label 2305*/ GIMT_Encode4(144402),
44741
    // Label 2299: @143842
44742
0
    GIM_Try, /*On fail goto*//*Label 2307*/ GIMT_Encode4(143907), // Rule ID 2358 //
44743
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
44744
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
44745
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44746
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44747
      // (uint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a)  =>  (VUITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
44748
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44749
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44750
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44751
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44752
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44753
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VUITOH),
44754
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
44755
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44756
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44757
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44758
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44759
0
      GIR_EraseFromParent, /*InsnID*/0,
44760
      // GIR_Coverage, 2358,
44761
0
      GIR_Done,
44762
    // Label 2307: @143907
44763
0
    GIM_Reject,
44764
    // Label 2300: @143908
44765
0
    GIM_Try, /*On fail goto*//*Label 2308*/ GIMT_Encode4(144119),
44766
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
44767
0
      GIM_Try, /*On fail goto*//*Label 2309*/ GIMT_Encode4(143978), // Rule ID 2356 //
44768
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
44769
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44770
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44771
        // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a)  =>  (VUITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
44772
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44773
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44774
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44775
0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44776
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44777
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VUITOS),
44778
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
44779
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44780
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44781
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44782
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44783
0
        GIR_EraseFromParent, /*InsnID*/0,
44784
        // GIR_Coverage, 2356,
44785
0
        GIR_Done,
44786
      // Label 2309: @143978
44787
0
      GIM_Try, /*On fail goto*//*Label 2310*/ GIMT_Encode4(144118), // Rule ID 2740 //
44788
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
44789
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44790
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44791
        // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a)  =>  (EXTRACT_SUBREG:{ *:[f32] } (VCVTu2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
44792
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
44793
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
44794
0
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
44795
0
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
44796
0
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44797
0
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44798
0
        GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a
44799
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
44800
0
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44801
0
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44802
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
44803
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
44804
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44805
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
44806
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
44807
0
        GIR_AddImm8, /*InsnID*/2, /*Imm*/17,
44808
0
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
44809
0
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
44810
0
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
44811
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fd),
44812
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44813
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44814
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
44815
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44816
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44817
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44818
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
44819
0
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
44820
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
44821
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
44822
0
        GIR_EraseFromParent, /*InsnID*/0,
44823
        // GIR_Coverage, 2740,
44824
0
        GIR_Done,
44825
      // Label 2310: @144118
44826
0
      GIM_Reject,
44827
    // Label 2308: @144119
44828
0
    GIM_Reject,
44829
    // Label 2301: @144120
44830
0
    GIM_Try, /*On fail goto*//*Label 2311*/ GIMT_Encode4(144185), // Rule ID 2354 //
44831
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
44832
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
44833
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44834
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44835
      // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a)  =>  (VUITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
44836
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44837
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44838
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44839
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44840
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44841
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VUITOD),
44842
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
44843
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44844
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44845
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44846
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44847
0
      GIR_EraseFromParent, /*InsnID*/0,
44848
      // GIR_Coverage, 2354,
44849
0
      GIR_Done,
44850
    // Label 2311: @144185
44851
0
    GIM_Reject,
44852
    // Label 2302: @144186
44853
0
    GIM_Try, /*On fail goto*//*Label 2312*/ GIMT_Encode4(144234), // Rule ID 1626 //
44854
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
44855
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
44856
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44857
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44858
      // (uint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)  =>  (VCVTu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)
44859
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fd),
44860
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
44861
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44862
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44863
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44864
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44865
0
      GIR_EraseFromParent, /*InsnID*/0,
44866
      // GIR_Coverage, 1626,
44867
0
      GIR_Done,
44868
    // Label 2312: @144234
44869
0
    GIM_Reject,
44870
    // Label 2303: @144235
44871
0
    GIM_Try, /*On fail goto*//*Label 2313*/ GIMT_Encode4(144283), // Rule ID 1634 //
44872
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
44873
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
44874
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44875
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44876
      // (uint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)  =>  (VCVTu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)
44877
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTu2hd),
44878
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
44879
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44880
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44881
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44882
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44883
0
      GIR_EraseFromParent, /*InsnID*/0,
44884
      // GIR_Coverage, 1634,
44885
0
      GIR_Done,
44886
    // Label 2313: @144283
44887
0
    GIM_Reject,
44888
    // Label 2304: @144284
44889
0
    GIM_Try, /*On fail goto*//*Label 2314*/ GIMT_Encode4(144401),
44890
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
44891
0
      GIM_Try, /*On fail goto*//*Label 2315*/ GIMT_Encode4(144337), // Rule ID 1630 //
44892
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
44893
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44894
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44895
        // (uint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)  =>  (VCVTu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)
44896
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fq),
44897
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
44898
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44899
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44900
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44901
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44902
0
        GIR_EraseFromParent, /*InsnID*/0,
44903
        // GIR_Coverage, 1630,
44904
0
        GIR_Done,
44905
      // Label 2315: @144337
44906
0
      GIM_Try, /*On fail goto*//*Label 2316*/ GIMT_Encode4(144400), // Rule ID 4228 //
44907
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
44908
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44909
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44910
        // (uint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VCVTf32u32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
44911
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44912
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44913
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
44914
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32n),
44915
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
44916
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
44917
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44918
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44919
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44920
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44921
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44922
0
        GIR_EraseFromParent, /*InsnID*/0,
44923
        // GIR_Coverage, 4228,
44924
0
        GIR_Done,
44925
      // Label 2316: @144400
44926
0
      GIM_Reject,
44927
    // Label 2314: @144401
44928
0
    GIM_Reject,
44929
    // Label 2305: @144402
44930
0
    GIM_Try, /*On fail goto*//*Label 2317*/ GIMT_Encode4(144519),
44931
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
44932
0
      GIM_Try, /*On fail goto*//*Label 2318*/ GIMT_Encode4(144455), // Rule ID 1638 //
44933
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
44934
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44935
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44936
        // (uint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)  =>  (VCVTu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)
44937
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCVTu2hq),
44938
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
44939
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44940
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44941
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44942
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44943
0
        GIR_EraseFromParent, /*InsnID*/0,
44944
        // GIR_Coverage, 1638,
44945
0
        GIR_Done,
44946
      // Label 2318: @144455
44947
0
      GIM_Try, /*On fail goto*//*Label 2319*/ GIMT_Encode4(144518), // Rule ID 4224 //
44948
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
44949
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44950
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44951
        // (uint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VCVTf16u16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
44952
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44953
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44954
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
44955
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16n),
44956
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
44957
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
44958
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44959
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44960
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44961
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44962
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44963
0
        GIR_EraseFromParent, /*InsnID*/0,
44964
        // GIR_Coverage, 4224,
44965
0
        GIR_Done,
44966
      // Label 2319: @144518
44967
0
      GIM_Reject,
44968
    // Label 2317: @144519
44969
0
    GIM_Reject,
44970
    // Label 2306: @144520
44971
0
    GIM_Reject,
44972
    // Label 44: @144521
44973
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2327*/ GIMT_Encode4(145408),
44974
0
    /*GILLT_s16*//*Label 2320*/ GIMT_Encode4(144584),
44975
0
    /*GILLT_s32*//*Label 2321*/ GIMT_Encode4(144633),
44976
0
    /*GILLT_s64*//*Label 2322*/ GIMT_Encode4(144845), GIMT_Encode4(0),
44977
0
    /*GILLT_v2s32*//*Label 2323*/ GIMT_Encode4(144894), GIMT_Encode4(0), GIMT_Encode4(0),
44978
0
    /*GILLT_v4s16*//*Label 2324*/ GIMT_Encode4(144943),
44979
0
    /*GILLT_v4s32*//*Label 2325*/ GIMT_Encode4(144992), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
44980
0
    /*GILLT_v8s16*//*Label 2326*/ GIMT_Encode4(145200),
44981
    // Label 2320: @144584
44982
0
    GIM_Try, /*On fail goto*//*Label 2328*/ GIMT_Encode4(144632), // Rule ID 670 //
44983
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
44984
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
44985
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44986
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44987
      // (fabs:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VABSH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
44988
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABSH),
44989
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
44990
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
44991
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44992
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44993
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44994
0
      GIR_EraseFromParent, /*InsnID*/0,
44995
      // GIR_Coverage, 670,
44996
0
      GIR_Done,
44997
    // Label 2328: @144632
44998
0
    GIM_Reject,
44999
    // Label 2321: @144633
45000
0
    GIM_Try, /*On fail goto*//*Label 2329*/ GIMT_Encode4(144844),
45001
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
45002
0
      GIM_Try, /*On fail goto*//*Label 2330*/ GIMT_Encode4(144686), // Rule ID 669 //
45003
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
45004
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45005
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45006
        // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VABSS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
45007
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABSS),
45008
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
45009
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
45010
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45011
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45012
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45013
0
        GIR_EraseFromParent, /*InsnID*/0,
45014
        // GIR_Coverage, 669,
45015
0
        GIR_Done,
45016
      // Label 2330: @144686
45017
0
      GIM_Try, /*On fail goto*//*Label 2331*/ GIMT_Encode4(144843), // Rule ID 2731 //
45018
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
45019
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45020
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45021
        // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$a)  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VABSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
45022
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
45023
0
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
45024
0
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
45025
0
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
45026
0
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
45027
0
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45028
0
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45029
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
45030
0
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45031
0
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45032
0
        GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
45033
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
45034
0
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45035
0
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45036
0
        GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
45037
0
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
45038
0
        GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
45039
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45040
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45041
0
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
45042
0
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VABSfd),
45043
0
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45044
0
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
45045
0
        GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
45046
0
        GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45047
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45048
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45049
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45050
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45051
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45052
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45053
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
45054
0
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
45055
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45056
0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45057
0
        GIR_EraseFromParent, /*InsnID*/0,
45058
        // GIR_Coverage, 2731,
45059
0
        GIR_Done,
45060
      // Label 2331: @144843
45061
0
      GIM_Reject,
45062
    // Label 2329: @144844
45063
0
    GIM_Reject,
45064
    // Label 2322: @144845
45065
0
    GIM_Try, /*On fail goto*//*Label 2332*/ GIMT_Encode4(144893), // Rule ID 668 //
45066
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
45067
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
45068
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45069
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45070
      // (fabs:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VABSD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
45071
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABSD),
45072
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
45073
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
45074
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45075
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45076
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45077
0
      GIR_EraseFromParent, /*InsnID*/0,
45078
      // GIR_Coverage, 668,
45079
0
      GIR_Done,
45080
    // Label 2332: @144893
45081
0
    GIM_Reject,
45082
    // Label 2323: @144894
45083
0
    GIM_Try, /*On fail goto*//*Label 2333*/ GIMT_Encode4(144942), // Rule ID 1533 //
45084
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
45085
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
45086
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45087
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45088
      // (fabs:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)  =>  (VABSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
45089
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABSfd),
45090
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
45091
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
45092
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45093
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45094
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45095
0
      GIR_EraseFromParent, /*InsnID*/0,
45096
      // GIR_Coverage, 1533,
45097
0
      GIR_Done,
45098
    // Label 2333: @144942
45099
0
    GIM_Reject,
45100
    // Label 2324: @144943
45101
0
    GIM_Try, /*On fail goto*//*Label 2334*/ GIMT_Encode4(144991), // Rule ID 1535 //
45102
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
45103
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
45104
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45105
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45106
      // (fabs:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)  =>  (VABShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
45107
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABShd),
45108
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
45109
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
45110
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45111
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45112
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45113
0
      GIR_EraseFromParent, /*InsnID*/0,
45114
      // GIR_Coverage, 1535,
45115
0
      GIR_Done,
45116
    // Label 2334: @144991
45117
0
    GIM_Reject,
45118
    // Label 2325: @144992
45119
0
    GIM_Try, /*On fail goto*//*Label 2335*/ GIMT_Encode4(145199),
45120
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
45121
0
      GIM_Try, /*On fail goto*//*Label 2336*/ GIMT_Encode4(145091), // Rule ID 4165 //
45122
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45123
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45124
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45125
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
45126
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
45127
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
45128
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45129
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45130
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
45131
        // (fabs:{ *:[v4f32] } (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn))  =>  (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
45132
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45133
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45134
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
45135
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf32),
45136
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
45137
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
45138
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn
45139
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45140
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45141
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45142
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45143
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45144
0
        GIR_EraseFromParent, /*InsnID*/0,
45145
        // GIR_Coverage, 4165,
45146
0
        GIR_Done,
45147
      // Label 2336: @145091
45148
0
      GIM_Try, /*On fail goto*//*Label 2337*/ GIMT_Encode4(145135), // Rule ID 1534 //
45149
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
45150
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45151
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45152
        // (fabs:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)  =>  (VABSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
45153
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABSfq),
45154
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
45155
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
45156
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45157
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45158
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45159
0
        GIR_EraseFromParent, /*InsnID*/0,
45160
        // GIR_Coverage, 1534,
45161
0
        GIR_Done,
45162
      // Label 2337: @145135
45163
0
      GIM_Try, /*On fail goto*//*Label 2338*/ GIMT_Encode4(145198), // Rule ID 4236 //
45164
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
45165
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45166
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45167
        // (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$v)  =>  (MVE_VABSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$v)
45168
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45169
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45170
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
45171
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSf32),
45172
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
45173
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v
45174
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45175
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45176
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45177
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45178
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45179
0
        GIR_EraseFromParent, /*InsnID*/0,
45180
        // GIR_Coverage, 4236,
45181
0
        GIR_Done,
45182
      // Label 2338: @145198
45183
0
      GIM_Reject,
45184
    // Label 2335: @145199
45185
0
    GIM_Reject,
45186
    // Label 2326: @145200
45187
0
    GIM_Try, /*On fail goto*//*Label 2339*/ GIMT_Encode4(145407),
45188
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
45189
0
      GIM_Try, /*On fail goto*//*Label 2340*/ GIMT_Encode4(145299), // Rule ID 4164 //
45190
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45191
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45192
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45193
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
45194
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
45195
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
45196
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45197
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45198
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
45199
        // (fabs:{ *:[v8f16] } (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn))  =>  (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
45200
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45201
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45202
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
45203
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf16),
45204
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
45205
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
45206
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn
45207
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45208
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45209
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45210
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45211
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45212
0
        GIR_EraseFromParent, /*InsnID*/0,
45213
        // GIR_Coverage, 4164,
45214
0
        GIR_Done,
45215
      // Label 2340: @145299
45216
0
      GIM_Try, /*On fail goto*//*Label 2341*/ GIMT_Encode4(145343), // Rule ID 1536 //
45217
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
45218
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45219
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45220
        // (fabs:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)  =>  (VABShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
45221
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABShq),
45222
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
45223
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
45224
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45225
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45226
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45227
0
        GIR_EraseFromParent, /*InsnID*/0,
45228
        // GIR_Coverage, 1536,
45229
0
        GIR_Done,
45230
      // Label 2341: @145343
45231
0
      GIM_Try, /*On fail goto*//*Label 2342*/ GIMT_Encode4(145406), // Rule ID 4234 //
45232
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
45233
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45234
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45235
        // (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$v)  =>  (MVE_VABSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$v)
45236
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45237
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45238
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
45239
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSf16),
45240
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
45241
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v
45242
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45243
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45244
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45245
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45246
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45247
0
        GIR_EraseFromParent, /*InsnID*/0,
45248
        // GIR_Coverage, 4234,
45249
0
        GIR_Done,
45250
      // Label 2342: @145406
45251
0
      GIM_Reject,
45252
    // Label 2339: @145407
45253
0
    GIM_Reject,
45254
    // Label 2327: @145408
45255
0
    GIM_Reject,
45256
    // Label 45: @145409
45257
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2350*/ GIMT_Encode4(146082),
45258
0
    /*GILLT_s16*//*Label 2343*/ GIMT_Encode4(145472),
45259
0
    /*GILLT_s32*//*Label 2344*/ GIMT_Encode4(145512),
45260
0
    /*GILLT_s64*//*Label 2345*/ GIMT_Encode4(145552), GIMT_Encode4(0),
45261
0
    /*GILLT_v2s32*//*Label 2346*/ GIMT_Encode4(145592), GIMT_Encode4(0), GIMT_Encode4(0),
45262
0
    /*GILLT_v4s16*//*Label 2347*/ GIMT_Encode4(145632),
45263
0
    /*GILLT_v4s32*//*Label 2348*/ GIMT_Encode4(145672), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
45264
0
    /*GILLT_v8s16*//*Label 2349*/ GIMT_Encode4(145877),
45265
    // Label 2343: @145472
45266
0
    GIM_Try, /*On fail goto*//*Label 2351*/ GIMT_Encode4(145511), // Rule ID 659 //
45267
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
45268
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
45269
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
45270
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45271
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45272
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45273
      // (fminnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)  =>  (VFP_VMINNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
45274
0
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMH),
45275
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45276
      // GIR_Coverage, 659,
45277
0
      GIR_Done,
45278
    // Label 2351: @145511
45279
0
    GIM_Reject,
45280
    // Label 2344: @145512
45281
0
    GIM_Try, /*On fail goto*//*Label 2352*/ GIMT_Encode4(145551), // Rule ID 660 //
45282
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
45283
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
45284
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
45285
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45286
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45287
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45288
      // (fminnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)  =>  (VFP_VMINNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
45289
0
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMS),
45290
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45291
      // GIR_Coverage, 660,
45292
0
      GIR_Done,
45293
    // Label 2352: @145551
45294
0
    GIM_Reject,
45295
    // Label 2345: @145552
45296
0
    GIM_Try, /*On fail goto*//*Label 2353*/ GIMT_Encode4(145591), // Rule ID 661 //
45297
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
45298
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
45299
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
45300
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45301
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45302
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45303
      // (fminnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)  =>  (VFP_VMINNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
45304
0
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMD),
45305
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45306
      // GIR_Coverage, 661,
45307
0
      GIR_Done,
45308
    // Label 2353: @145591
45309
0
    GIM_Reject,
45310
    // Label 2346: @145592
45311
0
    GIM_Try, /*On fail goto*//*Label 2354*/ GIMT_Encode4(145631), // Rule ID 1252 //
45312
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON),
45313
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
45314
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
45315
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45316
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45317
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45318
      // (fminnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (NEON_VMINNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
45319
0
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNDf),
45320
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45321
      // GIR_Coverage, 1252,
45322
0
      GIR_Done,
45323
    // Label 2354: @145631
45324
0
    GIM_Reject,
45325
    // Label 2347: @145632
45326
0
    GIM_Try, /*On fail goto*//*Label 2355*/ GIMT_Encode4(145671), // Rule ID 1254 //
45327
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON),
45328
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
45329
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
45330
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45331
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45332
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45333
      // (fminnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (NEON_VMINNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
45334
0
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNDh),
45335
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45336
      // GIR_Coverage, 1254,
45337
0
      GIR_Done,
45338
    // Label 2355: @145671
45339
0
    GIM_Reject,
45340
    // Label 2348: @145672
45341
0
    GIM_Try, /*On fail goto*//*Label 2356*/ GIMT_Encode4(145876),
45342
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
45343
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
45344
0
      GIM_Try, /*On fail goto*//*Label 2357*/ GIMT_Encode4(145772), // Rule ID 4246 //
45345
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
45346
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45347
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45348
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
45349
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
45350
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45351
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
45352
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
45353
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
45354
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45355
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
45356
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
45357
        // (fminnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm))  =>  (MVE_VMINNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm)
45358
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf32),
45359
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
45360
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
45361
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
45362
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45363
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45364
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45365
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45366
0
        GIR_EraseFromParent, /*InsnID*/0,
45367
        // GIR_Coverage, 4246,
45368
0
        GIR_Done,
45369
      // Label 2357: @145772
45370
0
      GIM_Try, /*On fail goto*//*Label 2358*/ GIMT_Encode4(145803), // Rule ID 1253 //
45371
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON),
45372
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45373
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45374
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45375
        // (fminnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (NEON_VMINNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
45376
0
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNQf),
45377
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45378
        // GIR_Coverage, 1253,
45379
0
        GIR_Done,
45380
      // Label 2358: @145803
45381
0
      GIM_Try, /*On fail goto*//*Label 2359*/ GIMT_Encode4(145875), // Rule ID 3394 //
45382
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45383
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45384
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45385
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45386
        // (fminnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)  =>  (MVE_VMINNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
45387
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45388
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45389
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
45390
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf32),
45391
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
45392
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
45393
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
45394
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45395
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45396
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45397
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45398
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45399
0
        GIR_EraseFromParent, /*InsnID*/0,
45400
        // GIR_Coverage, 3394,
45401
0
        GIR_Done,
45402
      // Label 2359: @145875
45403
0
      GIM_Reject,
45404
    // Label 2356: @145876
45405
0
    GIM_Reject,
45406
    // Label 2349: @145877
45407
0
    GIM_Try, /*On fail goto*//*Label 2360*/ GIMT_Encode4(146081),
45408
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
45409
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
45410
0
      GIM_Try, /*On fail goto*//*Label 2361*/ GIMT_Encode4(145977), // Rule ID 4248 //
45411
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
45412
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45413
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45414
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
45415
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
45416
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45417
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
45418
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
45419
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
45420
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45421
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
45422
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
45423
        // (fminnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm))  =>  (MVE_VMINNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm)
45424
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf16),
45425
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
45426
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
45427
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
45428
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45429
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45430
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45431
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45432
0
        GIR_EraseFromParent, /*InsnID*/0,
45433
        // GIR_Coverage, 4248,
45434
0
        GIR_Done,
45435
      // Label 2361: @145977
45436
0
      GIM_Try, /*On fail goto*//*Label 2362*/ GIMT_Encode4(146008), // Rule ID 1255 //
45437
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON),
45438
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45439
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45440
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45441
        // (fminnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (NEON_VMINNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
45442
0
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNQh),
45443
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45444
        // GIR_Coverage, 1255,
45445
0
        GIR_Done,
45446
      // Label 2362: @146008
45447
0
      GIM_Try, /*On fail goto*//*Label 2363*/ GIMT_Encode4(146080), // Rule ID 3397 //
45448
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45449
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45450
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45451
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45452
        // (fminnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)  =>  (MVE_VMINNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
45453
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45454
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45455
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
45456
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf16),
45457
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
45458
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
45459
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
45460
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45461
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45462
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45463
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45464
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45465
0
        GIR_EraseFromParent, /*InsnID*/0,
45466
        // GIR_Coverage, 3397,
45467
0
        GIR_Done,
45468
      // Label 2363: @146080
45469
0
      GIM_Reject,
45470
    // Label 2360: @146081
45471
0
    GIM_Reject,
45472
    // Label 2350: @146082
45473
0
    GIM_Reject,
45474
    // Label 46: @146083
45475
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2371*/ GIMT_Encode4(146756),
45476
0
    /*GILLT_s16*//*Label 2364*/ GIMT_Encode4(146146),
45477
0
    /*GILLT_s32*//*Label 2365*/ GIMT_Encode4(146186),
45478
0
    /*GILLT_s64*//*Label 2366*/ GIMT_Encode4(146226), GIMT_Encode4(0),
45479
0
    /*GILLT_v2s32*//*Label 2367*/ GIMT_Encode4(146266), GIMT_Encode4(0), GIMT_Encode4(0),
45480
0
    /*GILLT_v4s16*//*Label 2368*/ GIMT_Encode4(146306),
45481
0
    /*GILLT_v4s32*//*Label 2369*/ GIMT_Encode4(146346), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
45482
0
    /*GILLT_v8s16*//*Label 2370*/ GIMT_Encode4(146551),
45483
    // Label 2364: @146146
45484
0
    GIM_Try, /*On fail goto*//*Label 2372*/ GIMT_Encode4(146185), // Rule ID 656 //
45485
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
45486
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
45487
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
45488
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45489
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45490
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45491
      // (fmaxnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)  =>  (VFP_VMAXNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
45492
0
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMH),
45493
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45494
      // GIR_Coverage, 656,
45495
0
      GIR_Done,
45496
    // Label 2372: @146185
45497
0
    GIM_Reject,
45498
    // Label 2365: @146186
45499
0
    GIM_Try, /*On fail goto*//*Label 2373*/ GIMT_Encode4(146225), // Rule ID 657 //
45500
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
45501
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
45502
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
45503
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45504
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45505
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45506
      // (fmaxnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)  =>  (VFP_VMAXNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
45507
0
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMS),
45508
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45509
      // GIR_Coverage, 657,
45510
0
      GIR_Done,
45511
    // Label 2373: @146225
45512
0
    GIM_Reject,
45513
    // Label 2366: @146226
45514
0
    GIM_Try, /*On fail goto*//*Label 2374*/ GIMT_Encode4(146265), // Rule ID 658 //
45515
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
45516
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
45517
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
45518
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45519
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45520
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45521
      // (fmaxnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)  =>  (VFP_VMAXNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
45522
0
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMD),
45523
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45524
      // GIR_Coverage, 658,
45525
0
      GIR_Done,
45526
    // Label 2374: @146265
45527
0
    GIM_Reject,
45528
    // Label 2367: @146266
45529
0
    GIM_Try, /*On fail goto*//*Label 2375*/ GIMT_Encode4(146305), // Rule ID 1232 //
45530
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON),
45531
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
45532
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
45533
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45534
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45535
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45536
      // (fmaxnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (NEON_VMAXNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
45537
0
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNDf),
45538
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45539
      // GIR_Coverage, 1232,
45540
0
      GIR_Done,
45541
    // Label 2375: @146305
45542
0
    GIM_Reject,
45543
    // Label 2368: @146306
45544
0
    GIM_Try, /*On fail goto*//*Label 2376*/ GIMT_Encode4(146345), // Rule ID 1234 //
45545
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON),
45546
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
45547
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
45548
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45549
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45550
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45551
      // (fmaxnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (NEON_VMAXNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
45552
0
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNDh),
45553
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45554
      // GIR_Coverage, 1234,
45555
0
      GIR_Done,
45556
    // Label 2376: @146345
45557
0
    GIM_Reject,
45558
    // Label 2369: @146346
45559
0
    GIM_Try, /*On fail goto*//*Label 2377*/ GIMT_Encode4(146550),
45560
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
45561
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
45562
0
      GIM_Try, /*On fail goto*//*Label 2378*/ GIMT_Encode4(146446), // Rule ID 4242 //
45563
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
45564
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45565
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45566
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
45567
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
45568
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45569
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
45570
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
45571
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
45572
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45573
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
45574
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
45575
        // (fmaxnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm))  =>  (MVE_VMAXNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm)
45576
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf32),
45577
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
45578
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
45579
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
45580
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45581
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45582
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45583
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45584
0
        GIR_EraseFromParent, /*InsnID*/0,
45585
        // GIR_Coverage, 4242,
45586
0
        GIR_Done,
45587
      // Label 2378: @146446
45588
0
      GIM_Try, /*On fail goto*//*Label 2379*/ GIMT_Encode4(146477), // Rule ID 1233 //
45589
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON),
45590
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45591
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45592
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45593
        // (fmaxnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (NEON_VMAXNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
45594
0
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNQf),
45595
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45596
        // GIR_Coverage, 1233,
45597
0
        GIR_Done,
45598
      // Label 2379: @146477
45599
0
      GIM_Try, /*On fail goto*//*Label 2380*/ GIMT_Encode4(146549), // Rule ID 3136 //
45600
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45601
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45602
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45603
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45604
        // (fmaxnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)  =>  (MVE_VMAXNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
45605
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45606
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45607
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
45608
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf32),
45609
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
45610
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
45611
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
45612
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45613
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45614
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45615
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45616
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45617
0
        GIR_EraseFromParent, /*InsnID*/0,
45618
        // GIR_Coverage, 3136,
45619
0
        GIR_Done,
45620
      // Label 2380: @146549
45621
0
      GIM_Reject,
45622
    // Label 2377: @146550
45623
0
    GIM_Reject,
45624
    // Label 2370: @146551
45625
0
    GIM_Try, /*On fail goto*//*Label 2381*/ GIMT_Encode4(146755),
45626
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
45627
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
45628
0
      GIM_Try, /*On fail goto*//*Label 2382*/ GIMT_Encode4(146651), // Rule ID 4244 //
45629
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
45630
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45631
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45632
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
45633
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
45634
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45635
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
45636
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
45637
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
45638
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45639
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
45640
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
45641
        // (fmaxnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm))  =>  (MVE_VMAXNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm)
45642
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf16),
45643
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
45644
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
45645
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
45646
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45647
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45648
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45649
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45650
0
        GIR_EraseFromParent, /*InsnID*/0,
45651
        // GIR_Coverage, 4244,
45652
0
        GIR_Done,
45653
      // Label 2382: @146651
45654
0
      GIM_Try, /*On fail goto*//*Label 2383*/ GIMT_Encode4(146682), // Rule ID 1235 //
45655
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON),
45656
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45657
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45658
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45659
        // (fmaxnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (NEON_VMAXNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
45660
0
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNQh),
45661
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45662
        // GIR_Coverage, 1235,
45663
0
        GIR_Done,
45664
      // Label 2383: @146682
45665
0
      GIM_Try, /*On fail goto*//*Label 2384*/ GIMT_Encode4(146754), // Rule ID 3391 //
45666
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45667
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45668
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45669
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45670
        // (fmaxnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)  =>  (MVE_VMAXNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
45671
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45672
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45673
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
45674
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf16),
45675
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
45676
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
45677
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
45678
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45679
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45680
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45681
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45682
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45683
0
        GIR_EraseFromParent, /*InsnID*/0,
45684
        // GIR_Coverage, 3391,
45685
0
        GIR_Done,
45686
      // Label 2384: @146754
45687
0
      GIM_Reject,
45688
    // Label 2381: @146755
45689
0
    GIM_Reject,
45690
    // Label 2371: @146756
45691
0
    GIM_Reject,
45692
    // Label 47: @146757
45693
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2391*/ GIMT_Encode4(147552),
45694
0
    /*GILLT_s16*//*Label 2385*/ GIMT_Encode4(146820),
45695
0
    /*GILLT_s32*//*Label 2386*/ GIMT_Encode4(147062), GIMT_Encode4(0), GIMT_Encode4(0),
45696
0
    /*GILLT_v2s32*//*Label 2387*/ GIMT_Encode4(147304), GIMT_Encode4(0), GIMT_Encode4(0),
45697
0
    /*GILLT_v4s16*//*Label 2388*/ GIMT_Encode4(147366),
45698
0
    /*GILLT_v4s32*//*Label 2389*/ GIMT_Encode4(147428), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
45699
0
    /*GILLT_v8s16*//*Label 2390*/ GIMT_Encode4(147490),
45700
    // Label 2385: @146820
45701
0
    GIM_Try, /*On fail goto*//*Label 2392*/ GIMT_Encode4(147061), // Rule ID 2734 //
45702
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
45703
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
45704
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
45705
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45706
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45707
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45708
      // (fminimum:{ *:[f16] } HPR:{ *:[f16] }:$a, HPR:{ *:[f16] }:$b)  =>  (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (VMINhd:{ *:[f64] } (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
45709
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16,
45710
0
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
45711
0
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
45712
0
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
45713
0
      GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
45714
0
      GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
45715
0
      GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16,
45716
0
      GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
45717
0
      GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45718
0
      GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45719
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
45720
0
      GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45721
0
      GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45722
0
      GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
45723
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
45724
0
      GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45725
0
      GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45726
0
      GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
45727
0
      GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
45728
0
      GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
45729
0
      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45730
0
      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45731
0
      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID),
45732
0
      GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45733
0
      GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45734
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
45735
0
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45736
0
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45737
0
      GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
45738
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
45739
0
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45740
0
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45741
0
      GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
45742
0
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
45743
0
      GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
45744
0
      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45745
0
      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45746
0
      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID),
45747
0
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMINhd),
45748
0
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45749
0
      GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
45750
0
      GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
45751
0
      GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
45752
0
      GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45753
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45754
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45755
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45756
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45757
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45758
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45759
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
45760
0
      GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
45761
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45762
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45763
0
      GIR_EraseFromParent, /*InsnID*/0,
45764
      // GIR_Coverage, 2734,
45765
0
      GIR_Done,
45766
    // Label 2392: @147061
45767
0
    GIM_Reject,
45768
    // Label 2386: @147062
45769
0
    GIM_Try, /*On fail goto*//*Label 2393*/ GIMT_Encode4(147303), // Rule ID 2736 //
45770
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
45771
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
45772
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
45773
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45774
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45775
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45776
      // (fminimum:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMINfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
45777
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
45778
0
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
45779
0
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
45780
0
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
45781
0
      GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
45782
0
      GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
45783
0
      GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
45784
0
      GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
45785
0
      GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45786
0
      GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45787
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
45788
0
      GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45789
0
      GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45790
0
      GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
45791
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
45792
0
      GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45793
0
      GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45794
0
      GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
45795
0
      GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
45796
0
      GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
45797
0
      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45798
0
      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45799
0
      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
45800
0
      GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45801
0
      GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45802
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
45803
0
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45804
0
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45805
0
      GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
45806
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
45807
0
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45808
0
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45809
0
      GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
45810
0
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
45811
0
      GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
45812
0
      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45813
0
      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45814
0
      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
45815
0
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMINfd),
45816
0
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45817
0
      GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
45818
0
      GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
45819
0
      GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
45820
0
      GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45821
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45822
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45823
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45824
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45825
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45826
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45827
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
45828
0
      GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
45829
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45830
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45831
0
      GIR_EraseFromParent, /*InsnID*/0,
45832
      // GIR_Coverage, 2736,
45833
0
      GIR_Done,
45834
    // Label 2393: @147303
45835
0
    GIM_Reject,
45836
    // Label 2387: @147304
45837
0
    GIM_Try, /*On fail goto*//*Label 2394*/ GIMT_Encode4(147365), // Rule ID 1248 //
45838
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
45839
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
45840
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
45841
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45842
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45843
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45844
      // (fminimum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VMINfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
45845
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMINfd),
45846
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
45847
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
45848
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
45849
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45850
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45851
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45852
0
      GIR_EraseFromParent, /*InsnID*/0,
45853
      // GIR_Coverage, 1248,
45854
0
      GIR_Done,
45855
    // Label 2394: @147365
45856
0
    GIM_Reject,
45857
    // Label 2388: @147366
45858
0
    GIM_Try, /*On fail goto*//*Label 2395*/ GIMT_Encode4(147427), // Rule ID 1250 //
45859
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
45860
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
45861
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
45862
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45863
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45864
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45865
      // (fminimum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VMINhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
45866
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMINhd),
45867
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
45868
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
45869
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
45870
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45871
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45872
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45873
0
      GIR_EraseFromParent, /*InsnID*/0,
45874
      // GIR_Coverage, 1250,
45875
0
      GIR_Done,
45876
    // Label 2395: @147427
45877
0
    GIM_Reject,
45878
    // Label 2389: @147428
45879
0
    GIM_Try, /*On fail goto*//*Label 2396*/ GIMT_Encode4(147489), // Rule ID 1249 //
45880
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
45881
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
45882
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
45883
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45884
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45885
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45886
      // (fminimum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VMINfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
45887
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMINfq),
45888
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
45889
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
45890
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
45891
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45892
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45893
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45894
0
      GIR_EraseFromParent, /*InsnID*/0,
45895
      // GIR_Coverage, 1249,
45896
0
      GIR_Done,
45897
    // Label 2396: @147489
45898
0
    GIM_Reject,
45899
    // Label 2390: @147490
45900
0
    GIM_Try, /*On fail goto*//*Label 2397*/ GIMT_Encode4(147551), // Rule ID 1251 //
45901
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
45902
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
45903
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
45904
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45905
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45906
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45907
      // (fminimum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VMINhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
45908
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMINhq),
45909
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
45910
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
45911
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
45912
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45913
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45914
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45915
0
      GIR_EraseFromParent, /*InsnID*/0,
45916
      // GIR_Coverage, 1251,
45917
0
      GIR_Done,
45918
    // Label 2397: @147551
45919
0
    GIM_Reject,
45920
    // Label 2391: @147552
45921
0
    GIM_Reject,
45922
    // Label 48: @147553
45923
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2404*/ GIMT_Encode4(148348),
45924
0
    /*GILLT_s16*//*Label 2398*/ GIMT_Encode4(147616),
45925
0
    /*GILLT_s32*//*Label 2399*/ GIMT_Encode4(147858), GIMT_Encode4(0), GIMT_Encode4(0),
45926
0
    /*GILLT_v2s32*//*Label 2400*/ GIMT_Encode4(148100), GIMT_Encode4(0), GIMT_Encode4(0),
45927
0
    /*GILLT_v4s16*//*Label 2401*/ GIMT_Encode4(148162),
45928
0
    /*GILLT_v4s32*//*Label 2402*/ GIMT_Encode4(148224), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
45929
0
    /*GILLT_v8s16*//*Label 2403*/ GIMT_Encode4(148286),
45930
    // Label 2398: @147616
45931
0
    GIM_Try, /*On fail goto*//*Label 2405*/ GIMT_Encode4(147857), // Rule ID 2733 //
45932
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
45933
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
45934
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
45935
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45936
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45937
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45938
      // (fmaximum:{ *:[f16] } HPR:{ *:[f16] }:$a, HPR:{ *:[f16] }:$b)  =>  (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (VMAXhd:{ *:[f64] } (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
45939
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16,
45940
0
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
45941
0
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
45942
0
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
45943
0
      GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
45944
0
      GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
45945
0
      GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16,
45946
0
      GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
45947
0
      GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45948
0
      GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45949
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
45950
0
      GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45951
0
      GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45952
0
      GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
45953
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
45954
0
      GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45955
0
      GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45956
0
      GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
45957
0
      GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
45958
0
      GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
45959
0
      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45960
0
      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45961
0
      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID),
45962
0
      GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45963
0
      GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45964
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
45965
0
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45966
0
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45967
0
      GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
45968
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
45969
0
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45970
0
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45971
0
      GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
45972
0
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
45973
0
      GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
45974
0
      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45975
0
      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45976
0
      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID),
45977
0
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMAXhd),
45978
0
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45979
0
      GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
45980
0
      GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
45981
0
      GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
45982
0
      GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45983
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45984
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45985
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45986
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45987
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45988
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45989
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
45990
0
      GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
45991
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45992
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45993
0
      GIR_EraseFromParent, /*InsnID*/0,
45994
      // GIR_Coverage, 2733,
45995
0
      GIR_Done,
45996
    // Label 2405: @147857
45997
0
    GIM_Reject,
45998
    // Label 2399: @147858
45999
0
    GIM_Try, /*On fail goto*//*Label 2406*/ GIMT_Encode4(148099), // Rule ID 2735 //
46000
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46001
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
46002
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
46003
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46004
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46005
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46006
      // (fmaximum:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMAXfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
46007
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
46008
0
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
46009
0
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
46010
0
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
46011
0
      GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
46012
0
      GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
46013
0
      GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
46014
0
      GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
46015
0
      GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46016
0
      GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46017
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
46018
0
      GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46019
0
      GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46020
0
      GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
46021
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
46022
0
      GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
46023
0
      GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46024
0
      GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
46025
0
      GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
46026
0
      GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
46027
0
      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46028
0
      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46029
0
      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
46030
0
      GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46031
0
      GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46032
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
46033
0
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46034
0
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46035
0
      GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
46036
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
46037
0
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
46038
0
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46039
0
      GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
46040
0
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
46041
0
      GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
46042
0
      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46043
0
      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46044
0
      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
46045
0
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMAXfd),
46046
0
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46047
0
      GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
46048
0
      GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
46049
0
      GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
46050
0
      GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46051
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46052
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46053
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46054
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
46055
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
46056
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46057
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
46058
0
      GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
46059
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
46060
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46061
0
      GIR_EraseFromParent, /*InsnID*/0,
46062
      // GIR_Coverage, 2735,
46063
0
      GIR_Done,
46064
    // Label 2406: @148099
46065
0
    GIM_Reject,
46066
    // Label 2400: @148100
46067
0
    GIM_Try, /*On fail goto*//*Label 2407*/ GIMT_Encode4(148161), // Rule ID 1228 //
46068
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46069
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
46070
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
46071
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46072
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46073
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46074
      // (fmaximum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VMAXfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
46075
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMAXfd),
46076
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
46077
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46078
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46079
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46080
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46081
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46082
0
      GIR_EraseFromParent, /*InsnID*/0,
46083
      // GIR_Coverage, 1228,
46084
0
      GIR_Done,
46085
    // Label 2407: @148161
46086
0
    GIM_Reject,
46087
    // Label 2401: @148162
46088
0
    GIM_Try, /*On fail goto*//*Label 2408*/ GIMT_Encode4(148223), // Rule ID 1230 //
46089
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
46090
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
46091
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
46092
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46093
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46094
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46095
      // (fmaximum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VMAXhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
46096
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMAXhd),
46097
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
46098
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46099
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46100
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46101
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46102
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46103
0
      GIR_EraseFromParent, /*InsnID*/0,
46104
      // GIR_Coverage, 1230,
46105
0
      GIR_Done,
46106
    // Label 2408: @148223
46107
0
    GIM_Reject,
46108
    // Label 2402: @148224
46109
0
    GIM_Try, /*On fail goto*//*Label 2409*/ GIMT_Encode4(148285), // Rule ID 1229 //
46110
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46111
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
46112
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
46113
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46114
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46115
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46116
      // (fmaximum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VMAXfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
46117
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMAXfq),
46118
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
46119
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46120
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46121
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46122
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46123
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46124
0
      GIR_EraseFromParent, /*InsnID*/0,
46125
      // GIR_Coverage, 1229,
46126
0
      GIR_Done,
46127
    // Label 2409: @148285
46128
0
    GIM_Reject,
46129
    // Label 2403: @148286
46130
0
    GIM_Try, /*On fail goto*//*Label 2410*/ GIMT_Encode4(148347), // Rule ID 1231 //
46131
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
46132
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
46133
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
46134
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46135
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46136
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46137
      // (fmaximum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VMAXhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
46138
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMAXhq),
46139
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
46140
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46141
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46142
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46143
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46144
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46145
0
      GIR_EraseFromParent, /*InsnID*/0,
46146
      // GIR_Coverage, 1231,
46147
0
      GIR_Done,
46148
    // Label 2410: @148347
46149
0
    GIM_Reject,
46150
    // Label 2404: @148348
46151
0
    GIM_Reject,
46152
    // Label 49: @148349
46153
0
    GIM_Try, /*On fail goto*//*Label 2411*/ GIMT_Encode4(148389), // Rule ID 2423 //
46154
0
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
46155
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
46156
      // (get_fpenv:{ *:[i32] })  =>  (VMRS:{ *:[i32] })
46157
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMRS),
46158
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rt]
46159
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46160
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46161
0
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
46162
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46163
0
      GIR_EraseFromParent, /*InsnID*/0,
46164
      // GIR_Coverage, 2423,
46165
0
      GIR_Done,
46166
    // Label 2411: @148389
46167
0
    GIM_Reject,
46168
    // Label 50: @148390
46169
0
    GIM_Try, /*On fail goto*//*Label 2412*/ GIMT_Encode4(148433), // Rule ID 2424 //
46170
0
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
46171
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
46172
      // (set_fpenv GPRnopc:{ *:[i32] }:$Rt)  =>  (VMSR GPRnopc:{ *:[i32] }:$Rt)
46173
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMSR),
46174
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
46175
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46176
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46177
0
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0,
46178
0
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
46179
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46180
0
      GIR_EraseFromParent, /*InsnID*/0,
46181
      // GIR_Coverage, 2424,
46182
0
      GIR_Done,
46183
    // Label 2412: @148433
46184
0
    GIM_Reject,
46185
    // Label 51: @148434
46186
0
    GIM_Try, /*On fail goto*//*Label 2413*/ GIMT_Encode4(148502), // Rule ID 2425 //
46187
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
46188
      // (reset_fpenv)  =>  (VMSR (MOVi:{ *:[i32] } 0:{ *:[i32] }))
46189
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
46190
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MOVi),
46191
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46192
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
46193
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
46194
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46195
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46196
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
46197
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMSR),
46198
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46199
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46200
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46201
0
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0,
46202
0
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
46203
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46204
0
      GIR_EraseFromParent, /*InsnID*/0,
46205
      // GIR_Coverage, 2425,
46206
0
      GIR_Done,
46207
    // Label 2413: @148502
46208
0
    GIM_Try, /*On fail goto*//*Label 2414*/ GIMT_Encode4(148564), // Rule ID 2426 //
46209
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb),
46210
      // (reset_fpenv)  =>  (VMSR (tMOVi8:{ *:[i32] } 0:{ *:[i32] }))
46211
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
46212
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8),
46213
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46214
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
46215
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
46216
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46217
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
46218
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMSR),
46219
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46220
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46221
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46222
0
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0,
46223
0
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
46224
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46225
0
      GIR_EraseFromParent, /*InsnID*/0,
46226
      // GIR_Coverage, 2426,
46227
0
      GIR_Done,
46228
    // Label 2414: @148564
46229
0
    GIM_Reject,
46230
    // Label 52: @148565
46231
0
    GIM_Try, /*On fail goto*//*Label 2415*/ GIMT_Encode4(148605), // Rule ID 2427 //
46232
0
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
46233
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
46234
      // (get_fpmode:{ *:[i32] })  =>  (VMRS:{ *:[i32] })
46235
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMRS),
46236
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rt]
46237
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46238
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46239
0
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
46240
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46241
0
      GIR_EraseFromParent, /*InsnID*/0,
46242
      // GIR_Coverage, 2427,
46243
0
      GIR_Done,
46244
    // Label 2415: @148605
46245
0
    GIM_Reject,
46246
    // Label 53: @148606
46247
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2422*/ GIMT_Encode4(149271),
46248
0
    /*GILLT_v2s32*//*Label 2416*/ GIMT_Encode4(148665), GIMT_Encode4(0), GIMT_Encode4(0),
46249
0
    /*GILLT_v4s16*//*Label 2417*/ GIMT_Encode4(148727),
46250
0
    /*GILLT_v4s32*//*Label 2418*/ GIMT_Encode4(148789), GIMT_Encode4(0), GIMT_Encode4(0),
46251
0
    /*GILLT_v8s8*//*Label 2419*/ GIMT_Encode4(148929),
46252
0
    /*GILLT_v8s16*//*Label 2420*/ GIMT_Encode4(148991), GIMT_Encode4(0), GIMT_Encode4(0),
46253
0
    /*GILLT_v16s8*//*Label 2421*/ GIMT_Encode4(149131),
46254
    // Label 2416: @148665
46255
0
    GIM_Try, /*On fail goto*//*Label 2423*/ GIMT_Encode4(148726), // Rule ID 1237 //
46256
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46257
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
46258
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
46259
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46260
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46261
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46262
      // (smin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VMINsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
46263
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMINsv2i32),
46264
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
46265
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46266
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46267
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46268
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46269
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46270
0
      GIR_EraseFromParent, /*InsnID*/0,
46271
      // GIR_Coverage, 1237,
46272
0
      GIR_Done,
46273
    // Label 2423: @148726
46274
0
    GIM_Reject,
46275
    // Label 2417: @148727
46276
0
    GIM_Try, /*On fail goto*//*Label 2424*/ GIMT_Encode4(148788), // Rule ID 1236 //
46277
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46278
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
46279
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
46280
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46281
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46282
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46283
      // (smin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VMINsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
46284
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMINsv4i16),
46285
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
46286
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46287
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46288
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46289
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46290
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46291
0
      GIR_EraseFromParent, /*InsnID*/0,
46292
      // GIR_Coverage, 1236,
46293
0
      GIR_Done,
46294
    // Label 2424: @148788
46295
0
    GIM_Reject,
46296
    // Label 2418: @148789
46297
0
    GIM_Try, /*On fail goto*//*Label 2425*/ GIMT_Encode4(148928),
46298
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
46299
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
46300
0
      GIM_Try, /*On fail goto*//*Label 2426*/ GIMT_Encode4(148855), // Rule ID 1239 //
46301
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46302
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46303
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46304
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46305
        // (smin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VMINsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
46306
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMINsv4i32),
46307
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
46308
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46309
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46310
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46311
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46312
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46313
0
        GIR_EraseFromParent, /*InsnID*/0,
46314
        // GIR_Coverage, 1239,
46315
0
        GIR_Done,
46316
      // Label 2426: @148855
46317
0
      GIM_Try, /*On fail goto*//*Label 2427*/ GIMT_Encode4(148927), // Rule ID 3406 //
46318
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46319
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46320
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46321
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46322
        // (smin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VMINs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
46323
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46324
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46325
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
46326
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs32),
46327
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
46328
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
46329
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
46330
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46331
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46332
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46333
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46334
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46335
0
        GIR_EraseFromParent, /*InsnID*/0,
46336
        // GIR_Coverage, 3406,
46337
0
        GIR_Done,
46338
      // Label 2427: @148927
46339
0
      GIM_Reject,
46340
    // Label 2425: @148928
46341
0
    GIM_Reject,
46342
    // Label 2419: @148929
46343
0
    GIM_Try, /*On fail goto*//*Label 2428*/ GIMT_Encode4(148990), // Rule ID 1240 //
46344
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46345
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
46346
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
46347
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46348
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46349
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46350
      // (smin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMINsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
46351
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMINsv8i8),
46352
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
46353
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46354
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46355
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46356
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46357
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46358
0
      GIR_EraseFromParent, /*InsnID*/0,
46359
      // GIR_Coverage, 1240,
46360
0
      GIR_Done,
46361
    // Label 2428: @148990
46362
0
    GIM_Reject,
46363
    // Label 2420: @148991
46364
0
    GIM_Try, /*On fail goto*//*Label 2429*/ GIMT_Encode4(149130),
46365
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
46366
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
46367
0
      GIM_Try, /*On fail goto*//*Label 2430*/ GIMT_Encode4(149057), // Rule ID 1238 //
46368
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46369
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46370
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46371
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46372
        // (smin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VMINsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
46373
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMINsv8i16),
46374
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
46375
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46376
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46377
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46378
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46379
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46380
0
        GIR_EraseFromParent, /*InsnID*/0,
46381
        // GIR_Coverage, 1238,
46382
0
        GIR_Done,
46383
      // Label 2430: @149057
46384
0
      GIM_Try, /*On fail goto*//*Label 2431*/ GIMT_Encode4(149129), // Rule ID 3403 //
46385
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46386
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46387
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46388
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46389
        // (smin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VMINs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
46390
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46391
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46392
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
46393
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs16),
46394
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
46395
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
46396
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
46397
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46398
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46399
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46400
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46401
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46402
0
        GIR_EraseFromParent, /*InsnID*/0,
46403
        // GIR_Coverage, 3403,
46404
0
        GIR_Done,
46405
      // Label 2431: @149129
46406
0
      GIM_Reject,
46407
    // Label 2429: @149130
46408
0
    GIM_Reject,
46409
    // Label 2421: @149131
46410
0
    GIM_Try, /*On fail goto*//*Label 2432*/ GIMT_Encode4(149270),
46411
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
46412
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
46413
0
      GIM_Try, /*On fail goto*//*Label 2433*/ GIMT_Encode4(149197), // Rule ID 1241 //
46414
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46415
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46416
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46417
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46418
        // (smin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VMINsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
46419
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMINsv16i8),
46420
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
46421
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46422
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46423
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46424
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46425
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46426
0
        GIR_EraseFromParent, /*InsnID*/0,
46427
        // GIR_Coverage, 1241,
46428
0
        GIR_Done,
46429
      // Label 2433: @149197
46430
0
      GIM_Try, /*On fail goto*//*Label 2434*/ GIMT_Encode4(149269), // Rule ID 3400 //
46431
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46432
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46433
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46434
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46435
        // (smin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VMINs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
46436
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46437
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46438
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
46439
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs8),
46440
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
46441
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
46442
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
46443
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46444
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46445
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46446
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46447
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46448
0
        GIR_EraseFromParent, /*InsnID*/0,
46449
        // GIR_Coverage, 3400,
46450
0
        GIR_Done,
46451
      // Label 2434: @149269
46452
0
      GIM_Reject,
46453
    // Label 2432: @149270
46454
0
    GIM_Reject,
46455
    // Label 2422: @149271
46456
0
    GIM_Reject,
46457
    // Label 54: @149272
46458
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2441*/ GIMT_Encode4(149937),
46459
0
    /*GILLT_v2s32*//*Label 2435*/ GIMT_Encode4(149331), GIMT_Encode4(0), GIMT_Encode4(0),
46460
0
    /*GILLT_v4s16*//*Label 2436*/ GIMT_Encode4(149393),
46461
0
    /*GILLT_v4s32*//*Label 2437*/ GIMT_Encode4(149455), GIMT_Encode4(0), GIMT_Encode4(0),
46462
0
    /*GILLT_v8s8*//*Label 2438*/ GIMT_Encode4(149595),
46463
0
    /*GILLT_v8s16*//*Label 2439*/ GIMT_Encode4(149657), GIMT_Encode4(0), GIMT_Encode4(0),
46464
0
    /*GILLT_v16s8*//*Label 2440*/ GIMT_Encode4(149797),
46465
    // Label 2435: @149331
46466
0
    GIM_Try, /*On fail goto*//*Label 2442*/ GIMT_Encode4(149392), // Rule ID 1217 //
46467
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46468
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
46469
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
46470
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46471
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46472
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46473
      // (smax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VMAXsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
46474
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMAXsv2i32),
46475
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
46476
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46477
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46478
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46479
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46480
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46481
0
      GIR_EraseFromParent, /*InsnID*/0,
46482
      // GIR_Coverage, 1217,
46483
0
      GIR_Done,
46484
    // Label 2442: @149392
46485
0
    GIM_Reject,
46486
    // Label 2436: @149393
46487
0
    GIM_Try, /*On fail goto*//*Label 2443*/ GIMT_Encode4(149454), // Rule ID 1216 //
46488
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46489
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
46490
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
46491
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46492
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46493
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46494
      // (smax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VMAXsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
46495
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMAXsv4i16),
46496
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
46497
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46498
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46499
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46500
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46501
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46502
0
      GIR_EraseFromParent, /*InsnID*/0,
46503
      // GIR_Coverage, 1216,
46504
0
      GIR_Done,
46505
    // Label 2443: @149454
46506
0
    GIM_Reject,
46507
    // Label 2437: @149455
46508
0
    GIM_Try, /*On fail goto*//*Label 2444*/ GIMT_Encode4(149594),
46509
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
46510
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
46511
0
      GIM_Try, /*On fail goto*//*Label 2445*/ GIMT_Encode4(149521), // Rule ID 1219 //
46512
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46513
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46514
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46515
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46516
        // (smax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VMAXsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
46517
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMAXsv4i32),
46518
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
46519
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46520
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46521
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46522
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46523
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46524
0
        GIR_EraseFromParent, /*InsnID*/0,
46525
        // GIR_Coverage, 1219,
46526
0
        GIR_Done,
46527
      // Label 2445: @149521
46528
0
      GIM_Try, /*On fail goto*//*Label 2446*/ GIMT_Encode4(149593), // Rule ID 3424 //
46529
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46530
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46531
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46532
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46533
        // (smax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VMAXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
46534
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46535
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46536
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
46537
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs32),
46538
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
46539
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
46540
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
46541
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46542
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46543
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46544
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46545
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46546
0
        GIR_EraseFromParent, /*InsnID*/0,
46547
        // GIR_Coverage, 3424,
46548
0
        GIR_Done,
46549
      // Label 2446: @149593
46550
0
      GIM_Reject,
46551
    // Label 2444: @149594
46552
0
    GIM_Reject,
46553
    // Label 2438: @149595
46554
0
    GIM_Try, /*On fail goto*//*Label 2447*/ GIMT_Encode4(149656), // Rule ID 1220 //
46555
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46556
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
46557
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
46558
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46559
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46560
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46561
      // (smax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMAXsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
46562
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMAXsv8i8),
46563
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
46564
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46565
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46566
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46567
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46568
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46569
0
      GIR_EraseFromParent, /*InsnID*/0,
46570
      // GIR_Coverage, 1220,
46571
0
      GIR_Done,
46572
    // Label 2447: @149656
46573
0
    GIM_Reject,
46574
    // Label 2439: @149657
46575
0
    GIM_Try, /*On fail goto*//*Label 2448*/ GIMT_Encode4(149796),
46576
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
46577
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
46578
0
      GIM_Try, /*On fail goto*//*Label 2449*/ GIMT_Encode4(149723), // Rule ID 1218 //
46579
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46580
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46581
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46582
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46583
        // (smax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VMAXsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
46584
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMAXsv8i16),
46585
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
46586
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46587
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46588
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46589
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46590
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46591
0
        GIR_EraseFromParent, /*InsnID*/0,
46592
        // GIR_Coverage, 1218,
46593
0
        GIR_Done,
46594
      // Label 2449: @149723
46595
0
      GIM_Try, /*On fail goto*//*Label 2450*/ GIMT_Encode4(149795), // Rule ID 3421 //
46596
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46597
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46598
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46599
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46600
        // (smax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VMAXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
46601
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46602
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46603
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
46604
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs16),
46605
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
46606
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
46607
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
46608
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46609
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46610
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46611
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46612
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46613
0
        GIR_EraseFromParent, /*InsnID*/0,
46614
        // GIR_Coverage, 3421,
46615
0
        GIR_Done,
46616
      // Label 2450: @149795
46617
0
      GIM_Reject,
46618
    // Label 2448: @149796
46619
0
    GIM_Reject,
46620
    // Label 2440: @149797
46621
0
    GIM_Try, /*On fail goto*//*Label 2451*/ GIMT_Encode4(149936),
46622
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
46623
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
46624
0
      GIM_Try, /*On fail goto*//*Label 2452*/ GIMT_Encode4(149863), // Rule ID 1221 //
46625
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46626
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46627
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46628
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46629
        // (smax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VMAXsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
46630
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMAXsv16i8),
46631
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
46632
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46633
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46634
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46635
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46636
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46637
0
        GIR_EraseFromParent, /*InsnID*/0,
46638
        // GIR_Coverage, 1221,
46639
0
        GIR_Done,
46640
      // Label 2452: @149863
46641
0
      GIM_Try, /*On fail goto*//*Label 2453*/ GIMT_Encode4(149935), // Rule ID 3418 //
46642
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46643
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46644
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46645
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46646
        // (smax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VMAXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
46647
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46648
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46649
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
46650
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs8),
46651
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
46652
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
46653
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
46654
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46655
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46656
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46657
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46658
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46659
0
        GIR_EraseFromParent, /*InsnID*/0,
46660
        // GIR_Coverage, 3418,
46661
0
        GIR_Done,
46662
      // Label 2453: @149935
46663
0
      GIM_Reject,
46664
    // Label 2451: @149936
46665
0
    GIM_Reject,
46666
    // Label 2441: @149937
46667
0
    GIM_Reject,
46668
    // Label 55: @149938
46669
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2460*/ GIMT_Encode4(151041),
46670
0
    /*GILLT_v2s32*//*Label 2454*/ GIMT_Encode4(149997), GIMT_Encode4(0), GIMT_Encode4(0),
46671
0
    /*GILLT_v4s16*//*Label 2455*/ GIMT_Encode4(150059),
46672
0
    /*GILLT_v4s32*//*Label 2456*/ GIMT_Encode4(150121), GIMT_Encode4(0), GIMT_Encode4(0),
46673
0
    /*GILLT_v8s8*//*Label 2457*/ GIMT_Encode4(150407),
46674
0
    /*GILLT_v8s16*//*Label 2458*/ GIMT_Encode4(150469), GIMT_Encode4(0), GIMT_Encode4(0),
46675
0
    /*GILLT_v16s8*//*Label 2459*/ GIMT_Encode4(150755),
46676
    // Label 2454: @149997
46677
0
    GIM_Try, /*On fail goto*//*Label 2461*/ GIMT_Encode4(150058), // Rule ID 1243 //
46678
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46679
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
46680
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
46681
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46682
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46683
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46684
      // (umin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VMINuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
46685
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMINuv2i32),
46686
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
46687
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46688
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46689
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46690
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46691
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46692
0
      GIR_EraseFromParent, /*InsnID*/0,
46693
      // GIR_Coverage, 1243,
46694
0
      GIR_Done,
46695
    // Label 2461: @150058
46696
0
    GIM_Reject,
46697
    // Label 2455: @150059
46698
0
    GIM_Try, /*On fail goto*//*Label 2462*/ GIMT_Encode4(150120), // Rule ID 1242 //
46699
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46700
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
46701
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
46702
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46703
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46704
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46705
      // (umin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VMINuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
46706
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMINuv4i16),
46707
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
46708
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46709
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46710
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46711
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46712
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46713
0
      GIR_EraseFromParent, /*InsnID*/0,
46714
      // GIR_Coverage, 1242,
46715
0
      GIR_Done,
46716
    // Label 2462: @150120
46717
0
    GIM_Reject,
46718
    // Label 2456: @150121
46719
0
    GIM_Try, /*On fail goto*//*Label 2463*/ GIMT_Encode4(150406),
46720
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
46721
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
46722
0
      GIM_Try, /*On fail goto*//*Label 2464*/ GIMT_Encode4(150207), // Rule ID 6168 //
46723
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46724
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46725
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46726
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
46727
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
46728
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46729
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46730
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
46731
        // (umin:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd)  =>  (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
46732
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs32),
46733
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
46734
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
46735
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
46736
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46737
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46738
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46739
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46740
0
        GIR_EraseFromParent, /*InsnID*/0,
46741
        // GIR_Coverage, 6168,
46742
0
        GIR_Done,
46743
      // Label 2464: @150207
46744
0
      GIM_Try, /*On fail goto*//*Label 2465*/ GIMT_Encode4(150280), // Rule ID 3821 //
46745
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46746
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46747
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46748
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
46749
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
46750
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
46751
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46752
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
46753
        // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm))  =>  (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
46754
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs32),
46755
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
46756
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
46757
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
46758
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46759
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46760
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46761
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46762
0
        GIR_EraseFromParent, /*InsnID*/0,
46763
        // GIR_Coverage, 3821,
46764
0
        GIR_Done,
46765
      // Label 2465: @150280
46766
0
      GIM_Try, /*On fail goto*//*Label 2466*/ GIMT_Encode4(150333), // Rule ID 1245 //
46767
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46768
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46769
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46770
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46771
        // (umin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VMINuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
46772
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMINuv4i32),
46773
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
46774
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46775
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46776
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46777
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46778
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46779
0
        GIR_EraseFromParent, /*InsnID*/0,
46780
        // GIR_Coverage, 1245,
46781
0
        GIR_Done,
46782
      // Label 2466: @150333
46783
0
      GIM_Try, /*On fail goto*//*Label 2467*/ GIMT_Encode4(150405), // Rule ID 3415 //
46784
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46785
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46786
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46787
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46788
        // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VMINu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
46789
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46790
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46791
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
46792
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu32),
46793
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
46794
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
46795
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
46796
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46797
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46798
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46799
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46800
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46801
0
        GIR_EraseFromParent, /*InsnID*/0,
46802
        // GIR_Coverage, 3415,
46803
0
        GIR_Done,
46804
      // Label 2467: @150405
46805
0
      GIM_Reject,
46806
    // Label 2463: @150406
46807
0
    GIM_Reject,
46808
    // Label 2457: @150407
46809
0
    GIM_Try, /*On fail goto*//*Label 2468*/ GIMT_Encode4(150468), // Rule ID 1246 //
46810
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46811
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
46812
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
46813
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46814
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46815
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46816
      // (umin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMINuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
46817
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMINuv8i8),
46818
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
46819
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46820
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46821
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46822
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46823
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46824
0
      GIR_EraseFromParent, /*InsnID*/0,
46825
      // GIR_Coverage, 1246,
46826
0
      GIR_Done,
46827
    // Label 2468: @150468
46828
0
    GIM_Reject,
46829
    // Label 2458: @150469
46830
0
    GIM_Try, /*On fail goto*//*Label 2469*/ GIMT_Encode4(150754),
46831
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
46832
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
46833
0
      GIM_Try, /*On fail goto*//*Label 2470*/ GIMT_Encode4(150555), // Rule ID 6167 //
46834
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46835
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46836
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46837
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
46838
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
46839
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46840
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46841
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
46842
        // (umin:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd)  =>  (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
46843
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs16),
46844
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
46845
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
46846
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
46847
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46848
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46849
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46850
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46851
0
        GIR_EraseFromParent, /*InsnID*/0,
46852
        // GIR_Coverage, 6167,
46853
0
        GIR_Done,
46854
      // Label 2470: @150555
46855
0
      GIM_Try, /*On fail goto*//*Label 2471*/ GIMT_Encode4(150628), // Rule ID 3819 //
46856
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46857
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46858
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46859
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
46860
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
46861
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
46862
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46863
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
46864
        // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm))  =>  (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
46865
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs16),
46866
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
46867
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
46868
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
46869
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46870
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46871
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46872
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46873
0
        GIR_EraseFromParent, /*InsnID*/0,
46874
        // GIR_Coverage, 3819,
46875
0
        GIR_Done,
46876
      // Label 2471: @150628
46877
0
      GIM_Try, /*On fail goto*//*Label 2472*/ GIMT_Encode4(150681), // Rule ID 1244 //
46878
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46879
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46880
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46881
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46882
        // (umin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VMINuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
46883
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMINuv8i16),
46884
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
46885
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46886
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46887
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46888
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46889
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46890
0
        GIR_EraseFromParent, /*InsnID*/0,
46891
        // GIR_Coverage, 1244,
46892
0
        GIR_Done,
46893
      // Label 2472: @150681
46894
0
      GIM_Try, /*On fail goto*//*Label 2473*/ GIMT_Encode4(150753), // Rule ID 3412 //
46895
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46896
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46897
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46898
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46899
        // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VMINu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
46900
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46901
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46902
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
46903
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu16),
46904
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
46905
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
46906
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
46907
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46908
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46909
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46910
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46911
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46912
0
        GIR_EraseFromParent, /*InsnID*/0,
46913
        // GIR_Coverage, 3412,
46914
0
        GIR_Done,
46915
      // Label 2473: @150753
46916
0
      GIM_Reject,
46917
    // Label 2469: @150754
46918
0
    GIM_Reject,
46919
    // Label 2459: @150755
46920
0
    GIM_Try, /*On fail goto*//*Label 2474*/ GIMT_Encode4(151040),
46921
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
46922
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
46923
0
      GIM_Try, /*On fail goto*//*Label 2475*/ GIMT_Encode4(150841), // Rule ID 6166 //
46924
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46925
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46926
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46927
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
46928
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
46929
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46930
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46931
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
46932
        // (umin:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd)  =>  (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
46933
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs8),
46934
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
46935
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
46936
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
46937
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46938
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46939
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46940
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46941
0
        GIR_EraseFromParent, /*InsnID*/0,
46942
        // GIR_Coverage, 6166,
46943
0
        GIR_Done,
46944
      // Label 2475: @150841
46945
0
      GIM_Try, /*On fail goto*//*Label 2476*/ GIMT_Encode4(150914), // Rule ID 3817 //
46946
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46947
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46948
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46949
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
46950
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
46951
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
46952
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46953
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
46954
        // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm))  =>  (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
46955
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs8),
46956
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
46957
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
46958
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
46959
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46960
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46961
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46962
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46963
0
        GIR_EraseFromParent, /*InsnID*/0,
46964
        // GIR_Coverage, 3817,
46965
0
        GIR_Done,
46966
      // Label 2476: @150914
46967
0
      GIM_Try, /*On fail goto*//*Label 2477*/ GIMT_Encode4(150967), // Rule ID 1247 //
46968
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46969
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46970
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46971
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46972
        // (umin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VMINuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
46973
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMINuv16i8),
46974
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
46975
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46976
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46977
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46978
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46979
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46980
0
        GIR_EraseFromParent, /*InsnID*/0,
46981
        // GIR_Coverage, 1247,
46982
0
        GIR_Done,
46983
      // Label 2477: @150967
46984
0
      GIM_Try, /*On fail goto*//*Label 2478*/ GIMT_Encode4(151039), // Rule ID 3409 //
46985
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46986
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46987
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46988
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46989
        // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VMINu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
46990
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46991
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46992
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
46993
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu8),
46994
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
46995
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
46996
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
46997
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46998
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46999
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47000
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47001
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47002
0
        GIR_EraseFromParent, /*InsnID*/0,
47003
        // GIR_Coverage, 3409,
47004
0
        GIR_Done,
47005
      // Label 2478: @151039
47006
0
      GIM_Reject,
47007
    // Label 2474: @151040
47008
0
    GIM_Reject,
47009
    // Label 2460: @151041
47010
0
    GIM_Reject,
47011
    // Label 56: @151042
47012
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2485*/ GIMT_Encode4(152145),
47013
0
    /*GILLT_v2s32*//*Label 2479*/ GIMT_Encode4(151101), GIMT_Encode4(0), GIMT_Encode4(0),
47014
0
    /*GILLT_v4s16*//*Label 2480*/ GIMT_Encode4(151163),
47015
0
    /*GILLT_v4s32*//*Label 2481*/ GIMT_Encode4(151225), GIMT_Encode4(0), GIMT_Encode4(0),
47016
0
    /*GILLT_v8s8*//*Label 2482*/ GIMT_Encode4(151511),
47017
0
    /*GILLT_v8s16*//*Label 2483*/ GIMT_Encode4(151573), GIMT_Encode4(0), GIMT_Encode4(0),
47018
0
    /*GILLT_v16s8*//*Label 2484*/ GIMT_Encode4(151859),
47019
    // Label 2479: @151101
47020
0
    GIM_Try, /*On fail goto*//*Label 2486*/ GIMT_Encode4(151162), // Rule ID 1223 //
47021
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47022
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
47023
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
47024
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47025
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47026
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47027
      // (umax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VMAXuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
47028
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMAXuv2i32),
47029
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
47030
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
47031
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
47032
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47033
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47034
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47035
0
      GIR_EraseFromParent, /*InsnID*/0,
47036
      // GIR_Coverage, 1223,
47037
0
      GIR_Done,
47038
    // Label 2486: @151162
47039
0
    GIM_Reject,
47040
    // Label 2480: @151163
47041
0
    GIM_Try, /*On fail goto*//*Label 2487*/ GIMT_Encode4(151224), // Rule ID 1222 //
47042
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47043
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
47044
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
47045
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47046
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47047
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47048
      // (umax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VMAXuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
47049
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMAXuv4i16),
47050
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
47051
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
47052
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
47053
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47054
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47055
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47056
0
      GIR_EraseFromParent, /*InsnID*/0,
47057
      // GIR_Coverage, 1222,
47058
0
      GIR_Done,
47059
    // Label 2487: @151224
47060
0
    GIM_Reject,
47061
    // Label 2481: @151225
47062
0
    GIM_Try, /*On fail goto*//*Label 2488*/ GIMT_Encode4(151510),
47063
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
47064
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
47065
0
      GIM_Try, /*On fail goto*//*Label 2489*/ GIMT_Encode4(151311), // Rule ID 6171 //
47066
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47067
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47068
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47069
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47070
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
47071
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47072
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47073
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
47074
        // (umax:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd)  =>  (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
47075
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs32),
47076
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
47077
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
47078
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47079
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47080
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47081
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47082
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47083
0
        GIR_EraseFromParent, /*InsnID*/0,
47084
        // GIR_Coverage, 6171,
47085
0
        GIR_Done,
47086
      // Label 2489: @151311
47087
0
      GIM_Try, /*On fail goto*//*Label 2490*/ GIMT_Encode4(151384), // Rule ID 3827 //
47088
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47089
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47090
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47091
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47092
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47093
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
47094
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47095
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
47096
        // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm))  =>  (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
47097
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs32),
47098
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
47099
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
47100
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47101
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47102
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47103
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47104
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47105
0
        GIR_EraseFromParent, /*InsnID*/0,
47106
        // GIR_Coverage, 3827,
47107
0
        GIR_Done,
47108
      // Label 2490: @151384
47109
0
      GIM_Try, /*On fail goto*//*Label 2491*/ GIMT_Encode4(151437), // Rule ID 1225 //
47110
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47111
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47112
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47113
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47114
        // (umax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VMAXuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
47115
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMAXuv4i32),
47116
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
47117
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
47118
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
47119
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47120
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47121
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47122
0
        GIR_EraseFromParent, /*InsnID*/0,
47123
        // GIR_Coverage, 1225,
47124
0
        GIR_Done,
47125
      // Label 2491: @151437
47126
0
      GIM_Try, /*On fail goto*//*Label 2492*/ GIMT_Encode4(151509), // Rule ID 3433 //
47127
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47128
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47129
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47130
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47131
        // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VMAXu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
47132
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47133
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47134
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
47135
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu32),
47136
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
47137
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
47138
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
47139
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47140
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47141
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47142
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47143
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47144
0
        GIR_EraseFromParent, /*InsnID*/0,
47145
        // GIR_Coverage, 3433,
47146
0
        GIR_Done,
47147
      // Label 2492: @151509
47148
0
      GIM_Reject,
47149
    // Label 2488: @151510
47150
0
    GIM_Reject,
47151
    // Label 2482: @151511
47152
0
    GIM_Try, /*On fail goto*//*Label 2493*/ GIMT_Encode4(151572), // Rule ID 1226 //
47153
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47154
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
47155
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
47156
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47157
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47158
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47159
      // (umax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMAXuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
47160
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMAXuv8i8),
47161
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
47162
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
47163
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
47164
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47165
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47166
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47167
0
      GIR_EraseFromParent, /*InsnID*/0,
47168
      // GIR_Coverage, 1226,
47169
0
      GIR_Done,
47170
    // Label 2493: @151572
47171
0
    GIM_Reject,
47172
    // Label 2483: @151573
47173
0
    GIM_Try, /*On fail goto*//*Label 2494*/ GIMT_Encode4(151858),
47174
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
47175
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
47176
0
      GIM_Try, /*On fail goto*//*Label 2495*/ GIMT_Encode4(151659), // Rule ID 6170 //
47177
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47178
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47179
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47180
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47181
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
47182
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47183
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47184
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
47185
        // (umax:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd)  =>  (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
47186
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs16),
47187
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
47188
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
47189
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47190
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47191
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47192
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47193
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47194
0
        GIR_EraseFromParent, /*InsnID*/0,
47195
        // GIR_Coverage, 6170,
47196
0
        GIR_Done,
47197
      // Label 2495: @151659
47198
0
      GIM_Try, /*On fail goto*//*Label 2496*/ GIMT_Encode4(151732), // Rule ID 3825 //
47199
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47200
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47201
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47202
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47203
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47204
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
47205
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47206
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
47207
        // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm))  =>  (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
47208
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs16),
47209
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
47210
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
47211
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47212
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47213
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47214
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47215
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47216
0
        GIR_EraseFromParent, /*InsnID*/0,
47217
        // GIR_Coverage, 3825,
47218
0
        GIR_Done,
47219
      // Label 2496: @151732
47220
0
      GIM_Try, /*On fail goto*//*Label 2497*/ GIMT_Encode4(151785), // Rule ID 1224 //
47221
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47222
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47223
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47224
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47225
        // (umax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VMAXuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
47226
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMAXuv8i16),
47227
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
47228
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
47229
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
47230
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47231
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47232
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47233
0
        GIR_EraseFromParent, /*InsnID*/0,
47234
        // GIR_Coverage, 1224,
47235
0
        GIR_Done,
47236
      // Label 2497: @151785
47237
0
      GIM_Try, /*On fail goto*//*Label 2498*/ GIMT_Encode4(151857), // Rule ID 3430 //
47238
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47239
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47240
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47241
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47242
        // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VMAXu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
47243
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47244
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47245
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
47246
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu16),
47247
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
47248
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
47249
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
47250
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47251
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47252
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47253
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47254
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47255
0
        GIR_EraseFromParent, /*InsnID*/0,
47256
        // GIR_Coverage, 3430,
47257
0
        GIR_Done,
47258
      // Label 2498: @151857
47259
0
      GIM_Reject,
47260
    // Label 2494: @151858
47261
0
    GIM_Reject,
47262
    // Label 2484: @151859
47263
0
    GIM_Try, /*On fail goto*//*Label 2499*/ GIMT_Encode4(152144),
47264
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
47265
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
47266
0
      GIM_Try, /*On fail goto*//*Label 2500*/ GIMT_Encode4(151945), // Rule ID 6169 //
47267
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47268
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47269
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47270
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47271
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
47272
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47273
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47274
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
47275
        // (umax:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd)  =>  (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
47276
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs8),
47277
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
47278
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
47279
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47280
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47281
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47282
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47283
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47284
0
        GIR_EraseFromParent, /*InsnID*/0,
47285
        // GIR_Coverage, 6169,
47286
0
        GIR_Done,
47287
      // Label 2500: @151945
47288
0
      GIM_Try, /*On fail goto*//*Label 2501*/ GIMT_Encode4(152018), // Rule ID 3823 //
47289
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47290
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47291
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47292
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47293
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47294
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
47295
0
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47296
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
47297
        // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm))  =>  (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
47298
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs8),
47299
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
47300
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
47301
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47302
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47303
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47304
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47305
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47306
0
        GIR_EraseFromParent, /*InsnID*/0,
47307
        // GIR_Coverage, 3823,
47308
0
        GIR_Done,
47309
      // Label 2501: @152018
47310
0
      GIM_Try, /*On fail goto*//*Label 2502*/ GIMT_Encode4(152071), // Rule ID 1227 //
47311
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47312
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47313
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47314
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47315
        // (umax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VMAXuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
47316
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VMAXuv16i8),
47317
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
47318
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
47319
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
47320
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47321
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47322
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47323
0
        GIR_EraseFromParent, /*InsnID*/0,
47324
        // GIR_Coverage, 1227,
47325
0
        GIR_Done,
47326
      // Label 2502: @152071
47327
0
      GIM_Try, /*On fail goto*//*Label 2503*/ GIMT_Encode4(152143), // Rule ID 3427 //
47328
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47329
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47330
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47331
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47332
        // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VMAXu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
47333
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47334
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47335
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
47336
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu8),
47337
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
47338
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
47339
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
47340
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47341
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47342
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47343
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47344
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47345
0
        GIR_EraseFromParent, /*InsnID*/0,
47346
        // GIR_Coverage, 3427,
47347
0
        GIR_Done,
47348
      // Label 2503: @152143
47349
0
      GIM_Reject,
47350
    // Label 2499: @152144
47351
0
    GIM_Reject,
47352
    // Label 2485: @152145
47353
0
    GIM_Reject,
47354
    // Label 57: @152146
47355
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2510*/ GIMT_Encode4(152904),
47356
0
    /*GILLT_v2s32*//*Label 2504*/ GIMT_Encode4(152205), GIMT_Encode4(0), GIMT_Encode4(0),
47357
0
    /*GILLT_v4s16*//*Label 2505*/ GIMT_Encode4(152254),
47358
0
    /*GILLT_v4s32*//*Label 2506*/ GIMT_Encode4(152303), GIMT_Encode4(0), GIMT_Encode4(0),
47359
0
    /*GILLT_v8s8*//*Label 2507*/ GIMT_Encode4(152520),
47360
0
    /*GILLT_v8s16*//*Label 2508*/ GIMT_Encode4(152569), GIMT_Encode4(0), GIMT_Encode4(0),
47361
0
    /*GILLT_v16s8*//*Label 2509*/ GIMT_Encode4(152786),
47362
    // Label 2504: @152205
47363
0
    GIM_Try, /*On fail goto*//*Label 2511*/ GIMT_Encode4(152253), // Rule ID 1529 //
47364
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47365
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
47366
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47367
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47368
      // (abs:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)  =>  (VABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
47369
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABSv2i32),
47370
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
47371
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47372
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47373
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47374
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47375
0
      GIR_EraseFromParent, /*InsnID*/0,
47376
      // GIR_Coverage, 1529,
47377
0
      GIR_Done,
47378
    // Label 2511: @152253
47379
0
    GIM_Reject,
47380
    // Label 2505: @152254
47381
0
    GIM_Try, /*On fail goto*//*Label 2512*/ GIMT_Encode4(152302), // Rule ID 1528 //
47382
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47383
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
47384
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47385
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47386
      // (abs:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)  =>  (VABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
47387
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABSv4i16),
47388
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
47389
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47390
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47391
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47392
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47393
0
      GIR_EraseFromParent, /*InsnID*/0,
47394
      // GIR_Coverage, 1528,
47395
0
      GIR_Done,
47396
    // Label 2512: @152302
47397
0
    GIM_Reject,
47398
    // Label 2506: @152303
47399
0
    GIM_Try, /*On fail goto*//*Label 2513*/ GIMT_Encode4(152519),
47400
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
47401
0
      GIM_Try, /*On fail goto*//*Label 2514*/ GIMT_Encode4(152411), // Rule ID 2585 //
47402
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47403
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47404
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47405
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
47406
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
47407
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
47408
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
47409
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
47410
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
47411
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47412
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
47413
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
47414
0
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s16,
47415
0
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47416
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
47417
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
47418
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
47419
        // (abs:{ *:[v4i32] } (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$opA), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$opB)))  =>  (VABDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$opA, DPR:{ *:[v4i16] }:$opB)
47420
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDLuv4i32),
47421
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
47422
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // opA
47423
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // opB
47424
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47425
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47426
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47427
0
        GIR_EraseFromParent, /*InsnID*/0,
47428
        // GIR_Coverage, 2585,
47429
0
        GIR_Done,
47430
      // Label 2514: @152411
47431
0
      GIM_Try, /*On fail goto*//*Label 2515*/ GIMT_Encode4(152455), // Rule ID 1532 //
47432
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47433
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47434
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47435
        // (abs:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)  =>  (VABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
47436
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABSv4i32),
47437
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
47438
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47439
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47440
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47441
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47442
0
        GIR_EraseFromParent, /*InsnID*/0,
47443
        // GIR_Coverage, 1532,
47444
0
        GIR_Done,
47445
      // Label 2515: @152455
47446
0
      GIM_Try, /*On fail goto*//*Label 2516*/ GIMT_Encode4(152518), // Rule ID 3796 //
47447
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47448
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47449
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47450
        // (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v)  =>  (MVE_VABSs32:{ *:[v4i32] } ?:{ *:[v4i32] }:$v)
47451
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47452
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47453
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
47454
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs32),
47455
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
47456
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v
47457
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47458
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47459
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47460
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47461
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47462
0
        GIR_EraseFromParent, /*InsnID*/0,
47463
        // GIR_Coverage, 3796,
47464
0
        GIR_Done,
47465
      // Label 2516: @152518
47466
0
      GIM_Reject,
47467
    // Label 2513: @152519
47468
0
    GIM_Reject,
47469
    // Label 2507: @152520
47470
0
    GIM_Try, /*On fail goto*//*Label 2517*/ GIMT_Encode4(152568), // Rule ID 1527 //
47471
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47472
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
47473
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47474
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47475
      // (abs:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)  =>  (VABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
47476
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABSv8i8),
47477
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
47478
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47479
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47480
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47481
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47482
0
      GIR_EraseFromParent, /*InsnID*/0,
47483
      // GIR_Coverage, 1527,
47484
0
      GIR_Done,
47485
    // Label 2517: @152568
47486
0
    GIM_Reject,
47487
    // Label 2508: @152569
47488
0
    GIM_Try, /*On fail goto*//*Label 2518*/ GIMT_Encode4(152785),
47489
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
47490
0
      GIM_Try, /*On fail goto*//*Label 2519*/ GIMT_Encode4(152677), // Rule ID 2584 //
47491
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47492
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47493
0
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47494
0
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
47495
0
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
47496
0
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
47497
0
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
47498
0
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
47499
0
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
47500
0
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47501
0
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
47502
0
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
47503
0
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s8,
47504
0
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47505
0
        GIM_CheckIsSafeToFold, /*InsnID*/1,
47506
0
        GIM_CheckIsSafeToFold, /*InsnID*/2,
47507
0
        GIM_CheckIsSafeToFold, /*InsnID*/3,
47508
        // (abs:{ *:[v8i16] } (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$opA), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$opB)))  =>  (VABDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$opA, DPR:{ *:[v8i8] }:$opB)
47509
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABDLuv8i16),
47510
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
47511
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // opA
47512
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // opB
47513
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47514
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47515
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47516
0
        GIR_EraseFromParent, /*InsnID*/0,
47517
        // GIR_Coverage, 2584,
47518
0
        GIR_Done,
47519
      // Label 2519: @152677
47520
0
      GIM_Try, /*On fail goto*//*Label 2520*/ GIMT_Encode4(152721), // Rule ID 1531 //
47521
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47522
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47523
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47524
        // (abs:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)  =>  (VABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
47525
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABSv8i16),
47526
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
47527
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47528
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47529
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47530
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47531
0
        GIR_EraseFromParent, /*InsnID*/0,
47532
        // GIR_Coverage, 1531,
47533
0
        GIR_Done,
47534
      // Label 2520: @152721
47535
0
      GIM_Try, /*On fail goto*//*Label 2521*/ GIMT_Encode4(152784), // Rule ID 3790 //
47536
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47537
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47538
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47539
        // (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v)  =>  (MVE_VABSs16:{ *:[v8i16] } ?:{ *:[v8i16] }:$v)
47540
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47541
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47542
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
47543
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs16),
47544
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
47545
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v
47546
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47547
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47548
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47549
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47550
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47551
0
        GIR_EraseFromParent, /*InsnID*/0,
47552
        // GIR_Coverage, 3790,
47553
0
        GIR_Done,
47554
      // Label 2521: @152784
47555
0
      GIM_Reject,
47556
    // Label 2518: @152785
47557
0
    GIM_Reject,
47558
    // Label 2509: @152786
47559
0
    GIM_Try, /*On fail goto*//*Label 2522*/ GIMT_Encode4(152903),
47560
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
47561
0
      GIM_Try, /*On fail goto*//*Label 2523*/ GIMT_Encode4(152839), // Rule ID 1530 //
47562
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47563
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47564
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47565
        // (abs:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)  =>  (VABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
47566
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VABSv16i8),
47567
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
47568
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47569
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47570
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47571
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47572
0
        GIR_EraseFromParent, /*InsnID*/0,
47573
        // GIR_Coverage, 1530,
47574
0
        GIR_Done,
47575
      // Label 2523: @152839
47576
0
      GIM_Try, /*On fail goto*//*Label 2524*/ GIMT_Encode4(152902), // Rule ID 3784 //
47577
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47578
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47579
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47580
        // (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v)  =>  (MVE_VABSs8:{ *:[v16i8] } ?:{ *:[v16i8] }:$v)
47581
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47582
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47583
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
47584
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs8),
47585
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
47586
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v
47587
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47588
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47589
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47590
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47591
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47592
0
        GIR_EraseFromParent, /*InsnID*/0,
47593
        // GIR_Coverage, 3784,
47594
0
        GIR_Done,
47595
      // Label 2524: @152902
47596
0
      GIM_Reject,
47597
    // Label 2522: @152903
47598
0
    GIM_Reject,
47599
    // Label 2510: @152904
47600
0
    GIM_Reject,
47601
    // Label 58: @152905
47602
0
    GIM_Try, /*On fail goto*//*Label 2525*/ GIMT_Encode4(152990),
47603
0
      GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
47604
0
      GIM_Try, /*On fail goto*//*Label 2526*/ GIMT_Encode4(152929), // Rule ID 32 //
47605
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
47606
        // (br (bb:{ *:[Other] }):$target)  =>  (B (bb:{ *:[Other] }):$target)
47607
0
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::B),
47608
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47609
        // GIR_Coverage, 32,
47610
0
        GIR_Done,
47611
      // Label 2526: @152929
47612
0
      GIM_Try, /*On fail goto*//*Label 2527*/ GIMT_Encode4(152959), // Rule ID 290 //
47613
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
47614
        // (br (bb:{ *:[Other] }):$target)  =>  (tB (bb:{ *:[Other] }):$target)
47615
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::tB),
47616
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // target
47617
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47618
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47619
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47620
0
        GIR_EraseFromParent, /*InsnID*/0,
47621
        // GIR_Coverage, 290,
47622
0
        GIR_Done,
47623
      // Label 2527: @152959
47624
0
      GIM_Try, /*On fail goto*//*Label 2528*/ GIMT_Encode4(152989), // Rule ID 594 //
47625
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV8MBaseline_IsThumb),
47626
        // (br (bb:{ *:[Other] }):$target)  =>  (t2B (bb:{ *:[Other] }):$target)
47627
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2B),
47628
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // target
47629
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47630
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47631
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47632
0
        GIR_EraseFromParent, /*InsnID*/0,
47633
        // GIR_Coverage, 594,
47634
0
        GIR_Done,
47635
      // Label 2528: @152989
47636
0
      GIM_Reject,
47637
    // Label 2525: @152990
47638
0
    GIM_Reject,
47639
    // Label 59: @152991
47640
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 2531*/ GIMT_Encode4(153166),
47641
0
    /*GILLT_s16*//*Label 2529*/ GIMT_Encode4(153010),
47642
0
    /*GILLT_s32*//*Label 2530*/ GIMT_Encode4(153100),
47643
    // Label 2529: @153010
47644
0
    GIM_Try, /*On fail goto*//*Label 2532*/ GIMT_Encode4(153099), // Rule ID 2643 //
47645
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON),
47646
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
47647
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
47648
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
47649
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47650
0
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47651
0
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
47652
0
      GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm_odd),
47653
      // MIs[1] Operand 1
47654
      // No operand predicates
47655
0
      GIM_CheckIsSafeToFold, /*InsnID*/1,
47656
      // (extractelt:{ *:[bf16] } DPR:{ *:[v4bf16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm_odd>>:$lane)  =>  (COPY_TO_REGCLASS:{ *:[bf16] } (VGETLNu16:{ *:[i32] } DPR:{ *:[v4bf16] }:$src, (imm:{ *:[i32] }):$lane), HPR:{ *:[i32] })
47657
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47658
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VGETLNu16),
47659
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47660
0
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
47661
0
      GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // lane
47662
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
47663
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47664
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47665
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
47666
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
47667
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47668
0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
47669
0
      GIR_EraseFromParent, /*InsnID*/0,
47670
      // GIR_Coverage, 2643,
47671
0
      GIR_Done,
47672
    // Label 2532: @153099
47673
0
    GIM_Reject,
47674
    // Label 2530: @153100
47675
0
    GIM_Try, /*On fail goto*//*Label 2533*/ GIMT_Encode4(153165), // Rule ID 1589 //
47676
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs_HasFastVGETLNi32),
47677
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
47678
0
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
47679
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
47680
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47681
0
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47682
0
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
47683
      // MIs[1] Operand 1
47684
      // No operand predicates
47685
0
      GIM_CheckIsSafeToFold, /*InsnID*/1,
47686
      // (extractelt:{ *:[i32] } DPR:{ *:[v2i32] }:$V, (imm:{ *:[i32] }):$lane)  =>  (VGETLNi32:{ *:[i32] } DPR:{ *:[v2i32] }:$V, (imm:{ *:[i32] }):$lane)
47687
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VGETLNi32),
47688
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[R]
47689
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // V
47690
0
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane
47691
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47692
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47693
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47694
0
      GIR_EraseFromParent, /*InsnID*/0,
47695
      // GIR_Coverage, 1589,
47696
0
      GIR_Done,
47697
    // Label 2533: @153165
47698
0
    GIM_Reject,
47699
    // Label 2531: @153166
47700
0
    GIM_Reject,
47701
    // Label 60: @153167
47702
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 2541*/ GIMT_Encode4(153838),
47703
0
    /*GILLT_s32*//*Label 2534*/ GIMT_Encode4(153238), GIMT_Encode4(0), GIMT_Encode4(0),
47704
0
    /*GILLT_v2s32*//*Label 2535*/ GIMT_Encode4(153337), GIMT_Encode4(0), GIMT_Encode4(0),
47705
0
    /*GILLT_v4s16*//*Label 2536*/ GIMT_Encode4(153386),
47706
0
    /*GILLT_v4s32*//*Label 2537*/ GIMT_Encode4(153435), GIMT_Encode4(0), GIMT_Encode4(0),
47707
0
    /*GILLT_v8s8*//*Label 2538*/ GIMT_Encode4(153553),
47708
0
    /*GILLT_v8s16*//*Label 2539*/ GIMT_Encode4(153602), GIMT_Encode4(0), GIMT_Encode4(0),
47709
0
    /*GILLT_v16s8*//*Label 2540*/ GIMT_Encode4(153720),
47710
    // Label 2534: @153238
47711
0
    GIM_Try, /*On fail goto*//*Label 2542*/ GIMT_Encode4(153336),
47712
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
47713
0
      GIM_Try, /*On fail goto*//*Label 2543*/ GIMT_Encode4(153291), // Rule ID 197 //
47714
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5T_IsARM),
47715
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
47716
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
47717
        // (ctlz:{ *:[i32] } GPR:{ *:[i32] }:$Rm)  =>  (CLZ:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
47718
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::CLZ),
47719
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
47720
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
47721
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47722
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47723
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47724
0
        GIR_EraseFromParent, /*InsnID*/0,
47725
        // GIR_Coverage, 197,
47726
0
        GIR_Done,
47727
      // Label 2543: @153291
47728
0
      GIM_Try, /*On fail goto*//*Label 2544*/ GIMT_Encode4(153335), // Rule ID 542 //
47729
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
47730
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47731
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47732
        // (ctlz:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)  =>  (t2CLZ:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
47733
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2CLZ),
47734
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
47735
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
47736
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47737
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47738
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47739
0
        GIR_EraseFromParent, /*InsnID*/0,
47740
        // GIR_Coverage, 542,
47741
0
        GIR_Done,
47742
      // Label 2544: @153335
47743
0
      GIM_Reject,
47744
    // Label 2542: @153336
47745
0
    GIM_Reject,
47746
    // Label 2535: @153337
47747
0
    GIM_Try, /*On fail goto*//*Label 2545*/ GIMT_Encode4(153385), // Rule ID 1567 //
47748
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47749
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
47750
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47751
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47752
      // (ctlz:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)  =>  (VCLZv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
47753
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCLZv2i32),
47754
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
47755
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47756
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47757
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47758
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47759
0
      GIR_EraseFromParent, /*InsnID*/0,
47760
      // GIR_Coverage, 1567,
47761
0
      GIR_Done,
47762
    // Label 2545: @153385
47763
0
    GIM_Reject,
47764
    // Label 2536: @153386
47765
0
    GIM_Try, /*On fail goto*//*Label 2546*/ GIMT_Encode4(153434), // Rule ID 1566 //
47766
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47767
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
47768
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47769
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47770
      // (ctlz:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)  =>  (VCLZv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
47771
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCLZv4i16),
47772
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
47773
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47774
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47775
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47776
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47777
0
      GIR_EraseFromParent, /*InsnID*/0,
47778
      // GIR_Coverage, 1566,
47779
0
      GIR_Done,
47780
    // Label 2546: @153434
47781
0
    GIM_Reject,
47782
    // Label 2537: @153435
47783
0
    GIM_Try, /*On fail goto*//*Label 2547*/ GIMT_Encode4(153552),
47784
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
47785
0
      GIM_Try, /*On fail goto*//*Label 2548*/ GIMT_Encode4(153488), // Rule ID 1570 //
47786
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47787
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47788
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47789
        // (ctlz:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)  =>  (VCLZv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
47790
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCLZv4i32),
47791
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
47792
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47793
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47794
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47795
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47796
0
        GIR_EraseFromParent, /*InsnID*/0,
47797
        // GIR_Coverage, 1570,
47798
0
        GIR_Done,
47799
      // Label 2548: @153488
47800
0
      GIM_Try, /*On fail goto*//*Label 2549*/ GIMT_Encode4(153551), // Rule ID 3782 //
47801
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47802
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47803
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47804
        // (ctlz:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val)  =>  (MVE_VCLZs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val)
47805
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47806
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47807
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
47808
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs32),
47809
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
47810
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
47811
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47812
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47813
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47814
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47815
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47816
0
        GIR_EraseFromParent, /*InsnID*/0,
47817
        // GIR_Coverage, 3782,
47818
0
        GIR_Done,
47819
      // Label 2549: @153551
47820
0
      GIM_Reject,
47821
    // Label 2547: @153552
47822
0
    GIM_Reject,
47823
    // Label 2538: @153553
47824
0
    GIM_Try, /*On fail goto*//*Label 2550*/ GIMT_Encode4(153601), // Rule ID 1565 //
47825
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47826
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
47827
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47828
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47829
      // (ctlz:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)  =>  (VCLZv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
47830
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCLZv8i8),
47831
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
47832
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47833
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47834
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47835
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47836
0
      GIR_EraseFromParent, /*InsnID*/0,
47837
      // GIR_Coverage, 1565,
47838
0
      GIR_Done,
47839
    // Label 2550: @153601
47840
0
    GIM_Reject,
47841
    // Label 2539: @153602
47842
0
    GIM_Try, /*On fail goto*//*Label 2551*/ GIMT_Encode4(153719),
47843
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
47844
0
      GIM_Try, /*On fail goto*//*Label 2552*/ GIMT_Encode4(153655), // Rule ID 1569 //
47845
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47846
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47847
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47848
        // (ctlz:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)  =>  (VCLZv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
47849
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCLZv8i16),
47850
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
47851
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47852
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47853
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47854
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47855
0
        GIR_EraseFromParent, /*InsnID*/0,
47856
        // GIR_Coverage, 1569,
47857
0
        GIR_Done,
47858
      // Label 2552: @153655
47859
0
      GIM_Try, /*On fail goto*//*Label 2553*/ GIMT_Encode4(153718), // Rule ID 3780 //
47860
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47861
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47862
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47863
        // (ctlz:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val)  =>  (MVE_VCLZs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val)
47864
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47865
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47866
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
47867
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs16),
47868
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
47869
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
47870
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47871
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47872
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47873
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47874
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47875
0
        GIR_EraseFromParent, /*InsnID*/0,
47876
        // GIR_Coverage, 3780,
47877
0
        GIR_Done,
47878
      // Label 2553: @153718
47879
0
      GIM_Reject,
47880
    // Label 2551: @153719
47881
0
    GIM_Reject,
47882
    // Label 2540: @153720
47883
0
    GIM_Try, /*On fail goto*//*Label 2554*/ GIMT_Encode4(153837),
47884
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
47885
0
      GIM_Try, /*On fail goto*//*Label 2555*/ GIMT_Encode4(153773), // Rule ID 1568 //
47886
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47887
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47888
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47889
        // (ctlz:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)  =>  (VCLZv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
47890
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCLZv16i8),
47891
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
47892
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47893
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47894
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47895
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47896
0
        GIR_EraseFromParent, /*InsnID*/0,
47897
        // GIR_Coverage, 1568,
47898
0
        GIR_Done,
47899
      // Label 2555: @153773
47900
0
      GIM_Try, /*On fail goto*//*Label 2556*/ GIMT_Encode4(153836), // Rule ID 3778 //
47901
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47902
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47903
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47904
        // (ctlz:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val)  =>  (MVE_VCLZs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val)
47905
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47906
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47907
0
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
47908
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs8),
47909
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
47910
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
47911
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47912
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47913
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47914
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47915
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47916
0
        GIR_EraseFromParent, /*InsnID*/0,
47917
        // GIR_Coverage, 3778,
47918
0
        GIR_Done,
47919
      // Label 2556: @153836
47920
0
      GIM_Reject,
47921
    // Label 2554: @153837
47922
0
    GIM_Reject,
47923
    // Label 2541: @153838
47924
0
    GIM_Reject,
47925
    // Label 61: @153839
47926
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(16), /*)*//*default:*//*Label 2559*/ GIMT_Encode4(153968),
47927
0
    /*GILLT_v8s8*//*Label 2557*/ GIMT_Encode4(153870), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
47928
0
    /*GILLT_v16s8*//*Label 2558*/ GIMT_Encode4(153919),
47929
    // Label 2557: @153870
47930
0
    GIM_Try, /*On fail goto*//*Label 2560*/ GIMT_Encode4(153918), // Rule ID 1571 //
47931
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47932
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
47933
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47934
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47935
      // (ctpop:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)  =>  (VCNTd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
47936
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCNTd),
47937
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
47938
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47939
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47940
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47941
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47942
0
      GIR_EraseFromParent, /*InsnID*/0,
47943
      // GIR_Coverage, 1571,
47944
0
      GIR_Done,
47945
    // Label 2560: @153918
47946
0
    GIM_Reject,
47947
    // Label 2558: @153919
47948
0
    GIM_Try, /*On fail goto*//*Label 2561*/ GIMT_Encode4(153967), // Rule ID 1572 //
47949
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47950
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
47951
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47952
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47953
      // (ctpop:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)  =>  (VCNTq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
47954
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VCNTq),
47955
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Vd]
47956
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47957
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47958
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47959
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47960
0
      GIR_EraseFromParent, /*InsnID*/0,
47961
      // GIR_Coverage, 1572,
47962
0
      GIR_Done,
47963
    // Label 2561: @153967
47964
0
    GIM_Reject,
47965
    // Label 2559: @153968
47966
0
    GIM_Reject,
47967
    // Label 62: @153969
47968
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 2565*/ GIMT_Encode4(154307),
47969
0
    /*GILLT_s32*//*Label 2562*/ GIMT_Encode4(154028), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
47970
0
    /*GILLT_v4s32*//*Label 2563*/ GIMT_Encode4(154171), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
47971
0
    /*GILLT_v8s16*//*Label 2564*/ GIMT_Encode4(154239),
47972
    // Label 2562: @154028
47973
0
    GIM_Try, /*On fail goto*//*Label 2566*/ GIMT_Encode4(154170),
47974
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
47975
0
      GIM_Try, /*On fail goto*//*Label 2567*/ GIMT_Encode4(154081), // Rule ID 199 //
47976
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
47977
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
47978
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
47979
        // (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm)  =>  (REV:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
47980
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::REV),
47981
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
47982
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
47983
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47984
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47985
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47986
0
        GIR_EraseFromParent, /*InsnID*/0,
47987
        // GIR_Coverage, 199,
47988
0
        GIR_Done,
47989
      // Label 2567: @154081
47990
0
      GIM_Try, /*On fail goto*//*Label 2568*/ GIMT_Encode4(154125), // Rule ID 333 //
47991
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
47992
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
47993
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
47994
        // (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)  =>  (tREV:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
47995
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::tREV),
47996
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
47997
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
47998
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47999
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48000
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48001
0
        GIR_EraseFromParent, /*InsnID*/0,
48002
        // GIR_Coverage, 333,
48003
0
        GIR_Done,
48004
      // Label 2568: @154125
48005
0
      GIM_Try, /*On fail goto*//*Label 2569*/ GIMT_Encode4(154169), // Rule ID 544 //
48006
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
48007
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48008
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48009
        // (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)  =>  (t2REV:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
48010
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2REV),
48011
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
48012
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
48013
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48014
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48015
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48016
0
        GIR_EraseFromParent, /*InsnID*/0,
48017
        // GIR_Coverage, 544,
48018
0
        GIR_Done,
48019
      // Label 2569: @154169
48020
0
      GIM_Reject,
48021
    // Label 2566: @154170
48022
0
    GIM_Reject,
48023
    // Label 2563: @154171
48024
0
    GIM_Try, /*On fail goto*//*Label 2570*/ GIMT_Encode4(154238), // Rule ID 3437 //
48025
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48026
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
48027
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48028
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48029
      // (bswap:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src)
48030
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48031
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48032
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
48033
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
48034
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
48035
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
48036
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48037
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48038
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48039
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48040
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48041
0
      GIR_EraseFromParent, /*InsnID*/0,
48042
      // GIR_Coverage, 3437,
48043
0
      GIR_Done,
48044
    // Label 2570: @154238
48045
0
    GIM_Reject,
48046
    // Label 2564: @154239
48047
0
    GIM_Try, /*On fail goto*//*Label 2571*/ GIMT_Encode4(154306), // Rule ID 3436 //
48048
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48049
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
48050
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48051
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48052
      // (bswap:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src)
48053
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48054
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48055
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
48056
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
48057
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
48058
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
48059
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48060
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48061
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48062
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48063
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48064
0
      GIR_EraseFromParent, /*InsnID*/0,
48065
      // GIR_Coverage, 3436,
48066
0
      GIR_Done,
48067
    // Label 2571: @154306
48068
0
    GIM_Reject,
48069
    // Label 2565: @154307
48070
0
    GIM_Reject,
48071
    // Label 63: @154308
48072
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 2576*/ GIMT_Encode4(154787),
48073
0
    /*GILLT_s32*//*Label 2572*/ GIMT_Encode4(154379), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48074
0
    /*GILLT_v4s32*//*Label 2573*/ GIMT_Encode4(154478), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48075
0
    /*GILLT_v8s16*//*Label 2574*/ GIMT_Encode4(154581), GIMT_Encode4(0), GIMT_Encode4(0),
48076
0
    /*GILLT_v16s8*//*Label 2575*/ GIMT_Encode4(154684),
48077
    // Label 2572: @154379
48078
0
    GIM_Try, /*On fail goto*//*Label 2577*/ GIMT_Encode4(154477),
48079
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
48080
0
      GIM_Try, /*On fail goto*//*Label 2578*/ GIMT_Encode4(154432), // Rule ID 198 //
48081
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM),
48082
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
48083
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
48084
        // (bitreverse:{ *:[i32] } GPR:{ *:[i32] }:$Rm)  =>  (RBIT:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
48085
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::RBIT),
48086
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
48087
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
48088
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48089
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48090
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48091
0
        GIR_EraseFromParent, /*InsnID*/0,
48092
        // GIR_Coverage, 198,
48093
0
        GIR_Done,
48094
      // Label 2578: @154432
48095
0
      GIM_Try, /*On fail goto*//*Label 2579*/ GIMT_Encode4(154476), // Rule ID 543 //
48096
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
48097
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48098
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48099
        // (bitreverse:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)  =>  (t2RBIT:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
48100
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::t2RBIT),
48101
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rd]
48102
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
48103
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48104
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48105
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48106
0
        GIR_EraseFromParent, /*InsnID*/0,
48107
        // GIR_Coverage, 543,
48108
0
        GIR_Done,
48109
      // Label 2579: @154476
48110
0
      GIM_Reject,
48111
    // Label 2577: @154477
48112
0
    GIM_Reject,
48113
    // Label 2573: @154478
48114
0
    GIM_Try, /*On fail goto*//*Label 2580*/ GIMT_Encode4(154580), // Rule ID 4882 //
48115
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48116
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
48117
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48118
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48119
      // (bitreverse:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1)  =>  (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1, (t2MOVi:{ *:[i32] } 32:{ *:[i32] }))
48120
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
48121
0
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
48122
0
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48123
0
      GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/1,
48124
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
48125
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48126
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/32,
48127
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
48128
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48129
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48130
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48131
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32),
48132
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
48133
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
48134
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48135
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48136
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48137
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48138
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
48139
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48140
0
      GIR_EraseFromParent, /*InsnID*/0,
48141
      // GIR_Coverage, 4882,
48142
0
      GIR_Done,
48143
    // Label 2580: @154580
48144
0
    GIM_Reject,
48145
    // Label 2574: @154581
48146
0
    GIM_Try, /*On fail goto*//*Label 2581*/ GIMT_Encode4(154683), // Rule ID 4883 //
48147
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48148
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
48149
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48150
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48151
      // (bitreverse:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1)  =>  (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1, (t2MOVi:{ *:[i32] } 16:{ *:[i32] }))
48152
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
48153
0
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
48154
0
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48155
0
      GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/1,
48156
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
48157
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48158
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/16,
48159
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
48160
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48161
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48162
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48163
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16),
48164
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
48165
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
48166
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48167
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48168
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48169
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48170
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
48171
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48172
0
      GIR_EraseFromParent, /*InsnID*/0,
48173
      // GIR_Coverage, 4883,
48174
0
      GIR_Done,
48175
    // Label 2581: @154683
48176
0
    GIM_Reject,
48177
    // Label 2575: @154684
48178
0
    GIM_Try, /*On fail goto*//*Label 2582*/ GIMT_Encode4(154786), // Rule ID 4881 //
48179
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48180
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
48181
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48182
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48183
      // (bitreverse:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1)  =>  (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1, (t2MOVi:{ *:[i32] } 8:{ *:[i32] }))
48184
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
48185
0
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
48186
0
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48187
0
      GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/1,
48188
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
48189
0
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48190
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
48191
0
      GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
48192
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48193
0
      GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48194
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48195
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR8),
48196
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
48197
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
48198
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48199
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48200
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48201
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48202
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
48203
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48204
0
      GIR_EraseFromParent, /*InsnID*/0,
48205
      // GIR_Coverage, 4881,
48206
0
      GIR_Done,
48207
    // Label 2582: @154786
48208
0
    GIM_Reject,
48209
    // Label 2576: @154787
48210
0
    GIM_Reject,
48211
    // Label 64: @154788
48212
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2588*/ GIMT_Encode4(155080),
48213
0
    /*GILLT_s16*//*Label 2583*/ GIMT_Encode4(154851),
48214
0
    /*GILLT_s32*//*Label 2584*/ GIMT_Encode4(154882),
48215
0
    /*GILLT_s64*//*Label 2585*/ GIMT_Encode4(154913), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48216
0
    /*GILLT_v4s32*//*Label 2586*/ GIMT_Encode4(154944), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48217
0
    /*GILLT_v8s16*//*Label 2587*/ GIMT_Encode4(155012),
48218
    // Label 2583: @154851
48219
0
    GIM_Try, /*On fail goto*//*Label 2589*/ GIMT_Encode4(154881), // Rule ID 697 //
48220
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
48221
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
48222
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
48223
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
48224
      // (fceil:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VRINTPH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
48225
0
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPH),
48226
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48227
      // GIR_Coverage, 697,
48228
0
      GIR_Done,
48229
    // Label 2589: @154881
48230
0
    GIM_Reject,
48231
    // Label 2584: @154882
48232
0
    GIM_Try, /*On fail goto*//*Label 2590*/ GIMT_Encode4(154912), // Rule ID 698 //
48233
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
48234
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
48235
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
48236
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
48237
      // (fceil:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VRINTPS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
48238
0
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPS),
48239
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48240
      // GIR_Coverage, 698,
48241
0
      GIR_Done,
48242
    // Label 2590: @154912
48243
0
    GIM_Reject,
48244
    // Label 2585: @154913
48245
0
    GIM_Try, /*On fail goto*//*Label 2591*/ GIMT_Encode4(154943), // Rule ID 699 //
48246
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
48247
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
48248
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48249
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48250
      // (fceil:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VRINTPD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
48251
0
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPD),
48252
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48253
      // GIR_Coverage, 699,
48254
0
      GIR_Done,
48255
    // Label 2591: @154943
48256
0
    GIM_Reject,
48257
    // Label 2586: @154944
48258
0
    GIM_Try, /*On fail goto*//*Label 2592*/ GIMT_Encode4(155011), // Rule ID 4110 //
48259
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
48260
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
48261
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48262
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48263
      // (fceil:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)  =>  (MVE_VRINTf32P:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
48264
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48265
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48266
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
48267
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32P),
48268
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
48269
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
48270
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48271
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48272
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48273
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48274
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48275
0
      GIR_EraseFromParent, /*InsnID*/0,
48276
      // GIR_Coverage, 4110,
48277
0
      GIR_Done,
48278
    // Label 2592: @155011
48279
0
    GIM_Reject,
48280
    // Label 2587: @155012
48281
0
    GIM_Try, /*On fail goto*//*Label 2593*/ GIMT_Encode4(155079), // Rule ID 4098 //
48282
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
48283
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
48284
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48285
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48286
      // (fceil:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)  =>  (MVE_VRINTf16P:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
48287
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48288
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48289
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
48290
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16P),
48291
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
48292
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
48293
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48294
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48295
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48296
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48297
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48298
0
      GIR_EraseFromParent, /*InsnID*/0,
48299
      // GIR_Coverage, 4098,
48300
0
      GIR_Done,
48301
    // Label 2593: @155079
48302
0
    GIM_Reject,
48303
    // Label 2588: @155080
48304
0
    GIM_Reject,
48305
    // Label 65: @155081
48306
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2597*/ GIMT_Encode4(155251),
48307
0
    /*GILLT_s16*//*Label 2594*/ GIMT_Encode4(155104),
48308
0
    /*GILLT_s32*//*Label 2595*/ GIMT_Encode4(155153),
48309
0
    /*GILLT_s64*//*Label 2596*/ GIMT_Encode4(155202),
48310
    // Label 2594: @155104
48311
0
    GIM_Try, /*On fail goto*//*Label 2598*/ GIMT_Encode4(155152), // Rule ID 705 //
48312
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
48313
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
48314
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
48315
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
48316
      // (fsqrt:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VSQRTH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
48317
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSQRTH),
48318
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
48319
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
48320
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48321
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48322
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48323
0
      GIR_EraseFromParent, /*InsnID*/0,
48324
      // GIR_Coverage, 705,
48325
0
      GIR_Done,
48326
    // Label 2598: @155152
48327
0
    GIM_Reject,
48328
    // Label 2595: @155153
48329
0
    GIM_Try, /*On fail goto*//*Label 2599*/ GIMT_Encode4(155201), // Rule ID 704 //
48330
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2),
48331
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
48332
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
48333
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
48334
      // (fsqrt:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VSQRTS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
48335
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSQRTS),
48336
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
48337
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
48338
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48339
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48340
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48341
0
      GIR_EraseFromParent, /*InsnID*/0,
48342
      // GIR_Coverage, 704,
48343
0
      GIR_Done,
48344
    // Label 2599: @155201
48345
0
    GIM_Reject,
48346
    // Label 2596: @155202
48347
0
    GIM_Try, /*On fail goto*//*Label 2600*/ GIMT_Encode4(155250), // Rule ID 703 //
48348
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
48349
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
48350
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48351
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48352
      // (fsqrt:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VSQRTD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
48353
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VSQRTD),
48354
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
48355
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
48356
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48357
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48358
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48359
0
      GIR_EraseFromParent, /*InsnID*/0,
48360
      // GIR_Coverage, 703,
48361
0
      GIR_Done,
48362
    // Label 2600: @155250
48363
0
    GIM_Reject,
48364
    // Label 2597: @155251
48365
0
    GIM_Reject,
48366
    // Label 66: @155252
48367
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2606*/ GIMT_Encode4(155544),
48368
0
    /*GILLT_s16*//*Label 2601*/ GIMT_Encode4(155315),
48369
0
    /*GILLT_s32*//*Label 2602*/ GIMT_Encode4(155346),
48370
0
    /*GILLT_s64*//*Label 2603*/ GIMT_Encode4(155377), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48371
0
    /*GILLT_v4s32*//*Label 2604*/ GIMT_Encode4(155408), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48372
0
    /*GILLT_v8s16*//*Label 2605*/ GIMT_Encode4(155476),
48373
    // Label 2601: @155315
48374
0
    GIM_Try, /*On fail goto*//*Label 2607*/ GIMT_Encode4(155345), // Rule ID 700 //
48375
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
48376
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
48377
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
48378
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
48379
      // (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VRINTMH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
48380
0
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMH),
48381
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48382
      // GIR_Coverage, 700,
48383
0
      GIR_Done,
48384
    // Label 2607: @155345
48385
0
    GIM_Reject,
48386
    // Label 2602: @155346
48387
0
    GIM_Try, /*On fail goto*//*Label 2608*/ GIMT_Encode4(155376), // Rule ID 701 //
48388
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
48389
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
48390
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
48391
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
48392
      // (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VRINTMS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
48393
0
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMS),
48394
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48395
      // GIR_Coverage, 701,
48396
0
      GIR_Done,
48397
    // Label 2608: @155376
48398
0
    GIM_Reject,
48399
    // Label 2603: @155377
48400
0
    GIM_Try, /*On fail goto*//*Label 2609*/ GIMT_Encode4(155407), // Rule ID 702 //
48401
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
48402
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
48403
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48404
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48405
      // (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VRINTMD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
48406
0
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMD),
48407
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48408
      // GIR_Coverage, 702,
48409
0
      GIR_Done,
48410
    // Label 2609: @155407
48411
0
    GIM_Reject,
48412
    // Label 2604: @155408
48413
0
    GIM_Try, /*On fail goto*//*Label 2610*/ GIMT_Encode4(155475), // Rule ID 4108 //
48414
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
48415
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
48416
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48417
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48418
      // (ffloor:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)  =>  (MVE_VRINTf32M:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
48419
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48420
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48421
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
48422
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32M),
48423
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
48424
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
48425
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48426
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48427
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48428
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48429
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48430
0
      GIR_EraseFromParent, /*InsnID*/0,
48431
      // GIR_Coverage, 4108,
48432
0
      GIR_Done,
48433
    // Label 2610: @155475
48434
0
    GIM_Reject,
48435
    // Label 2605: @155476
48436
0
    GIM_Try, /*On fail goto*//*Label 2611*/ GIMT_Encode4(155543), // Rule ID 4096 //
48437
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
48438
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
48439
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48440
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48441
      // (ffloor:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)  =>  (MVE_VRINTf16M:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
48442
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48443
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48444
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
48445
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16M),
48446
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
48447
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
48448
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48449
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48450
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48451
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48452
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48453
0
      GIR_EraseFromParent, /*InsnID*/0,
48454
      // GIR_Coverage, 4096,
48455
0
      GIR_Done,
48456
    // Label 2611: @155543
48457
0
    GIM_Reject,
48458
    // Label 2606: @155544
48459
0
    GIM_Reject,
48460
    // Label 67: @155545
48461
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2617*/ GIMT_Encode4(155891),
48462
0
    /*GILLT_s16*//*Label 2612*/ GIMT_Encode4(155608),
48463
0
    /*GILLT_s32*//*Label 2613*/ GIMT_Encode4(155657),
48464
0
    /*GILLT_s64*//*Label 2614*/ GIMT_Encode4(155706), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48465
0
    /*GILLT_v4s32*//*Label 2615*/ GIMT_Encode4(155755), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48466
0
    /*GILLT_v8s16*//*Label 2616*/ GIMT_Encode4(155823),
48467
    // Label 2612: @155608
48468
0
    GIM_Try, /*On fail goto*//*Label 2618*/ GIMT_Encode4(155656), // Rule ID 688 //
48469
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
48470
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
48471
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
48472
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
48473
      // (frint:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VRINTXH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
48474
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXH),
48475
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
48476
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
48477
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48478
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48479
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48480
0
      GIR_EraseFromParent, /*InsnID*/0,
48481
      // GIR_Coverage, 688,
48482
0
      GIR_Done,
48483
    // Label 2618: @155656
48484
0
    GIM_Reject,
48485
    // Label 2613: @155657
48486
0
    GIM_Try, /*On fail goto*//*Label 2619*/ GIMT_Encode4(155705), // Rule ID 689 //
48487
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
48488
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
48489
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
48490
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
48491
      // (frint:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VRINTXS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
48492
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXS),
48493
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
48494
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
48495
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48496
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48497
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48498
0
      GIR_EraseFromParent, /*InsnID*/0,
48499
      // GIR_Coverage, 689,
48500
0
      GIR_Done,
48501
    // Label 2619: @155705
48502
0
    GIM_Reject,
48503
    // Label 2614: @155706
48504
0
    GIM_Try, /*On fail goto*//*Label 2620*/ GIMT_Encode4(155754), // Rule ID 690 //
48505
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
48506
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
48507
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48508
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48509
      // (frint:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VRINTXD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
48510
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXD),
48511
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
48512
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
48513
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48514
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48515
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48516
0
      GIR_EraseFromParent, /*InsnID*/0,
48517
      // GIR_Coverage, 690,
48518
0
      GIR_Done,
48519
    // Label 2620: @155754
48520
0
    GIM_Reject,
48521
    // Label 2615: @155755
48522
0
    GIM_Try, /*On fail goto*//*Label 2621*/ GIMT_Encode4(155822), // Rule ID 4102 //
48523
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
48524
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
48525
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48526
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48527
      // (frint:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)  =>  (MVE_VRINTf32X:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
48528
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48529
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48530
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
48531
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32X),
48532
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
48533
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
48534
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48535
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48536
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48537
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48538
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48539
0
      GIR_EraseFromParent, /*InsnID*/0,
48540
      // GIR_Coverage, 4102,
48541
0
      GIR_Done,
48542
    // Label 2621: @155822
48543
0
    GIM_Reject,
48544
    // Label 2616: @155823
48545
0
    GIM_Try, /*On fail goto*//*Label 2622*/ GIMT_Encode4(155890), // Rule ID 4090 //
48546
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
48547
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
48548
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48549
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48550
      // (frint:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)  =>  (MVE_VRINTf16X:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
48551
0
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48552
0
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48553
0
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
48554
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16X),
48555
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Qd]
48556
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
48557
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48558
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48559
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48560
0
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48561
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48562
0
      GIR_EraseFromParent, /*InsnID*/0,
48563
      // GIR_Coverage, 4090,
48564
0
      GIR_Done,
48565
    // Label 2622: @155890
48566
0
    GIM_Reject,
48567
    // Label 2617: @155891
48568
0
    GIM_Reject,
48569
    // Label 68: @155892
48570
0
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2626*/ GIMT_Encode4(156062),
48571
0
    /*GILLT_s16*//*Label 2623*/ GIMT_Encode4(155915),
48572
0
    /*GILLT_s32*//*Label 2624*/ GIMT_Encode4(155964),
48573
0
    /*GILLT_s64*//*Label 2625*/ GIMT_Encode4(156013),
48574
    // Label 2623: @155915
48575
0
    GIM_Try, /*On fail goto*//*Label 2627*/ GIMT_Encode4(155963), // Rule ID 685 //
48576
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
48577
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
48578
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
48579
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
48580
      // (fnearbyint:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VRINTRH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
48581
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTRH),
48582
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
48583
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
48584
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48585
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48586
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48587
0
      GIR_EraseFromParent, /*InsnID*/0,
48588
      // GIR_Coverage, 685,
48589
0
      GIR_Done,
48590
    // Label 2627: @155963
48591
0
    GIM_Reject,
48592
    // Label 2624: @155964
48593
0
    GIM_Try, /*On fail goto*//*Label 2628*/ GIMT_Encode4(156012), // Rule ID 686 //
48594
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
48595
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
48596
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
48597
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
48598
      // (fnearbyint:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VRINTRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
48599
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTRS),
48600
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Sd]
48601
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
48602
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48603
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48604
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48605
0
      GIR_EraseFromParent, /*InsnID*/0,
48606
      // GIR_Coverage, 686,
48607
0
      GIR_Done,
48608
    // Label 2628: @156012
48609
0
    GIM_Reject,
48610
    // Label 2625: @156013
48611
0
    GIM_Try, /*On fail goto*//*Label 2629*/ GIMT_Encode4(156061), // Rule ID 687 //
48612
0
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
48613
0
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
48614
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48615
0
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48616
      // (fnearbyint:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VRINTRD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
48617
0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTRD),
48618
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Dd]
48619
0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
48620
0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48621
0
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48622
0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48623
0
      GIR_EraseFromParent, /*InsnID*/0,
48624
      // GIR_Coverage, 687,
48625
0
      GIR_Done,
48626
    // Label 2629: @156061
48627
0
    GIM_Reject,
48628
    // Label 2626: @156062
48629
0
    GIM_Reject,
48630
    // Label 69: @156063
48631
0
    GIM_Try, /*On fail goto*//*Label 2630*/ GIMT_Encode4(156269),
48632
0
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
48633
0
      GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2634*/ GIMT_Encode4(156268),
48634
0
      /*GILLT_v4s32*//*Label 2631*/ GIMT_Encode4(156115), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48635
0
      /*GILLT_v8s16*//*Label 2632*/ GIMT_Encode4(156166), GIMT_Encode4(0), GIMT_Encode4(0),
48636
0
      /*GILLT_v16s8*//*Label 2633*/ GIMT_Encode4(156217),
48637
      // Label 2631: @156115
48638
0
      GIM_Try, /*On fail goto*//*Label 2635*/ GIMT_Encode4(156165), // Rule ID 3193 //
48639
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48640
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
48641
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48642
        // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec)  =>  (MVE_VADDVu32no_acc:{ *:[i32] } ?:{ *:[v4i32] }:$vec)
48643
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32no_acc),
48644
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rda]
48645
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vec
48646
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48647
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48648
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48649
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48650
0
        GIR_EraseFromParent, /*InsnID*/0,
48651
        // GIR_Coverage, 3193,
48652
0
        GIR_Done,
48653
      // Label 2635: @156165
48654
0
      GIM_Reject,
48655
      // Label 2632: @156166
48656
0
      GIM_Try, /*On fail goto*//*Label 2636*/ GIMT_Encode4(156216), // Rule ID 3183 //
48657
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48658
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
48659
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48660
        // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec)  =>  (MVE_VADDVu16no_acc:{ *:[i32] } ?:{ *:[v8i16] }:$vec)
48661
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16no_acc),
48662
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rda]
48663
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vec
48664
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48665
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48666
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48667
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48668
0
        GIR_EraseFromParent, /*InsnID*/0,
48669
        // GIR_Coverage, 3183,
48670
0
        GIR_Done,
48671
      // Label 2636: @156216
48672
0
      GIM_Reject,
48673
      // Label 2633: @156217
48674
0
      GIM_Try, /*On fail goto*//*Label 2637*/ GIMT_Encode4(156267), // Rule ID 3155 //
48675
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48676
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
48677
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48678
        // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec)  =>  (MVE_VADDVu8no_acc:{ *:[i32] } ?:{ *:[v16i8] }:$vec)
48679
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8no_acc),
48680
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[Rda]
48681
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vec
48682
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48683
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48684
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48685
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48686
0
        GIR_EraseFromParent, /*InsnID*/0,
48687
        // GIR_Coverage, 3155,
48688
0
        GIR_Done,
48689
      // Label 2637: @156267
48690
0
      GIM_Reject,
48691
      // Label 2634: @156268
48692
0
      GIM_Reject,
48693
    // Label 2630: @156269
48694
0
    GIM_Reject,
48695
    // Label 70: @156270
48696
0
    GIM_Try, /*On fail goto*//*Label 2638*/ GIMT_Encode4(156580),
48697
0
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
48698
0
      GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2642*/ GIMT_Encode4(156579),
48699
0
      /*GILLT_v4s32*//*Label 2639*/ GIMT_Encode4(156322), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48700
0
      /*GILLT_v8s16*//*Label 2640*/ GIMT_Encode4(156415), GIMT_Encode4(0), GIMT_Encode4(0),
48701
0
      /*GILLT_v16s8*//*Label 2641*/ GIMT_Encode4(156493),
48702
      // Label 2639: @156322
48703
0
      GIM_Try, /*On fail goto*//*Label 2643*/ GIMT_Encode4(156414), // Rule ID 3253 //
48704
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48705
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48706
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48707
        // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VMAXVs32:{ *:[i32] } (t2MOVi:{ *:[i32] } -2147483648:{ *:[i32] }), ?:{ *:[v4i32] }:$src)
48708
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
48709
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
48710
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48711
0
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(-2147483648),
48712
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
48713
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48714
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48715
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48716
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs32),
48717
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
48718
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48719
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
48720
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48721
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48722
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48723
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48724
0
        GIR_EraseFromParent, /*InsnID*/0,
48725
        // GIR_Coverage, 3253,
48726
0
        GIR_Done,
48727
      // Label 2643: @156414
48728
0
      GIM_Reject,
48729
      // Label 2640: @156415
48730
0
      GIM_Try, /*On fail goto*//*Label 2644*/ GIMT_Encode4(156492), // Rule ID 3252 //
48731
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48732
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48733
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48734
        // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VMAXVs16:{ *:[i32] } (t2MOVi32imm:{ *:[i32] } -32768:{ *:[i32] }), ?:{ *:[v8i16] }:$src)
48735
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
48736
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi32imm),
48737
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48738
0
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(-32768),
48739
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48740
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs16),
48741
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
48742
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48743
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
48744
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48745
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48746
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48747
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48748
0
        GIR_EraseFromParent, /*InsnID*/0,
48749
        // GIR_Coverage, 3252,
48750
0
        GIR_Done,
48751
      // Label 2644: @156492
48752
0
      GIM_Reject,
48753
      // Label 2641: @156493
48754
0
      GIM_Try, /*On fail goto*//*Label 2645*/ GIMT_Encode4(156578), // Rule ID 3251 //
48755
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48756
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48757
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48758
        // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v16i8] }:$src)  =>  (MVE_VMAXVs8:{ *:[i32] } (t2MVNi:{ *:[i32] } 127:{ *:[i32] }), ?:{ *:[v16i8] }:$src)
48759
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
48760
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MVNi),
48761
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48762
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/127,
48763
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
48764
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48765
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48766
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48767
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs8),
48768
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
48769
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48770
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
48771
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48772
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48773
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48774
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48775
0
        GIR_EraseFromParent, /*InsnID*/0,
48776
        // GIR_Coverage, 3251,
48777
0
        GIR_Done,
48778
      // Label 2645: @156578
48779
0
      GIM_Reject,
48780
      // Label 2642: @156579
48781
0
      GIM_Reject,
48782
    // Label 2638: @156580
48783
0
    GIM_Reject,
48784
    // Label 71: @156581
48785
0
    GIM_Try, /*On fail goto*//*Label 2646*/ GIMT_Encode4(156900),
48786
0
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
48787
0
      GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2650*/ GIMT_Encode4(156899),
48788
0
      /*GILLT_v4s32*//*Label 2647*/ GIMT_Encode4(156633), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48789
0
      /*GILLT_v8s16*//*Label 2648*/ GIMT_Encode4(156726), GIMT_Encode4(0), GIMT_Encode4(0),
48790
0
      /*GILLT_v16s8*//*Label 2649*/ GIMT_Encode4(156813),
48791
      // Label 2647: @156633
48792
0
      GIM_Try, /*On fail goto*//*Label 2651*/ GIMT_Encode4(156725), // Rule ID 3259 //
48793
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48794
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48795
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48796
        // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VMINVs32:{ *:[i32] } (t2MVNi:{ *:[i32] } -2147483648:{ *:[i32] }), ?:{ *:[v4i32] }:$src)
48797
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
48798
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MVNi),
48799
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48800
0
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(-2147483648),
48801
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
48802
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48803
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48804
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48805
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs32),
48806
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
48807
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48808
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
48809
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48810
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48811
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48812
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48813
0
        GIR_EraseFromParent, /*InsnID*/0,
48814
        // GIR_Coverage, 3259,
48815
0
        GIR_Done,
48816
      // Label 2651: @156725
48817
0
      GIM_Reject,
48818
      // Label 2648: @156726
48819
0
      GIM_Try, /*On fail goto*//*Label 2652*/ GIMT_Encode4(156812), // Rule ID 3258 //
48820
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48821
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48822
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48823
        // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VMINVs16:{ *:[i32] } (t2MOVi16:{ *:[i32] } 32767:{ *:[i32] }), ?:{ *:[v8i16] }:$src)
48824
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
48825
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16),
48826
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48827
0
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767),
48828
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
48829
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48830
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48831
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs16),
48832
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
48833
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48834
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
48835
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48836
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48837
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48838
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48839
0
        GIR_EraseFromParent, /*InsnID*/0,
48840
        // GIR_Coverage, 3258,
48841
0
        GIR_Done,
48842
      // Label 2652: @156812
48843
0
      GIM_Reject,
48844
      // Label 2649: @156813
48845
0
      GIM_Try, /*On fail goto*//*Label 2653*/ GIMT_Encode4(156898), // Rule ID 3257 //
48846
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48847
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48848
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48849
        // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v16i8] }:$src)  =>  (MVE_VMINVs8:{ *:[i32] } (t2MOVi:{ *:[i32] } 127:{ *:[i32] }), ?:{ *:[v16i8] }:$src)
48850
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
48851
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
48852
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48853
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/127,
48854
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
48855
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48856
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48857
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48858
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs8),
48859
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
48860
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48861
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
48862
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48863
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48864
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48865
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48866
0
        GIR_EraseFromParent, /*InsnID*/0,
48867
        // GIR_Coverage, 3257,
48868
0
        GIR_Done,
48869
      // Label 2653: @156898
48870
0
      GIM_Reject,
48871
      // Label 2650: @156899
48872
0
      GIM_Reject,
48873
    // Label 2646: @156900
48874
0
    GIM_Reject,
48875
    // Label 72: @156901
48876
0
    GIM_Try, /*On fail goto*//*Label 2654*/ GIMT_Encode4(157212),
48877
0
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
48878
0
      GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2658*/ GIMT_Encode4(157211),
48879
0
      /*GILLT_v4s32*//*Label 2655*/ GIMT_Encode4(156953), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48880
0
      /*GILLT_v8s16*//*Label 2656*/ GIMT_Encode4(157039), GIMT_Encode4(0), GIMT_Encode4(0),
48881
0
      /*GILLT_v16s8*//*Label 2657*/ GIMT_Encode4(157125),
48882
      // Label 2655: @156953
48883
0
      GIM_Try, /*On fail goto*//*Label 2659*/ GIMT_Encode4(157038), // Rule ID 3256 //
48884
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48885
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48886
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48887
        // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VMAXVu32:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v4i32] }:$src)
48888
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
48889
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
48890
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48891
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
48892
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
48893
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48894
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48895
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48896
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu32),
48897
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
48898
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48899
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
48900
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48901
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48902
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48903
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48904
0
        GIR_EraseFromParent, /*InsnID*/0,
48905
        // GIR_Coverage, 3256,
48906
0
        GIR_Done,
48907
      // Label 2659: @157038
48908
0
      GIM_Reject,
48909
      // Label 2656: @157039
48910
0
      GIM_Try, /*On fail goto*//*Label 2660*/ GIMT_Encode4(157124), // Rule ID 3255 //
48911
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48912
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48913
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48914
        // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VMAXVu16:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v8i16] }:$src)
48915
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
48916
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
48917
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48918
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
48919
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
48920
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48921
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48922
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48923
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu16),
48924
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
48925
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48926
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
48927
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48928
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48929
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48930
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48931
0
        GIR_EraseFromParent, /*InsnID*/0,
48932
        // GIR_Coverage, 3255,
48933
0
        GIR_Done,
48934
      // Label 2660: @157124
48935
0
      GIM_Reject,
48936
      // Label 2657: @157125
48937
0
      GIM_Try, /*On fail goto*//*Label 2661*/ GIMT_Encode4(157210), // Rule ID 3254 //
48938
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48939
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48940
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48941
        // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v16i8] }:$src)  =>  (MVE_VMAXVu8:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v16i8] }:$src)
48942
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
48943
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
48944
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48945
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
48946
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
48947
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48948
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48949
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48950
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu8),
48951
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
48952
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48953
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
48954
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48955
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48956
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48957
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48958
0
        GIR_EraseFromParent, /*InsnID*/0,
48959
        // GIR_Coverage, 3254,
48960
0
        GIR_Done,
48961
      // Label 2661: @157210
48962
0
      GIM_Reject,
48963
      // Label 2658: @157211
48964
0
      GIM_Reject,
48965
    // Label 2654: @157212
48966
0
    GIM_Reject,
48967
    // Label 73: @157213
48968
0
    GIM_Try, /*On fail goto*//*Label 2662*/ GIMT_Encode4(157539),
48969
0
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
48970
0
      GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2666*/ GIMT_Encode4(157538),
48971
0
      /*GILLT_v4s32*//*Label 2663*/ GIMT_Encode4(157265), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48972
0
      /*GILLT_v8s16*//*Label 2664*/ GIMT_Encode4(157358), GIMT_Encode4(0), GIMT_Encode4(0),
48973
0
      /*GILLT_v16s8*//*Label 2665*/ GIMT_Encode4(157445),
48974
      // Label 2663: @157265
48975
0
      GIM_Try, /*On fail goto*//*Label 2667*/ GIMT_Encode4(157357), // Rule ID 3262 //
48976
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48977
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48978
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48979
        // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VMINVu32:{ *:[i32] } (t2MOVi:{ *:[i32] } 4294967295:{ *:[i32] }), ?:{ *:[v4i32] }:$src)
48980
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
48981
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
48982
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48983
0
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(4294967295),
48984
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
48985
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48986
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48987
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48988
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu32),
48989
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
48990
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48991
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
48992
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48993
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48994
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48995
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48996
0
        GIR_EraseFromParent, /*InsnID*/0,
48997
        // GIR_Coverage, 3262,
48998
0
        GIR_Done,
48999
      // Label 2667: @157357
49000
0
      GIM_Reject,
49001
      // Label 2664: @157358
49002
0
      GIM_Try, /*On fail goto*//*Label 2668*/ GIMT_Encode4(157444), // Rule ID 3261 //
49003
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
49004
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
49005
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
49006
        // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VMINVu16:{ *:[i32] } (t2MOVi16:{ *:[i32] } 65535:{ *:[i32] }), ?:{ *:[v8i16] }:$src)
49007
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
49008
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16),
49009
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49010
0
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535),
49011
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
49012
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49013
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
49014
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu16),
49015
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
49016
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49017
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
49018
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
49019
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49020
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49021
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
49022
0
        GIR_EraseFromParent, /*InsnID*/0,
49023
        // GIR_Coverage, 3261,
49024
0
        GIR_Done,
49025
      // Label 2668: @157444
49026
0
      GIM_Reject,
49027
      // Label 2665: @157445
49028
0
      GIM_Try, /*On fail goto*//*Label 2669*/ GIMT_Encode4(157537), // Rule ID 3260 //
49029
0
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
49030
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
49031
0
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
49032
        // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v16i8] }:$src)  =>  (MVE_VMINVu8:{ *:[i32] } (t2MOVi:{ *:[i32] } 255:{ *:[i32] }), ?:{ *:[v16i8] }:$src)
49033
0
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
49034
0
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
49035
0
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49036
0
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(255),
49037
0
        GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
49038
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49039
0
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49040
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
49041
0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu8),
49042
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[RdaDest]
49043
0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49044
0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
49045
0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
49046
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49047
0
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49048
0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
49049
0
        GIR_EraseFromParent, /*InsnID*/0,
49050
        // GIR_Coverage, 3260,
49051
0
        GIR_Done,
49052
      // Label 2669: @157537
49053
0
      GIM_Reject,
49054
      // Label 2666: @157538
49055
0
      GIM_Reject,
49056
    // Label 2662: @157539
49057
0
    GIM_Reject,
49058
    // Label 74: @157540
49059
0
    GIM_Reject,
49060
0
    }; // Size: 157541 bytes
49061
0
  return MatchTable0;
49062
0
}
49063
#undef GIMT_Encode2
49064
#undef GIMT_Encode4
49065
#undef GIMT_Encode8
49066
49067
#endif // ifdef GET_GLOBALISEL_IMPL
49068
49069
#ifdef GET_GLOBALISEL_PREDICATES_DECL
49070
PredicateBitset AvailableModuleFeatures;
49071
mutable PredicateBitset AvailableFunctionFeatures;
49072
0
PredicateBitset getAvailableFeatures() const {
49073
0
  return AvailableModuleFeatures | AvailableFunctionFeatures;
49074
0
}
49075
PredicateBitset
49076
computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const;
49077
PredicateBitset
49078
computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget,
49079
                                 const MachineFunction *MF) const;
49080
void setupGeneratedPerFunctionState(MachineFunction &MF) override;
49081
#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
49082
#ifdef GET_GLOBALISEL_PREDICATES_INIT
49083
AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
49084
AvailableFunctionFeatures()
49085
#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT