Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/ARM/ARMGenMCCodeEmitter.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Machine Code Emitter                                                       *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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uint64_t ARMMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
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    SmallVectorImpl<MCFixup> &Fixups,
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0
    const MCSubtargetInfo &STI) const {
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  static const uint64_t InstBits[] = {
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0
    UINT64_C(0),
509
0
    UINT64_C(0),
510
0
    UINT64_C(0),
511
0
    UINT64_C(0),
512
0
    UINT64_C(0),
513
0
    UINT64_C(0),
514
0
    UINT64_C(0),
515
0
    UINT64_C(0),
516
0
    UINT64_C(0),
517
0
    UINT64_C(0),
518
0
    UINT64_C(0),
519
0
    UINT64_C(0),
520
0
    UINT64_C(0),
521
0
    UINT64_C(0),
522
0
    UINT64_C(0),
523
0
    UINT64_C(0),
524
0
    UINT64_C(0),
525
0
    UINT64_C(0),
526
0
    UINT64_C(0),
527
0
    UINT64_C(0),
528
0
    UINT64_C(0),
529
0
    UINT64_C(0),
530
0
    UINT64_C(0),
531
0
    UINT64_C(0),
532
0
    UINT64_C(0),
533
0
    UINT64_C(0),
534
0
    UINT64_C(0),
535
0
    UINT64_C(0),
536
0
    UINT64_C(0),
537
0
    UINT64_C(0),
538
0
    UINT64_C(0),
539
0
    UINT64_C(0),
540
0
    UINT64_C(0),
541
0
    UINT64_C(0),
542
0
    UINT64_C(0),
543
0
    UINT64_C(0),
544
0
    UINT64_C(0),
545
0
    UINT64_C(0),
546
0
    UINT64_C(0),
547
0
    UINT64_C(0),
548
0
    UINT64_C(0),
549
0
    UINT64_C(0),
550
0
    UINT64_C(0),
551
0
    UINT64_C(0),
552
0
    UINT64_C(0),
553
0
    UINT64_C(0),
554
0
    UINT64_C(0),
555
0
    UINT64_C(0),
556
0
    UINT64_C(0),
557
0
    UINT64_C(0),
558
0
    UINT64_C(0),
559
0
    UINT64_C(0),
560
0
    UINT64_C(0),
561
0
    UINT64_C(0),
562
0
    UINT64_C(0),
563
0
    UINT64_C(0),
564
0
    UINT64_C(0),
565
0
    UINT64_C(0),
566
0
    UINT64_C(0),
567
0
    UINT64_C(0),
568
0
    UINT64_C(0),
569
0
    UINT64_C(0),
570
0
    UINT64_C(0),
571
0
    UINT64_C(0),
572
0
    UINT64_C(0),
573
0
    UINT64_C(0),
574
0
    UINT64_C(0),
575
0
    UINT64_C(0),
576
0
    UINT64_C(0),
577
0
    UINT64_C(0),
578
0
    UINT64_C(0),
579
0
    UINT64_C(0),
580
0
    UINT64_C(0),
581
0
    UINT64_C(0),
582
0
    UINT64_C(0),
583
0
    UINT64_C(0),
584
0
    UINT64_C(0),
585
0
    UINT64_C(0),
586
0
    UINT64_C(0),
587
0
    UINT64_C(0),
588
0
    UINT64_C(0),
589
0
    UINT64_C(0),
590
0
    UINT64_C(0),
591
0
    UINT64_C(0),
592
0
    UINT64_C(0),
593
0
    UINT64_C(0),
594
0
    UINT64_C(0),
595
0
    UINT64_C(0),
596
0
    UINT64_C(0),
597
0
    UINT64_C(0),
598
0
    UINT64_C(0),
599
0
    UINT64_C(0),
600
0
    UINT64_C(0),
601
0
    UINT64_C(0),
602
0
    UINT64_C(0),
603
0
    UINT64_C(0),
604
0
    UINT64_C(0),
605
0
    UINT64_C(0),
606
0
    UINT64_C(0),
607
0
    UINT64_C(0),
608
0
    UINT64_C(0),
609
0
    UINT64_C(0),
610
0
    UINT64_C(0),
611
0
    UINT64_C(0),
612
0
    UINT64_C(0),
613
0
    UINT64_C(0),
614
0
    UINT64_C(0),
615
0
    UINT64_C(0),
616
0
    UINT64_C(0),
617
0
    UINT64_C(0),
618
0
    UINT64_C(0),
619
0
    UINT64_C(0),
620
0
    UINT64_C(0),
621
0
    UINT64_C(0),
622
0
    UINT64_C(0),
623
0
    UINT64_C(0),
624
0
    UINT64_C(0),
625
0
    UINT64_C(0),
626
0
    UINT64_C(0),
627
0
    UINT64_C(0),
628
0
    UINT64_C(0),
629
0
    UINT64_C(0),
630
0
    UINT64_C(0),
631
0
    UINT64_C(0),
632
0
    UINT64_C(0),
633
0
    UINT64_C(0),
634
0
    UINT64_C(0),
635
0
    UINT64_C(0),
636
0
    UINT64_C(0),
637
0
    UINT64_C(0),
638
0
    UINT64_C(0),
639
0
    UINT64_C(0),
640
0
    UINT64_C(0),
641
0
    UINT64_C(0),
642
0
    UINT64_C(0),
643
0
    UINT64_C(0),
644
0
    UINT64_C(0),
645
0
    UINT64_C(0),
646
0
    UINT64_C(0),
647
0
    UINT64_C(0),
648
0
    UINT64_C(0),
649
0
    UINT64_C(0),
650
0
    UINT64_C(0),
651
0
    UINT64_C(0),
652
0
    UINT64_C(0),
653
0
    UINT64_C(0),
654
0
    UINT64_C(0),
655
0
    UINT64_C(0),
656
0
    UINT64_C(0),
657
0
    UINT64_C(0),
658
0
    UINT64_C(0),
659
0
    UINT64_C(0),
660
0
    UINT64_C(0),
661
0
    UINT64_C(0),
662
0
    UINT64_C(0),
663
0
    UINT64_C(0),
664
0
    UINT64_C(0),
665
0
    UINT64_C(0),
666
0
    UINT64_C(0),
667
0
    UINT64_C(0),
668
0
    UINT64_C(0),
669
0
    UINT64_C(0),
670
0
    UINT64_C(0),
671
0
    UINT64_C(0),
672
0
    UINT64_C(0),
673
0
    UINT64_C(0),
674
0
    UINT64_C(0),
675
0
    UINT64_C(0),
676
0
    UINT64_C(0),
677
0
    UINT64_C(0),
678
0
    UINT64_C(0),
679
0
    UINT64_C(0),
680
0
    UINT64_C(0),
681
0
    UINT64_C(0),
682
0
    UINT64_C(0),
683
0
    UINT64_C(0),
684
0
    UINT64_C(0),
685
0
    UINT64_C(0),
686
0
    UINT64_C(0),
687
0
    UINT64_C(0),
688
0
    UINT64_C(0),
689
0
    UINT64_C(0),
690
0
    UINT64_C(0),
691
0
    UINT64_C(0),
692
0
    UINT64_C(0),
693
0
    UINT64_C(0),
694
0
    UINT64_C(0),
695
0
    UINT64_C(0),
696
0
    UINT64_C(0),
697
0
    UINT64_C(0),
698
0
    UINT64_C(0),
699
0
    UINT64_C(0),
700
0
    UINT64_C(0),
701
0
    UINT64_C(0),
702
0
    UINT64_C(0),
703
0
    UINT64_C(0),
704
0
    UINT64_C(0),
705
0
    UINT64_C(0),
706
0
    UINT64_C(0),
707
0
    UINT64_C(0),
708
0
    UINT64_C(0),
709
0
    UINT64_C(0),
710
0
    UINT64_C(0),
711
0
    UINT64_C(0),
712
0
    UINT64_C(0),
713
0
    UINT64_C(0),
714
0
    UINT64_C(0),
715
0
    UINT64_C(0),
716
0
    UINT64_C(0),
717
0
    UINT64_C(0),
718
0
    UINT64_C(0),
719
0
    UINT64_C(0),
720
0
    UINT64_C(0),
721
0
    UINT64_C(0),
722
0
    UINT64_C(0),
723
0
    UINT64_C(0),
724
0
    UINT64_C(0),
725
0
    UINT64_C(0),
726
0
    UINT64_C(0),
727
0
    UINT64_C(0),
728
0
    UINT64_C(0),
729
0
    UINT64_C(0),
730
0
    UINT64_C(0),
731
0
    UINT64_C(0),
732
0
    UINT64_C(0),
733
0
    UINT64_C(0),
734
0
    UINT64_C(0),
735
0
    UINT64_C(0),
736
0
    UINT64_C(0),
737
0
    UINT64_C(0),
738
0
    UINT64_C(0),
739
0
    UINT64_C(0),
740
0
    UINT64_C(0),
741
0
    UINT64_C(0),
742
0
    UINT64_C(0),
743
0
    UINT64_C(0),
744
0
    UINT64_C(0),
745
0
    UINT64_C(0),
746
0
    UINT64_C(0),
747
0
    UINT64_C(0),
748
0
    UINT64_C(0),
749
0
    UINT64_C(0),
750
0
    UINT64_C(0),
751
0
    UINT64_C(0),
752
0
    UINT64_C(0),
753
0
    UINT64_C(0),
754
0
    UINT64_C(0),
755
0
    UINT64_C(0),
756
0
    UINT64_C(0),
757
0
    UINT64_C(0),
758
0
    UINT64_C(0),
759
0
    UINT64_C(0),
760
0
    UINT64_C(0),
761
0
    UINT64_C(44040192), // ADCri
762
0
    UINT64_C(10485760), // ADCrr
763
0
    UINT64_C(10485760), // ADCrsi
764
0
    UINT64_C(10485776), // ADCrsr
765
0
    UINT64_C(41943040), // ADDri
766
0
    UINT64_C(8388608),  // ADDrr
767
0
    UINT64_C(8388608),  // ADDrsi
768
0
    UINT64_C(8388624),  // ADDrsr
769
0
    UINT64_C(34537472), // ADR
770
0
    UINT64_C(4088398656), // AESD
771
0
    UINT64_C(4088398592), // AESE
772
0
    UINT64_C(4088398784), // AESIMC
773
0
    UINT64_C(4088398720), // AESMC
774
0
    UINT64_C(33554432), // ANDri
775
0
    UINT64_C(0),  // ANDrr
776
0
    UINT64_C(0),  // ANDrsi
777
0
    UINT64_C(16), // ANDrsr
778
0
    UINT64_C(4261416192), // BF16VDOTI_VDOTD
779
0
    UINT64_C(4261416256), // BF16VDOTI_VDOTQ
780
0
    UINT64_C(4227861760), // BF16VDOTS_VDOTD
781
0
    UINT64_C(4227861824), // BF16VDOTS_VDOTQ
782
0
    UINT64_C(4088792640), // BF16_VCVT
783
0
    UINT64_C(246614336),  // BF16_VCVTB
784
0
    UINT64_C(246614464),  // BF16_VCVTT
785
0
    UINT64_C(130023455),  // BFC
786
0
    UINT64_C(130023440),  // BFI
787
0
    UINT64_C(62914560), // BICri
788
0
    UINT64_C(29360128), // BICrr
789
0
    UINT64_C(29360128), // BICrsi
790
0
    UINT64_C(29360144), // BICrsr
791
0
    UINT64_C(3776970864), // BKPT
792
0
    UINT64_C(3942645760), // BL
793
0
    UINT64_C(3778019120), // BLX
794
0
    UINT64_C(19922736), // BLX_pred
795
0
    UINT64_C(4194304000), // BLXi
796
0
    UINT64_C(184549376),  // BL_pred
797
0
    UINT64_C(3778019088), // BX
798
0
    UINT64_C(19922720), // BXJ
799
0
    UINT64_C(19922718), // BX_RET
800
0
    UINT64_C(19922704), // BX_pred
801
0
    UINT64_C(167772160),  // Bcc
802
0
    UINT64_C(3992977408), // CDE_CX1
803
0
    UINT64_C(4261412864), // CDE_CX1A
804
0
    UINT64_C(3992977472), // CDE_CX1D
805
0
    UINT64_C(4261412928), // CDE_CX1DA
806
0
    UINT64_C(3997171712), // CDE_CX2
807
0
    UINT64_C(4265607168), // CDE_CX2A
808
0
    UINT64_C(3997171776), // CDE_CX2D
809
0
    UINT64_C(4265607232), // CDE_CX2DA
810
0
    UINT64_C(4001366016), // CDE_CX3
811
0
    UINT64_C(4269801472), // CDE_CX3A
812
0
    UINT64_C(4001366080), // CDE_CX3D
813
0
    UINT64_C(4269801536), // CDE_CX3DA
814
0
    UINT64_C(4246732800), // CDE_VCX1A_fpdp
815
0
    UINT64_C(4229955584), // CDE_VCX1A_fpsp
816
0
    UINT64_C(4229955648), // CDE_VCX1A_vec
817
0
    UINT64_C(3978297344), // CDE_VCX1_fpdp
818
0
    UINT64_C(3961520128), // CDE_VCX1_fpsp
819
0
    UINT64_C(3961520192), // CDE_VCX1_vec
820
0
    UINT64_C(4247781376), // CDE_VCX2A_fpdp
821
0
    UINT64_C(4231004160), // CDE_VCX2A_fpsp
822
0
    UINT64_C(4231004224), // CDE_VCX2A_vec
823
0
    UINT64_C(3979345920), // CDE_VCX2_fpdp
824
0
    UINT64_C(3962568704), // CDE_VCX2_fpsp
825
0
    UINT64_C(3962568768), // CDE_VCX2_vec
826
0
    UINT64_C(4253024256), // CDE_VCX3A_fpdp
827
0
    UINT64_C(4236247040), // CDE_VCX3A_fpsp
828
0
    UINT64_C(4236247104), // CDE_VCX3A_vec
829
0
    UINT64_C(3984588800), // CDE_VCX3_fpdp
830
0
    UINT64_C(3967811584), // CDE_VCX3_fpsp
831
0
    UINT64_C(3967811648), // CDE_VCX3_vec
832
0
    UINT64_C(234881024),  // CDP
833
0
    UINT64_C(4261412864), // CDP2
834
0
    UINT64_C(4118802463), // CLREX
835
0
    UINT64_C(24055568), // CLZ
836
0
    UINT64_C(57671680), // CMNri
837
0
    UINT64_C(24117248), // CMNzrr
838
0
    UINT64_C(24117248), // CMNzrsi
839
0
    UINT64_C(24117264), // CMNzrsr
840
0
    UINT64_C(55574528), // CMPri
841
0
    UINT64_C(22020096), // CMPrr
842
0
    UINT64_C(22020096), // CMPrsi
843
0
    UINT64_C(22020112), // CMPrsr
844
0
    UINT64_C(4043440128), // CPS1p
845
0
    UINT64_C(4043309056), // CPS2p
846
0
    UINT64_C(4043440128), // CPS3p
847
0
    UINT64_C(3774873664), // CRC32B
848
0
    UINT64_C(3774874176), // CRC32CB
849
0
    UINT64_C(3776971328), // CRC32CH
850
0
    UINT64_C(3779068480), // CRC32CW
851
0
    UINT64_C(3776970816), // CRC32H
852
0
    UINT64_C(3779067968), // CRC32W
853
0
    UINT64_C(52490480), // DBG
854
0
    UINT64_C(4118802512), // DMB
855
0
    UINT64_C(4118802496), // DSB
856
0
    UINT64_C(35651584), // EORri
857
0
    UINT64_C(2097152),  // EORrr
858
0
    UINT64_C(2097152),  // EORrsi
859
0
    UINT64_C(2097168),  // EORrsr
860
0
    UINT64_C(23068782), // ERET
861
0
    UINT64_C(246418176),  // FCONSTD
862
0
    UINT64_C(246417664),  // FCONSTH
863
0
    UINT64_C(246417920),  // FCONSTS
864
0
    UINT64_C(221252353),  // FLDMXDB_UPD
865
0
    UINT64_C(210766593),  // FLDMXIA
866
0
    UINT64_C(212863745),  // FLDMXIA_UPD
867
0
    UINT64_C(250739216),  // FMSTAT
868
0
    UINT64_C(220203777),  // FSTMXDB_UPD
869
0
    UINT64_C(209718017),  // FSTMXIA
870
0
    UINT64_C(211815169),  // FSTMXIA_UPD
871
0
    UINT64_C(52490240), // HINT
872
0
    UINT64_C(3774873712), // HLT
873
0
    UINT64_C(3779068016), // HVC
874
0
    UINT64_C(4118802528), // ISB
875
0
    UINT64_C(26217631), // LDA
876
0
    UINT64_C(30411935), // LDAB
877
0
    UINT64_C(26218143), // LDAEX
878
0
    UINT64_C(30412447), // LDAEXB
879
0
    UINT64_C(28315295), // LDAEXD
880
0
    UINT64_C(32509599), // LDAEXH
881
0
    UINT64_C(32509087), // LDAH
882
0
    UINT64_C(4249878528), // LDC2L_OFFSET
883
0
    UINT64_C(4241489920), // LDC2L_OPTION
884
0
    UINT64_C(4235198464), // LDC2L_POST
885
0
    UINT64_C(4251975680), // LDC2L_PRE
886
0
    UINT64_C(4245684224), // LDC2_OFFSET
887
0
    UINT64_C(4237295616), // LDC2_OPTION
888
0
    UINT64_C(4231004160), // LDC2_POST
889
0
    UINT64_C(4247781376), // LDC2_PRE
890
0
    UINT64_C(223346688),  // LDCL_OFFSET
891
0
    UINT64_C(214958080),  // LDCL_OPTION
892
0
    UINT64_C(208666624),  // LDCL_POST
893
0
    UINT64_C(225443840),  // LDCL_PRE
894
0
    UINT64_C(219152384),  // LDC_OFFSET
895
0
    UINT64_C(210763776),  // LDC_OPTION
896
0
    UINT64_C(204472320),  // LDC_POST
897
0
    UINT64_C(221249536),  // LDC_PRE
898
0
    UINT64_C(135266304),  // LDMDA
899
0
    UINT64_C(137363456),  // LDMDA_UPD
900
0
    UINT64_C(152043520),  // LDMDB
901
0
    UINT64_C(154140672),  // LDMDB_UPD
902
0
    UINT64_C(143654912),  // LDMIA
903
0
    UINT64_C(145752064),  // LDMIA_UPD
904
0
    UINT64_C(160432128),  // LDMIB
905
0
    UINT64_C(162529280),  // LDMIB_UPD
906
0
    UINT64_C(74448896), // LDRBT_POST_IMM
907
0
    UINT64_C(108003328),  // LDRBT_POST_REG
908
0
    UINT64_C(72351744), // LDRB_POST_IMM
909
0
    UINT64_C(105906176),  // LDRB_POST_REG
910
0
    UINT64_C(91226112), // LDRB_PRE_IMM
911
0
    UINT64_C(124780544),  // LDRB_PRE_REG
912
0
    UINT64_C(89128960), // LDRBi12
913
0
    UINT64_C(122683392),  // LDRBrs
914
0
    UINT64_C(16777424), // LDRD
915
0
    UINT64_C(208),  // LDRD_POST
916
0
    UINT64_C(18874576), // LDRD_PRE
917
0
    UINT64_C(26218399), // LDREX
918
0
    UINT64_C(30412703), // LDREXB
919
0
    UINT64_C(28315551), // LDREXD
920
0
    UINT64_C(32509855), // LDREXH
921
0
    UINT64_C(17825968), // LDRH
922
0
    UINT64_C(7340208),  // LDRHTi
923
0
    UINT64_C(3145904),  // LDRHTr
924
0
    UINT64_C(1048752),  // LDRH_POST
925
0
    UINT64_C(19923120), // LDRH_PRE
926
0
    UINT64_C(17826000), // LDRSB
927
0
    UINT64_C(7340240),  // LDRSBTi
928
0
    UINT64_C(3145936),  // LDRSBTr
929
0
    UINT64_C(1048784),  // LDRSB_POST
930
0
    UINT64_C(19923152), // LDRSB_PRE
931
0
    UINT64_C(17826032), // LDRSH
932
0
    UINT64_C(7340272),  // LDRSHTi
933
0
    UINT64_C(3145968),  // LDRSHTr
934
0
    UINT64_C(1048816),  // LDRSH_POST
935
0
    UINT64_C(19923184), // LDRSH_PRE
936
0
    UINT64_C(70254592), // LDRT_POST_IMM
937
0
    UINT64_C(103809024),  // LDRT_POST_REG
938
0
    UINT64_C(68157440), // LDR_POST_IMM
939
0
    UINT64_C(101711872),  // LDR_POST_REG
940
0
    UINT64_C(87031808), // LDR_PRE_IMM
941
0
    UINT64_C(120586240),  // LDR_PRE_REG
942
0
    UINT64_C(85917696), // LDRcp
943
0
    UINT64_C(84934656), // LDRi12
944
0
    UINT64_C(118489088),  // LDRrs
945
0
    UINT64_C(234881040),  // MCR
946
0
    UINT64_C(4261412880), // MCR2
947
0
    UINT64_C(205520896),  // MCRR
948
0
    UINT64_C(4232052736), // MCRR2
949
0
    UINT64_C(2097296),  // MLA
950
0
    UINT64_C(6291600),  // MLS
951
0
    UINT64_C(27324430), // MOVPCLR
952
0
    UINT64_C(54525952), // MOVTi16
953
0
    UINT64_C(60817408), // MOVi
954
0
    UINT64_C(50331648), // MOVi16
955
0
    UINT64_C(27262976), // MOVr
956
0
    UINT64_C(27262976), // MOVr_TC
957
0
    UINT64_C(27262976), // MOVsi
958
0
    UINT64_C(27262992), // MOVsr
959
0
    UINT64_C(235929616),  // MRC
960
0
    UINT64_C(4262461456), // MRC2
961
0
    UINT64_C(206569472),  // MRRC
962
0
    UINT64_C(4233101312), // MRRC2
963
0
    UINT64_C(17760256), // MRS
964
0
    UINT64_C(16777728), // MRSbanked
965
0
    UINT64_C(21954560), // MRSsys
966
0
    UINT64_C(18935808), // MSR
967
0
    UINT64_C(18936320), // MSRbanked
968
0
    UINT64_C(52490240), // MSRi
969
0
    UINT64_C(144),  // MUL
970
0
    UINT64_C(3931111727), // MVE_ASRLi
971
0
    UINT64_C(3931111725), // MVE_ASRLr
972
0
    UINT64_C(4027637761), // MVE_DLSTP_16
973
0
    UINT64_C(4028686337), // MVE_DLSTP_32
974
0
    UINT64_C(4029734913), // MVE_DLSTP_64
975
0
    UINT64_C(4026589185), // MVE_DLSTP_8
976
0
    UINT64_C(4027572225), // MVE_LCTP
977
0
    UINT64_C(4028612609), // MVE_LETP
978
0
    UINT64_C(3931111695), // MVE_LSLLi
979
0
    UINT64_C(3931111693), // MVE_LSLLr
980
0
    UINT64_C(3931111711), // MVE_LSRL
981
0
    UINT64_C(3931115309), // MVE_SQRSHR
982
0
    UINT64_C(3931177261), // MVE_SQRSHRL
983
0
    UINT64_C(3931115327), // MVE_SQSHL
984
0
    UINT64_C(3931177279), // MVE_SQSHLL
985
0
    UINT64_C(3931115311), // MVE_SRSHR
986
0
    UINT64_C(3931177263), // MVE_SRSHRL
987
0
    UINT64_C(3931115277), // MVE_UQRSHL
988
0
    UINT64_C(3931177229), // MVE_UQRSHLL
989
0
    UINT64_C(3931115279), // MVE_UQSHL
990
0
    UINT64_C(3931177231), // MVE_UQSHLL
991
0
    UINT64_C(3931115295), // MVE_URSHR
992
0
    UINT64_C(3931177247), // MVE_URSHRL
993
0
    UINT64_C(4002418433), // MVE_VABAVs16
994
0
    UINT64_C(4003467009), // MVE_VABAVs32
995
0
    UINT64_C(4001369857), // MVE_VABAVs8
996
0
    UINT64_C(4270853889), // MVE_VABAVu16
997
0
    UINT64_C(4271902465), // MVE_VABAVu32
998
0
    UINT64_C(4269805313), // MVE_VABAVu8
999
0
    UINT64_C(4281339200), // MVE_VABDf16
1000
0
    UINT64_C(4280290624), // MVE_VABDf32
1001
0
    UINT64_C(4010805056), // MVE_VABDs16
1002
0
    UINT64_C(4011853632), // MVE_VABDs32
1003
0
    UINT64_C(4009756480), // MVE_VABDs8
1004
0
    UINT64_C(4279240512), // MVE_VABDu16
1005
0
    UINT64_C(4280289088), // MVE_VABDu32
1006
0
    UINT64_C(4278191936), // MVE_VABDu8
1007
0
    UINT64_C(4290053952), // MVE_VABSf16
1008
0
    UINT64_C(4290316096), // MVE_VABSf32
1009
0
    UINT64_C(4290052928), // MVE_VABSs16
1010
0
    UINT64_C(4290315072), // MVE_VABSs32
1011
0
    UINT64_C(4289790784), // MVE_VABSs8
1012
0
    UINT64_C(3996126976), // MVE_VADC
1013
0
    UINT64_C(3996131072), // MVE_VADCI
1014
0
    UINT64_C(4001959712), // MVE_VADDLVs32acc
1015
0
    UINT64_C(4001959680), // MVE_VADDLVs32no_acc
1016
0
    UINT64_C(4270395168), // MVE_VADDLVu32acc
1017
0
    UINT64_C(4270395136), // MVE_VADDLVu32no_acc
1018
0
    UINT64_C(4009037600), // MVE_VADDVs16acc
1019
0
    UINT64_C(4009037568), // MVE_VADDVs16no_acc
1020
0
    UINT64_C(4009299744), // MVE_VADDVs32acc
1021
0
    UINT64_C(4009299712), // MVE_VADDVs32no_acc
1022
0
    UINT64_C(4008775456), // MVE_VADDVs8acc
1023
0
    UINT64_C(4008775424), // MVE_VADDVs8no_acc
1024
0
    UINT64_C(4277473056), // MVE_VADDVu16acc
1025
0
    UINT64_C(4277473024), // MVE_VADDVu16no_acc
1026
0
    UINT64_C(4277735200), // MVE_VADDVu32acc
1027
0
    UINT64_C(4277735168), // MVE_VADDVu32no_acc
1028
0
    UINT64_C(4277210912), // MVE_VADDVu8acc
1029
0
    UINT64_C(4277210880), // MVE_VADDVu8no_acc
1030
0
    UINT64_C(4264562496), // MVE_VADD_qr_f16
1031
0
    UINT64_C(3996127040), // MVE_VADD_qr_f32
1032
0
    UINT64_C(3994095424), // MVE_VADD_qr_i16
1033
0
    UINT64_C(3995144000), // MVE_VADD_qr_i32
1034
0
    UINT64_C(3993046848), // MVE_VADD_qr_i8
1035
0
    UINT64_C(4010806592), // MVE_VADDf16
1036
0
    UINT64_C(4009758016), // MVE_VADDf32
1037
0
    UINT64_C(4010805312), // MVE_VADDi16
1038
0
    UINT64_C(4011853888), // MVE_VADDi32
1039
0
    UINT64_C(4009756736), // MVE_VADDi8
1040
0
    UINT64_C(4009754960), // MVE_VAND
1041
0
    UINT64_C(4010803536), // MVE_VBIC
1042
0
    UINT64_C(4018145648), // MVE_VBICimmi16
1043
0
    UINT64_C(4018143600), // MVE_VBICimmi32
1044
0
    UINT64_C(4262534752), // MVE_VBRSR16
1045
0
    UINT64_C(4263583328), // MVE_VBRSR32
1046
0
    UINT64_C(4261486176), // MVE_VBRSR8
1047
0
    UINT64_C(4236249152), // MVE_VCADDf16
1048
0
    UINT64_C(4237297728), // MVE_VCADDf32
1049
0
    UINT64_C(4262465280), // MVE_VCADDi16
1050
0
    UINT64_C(4263513856), // MVE_VCADDi32
1051
0
    UINT64_C(4261416704), // MVE_VCADDi8
1052
0
    UINT64_C(4289987648), // MVE_VCLSs16
1053
0
    UINT64_C(4290249792), // MVE_VCLSs32
1054
0
    UINT64_C(4289725504), // MVE_VCLSs8
1055
0
    UINT64_C(4289987776), // MVE_VCLZs16
1056
0
    UINT64_C(4290249920), // MVE_VCLZs32
1057
0
    UINT64_C(4289725632), // MVE_VCLZs8
1058
0
    UINT64_C(4229957696), // MVE_VCMLAf16
1059
0
    UINT64_C(4231006272), // MVE_VCMLAf32
1060
0
    UINT64_C(4264627968), // MVE_VCMPf16
1061
0
    UINT64_C(4264628032), // MVE_VCMPf16r
1062
0
    UINT64_C(3996192512), // MVE_VCMPf32
1063
0
    UINT64_C(3996192576), // MVE_VCMPf32r
1064
0
    UINT64_C(4262530816), // MVE_VCMPi16
1065
0
    UINT64_C(4262530880), // MVE_VCMPi16r
1066
0
    UINT64_C(4263579392), // MVE_VCMPi32
1067
0
    UINT64_C(4263579456), // MVE_VCMPi32r
1068
0
    UINT64_C(4261482240), // MVE_VCMPi8
1069
0
    UINT64_C(4261482304), // MVE_VCMPi8r
1070
0
    UINT64_C(4262534912), // MVE_VCMPs16
1071
0
    UINT64_C(4262534976), // MVE_VCMPs16r
1072
0
    UINT64_C(4263583488), // MVE_VCMPs32
1073
0
    UINT64_C(4263583552), // MVE_VCMPs32r
1074
0
    UINT64_C(4261486336), // MVE_VCMPs8
1075
0
    UINT64_C(4261486400), // MVE_VCMPs8r
1076
0
    UINT64_C(4262530817), // MVE_VCMPu16
1077
0
    UINT64_C(4262530912), // MVE_VCMPu16r
1078
0
    UINT64_C(4263579393), // MVE_VCMPu32
1079
0
    UINT64_C(4263579488), // MVE_VCMPu32r
1080
0
    UINT64_C(4261482241), // MVE_VCMPu8
1081
0
    UINT64_C(4261482336), // MVE_VCMPu8r
1082
0
    UINT64_C(3996126720), // MVE_VCMULf16
1083
0
    UINT64_C(4264562176), // MVE_VCMULf32
1084
0
    UINT64_C(4027639809), // MVE_VCTP16
1085
0
    UINT64_C(4028688385), // MVE_VCTP32
1086
0
    UINT64_C(4029736961), // MVE_VCTP64
1087
0
    UINT64_C(4026591233), // MVE_VCTP8
1088
0
    UINT64_C(3997109761), // MVE_VCVTf16f32bh
1089
0
    UINT64_C(3997113857), // MVE_VCVTf16f32th
1090
0
    UINT64_C(4021292112), // MVE_VCVTf16s16_fix
1091
0
    UINT64_C(4290184768), // MVE_VCVTf16s16n
1092
0
    UINT64_C(4289727568), // MVE_VCVTf16u16_fix
1093
0
    UINT64_C(4290184896), // MVE_VCVTf16u16n
1094
0
    UINT64_C(4265545217), // MVE_VCVTf32f16bh
1095
0
    UINT64_C(4265549313), // MVE_VCVTf32f16th
1096
0
    UINT64_C(4020244048), // MVE_VCVTf32s32_fix
1097
0
    UINT64_C(4290446912), // MVE_VCVTf32s32n
1098
0
    UINT64_C(4288679504), // MVE_VCVTf32u32_fix
1099
0
    UINT64_C(4290447040), // MVE_VCVTf32u32n
1100
0
    UINT64_C(4021292368), // MVE_VCVTs16f16_fix
1101
0
    UINT64_C(4290183232), // MVE_VCVTs16f16a
1102
0
    UINT64_C(4290184000), // MVE_VCVTs16f16m
1103
0
    UINT64_C(4290183488), // MVE_VCVTs16f16n
1104
0
    UINT64_C(4290183744), // MVE_VCVTs16f16p
1105
0
    UINT64_C(4290185024), // MVE_VCVTs16f16z
1106
0
    UINT64_C(4020244304), // MVE_VCVTs32f32_fix
1107
0
    UINT64_C(4290445376), // MVE_VCVTs32f32a
1108
0
    UINT64_C(4290446144), // MVE_VCVTs32f32m
1109
0
    UINT64_C(4290445632), // MVE_VCVTs32f32n
1110
0
    UINT64_C(4290445888), // MVE_VCVTs32f32p
1111
0
    UINT64_C(4290447168), // MVE_VCVTs32f32z
1112
0
    UINT64_C(4289727824), // MVE_VCVTu16f16_fix
1113
0
    UINT64_C(4290183360), // MVE_VCVTu16f16a
1114
0
    UINT64_C(4290184128), // MVE_VCVTu16f16m
1115
0
    UINT64_C(4290183616), // MVE_VCVTu16f16n
1116
0
    UINT64_C(4290183872), // MVE_VCVTu16f16p
1117
0
    UINT64_C(4290185152), // MVE_VCVTu16f16z
1118
0
    UINT64_C(4288679760), // MVE_VCVTu32f32_fix
1119
0
    UINT64_C(4290445504), // MVE_VCVTu32f32a
1120
0
    UINT64_C(4290446272), // MVE_VCVTu32f32m
1121
0
    UINT64_C(4290445760), // MVE_VCVTu32f32n
1122
0
    UINT64_C(4290446016), // MVE_VCVTu32f32p
1123
0
    UINT64_C(4290447296), // MVE_VCVTu32f32z
1124
0
    UINT64_C(3994099566), // MVE_VDDUPu16
1125
0
    UINT64_C(3995148142), // MVE_VDDUPu32
1126
0
    UINT64_C(3993050990), // MVE_VDDUPu8
1127
0
    UINT64_C(4003466032), // MVE_VDUP16
1128
0
    UINT64_C(4003466000), // MVE_VDUP32
1129
0
    UINT64_C(4007660304), // MVE_VDUP8
1130
0
    UINT64_C(3994099552), // MVE_VDWDUPu16
1131
0
    UINT64_C(3995148128), // MVE_VDWDUPu32
1132
0
    UINT64_C(3993050976), // MVE_VDWDUPu8
1133
0
    UINT64_C(4278190416), // MVE_VEOR
1134
0
    UINT64_C(4264631872), // MVE_VFMA_qr_Sf16
1135
0
    UINT64_C(3996196416), // MVE_VFMA_qr_Sf32
1136
0
    UINT64_C(4264627776), // MVE_VFMA_qr_f16
1137
0
    UINT64_C(3996192320), // MVE_VFMA_qr_f32
1138
0
    UINT64_C(4010806352), // MVE_VFMAf16
1139
0
    UINT64_C(4009757776), // MVE_VFMAf32
1140
0
    UINT64_C(4012903504), // MVE_VFMSf16
1141
0
    UINT64_C(4011854928), // MVE_VFMSf32
1142
0
    UINT64_C(3994029888), // MVE_VHADD_qr_s16
1143
0
    UINT64_C(3995078464), // MVE_VHADD_qr_s32
1144
0
    UINT64_C(3992981312), // MVE_VHADD_qr_s8
1145
0
    UINT64_C(4262465344), // MVE_VHADD_qr_u16
1146
0
    UINT64_C(4263513920), // MVE_VHADD_qr_u32
1147
0
    UINT64_C(4261416768), // MVE_VHADD_qr_u8
1148
0
    UINT64_C(4010803264), // MVE_VHADDs16
1149
0
    UINT64_C(4011851840), // MVE_VHADDs32
1150
0
    UINT64_C(4009754688), // MVE_VHADDs8
1151
0
    UINT64_C(4279238720), // MVE_VHADDu16
1152
0
    UINT64_C(4280287296), // MVE_VHADDu32
1153
0
    UINT64_C(4278190144), // MVE_VHADDu8
1154
0
    UINT64_C(3994029824), // MVE_VHCADDs16
1155
0
    UINT64_C(3995078400), // MVE_VHCADDs32
1156
0
    UINT64_C(3992981248), // MVE_VHCADDs8
1157
0
    UINT64_C(3994033984), // MVE_VHSUB_qr_s16
1158
0
    UINT64_C(3995082560), // MVE_VHSUB_qr_s32
1159
0
    UINT64_C(3992985408), // MVE_VHSUB_qr_s8
1160
0
    UINT64_C(4262469440), // MVE_VHSUB_qr_u16
1161
0
    UINT64_C(4263518016), // MVE_VHSUB_qr_u32
1162
0
    UINT64_C(4261420864), // MVE_VHSUB_qr_u8
1163
0
    UINT64_C(4010803776), // MVE_VHSUBs16
1164
0
    UINT64_C(4011852352), // MVE_VHSUBs32
1165
0
    UINT64_C(4009755200), // MVE_VHSUBs8
1166
0
    UINT64_C(4279239232), // MVE_VHSUBu16
1167
0
    UINT64_C(4280287808), // MVE_VHSUBu32
1168
0
    UINT64_C(4278190656), // MVE_VHSUBu8
1169
0
    UINT64_C(3994095470), // MVE_VIDUPu16
1170
0
    UINT64_C(3995144046), // MVE_VIDUPu32
1171
0
    UINT64_C(3993046894), // MVE_VIDUPu8
1172
0
    UINT64_C(3994095456), // MVE_VIWDUPu16
1173
0
    UINT64_C(3995144032), // MVE_VIWDUPu32
1174
0
    UINT64_C(3993046880), // MVE_VIWDUPu8
1175
0
    UINT64_C(4237303424), // MVE_VLD20_16
1176
0
    UINT64_C(4239400576), // MVE_VLD20_16_wb
1177
0
    UINT64_C(4237303552), // MVE_VLD20_32
1178
0
    UINT64_C(4239400704), // MVE_VLD20_32_wb
1179
0
    UINT64_C(4237303296), // MVE_VLD20_8
1180
0
    UINT64_C(4239400448), // MVE_VLD20_8_wb
1181
0
    UINT64_C(4237303456), // MVE_VLD21_16
1182
0
    UINT64_C(4239400608), // MVE_VLD21_16_wb
1183
0
    UINT64_C(4237303584), // MVE_VLD21_32
1184
0
    UINT64_C(4239400736), // MVE_VLD21_32_wb
1185
0
    UINT64_C(4237303328), // MVE_VLD21_8
1186
0
    UINT64_C(4239400480), // MVE_VLD21_8_wb
1187
0
    UINT64_C(4237303425), // MVE_VLD40_16
1188
0
    UINT64_C(4239400577), // MVE_VLD40_16_wb
1189
0
    UINT64_C(4237303553), // MVE_VLD40_32
1190
0
    UINT64_C(4239400705), // MVE_VLD40_32_wb
1191
0
    UINT64_C(4237303297), // MVE_VLD40_8
1192
0
    UINT64_C(4239400449), // MVE_VLD40_8_wb
1193
0
    UINT64_C(4237303457), // MVE_VLD41_16
1194
0
    UINT64_C(4239400609), // MVE_VLD41_16_wb
1195
0
    UINT64_C(4237303585), // MVE_VLD41_32
1196
0
    UINT64_C(4239400737), // MVE_VLD41_32_wb
1197
0
    UINT64_C(4237303329), // MVE_VLD41_8
1198
0
    UINT64_C(4239400481), // MVE_VLD41_8_wb
1199
0
    UINT64_C(4237303489), // MVE_VLD42_16
1200
0
    UINT64_C(4239400641), // MVE_VLD42_16_wb
1201
0
    UINT64_C(4237303617), // MVE_VLD42_32
1202
0
    UINT64_C(4239400769), // MVE_VLD42_32_wb
1203
0
    UINT64_C(4237303361), // MVE_VLD42_8
1204
0
    UINT64_C(4239400513), // MVE_VLD42_8_wb
1205
0
    UINT64_C(4237303521), // MVE_VLD43_16
1206
0
    UINT64_C(4239400673), // MVE_VLD43_16_wb
1207
0
    UINT64_C(4237303649), // MVE_VLD43_32
1208
0
    UINT64_C(4239400801), // MVE_VLD43_32_wb
1209
0
    UINT64_C(4237303393), // MVE_VLD43_8
1210
0
    UINT64_C(4239400545), // MVE_VLD43_8_wb
1211
0
    UINT64_C(3977252480), // MVE_VLDRBS16
1212
0
    UINT64_C(3962572416), // MVE_VLDRBS16_post
1213
0
    UINT64_C(3979349632), // MVE_VLDRBS16_pre
1214
0
    UINT64_C(3968863872), // MVE_VLDRBS16_rq
1215
0
    UINT64_C(3977252608), // MVE_VLDRBS32
1216
0
    UINT64_C(3962572544), // MVE_VLDRBS32_post
1217
0
    UINT64_C(3979349760), // MVE_VLDRBS32_pre
1218
0
    UINT64_C(3968864000), // MVE_VLDRBS32_rq
1219
0
    UINT64_C(4245687936), // MVE_VLDRBU16
1220
0
    UINT64_C(4231007872), // MVE_VLDRBU16_post
1221
0
    UINT64_C(4247785088), // MVE_VLDRBU16_pre
1222
0
    UINT64_C(4237299328), // MVE_VLDRBU16_rq
1223
0
    UINT64_C(4245688064), // MVE_VLDRBU32
1224
0
    UINT64_C(4231008000), // MVE_VLDRBU32_post
1225
0
    UINT64_C(4247785216), // MVE_VLDRBU32_pre
1226
0
    UINT64_C(4237299456), // MVE_VLDRBU32_rq
1227
0
    UINT64_C(3977256448), // MVE_VLDRBU8
1228
0
    UINT64_C(3962576384), // MVE_VLDRBU8_post
1229
0
    UINT64_C(3979353600), // MVE_VLDRBU8_pre
1230
0
    UINT64_C(4237299200), // MVE_VLDRBU8_rq
1231
0
    UINT64_C(4245692160), // MVE_VLDRDU64_qi
1232
0
    UINT64_C(4247789312), // MVE_VLDRDU64_qi_pre
1233
0
    UINT64_C(4237299665), // MVE_VLDRDU64_rq
1234
0
    UINT64_C(4237299664), // MVE_VLDRDU64_rq_u
1235
0
    UINT64_C(3977776896), // MVE_VLDRHS32
1236
0
    UINT64_C(3963096832), // MVE_VLDRHS32_post
1237
0
    UINT64_C(3979874048), // MVE_VLDRHS32_pre
1238
0
    UINT64_C(3968864017), // MVE_VLDRHS32_rq
1239
0
    UINT64_C(3968864016), // MVE_VLDRHS32_rq_u
1240
0
    UINT64_C(3977256576), // MVE_VLDRHU16
1241
0
    UINT64_C(3962576512), // MVE_VLDRHU16_post
1242
0
    UINT64_C(3979353728), // MVE_VLDRHU16_pre
1243
0
    UINT64_C(4237299345), // MVE_VLDRHU16_rq
1244
0
    UINT64_C(4237299344), // MVE_VLDRHU16_rq_u
1245
0
    UINT64_C(4246212352), // MVE_VLDRHU32
1246
0
    UINT64_C(4231532288), // MVE_VLDRHU32_post
1247
0
    UINT64_C(4248309504), // MVE_VLDRHU32_pre
1248
0
    UINT64_C(4237299473), // MVE_VLDRHU32_rq
1249
0
    UINT64_C(4237299472), // MVE_VLDRHU32_rq_u
1250
0
    UINT64_C(3977256704), // MVE_VLDRWU32
1251
0
    UINT64_C(3962576640), // MVE_VLDRWU32_post
1252
0
    UINT64_C(3979353856), // MVE_VLDRWU32_pre
1253
0
    UINT64_C(4245691904), // MVE_VLDRWU32_qi
1254
0
    UINT64_C(4247789056), // MVE_VLDRWU32_qi_pre
1255
0
    UINT64_C(4237299521), // MVE_VLDRWU32_rq
1256
0
    UINT64_C(4237299520), // MVE_VLDRWU32_rq_u
1257
0
    UINT64_C(4007923456), // MVE_VMAXAVs16
1258
0
    UINT64_C(4008185600), // MVE_VMAXAVs32
1259
0
    UINT64_C(4007661312), // MVE_VMAXAVs8
1260
0
    UINT64_C(3996585601), // MVE_VMAXAs16
1261
0
    UINT64_C(3996847745), // MVE_VMAXAs32
1262
0
    UINT64_C(3996323457), // MVE_VMAXAs8
1263
0
    UINT64_C(4276883200), // MVE_VMAXNMAVf16
1264
0
    UINT64_C(4008447744), // MVE_VMAXNMAVf32
1265
0
    UINT64_C(4265545345), // MVE_VMAXNMAf16
1266
0
    UINT64_C(3997109889), // MVE_VMAXNMAf32
1267
0
    UINT64_C(4277014272), // MVE_VMAXNMVf16
1268
0
    UINT64_C(4008578816), // MVE_VMAXNMVf32
1269
0
    UINT64_C(4279242576), // MVE_VMAXNMf16
1270
0
    UINT64_C(4278194000), // MVE_VMAXNMf32
1271
0
    UINT64_C(4008054528), // MVE_VMAXVs16
1272
0
    UINT64_C(4008316672), // MVE_VMAXVs32
1273
0
    UINT64_C(4007792384), // MVE_VMAXVs8
1274
0
    UINT64_C(4276489984), // MVE_VMAXVu16
1275
0
    UINT64_C(4276752128), // MVE_VMAXVu32
1276
0
    UINT64_C(4276227840), // MVE_VMAXVu8
1277
0
    UINT64_C(4010804800), // MVE_VMAXs16
1278
0
    UINT64_C(4011853376), // MVE_VMAXs32
1279
0
    UINT64_C(4009756224), // MVE_VMAXs8
1280
0
    UINT64_C(4279240256), // MVE_VMAXu16
1281
0
    UINT64_C(4280288832), // MVE_VMAXu32
1282
0
    UINT64_C(4278191680), // MVE_VMAXu8
1283
0
    UINT64_C(4007923584), // MVE_VMINAVs16
1284
0
    UINT64_C(4008185728), // MVE_VMINAVs32
1285
0
    UINT64_C(4007661440), // MVE_VMINAVs8
1286
0
    UINT64_C(3996589697), // MVE_VMINAs16
1287
0
    UINT64_C(3996851841), // MVE_VMINAs32
1288
0
    UINT64_C(3996327553), // MVE_VMINAs8
1289
0
    UINT64_C(4276883328), // MVE_VMINNMAVf16
1290
0
    UINT64_C(4008447872), // MVE_VMINNMAVf32
1291
0
    UINT64_C(4265549441), // MVE_VMINNMAf16
1292
0
    UINT64_C(3997113985), // MVE_VMINNMAf32
1293
0
    UINT64_C(4277014400), // MVE_VMINNMVf16
1294
0
    UINT64_C(4008578944), // MVE_VMINNMVf32
1295
0
    UINT64_C(4281339728), // MVE_VMINNMf16
1296
0
    UINT64_C(4280291152), // MVE_VMINNMf32
1297
0
    UINT64_C(4008054656), // MVE_VMINVs16
1298
0
    UINT64_C(4008316800), // MVE_VMINVs32
1299
0
    UINT64_C(4007792512), // MVE_VMINVs8
1300
0
    UINT64_C(4276490112), // MVE_VMINVu16
1301
0
    UINT64_C(4276752256), // MVE_VMINVu32
1302
0
    UINT64_C(4276227968), // MVE_VMINVu8
1303
0
    UINT64_C(4010804816), // MVE_VMINs16
1304
0
    UINT64_C(4011853392), // MVE_VMINs32
1305
0
    UINT64_C(4009756240), // MVE_VMINs8
1306
0
    UINT64_C(4279240272), // MVE_VMINu16
1307
0
    UINT64_C(4280288848), // MVE_VMINu32
1308
0
    UINT64_C(4278191696), // MVE_VMINu8
1309
0
    UINT64_C(4008709664), // MVE_VMLADAVas16
1310
0
    UINT64_C(4008775200), // MVE_VMLADAVas32
1311
0
    UINT64_C(4008709920), // MVE_VMLADAVas8
1312
0
    UINT64_C(4277145120), // MVE_VMLADAVau16
1313
0
    UINT64_C(4277210656), // MVE_VMLADAVau32
1314
0
    UINT64_C(4277145376), // MVE_VMLADAVau8
1315
0
    UINT64_C(4008713760), // MVE_VMLADAVaxs16
1316
0
    UINT64_C(4008779296), // MVE_VMLADAVaxs32
1317
0
    UINT64_C(4008714016), // MVE_VMLADAVaxs8
1318
0
    UINT64_C(4008709632), // MVE_VMLADAVs16
1319
0
    UINT64_C(4008775168), // MVE_VMLADAVs32
1320
0
    UINT64_C(4008709888), // MVE_VMLADAVs8
1321
0
    UINT64_C(4277145088), // MVE_VMLADAVu16
1322
0
    UINT64_C(4277210624), // MVE_VMLADAVu32
1323
0
    UINT64_C(4277145344), // MVE_VMLADAVu8
1324
0
    UINT64_C(4008713728), // MVE_VMLADAVxs16
1325
0
    UINT64_C(4008779264), // MVE_VMLADAVxs32
1326
0
    UINT64_C(4008713984), // MVE_VMLADAVxs8
1327
0
    UINT64_C(4001369632), // MVE_VMLALDAVas16
1328
0
    UINT64_C(4001435168), // MVE_VMLALDAVas32
1329
0
    UINT64_C(4269805088), // MVE_VMLALDAVau16
1330
0
    UINT64_C(4269870624), // MVE_VMLALDAVau32
1331
0
    UINT64_C(4001373728), // MVE_VMLALDAVaxs16
1332
0
    UINT64_C(4001439264), // MVE_VMLALDAVaxs32
1333
0
    UINT64_C(4001369600), // MVE_VMLALDAVs16
1334
0
    UINT64_C(4001435136), // MVE_VMLALDAVs32
1335
0
    UINT64_C(4269805056), // MVE_VMLALDAVu16
1336
0
    UINT64_C(4269870592), // MVE_VMLALDAVu32
1337
0
    UINT64_C(4001373696), // MVE_VMLALDAVxs16
1338
0
    UINT64_C(4001439232), // MVE_VMLALDAVxs32
1339
0
    UINT64_C(3994099264), // MVE_VMLAS_qr_i16
1340
0
    UINT64_C(3995147840), // MVE_VMLAS_qr_i32
1341
0
    UINT64_C(3993050688), // MVE_VMLAS_qr_i8
1342
0
    UINT64_C(3994095168), // MVE_VMLA_qr_i16
1343
0
    UINT64_C(3995143744), // MVE_VMLA_qr_i32
1344
0
    UINT64_C(3993046592), // MVE_VMLA_qr_i8
1345
0
    UINT64_C(4008709665), // MVE_VMLSDAVas16
1346
0
    UINT64_C(4008775201), // MVE_VMLSDAVas32
1347
0
    UINT64_C(4277145121), // MVE_VMLSDAVas8
1348
0
    UINT64_C(4008713761), // MVE_VMLSDAVaxs16
1349
0
    UINT64_C(4008779297), // MVE_VMLSDAVaxs32
1350
0
    UINT64_C(4277149217), // MVE_VMLSDAVaxs8
1351
0
    UINT64_C(4008709633), // MVE_VMLSDAVs16
1352
0
    UINT64_C(4008775169), // MVE_VMLSDAVs32
1353
0
    UINT64_C(4277145089), // MVE_VMLSDAVs8
1354
0
    UINT64_C(4008713729), // MVE_VMLSDAVxs16
1355
0
    UINT64_C(4008779265), // MVE_VMLSDAVxs32
1356
0
    UINT64_C(4277149185), // MVE_VMLSDAVxs8
1357
0
    UINT64_C(4001369633), // MVE_VMLSLDAVas16
1358
0
    UINT64_C(4001435169), // MVE_VMLSLDAVas32
1359
0
    UINT64_C(4001373729), // MVE_VMLSLDAVaxs16
1360
0
    UINT64_C(4001439265), // MVE_VMLSLDAVaxs32
1361
0
    UINT64_C(4001369601), // MVE_VMLSLDAVs16
1362
0
    UINT64_C(4001435137), // MVE_VMLSLDAVs32
1363
0
    UINT64_C(4001373697), // MVE_VMLSLDAVxs16
1364
0
    UINT64_C(4001439233), // MVE_VMLSLDAVxs32
1365
0
    UINT64_C(4004515648), // MVE_VMOVLs16bh
1366
0
    UINT64_C(4004519744), // MVE_VMOVLs16th
1367
0
    UINT64_C(4003991360), // MVE_VMOVLs8bh
1368
0
    UINT64_C(4003995456), // MVE_VMOVLs8th
1369
0
    UINT64_C(4272951104), // MVE_VMOVLu16bh
1370
0
    UINT64_C(4272955200), // MVE_VMOVLu16th
1371
0
    UINT64_C(4272426816), // MVE_VMOVLu8bh
1372
0
    UINT64_C(4272430912), // MVE_VMOVLu8th
1373
0
    UINT64_C(4264627841), // MVE_VMOVNi16bh
1374
0
    UINT64_C(4264631937), // MVE_VMOVNi16th
1375
0
    UINT64_C(4264889985), // MVE_VMOVNi32bh
1376
0
    UINT64_C(4264894081), // MVE_VMOVNi32th
1377
0
    UINT64_C(3994028816), // MVE_VMOV_from_lane_32
1378
0
    UINT64_C(3994028848), // MVE_VMOV_from_lane_s16
1379
0
    UINT64_C(3998223120), // MVE_VMOV_from_lane_s8
1380
0
    UINT64_C(4002417456), // MVE_VMOV_from_lane_u16
1381
0
    UINT64_C(4006611728), // MVE_VMOV_from_lane_u8
1382
0
    UINT64_C(3960475392), // MVE_VMOV_q_rr
1383
0
    UINT64_C(3959426816), // MVE_VMOV_rr_q
1384
0
    UINT64_C(3992980272), // MVE_VMOV_to_lane_16
1385
0
    UINT64_C(3992980240), // MVE_VMOV_to_lane_32
1386
0
    UINT64_C(3997174544), // MVE_VMOV_to_lane_8
1387
0
    UINT64_C(4018147152), // MVE_VMOVimmf32
1388
0
    UINT64_C(4018145360), // MVE_VMOVimmi16
1389
0
    UINT64_C(4018143312), // MVE_VMOVimmi32
1390
0
    UINT64_C(4018146928), // MVE_VMOVimmi64
1391
0
    UINT64_C(4018146896), // MVE_VMOVimmi8
1392
0
    UINT64_C(3994095105), // MVE_VMULHs16
1393
0
    UINT64_C(3995143681), // MVE_VMULHs32
1394
0
    UINT64_C(3993046529), // MVE_VMULHs8
1395
0
    UINT64_C(4262530561), // MVE_VMULHu16
1396
0
    UINT64_C(4263579137), // MVE_VMULHu32
1397
0
    UINT64_C(4261481985), // MVE_VMULHu8
1398
0
    UINT64_C(4264627712), // MVE_VMULLBp16
1399
0
    UINT64_C(3996192256), // MVE_VMULLBp8
1400
0
    UINT64_C(3994095104), // MVE_VMULLBs16
1401
0
    UINT64_C(3995143680), // MVE_VMULLBs32
1402
0
    UINT64_C(3993046528), // MVE_VMULLBs8
1403
0
    UINT64_C(4262530560), // MVE_VMULLBu16
1404
0
    UINT64_C(4263579136), // MVE_VMULLBu32
1405
0
    UINT64_C(4261481984), // MVE_VMULLBu8
1406
0
    UINT64_C(4264631808), // MVE_VMULLTp16
1407
0
    UINT64_C(3996196352), // MVE_VMULLTp8
1408
0
    UINT64_C(3994099200), // MVE_VMULLTs16
1409
0
    UINT64_C(3995147776), // MVE_VMULLTs32
1410
0
    UINT64_C(3993050624), // MVE_VMULLTs8
1411
0
    UINT64_C(4262534656), // MVE_VMULLTu16
1412
0
    UINT64_C(4263583232), // MVE_VMULLTu32
1413
0
    UINT64_C(4261486080), // MVE_VMULLTu8
1414
0
    UINT64_C(4264627808), // MVE_VMUL_qr_f16
1415
0
    UINT64_C(3996192352), // MVE_VMUL_qr_f32
1416
0
    UINT64_C(3994099296), // MVE_VMUL_qr_i16
1417
0
    UINT64_C(3995147872), // MVE_VMUL_qr_i32
1418
0
    UINT64_C(3993050720), // MVE_VMUL_qr_i8
1419
0
    UINT64_C(4279242064), // MVE_VMULf16
1420
0
    UINT64_C(4278193488), // MVE_VMULf32
1421
0
    UINT64_C(4010805584), // MVE_VMULi16
1422
0
    UINT64_C(4011854160), // MVE_VMULi32
1423
0
    UINT64_C(4009757008), // MVE_VMULi8
1424
0
    UINT64_C(4289725888), // MVE_VMVN
1425
0
    UINT64_C(4018145392), // MVE_VMVNimmi16
1426
0
    UINT64_C(4018143344), // MVE_VMVNimmi32
1427
0
    UINT64_C(4290054080), // MVE_VNEGf16
1428
0
    UINT64_C(4290316224), // MVE_VNEGf32
1429
0
    UINT64_C(4290053056), // MVE_VNEGs16
1430
0
    UINT64_C(4290315200), // MVE_VNEGs32
1431
0
    UINT64_C(4289790912), // MVE_VNEGs8
1432
0
    UINT64_C(4012900688), // MVE_VORN
1433
0
    UINT64_C(4011852112), // MVE_VORR
1434
0
    UINT64_C(4018145616), // MVE_VORRimmi16
1435
0
    UINT64_C(4018143568), // MVE_VORRimmi32
1436
0
    UINT64_C(4264628045), // MVE_VPNOT
1437
0
    UINT64_C(4264627969), // MVE_VPSEL
1438
0
    UINT64_C(4264628045), // MVE_VPST
1439
0
    UINT64_C(4261482240), // MVE_VPTv16i8
1440
0
    UINT64_C(4261482304), // MVE_VPTv16i8r
1441
0
    UINT64_C(4261486336), // MVE_VPTv16s8
1442
0
    UINT64_C(4261486400), // MVE_VPTv16s8r
1443
0
    UINT64_C(4261482241), // MVE_VPTv16u8
1444
0
    UINT64_C(4261482336), // MVE_VPTv16u8r
1445
0
    UINT64_C(3996192512), // MVE_VPTv4f32
1446
0
    UINT64_C(3996192576), // MVE_VPTv4f32r
1447
0
    UINT64_C(4263579392), // MVE_VPTv4i32
1448
0
    UINT64_C(4263579456), // MVE_VPTv4i32r
1449
0
    UINT64_C(4263583488), // MVE_VPTv4s32
1450
0
    UINT64_C(4263583552), // MVE_VPTv4s32r
1451
0
    UINT64_C(4263579393), // MVE_VPTv4u32
1452
0
    UINT64_C(4263579488), // MVE_VPTv4u32r
1453
0
    UINT64_C(4264627968), // MVE_VPTv8f16
1454
0
    UINT64_C(4264628032), // MVE_VPTv8f16r
1455
0
    UINT64_C(4262530816), // MVE_VPTv8i16
1456
0
    UINT64_C(4262530880), // MVE_VPTv8i16r
1457
0
    UINT64_C(4262534912), // MVE_VPTv8s16
1458
0
    UINT64_C(4262534976), // MVE_VPTv8s16r
1459
0
    UINT64_C(4262530817), // MVE_VPTv8u16
1460
0
    UINT64_C(4262530912), // MVE_VPTv8u16r
1461
0
    UINT64_C(4289988416), // MVE_VQABSs16
1462
0
    UINT64_C(4290250560), // MVE_VQABSs32
1463
0
    UINT64_C(4289726272), // MVE_VQABSs8
1464
0
    UINT64_C(3994029920), // MVE_VQADD_qr_s16
1465
0
    UINT64_C(3995078496), // MVE_VQADD_qr_s32
1466
0
    UINT64_C(3992981344), // MVE_VQADD_qr_s8
1467
0
    UINT64_C(4262465376), // MVE_VQADD_qr_u16
1468
0
    UINT64_C(4263513952), // MVE_VQADD_qr_u32
1469
0
    UINT64_C(4261416800), // MVE_VQADD_qr_u8
1470
0
    UINT64_C(4010803280), // MVE_VQADDs16
1471
0
    UINT64_C(4011851856), // MVE_VQADDs32
1472
0
    UINT64_C(4009754704), // MVE_VQADDs8
1473
0
    UINT64_C(4279238736), // MVE_VQADDu16
1474
0
    UINT64_C(4280287312), // MVE_VQADDu32
1475
0
    UINT64_C(4278190160), // MVE_VQADDu8
1476
0
    UINT64_C(3994033664), // MVE_VQDMLADHXs16
1477
0
    UINT64_C(3995082240), // MVE_VQDMLADHXs32
1478
0
    UINT64_C(3992985088), // MVE_VQDMLADHXs8
1479
0
    UINT64_C(3994029568), // MVE_VQDMLADHs16
1480
0
    UINT64_C(3995078144), // MVE_VQDMLADHs32
1481
0
    UINT64_C(3992980992), // MVE_VQDMLADHs8
1482
0
    UINT64_C(3994029664), // MVE_VQDMLAH_qrs16
1483
0
    UINT64_C(3995078240), // MVE_VQDMLAH_qrs32
1484
0
    UINT64_C(3992981088), // MVE_VQDMLAH_qrs8
1485
0
    UINT64_C(3994033760), // MVE_VQDMLASH_qrs16
1486
0
    UINT64_C(3995082336), // MVE_VQDMLASH_qrs32
1487
0
    UINT64_C(3992985184), // MVE_VQDMLASH_qrs8
1488
0
    UINT64_C(4262469120), // MVE_VQDMLSDHXs16
1489
0
    UINT64_C(4263517696), // MVE_VQDMLSDHXs32
1490
0
    UINT64_C(4261420544), // MVE_VQDMLSDHXs8
1491
0
    UINT64_C(4262465024), // MVE_VQDMLSDHs16
1492
0
    UINT64_C(4263513600), // MVE_VQDMLSDHs32
1493
0
    UINT64_C(4261416448), // MVE_VQDMLSDHs8
1494
0
    UINT64_C(3994095200), // MVE_VQDMULH_qr_s16
1495
0
    UINT64_C(3995143776), // MVE_VQDMULH_qr_s32
1496
0
    UINT64_C(3993046624), // MVE_VQDMULH_qr_s8
1497
0
    UINT64_C(4010806080), // MVE_VQDMULHi16
1498
0
    UINT64_C(4011854656), // MVE_VQDMULHi32
1499
0
    UINT64_C(4009757504), // MVE_VQDMULHi8
1500
0
    UINT64_C(3996127072), // MVE_VQDMULL_qr_s16bh
1501
0
    UINT64_C(3996131168), // MVE_VQDMULL_qr_s16th
1502
0
    UINT64_C(4264562528), // MVE_VQDMULL_qr_s32bh
1503
0
    UINT64_C(4264566624), // MVE_VQDMULL_qr_s32th
1504
0
    UINT64_C(3996126977), // MVE_VQDMULLs16bh
1505
0
    UINT64_C(3996131073), // MVE_VQDMULLs16th
1506
0
    UINT64_C(4264562433), // MVE_VQDMULLs32bh
1507
0
    UINT64_C(4264566529), // MVE_VQDMULLs32th
1508
0
    UINT64_C(3996323329), // MVE_VQMOVNs16bh
1509
0
    UINT64_C(3996327425), // MVE_VQMOVNs16th
1510
0
    UINT64_C(3996585473), // MVE_VQMOVNs32bh
1511
0
    UINT64_C(3996589569), // MVE_VQMOVNs32th
1512
0
    UINT64_C(4264758785), // MVE_VQMOVNu16bh
1513
0
    UINT64_C(4264762881), // MVE_VQMOVNu16th
1514
0
    UINT64_C(4265020929), // MVE_VQMOVNu32bh
1515
0
    UINT64_C(4265025025), // MVE_VQMOVNu32th
1516
0
    UINT64_C(3996192385), // MVE_VQMOVUNs16bh
1517
0
    UINT64_C(3996196481), // MVE_VQMOVUNs16th
1518
0
    UINT64_C(3996454529), // MVE_VQMOVUNs32bh
1519
0
    UINT64_C(3996458625), // MVE_VQMOVUNs32th
1520
0
    UINT64_C(4289988544), // MVE_VQNEGs16
1521
0
    UINT64_C(4290250688), // MVE_VQNEGs32
1522
0
    UINT64_C(4289726400), // MVE_VQNEGs8
1523
0
    UINT64_C(3994033665), // MVE_VQRDMLADHXs16
1524
0
    UINT64_C(3995082241), // MVE_VQRDMLADHXs32
1525
0
    UINT64_C(3992985089), // MVE_VQRDMLADHXs8
1526
0
    UINT64_C(3994029569), // MVE_VQRDMLADHs16
1527
0
    UINT64_C(3995078145), // MVE_VQRDMLADHs32
1528
0
    UINT64_C(3992980993), // MVE_VQRDMLADHs8
1529
0
    UINT64_C(3994029632), // MVE_VQRDMLAH_qrs16
1530
0
    UINT64_C(3995078208), // MVE_VQRDMLAH_qrs32
1531
0
    UINT64_C(3992981056), // MVE_VQRDMLAH_qrs8
1532
0
    UINT64_C(3994033728), // MVE_VQRDMLASH_qrs16
1533
0
    UINT64_C(3995082304), // MVE_VQRDMLASH_qrs32
1534
0
    UINT64_C(3992985152), // MVE_VQRDMLASH_qrs8
1535
0
    UINT64_C(4262469121), // MVE_VQRDMLSDHXs16
1536
0
    UINT64_C(4263517697), // MVE_VQRDMLSDHXs32
1537
0
    UINT64_C(4261420545), // MVE_VQRDMLSDHXs8
1538
0
    UINT64_C(4262465025), // MVE_VQRDMLSDHs16
1539
0
    UINT64_C(4263513601), // MVE_VQRDMLSDHs32
1540
0
    UINT64_C(4261416449), // MVE_VQRDMLSDHs8
1541
0
    UINT64_C(4262530656), // MVE_VQRDMULH_qr_s16
1542
0
    UINT64_C(4263579232), // MVE_VQRDMULH_qr_s32
1543
0
    UINT64_C(4261482080), // MVE_VQRDMULH_qr_s8
1544
0
    UINT64_C(4279241536), // MVE_VQRDMULHi16
1545
0
    UINT64_C(4280290112), // MVE_VQRDMULHi32
1546
0
    UINT64_C(4278192960), // MVE_VQRDMULHi8
1547
0
    UINT64_C(4010804560), // MVE_VQRSHL_by_vecs16
1548
0
    UINT64_C(4011853136), // MVE_VQRSHL_by_vecs32
1549
0
    UINT64_C(4009755984), // MVE_VQRSHL_by_vecs8
1550
0
    UINT64_C(4279240016), // MVE_VQRSHL_by_vecu16
1551
0
    UINT64_C(4280288592), // MVE_VQRSHL_by_vecu32
1552
0
    UINT64_C(4278191440), // MVE_VQRSHL_by_vecu8
1553
0
    UINT64_C(3996589792), // MVE_VQRSHL_qrs16
1554
0
    UINT64_C(3996851936), // MVE_VQRSHL_qrs32
1555
0
    UINT64_C(3996327648), // MVE_VQRSHL_qrs8
1556
0
    UINT64_C(4265025248), // MVE_VQRSHL_qru16
1557
0
    UINT64_C(4265287392), // MVE_VQRSHL_qru32
1558
0
    UINT64_C(4264763104), // MVE_VQRSHL_qru8
1559
0
    UINT64_C(4001894209), // MVE_VQRSHRNbhs16
1560
0
    UINT64_C(4002418497), // MVE_VQRSHRNbhs32
1561
0
    UINT64_C(4270329665), // MVE_VQRSHRNbhu16
1562
0
    UINT64_C(4270853953), // MVE_VQRSHRNbhu32
1563
0
    UINT64_C(4001898305), // MVE_VQRSHRNths16
1564
0
    UINT64_C(4002422593), // MVE_VQRSHRNths32
1565
0
    UINT64_C(4270333761), // MVE_VQRSHRNthu16
1566
0
    UINT64_C(4270858049), // MVE_VQRSHRNthu32
1567
0
    UINT64_C(4270329792), // MVE_VQRSHRUNs16bh
1568
0
    UINT64_C(4270333888), // MVE_VQRSHRUNs16th
1569
0
    UINT64_C(4270854080), // MVE_VQRSHRUNs32bh
1570
0
    UINT64_C(4270858176), // MVE_VQRSHRUNs32th
1571
0
    UINT64_C(4287628880), // MVE_VQSHLU_imms16
1572
0
    UINT64_C(4288677456), // MVE_VQSHLU_imms32
1573
0
    UINT64_C(4287104592), // MVE_VQSHLU_imms8
1574
0
    UINT64_C(4010804304), // MVE_VQSHL_by_vecs16
1575
0
    UINT64_C(4011852880), // MVE_VQSHL_by_vecs32
1576
0
    UINT64_C(4009755728), // MVE_VQSHL_by_vecs8
1577
0
    UINT64_C(4279239760), // MVE_VQSHL_by_vecu16
1578
0
    UINT64_C(4280288336), // MVE_VQSHL_by_vecu32
1579
0
    UINT64_C(4278191184), // MVE_VQSHL_by_vecu8
1580
0
    UINT64_C(3996458720), // MVE_VQSHL_qrs16
1581
0
    UINT64_C(3996720864), // MVE_VQSHL_qrs32
1582
0
    UINT64_C(3996196576), // MVE_VQSHL_qrs8
1583
0
    UINT64_C(4264894176), // MVE_VQSHL_qru16
1584
0
    UINT64_C(4265156320), // MVE_VQSHL_qru32
1585
0
    UINT64_C(4264632032), // MVE_VQSHL_qru8
1586
0
    UINT64_C(4019193680), // MVE_VQSHLimms16
1587
0
    UINT64_C(4020242256), // MVE_VQSHLimms32
1588
0
    UINT64_C(4018669392), // MVE_VQSHLimms8
1589
0
    UINT64_C(4287629136), // MVE_VQSHLimmu16
1590
0
    UINT64_C(4288677712), // MVE_VQSHLimmu32
1591
0
    UINT64_C(4287104848), // MVE_VQSHLimmu8
1592
0
    UINT64_C(4001894208), // MVE_VQSHRNbhs16
1593
0
    UINT64_C(4002418496), // MVE_VQSHRNbhs32
1594
0
    UINT64_C(4270329664), // MVE_VQSHRNbhu16
1595
0
    UINT64_C(4270853952), // MVE_VQSHRNbhu32
1596
0
    UINT64_C(4001898304), // MVE_VQSHRNths16
1597
0
    UINT64_C(4002422592), // MVE_VQSHRNths32
1598
0
    UINT64_C(4270333760), // MVE_VQSHRNthu16
1599
0
    UINT64_C(4270858048), // MVE_VQSHRNthu32
1600
0
    UINT64_C(4001894336), // MVE_VQSHRUNs16bh
1601
0
    UINT64_C(4001898432), // MVE_VQSHRUNs16th
1602
0
    UINT64_C(4002418624), // MVE_VQSHRUNs32bh
1603
0
    UINT64_C(4002422720), // MVE_VQSHRUNs32th
1604
0
    UINT64_C(3994034016), // MVE_VQSUB_qr_s16
1605
0
    UINT64_C(3995082592), // MVE_VQSUB_qr_s32
1606
0
    UINT64_C(3992985440), // MVE_VQSUB_qr_s8
1607
0
    UINT64_C(4262469472), // MVE_VQSUB_qr_u16
1608
0
    UINT64_C(4263518048), // MVE_VQSUB_qr_u32
1609
0
    UINT64_C(4261420896), // MVE_VQSUB_qr_u8
1610
0
    UINT64_C(4010803792), // MVE_VQSUBs16
1611
0
    UINT64_C(4011852368), // MVE_VQSUBs32
1612
0
    UINT64_C(4009755216), // MVE_VQSUBs8
1613
0
    UINT64_C(4279239248), // MVE_VQSUBu16
1614
0
    UINT64_C(4280287824), // MVE_VQSUBu32
1615
0
    UINT64_C(4278190672), // MVE_VQSUBu8
1616
0
    UINT64_C(4289724736), // MVE_VREV16_8
1617
0
    UINT64_C(4289986752), // MVE_VREV32_16
1618
0
    UINT64_C(4289724608), // MVE_VREV32_8
1619
0
    UINT64_C(4289986624), // MVE_VREV64_16
1620
0
    UINT64_C(4290248768), // MVE_VREV64_32
1621
0
    UINT64_C(4289724480), // MVE_VREV64_8
1622
0
    UINT64_C(4010803520), // MVE_VRHADDs16
1623
0
    UINT64_C(4011852096), // MVE_VRHADDs32
1624
0
    UINT64_C(4009754944), // MVE_VRHADDs8
1625
0
    UINT64_C(4279238976), // MVE_VRHADDu16
1626
0
    UINT64_C(4280287552), // MVE_VRHADDu32
1627
0
    UINT64_C(4278190400), // MVE_VRHADDu8
1628
0
    UINT64_C(4290118976), // MVE_VRINTf16A
1629
0
    UINT64_C(4290119360), // MVE_VRINTf16M
1630
0
    UINT64_C(4290118720), // MVE_VRINTf16N
1631
0
    UINT64_C(4290119616), // MVE_VRINTf16P
1632
0
    UINT64_C(4290118848), // MVE_VRINTf16X
1633
0
    UINT64_C(4290119104), // MVE_VRINTf16Z
1634
0
    UINT64_C(4290381120), // MVE_VRINTf32A
1635
0
    UINT64_C(4290381504), // MVE_VRINTf32M
1636
0
    UINT64_C(4290380864), // MVE_VRINTf32N
1637
0
    UINT64_C(4290381760), // MVE_VRINTf32P
1638
0
    UINT64_C(4290380992), // MVE_VRINTf32X
1639
0
    UINT64_C(4290381248), // MVE_VRINTf32Z
1640
0
    UINT64_C(4001369888), // MVE_VRMLALDAVHas32
1641
0
    UINT64_C(4269805344), // MVE_VRMLALDAVHau32
1642
0
    UINT64_C(4001373984), // MVE_VRMLALDAVHaxs32
1643
0
    UINT64_C(4001369856), // MVE_VRMLALDAVHs32
1644
0
    UINT64_C(4269805312), // MVE_VRMLALDAVHu32
1645
0
    UINT64_C(4001373952), // MVE_VRMLALDAVHxs32
1646
0
    UINT64_C(4269805089), // MVE_VRMLSLDAVHas32
1647
0
    UINT64_C(4269809185), // MVE_VRMLSLDAVHaxs32
1648
0
    UINT64_C(4269805057), // MVE_VRMLSLDAVHs32
1649
0
    UINT64_C(4269809153), // MVE_VRMLSLDAVHxs32
1650
0
    UINT64_C(3994099201), // MVE_VRMULHs16
1651
0
    UINT64_C(3995147777), // MVE_VRMULHs32
1652
0
    UINT64_C(3993050625), // MVE_VRMULHs8
1653
0
    UINT64_C(4262534657), // MVE_VRMULHu16
1654
0
    UINT64_C(4263583233), // MVE_VRMULHu32
1655
0
    UINT64_C(4261486081), // MVE_VRMULHu8
1656
0
    UINT64_C(4010804544), // MVE_VRSHL_by_vecs16
1657
0
    UINT64_C(4011853120), // MVE_VRSHL_by_vecs32
1658
0
    UINT64_C(4009755968), // MVE_VRSHL_by_vecs8
1659
0
    UINT64_C(4279240000), // MVE_VRSHL_by_vecu16
1660
0
    UINT64_C(4280288576), // MVE_VRSHL_by_vecu32
1661
0
    UINT64_C(4278191424), // MVE_VRSHL_by_vecu8
1662
0
    UINT64_C(3996589664), // MVE_VRSHL_qrs16
1663
0
    UINT64_C(3996851808), // MVE_VRSHL_qrs32
1664
0
    UINT64_C(3996327520), // MVE_VRSHL_qrs8
1665
0
    UINT64_C(4265025120), // MVE_VRSHL_qru16
1666
0
    UINT64_C(4265287264), // MVE_VRSHL_qru32
1667
0
    UINT64_C(4264762976), // MVE_VRSHL_qru8
1668
0
    UINT64_C(4270329793), // MVE_VRSHRNi16bh
1669
0
    UINT64_C(4270333889), // MVE_VRSHRNi16th
1670
0
    UINT64_C(4270854081), // MVE_VRSHRNi32bh
1671
0
    UINT64_C(4270858177), // MVE_VRSHRNi32th
1672
0
    UINT64_C(4019192400), // MVE_VRSHR_imms16
1673
0
    UINT64_C(4020240976), // MVE_VRSHR_imms32
1674
0
    UINT64_C(4018668112), // MVE_VRSHR_imms8
1675
0
    UINT64_C(4287627856), // MVE_VRSHR_immu16
1676
0
    UINT64_C(4288676432), // MVE_VRSHR_immu32
1677
0
    UINT64_C(4287103568), // MVE_VRSHR_immu8
1678
0
    UINT64_C(4264562432), // MVE_VSBC
1679
0
    UINT64_C(4264566528), // MVE_VSBCI
1680
0
    UINT64_C(4003467200), // MVE_VSHLC
1681
0
    UINT64_C(4004515648), // MVE_VSHLL_imms16bh
1682
0
    UINT64_C(4004519744), // MVE_VSHLL_imms16th
1683
0
    UINT64_C(4003991360), // MVE_VSHLL_imms8bh
1684
0
    UINT64_C(4003995456), // MVE_VSHLL_imms8th
1685
0
    UINT64_C(4272951104), // MVE_VSHLL_immu16bh
1686
0
    UINT64_C(4272955200), // MVE_VSHLL_immu16th
1687
0
    UINT64_C(4272426816), // MVE_VSHLL_immu8bh
1688
0
    UINT64_C(4272430912), // MVE_VSHLL_immu8th
1689
0
    UINT64_C(3996454401), // MVE_VSHLL_lws16bh
1690
0
    UINT64_C(3996458497), // MVE_VSHLL_lws16th
1691
0
    UINT64_C(3996192257), // MVE_VSHLL_lws8bh
1692
0
    UINT64_C(3996196353), // MVE_VSHLL_lws8th
1693
0
    UINT64_C(4264889857), // MVE_VSHLL_lwu16bh
1694
0
    UINT64_C(4264893953), // MVE_VSHLL_lwu16th
1695
0
    UINT64_C(4264627713), // MVE_VSHLL_lwu8bh
1696
0
    UINT64_C(4264631809), // MVE_VSHLL_lwu8th
1697
0
    UINT64_C(4010804288), // MVE_VSHL_by_vecs16
1698
0
    UINT64_C(4011852864), // MVE_VSHL_by_vecs32
1699
0
    UINT64_C(4009755712), // MVE_VSHL_by_vecs8
1700
0
    UINT64_C(4279239744), // MVE_VSHL_by_vecu16
1701
0
    UINT64_C(4280288320), // MVE_VSHL_by_vecu32
1702
0
    UINT64_C(4278191168), // MVE_VSHL_by_vecu8
1703
0
    UINT64_C(4019193168), // MVE_VSHL_immi16
1704
0
    UINT64_C(4020241744), // MVE_VSHL_immi32
1705
0
    UINT64_C(4018668880), // MVE_VSHL_immi8
1706
0
    UINT64_C(3996458592), // MVE_VSHL_qrs16
1707
0
    UINT64_C(3996720736), // MVE_VSHL_qrs32
1708
0
    UINT64_C(3996196448), // MVE_VSHL_qrs8
1709
0
    UINT64_C(4264894048), // MVE_VSHL_qru16
1710
0
    UINT64_C(4265156192), // MVE_VSHL_qru32
1711
0
    UINT64_C(4264631904), // MVE_VSHL_qru8
1712
0
    UINT64_C(4001894337), // MVE_VSHRNi16bh
1713
0
    UINT64_C(4001898433), // MVE_VSHRNi16th
1714
0
    UINT64_C(4002418625), // MVE_VSHRNi32bh
1715
0
    UINT64_C(4002422721), // MVE_VSHRNi32th
1716
0
    UINT64_C(4019191888), // MVE_VSHR_imms16
1717
0
    UINT64_C(4020240464), // MVE_VSHR_imms32
1718
0
    UINT64_C(4018667600), // MVE_VSHR_imms8
1719
0
    UINT64_C(4287627344), // MVE_VSHR_immu16
1720
0
    UINT64_C(4288675920), // MVE_VSHR_immu32
1721
0
    UINT64_C(4287103056), // MVE_VSHR_immu8
1722
0
    UINT64_C(4287628624), // MVE_VSLIimm16
1723
0
    UINT64_C(4288677200), // MVE_VSLIimm32
1724
0
    UINT64_C(4287104336), // MVE_VSLIimm8
1725
0
    UINT64_C(4287628368), // MVE_VSRIimm16
1726
0
    UINT64_C(4288676944), // MVE_VSRIimm32
1727
0
    UINT64_C(4287104080), // MVE_VSRIimm8
1728
0
    UINT64_C(4236254848), // MVE_VST20_16
1729
0
    UINT64_C(4238352000), // MVE_VST20_16_wb
1730
0
    UINT64_C(4236254976), // MVE_VST20_32
1731
0
    UINT64_C(4238352128), // MVE_VST20_32_wb
1732
0
    UINT64_C(4236254720), // MVE_VST20_8
1733
0
    UINT64_C(4238351872), // MVE_VST20_8_wb
1734
0
    UINT64_C(4236254880), // MVE_VST21_16
1735
0
    UINT64_C(4238352032), // MVE_VST21_16_wb
1736
0
    UINT64_C(4236255008), // MVE_VST21_32
1737
0
    UINT64_C(4238352160), // MVE_VST21_32_wb
1738
0
    UINT64_C(4236254752), // MVE_VST21_8
1739
0
    UINT64_C(4238351904), // MVE_VST21_8_wb
1740
0
    UINT64_C(4236254849), // MVE_VST40_16
1741
0
    UINT64_C(4238352001), // MVE_VST40_16_wb
1742
0
    UINT64_C(4236254977), // MVE_VST40_32
1743
0
    UINT64_C(4238352129), // MVE_VST40_32_wb
1744
0
    UINT64_C(4236254721), // MVE_VST40_8
1745
0
    UINT64_C(4238351873), // MVE_VST40_8_wb
1746
0
    UINT64_C(4236254881), // MVE_VST41_16
1747
0
    UINT64_C(4238352033), // MVE_VST41_16_wb
1748
0
    UINT64_C(4236255009), // MVE_VST41_32
1749
0
    UINT64_C(4238352161), // MVE_VST41_32_wb
1750
0
    UINT64_C(4236254753), // MVE_VST41_8
1751
0
    UINT64_C(4238351905), // MVE_VST41_8_wb
1752
0
    UINT64_C(4236254913), // MVE_VST42_16
1753
0
    UINT64_C(4238352065), // MVE_VST42_16_wb
1754
0
    UINT64_C(4236255041), // MVE_VST42_32
1755
0
    UINT64_C(4238352193), // MVE_VST42_32_wb
1756
0
    UINT64_C(4236254785), // MVE_VST42_8
1757
0
    UINT64_C(4238351937), // MVE_VST42_8_wb
1758
0
    UINT64_C(4236254945), // MVE_VST43_16
1759
0
    UINT64_C(4238352097), // MVE_VST43_16_wb
1760
0
    UINT64_C(4236255073), // MVE_VST43_32
1761
0
    UINT64_C(4238352225), // MVE_VST43_32_wb
1762
0
    UINT64_C(4236254817), // MVE_VST43_8
1763
0
    UINT64_C(4238351969), // MVE_VST43_8_wb
1764
0
    UINT64_C(3976203904), // MVE_VSTRB16
1765
0
    UINT64_C(3961523840), // MVE_VSTRB16_post
1766
0
    UINT64_C(3978301056), // MVE_VSTRB16_pre
1767
0
    UINT64_C(3967815296), // MVE_VSTRB16_rq
1768
0
    UINT64_C(3976204032), // MVE_VSTRB32
1769
0
    UINT64_C(3961523968), // MVE_VSTRB32_post
1770
0
    UINT64_C(3978301184), // MVE_VSTRB32_pre
1771
0
    UINT64_C(3967815424), // MVE_VSTRB32_rq
1772
0
    UINT64_C(3967815168), // MVE_VSTRB8_rq
1773
0
    UINT64_C(3976207872), // MVE_VSTRBU8
1774
0
    UINT64_C(3961527808), // MVE_VSTRBU8_post
1775
0
    UINT64_C(3978305024), // MVE_VSTRBU8_pre
1776
0
    UINT64_C(4244643584), // MVE_VSTRD64_qi
1777
0
    UINT64_C(4246740736), // MVE_VSTRD64_qi_pre
1778
0
    UINT64_C(3967815633), // MVE_VSTRD64_rq
1779
0
    UINT64_C(3967815632), // MVE_VSTRD64_rq_u
1780
0
    UINT64_C(3967815313), // MVE_VSTRH16_rq
1781
0
    UINT64_C(3967815312), // MVE_VSTRH16_rq_u
1782
0
    UINT64_C(3976728320), // MVE_VSTRH32
1783
0
    UINT64_C(3962048256), // MVE_VSTRH32_post
1784
0
    UINT64_C(3978825472), // MVE_VSTRH32_pre
1785
0
    UINT64_C(3967815441), // MVE_VSTRH32_rq
1786
0
    UINT64_C(3967815440), // MVE_VSTRH32_rq_u
1787
0
    UINT64_C(3976208000), // MVE_VSTRHU16
1788
0
    UINT64_C(3961527936), // MVE_VSTRHU16_post
1789
0
    UINT64_C(3978305152), // MVE_VSTRHU16_pre
1790
0
    UINT64_C(4244643328), // MVE_VSTRW32_qi
1791
0
    UINT64_C(4246740480), // MVE_VSTRW32_qi_pre
1792
0
    UINT64_C(3967815489), // MVE_VSTRW32_rq
1793
0
    UINT64_C(3967815488), // MVE_VSTRW32_rq_u
1794
0
    UINT64_C(3976208128), // MVE_VSTRWU32
1795
0
    UINT64_C(3961528064), // MVE_VSTRWU32_post
1796
0
    UINT64_C(3978305280), // MVE_VSTRWU32_pre
1797
0
    UINT64_C(4264566592), // MVE_VSUB_qr_f16
1798
0
    UINT64_C(3996131136), // MVE_VSUB_qr_f32
1799
0
    UINT64_C(3994099520), // MVE_VSUB_qr_i16
1800
0
    UINT64_C(3995148096), // MVE_VSUB_qr_i32
1801
0
    UINT64_C(3993050944), // MVE_VSUB_qr_i8
1802
0
    UINT64_C(4012903744), // MVE_VSUBf16
1803
0
    UINT64_C(4011855168), // MVE_VSUBf32
1804
0
    UINT64_C(4279240768), // MVE_VSUBi16
1805
0
    UINT64_C(4280289344), // MVE_VSUBi32
1806
0
    UINT64_C(4278192192), // MVE_VSUBi8
1807
0
    UINT64_C(4027629569), // MVE_WLSTP_16
1808
0
    UINT64_C(4028678145), // MVE_WLSTP_32
1809
0
    UINT64_C(4029726721), // MVE_WLSTP_64
1810
0
    UINT64_C(4026580993), // MVE_WLSTP_8
1811
0
    UINT64_C(65011712), // MVNi
1812
0
    UINT64_C(31457280), // MVNr
1813
0
    UINT64_C(31457280), // MVNsi
1814
0
    UINT64_C(31457296), // MVNsr
1815
0
    UINT64_C(4076867344), // NEON_VMAXNMNDf
1816
0
    UINT64_C(4077915920), // NEON_VMAXNMNDh
1817
0
    UINT64_C(4076867408), // NEON_VMAXNMNQf
1818
0
    UINT64_C(4077915984), // NEON_VMAXNMNQh
1819
0
    UINT64_C(4078964496), // NEON_VMINNMNDf
1820
0
    UINT64_C(4080013072), // NEON_VMINNMNDh
1821
0
    UINT64_C(4078964560), // NEON_VMINNMNQf
1822
0
    UINT64_C(4080013136), // NEON_VMINNMNQh
1823
0
    UINT64_C(58720256), // ORRri
1824
0
    UINT64_C(25165824), // ORRrr
1825
0
    UINT64_C(25165824), // ORRrsi
1826
0
    UINT64_C(25165840), // ORRrsr
1827
0
    UINT64_C(109051920),  // PKHBT
1828
0
    UINT64_C(109051984),  // PKHTB
1829
0
    UINT64_C(4111527936), // PLDWi12
1830
0
    UINT64_C(4145082368), // PLDWrs
1831
0
    UINT64_C(4115722240), // PLDi12
1832
0
    UINT64_C(4149276672), // PLDrs
1833
0
    UINT64_C(4098945024), // PLIi12
1834
0
    UINT64_C(4132499456), // PLIrs
1835
0
    UINT64_C(16777296), // QADD
1836
0
    UINT64_C(102764304),  // QADD16
1837
0
    UINT64_C(102764432),  // QADD8
1838
0
    UINT64_C(102764336),  // QASX
1839
0
    UINT64_C(20971600), // QDADD
1840
0
    UINT64_C(23068752), // QDSUB
1841
0
    UINT64_C(102764368),  // QSAX
1842
0
    UINT64_C(18874448), // QSUB
1843
0
    UINT64_C(102764400),  // QSUB16
1844
0
    UINT64_C(102764528),  // QSUB8
1845
0
    UINT64_C(117378864),  // RBIT
1846
0
    UINT64_C(113184560),  // REV
1847
0
    UINT64_C(113184688),  // REV16
1848
0
    UINT64_C(117378992),  // REVSH
1849
0
    UINT64_C(4161800704), // RFEDA
1850
0
    UINT64_C(4163897856), // RFEDA_UPD
1851
0
    UINT64_C(4178577920), // RFEDB
1852
0
    UINT64_C(4180675072), // RFEDB_UPD
1853
0
    UINT64_C(4170189312), // RFEIA
1854
0
    UINT64_C(4172286464), // RFEIA_UPD
1855
0
    UINT64_C(4186966528), // RFEIB
1856
0
    UINT64_C(4189063680), // RFEIB_UPD
1857
0
    UINT64_C(39845888), // RSBri
1858
0
    UINT64_C(6291456),  // RSBrr
1859
0
    UINT64_C(6291456),  // RSBrsi
1860
0
    UINT64_C(6291472),  // RSBrsr
1861
0
    UINT64_C(48234496), // RSCri
1862
0
    UINT64_C(14680064), // RSCrr
1863
0
    UINT64_C(14680064), // RSCrsi
1864
0
    UINT64_C(14680080), // RSCrsr
1865
0
    UINT64_C(101715728),  // SADD16
1866
0
    UINT64_C(101715856),  // SADD8
1867
0
    UINT64_C(101715760),  // SASX
1868
0
    UINT64_C(4118802544), // SB
1869
0
    UINT64_C(46137344), // SBCri
1870
0
    UINT64_C(12582912), // SBCrr
1871
0
    UINT64_C(12582912), // SBCrsi
1872
0
    UINT64_C(12582928), // SBCrsr
1873
0
    UINT64_C(127926352),  // SBFX
1874
0
    UINT64_C(118550544),  // SDIV
1875
0
    UINT64_C(109055920),  // SEL
1876
0
    UINT64_C(4043374592), // SETEND
1877
0
    UINT64_C(4044357632), // SETPAN
1878
0
    UINT64_C(4060089408), // SHA1C
1879
0
    UINT64_C(4088988352), // SHA1H
1880
0
    UINT64_C(4062186560), // SHA1M
1881
0
    UINT64_C(4061137984), // SHA1P
1882
0
    UINT64_C(4063235136), // SHA1SU0
1883
0
    UINT64_C(4089054080), // SHA1SU1
1884
0
    UINT64_C(4076866624), // SHA256H
1885
0
    UINT64_C(4077915200), // SHA256H2
1886
0
    UINT64_C(4089054144), // SHA256SU0
1887
0
    UINT64_C(4078963776), // SHA256SU1
1888
0
    UINT64_C(103812880),  // SHADD16
1889
0
    UINT64_C(103813008),  // SHADD8
1890
0
    UINT64_C(103812912),  // SHASX
1891
0
    UINT64_C(103812944),  // SHSAX
1892
0
    UINT64_C(103812976),  // SHSUB16
1893
0
    UINT64_C(103813104),  // SHSUB8
1894
0
    UINT64_C(23068784), // SMC
1895
0
    UINT64_C(16777344), // SMLABB
1896
0
    UINT64_C(16777408), // SMLABT
1897
0
    UINT64_C(117440528),  // SMLAD
1898
0
    UINT64_C(117440560),  // SMLADX
1899
0
    UINT64_C(14680208), // SMLAL
1900
0
    UINT64_C(20971648), // SMLALBB
1901
0
    UINT64_C(20971712), // SMLALBT
1902
0
    UINT64_C(121634832),  // SMLALD
1903
0
    UINT64_C(121634864),  // SMLALDX
1904
0
    UINT64_C(20971680), // SMLALTB
1905
0
    UINT64_C(20971744), // SMLALTT
1906
0
    UINT64_C(16777376), // SMLATB
1907
0
    UINT64_C(16777440), // SMLATT
1908
0
    UINT64_C(18874496), // SMLAWB
1909
0
    UINT64_C(18874560), // SMLAWT
1910
0
    UINT64_C(117440592),  // SMLSD
1911
0
    UINT64_C(117440624),  // SMLSDX
1912
0
    UINT64_C(121634896),  // SMLSLD
1913
0
    UINT64_C(121634928),  // SMLSLDX
1914
0
    UINT64_C(122683408),  // SMMLA
1915
0
    UINT64_C(122683440),  // SMMLAR
1916
0
    UINT64_C(122683600),  // SMMLS
1917
0
    UINT64_C(122683632),  // SMMLSR
1918
0
    UINT64_C(122744848),  // SMMUL
1919
0
    UINT64_C(122744880),  // SMMULR
1920
0
    UINT64_C(117501968),  // SMUAD
1921
0
    UINT64_C(117502000),  // SMUADX
1922
0
    UINT64_C(23068800), // SMULBB
1923
0
    UINT64_C(23068864), // SMULBT
1924
0
    UINT64_C(12583056), // SMULL
1925
0
    UINT64_C(23068832), // SMULTB
1926
0
    UINT64_C(23068896), // SMULTT
1927
0
    UINT64_C(18874528), // SMULWB
1928
0
    UINT64_C(18874592), // SMULWT
1929
0
    UINT64_C(117502032),  // SMUSD
1930
0
    UINT64_C(117502064),  // SMUSDX
1931
0
    UINT64_C(4165797120), // SRSDA
1932
0
    UINT64_C(4167894272), // SRSDA_UPD
1933
0
    UINT64_C(4182574336), // SRSDB
1934
0
    UINT64_C(4184671488), // SRSDB_UPD
1935
0
    UINT64_C(4174185728), // SRSIA
1936
0
    UINT64_C(4176282880), // SRSIA_UPD
1937
0
    UINT64_C(4190962944), // SRSIB
1938
0
    UINT64_C(4193060096), // SRSIB_UPD
1939
0
    UINT64_C(111149072),  // SSAT
1940
0
    UINT64_C(111152944),  // SSAT16
1941
0
    UINT64_C(101715792),  // SSAX
1942
0
    UINT64_C(101715824),  // SSUB16
1943
0
    UINT64_C(101715952),  // SSUB8
1944
0
    UINT64_C(4248829952), // STC2L_OFFSET
1945
0
    UINT64_C(4240441344), // STC2L_OPTION
1946
0
    UINT64_C(4234149888), // STC2L_POST
1947
0
    UINT64_C(4250927104), // STC2L_PRE
1948
0
    UINT64_C(4244635648), // STC2_OFFSET
1949
0
    UINT64_C(4236247040), // STC2_OPTION
1950
0
    UINT64_C(4229955584), // STC2_POST
1951
0
    UINT64_C(4246732800), // STC2_PRE
1952
0
    UINT64_C(222298112),  // STCL_OFFSET
1953
0
    UINT64_C(213909504),  // STCL_OPTION
1954
0
    UINT64_C(207618048),  // STCL_POST
1955
0
    UINT64_C(224395264),  // STCL_PRE
1956
0
    UINT64_C(218103808),  // STC_OFFSET
1957
0
    UINT64_C(209715200),  // STC_OPTION
1958
0
    UINT64_C(203423744),  // STC_POST
1959
0
    UINT64_C(220200960),  // STC_PRE
1960
0
    UINT64_C(25230480), // STL
1961
0
    UINT64_C(29424784), // STLB
1962
0
    UINT64_C(25169552), // STLEX
1963
0
    UINT64_C(29363856), // STLEXB
1964
0
    UINT64_C(27266704), // STLEXD
1965
0
    UINT64_C(31461008), // STLEXH
1966
0
    UINT64_C(31521936), // STLH
1967
0
    UINT64_C(134217728),  // STMDA
1968
0
    UINT64_C(136314880),  // STMDA_UPD
1969
0
    UINT64_C(150994944),  // STMDB
1970
0
    UINT64_C(153092096),  // STMDB_UPD
1971
0
    UINT64_C(142606336),  // STMIA
1972
0
    UINT64_C(144703488),  // STMIA_UPD
1973
0
    UINT64_C(159383552),  // STMIB
1974
0
    UINT64_C(161480704),  // STMIB_UPD
1975
0
    UINT64_C(73400320), // STRBT_POST_IMM
1976
0
    UINT64_C(106954752),  // STRBT_POST_REG
1977
0
    UINT64_C(71303168), // STRB_POST_IMM
1978
0
    UINT64_C(104857600),  // STRB_POST_REG
1979
0
    UINT64_C(90177536), // STRB_PRE_IMM
1980
0
    UINT64_C(123731968),  // STRB_PRE_REG
1981
0
    UINT64_C(88080384), // STRBi12
1982
0
    UINT64_C(121634816),  // STRBrs
1983
0
    UINT64_C(16777456), // STRD
1984
0
    UINT64_C(240),  // STRD_POST
1985
0
    UINT64_C(18874608), // STRD_PRE
1986
0
    UINT64_C(25169808), // STREX
1987
0
    UINT64_C(29364112), // STREXB
1988
0
    UINT64_C(27266960), // STREXD
1989
0
    UINT64_C(31461264), // STREXH
1990
0
    UINT64_C(16777392), // STRH
1991
0
    UINT64_C(6291632),  // STRHTi
1992
0
    UINT64_C(2097328),  // STRHTr
1993
0
    UINT64_C(176),  // STRH_POST
1994
0
    UINT64_C(18874544), // STRH_PRE
1995
0
    UINT64_C(69206016), // STRT_POST_IMM
1996
0
    UINT64_C(102760448),  // STRT_POST_REG
1997
0
    UINT64_C(67108864), // STR_POST_IMM
1998
0
    UINT64_C(100663296),  // STR_POST_REG
1999
0
    UINT64_C(85983232), // STR_PRE_IMM
2000
0
    UINT64_C(119537664),  // STR_PRE_REG
2001
0
    UINT64_C(83886080), // STRi12
2002
0
    UINT64_C(117440512),  // STRrs
2003
0
    UINT64_C(37748736), // SUBri
2004
0
    UINT64_C(4194304),  // SUBrr
2005
0
    UINT64_C(4194304),  // SUBrsi
2006
0
    UINT64_C(4194320),  // SUBrsr
2007
0
    UINT64_C(251658240),  // SVC
2008
0
    UINT64_C(16777360), // SWP
2009
0
    UINT64_C(20971664), // SWPB
2010
0
    UINT64_C(111149168),  // SXTAB
2011
0
    UINT64_C(109052016),  // SXTAB16
2012
0
    UINT64_C(112197744),  // SXTAH
2013
0
    UINT64_C(112132208),  // SXTB
2014
0
    UINT64_C(110035056),  // SXTB16
2015
0
    UINT64_C(113180784),  // SXTH
2016
0
    UINT64_C(53477376), // TEQri
2017
0
    UINT64_C(19922944), // TEQrr
2018
0
    UINT64_C(19922944), // TEQrsi
2019
0
    UINT64_C(19922960), // TEQrsr
2020
0
    UINT64_C(3892305662), // TRAP
2021
0
    UINT64_C(3892240112), // TRAPNaCl
2022
0
    UINT64_C(3810586642), // TSB
2023
0
    UINT64_C(51380224), // TSTri
2024
0
    UINT64_C(17825792), // TSTrr
2025
0
    UINT64_C(17825792), // TSTrsi
2026
0
    UINT64_C(17825808), // TSTrsr
2027
0
    UINT64_C(105910032),  // UADD16
2028
0
    UINT64_C(105910160),  // UADD8
2029
0
    UINT64_C(105910064),  // UASX
2030
0
    UINT64_C(132120656),  // UBFX
2031
0
    UINT64_C(3891265776), // UDF
2032
0
    UINT64_C(120647696),  // UDIV
2033
0
    UINT64_C(108007184),  // UHADD16
2034
0
    UINT64_C(108007312),  // UHADD8
2035
0
    UINT64_C(108007216),  // UHASX
2036
0
    UINT64_C(108007248),  // UHSAX
2037
0
    UINT64_C(108007280),  // UHSUB16
2038
0
    UINT64_C(108007408),  // UHSUB8
2039
0
    UINT64_C(4194448),  // UMAAL
2040
0
    UINT64_C(10485904), // UMLAL
2041
0
    UINT64_C(8388752),  // UMULL
2042
0
    UINT64_C(106958608),  // UQADD16
2043
0
    UINT64_C(106958736),  // UQADD8
2044
0
    UINT64_C(106958640),  // UQASX
2045
0
    UINT64_C(106958672),  // UQSAX
2046
0
    UINT64_C(106958704),  // UQSUB16
2047
0
    UINT64_C(106958832),  // UQSUB8
2048
0
    UINT64_C(125890576),  // USAD8
2049
0
    UINT64_C(125829136),  // USADA8
2050
0
    UINT64_C(115343376),  // USAT
2051
0
    UINT64_C(115347248),  // USAT16
2052
0
    UINT64_C(105910096),  // USAX
2053
0
    UINT64_C(105910128),  // USUB16
2054
0
    UINT64_C(105910256),  // USUB8
2055
0
    UINT64_C(115343472),  // UXTAB
2056
0
    UINT64_C(113246320),  // UXTAB16
2057
0
    UINT64_C(116392048),  // UXTAH
2058
0
    UINT64_C(116326512),  // UXTB
2059
0
    UINT64_C(114229360),  // UXTB16
2060
0
    UINT64_C(117375088),  // UXTH
2061
0
    UINT64_C(4070573312), // VABALsv2i64
2062
0
    UINT64_C(4069524736), // VABALsv4i32
2063
0
    UINT64_C(4068476160), // VABALsv8i16
2064
0
    UINT64_C(4087350528), // VABALuv2i64
2065
0
    UINT64_C(4086301952), // VABALuv4i32
2066
0
    UINT64_C(4085253376), // VABALuv8i16
2067
0
    UINT64_C(4060088144), // VABAsv16i8
2068
0
    UINT64_C(4062185232), // VABAsv2i32
2069
0
    UINT64_C(4061136656), // VABAsv4i16
2070
0
    UINT64_C(4062185296), // VABAsv4i32
2071
0
    UINT64_C(4061136720), // VABAsv8i16
2072
0
    UINT64_C(4060088080), // VABAsv8i8
2073
0
    UINT64_C(4076865360), // VABAuv16i8
2074
0
    UINT64_C(4078962448), // VABAuv2i32
2075
0
    UINT64_C(4077913872), // VABAuv4i16
2076
0
    UINT64_C(4078962512), // VABAuv4i32
2077
0
    UINT64_C(4077913936), // VABAuv8i16
2078
0
    UINT64_C(4076865296), // VABAuv8i8
2079
0
    UINT64_C(4070573824), // VABDLsv2i64
2080
0
    UINT64_C(4069525248), // VABDLsv4i32
2081
0
    UINT64_C(4068476672), // VABDLsv8i16
2082
0
    UINT64_C(4087351040), // VABDLuv2i64
2083
0
    UINT64_C(4086302464), // VABDLuv4i32
2084
0
    UINT64_C(4085253888), // VABDLuv8i16
2085
0
    UINT64_C(4078963968), // VABDfd
2086
0
    UINT64_C(4078964032), // VABDfq
2087
0
    UINT64_C(4080012544), // VABDhd
2088
0
    UINT64_C(4080012608), // VABDhq
2089
0
    UINT64_C(4060088128), // VABDsv16i8
2090
0
    UINT64_C(4062185216), // VABDsv2i32
2091
0
    UINT64_C(4061136640), // VABDsv4i16
2092
0
    UINT64_C(4062185280), // VABDsv4i32
2093
0
    UINT64_C(4061136704), // VABDsv8i16
2094
0
    UINT64_C(4060088064), // VABDsv8i8
2095
0
    UINT64_C(4076865344), // VABDuv16i8
2096
0
    UINT64_C(4078962432), // VABDuv2i32
2097
0
    UINT64_C(4077913856), // VABDuv4i16
2098
0
    UINT64_C(4078962496), // VABDuv4i32
2099
0
    UINT64_C(4077913920), // VABDuv8i16
2100
0
    UINT64_C(4076865280), // VABDuv8i8
2101
0
    UINT64_C(246418368),  // VABSD
2102
0
    UINT64_C(246417856),  // VABSH
2103
0
    UINT64_C(246418112),  // VABSS
2104
0
    UINT64_C(4088989440), // VABSfd
2105
0
    UINT64_C(4088989504), // VABSfq
2106
0
    UINT64_C(4088727296), // VABShd
2107
0
    UINT64_C(4088727360), // VABShq
2108
0
    UINT64_C(4088464192), // VABSv16i8
2109
0
    UINT64_C(4088988416), // VABSv2i32
2110
0
    UINT64_C(4088726272), // VABSv4i16
2111
0
    UINT64_C(4088988480), // VABSv4i32
2112
0
    UINT64_C(4088726336), // VABSv8i16
2113
0
    UINT64_C(4088464128), // VABSv8i8
2114
0
    UINT64_C(4076867088), // VACGEfd
2115
0
    UINT64_C(4076867152), // VACGEfq
2116
0
    UINT64_C(4077915664), // VACGEhd
2117
0
    UINT64_C(4077915728), // VACGEhq
2118
0
    UINT64_C(4078964240), // VACGTfd
2119
0
    UINT64_C(4078964304), // VACGTfq
2120
0
    UINT64_C(4080012816), // VACGThd
2121
0
    UINT64_C(4080012880), // VACGThq
2122
0
    UINT64_C(238029568),  // VADDD
2123
0
    UINT64_C(238029056),  // VADDH
2124
0
    UINT64_C(4070573056), // VADDHNv2i32
2125
0
    UINT64_C(4069524480), // VADDHNv4i16
2126
0
    UINT64_C(4068475904), // VADDHNv8i8
2127
0
    UINT64_C(4070572032), // VADDLsv2i64
2128
0
    UINT64_C(4069523456), // VADDLsv4i32
2129
0
    UINT64_C(4068474880), // VADDLsv8i16
2130
0
    UINT64_C(4087349248), // VADDLuv2i64
2131
0
    UINT64_C(4086300672), // VADDLuv4i32
2132
0
    UINT64_C(4085252096), // VADDLuv8i16
2133
0
    UINT64_C(238029312),  // VADDS
2134
0
    UINT64_C(4070572288), // VADDWsv2i64
2135
0
    UINT64_C(4069523712), // VADDWsv4i32
2136
0
    UINT64_C(4068475136), // VADDWsv8i16
2137
0
    UINT64_C(4087349504), // VADDWuv2i64
2138
0
    UINT64_C(4086300928), // VADDWuv4i32
2139
0
    UINT64_C(4085252352), // VADDWuv8i16
2140
0
    UINT64_C(4060089600), // VADDfd
2141
0
    UINT64_C(4060089664), // VADDfq
2142
0
    UINT64_C(4061138176), // VADDhd
2143
0
    UINT64_C(4061138240), // VADDhq
2144
0
    UINT64_C(4060088384), // VADDv16i8
2145
0
    UINT64_C(4063234048), // VADDv1i64
2146
0
    UINT64_C(4062185472), // VADDv2i32
2147
0
    UINT64_C(4063234112), // VADDv2i64
2148
0
    UINT64_C(4061136896), // VADDv4i16
2149
0
    UINT64_C(4062185536), // VADDv4i32
2150
0
    UINT64_C(4061136960), // VADDv8i16
2151
0
    UINT64_C(4060088320), // VADDv8i8
2152
0
    UINT64_C(4060086544), // VANDd
2153
0
    UINT64_C(4060086608), // VANDq
2154
0
    UINT64_C(4231006224), // VBF16MALBQ
2155
0
    UINT64_C(4264560656), // VBF16MALBQI
2156
0
    UINT64_C(4231006288), // VBF16MALTQ
2157
0
    UINT64_C(4264560720), // VBF16MALTQI
2158
0
    UINT64_C(4061135120), // VBICd
2159
0
    UINT64_C(4068475184), // VBICiv2i32
2160
0
    UINT64_C(4068477232), // VBICiv4i16
2161
0
    UINT64_C(4068475248), // VBICiv4i32
2162
0
    UINT64_C(4068477296), // VBICiv8i16
2163
0
    UINT64_C(4061135184), // VBICq
2164
0
    UINT64_C(4080009488), // VBIFd
2165
0
    UINT64_C(4080009552), // VBIFq
2166
0
    UINT64_C(4078960912), // VBITd
2167
0
    UINT64_C(4078960976), // VBITq
2168
0
    UINT64_C(4077912336), // VBSLd
2169
0
    UINT64_C(4077912400), // VBSLq
2170
0
    UINT64_C(0),  // VBSPd
2171
0
    UINT64_C(0),  // VBSPq
2172
0
    UINT64_C(4237297664), // VCADDv2f32
2173
0
    UINT64_C(4236249088), // VCADDv4f16
2174
0
    UINT64_C(4237297728), // VCADDv4f32
2175
0
    UINT64_C(4236249152), // VCADDv8f16
2176
0
    UINT64_C(4060089856), // VCEQfd
2177
0
    UINT64_C(4060089920), // VCEQfq
2178
0
    UINT64_C(4061138432), // VCEQhd
2179
0
    UINT64_C(4061138496), // VCEQhq
2180
0
    UINT64_C(4076865616), // VCEQv16i8
2181
0
    UINT64_C(4078962704), // VCEQv2i32
2182
0
    UINT64_C(4077914128), // VCEQv4i16
2183
0
    UINT64_C(4078962768), // VCEQv4i32
2184
0
    UINT64_C(4077914192), // VCEQv8i16
2185
0
    UINT64_C(4076865552), // VCEQv8i8
2186
0
    UINT64_C(4088463680), // VCEQzv16i8
2187
0
    UINT64_C(4088988928), // VCEQzv2f32
2188
0
    UINT64_C(4088987904), // VCEQzv2i32
2189
0
    UINT64_C(4088726784), // VCEQzv4f16
2190
0
    UINT64_C(4088988992), // VCEQzv4f32
2191
0
    UINT64_C(4088725760), // VCEQzv4i16
2192
0
    UINT64_C(4088987968), // VCEQzv4i32
2193
0
    UINT64_C(4088726848), // VCEQzv8f16
2194
0
    UINT64_C(4088725824), // VCEQzv8i16
2195
0
    UINT64_C(4088463616), // VCEQzv8i8
2196
0
    UINT64_C(4076867072), // VCGEfd
2197
0
    UINT64_C(4076867136), // VCGEfq
2198
0
    UINT64_C(4077915648), // VCGEhd
2199
0
    UINT64_C(4077915712), // VCGEhq
2200
0
    UINT64_C(4060087120), // VCGEsv16i8
2201
0
    UINT64_C(4062184208), // VCGEsv2i32
2202
0
    UINT64_C(4061135632), // VCGEsv4i16
2203
0
    UINT64_C(4062184272), // VCGEsv4i32
2204
0
    UINT64_C(4061135696), // VCGEsv8i16
2205
0
    UINT64_C(4060087056), // VCGEsv8i8
2206
0
    UINT64_C(4076864336), // VCGEuv16i8
2207
0
    UINT64_C(4078961424), // VCGEuv2i32
2208
0
    UINT64_C(4077912848), // VCGEuv4i16
2209
0
    UINT64_C(4078961488), // VCGEuv4i32
2210
0
    UINT64_C(4077912912), // VCGEuv8i16
2211
0
    UINT64_C(4076864272), // VCGEuv8i8
2212
0
    UINT64_C(4088463552), // VCGEzv16i8
2213
0
    UINT64_C(4088988800), // VCGEzv2f32
2214
0
    UINT64_C(4088987776), // VCGEzv2i32
2215
0
    UINT64_C(4088726656), // VCGEzv4f16
2216
0
    UINT64_C(4088988864), // VCGEzv4f32
2217
0
    UINT64_C(4088725632), // VCGEzv4i16
2218
0
    UINT64_C(4088987840), // VCGEzv4i32
2219
0
    UINT64_C(4088726720), // VCGEzv8f16
2220
0
    UINT64_C(4088725696), // VCGEzv8i16
2221
0
    UINT64_C(4088463488), // VCGEzv8i8
2222
0
    UINT64_C(4078964224), // VCGTfd
2223
0
    UINT64_C(4078964288), // VCGTfq
2224
0
    UINT64_C(4080012800), // VCGThd
2225
0
    UINT64_C(4080012864), // VCGThq
2226
0
    UINT64_C(4060087104), // VCGTsv16i8
2227
0
    UINT64_C(4062184192), // VCGTsv2i32
2228
0
    UINT64_C(4061135616), // VCGTsv4i16
2229
0
    UINT64_C(4062184256), // VCGTsv4i32
2230
0
    UINT64_C(4061135680), // VCGTsv8i16
2231
0
    UINT64_C(4060087040), // VCGTsv8i8
2232
0
    UINT64_C(4076864320), // VCGTuv16i8
2233
0
    UINT64_C(4078961408), // VCGTuv2i32
2234
0
    UINT64_C(4077912832), // VCGTuv4i16
2235
0
    UINT64_C(4078961472), // VCGTuv4i32
2236
0
    UINT64_C(4077912896), // VCGTuv8i16
2237
0
    UINT64_C(4076864256), // VCGTuv8i8
2238
0
    UINT64_C(4088463424), // VCGTzv16i8
2239
0
    UINT64_C(4088988672), // VCGTzv2f32
2240
0
    UINT64_C(4088987648), // VCGTzv2i32
2241
0
    UINT64_C(4088726528), // VCGTzv4f16
2242
0
    UINT64_C(4088988736), // VCGTzv4f32
2243
0
    UINT64_C(4088725504), // VCGTzv4i16
2244
0
    UINT64_C(4088987712), // VCGTzv4i32
2245
0
    UINT64_C(4088726592), // VCGTzv8f16
2246
0
    UINT64_C(4088725568), // VCGTzv8i16
2247
0
    UINT64_C(4088463360), // VCGTzv8i8
2248
0
    UINT64_C(4088463808), // VCLEzv16i8
2249
0
    UINT64_C(4088989056), // VCLEzv2f32
2250
0
    UINT64_C(4088988032), // VCLEzv2i32
2251
0
    UINT64_C(4088726912), // VCLEzv4f16
2252
0
    UINT64_C(4088989120), // VCLEzv4f32
2253
0
    UINT64_C(4088725888), // VCLEzv4i16
2254
0
    UINT64_C(4088988096), // VCLEzv4i32
2255
0
    UINT64_C(4088726976), // VCLEzv8f16
2256
0
    UINT64_C(4088725952), // VCLEzv8i16
2257
0
    UINT64_C(4088463744), // VCLEzv8i8
2258
0
    UINT64_C(4088398912), // VCLSv16i8
2259
0
    UINT64_C(4088923136), // VCLSv2i32
2260
0
    UINT64_C(4088660992), // VCLSv4i16
2261
0
    UINT64_C(4088923200), // VCLSv4i32
2262
0
    UINT64_C(4088661056), // VCLSv8i16
2263
0
    UINT64_C(4088398848), // VCLSv8i8
2264
0
    UINT64_C(4088463936), // VCLTzv16i8
2265
0
    UINT64_C(4088989184), // VCLTzv2f32
2266
0
    UINT64_C(4088988160), // VCLTzv2i32
2267
0
    UINT64_C(4088727040), // VCLTzv4f16
2268
0
    UINT64_C(4088989248), // VCLTzv4f32
2269
0
    UINT64_C(4088726016), // VCLTzv4i16
2270
0
    UINT64_C(4088988224), // VCLTzv4i32
2271
0
    UINT64_C(4088727104), // VCLTzv8f16
2272
0
    UINT64_C(4088726080), // VCLTzv8i16
2273
0
    UINT64_C(4088463872), // VCLTzv8i8
2274
0
    UINT64_C(4088399040), // VCLZv16i8
2275
0
    UINT64_C(4088923264), // VCLZv2i32
2276
0
    UINT64_C(4088661120), // VCLZv4i16
2277
0
    UINT64_C(4088923328), // VCLZv4i32
2278
0
    UINT64_C(4088661184), // VCLZv8i16
2279
0
    UINT64_C(4088398976), // VCLZv8i8
2280
0
    UINT64_C(4231006208), // VCMLAv2f32
2281
0
    UINT64_C(4269803520), // VCMLAv2f32_indexed
2282
0
    UINT64_C(4229957632), // VCMLAv4f16
2283
0
    UINT64_C(4261414912), // VCMLAv4f16_indexed
2284
0
    UINT64_C(4231006272), // VCMLAv4f32
2285
0
    UINT64_C(4269803584), // VCMLAv4f32_indexed
2286
0
    UINT64_C(4229957696), // VCMLAv8f16
2287
0
    UINT64_C(4261414976), // VCMLAv8f16_indexed
2288
0
    UINT64_C(246680384),  // VCMPD
2289
0
    UINT64_C(246680512),  // VCMPED
2290
0
    UINT64_C(246680000),  // VCMPEH
2291
0
    UINT64_C(246680256),  // VCMPES
2292
0
    UINT64_C(246746048),  // VCMPEZD
2293
0
    UINT64_C(246745536),  // VCMPEZH
2294
0
    UINT64_C(246745792),  // VCMPEZS
2295
0
    UINT64_C(246679872),  // VCMPH
2296
0
    UINT64_C(246680128),  // VCMPS
2297
0
    UINT64_C(246745920),  // VCMPZD
2298
0
    UINT64_C(246745408),  // VCMPZH
2299
0
    UINT64_C(246745664),  // VCMPZS
2300
0
    UINT64_C(4088399104), // VCNTd
2301
0
    UINT64_C(4088399168), // VCNTq
2302
0
    UINT64_C(4089118720), // VCVTANSDf
2303
0
    UINT64_C(4088856576), // VCVTANSDh
2304
0
    UINT64_C(4089118784), // VCVTANSQf
2305
0
    UINT64_C(4088856640), // VCVTANSQh
2306
0
    UINT64_C(4089118848), // VCVTANUDf
2307
0
    UINT64_C(4088856704), // VCVTANUDh
2308
0
    UINT64_C(4089118912), // VCVTANUQf
2309
0
    UINT64_C(4088856768), // VCVTANUQh
2310
0
    UINT64_C(4273736640), // VCVTASD
2311
0
    UINT64_C(4273736128), // VCVTASH
2312
0
    UINT64_C(4273736384), // VCVTASS
2313
0
    UINT64_C(4273736512), // VCVTAUD
2314
0
    UINT64_C(4273736000), // VCVTAUH
2315
0
    UINT64_C(4273736256), // VCVTAUS
2316
0
    UINT64_C(246614848),  // VCVTBDH
2317
0
    UINT64_C(246549312),  // VCVTBHD
2318
0
    UINT64_C(246549056),  // VCVTBHS
2319
0
    UINT64_C(246614592),  // VCVTBSH
2320
0
    UINT64_C(246876864),  // VCVTDS
2321
0
    UINT64_C(4089119488), // VCVTMNSDf
2322
0
    UINT64_C(4088857344), // VCVTMNSDh
2323
0
    UINT64_C(4089119552), // VCVTMNSQf
2324
0
    UINT64_C(4088857408), // VCVTMNSQh
2325
0
    UINT64_C(4089119616), // VCVTMNUDf
2326
0
    UINT64_C(4088857472), // VCVTMNUDh
2327
0
    UINT64_C(4089119680), // VCVTMNUQf
2328
0
    UINT64_C(4088857536), // VCVTMNUQh
2329
0
    UINT64_C(4273933248), // VCVTMSD
2330
0
    UINT64_C(4273932736), // VCVTMSH
2331
0
    UINT64_C(4273932992), // VCVTMSS
2332
0
    UINT64_C(4273933120), // VCVTMUD
2333
0
    UINT64_C(4273932608), // VCVTMUH
2334
0
    UINT64_C(4273932864), // VCVTMUS
2335
0
    UINT64_C(4089118976), // VCVTNNSDf
2336
0
    UINT64_C(4088856832), // VCVTNNSDh
2337
0
    UINT64_C(4089119040), // VCVTNNSQf
2338
0
    UINT64_C(4088856896), // VCVTNNSQh
2339
0
    UINT64_C(4089119104), // VCVTNNUDf
2340
0
    UINT64_C(4088856960), // VCVTNNUDh
2341
0
    UINT64_C(4089119168), // VCVTNNUQf
2342
0
    UINT64_C(4088857024), // VCVTNNUQh
2343
0
    UINT64_C(4273802176), // VCVTNSD
2344
0
    UINT64_C(4273801664), // VCVTNSH
2345
0
    UINT64_C(4273801920), // VCVTNSS
2346
0
    UINT64_C(4273802048), // VCVTNUD
2347
0
    UINT64_C(4273801536), // VCVTNUH
2348
0
    UINT64_C(4273801792), // VCVTNUS
2349
0
    UINT64_C(4089119232), // VCVTPNSDf
2350
0
    UINT64_C(4088857088), // VCVTPNSDh
2351
0
    UINT64_C(4089119296), // VCVTPNSQf
2352
0
    UINT64_C(4088857152), // VCVTPNSQh
2353
0
    UINT64_C(4089119360), // VCVTPNUDf
2354
0
    UINT64_C(4088857216), // VCVTPNUDh
2355
0
    UINT64_C(4089119424), // VCVTPNUQf
2356
0
    UINT64_C(4088857280), // VCVTPNUQh
2357
0
    UINT64_C(4273867712), // VCVTPSD
2358
0
    UINT64_C(4273867200), // VCVTPSH
2359
0
    UINT64_C(4273867456), // VCVTPSS
2360
0
    UINT64_C(4273867584), // VCVTPUD
2361
0
    UINT64_C(4273867072), // VCVTPUH
2362
0
    UINT64_C(4273867328), // VCVTPUS
2363
0
    UINT64_C(246877120),  // VCVTSD
2364
0
    UINT64_C(246614976),  // VCVTTDH
2365
0
    UINT64_C(246549440),  // VCVTTHD
2366
0
    UINT64_C(246549184),  // VCVTTHS
2367
0
    UINT64_C(246614720),  // VCVTTSH
2368
0
    UINT64_C(4088792576), // VCVTf2h
2369
0
    UINT64_C(4089120512), // VCVTf2sd
2370
0
    UINT64_C(4089120576), // VCVTf2sq
2371
0
    UINT64_C(4089120640), // VCVTf2ud
2372
0
    UINT64_C(4089120704), // VCVTf2uq
2373
0
    UINT64_C(4068478736), // VCVTf2xsd
2374
0
    UINT64_C(4068478800), // VCVTf2xsq
2375
0
    UINT64_C(4085255952), // VCVTf2xud
2376
0
    UINT64_C(4085256016), // VCVTf2xuq
2377
0
    UINT64_C(4088792832), // VCVTh2f
2378
0
    UINT64_C(4088858368), // VCVTh2sd
2379
0
    UINT64_C(4088858432), // VCVTh2sq
2380
0
    UINT64_C(4088858496), // VCVTh2ud
2381
0
    UINT64_C(4088858560), // VCVTh2uq
2382
0
    UINT64_C(4068478224), // VCVTh2xsd
2383
0
    UINT64_C(4068478288), // VCVTh2xsq
2384
0
    UINT64_C(4085255440), // VCVTh2xud
2385
0
    UINT64_C(4085255504), // VCVTh2xuq
2386
0
    UINT64_C(4089120256), // VCVTs2fd
2387
0
    UINT64_C(4089120320), // VCVTs2fq
2388
0
    UINT64_C(4088858112), // VCVTs2hd
2389
0
    UINT64_C(4088858176), // VCVTs2hq
2390
0
    UINT64_C(4089120384), // VCVTu2fd
2391
0
    UINT64_C(4089120448), // VCVTu2fq
2392
0
    UINT64_C(4088858240), // VCVTu2hd
2393
0
    UINT64_C(4088858304), // VCVTu2hq
2394
0
    UINT64_C(4068478480), // VCVTxs2fd
2395
0
    UINT64_C(4068478544), // VCVTxs2fq
2396
0
    UINT64_C(4068477968), // VCVTxs2hd
2397
0
    UINT64_C(4068478032), // VCVTxs2hq
2398
0
    UINT64_C(4085255696), // VCVTxu2fd
2399
0
    UINT64_C(4085255760), // VCVTxu2fq
2400
0
    UINT64_C(4085255184), // VCVTxu2hd
2401
0
    UINT64_C(4085255248), // VCVTxu2hq
2402
0
    UINT64_C(243272448),  // VDIVD
2403
0
    UINT64_C(243271936),  // VDIVH
2404
0
    UINT64_C(243272192),  // VDIVS
2405
0
    UINT64_C(243272496),  // VDUP16d
2406
0
    UINT64_C(245369648),  // VDUP16q
2407
0
    UINT64_C(243272464),  // VDUP32d
2408
0
    UINT64_C(245369616),  // VDUP32q
2409
0
    UINT64_C(247466768),  // VDUP8d
2410
0
    UINT64_C(249563920),  // VDUP8q
2411
0
    UINT64_C(4088531968), // VDUPLN16d
2412
0
    UINT64_C(4088532032), // VDUPLN16q
2413
0
    UINT64_C(4088663040), // VDUPLN32d
2414
0
    UINT64_C(4088663104), // VDUPLN32q
2415
0
    UINT64_C(4088466432), // VDUPLN8d
2416
0
    UINT64_C(4088466496), // VDUPLN8q
2417
0
    UINT64_C(4076863760), // VEORd
2418
0
    UINT64_C(4076863824), // VEORq
2419
0
    UINT64_C(4071620608), // VEXTd16
2420
0
    UINT64_C(4071620608), // VEXTd32
2421
0
    UINT64_C(4071620608), // VEXTd8
2422
0
    UINT64_C(4071620672), // VEXTq16
2423
0
    UINT64_C(4071620672), // VEXTq32
2424
0
    UINT64_C(4071620672), // VEXTq64
2425
0
    UINT64_C(4071620672), // VEXTq8
2426
0
    UINT64_C(245369600),  // VFMAD
2427
0
    UINT64_C(245369088),  // VFMAH
2428
0
    UINT64_C(4229957648), // VFMALD
2429
0
    UINT64_C(4261414928), // VFMALDI
2430
0
    UINT64_C(4229957712), // VFMALQ
2431
0
    UINT64_C(4261414992), // VFMALQI
2432
0
    UINT64_C(245369344),  // VFMAS
2433
0
    UINT64_C(4060089360), // VFMAfd
2434
0
    UINT64_C(4060089424), // VFMAfq
2435
0
    UINT64_C(4061137936), // VFMAhd
2436
0
    UINT64_C(4061138000), // VFMAhq
2437
0
    UINT64_C(245369664),  // VFMSD
2438
0
    UINT64_C(245369152),  // VFMSH
2439
0
    UINT64_C(4238346256), // VFMSLD
2440
0
    UINT64_C(4262463504), // VFMSLDI
2441
0
    UINT64_C(4238346320), // VFMSLQ
2442
0
    UINT64_C(4262463568), // VFMSLQI
2443
0
    UINT64_C(245369408),  // VFMSS
2444
0
    UINT64_C(4062186512), // VFMSfd
2445
0
    UINT64_C(4062186576), // VFMSfq
2446
0
    UINT64_C(4063235088), // VFMShd
2447
0
    UINT64_C(4063235152), // VFMShq
2448
0
    UINT64_C(244321088),  // VFNMAD
2449
0
    UINT64_C(244320576),  // VFNMAH
2450
0
    UINT64_C(244320832),  // VFNMAS
2451
0
    UINT64_C(244321024),  // VFNMSD
2452
0
    UINT64_C(244320512),  // VFNMSH
2453
0
    UINT64_C(244320768),  // VFNMSS
2454
0
    UINT64_C(4269804288), // VFP_VMAXNMD
2455
0
    UINT64_C(4269803776), // VFP_VMAXNMH
2456
0
    UINT64_C(4269804032), // VFP_VMAXNMS
2457
0
    UINT64_C(4269804352), // VFP_VMINNMD
2458
0
    UINT64_C(4269803840), // VFP_VMINNMH
2459
0
    UINT64_C(4269804096), // VFP_VMINNMS
2460
0
    UINT64_C(235932432),  // VGETLNi32
2461
0
    UINT64_C(235932464),  // VGETLNs16
2462
0
    UINT64_C(240126736),  // VGETLNs8
2463
0
    UINT64_C(244321072),  // VGETLNu16
2464
0
    UINT64_C(248515344),  // VGETLNu8
2465
0
    UINT64_C(4060086336), // VHADDsv16i8
2466
0
    UINT64_C(4062183424), // VHADDsv2i32
2467
0
    UINT64_C(4061134848), // VHADDsv4i16
2468
0
    UINT64_C(4062183488), // VHADDsv4i32
2469
0
    UINT64_C(4061134912), // VHADDsv8i16
2470
0
    UINT64_C(4060086272), // VHADDsv8i8
2471
0
    UINT64_C(4076863552), // VHADDuv16i8
2472
0
    UINT64_C(4078960640), // VHADDuv2i32
2473
0
    UINT64_C(4077912064), // VHADDuv4i16
2474
0
    UINT64_C(4078960704), // VHADDuv4i32
2475
0
    UINT64_C(4077912128), // VHADDuv8i16
2476
0
    UINT64_C(4076863488), // VHADDuv8i8
2477
0
    UINT64_C(4060086848), // VHSUBsv16i8
2478
0
    UINT64_C(4062183936), // VHSUBsv2i32
2479
0
    UINT64_C(4061135360), // VHSUBsv4i16
2480
0
    UINT64_C(4062184000), // VHSUBsv4i32
2481
0
    UINT64_C(4061135424), // VHSUBsv8i16
2482
0
    UINT64_C(4060086784), // VHSUBsv8i8
2483
0
    UINT64_C(4076864064), // VHSUBuv16i8
2484
0
    UINT64_C(4078961152), // VHSUBuv2i32
2485
0
    UINT64_C(4077912576), // VHSUBuv4i16
2486
0
    UINT64_C(4078961216), // VHSUBuv4i32
2487
0
    UINT64_C(4077912640), // VHSUBuv8i16
2488
0
    UINT64_C(4076864000), // VHSUBuv8i8
2489
0
    UINT64_C(4272949952), // VINSH
2490
0
    UINT64_C(247008192),  // VJCVT
2491
0
    UINT64_C(4104129615), // VLD1DUPd16
2492
0
    UINT64_C(4104129613), // VLD1DUPd16wb_fixed
2493
0
    UINT64_C(4104129600), // VLD1DUPd16wb_register
2494
0
    UINT64_C(4104129679), // VLD1DUPd32
2495
0
    UINT64_C(4104129677), // VLD1DUPd32wb_fixed
2496
0
    UINT64_C(4104129664), // VLD1DUPd32wb_register
2497
0
    UINT64_C(4104129551), // VLD1DUPd8
2498
0
    UINT64_C(4104129549), // VLD1DUPd8wb_fixed
2499
0
    UINT64_C(4104129536), // VLD1DUPd8wb_register
2500
0
    UINT64_C(4104129647), // VLD1DUPq16
2501
0
    UINT64_C(4104129645), // VLD1DUPq16wb_fixed
2502
0
    UINT64_C(4104129632), // VLD1DUPq16wb_register
2503
0
    UINT64_C(4104129711), // VLD1DUPq32
2504
0
    UINT64_C(4104129709), // VLD1DUPq32wb_fixed
2505
0
    UINT64_C(4104129696), // VLD1DUPq32wb_register
2506
0
    UINT64_C(4104129583), // VLD1DUPq8
2507
0
    UINT64_C(4104129581), // VLD1DUPq8wb_fixed
2508
0
    UINT64_C(4104129568), // VLD1DUPq8wb_register
2509
0
    UINT64_C(4104127503), // VLD1LNd16
2510
0
    UINT64_C(4104127488), // VLD1LNd16_UPD
2511
0
    UINT64_C(4104128527), // VLD1LNd32
2512
0
    UINT64_C(4104128512), // VLD1LNd32_UPD
2513
0
    UINT64_C(4104126479), // VLD1LNd8
2514
0
    UINT64_C(4104126464), // VLD1LNd8_UPD
2515
0
    UINT64_C(0),  // VLD1LNq16Pseudo
2516
0
    UINT64_C(0),  // VLD1LNq16Pseudo_UPD
2517
0
    UINT64_C(0),  // VLD1LNq32Pseudo
2518
0
    UINT64_C(0),  // VLD1LNq32Pseudo_UPD
2519
0
    UINT64_C(0),  // VLD1LNq8Pseudo
2520
0
    UINT64_C(0),  // VLD1LNq8Pseudo_UPD
2521
0
    UINT64_C(4095739727), // VLD1d16
2522
0
    UINT64_C(4095738447), // VLD1d16Q
2523
0
    UINT64_C(0),  // VLD1d16QPseudo
2524
0
    UINT64_C(0),  // VLD1d16QPseudoWB_fixed
2525
0
    UINT64_C(0),  // VLD1d16QPseudoWB_register
2526
0
    UINT64_C(4095738445), // VLD1d16Qwb_fixed
2527
0
    UINT64_C(4095738432), // VLD1d16Qwb_register
2528
0
    UINT64_C(4095739471), // VLD1d16T
2529
0
    UINT64_C(0),  // VLD1d16TPseudo
2530
0
    UINT64_C(0),  // VLD1d16TPseudoWB_fixed
2531
0
    UINT64_C(0),  // VLD1d16TPseudoWB_register
2532
0
    UINT64_C(4095739469), // VLD1d16Twb_fixed
2533
0
    UINT64_C(4095739456), // VLD1d16Twb_register
2534
0
    UINT64_C(4095739725), // VLD1d16wb_fixed
2535
0
    UINT64_C(4095739712), // VLD1d16wb_register
2536
0
    UINT64_C(4095739791), // VLD1d32
2537
0
    UINT64_C(4095738511), // VLD1d32Q
2538
0
    UINT64_C(0),  // VLD1d32QPseudo
2539
0
    UINT64_C(0),  // VLD1d32QPseudoWB_fixed
2540
0
    UINT64_C(0),  // VLD1d32QPseudoWB_register
2541
0
    UINT64_C(4095738509), // VLD1d32Qwb_fixed
2542
0
    UINT64_C(4095738496), // VLD1d32Qwb_register
2543
0
    UINT64_C(4095739535), // VLD1d32T
2544
0
    UINT64_C(0),  // VLD1d32TPseudo
2545
0
    UINT64_C(0),  // VLD1d32TPseudoWB_fixed
2546
0
    UINT64_C(0),  // VLD1d32TPseudoWB_register
2547
0
    UINT64_C(4095739533), // VLD1d32Twb_fixed
2548
0
    UINT64_C(4095739520), // VLD1d32Twb_register
2549
0
    UINT64_C(4095739789), // VLD1d32wb_fixed
2550
0
    UINT64_C(4095739776), // VLD1d32wb_register
2551
0
    UINT64_C(4095739855), // VLD1d64
2552
0
    UINT64_C(4095738575), // VLD1d64Q
2553
0
    UINT64_C(0),  // VLD1d64QPseudo
2554
0
    UINT64_C(0),  // VLD1d64QPseudoWB_fixed
2555
0
    UINT64_C(0),  // VLD1d64QPseudoWB_register
2556
0
    UINT64_C(4095738573), // VLD1d64Qwb_fixed
2557
0
    UINT64_C(4095738560), // VLD1d64Qwb_register
2558
0
    UINT64_C(4095739599), // VLD1d64T
2559
0
    UINT64_C(0),  // VLD1d64TPseudo
2560
0
    UINT64_C(0),  // VLD1d64TPseudoWB_fixed
2561
0
    UINT64_C(0),  // VLD1d64TPseudoWB_register
2562
0
    UINT64_C(4095739597), // VLD1d64Twb_fixed
2563
0
    UINT64_C(4095739584), // VLD1d64Twb_register
2564
0
    UINT64_C(4095739853), // VLD1d64wb_fixed
2565
0
    UINT64_C(4095739840), // VLD1d64wb_register
2566
0
    UINT64_C(4095739663), // VLD1d8
2567
0
    UINT64_C(4095738383), // VLD1d8Q
2568
0
    UINT64_C(0),  // VLD1d8QPseudo
2569
0
    UINT64_C(0),  // VLD1d8QPseudoWB_fixed
2570
0
    UINT64_C(0),  // VLD1d8QPseudoWB_register
2571
0
    UINT64_C(4095738381), // VLD1d8Qwb_fixed
2572
0
    UINT64_C(4095738368), // VLD1d8Qwb_register
2573
0
    UINT64_C(4095739407), // VLD1d8T
2574
0
    UINT64_C(0),  // VLD1d8TPseudo
2575
0
    UINT64_C(0),  // VLD1d8TPseudoWB_fixed
2576
0
    UINT64_C(0),  // VLD1d8TPseudoWB_register
2577
0
    UINT64_C(4095739405), // VLD1d8Twb_fixed
2578
0
    UINT64_C(4095739392), // VLD1d8Twb_register
2579
0
    UINT64_C(4095739661), // VLD1d8wb_fixed
2580
0
    UINT64_C(4095739648), // VLD1d8wb_register
2581
0
    UINT64_C(4095740495), // VLD1q16
2582
0
    UINT64_C(0),  // VLD1q16HighQPseudo
2583
0
    UINT64_C(0),  // VLD1q16HighQPseudo_UPD
2584
0
    UINT64_C(0),  // VLD1q16HighTPseudo
2585
0
    UINT64_C(0),  // VLD1q16HighTPseudo_UPD
2586
0
    UINT64_C(0),  // VLD1q16LowQPseudo_UPD
2587
0
    UINT64_C(0),  // VLD1q16LowTPseudo_UPD
2588
0
    UINT64_C(4095740493), // VLD1q16wb_fixed
2589
0
    UINT64_C(4095740480), // VLD1q16wb_register
2590
0
    UINT64_C(4095740559), // VLD1q32
2591
0
    UINT64_C(0),  // VLD1q32HighQPseudo
2592
0
    UINT64_C(0),  // VLD1q32HighQPseudo_UPD
2593
0
    UINT64_C(0),  // VLD1q32HighTPseudo
2594
0
    UINT64_C(0),  // VLD1q32HighTPseudo_UPD
2595
0
    UINT64_C(0),  // VLD1q32LowQPseudo_UPD
2596
0
    UINT64_C(0),  // VLD1q32LowTPseudo_UPD
2597
0
    UINT64_C(4095740557), // VLD1q32wb_fixed
2598
0
    UINT64_C(4095740544), // VLD1q32wb_register
2599
0
    UINT64_C(4095740623), // VLD1q64
2600
0
    UINT64_C(0),  // VLD1q64HighQPseudo
2601
0
    UINT64_C(0),  // VLD1q64HighQPseudo_UPD
2602
0
    UINT64_C(0),  // VLD1q64HighTPseudo
2603
0
    UINT64_C(0),  // VLD1q64HighTPseudo_UPD
2604
0
    UINT64_C(0),  // VLD1q64LowQPseudo_UPD
2605
0
    UINT64_C(0),  // VLD1q64LowTPseudo_UPD
2606
0
    UINT64_C(4095740621), // VLD1q64wb_fixed
2607
0
    UINT64_C(4095740608), // VLD1q64wb_register
2608
0
    UINT64_C(4095740431), // VLD1q8
2609
0
    UINT64_C(0),  // VLD1q8HighQPseudo
2610
0
    UINT64_C(0),  // VLD1q8HighQPseudo_UPD
2611
0
    UINT64_C(0),  // VLD1q8HighTPseudo
2612
0
    UINT64_C(0),  // VLD1q8HighTPseudo_UPD
2613
0
    UINT64_C(0),  // VLD1q8LowQPseudo_UPD
2614
0
    UINT64_C(0),  // VLD1q8LowTPseudo_UPD
2615
0
    UINT64_C(4095740429), // VLD1q8wb_fixed
2616
0
    UINT64_C(4095740416), // VLD1q8wb_register
2617
0
    UINT64_C(4104129871), // VLD2DUPd16
2618
0
    UINT64_C(4104129869), // VLD2DUPd16wb_fixed
2619
0
    UINT64_C(4104129856), // VLD2DUPd16wb_register
2620
0
    UINT64_C(4104129903), // VLD2DUPd16x2
2621
0
    UINT64_C(4104129901), // VLD2DUPd16x2wb_fixed
2622
0
    UINT64_C(4104129888), // VLD2DUPd16x2wb_register
2623
0
    UINT64_C(4104129935), // VLD2DUPd32
2624
0
    UINT64_C(4104129933), // VLD2DUPd32wb_fixed
2625
0
    UINT64_C(4104129920), // VLD2DUPd32wb_register
2626
0
    UINT64_C(4104129967), // VLD2DUPd32x2
2627
0
    UINT64_C(4104129965), // VLD2DUPd32x2wb_fixed
2628
0
    UINT64_C(4104129952), // VLD2DUPd32x2wb_register
2629
0
    UINT64_C(4104129807), // VLD2DUPd8
2630
0
    UINT64_C(4104129805), // VLD2DUPd8wb_fixed
2631
0
    UINT64_C(4104129792), // VLD2DUPd8wb_register
2632
0
    UINT64_C(4104129839), // VLD2DUPd8x2
2633
0
    UINT64_C(4104129837), // VLD2DUPd8x2wb_fixed
2634
0
    UINT64_C(4104129824), // VLD2DUPd8x2wb_register
2635
0
    UINT64_C(0),  // VLD2DUPq16EvenPseudo
2636
0
    UINT64_C(0),  // VLD2DUPq16OddPseudo
2637
0
    UINT64_C(0),  // VLD2DUPq16OddPseudoWB_fixed
2638
0
    UINT64_C(0),  // VLD2DUPq16OddPseudoWB_register
2639
0
    UINT64_C(0),  // VLD2DUPq32EvenPseudo
2640
0
    UINT64_C(0),  // VLD2DUPq32OddPseudo
2641
0
    UINT64_C(0),  // VLD2DUPq32OddPseudoWB_fixed
2642
0
    UINT64_C(0),  // VLD2DUPq32OddPseudoWB_register
2643
0
    UINT64_C(0),  // VLD2DUPq8EvenPseudo
2644
0
    UINT64_C(0),  // VLD2DUPq8OddPseudo
2645
0
    UINT64_C(0),  // VLD2DUPq8OddPseudoWB_fixed
2646
0
    UINT64_C(0),  // VLD2DUPq8OddPseudoWB_register
2647
0
    UINT64_C(4104127759), // VLD2LNd16
2648
0
    UINT64_C(0),  // VLD2LNd16Pseudo
2649
0
    UINT64_C(0),  // VLD2LNd16Pseudo_UPD
2650
0
    UINT64_C(4104127744), // VLD2LNd16_UPD
2651
0
    UINT64_C(4104128783), // VLD2LNd32
2652
0
    UINT64_C(0),  // VLD2LNd32Pseudo
2653
0
    UINT64_C(0),  // VLD2LNd32Pseudo_UPD
2654
0
    UINT64_C(4104128768), // VLD2LNd32_UPD
2655
0
    UINT64_C(4104126735), // VLD2LNd8
2656
0
    UINT64_C(0),  // VLD2LNd8Pseudo
2657
0
    UINT64_C(0),  // VLD2LNd8Pseudo_UPD
2658
0
    UINT64_C(4104126720), // VLD2LNd8_UPD
2659
0
    UINT64_C(4104127791), // VLD2LNq16
2660
0
    UINT64_C(0),  // VLD2LNq16Pseudo
2661
0
    UINT64_C(0),  // VLD2LNq16Pseudo_UPD
2662
0
    UINT64_C(4104127776), // VLD2LNq16_UPD
2663
0
    UINT64_C(4104128847), // VLD2LNq32
2664
0
    UINT64_C(0),  // VLD2LNq32Pseudo
2665
0
    UINT64_C(0),  // VLD2LNq32Pseudo_UPD
2666
0
    UINT64_C(4104128832), // VLD2LNq32_UPD
2667
0
    UINT64_C(4095740239), // VLD2b16
2668
0
    UINT64_C(4095740237), // VLD2b16wb_fixed
2669
0
    UINT64_C(4095740224), // VLD2b16wb_register
2670
0
    UINT64_C(4095740303), // VLD2b32
2671
0
    UINT64_C(4095740301), // VLD2b32wb_fixed
2672
0
    UINT64_C(4095740288), // VLD2b32wb_register
2673
0
    UINT64_C(4095740175), // VLD2b8
2674
0
    UINT64_C(4095740173), // VLD2b8wb_fixed
2675
0
    UINT64_C(4095740160), // VLD2b8wb_register
2676
0
    UINT64_C(4095739983), // VLD2d16
2677
0
    UINT64_C(4095739981), // VLD2d16wb_fixed
2678
0
    UINT64_C(4095739968), // VLD2d16wb_register
2679
0
    UINT64_C(4095740047), // VLD2d32
2680
0
    UINT64_C(4095740045), // VLD2d32wb_fixed
2681
0
    UINT64_C(4095740032), // VLD2d32wb_register
2682
0
    UINT64_C(4095739919), // VLD2d8
2683
0
    UINT64_C(4095739917), // VLD2d8wb_fixed
2684
0
    UINT64_C(4095739904), // VLD2d8wb_register
2685
0
    UINT64_C(4095738703), // VLD2q16
2686
0
    UINT64_C(0),  // VLD2q16Pseudo
2687
0
    UINT64_C(0),  // VLD2q16PseudoWB_fixed
2688
0
    UINT64_C(0),  // VLD2q16PseudoWB_register
2689
0
    UINT64_C(4095738701), // VLD2q16wb_fixed
2690
0
    UINT64_C(4095738688), // VLD2q16wb_register
2691
0
    UINT64_C(4095738767), // VLD2q32
2692
0
    UINT64_C(0),  // VLD2q32Pseudo
2693
0
    UINT64_C(0),  // VLD2q32PseudoWB_fixed
2694
0
    UINT64_C(0),  // VLD2q32PseudoWB_register
2695
0
    UINT64_C(4095738765), // VLD2q32wb_fixed
2696
0
    UINT64_C(4095738752), // VLD2q32wb_register
2697
0
    UINT64_C(4095738639), // VLD2q8
2698
0
    UINT64_C(0),  // VLD2q8Pseudo
2699
0
    UINT64_C(0),  // VLD2q8PseudoWB_fixed
2700
0
    UINT64_C(0),  // VLD2q8PseudoWB_register
2701
0
    UINT64_C(4095738637), // VLD2q8wb_fixed
2702
0
    UINT64_C(4095738624), // VLD2q8wb_register
2703
0
    UINT64_C(4104130127), // VLD3DUPd16
2704
0
    UINT64_C(0),  // VLD3DUPd16Pseudo
2705
0
    UINT64_C(0),  // VLD3DUPd16Pseudo_UPD
2706
0
    UINT64_C(4104130112), // VLD3DUPd16_UPD
2707
0
    UINT64_C(4104130191), // VLD3DUPd32
2708
0
    UINT64_C(0),  // VLD3DUPd32Pseudo
2709
0
    UINT64_C(0),  // VLD3DUPd32Pseudo_UPD
2710
0
    UINT64_C(4104130176), // VLD3DUPd32_UPD
2711
0
    UINT64_C(4104130063), // VLD3DUPd8
2712
0
    UINT64_C(0),  // VLD3DUPd8Pseudo
2713
0
    UINT64_C(0),  // VLD3DUPd8Pseudo_UPD
2714
0
    UINT64_C(4104130048), // VLD3DUPd8_UPD
2715
0
    UINT64_C(4104130159), // VLD3DUPq16
2716
0
    UINT64_C(0),  // VLD3DUPq16EvenPseudo
2717
0
    UINT64_C(0),  // VLD3DUPq16OddPseudo
2718
0
    UINT64_C(0),  // VLD3DUPq16OddPseudo_UPD
2719
0
    UINT64_C(4104130144), // VLD3DUPq16_UPD
2720
0
    UINT64_C(4104130223), // VLD3DUPq32
2721
0
    UINT64_C(0),  // VLD3DUPq32EvenPseudo
2722
0
    UINT64_C(0),  // VLD3DUPq32OddPseudo
2723
0
    UINT64_C(0),  // VLD3DUPq32OddPseudo_UPD
2724
0
    UINT64_C(4104130208), // VLD3DUPq32_UPD
2725
0
    UINT64_C(4104130095), // VLD3DUPq8
2726
0
    UINT64_C(0),  // VLD3DUPq8EvenPseudo
2727
0
    UINT64_C(0),  // VLD3DUPq8OddPseudo
2728
0
    UINT64_C(0),  // VLD3DUPq8OddPseudo_UPD
2729
0
    UINT64_C(4104130080), // VLD3DUPq8_UPD
2730
0
    UINT64_C(4104128015), // VLD3LNd16
2731
0
    UINT64_C(0),  // VLD3LNd16Pseudo
2732
0
    UINT64_C(0),  // VLD3LNd16Pseudo_UPD
2733
0
    UINT64_C(4104128000), // VLD3LNd16_UPD
2734
0
    UINT64_C(4104129039), // VLD3LNd32
2735
0
    UINT64_C(0),  // VLD3LNd32Pseudo
2736
0
    UINT64_C(0),  // VLD3LNd32Pseudo_UPD
2737
0
    UINT64_C(4104129024), // VLD3LNd32_UPD
2738
0
    UINT64_C(4104126991), // VLD3LNd8
2739
0
    UINT64_C(0),  // VLD3LNd8Pseudo
2740
0
    UINT64_C(0),  // VLD3LNd8Pseudo_UPD
2741
0
    UINT64_C(4104126976), // VLD3LNd8_UPD
2742
0
    UINT64_C(4104128047), // VLD3LNq16
2743
0
    UINT64_C(0),  // VLD3LNq16Pseudo
2744
0
    UINT64_C(0),  // VLD3LNq16Pseudo_UPD
2745
0
    UINT64_C(4104128032), // VLD3LNq16_UPD
2746
0
    UINT64_C(4104129103), // VLD3LNq32
2747
0
    UINT64_C(0),  // VLD3LNq32Pseudo
2748
0
    UINT64_C(0),  // VLD3LNq32Pseudo_UPD
2749
0
    UINT64_C(4104129088), // VLD3LNq32_UPD
2750
0
    UINT64_C(4095738959), // VLD3d16
2751
0
    UINT64_C(0),  // VLD3d16Pseudo
2752
0
    UINT64_C(0),  // VLD3d16Pseudo_UPD
2753
0
    UINT64_C(4095738944), // VLD3d16_UPD
2754
0
    UINT64_C(4095739023), // VLD3d32
2755
0
    UINT64_C(0),  // VLD3d32Pseudo
2756
0
    UINT64_C(0),  // VLD3d32Pseudo_UPD
2757
0
    UINT64_C(4095739008), // VLD3d32_UPD
2758
0
    UINT64_C(4095738895), // VLD3d8
2759
0
    UINT64_C(0),  // VLD3d8Pseudo
2760
0
    UINT64_C(0),  // VLD3d8Pseudo_UPD
2761
0
    UINT64_C(4095738880), // VLD3d8_UPD
2762
0
    UINT64_C(4095739215), // VLD3q16
2763
0
    UINT64_C(0),  // VLD3q16Pseudo_UPD
2764
0
    UINT64_C(4095739200), // VLD3q16_UPD
2765
0
    UINT64_C(0),  // VLD3q16oddPseudo
2766
0
    UINT64_C(0),  // VLD3q16oddPseudo_UPD
2767
0
    UINT64_C(4095739279), // VLD3q32
2768
0
    UINT64_C(0),  // VLD3q32Pseudo_UPD
2769
0
    UINT64_C(4095739264), // VLD3q32_UPD
2770
0
    UINT64_C(0),  // VLD3q32oddPseudo
2771
0
    UINT64_C(0),  // VLD3q32oddPseudo_UPD
2772
0
    UINT64_C(4095739151), // VLD3q8
2773
0
    UINT64_C(0),  // VLD3q8Pseudo_UPD
2774
0
    UINT64_C(4095739136), // VLD3q8_UPD
2775
0
    UINT64_C(0),  // VLD3q8oddPseudo
2776
0
    UINT64_C(0),  // VLD3q8oddPseudo_UPD
2777
0
    UINT64_C(4104130383), // VLD4DUPd16
2778
0
    UINT64_C(0),  // VLD4DUPd16Pseudo
2779
0
    UINT64_C(0),  // VLD4DUPd16Pseudo_UPD
2780
0
    UINT64_C(4104130368), // VLD4DUPd16_UPD
2781
0
    UINT64_C(4104130447), // VLD4DUPd32
2782
0
    UINT64_C(0),  // VLD4DUPd32Pseudo
2783
0
    UINT64_C(0),  // VLD4DUPd32Pseudo_UPD
2784
0
    UINT64_C(4104130432), // VLD4DUPd32_UPD
2785
0
    UINT64_C(4104130319), // VLD4DUPd8
2786
0
    UINT64_C(0),  // VLD4DUPd8Pseudo
2787
0
    UINT64_C(0),  // VLD4DUPd8Pseudo_UPD
2788
0
    UINT64_C(4104130304), // VLD4DUPd8_UPD
2789
0
    UINT64_C(4104130415), // VLD4DUPq16
2790
0
    UINT64_C(0),  // VLD4DUPq16EvenPseudo
2791
0
    UINT64_C(0),  // VLD4DUPq16OddPseudo
2792
0
    UINT64_C(0),  // VLD4DUPq16OddPseudo_UPD
2793
0
    UINT64_C(4104130400), // VLD4DUPq16_UPD
2794
0
    UINT64_C(4104130479), // VLD4DUPq32
2795
0
    UINT64_C(0),  // VLD4DUPq32EvenPseudo
2796
0
    UINT64_C(0),  // VLD4DUPq32OddPseudo
2797
0
    UINT64_C(0),  // VLD4DUPq32OddPseudo_UPD
2798
0
    UINT64_C(4104130464), // VLD4DUPq32_UPD
2799
0
    UINT64_C(4104130351), // VLD4DUPq8
2800
0
    UINT64_C(0),  // VLD4DUPq8EvenPseudo
2801
0
    UINT64_C(0),  // VLD4DUPq8OddPseudo
2802
0
    UINT64_C(0),  // VLD4DUPq8OddPseudo_UPD
2803
0
    UINT64_C(4104130336), // VLD4DUPq8_UPD
2804
0
    UINT64_C(4104128271), // VLD4LNd16
2805
0
    UINT64_C(0),  // VLD4LNd16Pseudo
2806
0
    UINT64_C(0),  // VLD4LNd16Pseudo_UPD
2807
0
    UINT64_C(4104128256), // VLD4LNd16_UPD
2808
0
    UINT64_C(4104129295), // VLD4LNd32
2809
0
    UINT64_C(0),  // VLD4LNd32Pseudo
2810
0
    UINT64_C(0),  // VLD4LNd32Pseudo_UPD
2811
0
    UINT64_C(4104129280), // VLD4LNd32_UPD
2812
0
    UINT64_C(4104127247), // VLD4LNd8
2813
0
    UINT64_C(0),  // VLD4LNd8Pseudo
2814
0
    UINT64_C(0),  // VLD4LNd8Pseudo_UPD
2815
0
    UINT64_C(4104127232), // VLD4LNd8_UPD
2816
0
    UINT64_C(4104128303), // VLD4LNq16
2817
0
    UINT64_C(0),  // VLD4LNq16Pseudo
2818
0
    UINT64_C(0),  // VLD4LNq16Pseudo_UPD
2819
0
    UINT64_C(4104128288), // VLD4LNq16_UPD
2820
0
    UINT64_C(4104129359), // VLD4LNq32
2821
0
    UINT64_C(0),  // VLD4LNq32Pseudo
2822
0
    UINT64_C(0),  // VLD4LNq32Pseudo_UPD
2823
0
    UINT64_C(4104129344), // VLD4LNq32_UPD
2824
0
    UINT64_C(4095737935), // VLD4d16
2825
0
    UINT64_C(0),  // VLD4d16Pseudo
2826
0
    UINT64_C(0),  // VLD4d16Pseudo_UPD
2827
0
    UINT64_C(4095737920), // VLD4d16_UPD
2828
0
    UINT64_C(4095737999), // VLD4d32
2829
0
    UINT64_C(0),  // VLD4d32Pseudo
2830
0
    UINT64_C(0),  // VLD4d32Pseudo_UPD
2831
0
    UINT64_C(4095737984), // VLD4d32_UPD
2832
0
    UINT64_C(4095737871), // VLD4d8
2833
0
    UINT64_C(0),  // VLD4d8Pseudo
2834
0
    UINT64_C(0),  // VLD4d8Pseudo_UPD
2835
0
    UINT64_C(4095737856), // VLD4d8_UPD
2836
0
    UINT64_C(4095738191), // VLD4q16
2837
0
    UINT64_C(0),  // VLD4q16Pseudo_UPD
2838
0
    UINT64_C(4095738176), // VLD4q16_UPD
2839
0
    UINT64_C(0),  // VLD4q16oddPseudo
2840
0
    UINT64_C(0),  // VLD4q16oddPseudo_UPD
2841
0
    UINT64_C(4095738255), // VLD4q32
2842
0
    UINT64_C(0),  // VLD4q32Pseudo_UPD
2843
0
    UINT64_C(4095738240), // VLD4q32_UPD
2844
0
    UINT64_C(0),  // VLD4q32oddPseudo
2845
0
    UINT64_C(0),  // VLD4q32oddPseudo_UPD
2846
0
    UINT64_C(4095738127), // VLD4q8
2847
0
    UINT64_C(0),  // VLD4q8Pseudo_UPD
2848
0
    UINT64_C(4095738112), // VLD4q8_UPD
2849
0
    UINT64_C(0),  // VLD4q8oddPseudo
2850
0
    UINT64_C(0),  // VLD4q8oddPseudo_UPD
2851
0
    UINT64_C(221252352),  // VLDMDDB_UPD
2852
0
    UINT64_C(210766592),  // VLDMDIA
2853
0
    UINT64_C(212863744),  // VLDMDIA_UPD
2854
0
    UINT64_C(0),  // VLDMQIA
2855
0
    UINT64_C(221252096),  // VLDMSDB_UPD
2856
0
    UINT64_C(210766336),  // VLDMSIA
2857
0
    UINT64_C(212863488),  // VLDMSIA_UPD
2858
0
    UINT64_C(219155200),  // VLDRD
2859
0
    UINT64_C(219154688),  // VLDRH
2860
0
    UINT64_C(219154944),  // VLDRS
2861
0
    UINT64_C(223399808),  // VLDR_FPCXTNS_off
2862
0
    UINT64_C(208719744),  // VLDR_FPCXTNS_post
2863
0
    UINT64_C(225496960),  // VLDR_FPCXTNS_pre
2864
0
    UINT64_C(223408000),  // VLDR_FPCXTS_off
2865
0
    UINT64_C(208727936),  // VLDR_FPCXTS_post
2866
0
    UINT64_C(225505152),  // VLDR_FPCXTS_pre
2867
0
    UINT64_C(219172736),  // VLDR_FPSCR_NZCVQC_off
2868
0
    UINT64_C(204492672),  // VLDR_FPSCR_NZCVQC_post
2869
0
    UINT64_C(221269888),  // VLDR_FPSCR_NZCVQC_pre
2870
0
    UINT64_C(219164544),  // VLDR_FPSCR_off
2871
0
    UINT64_C(204484480),  // VLDR_FPSCR_post
2872
0
    UINT64_C(221261696),  // VLDR_FPSCR_pre
2873
0
    UINT64_C(223391616),  // VLDR_P0_off
2874
0
    UINT64_C(208711552),  // VLDR_P0_post
2875
0
    UINT64_C(225488768),  // VLDR_P0_pre
2876
0
    UINT64_C(223383424),  // VLDR_VPR_off
2877
0
    UINT64_C(208703360),  // VLDR_VPR_post
2878
0
    UINT64_C(225480576),  // VLDR_VPR_pre
2879
0
    UINT64_C(204474880),  // VLLDM
2880
0
    UINT64_C(203426304),  // VLSTM
2881
0
    UINT64_C(4060090112), // VMAXfd
2882
0
    UINT64_C(4060090176), // VMAXfq
2883
0
    UINT64_C(4061138688), // VMAXhd
2884
0
    UINT64_C(4061138752), // VMAXhq
2885
0
    UINT64_C(4060087872), // VMAXsv16i8
2886
0
    UINT64_C(4062184960), // VMAXsv2i32
2887
0
    UINT64_C(4061136384), // VMAXsv4i16
2888
0
    UINT64_C(4062185024), // VMAXsv4i32
2889
0
    UINT64_C(4061136448), // VMAXsv8i16
2890
0
    UINT64_C(4060087808), // VMAXsv8i8
2891
0
    UINT64_C(4076865088), // VMAXuv16i8
2892
0
    UINT64_C(4078962176), // VMAXuv2i32
2893
0
    UINT64_C(4077913600), // VMAXuv4i16
2894
0
    UINT64_C(4078962240), // VMAXuv4i32
2895
0
    UINT64_C(4077913664), // VMAXuv8i16
2896
0
    UINT64_C(4076865024), // VMAXuv8i8
2897
0
    UINT64_C(4062187264), // VMINfd
2898
0
    UINT64_C(4062187328), // VMINfq
2899
0
    UINT64_C(4063235840), // VMINhd
2900
0
    UINT64_C(4063235904), // VMINhq
2901
0
    UINT64_C(4060087888), // VMINsv16i8
2902
0
    UINT64_C(4062184976), // VMINsv2i32
2903
0
    UINT64_C(4061136400), // VMINsv4i16
2904
0
    UINT64_C(4062185040), // VMINsv4i32
2905
0
    UINT64_C(4061136464), // VMINsv8i16
2906
0
    UINT64_C(4060087824), // VMINsv8i8
2907
0
    UINT64_C(4076865104), // VMINuv16i8
2908
0
    UINT64_C(4078962192), // VMINuv2i32
2909
0
    UINT64_C(4077913616), // VMINuv4i16
2910
0
    UINT64_C(4078962256), // VMINuv4i32
2911
0
    UINT64_C(4077913680), // VMINuv8i16
2912
0
    UINT64_C(4076865040), // VMINuv8i8
2913
0
    UINT64_C(234883840),  // VMLAD
2914
0
    UINT64_C(234883328),  // VMLAH
2915
0
    UINT64_C(4070572608), // VMLALslsv2i32
2916
0
    UINT64_C(4069524032), // VMLALslsv4i16
2917
0
    UINT64_C(4087349824), // VMLALsluv2i32
2918
0
    UINT64_C(4086301248), // VMLALsluv4i16
2919
0
    UINT64_C(4070574080), // VMLALsv2i64
2920
0
    UINT64_C(4069525504), // VMLALsv4i32
2921
0
    UINT64_C(4068476928), // VMLALsv8i16
2922
0
    UINT64_C(4087351296), // VMLALuv2i64
2923
0
    UINT64_C(4086302720), // VMLALuv4i32
2924
0
    UINT64_C(4085254144), // VMLALuv8i16
2925
0
    UINT64_C(234883584),  // VMLAS
2926
0
    UINT64_C(4060089616), // VMLAfd
2927
0
    UINT64_C(4060089680), // VMLAfq
2928
0
    UINT64_C(4061138192), // VMLAhd
2929
0
    UINT64_C(4061138256), // VMLAhq
2930
0
    UINT64_C(4070572352), // VMLAslfd
2931
0
    UINT64_C(4087349568), // VMLAslfq
2932
0
    UINT64_C(4069523776), // VMLAslhd
2933
0
    UINT64_C(4086300992), // VMLAslhq
2934
0
    UINT64_C(4070572096), // VMLAslv2i32
2935
0
    UINT64_C(4069523520), // VMLAslv4i16
2936
0
    UINT64_C(4087349312), // VMLAslv4i32
2937
0
    UINT64_C(4086300736), // VMLAslv8i16
2938
0
    UINT64_C(4060088640), // VMLAv16i8
2939
0
    UINT64_C(4062185728), // VMLAv2i32
2940
0
    UINT64_C(4061137152), // VMLAv4i16
2941
0
    UINT64_C(4062185792), // VMLAv4i32
2942
0
    UINT64_C(4061137216), // VMLAv8i16
2943
0
    UINT64_C(4060088576), // VMLAv8i8
2944
0
    UINT64_C(234883904),  // VMLSD
2945
0
    UINT64_C(234883392),  // VMLSH
2946
0
    UINT64_C(4070573632), // VMLSLslsv2i32
2947
0
    UINT64_C(4069525056), // VMLSLslsv4i16
2948
0
    UINT64_C(4087350848), // VMLSLsluv2i32
2949
0
    UINT64_C(4086302272), // VMLSLsluv4i16
2950
0
    UINT64_C(4070574592), // VMLSLsv2i64
2951
0
    UINT64_C(4069526016), // VMLSLsv4i32
2952
0
    UINT64_C(4068477440), // VMLSLsv8i16
2953
0
    UINT64_C(4087351808), // VMLSLuv2i64
2954
0
    UINT64_C(4086303232), // VMLSLuv4i32
2955
0
    UINT64_C(4085254656), // VMLSLuv8i16
2956
0
    UINT64_C(234883648),  // VMLSS
2957
0
    UINT64_C(4062186768), // VMLSfd
2958
0
    UINT64_C(4062186832), // VMLSfq
2959
0
    UINT64_C(4063235344), // VMLShd
2960
0
    UINT64_C(4063235408), // VMLShq
2961
0
    UINT64_C(4070573376), // VMLSslfd
2962
0
    UINT64_C(4087350592), // VMLSslfq
2963
0
    UINT64_C(4069524800), // VMLSslhd
2964
0
    UINT64_C(4086302016), // VMLSslhq
2965
0
    UINT64_C(4070573120), // VMLSslv2i32
2966
0
    UINT64_C(4069524544), // VMLSslv4i16
2967
0
    UINT64_C(4087350336), // VMLSslv4i32
2968
0
    UINT64_C(4086301760), // VMLSslv8i16
2969
0
    UINT64_C(4076865856), // VMLSv16i8
2970
0
    UINT64_C(4078962944), // VMLSv2i32
2971
0
    UINT64_C(4077914368), // VMLSv4i16
2972
0
    UINT64_C(4078963008), // VMLSv4i32
2973
0
    UINT64_C(4077914432), // VMLSv8i16
2974
0
    UINT64_C(4076865792), // VMLSv8i8
2975
0
    UINT64_C(4227861568), // VMMLA
2976
0
    UINT64_C(246418240),  // VMOVD
2977
0
    UINT64_C(205523728),  // VMOVDRR
2978
0
    UINT64_C(4272949824), // VMOVH
2979
0
    UINT64_C(234883344),  // VMOVHR
2980
0
    UINT64_C(4070574608), // VMOVLsv2i64
2981
0
    UINT64_C(4069526032), // VMOVLsv4i32
2982
0
    UINT64_C(4069001744), // VMOVLsv8i16
2983
0
    UINT64_C(4087351824), // VMOVLuv2i64
2984
0
    UINT64_C(4086303248), // VMOVLuv4i32
2985
0
    UINT64_C(4085778960), // VMOVLuv8i16
2986
0
    UINT64_C(4089053696), // VMOVNv2i32
2987
0
    UINT64_C(4088791552), // VMOVNv4i16
2988
0
    UINT64_C(4088529408), // VMOVNv8i8
2989
0
    UINT64_C(235931920),  // VMOVRH
2990
0
    UINT64_C(206572304),  // VMOVRRD
2991
0
    UINT64_C(206572048),  // VMOVRRS
2992
0
    UINT64_C(235932176),  // VMOVRS
2993
0
    UINT64_C(246417984),  // VMOVS
2994
0
    UINT64_C(234883600),  // VMOVSR
2995
0
    UINT64_C(205523472),  // VMOVSRR
2996
0
    UINT64_C(4068478544), // VMOVv16i8
2997
0
    UINT64_C(4068478512), // VMOVv1i64
2998
0
    UINT64_C(4068478736), // VMOVv2f32
2999
0
    UINT64_C(4068474896), // VMOVv2i32
3000
0
    UINT64_C(4068478576), // VMOVv2i64
3001
0
    UINT64_C(4068478800), // VMOVv4f32
3002
0
    UINT64_C(4068476944), // VMOVv4i16
3003
0
    UINT64_C(4068474960), // VMOVv4i32
3004
0
    UINT64_C(4068477008), // VMOVv8i16
3005
0
    UINT64_C(4068478480), // VMOVv8i8
3006
0
    UINT64_C(250677776),  // VMRS
3007
0
    UINT64_C(251529744),  // VMRS_FPCXTNS
3008
0
    UINT64_C(251595280),  // VMRS_FPCXTS
3009
0
    UINT64_C(251136528),  // VMRS_FPEXC
3010
0
    UINT64_C(251202064),  // VMRS_FPINST
3011
0
    UINT64_C(251267600),  // VMRS_FPINST2
3012
0
    UINT64_C(250743312),  // VMRS_FPSCR_NZCVQC
3013
0
    UINT64_C(250612240),  // VMRS_FPSID
3014
0
    UINT64_C(251070992),  // VMRS_MVFR0
3015
0
    UINT64_C(251005456),  // VMRS_MVFR1
3016
0
    UINT64_C(250939920),  // VMRS_MVFR2
3017
0
    UINT64_C(251464208),  // VMRS_P0
3018
0
    UINT64_C(251398672),  // VMRS_VPR
3019
0
    UINT64_C(249629200),  // VMSR
3020
0
    UINT64_C(250481168),  // VMSR_FPCXTNS
3021
0
    UINT64_C(250546704),  // VMSR_FPCXTS
3022
0
    UINT64_C(250087952),  // VMSR_FPEXC
3023
0
    UINT64_C(250153488),  // VMSR_FPINST
3024
0
    UINT64_C(250219024),  // VMSR_FPINST2
3025
0
    UINT64_C(249694736),  // VMSR_FPSCR_NZCVQC
3026
0
    UINT64_C(249563664),  // VMSR_FPSID
3027
0
    UINT64_C(250415632),  // VMSR_P0
3028
0
    UINT64_C(250350096),  // VMSR_VPR
3029
0
    UINT64_C(236980992),  // VMULD
3030
0
    UINT64_C(236980480),  // VMULH
3031
0
    UINT64_C(4070575616), // VMULLp64
3032
0
    UINT64_C(4068478464), // VMULLp8
3033
0
    UINT64_C(4070574656), // VMULLslsv2i32
3034
0
    UINT64_C(4069526080), // VMULLslsv4i16
3035
0
    UINT64_C(4087351872), // VMULLsluv2i32
3036
0
    UINT64_C(4086303296), // VMULLsluv4i16
3037
0
    UINT64_C(4070575104), // VMULLsv2i64
3038
0
    UINT64_C(4069526528), // VMULLsv4i32
3039
0
    UINT64_C(4068477952), // VMULLsv8i16
3040
0
    UINT64_C(4087352320), // VMULLuv2i64
3041
0
    UINT64_C(4086303744), // VMULLuv4i32
3042
0
    UINT64_C(4085255168), // VMULLuv8i16
3043
0
    UINT64_C(236980736),  // VMULS
3044
0
    UINT64_C(4076866832), // VMULfd
3045
0
    UINT64_C(4076866896), // VMULfq
3046
0
    UINT64_C(4077915408), // VMULhd
3047
0
    UINT64_C(4077915472), // VMULhq
3048
0
    UINT64_C(4076865808), // VMULpd
3049
0
    UINT64_C(4076865872), // VMULpq
3050
0
    UINT64_C(4070574400), // VMULslfd
3051
0
    UINT64_C(4087351616), // VMULslfq
3052
0
    UINT64_C(4069525824), // VMULslhd
3053
0
    UINT64_C(4086303040), // VMULslhq
3054
0
    UINT64_C(4070574144), // VMULslv2i32
3055
0
    UINT64_C(4069525568), // VMULslv4i16
3056
0
    UINT64_C(4087351360), // VMULslv4i32
3057
0
    UINT64_C(4086302784), // VMULslv8i16
3058
0
    UINT64_C(4060088656), // VMULv16i8
3059
0
    UINT64_C(4062185744), // VMULv2i32
3060
0
    UINT64_C(4061137168), // VMULv4i16
3061
0
    UINT64_C(4062185808), // VMULv4i32
3062
0
    UINT64_C(4061137232), // VMULv8i16
3063
0
    UINT64_C(4060088592), // VMULv8i8
3064
0
    UINT64_C(4088399232), // VMVNd
3065
0
    UINT64_C(4088399296), // VMVNq
3066
0
    UINT64_C(4068474928), // VMVNv2i32
3067
0
    UINT64_C(4068476976), // VMVNv4i16
3068
0
    UINT64_C(4068474992), // VMVNv4i32
3069
0
    UINT64_C(4068477040), // VMVNv8i16
3070
0
    UINT64_C(246483776),  // VNEGD
3071
0
    UINT64_C(246483264),  // VNEGH
3072
0
    UINT64_C(246483520),  // VNEGS
3073
0
    UINT64_C(4088989632), // VNEGf32q
3074
0
    UINT64_C(4088989568), // VNEGfd
3075
0
    UINT64_C(4088727424), // VNEGhd
3076
0
    UINT64_C(4088727488), // VNEGhq
3077
0
    UINT64_C(4088726400), // VNEGs16d
3078
0
    UINT64_C(4088726464), // VNEGs16q
3079
0
    UINT64_C(4088988544), // VNEGs32d
3080
0
    UINT64_C(4088988608), // VNEGs32q
3081
0
    UINT64_C(4088464256), // VNEGs8d
3082
0
    UINT64_C(4088464320), // VNEGs8q
3083
0
    UINT64_C(235932480),  // VNMLAD
3084
0
    UINT64_C(235931968),  // VNMLAH
3085
0
    UINT64_C(235932224),  // VNMLAS
3086
0
    UINT64_C(235932416),  // VNMLSD
3087
0
    UINT64_C(235931904),  // VNMLSH
3088
0
    UINT64_C(235932160),  // VNMLSS
3089
0
    UINT64_C(236981056),  // VNMULD
3090
0
    UINT64_C(236980544),  // VNMULH
3091
0
    UINT64_C(236980800),  // VNMULS
3092
0
    UINT64_C(4063232272), // VORNd
3093
0
    UINT64_C(4063232336), // VORNq
3094
0
    UINT64_C(4062183696), // VORRd
3095
0
    UINT64_C(4068475152), // VORRiv2i32
3096
0
    UINT64_C(4068477200), // VORRiv4i16
3097
0
    UINT64_C(4068475216), // VORRiv4i32
3098
0
    UINT64_C(4068477264), // VORRiv8i16
3099
0
    UINT64_C(4062183760), // VORRq
3100
0
    UINT64_C(4088399424), // VPADALsv16i8
3101
0
    UINT64_C(4088923648), // VPADALsv2i32
3102
0
    UINT64_C(4088661504), // VPADALsv4i16
3103
0
    UINT64_C(4088923712), // VPADALsv4i32
3104
0
    UINT64_C(4088661568), // VPADALsv8i16
3105
0
    UINT64_C(4088399360), // VPADALsv8i8
3106
0
    UINT64_C(4088399552), // VPADALuv16i8
3107
0
    UINT64_C(4088923776), // VPADALuv2i32
3108
0
    UINT64_C(4088661632), // VPADALuv4i16
3109
0
    UINT64_C(4088923840), // VPADALuv4i32
3110
0
    UINT64_C(4088661696), // VPADALuv8i16
3111
0
    UINT64_C(4088399488), // VPADALuv8i8
3112
0
    UINT64_C(4088398400), // VPADDLsv16i8
3113
0
    UINT64_C(4088922624), // VPADDLsv2i32
3114
0
    UINT64_C(4088660480), // VPADDLsv4i16
3115
0
    UINT64_C(4088922688), // VPADDLsv4i32
3116
0
    UINT64_C(4088660544), // VPADDLsv8i16
3117
0
    UINT64_C(4088398336), // VPADDLsv8i8
3118
0
    UINT64_C(4088398528), // VPADDLuv16i8
3119
0
    UINT64_C(4088922752), // VPADDLuv2i32
3120
0
    UINT64_C(4088660608), // VPADDLuv4i16
3121
0
    UINT64_C(4088922816), // VPADDLuv4i32
3122
0
    UINT64_C(4088660672), // VPADDLuv8i16
3123
0
    UINT64_C(4088398464), // VPADDLuv8i8
3124
0
    UINT64_C(4076866816), // VPADDf
3125
0
    UINT64_C(4077915392), // VPADDh
3126
0
    UINT64_C(4061137680), // VPADDi16
3127
0
    UINT64_C(4062186256), // VPADDi32
3128
0
    UINT64_C(4060089104), // VPADDi8
3129
0
    UINT64_C(4076867328), // VPMAXf
3130
0
    UINT64_C(4077915904), // VPMAXh
3131
0
    UINT64_C(4061137408), // VPMAXs16
3132
0
    UINT64_C(4062185984), // VPMAXs32
3133
0
    UINT64_C(4060088832), // VPMAXs8
3134
0
    UINT64_C(4077914624), // VPMAXu16
3135
0
    UINT64_C(4078963200), // VPMAXu32
3136
0
    UINT64_C(4076866048), // VPMAXu8
3137
0
    UINT64_C(4078964480), // VPMINf
3138
0
    UINT64_C(4080013056), // VPMINh
3139
0
    UINT64_C(4061137424), // VPMINs16
3140
0
    UINT64_C(4062186000), // VPMINs32
3141
0
    UINT64_C(4060088848), // VPMINs8
3142
0
    UINT64_C(4077914640), // VPMINu16
3143
0
    UINT64_C(4078963216), // VPMINu32
3144
0
    UINT64_C(4076866064), // VPMINu8
3145
0
    UINT64_C(4088399680), // VQABSv16i8
3146
0
    UINT64_C(4088923904), // VQABSv2i32
3147
0
    UINT64_C(4088661760), // VQABSv4i16
3148
0
    UINT64_C(4088923968), // VQABSv4i32
3149
0
    UINT64_C(4088661824), // VQABSv8i16
3150
0
    UINT64_C(4088399616), // VQABSv8i8
3151
0
    UINT64_C(4060086352), // VQADDsv16i8
3152
0
    UINT64_C(4063232016), // VQADDsv1i64
3153
0
    UINT64_C(4062183440), // VQADDsv2i32
3154
0
    UINT64_C(4063232080), // VQADDsv2i64
3155
0
    UINT64_C(4061134864), // VQADDsv4i16
3156
0
    UINT64_C(4062183504), // VQADDsv4i32
3157
0
    UINT64_C(4061134928), // VQADDsv8i16
3158
0
    UINT64_C(4060086288), // VQADDsv8i8
3159
0
    UINT64_C(4076863568), // VQADDuv16i8
3160
0
    UINT64_C(4080009232), // VQADDuv1i64
3161
0
    UINT64_C(4078960656), // VQADDuv2i32
3162
0
    UINT64_C(4080009296), // VQADDuv2i64
3163
0
    UINT64_C(4077912080), // VQADDuv4i16
3164
0
    UINT64_C(4078960720), // VQADDuv4i32
3165
0
    UINT64_C(4077912144), // VQADDuv8i16
3166
0
    UINT64_C(4076863504), // VQADDuv8i8
3167
0
    UINT64_C(4070572864), // VQDMLALslv2i32
3168
0
    UINT64_C(4069524288), // VQDMLALslv4i16
3169
0
    UINT64_C(4070574336), // VQDMLALv2i64
3170
0
    UINT64_C(4069525760), // VQDMLALv4i32
3171
0
    UINT64_C(4070573888), // VQDMLSLslv2i32
3172
0
    UINT64_C(4069525312), // VQDMLSLslv4i16
3173
0
    UINT64_C(4070574848), // VQDMLSLv2i64
3174
0
    UINT64_C(4069526272), // VQDMLSLv4i32
3175
0
    UINT64_C(4070575168), // VQDMULHslv2i32
3176
0
    UINT64_C(4069526592), // VQDMULHslv4i16
3177
0
    UINT64_C(4087352384), // VQDMULHslv4i32
3178
0
    UINT64_C(4086303808), // VQDMULHslv8i16
3179
0
    UINT64_C(4062186240), // VQDMULHv2i32
3180
0
    UINT64_C(4061137664), // VQDMULHv4i16
3181
0
    UINT64_C(4062186304), // VQDMULHv4i32
3182
0
    UINT64_C(4061137728), // VQDMULHv8i16
3183
0
    UINT64_C(4070574912), // VQDMULLslv2i32
3184
0
    UINT64_C(4069526336), // VQDMULLslv4i16
3185
0
    UINT64_C(4070575360), // VQDMULLv2i64
3186
0
    UINT64_C(4069526784), // VQDMULLv4i32
3187
0
    UINT64_C(4089053760), // VQMOVNsuv2i32
3188
0
    UINT64_C(4088791616), // VQMOVNsuv4i16
3189
0
    UINT64_C(4088529472), // VQMOVNsuv8i8
3190
0
    UINT64_C(4089053824), // VQMOVNsv2i32
3191
0
    UINT64_C(4088791680), // VQMOVNsv4i16
3192
0
    UINT64_C(4088529536), // VQMOVNsv8i8
3193
0
    UINT64_C(4089053888), // VQMOVNuv2i32
3194
0
    UINT64_C(4088791744), // VQMOVNuv4i16
3195
0
    UINT64_C(4088529600), // VQMOVNuv8i8
3196
0
    UINT64_C(4088399808), // VQNEGv16i8
3197
0
    UINT64_C(4088924032), // VQNEGv2i32
3198
0
    UINT64_C(4088661888), // VQNEGv4i16
3199
0
    UINT64_C(4088924096), // VQNEGv4i32
3200
0
    UINT64_C(4088661952), // VQNEGv8i16
3201
0
    UINT64_C(4088399744), // VQNEGv8i8
3202
0
    UINT64_C(4070575680), // VQRDMLAHslv2i32
3203
0
    UINT64_C(4069527104), // VQRDMLAHslv4i16
3204
0
    UINT64_C(4087352896), // VQRDMLAHslv4i32
3205
0
    UINT64_C(4086304320), // VQRDMLAHslv8i16
3206
0
    UINT64_C(4078963472), // VQRDMLAHv2i32
3207
0
    UINT64_C(4077914896), // VQRDMLAHv4i16
3208
0
    UINT64_C(4078963536), // VQRDMLAHv4i32
3209
0
    UINT64_C(4077914960), // VQRDMLAHv8i16
3210
0
    UINT64_C(4070575936), // VQRDMLSHslv2i32
3211
0
    UINT64_C(4069527360), // VQRDMLSHslv4i16
3212
0
    UINT64_C(4087353152), // VQRDMLSHslv4i32
3213
0
    UINT64_C(4086304576), // VQRDMLSHslv8i16
3214
0
    UINT64_C(4078963728), // VQRDMLSHv2i32
3215
0
    UINT64_C(4077915152), // VQRDMLSHv4i16
3216
0
    UINT64_C(4078963792), // VQRDMLSHv4i32
3217
0
    UINT64_C(4077915216), // VQRDMLSHv8i16
3218
0
    UINT64_C(4070575424), // VQRDMULHslv2i32
3219
0
    UINT64_C(4069526848), // VQRDMULHslv4i16
3220
0
    UINT64_C(4087352640), // VQRDMULHslv4i32
3221
0
    UINT64_C(4086304064), // VQRDMULHslv8i16
3222
0
    UINT64_C(4078963456), // VQRDMULHv2i32
3223
0
    UINT64_C(4077914880), // VQRDMULHv4i16
3224
0
    UINT64_C(4078963520), // VQRDMULHv4i32
3225
0
    UINT64_C(4077914944), // VQRDMULHv8i16
3226
0
    UINT64_C(4060087632), // VQRSHLsv16i8
3227
0
    UINT64_C(4063233296), // VQRSHLsv1i64
3228
0
    UINT64_C(4062184720), // VQRSHLsv2i32
3229
0
    UINT64_C(4063233360), // VQRSHLsv2i64
3230
0
    UINT64_C(4061136144), // VQRSHLsv4i16
3231
0
    UINT64_C(4062184784), // VQRSHLsv4i32
3232
0
    UINT64_C(4061136208), // VQRSHLsv8i16
3233
0
    UINT64_C(4060087568), // VQRSHLsv8i8
3234
0
    UINT64_C(4076864848), // VQRSHLuv16i8
3235
0
    UINT64_C(4080010512), // VQRSHLuv1i64
3236
0
    UINT64_C(4078961936), // VQRSHLuv2i32
3237
0
    UINT64_C(4080010576), // VQRSHLuv2i64
3238
0
    UINT64_C(4077913360), // VQRSHLuv4i16
3239
0
    UINT64_C(4078962000), // VQRSHLuv4i32
3240
0
    UINT64_C(4077913424), // VQRSHLuv8i16
3241
0
    UINT64_C(4076864784), // VQRSHLuv8i8
3242
0
    UINT64_C(4070574416), // VQRSHRNsv2i32
3243
0
    UINT64_C(4069525840), // VQRSHRNsv4i16
3244
0
    UINT64_C(4069001552), // VQRSHRNsv8i8
3245
0
    UINT64_C(4087351632), // VQRSHRNuv2i32
3246
0
    UINT64_C(4086303056), // VQRSHRNuv4i16
3247
0
    UINT64_C(4085778768), // VQRSHRNuv8i8
3248
0
    UINT64_C(4087351376), // VQRSHRUNv2i32
3249
0
    UINT64_C(4086302800), // VQRSHRUNv4i16
3250
0
    UINT64_C(4085778512), // VQRSHRUNv8i8
3251
0
    UINT64_C(4069001040), // VQSHLsiv16i8
3252
0
    UINT64_C(4068476816), // VQSHLsiv1i64
3253
0
    UINT64_C(4070573840), // VQSHLsiv2i32
3254
0
    UINT64_C(4068476880), // VQSHLsiv2i64
3255
0
    UINT64_C(4069525264), // VQSHLsiv4i16
3256
0
    UINT64_C(4070573904), // VQSHLsiv4i32
3257
0
    UINT64_C(4069525328), // VQSHLsiv8i16
3258
0
    UINT64_C(4069000976), // VQSHLsiv8i8
3259
0
    UINT64_C(4085778000), // VQSHLsuv16i8
3260
0
    UINT64_C(4085253776), // VQSHLsuv1i64
3261
0
    UINT64_C(4087350800), // VQSHLsuv2i32
3262
0
    UINT64_C(4085253840), // VQSHLsuv2i64
3263
0
    UINT64_C(4086302224), // VQSHLsuv4i16
3264
0
    UINT64_C(4087350864), // VQSHLsuv4i32
3265
0
    UINT64_C(4086302288), // VQSHLsuv8i16
3266
0
    UINT64_C(4085777936), // VQSHLsuv8i8
3267
0
    UINT64_C(4060087376), // VQSHLsv16i8
3268
0
    UINT64_C(4063233040), // VQSHLsv1i64
3269
0
    UINT64_C(4062184464), // VQSHLsv2i32
3270
0
    UINT64_C(4063233104), // VQSHLsv2i64
3271
0
    UINT64_C(4061135888), // VQSHLsv4i16
3272
0
    UINT64_C(4062184528), // VQSHLsv4i32
3273
0
    UINT64_C(4061135952), // VQSHLsv8i16
3274
0
    UINT64_C(4060087312), // VQSHLsv8i8
3275
0
    UINT64_C(4085778256), // VQSHLuiv16i8
3276
0
    UINT64_C(4085254032), // VQSHLuiv1i64
3277
0
    UINT64_C(4087351056), // VQSHLuiv2i32
3278
0
    UINT64_C(4085254096), // VQSHLuiv2i64
3279
0
    UINT64_C(4086302480), // VQSHLuiv4i16
3280
0
    UINT64_C(4087351120), // VQSHLuiv4i32
3281
0
    UINT64_C(4086302544), // VQSHLuiv8i16
3282
0
    UINT64_C(4085778192), // VQSHLuiv8i8
3283
0
    UINT64_C(4076864592), // VQSHLuv16i8
3284
0
    UINT64_C(4080010256), // VQSHLuv1i64
3285
0
    UINT64_C(4078961680), // VQSHLuv2i32
3286
0
    UINT64_C(4080010320), // VQSHLuv2i64
3287
0
    UINT64_C(4077913104), // VQSHLuv4i16
3288
0
    UINT64_C(4078961744), // VQSHLuv4i32
3289
0
    UINT64_C(4077913168), // VQSHLuv8i16
3290
0
    UINT64_C(4076864528), // VQSHLuv8i8
3291
0
    UINT64_C(4070574352), // VQSHRNsv2i32
3292
0
    UINT64_C(4069525776), // VQSHRNsv4i16
3293
0
    UINT64_C(4069001488), // VQSHRNsv8i8
3294
0
    UINT64_C(4087351568), // VQSHRNuv2i32
3295
0
    UINT64_C(4086302992), // VQSHRNuv4i16
3296
0
    UINT64_C(4085778704), // VQSHRNuv8i8
3297
0
    UINT64_C(4087351312), // VQSHRUNv2i32
3298
0
    UINT64_C(4086302736), // VQSHRUNv4i16
3299
0
    UINT64_C(4085778448), // VQSHRUNv8i8
3300
0
    UINT64_C(4060086864), // VQSUBsv16i8
3301
0
    UINT64_C(4063232528), // VQSUBsv1i64
3302
0
    UINT64_C(4062183952), // VQSUBsv2i32
3303
0
    UINT64_C(4063232592), // VQSUBsv2i64
3304
0
    UINT64_C(4061135376), // VQSUBsv4i16
3305
0
    UINT64_C(4062184016), // VQSUBsv4i32
3306
0
    UINT64_C(4061135440), // VQSUBsv8i16
3307
0
    UINT64_C(4060086800), // VQSUBsv8i8
3308
0
    UINT64_C(4076864080), // VQSUBuv16i8
3309
0
    UINT64_C(4080009744), // VQSUBuv1i64
3310
0
    UINT64_C(4078961168), // VQSUBuv2i32
3311
0
    UINT64_C(4080009808), // VQSUBuv2i64
3312
0
    UINT64_C(4077912592), // VQSUBuv4i16
3313
0
    UINT64_C(4078961232), // VQSUBuv4i32
3314
0
    UINT64_C(4077912656), // VQSUBuv8i16
3315
0
    UINT64_C(4076864016), // VQSUBuv8i8
3316
0
    UINT64_C(4087350272), // VRADDHNv2i32
3317
0
    UINT64_C(4086301696), // VRADDHNv4i16
3318
0
    UINT64_C(4085253120), // VRADDHNv8i8
3319
0
    UINT64_C(4089119744), // VRECPEd
3320
0
    UINT64_C(4089120000), // VRECPEfd
3321
0
    UINT64_C(4089120064), // VRECPEfq
3322
0
    UINT64_C(4088857856), // VRECPEhd
3323
0
    UINT64_C(4088857920), // VRECPEhq
3324
0
    UINT64_C(4089119808), // VRECPEq
3325
0
    UINT64_C(4060090128), // VRECPSfd
3326
0
    UINT64_C(4060090192), // VRECPSfq
3327
0
    UINT64_C(4061138704), // VRECPShd
3328
0
    UINT64_C(4061138768), // VRECPShq
3329
0
    UINT64_C(4088398080), // VREV16d8
3330
0
    UINT64_C(4088398144), // VREV16q8
3331
0
    UINT64_C(4088660096), // VREV32d16
3332
0
    UINT64_C(4088397952), // VREV32d8
3333
0
    UINT64_C(4088660160), // VREV32q16
3334
0
    UINT64_C(4088398016), // VREV32q8
3335
0
    UINT64_C(4088659968), // VREV64d16
3336
0
    UINT64_C(4088922112), // VREV64d32
3337
0
    UINT64_C(4088397824), // VREV64d8
3338
0
    UINT64_C(4088660032), // VREV64q16
3339
0
    UINT64_C(4088922176), // VREV64q32
3340
0
    UINT64_C(4088397888), // VREV64q8
3341
0
    UINT64_C(4060086592), // VRHADDsv16i8
3342
0
    UINT64_C(4062183680), // VRHADDsv2i32
3343
0
    UINT64_C(4061135104), // VRHADDsv4i16
3344
0
    UINT64_C(4062183744), // VRHADDsv4i32
3345
0
    UINT64_C(4061135168), // VRHADDsv8i16
3346
0
    UINT64_C(4060086528), // VRHADDsv8i8
3347
0
    UINT64_C(4076863808), // VRHADDuv16i8
3348
0
    UINT64_C(4078960896), // VRHADDuv2i32
3349
0
    UINT64_C(4077912320), // VRHADDuv4i16
3350
0
    UINT64_C(4078960960), // VRHADDuv4i32
3351
0
    UINT64_C(4077912384), // VRHADDuv8i16
3352
0
    UINT64_C(4076863744), // VRHADDuv8i8
3353
0
    UINT64_C(4273474368), // VRINTAD
3354
0
    UINT64_C(4273473856), // VRINTAH
3355
0
    UINT64_C(4089054464), // VRINTANDf
3356
0
    UINT64_C(4088792320), // VRINTANDh
3357
0
    UINT64_C(4089054528), // VRINTANQf
3358
0
    UINT64_C(4088792384), // VRINTANQh
3359
0
    UINT64_C(4273474112), // VRINTAS
3360
0
    UINT64_C(4273670976), // VRINTMD
3361
0
    UINT64_C(4273670464), // VRINTMH
3362
0
    UINT64_C(4089054848), // VRINTMNDf
3363
0
    UINT64_C(4088792704), // VRINTMNDh
3364
0
    UINT64_C(4089054912), // VRINTMNQf
3365
0
    UINT64_C(4088792768), // VRINTMNQh
3366
0
    UINT64_C(4273670720), // VRINTMS
3367
0
    UINT64_C(4273539904), // VRINTND
3368
0
    UINT64_C(4273539392), // VRINTNH
3369
0
    UINT64_C(4089054208), // VRINTNNDf
3370
0
    UINT64_C(4088792064), // VRINTNNDh
3371
0
    UINT64_C(4089054272), // VRINTNNQf
3372
0
    UINT64_C(4088792128), // VRINTNNQh
3373
0
    UINT64_C(4273539648), // VRINTNS
3374
0
    UINT64_C(4273605440), // VRINTPD
3375
0
    UINT64_C(4273604928), // VRINTPH
3376
0
    UINT64_C(4089055104), // VRINTPNDf
3377
0
    UINT64_C(4088792960), // VRINTPNDh
3378
0
    UINT64_C(4089055168), // VRINTPNQf
3379
0
    UINT64_C(4088793024), // VRINTPNQh
3380
0
    UINT64_C(4273605184), // VRINTPS
3381
0
    UINT64_C(246811456),  // VRINTRD
3382
0
    UINT64_C(246810944),  // VRINTRH
3383
0
    UINT64_C(246811200),  // VRINTRS
3384
0
    UINT64_C(246876992),  // VRINTXD
3385
0
    UINT64_C(246876480),  // VRINTXH
3386
0
    UINT64_C(4089054336), // VRINTXNDf
3387
0
    UINT64_C(4088792192), // VRINTXNDh
3388
0
    UINT64_C(4089054400), // VRINTXNQf
3389
0
    UINT64_C(4088792256), // VRINTXNQh
3390
0
    UINT64_C(246876736),  // VRINTXS
3391
0
    UINT64_C(246811584),  // VRINTZD
3392
0
    UINT64_C(246811072),  // VRINTZH
3393
0
    UINT64_C(4089054592), // VRINTZNDf
3394
0
    UINT64_C(4088792448), // VRINTZNDh
3395
0
    UINT64_C(4089054656), // VRINTZNQf
3396
0
    UINT64_C(4088792512), // VRINTZNQh
3397
0
    UINT64_C(246811328),  // VRINTZS
3398
0
    UINT64_C(4060087616), // VRSHLsv16i8
3399
0
    UINT64_C(4063233280), // VRSHLsv1i64
3400
0
    UINT64_C(4062184704), // VRSHLsv2i32
3401
0
    UINT64_C(4063233344), // VRSHLsv2i64
3402
0
    UINT64_C(4061136128), // VRSHLsv4i16
3403
0
    UINT64_C(4062184768), // VRSHLsv4i32
3404
0
    UINT64_C(4061136192), // VRSHLsv8i16
3405
0
    UINT64_C(4060087552), // VRSHLsv8i8
3406
0
    UINT64_C(4076864832), // VRSHLuv16i8
3407
0
    UINT64_C(4080010496), // VRSHLuv1i64
3408
0
    UINT64_C(4078961920), // VRSHLuv2i32
3409
0
    UINT64_C(4080010560), // VRSHLuv2i64
3410
0
    UINT64_C(4077913344), // VRSHLuv4i16
3411
0
    UINT64_C(4078961984), // VRSHLuv4i32
3412
0
    UINT64_C(4077913408), // VRSHLuv8i16
3413
0
    UINT64_C(4076864768), // VRSHLuv8i8
3414
0
    UINT64_C(4070574160), // VRSHRNv2i32
3415
0
    UINT64_C(4069525584), // VRSHRNv4i16
3416
0
    UINT64_C(4069001296), // VRSHRNv8i8
3417
0
    UINT64_C(4068999760), // VRSHRsv16i8
3418
0
    UINT64_C(4068475536), // VRSHRsv1i64
3419
0
    UINT64_C(4070572560), // VRSHRsv2i32
3420
0
    UINT64_C(4068475600), // VRSHRsv2i64
3421
0
    UINT64_C(4069523984), // VRSHRsv4i16
3422
0
    UINT64_C(4070572624), // VRSHRsv4i32
3423
0
    UINT64_C(4069524048), // VRSHRsv8i16
3424
0
    UINT64_C(4068999696), // VRSHRsv8i8
3425
0
    UINT64_C(4085776976), // VRSHRuv16i8
3426
0
    UINT64_C(4085252752), // VRSHRuv1i64
3427
0
    UINT64_C(4087349776), // VRSHRuv2i32
3428
0
    UINT64_C(4085252816), // VRSHRuv2i64
3429
0
    UINT64_C(4086301200), // VRSHRuv4i16
3430
0
    UINT64_C(4087349840), // VRSHRuv4i32
3431
0
    UINT64_C(4086301264), // VRSHRuv8i16
3432
0
    UINT64_C(4085776912), // VRSHRuv8i8
3433
0
    UINT64_C(4089119872), // VRSQRTEd
3434
0
    UINT64_C(4089120128), // VRSQRTEfd
3435
0
    UINT64_C(4089120192), // VRSQRTEfq
3436
0
    UINT64_C(4088857984), // VRSQRTEhd
3437
0
    UINT64_C(4088858048), // VRSQRTEhq
3438
0
    UINT64_C(4089119936), // VRSQRTEq
3439
0
    UINT64_C(4062187280), // VRSQRTSfd
3440
0
    UINT64_C(4062187344), // VRSQRTSfq
3441
0
    UINT64_C(4063235856), // VRSQRTShd
3442
0
    UINT64_C(4063235920), // VRSQRTShq
3443
0
    UINT64_C(4069000016), // VRSRAsv16i8
3444
0
    UINT64_C(4068475792), // VRSRAsv1i64
3445
0
    UINT64_C(4070572816), // VRSRAsv2i32
3446
0
    UINT64_C(4068475856), // VRSRAsv2i64
3447
0
    UINT64_C(4069524240), // VRSRAsv4i16
3448
0
    UINT64_C(4070572880), // VRSRAsv4i32
3449
0
    UINT64_C(4069524304), // VRSRAsv8i16
3450
0
    UINT64_C(4068999952), // VRSRAsv8i8
3451
0
    UINT64_C(4085777232), // VRSRAuv16i8
3452
0
    UINT64_C(4085253008), // VRSRAuv1i64
3453
0
    UINT64_C(4087350032), // VRSRAuv2i32
3454
0
    UINT64_C(4085253072), // VRSRAuv2i64
3455
0
    UINT64_C(4086301456), // VRSRAuv4i16
3456
0
    UINT64_C(4087350096), // VRSRAuv4i32
3457
0
    UINT64_C(4086301520), // VRSRAuv8i16
3458
0
    UINT64_C(4085777168), // VRSRAuv8i8
3459
0
    UINT64_C(4087350784), // VRSUBHNv2i32
3460
0
    UINT64_C(4086302208), // VRSUBHNv4i16
3461
0
    UINT64_C(4085253632), // VRSUBHNv8i8
3462
0
    UINT64_C(3969846016), // VSCCLRMD
3463
0
    UINT64_C(3969845760), // VSCCLRMS
3464
0
    UINT64_C(4229958912), // VSDOTD
3465
0
    UINT64_C(4263513344), // VSDOTDI
3466
0
    UINT64_C(4229958976), // VSDOTQ
3467
0
    UINT64_C(4263513408), // VSDOTQI
3468
0
    UINT64_C(4261415680), // VSELEQD
3469
0
    UINT64_C(4261415168), // VSELEQH
3470
0
    UINT64_C(4261415424), // VSELEQS
3471
0
    UINT64_C(4263512832), // VSELGED
3472
0
    UINT64_C(4263512320), // VSELGEH
3473
0
    UINT64_C(4263512576), // VSELGES
3474
0
    UINT64_C(4264561408), // VSELGTD
3475
0
    UINT64_C(4264560896), // VSELGTH
3476
0
    UINT64_C(4264561152), // VSELGTS
3477
0
    UINT64_C(4262464256), // VSELVSD
3478
0
    UINT64_C(4262463744), // VSELVSH
3479
0
    UINT64_C(4262464000), // VSELVSS
3480
0
    UINT64_C(234883888),  // VSETLNi16
3481
0
    UINT64_C(234883856),  // VSETLNi32
3482
0
    UINT64_C(239078160),  // VSETLNi8
3483
0
    UINT64_C(4088791808), // VSHLLi16
3484
0
    UINT64_C(4089053952), // VSHLLi32
3485
0
    UINT64_C(4088529664), // VSHLLi8
3486
0
    UINT64_C(4070574608), // VSHLLsv2i64
3487
0
    UINT64_C(4069526032), // VSHLLsv4i32
3488
0
    UINT64_C(4069001744), // VSHLLsv8i16
3489
0
    UINT64_C(4087351824), // VSHLLuv2i64
3490
0
    UINT64_C(4086303248), // VSHLLuv4i32
3491
0
    UINT64_C(4085778960), // VSHLLuv8i16
3492
0
    UINT64_C(4069000528), // VSHLiv16i8
3493
0
    UINT64_C(4068476304), // VSHLiv1i64
3494
0
    UINT64_C(4070573328), // VSHLiv2i32
3495
0
    UINT64_C(4068476368), // VSHLiv2i64
3496
0
    UINT64_C(4069524752), // VSHLiv4i16
3497
0
    UINT64_C(4070573392), // VSHLiv4i32
3498
0
    UINT64_C(4069524816), // VSHLiv8i16
3499
0
    UINT64_C(4069000464), // VSHLiv8i8
3500
0
    UINT64_C(4060087360), // VSHLsv16i8
3501
0
    UINT64_C(4063233024), // VSHLsv1i64
3502
0
    UINT64_C(4062184448), // VSHLsv2i32
3503
0
    UINT64_C(4063233088), // VSHLsv2i64
3504
0
    UINT64_C(4061135872), // VSHLsv4i16
3505
0
    UINT64_C(4062184512), // VSHLsv4i32
3506
0
    UINT64_C(4061135936), // VSHLsv8i16
3507
0
    UINT64_C(4060087296), // VSHLsv8i8
3508
0
    UINT64_C(4076864576), // VSHLuv16i8
3509
0
    UINT64_C(4080010240), // VSHLuv1i64
3510
0
    UINT64_C(4078961664), // VSHLuv2i32
3511
0
    UINT64_C(4080010304), // VSHLuv2i64
3512
0
    UINT64_C(4077913088), // VSHLuv4i16
3513
0
    UINT64_C(4078961728), // VSHLuv4i32
3514
0
    UINT64_C(4077913152), // VSHLuv8i16
3515
0
    UINT64_C(4076864512), // VSHLuv8i8
3516
0
    UINT64_C(4070574096), // VSHRNv2i32
3517
0
    UINT64_C(4069525520), // VSHRNv4i16
3518
0
    UINT64_C(4069001232), // VSHRNv8i8
3519
0
    UINT64_C(4068999248), // VSHRsv16i8
3520
0
    UINT64_C(4068475024), // VSHRsv1i64
3521
0
    UINT64_C(4070572048), // VSHRsv2i32
3522
0
    UINT64_C(4068475088), // VSHRsv2i64
3523
0
    UINT64_C(4069523472), // VSHRsv4i16
3524
0
    UINT64_C(4070572112), // VSHRsv4i32
3525
0
    UINT64_C(4069523536), // VSHRsv8i16
3526
0
    UINT64_C(4068999184), // VSHRsv8i8
3527
0
    UINT64_C(4085776464), // VSHRuv16i8
3528
0
    UINT64_C(4085252240), // VSHRuv1i64
3529
0
    UINT64_C(4087349264), // VSHRuv2i32
3530
0
    UINT64_C(4085252304), // VSHRuv2i64
3531
0
    UINT64_C(4086300688), // VSHRuv4i16
3532
0
    UINT64_C(4087349328), // VSHRuv4i32
3533
0
    UINT64_C(4086300752), // VSHRuv8i16
3534
0
    UINT64_C(4085776400), // VSHRuv8i8
3535
0
    UINT64_C(247073600),  // VSHTOD
3536
0
    UINT64_C(247073088),  // VSHTOH
3537
0
    UINT64_C(247073344),  // VSHTOS
3538
0
    UINT64_C(246942656),  // VSITOD
3539
0
    UINT64_C(246942144),  // VSITOH
3540
0
    UINT64_C(246942400),  // VSITOS
3541
0
    UINT64_C(4085777744), // VSLIv16i8
3542
0
    UINT64_C(4085253520), // VSLIv1i64
3543
0
    UINT64_C(4087350544), // VSLIv2i32
3544
0
    UINT64_C(4085253584), // VSLIv2i64
3545
0
    UINT64_C(4086301968), // VSLIv4i16
3546
0
    UINT64_C(4087350608), // VSLIv4i32
3547
0
    UINT64_C(4086302032), // VSLIv8i16
3548
0
    UINT64_C(4085777680), // VSLIv8i8
3549
0
    UINT64_C(247073728),  // VSLTOD
3550
0
    UINT64_C(247073216),  // VSLTOH
3551
0
    UINT64_C(247073472),  // VSLTOS
3552
0
    UINT64_C(4229958720), // VSMMLA
3553
0
    UINT64_C(246483904),  // VSQRTD
3554
0
    UINT64_C(246483392),  // VSQRTH
3555
0
    UINT64_C(246483648),  // VSQRTS
3556
0
    UINT64_C(4068999504), // VSRAsv16i8
3557
0
    UINT64_C(4068475280), // VSRAsv1i64
3558
0
    UINT64_C(4070572304), // VSRAsv2i32
3559
0
    UINT64_C(4068475344), // VSRAsv2i64
3560
0
    UINT64_C(4069523728), // VSRAsv4i16
3561
0
    UINT64_C(4070572368), // VSRAsv4i32
3562
0
    UINT64_C(4069523792), // VSRAsv8i16
3563
0
    UINT64_C(4068999440), // VSRAsv8i8
3564
0
    UINT64_C(4085776720), // VSRAuv16i8
3565
0
    UINT64_C(4085252496), // VSRAuv1i64
3566
0
    UINT64_C(4087349520), // VSRAuv2i32
3567
0
    UINT64_C(4085252560), // VSRAuv2i64
3568
0
    UINT64_C(4086300944), // VSRAuv4i16
3569
0
    UINT64_C(4087349584), // VSRAuv4i32
3570
0
    UINT64_C(4086301008), // VSRAuv8i16
3571
0
    UINT64_C(4085776656), // VSRAuv8i8
3572
0
    UINT64_C(4085777488), // VSRIv16i8
3573
0
    UINT64_C(4085253264), // VSRIv1i64
3574
0
    UINT64_C(4087350288), // VSRIv2i32
3575
0
    UINT64_C(4085253328), // VSRIv2i64
3576
0
    UINT64_C(4086301712), // VSRIv4i16
3577
0
    UINT64_C(4087350352), // VSRIv4i32
3578
0
    UINT64_C(4086301776), // VSRIv8i16
3579
0
    UINT64_C(4085777424), // VSRIv8i8
3580
0
    UINT64_C(4102030351), // VST1LNd16
3581
0
    UINT64_C(4102030336), // VST1LNd16_UPD
3582
0
    UINT64_C(4102031375), // VST1LNd32
3583
0
    UINT64_C(4102031360), // VST1LNd32_UPD
3584
0
    UINT64_C(4102029327), // VST1LNd8
3585
0
    UINT64_C(4102029312), // VST1LNd8_UPD
3586
0
    UINT64_C(0),  // VST1LNq16Pseudo
3587
0
    UINT64_C(0),  // VST1LNq16Pseudo_UPD
3588
0
    UINT64_C(0),  // VST1LNq32Pseudo
3589
0
    UINT64_C(0),  // VST1LNq32Pseudo_UPD
3590
0
    UINT64_C(0),  // VST1LNq8Pseudo
3591
0
    UINT64_C(0),  // VST1LNq8Pseudo_UPD
3592
0
    UINT64_C(4093642575), // VST1d16
3593
0
    UINT64_C(4093641295), // VST1d16Q
3594
0
    UINT64_C(0),  // VST1d16QPseudo
3595
0
    UINT64_C(0),  // VST1d16QPseudoWB_fixed
3596
0
    UINT64_C(0),  // VST1d16QPseudoWB_register
3597
0
    UINT64_C(4093641293), // VST1d16Qwb_fixed
3598
0
    UINT64_C(4093641280), // VST1d16Qwb_register
3599
0
    UINT64_C(4093642319), // VST1d16T
3600
0
    UINT64_C(0),  // VST1d16TPseudo
3601
0
    UINT64_C(0),  // VST1d16TPseudoWB_fixed
3602
0
    UINT64_C(0),  // VST1d16TPseudoWB_register
3603
0
    UINT64_C(4093642317), // VST1d16Twb_fixed
3604
0
    UINT64_C(4093642304), // VST1d16Twb_register
3605
0
    UINT64_C(4093642573), // VST1d16wb_fixed
3606
0
    UINT64_C(4093642560), // VST1d16wb_register
3607
0
    UINT64_C(4093642639), // VST1d32
3608
0
    UINT64_C(4093641359), // VST1d32Q
3609
0
    UINT64_C(0),  // VST1d32QPseudo
3610
0
    UINT64_C(0),  // VST1d32QPseudoWB_fixed
3611
0
    UINT64_C(0),  // VST1d32QPseudoWB_register
3612
0
    UINT64_C(4093641357), // VST1d32Qwb_fixed
3613
0
    UINT64_C(4093641344), // VST1d32Qwb_register
3614
0
    UINT64_C(4093642383), // VST1d32T
3615
0
    UINT64_C(0),  // VST1d32TPseudo
3616
0
    UINT64_C(0),  // VST1d32TPseudoWB_fixed
3617
0
    UINT64_C(0),  // VST1d32TPseudoWB_register
3618
0
    UINT64_C(4093642381), // VST1d32Twb_fixed
3619
0
    UINT64_C(4093642368), // VST1d32Twb_register
3620
0
    UINT64_C(4093642637), // VST1d32wb_fixed
3621
0
    UINT64_C(4093642624), // VST1d32wb_register
3622
0
    UINT64_C(4093642703), // VST1d64
3623
0
    UINT64_C(4093641423), // VST1d64Q
3624
0
    UINT64_C(0),  // VST1d64QPseudo
3625
0
    UINT64_C(0),  // VST1d64QPseudoWB_fixed
3626
0
    UINT64_C(0),  // VST1d64QPseudoWB_register
3627
0
    UINT64_C(4093641421), // VST1d64Qwb_fixed
3628
0
    UINT64_C(4093641408), // VST1d64Qwb_register
3629
0
    UINT64_C(4093642447), // VST1d64T
3630
0
    UINT64_C(0),  // VST1d64TPseudo
3631
0
    UINT64_C(0),  // VST1d64TPseudoWB_fixed
3632
0
    UINT64_C(0),  // VST1d64TPseudoWB_register
3633
0
    UINT64_C(4093642445), // VST1d64Twb_fixed
3634
0
    UINT64_C(4093642432), // VST1d64Twb_register
3635
0
    UINT64_C(4093642701), // VST1d64wb_fixed
3636
0
    UINT64_C(4093642688), // VST1d64wb_register
3637
0
    UINT64_C(4093642511), // VST1d8
3638
0
    UINT64_C(4093641231), // VST1d8Q
3639
0
    UINT64_C(0),  // VST1d8QPseudo
3640
0
    UINT64_C(0),  // VST1d8QPseudoWB_fixed
3641
0
    UINT64_C(0),  // VST1d8QPseudoWB_register
3642
0
    UINT64_C(4093641229), // VST1d8Qwb_fixed
3643
0
    UINT64_C(4093641216), // VST1d8Qwb_register
3644
0
    UINT64_C(4093642255), // VST1d8T
3645
0
    UINT64_C(0),  // VST1d8TPseudo
3646
0
    UINT64_C(0),  // VST1d8TPseudoWB_fixed
3647
0
    UINT64_C(0),  // VST1d8TPseudoWB_register
3648
0
    UINT64_C(4093642253), // VST1d8Twb_fixed
3649
0
    UINT64_C(4093642240), // VST1d8Twb_register
3650
0
    UINT64_C(4093642509), // VST1d8wb_fixed
3651
0
    UINT64_C(4093642496), // VST1d8wb_register
3652
0
    UINT64_C(4093643343), // VST1q16
3653
0
    UINT64_C(0),  // VST1q16HighQPseudo
3654
0
    UINT64_C(0),  // VST1q16HighQPseudo_UPD
3655
0
    UINT64_C(0),  // VST1q16HighTPseudo
3656
0
    UINT64_C(0),  // VST1q16HighTPseudo_UPD
3657
0
    UINT64_C(0),  // VST1q16LowQPseudo_UPD
3658
0
    UINT64_C(0),  // VST1q16LowTPseudo_UPD
3659
0
    UINT64_C(4093643341), // VST1q16wb_fixed
3660
0
    UINT64_C(4093643328), // VST1q16wb_register
3661
0
    UINT64_C(4093643407), // VST1q32
3662
0
    UINT64_C(0),  // VST1q32HighQPseudo
3663
0
    UINT64_C(0),  // VST1q32HighQPseudo_UPD
3664
0
    UINT64_C(0),  // VST1q32HighTPseudo
3665
0
    UINT64_C(0),  // VST1q32HighTPseudo_UPD
3666
0
    UINT64_C(0),  // VST1q32LowQPseudo_UPD
3667
0
    UINT64_C(0),  // VST1q32LowTPseudo_UPD
3668
0
    UINT64_C(4093643405), // VST1q32wb_fixed
3669
0
    UINT64_C(4093643392), // VST1q32wb_register
3670
0
    UINT64_C(4093643471), // VST1q64
3671
0
    UINT64_C(0),  // VST1q64HighQPseudo
3672
0
    UINT64_C(0),  // VST1q64HighQPseudo_UPD
3673
0
    UINT64_C(0),  // VST1q64HighTPseudo
3674
0
    UINT64_C(0),  // VST1q64HighTPseudo_UPD
3675
0
    UINT64_C(0),  // VST1q64LowQPseudo_UPD
3676
0
    UINT64_C(0),  // VST1q64LowTPseudo_UPD
3677
0
    UINT64_C(4093643469), // VST1q64wb_fixed
3678
0
    UINT64_C(4093643456), // VST1q64wb_register
3679
0
    UINT64_C(4093643279), // VST1q8
3680
0
    UINT64_C(0),  // VST1q8HighQPseudo
3681
0
    UINT64_C(0),  // VST1q8HighQPseudo_UPD
3682
0
    UINT64_C(0),  // VST1q8HighTPseudo
3683
0
    UINT64_C(0),  // VST1q8HighTPseudo_UPD
3684
0
    UINT64_C(0),  // VST1q8LowQPseudo_UPD
3685
0
    UINT64_C(0),  // VST1q8LowTPseudo_UPD
3686
0
    UINT64_C(4093643277), // VST1q8wb_fixed
3687
0
    UINT64_C(4093643264), // VST1q8wb_register
3688
0
    UINT64_C(4102030607), // VST2LNd16
3689
0
    UINT64_C(0),  // VST2LNd16Pseudo
3690
0
    UINT64_C(0),  // VST2LNd16Pseudo_UPD
3691
0
    UINT64_C(4102030592), // VST2LNd16_UPD
3692
0
    UINT64_C(4102031631), // VST2LNd32
3693
0
    UINT64_C(0),  // VST2LNd32Pseudo
3694
0
    UINT64_C(0),  // VST2LNd32Pseudo_UPD
3695
0
    UINT64_C(4102031616), // VST2LNd32_UPD
3696
0
    UINT64_C(4102029583), // VST2LNd8
3697
0
    UINT64_C(0),  // VST2LNd8Pseudo
3698
0
    UINT64_C(0),  // VST2LNd8Pseudo_UPD
3699
0
    UINT64_C(4102029568), // VST2LNd8_UPD
3700
0
    UINT64_C(4102030639), // VST2LNq16
3701
0
    UINT64_C(0),  // VST2LNq16Pseudo
3702
0
    UINT64_C(0),  // VST2LNq16Pseudo_UPD
3703
0
    UINT64_C(4102030624), // VST2LNq16_UPD
3704
0
    UINT64_C(4102031695), // VST2LNq32
3705
0
    UINT64_C(0),  // VST2LNq32Pseudo
3706
0
    UINT64_C(0),  // VST2LNq32Pseudo_UPD
3707
0
    UINT64_C(4102031680), // VST2LNq32_UPD
3708
0
    UINT64_C(4093643087), // VST2b16
3709
0
    UINT64_C(4093643085), // VST2b16wb_fixed
3710
0
    UINT64_C(4093643072), // VST2b16wb_register
3711
0
    UINT64_C(4093643151), // VST2b32
3712
0
    UINT64_C(4093643149), // VST2b32wb_fixed
3713
0
    UINT64_C(4093643136), // VST2b32wb_register
3714
0
    UINT64_C(4093643023), // VST2b8
3715
0
    UINT64_C(4093643021), // VST2b8wb_fixed
3716
0
    UINT64_C(4093643008), // VST2b8wb_register
3717
0
    UINT64_C(4093642831), // VST2d16
3718
0
    UINT64_C(4093642829), // VST2d16wb_fixed
3719
0
    UINT64_C(4093642816), // VST2d16wb_register
3720
0
    UINT64_C(4093642895), // VST2d32
3721
0
    UINT64_C(4093642893), // VST2d32wb_fixed
3722
0
    UINT64_C(4093642880), // VST2d32wb_register
3723
0
    UINT64_C(4093642767), // VST2d8
3724
0
    UINT64_C(4093642765), // VST2d8wb_fixed
3725
0
    UINT64_C(4093642752), // VST2d8wb_register
3726
0
    UINT64_C(4093641551), // VST2q16
3727
0
    UINT64_C(0),  // VST2q16Pseudo
3728
0
    UINT64_C(0),  // VST2q16PseudoWB_fixed
3729
0
    UINT64_C(0),  // VST2q16PseudoWB_register
3730
0
    UINT64_C(4093641549), // VST2q16wb_fixed
3731
0
    UINT64_C(4093641536), // VST2q16wb_register
3732
0
    UINT64_C(4093641615), // VST2q32
3733
0
    UINT64_C(0),  // VST2q32Pseudo
3734
0
    UINT64_C(0),  // VST2q32PseudoWB_fixed
3735
0
    UINT64_C(0),  // VST2q32PseudoWB_register
3736
0
    UINT64_C(4093641613), // VST2q32wb_fixed
3737
0
    UINT64_C(4093641600), // VST2q32wb_register
3738
0
    UINT64_C(4093641487), // VST2q8
3739
0
    UINT64_C(0),  // VST2q8Pseudo
3740
0
    UINT64_C(0),  // VST2q8PseudoWB_fixed
3741
0
    UINT64_C(0),  // VST2q8PseudoWB_register
3742
0
    UINT64_C(4093641485), // VST2q8wb_fixed
3743
0
    UINT64_C(4093641472), // VST2q8wb_register
3744
0
    UINT64_C(4102030863), // VST3LNd16
3745
0
    UINT64_C(0),  // VST3LNd16Pseudo
3746
0
    UINT64_C(0),  // VST3LNd16Pseudo_UPD
3747
0
    UINT64_C(4102030848), // VST3LNd16_UPD
3748
0
    UINT64_C(4102031887), // VST3LNd32
3749
0
    UINT64_C(0),  // VST3LNd32Pseudo
3750
0
    UINT64_C(0),  // VST3LNd32Pseudo_UPD
3751
0
    UINT64_C(4102031872), // VST3LNd32_UPD
3752
0
    UINT64_C(4102029839), // VST3LNd8
3753
0
    UINT64_C(0),  // VST3LNd8Pseudo
3754
0
    UINT64_C(0),  // VST3LNd8Pseudo_UPD
3755
0
    UINT64_C(4102029824), // VST3LNd8_UPD
3756
0
    UINT64_C(4102030895), // VST3LNq16
3757
0
    UINT64_C(0),  // VST3LNq16Pseudo
3758
0
    UINT64_C(0),  // VST3LNq16Pseudo_UPD
3759
0
    UINT64_C(4102030880), // VST3LNq16_UPD
3760
0
    UINT64_C(4102031951), // VST3LNq32
3761
0
    UINT64_C(0),  // VST3LNq32Pseudo
3762
0
    UINT64_C(0),  // VST3LNq32Pseudo_UPD
3763
0
    UINT64_C(4102031936), // VST3LNq32_UPD
3764
0
    UINT64_C(4093641807), // VST3d16
3765
0
    UINT64_C(0),  // VST3d16Pseudo
3766
0
    UINT64_C(0),  // VST3d16Pseudo_UPD
3767
0
    UINT64_C(4093641792), // VST3d16_UPD
3768
0
    UINT64_C(4093641871), // VST3d32
3769
0
    UINT64_C(0),  // VST3d32Pseudo
3770
0
    UINT64_C(0),  // VST3d32Pseudo_UPD
3771
0
    UINT64_C(4093641856), // VST3d32_UPD
3772
0
    UINT64_C(4093641743), // VST3d8
3773
0
    UINT64_C(0),  // VST3d8Pseudo
3774
0
    UINT64_C(0),  // VST3d8Pseudo_UPD
3775
0
    UINT64_C(4093641728), // VST3d8_UPD
3776
0
    UINT64_C(4093642063), // VST3q16
3777
0
    UINT64_C(0),  // VST3q16Pseudo_UPD
3778
0
    UINT64_C(4093642048), // VST3q16_UPD
3779
0
    UINT64_C(0),  // VST3q16oddPseudo
3780
0
    UINT64_C(0),  // VST3q16oddPseudo_UPD
3781
0
    UINT64_C(4093642127), // VST3q32
3782
0
    UINT64_C(0),  // VST3q32Pseudo_UPD
3783
0
    UINT64_C(4093642112), // VST3q32_UPD
3784
0
    UINT64_C(0),  // VST3q32oddPseudo
3785
0
    UINT64_C(0),  // VST3q32oddPseudo_UPD
3786
0
    UINT64_C(4093641999), // VST3q8
3787
0
    UINT64_C(0),  // VST3q8Pseudo_UPD
3788
0
    UINT64_C(4093641984), // VST3q8_UPD
3789
0
    UINT64_C(0),  // VST3q8oddPseudo
3790
0
    UINT64_C(0),  // VST3q8oddPseudo_UPD
3791
0
    UINT64_C(4102031119), // VST4LNd16
3792
0
    UINT64_C(0),  // VST4LNd16Pseudo
3793
0
    UINT64_C(0),  // VST4LNd16Pseudo_UPD
3794
0
    UINT64_C(4102031104), // VST4LNd16_UPD
3795
0
    UINT64_C(4102032143), // VST4LNd32
3796
0
    UINT64_C(0),  // VST4LNd32Pseudo
3797
0
    UINT64_C(0),  // VST4LNd32Pseudo_UPD
3798
0
    UINT64_C(4102032128), // VST4LNd32_UPD
3799
0
    UINT64_C(4102030095), // VST4LNd8
3800
0
    UINT64_C(0),  // VST4LNd8Pseudo
3801
0
    UINT64_C(0),  // VST4LNd8Pseudo_UPD
3802
0
    UINT64_C(4102030080), // VST4LNd8_UPD
3803
0
    UINT64_C(4102031151), // VST4LNq16
3804
0
    UINT64_C(0),  // VST4LNq16Pseudo
3805
0
    UINT64_C(0),  // VST4LNq16Pseudo_UPD
3806
0
    UINT64_C(4102031136), // VST4LNq16_UPD
3807
0
    UINT64_C(4102032207), // VST4LNq32
3808
0
    UINT64_C(0),  // VST4LNq32Pseudo
3809
0
    UINT64_C(0),  // VST4LNq32Pseudo_UPD
3810
0
    UINT64_C(4102032192), // VST4LNq32_UPD
3811
0
    UINT64_C(4093640783), // VST4d16
3812
0
    UINT64_C(0),  // VST4d16Pseudo
3813
0
    UINT64_C(0),  // VST4d16Pseudo_UPD
3814
0
    UINT64_C(4093640768), // VST4d16_UPD
3815
0
    UINT64_C(4093640847), // VST4d32
3816
0
    UINT64_C(0),  // VST4d32Pseudo
3817
0
    UINT64_C(0),  // VST4d32Pseudo_UPD
3818
0
    UINT64_C(4093640832), // VST4d32_UPD
3819
0
    UINT64_C(4093640719), // VST4d8
3820
0
    UINT64_C(0),  // VST4d8Pseudo
3821
0
    UINT64_C(0),  // VST4d8Pseudo_UPD
3822
0
    UINT64_C(4093640704), // VST4d8_UPD
3823
0
    UINT64_C(4093641039), // VST4q16
3824
0
    UINT64_C(0),  // VST4q16Pseudo_UPD
3825
0
    UINT64_C(4093641024), // VST4q16_UPD
3826
0
    UINT64_C(0),  // VST4q16oddPseudo
3827
0
    UINT64_C(0),  // VST4q16oddPseudo_UPD
3828
0
    UINT64_C(4093641103), // VST4q32
3829
0
    UINT64_C(0),  // VST4q32Pseudo_UPD
3830
0
    UINT64_C(4093641088), // VST4q32_UPD
3831
0
    UINT64_C(0),  // VST4q32oddPseudo
3832
0
    UINT64_C(0),  // VST4q32oddPseudo_UPD
3833
0
    UINT64_C(4093640975), // VST4q8
3834
0
    UINT64_C(0),  // VST4q8Pseudo_UPD
3835
0
    UINT64_C(4093640960), // VST4q8_UPD
3836
0
    UINT64_C(0),  // VST4q8oddPseudo
3837
0
    UINT64_C(0),  // VST4q8oddPseudo_UPD
3838
0
    UINT64_C(220203776),  // VSTMDDB_UPD
3839
0
    UINT64_C(209718016),  // VSTMDIA
3840
0
    UINT64_C(211815168),  // VSTMDIA_UPD
3841
0
    UINT64_C(0),  // VSTMQIA
3842
0
    UINT64_C(220203520),  // VSTMSDB_UPD
3843
0
    UINT64_C(209717760),  // VSTMSIA
3844
0
    UINT64_C(211814912),  // VSTMSIA_UPD
3845
0
    UINT64_C(218106624),  // VSTRD
3846
0
    UINT64_C(218106112),  // VSTRH
3847
0
    UINT64_C(218106368),  // VSTRS
3848
0
    UINT64_C(222351232),  // VSTR_FPCXTNS_off
3849
0
    UINT64_C(207671168),  // VSTR_FPCXTNS_post
3850
0
    UINT64_C(224448384),  // VSTR_FPCXTNS_pre
3851
0
    UINT64_C(222359424),  // VSTR_FPCXTS_off
3852
0
    UINT64_C(207679360),  // VSTR_FPCXTS_post
3853
0
    UINT64_C(224456576),  // VSTR_FPCXTS_pre
3854
0
    UINT64_C(218124160),  // VSTR_FPSCR_NZCVQC_off
3855
0
    UINT64_C(203444096),  // VSTR_FPSCR_NZCVQC_post
3856
0
    UINT64_C(220221312),  // VSTR_FPSCR_NZCVQC_pre
3857
0
    UINT64_C(218115968),  // VSTR_FPSCR_off
3858
0
    UINT64_C(203435904),  // VSTR_FPSCR_post
3859
0
    UINT64_C(220213120),  // VSTR_FPSCR_pre
3860
0
    UINT64_C(222343040),  // VSTR_P0_off
3861
0
    UINT64_C(207662976),  // VSTR_P0_post
3862
0
    UINT64_C(224440192),  // VSTR_P0_pre
3863
0
    UINT64_C(222334848),  // VSTR_VPR_off
3864
0
    UINT64_C(207654784),  // VSTR_VPR_post
3865
0
    UINT64_C(224432000),  // VSTR_VPR_pre
3866
0
    UINT64_C(238029632),  // VSUBD
3867
0
    UINT64_C(238029120),  // VSUBH
3868
0
    UINT64_C(4070573568), // VSUBHNv2i32
3869
0
    UINT64_C(4069524992), // VSUBHNv4i16
3870
0
    UINT64_C(4068476416), // VSUBHNv8i8
3871
0
    UINT64_C(4070572544), // VSUBLsv2i64
3872
0
    UINT64_C(4069523968), // VSUBLsv4i32
3873
0
    UINT64_C(4068475392), // VSUBLsv8i16
3874
0
    UINT64_C(4087349760), // VSUBLuv2i64
3875
0
    UINT64_C(4086301184), // VSUBLuv4i32
3876
0
    UINT64_C(4085252608), // VSUBLuv8i16
3877
0
    UINT64_C(238029376),  // VSUBS
3878
0
    UINT64_C(4070572800), // VSUBWsv2i64
3879
0
    UINT64_C(4069524224), // VSUBWsv4i32
3880
0
    UINT64_C(4068475648), // VSUBWsv8i16
3881
0
    UINT64_C(4087350016), // VSUBWuv2i64
3882
0
    UINT64_C(4086301440), // VSUBWuv4i32
3883
0
    UINT64_C(4085252864), // VSUBWuv8i16
3884
0
    UINT64_C(4062186752), // VSUBfd
3885
0
    UINT64_C(4062186816), // VSUBfq
3886
0
    UINT64_C(4063235328), // VSUBhd
3887
0
    UINT64_C(4063235392), // VSUBhq
3888
0
    UINT64_C(4076865600), // VSUBv16i8
3889
0
    UINT64_C(4080011264), // VSUBv1i64
3890
0
    UINT64_C(4078962688), // VSUBv2i32
3891
0
    UINT64_C(4080011328), // VSUBv2i64
3892
0
    UINT64_C(4077914112), // VSUBv4i16
3893
0
    UINT64_C(4078962752), // VSUBv4i32
3894
0
    UINT64_C(4077914176), // VSUBv8i16
3895
0
    UINT64_C(4076865536), // VSUBv8i8
3896
0
    UINT64_C(4269804816), // VSUDOTDI
3897
0
    UINT64_C(4269804880), // VSUDOTQI
3898
0
    UINT64_C(4088528896), // VSWPd
3899
0
    UINT64_C(4088528960), // VSWPq
3900
0
    UINT64_C(4088399872), // VTBL1
3901
0
    UINT64_C(4088400128), // VTBL2
3902
0
    UINT64_C(4088400384), // VTBL3
3903
0
    UINT64_C(0),  // VTBL3Pseudo
3904
0
    UINT64_C(4088400640), // VTBL4
3905
0
    UINT64_C(0),  // VTBL4Pseudo
3906
0
    UINT64_C(4088399936), // VTBX1
3907
0
    UINT64_C(4088400192), // VTBX2
3908
0
    UINT64_C(4088400448), // VTBX3
3909
0
    UINT64_C(0),  // VTBX3Pseudo
3910
0
    UINT64_C(4088400704), // VTBX4
3911
0
    UINT64_C(0),  // VTBX4Pseudo
3912
0
    UINT64_C(247335744),  // VTOSHD
3913
0
    UINT64_C(247335232),  // VTOSHH
3914
0
    UINT64_C(247335488),  // VTOSHS
3915
0
    UINT64_C(247270208),  // VTOSIRD
3916
0
    UINT64_C(247269696),  // VTOSIRH
3917
0
    UINT64_C(247269952),  // VTOSIRS
3918
0
    UINT64_C(247270336),  // VTOSIZD
3919
0
    UINT64_C(247269824),  // VTOSIZH
3920
0
    UINT64_C(247270080),  // VTOSIZS
3921
0
    UINT64_C(247335872),  // VTOSLD
3922
0
    UINT64_C(247335360),  // VTOSLH
3923
0
    UINT64_C(247335616),  // VTOSLS
3924
0
    UINT64_C(247401280),  // VTOUHD
3925
0
    UINT64_C(247400768),  // VTOUHH
3926
0
    UINT64_C(247401024),  // VTOUHS
3927
0
    UINT64_C(247204672),  // VTOUIRD
3928
0
    UINT64_C(247204160),  // VTOUIRH
3929
0
    UINT64_C(247204416),  // VTOUIRS
3930
0
    UINT64_C(247204800),  // VTOUIZD
3931
0
    UINT64_C(247204288),  // VTOUIZH
3932
0
    UINT64_C(247204544),  // VTOUIZS
3933
0
    UINT64_C(247401408),  // VTOULD
3934
0
    UINT64_C(247400896),  // VTOULH
3935
0
    UINT64_C(247401152),  // VTOULS
3936
0
    UINT64_C(4088791168), // VTRNd16
3937
0
    UINT64_C(4089053312), // VTRNd32
3938
0
    UINT64_C(4088529024), // VTRNd8
3939
0
    UINT64_C(4088791232), // VTRNq16
3940
0
    UINT64_C(4089053376), // VTRNq32
3941
0
    UINT64_C(4088529088), // VTRNq8
3942
0
    UINT64_C(4060088400), // VTSTv16i8
3943
0
    UINT64_C(4062185488), // VTSTv2i32
3944
0
    UINT64_C(4061136912), // VTSTv4i16
3945
0
    UINT64_C(4062185552), // VTSTv4i32
3946
0
    UINT64_C(4061136976), // VTSTv8i16
3947
0
    UINT64_C(4060088336), // VTSTv8i8
3948
0
    UINT64_C(4229958928), // VUDOTD
3949
0
    UINT64_C(4263513360), // VUDOTDI
3950
0
    UINT64_C(4229958992), // VUDOTQ
3951
0
    UINT64_C(4263513424), // VUDOTQI
3952
0
    UINT64_C(247139136),  // VUHTOD
3953
0
    UINT64_C(247138624),  // VUHTOH
3954
0
    UINT64_C(247138880),  // VUHTOS
3955
0
    UINT64_C(246942528),  // VUITOD
3956
0
    UINT64_C(246942016),  // VUITOH
3957
0
    UINT64_C(246942272),  // VUITOS
3958
0
    UINT64_C(247139264),  // VULTOD
3959
0
    UINT64_C(247138752),  // VULTOH
3960
0
    UINT64_C(247139008),  // VULTOS
3961
0
    UINT64_C(4229958736), // VUMMLA
3962
0
    UINT64_C(4238347520), // VUSDOTD
3963
0
    UINT64_C(4269804800), // VUSDOTDI
3964
0
    UINT64_C(4238347584), // VUSDOTQ
3965
0
    UINT64_C(4269804864), // VUSDOTQI
3966
0
    UINT64_C(4238347328), // VUSMMLA
3967
0
    UINT64_C(4088791296), // VUZPd16
3968
0
    UINT64_C(4088529152), // VUZPd8
3969
0
    UINT64_C(4088791360), // VUZPq16
3970
0
    UINT64_C(4089053504), // VUZPq32
3971
0
    UINT64_C(4088529216), // VUZPq8
3972
0
    UINT64_C(4088791424), // VZIPd16
3973
0
    UINT64_C(4088529280), // VZIPd8
3974
0
    UINT64_C(4088791488), // VZIPq16
3975
0
    UINT64_C(4089053632), // VZIPq32
3976
0
    UINT64_C(4088529344), // VZIPq8
3977
0
    UINT64_C(139460608),  // sysLDMDA
3978
0
    UINT64_C(141557760),  // sysLDMDA_UPD
3979
0
    UINT64_C(156237824),  // sysLDMDB
3980
0
    UINT64_C(158334976),  // sysLDMDB_UPD
3981
0
    UINT64_C(147849216),  // sysLDMIA
3982
0
    UINT64_C(149946368),  // sysLDMIA_UPD
3983
0
    UINT64_C(164626432),  // sysLDMIB
3984
0
    UINT64_C(166723584),  // sysLDMIB_UPD
3985
0
    UINT64_C(138412032),  // sysSTMDA
3986
0
    UINT64_C(140509184),  // sysSTMDA_UPD
3987
0
    UINT64_C(155189248),  // sysSTMDB
3988
0
    UINT64_C(157286400),  // sysSTMDB_UPD
3989
0
    UINT64_C(146800640),  // sysSTMIA
3990
0
    UINT64_C(148897792),  // sysSTMIA_UPD
3991
0
    UINT64_C(163577856),  // sysSTMIB
3992
0
    UINT64_C(165675008),  // sysSTMIB_UPD
3993
0
    UINT64_C(4047503360), // t2ADCri
3994
0
    UINT64_C(3946840064), // t2ADCrr
3995
0
    UINT64_C(3946840064), // t2ADCrs
3996
0
    UINT64_C(4043309056), // t2ADDri
3997
0
    UINT64_C(4060086272), // t2ADDri12
3998
0
    UINT64_C(3942645760), // t2ADDrr
3999
0
    UINT64_C(3942645760), // t2ADDrs
4000
0
    UINT64_C(4044164352), // t2ADDspImm
4001
0
    UINT64_C(4060941568), // t2ADDspImm12
4002
0
    UINT64_C(4061069312), // t2ADR
4003
0
    UINT64_C(4026531840), // t2ANDri
4004
0
    UINT64_C(3925868544), // t2ANDrr
4005
0
    UINT64_C(3925868544), // t2ANDrs
4006
0
    UINT64_C(3931045920), // t2ASRri
4007
0
    UINT64_C(4198559744), // t2ASRrr
4008
0
    UINT64_C(4088365101), // t2AUT
4009
0
    UINT64_C(4216327936), // t2AUTG
4010
0
    UINT64_C(4026568704), // t2B
4011
0
    UINT64_C(4084137984), // t2BFC
4012
0
    UINT64_C(4083154944), // t2BFI
4013
0
    UINT64_C(4026580993), // t2BFLi
4014
0
    UINT64_C(4033929217), // t2BFLr
4015
0
    UINT64_C(4030783489), // t2BFi
4016
0
    UINT64_C(4026589185), // t2BFic
4017
0
    UINT64_C(4032880641), // t2BFr
4018
0
    UINT64_C(4028628992), // t2BICri
4019
0
    UINT64_C(3927965696), // t2BICrr
4020
0
    UINT64_C(3927965696), // t2BICrs
4021
0
    UINT64_C(4088365071), // t2BTI
4022
0
    UINT64_C(4216327952), // t2BXAUT
4023
0
    UINT64_C(4089483008), // t2BXJ
4024
0
    UINT64_C(4026564608), // t2Bcc
4025
0
    UINT64_C(3992977408), // t2CDP
4026
0
    UINT64_C(4261412864), // t2CDP2
4027
0
    UINT64_C(4089417519), // t2CLREX
4028
0
    UINT64_C(3902734336), // t2CLRM
4029
0
    UINT64_C(4205899904), // t2CLZ
4030
0
    UINT64_C(4044361472), // t2CMNri
4031
0
    UINT64_C(3943698176), // t2CMNzrr
4032
0
    UINT64_C(3943698176), // t2CMNzrs
4033
0
    UINT64_C(4054847232), // t2CMPri
4034
0
    UINT64_C(3954183936), // t2CMPrr
4035
0
    UINT64_C(3954183936), // t2CMPrs
4036
0
    UINT64_C(4088365312), // t2CPS1p
4037
0
    UINT64_C(4088365056), // t2CPS2p
4038
0
    UINT64_C(4088365312), // t2CPS3p
4039
0
    UINT64_C(4206948480), // t2CRC32B
4040
0
    UINT64_C(4207997056), // t2CRC32CB
4041
0
    UINT64_C(4207997072), // t2CRC32CH
4042
0
    UINT64_C(4207997088), // t2CRC32CW
4043
0
    UINT64_C(4206948496), // t2CRC32H
4044
0
    UINT64_C(4206948512), // t2CRC32W
4045
0
    UINT64_C(3931144192), // t2CSEL
4046
0
    UINT64_C(3931148288), // t2CSINC
4047
0
    UINT64_C(3931152384), // t2CSINV
4048
0
    UINT64_C(3931156480), // t2CSNEG
4049
0
    UINT64_C(4088365296), // t2DBG
4050
0
    UINT64_C(4153376769), // t2DCPS1
4051
0
    UINT64_C(4153376770), // t2DCPS2
4052
0
    UINT64_C(4153376771), // t2DCPS3
4053
0
    UINT64_C(4030783489), // t2DLS
4054
0
    UINT64_C(4089417552), // t2DMB
4055
0
    UINT64_C(4089417536), // t2DSB
4056
0
    UINT64_C(4034920448), // t2EORri
4057
0
    UINT64_C(3934257152), // t2EORrr
4058
0
    UINT64_C(3934257152), // t2EORrs
4059
0
    UINT64_C(4088365056), // t2HINT
4060
0
    UINT64_C(4158685184), // t2HVC
4061
0
    UINT64_C(4089417568), // t2ISB
4062
0
    UINT64_C(48896),  // t2IT
4063
0
    UINT64_C(0),  // t2Int_eh_sjlj_setjmp
4064
0
    UINT64_C(0),  // t2Int_eh_sjlj_setjmp_nofp
4065
0
    UINT64_C(3905949615), // t2LDA
4066
0
    UINT64_C(3905949583), // t2LDAB
4067
0
    UINT64_C(3905949679), // t2LDAEX
4068
0
    UINT64_C(3905949647), // t2LDAEXB
4069
0
    UINT64_C(3905945855), // t2LDAEXD
4070
0
    UINT64_C(3905949663), // t2LDAEXH
4071
0
    UINT64_C(3905949599), // t2LDAH
4072
0
    UINT64_C(4249878528), // t2LDC2L_OFFSET
4073
0
    UINT64_C(4241489920), // t2LDC2L_OPTION
4074
0
    UINT64_C(4235198464), // t2LDC2L_POST
4075
0
    UINT64_C(4251975680), // t2LDC2L_PRE
4076
0
    UINT64_C(4245684224), // t2LDC2_OFFSET
4077
0
    UINT64_C(4237295616), // t2LDC2_OPTION
4078
0
    UINT64_C(4231004160), // t2LDC2_POST
4079
0
    UINT64_C(4247781376), // t2LDC2_PRE
4080
0
    UINT64_C(3981443072), // t2LDCL_OFFSET
4081
0
    UINT64_C(3973054464), // t2LDCL_OPTION
4082
0
    UINT64_C(3966763008), // t2LDCL_POST
4083
0
    UINT64_C(3983540224), // t2LDCL_PRE
4084
0
    UINT64_C(3977248768), // t2LDC_OFFSET
4085
0
    UINT64_C(3968860160), // t2LDC_OPTION
4086
0
    UINT64_C(3962568704), // t2LDC_POST
4087
0
    UINT64_C(3979345920), // t2LDC_PRE
4088
0
    UINT64_C(3910139904), // t2LDMDB
4089
0
    UINT64_C(3912237056), // t2LDMDB_UPD
4090
0
    UINT64_C(3901751296), // t2LDMIA
4091
0
    UINT64_C(3903848448), // t2LDMIA_UPD
4092
0
    UINT64_C(4161801728), // t2LDRBT
4093
0
    UINT64_C(4161800448), // t2LDRB_POST
4094
0
    UINT64_C(4161801472), // t2LDRB_PRE
4095
0
    UINT64_C(4170186752), // t2LDRBi12
4096
0
    UINT64_C(4161801216), // t2LDRBi8
4097
0
    UINT64_C(4162781184), // t2LDRBpci
4098
0
    UINT64_C(4161798144), // t2LDRBs
4099
0
    UINT64_C(3899654144), // t2LDRD_POST
4100
0
    UINT64_C(3916431360), // t2LDRD_PRE
4101
0
    UINT64_C(3914334208), // t2LDRDi8
4102
0
    UINT64_C(3897560832), // t2LDREX
4103
0
    UINT64_C(3905949519), // t2LDREXB
4104
0
    UINT64_C(3905945727), // t2LDREXD
4105
0
    UINT64_C(3905949535), // t2LDREXH
4106
0
    UINT64_C(4163898880), // t2LDRHT
4107
0
    UINT64_C(4163897600), // t2LDRH_POST
4108
0
    UINT64_C(4163898624), // t2LDRH_PRE
4109
0
    UINT64_C(4172283904), // t2LDRHi12
4110
0
    UINT64_C(4163898368), // t2LDRHi8
4111
0
    UINT64_C(4164878336), // t2LDRHpci
4112
0
    UINT64_C(4163895296), // t2LDRHs
4113
0
    UINT64_C(4178578944), // t2LDRSBT
4114
0
    UINT64_C(4178577664), // t2LDRSB_POST
4115
0
    UINT64_C(4178578688), // t2LDRSB_PRE
4116
0
    UINT64_C(4186963968), // t2LDRSBi12
4117
0
    UINT64_C(4178578432), // t2LDRSBi8
4118
0
    UINT64_C(4179558400), // t2LDRSBpci
4119
0
    UINT64_C(4178575360), // t2LDRSBs
4120
0
    UINT64_C(4180676096), // t2LDRSHT
4121
0
    UINT64_C(4180674816), // t2LDRSH_POST
4122
0
    UINT64_C(4180675840), // t2LDRSH_PRE
4123
0
    UINT64_C(4189061120), // t2LDRSHi12
4124
0
    UINT64_C(4180675584), // t2LDRSHi8
4125
0
    UINT64_C(4181655552), // t2LDRSHpci
4126
0
    UINT64_C(4180672512), // t2LDRSHs
4127
0
    UINT64_C(4165996032), // t2LDRT
4128
0
    UINT64_C(4165994752), // t2LDR_POST
4129
0
    UINT64_C(4165995776), // t2LDR_PRE
4130
0
    UINT64_C(4174381056), // t2LDRi12
4131
0
    UINT64_C(4165995520), // t2LDRi8
4132
0
    UINT64_C(4166975488), // t2LDRpci
4133
0
    UINT64_C(4165992448), // t2LDRs
4134
0
    UINT64_C(4029661185), // t2LE
4135
0
    UINT64_C(4027564033), // t2LEUpdate
4136
0
    UINT64_C(3931045888), // t2LSLri
4137
0
    UINT64_C(4194365440), // t2LSLrr
4138
0
    UINT64_C(3931045904), // t2LSRri
4139
0
    UINT64_C(4196462592), // t2LSRrr
4140
0
    UINT64_C(3992977424), // t2MCR
4141
0
    UINT64_C(4261412880), // t2MCR2
4142
0
    UINT64_C(3963617280), // t2MCRR
4143
0
    UINT64_C(4232052736), // t2MCRR2
4144
0
    UINT64_C(4211081216), // t2MLA
4145
0
    UINT64_C(4211081232), // t2MLS
4146
0
    UINT64_C(4072669184), // t2MOVTi16
4147
0
    UINT64_C(4031709184), // t2MOVi
4148
0
    UINT64_C(4064280576), // t2MOVi16
4149
0
    UINT64_C(3931045888), // t2MOVr
4150
0
    UINT64_C(3932094560), // t2MOVsra_glue
4151
0
    UINT64_C(3932094544), // t2MOVsrl_glue
4152
0
    UINT64_C(3994026000), // t2MRC
4153
0
    UINT64_C(4262461456), // t2MRC2
4154
0
    UINT64_C(3964665856), // t2MRRC
4155
0
    UINT64_C(4233101312), // t2MRRC2
4156
0
    UINT64_C(4092559360), // t2MRS_AR
4157
0
    UINT64_C(4092559360), // t2MRS_M
4158
0
    UINT64_C(4091576352), // t2MRSbanked
4159
0
    UINT64_C(4093607936), // t2MRSsys_AR
4160
0
    UINT64_C(4085284864), // t2MSR_AR
4161
0
    UINT64_C(4085284864), // t2MSR_M
4162
0
    UINT64_C(4085284896), // t2MSRbanked
4163
0
    UINT64_C(4211142656), // t2MUL
4164
0
    UINT64_C(4033806336), // t2MVNi
4165
0
    UINT64_C(3933143040), // t2MVNr
4166
0
    UINT64_C(3933143040), // t2MVNs
4167
0
    UINT64_C(4032823296), // t2ORNri
4168
0
    UINT64_C(3932160000), // t2ORNrr
4169
0
    UINT64_C(3932160000), // t2ORNrs
4170
0
    UINT64_C(4030726144), // t2ORRri
4171
0
    UINT64_C(3930062848), // t2ORRrr
4172
0
    UINT64_C(3930062848), // t2ORRrs
4173
0
    UINT64_C(4088365085), // t2PAC
4174
0
    UINT64_C(4088365069), // t2PACBTI
4175
0
    UINT64_C(4217434112), // t2PACG
4176
0
    UINT64_C(3938451456), // t2PKHBT
4177
0
    UINT64_C(3938451488), // t2PKHTB
4178
0
    UINT64_C(4172345344), // t2PLDWi12
4179
0
    UINT64_C(4163959808), // t2PLDWi8
4180
0
    UINT64_C(4163956736), // t2PLDWs
4181
0
    UINT64_C(4170248192), // t2PLDi12
4182
0
    UINT64_C(4161862656), // t2PLDi8
4183
0
    UINT64_C(4162842624), // t2PLDpci
4184
0
    UINT64_C(4161859584), // t2PLDs
4185
0
    UINT64_C(4187025408), // t2PLIi12
4186
0
    UINT64_C(4178639872), // t2PLIi8
4187
0
    UINT64_C(4179619840), // t2PLIpci
4188
0
    UINT64_C(4178636800), // t2PLIs
4189
0
    UINT64_C(4202754176), // t2QADD
4190
0
    UINT64_C(4203802640), // t2QADD16
4191
0
    UINT64_C(4202754064), // t2QADD8
4192
0
    UINT64_C(4204851216), // t2QASX
4193
0
    UINT64_C(4202754192), // t2QDADD
4194
0
    UINT64_C(4202754224), // t2QDSUB
4195
0
    UINT64_C(4209045520), // t2QSAX
4196
0
    UINT64_C(4202754208), // t2QSUB
4197
0
    UINT64_C(4207996944), // t2QSUB16
4198
0
    UINT64_C(4206948368), // t2QSUB8
4199
0
    UINT64_C(4203802784), // t2RBIT
4200
0
    UINT64_C(4203802752), // t2REV
4201
0
    UINT64_C(4203802768), // t2REV16
4202
0
    UINT64_C(4203802800), // t2REVSH
4203
0
    UINT64_C(3893411840), // t2RFEDB
4204
0
    UINT64_C(3895508992), // t2RFEDBW
4205
0
    UINT64_C(3918577664), // t2RFEIA
4206
0
    UINT64_C(3920674816), // t2RFEIAW
4207
0
    UINT64_C(3931045936), // t2RORri
4208
0
    UINT64_C(4200656896), // t2RORrr
4209
0
    UINT64_C(3931045936), // t2RRX
4210
0
    UINT64_C(4055891968), // t2RSBri
4211
0
    UINT64_C(3955228672), // t2RSBrr
4212
0
    UINT64_C(3955228672), // t2RSBrs
4213
0
    UINT64_C(4203802624), // t2SADD16
4214
0
    UINT64_C(4202754048), // t2SADD8
4215
0
    UINT64_C(4204851200), // t2SASX
4216
0
    UINT64_C(4089417584), // t2SB
4217
0
    UINT64_C(4049600512), // t2SBCri
4218
0
    UINT64_C(3948937216), // t2SBCrr
4219
0
    UINT64_C(3948937216), // t2SBCrs
4220
0
    UINT64_C(4081057792), // t2SBFX
4221
0
    UINT64_C(4220580080), // t2SDIV
4222
0
    UINT64_C(4204851328), // t2SEL
4223
0
    UINT64_C(46608),  // t2SETPAN
4224
0
    UINT64_C(3917474175), // t2SG
4225
0
    UINT64_C(4203802656), // t2SHADD16
4226
0
    UINT64_C(4202754080), // t2SHADD8
4227
0
    UINT64_C(4204851232), // t2SHASX
4228
0
    UINT64_C(4209045536), // t2SHSAX
4229
0
    UINT64_C(4207996960), // t2SHSUB16
4230
0
    UINT64_C(4206948384), // t2SHSUB8
4231
0
    UINT64_C(4159733760), // t2SMC
4232
0
    UINT64_C(4212129792), // t2SMLABB
4233
0
    UINT64_C(4212129808), // t2SMLABT
4234
0
    UINT64_C(4213178368), // t2SMLAD
4235
0
    UINT64_C(4213178384), // t2SMLADX
4236
0
    UINT64_C(4223664128), // t2SMLAL
4237
0
    UINT64_C(4223664256), // t2SMLALBB
4238
0
    UINT64_C(4223664272), // t2SMLALBT
4239
0
    UINT64_C(4223664320), // t2SMLALD
4240
0
    UINT64_C(4223664336), // t2SMLALDX
4241
0
    UINT64_C(4223664288), // t2SMLALTB
4242
0
    UINT64_C(4223664304), // t2SMLALTT
4243
0
    UINT64_C(4212129824), // t2SMLATB
4244
0
    UINT64_C(4212129840), // t2SMLATT
4245
0
    UINT64_C(4214226944), // t2SMLAWB
4246
0
    UINT64_C(4214226960), // t2SMLAWT
4247
0
    UINT64_C(4215275520), // t2SMLSD
4248
0
    UINT64_C(4215275536), // t2SMLSDX
4249
0
    UINT64_C(4224712896), // t2SMLSLD
4250
0
    UINT64_C(4224712912), // t2SMLSLDX
4251
0
    UINT64_C(4216324096), // t2SMMLA
4252
0
    UINT64_C(4216324112), // t2SMMLAR
4253
0
    UINT64_C(4217372672), // t2SMMLS
4254
0
    UINT64_C(4217372688), // t2SMMLSR
4255
0
    UINT64_C(4216385536), // t2SMMUL
4256
0
    UINT64_C(4216385552), // t2SMMULR
4257
0
    UINT64_C(4213239808), // t2SMUAD
4258
0
    UINT64_C(4213239824), // t2SMUADX
4259
0
    UINT64_C(4212191232), // t2SMULBB
4260
0
    UINT64_C(4212191248), // t2SMULBT
4261
0
    UINT64_C(4219469824), // t2SMULL
4262
0
    UINT64_C(4212191264), // t2SMULTB
4263
0
    UINT64_C(4212191280), // t2SMULTT
4264
0
    UINT64_C(4214288384), // t2SMULWB
4265
0
    UINT64_C(4214288400), // t2SMULWT
4266
0
    UINT64_C(4215336960), // t2SMUSD
4267
0
    UINT64_C(4215336976), // t2SMUSDX
4268
0
    UINT64_C(3893215232), // t2SRSDB
4269
0
    UINT64_C(3895312384), // t2SRSDB_UPD
4270
0
    UINT64_C(3918381056), // t2SRSIA
4271
0
    UINT64_C(3920478208), // t2SRSIA_UPD
4272
0
    UINT64_C(4076863488), // t2SSAT
4273
0
    UINT64_C(4078960640), // t2SSAT16
4274
0
    UINT64_C(4209045504), // t2SSAX
4275
0
    UINT64_C(4207996928), // t2SSUB16
4276
0
    UINT64_C(4206948352), // t2SSUB8
4277
0
    UINT64_C(4248829952), // t2STC2L_OFFSET
4278
0
    UINT64_C(4240441344), // t2STC2L_OPTION
4279
0
    UINT64_C(4234149888), // t2STC2L_POST
4280
0
    UINT64_C(4250927104), // t2STC2L_PRE
4281
0
    UINT64_C(4244635648), // t2STC2_OFFSET
4282
0
    UINT64_C(4236247040), // t2STC2_OPTION
4283
0
    UINT64_C(4229955584), // t2STC2_POST
4284
0
    UINT64_C(4246732800), // t2STC2_PRE
4285
0
    UINT64_C(3980394496), // t2STCL_OFFSET
4286
0
    UINT64_C(3972005888), // t2STCL_OPTION
4287
0
    UINT64_C(3965714432), // t2STCL_POST
4288
0
    UINT64_C(3982491648), // t2STCL_PRE
4289
0
    UINT64_C(3976200192), // t2STC_OFFSET
4290
0
    UINT64_C(3967811584), // t2STC_OPTION
4291
0
    UINT64_C(3961520128), // t2STC_POST
4292
0
    UINT64_C(3978297344), // t2STC_PRE
4293
0
    UINT64_C(3904901039), // t2STL
4294
0
    UINT64_C(3904901007), // t2STLB
4295
0
    UINT64_C(3904901088), // t2STLEX
4296
0
    UINT64_C(3904901056), // t2STLEXB
4297
0
    UINT64_C(3904897264), // t2STLEXD
4298
0
    UINT64_C(3904901072), // t2STLEXH
4299
0
    UINT64_C(3904901023), // t2STLH
4300
0
    UINT64_C(3909091328), // t2STMDB
4301
0
    UINT64_C(3911188480), // t2STMDB_UPD
4302
0
    UINT64_C(3900702720), // t2STMIA
4303
0
    UINT64_C(3902799872), // t2STMIA_UPD
4304
0
    UINT64_C(4160753152), // t2STRBT
4305
0
    UINT64_C(4160751872), // t2STRB_POST
4306
0
    UINT64_C(4160752896), // t2STRB_PRE
4307
0
    UINT64_C(4169138176), // t2STRBi12
4308
0
    UINT64_C(4160752640), // t2STRBi8
4309
0
    UINT64_C(4160749568), // t2STRBs
4310
0
    UINT64_C(3898605568), // t2STRD_POST
4311
0
    UINT64_C(3915382784), // t2STRD_PRE
4312
0
    UINT64_C(3913285632), // t2STRDi8
4313
0
    UINT64_C(3896508416), // t2STREX
4314
0
    UINT64_C(3904900928), // t2STREXB
4315
0
    UINT64_C(3904897136), // t2STREXD
4316
0
    UINT64_C(3904900944), // t2STREXH
4317
0
    UINT64_C(4162850304), // t2STRHT
4318
0
    UINT64_C(4162849024), // t2STRH_POST
4319
0
    UINT64_C(4162850048), // t2STRH_PRE
4320
0
    UINT64_C(4171235328), // t2STRHi12
4321
0
    UINT64_C(4162849792), // t2STRHi8
4322
0
    UINT64_C(4162846720), // t2STRHs
4323
0
    UINT64_C(4164947456), // t2STRT
4324
0
    UINT64_C(4164946176), // t2STR_POST
4325
0
    UINT64_C(4164947200), // t2STR_PRE
4326
0
    UINT64_C(4173332480), // t2STRi12
4327
0
    UINT64_C(4164946944), // t2STRi8
4328
0
    UINT64_C(4164943872), // t2STRs
4329
0
    UINT64_C(4091449088), // t2SUBS_PC_LR
4330
0
    UINT64_C(4053794816), // t2SUBri
4331
0
    UINT64_C(4070572032), // t2SUBri12
4332
0
    UINT64_C(3953131520), // t2SUBrr
4333
0
    UINT64_C(3953131520), // t2SUBrs
4334
0
    UINT64_C(4054650112), // t2SUBspImm
4335
0
    UINT64_C(4071427328), // t2SUBspImm12
4336
0
    UINT64_C(4198559872), // t2SXTAB
4337
0
    UINT64_C(4196462720), // t2SXTAB16
4338
0
    UINT64_C(4194365568), // t2SXTAH
4339
0
    UINT64_C(4199542912), // t2SXTB
4340
0
    UINT64_C(4197445760), // t2SXTB16
4341
0
    UINT64_C(4195348608), // t2SXTH
4342
0
    UINT64_C(3906007040), // t2TBB
4343
0
    UINT64_C(3906007056), // t2TBH
4344
0
    UINT64_C(4035972864), // t2TEQri
4345
0
    UINT64_C(3935309568), // t2TEQrr
4346
0
    UINT64_C(3935309568), // t2TEQrs
4347
0
    UINT64_C(4088365074), // t2TSB
4348
0
    UINT64_C(4027584256), // t2TSTri
4349
0
    UINT64_C(3926920960), // t2TSTrr
4350
0
    UINT64_C(3926920960), // t2TSTrs
4351
0
    UINT64_C(3896569856), // t2TT
4352
0
    UINT64_C(3896569984), // t2TTA
4353
0
    UINT64_C(3896570048), // t2TTAT
4354
0
    UINT64_C(3896569920), // t2TTT
4355
0
    UINT64_C(4203802688), // t2UADD16
4356
0
    UINT64_C(4202754112), // t2UADD8
4357
0
    UINT64_C(4204851264), // t2UASX
4358
0
    UINT64_C(4089446400), // t2UBFX
4359
0
    UINT64_C(4159741952), // t2UDF
4360
0
    UINT64_C(4222677232), // t2UDIV
4361
0
    UINT64_C(4203802720), // t2UHADD16
4362
0
    UINT64_C(4202754144), // t2UHADD8
4363
0
    UINT64_C(4204851296), // t2UHASX
4364
0
    UINT64_C(4209045600), // t2UHSAX
4365
0
    UINT64_C(4207997024), // t2UHSUB16
4366
0
    UINT64_C(4206948448), // t2UHSUB8
4367
0
    UINT64_C(4225761376), // t2UMAAL
4368
0
    UINT64_C(4225761280), // t2UMLAL
4369
0
    UINT64_C(4221566976), // t2UMULL
4370
0
    UINT64_C(4203802704), // t2UQADD16
4371
0
    UINT64_C(4202754128), // t2UQADD8
4372
0
    UINT64_C(4204851280), // t2UQASX
4373
0
    UINT64_C(4209045584), // t2UQSAX
4374
0
    UINT64_C(4207997008), // t2UQSUB16
4375
0
    UINT64_C(4206948432), // t2UQSUB8
4376
0
    UINT64_C(4218482688), // t2USAD8
4377
0
    UINT64_C(4218421248), // t2USADA8
4378
0
    UINT64_C(4085252096), // t2USAT
4379
0
    UINT64_C(4087349248), // t2USAT16
4380
0
    UINT64_C(4209045568), // t2USAX
4381
0
    UINT64_C(4207996992), // t2USUB16
4382
0
    UINT64_C(4206948416), // t2USUB8
4383
0
    UINT64_C(4199608448), // t2UXTAB
4384
0
    UINT64_C(4197511296), // t2UXTAB16
4385
0
    UINT64_C(4195414144), // t2UXTAH
4386
0
    UINT64_C(4200591488), // t2UXTB
4387
0
    UINT64_C(4198494336), // t2UXTB16
4388
0
    UINT64_C(4196397184), // t2UXTH
4389
0
    UINT64_C(4030775297), // t2WLS
4390
0
    UINT64_C(16704),  // tADC
4391
0
    UINT64_C(17408),  // tADDhirr
4392
0
    UINT64_C(7168), // tADDi3
4393
0
    UINT64_C(12288),  // tADDi8
4394
0
    UINT64_C(17512),  // tADDrSP
4395
0
    UINT64_C(43008),  // tADDrSPi
4396
0
    UINT64_C(6144), // tADDrr
4397
0
    UINT64_C(45056),  // tADDspi
4398
0
    UINT64_C(17541),  // tADDspr
4399
0
    UINT64_C(40960),  // tADR
4400
0
    UINT64_C(16384),  // tAND
4401
0
    UINT64_C(4096), // tASRri
4402
0
    UINT64_C(16640),  // tASRrr
4403
0
    UINT64_C(57344),  // tB
4404
0
    UINT64_C(17280),  // tBIC
4405
0
    UINT64_C(48640),  // tBKPT
4406
0
    UINT64_C(4026585088), // tBL
4407
0
    UINT64_C(18308),  // tBLXNSr
4408
0
    UINT64_C(4026580992), // tBLXi
4409
0
    UINT64_C(18304),  // tBLXr
4410
0
    UINT64_C(18176),  // tBX
4411
0
    UINT64_C(18180),  // tBXNS
4412
0
    UINT64_C(53248),  // tBcc
4413
0
    UINT64_C(47360),  // tCBNZ
4414
0
    UINT64_C(45312),  // tCBZ
4415
0
    UINT64_C(17088),  // tCMNz
4416
0
    UINT64_C(17664),  // tCMPhir
4417
0
    UINT64_C(10240),  // tCMPi8
4418
0
    UINT64_C(17024),  // tCMPr
4419
0
    UINT64_C(46688),  // tCPS
4420
0
    UINT64_C(16448),  // tEOR
4421
0
    UINT64_C(48896),  // tHINT
4422
0
    UINT64_C(47744),  // tHLT
4423
0
    UINT64_C(0),  // tInt_WIN_eh_sjlj_longjmp
4424
0
    UINT64_C(0),  // tInt_eh_sjlj_longjmp
4425
0
    UINT64_C(0),  // tInt_eh_sjlj_setjmp
4426
0
    UINT64_C(51200),  // tLDMIA
4427
0
    UINT64_C(30720),  // tLDRBi
4428
0
    UINT64_C(23552),  // tLDRBr
4429
0
    UINT64_C(34816),  // tLDRHi
4430
0
    UINT64_C(23040),  // tLDRHr
4431
0
    UINT64_C(22016),  // tLDRSB
4432
0
    UINT64_C(24064),  // tLDRSH
4433
0
    UINT64_C(26624),  // tLDRi
4434
0
    UINT64_C(18432),  // tLDRpci
4435
0
    UINT64_C(22528),  // tLDRr
4436
0
    UINT64_C(38912),  // tLDRspi
4437
0
    UINT64_C(0),  // tLSLri
4438
0
    UINT64_C(16512),  // tLSLrr
4439
0
    UINT64_C(2048), // tLSRri
4440
0
    UINT64_C(16576),  // tLSRrr
4441
0
    UINT64_C(0),  // tMOVSr
4442
0
    UINT64_C(8192), // tMOVi8
4443
0
    UINT64_C(17920),  // tMOVr
4444
0
    UINT64_C(17216),  // tMUL
4445
0
    UINT64_C(17344),  // tMVN
4446
0
    UINT64_C(17152),  // tORR
4447
0
    UINT64_C(17528),  // tPICADD
4448
0
    UINT64_C(48128),  // tPOP
4449
0
    UINT64_C(46080),  // tPUSH
4450
0
    UINT64_C(47616),  // tREV
4451
0
    UINT64_C(47680),  // tREV16
4452
0
    UINT64_C(47808),  // tREVSH
4453
0
    UINT64_C(16832),  // tROR
4454
0
    UINT64_C(16960),  // tRSB
4455
0
    UINT64_C(16768),  // tSBC
4456
0
    UINT64_C(46672),  // tSETEND
4457
0
    UINT64_C(49152),  // tSTMIA_UPD
4458
0
    UINT64_C(28672),  // tSTRBi
4459
0
    UINT64_C(21504),  // tSTRBr
4460
0
    UINT64_C(32768),  // tSTRHi
4461
0
    UINT64_C(20992),  // tSTRHr
4462
0
    UINT64_C(24576),  // tSTRi
4463
0
    UINT64_C(20480),  // tSTRr
4464
0
    UINT64_C(36864),  // tSTRspi
4465
0
    UINT64_C(7680), // tSUBi3
4466
0
    UINT64_C(14336),  // tSUBi8
4467
0
    UINT64_C(6656), // tSUBrr
4468
0
    UINT64_C(45184),  // tSUBspi
4469
0
    UINT64_C(57088),  // tSVC
4470
0
    UINT64_C(45632),  // tSXTB
4471
0
    UINT64_C(45568),  // tSXTH
4472
0
    UINT64_C(57086),  // tTRAP
4473
0
    UINT64_C(16896),  // tTST
4474
0
    UINT64_C(56832),  // tUDF
4475
0
    UINT64_C(45760),  // tUXTB
4476
0
    UINT64_C(45696),  // tUXTH
4477
0
    UINT64_C(57081),  // t__brkdiv0
4478
0
    UINT64_C(0)
4479
0
  };
4480
0
  const unsigned opcode = MI.getOpcode();
4481
0
  uint64_t Value = InstBits[opcode];
4482
0
  uint64_t op = 0;
4483
0
  (void)op;  // suppress warning
4484
0
  switch (opcode) {
4485
0
    case ARM::CLREX:
4486
0
    case ARM::MVE_LCTP:
4487
0
    case ARM::MVE_VPNOT:
4488
0
    case ARM::SB:
4489
0
    case ARM::TRAP:
4490
0
    case ARM::TRAPNaCl:
4491
0
    case ARM::TSB:
4492
0
    case ARM::VBSPd:
4493
0
    case ARM::VBSPq:
4494
0
    case ARM::VLD1LNq8Pseudo:
4495
0
    case ARM::VLD1LNq8Pseudo_UPD:
4496
0
    case ARM::VLD1LNq16Pseudo:
4497
0
    case ARM::VLD1LNq16Pseudo_UPD:
4498
0
    case ARM::VLD1LNq32Pseudo:
4499
0
    case ARM::VLD1LNq32Pseudo_UPD:
4500
0
    case ARM::VLD1d8QPseudo:
4501
0
    case ARM::VLD1d8QPseudoWB_fixed:
4502
0
    case ARM::VLD1d8QPseudoWB_register:
4503
0
    case ARM::VLD1d8TPseudo:
4504
0
    case ARM::VLD1d8TPseudoWB_fixed:
4505
0
    case ARM::VLD1d8TPseudoWB_register:
4506
0
    case ARM::VLD1d16QPseudo:
4507
0
    case ARM::VLD1d16QPseudoWB_fixed:
4508
0
    case ARM::VLD1d16QPseudoWB_register:
4509
0
    case ARM::VLD1d16TPseudo:
4510
0
    case ARM::VLD1d16TPseudoWB_fixed:
4511
0
    case ARM::VLD1d16TPseudoWB_register:
4512
0
    case ARM::VLD1d32QPseudo:
4513
0
    case ARM::VLD1d32QPseudoWB_fixed:
4514
0
    case ARM::VLD1d32QPseudoWB_register:
4515
0
    case ARM::VLD1d32TPseudo:
4516
0
    case ARM::VLD1d32TPseudoWB_fixed:
4517
0
    case ARM::VLD1d32TPseudoWB_register:
4518
0
    case ARM::VLD1d64QPseudo:
4519
0
    case ARM::VLD1d64QPseudoWB_fixed:
4520
0
    case ARM::VLD1d64QPseudoWB_register:
4521
0
    case ARM::VLD1d64TPseudo:
4522
0
    case ARM::VLD1d64TPseudoWB_fixed:
4523
0
    case ARM::VLD1d64TPseudoWB_register:
4524
0
    case ARM::VLD1q8HighQPseudo:
4525
0
    case ARM::VLD1q8HighQPseudo_UPD:
4526
0
    case ARM::VLD1q8HighTPseudo:
4527
0
    case ARM::VLD1q8HighTPseudo_UPD:
4528
0
    case ARM::VLD1q8LowQPseudo_UPD:
4529
0
    case ARM::VLD1q8LowTPseudo_UPD:
4530
0
    case ARM::VLD1q16HighQPseudo:
4531
0
    case ARM::VLD1q16HighQPseudo_UPD:
4532
0
    case ARM::VLD1q16HighTPseudo:
4533
0
    case ARM::VLD1q16HighTPseudo_UPD:
4534
0
    case ARM::VLD1q16LowQPseudo_UPD:
4535
0
    case ARM::VLD1q16LowTPseudo_UPD:
4536
0
    case ARM::VLD1q32HighQPseudo:
4537
0
    case ARM::VLD1q32HighQPseudo_UPD:
4538
0
    case ARM::VLD1q32HighTPseudo:
4539
0
    case ARM::VLD1q32HighTPseudo_UPD:
4540
0
    case ARM::VLD1q32LowQPseudo_UPD:
4541
0
    case ARM::VLD1q32LowTPseudo_UPD:
4542
0
    case ARM::VLD1q64HighQPseudo:
4543
0
    case ARM::VLD1q64HighQPseudo_UPD:
4544
0
    case ARM::VLD1q64HighTPseudo:
4545
0
    case ARM::VLD1q64HighTPseudo_UPD:
4546
0
    case ARM::VLD1q64LowQPseudo_UPD:
4547
0
    case ARM::VLD1q64LowTPseudo_UPD:
4548
0
    case ARM::VLD2DUPq8EvenPseudo:
4549
0
    case ARM::VLD2DUPq8OddPseudo:
4550
0
    case ARM::VLD2DUPq8OddPseudoWB_fixed:
4551
0
    case ARM::VLD2DUPq8OddPseudoWB_register:
4552
0
    case ARM::VLD2DUPq16EvenPseudo:
4553
0
    case ARM::VLD2DUPq16OddPseudo:
4554
0
    case ARM::VLD2DUPq16OddPseudoWB_fixed:
4555
0
    case ARM::VLD2DUPq16OddPseudoWB_register:
4556
0
    case ARM::VLD2DUPq32EvenPseudo:
4557
0
    case ARM::VLD2DUPq32OddPseudo:
4558
0
    case ARM::VLD2DUPq32OddPseudoWB_fixed:
4559
0
    case ARM::VLD2DUPq32OddPseudoWB_register:
4560
0
    case ARM::VLD2LNd8Pseudo:
4561
0
    case ARM::VLD2LNd8Pseudo_UPD:
4562
0
    case ARM::VLD2LNd16Pseudo:
4563
0
    case ARM::VLD2LNd16Pseudo_UPD:
4564
0
    case ARM::VLD2LNd32Pseudo:
4565
0
    case ARM::VLD2LNd32Pseudo_UPD:
4566
0
    case ARM::VLD2LNq16Pseudo:
4567
0
    case ARM::VLD2LNq16Pseudo_UPD:
4568
0
    case ARM::VLD2LNq32Pseudo:
4569
0
    case ARM::VLD2LNq32Pseudo_UPD:
4570
0
    case ARM::VLD2q8Pseudo:
4571
0
    case ARM::VLD2q8PseudoWB_fixed:
4572
0
    case ARM::VLD2q8PseudoWB_register:
4573
0
    case ARM::VLD2q16Pseudo:
4574
0
    case ARM::VLD2q16PseudoWB_fixed:
4575
0
    case ARM::VLD2q16PseudoWB_register:
4576
0
    case ARM::VLD2q32Pseudo:
4577
0
    case ARM::VLD2q32PseudoWB_fixed:
4578
0
    case ARM::VLD2q32PseudoWB_register:
4579
0
    case ARM::VLD3DUPd8Pseudo:
4580
0
    case ARM::VLD3DUPd8Pseudo_UPD:
4581
0
    case ARM::VLD3DUPd16Pseudo:
4582
0
    case ARM::VLD3DUPd16Pseudo_UPD:
4583
0
    case ARM::VLD3DUPd32Pseudo:
4584
0
    case ARM::VLD3DUPd32Pseudo_UPD:
4585
0
    case ARM::VLD3DUPq8EvenPseudo:
4586
0
    case ARM::VLD3DUPq8OddPseudo:
4587
0
    case ARM::VLD3DUPq8OddPseudo_UPD:
4588
0
    case ARM::VLD3DUPq16EvenPseudo:
4589
0
    case ARM::VLD3DUPq16OddPseudo:
4590
0
    case ARM::VLD3DUPq16OddPseudo_UPD:
4591
0
    case ARM::VLD3DUPq32EvenPseudo:
4592
0
    case ARM::VLD3DUPq32OddPseudo:
4593
0
    case ARM::VLD3DUPq32OddPseudo_UPD:
4594
0
    case ARM::VLD3LNd8Pseudo:
4595
0
    case ARM::VLD3LNd8Pseudo_UPD:
4596
0
    case ARM::VLD3LNd16Pseudo:
4597
0
    case ARM::VLD3LNd16Pseudo_UPD:
4598
0
    case ARM::VLD3LNd32Pseudo:
4599
0
    case ARM::VLD3LNd32Pseudo_UPD:
4600
0
    case ARM::VLD3LNq16Pseudo:
4601
0
    case ARM::VLD3LNq16Pseudo_UPD:
4602
0
    case ARM::VLD3LNq32Pseudo:
4603
0
    case ARM::VLD3LNq32Pseudo_UPD:
4604
0
    case ARM::VLD3d8Pseudo:
4605
0
    case ARM::VLD3d8Pseudo_UPD:
4606
0
    case ARM::VLD3d16Pseudo:
4607
0
    case ARM::VLD3d16Pseudo_UPD:
4608
0
    case ARM::VLD3d32Pseudo:
4609
0
    case ARM::VLD3d32Pseudo_UPD:
4610
0
    case ARM::VLD3q8Pseudo_UPD:
4611
0
    case ARM::VLD3q8oddPseudo:
4612
0
    case ARM::VLD3q8oddPseudo_UPD:
4613
0
    case ARM::VLD3q16Pseudo_UPD:
4614
0
    case ARM::VLD3q16oddPseudo:
4615
0
    case ARM::VLD3q16oddPseudo_UPD:
4616
0
    case ARM::VLD3q32Pseudo_UPD:
4617
0
    case ARM::VLD3q32oddPseudo:
4618
0
    case ARM::VLD3q32oddPseudo_UPD:
4619
0
    case ARM::VLD4DUPd8Pseudo:
4620
0
    case ARM::VLD4DUPd8Pseudo_UPD:
4621
0
    case ARM::VLD4DUPd16Pseudo:
4622
0
    case ARM::VLD4DUPd16Pseudo_UPD:
4623
0
    case ARM::VLD4DUPd32Pseudo:
4624
0
    case ARM::VLD4DUPd32Pseudo_UPD:
4625
0
    case ARM::VLD4DUPq8EvenPseudo:
4626
0
    case ARM::VLD4DUPq8OddPseudo:
4627
0
    case ARM::VLD4DUPq8OddPseudo_UPD:
4628
0
    case ARM::VLD4DUPq16EvenPseudo:
4629
0
    case ARM::VLD4DUPq16OddPseudo:
4630
0
    case ARM::VLD4DUPq16OddPseudo_UPD:
4631
0
    case ARM::VLD4DUPq32EvenPseudo:
4632
0
    case ARM::VLD4DUPq32OddPseudo:
4633
0
    case ARM::VLD4DUPq32OddPseudo_UPD:
4634
0
    case ARM::VLD4LNd8Pseudo:
4635
0
    case ARM::VLD4LNd8Pseudo_UPD:
4636
0
    case ARM::VLD4LNd16Pseudo:
4637
0
    case ARM::VLD4LNd16Pseudo_UPD:
4638
0
    case ARM::VLD4LNd32Pseudo:
4639
0
    case ARM::VLD4LNd32Pseudo_UPD:
4640
0
    case ARM::VLD4LNq16Pseudo:
4641
0
    case ARM::VLD4LNq16Pseudo_UPD:
4642
0
    case ARM::VLD4LNq32Pseudo:
4643
0
    case ARM::VLD4LNq32Pseudo_UPD:
4644
0
    case ARM::VLD4d8Pseudo:
4645
0
    case ARM::VLD4d8Pseudo_UPD:
4646
0
    case ARM::VLD4d16Pseudo:
4647
0
    case ARM::VLD4d16Pseudo_UPD:
4648
0
    case ARM::VLD4d32Pseudo:
4649
0
    case ARM::VLD4d32Pseudo_UPD:
4650
0
    case ARM::VLD4q8Pseudo_UPD:
4651
0
    case ARM::VLD4q8oddPseudo:
4652
0
    case ARM::VLD4q8oddPseudo_UPD:
4653
0
    case ARM::VLD4q16Pseudo_UPD:
4654
0
    case ARM::VLD4q16oddPseudo:
4655
0
    case ARM::VLD4q16oddPseudo_UPD:
4656
0
    case ARM::VLD4q32Pseudo_UPD:
4657
0
    case ARM::VLD4q32oddPseudo:
4658
0
    case ARM::VLD4q32oddPseudo_UPD:
4659
0
    case ARM::VLDMQIA:
4660
0
    case ARM::VST1LNq8Pseudo:
4661
0
    case ARM::VST1LNq8Pseudo_UPD:
4662
0
    case ARM::VST1LNq16Pseudo:
4663
0
    case ARM::VST1LNq16Pseudo_UPD:
4664
0
    case ARM::VST1LNq32Pseudo:
4665
0
    case ARM::VST1LNq32Pseudo_UPD:
4666
0
    case ARM::VST1d8QPseudo:
4667
0
    case ARM::VST1d8QPseudoWB_fixed:
4668
0
    case ARM::VST1d8QPseudoWB_register:
4669
0
    case ARM::VST1d8TPseudo:
4670
0
    case ARM::VST1d8TPseudoWB_fixed:
4671
0
    case ARM::VST1d8TPseudoWB_register:
4672
0
    case ARM::VST1d16QPseudo:
4673
0
    case ARM::VST1d16QPseudoWB_fixed:
4674
0
    case ARM::VST1d16QPseudoWB_register:
4675
0
    case ARM::VST1d16TPseudo:
4676
0
    case ARM::VST1d16TPseudoWB_fixed:
4677
0
    case ARM::VST1d16TPseudoWB_register:
4678
0
    case ARM::VST1d32QPseudo:
4679
0
    case ARM::VST1d32QPseudoWB_fixed:
4680
0
    case ARM::VST1d32QPseudoWB_register:
4681
0
    case ARM::VST1d32TPseudo:
4682
0
    case ARM::VST1d32TPseudoWB_fixed:
4683
0
    case ARM::VST1d32TPseudoWB_register:
4684
0
    case ARM::VST1d64QPseudo:
4685
0
    case ARM::VST1d64QPseudoWB_fixed:
4686
0
    case ARM::VST1d64QPseudoWB_register:
4687
0
    case ARM::VST1d64TPseudo:
4688
0
    case ARM::VST1d64TPseudoWB_fixed:
4689
0
    case ARM::VST1d64TPseudoWB_register:
4690
0
    case ARM::VST1q8HighQPseudo:
4691
0
    case ARM::VST1q8HighQPseudo_UPD:
4692
0
    case ARM::VST1q8HighTPseudo:
4693
0
    case ARM::VST1q8HighTPseudo_UPD:
4694
0
    case ARM::VST1q8LowQPseudo_UPD:
4695
0
    case ARM::VST1q8LowTPseudo_UPD:
4696
0
    case ARM::VST1q16HighQPseudo:
4697
0
    case ARM::VST1q16HighQPseudo_UPD:
4698
0
    case ARM::VST1q16HighTPseudo:
4699
0
    case ARM::VST1q16HighTPseudo_UPD:
4700
0
    case ARM::VST1q16LowQPseudo_UPD:
4701
0
    case ARM::VST1q16LowTPseudo_UPD:
4702
0
    case ARM::VST1q32HighQPseudo:
4703
0
    case ARM::VST1q32HighQPseudo_UPD:
4704
0
    case ARM::VST1q32HighTPseudo:
4705
0
    case ARM::VST1q32HighTPseudo_UPD:
4706
0
    case ARM::VST1q32LowQPseudo_UPD:
4707
0
    case ARM::VST1q32LowTPseudo_UPD:
4708
0
    case ARM::VST1q64HighQPseudo:
4709
0
    case ARM::VST1q64HighQPseudo_UPD:
4710
0
    case ARM::VST1q64HighTPseudo:
4711
0
    case ARM::VST1q64HighTPseudo_UPD:
4712
0
    case ARM::VST1q64LowQPseudo_UPD:
4713
0
    case ARM::VST1q64LowTPseudo_UPD:
4714
0
    case ARM::VST2LNd8Pseudo:
4715
0
    case ARM::VST2LNd8Pseudo_UPD:
4716
0
    case ARM::VST2LNd16Pseudo:
4717
0
    case ARM::VST2LNd16Pseudo_UPD:
4718
0
    case ARM::VST2LNd32Pseudo:
4719
0
    case ARM::VST2LNd32Pseudo_UPD:
4720
0
    case ARM::VST2LNq16Pseudo:
4721
0
    case ARM::VST2LNq16Pseudo_UPD:
4722
0
    case ARM::VST2LNq32Pseudo:
4723
0
    case ARM::VST2LNq32Pseudo_UPD:
4724
0
    case ARM::VST2q8Pseudo:
4725
0
    case ARM::VST2q8PseudoWB_fixed:
4726
0
    case ARM::VST2q8PseudoWB_register:
4727
0
    case ARM::VST2q16Pseudo:
4728
0
    case ARM::VST2q16PseudoWB_fixed:
4729
0
    case ARM::VST2q16PseudoWB_register:
4730
0
    case ARM::VST2q32Pseudo:
4731
0
    case ARM::VST2q32PseudoWB_fixed:
4732
0
    case ARM::VST2q32PseudoWB_register:
4733
0
    case ARM::VST3LNd8Pseudo:
4734
0
    case ARM::VST3LNd8Pseudo_UPD:
4735
0
    case ARM::VST3LNd16Pseudo:
4736
0
    case ARM::VST3LNd16Pseudo_UPD:
4737
0
    case ARM::VST3LNd32Pseudo:
4738
0
    case ARM::VST3LNd32Pseudo_UPD:
4739
0
    case ARM::VST3LNq16Pseudo:
4740
0
    case ARM::VST3LNq16Pseudo_UPD:
4741
0
    case ARM::VST3LNq32Pseudo:
4742
0
    case ARM::VST3LNq32Pseudo_UPD:
4743
0
    case ARM::VST3d8Pseudo:
4744
0
    case ARM::VST3d8Pseudo_UPD:
4745
0
    case ARM::VST3d16Pseudo:
4746
0
    case ARM::VST3d16Pseudo_UPD:
4747
0
    case ARM::VST3d32Pseudo:
4748
0
    case ARM::VST3d32Pseudo_UPD:
4749
0
    case ARM::VST3q8Pseudo_UPD:
4750
0
    case ARM::VST3q8oddPseudo:
4751
0
    case ARM::VST3q8oddPseudo_UPD:
4752
0
    case ARM::VST3q16Pseudo_UPD:
4753
0
    case ARM::VST3q16oddPseudo:
4754
0
    case ARM::VST3q16oddPseudo_UPD:
4755
0
    case ARM::VST3q32Pseudo_UPD:
4756
0
    case ARM::VST3q32oddPseudo:
4757
0
    case ARM::VST3q32oddPseudo_UPD:
4758
0
    case ARM::VST4LNd8Pseudo:
4759
0
    case ARM::VST4LNd8Pseudo_UPD:
4760
0
    case ARM::VST4LNd16Pseudo:
4761
0
    case ARM::VST4LNd16Pseudo_UPD:
4762
0
    case ARM::VST4LNd32Pseudo:
4763
0
    case ARM::VST4LNd32Pseudo_UPD:
4764
0
    case ARM::VST4LNq16Pseudo:
4765
0
    case ARM::VST4LNq16Pseudo_UPD:
4766
0
    case ARM::VST4LNq32Pseudo:
4767
0
    case ARM::VST4LNq32Pseudo_UPD:
4768
0
    case ARM::VST4d8Pseudo:
4769
0
    case ARM::VST4d8Pseudo_UPD:
4770
0
    case ARM::VST4d16Pseudo:
4771
0
    case ARM::VST4d16Pseudo_UPD:
4772
0
    case ARM::VST4d32Pseudo:
4773
0
    case ARM::VST4d32Pseudo_UPD:
4774
0
    case ARM::VST4q8Pseudo_UPD:
4775
0
    case ARM::VST4q8oddPseudo:
4776
0
    case ARM::VST4q8oddPseudo_UPD:
4777
0
    case ARM::VST4q16Pseudo_UPD:
4778
0
    case ARM::VST4q16oddPseudo:
4779
0
    case ARM::VST4q16oddPseudo_UPD:
4780
0
    case ARM::VST4q32Pseudo_UPD:
4781
0
    case ARM::VST4q32oddPseudo:
4782
0
    case ARM::VST4q32oddPseudo_UPD:
4783
0
    case ARM::VSTMQIA:
4784
0
    case ARM::VTBL3Pseudo:
4785
0
    case ARM::VTBL4Pseudo:
4786
0
    case ARM::VTBX3Pseudo:
4787
0
    case ARM::VTBX4Pseudo:
4788
0
    case ARM::t2AUT:
4789
0
    case ARM::t2BTI:
4790
0
    case ARM::t2CLREX:
4791
0
    case ARM::t2DCPS1:
4792
0
    case ARM::t2DCPS2:
4793
0
    case ARM::t2DCPS3:
4794
0
    case ARM::t2Int_eh_sjlj_setjmp:
4795
0
    case ARM::t2Int_eh_sjlj_setjmp_nofp:
4796
0
    case ARM::t2PAC:
4797
0
    case ARM::t2PACBTI:
4798
0
    case ARM::t2SB:
4799
0
    case ARM::t2SG:
4800
0
    case ARM::t2TSB:
4801
0
    case ARM::tInt_WIN_eh_sjlj_longjmp:
4802
0
    case ARM::tInt_eh_sjlj_longjmp:
4803
0
    case ARM::tInt_eh_sjlj_setjmp:
4804
0
    case ARM::tTRAP:
4805
0
    case ARM::t__brkdiv0: {
4806
0
      break;
4807
0
    }
4808
0
    case ARM::VRINTAD:
4809
0
    case ARM::VRINTMD:
4810
0
    case ARM::VRINTND:
4811
0
    case ARM::VRINTPD: {
4812
      // op: Dd
4813
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4814
0
      Value |= (op & UINT64_C(16)) << 18;
4815
0
      Value |= (op & UINT64_C(15)) << 12;
4816
      // op: Dm
4817
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4818
0
      Value |= (op & UINT64_C(16)) << 1;
4819
0
      Value |= (op & UINT64_C(15));
4820
0
      break;
4821
0
    }
4822
0
    case ARM::VFP_VMAXNMD:
4823
0
    case ARM::VFP_VMINNMD:
4824
0
    case ARM::VSELEQD:
4825
0
    case ARM::VSELGED:
4826
0
    case ARM::VSELGTD:
4827
0
    case ARM::VSELVSD: {
4828
      // op: Dd
4829
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4830
0
      Value |= (op & UINT64_C(16)) << 18;
4831
0
      Value |= (op & UINT64_C(15)) << 12;
4832
      // op: Dn
4833
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4834
0
      Value |= (op & UINT64_C(15)) << 16;
4835
0
      Value |= (op & UINT64_C(16)) << 3;
4836
      // op: Dm
4837
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4838
0
      Value |= (op & UINT64_C(16)) << 1;
4839
0
      Value |= (op & UINT64_C(15));
4840
0
      break;
4841
0
    }
4842
0
    case ARM::MVE_VPST: {
4843
      // op: Mk
4844
0
      op = getVPTMaskOpValue(MI, 0, Fixups, STI);
4845
0
      Value |= (op & UINT64_C(8)) << 19;
4846
0
      Value |= (op & UINT64_C(7)) << 13;
4847
0
      break;
4848
0
    }
4849
0
    case ARM::MVE_VDUP8:
4850
0
    case ARM::MVE_VDUP16:
4851
0
    case ARM::MVE_VDUP32: {
4852
      // op: Qd
4853
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4854
0
      Value |= (op & UINT64_C(7)) << 17;
4855
0
      Value |= (op & UINT64_C(8)) << 4;
4856
      // op: Rt
4857
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4858
0
      op &= UINT64_C(15);
4859
0
      op <<= 12;
4860
0
      Value |= op;
4861
0
      break;
4862
0
    }
4863
0
    case ARM::MVE_VMOV_to_lane_32: {
4864
      // op: Qd
4865
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4866
0
      Value |= (op & UINT64_C(7)) << 17;
4867
0
      Value |= (op & UINT64_C(8)) << 4;
4868
      // op: Rt
4869
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4870
0
      op &= UINT64_C(15);
4871
0
      op <<= 12;
4872
0
      Value |= op;
4873
      // op: Idx
4874
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4875
0
      Value |= (op & UINT64_C(1)) << 21;
4876
0
      Value |= (op & UINT64_C(2)) << 15;
4877
0
      break;
4878
0
    }
4879
0
    case ARM::MVE_VMOV_to_lane_16: {
4880
      // op: Qd
4881
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4882
0
      Value |= (op & UINT64_C(7)) << 17;
4883
0
      Value |= (op & UINT64_C(8)) << 4;
4884
      // op: Rt
4885
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4886
0
      op &= UINT64_C(15);
4887
0
      op <<= 12;
4888
0
      Value |= op;
4889
      // op: Idx
4890
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4891
0
      Value |= (op & UINT64_C(2)) << 20;
4892
0
      Value |= (op & UINT64_C(4)) << 14;
4893
0
      Value |= (op & UINT64_C(1)) << 6;
4894
0
      break;
4895
0
    }
4896
0
    case ARM::MVE_VMOV_to_lane_8: {
4897
      // op: Qd
4898
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4899
0
      Value |= (op & UINT64_C(7)) << 17;
4900
0
      Value |= (op & UINT64_C(8)) << 4;
4901
      // op: Rt
4902
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4903
0
      op &= UINT64_C(15);
4904
0
      op <<= 12;
4905
0
      Value |= op;
4906
      // op: Idx
4907
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4908
0
      Value |= (op & UINT64_C(4)) << 19;
4909
0
      Value |= (op & UINT64_C(8)) << 13;
4910
0
      Value |= (op & UINT64_C(3)) << 5;
4911
0
      break;
4912
0
    }
4913
0
    case ARM::MVE_VABSs8:
4914
0
    case ARM::MVE_VABSs16:
4915
0
    case ARM::MVE_VABSs32:
4916
0
    case ARM::MVE_VCLSs8:
4917
0
    case ARM::MVE_VCLSs16:
4918
0
    case ARM::MVE_VCLSs32:
4919
0
    case ARM::MVE_VCLZs8:
4920
0
    case ARM::MVE_VCLZs16:
4921
0
    case ARM::MVE_VCLZs32:
4922
0
    case ARM::MVE_VCVTf32f16bh:
4923
0
    case ARM::MVE_VCVTf32f16th:
4924
0
    case ARM::MVE_VMOVLs8bh:
4925
0
    case ARM::MVE_VMOVLs8th:
4926
0
    case ARM::MVE_VMOVLs16bh:
4927
0
    case ARM::MVE_VMOVLs16th:
4928
0
    case ARM::MVE_VMOVLu8bh:
4929
0
    case ARM::MVE_VMOVLu8th:
4930
0
    case ARM::MVE_VMOVLu16bh:
4931
0
    case ARM::MVE_VMOVLu16th:
4932
0
    case ARM::MVE_VMVN:
4933
0
    case ARM::MVE_VNEGs8:
4934
0
    case ARM::MVE_VNEGs16:
4935
0
    case ARM::MVE_VNEGs32:
4936
0
    case ARM::MVE_VQABSs8:
4937
0
    case ARM::MVE_VQABSs16:
4938
0
    case ARM::MVE_VQABSs32:
4939
0
    case ARM::MVE_VQNEGs8:
4940
0
    case ARM::MVE_VQNEGs16:
4941
0
    case ARM::MVE_VQNEGs32:
4942
0
    case ARM::MVE_VREV16_8:
4943
0
    case ARM::MVE_VREV32_8:
4944
0
    case ARM::MVE_VREV32_16:
4945
0
    case ARM::MVE_VREV64_8:
4946
0
    case ARM::MVE_VREV64_16:
4947
0
    case ARM::MVE_VREV64_32:
4948
0
    case ARM::MVE_VSHLL_lws8bh:
4949
0
    case ARM::MVE_VSHLL_lws8th:
4950
0
    case ARM::MVE_VSHLL_lws16bh:
4951
0
    case ARM::MVE_VSHLL_lws16th:
4952
0
    case ARM::MVE_VSHLL_lwu8bh:
4953
0
    case ARM::MVE_VSHLL_lwu8th:
4954
0
    case ARM::MVE_VSHLL_lwu16bh:
4955
0
    case ARM::MVE_VSHLL_lwu16th: {
4956
      // op: Qd
4957
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4958
0
      Value |= (op & UINT64_C(8)) << 19;
4959
0
      Value |= (op & UINT64_C(7)) << 13;
4960
      // op: Qm
4961
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4962
0
      Value |= (op & UINT64_C(8)) << 2;
4963
0
      Value |= (op & UINT64_C(7)) << 1;
4964
0
      break;
4965
0
    }
4966
0
    case ARM::MVE_VQRSHL_by_vecs8:
4967
0
    case ARM::MVE_VQRSHL_by_vecs16:
4968
0
    case ARM::MVE_VQRSHL_by_vecs32:
4969
0
    case ARM::MVE_VQRSHL_by_vecu8:
4970
0
    case ARM::MVE_VQRSHL_by_vecu16:
4971
0
    case ARM::MVE_VQRSHL_by_vecu32:
4972
0
    case ARM::MVE_VQSHL_by_vecs8:
4973
0
    case ARM::MVE_VQSHL_by_vecs16:
4974
0
    case ARM::MVE_VQSHL_by_vecs32:
4975
0
    case ARM::MVE_VQSHL_by_vecu8:
4976
0
    case ARM::MVE_VQSHL_by_vecu16:
4977
0
    case ARM::MVE_VQSHL_by_vecu32:
4978
0
    case ARM::MVE_VRSHL_by_vecs8:
4979
0
    case ARM::MVE_VRSHL_by_vecs16:
4980
0
    case ARM::MVE_VRSHL_by_vecs32:
4981
0
    case ARM::MVE_VRSHL_by_vecu8:
4982
0
    case ARM::MVE_VRSHL_by_vecu16:
4983
0
    case ARM::MVE_VRSHL_by_vecu32:
4984
0
    case ARM::MVE_VSHL_by_vecs8:
4985
0
    case ARM::MVE_VSHL_by_vecs16:
4986
0
    case ARM::MVE_VSHL_by_vecs32:
4987
0
    case ARM::MVE_VSHL_by_vecu8:
4988
0
    case ARM::MVE_VSHL_by_vecu16:
4989
0
    case ARM::MVE_VSHL_by_vecu32: {
4990
      // op: Qd
4991
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4992
0
      Value |= (op & UINT64_C(8)) << 19;
4993
0
      Value |= (op & UINT64_C(7)) << 13;
4994
      // op: Qm
4995
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4996
0
      Value |= (op & UINT64_C(8)) << 2;
4997
0
      Value |= (op & UINT64_C(7)) << 1;
4998
      // op: Qn
4999
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5000
0
      Value |= (op & UINT64_C(7)) << 17;
5001
0
      Value |= (op & UINT64_C(8)) << 4;
5002
0
      break;
5003
0
    }
5004
0
    case ARM::MVE_VSHLL_imms16bh:
5005
0
    case ARM::MVE_VSHLL_imms16th:
5006
0
    case ARM::MVE_VSHLL_immu16bh:
5007
0
    case ARM::MVE_VSHLL_immu16th: {
5008
      // op: Qd
5009
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5010
0
      Value |= (op & UINT64_C(8)) << 19;
5011
0
      Value |= (op & UINT64_C(7)) << 13;
5012
      // op: Qm
5013
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5014
0
      Value |= (op & UINT64_C(8)) << 2;
5015
0
      Value |= (op & UINT64_C(7)) << 1;
5016
      // op: imm
5017
0
      op = getMVEShiftImmOpValue(MI, 2, Fixups, STI);
5018
0
      op &= UINT64_C(15);
5019
0
      op <<= 16;
5020
0
      Value |= op;
5021
0
      break;
5022
0
    }
5023
0
    case ARM::MVE_VSHLL_imms8bh:
5024
0
    case ARM::MVE_VSHLL_imms8th:
5025
0
    case ARM::MVE_VSHLL_immu8bh:
5026
0
    case ARM::MVE_VSHLL_immu8th: {
5027
      // op: Qd
5028
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5029
0
      Value |= (op & UINT64_C(8)) << 19;
5030
0
      Value |= (op & UINT64_C(7)) << 13;
5031
      // op: Qm
5032
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5033
0
      Value |= (op & UINT64_C(8)) << 2;
5034
0
      Value |= (op & UINT64_C(7)) << 1;
5035
      // op: imm
5036
0
      op = getMVEShiftImmOpValue(MI, 2, Fixups, STI);
5037
0
      op &= UINT64_C(7);
5038
0
      op <<= 16;
5039
0
      Value |= op;
5040
0
      break;
5041
0
    }
5042
0
    case ARM::MVE_VQSHLU_imms16:
5043
0
    case ARM::MVE_VQSHLimms16:
5044
0
    case ARM::MVE_VQSHLimmu16:
5045
0
    case ARM::MVE_VSHL_immi16: {
5046
      // op: Qd
5047
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5048
0
      Value |= (op & UINT64_C(8)) << 19;
5049
0
      Value |= (op & UINT64_C(7)) << 13;
5050
      // op: Qm
5051
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5052
0
      Value |= (op & UINT64_C(8)) << 2;
5053
0
      Value |= (op & UINT64_C(7)) << 1;
5054
      // op: imm
5055
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5056
0
      op &= UINT64_C(15);
5057
0
      op <<= 16;
5058
0
      Value |= op;
5059
0
      break;
5060
0
    }
5061
0
    case ARM::MVE_VQSHLU_imms32:
5062
0
    case ARM::MVE_VQSHLimms32:
5063
0
    case ARM::MVE_VQSHLimmu32:
5064
0
    case ARM::MVE_VSHL_immi32: {
5065
      // op: Qd
5066
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5067
0
      Value |= (op & UINT64_C(8)) << 19;
5068
0
      Value |= (op & UINT64_C(7)) << 13;
5069
      // op: Qm
5070
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5071
0
      Value |= (op & UINT64_C(8)) << 2;
5072
0
      Value |= (op & UINT64_C(7)) << 1;
5073
      // op: imm
5074
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5075
0
      op &= UINT64_C(31);
5076
0
      op <<= 16;
5077
0
      Value |= op;
5078
0
      break;
5079
0
    }
5080
0
    case ARM::MVE_VQSHLU_imms8:
5081
0
    case ARM::MVE_VQSHLimms8:
5082
0
    case ARM::MVE_VQSHLimmu8:
5083
0
    case ARM::MVE_VSHL_immi8: {
5084
      // op: Qd
5085
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5086
0
      Value |= (op & UINT64_C(8)) << 19;
5087
0
      Value |= (op & UINT64_C(7)) << 13;
5088
      // op: Qm
5089
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5090
0
      Value |= (op & UINT64_C(8)) << 2;
5091
0
      Value |= (op & UINT64_C(7)) << 1;
5092
      // op: imm
5093
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5094
0
      op &= UINT64_C(7);
5095
0
      op <<= 16;
5096
0
      Value |= op;
5097
0
      break;
5098
0
    }
5099
0
    case ARM::MVE_VRSHR_imms16:
5100
0
    case ARM::MVE_VRSHR_immu16:
5101
0
    case ARM::MVE_VSHR_imms16:
5102
0
    case ARM::MVE_VSHR_immu16: {
5103
      // op: Qd
5104
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5105
0
      Value |= (op & UINT64_C(8)) << 19;
5106
0
      Value |= (op & UINT64_C(7)) << 13;
5107
      // op: Qm
5108
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5109
0
      Value |= (op & UINT64_C(8)) << 2;
5110
0
      Value |= (op & UINT64_C(7)) << 1;
5111
      // op: imm
5112
0
      op = getShiftRight16Imm(MI, 2, Fixups, STI);
5113
0
      op &= UINT64_C(15);
5114
0
      op <<= 16;
5115
0
      Value |= op;
5116
0
      break;
5117
0
    }
5118
0
    case ARM::MVE_VRSHR_imms32:
5119
0
    case ARM::MVE_VRSHR_immu32:
5120
0
    case ARM::MVE_VSHR_imms32:
5121
0
    case ARM::MVE_VSHR_immu32: {
5122
      // op: Qd
5123
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5124
0
      Value |= (op & UINT64_C(8)) << 19;
5125
0
      Value |= (op & UINT64_C(7)) << 13;
5126
      // op: Qm
5127
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5128
0
      Value |= (op & UINT64_C(8)) << 2;
5129
0
      Value |= (op & UINT64_C(7)) << 1;
5130
      // op: imm
5131
0
      op = getShiftRight32Imm(MI, 2, Fixups, STI);
5132
0
      op &= UINT64_C(31);
5133
0
      op <<= 16;
5134
0
      Value |= op;
5135
0
      break;
5136
0
    }
5137
0
    case ARM::MVE_VRSHR_imms8:
5138
0
    case ARM::MVE_VRSHR_immu8:
5139
0
    case ARM::MVE_VSHR_imms8:
5140
0
    case ARM::MVE_VSHR_immu8: {
5141
      // op: Qd
5142
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5143
0
      Value |= (op & UINT64_C(8)) << 19;
5144
0
      Value |= (op & UINT64_C(7)) << 13;
5145
      // op: Qm
5146
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5147
0
      Value |= (op & UINT64_C(8)) << 2;
5148
0
      Value |= (op & UINT64_C(7)) << 1;
5149
      // op: imm
5150
0
      op = getShiftRight8Imm(MI, 2, Fixups, STI);
5151
0
      op &= UINT64_C(7);
5152
0
      op <<= 16;
5153
0
      Value |= op;
5154
0
      break;
5155
0
    }
5156
0
    case ARM::MVE_VCVTf16f32bh:
5157
0
    case ARM::MVE_VCVTf16f32th:
5158
0
    case ARM::MVE_VMAXAs8:
5159
0
    case ARM::MVE_VMAXAs16:
5160
0
    case ARM::MVE_VMAXAs32:
5161
0
    case ARM::MVE_VMAXNMAf16:
5162
0
    case ARM::MVE_VMAXNMAf32:
5163
0
    case ARM::MVE_VMINAs8:
5164
0
    case ARM::MVE_VMINAs16:
5165
0
    case ARM::MVE_VMINAs32:
5166
0
    case ARM::MVE_VMINNMAf16:
5167
0
    case ARM::MVE_VMINNMAf32:
5168
0
    case ARM::MVE_VMOVNi16bh:
5169
0
    case ARM::MVE_VMOVNi16th:
5170
0
    case ARM::MVE_VMOVNi32bh:
5171
0
    case ARM::MVE_VMOVNi32th:
5172
0
    case ARM::MVE_VQMOVNs16bh:
5173
0
    case ARM::MVE_VQMOVNs16th:
5174
0
    case ARM::MVE_VQMOVNs32bh:
5175
0
    case ARM::MVE_VQMOVNs32th:
5176
0
    case ARM::MVE_VQMOVNu16bh:
5177
0
    case ARM::MVE_VQMOVNu16th:
5178
0
    case ARM::MVE_VQMOVNu32bh:
5179
0
    case ARM::MVE_VQMOVNu32th:
5180
0
    case ARM::MVE_VQMOVUNs16bh:
5181
0
    case ARM::MVE_VQMOVUNs16th:
5182
0
    case ARM::MVE_VQMOVUNs32bh:
5183
0
    case ARM::MVE_VQMOVUNs32th: {
5184
      // op: Qd
5185
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5186
0
      Value |= (op & UINT64_C(8)) << 19;
5187
0
      Value |= (op & UINT64_C(7)) << 13;
5188
      // op: Qm
5189
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5190
0
      Value |= (op & UINT64_C(8)) << 2;
5191
0
      Value |= (op & UINT64_C(7)) << 1;
5192
0
      break;
5193
0
    }
5194
0
    case ARM::MVE_VAND:
5195
0
    case ARM::MVE_VBIC:
5196
0
    case ARM::MVE_VEOR:
5197
0
    case ARM::MVE_VMULHs8:
5198
0
    case ARM::MVE_VMULHs16:
5199
0
    case ARM::MVE_VMULHs32:
5200
0
    case ARM::MVE_VMULHu8:
5201
0
    case ARM::MVE_VMULHu16:
5202
0
    case ARM::MVE_VMULHu32:
5203
0
    case ARM::MVE_VMULLBp8:
5204
0
    case ARM::MVE_VMULLBp16:
5205
0
    case ARM::MVE_VMULLBs8:
5206
0
    case ARM::MVE_VMULLBs16:
5207
0
    case ARM::MVE_VMULLBs32:
5208
0
    case ARM::MVE_VMULLBu8:
5209
0
    case ARM::MVE_VMULLBu16:
5210
0
    case ARM::MVE_VMULLBu32:
5211
0
    case ARM::MVE_VMULLTp8:
5212
0
    case ARM::MVE_VMULLTp16:
5213
0
    case ARM::MVE_VMULLTs8:
5214
0
    case ARM::MVE_VMULLTs16:
5215
0
    case ARM::MVE_VMULLTs32:
5216
0
    case ARM::MVE_VMULLTu8:
5217
0
    case ARM::MVE_VMULLTu16:
5218
0
    case ARM::MVE_VMULLTu32:
5219
0
    case ARM::MVE_VORN:
5220
0
    case ARM::MVE_VORR:
5221
0
    case ARM::MVE_VQDMULLs16bh:
5222
0
    case ARM::MVE_VQDMULLs16th:
5223
0
    case ARM::MVE_VQDMULLs32bh:
5224
0
    case ARM::MVE_VQDMULLs32th:
5225
0
    case ARM::MVE_VRMULHs8:
5226
0
    case ARM::MVE_VRMULHs16:
5227
0
    case ARM::MVE_VRMULHs32:
5228
0
    case ARM::MVE_VRMULHu8:
5229
0
    case ARM::MVE_VRMULHu16:
5230
0
    case ARM::MVE_VRMULHu32: {
5231
      // op: Qd
5232
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5233
0
      Value |= (op & UINT64_C(8)) << 19;
5234
0
      Value |= (op & UINT64_C(7)) << 13;
5235
      // op: Qm
5236
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5237
0
      Value |= (op & UINT64_C(8)) << 2;
5238
0
      Value |= (op & UINT64_C(7)) << 1;
5239
      // op: Qn
5240
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5241
0
      Value |= (op & UINT64_C(7)) << 17;
5242
0
      Value |= (op & UINT64_C(8)) << 4;
5243
0
      break;
5244
0
    }
5245
0
    case ARM::MVE_VCMULf16:
5246
0
    case ARM::MVE_VCMULf32: {
5247
      // op: Qd
5248
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5249
0
      Value |= (op & UINT64_C(8)) << 19;
5250
0
      Value |= (op & UINT64_C(7)) << 13;
5251
      // op: Qm
5252
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5253
0
      Value |= (op & UINT64_C(8)) << 2;
5254
0
      Value |= (op & UINT64_C(7)) << 1;
5255
      // op: Qn
5256
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5257
0
      Value |= (op & UINT64_C(7)) << 17;
5258
0
      Value |= (op & UINT64_C(8)) << 4;
5259
      // op: rot
5260
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5261
0
      Value |= (op & UINT64_C(2)) << 11;
5262
0
      Value |= (op & UINT64_C(1));
5263
0
      break;
5264
0
    }
5265
0
    case ARM::MVE_VCADDi8:
5266
0
    case ARM::MVE_VCADDi16:
5267
0
    case ARM::MVE_VCADDi32:
5268
0
    case ARM::MVE_VHCADDs8:
5269
0
    case ARM::MVE_VHCADDs16:
5270
0
    case ARM::MVE_VHCADDs32: {
5271
      // op: Qd
5272
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5273
0
      Value |= (op & UINT64_C(8)) << 19;
5274
0
      Value |= (op & UINT64_C(7)) << 13;
5275
      // op: Qm
5276
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5277
0
      Value |= (op & UINT64_C(8)) << 2;
5278
0
      Value |= (op & UINT64_C(7)) << 1;
5279
      // op: Qn
5280
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5281
0
      Value |= (op & UINT64_C(7)) << 17;
5282
0
      Value |= (op & UINT64_C(8)) << 4;
5283
      // op: rot
5284
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5285
0
      op &= UINT64_C(1);
5286
0
      op <<= 12;
5287
0
      Value |= op;
5288
0
      break;
5289
0
    }
5290
0
    case ARM::MVE_VSLIimm16: {
5291
      // op: Qd
5292
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5293
0
      Value |= (op & UINT64_C(8)) << 19;
5294
0
      Value |= (op & UINT64_C(7)) << 13;
5295
      // op: Qm
5296
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5297
0
      Value |= (op & UINT64_C(8)) << 2;
5298
0
      Value |= (op & UINT64_C(7)) << 1;
5299
      // op: imm
5300
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5301
0
      op &= UINT64_C(15);
5302
0
      op <<= 16;
5303
0
      Value |= op;
5304
0
      break;
5305
0
    }
5306
0
    case ARM::MVE_VSLIimm32: {
5307
      // op: Qd
5308
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5309
0
      Value |= (op & UINT64_C(8)) << 19;
5310
0
      Value |= (op & UINT64_C(7)) << 13;
5311
      // op: Qm
5312
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5313
0
      Value |= (op & UINT64_C(8)) << 2;
5314
0
      Value |= (op & UINT64_C(7)) << 1;
5315
      // op: imm
5316
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5317
0
      op &= UINT64_C(31);
5318
0
      op <<= 16;
5319
0
      Value |= op;
5320
0
      break;
5321
0
    }
5322
0
    case ARM::MVE_VSLIimm8: {
5323
      // op: Qd
5324
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5325
0
      Value |= (op & UINT64_C(8)) << 19;
5326
0
      Value |= (op & UINT64_C(7)) << 13;
5327
      // op: Qm
5328
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5329
0
      Value |= (op & UINT64_C(8)) << 2;
5330
0
      Value |= (op & UINT64_C(7)) << 1;
5331
      // op: imm
5332
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5333
0
      op &= UINT64_C(7);
5334
0
      op <<= 16;
5335
0
      Value |= op;
5336
0
      break;
5337
0
    }
5338
0
    case ARM::MVE_VQRSHRNbhs32:
5339
0
    case ARM::MVE_VQRSHRNbhu32:
5340
0
    case ARM::MVE_VQRSHRNths32:
5341
0
    case ARM::MVE_VQRSHRNthu32:
5342
0
    case ARM::MVE_VQRSHRUNs32bh:
5343
0
    case ARM::MVE_VQRSHRUNs32th:
5344
0
    case ARM::MVE_VQSHRNbhs32:
5345
0
    case ARM::MVE_VQSHRNbhu32:
5346
0
    case ARM::MVE_VQSHRNths32:
5347
0
    case ARM::MVE_VQSHRNthu32:
5348
0
    case ARM::MVE_VQSHRUNs32bh:
5349
0
    case ARM::MVE_VQSHRUNs32th:
5350
0
    case ARM::MVE_VRSHRNi32bh:
5351
0
    case ARM::MVE_VRSHRNi32th:
5352
0
    case ARM::MVE_VSHRNi32bh:
5353
0
    case ARM::MVE_VSHRNi32th:
5354
0
    case ARM::MVE_VSRIimm16: {
5355
      // op: Qd
5356
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5357
0
      Value |= (op & UINT64_C(8)) << 19;
5358
0
      Value |= (op & UINT64_C(7)) << 13;
5359
      // op: Qm
5360
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5361
0
      Value |= (op & UINT64_C(8)) << 2;
5362
0
      Value |= (op & UINT64_C(7)) << 1;
5363
      // op: imm
5364
0
      op = getShiftRight16Imm(MI, 3, Fixups, STI);
5365
0
      op &= UINT64_C(15);
5366
0
      op <<= 16;
5367
0
      Value |= op;
5368
0
      break;
5369
0
    }
5370
0
    case ARM::MVE_VSRIimm32: {
5371
      // op: Qd
5372
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5373
0
      Value |= (op & UINT64_C(8)) << 19;
5374
0
      Value |= (op & UINT64_C(7)) << 13;
5375
      // op: Qm
5376
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5377
0
      Value |= (op & UINT64_C(8)) << 2;
5378
0
      Value |= (op & UINT64_C(7)) << 1;
5379
      // op: imm
5380
0
      op = getShiftRight32Imm(MI, 3, Fixups, STI);
5381
0
      op &= UINT64_C(31);
5382
0
      op <<= 16;
5383
0
      Value |= op;
5384
0
      break;
5385
0
    }
5386
0
    case ARM::MVE_VQRSHRNbhs16:
5387
0
    case ARM::MVE_VQRSHRNbhu16:
5388
0
    case ARM::MVE_VQRSHRNths16:
5389
0
    case ARM::MVE_VQRSHRNthu16:
5390
0
    case ARM::MVE_VQRSHRUNs16bh:
5391
0
    case ARM::MVE_VQRSHRUNs16th:
5392
0
    case ARM::MVE_VQSHRNbhs16:
5393
0
    case ARM::MVE_VQSHRNbhu16:
5394
0
    case ARM::MVE_VQSHRNths16:
5395
0
    case ARM::MVE_VQSHRNthu16:
5396
0
    case ARM::MVE_VQSHRUNs16bh:
5397
0
    case ARM::MVE_VQSHRUNs16th:
5398
0
    case ARM::MVE_VRSHRNi16bh:
5399
0
    case ARM::MVE_VRSHRNi16th:
5400
0
    case ARM::MVE_VSHRNi16bh:
5401
0
    case ARM::MVE_VSHRNi16th:
5402
0
    case ARM::MVE_VSRIimm8: {
5403
      // op: Qd
5404
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5405
0
      Value |= (op & UINT64_C(8)) << 19;
5406
0
      Value |= (op & UINT64_C(7)) << 13;
5407
      // op: Qm
5408
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5409
0
      Value |= (op & UINT64_C(8)) << 2;
5410
0
      Value |= (op & UINT64_C(7)) << 1;
5411
      // op: imm
5412
0
      op = getShiftRight8Imm(MI, 3, Fixups, STI);
5413
0
      op &= UINT64_C(7);
5414
0
      op <<= 16;
5415
0
      Value |= op;
5416
0
      break;
5417
0
    }
5418
0
    case ARM::MVE_VADC:
5419
0
    case ARM::MVE_VADCI:
5420
0
    case ARM::MVE_VQDMLADHXs8:
5421
0
    case ARM::MVE_VQDMLADHXs16:
5422
0
    case ARM::MVE_VQDMLADHXs32:
5423
0
    case ARM::MVE_VQDMLADHs8:
5424
0
    case ARM::MVE_VQDMLADHs16:
5425
0
    case ARM::MVE_VQDMLADHs32:
5426
0
    case ARM::MVE_VQDMLSDHXs8:
5427
0
    case ARM::MVE_VQDMLSDHXs16:
5428
0
    case ARM::MVE_VQDMLSDHXs32:
5429
0
    case ARM::MVE_VQDMLSDHs8:
5430
0
    case ARM::MVE_VQDMLSDHs16:
5431
0
    case ARM::MVE_VQDMLSDHs32:
5432
0
    case ARM::MVE_VQRDMLADHXs8:
5433
0
    case ARM::MVE_VQRDMLADHXs16:
5434
0
    case ARM::MVE_VQRDMLADHXs32:
5435
0
    case ARM::MVE_VQRDMLADHs8:
5436
0
    case ARM::MVE_VQRDMLADHs16:
5437
0
    case ARM::MVE_VQRDMLADHs32:
5438
0
    case ARM::MVE_VQRDMLSDHXs8:
5439
0
    case ARM::MVE_VQRDMLSDHXs16:
5440
0
    case ARM::MVE_VQRDMLSDHXs32:
5441
0
    case ARM::MVE_VQRDMLSDHs8:
5442
0
    case ARM::MVE_VQRDMLSDHs16:
5443
0
    case ARM::MVE_VQRDMLSDHs32:
5444
0
    case ARM::MVE_VSBC:
5445
0
    case ARM::MVE_VSBCI: {
5446
      // op: Qd
5447
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5448
0
      Value |= (op & UINT64_C(8)) << 19;
5449
0
      Value |= (op & UINT64_C(7)) << 13;
5450
      // op: Qm
5451
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5452
0
      Value |= (op & UINT64_C(8)) << 2;
5453
0
      Value |= (op & UINT64_C(7)) << 1;
5454
      // op: Qn
5455
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5456
0
      Value |= (op & UINT64_C(7)) << 17;
5457
0
      Value |= (op & UINT64_C(8)) << 4;
5458
0
      break;
5459
0
    }
5460
0
    case ARM::MVE_VABDs8:
5461
0
    case ARM::MVE_VABDs16:
5462
0
    case ARM::MVE_VABDs32:
5463
0
    case ARM::MVE_VABDu8:
5464
0
    case ARM::MVE_VABDu16:
5465
0
    case ARM::MVE_VABDu32:
5466
0
    case ARM::MVE_VADDi8:
5467
0
    case ARM::MVE_VADDi16:
5468
0
    case ARM::MVE_VADDi32:
5469
0
    case ARM::MVE_VHADDs8:
5470
0
    case ARM::MVE_VHADDs16:
5471
0
    case ARM::MVE_VHADDs32:
5472
0
    case ARM::MVE_VHADDu8:
5473
0
    case ARM::MVE_VHADDu16:
5474
0
    case ARM::MVE_VHADDu32:
5475
0
    case ARM::MVE_VHSUBs8:
5476
0
    case ARM::MVE_VHSUBs16:
5477
0
    case ARM::MVE_VHSUBs32:
5478
0
    case ARM::MVE_VHSUBu8:
5479
0
    case ARM::MVE_VHSUBu16:
5480
0
    case ARM::MVE_VHSUBu32:
5481
0
    case ARM::MVE_VMAXNMf16:
5482
0
    case ARM::MVE_VMAXNMf32:
5483
0
    case ARM::MVE_VMAXs8:
5484
0
    case ARM::MVE_VMAXs16:
5485
0
    case ARM::MVE_VMAXs32:
5486
0
    case ARM::MVE_VMAXu8:
5487
0
    case ARM::MVE_VMAXu16:
5488
0
    case ARM::MVE_VMAXu32:
5489
0
    case ARM::MVE_VMINNMf16:
5490
0
    case ARM::MVE_VMINNMf32:
5491
0
    case ARM::MVE_VMINs8:
5492
0
    case ARM::MVE_VMINs16:
5493
0
    case ARM::MVE_VMINs32:
5494
0
    case ARM::MVE_VMINu8:
5495
0
    case ARM::MVE_VMINu16:
5496
0
    case ARM::MVE_VMINu32:
5497
0
    case ARM::MVE_VMULi8:
5498
0
    case ARM::MVE_VMULi16:
5499
0
    case ARM::MVE_VMULi32:
5500
0
    case ARM::MVE_VQADDs8:
5501
0
    case ARM::MVE_VQADDs16:
5502
0
    case ARM::MVE_VQADDs32:
5503
0
    case ARM::MVE_VQADDu8:
5504
0
    case ARM::MVE_VQADDu16:
5505
0
    case ARM::MVE_VQADDu32:
5506
0
    case ARM::MVE_VQDMULHi8:
5507
0
    case ARM::MVE_VQDMULHi16:
5508
0
    case ARM::MVE_VQDMULHi32:
5509
0
    case ARM::MVE_VQRDMULHi8:
5510
0
    case ARM::MVE_VQRDMULHi16:
5511
0
    case ARM::MVE_VQRDMULHi32:
5512
0
    case ARM::MVE_VQSUBs8:
5513
0
    case ARM::MVE_VQSUBs16:
5514
0
    case ARM::MVE_VQSUBs32:
5515
0
    case ARM::MVE_VQSUBu8:
5516
0
    case ARM::MVE_VQSUBu16:
5517
0
    case ARM::MVE_VQSUBu32:
5518
0
    case ARM::MVE_VRHADDs8:
5519
0
    case ARM::MVE_VRHADDs16:
5520
0
    case ARM::MVE_VRHADDs32:
5521
0
    case ARM::MVE_VRHADDu8:
5522
0
    case ARM::MVE_VRHADDu16:
5523
0
    case ARM::MVE_VRHADDu32:
5524
0
    case ARM::MVE_VSUBi8:
5525
0
    case ARM::MVE_VSUBi16:
5526
0
    case ARM::MVE_VSUBi32: {
5527
      // op: Qd
5528
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5529
0
      Value |= (op & UINT64_C(8)) << 19;
5530
0
      Value |= (op & UINT64_C(7)) << 13;
5531
      // op: Qn
5532
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5533
0
      Value |= (op & UINT64_C(7)) << 17;
5534
0
      Value |= (op & UINT64_C(8)) << 4;
5535
      // op: Qm
5536
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5537
0
      Value |= (op & UINT64_C(8)) << 2;
5538
0
      Value |= (op & UINT64_C(7)) << 1;
5539
0
      break;
5540
0
    }
5541
0
    case ARM::MVE_VADD_qr_f16:
5542
0
    case ARM::MVE_VADD_qr_f32:
5543
0
    case ARM::MVE_VADD_qr_i8:
5544
0
    case ARM::MVE_VADD_qr_i16:
5545
0
    case ARM::MVE_VADD_qr_i32:
5546
0
    case ARM::MVE_VBRSR8:
5547
0
    case ARM::MVE_VBRSR16:
5548
0
    case ARM::MVE_VBRSR32:
5549
0
    case ARM::MVE_VHADD_qr_s8:
5550
0
    case ARM::MVE_VHADD_qr_s16:
5551
0
    case ARM::MVE_VHADD_qr_s32:
5552
0
    case ARM::MVE_VHADD_qr_u8:
5553
0
    case ARM::MVE_VHADD_qr_u16:
5554
0
    case ARM::MVE_VHADD_qr_u32:
5555
0
    case ARM::MVE_VHSUB_qr_s8:
5556
0
    case ARM::MVE_VHSUB_qr_s16:
5557
0
    case ARM::MVE_VHSUB_qr_s32:
5558
0
    case ARM::MVE_VHSUB_qr_u8:
5559
0
    case ARM::MVE_VHSUB_qr_u16:
5560
0
    case ARM::MVE_VHSUB_qr_u32:
5561
0
    case ARM::MVE_VMUL_qr_f16:
5562
0
    case ARM::MVE_VMUL_qr_f32:
5563
0
    case ARM::MVE_VMUL_qr_i8:
5564
0
    case ARM::MVE_VMUL_qr_i16:
5565
0
    case ARM::MVE_VMUL_qr_i32:
5566
0
    case ARM::MVE_VQADD_qr_s8:
5567
0
    case ARM::MVE_VQADD_qr_s16:
5568
0
    case ARM::MVE_VQADD_qr_s32:
5569
0
    case ARM::MVE_VQADD_qr_u8:
5570
0
    case ARM::MVE_VQADD_qr_u16:
5571
0
    case ARM::MVE_VQADD_qr_u32:
5572
0
    case ARM::MVE_VQDMULH_qr_s8:
5573
0
    case ARM::MVE_VQDMULH_qr_s16:
5574
0
    case ARM::MVE_VQDMULH_qr_s32:
5575
0
    case ARM::MVE_VQDMULL_qr_s16bh:
5576
0
    case ARM::MVE_VQDMULL_qr_s16th:
5577
0
    case ARM::MVE_VQDMULL_qr_s32bh:
5578
0
    case ARM::MVE_VQDMULL_qr_s32th:
5579
0
    case ARM::MVE_VQRDMULH_qr_s8:
5580
0
    case ARM::MVE_VQRDMULH_qr_s16:
5581
0
    case ARM::MVE_VQRDMULH_qr_s32:
5582
0
    case ARM::MVE_VQSUB_qr_s8:
5583
0
    case ARM::MVE_VQSUB_qr_s16:
5584
0
    case ARM::MVE_VQSUB_qr_s32:
5585
0
    case ARM::MVE_VQSUB_qr_u8:
5586
0
    case ARM::MVE_VQSUB_qr_u16:
5587
0
    case ARM::MVE_VQSUB_qr_u32:
5588
0
    case ARM::MVE_VSUB_qr_f16:
5589
0
    case ARM::MVE_VSUB_qr_f32:
5590
0
    case ARM::MVE_VSUB_qr_i8:
5591
0
    case ARM::MVE_VSUB_qr_i16:
5592
0
    case ARM::MVE_VSUB_qr_i32: {
5593
      // op: Qd
5594
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5595
0
      Value |= (op & UINT64_C(8)) << 19;
5596
0
      Value |= (op & UINT64_C(7)) << 13;
5597
      // op: Qn
5598
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5599
0
      Value |= (op & UINT64_C(7)) << 17;
5600
0
      Value |= (op & UINT64_C(8)) << 4;
5601
      // op: Rm
5602
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5603
0
      op &= UINT64_C(15);
5604
0
      Value |= op;
5605
0
      break;
5606
0
    }
5607
0
    case ARM::MVE_VFMA_qr_Sf16:
5608
0
    case ARM::MVE_VFMA_qr_Sf32:
5609
0
    case ARM::MVE_VFMA_qr_f16:
5610
0
    case ARM::MVE_VFMA_qr_f32:
5611
0
    case ARM::MVE_VMLAS_qr_i8:
5612
0
    case ARM::MVE_VMLAS_qr_i16:
5613
0
    case ARM::MVE_VMLAS_qr_i32:
5614
0
    case ARM::MVE_VMLA_qr_i8:
5615
0
    case ARM::MVE_VMLA_qr_i16:
5616
0
    case ARM::MVE_VMLA_qr_i32:
5617
0
    case ARM::MVE_VQDMLAH_qrs8:
5618
0
    case ARM::MVE_VQDMLAH_qrs16:
5619
0
    case ARM::MVE_VQDMLAH_qrs32:
5620
0
    case ARM::MVE_VQDMLASH_qrs8:
5621
0
    case ARM::MVE_VQDMLASH_qrs16:
5622
0
    case ARM::MVE_VQDMLASH_qrs32:
5623
0
    case ARM::MVE_VQRDMLAH_qrs8:
5624
0
    case ARM::MVE_VQRDMLAH_qrs16:
5625
0
    case ARM::MVE_VQRDMLAH_qrs32:
5626
0
    case ARM::MVE_VQRDMLASH_qrs8:
5627
0
    case ARM::MVE_VQRDMLASH_qrs16:
5628
0
    case ARM::MVE_VQRDMLASH_qrs32: {
5629
      // op: Qd
5630
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5631
0
      Value |= (op & UINT64_C(8)) << 19;
5632
0
      Value |= (op & UINT64_C(7)) << 13;
5633
      // op: Qn
5634
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5635
0
      Value |= (op & UINT64_C(7)) << 17;
5636
0
      Value |= (op & UINT64_C(8)) << 4;
5637
      // op: Rm
5638
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5639
0
      op &= UINT64_C(15);
5640
0
      Value |= op;
5641
0
      break;
5642
0
    }
5643
0
    case ARM::MVE_VQRSHL_qrs8:
5644
0
    case ARM::MVE_VQRSHL_qrs16:
5645
0
    case ARM::MVE_VQRSHL_qrs32:
5646
0
    case ARM::MVE_VQRSHL_qru8:
5647
0
    case ARM::MVE_VQRSHL_qru16:
5648
0
    case ARM::MVE_VQRSHL_qru32:
5649
0
    case ARM::MVE_VQSHL_qrs8:
5650
0
    case ARM::MVE_VQSHL_qrs16:
5651
0
    case ARM::MVE_VQSHL_qrs32:
5652
0
    case ARM::MVE_VQSHL_qru8:
5653
0
    case ARM::MVE_VQSHL_qru16:
5654
0
    case ARM::MVE_VQSHL_qru32:
5655
0
    case ARM::MVE_VRSHL_qrs8:
5656
0
    case ARM::MVE_VRSHL_qrs16:
5657
0
    case ARM::MVE_VRSHL_qrs32:
5658
0
    case ARM::MVE_VRSHL_qru8:
5659
0
    case ARM::MVE_VRSHL_qru16:
5660
0
    case ARM::MVE_VRSHL_qru32:
5661
0
    case ARM::MVE_VSHL_qrs8:
5662
0
    case ARM::MVE_VSHL_qrs16:
5663
0
    case ARM::MVE_VSHL_qrs32:
5664
0
    case ARM::MVE_VSHL_qru8:
5665
0
    case ARM::MVE_VSHL_qru16:
5666
0
    case ARM::MVE_VSHL_qru32: {
5667
      // op: Qd
5668
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5669
0
      Value |= (op & UINT64_C(8)) << 19;
5670
0
      Value |= (op & UINT64_C(7)) << 13;
5671
      // op: Rm
5672
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5673
0
      op &= UINT64_C(15);
5674
0
      Value |= op;
5675
0
      break;
5676
0
    }
5677
0
    case ARM::MVE_VDWDUPu8:
5678
0
    case ARM::MVE_VDWDUPu16:
5679
0
    case ARM::MVE_VDWDUPu32:
5680
0
    case ARM::MVE_VIWDUPu8:
5681
0
    case ARM::MVE_VIWDUPu16:
5682
0
    case ARM::MVE_VIWDUPu32: {
5683
      // op: Qd
5684
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5685
0
      Value |= (op & UINT64_C(8)) << 19;
5686
0
      Value |= (op & UINT64_C(7)) << 13;
5687
      // op: Rm
5688
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5689
0
      op &= UINT64_C(14);
5690
0
      Value |= op;
5691
      // op: Rn
5692
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5693
0
      op &= UINT64_C(14);
5694
0
      op <<= 16;
5695
0
      Value |= op;
5696
      // op: imm
5697
0
      op = getPowerTwoOpValue(MI, 4, Fixups, STI);
5698
0
      Value |= (op & UINT64_C(2)) << 6;
5699
0
      Value |= (op & UINT64_C(1));
5700
0
      break;
5701
0
    }
5702
0
    case ARM::MVE_VDDUPu8:
5703
0
    case ARM::MVE_VDDUPu16:
5704
0
    case ARM::MVE_VDDUPu32:
5705
0
    case ARM::MVE_VIDUPu8:
5706
0
    case ARM::MVE_VIDUPu16:
5707
0
    case ARM::MVE_VIDUPu32: {
5708
      // op: Qd
5709
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5710
0
      Value |= (op & UINT64_C(8)) << 19;
5711
0
      Value |= (op & UINT64_C(7)) << 13;
5712
      // op: Rn
5713
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5714
0
      op &= UINT64_C(14);
5715
0
      op <<= 16;
5716
0
      Value |= op;
5717
      // op: imm
5718
0
      op = getPowerTwoOpValue(MI, 3, Fixups, STI);
5719
0
      Value |= (op & UINT64_C(2)) << 6;
5720
0
      Value |= (op & UINT64_C(1));
5721
0
      break;
5722
0
    }
5723
0
    case ARM::MVE_VLDRWU32_qi:
5724
0
    case ARM::MVE_VSTRW32_qi: {
5725
      // op: Qd
5726
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5727
0
      op &= UINT64_C(7);
5728
0
      op <<= 13;
5729
0
      Value |= op;
5730
      // op: addr
5731
0
      op = getMveAddrModeQOpValue<2>(MI, 1, Fixups, STI);
5732
0
      Value |= (op & UINT64_C(128)) << 16;
5733
0
      Value |= (op & UINT64_C(1792)) << 9;
5734
0
      Value |= (op & UINT64_C(127));
5735
0
      break;
5736
0
    }
5737
0
    case ARM::MVE_VLDRDU64_qi:
5738
0
    case ARM::MVE_VSTRD64_qi: {
5739
      // op: Qd
5740
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5741
0
      op &= UINT64_C(7);
5742
0
      op <<= 13;
5743
0
      Value |= op;
5744
      // op: addr
5745
0
      op = getMveAddrModeQOpValue<3>(MI, 1, Fixups, STI);
5746
0
      Value |= (op & UINT64_C(128)) << 16;
5747
0
      Value |= (op & UINT64_C(1792)) << 9;
5748
0
      Value |= (op & UINT64_C(127));
5749
0
      break;
5750
0
    }
5751
0
    case ARM::MVE_VLDRBS16_rq:
5752
0
    case ARM::MVE_VLDRBS32_rq:
5753
0
    case ARM::MVE_VLDRBU8_rq:
5754
0
    case ARM::MVE_VLDRBU16_rq:
5755
0
    case ARM::MVE_VLDRBU32_rq:
5756
0
    case ARM::MVE_VLDRDU64_rq:
5757
0
    case ARM::MVE_VLDRDU64_rq_u:
5758
0
    case ARM::MVE_VLDRHS32_rq:
5759
0
    case ARM::MVE_VLDRHS32_rq_u:
5760
0
    case ARM::MVE_VLDRHU16_rq:
5761
0
    case ARM::MVE_VLDRHU16_rq_u:
5762
0
    case ARM::MVE_VLDRHU32_rq:
5763
0
    case ARM::MVE_VLDRHU32_rq_u:
5764
0
    case ARM::MVE_VLDRWU32_rq:
5765
0
    case ARM::MVE_VLDRWU32_rq_u:
5766
0
    case ARM::MVE_VSTRB8_rq:
5767
0
    case ARM::MVE_VSTRB16_rq:
5768
0
    case ARM::MVE_VSTRB32_rq:
5769
0
    case ARM::MVE_VSTRD64_rq:
5770
0
    case ARM::MVE_VSTRD64_rq_u:
5771
0
    case ARM::MVE_VSTRH16_rq:
5772
0
    case ARM::MVE_VSTRH16_rq_u:
5773
0
    case ARM::MVE_VSTRH32_rq:
5774
0
    case ARM::MVE_VSTRH32_rq_u:
5775
0
    case ARM::MVE_VSTRW32_rq:
5776
0
    case ARM::MVE_VSTRW32_rq_u: {
5777
      // op: Qd
5778
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5779
0
      op &= UINT64_C(7);
5780
0
      op <<= 13;
5781
0
      Value |= op;
5782
      // op: addr
5783
0
      op = getMveAddrModeRQOpValue(MI, 1, Fixups, STI);
5784
0
      Value |= (op & UINT64_C(120)) << 13;
5785
0
      Value |= (op & UINT64_C(7)) << 1;
5786
0
      break;
5787
0
    }
5788
0
    case ARM::MVE_VLDRBS16:
5789
0
    case ARM::MVE_VLDRBS32:
5790
0
    case ARM::MVE_VLDRBU16:
5791
0
    case ARM::MVE_VLDRBU32:
5792
0
    case ARM::MVE_VSTRB16:
5793
0
    case ARM::MVE_VSTRB32: {
5794
      // op: Qd
5795
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5796
0
      op &= UINT64_C(7);
5797
0
      op <<= 13;
5798
0
      Value |= op;
5799
      // op: addr
5800
0
      op = getT2AddrModeImmOpValue<7,0>(MI, 1, Fixups, STI);
5801
0
      Value |= (op & UINT64_C(128)) << 16;
5802
0
      Value |= (op & UINT64_C(1792)) << 8;
5803
0
      Value |= (op & UINT64_C(127));
5804
0
      break;
5805
0
    }
5806
0
    case ARM::MVE_VLDRBU8:
5807
0
    case ARM::MVE_VSTRBU8: {
5808
      // op: Qd
5809
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5810
0
      op &= UINT64_C(7);
5811
0
      op <<= 13;
5812
0
      Value |= op;
5813
      // op: addr
5814
0
      op = getT2AddrModeImmOpValue<7,0>(MI, 1, Fixups, STI);
5815
0
      Value |= (op & UINT64_C(128)) << 16;
5816
0
      Value |= (op & UINT64_C(3840)) << 8;
5817
0
      Value |= (op & UINT64_C(127));
5818
0
      break;
5819
0
    }
5820
0
    case ARM::MVE_VLDRHS32:
5821
0
    case ARM::MVE_VLDRHU32:
5822
0
    case ARM::MVE_VSTRH32: {
5823
      // op: Qd
5824
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5825
0
      op &= UINT64_C(7);
5826
0
      op <<= 13;
5827
0
      Value |= op;
5828
      // op: addr
5829
0
      op = getT2AddrModeImmOpValue<7,1>(MI, 1, Fixups, STI);
5830
0
      Value |= (op & UINT64_C(128)) << 16;
5831
0
      Value |= (op & UINT64_C(1792)) << 8;
5832
0
      Value |= (op & UINT64_C(127));
5833
0
      break;
5834
0
    }
5835
0
    case ARM::MVE_VLDRHU16:
5836
0
    case ARM::MVE_VSTRHU16: {
5837
      // op: Qd
5838
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5839
0
      op &= UINT64_C(7);
5840
0
      op <<= 13;
5841
0
      Value |= op;
5842
      // op: addr
5843
0
      op = getT2AddrModeImmOpValue<7,1>(MI, 1, Fixups, STI);
5844
0
      Value |= (op & UINT64_C(128)) << 16;
5845
0
      Value |= (op & UINT64_C(3840)) << 8;
5846
0
      Value |= (op & UINT64_C(127));
5847
0
      break;
5848
0
    }
5849
0
    case ARM::MVE_VLDRWU32:
5850
0
    case ARM::MVE_VSTRWU32: {
5851
      // op: Qd
5852
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5853
0
      op &= UINT64_C(7);
5854
0
      op <<= 13;
5855
0
      Value |= op;
5856
      // op: addr
5857
0
      op = getT2AddrModeImmOpValue<7,2>(MI, 1, Fixups, STI);
5858
0
      Value |= (op & UINT64_C(128)) << 16;
5859
0
      Value |= (op & UINT64_C(3840)) << 8;
5860
0
      Value |= (op & UINT64_C(127));
5861
0
      break;
5862
0
    }
5863
0
    case ARM::MVE_VMOV_from_lane_32: {
5864
      // op: Qd
5865
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5866
0
      Value |= (op & UINT64_C(7)) << 17;
5867
0
      Value |= (op & UINT64_C(8)) << 4;
5868
      // op: Rt
5869
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5870
0
      op &= UINT64_C(15);
5871
0
      op <<= 12;
5872
0
      Value |= op;
5873
      // op: Idx
5874
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5875
0
      Value |= (op & UINT64_C(1)) << 21;
5876
0
      Value |= (op & UINT64_C(2)) << 15;
5877
0
      break;
5878
0
    }
5879
0
    case ARM::MVE_VMOV_from_lane_s16:
5880
0
    case ARM::MVE_VMOV_from_lane_u16: {
5881
      // op: Qd
5882
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5883
0
      Value |= (op & UINT64_C(7)) << 17;
5884
0
      Value |= (op & UINT64_C(8)) << 4;
5885
      // op: Rt
5886
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5887
0
      op &= UINT64_C(15);
5888
0
      op <<= 12;
5889
0
      Value |= op;
5890
      // op: Idx
5891
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5892
0
      Value |= (op & UINT64_C(2)) << 20;
5893
0
      Value |= (op & UINT64_C(4)) << 14;
5894
0
      Value |= (op & UINT64_C(1)) << 6;
5895
0
      break;
5896
0
    }
5897
0
    case ARM::MVE_VMOV_from_lane_s8:
5898
0
    case ARM::MVE_VMOV_from_lane_u8: {
5899
      // op: Qd
5900
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5901
0
      Value |= (op & UINT64_C(7)) << 17;
5902
0
      Value |= (op & UINT64_C(8)) << 4;
5903
      // op: Rt
5904
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5905
0
      op &= UINT64_C(15);
5906
0
      op <<= 12;
5907
0
      Value |= op;
5908
      // op: Idx
5909
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5910
0
      Value |= (op & UINT64_C(4)) << 19;
5911
0
      Value |= (op & UINT64_C(8)) << 13;
5912
0
      Value |= (op & UINT64_C(3)) << 5;
5913
0
      break;
5914
0
    }
5915
0
    case ARM::MVE_VLDRWU32_qi_pre:
5916
0
    case ARM::MVE_VSTRW32_qi_pre: {
5917
      // op: Qd
5918
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5919
0
      op &= UINT64_C(7);
5920
0
      op <<= 13;
5921
0
      Value |= op;
5922
      // op: addr
5923
0
      op = getMveAddrModeQOpValue<2>(MI, 2, Fixups, STI);
5924
0
      Value |= (op & UINT64_C(128)) << 16;
5925
0
      Value |= (op & UINT64_C(1792)) << 9;
5926
0
      Value |= (op & UINT64_C(127));
5927
0
      break;
5928
0
    }
5929
0
    case ARM::MVE_VLDRDU64_qi_pre:
5930
0
    case ARM::MVE_VSTRD64_qi_pre: {
5931
      // op: Qd
5932
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5933
0
      op &= UINT64_C(7);
5934
0
      op <<= 13;
5935
0
      Value |= op;
5936
      // op: addr
5937
0
      op = getMveAddrModeQOpValue<3>(MI, 2, Fixups, STI);
5938
0
      Value |= (op & UINT64_C(128)) << 16;
5939
0
      Value |= (op & UINT64_C(1792)) << 9;
5940
0
      Value |= (op & UINT64_C(127));
5941
0
      break;
5942
0
    }
5943
0
    case ARM::MVE_VLDRBS16_pre:
5944
0
    case ARM::MVE_VLDRBS32_pre:
5945
0
    case ARM::MVE_VLDRBU16_pre:
5946
0
    case ARM::MVE_VLDRBU32_pre:
5947
0
    case ARM::MVE_VSTRB16_pre:
5948
0
    case ARM::MVE_VSTRB32_pre: {
5949
      // op: Qd
5950
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5951
0
      op &= UINT64_C(7);
5952
0
      op <<= 13;
5953
0
      Value |= op;
5954
      // op: addr
5955
0
      op = getT2AddrModeImmOpValue<7,0>(MI, 2, Fixups, STI);
5956
0
      Value |= (op & UINT64_C(128)) << 16;
5957
0
      Value |= (op & UINT64_C(1792)) << 8;
5958
0
      Value |= (op & UINT64_C(127));
5959
0
      break;
5960
0
    }
5961
0
    case ARM::MVE_VLDRBU8_pre:
5962
0
    case ARM::MVE_VSTRBU8_pre: {
5963
      // op: Qd
5964
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5965
0
      op &= UINT64_C(7);
5966
0
      op <<= 13;
5967
0
      Value |= op;
5968
      // op: addr
5969
0
      op = getT2AddrModeImmOpValue<7,0>(MI, 2, Fixups, STI);
5970
0
      Value |= (op & UINT64_C(128)) << 16;
5971
0
      Value |= (op & UINT64_C(3840)) << 8;
5972
0
      Value |= (op & UINT64_C(127));
5973
0
      break;
5974
0
    }
5975
0
    case ARM::MVE_VLDRHS32_pre:
5976
0
    case ARM::MVE_VLDRHU32_pre:
5977
0
    case ARM::MVE_VSTRH32_pre: {
5978
      // op: Qd
5979
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5980
0
      op &= UINT64_C(7);
5981
0
      op <<= 13;
5982
0
      Value |= op;
5983
      // op: addr
5984
0
      op = getT2AddrModeImmOpValue<7,1>(MI, 2, Fixups, STI);
5985
0
      Value |= (op & UINT64_C(128)) << 16;
5986
0
      Value |= (op & UINT64_C(1792)) << 8;
5987
0
      Value |= (op & UINT64_C(127));
5988
0
      break;
5989
0
    }
5990
0
    case ARM::MVE_VLDRHU16_pre:
5991
0
    case ARM::MVE_VSTRHU16_pre: {
5992
      // op: Qd
5993
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5994
0
      op &= UINT64_C(7);
5995
0
      op <<= 13;
5996
0
      Value |= op;
5997
      // op: addr
5998
0
      op = getT2AddrModeImmOpValue<7,1>(MI, 2, Fixups, STI);
5999
0
      Value |= (op & UINT64_C(128)) << 16;
6000
0
      Value |= (op & UINT64_C(3840)) << 8;
6001
0
      Value |= (op & UINT64_C(127));
6002
0
      break;
6003
0
    }
6004
0
    case ARM::MVE_VLDRWU32_pre:
6005
0
    case ARM::MVE_VSTRWU32_pre: {
6006
      // op: Qd
6007
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6008
0
      op &= UINT64_C(7);
6009
0
      op <<= 13;
6010
0
      Value |= op;
6011
      // op: addr
6012
0
      op = getT2AddrModeImmOpValue<7,2>(MI, 2, Fixups, STI);
6013
0
      Value |= (op & UINT64_C(128)) << 16;
6014
0
      Value |= (op & UINT64_C(3840)) << 8;
6015
0
      Value |= (op & UINT64_C(127));
6016
0
      break;
6017
0
    }
6018
0
    case ARM::MVE_VLDRBU8_post:
6019
0
    case ARM::MVE_VSTRBU8_post: {
6020
      // op: Qd
6021
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6022
0
      op &= UINT64_C(7);
6023
0
      op <<= 13;
6024
0
      Value |= op;
6025
      // op: addr
6026
0
      op = getT2ScaledImmOpValue<7,0>(MI, 3, Fixups, STI);
6027
0
      Value |= (op & UINT64_C(128)) << 16;
6028
0
      Value |= (op & UINT64_C(127));
6029
      // op: Rn
6030
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6031
0
      op &= UINT64_C(15);
6032
0
      op <<= 16;
6033
0
      Value |= op;
6034
0
      break;
6035
0
    }
6036
0
    case ARM::MVE_VLDRBS16_post:
6037
0
    case ARM::MVE_VLDRBS32_post:
6038
0
    case ARM::MVE_VLDRBU16_post:
6039
0
    case ARM::MVE_VLDRBU32_post:
6040
0
    case ARM::MVE_VSTRB16_post:
6041
0
    case ARM::MVE_VSTRB32_post: {
6042
      // op: Qd
6043
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6044
0
      op &= UINT64_C(7);
6045
0
      op <<= 13;
6046
0
      Value |= op;
6047
      // op: addr
6048
0
      op = getT2ScaledImmOpValue<7,0>(MI, 3, Fixups, STI);
6049
0
      Value |= (op & UINT64_C(128)) << 16;
6050
0
      Value |= (op & UINT64_C(127));
6051
      // op: Rn
6052
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6053
0
      op &= UINT64_C(7);
6054
0
      op <<= 16;
6055
0
      Value |= op;
6056
0
      break;
6057
0
    }
6058
0
    case ARM::MVE_VLDRHU16_post:
6059
0
    case ARM::MVE_VSTRHU16_post: {
6060
      // op: Qd
6061
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6062
0
      op &= UINT64_C(7);
6063
0
      op <<= 13;
6064
0
      Value |= op;
6065
      // op: addr
6066
0
      op = getT2ScaledImmOpValue<7,1>(MI, 3, Fixups, STI);
6067
0
      Value |= (op & UINT64_C(128)) << 16;
6068
0
      Value |= (op & UINT64_C(127));
6069
      // op: Rn
6070
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6071
0
      op &= UINT64_C(15);
6072
0
      op <<= 16;
6073
0
      Value |= op;
6074
0
      break;
6075
0
    }
6076
0
    case ARM::MVE_VLDRHS32_post:
6077
0
    case ARM::MVE_VLDRHU32_post:
6078
0
    case ARM::MVE_VSTRH32_post: {
6079
      // op: Qd
6080
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6081
0
      op &= UINT64_C(7);
6082
0
      op <<= 13;
6083
0
      Value |= op;
6084
      // op: addr
6085
0
      op = getT2ScaledImmOpValue<7,1>(MI, 3, Fixups, STI);
6086
0
      Value |= (op & UINT64_C(128)) << 16;
6087
0
      Value |= (op & UINT64_C(127));
6088
      // op: Rn
6089
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6090
0
      op &= UINT64_C(7);
6091
0
      op <<= 16;
6092
0
      Value |= op;
6093
0
      break;
6094
0
    }
6095
0
    case ARM::MVE_VLDRWU32_post:
6096
0
    case ARM::MVE_VSTRWU32_post: {
6097
      // op: Qd
6098
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6099
0
      op &= UINT64_C(7);
6100
0
      op <<= 13;
6101
0
      Value |= op;
6102
      // op: addr
6103
0
      op = getT2ScaledImmOpValue<7,2>(MI, 3, Fixups, STI);
6104
0
      Value |= (op & UINT64_C(128)) << 16;
6105
0
      Value |= (op & UINT64_C(127));
6106
      // op: Rn
6107
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6108
0
      op &= UINT64_C(15);
6109
0
      op <<= 16;
6110
0
      Value |= op;
6111
0
      break;
6112
0
    }
6113
0
    case ARM::MVE_VABSf16:
6114
0
    case ARM::MVE_VABSf32:
6115
0
    case ARM::MVE_VCVTf16s16n:
6116
0
    case ARM::MVE_VCVTf16u16n:
6117
0
    case ARM::MVE_VCVTf32s32n:
6118
0
    case ARM::MVE_VCVTf32u32n:
6119
0
    case ARM::MVE_VCVTs16f16a:
6120
0
    case ARM::MVE_VCVTs16f16m:
6121
0
    case ARM::MVE_VCVTs16f16n:
6122
0
    case ARM::MVE_VCVTs16f16p:
6123
0
    case ARM::MVE_VCVTs16f16z:
6124
0
    case ARM::MVE_VCVTs32f32a:
6125
0
    case ARM::MVE_VCVTs32f32m:
6126
0
    case ARM::MVE_VCVTs32f32n:
6127
0
    case ARM::MVE_VCVTs32f32p:
6128
0
    case ARM::MVE_VCVTs32f32z:
6129
0
    case ARM::MVE_VCVTu16f16a:
6130
0
    case ARM::MVE_VCVTu16f16m:
6131
0
    case ARM::MVE_VCVTu16f16n:
6132
0
    case ARM::MVE_VCVTu16f16p:
6133
0
    case ARM::MVE_VCVTu16f16z:
6134
0
    case ARM::MVE_VCVTu32f32a:
6135
0
    case ARM::MVE_VCVTu32f32m:
6136
0
    case ARM::MVE_VCVTu32f32n:
6137
0
    case ARM::MVE_VCVTu32f32p:
6138
0
    case ARM::MVE_VCVTu32f32z:
6139
0
    case ARM::MVE_VNEGf16:
6140
0
    case ARM::MVE_VNEGf32:
6141
0
    case ARM::MVE_VRINTf16A:
6142
0
    case ARM::MVE_VRINTf16M:
6143
0
    case ARM::MVE_VRINTf16N:
6144
0
    case ARM::MVE_VRINTf16P:
6145
0
    case ARM::MVE_VRINTf16X:
6146
0
    case ARM::MVE_VRINTf16Z:
6147
0
    case ARM::MVE_VRINTf32A:
6148
0
    case ARM::MVE_VRINTf32M:
6149
0
    case ARM::MVE_VRINTf32N:
6150
0
    case ARM::MVE_VRINTf32P:
6151
0
    case ARM::MVE_VRINTf32X:
6152
0
    case ARM::MVE_VRINTf32Z: {
6153
      // op: Qm
6154
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6155
0
      Value |= (op & UINT64_C(8)) << 2;
6156
0
      Value |= (op & UINT64_C(7)) << 1;
6157
      // op: Qd
6158
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6159
0
      Value |= (op & UINT64_C(8)) << 19;
6160
0
      Value |= (op & UINT64_C(7)) << 13;
6161
0
      break;
6162
0
    }
6163
0
    case ARM::MVE_VCVTf16s16_fix:
6164
0
    case ARM::MVE_VCVTf16u16_fix:
6165
0
    case ARM::MVE_VCVTs16f16_fix:
6166
0
    case ARM::MVE_VCVTu16f16_fix: {
6167
      // op: Qm
6168
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6169
0
      Value |= (op & UINT64_C(8)) << 2;
6170
0
      Value |= (op & UINT64_C(7)) << 1;
6171
      // op: Qd
6172
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6173
0
      Value |= (op & UINT64_C(8)) << 19;
6174
0
      Value |= (op & UINT64_C(7)) << 13;
6175
      // op: imm6
6176
0
      op = getNEONVcvtImm32OpValue(MI, 2, Fixups, STI);
6177
0
      op &= UINT64_C(15);
6178
0
      op <<= 16;
6179
0
      Value |= op;
6180
0
      break;
6181
0
    }
6182
0
    case ARM::MVE_VCVTf32s32_fix:
6183
0
    case ARM::MVE_VCVTf32u32_fix:
6184
0
    case ARM::MVE_VCVTs32f32_fix:
6185
0
    case ARM::MVE_VCVTu32f32_fix: {
6186
      // op: Qm
6187
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6188
0
      Value |= (op & UINT64_C(8)) << 2;
6189
0
      Value |= (op & UINT64_C(7)) << 1;
6190
      // op: Qd
6191
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6192
0
      Value |= (op & UINT64_C(8)) << 19;
6193
0
      Value |= (op & UINT64_C(7)) << 13;
6194
      // op: imm6
6195
0
      op = getNEONVcvtImm32OpValue(MI, 2, Fixups, STI);
6196
0
      op &= UINT64_C(31);
6197
0
      op <<= 16;
6198
0
      Value |= op;
6199
0
      break;
6200
0
    }
6201
0
    case ARM::MVE_VADDVs8no_acc:
6202
0
    case ARM::MVE_VADDVs16no_acc:
6203
0
    case ARM::MVE_VADDVs32no_acc:
6204
0
    case ARM::MVE_VADDVu8no_acc:
6205
0
    case ARM::MVE_VADDVu16no_acc:
6206
0
    case ARM::MVE_VADDVu32no_acc: {
6207
      // op: Qm
6208
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6209
0
      op &= UINT64_C(7);
6210
0
      op <<= 1;
6211
0
      Value |= op;
6212
      // op: Rda
6213
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6214
0
      op &= UINT64_C(14);
6215
0
      op <<= 12;
6216
0
      Value |= op;
6217
0
      break;
6218
0
    }
6219
0
    case ARM::MVE_VABDf16:
6220
0
    case ARM::MVE_VABDf32:
6221
0
    case ARM::MVE_VADDf16:
6222
0
    case ARM::MVE_VADDf32:
6223
0
    case ARM::MVE_VMULf16:
6224
0
    case ARM::MVE_VMULf32:
6225
0
    case ARM::MVE_VSUBf16:
6226
0
    case ARM::MVE_VSUBf32: {
6227
      // op: Qm
6228
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6229
0
      Value |= (op & UINT64_C(8)) << 2;
6230
0
      Value |= (op & UINT64_C(7)) << 1;
6231
      // op: Qd
6232
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6233
0
      Value |= (op & UINT64_C(8)) << 19;
6234
0
      Value |= (op & UINT64_C(7)) << 13;
6235
      // op: Qn
6236
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6237
0
      Value |= (op & UINT64_C(7)) << 17;
6238
0
      Value |= (op & UINT64_C(8)) << 4;
6239
0
      break;
6240
0
    }
6241
0
    case ARM::MVE_VCADDf16:
6242
0
    case ARM::MVE_VCADDf32: {
6243
      // op: Qm
6244
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6245
0
      Value |= (op & UINT64_C(8)) << 2;
6246
0
      Value |= (op & UINT64_C(7)) << 1;
6247
      // op: Qd
6248
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6249
0
      Value |= (op & UINT64_C(8)) << 19;
6250
0
      Value |= (op & UINT64_C(7)) << 13;
6251
      // op: Qn
6252
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6253
0
      Value |= (op & UINT64_C(7)) << 17;
6254
0
      Value |= (op & UINT64_C(8)) << 4;
6255
      // op: rot
6256
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6257
0
      op &= UINT64_C(1);
6258
0
      op <<= 24;
6259
0
      Value |= op;
6260
0
      break;
6261
0
    }
6262
0
    case ARM::MVE_VADDVs8acc:
6263
0
    case ARM::MVE_VADDVs16acc:
6264
0
    case ARM::MVE_VADDVs32acc:
6265
0
    case ARM::MVE_VADDVu8acc:
6266
0
    case ARM::MVE_VADDVu16acc:
6267
0
    case ARM::MVE_VADDVu32acc: {
6268
      // op: Qm
6269
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6270
0
      op &= UINT64_C(7);
6271
0
      op <<= 1;
6272
0
      Value |= op;
6273
      // op: Rda
6274
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6275
0
      op &= UINT64_C(14);
6276
0
      op <<= 12;
6277
0
      Value |= op;
6278
0
      break;
6279
0
    }
6280
0
    case ARM::MVE_VMAXAVs8:
6281
0
    case ARM::MVE_VMAXAVs16:
6282
0
    case ARM::MVE_VMAXAVs32:
6283
0
    case ARM::MVE_VMAXNMAVf16:
6284
0
    case ARM::MVE_VMAXNMAVf32:
6285
0
    case ARM::MVE_VMAXNMVf16:
6286
0
    case ARM::MVE_VMAXNMVf32:
6287
0
    case ARM::MVE_VMAXVs8:
6288
0
    case ARM::MVE_VMAXVs16:
6289
0
    case ARM::MVE_VMAXVs32:
6290
0
    case ARM::MVE_VMAXVu8:
6291
0
    case ARM::MVE_VMAXVu16:
6292
0
    case ARM::MVE_VMAXVu32:
6293
0
    case ARM::MVE_VMINAVs8:
6294
0
    case ARM::MVE_VMINAVs16:
6295
0
    case ARM::MVE_VMINAVs32:
6296
0
    case ARM::MVE_VMINNMAVf16:
6297
0
    case ARM::MVE_VMINNMAVf32:
6298
0
    case ARM::MVE_VMINNMVf16:
6299
0
    case ARM::MVE_VMINNMVf32:
6300
0
    case ARM::MVE_VMINVs8:
6301
0
    case ARM::MVE_VMINVs16:
6302
0
    case ARM::MVE_VMINVs32:
6303
0
    case ARM::MVE_VMINVu8:
6304
0
    case ARM::MVE_VMINVu16:
6305
0
    case ARM::MVE_VMINVu32: {
6306
      // op: Qm
6307
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6308
0
      op &= UINT64_C(7);
6309
0
      op <<= 1;
6310
0
      Value |= op;
6311
      // op: RdaDest
6312
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6313
0
      op &= UINT64_C(15);
6314
0
      op <<= 12;
6315
0
      Value |= op;
6316
0
      break;
6317
0
    }
6318
0
    case ARM::MVE_VADDLVs32no_acc:
6319
0
    case ARM::MVE_VADDLVu32no_acc: {
6320
      // op: Qm
6321
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6322
0
      op &= UINT64_C(7);
6323
0
      op <<= 1;
6324
0
      Value |= op;
6325
      // op: RdaLo
6326
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6327
0
      op &= UINT64_C(14);
6328
0
      op <<= 12;
6329
0
      Value |= op;
6330
      // op: RdaHi
6331
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6332
0
      op &= UINT64_C(14);
6333
0
      op <<= 19;
6334
0
      Value |= op;
6335
0
      break;
6336
0
    }
6337
0
    case ARM::MVE_VFMAf16:
6338
0
    case ARM::MVE_VFMAf32:
6339
0
    case ARM::MVE_VFMSf16:
6340
0
    case ARM::MVE_VFMSf32: {
6341
      // op: Qm
6342
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6343
0
      Value |= (op & UINT64_C(8)) << 2;
6344
0
      Value |= (op & UINT64_C(7)) << 1;
6345
      // op: Qd
6346
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6347
0
      Value |= (op & UINT64_C(8)) << 19;
6348
0
      Value |= (op & UINT64_C(7)) << 13;
6349
      // op: Qn
6350
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6351
0
      Value |= (op & UINT64_C(7)) << 17;
6352
0
      Value |= (op & UINT64_C(8)) << 4;
6353
0
      break;
6354
0
    }
6355
0
    case ARM::MVE_VCMLAf16:
6356
0
    case ARM::MVE_VCMLAf32: {
6357
      // op: Qm
6358
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6359
0
      Value |= (op & UINT64_C(8)) << 2;
6360
0
      Value |= (op & UINT64_C(7)) << 1;
6361
      // op: Qd
6362
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6363
0
      Value |= (op & UINT64_C(8)) << 19;
6364
0
      Value |= (op & UINT64_C(7)) << 13;
6365
      // op: Qn
6366
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6367
0
      Value |= (op & UINT64_C(7)) << 17;
6368
0
      Value |= (op & UINT64_C(8)) << 4;
6369
      // op: rot
6370
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
6371
0
      op &= UINT64_C(3);
6372
0
      op <<= 23;
6373
0
      Value |= op;
6374
0
      break;
6375
0
    }
6376
0
    case ARM::MVE_VABAVs8:
6377
0
    case ARM::MVE_VABAVs16:
6378
0
    case ARM::MVE_VABAVs32:
6379
0
    case ARM::MVE_VABAVu8:
6380
0
    case ARM::MVE_VABAVu16:
6381
0
    case ARM::MVE_VABAVu32: {
6382
      // op: Qm
6383
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6384
0
      Value |= (op & UINT64_C(8)) << 2;
6385
0
      Value |= (op & UINT64_C(7)) << 1;
6386
      // op: Qn
6387
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6388
0
      Value |= (op & UINT64_C(7)) << 17;
6389
0
      Value |= (op & UINT64_C(8)) << 4;
6390
      // op: Rda
6391
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6392
0
      op &= UINT64_C(15);
6393
0
      op <<= 12;
6394
0
      Value |= op;
6395
0
      break;
6396
0
    }
6397
0
    case ARM::MVE_VADDLVs32acc:
6398
0
    case ARM::MVE_VADDLVu32acc: {
6399
      // op: Qm
6400
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
6401
0
      op &= UINT64_C(7);
6402
0
      op <<= 1;
6403
0
      Value |= op;
6404
      // op: RdaLo
6405
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6406
0
      op &= UINT64_C(14);
6407
0
      op <<= 12;
6408
0
      Value |= op;
6409
      // op: RdaHi
6410
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6411
0
      op &= UINT64_C(14);
6412
0
      op <<= 19;
6413
0
      Value |= op;
6414
0
      break;
6415
0
    }
6416
0
    case ARM::MVE_VPSEL: {
6417
      // op: Qn
6418
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6419
0
      Value |= (op & UINT64_C(7)) << 17;
6420
0
      Value |= (op & UINT64_C(8)) << 4;
6421
      // op: Qd
6422
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6423
0
      Value |= (op & UINT64_C(8)) << 19;
6424
0
      Value |= (op & UINT64_C(7)) << 13;
6425
      // op: Qm
6426
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6427
0
      Value |= (op & UINT64_C(8)) << 2;
6428
0
      Value |= (op & UINT64_C(7)) << 1;
6429
0
      break;
6430
0
    }
6431
0
    case ARM::t2AUTG:
6432
0
    case ARM::t2BXAUT: {
6433
      // op: Ra
6434
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6435
0
      op &= UINT64_C(15);
6436
0
      op <<= 12;
6437
0
      Value |= op;
6438
      // op: Rn
6439
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6440
0
      op &= UINT64_C(15);
6441
0
      op <<= 16;
6442
0
      Value |= op;
6443
      // op: Rm
6444
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
6445
0
      op &= UINT64_C(15);
6446
0
      Value |= op;
6447
0
      break;
6448
0
    }
6449
0
    case ARM::tMOVr: {
6450
      // op: Rd
6451
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6452
0
      Value |= (op & UINT64_C(8)) << 4;
6453
0
      Value |= (op & UINT64_C(7));
6454
      // op: Rm
6455
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6456
0
      op &= UINT64_C(15);
6457
0
      op <<= 3;
6458
0
      Value |= op;
6459
0
      break;
6460
0
    }
6461
0
    case ARM::t2STLEX: {
6462
      // op: Rd
6463
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6464
0
      op &= UINT64_C(15);
6465
0
      Value |= op;
6466
      // op: Rt
6467
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6468
0
      op &= UINT64_C(15);
6469
0
      op <<= 12;
6470
0
      Value |= op;
6471
      // op: addr
6472
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6473
0
      op &= UINT64_C(15);
6474
0
      op <<= 16;
6475
0
      Value |= op;
6476
0
      break;
6477
0
    }
6478
0
    case ARM::t2STLEXB:
6479
0
    case ARM::t2STLEXH:
6480
0
    case ARM::t2STREXB:
6481
0
    case ARM::t2STREXH: {
6482
      // op: Rd
6483
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6484
0
      op &= UINT64_C(15);
6485
0
      Value |= op;
6486
      // op: addr
6487
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6488
0
      op &= UINT64_C(15);
6489
0
      op <<= 16;
6490
0
      Value |= op;
6491
      // op: Rt
6492
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6493
0
      op &= UINT64_C(15);
6494
0
      op <<= 12;
6495
0
      Value |= op;
6496
0
      break;
6497
0
    }
6498
0
    case ARM::t2STLEXD:
6499
0
    case ARM::t2STREXD: {
6500
      // op: Rd
6501
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6502
0
      op &= UINT64_C(15);
6503
0
      Value |= op;
6504
      // op: addr
6505
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6506
0
      op &= UINT64_C(15);
6507
0
      op <<= 16;
6508
0
      Value |= op;
6509
      // op: Rt
6510
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6511
0
      op &= UINT64_C(15);
6512
0
      op <<= 12;
6513
0
      Value |= op;
6514
      // op: Rt2
6515
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6516
0
      op &= UINT64_C(15);
6517
0
      op <<= 8;
6518
0
      Value |= op;
6519
0
      break;
6520
0
    }
6521
0
    case ARM::CRC32B:
6522
0
    case ARM::CRC32CB:
6523
0
    case ARM::CRC32CH:
6524
0
    case ARM::CRC32CW:
6525
0
    case ARM::CRC32H:
6526
0
    case ARM::CRC32W: {
6527
      // op: Rd
6528
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6529
0
      op &= UINT64_C(15);
6530
0
      op <<= 12;
6531
0
      Value |= op;
6532
      // op: Rn
6533
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6534
0
      op &= UINT64_C(15);
6535
0
      op <<= 16;
6536
0
      Value |= op;
6537
      // op: Rm
6538
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6539
0
      op &= UINT64_C(15);
6540
0
      Value |= op;
6541
0
      break;
6542
0
    }
6543
0
    case ARM::t2MRS_AR:
6544
0
    case ARM::t2MRSsys_AR: {
6545
      // op: Rd
6546
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6547
0
      op &= UINT64_C(15);
6548
0
      op <<= 8;
6549
0
      Value |= op;
6550
0
      break;
6551
0
    }
6552
0
    case ARM::t2CLZ:
6553
0
    case ARM::t2RBIT:
6554
0
    case ARM::t2REV:
6555
0
    case ARM::t2REV16:
6556
0
    case ARM::t2REVSH: {
6557
      // op: Rd
6558
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6559
0
      op &= UINT64_C(15);
6560
0
      op <<= 8;
6561
0
      Value |= op;
6562
      // op: Rm
6563
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6564
0
      Value |= (op & UINT64_C(15)) << 16;
6565
0
      Value |= (op & UINT64_C(15));
6566
0
      break;
6567
0
    }
6568
0
    case ARM::t2MOVsra_glue:
6569
0
    case ARM::t2MOVsrl_glue: {
6570
      // op: Rd
6571
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6572
0
      op &= UINT64_C(15);
6573
0
      op <<= 8;
6574
0
      Value |= op;
6575
      // op: Rm
6576
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6577
0
      op &= UINT64_C(15);
6578
0
      Value |= op;
6579
0
      break;
6580
0
    }
6581
0
    case ARM::t2SXTB:
6582
0
    case ARM::t2SXTB16:
6583
0
    case ARM::t2SXTH:
6584
0
    case ARM::t2UXTB:
6585
0
    case ARM::t2UXTB16:
6586
0
    case ARM::t2UXTH: {
6587
      // op: Rd
6588
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6589
0
      op &= UINT64_C(15);
6590
0
      op <<= 8;
6591
0
      Value |= op;
6592
      // op: Rm
6593
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6594
0
      op &= UINT64_C(15);
6595
0
      Value |= op;
6596
      // op: rot
6597
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6598
0
      op &= UINT64_C(3);
6599
0
      op <<= 4;
6600
0
      Value |= op;
6601
0
      break;
6602
0
    }
6603
0
    case ARM::t2CSEL:
6604
0
    case ARM::t2CSINC:
6605
0
    case ARM::t2CSINV:
6606
0
    case ARM::t2CSNEG: {
6607
      // op: Rd
6608
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6609
0
      op &= UINT64_C(15);
6610
0
      op <<= 8;
6611
0
      Value |= op;
6612
      // op: Rm
6613
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6614
0
      op &= UINT64_C(15);
6615
0
      Value |= op;
6616
      // op: Rn
6617
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6618
0
      op &= UINT64_C(15);
6619
0
      op <<= 16;
6620
0
      Value |= op;
6621
      // op: fcond
6622
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6623
0
      op &= UINT64_C(15);
6624
0
      op <<= 4;
6625
0
      Value |= op;
6626
0
      break;
6627
0
    }
6628
0
    case ARM::t2CRC32B:
6629
0
    case ARM::t2CRC32CB:
6630
0
    case ARM::t2CRC32CH:
6631
0
    case ARM::t2CRC32CW:
6632
0
    case ARM::t2CRC32H:
6633
0
    case ARM::t2CRC32W:
6634
0
    case ARM::t2MUL:
6635
0
    case ARM::t2QADD8:
6636
0
    case ARM::t2QADD16:
6637
0
    case ARM::t2QASX:
6638
0
    case ARM::t2QSAX:
6639
0
    case ARM::t2QSUB8:
6640
0
    case ARM::t2QSUB16:
6641
0
    case ARM::t2SADD8:
6642
0
    case ARM::t2SADD16:
6643
0
    case ARM::t2SASX:
6644
0
    case ARM::t2SDIV:
6645
0
    case ARM::t2SEL:
6646
0
    case ARM::t2SHADD8:
6647
0
    case ARM::t2SHADD16:
6648
0
    case ARM::t2SHASX:
6649
0
    case ARM::t2SHSAX:
6650
0
    case ARM::t2SHSUB8:
6651
0
    case ARM::t2SHSUB16:
6652
0
    case ARM::t2SMMUL:
6653
0
    case ARM::t2SMMULR:
6654
0
    case ARM::t2SMUAD:
6655
0
    case ARM::t2SMUADX:
6656
0
    case ARM::t2SMULBB:
6657
0
    case ARM::t2SMULBT:
6658
0
    case ARM::t2SMULTB:
6659
0
    case ARM::t2SMULTT:
6660
0
    case ARM::t2SMULWB:
6661
0
    case ARM::t2SMULWT:
6662
0
    case ARM::t2SMUSD:
6663
0
    case ARM::t2SMUSDX:
6664
0
    case ARM::t2SSAX:
6665
0
    case ARM::t2SSUB8:
6666
0
    case ARM::t2SSUB16:
6667
0
    case ARM::t2UADD8:
6668
0
    case ARM::t2UADD16:
6669
0
    case ARM::t2UASX:
6670
0
    case ARM::t2UDIV:
6671
0
    case ARM::t2UHADD8:
6672
0
    case ARM::t2UHADD16:
6673
0
    case ARM::t2UHASX:
6674
0
    case ARM::t2UHSAX:
6675
0
    case ARM::t2UHSUB8:
6676
0
    case ARM::t2UHSUB16:
6677
0
    case ARM::t2UQADD8:
6678
0
    case ARM::t2UQADD16:
6679
0
    case ARM::t2UQASX:
6680
0
    case ARM::t2UQSAX:
6681
0
    case ARM::t2UQSUB8:
6682
0
    case ARM::t2UQSUB16:
6683
0
    case ARM::t2USAD8:
6684
0
    case ARM::t2USAX:
6685
0
    case ARM::t2USUB8:
6686
0
    case ARM::t2USUB16: {
6687
      // op: Rd
6688
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6689
0
      op &= UINT64_C(15);
6690
0
      op <<= 8;
6691
0
      Value |= op;
6692
      // op: Rn
6693
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6694
0
      op &= UINT64_C(15);
6695
0
      op <<= 16;
6696
0
      Value |= op;
6697
      // op: Rm
6698
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6699
0
      op &= UINT64_C(15);
6700
0
      Value |= op;
6701
0
      break;
6702
0
    }
6703
0
    case ARM::t2MLA:
6704
0
    case ARM::t2MLS:
6705
0
    case ARM::t2SMLABB:
6706
0
    case ARM::t2SMLABT:
6707
0
    case ARM::t2SMLAD:
6708
0
    case ARM::t2SMLADX:
6709
0
    case ARM::t2SMLATB:
6710
0
    case ARM::t2SMLATT:
6711
0
    case ARM::t2SMLAWB:
6712
0
    case ARM::t2SMLAWT:
6713
0
    case ARM::t2SMLSD:
6714
0
    case ARM::t2SMLSDX:
6715
0
    case ARM::t2SMMLA:
6716
0
    case ARM::t2SMMLAR:
6717
0
    case ARM::t2SMMLS:
6718
0
    case ARM::t2SMMLSR:
6719
0
    case ARM::t2USADA8: {
6720
      // op: Rd
6721
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6722
0
      op &= UINT64_C(15);
6723
0
      op <<= 8;
6724
0
      Value |= op;
6725
      // op: Rn
6726
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6727
0
      op &= UINT64_C(15);
6728
0
      op <<= 16;
6729
0
      Value |= op;
6730
      // op: Rm
6731
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6732
0
      op &= UINT64_C(15);
6733
0
      Value |= op;
6734
      // op: Ra
6735
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6736
0
      op &= UINT64_C(15);
6737
0
      op <<= 12;
6738
0
      Value |= op;
6739
0
      break;
6740
0
    }
6741
0
    case ARM::t2SXTAB:
6742
0
    case ARM::t2SXTAB16:
6743
0
    case ARM::t2SXTAH:
6744
0
    case ARM::t2UXTAB:
6745
0
    case ARM::t2UXTAB16:
6746
0
    case ARM::t2UXTAH: {
6747
      // op: Rd
6748
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6749
0
      op &= UINT64_C(15);
6750
0
      op <<= 8;
6751
0
      Value |= op;
6752
      // op: Rn
6753
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6754
0
      op &= UINT64_C(15);
6755
0
      op <<= 16;
6756
0
      Value |= op;
6757
      // op: Rm
6758
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6759
0
      op &= UINT64_C(15);
6760
0
      Value |= op;
6761
      // op: rot
6762
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6763
0
      op &= UINT64_C(3);
6764
0
      op <<= 4;
6765
0
      Value |= op;
6766
0
      break;
6767
0
    }
6768
0
    case ARM::t2PKHBT:
6769
0
    case ARM::t2PKHTB: {
6770
      // op: Rd
6771
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6772
0
      op &= UINT64_C(15);
6773
0
      op <<= 8;
6774
0
      Value |= op;
6775
      // op: Rn
6776
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6777
0
      op &= UINT64_C(15);
6778
0
      op <<= 16;
6779
0
      Value |= op;
6780
      // op: Rm
6781
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6782
0
      op &= UINT64_C(15);
6783
0
      Value |= op;
6784
      // op: sh
6785
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6786
0
      Value |= (op & UINT64_C(28)) << 10;
6787
0
      Value |= (op & UINT64_C(3)) << 6;
6788
0
      break;
6789
0
    }
6790
0
    case ARM::t2ADDri12:
6791
0
    case ARM::t2SUBri12: {
6792
      // op: Rd
6793
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6794
0
      op &= UINT64_C(15);
6795
0
      op <<= 8;
6796
0
      Value |= op;
6797
      // op: Rn
6798
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6799
0
      op &= UINT64_C(15);
6800
0
      op <<= 16;
6801
0
      Value |= op;
6802
      // op: imm
6803
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6804
0
      Value |= (op & UINT64_C(2048)) << 15;
6805
0
      Value |= (op & UINT64_C(1792)) << 4;
6806
0
      Value |= (op & UINT64_C(255));
6807
0
      break;
6808
0
    }
6809
0
    case ARM::t2QADD:
6810
0
    case ARM::t2QDADD:
6811
0
    case ARM::t2QDSUB:
6812
0
    case ARM::t2QSUB: {
6813
      // op: Rd
6814
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6815
0
      op &= UINT64_C(15);
6816
0
      op <<= 8;
6817
0
      Value |= op;
6818
      // op: Rn
6819
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6820
0
      op &= UINT64_C(15);
6821
0
      op <<= 16;
6822
0
      Value |= op;
6823
      // op: Rm
6824
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6825
0
      op &= UINT64_C(15);
6826
0
      Value |= op;
6827
0
      break;
6828
0
    }
6829
0
    case ARM::t2BFI: {
6830
      // op: Rd
6831
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6832
0
      op &= UINT64_C(15);
6833
0
      op <<= 8;
6834
0
      Value |= op;
6835
      // op: Rn
6836
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6837
0
      op &= UINT64_C(15);
6838
0
      op <<= 16;
6839
0
      Value |= op;
6840
      // op: imm
6841
0
      op = getBitfieldInvertedMaskOpValue(MI, 3, Fixups, STI);
6842
0
      Value |= (op & UINT64_C(28)) << 10;
6843
0
      Value |= (op & UINT64_C(3)) << 6;
6844
0
      Value |= (op & UINT64_C(992)) >> 5;
6845
0
      break;
6846
0
    }
6847
0
    case ARM::t2SSAT16:
6848
0
    case ARM::t2USAT16: {
6849
      // op: Rd
6850
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6851
0
      op &= UINT64_C(15);
6852
0
      op <<= 8;
6853
0
      Value |= op;
6854
      // op: Rn
6855
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6856
0
      op &= UINT64_C(15);
6857
0
      op <<= 16;
6858
0
      Value |= op;
6859
      // op: sat_imm
6860
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6861
0
      op &= UINT64_C(15);
6862
0
      Value |= op;
6863
0
      break;
6864
0
    }
6865
0
    case ARM::t2SSAT:
6866
0
    case ARM::t2USAT: {
6867
      // op: Rd
6868
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6869
0
      op &= UINT64_C(15);
6870
0
      op <<= 8;
6871
0
      Value |= op;
6872
      // op: Rn
6873
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6874
0
      op &= UINT64_C(15);
6875
0
      op <<= 16;
6876
0
      Value |= op;
6877
      // op: sat_imm
6878
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6879
0
      op &= UINT64_C(31);
6880
0
      Value |= op;
6881
      // op: sh
6882
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6883
0
      Value |= (op & UINT64_C(32)) << 16;
6884
0
      Value |= (op & UINT64_C(28)) << 10;
6885
0
      Value |= (op & UINT64_C(3)) << 6;
6886
0
      break;
6887
0
    }
6888
0
    case ARM::t2PACG: {
6889
      // op: Rd
6890
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6891
0
      op &= UINT64_C(15);
6892
0
      op <<= 8;
6893
0
      Value |= op;
6894
      // op: Rn
6895
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6896
0
      op &= UINT64_C(15);
6897
0
      op <<= 16;
6898
0
      Value |= op;
6899
      // op: Rm
6900
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
6901
0
      op &= UINT64_C(15);
6902
0
      Value |= op;
6903
0
      break;
6904
0
    }
6905
0
    case ARM::t2STREX: {
6906
      // op: Rd
6907
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6908
0
      op &= UINT64_C(15);
6909
0
      op <<= 8;
6910
0
      Value |= op;
6911
      // op: Rt
6912
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6913
0
      op &= UINT64_C(15);
6914
0
      op <<= 12;
6915
0
      Value |= op;
6916
      // op: addr
6917
0
      op = getT2AddrModeImm0_1020s4OpValue(MI, 2, Fixups, STI);
6918
0
      Value |= (op & UINT64_C(3840)) << 8;
6919
0
      Value |= (op & UINT64_C(255));
6920
0
      break;
6921
0
    }
6922
0
    case ARM::t2MRS_M: {
6923
      // op: Rd
6924
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6925
0
      op &= UINT64_C(15);
6926
0
      op <<= 8;
6927
0
      Value |= op;
6928
      // op: SYSm
6929
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6930
0
      op &= UINT64_C(255);
6931
0
      Value |= op;
6932
0
      break;
6933
0
    }
6934
0
    case ARM::t2ADR: {
6935
      // op: Rd
6936
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6937
0
      op &= UINT64_C(15);
6938
0
      op <<= 8;
6939
0
      Value |= op;
6940
      // op: addr
6941
0
      op = getT2AdrLabelOpValue(MI, 1, Fixups, STI);
6942
0
      Value |= (op & UINT64_C(2048)) << 15;
6943
0
      Value |= (op & UINT64_C(4096)) << 11;
6944
0
      Value |= (op & UINT64_C(4096)) << 9;
6945
0
      Value |= (op & UINT64_C(1792)) << 4;
6946
0
      Value |= (op & UINT64_C(255));
6947
0
      break;
6948
0
    }
6949
0
    case ARM::t2BFC: {
6950
      // op: Rd
6951
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6952
0
      op &= UINT64_C(15);
6953
0
      op <<= 8;
6954
0
      Value |= op;
6955
      // op: imm
6956
0
      op = getBitfieldInvertedMaskOpValue(MI, 2, Fixups, STI);
6957
0
      Value |= (op & UINT64_C(28)) << 10;
6958
0
      Value |= (op & UINT64_C(3)) << 6;
6959
0
      Value |= (op & UINT64_C(992)) >> 5;
6960
0
      break;
6961
0
    }
6962
0
    case ARM::t2MOVi16: {
6963
      // op: Rd
6964
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6965
0
      op &= UINT64_C(15);
6966
0
      op <<= 8;
6967
0
      Value |= op;
6968
      // op: imm
6969
0
      op = getHiLoImmOpValue(MI, 1, Fixups, STI);
6970
0
      Value |= (op & UINT64_C(2048)) << 15;
6971
0
      Value |= (op & UINT64_C(61440)) << 4;
6972
0
      Value |= (op & UINT64_C(1792)) << 4;
6973
0
      Value |= (op & UINT64_C(255));
6974
0
      break;
6975
0
    }
6976
0
    case ARM::t2MOVTi16: {
6977
      // op: Rd
6978
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6979
0
      op &= UINT64_C(15);
6980
0
      op <<= 8;
6981
0
      Value |= op;
6982
      // op: imm
6983
0
      op = getHiLoImmOpValue(MI, 2, Fixups, STI);
6984
0
      Value |= (op & UINT64_C(2048)) << 15;
6985
0
      Value |= (op & UINT64_C(61440)) << 4;
6986
0
      Value |= (op & UINT64_C(1792)) << 4;
6987
0
      Value |= (op & UINT64_C(255));
6988
0
      break;
6989
0
    }
6990
0
    case ARM::t2SBFX:
6991
0
    case ARM::t2UBFX: {
6992
      // op: Rd
6993
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6994
0
      op &= UINT64_C(15);
6995
0
      op <<= 8;
6996
0
      Value |= op;
6997
      // op: msb
6998
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6999
0
      op &= UINT64_C(31);
7000
0
      Value |= op;
7001
      // op: lsb
7002
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7003
0
      Value |= (op & UINT64_C(28)) << 10;
7004
0
      Value |= (op & UINT64_C(3)) << 6;
7005
      // op: Rn
7006
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7007
0
      op &= UINT64_C(15);
7008
0
      op <<= 16;
7009
0
      Value |= op;
7010
0
      break;
7011
0
    }
7012
0
    case ARM::tMOVSr: {
7013
      // op: Rd
7014
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7015
0
      op &= UINT64_C(7);
7016
0
      Value |= op;
7017
      // op: Rm
7018
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7019
0
      op &= UINT64_C(7);
7020
0
      op <<= 3;
7021
0
      Value |= op;
7022
0
      break;
7023
0
    }
7024
0
    case ARM::tADDi3:
7025
0
    case ARM::tSUBi3: {
7026
      // op: Rd
7027
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7028
0
      op &= UINT64_C(7);
7029
0
      Value |= op;
7030
      // op: Rm
7031
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7032
0
      op &= UINT64_C(7);
7033
0
      op <<= 3;
7034
0
      Value |= op;
7035
      // op: imm3
7036
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7037
0
      op &= UINT64_C(7);
7038
0
      op <<= 6;
7039
0
      Value |= op;
7040
0
      break;
7041
0
    }
7042
0
    case ARM::tASRri:
7043
0
    case ARM::tLSLri:
7044
0
    case ARM::tLSRri: {
7045
      // op: Rd
7046
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7047
0
      op &= UINT64_C(7);
7048
0
      Value |= op;
7049
      // op: Rm
7050
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7051
0
      op &= UINT64_C(7);
7052
0
      op <<= 3;
7053
0
      Value |= op;
7054
      // op: imm5
7055
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7056
0
      op &= UINT64_C(31);
7057
0
      op <<= 6;
7058
0
      Value |= op;
7059
0
      break;
7060
0
    }
7061
0
    case ARM::tMUL:
7062
0
    case ARM::tMVN:
7063
0
    case ARM::tRSB: {
7064
      // op: Rd
7065
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7066
0
      op &= UINT64_C(7);
7067
0
      Value |= op;
7068
      // op: Rn
7069
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7070
0
      op &= UINT64_C(7);
7071
0
      op <<= 3;
7072
0
      Value |= op;
7073
0
      break;
7074
0
    }
7075
0
    case ARM::tADR: {
7076
      // op: Rd
7077
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7078
0
      op &= UINT64_C(7);
7079
0
      op <<= 8;
7080
0
      Value |= op;
7081
      // op: addr
7082
0
      op = getThumbAdrLabelOpValue(MI, 1, Fixups, STI);
7083
0
      op &= UINT64_C(255);
7084
0
      Value |= op;
7085
0
      break;
7086
0
    }
7087
0
    case ARM::tMOVi8: {
7088
      // op: Rd
7089
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7090
0
      op &= UINT64_C(7);
7091
0
      op <<= 8;
7092
0
      Value |= op;
7093
      // op: imm8
7094
0
      op = getHiLoImmOpValue(MI, 2, Fixups, STI);
7095
0
      op &= UINT64_C(255);
7096
0
      Value |= op;
7097
0
      break;
7098
0
    }
7099
0
    case ARM::t2SMLALD:
7100
0
    case ARM::t2SMLALDX:
7101
0
    case ARM::t2SMLSLD:
7102
0
    case ARM::t2SMLSLDX: {
7103
      // op: Rd
7104
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7105
0
      op &= UINT64_C(15);
7106
0
      op <<= 8;
7107
0
      Value |= op;
7108
      // op: Rn
7109
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7110
0
      op &= UINT64_C(15);
7111
0
      op <<= 16;
7112
0
      Value |= op;
7113
      // op: Rm
7114
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7115
0
      op &= UINT64_C(15);
7116
0
      Value |= op;
7117
      // op: Ra
7118
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7119
0
      op &= UINT64_C(15);
7120
0
      op <<= 12;
7121
0
      Value |= op;
7122
0
      break;
7123
0
    }
7124
0
    case ARM::t2SMLAL:
7125
0
    case ARM::t2SMLALBB:
7126
0
    case ARM::t2SMLALBT:
7127
0
    case ARM::t2SMLALTB:
7128
0
    case ARM::t2SMLALTT:
7129
0
    case ARM::t2SMULL:
7130
0
    case ARM::t2UMAAL:
7131
0
    case ARM::t2UMLAL:
7132
0
    case ARM::t2UMULL: {
7133
      // op: RdLo
7134
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7135
0
      op &= UINT64_C(15);
7136
0
      op <<= 12;
7137
0
      Value |= op;
7138
      // op: RdHi
7139
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7140
0
      op &= UINT64_C(15);
7141
0
      op <<= 8;
7142
0
      Value |= op;
7143
      // op: Rn
7144
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7145
0
      op &= UINT64_C(15);
7146
0
      op <<= 16;
7147
0
      Value |= op;
7148
      // op: Rm
7149
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7150
0
      op &= UINT64_C(15);
7151
0
      Value |= op;
7152
0
      break;
7153
0
    }
7154
0
    case ARM::MVE_VMLADAVs8:
7155
0
    case ARM::MVE_VMLADAVs16:
7156
0
    case ARM::MVE_VMLADAVs32:
7157
0
    case ARM::MVE_VMLADAVu8:
7158
0
    case ARM::MVE_VMLADAVu16:
7159
0
    case ARM::MVE_VMLADAVu32:
7160
0
    case ARM::MVE_VMLADAVxs8:
7161
0
    case ARM::MVE_VMLADAVxs16:
7162
0
    case ARM::MVE_VMLADAVxs32:
7163
0
    case ARM::MVE_VMLSDAVs8:
7164
0
    case ARM::MVE_VMLSDAVs16:
7165
0
    case ARM::MVE_VMLSDAVs32:
7166
0
    case ARM::MVE_VMLSDAVxs8:
7167
0
    case ARM::MVE_VMLSDAVxs16:
7168
0
    case ARM::MVE_VMLSDAVxs32: {
7169
      // op: RdaDest
7170
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7171
0
      op &= UINT64_C(14);
7172
0
      op <<= 12;
7173
0
      Value |= op;
7174
      // op: Qm
7175
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7176
0
      op &= UINT64_C(7);
7177
0
      op <<= 1;
7178
0
      Value |= op;
7179
      // op: Qn
7180
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7181
0
      op &= UINT64_C(7);
7182
0
      op <<= 17;
7183
0
      Value |= op;
7184
0
      break;
7185
0
    }
7186
0
    case ARM::MVE_VMLADAVas8:
7187
0
    case ARM::MVE_VMLADAVas16:
7188
0
    case ARM::MVE_VMLADAVas32:
7189
0
    case ARM::MVE_VMLADAVau8:
7190
0
    case ARM::MVE_VMLADAVau16:
7191
0
    case ARM::MVE_VMLADAVau32:
7192
0
    case ARM::MVE_VMLADAVaxs8:
7193
0
    case ARM::MVE_VMLADAVaxs16:
7194
0
    case ARM::MVE_VMLADAVaxs32:
7195
0
    case ARM::MVE_VMLSDAVas8:
7196
0
    case ARM::MVE_VMLSDAVas16:
7197
0
    case ARM::MVE_VMLSDAVas32:
7198
0
    case ARM::MVE_VMLSDAVaxs8:
7199
0
    case ARM::MVE_VMLSDAVaxs16:
7200
0
    case ARM::MVE_VMLSDAVaxs32: {
7201
      // op: RdaDest
7202
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7203
0
      op &= UINT64_C(14);
7204
0
      op <<= 12;
7205
0
      Value |= op;
7206
      // op: Qm
7207
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7208
0
      op &= UINT64_C(7);
7209
0
      op <<= 1;
7210
0
      Value |= op;
7211
      // op: Qn
7212
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7213
0
      op &= UINT64_C(7);
7214
0
      op <<= 17;
7215
0
      Value |= op;
7216
0
      break;
7217
0
    }
7218
0
    case ARM::MVE_SQRSHR:
7219
0
    case ARM::MVE_UQRSHL: {
7220
      // op: RdaDest
7221
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7222
0
      op &= UINT64_C(15);
7223
0
      op <<= 16;
7224
0
      Value |= op;
7225
      // op: Rm
7226
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7227
0
      op &= UINT64_C(15);
7228
0
      op <<= 12;
7229
0
      Value |= op;
7230
0
      break;
7231
0
    }
7232
0
    case ARM::MVE_SQSHL:
7233
0
    case ARM::MVE_SRSHR:
7234
0
    case ARM::MVE_UQSHL:
7235
0
    case ARM::MVE_URSHR: {
7236
      // op: RdaDest
7237
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7238
0
      op &= UINT64_C(15);
7239
0
      op <<= 16;
7240
0
      Value |= op;
7241
      // op: imm
7242
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7243
0
      Value |= (op & UINT64_C(28)) << 10;
7244
0
      Value |= (op & UINT64_C(3)) << 6;
7245
0
      break;
7246
0
    }
7247
0
    case ARM::MVE_ASRLr:
7248
0
    case ARM::MVE_LSLLr: {
7249
      // op: RdaLo
7250
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7251
0
      op &= UINT64_C(14);
7252
0
      op <<= 16;
7253
0
      Value |= op;
7254
      // op: RdaHi
7255
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7256
0
      op &= UINT64_C(14);
7257
0
      op <<= 8;
7258
0
      Value |= op;
7259
      // op: Rm
7260
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7261
0
      op &= UINT64_C(15);
7262
0
      op <<= 12;
7263
0
      Value |= op;
7264
0
      break;
7265
0
    }
7266
0
    case ARM::MVE_SQRSHRL:
7267
0
    case ARM::MVE_UQRSHLL: {
7268
      // op: RdaLo
7269
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7270
0
      op &= UINT64_C(14);
7271
0
      op <<= 16;
7272
0
      Value |= op;
7273
      // op: RdaHi
7274
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7275
0
      op &= UINT64_C(14);
7276
0
      op <<= 8;
7277
0
      Value |= op;
7278
      // op: Rm
7279
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7280
0
      op &= UINT64_C(15);
7281
0
      op <<= 12;
7282
0
      Value |= op;
7283
      // op: sat
7284
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
7285
0
      op &= UINT64_C(1);
7286
0
      op <<= 7;
7287
0
      Value |= op;
7288
0
      break;
7289
0
    }
7290
0
    case ARM::MVE_ASRLi:
7291
0
    case ARM::MVE_LSLLi:
7292
0
    case ARM::MVE_LSRL:
7293
0
    case ARM::MVE_SQSHLL:
7294
0
    case ARM::MVE_SRSHRL:
7295
0
    case ARM::MVE_UQSHLL:
7296
0
    case ARM::MVE_URSHRL: {
7297
      // op: RdaLo
7298
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7299
0
      op &= UINT64_C(14);
7300
0
      op <<= 16;
7301
0
      Value |= op;
7302
      // op: RdaHi
7303
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7304
0
      op &= UINT64_C(14);
7305
0
      op <<= 8;
7306
0
      Value |= op;
7307
      // op: imm
7308
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7309
0
      Value |= (op & UINT64_C(28)) << 10;
7310
0
      Value |= (op & UINT64_C(3)) << 6;
7311
0
      break;
7312
0
    }
7313
0
    case ARM::MVE_VMLALDAVs16:
7314
0
    case ARM::MVE_VMLALDAVs32:
7315
0
    case ARM::MVE_VMLALDAVu16:
7316
0
    case ARM::MVE_VMLALDAVu32:
7317
0
    case ARM::MVE_VMLALDAVxs16:
7318
0
    case ARM::MVE_VMLALDAVxs32:
7319
0
    case ARM::MVE_VMLSLDAVs16:
7320
0
    case ARM::MVE_VMLSLDAVs32:
7321
0
    case ARM::MVE_VMLSLDAVxs16:
7322
0
    case ARM::MVE_VMLSLDAVxs32:
7323
0
    case ARM::MVE_VRMLALDAVHs32:
7324
0
    case ARM::MVE_VRMLALDAVHu32:
7325
0
    case ARM::MVE_VRMLALDAVHxs32:
7326
0
    case ARM::MVE_VRMLSLDAVHs32:
7327
0
    case ARM::MVE_VRMLSLDAVHxs32: {
7328
      // op: RdaLoDest
7329
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7330
0
      op &= UINT64_C(14);
7331
0
      op <<= 12;
7332
0
      Value |= op;
7333
      // op: RdaHiDest
7334
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7335
0
      op &= UINT64_C(14);
7336
0
      op <<= 19;
7337
0
      Value |= op;
7338
      // op: Qm
7339
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7340
0
      op &= UINT64_C(7);
7341
0
      op <<= 1;
7342
0
      Value |= op;
7343
      // op: Qn
7344
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7345
0
      op &= UINT64_C(7);
7346
0
      op <<= 17;
7347
0
      Value |= op;
7348
0
      break;
7349
0
    }
7350
0
    case ARM::MVE_VMLALDAVas16:
7351
0
    case ARM::MVE_VMLALDAVas32:
7352
0
    case ARM::MVE_VMLALDAVau16:
7353
0
    case ARM::MVE_VMLALDAVau32:
7354
0
    case ARM::MVE_VMLALDAVaxs16:
7355
0
    case ARM::MVE_VMLALDAVaxs32:
7356
0
    case ARM::MVE_VMLSLDAVas16:
7357
0
    case ARM::MVE_VMLSLDAVas32:
7358
0
    case ARM::MVE_VMLSLDAVaxs16:
7359
0
    case ARM::MVE_VMLSLDAVaxs32:
7360
0
    case ARM::MVE_VRMLALDAVHas32:
7361
0
    case ARM::MVE_VRMLALDAVHau32:
7362
0
    case ARM::MVE_VRMLALDAVHaxs32:
7363
0
    case ARM::MVE_VRMLSLDAVHas32:
7364
0
    case ARM::MVE_VRMLSLDAVHaxs32: {
7365
      // op: RdaLoDest
7366
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7367
0
      op &= UINT64_C(14);
7368
0
      op <<= 12;
7369
0
      Value |= op;
7370
      // op: RdaHiDest
7371
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7372
0
      op &= UINT64_C(14);
7373
0
      op <<= 19;
7374
0
      Value |= op;
7375
      // op: Qm
7376
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
7377
0
      op &= UINT64_C(7);
7378
0
      op <<= 1;
7379
0
      Value |= op;
7380
      // op: Qn
7381
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7382
0
      op &= UINT64_C(7);
7383
0
      op <<= 17;
7384
0
      Value |= op;
7385
0
      break;
7386
0
    }
7387
0
    case ARM::tADDrSP: {
7388
      // op: Rdn
7389
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7390
0
      Value |= (op & UINT64_C(8)) << 4;
7391
0
      Value |= (op & UINT64_C(7));
7392
0
      break;
7393
0
    }
7394
0
    case ARM::tADDhirr: {
7395
      // op: Rdn
7396
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7397
0
      Value |= (op & UINT64_C(8)) << 4;
7398
0
      Value |= (op & UINT64_C(7));
7399
      // op: Rm
7400
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7401
0
      op &= UINT64_C(15);
7402
0
      op <<= 3;
7403
0
      Value |= op;
7404
0
      break;
7405
0
    }
7406
0
    case ARM::tADC:
7407
0
    case ARM::tAND:
7408
0
    case ARM::tASRrr:
7409
0
    case ARM::tBIC:
7410
0
    case ARM::tEOR:
7411
0
    case ARM::tLSLrr:
7412
0
    case ARM::tLSRrr:
7413
0
    case ARM::tORR:
7414
0
    case ARM::tROR:
7415
0
    case ARM::tSBC: {
7416
      // op: Rdn
7417
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7418
0
      op &= UINT64_C(7);
7419
0
      Value |= op;
7420
      // op: Rm
7421
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7422
0
      op &= UINT64_C(7);
7423
0
      op <<= 3;
7424
0
      Value |= op;
7425
0
      break;
7426
0
    }
7427
0
    case ARM::tADDi8: {
7428
      // op: Rdn
7429
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7430
0
      op &= UINT64_C(7);
7431
0
      op <<= 8;
7432
0
      Value |= op;
7433
      // op: imm8
7434
0
      op = getHiLoImmOpValue(MI, 3, Fixups, STI);
7435
0
      op &= UINT64_C(255);
7436
0
      Value |= op;
7437
0
      break;
7438
0
    }
7439
0
    case ARM::tSUBi8: {
7440
      // op: Rdn
7441
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7442
0
      op &= UINT64_C(7);
7443
0
      op <<= 8;
7444
0
      Value |= op;
7445
      // op: imm8
7446
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7447
0
      op &= UINT64_C(255);
7448
0
      Value |= op;
7449
0
      break;
7450
0
    }
7451
0
    case ARM::tBX:
7452
0
    case ARM::tBXNS: {
7453
      // op: Rm
7454
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7455
0
      op &= UINT64_C(15);
7456
0
      op <<= 3;
7457
0
      Value |= op;
7458
0
      break;
7459
0
    }
7460
0
    case ARM::tCMPhir: {
7461
      // op: Rm
7462
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7463
0
      op &= UINT64_C(15);
7464
0
      op <<= 3;
7465
0
      Value |= op;
7466
      // op: Rn
7467
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7468
0
      Value |= (op & UINT64_C(8)) << 4;
7469
0
      Value |= (op & UINT64_C(7));
7470
0
      break;
7471
0
    }
7472
0
    case ARM::tREV:
7473
0
    case ARM::tREV16:
7474
0
    case ARM::tREVSH:
7475
0
    case ARM::tSXTB:
7476
0
    case ARM::tSXTH:
7477
0
    case ARM::tUXTB:
7478
0
    case ARM::tUXTH: {
7479
      // op: Rm
7480
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7481
0
      op &= UINT64_C(7);
7482
0
      op <<= 3;
7483
0
      Value |= op;
7484
      // op: Rd
7485
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7486
0
      op &= UINT64_C(7);
7487
0
      Value |= op;
7488
0
      break;
7489
0
    }
7490
0
    case ARM::tCMNz:
7491
0
    case ARM::tCMPr:
7492
0
    case ARM::tTST: {
7493
      // op: Rm
7494
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7495
0
      op &= UINT64_C(7);
7496
0
      op <<= 3;
7497
0
      Value |= op;
7498
      // op: Rn
7499
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7500
0
      op &= UINT64_C(7);
7501
0
      Value |= op;
7502
0
      break;
7503
0
    }
7504
0
    case ARM::tADDspr: {
7505
      // op: Rm
7506
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7507
0
      op &= UINT64_C(15);
7508
0
      op <<= 3;
7509
0
      Value |= op;
7510
0
      break;
7511
0
    }
7512
0
    case ARM::tADDrr:
7513
0
    case ARM::tSUBrr: {
7514
      // op: Rm
7515
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7516
0
      op &= UINT64_C(7);
7517
0
      op <<= 6;
7518
0
      Value |= op;
7519
      // op: Rn
7520
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7521
0
      op &= UINT64_C(7);
7522
0
      op <<= 3;
7523
0
      Value |= op;
7524
      // op: Rd
7525
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7526
0
      op &= UINT64_C(7);
7527
0
      Value |= op;
7528
0
      break;
7529
0
    }
7530
0
    case ARM::RFEDA:
7531
0
    case ARM::RFEDA_UPD:
7532
0
    case ARM::RFEDB:
7533
0
    case ARM::RFEDB_UPD:
7534
0
    case ARM::RFEIA:
7535
0
    case ARM::RFEIA_UPD:
7536
0
    case ARM::RFEIB:
7537
0
    case ARM::RFEIB_UPD:
7538
0
    case ARM::t2RFEDB:
7539
0
    case ARM::t2RFEDBW:
7540
0
    case ARM::t2RFEIA:
7541
0
    case ARM::t2RFEIAW: {
7542
      // op: Rn
7543
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7544
0
      op &= UINT64_C(15);
7545
0
      op <<= 16;
7546
0
      Value |= op;
7547
0
      break;
7548
0
    }
7549
0
    case ARM::t2CMNzrr:
7550
0
    case ARM::t2CMPrr:
7551
0
    case ARM::t2TBB:
7552
0
    case ARM::t2TBH:
7553
0
    case ARM::t2TEQrr:
7554
0
    case ARM::t2TSTrr: {
7555
      // op: Rn
7556
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7557
0
      op &= UINT64_C(15);
7558
0
      op <<= 16;
7559
0
      Value |= op;
7560
      // op: Rm
7561
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7562
0
      op &= UINT64_C(15);
7563
0
      Value |= op;
7564
0
      break;
7565
0
    }
7566
0
    case ARM::t2CMNzrs:
7567
0
    case ARM::t2CMPrs:
7568
0
    case ARM::t2TEQrs:
7569
0
    case ARM::t2TSTrs: {
7570
      // op: Rn
7571
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7572
0
      op &= UINT64_C(15);
7573
0
      op <<= 16;
7574
0
      Value |= op;
7575
      // op: ShiftedRm
7576
0
      op = getT2SORegOpValue(MI, 1, Fixups, STI);
7577
0
      Value |= (op & UINT64_C(3584)) << 3;
7578
0
      Value |= (op & UINT64_C(480)) >> 1;
7579
0
      Value |= (op & UINT64_C(15));
7580
0
      break;
7581
0
    }
7582
0
    case ARM::t2CMNri:
7583
0
    case ARM::t2CMPri:
7584
0
    case ARM::t2TEQri:
7585
0
    case ARM::t2TSTri: {
7586
      // op: Rn
7587
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7588
0
      op &= UINT64_C(15);
7589
0
      op <<= 16;
7590
0
      Value |= op;
7591
      // op: imm
7592
0
      op = getT2SOImmOpValue(MI, 1, Fixups, STI);
7593
0
      Value |= (op & UINT64_C(2048)) << 15;
7594
0
      Value |= (op & UINT64_C(1792)) << 4;
7595
0
      Value |= (op & UINT64_C(255));
7596
0
      break;
7597
0
    }
7598
0
    case ARM::t2STMDB:
7599
0
    case ARM::t2STMIA: {
7600
      // op: Rn
7601
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7602
0
      op &= UINT64_C(15);
7603
0
      op <<= 16;
7604
0
      Value |= op;
7605
      // op: regs
7606
0
      op = getRegisterListOpValue(MI, 3, Fixups, STI);
7607
0
      Value |= (op & UINT64_C(16384));
7608
0
      Value |= (op & UINT64_C(8191));
7609
0
      break;
7610
0
    }
7611
0
    case ARM::t2LDMDB:
7612
0
    case ARM::t2LDMIA: {
7613
      // op: Rn
7614
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7615
0
      op &= UINT64_C(15);
7616
0
      op <<= 16;
7617
0
      Value |= op;
7618
      // op: regs
7619
0
      op = getRegisterListOpValue(MI, 3, Fixups, STI);
7620
0
      op &= UINT64_C(65535);
7621
0
      Value |= op;
7622
0
      break;
7623
0
    }
7624
0
    case ARM::tCMPi8: {
7625
      // op: Rn
7626
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7627
0
      op &= UINT64_C(7);
7628
0
      op <<= 8;
7629
0
      Value |= op;
7630
      // op: imm8
7631
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7632
0
      op &= UINT64_C(255);
7633
0
      Value |= op;
7634
0
      break;
7635
0
    }
7636
0
    case ARM::tLDMIA: {
7637
      // op: Rn
7638
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7639
0
      op &= UINT64_C(7);
7640
0
      op <<= 8;
7641
0
      Value |= op;
7642
      // op: regs
7643
0
      op = getRegisterListOpValue(MI, 3, Fixups, STI);
7644
0
      op &= UINT64_C(255);
7645
0
      Value |= op;
7646
0
      break;
7647
0
    }
7648
0
    case ARM::MVE_DLSTP_8:
7649
0
    case ARM::MVE_DLSTP_16:
7650
0
    case ARM::MVE_DLSTP_32:
7651
0
    case ARM::MVE_DLSTP_64:
7652
0
    case ARM::MVE_VCTP8:
7653
0
    case ARM::MVE_VCTP16:
7654
0
    case ARM::MVE_VCTP32:
7655
0
    case ARM::MVE_VCTP64:
7656
0
    case ARM::t2DLS: {
7657
      // op: Rn
7658
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7659
0
      op &= UINT64_C(15);
7660
0
      op <<= 16;
7661
0
      Value |= op;
7662
0
      break;
7663
0
    }
7664
0
    case ARM::t2TT:
7665
0
    case ARM::t2TTA:
7666
0
    case ARM::t2TTAT:
7667
0
    case ARM::t2TTT: {
7668
      // op: Rn
7669
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7670
0
      op &= UINT64_C(15);
7671
0
      op <<= 16;
7672
0
      Value |= op;
7673
      // op: Rt
7674
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7675
0
      op &= UINT64_C(15);
7676
0
      op <<= 8;
7677
0
      Value |= op;
7678
0
      break;
7679
0
    }
7680
0
    case ARM::MVE_WLSTP_8:
7681
0
    case ARM::MVE_WLSTP_16:
7682
0
    case ARM::MVE_WLSTP_32:
7683
0
    case ARM::MVE_WLSTP_64:
7684
0
    case ARM::t2WLS: {
7685
      // op: Rn
7686
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7687
0
      op &= UINT64_C(15);
7688
0
      op <<= 16;
7689
0
      Value |= op;
7690
      // op: label
7691
0
      op = getBFTargetOpValue<false, ARM::fixup_wls>(MI, 2, Fixups, STI);
7692
0
      Value |= (op & UINT64_C(1)) << 11;
7693
0
      Value |= (op & UINT64_C(2046));
7694
0
      break;
7695
0
    }
7696
0
    case ARM::t2STMDB_UPD:
7697
0
    case ARM::t2STMIA_UPD: {
7698
      // op: Rn
7699
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7700
0
      op &= UINT64_C(15);
7701
0
      op <<= 16;
7702
0
      Value |= op;
7703
      // op: regs
7704
0
      op = getRegisterListOpValue(MI, 4, Fixups, STI);
7705
0
      Value |= (op & UINT64_C(16384));
7706
0
      Value |= (op & UINT64_C(8191));
7707
0
      break;
7708
0
    }
7709
0
    case ARM::t2LDMDB_UPD:
7710
0
    case ARM::t2LDMIA_UPD: {
7711
      // op: Rn
7712
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7713
0
      op &= UINT64_C(15);
7714
0
      op <<= 16;
7715
0
      Value |= op;
7716
      // op: regs
7717
0
      op = getRegisterListOpValue(MI, 4, Fixups, STI);
7718
0
      op &= UINT64_C(65535);
7719
0
      Value |= op;
7720
0
      break;
7721
0
    }
7722
0
    case ARM::tSTMIA_UPD: {
7723
      // op: Rn
7724
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7725
0
      op &= UINT64_C(7);
7726
0
      op <<= 8;
7727
0
      Value |= op;
7728
      // op: regs
7729
0
      op = getRegisterListOpValue(MI, 4, Fixups, STI);
7730
0
      op &= UINT64_C(255);
7731
0
      Value |= op;
7732
0
      break;
7733
0
    }
7734
0
    case ARM::MVE_VMOV_rr_q: {
7735
      // op: Rt
7736
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7737
0
      op &= UINT64_C(15);
7738
0
      Value |= op;
7739
      // op: Rt2
7740
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7741
0
      op &= UINT64_C(15);
7742
0
      op <<= 16;
7743
0
      Value |= op;
7744
      // op: Qd
7745
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7746
0
      Value |= (op & UINT64_C(8)) << 19;
7747
0
      Value |= (op & UINT64_C(7)) << 13;
7748
      // op: idx2
7749
0
      op = getMVEPairVectorIndexOpValue<0>(MI, 4, Fixups, STI);
7750
0
      op &= UINT64_C(1);
7751
0
      op <<= 4;
7752
0
      Value |= op;
7753
0
      break;
7754
0
    }
7755
0
    case ARM::t2LDRB_POST:
7756
0
    case ARM::t2LDRH_POST:
7757
0
    case ARM::t2LDRSB_POST:
7758
0
    case ARM::t2LDRSH_POST:
7759
0
    case ARM::t2LDR_POST: {
7760
      // op: Rt
7761
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7762
0
      op &= UINT64_C(15);
7763
0
      op <<= 12;
7764
0
      Value |= op;
7765
      // op: Rn
7766
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7767
0
      op &= UINT64_C(15);
7768
0
      op <<= 16;
7769
0
      Value |= op;
7770
      // op: offset
7771
0
      op = getT2AddrModeImm8OffsetOpValue(MI, 3, Fixups, STI);
7772
0
      Value |= (op & UINT64_C(256)) << 1;
7773
0
      Value |= (op & UINT64_C(255));
7774
0
      break;
7775
0
    }
7776
0
    case ARM::MRRC2:
7777
0
    case ARM::t2MRRC:
7778
0
    case ARM::t2MRRC2: {
7779
      // op: Rt
7780
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7781
0
      op &= UINT64_C(15);
7782
0
      op <<= 12;
7783
0
      Value |= op;
7784
      // op: Rt2
7785
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7786
0
      op &= UINT64_C(15);
7787
0
      op <<= 16;
7788
0
      Value |= op;
7789
      // op: cop
7790
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7791
0
      op &= UINT64_C(15);
7792
0
      op <<= 8;
7793
0
      Value |= op;
7794
      // op: opc1
7795
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7796
0
      op &= UINT64_C(15);
7797
0
      op <<= 4;
7798
0
      Value |= op;
7799
      // op: CRm
7800
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7801
0
      op &= UINT64_C(15);
7802
0
      Value |= op;
7803
0
      break;
7804
0
    }
7805
0
    case ARM::t2LDRD_POST: {
7806
      // op: Rt
7807
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7808
0
      op &= UINT64_C(15);
7809
0
      op <<= 12;
7810
0
      Value |= op;
7811
      // op: Rt2
7812
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7813
0
      op &= UINT64_C(15);
7814
0
      op <<= 8;
7815
0
      Value |= op;
7816
      // op: addr
7817
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7818
0
      op &= UINT64_C(15);
7819
0
      op <<= 16;
7820
0
      Value |= op;
7821
      // op: imm
7822
0
      op = getT2ScaledImmOpValue<8,2>(MI, 4, Fixups, STI);
7823
0
      Value |= (op & UINT64_C(256)) << 15;
7824
0
      Value |= (op & UINT64_C(255));
7825
0
      break;
7826
0
    }
7827
0
    case ARM::t2LDRDi8:
7828
0
    case ARM::t2STRDi8: {
7829
      // op: Rt
7830
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7831
0
      op &= UINT64_C(15);
7832
0
      op <<= 12;
7833
0
      Value |= op;
7834
      // op: Rt2
7835
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7836
0
      op &= UINT64_C(15);
7837
0
      op <<= 8;
7838
0
      Value |= op;
7839
      // op: addr
7840
0
      op = getT2AddrModeImm8s4OpValue(MI, 2, Fixups, STI);
7841
0
      Value |= (op & UINT64_C(256)) << 15;
7842
0
      Value |= (op & UINT64_C(7680)) << 7;
7843
0
      Value |= (op & UINT64_C(255));
7844
0
      break;
7845
0
    }
7846
0
    case ARM::t2LDRD_PRE: {
7847
      // op: Rt
7848
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7849
0
      op &= UINT64_C(15);
7850
0
      op <<= 12;
7851
0
      Value |= op;
7852
      // op: Rt2
7853
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7854
0
      op &= UINT64_C(15);
7855
0
      op <<= 8;
7856
0
      Value |= op;
7857
      // op: addr
7858
0
      op = getT2AddrModeImm8s4OpValue(MI, 3, Fixups, STI);
7859
0
      Value |= (op & UINT64_C(256)) << 15;
7860
0
      Value |= (op & UINT64_C(7680)) << 7;
7861
0
      Value |= (op & UINT64_C(255));
7862
0
      break;
7863
0
    }
7864
0
    case ARM::t2LDRBi12:
7865
0
    case ARM::t2LDRHi12:
7866
0
    case ARM::t2LDRSBi12:
7867
0
    case ARM::t2LDRSHi12:
7868
0
    case ARM::t2LDRi12:
7869
0
    case ARM::t2STRBi12:
7870
0
    case ARM::t2STRHi12:
7871
0
    case ARM::t2STRi12: {
7872
      // op: Rt
7873
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7874
0
      op &= UINT64_C(15);
7875
0
      op <<= 12;
7876
0
      Value |= op;
7877
      // op: addr
7878
0
      op = getAddrModeImm12OpValue(MI, 1, Fixups, STI);
7879
0
      Value |= (op & UINT64_C(122880)) << 3;
7880
0
      Value |= (op & UINT64_C(4095));
7881
0
      break;
7882
0
    }
7883
0
    case ARM::t2LDRBpci:
7884
0
    case ARM::t2LDRHpci:
7885
0
    case ARM::t2LDRSBpci:
7886
0
    case ARM::t2LDRSHpci:
7887
0
    case ARM::t2LDRpci: {
7888
      // op: Rt
7889
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7890
0
      op &= UINT64_C(15);
7891
0
      op <<= 12;
7892
0
      Value |= op;
7893
      // op: addr
7894
0
      op = getAddrModeImm12OpValue(MI, 1, Fixups, STI);
7895
0
      Value |= (op & UINT64_C(4096)) << 11;
7896
0
      Value |= (op & UINT64_C(4095));
7897
0
      break;
7898
0
    }
7899
0
    case ARM::t2LDA:
7900
0
    case ARM::t2LDAB:
7901
0
    case ARM::t2LDAEX:
7902
0
    case ARM::t2LDAH:
7903
0
    case ARM::t2STL:
7904
0
    case ARM::t2STLB:
7905
0
    case ARM::t2STLH: {
7906
      // op: Rt
7907
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7908
0
      op &= UINT64_C(15);
7909
0
      op <<= 12;
7910
0
      Value |= op;
7911
      // op: addr
7912
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7913
0
      op &= UINT64_C(15);
7914
0
      op <<= 16;
7915
0
      Value |= op;
7916
0
      break;
7917
0
    }
7918
0
    case ARM::t2LDREX: {
7919
      // op: Rt
7920
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7921
0
      op &= UINT64_C(15);
7922
0
      op <<= 12;
7923
0
      Value |= op;
7924
      // op: addr
7925
0
      op = getT2AddrModeImm0_1020s4OpValue(MI, 1, Fixups, STI);
7926
0
      Value |= (op & UINT64_C(3840)) << 8;
7927
0
      Value |= (op & UINT64_C(255));
7928
0
      break;
7929
0
    }
7930
0
    case ARM::t2LDRBT:
7931
0
    case ARM::t2LDRHT:
7932
0
    case ARM::t2LDRSBT:
7933
0
    case ARM::t2LDRSHT:
7934
0
    case ARM::t2LDRT:
7935
0
    case ARM::t2STRBT:
7936
0
    case ARM::t2STRHT:
7937
0
    case ARM::t2STRT: {
7938
      // op: Rt
7939
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7940
0
      op &= UINT64_C(15);
7941
0
      op <<= 12;
7942
0
      Value |= op;
7943
      // op: addr
7944
0
      op = getT2AddrModeImmOpValue<8,0>(MI, 1, Fixups, STI);
7945
0
      Value |= (op & UINT64_C(7680)) << 7;
7946
0
      Value |= (op & UINT64_C(255));
7947
0
      break;
7948
0
    }
7949
0
    case ARM::t2LDRBi8:
7950
0
    case ARM::t2LDRHi8:
7951
0
    case ARM::t2LDRSBi8:
7952
0
    case ARM::t2LDRSHi8:
7953
0
    case ARM::t2LDRi8:
7954
0
    case ARM::t2STRBi8:
7955
0
    case ARM::t2STRHi8:
7956
0
    case ARM::t2STRi8: {
7957
      // op: Rt
7958
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7959
0
      op &= UINT64_C(15);
7960
0
      op <<= 12;
7961
0
      Value |= op;
7962
      // op: addr
7963
0
      op = getT2AddrModeImmOpValue<8,0>(MI, 1, Fixups, STI);
7964
0
      Value |= (op & UINT64_C(7680)) << 7;
7965
0
      Value |= (op & UINT64_C(256)) << 1;
7966
0
      Value |= (op & UINT64_C(255));
7967
0
      break;
7968
0
    }
7969
0
    case ARM::t2LDRB_PRE:
7970
0
    case ARM::t2LDRH_PRE:
7971
0
    case ARM::t2LDRSB_PRE:
7972
0
    case ARM::t2LDRSH_PRE:
7973
0
    case ARM::t2LDR_PRE: {
7974
      // op: Rt
7975
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7976
0
      op &= UINT64_C(15);
7977
0
      op <<= 12;
7978
0
      Value |= op;
7979
      // op: addr
7980
0
      op = getT2AddrModeImmOpValue<8,0>(MI, 2, Fixups, STI);
7981
0
      Value |= (op & UINT64_C(7680)) << 7;
7982
0
      Value |= (op & UINT64_C(256)) << 1;
7983
0
      Value |= (op & UINT64_C(255));
7984
0
      break;
7985
0
    }
7986
0
    case ARM::t2LDRBs:
7987
0
    case ARM::t2LDRHs:
7988
0
    case ARM::t2LDRSBs:
7989
0
    case ARM::t2LDRSHs:
7990
0
    case ARM::t2LDRs:
7991
0
    case ARM::t2STRBs:
7992
0
    case ARM::t2STRHs:
7993
0
    case ARM::t2STRs: {
7994
      // op: Rt
7995
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7996
0
      op &= UINT64_C(15);
7997
0
      op <<= 12;
7998
0
      Value |= op;
7999
      // op: addr
8000
0
      op = getT2AddrModeSORegOpValue(MI, 1, Fixups, STI);
8001
0
      Value |= (op & UINT64_C(960)) << 10;
8002
0
      Value |= (op & UINT64_C(3)) << 4;
8003
0
      Value |= (op & UINT64_C(60)) >> 2;
8004
0
      break;
8005
0
    }
8006
0
    case ARM::MRC2:
8007
0
    case ARM::t2MRC:
8008
0
    case ARM::t2MRC2: {
8009
      // op: Rt
8010
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8011
0
      op &= UINT64_C(15);
8012
0
      op <<= 12;
8013
0
      Value |= op;
8014
      // op: cop
8015
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8016
0
      op &= UINT64_C(15);
8017
0
      op <<= 8;
8018
0
      Value |= op;
8019
      // op: opc1
8020
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8021
0
      op &= UINT64_C(7);
8022
0
      op <<= 21;
8023
0
      Value |= op;
8024
      // op: opc2
8025
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
8026
0
      op &= UINT64_C(7);
8027
0
      op <<= 5;
8028
0
      Value |= op;
8029
      // op: CRm
8030
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8031
0
      op &= UINT64_C(15);
8032
0
      Value |= op;
8033
      // op: CRn
8034
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8035
0
      op &= UINT64_C(15);
8036
0
      op <<= 16;
8037
0
      Value |= op;
8038
0
      break;
8039
0
    }
8040
0
    case ARM::tLDRBi:
8041
0
    case ARM::tLDRHi:
8042
0
    case ARM::tLDRi:
8043
0
    case ARM::tSTRBi:
8044
0
    case ARM::tSTRHi:
8045
0
    case ARM::tSTRi: {
8046
      // op: Rt
8047
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8048
0
      op &= UINT64_C(7);
8049
0
      Value |= op;
8050
      // op: addr
8051
0
      op = getAddrModeISOpValue(MI, 1, Fixups, STI);
8052
0
      op &= UINT64_C(255);
8053
0
      op <<= 3;
8054
0
      Value |= op;
8055
0
      break;
8056
0
    }
8057
0
    case ARM::tLDRBr:
8058
0
    case ARM::tLDRHr:
8059
0
    case ARM::tLDRSB:
8060
0
    case ARM::tLDRSH:
8061
0
    case ARM::tLDRr:
8062
0
    case ARM::tSTRBr:
8063
0
    case ARM::tSTRHr:
8064
0
    case ARM::tSTRr: {
8065
      // op: Rt
8066
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8067
0
      op &= UINT64_C(7);
8068
0
      Value |= op;
8069
      // op: addr
8070
0
      op = getThumbAddrModeRegRegOpValue(MI, 1, Fixups, STI);
8071
0
      op &= UINT64_C(63);
8072
0
      op <<= 3;
8073
0
      Value |= op;
8074
0
      break;
8075
0
    }
8076
0
    case ARM::tLDRpci: {
8077
      // op: Rt
8078
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8079
0
      op &= UINT64_C(7);
8080
0
      op <<= 8;
8081
0
      Value |= op;
8082
      // op: addr
8083
0
      op = getAddrModePCOpValue(MI, 1, Fixups, STI);
8084
0
      op &= UINT64_C(255);
8085
0
      Value |= op;
8086
0
      break;
8087
0
    }
8088
0
    case ARM::tLDRspi:
8089
0
    case ARM::tSTRspi: {
8090
      // op: Rt
8091
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8092
0
      op &= UINT64_C(7);
8093
0
      op <<= 8;
8094
0
      Value |= op;
8095
      // op: addr
8096
0
      op = getAddrModeThumbSPOpValue(MI, 1, Fixups, STI);
8097
0
      op &= UINT64_C(255);
8098
0
      Value |= op;
8099
0
      break;
8100
0
    }
8101
0
    case ARM::t2STRB_POST:
8102
0
    case ARM::t2STRH_POST:
8103
0
    case ARM::t2STR_POST: {
8104
      // op: Rt
8105
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8106
0
      op &= UINT64_C(15);
8107
0
      op <<= 12;
8108
0
      Value |= op;
8109
      // op: Rn
8110
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8111
0
      op &= UINT64_C(15);
8112
0
      op <<= 16;
8113
0
      Value |= op;
8114
      // op: offset
8115
0
      op = getT2AddrModeImm8OffsetOpValue(MI, 3, Fixups, STI);
8116
0
      Value |= (op & UINT64_C(256)) << 1;
8117
0
      Value |= (op & UINT64_C(255));
8118
0
      break;
8119
0
    }
8120
0
    case ARM::t2STRD_POST: {
8121
      // op: Rt
8122
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8123
0
      op &= UINT64_C(15);
8124
0
      op <<= 12;
8125
0
      Value |= op;
8126
      // op: Rt2
8127
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8128
0
      op &= UINT64_C(15);
8129
0
      op <<= 8;
8130
0
      Value |= op;
8131
      // op: addr
8132
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8133
0
      op &= UINT64_C(15);
8134
0
      op <<= 16;
8135
0
      Value |= op;
8136
      // op: imm
8137
0
      op = getT2ScaledImmOpValue<8,2>(MI, 4, Fixups, STI);
8138
0
      Value |= (op & UINT64_C(256)) << 15;
8139
0
      Value |= (op & UINT64_C(255));
8140
0
      break;
8141
0
    }
8142
0
    case ARM::t2STRD_PRE: {
8143
      // op: Rt
8144
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8145
0
      op &= UINT64_C(15);
8146
0
      op <<= 12;
8147
0
      Value |= op;
8148
      // op: Rt2
8149
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8150
0
      op &= UINT64_C(15);
8151
0
      op <<= 8;
8152
0
      Value |= op;
8153
      // op: addr
8154
0
      op = getT2AddrModeImm8s4OpValue(MI, 3, Fixups, STI);
8155
0
      Value |= (op & UINT64_C(256)) << 15;
8156
0
      Value |= (op & UINT64_C(7680)) << 7;
8157
0
      Value |= (op & UINT64_C(255));
8158
0
      break;
8159
0
    }
8160
0
    case ARM::t2STRB_PRE:
8161
0
    case ARM::t2STRH_PRE:
8162
0
    case ARM::t2STR_PRE: {
8163
      // op: Rt
8164
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8165
0
      op &= UINT64_C(15);
8166
0
      op <<= 12;
8167
0
      Value |= op;
8168
      // op: addr
8169
0
      op = getT2AddrModeImmOpValue<8,0>(MI, 2, Fixups, STI);
8170
0
      Value |= (op & UINT64_C(7680)) << 7;
8171
0
      Value |= (op & UINT64_C(256)) << 1;
8172
0
      Value |= (op & UINT64_C(255));
8173
0
      break;
8174
0
    }
8175
0
    case ARM::MVE_VMOV_q_rr: {
8176
      // op: Rt
8177
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8178
0
      op &= UINT64_C(15);
8179
0
      Value |= op;
8180
      // op: Rt2
8181
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8182
0
      op &= UINT64_C(15);
8183
0
      op <<= 16;
8184
0
      Value |= op;
8185
      // op: Qd
8186
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8187
0
      Value |= (op & UINT64_C(8)) << 19;
8188
0
      Value |= (op & UINT64_C(7)) << 13;
8189
      // op: idx2
8190
0
      op = getMVEPairVectorIndexOpValue<0>(MI, 5, Fixups, STI);
8191
0
      op &= UINT64_C(1);
8192
0
      op <<= 4;
8193
0
      Value |= op;
8194
0
      break;
8195
0
    }
8196
0
    case ARM::MCRR2:
8197
0
    case ARM::t2MCRR:
8198
0
    case ARM::t2MCRR2: {
8199
      // op: Rt
8200
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8201
0
      op &= UINT64_C(15);
8202
0
      op <<= 12;
8203
0
      Value |= op;
8204
      // op: Rt2
8205
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8206
0
      op &= UINT64_C(15);
8207
0
      op <<= 16;
8208
0
      Value |= op;
8209
      // op: cop
8210
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8211
0
      op &= UINT64_C(15);
8212
0
      op <<= 8;
8213
0
      Value |= op;
8214
      // op: opc1
8215
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8216
0
      op &= UINT64_C(15);
8217
0
      op <<= 4;
8218
0
      Value |= op;
8219
      // op: CRm
8220
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8221
0
      op &= UINT64_C(15);
8222
0
      Value |= op;
8223
0
      break;
8224
0
    }
8225
0
    case ARM::MCR2:
8226
0
    case ARM::t2MCR:
8227
0
    case ARM::t2MCR2: {
8228
      // op: Rt
8229
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8230
0
      op &= UINT64_C(15);
8231
0
      op <<= 12;
8232
0
      Value |= op;
8233
      // op: cop
8234
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8235
0
      op &= UINT64_C(15);
8236
0
      op <<= 8;
8237
0
      Value |= op;
8238
      // op: opc1
8239
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8240
0
      op &= UINT64_C(7);
8241
0
      op <<= 21;
8242
0
      Value |= op;
8243
      // op: opc2
8244
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
8245
0
      op &= UINT64_C(7);
8246
0
      op <<= 5;
8247
0
      Value |= op;
8248
      // op: CRm
8249
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8250
0
      op &= UINT64_C(15);
8251
0
      Value |= op;
8252
      // op: CRn
8253
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8254
0
      op &= UINT64_C(15);
8255
0
      op <<= 16;
8256
0
      Value |= op;
8257
0
      break;
8258
0
    }
8259
0
    case ARM::t2MSR_M: {
8260
      // op: SYSm
8261
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8262
0
      Value |= (op & UINT64_C(3072));
8263
0
      Value |= (op & UINT64_C(255));
8264
      // op: Rn
8265
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8266
0
      op &= UINT64_C(15);
8267
0
      op <<= 16;
8268
0
      Value |= op;
8269
0
      break;
8270
0
    }
8271
0
    case ARM::VCVTASD:
8272
0
    case ARM::VCVTAUD:
8273
0
    case ARM::VCVTMSD:
8274
0
    case ARM::VCVTMUD:
8275
0
    case ARM::VCVTNSD:
8276
0
    case ARM::VCVTNUD:
8277
0
    case ARM::VCVTPSD:
8278
0
    case ARM::VCVTPUD: {
8279
      // op: Sd
8280
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8281
0
      Value |= (op & UINT64_C(1)) << 22;
8282
0
      Value |= (op & UINT64_C(30)) << 11;
8283
      // op: Dm
8284
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8285
0
      Value |= (op & UINT64_C(16)) << 1;
8286
0
      Value |= (op & UINT64_C(15));
8287
0
      break;
8288
0
    }
8289
0
    case ARM::VCVTASH:
8290
0
    case ARM::VCVTASS:
8291
0
    case ARM::VCVTAUH:
8292
0
    case ARM::VCVTAUS:
8293
0
    case ARM::VCVTMSH:
8294
0
    case ARM::VCVTMSS:
8295
0
    case ARM::VCVTMUH:
8296
0
    case ARM::VCVTMUS:
8297
0
    case ARM::VCVTNSH:
8298
0
    case ARM::VCVTNSS:
8299
0
    case ARM::VCVTNUH:
8300
0
    case ARM::VCVTNUS:
8301
0
    case ARM::VCVTPSH:
8302
0
    case ARM::VCVTPSS:
8303
0
    case ARM::VCVTPUH:
8304
0
    case ARM::VCVTPUS:
8305
0
    case ARM::VMOVH:
8306
0
    case ARM::VRINTAH:
8307
0
    case ARM::VRINTAS:
8308
0
    case ARM::VRINTMH:
8309
0
    case ARM::VRINTMS:
8310
0
    case ARM::VRINTNH:
8311
0
    case ARM::VRINTNS:
8312
0
    case ARM::VRINTPH:
8313
0
    case ARM::VRINTPS: {
8314
      // op: Sd
8315
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8316
0
      Value |= (op & UINT64_C(1)) << 22;
8317
0
      Value |= (op & UINT64_C(30)) << 11;
8318
      // op: Sm
8319
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8320
0
      Value |= (op & UINT64_C(1)) << 5;
8321
0
      Value |= (op & UINT64_C(30)) >> 1;
8322
0
      break;
8323
0
    }
8324
0
    case ARM::VINSH: {
8325
      // op: Sd
8326
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8327
0
      Value |= (op & UINT64_C(1)) << 22;
8328
0
      Value |= (op & UINT64_C(30)) << 11;
8329
      // op: Sm
8330
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8331
0
      Value |= (op & UINT64_C(1)) << 5;
8332
0
      Value |= (op & UINT64_C(30)) >> 1;
8333
0
      break;
8334
0
    }
8335
0
    case ARM::VFP_VMAXNMH:
8336
0
    case ARM::VFP_VMAXNMS:
8337
0
    case ARM::VFP_VMINNMH:
8338
0
    case ARM::VFP_VMINNMS:
8339
0
    case ARM::VSELEQH:
8340
0
    case ARM::VSELEQS:
8341
0
    case ARM::VSELGEH:
8342
0
    case ARM::VSELGES:
8343
0
    case ARM::VSELGTH:
8344
0
    case ARM::VSELGTS:
8345
0
    case ARM::VSELVSH:
8346
0
    case ARM::VSELVSS: {
8347
      // op: Sd
8348
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8349
0
      Value |= (op & UINT64_C(1)) << 22;
8350
0
      Value |= (op & UINT64_C(30)) << 11;
8351
      // op: Sn
8352
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8353
0
      Value |= (op & UINT64_C(30)) << 15;
8354
0
      Value |= (op & UINT64_C(1)) << 7;
8355
      // op: Sm
8356
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8357
0
      Value |= (op & UINT64_C(1)) << 5;
8358
0
      Value |= (op & UINT64_C(30)) >> 1;
8359
0
      break;
8360
0
    }
8361
0
    case ARM::VDUP8d:
8362
0
    case ARM::VDUP8q:
8363
0
    case ARM::VDUP16d:
8364
0
    case ARM::VDUP16q:
8365
0
    case ARM::VDUP32d:
8366
0
    case ARM::VDUP32q: {
8367
      // op: V
8368
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8369
0
      Value |= (op & UINT64_C(15)) << 16;
8370
0
      Value |= (op & UINT64_C(16)) << 3;
8371
      // op: R
8372
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8373
0
      op &= UINT64_C(15);
8374
0
      op <<= 12;
8375
0
      Value |= op;
8376
      // op: p
8377
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8378
0
      op &= UINT64_C(15);
8379
0
      op <<= 28;
8380
0
      Value |= op;
8381
0
      Value = NEONThumb2DupPostEncoder(MI, Value, STI);
8382
0
      break;
8383
0
    }
8384
0
    case ARM::VSETLNi16: {
8385
      // op: V
8386
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8387
0
      Value |= (op & UINT64_C(15)) << 16;
8388
0
      Value |= (op & UINT64_C(16)) << 3;
8389
      // op: R
8390
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8391
0
      op &= UINT64_C(15);
8392
0
      op <<= 12;
8393
0
      Value |= op;
8394
      // op: p
8395
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8396
0
      op &= UINT64_C(15);
8397
0
      op <<= 28;
8398
0
      Value |= op;
8399
      // op: lane
8400
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8401
0
      Value |= (op & UINT64_C(2)) << 20;
8402
0
      Value |= (op & UINT64_C(1)) << 6;
8403
0
      Value = NEONThumb2DupPostEncoder(MI, Value, STI);
8404
0
      break;
8405
0
    }
8406
0
    case ARM::VSETLNi8: {
8407
      // op: V
8408
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8409
0
      Value |= (op & UINT64_C(15)) << 16;
8410
0
      Value |= (op & UINT64_C(16)) << 3;
8411
      // op: R
8412
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8413
0
      op &= UINT64_C(15);
8414
0
      op <<= 12;
8415
0
      Value |= op;
8416
      // op: p
8417
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8418
0
      op &= UINT64_C(15);
8419
0
      op <<= 28;
8420
0
      Value |= op;
8421
      // op: lane
8422
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8423
0
      Value |= (op & UINT64_C(4)) << 19;
8424
0
      Value |= (op & UINT64_C(3)) << 5;
8425
0
      Value = NEONThumb2DupPostEncoder(MI, Value, STI);
8426
0
      break;
8427
0
    }
8428
0
    case ARM::VSETLNi32: {
8429
      // op: V
8430
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8431
0
      Value |= (op & UINT64_C(15)) << 16;
8432
0
      Value |= (op & UINT64_C(16)) << 3;
8433
      // op: R
8434
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8435
0
      op &= UINT64_C(15);
8436
0
      op <<= 12;
8437
0
      Value |= op;
8438
      // op: p
8439
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8440
0
      op &= UINT64_C(15);
8441
0
      op <<= 28;
8442
0
      Value |= op;
8443
      // op: lane
8444
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8445
0
      op &= UINT64_C(1);
8446
0
      op <<= 21;
8447
0
      Value |= op;
8448
0
      Value = NEONThumb2DupPostEncoder(MI, Value, STI);
8449
0
      break;
8450
0
    }
8451
0
    case ARM::VGETLNs16:
8452
0
    case ARM::VGETLNu16: {
8453
      // op: V
8454
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8455
0
      Value |= (op & UINT64_C(15)) << 16;
8456
0
      Value |= (op & UINT64_C(16)) << 3;
8457
      // op: R
8458
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8459
0
      op &= UINT64_C(15);
8460
0
      op <<= 12;
8461
0
      Value |= op;
8462
      // op: p
8463
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8464
0
      op &= UINT64_C(15);
8465
0
      op <<= 28;
8466
0
      Value |= op;
8467
      // op: lane
8468
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8469
0
      Value |= (op & UINT64_C(2)) << 20;
8470
0
      Value |= (op & UINT64_C(1)) << 6;
8471
0
      Value = NEONThumb2DupPostEncoder(MI, Value, STI);
8472
0
      break;
8473
0
    }
8474
0
    case ARM::VGETLNs8:
8475
0
    case ARM::VGETLNu8: {
8476
      // op: V
8477
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8478
0
      Value |= (op & UINT64_C(15)) << 16;
8479
0
      Value |= (op & UINT64_C(16)) << 3;
8480
      // op: R
8481
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8482
0
      op &= UINT64_C(15);
8483
0
      op <<= 12;
8484
0
      Value |= op;
8485
      // op: p
8486
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8487
0
      op &= UINT64_C(15);
8488
0
      op <<= 28;
8489
0
      Value |= op;
8490
      // op: lane
8491
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8492
0
      Value |= (op & UINT64_C(4)) << 19;
8493
0
      Value |= (op & UINT64_C(3)) << 5;
8494
0
      Value = NEONThumb2DupPostEncoder(MI, Value, STI);
8495
0
      break;
8496
0
    }
8497
0
    case ARM::VGETLNi32: {
8498
      // op: V
8499
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8500
0
      Value |= (op & UINT64_C(15)) << 16;
8501
0
      Value |= (op & UINT64_C(16)) << 3;
8502
      // op: R
8503
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8504
0
      op &= UINT64_C(15);
8505
0
      op <<= 12;
8506
0
      Value |= op;
8507
      // op: p
8508
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8509
0
      op &= UINT64_C(15);
8510
0
      op <<= 28;
8511
0
      Value |= op;
8512
      // op: lane
8513
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8514
0
      op &= UINT64_C(1);
8515
0
      op <<= 21;
8516
0
      Value |= op;
8517
0
      Value = NEONThumb2DupPostEncoder(MI, Value, STI);
8518
0
      break;
8519
0
    }
8520
0
    case ARM::MVE_VST20_8:
8521
0
    case ARM::MVE_VST20_16:
8522
0
    case ARM::MVE_VST20_32:
8523
0
    case ARM::MVE_VST21_8:
8524
0
    case ARM::MVE_VST21_16:
8525
0
    case ARM::MVE_VST21_32:
8526
0
    case ARM::MVE_VST40_8:
8527
0
    case ARM::MVE_VST40_16:
8528
0
    case ARM::MVE_VST40_32:
8529
0
    case ARM::MVE_VST41_8:
8530
0
    case ARM::MVE_VST41_16:
8531
0
    case ARM::MVE_VST41_32:
8532
0
    case ARM::MVE_VST42_8:
8533
0
    case ARM::MVE_VST42_16:
8534
0
    case ARM::MVE_VST42_32:
8535
0
    case ARM::MVE_VST43_8:
8536
0
    case ARM::MVE_VST43_16:
8537
0
    case ARM::MVE_VST43_32: {
8538
      // op: VQd
8539
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8540
0
      op &= UINT64_C(7);
8541
0
      op <<= 13;
8542
0
      Value |= op;
8543
      // op: Rn
8544
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8545
0
      op &= UINT64_C(15);
8546
0
      op <<= 16;
8547
0
      Value |= op;
8548
0
      break;
8549
0
    }
8550
0
    case ARM::MVE_VLD20_8:
8551
0
    case ARM::MVE_VLD20_16:
8552
0
    case ARM::MVE_VLD20_32:
8553
0
    case ARM::MVE_VLD21_8:
8554
0
    case ARM::MVE_VLD21_16:
8555
0
    case ARM::MVE_VLD21_32:
8556
0
    case ARM::MVE_VLD40_8:
8557
0
    case ARM::MVE_VLD40_16:
8558
0
    case ARM::MVE_VLD40_32:
8559
0
    case ARM::MVE_VLD41_8:
8560
0
    case ARM::MVE_VLD41_16:
8561
0
    case ARM::MVE_VLD41_32:
8562
0
    case ARM::MVE_VLD42_8:
8563
0
    case ARM::MVE_VLD42_16:
8564
0
    case ARM::MVE_VLD42_32:
8565
0
    case ARM::MVE_VLD43_8:
8566
0
    case ARM::MVE_VLD43_16:
8567
0
    case ARM::MVE_VLD43_32: {
8568
      // op: VQd
8569
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8570
0
      op &= UINT64_C(7);
8571
0
      op <<= 13;
8572
0
      Value |= op;
8573
      // op: Rn
8574
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8575
0
      op &= UINT64_C(15);
8576
0
      op <<= 16;
8577
0
      Value |= op;
8578
0
      break;
8579
0
    }
8580
0
    case ARM::MVE_VLD20_8_wb:
8581
0
    case ARM::MVE_VLD20_16_wb:
8582
0
    case ARM::MVE_VLD20_32_wb:
8583
0
    case ARM::MVE_VLD21_8_wb:
8584
0
    case ARM::MVE_VLD21_16_wb:
8585
0
    case ARM::MVE_VLD21_32_wb:
8586
0
    case ARM::MVE_VLD40_8_wb:
8587
0
    case ARM::MVE_VLD40_16_wb:
8588
0
    case ARM::MVE_VLD40_32_wb:
8589
0
    case ARM::MVE_VLD41_8_wb:
8590
0
    case ARM::MVE_VLD41_16_wb:
8591
0
    case ARM::MVE_VLD41_32_wb:
8592
0
    case ARM::MVE_VLD42_8_wb:
8593
0
    case ARM::MVE_VLD42_16_wb:
8594
0
    case ARM::MVE_VLD42_32_wb:
8595
0
    case ARM::MVE_VLD43_8_wb:
8596
0
    case ARM::MVE_VLD43_16_wb:
8597
0
    case ARM::MVE_VLD43_32_wb: {
8598
      // op: VQd
8599
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8600
0
      op &= UINT64_C(7);
8601
0
      op <<= 13;
8602
0
      Value |= op;
8603
      // op: Rn
8604
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8605
0
      op &= UINT64_C(15);
8606
0
      op <<= 16;
8607
0
      Value |= op;
8608
0
      break;
8609
0
    }
8610
0
    case ARM::MVE_VST20_8_wb:
8611
0
    case ARM::MVE_VST20_16_wb:
8612
0
    case ARM::MVE_VST20_32_wb:
8613
0
    case ARM::MVE_VST21_8_wb:
8614
0
    case ARM::MVE_VST21_16_wb:
8615
0
    case ARM::MVE_VST21_32_wb:
8616
0
    case ARM::MVE_VST40_8_wb:
8617
0
    case ARM::MVE_VST40_16_wb:
8618
0
    case ARM::MVE_VST40_32_wb:
8619
0
    case ARM::MVE_VST41_8_wb:
8620
0
    case ARM::MVE_VST41_16_wb:
8621
0
    case ARM::MVE_VST41_32_wb:
8622
0
    case ARM::MVE_VST42_8_wb:
8623
0
    case ARM::MVE_VST42_16_wb:
8624
0
    case ARM::MVE_VST42_32_wb:
8625
0
    case ARM::MVE_VST43_8_wb:
8626
0
    case ARM::MVE_VST43_16_wb:
8627
0
    case ARM::MVE_VST43_32_wb: {
8628
      // op: VQd
8629
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8630
0
      op &= UINT64_C(7);
8631
0
      op <<= 13;
8632
0
      Value |= op;
8633
      // op: Rn
8634
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8635
0
      op &= UINT64_C(15);
8636
0
      op <<= 16;
8637
0
      Value |= op;
8638
0
      break;
8639
0
    }
8640
0
    case ARM::VLD1d8:
8641
0
    case ARM::VLD1d8T:
8642
0
    case ARM::VLD1d16:
8643
0
    case ARM::VLD1d16T:
8644
0
    case ARM::VLD1d32:
8645
0
    case ARM::VLD1d32T:
8646
0
    case ARM::VLD1d64:
8647
0
    case ARM::VLD1d64T: {
8648
      // op: Vd
8649
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8650
0
      Value |= (op & UINT64_C(16)) << 18;
8651
0
      Value |= (op & UINT64_C(15)) << 12;
8652
      // op: Rn
8653
0
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
8654
0
      Value |= (op & UINT64_C(15)) << 16;
8655
0
      Value |= (op & UINT64_C(16));
8656
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8657
0
      break;
8658
0
    }
8659
0
    case ARM::VLD1LNd16: {
8660
      // op: Vd
8661
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8662
0
      Value |= (op & UINT64_C(16)) << 18;
8663
0
      Value |= (op & UINT64_C(15)) << 12;
8664
      // op: Rn
8665
0
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
8666
0
      Value |= (op & UINT64_C(15)) << 16;
8667
0
      Value |= (op & UINT64_C(48));
8668
      // op: lane
8669
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8670
0
      op &= UINT64_C(3);
8671
0
      op <<= 6;
8672
0
      Value |= op;
8673
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8674
0
      break;
8675
0
    }
8676
0
    case ARM::VLD1d8Q:
8677
0
    case ARM::VLD1d16Q:
8678
0
    case ARM::VLD1d32Q:
8679
0
    case ARM::VLD1d64Q:
8680
0
    case ARM::VLD1q8:
8681
0
    case ARM::VLD1q16:
8682
0
    case ARM::VLD1q32:
8683
0
    case ARM::VLD1q64:
8684
0
    case ARM::VLD2b8:
8685
0
    case ARM::VLD2b16:
8686
0
    case ARM::VLD2b32:
8687
0
    case ARM::VLD2d8:
8688
0
    case ARM::VLD2d16:
8689
0
    case ARM::VLD2d32:
8690
0
    case ARM::VLD2q8:
8691
0
    case ARM::VLD2q16:
8692
0
    case ARM::VLD2q32: {
8693
      // op: Vd
8694
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8695
0
      Value |= (op & UINT64_C(16)) << 18;
8696
0
      Value |= (op & UINT64_C(15)) << 12;
8697
      // op: Rn
8698
0
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
8699
0
      Value |= (op & UINT64_C(15)) << 16;
8700
0
      Value |= (op & UINT64_C(48));
8701
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8702
0
      break;
8703
0
    }
8704
0
    case ARM::VLD1LNd8: {
8705
      // op: Vd
8706
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8707
0
      Value |= (op & UINT64_C(16)) << 18;
8708
0
      Value |= (op & UINT64_C(15)) << 12;
8709
      // op: Rn
8710
0
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
8711
0
      op &= UINT64_C(15);
8712
0
      op <<= 16;
8713
0
      Value |= op;
8714
      // op: lane
8715
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8716
0
      op &= UINT64_C(7);
8717
0
      op <<= 5;
8718
0
      Value |= op;
8719
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8720
0
      break;
8721
0
    }
8722
0
    case ARM::VLD1LNd32_UPD: {
8723
      // op: Vd
8724
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8725
0
      Value |= (op & UINT64_C(16)) << 18;
8726
0
      Value |= (op & UINT64_C(15)) << 12;
8727
      // op: Rn
8728
0
      op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
8729
0
      Value |= (op & UINT64_C(15)) << 16;
8730
0
      Value |= (op & UINT64_C(16)) << 1;
8731
0
      Value |= (op & UINT64_C(16));
8732
      // op: Rm
8733
0
      op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI);
8734
0
      op &= UINT64_C(15);
8735
0
      Value |= op;
8736
      // op: lane
8737
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
8738
0
      op &= UINT64_C(1);
8739
0
      op <<= 7;
8740
0
      Value |= op;
8741
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8742
0
      break;
8743
0
    }
8744
0
    case ARM::VLD1LNd16_UPD: {
8745
      // op: Vd
8746
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8747
0
      Value |= (op & UINT64_C(16)) << 18;
8748
0
      Value |= (op & UINT64_C(15)) << 12;
8749
      // op: Rn
8750
0
      op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
8751
0
      Value |= (op & UINT64_C(15)) << 16;
8752
0
      Value |= (op & UINT64_C(16));
8753
      // op: Rm
8754
0
      op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI);
8755
0
      op &= UINT64_C(15);
8756
0
      Value |= op;
8757
      // op: lane
8758
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
8759
0
      op &= UINT64_C(3);
8760
0
      op <<= 6;
8761
0
      Value |= op;
8762
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8763
0
      break;
8764
0
    }
8765
0
    case ARM::VLD1d8Twb_register:
8766
0
    case ARM::VLD1d8wb_register:
8767
0
    case ARM::VLD1d16Twb_register:
8768
0
    case ARM::VLD1d16wb_register:
8769
0
    case ARM::VLD1d32Twb_register:
8770
0
    case ARM::VLD1d32wb_register:
8771
0
    case ARM::VLD1d64Twb_register:
8772
0
    case ARM::VLD1d64wb_register: {
8773
      // op: Vd
8774
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8775
0
      Value |= (op & UINT64_C(16)) << 18;
8776
0
      Value |= (op & UINT64_C(15)) << 12;
8777
      // op: Rn
8778
0
      op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
8779
0
      Value |= (op & UINT64_C(15)) << 16;
8780
0
      Value |= (op & UINT64_C(16));
8781
      // op: Rm
8782
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8783
0
      op &= UINT64_C(15);
8784
0
      Value |= op;
8785
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8786
0
      break;
8787
0
    }
8788
0
    case ARM::VLD2LNd32:
8789
0
    case ARM::VLD2LNq32: {
8790
      // op: Vd
8791
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8792
0
      Value |= (op & UINT64_C(16)) << 18;
8793
0
      Value |= (op & UINT64_C(15)) << 12;
8794
      // op: Rn
8795
0
      op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
8796
0
      Value |= (op & UINT64_C(15)) << 16;
8797
0
      Value |= (op & UINT64_C(16));
8798
      // op: lane
8799
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
8800
0
      op &= UINT64_C(1);
8801
0
      op <<= 7;
8802
0
      Value |= op;
8803
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8804
0
      break;
8805
0
    }
8806
0
    case ARM::VLD2LNd16:
8807
0
    case ARM::VLD2LNq16: {
8808
      // op: Vd
8809
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8810
0
      Value |= (op & UINT64_C(16)) << 18;
8811
0
      Value |= (op & UINT64_C(15)) << 12;
8812
      // op: Rn
8813
0
      op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
8814
0
      Value |= (op & UINT64_C(15)) << 16;
8815
0
      Value |= (op & UINT64_C(16));
8816
      // op: lane
8817
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
8818
0
      op &= UINT64_C(3);
8819
0
      op <<= 6;
8820
0
      Value |= op;
8821
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8822
0
      break;
8823
0
    }
8824
0
    case ARM::VLD2LNd8: {
8825
      // op: Vd
8826
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8827
0
      Value |= (op & UINT64_C(16)) << 18;
8828
0
      Value |= (op & UINT64_C(15)) << 12;
8829
      // op: Rn
8830
0
      op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
8831
0
      Value |= (op & UINT64_C(15)) << 16;
8832
0
      Value |= (op & UINT64_C(16));
8833
      // op: lane
8834
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
8835
0
      op &= UINT64_C(7);
8836
0
      op <<= 5;
8837
0
      Value |= op;
8838
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8839
0
      break;
8840
0
    }
8841
0
    case ARM::VLD1d8Twb_fixed:
8842
0
    case ARM::VLD1d8wb_fixed:
8843
0
    case ARM::VLD1d16Twb_fixed:
8844
0
    case ARM::VLD1d16wb_fixed:
8845
0
    case ARM::VLD1d32Twb_fixed:
8846
0
    case ARM::VLD1d32wb_fixed:
8847
0
    case ARM::VLD1d64Twb_fixed:
8848
0
    case ARM::VLD1d64wb_fixed: {
8849
      // op: Vd
8850
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8851
0
      Value |= (op & UINT64_C(16)) << 18;
8852
0
      Value |= (op & UINT64_C(15)) << 12;
8853
      // op: Rn
8854
0
      op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
8855
0
      Value |= (op & UINT64_C(15)) << 16;
8856
0
      Value |= (op & UINT64_C(16));
8857
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8858
0
      break;
8859
0
    }
8860
0
    case ARM::VLD1d8Qwb_register:
8861
0
    case ARM::VLD1d16Qwb_register:
8862
0
    case ARM::VLD1d32Qwb_register:
8863
0
    case ARM::VLD1d64Qwb_register:
8864
0
    case ARM::VLD1q8wb_register:
8865
0
    case ARM::VLD1q16wb_register:
8866
0
    case ARM::VLD1q32wb_register:
8867
0
    case ARM::VLD1q64wb_register:
8868
0
    case ARM::VLD2b8wb_register:
8869
0
    case ARM::VLD2b16wb_register:
8870
0
    case ARM::VLD2b32wb_register:
8871
0
    case ARM::VLD2d8wb_register:
8872
0
    case ARM::VLD2d16wb_register:
8873
0
    case ARM::VLD2d32wb_register:
8874
0
    case ARM::VLD2q8wb_register:
8875
0
    case ARM::VLD2q16wb_register:
8876
0
    case ARM::VLD2q32wb_register: {
8877
      // op: Vd
8878
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8879
0
      Value |= (op & UINT64_C(16)) << 18;
8880
0
      Value |= (op & UINT64_C(15)) << 12;
8881
      // op: Rn
8882
0
      op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
8883
0
      Value |= (op & UINT64_C(15)) << 16;
8884
0
      Value |= (op & UINT64_C(48));
8885
      // op: Rm
8886
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8887
0
      op &= UINT64_C(15);
8888
0
      Value |= op;
8889
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8890
0
      break;
8891
0
    }
8892
0
    case ARM::VLD1d8Qwb_fixed:
8893
0
    case ARM::VLD1d16Qwb_fixed:
8894
0
    case ARM::VLD1d32Qwb_fixed:
8895
0
    case ARM::VLD1d64Qwb_fixed:
8896
0
    case ARM::VLD1q8wb_fixed:
8897
0
    case ARM::VLD1q16wb_fixed:
8898
0
    case ARM::VLD1q32wb_fixed:
8899
0
    case ARM::VLD1q64wb_fixed:
8900
0
    case ARM::VLD2b8wb_fixed:
8901
0
    case ARM::VLD2b16wb_fixed:
8902
0
    case ARM::VLD2b32wb_fixed:
8903
0
    case ARM::VLD2d8wb_fixed:
8904
0
    case ARM::VLD2d16wb_fixed:
8905
0
    case ARM::VLD2d32wb_fixed:
8906
0
    case ARM::VLD2q8wb_fixed:
8907
0
    case ARM::VLD2q16wb_fixed:
8908
0
    case ARM::VLD2q32wb_fixed: {
8909
      // op: Vd
8910
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8911
0
      Value |= (op & UINT64_C(16)) << 18;
8912
0
      Value |= (op & UINT64_C(15)) << 12;
8913
      // op: Rn
8914
0
      op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
8915
0
      Value |= (op & UINT64_C(15)) << 16;
8916
0
      Value |= (op & UINT64_C(48));
8917
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8918
0
      break;
8919
0
    }
8920
0
    case ARM::VLD1LNd8_UPD: {
8921
      // op: Vd
8922
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8923
0
      Value |= (op & UINT64_C(16)) << 18;
8924
0
      Value |= (op & UINT64_C(15)) << 12;
8925
      // op: Rn
8926
0
      op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
8927
0
      op &= UINT64_C(15);
8928
0
      op <<= 16;
8929
0
      Value |= op;
8930
      // op: Rm
8931
0
      op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI);
8932
0
      op &= UINT64_C(15);
8933
0
      Value |= op;
8934
      // op: lane
8935
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
8936
0
      op &= UINT64_C(7);
8937
0
      op <<= 5;
8938
0
      Value |= op;
8939
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8940
0
      break;
8941
0
    }
8942
0
    case ARM::VLD2LNd32_UPD:
8943
0
    case ARM::VLD2LNq32_UPD: {
8944
      // op: Vd
8945
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8946
0
      Value |= (op & UINT64_C(16)) << 18;
8947
0
      Value |= (op & UINT64_C(15)) << 12;
8948
      // op: Rn
8949
0
      op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI);
8950
0
      Value |= (op & UINT64_C(15)) << 16;
8951
0
      Value |= (op & UINT64_C(16));
8952
      // op: Rm
8953
0
      op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI);
8954
0
      op &= UINT64_C(15);
8955
0
      Value |= op;
8956
      // op: lane
8957
0
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
8958
0
      op &= UINT64_C(1);
8959
0
      op <<= 7;
8960
0
      Value |= op;
8961
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8962
0
      break;
8963
0
    }
8964
0
    case ARM::VLD2LNd16_UPD:
8965
0
    case ARM::VLD2LNq16_UPD: {
8966
      // op: Vd
8967
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8968
0
      Value |= (op & UINT64_C(16)) << 18;
8969
0
      Value |= (op & UINT64_C(15)) << 12;
8970
      // op: Rn
8971
0
      op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI);
8972
0
      Value |= (op & UINT64_C(15)) << 16;
8973
0
      Value |= (op & UINT64_C(16));
8974
      // op: Rm
8975
0
      op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI);
8976
0
      op &= UINT64_C(15);
8977
0
      Value |= op;
8978
      // op: lane
8979
0
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
8980
0
      op &= UINT64_C(3);
8981
0
      op <<= 6;
8982
0
      Value |= op;
8983
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8984
0
      break;
8985
0
    }
8986
0
    case ARM::VLD2LNd8_UPD: {
8987
      // op: Vd
8988
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8989
0
      Value |= (op & UINT64_C(16)) << 18;
8990
0
      Value |= (op & UINT64_C(15)) << 12;
8991
      // op: Rn
8992
0
      op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI);
8993
0
      Value |= (op & UINT64_C(15)) << 16;
8994
0
      Value |= (op & UINT64_C(16));
8995
      // op: Rm
8996
0
      op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI);
8997
0
      op &= UINT64_C(15);
8998
0
      Value |= op;
8999
      // op: lane
9000
0
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
9001
0
      op &= UINT64_C(7);
9002
0
      op <<= 5;
9003
0
      Value |= op;
9004
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9005
0
      break;
9006
0
    }
9007
0
    case ARM::VLD3d8:
9008
0
    case ARM::VLD3d16:
9009
0
    case ARM::VLD3d32:
9010
0
    case ARM::VLD3q8:
9011
0
    case ARM::VLD3q16:
9012
0
    case ARM::VLD3q32: {
9013
      // op: Vd
9014
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9015
0
      Value |= (op & UINT64_C(16)) << 18;
9016
0
      Value |= (op & UINT64_C(15)) << 12;
9017
      // op: Rn
9018
0
      op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI);
9019
0
      Value |= (op & UINT64_C(15)) << 16;
9020
0
      Value |= (op & UINT64_C(16));
9021
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9022
0
      break;
9023
0
    }
9024
0
    case ARM::VLD3LNd32:
9025
0
    case ARM::VLD3LNq32: {
9026
      // op: Vd
9027
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9028
0
      Value |= (op & UINT64_C(16)) << 18;
9029
0
      Value |= (op & UINT64_C(15)) << 12;
9030
      // op: Rn
9031
0
      op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI);
9032
0
      op &= UINT64_C(15);
9033
0
      op <<= 16;
9034
0
      Value |= op;
9035
      // op: lane
9036
0
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
9037
0
      op &= UINT64_C(1);
9038
0
      op <<= 7;
9039
0
      Value |= op;
9040
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9041
0
      break;
9042
0
    }
9043
0
    case ARM::VLD3LNd16:
9044
0
    case ARM::VLD3LNq16: {
9045
      // op: Vd
9046
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9047
0
      Value |= (op & UINT64_C(16)) << 18;
9048
0
      Value |= (op & UINT64_C(15)) << 12;
9049
      // op: Rn
9050
0
      op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI);
9051
0
      op &= UINT64_C(15);
9052
0
      op <<= 16;
9053
0
      Value |= op;
9054
      // op: lane
9055
0
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
9056
0
      op &= UINT64_C(3);
9057
0
      op <<= 6;
9058
0
      Value |= op;
9059
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9060
0
      break;
9061
0
    }
9062
0
    case ARM::VLD3LNd8: {
9063
      // op: Vd
9064
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9065
0
      Value |= (op & UINT64_C(16)) << 18;
9066
0
      Value |= (op & UINT64_C(15)) << 12;
9067
      // op: Rn
9068
0
      op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI);
9069
0
      op &= UINT64_C(15);
9070
0
      op <<= 16;
9071
0
      Value |= op;
9072
      // op: lane
9073
0
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
9074
0
      op &= UINT64_C(7);
9075
0
      op <<= 5;
9076
0
      Value |= op;
9077
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9078
0
      break;
9079
0
    }
9080
0
    case ARM::VLD3d8_UPD:
9081
0
    case ARM::VLD3d16_UPD:
9082
0
    case ARM::VLD3d32_UPD:
9083
0
    case ARM::VLD3q8_UPD:
9084
0
    case ARM::VLD3q16_UPD:
9085
0
    case ARM::VLD3q32_UPD: {
9086
      // op: Vd
9087
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9088
0
      Value |= (op & UINT64_C(16)) << 18;
9089
0
      Value |= (op & UINT64_C(15)) << 12;
9090
      // op: Rn
9091
0
      op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
9092
0
      Value |= (op & UINT64_C(15)) << 16;
9093
0
      Value |= (op & UINT64_C(16));
9094
      // op: Rm
9095
0
      op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI);
9096
0
      op &= UINT64_C(15);
9097
0
      Value |= op;
9098
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9099
0
      break;
9100
0
    }
9101
0
    case ARM::VLD4LNd16:
9102
0
    case ARM::VLD4LNq16: {
9103
      // op: Vd
9104
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9105
0
      Value |= (op & UINT64_C(16)) << 18;
9106
0
      Value |= (op & UINT64_C(15)) << 12;
9107
      // op: Rn
9108
0
      op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
9109
0
      Value |= (op & UINT64_C(15)) << 16;
9110
0
      Value |= (op & UINT64_C(16));
9111
      // op: lane
9112
0
      op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
9113
0
      op &= UINT64_C(3);
9114
0
      op <<= 6;
9115
0
      Value |= op;
9116
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9117
0
      break;
9118
0
    }
9119
0
    case ARM::VLD4LNd8: {
9120
      // op: Vd
9121
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9122
0
      Value |= (op & UINT64_C(16)) << 18;
9123
0
      Value |= (op & UINT64_C(15)) << 12;
9124
      // op: Rn
9125
0
      op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
9126
0
      Value |= (op & UINT64_C(15)) << 16;
9127
0
      Value |= (op & UINT64_C(16));
9128
      // op: lane
9129
0
      op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
9130
0
      op &= UINT64_C(7);
9131
0
      op <<= 5;
9132
0
      Value |= op;
9133
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9134
0
      break;
9135
0
    }
9136
0
    case ARM::VLD4LNd32:
9137
0
    case ARM::VLD4LNq32: {
9138
      // op: Vd
9139
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9140
0
      Value |= (op & UINT64_C(16)) << 18;
9141
0
      Value |= (op & UINT64_C(15)) << 12;
9142
      // op: Rn
9143
0
      op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
9144
0
      Value |= (op & UINT64_C(15)) << 16;
9145
0
      Value |= (op & UINT64_C(48));
9146
      // op: lane
9147
0
      op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
9148
0
      op &= UINT64_C(1);
9149
0
      op <<= 7;
9150
0
      Value |= op;
9151
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9152
0
      break;
9153
0
    }
9154
0
    case ARM::VLD4d8:
9155
0
    case ARM::VLD4d16:
9156
0
    case ARM::VLD4d32:
9157
0
    case ARM::VLD4q8:
9158
0
    case ARM::VLD4q16:
9159
0
    case ARM::VLD4q32: {
9160
      // op: Vd
9161
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9162
0
      Value |= (op & UINT64_C(16)) << 18;
9163
0
      Value |= (op & UINT64_C(15)) << 12;
9164
      // op: Rn
9165
0
      op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
9166
0
      Value |= (op & UINT64_C(15)) << 16;
9167
0
      Value |= (op & UINT64_C(48));
9168
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9169
0
      break;
9170
0
    }
9171
0
    case ARM::VLD3LNd32_UPD:
9172
0
    case ARM::VLD3LNq32_UPD: {
9173
      // op: Vd
9174
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9175
0
      Value |= (op & UINT64_C(16)) << 18;
9176
0
      Value |= (op & UINT64_C(15)) << 12;
9177
      // op: Rn
9178
0
      op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
9179
0
      op &= UINT64_C(15);
9180
0
      op <<= 16;
9181
0
      Value |= op;
9182
      // op: Rm
9183
0
      op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI);
9184
0
      op &= UINT64_C(15);
9185
0
      Value |= op;
9186
      // op: lane
9187
0
      op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
9188
0
      op &= UINT64_C(1);
9189
0
      op <<= 7;
9190
0
      Value |= op;
9191
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9192
0
      break;
9193
0
    }
9194
0
    case ARM::VLD3LNd16_UPD:
9195
0
    case ARM::VLD3LNq16_UPD: {
9196
      // op: Vd
9197
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9198
0
      Value |= (op & UINT64_C(16)) << 18;
9199
0
      Value |= (op & UINT64_C(15)) << 12;
9200
      // op: Rn
9201
0
      op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
9202
0
      op &= UINT64_C(15);
9203
0
      op <<= 16;
9204
0
      Value |= op;
9205
      // op: Rm
9206
0
      op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI);
9207
0
      op &= UINT64_C(15);
9208
0
      Value |= op;
9209
      // op: lane
9210
0
      op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
9211
0
      op &= UINT64_C(3);
9212
0
      op <<= 6;
9213
0
      Value |= op;
9214
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9215
0
      break;
9216
0
    }
9217
0
    case ARM::VLD3LNd8_UPD: {
9218
      // op: Vd
9219
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9220
0
      Value |= (op & UINT64_C(16)) << 18;
9221
0
      Value |= (op & UINT64_C(15)) << 12;
9222
      // op: Rn
9223
0
      op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
9224
0
      op &= UINT64_C(15);
9225
0
      op <<= 16;
9226
0
      Value |= op;
9227
      // op: Rm
9228
0
      op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI);
9229
0
      op &= UINT64_C(15);
9230
0
      Value |= op;
9231
      // op: lane
9232
0
      op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
9233
0
      op &= UINT64_C(7);
9234
0
      op <<= 5;
9235
0
      Value |= op;
9236
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9237
0
      break;
9238
0
    }
9239
0
    case ARM::VLD4LNd16_UPD:
9240
0
    case ARM::VLD4LNq16_UPD: {
9241
      // op: Vd
9242
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9243
0
      Value |= (op & UINT64_C(16)) << 18;
9244
0
      Value |= (op & UINT64_C(15)) << 12;
9245
      // op: Rn
9246
0
      op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI);
9247
0
      Value |= (op & UINT64_C(15)) << 16;
9248
0
      Value |= (op & UINT64_C(16));
9249
      // op: Rm
9250
0
      op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI);
9251
0
      op &= UINT64_C(15);
9252
0
      Value |= op;
9253
      // op: lane
9254
0
      op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI);
9255
0
      op &= UINT64_C(3);
9256
0
      op <<= 6;
9257
0
      Value |= op;
9258
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9259
0
      break;
9260
0
    }
9261
0
    case ARM::VLD4LNd8_UPD: {
9262
      // op: Vd
9263
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9264
0
      Value |= (op & UINT64_C(16)) << 18;
9265
0
      Value |= (op & UINT64_C(15)) << 12;
9266
      // op: Rn
9267
0
      op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI);
9268
0
      Value |= (op & UINT64_C(15)) << 16;
9269
0
      Value |= (op & UINT64_C(16));
9270
      // op: Rm
9271
0
      op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI);
9272
0
      op &= UINT64_C(15);
9273
0
      Value |= op;
9274
      // op: lane
9275
0
      op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI);
9276
0
      op &= UINT64_C(7);
9277
0
      op <<= 5;
9278
0
      Value |= op;
9279
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9280
0
      break;
9281
0
    }
9282
0
    case ARM::VLD4LNd32_UPD:
9283
0
    case ARM::VLD4LNq32_UPD: {
9284
      // op: Vd
9285
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9286
0
      Value |= (op & UINT64_C(16)) << 18;
9287
0
      Value |= (op & UINT64_C(15)) << 12;
9288
      // op: Rn
9289
0
      op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI);
9290
0
      Value |= (op & UINT64_C(15)) << 16;
9291
0
      Value |= (op & UINT64_C(48));
9292
      // op: Rm
9293
0
      op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI);
9294
0
      op &= UINT64_C(15);
9295
0
      Value |= op;
9296
      // op: lane
9297
0
      op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI);
9298
0
      op &= UINT64_C(1);
9299
0
      op <<= 7;
9300
0
      Value |= op;
9301
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9302
0
      break;
9303
0
    }
9304
0
    case ARM::VLD4d8_UPD:
9305
0
    case ARM::VLD4d16_UPD:
9306
0
    case ARM::VLD4d32_UPD:
9307
0
    case ARM::VLD4q8_UPD:
9308
0
    case ARM::VLD4q16_UPD:
9309
0
    case ARM::VLD4q32_UPD: {
9310
      // op: Vd
9311
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9312
0
      Value |= (op & UINT64_C(16)) << 18;
9313
0
      Value |= (op & UINT64_C(15)) << 12;
9314
      // op: Rn
9315
0
      op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI);
9316
0
      Value |= (op & UINT64_C(15)) << 16;
9317
0
      Value |= (op & UINT64_C(48));
9318
      // op: Rm
9319
0
      op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI);
9320
0
      op &= UINT64_C(15);
9321
0
      Value |= op;
9322
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9323
0
      break;
9324
0
    }
9325
0
    case ARM::VLD1DUPd8:
9326
0
    case ARM::VLD1DUPd16:
9327
0
    case ARM::VLD1DUPd32:
9328
0
    case ARM::VLD1DUPq8:
9329
0
    case ARM::VLD1DUPq16:
9330
0
    case ARM::VLD1DUPq32:
9331
0
    case ARM::VLD2DUPd8:
9332
0
    case ARM::VLD2DUPd8x2:
9333
0
    case ARM::VLD2DUPd16:
9334
0
    case ARM::VLD2DUPd16x2:
9335
0
    case ARM::VLD2DUPd32:
9336
0
    case ARM::VLD2DUPd32x2: {
9337
      // op: Vd
9338
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9339
0
      Value |= (op & UINT64_C(16)) << 18;
9340
0
      Value |= (op & UINT64_C(15)) << 12;
9341
      // op: Rn
9342
0
      op = getAddrMode6DupAddressOpValue(MI, 1, Fixups, STI);
9343
0
      Value |= (op & UINT64_C(15)) << 16;
9344
0
      Value |= (op & UINT64_C(16));
9345
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9346
0
      break;
9347
0
    }
9348
0
    case ARM::VLD1DUPd8wb_register:
9349
0
    case ARM::VLD1DUPd16wb_register:
9350
0
    case ARM::VLD1DUPd32wb_register:
9351
0
    case ARM::VLD1DUPq8wb_register:
9352
0
    case ARM::VLD1DUPq16wb_register:
9353
0
    case ARM::VLD1DUPq32wb_register:
9354
0
    case ARM::VLD2DUPd8wb_register:
9355
0
    case ARM::VLD2DUPd8x2wb_register:
9356
0
    case ARM::VLD2DUPd16wb_register:
9357
0
    case ARM::VLD2DUPd16x2wb_register:
9358
0
    case ARM::VLD2DUPd32wb_register:
9359
0
    case ARM::VLD2DUPd32x2wb_register: {
9360
      // op: Vd
9361
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9362
0
      Value |= (op & UINT64_C(16)) << 18;
9363
0
      Value |= (op & UINT64_C(15)) << 12;
9364
      // op: Rn
9365
0
      op = getAddrMode6DupAddressOpValue(MI, 2, Fixups, STI);
9366
0
      Value |= (op & UINT64_C(15)) << 16;
9367
0
      Value |= (op & UINT64_C(16));
9368
      // op: Rm
9369
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
9370
0
      op &= UINT64_C(15);
9371
0
      Value |= op;
9372
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9373
0
      break;
9374
0
    }
9375
0
    case ARM::VLD1DUPd8wb_fixed:
9376
0
    case ARM::VLD1DUPd16wb_fixed:
9377
0
    case ARM::VLD1DUPd32wb_fixed:
9378
0
    case ARM::VLD1DUPq8wb_fixed:
9379
0
    case ARM::VLD1DUPq16wb_fixed:
9380
0
    case ARM::VLD1DUPq32wb_fixed:
9381
0
    case ARM::VLD2DUPd8wb_fixed:
9382
0
    case ARM::VLD2DUPd8x2wb_fixed:
9383
0
    case ARM::VLD2DUPd16wb_fixed:
9384
0
    case ARM::VLD2DUPd16x2wb_fixed:
9385
0
    case ARM::VLD2DUPd32wb_fixed:
9386
0
    case ARM::VLD2DUPd32x2wb_fixed: {
9387
      // op: Vd
9388
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9389
0
      Value |= (op & UINT64_C(16)) << 18;
9390
0
      Value |= (op & UINT64_C(15)) << 12;
9391
      // op: Rn
9392
0
      op = getAddrMode6DupAddressOpValue(MI, 2, Fixups, STI);
9393
0
      Value |= (op & UINT64_C(15)) << 16;
9394
0
      Value |= (op & UINT64_C(16));
9395
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9396
0
      break;
9397
0
    }
9398
0
    case ARM::VLD3DUPd8:
9399
0
    case ARM::VLD3DUPd16:
9400
0
    case ARM::VLD3DUPd32:
9401
0
    case ARM::VLD3DUPq8:
9402
0
    case ARM::VLD3DUPq16:
9403
0
    case ARM::VLD3DUPq32: {
9404
      // op: Vd
9405
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9406
0
      Value |= (op & UINT64_C(16)) << 18;
9407
0
      Value |= (op & UINT64_C(15)) << 12;
9408
      // op: Rn
9409
0
      op = getAddrMode6DupAddressOpValue(MI, 3, Fixups, STI);
9410
0
      op &= UINT64_C(15);
9411
0
      op <<= 16;
9412
0
      Value |= op;
9413
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9414
0
      break;
9415
0
    }
9416
0
    case ARM::VLD4DUPd8:
9417
0
    case ARM::VLD4DUPd16:
9418
0
    case ARM::VLD4DUPq8:
9419
0
    case ARM::VLD4DUPq16: {
9420
      // op: Vd
9421
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9422
0
      Value |= (op & UINT64_C(16)) << 18;
9423
0
      Value |= (op & UINT64_C(15)) << 12;
9424
      // op: Rn
9425
0
      op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI);
9426
0
      Value |= (op & UINT64_C(15)) << 16;
9427
0
      Value |= (op & UINT64_C(16));
9428
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9429
0
      break;
9430
0
    }
9431
0
    case ARM::VLD4DUPd32:
9432
0
    case ARM::VLD4DUPq32: {
9433
      // op: Vd
9434
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9435
0
      Value |= (op & UINT64_C(16)) << 18;
9436
0
      Value |= (op & UINT64_C(15)) << 12;
9437
      // op: Rn
9438
0
      op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI);
9439
0
      Value |= (op & UINT64_C(15)) << 16;
9440
0
      Value |= (op & UINT64_C(32)) << 1;
9441
0
      Value |= (op & UINT64_C(16));
9442
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9443
0
      break;
9444
0
    }
9445
0
    case ARM::VLD3DUPd8_UPD:
9446
0
    case ARM::VLD3DUPd16_UPD:
9447
0
    case ARM::VLD3DUPd32_UPD:
9448
0
    case ARM::VLD3DUPq8_UPD:
9449
0
    case ARM::VLD3DUPq16_UPD:
9450
0
    case ARM::VLD3DUPq32_UPD: {
9451
      // op: Vd
9452
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9453
0
      Value |= (op & UINT64_C(16)) << 18;
9454
0
      Value |= (op & UINT64_C(15)) << 12;
9455
      // op: Rn
9456
0
      op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI);
9457
0
      op &= UINT64_C(15);
9458
0
      op <<= 16;
9459
0
      Value |= op;
9460
      // op: Rm
9461
0
      op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI);
9462
0
      op &= UINT64_C(15);
9463
0
      Value |= op;
9464
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9465
0
      break;
9466
0
    }
9467
0
    case ARM::VLD4DUPd8_UPD:
9468
0
    case ARM::VLD4DUPd16_UPD:
9469
0
    case ARM::VLD4DUPq8_UPD:
9470
0
    case ARM::VLD4DUPq16_UPD: {
9471
      // op: Vd
9472
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9473
0
      Value |= (op & UINT64_C(16)) << 18;
9474
0
      Value |= (op & UINT64_C(15)) << 12;
9475
      // op: Rn
9476
0
      op = getAddrMode6DupAddressOpValue(MI, 5, Fixups, STI);
9477
0
      Value |= (op & UINT64_C(15)) << 16;
9478
0
      Value |= (op & UINT64_C(16));
9479
      // op: Rm
9480
0
      op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI);
9481
0
      op &= UINT64_C(15);
9482
0
      Value |= op;
9483
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9484
0
      break;
9485
0
    }
9486
0
    case ARM::VLD4DUPd32_UPD:
9487
0
    case ARM::VLD4DUPq32_UPD: {
9488
      // op: Vd
9489
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9490
0
      Value |= (op & UINT64_C(16)) << 18;
9491
0
      Value |= (op & UINT64_C(15)) << 12;
9492
      // op: Rn
9493
0
      op = getAddrMode6DupAddressOpValue(MI, 5, Fixups, STI);
9494
0
      Value |= (op & UINT64_C(15)) << 16;
9495
0
      Value |= (op & UINT64_C(32)) << 1;
9496
0
      Value |= (op & UINT64_C(16));
9497
      // op: Rm
9498
0
      op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI);
9499
0
      op &= UINT64_C(15);
9500
0
      Value |= op;
9501
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9502
0
      break;
9503
0
    }
9504
0
    case ARM::VLD1LNd32: {
9505
      // op: Vd
9506
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9507
0
      Value |= (op & UINT64_C(16)) << 18;
9508
0
      Value |= (op & UINT64_C(15)) << 12;
9509
      // op: Rn
9510
0
      op = getAddrMode6OneLane32AddressOpValue(MI, 1, Fixups, STI);
9511
0
      Value |= (op & UINT64_C(15)) << 16;
9512
0
      Value |= (op & UINT64_C(48));
9513
      // op: lane
9514
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
9515
0
      op &= UINT64_C(1);
9516
0
      op <<= 7;
9517
0
      Value |= op;
9518
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9519
0
      break;
9520
0
    }
9521
0
    case ARM::VMOVv1i64:
9522
0
    case ARM::VMOVv2f32:
9523
0
    case ARM::VMOVv2i64:
9524
0
    case ARM::VMOVv4f32:
9525
0
    case ARM::VMOVv8i8:
9526
0
    case ARM::VMOVv16i8: {
9527
      // op: Vd
9528
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9529
0
      Value |= (op & UINT64_C(16)) << 18;
9530
0
      Value |= (op & UINT64_C(15)) << 12;
9531
      // op: SIMM
9532
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9533
0
      Value |= (op & UINT64_C(128)) << 17;
9534
0
      Value |= (op & UINT64_C(112)) << 12;
9535
0
      Value |= (op & UINT64_C(15));
9536
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9537
0
      break;
9538
0
    }
9539
0
    case ARM::VBICiv2i32:
9540
0
    case ARM::VBICiv4i32:
9541
0
    case ARM::VORRiv2i32:
9542
0
    case ARM::VORRiv4i32: {
9543
      // op: Vd
9544
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9545
0
      Value |= (op & UINT64_C(16)) << 18;
9546
0
      Value |= (op & UINT64_C(15)) << 12;
9547
      // op: SIMM
9548
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9549
0
      Value |= (op & UINT64_C(128)) << 17;
9550
0
      Value |= (op & UINT64_C(112)) << 12;
9551
0
      Value |= (op & UINT64_C(1536));
9552
0
      Value |= (op & UINT64_C(15));
9553
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9554
0
      break;
9555
0
    }
9556
0
    case ARM::VMOVv2i32:
9557
0
    case ARM::VMOVv4i32:
9558
0
    case ARM::VMVNv2i32:
9559
0
    case ARM::VMVNv4i32: {
9560
      // op: Vd
9561
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9562
0
      Value |= (op & UINT64_C(16)) << 18;
9563
0
      Value |= (op & UINT64_C(15)) << 12;
9564
      // op: SIMM
9565
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9566
0
      Value |= (op & UINT64_C(128)) << 17;
9567
0
      Value |= (op & UINT64_C(112)) << 12;
9568
0
      Value |= (op & UINT64_C(3840));
9569
0
      Value |= (op & UINT64_C(15));
9570
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9571
0
      break;
9572
0
    }
9573
0
    case ARM::VBICiv4i16:
9574
0
    case ARM::VBICiv8i16:
9575
0
    case ARM::VMOVv4i16:
9576
0
    case ARM::VMOVv8i16:
9577
0
    case ARM::VMVNv4i16:
9578
0
    case ARM::VMVNv8i16:
9579
0
    case ARM::VORRiv4i16:
9580
0
    case ARM::VORRiv8i16: {
9581
      // op: Vd
9582
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9583
0
      Value |= (op & UINT64_C(16)) << 18;
9584
0
      Value |= (op & UINT64_C(15)) << 12;
9585
      // op: SIMM
9586
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9587
0
      Value |= (op & UINT64_C(128)) << 17;
9588
0
      Value |= (op & UINT64_C(112)) << 12;
9589
0
      Value |= (op & UINT64_C(512));
9590
0
      Value |= (op & UINT64_C(15));
9591
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9592
0
      break;
9593
0
    }
9594
0
    case ARM::VQSHLsiv4i16:
9595
0
    case ARM::VQSHLsiv8i16:
9596
0
    case ARM::VQSHLsuv4i16:
9597
0
    case ARM::VQSHLsuv8i16:
9598
0
    case ARM::VQSHLuiv4i16:
9599
0
    case ARM::VQSHLuiv8i16:
9600
0
    case ARM::VSHLLsv4i32:
9601
0
    case ARM::VSHLLuv4i32:
9602
0
    case ARM::VSHLiv4i16:
9603
0
    case ARM::VSHLiv8i16: {
9604
      // op: Vd
9605
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9606
0
      Value |= (op & UINT64_C(16)) << 18;
9607
0
      Value |= (op & UINT64_C(15)) << 12;
9608
      // op: Vm
9609
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9610
0
      Value |= (op & UINT64_C(16)) << 1;
9611
0
      Value |= (op & UINT64_C(15));
9612
      // op: SIMM
9613
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9614
0
      op &= UINT64_C(15);
9615
0
      op <<= 16;
9616
0
      Value |= op;
9617
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9618
0
      break;
9619
0
    }
9620
0
    case ARM::VQSHLsiv2i32:
9621
0
    case ARM::VQSHLsiv4i32:
9622
0
    case ARM::VQSHLsuv2i32:
9623
0
    case ARM::VQSHLsuv4i32:
9624
0
    case ARM::VQSHLuiv2i32:
9625
0
    case ARM::VQSHLuiv4i32:
9626
0
    case ARM::VSHLLsv2i64:
9627
0
    case ARM::VSHLLuv2i64:
9628
0
    case ARM::VSHLiv2i32:
9629
0
    case ARM::VSHLiv4i32: {
9630
      // op: Vd
9631
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9632
0
      Value |= (op & UINT64_C(16)) << 18;
9633
0
      Value |= (op & UINT64_C(15)) << 12;
9634
      // op: Vm
9635
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9636
0
      Value |= (op & UINT64_C(16)) << 1;
9637
0
      Value |= (op & UINT64_C(15));
9638
      // op: SIMM
9639
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9640
0
      op &= UINT64_C(31);
9641
0
      op <<= 16;
9642
0
      Value |= op;
9643
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9644
0
      break;
9645
0
    }
9646
0
    case ARM::VQSHLsiv1i64:
9647
0
    case ARM::VQSHLsiv2i64:
9648
0
    case ARM::VQSHLsuv1i64:
9649
0
    case ARM::VQSHLsuv2i64:
9650
0
    case ARM::VQSHLuiv1i64:
9651
0
    case ARM::VQSHLuiv2i64:
9652
0
    case ARM::VSHLiv1i64:
9653
0
    case ARM::VSHLiv2i64: {
9654
      // op: Vd
9655
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9656
0
      Value |= (op & UINT64_C(16)) << 18;
9657
0
      Value |= (op & UINT64_C(15)) << 12;
9658
      // op: Vm
9659
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9660
0
      Value |= (op & UINT64_C(16)) << 1;
9661
0
      Value |= (op & UINT64_C(15));
9662
      // op: SIMM
9663
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9664
0
      op &= UINT64_C(63);
9665
0
      op <<= 16;
9666
0
      Value |= op;
9667
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9668
0
      break;
9669
0
    }
9670
0
    case ARM::VQSHLsiv8i8:
9671
0
    case ARM::VQSHLsiv16i8:
9672
0
    case ARM::VQSHLsuv8i8:
9673
0
    case ARM::VQSHLsuv16i8:
9674
0
    case ARM::VQSHLuiv8i8:
9675
0
    case ARM::VQSHLuiv16i8:
9676
0
    case ARM::VSHLLsv8i16:
9677
0
    case ARM::VSHLLuv8i16:
9678
0
    case ARM::VSHLiv8i8:
9679
0
    case ARM::VSHLiv16i8: {
9680
      // op: Vd
9681
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9682
0
      Value |= (op & UINT64_C(16)) << 18;
9683
0
      Value |= (op & UINT64_C(15)) << 12;
9684
      // op: Vm
9685
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9686
0
      Value |= (op & UINT64_C(16)) << 1;
9687
0
      Value |= (op & UINT64_C(15));
9688
      // op: SIMM
9689
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9690
0
      op &= UINT64_C(7);
9691
0
      op <<= 16;
9692
0
      Value |= op;
9693
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9694
0
      break;
9695
0
    }
9696
0
    case ARM::VCVTf2xsd:
9697
0
    case ARM::VCVTf2xsq:
9698
0
    case ARM::VCVTf2xud:
9699
0
    case ARM::VCVTf2xuq:
9700
0
    case ARM::VCVTh2xsd:
9701
0
    case ARM::VCVTh2xsq:
9702
0
    case ARM::VCVTh2xud:
9703
0
    case ARM::VCVTh2xuq:
9704
0
    case ARM::VCVTxs2fd:
9705
0
    case ARM::VCVTxs2fq:
9706
0
    case ARM::VCVTxs2hd:
9707
0
    case ARM::VCVTxs2hq:
9708
0
    case ARM::VCVTxu2fd:
9709
0
    case ARM::VCVTxu2fq:
9710
0
    case ARM::VCVTxu2hd:
9711
0
    case ARM::VCVTxu2hq: {
9712
      // op: Vd
9713
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9714
0
      Value |= (op & UINT64_C(16)) << 18;
9715
0
      Value |= (op & UINT64_C(15)) << 12;
9716
      // op: Vm
9717
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9718
0
      Value |= (op & UINT64_C(16)) << 1;
9719
0
      Value |= (op & UINT64_C(15));
9720
      // op: SIMM
9721
0
      op = getNEONVcvtImm32OpValue(MI, 2, Fixups, STI);
9722
0
      op &= UINT64_C(63);
9723
0
      op <<= 16;
9724
0
      Value |= op;
9725
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9726
0
      break;
9727
0
    }
9728
0
    case ARM::VQRSHRNsv4i16:
9729
0
    case ARM::VQRSHRNuv4i16:
9730
0
    case ARM::VQRSHRUNv4i16:
9731
0
    case ARM::VQSHRNsv4i16:
9732
0
    case ARM::VQSHRNuv4i16:
9733
0
    case ARM::VQSHRUNv4i16:
9734
0
    case ARM::VRSHRNv4i16:
9735
0
    case ARM::VRSHRsv4i16:
9736
0
    case ARM::VRSHRsv8i16:
9737
0
    case ARM::VRSHRuv4i16:
9738
0
    case ARM::VRSHRuv8i16:
9739
0
    case ARM::VSHRNv4i16:
9740
0
    case ARM::VSHRsv4i16:
9741
0
    case ARM::VSHRsv8i16:
9742
0
    case ARM::VSHRuv4i16:
9743
0
    case ARM::VSHRuv8i16: {
9744
      // op: Vd
9745
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9746
0
      Value |= (op & UINT64_C(16)) << 18;
9747
0
      Value |= (op & UINT64_C(15)) << 12;
9748
      // op: Vm
9749
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9750
0
      Value |= (op & UINT64_C(16)) << 1;
9751
0
      Value |= (op & UINT64_C(15));
9752
      // op: SIMM
9753
0
      op = getShiftRight16Imm(MI, 2, Fixups, STI);
9754
0
      op &= UINT64_C(15);
9755
0
      op <<= 16;
9756
0
      Value |= op;
9757
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9758
0
      break;
9759
0
    }
9760
0
    case ARM::VQRSHRNsv2i32:
9761
0
    case ARM::VQRSHRNuv2i32:
9762
0
    case ARM::VQRSHRUNv2i32:
9763
0
    case ARM::VQSHRNsv2i32:
9764
0
    case ARM::VQSHRNuv2i32:
9765
0
    case ARM::VQSHRUNv2i32:
9766
0
    case ARM::VRSHRNv2i32:
9767
0
    case ARM::VRSHRsv2i32:
9768
0
    case ARM::VRSHRsv4i32:
9769
0
    case ARM::VRSHRuv2i32:
9770
0
    case ARM::VRSHRuv4i32:
9771
0
    case ARM::VSHRNv2i32:
9772
0
    case ARM::VSHRsv2i32:
9773
0
    case ARM::VSHRsv4i32:
9774
0
    case ARM::VSHRuv2i32:
9775
0
    case ARM::VSHRuv4i32: {
9776
      // op: Vd
9777
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9778
0
      Value |= (op & UINT64_C(16)) << 18;
9779
0
      Value |= (op & UINT64_C(15)) << 12;
9780
      // op: Vm
9781
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9782
0
      Value |= (op & UINT64_C(16)) << 1;
9783
0
      Value |= (op & UINT64_C(15));
9784
      // op: SIMM
9785
0
      op = getShiftRight32Imm(MI, 2, Fixups, STI);
9786
0
      op &= UINT64_C(31);
9787
0
      op <<= 16;
9788
0
      Value |= op;
9789
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9790
0
      break;
9791
0
    }
9792
0
    case ARM::VRSHRsv1i64:
9793
0
    case ARM::VRSHRsv2i64:
9794
0
    case ARM::VRSHRuv1i64:
9795
0
    case ARM::VRSHRuv2i64:
9796
0
    case ARM::VSHRsv1i64:
9797
0
    case ARM::VSHRsv2i64:
9798
0
    case ARM::VSHRuv1i64:
9799
0
    case ARM::VSHRuv2i64: {
9800
      // op: Vd
9801
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9802
0
      Value |= (op & UINT64_C(16)) << 18;
9803
0
      Value |= (op & UINT64_C(15)) << 12;
9804
      // op: Vm
9805
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9806
0
      Value |= (op & UINT64_C(16)) << 1;
9807
0
      Value |= (op & UINT64_C(15));
9808
      // op: SIMM
9809
0
      op = getShiftRight64Imm(MI, 2, Fixups, STI);
9810
0
      op &= UINT64_C(63);
9811
0
      op <<= 16;
9812
0
      Value |= op;
9813
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9814
0
      break;
9815
0
    }
9816
0
    case ARM::VQRSHRNsv8i8:
9817
0
    case ARM::VQRSHRNuv8i8:
9818
0
    case ARM::VQRSHRUNv8i8:
9819
0
    case ARM::VQSHRNsv8i8:
9820
0
    case ARM::VQSHRNuv8i8:
9821
0
    case ARM::VQSHRUNv8i8:
9822
0
    case ARM::VRSHRNv8i8:
9823
0
    case ARM::VRSHRsv8i8:
9824
0
    case ARM::VRSHRsv16i8:
9825
0
    case ARM::VRSHRuv8i8:
9826
0
    case ARM::VRSHRuv16i8:
9827
0
    case ARM::VSHRNv8i8:
9828
0
    case ARM::VSHRsv8i8:
9829
0
    case ARM::VSHRsv16i8:
9830
0
    case ARM::VSHRuv8i8:
9831
0
    case ARM::VSHRuv16i8: {
9832
      // op: Vd
9833
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9834
0
      Value |= (op & UINT64_C(16)) << 18;
9835
0
      Value |= (op & UINT64_C(15)) << 12;
9836
      // op: Vm
9837
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9838
0
      Value |= (op & UINT64_C(16)) << 1;
9839
0
      Value |= (op & UINT64_C(15));
9840
      // op: SIMM
9841
0
      op = getShiftRight8Imm(MI, 2, Fixups, STI);
9842
0
      op &= UINT64_C(7);
9843
0
      op <<= 16;
9844
0
      Value |= op;
9845
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9846
0
      break;
9847
0
    }
9848
0
    case ARM::VDUPLN32d:
9849
0
    case ARM::VDUPLN32q: {
9850
      // op: Vd
9851
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9852
0
      Value |= (op & UINT64_C(16)) << 18;
9853
0
      Value |= (op & UINT64_C(15)) << 12;
9854
      // op: Vm
9855
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9856
0
      Value |= (op & UINT64_C(16)) << 1;
9857
0
      Value |= (op & UINT64_C(15));
9858
      // op: lane
9859
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9860
0
      op &= UINT64_C(1);
9861
0
      op <<= 19;
9862
0
      Value |= op;
9863
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9864
0
      break;
9865
0
    }
9866
0
    case ARM::VDUPLN16d:
9867
0
    case ARM::VDUPLN16q: {
9868
      // op: Vd
9869
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9870
0
      Value |= (op & UINT64_C(16)) << 18;
9871
0
      Value |= (op & UINT64_C(15)) << 12;
9872
      // op: Vm
9873
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9874
0
      Value |= (op & UINT64_C(16)) << 1;
9875
0
      Value |= (op & UINT64_C(15));
9876
      // op: lane
9877
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9878
0
      op &= UINT64_C(3);
9879
0
      op <<= 18;
9880
0
      Value |= op;
9881
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9882
0
      break;
9883
0
    }
9884
0
    case ARM::VDUPLN8d:
9885
0
    case ARM::VDUPLN8q: {
9886
      // op: Vd
9887
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9888
0
      Value |= (op & UINT64_C(16)) << 18;
9889
0
      Value |= (op & UINT64_C(15)) << 12;
9890
      // op: Vm
9891
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9892
0
      Value |= (op & UINT64_C(16)) << 1;
9893
0
      Value |= (op & UINT64_C(15));
9894
      // op: lane
9895
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9896
0
      op &= UINT64_C(7);
9897
0
      op <<= 17;
9898
0
      Value |= op;
9899
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9900
0
      break;
9901
0
    }
9902
0
    case ARM::AESIMC:
9903
0
    case ARM::AESMC:
9904
0
    case ARM::BF16_VCVT:
9905
0
    case ARM::SHA1H:
9906
0
    case ARM::VABSfd:
9907
0
    case ARM::VABSfq:
9908
0
    case ARM::VABShd:
9909
0
    case ARM::VABShq:
9910
0
    case ARM::VABSv2i32:
9911
0
    case ARM::VABSv4i16:
9912
0
    case ARM::VABSv4i32:
9913
0
    case ARM::VABSv8i8:
9914
0
    case ARM::VABSv8i16:
9915
0
    case ARM::VABSv16i8:
9916
0
    case ARM::VCEQzv2f32:
9917
0
    case ARM::VCEQzv2i32:
9918
0
    case ARM::VCEQzv4f16:
9919
0
    case ARM::VCEQzv4f32:
9920
0
    case ARM::VCEQzv4i16:
9921
0
    case ARM::VCEQzv4i32:
9922
0
    case ARM::VCEQzv8f16:
9923
0
    case ARM::VCEQzv8i8:
9924
0
    case ARM::VCEQzv8i16:
9925
0
    case ARM::VCEQzv16i8:
9926
0
    case ARM::VCGEzv2f32:
9927
0
    case ARM::VCGEzv2i32:
9928
0
    case ARM::VCGEzv4f16:
9929
0
    case ARM::VCGEzv4f32:
9930
0
    case ARM::VCGEzv4i16:
9931
0
    case ARM::VCGEzv4i32:
9932
0
    case ARM::VCGEzv8f16:
9933
0
    case ARM::VCGEzv8i8:
9934
0
    case ARM::VCGEzv8i16:
9935
0
    case ARM::VCGEzv16i8:
9936
0
    case ARM::VCGTzv2f32:
9937
0
    case ARM::VCGTzv2i32:
9938
0
    case ARM::VCGTzv4f16:
9939
0
    case ARM::VCGTzv4f32:
9940
0
    case ARM::VCGTzv4i16:
9941
0
    case ARM::VCGTzv4i32:
9942
0
    case ARM::VCGTzv8f16:
9943
0
    case ARM::VCGTzv8i8:
9944
0
    case ARM::VCGTzv8i16:
9945
0
    case ARM::VCGTzv16i8:
9946
0
    case ARM::VCLEzv2f32:
9947
0
    case ARM::VCLEzv2i32:
9948
0
    case ARM::VCLEzv4f16:
9949
0
    case ARM::VCLEzv4f32:
9950
0
    case ARM::VCLEzv4i16:
9951
0
    case ARM::VCLEzv4i32:
9952
0
    case ARM::VCLEzv8f16:
9953
0
    case ARM::VCLEzv8i8:
9954
0
    case ARM::VCLEzv8i16:
9955
0
    case ARM::VCLEzv16i8:
9956
0
    case ARM::VCLSv2i32:
9957
0
    case ARM::VCLSv4i16:
9958
0
    case ARM::VCLSv4i32:
9959
0
    case ARM::VCLSv8i8:
9960
0
    case ARM::VCLSv8i16:
9961
0
    case ARM::VCLSv16i8:
9962
0
    case ARM::VCLTzv2f32:
9963
0
    case ARM::VCLTzv2i32:
9964
0
    case ARM::VCLTzv4f16:
9965
0
    case ARM::VCLTzv4f32:
9966
0
    case ARM::VCLTzv4i16:
9967
0
    case ARM::VCLTzv4i32:
9968
0
    case ARM::VCLTzv8f16:
9969
0
    case ARM::VCLTzv8i8:
9970
0
    case ARM::VCLTzv8i16:
9971
0
    case ARM::VCLTzv16i8:
9972
0
    case ARM::VCLZv2i32:
9973
0
    case ARM::VCLZv4i16:
9974
0
    case ARM::VCLZv4i32:
9975
0
    case ARM::VCLZv8i8:
9976
0
    case ARM::VCLZv8i16:
9977
0
    case ARM::VCLZv16i8:
9978
0
    case ARM::VCNTd:
9979
0
    case ARM::VCNTq:
9980
0
    case ARM::VCVTf2h:
9981
0
    case ARM::VCVTf2sd:
9982
0
    case ARM::VCVTf2sq:
9983
0
    case ARM::VCVTf2ud:
9984
0
    case ARM::VCVTf2uq:
9985
0
    case ARM::VCVTh2f:
9986
0
    case ARM::VCVTh2sd:
9987
0
    case ARM::VCVTh2sq:
9988
0
    case ARM::VCVTh2ud:
9989
0
    case ARM::VCVTh2uq:
9990
0
    case ARM::VCVTs2fd:
9991
0
    case ARM::VCVTs2fq:
9992
0
    case ARM::VCVTs2hd:
9993
0
    case ARM::VCVTs2hq:
9994
0
    case ARM::VCVTu2fd:
9995
0
    case ARM::VCVTu2fq:
9996
0
    case ARM::VCVTu2hd:
9997
0
    case ARM::VCVTu2hq:
9998
0
    case ARM::VMOVLsv2i64:
9999
0
    case ARM::VMOVLsv4i32:
10000
0
    case ARM::VMOVLsv8i16:
10001
0
    case ARM::VMOVLuv2i64:
10002
0
    case ARM::VMOVLuv4i32:
10003
0
    case ARM::VMOVLuv8i16:
10004
0
    case ARM::VMOVNv2i32:
10005
0
    case ARM::VMOVNv4i16:
10006
0
    case ARM::VMOVNv8i8:
10007
0
    case ARM::VMVNd:
10008
0
    case ARM::VMVNq:
10009
0
    case ARM::VNEGf32q:
10010
0
    case ARM::VNEGfd:
10011
0
    case ARM::VNEGhd:
10012
0
    case ARM::VNEGhq:
10013
0
    case ARM::VNEGs8d:
10014
0
    case ARM::VNEGs8q:
10015
0
    case ARM::VNEGs16d:
10016
0
    case ARM::VNEGs16q:
10017
0
    case ARM::VNEGs32d:
10018
0
    case ARM::VNEGs32q:
10019
0
    case ARM::VPADDLsv2i32:
10020
0
    case ARM::VPADDLsv4i16:
10021
0
    case ARM::VPADDLsv4i32:
10022
0
    case ARM::VPADDLsv8i8:
10023
0
    case ARM::VPADDLsv8i16:
10024
0
    case ARM::VPADDLsv16i8:
10025
0
    case ARM::VPADDLuv2i32:
10026
0
    case ARM::VPADDLuv4i16:
10027
0
    case ARM::VPADDLuv4i32:
10028
0
    case ARM::VPADDLuv8i8:
10029
0
    case ARM::VPADDLuv8i16:
10030
0
    case ARM::VPADDLuv16i8:
10031
0
    case ARM::VQABSv2i32:
10032
0
    case ARM::VQABSv4i16:
10033
0
    case ARM::VQABSv4i32:
10034
0
    case ARM::VQABSv8i8:
10035
0
    case ARM::VQABSv8i16:
10036
0
    case ARM::VQABSv16i8:
10037
0
    case ARM::VQMOVNsuv2i32:
10038
0
    case ARM::VQMOVNsuv4i16:
10039
0
    case ARM::VQMOVNsuv8i8:
10040
0
    case ARM::VQMOVNsv2i32:
10041
0
    case ARM::VQMOVNsv4i16:
10042
0
    case ARM::VQMOVNsv8i8:
10043
0
    case ARM::VQMOVNuv2i32:
10044
0
    case ARM::VQMOVNuv4i16:
10045
0
    case ARM::VQMOVNuv8i8:
10046
0
    case ARM::VQNEGv2i32:
10047
0
    case ARM::VQNEGv4i16:
10048
0
    case ARM::VQNEGv4i32:
10049
0
    case ARM::VQNEGv8i8:
10050
0
    case ARM::VQNEGv8i16:
10051
0
    case ARM::VQNEGv16i8:
10052
0
    case ARM::VRECPEd:
10053
0
    case ARM::VRECPEfd:
10054
0
    case ARM::VRECPEfq:
10055
0
    case ARM::VRECPEhd:
10056
0
    case ARM::VRECPEhq:
10057
0
    case ARM::VRECPEq:
10058
0
    case ARM::VREV16d8:
10059
0
    case ARM::VREV16q8:
10060
0
    case ARM::VREV32d8:
10061
0
    case ARM::VREV32d16:
10062
0
    case ARM::VREV32q8:
10063
0
    case ARM::VREV32q16:
10064
0
    case ARM::VREV64d8:
10065
0
    case ARM::VREV64d16:
10066
0
    case ARM::VREV64d32:
10067
0
    case ARM::VREV64q8:
10068
0
    case ARM::VREV64q16:
10069
0
    case ARM::VREV64q32:
10070
0
    case ARM::VRSQRTEd:
10071
0
    case ARM::VRSQRTEfd:
10072
0
    case ARM::VRSQRTEfq:
10073
0
    case ARM::VRSQRTEhd:
10074
0
    case ARM::VRSQRTEhq:
10075
0
    case ARM::VRSQRTEq:
10076
0
    case ARM::VSHLLi8:
10077
0
    case ARM::VSHLLi16:
10078
0
    case ARM::VSHLLi32:
10079
0
    case ARM::VSWPd:
10080
0
    case ARM::VSWPq:
10081
0
    case ARM::VTRNd8:
10082
0
    case ARM::VTRNd16:
10083
0
    case ARM::VTRNd32:
10084
0
    case ARM::VTRNq8:
10085
0
    case ARM::VTRNq16:
10086
0
    case ARM::VTRNq32:
10087
0
    case ARM::VUZPd8:
10088
0
    case ARM::VUZPd16:
10089
0
    case ARM::VUZPq8:
10090
0
    case ARM::VUZPq16:
10091
0
    case ARM::VUZPq32:
10092
0
    case ARM::VZIPd8:
10093
0
    case ARM::VZIPd16:
10094
0
    case ARM::VZIPq8:
10095
0
    case ARM::VZIPq16:
10096
0
    case ARM::VZIPq32: {
10097
      // op: Vd
10098
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10099
0
      Value |= (op & UINT64_C(16)) << 18;
10100
0
      Value |= (op & UINT64_C(15)) << 12;
10101
      // op: Vm
10102
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10103
0
      Value |= (op & UINT64_C(16)) << 1;
10104
0
      Value |= (op & UINT64_C(15));
10105
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10106
0
      break;
10107
0
    }
10108
0
    case ARM::VCVTANSDf:
10109
0
    case ARM::VCVTANSDh:
10110
0
    case ARM::VCVTANSQf:
10111
0
    case ARM::VCVTANSQh:
10112
0
    case ARM::VCVTANUDf:
10113
0
    case ARM::VCVTANUDh:
10114
0
    case ARM::VCVTANUQf:
10115
0
    case ARM::VCVTANUQh:
10116
0
    case ARM::VCVTMNSDf:
10117
0
    case ARM::VCVTMNSDh:
10118
0
    case ARM::VCVTMNSQf:
10119
0
    case ARM::VCVTMNSQh:
10120
0
    case ARM::VCVTMNUDf:
10121
0
    case ARM::VCVTMNUDh:
10122
0
    case ARM::VCVTMNUQf:
10123
0
    case ARM::VCVTMNUQh:
10124
0
    case ARM::VCVTNNSDf:
10125
0
    case ARM::VCVTNNSDh:
10126
0
    case ARM::VCVTNNSQf:
10127
0
    case ARM::VCVTNNSQh:
10128
0
    case ARM::VCVTNNUDf:
10129
0
    case ARM::VCVTNNUDh:
10130
0
    case ARM::VCVTNNUQf:
10131
0
    case ARM::VCVTNNUQh:
10132
0
    case ARM::VCVTPNSDf:
10133
0
    case ARM::VCVTPNSDh:
10134
0
    case ARM::VCVTPNSQf:
10135
0
    case ARM::VCVTPNSQh:
10136
0
    case ARM::VCVTPNUDf:
10137
0
    case ARM::VCVTPNUDh:
10138
0
    case ARM::VCVTPNUQf:
10139
0
    case ARM::VCVTPNUQh:
10140
0
    case ARM::VRINTANDf:
10141
0
    case ARM::VRINTANDh:
10142
0
    case ARM::VRINTANQf:
10143
0
    case ARM::VRINTANQh:
10144
0
    case ARM::VRINTMNDf:
10145
0
    case ARM::VRINTMNDh:
10146
0
    case ARM::VRINTMNQf:
10147
0
    case ARM::VRINTMNQh:
10148
0
    case ARM::VRINTNNDf:
10149
0
    case ARM::VRINTNNDh:
10150
0
    case ARM::VRINTNNQf:
10151
0
    case ARM::VRINTNNQh:
10152
0
    case ARM::VRINTPNDf:
10153
0
    case ARM::VRINTPNDh:
10154
0
    case ARM::VRINTPNQf:
10155
0
    case ARM::VRINTPNQh:
10156
0
    case ARM::VRINTXNDf:
10157
0
    case ARM::VRINTXNDh:
10158
0
    case ARM::VRINTXNQf:
10159
0
    case ARM::VRINTXNQh:
10160
0
    case ARM::VRINTZNDf:
10161
0
    case ARM::VRINTZNDh:
10162
0
    case ARM::VRINTZNQf:
10163
0
    case ARM::VRINTZNQh: {
10164
      // op: Vd
10165
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10166
0
      Value |= (op & UINT64_C(16)) << 18;
10167
0
      Value |= (op & UINT64_C(15)) << 12;
10168
      // op: Vm
10169
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10170
0
      Value |= (op & UINT64_C(16)) << 1;
10171
0
      Value |= (op & UINT64_C(15));
10172
0
      Value = NEONThumb2V8PostEncoder(MI, Value, STI);
10173
0
      break;
10174
0
    }
10175
0
    case ARM::VSLIv4i16:
10176
0
    case ARM::VSLIv8i16: {
10177
      // op: Vd
10178
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10179
0
      Value |= (op & UINT64_C(16)) << 18;
10180
0
      Value |= (op & UINT64_C(15)) << 12;
10181
      // op: Vm
10182
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10183
0
      Value |= (op & UINT64_C(16)) << 1;
10184
0
      Value |= (op & UINT64_C(15));
10185
      // op: SIMM
10186
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10187
0
      op &= UINT64_C(15);
10188
0
      op <<= 16;
10189
0
      Value |= op;
10190
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10191
0
      break;
10192
0
    }
10193
0
    case ARM::VSLIv2i32:
10194
0
    case ARM::VSLIv4i32: {
10195
      // op: Vd
10196
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10197
0
      Value |= (op & UINT64_C(16)) << 18;
10198
0
      Value |= (op & UINT64_C(15)) << 12;
10199
      // op: Vm
10200
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10201
0
      Value |= (op & UINT64_C(16)) << 1;
10202
0
      Value |= (op & UINT64_C(15));
10203
      // op: SIMM
10204
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10205
0
      op &= UINT64_C(31);
10206
0
      op <<= 16;
10207
0
      Value |= op;
10208
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10209
0
      break;
10210
0
    }
10211
0
    case ARM::VSLIv1i64:
10212
0
    case ARM::VSLIv2i64: {
10213
      // op: Vd
10214
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10215
0
      Value |= (op & UINT64_C(16)) << 18;
10216
0
      Value |= (op & UINT64_C(15)) << 12;
10217
      // op: Vm
10218
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10219
0
      Value |= (op & UINT64_C(16)) << 1;
10220
0
      Value |= (op & UINT64_C(15));
10221
      // op: SIMM
10222
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10223
0
      op &= UINT64_C(63);
10224
0
      op <<= 16;
10225
0
      Value |= op;
10226
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10227
0
      break;
10228
0
    }
10229
0
    case ARM::VSLIv8i8:
10230
0
    case ARM::VSLIv16i8: {
10231
      // op: Vd
10232
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10233
0
      Value |= (op & UINT64_C(16)) << 18;
10234
0
      Value |= (op & UINT64_C(15)) << 12;
10235
      // op: Vm
10236
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10237
0
      Value |= (op & UINT64_C(16)) << 1;
10238
0
      Value |= (op & UINT64_C(15));
10239
      // op: SIMM
10240
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10241
0
      op &= UINT64_C(7);
10242
0
      op <<= 16;
10243
0
      Value |= op;
10244
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10245
0
      break;
10246
0
    }
10247
0
    case ARM::VRSRAsv4i16:
10248
0
    case ARM::VRSRAsv8i16:
10249
0
    case ARM::VRSRAuv4i16:
10250
0
    case ARM::VRSRAuv8i16:
10251
0
    case ARM::VSRAsv4i16:
10252
0
    case ARM::VSRAsv8i16:
10253
0
    case ARM::VSRAuv4i16:
10254
0
    case ARM::VSRAuv8i16:
10255
0
    case ARM::VSRIv4i16:
10256
0
    case ARM::VSRIv8i16: {
10257
      // op: Vd
10258
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10259
0
      Value |= (op & UINT64_C(16)) << 18;
10260
0
      Value |= (op & UINT64_C(15)) << 12;
10261
      // op: Vm
10262
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10263
0
      Value |= (op & UINT64_C(16)) << 1;
10264
0
      Value |= (op & UINT64_C(15));
10265
      // op: SIMM
10266
0
      op = getShiftRight16Imm(MI, 3, Fixups, STI);
10267
0
      op &= UINT64_C(15);
10268
0
      op <<= 16;
10269
0
      Value |= op;
10270
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10271
0
      break;
10272
0
    }
10273
0
    case ARM::VRSRAsv2i32:
10274
0
    case ARM::VRSRAsv4i32:
10275
0
    case ARM::VRSRAuv2i32:
10276
0
    case ARM::VRSRAuv4i32:
10277
0
    case ARM::VSRAsv2i32:
10278
0
    case ARM::VSRAsv4i32:
10279
0
    case ARM::VSRAuv2i32:
10280
0
    case ARM::VSRAuv4i32:
10281
0
    case ARM::VSRIv2i32:
10282
0
    case ARM::VSRIv4i32: {
10283
      // op: Vd
10284
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10285
0
      Value |= (op & UINT64_C(16)) << 18;
10286
0
      Value |= (op & UINT64_C(15)) << 12;
10287
      // op: Vm
10288
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10289
0
      Value |= (op & UINT64_C(16)) << 1;
10290
0
      Value |= (op & UINT64_C(15));
10291
      // op: SIMM
10292
0
      op = getShiftRight32Imm(MI, 3, Fixups, STI);
10293
0
      op &= UINT64_C(31);
10294
0
      op <<= 16;
10295
0
      Value |= op;
10296
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10297
0
      break;
10298
0
    }
10299
0
    case ARM::VRSRAsv1i64:
10300
0
    case ARM::VRSRAsv2i64:
10301
0
    case ARM::VRSRAuv1i64:
10302
0
    case ARM::VRSRAuv2i64:
10303
0
    case ARM::VSRAsv1i64:
10304
0
    case ARM::VSRAsv2i64:
10305
0
    case ARM::VSRAuv1i64:
10306
0
    case ARM::VSRAuv2i64:
10307
0
    case ARM::VSRIv1i64:
10308
0
    case ARM::VSRIv2i64: {
10309
      // op: Vd
10310
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10311
0
      Value |= (op & UINT64_C(16)) << 18;
10312
0
      Value |= (op & UINT64_C(15)) << 12;
10313
      // op: Vm
10314
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10315
0
      Value |= (op & UINT64_C(16)) << 1;
10316
0
      Value |= (op & UINT64_C(15));
10317
      // op: SIMM
10318
0
      op = getShiftRight64Imm(MI, 3, Fixups, STI);
10319
0
      op &= UINT64_C(63);
10320
0
      op <<= 16;
10321
0
      Value |= op;
10322
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10323
0
      break;
10324
0
    }
10325
0
    case ARM::VRSRAsv8i8:
10326
0
    case ARM::VRSRAsv16i8:
10327
0
    case ARM::VRSRAuv8i8:
10328
0
    case ARM::VRSRAuv16i8:
10329
0
    case ARM::VSRAsv8i8:
10330
0
    case ARM::VSRAsv16i8:
10331
0
    case ARM::VSRAuv8i8:
10332
0
    case ARM::VSRAuv16i8:
10333
0
    case ARM::VSRIv8i8:
10334
0
    case ARM::VSRIv16i8: {
10335
      // op: Vd
10336
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10337
0
      Value |= (op & UINT64_C(16)) << 18;
10338
0
      Value |= (op & UINT64_C(15)) << 12;
10339
      // op: Vm
10340
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10341
0
      Value |= (op & UINT64_C(16)) << 1;
10342
0
      Value |= (op & UINT64_C(15));
10343
      // op: SIMM
10344
0
      op = getShiftRight8Imm(MI, 3, Fixups, STI);
10345
0
      op &= UINT64_C(7);
10346
0
      op <<= 16;
10347
0
      Value |= op;
10348
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10349
0
      break;
10350
0
    }
10351
0
    case ARM::AESD:
10352
0
    case ARM::AESE:
10353
0
    case ARM::SHA1SU1:
10354
0
    case ARM::SHA256SU0:
10355
0
    case ARM::VPADALsv2i32:
10356
0
    case ARM::VPADALsv4i16:
10357
0
    case ARM::VPADALsv4i32:
10358
0
    case ARM::VPADALsv8i8:
10359
0
    case ARM::VPADALsv8i16:
10360
0
    case ARM::VPADALsv16i8:
10361
0
    case ARM::VPADALuv2i32:
10362
0
    case ARM::VPADALuv4i16:
10363
0
    case ARM::VPADALuv4i32:
10364
0
    case ARM::VPADALuv8i8:
10365
0
    case ARM::VPADALuv8i16:
10366
0
    case ARM::VPADALuv16i8: {
10367
      // op: Vd
10368
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10369
0
      Value |= (op & UINT64_C(16)) << 18;
10370
0
      Value |= (op & UINT64_C(15)) << 12;
10371
      // op: Vm
10372
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10373
0
      Value |= (op & UINT64_C(16)) << 1;
10374
0
      Value |= (op & UINT64_C(15));
10375
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10376
0
      break;
10377
0
    }
10378
0
    case ARM::VFMALQ:
10379
0
    case ARM::VFMSLQ: {
10380
      // op: Vd
10381
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10382
0
      Value |= (op & UINT64_C(16)) << 18;
10383
0
      Value |= (op & UINT64_C(15)) << 12;
10384
      // op: Vn
10385
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10386
0
      Value |= (op & UINT64_C(15)) << 16;
10387
0
      Value |= (op & UINT64_C(16)) << 3;
10388
      // op: Vm
10389
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10390
0
      Value |= (op & UINT64_C(16)) << 1;
10391
0
      Value |= (op & UINT64_C(15));
10392
0
      break;
10393
0
    }
10394
0
    case ARM::VEXTd32: {
10395
      // op: Vd
10396
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10397
0
      Value |= (op & UINT64_C(16)) << 18;
10398
0
      Value |= (op & UINT64_C(15)) << 12;
10399
      // op: Vn
10400
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10401
0
      Value |= (op & UINT64_C(15)) << 16;
10402
0
      Value |= (op & UINT64_C(16)) << 3;
10403
      // op: Vm
10404
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10405
0
      Value |= (op & UINT64_C(16)) << 1;
10406
0
      Value |= (op & UINT64_C(15));
10407
      // op: index
10408
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10409
0
      op &= UINT64_C(1);
10410
0
      op <<= 10;
10411
0
      Value |= op;
10412
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10413
0
      break;
10414
0
    }
10415
0
    case ARM::VEXTq64: {
10416
      // op: Vd
10417
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10418
0
      Value |= (op & UINT64_C(16)) << 18;
10419
0
      Value |= (op & UINT64_C(15)) << 12;
10420
      // op: Vn
10421
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10422
0
      Value |= (op & UINT64_C(15)) << 16;
10423
0
      Value |= (op & UINT64_C(16)) << 3;
10424
      // op: Vm
10425
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10426
0
      Value |= (op & UINT64_C(16)) << 1;
10427
0
      Value |= (op & UINT64_C(15));
10428
      // op: index
10429
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10430
0
      op &= UINT64_C(1);
10431
0
      op <<= 11;
10432
0
      Value |= op;
10433
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10434
0
      break;
10435
0
    }
10436
0
    case ARM::VEXTq8: {
10437
      // op: Vd
10438
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10439
0
      Value |= (op & UINT64_C(16)) << 18;
10440
0
      Value |= (op & UINT64_C(15)) << 12;
10441
      // op: Vn
10442
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10443
0
      Value |= (op & UINT64_C(15)) << 16;
10444
0
      Value |= (op & UINT64_C(16)) << 3;
10445
      // op: Vm
10446
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10447
0
      Value |= (op & UINT64_C(16)) << 1;
10448
0
      Value |= (op & UINT64_C(15));
10449
      // op: index
10450
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10451
0
      op &= UINT64_C(15);
10452
0
      op <<= 8;
10453
0
      Value |= op;
10454
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10455
0
      break;
10456
0
    }
10457
0
    case ARM::VEXTq32: {
10458
      // op: Vd
10459
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10460
0
      Value |= (op & UINT64_C(16)) << 18;
10461
0
      Value |= (op & UINT64_C(15)) << 12;
10462
      // op: Vn
10463
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10464
0
      Value |= (op & UINT64_C(15)) << 16;
10465
0
      Value |= (op & UINT64_C(16)) << 3;
10466
      // op: Vm
10467
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10468
0
      Value |= (op & UINT64_C(16)) << 1;
10469
0
      Value |= (op & UINT64_C(15));
10470
      // op: index
10471
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10472
0
      op &= UINT64_C(3);
10473
0
      op <<= 10;
10474
0
      Value |= op;
10475
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10476
0
      break;
10477
0
    }
10478
0
    case ARM::VEXTd16: {
10479
      // op: Vd
10480
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10481
0
      Value |= (op & UINT64_C(16)) << 18;
10482
0
      Value |= (op & UINT64_C(15)) << 12;
10483
      // op: Vn
10484
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10485
0
      Value |= (op & UINT64_C(15)) << 16;
10486
0
      Value |= (op & UINT64_C(16)) << 3;
10487
      // op: Vm
10488
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10489
0
      Value |= (op & UINT64_C(16)) << 1;
10490
0
      Value |= (op & UINT64_C(15));
10491
      // op: index
10492
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10493
0
      op &= UINT64_C(3);
10494
0
      op <<= 9;
10495
0
      Value |= op;
10496
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10497
0
      break;
10498
0
    }
10499
0
    case ARM::VEXTd8: {
10500
      // op: Vd
10501
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10502
0
      Value |= (op & UINT64_C(16)) << 18;
10503
0
      Value |= (op & UINT64_C(15)) << 12;
10504
      // op: Vn
10505
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10506
0
      Value |= (op & UINT64_C(15)) << 16;
10507
0
      Value |= (op & UINT64_C(16)) << 3;
10508
      // op: Vm
10509
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10510
0
      Value |= (op & UINT64_C(16)) << 1;
10511
0
      Value |= (op & UINT64_C(15));
10512
      // op: index
10513
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10514
0
      op &= UINT64_C(7);
10515
0
      op <<= 8;
10516
0
      Value |= op;
10517
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10518
0
      break;
10519
0
    }
10520
0
    case ARM::VEXTq16: {
10521
      // op: Vd
10522
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10523
0
      Value |= (op & UINT64_C(16)) << 18;
10524
0
      Value |= (op & UINT64_C(15)) << 12;
10525
      // op: Vn
10526
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10527
0
      Value |= (op & UINT64_C(15)) << 16;
10528
0
      Value |= (op & UINT64_C(16)) << 3;
10529
      // op: Vm
10530
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10531
0
      Value |= (op & UINT64_C(16)) << 1;
10532
0
      Value |= (op & UINT64_C(15));
10533
      // op: index
10534
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10535
0
      op &= UINT64_C(7);
10536
0
      op <<= 9;
10537
0
      Value |= op;
10538
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10539
0
      break;
10540
0
    }
10541
0
    case ARM::VCADDv2f32:
10542
0
    case ARM::VCADDv4f16:
10543
0
    case ARM::VCADDv4f32:
10544
0
    case ARM::VCADDv8f16: {
10545
      // op: Vd
10546
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10547
0
      Value |= (op & UINT64_C(16)) << 18;
10548
0
      Value |= (op & UINT64_C(15)) << 12;
10549
      // op: Vn
10550
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10551
0
      Value |= (op & UINT64_C(15)) << 16;
10552
0
      Value |= (op & UINT64_C(16)) << 3;
10553
      // op: Vm
10554
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10555
0
      Value |= (op & UINT64_C(16)) << 1;
10556
0
      Value |= (op & UINT64_C(15));
10557
      // op: rot
10558
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10559
0
      op &= UINT64_C(1);
10560
0
      op <<= 24;
10561
0
      Value |= op;
10562
0
      break;
10563
0
    }
10564
0
    case ARM::VABDLsv2i64:
10565
0
    case ARM::VABDLsv4i32:
10566
0
    case ARM::VABDLsv8i16:
10567
0
    case ARM::VABDLuv2i64:
10568
0
    case ARM::VABDLuv4i32:
10569
0
    case ARM::VABDLuv8i16:
10570
0
    case ARM::VABDfd:
10571
0
    case ARM::VABDfq:
10572
0
    case ARM::VABDhd:
10573
0
    case ARM::VABDhq:
10574
0
    case ARM::VABDsv2i32:
10575
0
    case ARM::VABDsv4i16:
10576
0
    case ARM::VABDsv4i32:
10577
0
    case ARM::VABDsv8i8:
10578
0
    case ARM::VABDsv8i16:
10579
0
    case ARM::VABDsv16i8:
10580
0
    case ARM::VABDuv2i32:
10581
0
    case ARM::VABDuv4i16:
10582
0
    case ARM::VABDuv4i32:
10583
0
    case ARM::VABDuv8i8:
10584
0
    case ARM::VABDuv8i16:
10585
0
    case ARM::VABDuv16i8:
10586
0
    case ARM::VACGEfd:
10587
0
    case ARM::VACGEfq:
10588
0
    case ARM::VACGEhd:
10589
0
    case ARM::VACGEhq:
10590
0
    case ARM::VACGTfd:
10591
0
    case ARM::VACGTfq:
10592
0
    case ARM::VACGThd:
10593
0
    case ARM::VACGThq:
10594
0
    case ARM::VADDHNv2i32:
10595
0
    case ARM::VADDHNv4i16:
10596
0
    case ARM::VADDHNv8i8:
10597
0
    case ARM::VADDLsv2i64:
10598
0
    case ARM::VADDLsv4i32:
10599
0
    case ARM::VADDLsv8i16:
10600
0
    case ARM::VADDLuv2i64:
10601
0
    case ARM::VADDLuv4i32:
10602
0
    case ARM::VADDLuv8i16:
10603
0
    case ARM::VADDWsv2i64:
10604
0
    case ARM::VADDWsv4i32:
10605
0
    case ARM::VADDWsv8i16:
10606
0
    case ARM::VADDWuv2i64:
10607
0
    case ARM::VADDWuv4i32:
10608
0
    case ARM::VADDWuv8i16:
10609
0
    case ARM::VADDfd:
10610
0
    case ARM::VADDfq:
10611
0
    case ARM::VADDhd:
10612
0
    case ARM::VADDhq:
10613
0
    case ARM::VADDv1i64:
10614
0
    case ARM::VADDv2i32:
10615
0
    case ARM::VADDv2i64:
10616
0
    case ARM::VADDv4i16:
10617
0
    case ARM::VADDv4i32:
10618
0
    case ARM::VADDv8i8:
10619
0
    case ARM::VADDv8i16:
10620
0
    case ARM::VADDv16i8:
10621
0
    case ARM::VANDd:
10622
0
    case ARM::VANDq:
10623
0
    case ARM::VBICd:
10624
0
    case ARM::VBICq:
10625
0
    case ARM::VCEQfd:
10626
0
    case ARM::VCEQfq:
10627
0
    case ARM::VCEQhd:
10628
0
    case ARM::VCEQhq:
10629
0
    case ARM::VCEQv2i32:
10630
0
    case ARM::VCEQv4i16:
10631
0
    case ARM::VCEQv4i32:
10632
0
    case ARM::VCEQv8i8:
10633
0
    case ARM::VCEQv8i16:
10634
0
    case ARM::VCEQv16i8:
10635
0
    case ARM::VCGEfd:
10636
0
    case ARM::VCGEfq:
10637
0
    case ARM::VCGEhd:
10638
0
    case ARM::VCGEhq:
10639
0
    case ARM::VCGEsv2i32:
10640
0
    case ARM::VCGEsv4i16:
10641
0
    case ARM::VCGEsv4i32:
10642
0
    case ARM::VCGEsv8i8:
10643
0
    case ARM::VCGEsv8i16:
10644
0
    case ARM::VCGEsv16i8:
10645
0
    case ARM::VCGEuv2i32:
10646
0
    case ARM::VCGEuv4i16:
10647
0
    case ARM::VCGEuv4i32:
10648
0
    case ARM::VCGEuv8i8:
10649
0
    case ARM::VCGEuv8i16:
10650
0
    case ARM::VCGEuv16i8:
10651
0
    case ARM::VCGTfd:
10652
0
    case ARM::VCGTfq:
10653
0
    case ARM::VCGThd:
10654
0
    case ARM::VCGThq:
10655
0
    case ARM::VCGTsv2i32:
10656
0
    case ARM::VCGTsv4i16:
10657
0
    case ARM::VCGTsv4i32:
10658
0
    case ARM::VCGTsv8i8:
10659
0
    case ARM::VCGTsv8i16:
10660
0
    case ARM::VCGTsv16i8:
10661
0
    case ARM::VCGTuv2i32:
10662
0
    case ARM::VCGTuv4i16:
10663
0
    case ARM::VCGTuv4i32:
10664
0
    case ARM::VCGTuv8i8:
10665
0
    case ARM::VCGTuv8i16:
10666
0
    case ARM::VCGTuv16i8:
10667
0
    case ARM::VEORd:
10668
0
    case ARM::VEORq:
10669
0
    case ARM::VHADDsv2i32:
10670
0
    case ARM::VHADDsv4i16:
10671
0
    case ARM::VHADDsv4i32:
10672
0
    case ARM::VHADDsv8i8:
10673
0
    case ARM::VHADDsv8i16:
10674
0
    case ARM::VHADDsv16i8:
10675
0
    case ARM::VHADDuv2i32:
10676
0
    case ARM::VHADDuv4i16:
10677
0
    case ARM::VHADDuv4i32:
10678
0
    case ARM::VHADDuv8i8:
10679
0
    case ARM::VHADDuv8i16:
10680
0
    case ARM::VHADDuv16i8:
10681
0
    case ARM::VHSUBsv2i32:
10682
0
    case ARM::VHSUBsv4i16:
10683
0
    case ARM::VHSUBsv4i32:
10684
0
    case ARM::VHSUBsv8i8:
10685
0
    case ARM::VHSUBsv8i16:
10686
0
    case ARM::VHSUBsv16i8:
10687
0
    case ARM::VHSUBuv2i32:
10688
0
    case ARM::VHSUBuv4i16:
10689
0
    case ARM::VHSUBuv4i32:
10690
0
    case ARM::VHSUBuv8i8:
10691
0
    case ARM::VHSUBuv8i16:
10692
0
    case ARM::VHSUBuv16i8:
10693
0
    case ARM::VMAXfd:
10694
0
    case ARM::VMAXfq:
10695
0
    case ARM::VMAXhd:
10696
0
    case ARM::VMAXhq:
10697
0
    case ARM::VMAXsv2i32:
10698
0
    case ARM::VMAXsv4i16:
10699
0
    case ARM::VMAXsv4i32:
10700
0
    case ARM::VMAXsv8i8:
10701
0
    case ARM::VMAXsv8i16:
10702
0
    case ARM::VMAXsv16i8:
10703
0
    case ARM::VMAXuv2i32:
10704
0
    case ARM::VMAXuv4i16:
10705
0
    case ARM::VMAXuv4i32:
10706
0
    case ARM::VMAXuv8i8:
10707
0
    case ARM::VMAXuv8i16:
10708
0
    case ARM::VMAXuv16i8:
10709
0
    case ARM::VMINfd:
10710
0
    case ARM::VMINfq:
10711
0
    case ARM::VMINhd:
10712
0
    case ARM::VMINhq:
10713
0
    case ARM::VMINsv2i32:
10714
0
    case ARM::VMINsv4i16:
10715
0
    case ARM::VMINsv4i32:
10716
0
    case ARM::VMINsv8i8:
10717
0
    case ARM::VMINsv8i16:
10718
0
    case ARM::VMINsv16i8:
10719
0
    case ARM::VMINuv2i32:
10720
0
    case ARM::VMINuv4i16:
10721
0
    case ARM::VMINuv4i32:
10722
0
    case ARM::VMINuv8i8:
10723
0
    case ARM::VMINuv8i16:
10724
0
    case ARM::VMINuv16i8:
10725
0
    case ARM::VMULLp8:
10726
0
    case ARM::VMULLp64:
10727
0
    case ARM::VMULLsv2i64:
10728
0
    case ARM::VMULLsv4i32:
10729
0
    case ARM::VMULLsv8i16:
10730
0
    case ARM::VMULLuv2i64:
10731
0
    case ARM::VMULLuv4i32:
10732
0
    case ARM::VMULLuv8i16:
10733
0
    case ARM::VMULfd:
10734
0
    case ARM::VMULfq:
10735
0
    case ARM::VMULhd:
10736
0
    case ARM::VMULhq:
10737
0
    case ARM::VMULpd:
10738
0
    case ARM::VMULpq:
10739
0
    case ARM::VMULv2i32:
10740
0
    case ARM::VMULv4i16:
10741
0
    case ARM::VMULv4i32:
10742
0
    case ARM::VMULv8i8:
10743
0
    case ARM::VMULv8i16:
10744
0
    case ARM::VMULv16i8:
10745
0
    case ARM::VORNd:
10746
0
    case ARM::VORNq:
10747
0
    case ARM::VORRd:
10748
0
    case ARM::VORRq:
10749
0
    case ARM::VPADDf:
10750
0
    case ARM::VPADDh:
10751
0
    case ARM::VPADDi8:
10752
0
    case ARM::VPADDi16:
10753
0
    case ARM::VPADDi32:
10754
0
    case ARM::VPMAXf:
10755
0
    case ARM::VPMAXh:
10756
0
    case ARM::VPMAXs8:
10757
0
    case ARM::VPMAXs16:
10758
0
    case ARM::VPMAXs32:
10759
0
    case ARM::VPMAXu8:
10760
0
    case ARM::VPMAXu16:
10761
0
    case ARM::VPMAXu32:
10762
0
    case ARM::VPMINf:
10763
0
    case ARM::VPMINh:
10764
0
    case ARM::VPMINs8:
10765
0
    case ARM::VPMINs16:
10766
0
    case ARM::VPMINs32:
10767
0
    case ARM::VPMINu8:
10768
0
    case ARM::VPMINu16:
10769
0
    case ARM::VPMINu32:
10770
0
    case ARM::VQADDsv1i64:
10771
0
    case ARM::VQADDsv2i32:
10772
0
    case ARM::VQADDsv2i64:
10773
0
    case ARM::VQADDsv4i16:
10774
0
    case ARM::VQADDsv4i32:
10775
0
    case ARM::VQADDsv8i8:
10776
0
    case ARM::VQADDsv8i16:
10777
0
    case ARM::VQADDsv16i8:
10778
0
    case ARM::VQADDuv1i64:
10779
0
    case ARM::VQADDuv2i32:
10780
0
    case ARM::VQADDuv2i64:
10781
0
    case ARM::VQADDuv4i16:
10782
0
    case ARM::VQADDuv4i32:
10783
0
    case ARM::VQADDuv8i8:
10784
0
    case ARM::VQADDuv8i16:
10785
0
    case ARM::VQADDuv16i8:
10786
0
    case ARM::VQDMULHv2i32:
10787
0
    case ARM::VQDMULHv4i16:
10788
0
    case ARM::VQDMULHv4i32:
10789
0
    case ARM::VQDMULHv8i16:
10790
0
    case ARM::VQDMULLv2i64:
10791
0
    case ARM::VQDMULLv4i32:
10792
0
    case ARM::VQRDMULHv2i32:
10793
0
    case ARM::VQRDMULHv4i16:
10794
0
    case ARM::VQRDMULHv4i32:
10795
0
    case ARM::VQRDMULHv8i16:
10796
0
    case ARM::VQSUBsv1i64:
10797
0
    case ARM::VQSUBsv2i32:
10798
0
    case ARM::VQSUBsv2i64:
10799
0
    case ARM::VQSUBsv4i16:
10800
0
    case ARM::VQSUBsv4i32:
10801
0
    case ARM::VQSUBsv8i8:
10802
0
    case ARM::VQSUBsv8i16:
10803
0
    case ARM::VQSUBsv16i8:
10804
0
    case ARM::VQSUBuv1i64:
10805
0
    case ARM::VQSUBuv2i32:
10806
0
    case ARM::VQSUBuv2i64:
10807
0
    case ARM::VQSUBuv4i16:
10808
0
    case ARM::VQSUBuv4i32:
10809
0
    case ARM::VQSUBuv8i8:
10810
0
    case ARM::VQSUBuv8i16:
10811
0
    case ARM::VQSUBuv16i8:
10812
0
    case ARM::VRADDHNv2i32:
10813
0
    case ARM::VRADDHNv4i16:
10814
0
    case ARM::VRADDHNv8i8:
10815
0
    case ARM::VRECPSfd:
10816
0
    case ARM::VRECPSfq:
10817
0
    case ARM::VRECPShd:
10818
0
    case ARM::VRECPShq:
10819
0
    case ARM::VRHADDsv2i32:
10820
0
    case ARM::VRHADDsv4i16:
10821
0
    case ARM::VRHADDsv4i32:
10822
0
    case ARM::VRHADDsv8i8:
10823
0
    case ARM::VRHADDsv8i16:
10824
0
    case ARM::VRHADDsv16i8:
10825
0
    case ARM::VRHADDuv2i32:
10826
0
    case ARM::VRHADDuv4i16:
10827
0
    case ARM::VRHADDuv4i32:
10828
0
    case ARM::VRHADDuv8i8:
10829
0
    case ARM::VRHADDuv8i16:
10830
0
    case ARM::VRHADDuv16i8:
10831
0
    case ARM::VRSQRTSfd:
10832
0
    case ARM::VRSQRTSfq:
10833
0
    case ARM::VRSQRTShd:
10834
0
    case ARM::VRSQRTShq:
10835
0
    case ARM::VRSUBHNv2i32:
10836
0
    case ARM::VRSUBHNv4i16:
10837
0
    case ARM::VRSUBHNv8i8:
10838
0
    case ARM::VSUBHNv2i32:
10839
0
    case ARM::VSUBHNv4i16:
10840
0
    case ARM::VSUBHNv8i8:
10841
0
    case ARM::VSUBLsv2i64:
10842
0
    case ARM::VSUBLsv4i32:
10843
0
    case ARM::VSUBLsv8i16:
10844
0
    case ARM::VSUBLuv2i64:
10845
0
    case ARM::VSUBLuv4i32:
10846
0
    case ARM::VSUBLuv8i16:
10847
0
    case ARM::VSUBWsv2i64:
10848
0
    case ARM::VSUBWsv4i32:
10849
0
    case ARM::VSUBWsv8i16:
10850
0
    case ARM::VSUBWuv2i64:
10851
0
    case ARM::VSUBWuv4i32:
10852
0
    case ARM::VSUBWuv8i16:
10853
0
    case ARM::VSUBfd:
10854
0
    case ARM::VSUBfq:
10855
0
    case ARM::VSUBhd:
10856
0
    case ARM::VSUBhq:
10857
0
    case ARM::VSUBv1i64:
10858
0
    case ARM::VSUBv2i32:
10859
0
    case ARM::VSUBv2i64:
10860
0
    case ARM::VSUBv4i16:
10861
0
    case ARM::VSUBv4i32:
10862
0
    case ARM::VSUBv8i8:
10863
0
    case ARM::VSUBv8i16:
10864
0
    case ARM::VSUBv16i8:
10865
0
    case ARM::VTBL1:
10866
0
    case ARM::VTBL2:
10867
0
    case ARM::VTBL3:
10868
0
    case ARM::VTBL4:
10869
0
    case ARM::VTSTv2i32:
10870
0
    case ARM::VTSTv4i16:
10871
0
    case ARM::VTSTv4i32:
10872
0
    case ARM::VTSTv8i8:
10873
0
    case ARM::VTSTv8i16:
10874
0
    case ARM::VTSTv16i8: {
10875
      // op: Vd
10876
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10877
0
      Value |= (op & UINT64_C(16)) << 18;
10878
0
      Value |= (op & UINT64_C(15)) << 12;
10879
      // op: Vn
10880
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10881
0
      Value |= (op & UINT64_C(15)) << 16;
10882
0
      Value |= (op & UINT64_C(16)) << 3;
10883
      // op: Vm
10884
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10885
0
      Value |= (op & UINT64_C(16)) << 1;
10886
0
      Value |= (op & UINT64_C(15));
10887
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10888
0
      break;
10889
0
    }
10890
0
    case ARM::NEON_VMAXNMNDf:
10891
0
    case ARM::NEON_VMAXNMNDh:
10892
0
    case ARM::NEON_VMAXNMNQf:
10893
0
    case ARM::NEON_VMAXNMNQh:
10894
0
    case ARM::NEON_VMINNMNDf:
10895
0
    case ARM::NEON_VMINNMNDh:
10896
0
    case ARM::NEON_VMINNMNQf:
10897
0
    case ARM::NEON_VMINNMNQh: {
10898
      // op: Vd
10899
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10900
0
      Value |= (op & UINT64_C(16)) << 18;
10901
0
      Value |= (op & UINT64_C(15)) << 12;
10902
      // op: Vn
10903
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10904
0
      Value |= (op & UINT64_C(15)) << 16;
10905
0
      Value |= (op & UINT64_C(16)) << 3;
10906
      // op: Vm
10907
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10908
0
      Value |= (op & UINT64_C(16)) << 1;
10909
0
      Value |= (op & UINT64_C(15));
10910
0
      Value = NEONThumb2V8PostEncoder(MI, Value, STI);
10911
0
      break;
10912
0
    }
10913
0
    case ARM::VMULLslsv2i32:
10914
0
    case ARM::VMULLsluv2i32:
10915
0
    case ARM::VMULslfd:
10916
0
    case ARM::VMULslfq:
10917
0
    case ARM::VMULslv2i32:
10918
0
    case ARM::VMULslv4i32:
10919
0
    case ARM::VQDMULHslv2i32:
10920
0
    case ARM::VQDMULHslv4i32:
10921
0
    case ARM::VQDMULLslv2i32:
10922
0
    case ARM::VQRDMULHslv2i32:
10923
0
    case ARM::VQRDMULHslv4i32: {
10924
      // op: Vd
10925
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10926
0
      Value |= (op & UINT64_C(16)) << 18;
10927
0
      Value |= (op & UINT64_C(15)) << 12;
10928
      // op: Vn
10929
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10930
0
      Value |= (op & UINT64_C(15)) << 16;
10931
0
      Value |= (op & UINT64_C(16)) << 3;
10932
      // op: Vm
10933
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10934
0
      op &= UINT64_C(15);
10935
0
      Value |= op;
10936
      // op: lane
10937
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10938
0
      op &= UINT64_C(1);
10939
0
      op <<= 5;
10940
0
      Value |= op;
10941
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10942
0
      break;
10943
0
    }
10944
0
    case ARM::VFMALQI:
10945
0
    case ARM::VFMSLQI: {
10946
      // op: Vd
10947
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10948
0
      Value |= (op & UINT64_C(16)) << 18;
10949
0
      Value |= (op & UINT64_C(15)) << 12;
10950
      // op: Vn
10951
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10952
0
      Value |= (op & UINT64_C(15)) << 16;
10953
0
      Value |= (op & UINT64_C(16)) << 3;
10954
      // op: Vm
10955
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10956
0
      op &= UINT64_C(7);
10957
0
      Value |= op;
10958
      // op: idx
10959
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10960
0
      Value |= (op & UINT64_C(2)) << 4;
10961
0
      Value |= (op & UINT64_C(1)) << 3;
10962
0
      break;
10963
0
    }
10964
0
    case ARM::VMULLslsv4i16:
10965
0
    case ARM::VMULLsluv4i16:
10966
0
    case ARM::VMULslhd:
10967
0
    case ARM::VMULslhq:
10968
0
    case ARM::VMULslv4i16:
10969
0
    case ARM::VMULslv8i16:
10970
0
    case ARM::VQDMULHslv4i16:
10971
0
    case ARM::VQDMULHslv8i16:
10972
0
    case ARM::VQDMULLslv4i16:
10973
0
    case ARM::VQRDMULHslv4i16:
10974
0
    case ARM::VQRDMULHslv8i16: {
10975
      // op: Vd
10976
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10977
0
      Value |= (op & UINT64_C(16)) << 18;
10978
0
      Value |= (op & UINT64_C(15)) << 12;
10979
      // op: Vn
10980
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10981
0
      Value |= (op & UINT64_C(15)) << 16;
10982
0
      Value |= (op & UINT64_C(16)) << 3;
10983
      // op: Vm
10984
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10985
0
      op &= UINT64_C(7);
10986
0
      Value |= op;
10987
      // op: lane
10988
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10989
0
      Value |= (op & UINT64_C(2)) << 4;
10990
0
      Value |= (op & UINT64_C(1)) << 3;
10991
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10992
0
      break;
10993
0
    }
10994
0
    case ARM::VFMALDI:
10995
0
    case ARM::VFMSLDI: {
10996
      // op: Vd
10997
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10998
0
      Value |= (op & UINT64_C(16)) << 18;
10999
0
      Value |= (op & UINT64_C(15)) << 12;
11000
      // op: Vn
11001
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11002
0
      Value |= (op & UINT64_C(30)) << 15;
11003
0
      Value |= (op & UINT64_C(1)) << 7;
11004
      // op: Vm
11005
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11006
0
      Value |= (op & UINT64_C(1)) << 5;
11007
0
      Value |= (op & UINT64_C(14)) >> 1;
11008
      // op: idx
11009
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11010
0
      op &= UINT64_C(1);
11011
0
      op <<= 3;
11012
0
      Value |= op;
11013
0
      break;
11014
0
    }
11015
0
    case ARM::VFMALD:
11016
0
    case ARM::VFMSLD: {
11017
      // op: Vd
11018
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11019
0
      Value |= (op & UINT64_C(16)) << 18;
11020
0
      Value |= (op & UINT64_C(15)) << 12;
11021
      // op: Vn
11022
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11023
0
      Value |= (op & UINT64_C(30)) << 15;
11024
0
      Value |= (op & UINT64_C(1)) << 7;
11025
      // op: Vm
11026
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11027
0
      Value |= (op & UINT64_C(1)) << 5;
11028
0
      Value |= (op & UINT64_C(30)) >> 1;
11029
0
      break;
11030
0
    }
11031
0
    case ARM::VQRSHLsv1i64:
11032
0
    case ARM::VQRSHLsv2i32:
11033
0
    case ARM::VQRSHLsv2i64:
11034
0
    case ARM::VQRSHLsv4i16:
11035
0
    case ARM::VQRSHLsv4i32:
11036
0
    case ARM::VQRSHLsv8i8:
11037
0
    case ARM::VQRSHLsv8i16:
11038
0
    case ARM::VQRSHLsv16i8:
11039
0
    case ARM::VQRSHLuv1i64:
11040
0
    case ARM::VQRSHLuv2i32:
11041
0
    case ARM::VQRSHLuv2i64:
11042
0
    case ARM::VQRSHLuv4i16:
11043
0
    case ARM::VQRSHLuv4i32:
11044
0
    case ARM::VQRSHLuv8i8:
11045
0
    case ARM::VQRSHLuv8i16:
11046
0
    case ARM::VQRSHLuv16i8:
11047
0
    case ARM::VQSHLsv1i64:
11048
0
    case ARM::VQSHLsv2i32:
11049
0
    case ARM::VQSHLsv2i64:
11050
0
    case ARM::VQSHLsv4i16:
11051
0
    case ARM::VQSHLsv4i32:
11052
0
    case ARM::VQSHLsv8i8:
11053
0
    case ARM::VQSHLsv8i16:
11054
0
    case ARM::VQSHLsv16i8:
11055
0
    case ARM::VQSHLuv1i64:
11056
0
    case ARM::VQSHLuv2i32:
11057
0
    case ARM::VQSHLuv2i64:
11058
0
    case ARM::VQSHLuv4i16:
11059
0
    case ARM::VQSHLuv4i32:
11060
0
    case ARM::VQSHLuv8i8:
11061
0
    case ARM::VQSHLuv8i16:
11062
0
    case ARM::VQSHLuv16i8:
11063
0
    case ARM::VRSHLsv1i64:
11064
0
    case ARM::VRSHLsv2i32:
11065
0
    case ARM::VRSHLsv2i64:
11066
0
    case ARM::VRSHLsv4i16:
11067
0
    case ARM::VRSHLsv4i32:
11068
0
    case ARM::VRSHLsv8i8:
11069
0
    case ARM::VRSHLsv8i16:
11070
0
    case ARM::VRSHLsv16i8:
11071
0
    case ARM::VRSHLuv1i64:
11072
0
    case ARM::VRSHLuv2i32:
11073
0
    case ARM::VRSHLuv2i64:
11074
0
    case ARM::VRSHLuv4i16:
11075
0
    case ARM::VRSHLuv4i32:
11076
0
    case ARM::VRSHLuv8i8:
11077
0
    case ARM::VRSHLuv8i16:
11078
0
    case ARM::VRSHLuv16i8:
11079
0
    case ARM::VSHLsv1i64:
11080
0
    case ARM::VSHLsv2i32:
11081
0
    case ARM::VSHLsv2i64:
11082
0
    case ARM::VSHLsv4i16:
11083
0
    case ARM::VSHLsv4i32:
11084
0
    case ARM::VSHLsv8i8:
11085
0
    case ARM::VSHLsv8i16:
11086
0
    case ARM::VSHLsv16i8:
11087
0
    case ARM::VSHLuv1i64:
11088
0
    case ARM::VSHLuv2i32:
11089
0
    case ARM::VSHLuv2i64:
11090
0
    case ARM::VSHLuv4i16:
11091
0
    case ARM::VSHLuv4i32:
11092
0
    case ARM::VSHLuv8i8:
11093
0
    case ARM::VSHLuv8i16:
11094
0
    case ARM::VSHLuv16i8: {
11095
      // op: Vd
11096
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11097
0
      Value |= (op & UINT64_C(16)) << 18;
11098
0
      Value |= (op & UINT64_C(15)) << 12;
11099
      // op: Vn
11100
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11101
0
      Value |= (op & UINT64_C(15)) << 16;
11102
0
      Value |= (op & UINT64_C(16)) << 3;
11103
      // op: Vm
11104
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11105
0
      Value |= (op & UINT64_C(16)) << 1;
11106
0
      Value |= (op & UINT64_C(15));
11107
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
11108
0
      break;
11109
0
    }
11110
0
    case ARM::VCMLAv2f32:
11111
0
    case ARM::VCMLAv4f16:
11112
0
    case ARM::VCMLAv4f32:
11113
0
    case ARM::VCMLAv8f16: {
11114
      // op: Vd
11115
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11116
0
      Value |= (op & UINT64_C(16)) << 18;
11117
0
      Value |= (op & UINT64_C(15)) << 12;
11118
      // op: Vn
11119
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11120
0
      Value |= (op & UINT64_C(15)) << 16;
11121
0
      Value |= (op & UINT64_C(16)) << 3;
11122
      // op: Vm
11123
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11124
0
      Value |= (op & UINT64_C(16)) << 1;
11125
0
      Value |= (op & UINT64_C(15));
11126
      // op: rot
11127
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
11128
0
      op &= UINT64_C(3);
11129
0
      op <<= 23;
11130
0
      Value |= op;
11131
0
      break;
11132
0
    }
11133
0
    case ARM::VCMLAv2f32_indexed:
11134
0
    case ARM::VCMLAv4f32_indexed: {
11135
      // op: Vd
11136
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11137
0
      Value |= (op & UINT64_C(16)) << 18;
11138
0
      Value |= (op & UINT64_C(15)) << 12;
11139
      // op: Vn
11140
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11141
0
      Value |= (op & UINT64_C(15)) << 16;
11142
0
      Value |= (op & UINT64_C(16)) << 3;
11143
      // op: Vm
11144
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11145
0
      Value |= (op & UINT64_C(16)) << 1;
11146
0
      Value |= (op & UINT64_C(15));
11147
      // op: rot
11148
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
11149
0
      op &= UINT64_C(3);
11150
0
      op <<= 20;
11151
0
      Value |= op;
11152
0
      break;
11153
0
    }
11154
0
    case ARM::SHA1C:
11155
0
    case ARM::SHA1M:
11156
0
    case ARM::SHA1P:
11157
0
    case ARM::SHA1SU0:
11158
0
    case ARM::SHA256H:
11159
0
    case ARM::SHA256H2:
11160
0
    case ARM::SHA256SU1:
11161
0
    case ARM::VABALsv2i64:
11162
0
    case ARM::VABALsv4i32:
11163
0
    case ARM::VABALsv8i16:
11164
0
    case ARM::VABALuv2i64:
11165
0
    case ARM::VABALuv4i32:
11166
0
    case ARM::VABALuv8i16:
11167
0
    case ARM::VABAsv2i32:
11168
0
    case ARM::VABAsv4i16:
11169
0
    case ARM::VABAsv4i32:
11170
0
    case ARM::VABAsv8i8:
11171
0
    case ARM::VABAsv8i16:
11172
0
    case ARM::VABAsv16i8:
11173
0
    case ARM::VABAuv2i32:
11174
0
    case ARM::VABAuv4i16:
11175
0
    case ARM::VABAuv4i32:
11176
0
    case ARM::VABAuv8i8:
11177
0
    case ARM::VABAuv8i16:
11178
0
    case ARM::VABAuv16i8:
11179
0
    case ARM::VBIFd:
11180
0
    case ARM::VBIFq:
11181
0
    case ARM::VBITd:
11182
0
    case ARM::VBITq:
11183
0
    case ARM::VBSLd:
11184
0
    case ARM::VBSLq:
11185
0
    case ARM::VFMAfd:
11186
0
    case ARM::VFMAfq:
11187
0
    case ARM::VFMAhd:
11188
0
    case ARM::VFMAhq:
11189
0
    case ARM::VFMSfd:
11190
0
    case ARM::VFMSfq:
11191
0
    case ARM::VFMShd:
11192
0
    case ARM::VFMShq:
11193
0
    case ARM::VMLALsv2i64:
11194
0
    case ARM::VMLALsv4i32:
11195
0
    case ARM::VMLALsv8i16:
11196
0
    case ARM::VMLALuv2i64:
11197
0
    case ARM::VMLALuv4i32:
11198
0
    case ARM::VMLALuv8i16:
11199
0
    case ARM::VMLAfd:
11200
0
    case ARM::VMLAfq:
11201
0
    case ARM::VMLAhd:
11202
0
    case ARM::VMLAhq:
11203
0
    case ARM::VMLAv2i32:
11204
0
    case ARM::VMLAv4i16:
11205
0
    case ARM::VMLAv4i32:
11206
0
    case ARM::VMLAv8i8:
11207
0
    case ARM::VMLAv8i16:
11208
0
    case ARM::VMLAv16i8:
11209
0
    case ARM::VMLSLsv2i64:
11210
0
    case ARM::VMLSLsv4i32:
11211
0
    case ARM::VMLSLsv8i16:
11212
0
    case ARM::VMLSLuv2i64:
11213
0
    case ARM::VMLSLuv4i32:
11214
0
    case ARM::VMLSLuv8i16:
11215
0
    case ARM::VMLSfd:
11216
0
    case ARM::VMLSfq:
11217
0
    case ARM::VMLShd:
11218
0
    case ARM::VMLShq:
11219
0
    case ARM::VMLSv2i32:
11220
0
    case ARM::VMLSv4i16:
11221
0
    case ARM::VMLSv4i32:
11222
0
    case ARM::VMLSv8i8:
11223
0
    case ARM::VMLSv8i16:
11224
0
    case ARM::VMLSv16i8:
11225
0
    case ARM::VQDMLALv2i64:
11226
0
    case ARM::VQDMLALv4i32:
11227
0
    case ARM::VQDMLSLv2i64:
11228
0
    case ARM::VQDMLSLv4i32:
11229
0
    case ARM::VQRDMLAHv2i32:
11230
0
    case ARM::VQRDMLAHv4i16:
11231
0
    case ARM::VQRDMLAHv4i32:
11232
0
    case ARM::VQRDMLAHv8i16:
11233
0
    case ARM::VQRDMLSHv2i32:
11234
0
    case ARM::VQRDMLSHv4i16:
11235
0
    case ARM::VQRDMLSHv4i32:
11236
0
    case ARM::VQRDMLSHv8i16:
11237
0
    case ARM::VTBX1:
11238
0
    case ARM::VTBX2:
11239
0
    case ARM::VTBX3:
11240
0
    case ARM::VTBX4: {
11241
      // op: Vd
11242
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11243
0
      Value |= (op & UINT64_C(16)) << 18;
11244
0
      Value |= (op & UINT64_C(15)) << 12;
11245
      // op: Vn
11246
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11247
0
      Value |= (op & UINT64_C(15)) << 16;
11248
0
      Value |= (op & UINT64_C(16)) << 3;
11249
      // op: Vm
11250
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11251
0
      Value |= (op & UINT64_C(16)) << 1;
11252
0
      Value |= (op & UINT64_C(15));
11253
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
11254
0
      break;
11255
0
    }
11256
0
    case ARM::VMLALslsv2i32:
11257
0
    case ARM::VMLALsluv2i32:
11258
0
    case ARM::VMLAslfd:
11259
0
    case ARM::VMLAslfq:
11260
0
    case ARM::VMLAslv2i32:
11261
0
    case ARM::VMLAslv4i32:
11262
0
    case ARM::VMLSLslsv2i32:
11263
0
    case ARM::VMLSLsluv2i32:
11264
0
    case ARM::VMLSslfd:
11265
0
    case ARM::VMLSslfq:
11266
0
    case ARM::VMLSslv2i32:
11267
0
    case ARM::VMLSslv4i32:
11268
0
    case ARM::VQDMLALslv2i32:
11269
0
    case ARM::VQDMLSLslv2i32:
11270
0
    case ARM::VQRDMLAHslv2i32:
11271
0
    case ARM::VQRDMLAHslv4i32:
11272
0
    case ARM::VQRDMLSHslv2i32:
11273
0
    case ARM::VQRDMLSHslv4i32: {
11274
      // op: Vd
11275
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11276
0
      Value |= (op & UINT64_C(16)) << 18;
11277
0
      Value |= (op & UINT64_C(15)) << 12;
11278
      // op: Vn
11279
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11280
0
      Value |= (op & UINT64_C(15)) << 16;
11281
0
      Value |= (op & UINT64_C(16)) << 3;
11282
      // op: Vm
11283
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11284
0
      op &= UINT64_C(15);
11285
0
      Value |= op;
11286
      // op: lane
11287
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
11288
0
      op &= UINT64_C(1);
11289
0
      op <<= 5;
11290
0
      Value |= op;
11291
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
11292
0
      break;
11293
0
    }
11294
0
    case ARM::VCMLAv4f16_indexed:
11295
0
    case ARM::VCMLAv8f16_indexed: {
11296
      // op: Vd
11297
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11298
0
      Value |= (op & UINT64_C(16)) << 18;
11299
0
      Value |= (op & UINT64_C(15)) << 12;
11300
      // op: Vn
11301
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11302
0
      Value |= (op & UINT64_C(15)) << 16;
11303
0
      Value |= (op & UINT64_C(16)) << 3;
11304
      // op: Vm
11305
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11306
0
      op &= UINT64_C(15);
11307
0
      Value |= op;
11308
      // op: rot
11309
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
11310
0
      op &= UINT64_C(3);
11311
0
      op <<= 20;
11312
0
      Value |= op;
11313
      // op: lane
11314
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
11315
0
      op &= UINT64_C(1);
11316
0
      op <<= 5;
11317
0
      Value |= op;
11318
0
      break;
11319
0
    }
11320
0
    case ARM::VMLALslsv4i16:
11321
0
    case ARM::VMLALsluv4i16:
11322
0
    case ARM::VMLAslhd:
11323
0
    case ARM::VMLAslhq:
11324
0
    case ARM::VMLAslv4i16:
11325
0
    case ARM::VMLAslv8i16:
11326
0
    case ARM::VMLSLslsv4i16:
11327
0
    case ARM::VMLSLsluv4i16:
11328
0
    case ARM::VMLSslhd:
11329
0
    case ARM::VMLSslhq:
11330
0
    case ARM::VMLSslv4i16:
11331
0
    case ARM::VMLSslv8i16:
11332
0
    case ARM::VQDMLALslv4i16:
11333
0
    case ARM::VQDMLSLslv4i16:
11334
0
    case ARM::VQRDMLAHslv4i16:
11335
0
    case ARM::VQRDMLAHslv8i16:
11336
0
    case ARM::VQRDMLSHslv4i16:
11337
0
    case ARM::VQRDMLSHslv8i16: {
11338
      // op: Vd
11339
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11340
0
      Value |= (op & UINT64_C(16)) << 18;
11341
0
      Value |= (op & UINT64_C(15)) << 12;
11342
      // op: Vn
11343
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11344
0
      Value |= (op & UINT64_C(15)) << 16;
11345
0
      Value |= (op & UINT64_C(16)) << 3;
11346
      // op: Vm
11347
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11348
0
      op &= UINT64_C(7);
11349
0
      Value |= op;
11350
      // op: lane
11351
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
11352
0
      Value |= (op & UINT64_C(2)) << 4;
11353
0
      Value |= (op & UINT64_C(1)) << 3;
11354
0
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
11355
0
      break;
11356
0
    }
11357
0
    case ARM::BF16VDOTS_VDOTD:
11358
0
    case ARM::BF16VDOTS_VDOTQ:
11359
0
    case ARM::VBF16MALBQ:
11360
0
    case ARM::VBF16MALTQ:
11361
0
    case ARM::VMMLA:
11362
0
    case ARM::VSDOTD:
11363
0
    case ARM::VSDOTQ:
11364
0
    case ARM::VSMMLA:
11365
0
    case ARM::VUDOTD:
11366
0
    case ARM::VUDOTQ:
11367
0
    case ARM::VUMMLA:
11368
0
    case ARM::VUSDOTD:
11369
0
    case ARM::VUSDOTQ:
11370
0
    case ARM::VUSMMLA: {
11371
      // op: Vd
11372
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11373
0
      Value |= (op & UINT64_C(16)) << 18;
11374
0
      Value |= (op & UINT64_C(15)) << 12;
11375
      // op: Vn
11376
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11377
0
      Value |= (op & UINT64_C(15)) << 16;
11378
0
      Value |= (op & UINT64_C(16)) << 3;
11379
      // op: Vm
11380
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11381
0
      Value |= (op & UINT64_C(16)) << 1;
11382
0
      Value |= (op & UINT64_C(15));
11383
0
      break;
11384
0
    }
11385
0
    case ARM::BF16VDOTI_VDOTD:
11386
0
    case ARM::BF16VDOTI_VDOTQ:
11387
0
    case ARM::VSDOTDI:
11388
0
    case ARM::VSDOTQI:
11389
0
    case ARM::VSUDOTDI:
11390
0
    case ARM::VSUDOTQI:
11391
0
    case ARM::VUDOTDI:
11392
0
    case ARM::VUDOTQI:
11393
0
    case ARM::VUSDOTDI:
11394
0
    case ARM::VUSDOTQI: {
11395
      // op: Vd
11396
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11397
0
      Value |= (op & UINT64_C(16)) << 18;
11398
0
      Value |= (op & UINT64_C(15)) << 12;
11399
      // op: Vn
11400
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11401
0
      Value |= (op & UINT64_C(15)) << 16;
11402
0
      Value |= (op & UINT64_C(16)) << 3;
11403
      // op: Vm
11404
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11405
0
      op &= UINT64_C(15);
11406
0
      Value |= op;
11407
      // op: lane
11408
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
11409
0
      op &= UINT64_C(1);
11410
0
      op <<= 5;
11411
0
      Value |= op;
11412
0
      break;
11413
0
    }
11414
0
    case ARM::VBF16MALBQI:
11415
0
    case ARM::VBF16MALTQI: {
11416
      // op: Vd
11417
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11418
0
      Value |= (op & UINT64_C(16)) << 18;
11419
0
      Value |= (op & UINT64_C(15)) << 12;
11420
      // op: Vn
11421
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11422
0
      Value |= (op & UINT64_C(15)) << 16;
11423
0
      Value |= (op & UINT64_C(16)) << 3;
11424
      // op: Vm
11425
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11426
0
      op &= UINT64_C(7);
11427
0
      Value |= op;
11428
      // op: idx
11429
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
11430
0
      Value |= (op & UINT64_C(2)) << 4;
11431
0
      Value |= (op & UINT64_C(1)) << 3;
11432
0
      break;
11433
0
    }
11434
0
    case ARM::VST1LNd16: {
11435
      // op: Vd
11436
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11437
0
      Value |= (op & UINT64_C(16)) << 18;
11438
0
      Value |= (op & UINT64_C(15)) << 12;
11439
      // op: Rn
11440
0
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
11441
0
      Value |= (op & UINT64_C(15)) << 16;
11442
0
      Value |= (op & UINT64_C(16));
11443
      // op: lane
11444
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11445
0
      op &= UINT64_C(3);
11446
0
      op <<= 6;
11447
0
      Value |= op;
11448
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11449
0
      break;
11450
0
    }
11451
0
    case ARM::VST2LNd32:
11452
0
    case ARM::VST2LNq32: {
11453
      // op: Vd
11454
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11455
0
      Value |= (op & UINT64_C(16)) << 18;
11456
0
      Value |= (op & UINT64_C(15)) << 12;
11457
      // op: Rn
11458
0
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
11459
0
      Value |= (op & UINT64_C(15)) << 16;
11460
0
      Value |= (op & UINT64_C(16));
11461
      // op: lane
11462
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
11463
0
      op &= UINT64_C(1);
11464
0
      op <<= 7;
11465
0
      Value |= op;
11466
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11467
0
      break;
11468
0
    }
11469
0
    case ARM::VST2LNd16:
11470
0
    case ARM::VST2LNq16: {
11471
      // op: Vd
11472
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11473
0
      Value |= (op & UINT64_C(16)) << 18;
11474
0
      Value |= (op & UINT64_C(15)) << 12;
11475
      // op: Rn
11476
0
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
11477
0
      Value |= (op & UINT64_C(15)) << 16;
11478
0
      Value |= (op & UINT64_C(16));
11479
      // op: lane
11480
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
11481
0
      op &= UINT64_C(3);
11482
0
      op <<= 6;
11483
0
      Value |= op;
11484
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11485
0
      break;
11486
0
    }
11487
0
    case ARM::VST2LNd8: {
11488
      // op: Vd
11489
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11490
0
      Value |= (op & UINT64_C(16)) << 18;
11491
0
      Value |= (op & UINT64_C(15)) << 12;
11492
      // op: Rn
11493
0
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
11494
0
      Value |= (op & UINT64_C(15)) << 16;
11495
0
      Value |= (op & UINT64_C(16));
11496
      // op: lane
11497
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
11498
0
      op &= UINT64_C(7);
11499
0
      op <<= 5;
11500
0
      Value |= op;
11501
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11502
0
      break;
11503
0
    }
11504
0
    case ARM::VST4LNd16:
11505
0
    case ARM::VST4LNq16: {
11506
      // op: Vd
11507
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11508
0
      Value |= (op & UINT64_C(16)) << 18;
11509
0
      Value |= (op & UINT64_C(15)) << 12;
11510
      // op: Rn
11511
0
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
11512
0
      Value |= (op & UINT64_C(15)) << 16;
11513
0
      Value |= (op & UINT64_C(16));
11514
      // op: lane
11515
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
11516
0
      op &= UINT64_C(3);
11517
0
      op <<= 6;
11518
0
      Value |= op;
11519
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11520
0
      break;
11521
0
    }
11522
0
    case ARM::VST4LNd8: {
11523
      // op: Vd
11524
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11525
0
      Value |= (op & UINT64_C(16)) << 18;
11526
0
      Value |= (op & UINT64_C(15)) << 12;
11527
      // op: Rn
11528
0
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
11529
0
      Value |= (op & UINT64_C(15)) << 16;
11530
0
      Value |= (op & UINT64_C(16));
11531
      // op: lane
11532
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
11533
0
      op &= UINT64_C(7);
11534
0
      op <<= 5;
11535
0
      Value |= op;
11536
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11537
0
      break;
11538
0
    }
11539
0
    case ARM::VST1d8:
11540
0
    case ARM::VST1d8T:
11541
0
    case ARM::VST1d16:
11542
0
    case ARM::VST1d16T:
11543
0
    case ARM::VST1d32:
11544
0
    case ARM::VST1d32T:
11545
0
    case ARM::VST1d64:
11546
0
    case ARM::VST1d64T:
11547
0
    case ARM::VST3d8:
11548
0
    case ARM::VST3d16:
11549
0
    case ARM::VST3d32:
11550
0
    case ARM::VST3q8:
11551
0
    case ARM::VST3q16:
11552
0
    case ARM::VST3q32: {
11553
      // op: Vd
11554
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11555
0
      Value |= (op & UINT64_C(16)) << 18;
11556
0
      Value |= (op & UINT64_C(15)) << 12;
11557
      // op: Rn
11558
0
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
11559
0
      Value |= (op & UINT64_C(15)) << 16;
11560
0
      Value |= (op & UINT64_C(16));
11561
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11562
0
      break;
11563
0
    }
11564
0
    case ARM::VST4LNd32:
11565
0
    case ARM::VST4LNq32: {
11566
      // op: Vd
11567
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11568
0
      Value |= (op & UINT64_C(16)) << 18;
11569
0
      Value |= (op & UINT64_C(15)) << 12;
11570
      // op: Rn
11571
0
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
11572
0
      Value |= (op & UINT64_C(15)) << 16;
11573
0
      Value |= (op & UINT64_C(48));
11574
      // op: lane
11575
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
11576
0
      op &= UINT64_C(1);
11577
0
      op <<= 7;
11578
0
      Value |= op;
11579
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11580
0
      break;
11581
0
    }
11582
0
    case ARM::VST1d8Q:
11583
0
    case ARM::VST1d16Q:
11584
0
    case ARM::VST1d32Q:
11585
0
    case ARM::VST1d64Q:
11586
0
    case ARM::VST1q8:
11587
0
    case ARM::VST1q16:
11588
0
    case ARM::VST1q32:
11589
0
    case ARM::VST1q64:
11590
0
    case ARM::VST2b8:
11591
0
    case ARM::VST2b16:
11592
0
    case ARM::VST2b32:
11593
0
    case ARM::VST2d8:
11594
0
    case ARM::VST2d16:
11595
0
    case ARM::VST2d32:
11596
0
    case ARM::VST2q8:
11597
0
    case ARM::VST2q16:
11598
0
    case ARM::VST2q32:
11599
0
    case ARM::VST4d8:
11600
0
    case ARM::VST4d16:
11601
0
    case ARM::VST4d32:
11602
0
    case ARM::VST4q8:
11603
0
    case ARM::VST4q16:
11604
0
    case ARM::VST4q32: {
11605
      // op: Vd
11606
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11607
0
      Value |= (op & UINT64_C(16)) << 18;
11608
0
      Value |= (op & UINT64_C(15)) << 12;
11609
      // op: Rn
11610
0
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
11611
0
      Value |= (op & UINT64_C(15)) << 16;
11612
0
      Value |= (op & UINT64_C(48));
11613
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11614
0
      break;
11615
0
    }
11616
0
    case ARM::VST1LNd8: {
11617
      // op: Vd
11618
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11619
0
      Value |= (op & UINT64_C(16)) << 18;
11620
0
      Value |= (op & UINT64_C(15)) << 12;
11621
      // op: Rn
11622
0
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
11623
0
      op &= UINT64_C(15);
11624
0
      op <<= 16;
11625
0
      Value |= op;
11626
      // op: lane
11627
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11628
0
      op &= UINT64_C(7);
11629
0
      op <<= 5;
11630
0
      Value |= op;
11631
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11632
0
      break;
11633
0
    }
11634
0
    case ARM::VST3LNd32:
11635
0
    case ARM::VST3LNq32: {
11636
      // op: Vd
11637
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11638
0
      Value |= (op & UINT64_C(16)) << 18;
11639
0
      Value |= (op & UINT64_C(15)) << 12;
11640
      // op: Rn
11641
0
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
11642
0
      op &= UINT64_C(15);
11643
0
      op <<= 16;
11644
0
      Value |= op;
11645
      // op: lane
11646
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
11647
0
      op &= UINT64_C(1);
11648
0
      op <<= 7;
11649
0
      Value |= op;
11650
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11651
0
      break;
11652
0
    }
11653
0
    case ARM::VST3LNd16:
11654
0
    case ARM::VST3LNq16: {
11655
      // op: Vd
11656
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11657
0
      Value |= (op & UINT64_C(16)) << 18;
11658
0
      Value |= (op & UINT64_C(15)) << 12;
11659
      // op: Rn
11660
0
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
11661
0
      op &= UINT64_C(15);
11662
0
      op <<= 16;
11663
0
      Value |= op;
11664
      // op: lane
11665
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
11666
0
      op &= UINT64_C(3);
11667
0
      op <<= 6;
11668
0
      Value |= op;
11669
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11670
0
      break;
11671
0
    }
11672
0
    case ARM::VST3LNd8: {
11673
      // op: Vd
11674
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11675
0
      Value |= (op & UINT64_C(16)) << 18;
11676
0
      Value |= (op & UINT64_C(15)) << 12;
11677
      // op: Rn
11678
0
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
11679
0
      op &= UINT64_C(15);
11680
0
      op <<= 16;
11681
0
      Value |= op;
11682
      // op: lane
11683
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
11684
0
      op &= UINT64_C(7);
11685
0
      op <<= 5;
11686
0
      Value |= op;
11687
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11688
0
      break;
11689
0
    }
11690
0
    case ARM::VST1LNd32: {
11691
      // op: Vd
11692
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11693
0
      Value |= (op & UINT64_C(16)) << 18;
11694
0
      Value |= (op & UINT64_C(15)) << 12;
11695
      // op: Rn
11696
0
      op = getAddrMode6OneLane32AddressOpValue(MI, 0, Fixups, STI);
11697
0
      Value |= (op & UINT64_C(15)) << 16;
11698
0
      Value |= (op & UINT64_C(48));
11699
      // op: lane
11700
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11701
0
      op &= UINT64_C(1);
11702
0
      op <<= 7;
11703
0
      Value |= op;
11704
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11705
0
      break;
11706
0
    }
11707
0
    case ARM::VST1d8wb_fixed:
11708
0
    case ARM::VST1d16wb_fixed:
11709
0
    case ARM::VST1d32wb_fixed:
11710
0
    case ARM::VST1d64wb_fixed: {
11711
      // op: Vd
11712
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11713
0
      Value |= (op & UINT64_C(16)) << 18;
11714
0
      Value |= (op & UINT64_C(15)) << 12;
11715
      // op: Rn
11716
0
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
11717
0
      Value |= (op & UINT64_C(15)) << 16;
11718
0
      Value |= (op & UINT64_C(16));
11719
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11720
0
      break;
11721
0
    }
11722
0
    case ARM::VST1d8Qwb_fixed:
11723
0
    case ARM::VST1d8Twb_fixed:
11724
0
    case ARM::VST1d16Qwb_fixed:
11725
0
    case ARM::VST1d16Twb_fixed:
11726
0
    case ARM::VST1d32Qwb_fixed:
11727
0
    case ARM::VST1d32Twb_fixed:
11728
0
    case ARM::VST1d64Qwb_fixed:
11729
0
    case ARM::VST1d64Twb_fixed:
11730
0
    case ARM::VST1q8wb_fixed:
11731
0
    case ARM::VST1q16wb_fixed:
11732
0
    case ARM::VST1q32wb_fixed:
11733
0
    case ARM::VST1q64wb_fixed:
11734
0
    case ARM::VST2b8wb_fixed:
11735
0
    case ARM::VST2b16wb_fixed:
11736
0
    case ARM::VST2b32wb_fixed:
11737
0
    case ARM::VST2d8wb_fixed:
11738
0
    case ARM::VST2d16wb_fixed:
11739
0
    case ARM::VST2d32wb_fixed:
11740
0
    case ARM::VST2q8wb_fixed:
11741
0
    case ARM::VST2q16wb_fixed:
11742
0
    case ARM::VST2q32wb_fixed: {
11743
      // op: Vd
11744
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11745
0
      Value |= (op & UINT64_C(16)) << 18;
11746
0
      Value |= (op & UINT64_C(15)) << 12;
11747
      // op: Rn
11748
0
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
11749
0
      Value |= (op & UINT64_C(15)) << 16;
11750
0
      Value |= (op & UINT64_C(48));
11751
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11752
0
      break;
11753
0
    }
11754
0
    case ARM::VST1LNd16_UPD: {
11755
      // op: Vd
11756
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
11757
0
      Value |= (op & UINT64_C(16)) << 18;
11758
0
      Value |= (op & UINT64_C(15)) << 12;
11759
      // op: Rn
11760
0
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
11761
0
      Value |= (op & UINT64_C(15)) << 16;
11762
0
      Value |= (op & UINT64_C(16));
11763
      // op: Rm
11764
0
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
11765
0
      op &= UINT64_C(15);
11766
0
      Value |= op;
11767
      // op: lane
11768
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
11769
0
      op &= UINT64_C(3);
11770
0
      op <<= 6;
11771
0
      Value |= op;
11772
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11773
0
      break;
11774
0
    }
11775
0
    case ARM::VST2LNd32_UPD:
11776
0
    case ARM::VST2LNq32_UPD: {
11777
      // op: Vd
11778
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
11779
0
      Value |= (op & UINT64_C(16)) << 18;
11780
0
      Value |= (op & UINT64_C(15)) << 12;
11781
      // op: Rn
11782
0
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
11783
0
      Value |= (op & UINT64_C(15)) << 16;
11784
0
      Value |= (op & UINT64_C(16));
11785
      // op: Rm
11786
0
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
11787
0
      op &= UINT64_C(15);
11788
0
      Value |= op;
11789
      // op: lane
11790
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
11791
0
      op &= UINT64_C(1);
11792
0
      op <<= 7;
11793
0
      Value |= op;
11794
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11795
0
      break;
11796
0
    }
11797
0
    case ARM::VST2LNd16_UPD:
11798
0
    case ARM::VST2LNq16_UPD: {
11799
      // op: Vd
11800
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
11801
0
      Value |= (op & UINT64_C(16)) << 18;
11802
0
      Value |= (op & UINT64_C(15)) << 12;
11803
      // op: Rn
11804
0
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
11805
0
      Value |= (op & UINT64_C(15)) << 16;
11806
0
      Value |= (op & UINT64_C(16));
11807
      // op: Rm
11808
0
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
11809
0
      op &= UINT64_C(15);
11810
0
      Value |= op;
11811
      // op: lane
11812
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
11813
0
      op &= UINT64_C(3);
11814
0
      op <<= 6;
11815
0
      Value |= op;
11816
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11817
0
      break;
11818
0
    }
11819
0
    case ARM::VST2LNd8_UPD: {
11820
      // op: Vd
11821
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
11822
0
      Value |= (op & UINT64_C(16)) << 18;
11823
0
      Value |= (op & UINT64_C(15)) << 12;
11824
      // op: Rn
11825
0
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
11826
0
      Value |= (op & UINT64_C(15)) << 16;
11827
0
      Value |= (op & UINT64_C(16));
11828
      // op: Rm
11829
0
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
11830
0
      op &= UINT64_C(15);
11831
0
      Value |= op;
11832
      // op: lane
11833
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
11834
0
      op &= UINT64_C(7);
11835
0
      op <<= 5;
11836
0
      Value |= op;
11837
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11838
0
      break;
11839
0
    }
11840
0
    case ARM::VST4LNd16_UPD:
11841
0
    case ARM::VST4LNq16_UPD: {
11842
      // op: Vd
11843
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
11844
0
      Value |= (op & UINT64_C(16)) << 18;
11845
0
      Value |= (op & UINT64_C(15)) << 12;
11846
      // op: Rn
11847
0
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
11848
0
      Value |= (op & UINT64_C(15)) << 16;
11849
0
      Value |= (op & UINT64_C(16));
11850
      // op: Rm
11851
0
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
11852
0
      op &= UINT64_C(15);
11853
0
      Value |= op;
11854
      // op: lane
11855
0
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
11856
0
      op &= UINT64_C(3);
11857
0
      op <<= 6;
11858
0
      Value |= op;
11859
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11860
0
      break;
11861
0
    }
11862
0
    case ARM::VST4LNd8_UPD: {
11863
      // op: Vd
11864
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
11865
0
      Value |= (op & UINT64_C(16)) << 18;
11866
0
      Value |= (op & UINT64_C(15)) << 12;
11867
      // op: Rn
11868
0
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
11869
0
      Value |= (op & UINT64_C(15)) << 16;
11870
0
      Value |= (op & UINT64_C(16));
11871
      // op: Rm
11872
0
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
11873
0
      op &= UINT64_C(15);
11874
0
      Value |= op;
11875
      // op: lane
11876
0
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
11877
0
      op &= UINT64_C(7);
11878
0
      op <<= 5;
11879
0
      Value |= op;
11880
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11881
0
      break;
11882
0
    }
11883
0
    case ARM::VST3d8_UPD:
11884
0
    case ARM::VST3d16_UPD:
11885
0
    case ARM::VST3d32_UPD:
11886
0
    case ARM::VST3q8_UPD:
11887
0
    case ARM::VST3q16_UPD:
11888
0
    case ARM::VST3q32_UPD: {
11889
      // op: Vd
11890
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
11891
0
      Value |= (op & UINT64_C(16)) << 18;
11892
0
      Value |= (op & UINT64_C(15)) << 12;
11893
      // op: Rn
11894
0
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
11895
0
      Value |= (op & UINT64_C(15)) << 16;
11896
0
      Value |= (op & UINT64_C(16));
11897
      // op: Rm
11898
0
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
11899
0
      op &= UINT64_C(15);
11900
0
      Value |= op;
11901
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11902
0
      break;
11903
0
    }
11904
0
    case ARM::VST1d8wb_register:
11905
0
    case ARM::VST1d16wb_register:
11906
0
    case ARM::VST1d32wb_register:
11907
0
    case ARM::VST1d64wb_register: {
11908
      // op: Vd
11909
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
11910
0
      Value |= (op & UINT64_C(16)) << 18;
11911
0
      Value |= (op & UINT64_C(15)) << 12;
11912
      // op: Rn
11913
0
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
11914
0
      Value |= (op & UINT64_C(15)) << 16;
11915
0
      Value |= (op & UINT64_C(16));
11916
      // op: Rm
11917
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11918
0
      op &= UINT64_C(15);
11919
0
      Value |= op;
11920
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11921
0
      break;
11922
0
    }
11923
0
    case ARM::VST4LNd32_UPD:
11924
0
    case ARM::VST4LNq32_UPD: {
11925
      // op: Vd
11926
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
11927
0
      Value |= (op & UINT64_C(16)) << 18;
11928
0
      Value |= (op & UINT64_C(15)) << 12;
11929
      // op: Rn
11930
0
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
11931
0
      Value |= (op & UINT64_C(15)) << 16;
11932
0
      Value |= (op & UINT64_C(48));
11933
      // op: Rm
11934
0
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
11935
0
      op &= UINT64_C(15);
11936
0
      Value |= op;
11937
      // op: lane
11938
0
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
11939
0
      op &= UINT64_C(1);
11940
0
      op <<= 7;
11941
0
      Value |= op;
11942
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11943
0
      break;
11944
0
    }
11945
0
    case ARM::VST4d8_UPD:
11946
0
    case ARM::VST4d16_UPD:
11947
0
    case ARM::VST4d32_UPD:
11948
0
    case ARM::VST4q8_UPD:
11949
0
    case ARM::VST4q16_UPD:
11950
0
    case ARM::VST4q32_UPD: {
11951
      // op: Vd
11952
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
11953
0
      Value |= (op & UINT64_C(16)) << 18;
11954
0
      Value |= (op & UINT64_C(15)) << 12;
11955
      // op: Rn
11956
0
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
11957
0
      Value |= (op & UINT64_C(15)) << 16;
11958
0
      Value |= (op & UINT64_C(48));
11959
      // op: Rm
11960
0
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
11961
0
      op &= UINT64_C(15);
11962
0
      Value |= op;
11963
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11964
0
      break;
11965
0
    }
11966
0
    case ARM::VST1d8Qwb_register:
11967
0
    case ARM::VST1d8Twb_register:
11968
0
    case ARM::VST1d16Qwb_register:
11969
0
    case ARM::VST1d16Twb_register:
11970
0
    case ARM::VST1d32Qwb_register:
11971
0
    case ARM::VST1d32Twb_register:
11972
0
    case ARM::VST1d64Qwb_register:
11973
0
    case ARM::VST1d64Twb_register:
11974
0
    case ARM::VST1q8wb_register:
11975
0
    case ARM::VST1q16wb_register:
11976
0
    case ARM::VST1q32wb_register:
11977
0
    case ARM::VST1q64wb_register:
11978
0
    case ARM::VST2b8wb_register:
11979
0
    case ARM::VST2b16wb_register:
11980
0
    case ARM::VST2b32wb_register:
11981
0
    case ARM::VST2d8wb_register:
11982
0
    case ARM::VST2d16wb_register:
11983
0
    case ARM::VST2d32wb_register:
11984
0
    case ARM::VST2q8wb_register:
11985
0
    case ARM::VST2q16wb_register:
11986
0
    case ARM::VST2q32wb_register: {
11987
      // op: Vd
11988
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
11989
0
      Value |= (op & UINT64_C(16)) << 18;
11990
0
      Value |= (op & UINT64_C(15)) << 12;
11991
      // op: Rn
11992
0
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
11993
0
      Value |= (op & UINT64_C(15)) << 16;
11994
0
      Value |= (op & UINT64_C(48));
11995
      // op: Rm
11996
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11997
0
      op &= UINT64_C(15);
11998
0
      Value |= op;
11999
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
12000
0
      break;
12001
0
    }
12002
0
    case ARM::VST1LNd8_UPD: {
12003
      // op: Vd
12004
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
12005
0
      Value |= (op & UINT64_C(16)) << 18;
12006
0
      Value |= (op & UINT64_C(15)) << 12;
12007
      // op: Rn
12008
0
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
12009
0
      op &= UINT64_C(15);
12010
0
      op <<= 16;
12011
0
      Value |= op;
12012
      // op: Rm
12013
0
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
12014
0
      op &= UINT64_C(15);
12015
0
      Value |= op;
12016
      // op: lane
12017
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
12018
0
      op &= UINT64_C(7);
12019
0
      op <<= 5;
12020
0
      Value |= op;
12021
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
12022
0
      break;
12023
0
    }
12024
0
    case ARM::VST3LNd32_UPD:
12025
0
    case ARM::VST3LNq32_UPD: {
12026
      // op: Vd
12027
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
12028
0
      Value |= (op & UINT64_C(16)) << 18;
12029
0
      Value |= (op & UINT64_C(15)) << 12;
12030
      // op: Rn
12031
0
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
12032
0
      op &= UINT64_C(15);
12033
0
      op <<= 16;
12034
0
      Value |= op;
12035
      // op: Rm
12036
0
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
12037
0
      op &= UINT64_C(15);
12038
0
      Value |= op;
12039
      // op: lane
12040
0
      op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI);
12041
0
      op &= UINT64_C(1);
12042
0
      op <<= 7;
12043
0
      Value |= op;
12044
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
12045
0
      break;
12046
0
    }
12047
0
    case ARM::VST3LNd16_UPD:
12048
0
    case ARM::VST3LNq16_UPD: {
12049
      // op: Vd
12050
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
12051
0
      Value |= (op & UINT64_C(16)) << 18;
12052
0
      Value |= (op & UINT64_C(15)) << 12;
12053
      // op: Rn
12054
0
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
12055
0
      op &= UINT64_C(15);
12056
0
      op <<= 16;
12057
0
      Value |= op;
12058
      // op: Rm
12059
0
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
12060
0
      op &= UINT64_C(15);
12061
0
      Value |= op;
12062
      // op: lane
12063
0
      op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI);
12064
0
      op &= UINT64_C(3);
12065
0
      op <<= 6;
12066
0
      Value |= op;
12067
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
12068
0
      break;
12069
0
    }
12070
0
    case ARM::VST3LNd8_UPD: {
12071
      // op: Vd
12072
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
12073
0
      Value |= (op & UINT64_C(16)) << 18;
12074
0
      Value |= (op & UINT64_C(15)) << 12;
12075
      // op: Rn
12076
0
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
12077
0
      op &= UINT64_C(15);
12078
0
      op <<= 16;
12079
0
      Value |= op;
12080
      // op: Rm
12081
0
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
12082
0
      op &= UINT64_C(15);
12083
0
      Value |= op;
12084
      // op: lane
12085
0
      op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI);
12086
0
      op &= UINT64_C(7);
12087
0
      op <<= 5;
12088
0
      Value |= op;
12089
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
12090
0
      break;
12091
0
    }
12092
0
    case ARM::VST1LNd32_UPD: {
12093
      // op: Vd
12094
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
12095
0
      Value |= (op & UINT64_C(16)) << 18;
12096
0
      Value |= (op & UINT64_C(15)) << 12;
12097
      // op: Rn
12098
0
      op = getAddrMode6OneLane32AddressOpValue(MI, 1, Fixups, STI);
12099
0
      Value |= (op & UINT64_C(15)) << 16;
12100
0
      Value |= (op & UINT64_C(48));
12101
      // op: Rm
12102
0
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
12103
0
      op &= UINT64_C(15);
12104
0
      Value |= op;
12105
      // op: lane
12106
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
12107
0
      op &= UINT64_C(1);
12108
0
      op <<= 7;
12109
0
      Value |= op;
12110
0
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
12111
0
      break;
12112
0
    }
12113
0
    case ARM::LDC2L_OFFSET:
12114
0
    case ARM::LDC2L_PRE:
12115
0
    case ARM::LDC2_OFFSET:
12116
0
    case ARM::LDC2_PRE:
12117
0
    case ARM::STC2L_OFFSET:
12118
0
    case ARM::STC2L_PRE:
12119
0
    case ARM::STC2_OFFSET:
12120
0
    case ARM::STC2_PRE:
12121
0
    case ARM::t2LDC2L_OFFSET:
12122
0
    case ARM::t2LDC2L_PRE:
12123
0
    case ARM::t2LDC2_OFFSET:
12124
0
    case ARM::t2LDC2_PRE:
12125
0
    case ARM::t2LDCL_OFFSET:
12126
0
    case ARM::t2LDCL_PRE:
12127
0
    case ARM::t2LDC_OFFSET:
12128
0
    case ARM::t2LDC_PRE:
12129
0
    case ARM::t2STC2L_OFFSET:
12130
0
    case ARM::t2STC2L_PRE:
12131
0
    case ARM::t2STC2_OFFSET:
12132
0
    case ARM::t2STC2_PRE:
12133
0
    case ARM::t2STCL_OFFSET:
12134
0
    case ARM::t2STCL_PRE:
12135
0
    case ARM::t2STC_OFFSET:
12136
0
    case ARM::t2STC_PRE: {
12137
      // op: addr
12138
0
      op = getAddrMode5OpValue(MI, 2, Fixups, STI);
12139
0
      Value |= (op & UINT64_C(256)) << 15;
12140
0
      Value |= (op & UINT64_C(7680)) << 7;
12141
0
      Value |= (op & UINT64_C(255));
12142
      // op: cop
12143
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12144
0
      op &= UINT64_C(15);
12145
0
      op <<= 8;
12146
0
      Value |= op;
12147
      // op: CRd
12148
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12149
0
      op &= UINT64_C(15);
12150
0
      op <<= 12;
12151
0
      Value |= op;
12152
0
      break;
12153
0
    }
12154
0
    case ARM::t2PLDWi12:
12155
0
    case ARM::t2PLDi12:
12156
0
    case ARM::t2PLIi12: {
12157
      // op: addr
12158
0
      op = getAddrModeImm12OpValue(MI, 0, Fixups, STI);
12159
0
      Value |= (op & UINT64_C(122880)) << 3;
12160
0
      Value |= (op & UINT64_C(4095));
12161
0
      break;
12162
0
    }
12163
0
    case ARM::PLDWi12:
12164
0
    case ARM::PLDi12:
12165
0
    case ARM::PLIi12: {
12166
      // op: addr
12167
0
      op = getAddrModeImm12OpValue(MI, 0, Fixups, STI);
12168
0
      Value |= (op & UINT64_C(4096)) << 11;
12169
0
      Value |= (op & UINT64_C(122880)) << 3;
12170
0
      Value |= (op & UINT64_C(4095));
12171
0
      break;
12172
0
    }
12173
0
    case ARM::t2PLDpci:
12174
0
    case ARM::t2PLIpci: {
12175
      // op: addr
12176
0
      op = getAddrModeImm12OpValue(MI, 0, Fixups, STI);
12177
0
      Value |= (op & UINT64_C(4096)) << 11;
12178
0
      Value |= (op & UINT64_C(4095));
12179
0
      break;
12180
0
    }
12181
0
    case ARM::t2LDAEXB:
12182
0
    case ARM::t2LDAEXH:
12183
0
    case ARM::t2LDREXB:
12184
0
    case ARM::t2LDREXH: {
12185
      // op: addr
12186
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12187
0
      op &= UINT64_C(15);
12188
0
      op <<= 16;
12189
0
      Value |= op;
12190
      // op: Rt
12191
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12192
0
      op &= UINT64_C(15);
12193
0
      op <<= 12;
12194
0
      Value |= op;
12195
0
      break;
12196
0
    }
12197
0
    case ARM::t2LDAEXD:
12198
0
    case ARM::t2LDREXD: {
12199
      // op: addr
12200
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12201
0
      op &= UINT64_C(15);
12202
0
      op <<= 16;
12203
0
      Value |= op;
12204
      // op: Rt
12205
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12206
0
      op &= UINT64_C(15);
12207
0
      op <<= 12;
12208
0
      Value |= op;
12209
      // op: Rt2
12210
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12211
0
      op &= UINT64_C(15);
12212
0
      op <<= 8;
12213
0
      Value |= op;
12214
0
      break;
12215
0
    }
12216
0
    case ARM::t2PLDWi8:
12217
0
    case ARM::t2PLDi8:
12218
0
    case ARM::t2PLIi8: {
12219
      // op: addr
12220
0
      op = getT2AddrModeImmOpValue<8,0>(MI, 0, Fixups, STI);
12221
0
      Value |= (op & UINT64_C(7680)) << 7;
12222
0
      Value |= (op & UINT64_C(255));
12223
0
      break;
12224
0
    }
12225
0
    case ARM::t2PLDWs:
12226
0
    case ARM::t2PLDs:
12227
0
    case ARM::t2PLIs: {
12228
      // op: addr
12229
0
      op = getT2AddrModeSORegOpValue(MI, 0, Fixups, STI);
12230
0
      Value |= (op & UINT64_C(960)) << 10;
12231
0
      Value |= (op & UINT64_C(3)) << 4;
12232
0
      Value |= (op & UINT64_C(60)) >> 2;
12233
0
      break;
12234
0
    }
12235
0
    case ARM::t2BFLr:
12236
0
    case ARM::t2BFr: {
12237
      // op: b_label
12238
0
      op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, 0, Fixups, STI);
12239
0
      op &= UINT64_C(15);
12240
0
      op <<= 23;
12241
0
      Value |= op;
12242
      // op: Rn
12243
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12244
0
      op &= UINT64_C(15);
12245
0
      op <<= 16;
12246
0
      Value |= op;
12247
0
      break;
12248
0
    }
12249
0
    case ARM::t2BFi: {
12250
      // op: b_label
12251
0
      op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, 0, Fixups, STI);
12252
0
      op &= UINT64_C(15);
12253
0
      op <<= 23;
12254
0
      Value |= op;
12255
      // op: label
12256
0
      op = getBFTargetOpValue<false, ARM::fixup_bf_target>(MI, 1, Fixups, STI);
12257
0
      Value |= (op & UINT64_C(63488)) << 5;
12258
0
      Value |= (op & UINT64_C(1)) << 11;
12259
0
      Value |= (op & UINT64_C(2046));
12260
0
      break;
12261
0
    }
12262
0
    case ARM::t2BFLi: {
12263
      // op: b_label
12264
0
      op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, 0, Fixups, STI);
12265
0
      op &= UINT64_C(15);
12266
0
      op <<= 23;
12267
0
      Value |= op;
12268
      // op: label
12269
0
      op = getBFTargetOpValue<false, ARM::fixup_bfl_target>(MI, 1, Fixups, STI);
12270
0
      Value |= (op & UINT64_C(260096)) << 5;
12271
0
      Value |= (op & UINT64_C(1)) << 11;
12272
0
      Value |= (op & UINT64_C(2046));
12273
0
      break;
12274
0
    }
12275
0
    case ARM::t2MSRbanked: {
12276
      // op: banked
12277
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12278
0
      Value |= (op & UINT64_C(32)) << 15;
12279
0
      Value |= (op & UINT64_C(15)) << 8;
12280
0
      Value |= (op & UINT64_C(16));
12281
      // op: Rn
12282
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12283
0
      op &= UINT64_C(15);
12284
0
      op <<= 16;
12285
0
      Value |= op;
12286
0
      break;
12287
0
    }
12288
0
    case ARM::t2MRSbanked: {
12289
      // op: banked
12290
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12291
0
      Value |= (op & UINT64_C(32)) << 15;
12292
0
      Value |= (op & UINT64_C(15)) << 16;
12293
0
      Value |= (op & UINT64_C(16));
12294
      // op: Rd
12295
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12296
0
      op &= UINT64_C(15);
12297
0
      op <<= 8;
12298
0
      Value |= op;
12299
0
      break;
12300
0
    }
12301
0
    case ARM::t2BFic: {
12302
      // op: bcond
12303
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12304
0
      op &= UINT64_C(15);
12305
0
      op <<= 18;
12306
0
      Value |= op;
12307
      // op: label
12308
0
      op = getBFTargetOpValue<false, ARM::fixup_bfc_target>(MI, 1, Fixups, STI);
12309
0
      Value |= (op & UINT64_C(2048)) << 5;
12310
0
      Value |= (op & UINT64_C(1)) << 11;
12311
0
      Value |= (op & UINT64_C(2046));
12312
      // op: ba_label
12313
0
      op = getBFAfterTargetOpValue(MI, 2, Fixups, STI);
12314
0
      op &= UINT64_C(1);
12315
0
      op <<= 17;
12316
0
      Value |= op;
12317
      // op: b_label
12318
0
      op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, 0, Fixups, STI);
12319
0
      op &= UINT64_C(15);
12320
0
      op <<= 23;
12321
0
      Value |= op;
12322
0
      break;
12323
0
    }
12324
0
    case ARM::t2IT: {
12325
      // op: cc
12326
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12327
0
      op &= UINT64_C(15);
12328
0
      op <<= 4;
12329
0
      Value |= op;
12330
      // op: mask
12331
0
      op = getITMaskOpValue(MI, 1, Fixups, STI);
12332
0
      op &= UINT64_C(15);
12333
0
      Value |= op;
12334
0
      break;
12335
0
    }
12336
0
    case ARM::CDE_VCX1_fpsp: {
12337
      // op: coproc
12338
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12339
0
      op &= UINT64_C(7);
12340
0
      op <<= 8;
12341
0
      Value |= op;
12342
      // op: imm
12343
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12344
0
      Value |= (op & UINT64_C(1920)) << 9;
12345
0
      Value |= (op & UINT64_C(64)) << 1;
12346
0
      Value |= (op & UINT64_C(63));
12347
      // op: Vd
12348
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12349
0
      Value |= (op & UINT64_C(1)) << 22;
12350
0
      Value |= (op & UINT64_C(30)) << 11;
12351
0
      break;
12352
0
    }
12353
0
    case ARM::CDE_VCX1_fpdp: {
12354
      // op: coproc
12355
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12356
0
      op &= UINT64_C(7);
12357
0
      op <<= 8;
12358
0
      Value |= op;
12359
      // op: imm
12360
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12361
0
      Value |= (op & UINT64_C(1920)) << 9;
12362
0
      Value |= (op & UINT64_C(64)) << 1;
12363
0
      Value |= (op & UINT64_C(63));
12364
      // op: Vd
12365
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12366
0
      Value |= (op & UINT64_C(16)) << 18;
12367
0
      Value |= (op & UINT64_C(15)) << 12;
12368
0
      break;
12369
0
    }
12370
0
    case ARM::CDE_VCX1_vec: {
12371
      // op: coproc
12372
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12373
0
      op &= UINT64_C(7);
12374
0
      op <<= 8;
12375
0
      Value |= op;
12376
      // op: imm
12377
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12378
0
      Value |= (op & UINT64_C(2048)) << 13;
12379
0
      Value |= (op & UINT64_C(1920)) << 9;
12380
0
      Value |= (op & UINT64_C(64)) << 1;
12381
0
      Value |= (op & UINT64_C(63));
12382
      // op: Qd
12383
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12384
0
      op &= UINT64_C(7);
12385
0
      op <<= 13;
12386
0
      Value |= op;
12387
0
      break;
12388
0
    }
12389
0
    case ARM::CDE_CX1:
12390
0
    case ARM::CDE_CX1D: {
12391
      // op: coproc
12392
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12393
0
      op &= UINT64_C(7);
12394
0
      op <<= 8;
12395
0
      Value |= op;
12396
      // op: imm
12397
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12398
0
      Value |= (op & UINT64_C(8064)) << 9;
12399
0
      Value |= (op & UINT64_C(64)) << 1;
12400
0
      Value |= (op & UINT64_C(63));
12401
      // op: Rd
12402
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12403
0
      op &= UINT64_C(15);
12404
0
      op <<= 12;
12405
0
      Value |= op;
12406
0
      break;
12407
0
    }
12408
0
    case ARM::CDE_VCX1A_fpsp: {
12409
      // op: coproc
12410
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12411
0
      op &= UINT64_C(7);
12412
0
      op <<= 8;
12413
0
      Value |= op;
12414
      // op: imm
12415
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12416
0
      Value |= (op & UINT64_C(1920)) << 9;
12417
0
      Value |= (op & UINT64_C(64)) << 1;
12418
0
      Value |= (op & UINT64_C(63));
12419
      // op: Vd
12420
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12421
0
      Value |= (op & UINT64_C(1)) << 22;
12422
0
      Value |= (op & UINT64_C(30)) << 11;
12423
0
      break;
12424
0
    }
12425
0
    case ARM::CDE_VCX1A_fpdp: {
12426
      // op: coproc
12427
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12428
0
      op &= UINT64_C(7);
12429
0
      op <<= 8;
12430
0
      Value |= op;
12431
      // op: imm
12432
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12433
0
      Value |= (op & UINT64_C(1920)) << 9;
12434
0
      Value |= (op & UINT64_C(64)) << 1;
12435
0
      Value |= (op & UINT64_C(63));
12436
      // op: Vd
12437
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12438
0
      Value |= (op & UINT64_C(16)) << 18;
12439
0
      Value |= (op & UINT64_C(15)) << 12;
12440
0
      break;
12441
0
    }
12442
0
    case ARM::CDE_VCX1A_vec: {
12443
      // op: coproc
12444
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12445
0
      op &= UINT64_C(7);
12446
0
      op <<= 8;
12447
0
      Value |= op;
12448
      // op: imm
12449
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12450
0
      Value |= (op & UINT64_C(2048)) << 13;
12451
0
      Value |= (op & UINT64_C(1920)) << 9;
12452
0
      Value |= (op & UINT64_C(64)) << 1;
12453
0
      Value |= (op & UINT64_C(63));
12454
      // op: Qd
12455
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12456
0
      op &= UINT64_C(7);
12457
0
      op <<= 13;
12458
0
      Value |= op;
12459
0
      break;
12460
0
    }
12461
0
    case ARM::CDE_CX2:
12462
0
    case ARM::CDE_CX2D: {
12463
      // op: coproc
12464
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12465
0
      op &= UINT64_C(7);
12466
0
      op <<= 8;
12467
0
      Value |= op;
12468
      // op: imm
12469
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12470
0
      Value |= (op & UINT64_C(384)) << 13;
12471
0
      Value |= (op & UINT64_C(64)) << 1;
12472
0
      Value |= (op & UINT64_C(63));
12473
      // op: Rd
12474
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12475
0
      op &= UINT64_C(15);
12476
0
      op <<= 12;
12477
0
      Value |= op;
12478
      // op: Rn
12479
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12480
0
      op &= UINT64_C(15);
12481
0
      op <<= 16;
12482
0
      Value |= op;
12483
0
      break;
12484
0
    }
12485
0
    case ARM::CDE_VCX2_fpsp: {
12486
      // op: coproc
12487
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12488
0
      op &= UINT64_C(7);
12489
0
      op <<= 8;
12490
0
      Value |= op;
12491
      // op: imm
12492
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12493
0
      Value |= (op & UINT64_C(60)) << 14;
12494
0
      Value |= (op & UINT64_C(2)) << 6;
12495
0
      Value |= (op & UINT64_C(1)) << 4;
12496
      // op: Vd
12497
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12498
0
      Value |= (op & UINT64_C(1)) << 22;
12499
0
      Value |= (op & UINT64_C(30)) << 11;
12500
      // op: Vm
12501
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12502
0
      Value |= (op & UINT64_C(1)) << 5;
12503
0
      Value |= (op & UINT64_C(30)) >> 1;
12504
0
      break;
12505
0
    }
12506
0
    case ARM::CDE_VCX2_fpdp: {
12507
      // op: coproc
12508
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12509
0
      op &= UINT64_C(7);
12510
0
      op <<= 8;
12511
0
      Value |= op;
12512
      // op: imm
12513
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12514
0
      Value |= (op & UINT64_C(60)) << 14;
12515
0
      Value |= (op & UINT64_C(2)) << 6;
12516
0
      Value |= (op & UINT64_C(1)) << 4;
12517
      // op: Vd
12518
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12519
0
      Value |= (op & UINT64_C(16)) << 18;
12520
0
      Value |= (op & UINT64_C(15)) << 12;
12521
      // op: Vm
12522
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12523
0
      Value |= (op & UINT64_C(16)) << 1;
12524
0
      Value |= (op & UINT64_C(15));
12525
0
      break;
12526
0
    }
12527
0
    case ARM::CDE_VCX2_vec: {
12528
      // op: coproc
12529
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12530
0
      op &= UINT64_C(7);
12531
0
      op <<= 8;
12532
0
      Value |= op;
12533
      // op: imm
12534
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12535
0
      Value |= (op & UINT64_C(64)) << 18;
12536
0
      Value |= (op & UINT64_C(60)) << 14;
12537
0
      Value |= (op & UINT64_C(2)) << 6;
12538
0
      Value |= (op & UINT64_C(1)) << 4;
12539
      // op: Qd
12540
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12541
0
      op &= UINT64_C(7);
12542
0
      op <<= 13;
12543
0
      Value |= op;
12544
      // op: Qm
12545
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12546
0
      op &= UINT64_C(7);
12547
0
      op <<= 1;
12548
0
      Value |= op;
12549
0
      break;
12550
0
    }
12551
0
    case ARM::CDE_CX1A:
12552
0
    case ARM::CDE_CX1DA: {
12553
      // op: coproc
12554
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12555
0
      op &= UINT64_C(7);
12556
0
      op <<= 8;
12557
0
      Value |= op;
12558
      // op: imm
12559
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12560
0
      Value |= (op & UINT64_C(8064)) << 9;
12561
0
      Value |= (op & UINT64_C(64)) << 1;
12562
0
      Value |= (op & UINT64_C(63));
12563
      // op: Rd
12564
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12565
0
      op &= UINT64_C(15);
12566
0
      op <<= 12;
12567
0
      Value |= op;
12568
0
      break;
12569
0
    }
12570
0
    case ARM::CDE_CX2A:
12571
0
    case ARM::CDE_CX2DA: {
12572
      // op: coproc
12573
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12574
0
      op &= UINT64_C(7);
12575
0
      op <<= 8;
12576
0
      Value |= op;
12577
      // op: imm
12578
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
12579
0
      Value |= (op & UINT64_C(384)) << 13;
12580
0
      Value |= (op & UINT64_C(64)) << 1;
12581
0
      Value |= (op & UINT64_C(63));
12582
      // op: Rd
12583
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12584
0
      op &= UINT64_C(15);
12585
0
      op <<= 12;
12586
0
      Value |= op;
12587
      // op: Rn
12588
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12589
0
      op &= UINT64_C(15);
12590
0
      op <<= 16;
12591
0
      Value |= op;
12592
0
      break;
12593
0
    }
12594
0
    case ARM::CDE_CX3:
12595
0
    case ARM::CDE_CX3D: {
12596
      // op: coproc
12597
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12598
0
      op &= UINT64_C(7);
12599
0
      op <<= 8;
12600
0
      Value |= op;
12601
      // op: imm
12602
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
12603
0
      Value |= (op & UINT64_C(56)) << 17;
12604
0
      Value |= (op & UINT64_C(4)) << 5;
12605
0
      Value |= (op & UINT64_C(3)) << 4;
12606
      // op: Rd
12607
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12608
0
      op &= UINT64_C(15);
12609
0
      Value |= op;
12610
      // op: Rn
12611
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12612
0
      op &= UINT64_C(15);
12613
0
      op <<= 16;
12614
0
      Value |= op;
12615
      // op: Rm
12616
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12617
0
      op &= UINT64_C(15);
12618
0
      op <<= 12;
12619
0
      Value |= op;
12620
0
      break;
12621
0
    }
12622
0
    case ARM::CDE_VCX3_fpsp: {
12623
      // op: coproc
12624
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12625
0
      op &= UINT64_C(7);
12626
0
      op <<= 8;
12627
0
      Value |= op;
12628
      // op: imm
12629
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
12630
0
      Value |= (op & UINT64_C(6)) << 19;
12631
0
      Value |= (op & UINT64_C(1)) << 4;
12632
      // op: Vd
12633
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12634
0
      Value |= (op & UINT64_C(1)) << 22;
12635
0
      Value |= (op & UINT64_C(30)) << 11;
12636
      // op: Vm
12637
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12638
0
      Value |= (op & UINT64_C(1)) << 5;
12639
0
      Value |= (op & UINT64_C(30)) >> 1;
12640
      // op: Vn
12641
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12642
0
      Value |= (op & UINT64_C(30)) << 15;
12643
0
      Value |= (op & UINT64_C(1)) << 7;
12644
0
      break;
12645
0
    }
12646
0
    case ARM::CDE_VCX3_fpdp: {
12647
      // op: coproc
12648
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12649
0
      op &= UINT64_C(7);
12650
0
      op <<= 8;
12651
0
      Value |= op;
12652
      // op: imm
12653
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
12654
0
      Value |= (op & UINT64_C(6)) << 19;
12655
0
      Value |= (op & UINT64_C(1)) << 4;
12656
      // op: Vd
12657
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12658
0
      Value |= (op & UINT64_C(16)) << 18;
12659
0
      Value |= (op & UINT64_C(15)) << 12;
12660
      // op: Vm
12661
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12662
0
      Value |= (op & UINT64_C(16)) << 1;
12663
0
      Value |= (op & UINT64_C(15));
12664
      // op: Vn
12665
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12666
0
      Value |= (op & UINT64_C(15)) << 16;
12667
0
      Value |= (op & UINT64_C(16)) << 3;
12668
0
      break;
12669
0
    }
12670
0
    case ARM::CDE_VCX2A_fpsp: {
12671
      // op: coproc
12672
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12673
0
      op &= UINT64_C(7);
12674
0
      op <<= 8;
12675
0
      Value |= op;
12676
      // op: imm
12677
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
12678
0
      Value |= (op & UINT64_C(60)) << 14;
12679
0
      Value |= (op & UINT64_C(2)) << 6;
12680
0
      Value |= (op & UINT64_C(1)) << 4;
12681
      // op: Vd
12682
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12683
0
      Value |= (op & UINT64_C(1)) << 22;
12684
0
      Value |= (op & UINT64_C(30)) << 11;
12685
      // op: Vm
12686
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12687
0
      Value |= (op & UINT64_C(1)) << 5;
12688
0
      Value |= (op & UINT64_C(30)) >> 1;
12689
0
      break;
12690
0
    }
12691
0
    case ARM::CDE_VCX2A_fpdp: {
12692
      // op: coproc
12693
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12694
0
      op &= UINT64_C(7);
12695
0
      op <<= 8;
12696
0
      Value |= op;
12697
      // op: imm
12698
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
12699
0
      Value |= (op & UINT64_C(60)) << 14;
12700
0
      Value |= (op & UINT64_C(2)) << 6;
12701
0
      Value |= (op & UINT64_C(1)) << 4;
12702
      // op: Vd
12703
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12704
0
      Value |= (op & UINT64_C(16)) << 18;
12705
0
      Value |= (op & UINT64_C(15)) << 12;
12706
      // op: Vm
12707
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12708
0
      Value |= (op & UINT64_C(16)) << 1;
12709
0
      Value |= (op & UINT64_C(15));
12710
0
      break;
12711
0
    }
12712
0
    case ARM::CDE_VCX2A_vec: {
12713
      // op: coproc
12714
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12715
0
      op &= UINT64_C(7);
12716
0
      op <<= 8;
12717
0
      Value |= op;
12718
      // op: imm
12719
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
12720
0
      Value |= (op & UINT64_C(64)) << 18;
12721
0
      Value |= (op & UINT64_C(60)) << 14;
12722
0
      Value |= (op & UINT64_C(2)) << 6;
12723
0
      Value |= (op & UINT64_C(1)) << 4;
12724
      // op: Qd
12725
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12726
0
      op &= UINT64_C(7);
12727
0
      op <<= 13;
12728
0
      Value |= op;
12729
      // op: Qm
12730
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12731
0
      op &= UINT64_C(7);
12732
0
      op <<= 1;
12733
0
      Value |= op;
12734
0
      break;
12735
0
    }
12736
0
    case ARM::CDE_VCX3_vec: {
12737
      // op: coproc
12738
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12739
0
      op &= UINT64_C(7);
12740
0
      op <<= 8;
12741
0
      Value |= op;
12742
      // op: imm
12743
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
12744
0
      Value |= (op & UINT64_C(8)) << 21;
12745
0
      Value |= (op & UINT64_C(6)) << 19;
12746
0
      Value |= (op & UINT64_C(1)) << 4;
12747
      // op: Qd
12748
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12749
0
      op &= UINT64_C(7);
12750
0
      op <<= 13;
12751
0
      Value |= op;
12752
      // op: Qm
12753
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12754
0
      op &= UINT64_C(7);
12755
0
      op <<= 1;
12756
0
      Value |= op;
12757
      // op: Qn
12758
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12759
0
      op &= UINT64_C(7);
12760
0
      op <<= 17;
12761
0
      Value |= op;
12762
0
      break;
12763
0
    }
12764
0
    case ARM::CDE_CX3A:
12765
0
    case ARM::CDE_CX3DA: {
12766
      // op: coproc
12767
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12768
0
      op &= UINT64_C(7);
12769
0
      op <<= 8;
12770
0
      Value |= op;
12771
      // op: imm
12772
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
12773
0
      Value |= (op & UINT64_C(56)) << 17;
12774
0
      Value |= (op & UINT64_C(4)) << 5;
12775
0
      Value |= (op & UINT64_C(3)) << 4;
12776
      // op: Rd
12777
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12778
0
      op &= UINT64_C(15);
12779
0
      Value |= op;
12780
      // op: Rn
12781
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12782
0
      op &= UINT64_C(15);
12783
0
      op <<= 16;
12784
0
      Value |= op;
12785
      // op: Rm
12786
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
12787
0
      op &= UINT64_C(15);
12788
0
      op <<= 12;
12789
0
      Value |= op;
12790
0
      break;
12791
0
    }
12792
0
    case ARM::CDE_VCX3A_fpsp: {
12793
      // op: coproc
12794
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12795
0
      op &= UINT64_C(7);
12796
0
      op <<= 8;
12797
0
      Value |= op;
12798
      // op: imm
12799
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
12800
0
      Value |= (op & UINT64_C(6)) << 19;
12801
0
      Value |= (op & UINT64_C(1)) << 4;
12802
      // op: Vd
12803
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12804
0
      Value |= (op & UINT64_C(1)) << 22;
12805
0
      Value |= (op & UINT64_C(30)) << 11;
12806
      // op: Vm
12807
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
12808
0
      Value |= (op & UINT64_C(1)) << 5;
12809
0
      Value |= (op & UINT64_C(30)) >> 1;
12810
      // op: Vn
12811
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12812
0
      Value |= (op & UINT64_C(30)) << 15;
12813
0
      Value |= (op & UINT64_C(1)) << 7;
12814
0
      break;
12815
0
    }
12816
0
    case ARM::CDE_VCX3A_fpdp: {
12817
      // op: coproc
12818
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12819
0
      op &= UINT64_C(7);
12820
0
      op <<= 8;
12821
0
      Value |= op;
12822
      // op: imm
12823
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
12824
0
      Value |= (op & UINT64_C(6)) << 19;
12825
0
      Value |= (op & UINT64_C(1)) << 4;
12826
      // op: Vd
12827
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12828
0
      Value |= (op & UINT64_C(16)) << 18;
12829
0
      Value |= (op & UINT64_C(15)) << 12;
12830
      // op: Vm
12831
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
12832
0
      Value |= (op & UINT64_C(16)) << 1;
12833
0
      Value |= (op & UINT64_C(15));
12834
      // op: Vn
12835
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12836
0
      Value |= (op & UINT64_C(15)) << 16;
12837
0
      Value |= (op & UINT64_C(16)) << 3;
12838
0
      break;
12839
0
    }
12840
0
    case ARM::CDE_VCX3A_vec: {
12841
      // op: coproc
12842
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12843
0
      op &= UINT64_C(7);
12844
0
      op <<= 8;
12845
0
      Value |= op;
12846
      // op: imm
12847
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
12848
0
      Value |= (op & UINT64_C(8)) << 21;
12849
0
      Value |= (op & UINT64_C(6)) << 19;
12850
0
      Value |= (op & UINT64_C(1)) << 4;
12851
      // op: Qd
12852
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12853
0
      op &= UINT64_C(7);
12854
0
      op <<= 13;
12855
0
      Value |= op;
12856
      // op: Qm
12857
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
12858
0
      op &= UINT64_C(7);
12859
0
      op <<= 1;
12860
0
      Value |= op;
12861
      // op: Qn
12862
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12863
0
      op &= UINT64_C(7);
12864
0
      op <<= 17;
12865
0
      Value |= op;
12866
0
      break;
12867
0
    }
12868
0
    case ARM::BX: {
12869
      // op: dst
12870
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12871
0
      op &= UINT64_C(15);
12872
0
      Value |= op;
12873
0
      break;
12874
0
    }
12875
0
    case ARM::tPICADD: {
12876
      // op: dst
12877
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12878
0
      op &= UINT64_C(7);
12879
0
      Value |= op;
12880
0
      break;
12881
0
    }
12882
0
    case ARM::tADDrSPi: {
12883
      // op: dst
12884
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12885
0
      op &= UINT64_C(7);
12886
0
      op <<= 8;
12887
0
      Value |= op;
12888
      // op: imm
12889
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12890
0
      op &= UINT64_C(255);
12891
0
      Value |= op;
12892
0
      break;
12893
0
    }
12894
0
    case ARM::tSETEND: {
12895
      // op: end
12896
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12897
0
      op &= UINT64_C(1);
12898
0
      op <<= 3;
12899
0
      Value |= op;
12900
0
      break;
12901
0
    }
12902
0
    case ARM::SETEND: {
12903
      // op: end
12904
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12905
0
      op &= UINT64_C(1);
12906
0
      op <<= 9;
12907
0
      Value |= op;
12908
0
      break;
12909
0
    }
12910
0
    case ARM::MVE_VPTv4s32r:
12911
0
    case ARM::MVE_VPTv8s16r:
12912
0
    case ARM::MVE_VPTv16s8r: {
12913
      // op: fc
12914
0
      op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI);
12915
0
      Value |= (op & UINT64_C(1)) << 7;
12916
0
      Value |= (op & UINT64_C(2)) << 4;
12917
      // op: Mk
12918
0
      op = getVPTMaskOpValue(MI, 0, Fixups, STI);
12919
0
      Value |= (op & UINT64_C(8)) << 19;
12920
0
      Value |= (op & UINT64_C(7)) << 13;
12921
      // op: Qn
12922
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12923
0
      op &= UINT64_C(7);
12924
0
      op <<= 17;
12925
0
      Value |= op;
12926
      // op: Rm
12927
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12928
0
      op &= UINT64_C(15);
12929
0
      Value |= op;
12930
0
      break;
12931
0
    }
12932
0
    case ARM::MVE_VCMPs8r:
12933
0
    case ARM::MVE_VCMPs16r:
12934
0
    case ARM::MVE_VCMPs32r: {
12935
      // op: fc
12936
0
      op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI);
12937
0
      Value |= (op & UINT64_C(1)) << 7;
12938
0
      Value |= (op & UINT64_C(2)) << 4;
12939
      // op: Qn
12940
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12941
0
      op &= UINT64_C(7);
12942
0
      op <<= 17;
12943
0
      Value |= op;
12944
      // op: Rm
12945
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12946
0
      op &= UINT64_C(15);
12947
0
      Value |= op;
12948
0
      break;
12949
0
    }
12950
0
    case ARM::MVE_VPTv4s32:
12951
0
    case ARM::MVE_VPTv8s16:
12952
0
    case ARM::MVE_VPTv16s8: {
12953
      // op: fc
12954
0
      op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI);
12955
0
      Value |= (op & UINT64_C(1)) << 7;
12956
0
      Value |= (op & UINT64_C(2)) >> 1;
12957
      // op: Mk
12958
0
      op = getVPTMaskOpValue(MI, 0, Fixups, STI);
12959
0
      Value |= (op & UINT64_C(8)) << 19;
12960
0
      Value |= (op & UINT64_C(7)) << 13;
12961
      // op: Qn
12962
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12963
0
      op &= UINT64_C(7);
12964
0
      op <<= 17;
12965
0
      Value |= op;
12966
      // op: Qm
12967
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12968
0
      Value |= (op & UINT64_C(8)) << 2;
12969
0
      Value |= (op & UINT64_C(7)) << 1;
12970
0
      break;
12971
0
    }
12972
0
    case ARM::MVE_VCMPs8:
12973
0
    case ARM::MVE_VCMPs16:
12974
0
    case ARM::MVE_VCMPs32: {
12975
      // op: fc
12976
0
      op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI);
12977
0
      Value |= (op & UINT64_C(1)) << 7;
12978
0
      Value |= (op & UINT64_C(2)) >> 1;
12979
      // op: Qn
12980
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12981
0
      op &= UINT64_C(7);
12982
0
      op <<= 17;
12983
0
      Value |= op;
12984
      // op: Qm
12985
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12986
0
      Value |= (op & UINT64_C(8)) << 2;
12987
0
      Value |= (op & UINT64_C(7)) << 1;
12988
0
      break;
12989
0
    }
12990
0
    case ARM::MVE_VPTv4f32r:
12991
0
    case ARM::MVE_VPTv8f16r: {
12992
      // op: fc
12993
0
      op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI);
12994
0
      Value |= (op & UINT64_C(4)) << 10;
12995
0
      Value |= (op & UINT64_C(1)) << 7;
12996
0
      Value |= (op & UINT64_C(2)) << 4;
12997
      // op: Mk
12998
0
      op = getVPTMaskOpValue(MI, 0, Fixups, STI);
12999
0
      Value |= (op & UINT64_C(8)) << 19;
13000
0
      Value |= (op & UINT64_C(7)) << 13;
13001
      // op: Qn
13002
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13003
0
      op &= UINT64_C(7);
13004
0
      op <<= 17;
13005
0
      Value |= op;
13006
      // op: Rm
13007
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13008
0
      op &= UINT64_C(15);
13009
0
      Value |= op;
13010
0
      break;
13011
0
    }
13012
0
    case ARM::MVE_VCMPf16r:
13013
0
    case ARM::MVE_VCMPf32r: {
13014
      // op: fc
13015
0
      op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI);
13016
0
      Value |= (op & UINT64_C(4)) << 10;
13017
0
      Value |= (op & UINT64_C(1)) << 7;
13018
0
      Value |= (op & UINT64_C(2)) << 4;
13019
      // op: Qn
13020
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13021
0
      op &= UINT64_C(7);
13022
0
      op <<= 17;
13023
0
      Value |= op;
13024
      // op: Rm
13025
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13026
0
      op &= UINT64_C(15);
13027
0
      Value |= op;
13028
0
      break;
13029
0
    }
13030
0
    case ARM::MVE_VPTv4f32:
13031
0
    case ARM::MVE_VPTv8f16: {
13032
      // op: fc
13033
0
      op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI);
13034
0
      Value |= (op & UINT64_C(4)) << 10;
13035
0
      Value |= (op & UINT64_C(1)) << 7;
13036
0
      Value |= (op & UINT64_C(2)) >> 1;
13037
      // op: Mk
13038
0
      op = getVPTMaskOpValue(MI, 0, Fixups, STI);
13039
0
      Value |= (op & UINT64_C(8)) << 19;
13040
0
      Value |= (op & UINT64_C(7)) << 13;
13041
      // op: Qn
13042
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13043
0
      op &= UINT64_C(7);
13044
0
      op <<= 17;
13045
0
      Value |= op;
13046
      // op: Qm
13047
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13048
0
      Value |= (op & UINT64_C(8)) << 2;
13049
0
      Value |= (op & UINT64_C(7)) << 1;
13050
0
      break;
13051
0
    }
13052
0
    case ARM::MVE_VCMPf16:
13053
0
    case ARM::MVE_VCMPf32: {
13054
      // op: fc
13055
0
      op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI);
13056
0
      Value |= (op & UINT64_C(4)) << 10;
13057
0
      Value |= (op & UINT64_C(1)) << 7;
13058
0
      Value |= (op & UINT64_C(2)) >> 1;
13059
      // op: Qn
13060
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13061
0
      op &= UINT64_C(7);
13062
0
      op <<= 17;
13063
0
      Value |= op;
13064
      // op: Qm
13065
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13066
0
      Value |= (op & UINT64_C(8)) << 2;
13067
0
      Value |= (op & UINT64_C(7)) << 1;
13068
0
      break;
13069
0
    }
13070
0
    case ARM::MVE_VPTv4i32:
13071
0
    case ARM::MVE_VPTv4u32:
13072
0
    case ARM::MVE_VPTv8i16:
13073
0
    case ARM::MVE_VPTv8u16:
13074
0
    case ARM::MVE_VPTv16i8:
13075
0
    case ARM::MVE_VPTv16u8: {
13076
      // op: fc
13077
0
      op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI);
13078
0
      op &= UINT64_C(1);
13079
0
      op <<= 7;
13080
0
      Value |= op;
13081
      // op: Mk
13082
0
      op = getVPTMaskOpValue(MI, 0, Fixups, STI);
13083
0
      Value |= (op & UINT64_C(8)) << 19;
13084
0
      Value |= (op & UINT64_C(7)) << 13;
13085
      // op: Qn
13086
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13087
0
      op &= UINT64_C(7);
13088
0
      op <<= 17;
13089
0
      Value |= op;
13090
      // op: Qm
13091
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13092
0
      Value |= (op & UINT64_C(8)) << 2;
13093
0
      Value |= (op & UINT64_C(7)) << 1;
13094
0
      break;
13095
0
    }
13096
0
    case ARM::MVE_VPTv4i32r:
13097
0
    case ARM::MVE_VPTv4u32r:
13098
0
    case ARM::MVE_VPTv8i16r:
13099
0
    case ARM::MVE_VPTv8u16r:
13100
0
    case ARM::MVE_VPTv16i8r:
13101
0
    case ARM::MVE_VPTv16u8r: {
13102
      // op: fc
13103
0
      op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI);
13104
0
      op &= UINT64_C(1);
13105
0
      op <<= 7;
13106
0
      Value |= op;
13107
      // op: Mk
13108
0
      op = getVPTMaskOpValue(MI, 0, Fixups, STI);
13109
0
      Value |= (op & UINT64_C(8)) << 19;
13110
0
      Value |= (op & UINT64_C(7)) << 13;
13111
      // op: Qn
13112
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13113
0
      op &= UINT64_C(7);
13114
0
      op <<= 17;
13115
0
      Value |= op;
13116
      // op: Rm
13117
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13118
0
      op &= UINT64_C(15);
13119
0
      Value |= op;
13120
0
      break;
13121
0
    }
13122
0
    case ARM::MVE_VCMPi8:
13123
0
    case ARM::MVE_VCMPi16:
13124
0
    case ARM::MVE_VCMPi32:
13125
0
    case ARM::MVE_VCMPu8:
13126
0
    case ARM::MVE_VCMPu16:
13127
0
    case ARM::MVE_VCMPu32: {
13128
      // op: fc
13129
0
      op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI);
13130
0
      op &= UINT64_C(1);
13131
0
      op <<= 7;
13132
0
      Value |= op;
13133
      // op: Qn
13134
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13135
0
      op &= UINT64_C(7);
13136
0
      op <<= 17;
13137
0
      Value |= op;
13138
      // op: Qm
13139
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13140
0
      Value |= (op & UINT64_C(8)) << 2;
13141
0
      Value |= (op & UINT64_C(7)) << 1;
13142
0
      break;
13143
0
    }
13144
0
    case ARM::MVE_VCMPi8r:
13145
0
    case ARM::MVE_VCMPi16r:
13146
0
    case ARM::MVE_VCMPi32r:
13147
0
    case ARM::MVE_VCMPu8r:
13148
0
    case ARM::MVE_VCMPu16r:
13149
0
    case ARM::MVE_VCMPu32r: {
13150
      // op: fc
13151
0
      op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI);
13152
0
      op &= UINT64_C(1);
13153
0
      op <<= 7;
13154
0
      Value |= op;
13155
      // op: Qn
13156
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13157
0
      op &= UINT64_C(7);
13158
0
      op <<= 17;
13159
0
      Value |= op;
13160
      // op: Rm
13161
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13162
0
      op &= UINT64_C(15);
13163
0
      Value |= op;
13164
0
      break;
13165
0
    }
13166
0
    case ARM::BL: {
13167
      // op: func
13168
0
      op = getARMBLTargetOpValue(MI, 0, Fixups, STI);
13169
0
      op &= UINT64_C(16777215);
13170
0
      Value |= op;
13171
0
      break;
13172
0
    }
13173
0
    case ARM::BLX: {
13174
      // op: func
13175
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13176
0
      op &= UINT64_C(15);
13177
0
      Value |= op;
13178
0
      break;
13179
0
    }
13180
0
    case ARM::t2BXJ: {
13181
      // op: func
13182
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13183
0
      op &= UINT64_C(15);
13184
0
      op <<= 16;
13185
0
      Value |= op;
13186
0
      break;
13187
0
    }
13188
0
    case ARM::tBLXNSr:
13189
0
    case ARM::tBLXr: {
13190
      // op: func
13191
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13192
0
      op &= UINT64_C(15);
13193
0
      op <<= 3;
13194
0
      Value |= op;
13195
0
      break;
13196
0
    }
13197
0
    case ARM::tBL: {
13198
      // op: func
13199
0
      op = getThumbBLTargetOpValue(MI, 2, Fixups, STI);
13200
0
      Value |= (op & UINT64_C(8388608)) << 3;
13201
0
      Value |= (op & UINT64_C(2095104)) << 5;
13202
0
      Value |= (op & UINT64_C(4194304)) >> 9;
13203
0
      Value |= (op & UINT64_C(2097152)) >> 10;
13204
0
      Value |= (op & UINT64_C(2047));
13205
0
      break;
13206
0
    }
13207
0
    case ARM::tBLXi: {
13208
      // op: func
13209
0
      op = getThumbBLXTargetOpValue(MI, 2, Fixups, STI);
13210
0
      Value |= (op & UINT64_C(8388608)) << 3;
13211
0
      Value |= (op & UINT64_C(2095104)) << 5;
13212
0
      Value |= (op & UINT64_C(4194304)) >> 9;
13213
0
      Value |= (op & UINT64_C(2097152)) >> 10;
13214
0
      Value |= (op & UINT64_C(2046));
13215
0
      break;
13216
0
    }
13217
0
    case ARM::HVC: {
13218
      // op: imm
13219
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13220
0
      Value |= (op & UINT64_C(65520)) << 4;
13221
0
      Value |= (op & UINT64_C(15));
13222
0
      break;
13223
0
    }
13224
0
    case ARM::t2SETPAN: {
13225
      // op: imm
13226
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13227
0
      op &= UINT64_C(1);
13228
0
      op <<= 3;
13229
0
      Value |= op;
13230
0
      break;
13231
0
    }
13232
0
    case ARM::SETPAN: {
13233
      // op: imm
13234
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13235
0
      op &= UINT64_C(1);
13236
0
      op <<= 9;
13237
0
      Value |= op;
13238
0
      break;
13239
0
    }
13240
0
    case ARM::tHINT: {
13241
      // op: imm
13242
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13243
0
      op &= UINT64_C(15);
13244
0
      op <<= 4;
13245
0
      Value |= op;
13246
0
      break;
13247
0
    }
13248
0
    case ARM::t2HINT:
13249
0
    case ARM::t2SUBS_PC_LR:
13250
0
    case ARM::tSVC: {
13251
      // op: imm
13252
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13253
0
      op &= UINT64_C(255);
13254
0
      Value |= op;
13255
0
      break;
13256
0
    }
13257
0
    case ARM::MVE_VMOVimmf32:
13258
0
    case ARM::MVE_VMOVimmi8:
13259
0
    case ARM::MVE_VMOVimmi64: {
13260
      // op: imm
13261
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13262
0
      Value |= (op & UINT64_C(128)) << 21;
13263
0
      Value |= (op & UINT64_C(112)) << 12;
13264
0
      Value |= (op & UINT64_C(15));
13265
      // op: Qd
13266
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13267
0
      Value |= (op & UINT64_C(8)) << 19;
13268
0
      Value |= (op & UINT64_C(7)) << 13;
13269
0
      break;
13270
0
    }
13271
0
    case ARM::MVE_VMOVimmi32:
13272
0
    case ARM::MVE_VMVNimmi32: {
13273
      // op: imm
13274
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13275
0
      Value |= (op & UINT64_C(128)) << 21;
13276
0
      Value |= (op & UINT64_C(112)) << 12;
13277
0
      Value |= (op & UINT64_C(3840));
13278
0
      Value |= (op & UINT64_C(15));
13279
      // op: Qd
13280
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13281
0
      Value |= (op & UINT64_C(8)) << 19;
13282
0
      Value |= (op & UINT64_C(7)) << 13;
13283
0
      break;
13284
0
    }
13285
0
    case ARM::MVE_VMOVimmi16:
13286
0
    case ARM::MVE_VMVNimmi16: {
13287
      // op: imm
13288
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13289
0
      Value |= (op & UINT64_C(128)) << 21;
13290
0
      Value |= (op & UINT64_C(112)) << 12;
13291
0
      Value |= (op & UINT64_C(512));
13292
0
      Value |= (op & UINT64_C(15));
13293
      // op: Qd
13294
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13295
0
      Value |= (op & UINT64_C(8)) << 19;
13296
0
      Value |= (op & UINT64_C(7)) << 13;
13297
0
      break;
13298
0
    }
13299
0
    case ARM::MVE_VBICimmi32:
13300
0
    case ARM::MVE_VORRimmi32: {
13301
      // op: imm
13302
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13303
0
      Value |= (op & UINT64_C(128)) << 21;
13304
0
      Value |= (op & UINT64_C(112)) << 12;
13305
0
      Value |= (op & UINT64_C(1536));
13306
0
      Value |= (op & UINT64_C(15));
13307
      // op: Qd
13308
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13309
0
      Value |= (op & UINT64_C(8)) << 19;
13310
0
      Value |= (op & UINT64_C(7)) << 13;
13311
0
      break;
13312
0
    }
13313
0
    case ARM::MVE_VBICimmi16:
13314
0
    case ARM::MVE_VORRimmi16: {
13315
      // op: imm
13316
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13317
0
      Value |= (op & UINT64_C(128)) << 21;
13318
0
      Value |= (op & UINT64_C(112)) << 12;
13319
0
      Value |= (op & UINT64_C(512));
13320
0
      Value |= (op & UINT64_C(15));
13321
      // op: Qd
13322
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13323
0
      Value |= (op & UINT64_C(8)) << 19;
13324
0
      Value |= (op & UINT64_C(7)) << 13;
13325
0
      break;
13326
0
    }
13327
0
    case ARM::t2ADDspImm12:
13328
0
    case ARM::t2SUBspImm12: {
13329
      // op: imm
13330
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13331
0
      Value |= (op & UINT64_C(2048)) << 15;
13332
0
      Value |= (op & UINT64_C(1792)) << 4;
13333
0
      Value |= (op & UINT64_C(255));
13334
0
      break;
13335
0
    }
13336
0
    case ARM::tADDspi:
13337
0
    case ARM::tSUBspi: {
13338
      // op: imm
13339
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13340
0
      op &= UINT64_C(127);
13341
0
      Value |= op;
13342
0
      break;
13343
0
    }
13344
0
    case ARM::MVE_VSHLC: {
13345
      // op: imm
13346
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
13347
0
      op &= UINT64_C(31);
13348
0
      op <<= 16;
13349
0
      Value |= op;
13350
      // op: Qd
13351
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13352
0
      Value |= (op & UINT64_C(8)) << 19;
13353
0
      Value |= (op & UINT64_C(7)) << 13;
13354
      // op: RdmDest
13355
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13356
0
      op &= UINT64_C(15);
13357
0
      Value |= op;
13358
0
      break;
13359
0
    }
13360
0
    case ARM::t2HVC:
13361
0
    case ARM::t2UDF: {
13362
      // op: imm16
13363
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13364
0
      Value |= (op & UINT64_C(61440)) << 4;
13365
0
      Value |= (op & UINT64_C(4095));
13366
0
      break;
13367
0
    }
13368
0
    case ARM::UDF: {
13369
      // op: imm16
13370
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13371
0
      Value |= (op & UINT64_C(65520)) << 4;
13372
0
      Value |= (op & UINT64_C(15));
13373
0
      break;
13374
0
    }
13375
0
    case ARM::tUDF: {
13376
      // op: imm8
13377
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13378
0
      op &= UINT64_C(255);
13379
0
      Value |= op;
13380
0
      break;
13381
0
    }
13382
0
    case ARM::tCPS: {
13383
      // op: imod
13384
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13385
0
      op &= UINT64_C(1);
13386
0
      op <<= 4;
13387
0
      Value |= op;
13388
      // op: iflags
13389
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13390
0
      op &= UINT64_C(7);
13391
0
      Value |= op;
13392
0
      break;
13393
0
    }
13394
0
    case ARM::CPS2p: {
13395
      // op: imod
13396
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13397
0
      op &= UINT64_C(3);
13398
0
      op <<= 18;
13399
0
      Value |= op;
13400
      // op: iflags
13401
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13402
0
      op &= UINT64_C(7);
13403
0
      op <<= 6;
13404
0
      Value |= op;
13405
0
      break;
13406
0
    }
13407
0
    case ARM::CPS3p: {
13408
      // op: imod
13409
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13410
0
      op &= UINT64_C(3);
13411
0
      op <<= 18;
13412
0
      Value |= op;
13413
      // op: iflags
13414
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13415
0
      op &= UINT64_C(7);
13416
0
      op <<= 6;
13417
0
      Value |= op;
13418
      // op: mode
13419
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13420
0
      op &= UINT64_C(31);
13421
0
      Value |= op;
13422
0
      break;
13423
0
    }
13424
0
    case ARM::t2CPS2p: {
13425
      // op: imod
13426
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13427
0
      op &= UINT64_C(3);
13428
0
      op <<= 9;
13429
0
      Value |= op;
13430
      // op: iflags
13431
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13432
0
      op &= UINT64_C(7);
13433
0
      op <<= 5;
13434
0
      Value |= op;
13435
0
      break;
13436
0
    }
13437
0
    case ARM::t2CPS3p: {
13438
      // op: imod
13439
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13440
0
      op &= UINT64_C(3);
13441
0
      op <<= 9;
13442
0
      Value |= op;
13443
      // op: iflags
13444
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13445
0
      op &= UINT64_C(7);
13446
0
      op <<= 5;
13447
0
      Value |= op;
13448
      // op: mode
13449
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13450
0
      op &= UINT64_C(31);
13451
0
      Value |= op;
13452
0
      break;
13453
0
    }
13454
0
    case ARM::t2LE: {
13455
      // op: label
13456
0
      op = getBFTargetOpValue<true, ARM::fixup_le>(MI, 0, Fixups, STI);
13457
0
      Value |= (op & UINT64_C(1)) << 11;
13458
0
      Value |= (op & UINT64_C(2046));
13459
0
      break;
13460
0
    }
13461
0
    case ARM::MVE_LETP:
13462
0
    case ARM::t2LEUpdate: {
13463
      // op: label
13464
0
      op = getBFTargetOpValue<true, ARM::fixup_le>(MI, 2, Fixups, STI);
13465
0
      Value |= (op & UINT64_C(1)) << 11;
13466
0
      Value |= (op & UINT64_C(2046));
13467
0
      break;
13468
0
    }
13469
0
    case ARM::t2MSR_AR: {
13470
      // op: mask
13471
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13472
0
      Value |= (op & UINT64_C(16)) << 16;
13473
0
      Value |= (op & UINT64_C(15)) << 8;
13474
      // op: Rn
13475
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13476
0
      op &= UINT64_C(15);
13477
0
      op <<= 16;
13478
0
      Value |= op;
13479
0
      break;
13480
0
    }
13481
0
    case ARM::CPS1p:
13482
0
    case ARM::SRSDA:
13483
0
    case ARM::SRSDA_UPD:
13484
0
    case ARM::SRSDB:
13485
0
    case ARM::SRSDB_UPD:
13486
0
    case ARM::SRSIA:
13487
0
    case ARM::SRSIA_UPD:
13488
0
    case ARM::SRSIB:
13489
0
    case ARM::SRSIB_UPD:
13490
0
    case ARM::t2CPS1p:
13491
0
    case ARM::t2SRSDB:
13492
0
    case ARM::t2SRSDB_UPD:
13493
0
    case ARM::t2SRSIA:
13494
0
    case ARM::t2SRSIA_UPD: {
13495
      // op: mode
13496
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13497
0
      op &= UINT64_C(31);
13498
0
      Value |= op;
13499
0
      break;
13500
0
    }
13501
0
    case ARM::LDC2L_POST:
13502
0
    case ARM::LDC2_POST:
13503
0
    case ARM::STC2L_POST:
13504
0
    case ARM::STC2_POST:
13505
0
    case ARM::t2LDC2L_POST:
13506
0
    case ARM::t2LDC2_POST:
13507
0
    case ARM::t2LDCL_POST:
13508
0
    case ARM::t2LDC_POST:
13509
0
    case ARM::t2STC2L_POST:
13510
0
    case ARM::t2STC2_POST:
13511
0
    case ARM::t2STCL_POST:
13512
0
    case ARM::t2STC_POST: {
13513
      // op: offset
13514
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
13515
0
      Value |= (op & UINT64_C(256)) << 15;
13516
0
      Value |= (op & UINT64_C(255));
13517
      // op: addr
13518
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13519
0
      op &= UINT64_C(15);
13520
0
      op <<= 16;
13521
0
      Value |= op;
13522
      // op: cop
13523
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13524
0
      op &= UINT64_C(15);
13525
0
      op <<= 8;
13526
0
      Value |= op;
13527
      // op: CRd
13528
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13529
0
      op &= UINT64_C(15);
13530
0
      op <<= 12;
13531
0
      Value |= op;
13532
0
      break;
13533
0
    }
13534
0
    case ARM::CDP2:
13535
0
    case ARM::t2CDP:
13536
0
    case ARM::t2CDP2: {
13537
      // op: opc1
13538
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13539
0
      op &= UINT64_C(15);
13540
0
      op <<= 20;
13541
0
      Value |= op;
13542
      // op: CRn
13543
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
13544
0
      op &= UINT64_C(15);
13545
0
      op <<= 16;
13546
0
      Value |= op;
13547
      // op: CRd
13548
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13549
0
      op &= UINT64_C(15);
13550
0
      op <<= 12;
13551
0
      Value |= op;
13552
      // op: cop
13553
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13554
0
      op &= UINT64_C(15);
13555
0
      op <<= 8;
13556
0
      Value |= op;
13557
      // op: opc2
13558
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
13559
0
      op &= UINT64_C(7);
13560
0
      op <<= 5;
13561
0
      Value |= op;
13562
      // op: CRm
13563
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
13564
0
      op &= UINT64_C(15);
13565
0
      Value |= op;
13566
0
      break;
13567
0
    }
13568
0
    case ARM::DMB:
13569
0
    case ARM::DSB:
13570
0
    case ARM::ISB:
13571
0
    case ARM::t2DBG:
13572
0
    case ARM::t2DMB:
13573
0
    case ARM::t2DSB:
13574
0
    case ARM::t2ISB: {
13575
      // op: opt
13576
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13577
0
      op &= UINT64_C(15);
13578
0
      Value |= op;
13579
0
      break;
13580
0
    }
13581
0
    case ARM::t2SMC: {
13582
      // op: opt
13583
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13584
0
      op &= UINT64_C(15);
13585
0
      op <<= 16;
13586
0
      Value |= op;
13587
0
      break;
13588
0
    }
13589
0
    case ARM::LDC2L_OPTION:
13590
0
    case ARM::LDC2_OPTION:
13591
0
    case ARM::STC2L_OPTION:
13592
0
    case ARM::STC2_OPTION:
13593
0
    case ARM::t2LDC2L_OPTION:
13594
0
    case ARM::t2LDC2_OPTION:
13595
0
    case ARM::t2LDCL_OPTION:
13596
0
    case ARM::t2LDC_OPTION:
13597
0
    case ARM::t2STC2L_OPTION:
13598
0
    case ARM::t2STC2_OPTION:
13599
0
    case ARM::t2STCL_OPTION:
13600
0
    case ARM::t2STC_OPTION: {
13601
      // op: option
13602
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
13603
0
      op &= UINT64_C(255);
13604
0
      Value |= op;
13605
      // op: addr
13606
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13607
0
      op &= UINT64_C(15);
13608
0
      op <<= 16;
13609
0
      Value |= op;
13610
      // op: cop
13611
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13612
0
      op &= UINT64_C(15);
13613
0
      op <<= 8;
13614
0
      Value |= op;
13615
      // op: CRd
13616
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13617
0
      op &= UINT64_C(15);
13618
0
      op <<= 12;
13619
0
      Value |= op;
13620
0
      break;
13621
0
    }
13622
0
    case ARM::BX_RET:
13623
0
    case ARM::ERET:
13624
0
    case ARM::MOVPCLR: {
13625
      // op: p
13626
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13627
0
      op &= UINT64_C(15);
13628
0
      op <<= 28;
13629
0
      Value |= op;
13630
0
      break;
13631
0
    }
13632
0
    case ARM::FMSTAT: {
13633
      // op: p
13634
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13635
0
      op &= UINT64_C(15);
13636
0
      op <<= 28;
13637
0
      Value |= op;
13638
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
13639
0
      break;
13640
0
    }
13641
0
    case ARM::t2Bcc: {
13642
      // op: p
13643
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13644
0
      op &= UINT64_C(15);
13645
0
      op <<= 22;
13646
0
      Value |= op;
13647
      // op: target
13648
0
      op = getBranchTargetOpValue(MI, 0, Fixups, STI);
13649
0
      Value |= (op & UINT64_C(1048576)) << 6;
13650
0
      Value |= (op & UINT64_C(258048)) << 4;
13651
0
      Value |= (op & UINT64_C(262144)) >> 5;
13652
0
      Value |= (op & UINT64_C(524288)) >> 8;
13653
0
      Value |= (op & UINT64_C(4094)) >> 1;
13654
0
      break;
13655
0
    }
13656
0
    case ARM::VCMPEZD:
13657
0
    case ARM::VCMPZD: {
13658
      // op: p
13659
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13660
0
      op &= UINT64_C(15);
13661
0
      op <<= 28;
13662
0
      Value |= op;
13663
      // op: Dd
13664
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13665
0
      Value |= (op & UINT64_C(16)) << 18;
13666
0
      Value |= (op & UINT64_C(15)) << 12;
13667
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
13668
0
      break;
13669
0
    }
13670
0
    case ARM::MRS:
13671
0
    case ARM::MRSsys: {
13672
      // op: p
13673
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13674
0
      op &= UINT64_C(15);
13675
0
      op <<= 28;
13676
0
      Value |= op;
13677
      // op: Rd
13678
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13679
0
      op &= UINT64_C(15);
13680
0
      op <<= 12;
13681
0
      Value |= op;
13682
0
      break;
13683
0
    }
13684
0
    case ARM::VLDMSIA:
13685
0
    case ARM::VSTMSIA: {
13686
      // op: p
13687
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13688
0
      op &= UINT64_C(15);
13689
0
      op <<= 28;
13690
0
      Value |= op;
13691
      // op: Rn
13692
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13693
0
      op &= UINT64_C(15);
13694
0
      op <<= 16;
13695
0
      Value |= op;
13696
      // op: regs
13697
0
      op = getRegisterListOpValue(MI, 3, Fixups, STI);
13698
0
      Value |= (op & UINT64_C(256)) << 14;
13699
0
      Value |= (op & UINT64_C(7680)) << 3;
13700
0
      Value |= (op & UINT64_C(255));
13701
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
13702
0
      break;
13703
0
    }
13704
0
    case ARM::FLDMXIA:
13705
0
    case ARM::FSTMXIA: {
13706
      // op: p
13707
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13708
0
      op &= UINT64_C(15);
13709
0
      op <<= 28;
13710
0
      Value |= op;
13711
      // op: Rn
13712
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13713
0
      op &= UINT64_C(15);
13714
0
      op <<= 16;
13715
0
      Value |= op;
13716
      // op: regs
13717
0
      op = getRegisterListOpValue(MI, 3, Fixups, STI);
13718
0
      Value |= (op & UINT64_C(3840)) << 4;
13719
0
      Value |= (op & UINT64_C(254));
13720
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
13721
0
      break;
13722
0
    }
13723
0
    case ARM::VLDMDIA:
13724
0
    case ARM::VSTMDIA: {
13725
      // op: p
13726
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13727
0
      op &= UINT64_C(15);
13728
0
      op <<= 28;
13729
0
      Value |= op;
13730
      // op: Rn
13731
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13732
0
      op &= UINT64_C(15);
13733
0
      op <<= 16;
13734
0
      Value |= op;
13735
      // op: regs
13736
0
      op = getRegisterListOpValue(MI, 3, Fixups, STI);
13737
0
      Value |= (op & UINT64_C(4096)) << 10;
13738
0
      Value |= (op & UINT64_C(3840)) << 4;
13739
0
      Value |= (op & UINT64_C(254));
13740
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
13741
0
      break;
13742
0
    }
13743
0
    case ARM::VLLDM:
13744
0
    case ARM::VLSTM: {
13745
      // op: p
13746
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13747
0
      op &= UINT64_C(15);
13748
0
      op <<= 28;
13749
0
      Value |= op;
13750
      // op: Rn
13751
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13752
0
      op &= UINT64_C(15);
13753
0
      op <<= 16;
13754
0
      Value |= op;
13755
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
13756
0
      break;
13757
0
    }
13758
0
    case ARM::VMRS:
13759
0
    case ARM::VMRS_FPCXTNS:
13760
0
    case ARM::VMRS_FPCXTS:
13761
0
    case ARM::VMRS_FPEXC:
13762
0
    case ARM::VMRS_FPINST:
13763
0
    case ARM::VMRS_FPINST2:
13764
0
    case ARM::VMRS_FPSID:
13765
0
    case ARM::VMRS_MVFR0:
13766
0
    case ARM::VMRS_MVFR1:
13767
0
    case ARM::VMRS_MVFR2:
13768
0
    case ARM::VMRS_VPR:
13769
0
    case ARM::VMSR:
13770
0
    case ARM::VMSR_FPCXTNS:
13771
0
    case ARM::VMSR_FPCXTS:
13772
0
    case ARM::VMSR_FPEXC:
13773
0
    case ARM::VMSR_FPINST:
13774
0
    case ARM::VMSR_FPINST2:
13775
0
    case ARM::VMSR_FPSID:
13776
0
    case ARM::VMSR_VPR: {
13777
      // op: p
13778
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13779
0
      op &= UINT64_C(15);
13780
0
      op <<= 28;
13781
0
      Value |= op;
13782
      // op: Rt
13783
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13784
0
      op &= UINT64_C(15);
13785
0
      op <<= 12;
13786
0
      Value |= op;
13787
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
13788
0
      break;
13789
0
    }
13790
0
    case ARM::VCMPEZH:
13791
0
    case ARM::VCMPEZS:
13792
0
    case ARM::VCMPZH:
13793
0
    case ARM::VCMPZS: {
13794
      // op: p
13795
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13796
0
      op &= UINT64_C(15);
13797
0
      op <<= 28;
13798
0
      Value |= op;
13799
      // op: Sd
13800
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13801
0
      Value |= (op & UINT64_C(1)) << 22;
13802
0
      Value |= (op & UINT64_C(30)) << 11;
13803
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
13804
0
      break;
13805
0
    }
13806
0
    case ARM::BX_pred: {
13807
      // op: p
13808
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13809
0
      op &= UINT64_C(15);
13810
0
      op <<= 28;
13811
0
      Value |= op;
13812
      // op: dst
13813
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13814
0
      op &= UINT64_C(15);
13815
0
      Value |= op;
13816
0
      break;
13817
0
    }
13818
0
    case ARM::BL_pred: {
13819
      // op: p
13820
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13821
0
      op &= UINT64_C(15);
13822
0
      op <<= 28;
13823
0
      Value |= op;
13824
      // op: func
13825
0
      op = getARMBLTargetOpValue(MI, 0, Fixups, STI);
13826
0
      op &= UINT64_C(16777215);
13827
0
      Value |= op;
13828
0
      break;
13829
0
    }
13830
0
    case ARM::BLX_pred:
13831
0
    case ARM::BXJ: {
13832
      // op: p
13833
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13834
0
      op &= UINT64_C(15);
13835
0
      op <<= 28;
13836
0
      Value |= op;
13837
      // op: func
13838
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13839
0
      op &= UINT64_C(15);
13840
0
      Value |= op;
13841
0
      break;
13842
0
    }
13843
0
    case ARM::HINT: {
13844
      // op: p
13845
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13846
0
      op &= UINT64_C(15);
13847
0
      op <<= 28;
13848
0
      Value |= op;
13849
      // op: imm
13850
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13851
0
      op &= UINT64_C(255);
13852
0
      Value |= op;
13853
0
      break;
13854
0
    }
13855
0
    case ARM::DBG:
13856
0
    case ARM::SMC: {
13857
      // op: p
13858
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13859
0
      op &= UINT64_C(15);
13860
0
      op <<= 28;
13861
0
      Value |= op;
13862
      // op: opt
13863
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13864
0
      op &= UINT64_C(15);
13865
0
      Value |= op;
13866
0
      break;
13867
0
    }
13868
0
    case ARM::LDMDA:
13869
0
    case ARM::LDMDB:
13870
0
    case ARM::LDMIA:
13871
0
    case ARM::LDMIB:
13872
0
    case ARM::STMDA:
13873
0
    case ARM::STMDB:
13874
0
    case ARM::STMIA:
13875
0
    case ARM::STMIB:
13876
0
    case ARM::sysLDMDA:
13877
0
    case ARM::sysLDMDB:
13878
0
    case ARM::sysLDMIA:
13879
0
    case ARM::sysLDMIB:
13880
0
    case ARM::sysSTMDA:
13881
0
    case ARM::sysSTMDB:
13882
0
    case ARM::sysSTMIA:
13883
0
    case ARM::sysSTMIB: {
13884
      // op: p
13885
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13886
0
      op &= UINT64_C(15);
13887
0
      op <<= 28;
13888
0
      Value |= op;
13889
      // op: regs
13890
0
      op = getRegisterListOpValue(MI, 3, Fixups, STI);
13891
0
      op &= UINT64_C(65535);
13892
0
      Value |= op;
13893
      // op: Rn
13894
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13895
0
      op &= UINT64_C(15);
13896
0
      op <<= 16;
13897
0
      Value |= op;
13898
0
      break;
13899
0
    }
13900
0
    case ARM::SVC: {
13901
      // op: p
13902
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13903
0
      op &= UINT64_C(15);
13904
0
      op <<= 28;
13905
0
      Value |= op;
13906
      // op: svc
13907
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13908
0
      op &= UINT64_C(16777215);
13909
0
      Value |= op;
13910
0
      break;
13911
0
    }
13912
0
    case ARM::Bcc: {
13913
      // op: p
13914
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13915
0
      op &= UINT64_C(15);
13916
0
      op <<= 28;
13917
0
      Value |= op;
13918
      // op: target
13919
0
      op = getARMBranchTargetOpValue(MI, 0, Fixups, STI);
13920
0
      op &= UINT64_C(16777215);
13921
0
      Value |= op;
13922
0
      break;
13923
0
    }
13924
0
    case ARM::tBcc: {
13925
      // op: p
13926
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13927
0
      op &= UINT64_C(15);
13928
0
      op <<= 8;
13929
0
      Value |= op;
13930
      // op: target
13931
0
      op = getThumbBCCTargetOpValue(MI, 0, Fixups, STI);
13932
0
      op &= UINT64_C(255);
13933
0
      Value |= op;
13934
0
      break;
13935
0
    }
13936
0
    case ARM::VABSD:
13937
0
    case ARM::VCMPD:
13938
0
    case ARM::VCMPED:
13939
0
    case ARM::VMOVD:
13940
0
    case ARM::VNEGD:
13941
0
    case ARM::VRINTRD:
13942
0
    case ARM::VRINTXD:
13943
0
    case ARM::VRINTZD:
13944
0
    case ARM::VSQRTD: {
13945
      // op: p
13946
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13947
0
      op &= UINT64_C(15);
13948
0
      op <<= 28;
13949
0
      Value |= op;
13950
      // op: Dd
13951
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13952
0
      Value |= (op & UINT64_C(16)) << 18;
13953
0
      Value |= (op & UINT64_C(15)) << 12;
13954
      // op: Dm
13955
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13956
0
      Value |= (op & UINT64_C(16)) << 1;
13957
0
      Value |= (op & UINT64_C(15));
13958
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
13959
0
      break;
13960
0
    }
13961
0
    case ARM::VCVTBHD:
13962
0
    case ARM::VCVTTHD:
13963
0
    case ARM::VSITOD:
13964
0
    case ARM::VUITOD: {
13965
      // op: p
13966
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13967
0
      op &= UINT64_C(15);
13968
0
      op <<= 28;
13969
0
      Value |= op;
13970
      // op: Dd
13971
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13972
0
      Value |= (op & UINT64_C(16)) << 18;
13973
0
      Value |= (op & UINT64_C(15)) << 12;
13974
      // op: Sm
13975
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13976
0
      Value |= (op & UINT64_C(1)) << 5;
13977
0
      Value |= (op & UINT64_C(30)) >> 1;
13978
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
13979
0
      break;
13980
0
    }
13981
0
    case ARM::FCONSTD: {
13982
      // op: p
13983
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
13984
0
      op &= UINT64_C(15);
13985
0
      op <<= 28;
13986
0
      Value |= op;
13987
      // op: Dd
13988
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
13989
0
      Value |= (op & UINT64_C(16)) << 18;
13990
0
      Value |= (op & UINT64_C(15)) << 12;
13991
      // op: imm
13992
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
13993
0
      Value |= (op & UINT64_C(240)) << 12;
13994
0
      Value |= (op & UINT64_C(15));
13995
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
13996
0
      break;
13997
0
    }
13998
0
    case ARM::CLZ:
13999
0
    case ARM::RBIT:
14000
0
    case ARM::REV:
14001
0
    case ARM::REV16:
14002
0
    case ARM::REVSH: {
14003
      // op: p
14004
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14005
0
      op &= UINT64_C(15);
14006
0
      op <<= 28;
14007
0
      Value |= op;
14008
      // op: Rd
14009
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14010
0
      op &= UINT64_C(15);
14011
0
      op <<= 12;
14012
0
      Value |= op;
14013
      // op: Rm
14014
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14015
0
      op &= UINT64_C(15);
14016
0
      Value |= op;
14017
0
      break;
14018
0
    }
14019
0
    case ARM::MOVi16: {
14020
      // op: p
14021
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14022
0
      op &= UINT64_C(15);
14023
0
      op <<= 28;
14024
0
      Value |= op;
14025
      // op: Rd
14026
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14027
0
      op &= UINT64_C(15);
14028
0
      op <<= 12;
14029
0
      Value |= op;
14030
      // op: imm
14031
0
      op = getHiLoImmOpValue(MI, 1, Fixups, STI);
14032
0
      Value |= (op & UINT64_C(61440)) << 4;
14033
0
      Value |= (op & UINT64_C(4095));
14034
0
      break;
14035
0
    }
14036
0
    case ARM::ADR: {
14037
      // op: p
14038
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14039
0
      op &= UINT64_C(15);
14040
0
      op <<= 28;
14041
0
      Value |= op;
14042
      // op: Rd
14043
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14044
0
      op &= UINT64_C(15);
14045
0
      op <<= 12;
14046
0
      Value |= op;
14047
      // op: label
14048
0
      op = getAdrLabelOpValue(MI, 1, Fixups, STI);
14049
0
      Value |= (op & UINT64_C(12288)) << 10;
14050
0
      Value |= (op & UINT64_C(4095));
14051
0
      break;
14052
0
    }
14053
0
    case ARM::CMNzrr:
14054
0
    case ARM::CMPrr:
14055
0
    case ARM::TEQrr:
14056
0
    case ARM::TSTrr: {
14057
      // op: p
14058
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14059
0
      op &= UINT64_C(15);
14060
0
      op <<= 28;
14061
0
      Value |= op;
14062
      // op: Rn
14063
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14064
0
      op &= UINT64_C(15);
14065
0
      op <<= 16;
14066
0
      Value |= op;
14067
      // op: Rm
14068
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14069
0
      op &= UINT64_C(15);
14070
0
      Value |= op;
14071
0
      break;
14072
0
    }
14073
0
    case ARM::CMNri:
14074
0
    case ARM::CMPri:
14075
0
    case ARM::TEQri:
14076
0
    case ARM::TSTri: {
14077
      // op: p
14078
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14079
0
      op &= UINT64_C(15);
14080
0
      op <<= 28;
14081
0
      Value |= op;
14082
      // op: Rn
14083
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14084
0
      op &= UINT64_C(15);
14085
0
      op <<= 16;
14086
0
      Value |= op;
14087
      // op: imm
14088
0
      op = getModImmOpValue(MI, 1, Fixups, STI);
14089
0
      op &= UINT64_C(4095);
14090
0
      Value |= op;
14091
0
      break;
14092
0
    }
14093
0
    case ARM::VLDMSDB_UPD:
14094
0
    case ARM::VLDMSIA_UPD:
14095
0
    case ARM::VSTMSDB_UPD:
14096
0
    case ARM::VSTMSIA_UPD: {
14097
      // op: p
14098
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14099
0
      op &= UINT64_C(15);
14100
0
      op <<= 28;
14101
0
      Value |= op;
14102
      // op: Rn
14103
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14104
0
      op &= UINT64_C(15);
14105
0
      op <<= 16;
14106
0
      Value |= op;
14107
      // op: regs
14108
0
      op = getRegisterListOpValue(MI, 4, Fixups, STI);
14109
0
      Value |= (op & UINT64_C(256)) << 14;
14110
0
      Value |= (op & UINT64_C(7680)) << 3;
14111
0
      Value |= (op & UINT64_C(255));
14112
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
14113
0
      break;
14114
0
    }
14115
0
    case ARM::FLDMXDB_UPD:
14116
0
    case ARM::FLDMXIA_UPD:
14117
0
    case ARM::FSTMXDB_UPD:
14118
0
    case ARM::FSTMXIA_UPD: {
14119
      // op: p
14120
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14121
0
      op &= UINT64_C(15);
14122
0
      op <<= 28;
14123
0
      Value |= op;
14124
      // op: Rn
14125
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14126
0
      op &= UINT64_C(15);
14127
0
      op <<= 16;
14128
0
      Value |= op;
14129
      // op: regs
14130
0
      op = getRegisterListOpValue(MI, 4, Fixups, STI);
14131
0
      Value |= (op & UINT64_C(3840)) << 4;
14132
0
      Value |= (op & UINT64_C(254));
14133
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
14134
0
      break;
14135
0
    }
14136
0
    case ARM::VLDMDDB_UPD:
14137
0
    case ARM::VLDMDIA_UPD:
14138
0
    case ARM::VSTMDDB_UPD:
14139
0
    case ARM::VSTMDIA_UPD: {
14140
      // op: p
14141
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14142
0
      op &= UINT64_C(15);
14143
0
      op <<= 28;
14144
0
      Value |= op;
14145
      // op: Rn
14146
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14147
0
      op &= UINT64_C(15);
14148
0
      op <<= 16;
14149
0
      Value |= op;
14150
      // op: regs
14151
0
      op = getRegisterListOpValue(MI, 4, Fixups, STI);
14152
0
      Value |= (op & UINT64_C(4096)) << 10;
14153
0
      Value |= (op & UINT64_C(3840)) << 4;
14154
0
      Value |= (op & UINT64_C(254));
14155
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
14156
0
      break;
14157
0
    }
14158
0
    case ARM::STL:
14159
0
    case ARM::STLB:
14160
0
    case ARM::STLH: {
14161
      // op: p
14162
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14163
0
      op &= UINT64_C(15);
14164
0
      op <<= 28;
14165
0
      Value |= op;
14166
      // op: Rt
14167
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14168
0
      op &= UINT64_C(15);
14169
0
      Value |= op;
14170
      // op: addr
14171
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14172
0
      op &= UINT64_C(15);
14173
0
      op <<= 16;
14174
0
      Value |= op;
14175
0
      break;
14176
0
    }
14177
0
    case ARM::VMOVRH:
14178
0
    case ARM::VMOVRS: {
14179
      // op: p
14180
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14181
0
      op &= UINT64_C(15);
14182
0
      op <<= 28;
14183
0
      Value |= op;
14184
      // op: Rt
14185
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14186
0
      op &= UINT64_C(15);
14187
0
      op <<= 12;
14188
0
      Value |= op;
14189
      // op: Sn
14190
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14191
0
      Value |= (op & UINT64_C(30)) << 15;
14192
0
      Value |= (op & UINT64_C(1)) << 7;
14193
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
14194
0
      break;
14195
0
    }
14196
0
    case ARM::LDA:
14197
0
    case ARM::LDAB:
14198
0
    case ARM::LDAEX:
14199
0
    case ARM::LDAEXB:
14200
0
    case ARM::LDAEXD:
14201
0
    case ARM::LDAEXH:
14202
0
    case ARM::LDAH:
14203
0
    case ARM::LDREX:
14204
0
    case ARM::LDREXB:
14205
0
    case ARM::LDREXD:
14206
0
    case ARM::LDREXH: {
14207
      // op: p
14208
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14209
0
      op &= UINT64_C(15);
14210
0
      op <<= 28;
14211
0
      Value |= op;
14212
      // op: Rt
14213
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14214
0
      op &= UINT64_C(15);
14215
0
      op <<= 12;
14216
0
      Value |= op;
14217
      // op: addr
14218
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14219
0
      op &= UINT64_C(15);
14220
0
      op <<= 16;
14221
0
      Value |= op;
14222
0
      break;
14223
0
    }
14224
0
    case ARM::VMRS_FPSCR_NZCVQC:
14225
0
    case ARM::VMRS_P0: {
14226
      // op: p
14227
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14228
0
      op &= UINT64_C(15);
14229
0
      op <<= 28;
14230
0
      Value |= op;
14231
      // op: Rt
14232
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14233
0
      op &= UINT64_C(15);
14234
0
      op <<= 12;
14235
0
      Value |= op;
14236
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
14237
0
      break;
14238
0
    }
14239
0
    case ARM::VMSR_FPSCR_NZCVQC:
14240
0
    case ARM::VMSR_P0: {
14241
      // op: p
14242
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14243
0
      op &= UINT64_C(15);
14244
0
      op <<= 28;
14245
0
      Value |= op;
14246
      // op: Rt
14247
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14248
0
      op &= UINT64_C(15);
14249
0
      op <<= 12;
14250
0
      Value |= op;
14251
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
14252
0
      break;
14253
0
    }
14254
0
    case ARM::VCVTSD:
14255
0
    case ARM::VJCVT:
14256
0
    case ARM::VTOSIRD:
14257
0
    case ARM::VTOSIZD:
14258
0
    case ARM::VTOUIRD:
14259
0
    case ARM::VTOUIZD: {
14260
      // op: p
14261
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14262
0
      op &= UINT64_C(15);
14263
0
      op <<= 28;
14264
0
      Value |= op;
14265
      // op: Sd
14266
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14267
0
      Value |= (op & UINT64_C(1)) << 22;
14268
0
      Value |= (op & UINT64_C(30)) << 11;
14269
      // op: Dm
14270
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14271
0
      Value |= (op & UINT64_C(16)) << 1;
14272
0
      Value |= (op & UINT64_C(15));
14273
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
14274
0
      break;
14275
0
    }
14276
0
    case ARM::VABSH:
14277
0
    case ARM::VABSS:
14278
0
    case ARM::VCMPEH:
14279
0
    case ARM::VCMPES:
14280
0
    case ARM::VCMPH:
14281
0
    case ARM::VCMPS:
14282
0
    case ARM::VCVTBHS:
14283
0
    case ARM::VCVTTHS:
14284
0
    case ARM::VMOVS:
14285
0
    case ARM::VNEGH:
14286
0
    case ARM::VNEGS:
14287
0
    case ARM::VRINTRH:
14288
0
    case ARM::VRINTRS:
14289
0
    case ARM::VRINTXH:
14290
0
    case ARM::VRINTXS:
14291
0
    case ARM::VRINTZH:
14292
0
    case ARM::VRINTZS:
14293
0
    case ARM::VSITOH:
14294
0
    case ARM::VSITOS:
14295
0
    case ARM::VSQRTH:
14296
0
    case ARM::VSQRTS:
14297
0
    case ARM::VTOSIRH:
14298
0
    case ARM::VTOSIRS:
14299
0
    case ARM::VTOSIZH:
14300
0
    case ARM::VTOSIZS:
14301
0
    case ARM::VTOUIRH:
14302
0
    case ARM::VTOUIRS:
14303
0
    case ARM::VTOUIZH:
14304
0
    case ARM::VTOUIZS:
14305
0
    case ARM::VUITOH:
14306
0
    case ARM::VUITOS: {
14307
      // op: p
14308
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14309
0
      op &= UINT64_C(15);
14310
0
      op <<= 28;
14311
0
      Value |= op;
14312
      // op: Sd
14313
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14314
0
      Value |= (op & UINT64_C(1)) << 22;
14315
0
      Value |= (op & UINT64_C(30)) << 11;
14316
      // op: Sm
14317
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14318
0
      Value |= (op & UINT64_C(1)) << 5;
14319
0
      Value |= (op & UINT64_C(30)) >> 1;
14320
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
14321
0
      break;
14322
0
    }
14323
0
    case ARM::FCONSTH:
14324
0
    case ARM::FCONSTS: {
14325
      // op: p
14326
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14327
0
      op &= UINT64_C(15);
14328
0
      op <<= 28;
14329
0
      Value |= op;
14330
      // op: Sd
14331
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14332
0
      Value |= (op & UINT64_C(1)) << 22;
14333
0
      Value |= (op & UINT64_C(30)) << 11;
14334
      // op: imm
14335
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14336
0
      Value |= (op & UINT64_C(240)) << 12;
14337
0
      Value |= (op & UINT64_C(15));
14338
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
14339
0
      break;
14340
0
    }
14341
0
    case ARM::VCVTDS: {
14342
      // op: p
14343
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14344
0
      op &= UINT64_C(15);
14345
0
      op <<= 28;
14346
0
      Value |= op;
14347
      // op: Sm
14348
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14349
0
      Value |= (op & UINT64_C(1)) << 5;
14350
0
      Value |= (op & UINT64_C(30)) >> 1;
14351
      // op: Dd
14352
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14353
0
      Value |= (op & UINT64_C(16)) << 18;
14354
0
      Value |= (op & UINT64_C(15)) << 12;
14355
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
14356
0
      break;
14357
0
    }
14358
0
    case ARM::VMOVHR:
14359
0
    case ARM::VMOVSR: {
14360
      // op: p
14361
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14362
0
      op &= UINT64_C(15);
14363
0
      op <<= 28;
14364
0
      Value |= op;
14365
      // op: Sn
14366
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14367
0
      Value |= (op & UINT64_C(30)) << 15;
14368
0
      Value |= (op & UINT64_C(1)) << 7;
14369
      // op: Rt
14370
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14371
0
      op &= UINT64_C(15);
14372
0
      op <<= 12;
14373
0
      Value |= op;
14374
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
14375
0
      break;
14376
0
    }
14377
0
    case ARM::VLDR_FPCXTNS_off:
14378
0
    case ARM::VLDR_FPCXTS_off:
14379
0
    case ARM::VLDR_FPSCR_NZCVQC_off:
14380
0
    case ARM::VLDR_FPSCR_off:
14381
0
    case ARM::VLDR_VPR_off:
14382
0
    case ARM::VSTR_FPCXTNS_off:
14383
0
    case ARM::VSTR_FPCXTS_off:
14384
0
    case ARM::VSTR_FPSCR_NZCVQC_off:
14385
0
    case ARM::VSTR_FPSCR_off:
14386
0
    case ARM::VSTR_VPR_off: {
14387
      // op: p
14388
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14389
0
      op &= UINT64_C(15);
14390
0
      op <<= 28;
14391
0
      Value |= op;
14392
      // op: addr
14393
0
      op = getT2AddrModeImm7s4OpValue(MI, 0, Fixups, STI);
14394
0
      Value |= (op & UINT64_C(128)) << 16;
14395
0
      Value |= (op & UINT64_C(3840)) << 8;
14396
0
      Value |= (op & UINT64_C(127));
14397
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
14398
0
      break;
14399
0
    }
14400
0
    case ARM::MSRbanked: {
14401
      // op: p
14402
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14403
0
      op &= UINT64_C(15);
14404
0
      op <<= 28;
14405
0
      Value |= op;
14406
      // op: banked
14407
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14408
0
      Value |= (op & UINT64_C(32)) << 17;
14409
0
      Value |= (op & UINT64_C(15)) << 16;
14410
0
      Value |= (op & UINT64_C(16)) << 4;
14411
      // op: Rn
14412
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14413
0
      op &= UINT64_C(15);
14414
0
      Value |= op;
14415
0
      break;
14416
0
    }
14417
0
    case ARM::MRSbanked: {
14418
      // op: p
14419
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14420
0
      op &= UINT64_C(15);
14421
0
      op <<= 28;
14422
0
      Value |= op;
14423
      // op: banked
14424
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14425
0
      Value |= (op & UINT64_C(32)) << 17;
14426
0
      Value |= (op & UINT64_C(15)) << 16;
14427
0
      Value |= (op & UINT64_C(16)) << 4;
14428
      // op: Rd
14429
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14430
0
      op &= UINT64_C(15);
14431
0
      op <<= 12;
14432
0
      Value |= op;
14433
0
      break;
14434
0
    }
14435
0
    case ARM::MSR: {
14436
      // op: p
14437
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14438
0
      op &= UINT64_C(15);
14439
0
      op <<= 28;
14440
0
      Value |= op;
14441
      // op: mask
14442
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14443
0
      Value |= (op & UINT64_C(16)) << 18;
14444
0
      Value |= (op & UINT64_C(15)) << 16;
14445
      // op: Rn
14446
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14447
0
      op &= UINT64_C(15);
14448
0
      Value |= op;
14449
0
      break;
14450
0
    }
14451
0
    case ARM::MSRi: {
14452
      // op: p
14453
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14454
0
      op &= UINT64_C(15);
14455
0
      op <<= 28;
14456
0
      Value |= op;
14457
      // op: mask
14458
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14459
0
      Value |= (op & UINT64_C(16)) << 18;
14460
0
      Value |= (op & UINT64_C(15)) << 16;
14461
      // op: imm
14462
0
      op = getModImmOpValue(MI, 1, Fixups, STI);
14463
0
      op &= UINT64_C(4095);
14464
0
      Value |= op;
14465
0
      break;
14466
0
    }
14467
0
    case ARM::LDMDA_UPD:
14468
0
    case ARM::LDMDB_UPD:
14469
0
    case ARM::LDMIA_UPD:
14470
0
    case ARM::LDMIB_UPD:
14471
0
    case ARM::STMDA_UPD:
14472
0
    case ARM::STMDB_UPD:
14473
0
    case ARM::STMIA_UPD:
14474
0
    case ARM::STMIB_UPD:
14475
0
    case ARM::sysLDMDA_UPD:
14476
0
    case ARM::sysLDMDB_UPD:
14477
0
    case ARM::sysLDMIA_UPD:
14478
0
    case ARM::sysLDMIB_UPD:
14479
0
    case ARM::sysSTMDA_UPD:
14480
0
    case ARM::sysSTMDB_UPD:
14481
0
    case ARM::sysSTMIA_UPD:
14482
0
    case ARM::sysSTMIB_UPD: {
14483
      // op: p
14484
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14485
0
      op &= UINT64_C(15);
14486
0
      op <<= 28;
14487
0
      Value |= op;
14488
      // op: regs
14489
0
      op = getRegisterListOpValue(MI, 4, Fixups, STI);
14490
0
      op &= UINT64_C(65535);
14491
0
      Value |= op;
14492
      // op: Rn
14493
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14494
0
      op &= UINT64_C(15);
14495
0
      op <<= 16;
14496
0
      Value |= op;
14497
0
      break;
14498
0
    }
14499
0
    case ARM::MOVr:
14500
0
    case ARM::MOVr_TC:
14501
0
    case ARM::MVNr: {
14502
      // op: p
14503
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14504
0
      op &= UINT64_C(15);
14505
0
      op <<= 28;
14506
0
      Value |= op;
14507
      // op: s
14508
0
      op = getCCOutOpValue(MI, 4, Fixups, STI);
14509
0
      op &= UINT64_C(1);
14510
0
      op <<= 20;
14511
0
      Value |= op;
14512
      // op: Rd
14513
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14514
0
      op &= UINT64_C(15);
14515
0
      op <<= 12;
14516
0
      Value |= op;
14517
      // op: Rm
14518
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14519
0
      op &= UINT64_C(15);
14520
0
      Value |= op;
14521
0
      break;
14522
0
    }
14523
0
    case ARM::MOVi:
14524
0
    case ARM::MVNi: {
14525
      // op: p
14526
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14527
0
      op &= UINT64_C(15);
14528
0
      op <<= 28;
14529
0
      Value |= op;
14530
      // op: s
14531
0
      op = getCCOutOpValue(MI, 4, Fixups, STI);
14532
0
      op &= UINT64_C(1);
14533
0
      op <<= 20;
14534
0
      Value |= op;
14535
      // op: Rd
14536
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14537
0
      op &= UINT64_C(15);
14538
0
      op <<= 12;
14539
0
      Value |= op;
14540
      // op: imm
14541
0
      op = getModImmOpValue(MI, 1, Fixups, STI);
14542
0
      op &= UINT64_C(4095);
14543
0
      Value |= op;
14544
0
      break;
14545
0
    }
14546
0
    case ARM::VADDD:
14547
0
    case ARM::VDIVD:
14548
0
    case ARM::VMULD:
14549
0
    case ARM::VNMULD:
14550
0
    case ARM::VSUBD: {
14551
      // op: p
14552
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14553
0
      op &= UINT64_C(15);
14554
0
      op <<= 28;
14555
0
      Value |= op;
14556
      // op: Dd
14557
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14558
0
      Value |= (op & UINT64_C(16)) << 18;
14559
0
      Value |= (op & UINT64_C(15)) << 12;
14560
      // op: Dn
14561
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14562
0
      Value |= (op & UINT64_C(15)) << 16;
14563
0
      Value |= (op & UINT64_C(16)) << 3;
14564
      // op: Dm
14565
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14566
0
      Value |= (op & UINT64_C(16)) << 1;
14567
0
      Value |= (op & UINT64_C(15));
14568
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
14569
0
      break;
14570
0
    }
14571
0
    case ARM::VLDRD:
14572
0
    case ARM::VSTRD: {
14573
      // op: p
14574
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14575
0
      op &= UINT64_C(15);
14576
0
      op <<= 28;
14577
0
      Value |= op;
14578
      // op: Dd
14579
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14580
0
      Value |= (op & UINT64_C(16)) << 18;
14581
0
      Value |= (op & UINT64_C(15)) << 12;
14582
      // op: addr
14583
0
      op = getAddrMode5OpValue(MI, 1, Fixups, STI);
14584
0
      Value |= (op & UINT64_C(256)) << 15;
14585
0
      Value |= (op & UINT64_C(7680)) << 7;
14586
0
      Value |= (op & UINT64_C(255));
14587
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
14588
0
      break;
14589
0
    }
14590
0
    case ARM::VMOVDRR: {
14591
      // op: p
14592
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14593
0
      op &= UINT64_C(15);
14594
0
      op <<= 28;
14595
0
      Value |= op;
14596
      // op: Dm
14597
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14598
0
      Value |= (op & UINT64_C(16)) << 1;
14599
0
      Value |= (op & UINT64_C(15));
14600
      // op: Rt
14601
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14602
0
      op &= UINT64_C(15);
14603
0
      op <<= 12;
14604
0
      Value |= op;
14605
      // op: Rt2
14606
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14607
0
      op &= UINT64_C(15);
14608
0
      op <<= 16;
14609
0
      Value |= op;
14610
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
14611
0
      break;
14612
0
    }
14613
0
    case ARM::VMOVRRD: {
14614
      // op: p
14615
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14616
0
      op &= UINT64_C(15);
14617
0
      op <<= 28;
14618
0
      Value |= op;
14619
      // op: Dm
14620
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14621
0
      Value |= (op & UINT64_C(16)) << 1;
14622
0
      Value |= (op & UINT64_C(15));
14623
      // op: Rt
14624
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14625
0
      op &= UINT64_C(15);
14626
0
      op <<= 12;
14627
0
      Value |= op;
14628
      // op: Rt2
14629
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14630
0
      op &= UINT64_C(15);
14631
0
      op <<= 16;
14632
0
      Value |= op;
14633
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
14634
0
      break;
14635
0
    }
14636
0
    case ARM::VCVTBDH:
14637
0
    case ARM::VCVTTDH: {
14638
      // op: p
14639
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14640
0
      op &= UINT64_C(15);
14641
0
      op <<= 28;
14642
0
      Value |= op;
14643
      // op: Dm
14644
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14645
0
      Value |= (op & UINT64_C(16)) << 1;
14646
0
      Value |= (op & UINT64_C(15));
14647
      // op: Sd
14648
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14649
0
      Value |= (op & UINT64_C(1)) << 22;
14650
0
      Value |= (op & UINT64_C(30)) << 11;
14651
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
14652
0
      break;
14653
0
    }
14654
0
    case ARM::SXTB:
14655
0
    case ARM::SXTB16:
14656
0
    case ARM::SXTH:
14657
0
    case ARM::UXTB:
14658
0
    case ARM::UXTB16:
14659
0
    case ARM::UXTH: {
14660
      // op: p
14661
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14662
0
      op &= UINT64_C(15);
14663
0
      op <<= 28;
14664
0
      Value |= op;
14665
      // op: Rd
14666
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14667
0
      op &= UINT64_C(15);
14668
0
      op <<= 12;
14669
0
      Value |= op;
14670
      // op: Rm
14671
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14672
0
      op &= UINT64_C(15);
14673
0
      Value |= op;
14674
      // op: rot
14675
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14676
0
      op &= UINT64_C(3);
14677
0
      op <<= 10;
14678
0
      Value |= op;
14679
0
      break;
14680
0
    }
14681
0
    case ARM::SEL: {
14682
      // op: p
14683
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14684
0
      op &= UINT64_C(15);
14685
0
      op <<= 28;
14686
0
      Value |= op;
14687
      // op: Rd
14688
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14689
0
      op &= UINT64_C(15);
14690
0
      op <<= 12;
14691
0
      Value |= op;
14692
      // op: Rn
14693
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14694
0
      op &= UINT64_C(15);
14695
0
      op <<= 16;
14696
0
      Value |= op;
14697
      // op: Rm
14698
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14699
0
      op &= UINT64_C(15);
14700
0
      Value |= op;
14701
0
      break;
14702
0
    }
14703
0
    case ARM::BFC: {
14704
      // op: p
14705
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14706
0
      op &= UINT64_C(15);
14707
0
      op <<= 28;
14708
0
      Value |= op;
14709
      // op: Rd
14710
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14711
0
      op &= UINT64_C(15);
14712
0
      op <<= 12;
14713
0
      Value |= op;
14714
      // op: imm
14715
0
      op = getBitfieldInvertedMaskOpValue(MI, 2, Fixups, STI);
14716
0
      Value |= (op & UINT64_C(992)) << 11;
14717
0
      Value |= (op & UINT64_C(31)) << 7;
14718
0
      break;
14719
0
    }
14720
0
    case ARM::MOVTi16: {
14721
      // op: p
14722
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14723
0
      op &= UINT64_C(15);
14724
0
      op <<= 28;
14725
0
      Value |= op;
14726
      // op: Rd
14727
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14728
0
      op &= UINT64_C(15);
14729
0
      op <<= 12;
14730
0
      Value |= op;
14731
      // op: imm
14732
0
      op = getHiLoImmOpValue(MI, 2, Fixups, STI);
14733
0
      Value |= (op & UINT64_C(61440)) << 4;
14734
0
      Value |= (op & UINT64_C(4095));
14735
0
      break;
14736
0
    }
14737
0
    case ARM::SSAT16:
14738
0
    case ARM::USAT16: {
14739
      // op: p
14740
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14741
0
      op &= UINT64_C(15);
14742
0
      op <<= 28;
14743
0
      Value |= op;
14744
      // op: Rd
14745
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14746
0
      op &= UINT64_C(15);
14747
0
      op <<= 12;
14748
0
      Value |= op;
14749
      // op: sat_imm
14750
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14751
0
      op &= UINT64_C(15);
14752
0
      op <<= 16;
14753
0
      Value |= op;
14754
      // op: Rn
14755
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14756
0
      op &= UINT64_C(15);
14757
0
      Value |= op;
14758
0
      break;
14759
0
    }
14760
0
    case ARM::SDIV:
14761
0
    case ARM::SMMUL:
14762
0
    case ARM::SMMULR:
14763
0
    case ARM::UDIV:
14764
0
    case ARM::USAD8: {
14765
      // op: p
14766
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14767
0
      op &= UINT64_C(15);
14768
0
      op <<= 28;
14769
0
      Value |= op;
14770
      // op: Rd
14771
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14772
0
      op &= UINT64_C(15);
14773
0
      op <<= 16;
14774
0
      Value |= op;
14775
      // op: Rn
14776
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14777
0
      op &= UINT64_C(15);
14778
0
      Value |= op;
14779
      // op: Rm
14780
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14781
0
      op &= UINT64_C(15);
14782
0
      op <<= 8;
14783
0
      Value |= op;
14784
0
      break;
14785
0
    }
14786
0
    case ARM::CMNzrsi:
14787
0
    case ARM::CMPrsi:
14788
0
    case ARM::TEQrsi:
14789
0
    case ARM::TSTrsi: {
14790
      // op: p
14791
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14792
0
      op &= UINT64_C(15);
14793
0
      op <<= 28;
14794
0
      Value |= op;
14795
      // op: Rn
14796
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14797
0
      op &= UINT64_C(15);
14798
0
      op <<= 16;
14799
0
      Value |= op;
14800
      // op: shift
14801
0
      op = getSORegImmOpValue(MI, 1, Fixups, STI);
14802
0
      Value |= (op & UINT64_C(4064));
14803
0
      Value |= (op & UINT64_C(15));
14804
0
      break;
14805
0
    }
14806
0
    case ARM::SMUAD:
14807
0
    case ARM::SMUADX:
14808
0
    case ARM::SMULBB:
14809
0
    case ARM::SMULBT:
14810
0
    case ARM::SMULTB:
14811
0
    case ARM::SMULTT:
14812
0
    case ARM::SMULWB:
14813
0
    case ARM::SMULWT:
14814
0
    case ARM::SMUSD:
14815
0
    case ARM::SMUSDX: {
14816
      // op: p
14817
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14818
0
      op &= UINT64_C(15);
14819
0
      op <<= 28;
14820
0
      Value |= op;
14821
      // op: Rn
14822
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14823
0
      op &= UINT64_C(15);
14824
0
      Value |= op;
14825
      // op: Rm
14826
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14827
0
      op &= UINT64_C(15);
14828
0
      op <<= 8;
14829
0
      Value |= op;
14830
      // op: Rd
14831
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14832
0
      op &= UINT64_C(15);
14833
0
      op <<= 16;
14834
0
      Value |= op;
14835
0
      break;
14836
0
    }
14837
0
    case ARM::QADD8:
14838
0
    case ARM::QADD16:
14839
0
    case ARM::QASX:
14840
0
    case ARM::QSAX:
14841
0
    case ARM::QSUB8:
14842
0
    case ARM::QSUB16:
14843
0
    case ARM::SADD8:
14844
0
    case ARM::SADD16:
14845
0
    case ARM::SASX:
14846
0
    case ARM::SHADD8:
14847
0
    case ARM::SHADD16:
14848
0
    case ARM::SHASX:
14849
0
    case ARM::SHSAX:
14850
0
    case ARM::SHSUB8:
14851
0
    case ARM::SHSUB16:
14852
0
    case ARM::SSAX:
14853
0
    case ARM::SSUB8:
14854
0
    case ARM::SSUB16:
14855
0
    case ARM::UADD8:
14856
0
    case ARM::UADD16:
14857
0
    case ARM::UASX:
14858
0
    case ARM::UHADD8:
14859
0
    case ARM::UHADD16:
14860
0
    case ARM::UHASX:
14861
0
    case ARM::UHSAX:
14862
0
    case ARM::UHSUB8:
14863
0
    case ARM::UHSUB16:
14864
0
    case ARM::UQADD8:
14865
0
    case ARM::UQADD16:
14866
0
    case ARM::UQASX:
14867
0
    case ARM::UQSAX:
14868
0
    case ARM::UQSUB8:
14869
0
    case ARM::UQSUB16:
14870
0
    case ARM::USAX:
14871
0
    case ARM::USUB8:
14872
0
    case ARM::USUB16: {
14873
      // op: p
14874
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14875
0
      op &= UINT64_C(15);
14876
0
      op <<= 28;
14877
0
      Value |= op;
14878
      // op: Rn
14879
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14880
0
      op &= UINT64_C(15);
14881
0
      op <<= 16;
14882
0
      Value |= op;
14883
      // op: Rd
14884
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14885
0
      op &= UINT64_C(15);
14886
0
      op <<= 12;
14887
0
      Value |= op;
14888
      // op: Rm
14889
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14890
0
      op &= UINT64_C(15);
14891
0
      Value |= op;
14892
0
      break;
14893
0
    }
14894
0
    case ARM::QADD:
14895
0
    case ARM::QDADD:
14896
0
    case ARM::QDSUB:
14897
0
    case ARM::QSUB: {
14898
      // op: p
14899
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14900
0
      op &= UINT64_C(15);
14901
0
      op <<= 28;
14902
0
      Value |= op;
14903
      // op: Rn
14904
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14905
0
      op &= UINT64_C(15);
14906
0
      op <<= 16;
14907
0
      Value |= op;
14908
      // op: Rd
14909
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14910
0
      op &= UINT64_C(15);
14911
0
      op <<= 12;
14912
0
      Value |= op;
14913
      // op: Rm
14914
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14915
0
      op &= UINT64_C(15);
14916
0
      Value |= op;
14917
0
      break;
14918
0
    }
14919
0
    case ARM::SWP:
14920
0
    case ARM::SWPB: {
14921
      // op: p
14922
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14923
0
      op &= UINT64_C(15);
14924
0
      op <<= 28;
14925
0
      Value |= op;
14926
      // op: Rt
14927
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14928
0
      op &= UINT64_C(15);
14929
0
      op <<= 12;
14930
0
      Value |= op;
14931
      // op: Rt2
14932
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14933
0
      op &= UINT64_C(15);
14934
0
      Value |= op;
14935
      // op: addr
14936
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14937
0
      op &= UINT64_C(15);
14938
0
      op <<= 16;
14939
0
      Value |= op;
14940
0
      break;
14941
0
    }
14942
0
    case ARM::LDRBi12:
14943
0
    case ARM::LDRi12:
14944
0
    case ARM::STRBi12:
14945
0
    case ARM::STRi12: {
14946
      // op: p
14947
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14948
0
      op &= UINT64_C(15);
14949
0
      op <<= 28;
14950
0
      Value |= op;
14951
      // op: Rt
14952
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14953
0
      op &= UINT64_C(15);
14954
0
      op <<= 12;
14955
0
      Value |= op;
14956
      // op: addr
14957
0
      op = getAddrModeImm12OpValue(MI, 1, Fixups, STI);
14958
0
      Value |= (op & UINT64_C(4096)) << 11;
14959
0
      Value |= (op & UINT64_C(122880)) << 3;
14960
0
      Value |= (op & UINT64_C(4095));
14961
0
      break;
14962
0
    }
14963
0
    case ARM::LDRcp: {
14964
      // op: p
14965
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14966
0
      op &= UINT64_C(15);
14967
0
      op <<= 28;
14968
0
      Value |= op;
14969
      // op: Rt
14970
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
14971
0
      op &= UINT64_C(15);
14972
0
      op <<= 12;
14973
0
      Value |= op;
14974
      // op: addr
14975
0
      op = getAddrModeImm12OpValue(MI, 1, Fixups, STI);
14976
0
      Value |= (op & UINT64_C(4096)) << 11;
14977
0
      Value |= (op & UINT64_C(4095));
14978
0
      break;
14979
0
    }
14980
0
    case ARM::STLEX:
14981
0
    case ARM::STLEXB:
14982
0
    case ARM::STLEXD:
14983
0
    case ARM::STLEXH:
14984
0
    case ARM::STREX:
14985
0
    case ARM::STREXB:
14986
0
    case ARM::STREXD:
14987
0
    case ARM::STREXH: {
14988
      // op: p
14989
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
14990
0
      op &= UINT64_C(15);
14991
0
      op <<= 28;
14992
0
      Value |= op;
14993
      // op: Rt
14994
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
14995
0
      op &= UINT64_C(15);
14996
0
      Value |= op;
14997
      // op: addr
14998
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
14999
0
      op &= UINT64_C(15);
15000
0
      op <<= 16;
15001
0
      Value |= op;
15002
      // op: Rd
15003
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15004
0
      op &= UINT64_C(15);
15005
0
      op <<= 12;
15006
0
      Value |= op;
15007
0
      break;
15008
0
    }
15009
0
    case ARM::BF16_VCVTB:
15010
0
    case ARM::BF16_VCVTT:
15011
0
    case ARM::VCVTBSH:
15012
0
    case ARM::VCVTTSH: {
15013
      // op: p
15014
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15015
0
      op &= UINT64_C(15);
15016
0
      op <<= 28;
15017
0
      Value |= op;
15018
      // op: Sd
15019
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15020
0
      Value |= (op & UINT64_C(1)) << 22;
15021
0
      Value |= (op & UINT64_C(30)) << 11;
15022
      // op: Sm
15023
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15024
0
      Value |= (op & UINT64_C(1)) << 5;
15025
0
      Value |= (op & UINT64_C(30)) >> 1;
15026
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
15027
0
      break;
15028
0
    }
15029
0
    case ARM::VADDH:
15030
0
    case ARM::VADDS:
15031
0
    case ARM::VDIVH:
15032
0
    case ARM::VDIVS:
15033
0
    case ARM::VMULH:
15034
0
    case ARM::VMULS:
15035
0
    case ARM::VNMULH:
15036
0
    case ARM::VNMULS:
15037
0
    case ARM::VSUBH:
15038
0
    case ARM::VSUBS: {
15039
      // op: p
15040
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15041
0
      op &= UINT64_C(15);
15042
0
      op <<= 28;
15043
0
      Value |= op;
15044
      // op: Sd
15045
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15046
0
      Value |= (op & UINT64_C(1)) << 22;
15047
0
      Value |= (op & UINT64_C(30)) << 11;
15048
      // op: Sn
15049
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15050
0
      Value |= (op & UINT64_C(30)) << 15;
15051
0
      Value |= (op & UINT64_C(1)) << 7;
15052
      // op: Sm
15053
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15054
0
      Value |= (op & UINT64_C(1)) << 5;
15055
0
      Value |= (op & UINT64_C(30)) >> 1;
15056
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
15057
0
      break;
15058
0
    }
15059
0
    case ARM::VLDRH:
15060
0
    case ARM::VSTRH: {
15061
      // op: p
15062
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15063
0
      op &= UINT64_C(15);
15064
0
      op <<= 28;
15065
0
      Value |= op;
15066
      // op: Sd
15067
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15068
0
      Value |= (op & UINT64_C(1)) << 22;
15069
0
      Value |= (op & UINT64_C(30)) << 11;
15070
      // op: addr
15071
0
      op = getAddrMode5FP16OpValue(MI, 1, Fixups, STI);
15072
0
      Value |= (op & UINT64_C(256)) << 15;
15073
0
      Value |= (op & UINT64_C(7680)) << 7;
15074
0
      Value |= (op & UINT64_C(255));
15075
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
15076
0
      break;
15077
0
    }
15078
0
    case ARM::VLDRS:
15079
0
    case ARM::VSTRS: {
15080
      // op: p
15081
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15082
0
      op &= UINT64_C(15);
15083
0
      op <<= 28;
15084
0
      Value |= op;
15085
      // op: Sd
15086
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15087
0
      Value |= (op & UINT64_C(1)) << 22;
15088
0
      Value |= (op & UINT64_C(30)) << 11;
15089
      // op: addr
15090
0
      op = getAddrMode5OpValue(MI, 1, Fixups, STI);
15091
0
      Value |= (op & UINT64_C(256)) << 15;
15092
0
      Value |= (op & UINT64_C(7680)) << 7;
15093
0
      Value |= (op & UINT64_C(255));
15094
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
15095
0
      break;
15096
0
    }
15097
0
    case ARM::VLDR_FPCXTNS_pre:
15098
0
    case ARM::VLDR_FPCXTS_pre:
15099
0
    case ARM::VLDR_FPSCR_NZCVQC_pre:
15100
0
    case ARM::VLDR_FPSCR_pre:
15101
0
    case ARM::VLDR_P0_off:
15102
0
    case ARM::VLDR_VPR_pre:
15103
0
    case ARM::VSTR_FPCXTNS_pre:
15104
0
    case ARM::VSTR_FPCXTS_pre:
15105
0
    case ARM::VSTR_FPSCR_NZCVQC_pre:
15106
0
    case ARM::VSTR_FPSCR_pre:
15107
0
    case ARM::VSTR_P0_off:
15108
0
    case ARM::VSTR_VPR_pre: {
15109
      // op: p
15110
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15111
0
      op &= UINT64_C(15);
15112
0
      op <<= 28;
15113
0
      Value |= op;
15114
      // op: addr
15115
0
      op = getT2AddrModeImm7s4OpValue(MI, 1, Fixups, STI);
15116
0
      Value |= (op & UINT64_C(128)) << 16;
15117
0
      Value |= (op & UINT64_C(3840)) << 8;
15118
0
      Value |= (op & UINT64_C(127));
15119
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
15120
0
      break;
15121
0
    }
15122
0
    case ARM::VLDR_FPCXTNS_post:
15123
0
    case ARM::VLDR_FPCXTS_post:
15124
0
    case ARM::VLDR_FPSCR_NZCVQC_post:
15125
0
    case ARM::VLDR_FPSCR_post:
15126
0
    case ARM::VLDR_VPR_post:
15127
0
    case ARM::VSTR_FPCXTNS_post:
15128
0
    case ARM::VSTR_FPCXTS_post:
15129
0
    case ARM::VSTR_FPSCR_NZCVQC_post:
15130
0
    case ARM::VSTR_FPSCR_post:
15131
0
    case ARM::VSTR_VPR_post: {
15132
      // op: p
15133
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15134
0
      op &= UINT64_C(15);
15135
0
      op <<= 28;
15136
0
      Value |= op;
15137
      // op: addr
15138
0
      op = getT2ScaledImmOpValue<7,2>(MI, 2, Fixups, STI);
15139
0
      Value |= (op & UINT64_C(128)) << 16;
15140
0
      Value |= (op & UINT64_C(127));
15141
      // op: Rn
15142
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15143
0
      op &= UINT64_C(15);
15144
0
      op <<= 16;
15145
0
      Value |= op;
15146
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
15147
0
      break;
15148
0
    }
15149
0
    case ARM::VSHTOH:
15150
0
    case ARM::VSHTOS:
15151
0
    case ARM::VSLTOH:
15152
0
    case ARM::VSLTOS:
15153
0
    case ARM::VTOSHH:
15154
0
    case ARM::VTOSHS:
15155
0
    case ARM::VTOSLH:
15156
0
    case ARM::VTOSLS:
15157
0
    case ARM::VTOUHH:
15158
0
    case ARM::VTOUHS:
15159
0
    case ARM::VTOULH:
15160
0
    case ARM::VTOULS:
15161
0
    case ARM::VUHTOH:
15162
0
    case ARM::VUHTOS:
15163
0
    case ARM::VULTOH:
15164
0
    case ARM::VULTOS: {
15165
      // op: p
15166
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15167
0
      op &= UINT64_C(15);
15168
0
      op <<= 28;
15169
0
      Value |= op;
15170
      // op: fbits
15171
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15172
0
      Value |= (op & UINT64_C(1)) << 5;
15173
0
      Value |= (op & UINT64_C(30)) >> 1;
15174
      // op: dst
15175
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15176
0
      Value |= (op & UINT64_C(1)) << 22;
15177
0
      Value |= (op & UINT64_C(30)) << 11;
15178
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
15179
0
      break;
15180
0
    }
15181
0
    case ARM::VSHTOD:
15182
0
    case ARM::VSLTOD:
15183
0
    case ARM::VTOSHD:
15184
0
    case ARM::VTOSLD:
15185
0
    case ARM::VTOUHD:
15186
0
    case ARM::VTOULD:
15187
0
    case ARM::VUHTOD:
15188
0
    case ARM::VULTOD: {
15189
      // op: p
15190
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15191
0
      op &= UINT64_C(15);
15192
0
      op <<= 28;
15193
0
      Value |= op;
15194
      // op: fbits
15195
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15196
0
      Value |= (op & UINT64_C(1)) << 5;
15197
0
      Value |= (op & UINT64_C(30)) >> 1;
15198
      // op: dst
15199
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15200
0
      Value |= (op & UINT64_C(16)) << 18;
15201
0
      Value |= (op & UINT64_C(15)) << 12;
15202
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
15203
0
      break;
15204
0
    }
15205
0
    case ARM::ADCrr:
15206
0
    case ARM::ADDrr:
15207
0
    case ARM::ANDrr:
15208
0
    case ARM::BICrr:
15209
0
    case ARM::EORrr:
15210
0
    case ARM::ORRrr:
15211
0
    case ARM::RSBrr:
15212
0
    case ARM::RSCrr:
15213
0
    case ARM::SBCrr:
15214
0
    case ARM::SUBrr: {
15215
      // op: p
15216
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15217
0
      op &= UINT64_C(15);
15218
0
      op <<= 28;
15219
0
      Value |= op;
15220
      // op: s
15221
0
      op = getCCOutOpValue(MI, 5, Fixups, STI);
15222
0
      op &= UINT64_C(1);
15223
0
      op <<= 20;
15224
0
      Value |= op;
15225
      // op: Rd
15226
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15227
0
      op &= UINT64_C(15);
15228
0
      op <<= 12;
15229
0
      Value |= op;
15230
      // op: Rn
15231
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15232
0
      op &= UINT64_C(15);
15233
0
      op <<= 16;
15234
0
      Value |= op;
15235
      // op: Rm
15236
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15237
0
      op &= UINT64_C(15);
15238
0
      Value |= op;
15239
0
      break;
15240
0
    }
15241
0
    case ARM::ADCri:
15242
0
    case ARM::ADDri:
15243
0
    case ARM::ANDri:
15244
0
    case ARM::BICri:
15245
0
    case ARM::EORri:
15246
0
    case ARM::ORRri:
15247
0
    case ARM::RSBri:
15248
0
    case ARM::RSCri:
15249
0
    case ARM::SBCri:
15250
0
    case ARM::SUBri: {
15251
      // op: p
15252
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15253
0
      op &= UINT64_C(15);
15254
0
      op <<= 28;
15255
0
      Value |= op;
15256
      // op: s
15257
0
      op = getCCOutOpValue(MI, 5, Fixups, STI);
15258
0
      op &= UINT64_C(1);
15259
0
      op <<= 20;
15260
0
      Value |= op;
15261
      // op: Rd
15262
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15263
0
      op &= UINT64_C(15);
15264
0
      op <<= 12;
15265
0
      Value |= op;
15266
      // op: Rn
15267
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15268
0
      op &= UINT64_C(15);
15269
0
      op <<= 16;
15270
0
      Value |= op;
15271
      // op: imm
15272
0
      op = getModImmOpValue(MI, 2, Fixups, STI);
15273
0
      op &= UINT64_C(4095);
15274
0
      Value |= op;
15275
0
      break;
15276
0
    }
15277
0
    case ARM::MVNsi: {
15278
      // op: p
15279
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15280
0
      op &= UINT64_C(15);
15281
0
      op <<= 28;
15282
0
      Value |= op;
15283
      // op: s
15284
0
      op = getCCOutOpValue(MI, 5, Fixups, STI);
15285
0
      op &= UINT64_C(1);
15286
0
      op <<= 20;
15287
0
      Value |= op;
15288
      // op: Rd
15289
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15290
0
      op &= UINT64_C(15);
15291
0
      op <<= 12;
15292
0
      Value |= op;
15293
      // op: shift
15294
0
      op = getSORegImmOpValue(MI, 1, Fixups, STI);
15295
0
      Value |= (op & UINT64_C(4064));
15296
0
      Value |= (op & UINT64_C(15));
15297
0
      break;
15298
0
    }
15299
0
    case ARM::MOVsi: {
15300
      // op: p
15301
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15302
0
      op &= UINT64_C(15);
15303
0
      op <<= 28;
15304
0
      Value |= op;
15305
      // op: s
15306
0
      op = getCCOutOpValue(MI, 5, Fixups, STI);
15307
0
      op &= UINT64_C(1);
15308
0
      op <<= 20;
15309
0
      Value |= op;
15310
      // op: Rd
15311
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15312
0
      op &= UINT64_C(15);
15313
0
      op <<= 12;
15314
0
      Value |= op;
15315
      // op: src
15316
0
      op = getSORegImmOpValue(MI, 1, Fixups, STI);
15317
0
      Value |= (op & UINT64_C(4064));
15318
0
      Value |= (op & UINT64_C(15));
15319
0
      break;
15320
0
    }
15321
0
    case ARM::MUL: {
15322
      // op: p
15323
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15324
0
      op &= UINT64_C(15);
15325
0
      op <<= 28;
15326
0
      Value |= op;
15327
      // op: s
15328
0
      op = getCCOutOpValue(MI, 5, Fixups, STI);
15329
0
      op &= UINT64_C(1);
15330
0
      op <<= 20;
15331
0
      Value |= op;
15332
      // op: Rd
15333
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15334
0
      op &= UINT64_C(15);
15335
0
      op <<= 16;
15336
0
      Value |= op;
15337
      // op: Rm
15338
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15339
0
      op &= UINT64_C(15);
15340
0
      op <<= 8;
15341
0
      Value |= op;
15342
      // op: Rn
15343
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15344
0
      op &= UINT64_C(15);
15345
0
      Value |= op;
15346
0
      break;
15347
0
    }
15348
0
    case ARM::VFMAD:
15349
0
    case ARM::VFMSD:
15350
0
    case ARM::VFNMAD:
15351
0
    case ARM::VFNMSD:
15352
0
    case ARM::VMLAD:
15353
0
    case ARM::VMLSD:
15354
0
    case ARM::VNMLAD:
15355
0
    case ARM::VNMLSD: {
15356
      // op: p
15357
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15358
0
      op &= UINT64_C(15);
15359
0
      op <<= 28;
15360
0
      Value |= op;
15361
      // op: Dd
15362
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15363
0
      Value |= (op & UINT64_C(16)) << 18;
15364
0
      Value |= (op & UINT64_C(15)) << 12;
15365
      // op: Dn
15366
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15367
0
      Value |= (op & UINT64_C(15)) << 16;
15368
0
      Value |= (op & UINT64_C(16)) << 3;
15369
      // op: Dm
15370
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15371
0
      Value |= (op & UINT64_C(16)) << 1;
15372
0
      Value |= (op & UINT64_C(15));
15373
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
15374
0
      break;
15375
0
    }
15376
0
    case ARM::SXTAB:
15377
0
    case ARM::SXTAB16:
15378
0
    case ARM::SXTAH:
15379
0
    case ARM::UXTAB:
15380
0
    case ARM::UXTAB16:
15381
0
    case ARM::UXTAH: {
15382
      // op: p
15383
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15384
0
      op &= UINT64_C(15);
15385
0
      op <<= 28;
15386
0
      Value |= op;
15387
      // op: Rd
15388
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15389
0
      op &= UINT64_C(15);
15390
0
      op <<= 12;
15391
0
      Value |= op;
15392
      // op: Rm
15393
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15394
0
      op &= UINT64_C(15);
15395
0
      Value |= op;
15396
      // op: Rn
15397
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15398
0
      op &= UINT64_C(15);
15399
0
      op <<= 16;
15400
0
      Value |= op;
15401
      // op: rot
15402
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15403
0
      op &= UINT64_C(3);
15404
0
      op <<= 10;
15405
0
      Value |= op;
15406
0
      break;
15407
0
    }
15408
0
    case ARM::SBFX:
15409
0
    case ARM::UBFX: {
15410
      // op: p
15411
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15412
0
      op &= UINT64_C(15);
15413
0
      op <<= 28;
15414
0
      Value |= op;
15415
      // op: Rd
15416
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15417
0
      op &= UINT64_C(15);
15418
0
      op <<= 12;
15419
0
      Value |= op;
15420
      // op: Rn
15421
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15422
0
      op &= UINT64_C(15);
15423
0
      Value |= op;
15424
      // op: lsb
15425
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15426
0
      op &= UINT64_C(31);
15427
0
      op <<= 7;
15428
0
      Value |= op;
15429
      // op: width
15430
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15431
0
      op &= UINT64_C(31);
15432
0
      op <<= 16;
15433
0
      Value |= op;
15434
0
      break;
15435
0
    }
15436
0
    case ARM::PKHBT:
15437
0
    case ARM::PKHTB: {
15438
      // op: p
15439
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15440
0
      op &= UINT64_C(15);
15441
0
      op <<= 28;
15442
0
      Value |= op;
15443
      // op: Rd
15444
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15445
0
      op &= UINT64_C(15);
15446
0
      op <<= 12;
15447
0
      Value |= op;
15448
      // op: Rn
15449
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15450
0
      op &= UINT64_C(15);
15451
0
      op <<= 16;
15452
0
      Value |= op;
15453
      // op: Rm
15454
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15455
0
      op &= UINT64_C(15);
15456
0
      Value |= op;
15457
      // op: sh
15458
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15459
0
      op &= UINT64_C(31);
15460
0
      op <<= 7;
15461
0
      Value |= op;
15462
0
      break;
15463
0
    }
15464
0
    case ARM::BFI: {
15465
      // op: p
15466
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15467
0
      op &= UINT64_C(15);
15468
0
      op <<= 28;
15469
0
      Value |= op;
15470
      // op: Rd
15471
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15472
0
      op &= UINT64_C(15);
15473
0
      op <<= 12;
15474
0
      Value |= op;
15475
      // op: Rn
15476
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15477
0
      op &= UINT64_C(15);
15478
0
      Value |= op;
15479
      // op: imm
15480
0
      op = getBitfieldInvertedMaskOpValue(MI, 3, Fixups, STI);
15481
0
      Value |= (op & UINT64_C(992)) << 11;
15482
0
      Value |= (op & UINT64_C(31)) << 7;
15483
0
      break;
15484
0
    }
15485
0
    case ARM::SSAT:
15486
0
    case ARM::USAT: {
15487
      // op: p
15488
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15489
0
      op &= UINT64_C(15);
15490
0
      op <<= 28;
15491
0
      Value |= op;
15492
      // op: Rd
15493
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15494
0
      op &= UINT64_C(15);
15495
0
      op <<= 12;
15496
0
      Value |= op;
15497
      // op: sat_imm
15498
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15499
0
      op &= UINT64_C(31);
15500
0
      op <<= 16;
15501
0
      Value |= op;
15502
      // op: Rn
15503
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15504
0
      op &= UINT64_C(15);
15505
0
      Value |= op;
15506
      // op: sh
15507
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15508
0
      Value |= (op & UINT64_C(31)) << 7;
15509
0
      Value |= (op & UINT64_C(32)) << 1;
15510
0
      break;
15511
0
    }
15512
0
    case ARM::MLS: {
15513
      // op: p
15514
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15515
0
      op &= UINT64_C(15);
15516
0
      op <<= 28;
15517
0
      Value |= op;
15518
      // op: Rd
15519
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15520
0
      op &= UINT64_C(15);
15521
0
      op <<= 16;
15522
0
      Value |= op;
15523
      // op: Rm
15524
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15525
0
      op &= UINT64_C(15);
15526
0
      op <<= 8;
15527
0
      Value |= op;
15528
      // op: Rn
15529
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15530
0
      op &= UINT64_C(15);
15531
0
      Value |= op;
15532
      // op: Ra
15533
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15534
0
      op &= UINT64_C(15);
15535
0
      op <<= 12;
15536
0
      Value |= op;
15537
0
      break;
15538
0
    }
15539
0
    case ARM::SMMLA:
15540
0
    case ARM::SMMLAR:
15541
0
    case ARM::SMMLS:
15542
0
    case ARM::SMMLSR:
15543
0
    case ARM::USADA8: {
15544
      // op: p
15545
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15546
0
      op &= UINT64_C(15);
15547
0
      op <<= 28;
15548
0
      Value |= op;
15549
      // op: Rd
15550
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15551
0
      op &= UINT64_C(15);
15552
0
      op <<= 16;
15553
0
      Value |= op;
15554
      // op: Rn
15555
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15556
0
      op &= UINT64_C(15);
15557
0
      Value |= op;
15558
      // op: Rm
15559
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15560
0
      op &= UINT64_C(15);
15561
0
      op <<= 8;
15562
0
      Value |= op;
15563
      // op: Ra
15564
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15565
0
      op &= UINT64_C(15);
15566
0
      op <<= 12;
15567
0
      Value |= op;
15568
0
      break;
15569
0
    }
15570
0
    case ARM::CMNzrsr:
15571
0
    case ARM::CMPrsr:
15572
0
    case ARM::TEQrsr:
15573
0
    case ARM::TSTrsr: {
15574
      // op: p
15575
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15576
0
      op &= UINT64_C(15);
15577
0
      op <<= 28;
15578
0
      Value |= op;
15579
      // op: Rn
15580
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15581
0
      op &= UINT64_C(15);
15582
0
      op <<= 16;
15583
0
      Value |= op;
15584
      // op: shift
15585
0
      op = getSORegRegOpValue(MI, 1, Fixups, STI);
15586
0
      Value |= (op & UINT64_C(3840));
15587
0
      Value |= (op & UINT64_C(96));
15588
0
      Value |= (op & UINT64_C(15));
15589
0
      break;
15590
0
    }
15591
0
    case ARM::SMLAD:
15592
0
    case ARM::SMLADX:
15593
0
    case ARM::SMLSD:
15594
0
    case ARM::SMLSDX: {
15595
      // op: p
15596
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15597
0
      op &= UINT64_C(15);
15598
0
      op <<= 28;
15599
0
      Value |= op;
15600
      // op: Rn
15601
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15602
0
      op &= UINT64_C(15);
15603
0
      Value |= op;
15604
      // op: Rm
15605
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15606
0
      op &= UINT64_C(15);
15607
0
      op <<= 8;
15608
0
      Value |= op;
15609
      // op: Ra
15610
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15611
0
      op &= UINT64_C(15);
15612
0
      op <<= 12;
15613
0
      Value |= op;
15614
      // op: Rd
15615
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15616
0
      op &= UINT64_C(15);
15617
0
      op <<= 16;
15618
0
      Value |= op;
15619
0
      break;
15620
0
    }
15621
0
    case ARM::SMLABB:
15622
0
    case ARM::SMLABT:
15623
0
    case ARM::SMLATB:
15624
0
    case ARM::SMLATT:
15625
0
    case ARM::SMLAWB:
15626
0
    case ARM::SMLAWT: {
15627
      // op: p
15628
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15629
0
      op &= UINT64_C(15);
15630
0
      op <<= 28;
15631
0
      Value |= op;
15632
      // op: Rn
15633
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15634
0
      op &= UINT64_C(15);
15635
0
      Value |= op;
15636
      // op: Rm
15637
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15638
0
      op &= UINT64_C(15);
15639
0
      op <<= 8;
15640
0
      Value |= op;
15641
      // op: Rd
15642
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15643
0
      op &= UINT64_C(15);
15644
0
      op <<= 16;
15645
0
      Value |= op;
15646
      // op: Ra
15647
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15648
0
      op &= UINT64_C(15);
15649
0
      op <<= 12;
15650
0
      Value |= op;
15651
0
      break;
15652
0
    }
15653
0
    case ARM::LDRB_PRE_IMM:
15654
0
    case ARM::LDR_PRE_IMM: {
15655
      // op: p
15656
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15657
0
      op &= UINT64_C(15);
15658
0
      op <<= 28;
15659
0
      Value |= op;
15660
      // op: Rt
15661
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15662
0
      op &= UINT64_C(15);
15663
0
      op <<= 12;
15664
0
      Value |= op;
15665
      // op: addr
15666
0
      op = getAddrModeImm12OpValue(MI, 2, Fixups, STI);
15667
0
      Value |= (op & UINT64_C(4096)) << 11;
15668
0
      Value |= (op & UINT64_C(122880)) << 3;
15669
0
      Value |= (op & UINT64_C(4095));
15670
0
      break;
15671
0
    }
15672
0
    case ARM::LDRBrs:
15673
0
    case ARM::LDRrs:
15674
0
    case ARM::STRBrs:
15675
0
    case ARM::STRrs: {
15676
      // op: p
15677
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15678
0
      op &= UINT64_C(15);
15679
0
      op <<= 28;
15680
0
      Value |= op;
15681
      // op: Rt
15682
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15683
0
      op &= UINT64_C(15);
15684
0
      op <<= 12;
15685
0
      Value |= op;
15686
      // op: shift
15687
0
      op = getLdStSORegOpValue(MI, 1, Fixups, STI);
15688
0
      Value |= (op & UINT64_C(4096)) << 11;
15689
0
      Value |= (op & UINT64_C(122880)) << 3;
15690
0
      Value |= (op & UINT64_C(4064));
15691
0
      Value |= (op & UINT64_C(15));
15692
0
      break;
15693
0
    }
15694
0
    case ARM::STRB_PRE_IMM:
15695
0
    case ARM::STR_PRE_IMM: {
15696
      // op: p
15697
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15698
0
      op &= UINT64_C(15);
15699
0
      op <<= 28;
15700
0
      Value |= op;
15701
      // op: Rt
15702
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15703
0
      op &= UINT64_C(15);
15704
0
      op <<= 12;
15705
0
      Value |= op;
15706
      // op: addr
15707
0
      op = getAddrModeImm12OpValue(MI, 2, Fixups, STI);
15708
0
      Value |= (op & UINT64_C(4096)) << 11;
15709
0
      Value |= (op & UINT64_C(122880)) << 3;
15710
0
      Value |= (op & UINT64_C(4095));
15711
0
      break;
15712
0
    }
15713
0
    case ARM::VFMAH:
15714
0
    case ARM::VFMAS:
15715
0
    case ARM::VFMSH:
15716
0
    case ARM::VFMSS:
15717
0
    case ARM::VFNMAH:
15718
0
    case ARM::VFNMAS:
15719
0
    case ARM::VFNMSH:
15720
0
    case ARM::VFNMSS:
15721
0
    case ARM::VMLAH:
15722
0
    case ARM::VMLAS:
15723
0
    case ARM::VMLSH:
15724
0
    case ARM::VMLSS:
15725
0
    case ARM::VNMLAH:
15726
0
    case ARM::VNMLAS:
15727
0
    case ARM::VNMLSH:
15728
0
    case ARM::VNMLSS: {
15729
      // op: p
15730
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15731
0
      op &= UINT64_C(15);
15732
0
      op <<= 28;
15733
0
      Value |= op;
15734
      // op: Sd
15735
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15736
0
      Value |= (op & UINT64_C(1)) << 22;
15737
0
      Value |= (op & UINT64_C(30)) << 11;
15738
      // op: Sn
15739
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15740
0
      Value |= (op & UINT64_C(30)) << 15;
15741
0
      Value |= (op & UINT64_C(1)) << 7;
15742
      // op: Sm
15743
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15744
0
      Value |= (op & UINT64_C(1)) << 5;
15745
0
      Value |= (op & UINT64_C(30)) >> 1;
15746
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
15747
0
      break;
15748
0
    }
15749
0
    case ARM::LDRH:
15750
0
    case ARM::LDRSB:
15751
0
    case ARM::LDRSH:
15752
0
    case ARM::STRH: {
15753
      // op: p
15754
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15755
0
      op &= UINT64_C(15);
15756
0
      op <<= 28;
15757
0
      Value |= op;
15758
      // op: addr
15759
0
      op = getAddrMode3OpValue(MI, 1, Fixups, STI);
15760
0
      Value |= (op & UINT64_C(256)) << 15;
15761
0
      Value |= (op & UINT64_C(8192)) << 9;
15762
0
      Value |= (op & UINT64_C(7680)) << 7;
15763
0
      Value |= (op & UINT64_C(240)) << 4;
15764
0
      Value |= (op & UINT64_C(15));
15765
      // op: Rt
15766
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15767
0
      op &= UINT64_C(15);
15768
0
      op <<= 12;
15769
0
      Value |= op;
15770
0
      break;
15771
0
    }
15772
0
    case ARM::LDCL_OFFSET:
15773
0
    case ARM::LDCL_PRE:
15774
0
    case ARM::LDC_OFFSET:
15775
0
    case ARM::LDC_PRE:
15776
0
    case ARM::STCL_OFFSET:
15777
0
    case ARM::STCL_PRE:
15778
0
    case ARM::STC_OFFSET:
15779
0
    case ARM::STC_PRE: {
15780
      // op: p
15781
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15782
0
      op &= UINT64_C(15);
15783
0
      op <<= 28;
15784
0
      Value |= op;
15785
      // op: addr
15786
0
      op = getAddrMode5OpValue(MI, 2, Fixups, STI);
15787
0
      Value |= (op & UINT64_C(256)) << 15;
15788
0
      Value |= (op & UINT64_C(7680)) << 7;
15789
0
      Value |= (op & UINT64_C(255));
15790
      // op: cop
15791
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15792
0
      op &= UINT64_C(15);
15793
0
      op <<= 8;
15794
0
      Value |= op;
15795
      // op: CRd
15796
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15797
0
      op &= UINT64_C(15);
15798
0
      op <<= 12;
15799
0
      Value |= op;
15800
0
      break;
15801
0
    }
15802
0
    case ARM::LDRHTi:
15803
0
    case ARM::LDRSBTi:
15804
0
    case ARM::LDRSHTi: {
15805
      // op: p
15806
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15807
0
      op &= UINT64_C(15);
15808
0
      op <<= 28;
15809
0
      Value |= op;
15810
      // op: addr
15811
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15812
0
      op &= UINT64_C(15);
15813
0
      op <<= 16;
15814
0
      Value |= op;
15815
      // op: Rt
15816
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15817
0
      op &= UINT64_C(15);
15818
0
      op <<= 12;
15819
0
      Value |= op;
15820
      // op: offset
15821
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15822
0
      Value |= (op & UINT64_C(256)) << 15;
15823
0
      Value |= (op & UINT64_C(240)) << 4;
15824
0
      Value |= (op & UINT64_C(15));
15825
0
      break;
15826
0
    }
15827
0
    case ARM::STRHTi: {
15828
      // op: p
15829
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15830
0
      op &= UINT64_C(15);
15831
0
      op <<= 28;
15832
0
      Value |= op;
15833
      // op: addr
15834
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15835
0
      op &= UINT64_C(15);
15836
0
      op <<= 16;
15837
0
      Value |= op;
15838
      // op: Rt
15839
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15840
0
      op &= UINT64_C(15);
15841
0
      op <<= 12;
15842
0
      Value |= op;
15843
      // op: offset
15844
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15845
0
      Value |= (op & UINT64_C(256)) << 15;
15846
0
      Value |= (op & UINT64_C(240)) << 4;
15847
0
      Value |= (op & UINT64_C(15));
15848
0
      break;
15849
0
    }
15850
0
    case ARM::VLDR_P0_pre:
15851
0
    case ARM::VSTR_P0_pre: {
15852
      // op: p
15853
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15854
0
      op &= UINT64_C(15);
15855
0
      op <<= 28;
15856
0
      Value |= op;
15857
      // op: addr
15858
0
      op = getT2AddrModeImm7s4OpValue(MI, 2, Fixups, STI);
15859
0
      Value |= (op & UINT64_C(128)) << 16;
15860
0
      Value |= (op & UINT64_C(3840)) << 8;
15861
0
      Value |= (op & UINT64_C(127));
15862
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
15863
0
      break;
15864
0
    }
15865
0
    case ARM::VLDR_P0_post:
15866
0
    case ARM::VSTR_P0_post: {
15867
      // op: p
15868
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15869
0
      op &= UINT64_C(15);
15870
0
      op <<= 28;
15871
0
      Value |= op;
15872
      // op: addr
15873
0
      op = getT2ScaledImmOpValue<7,2>(MI, 3, Fixups, STI);
15874
0
      Value |= (op & UINT64_C(128)) << 16;
15875
0
      Value |= (op & UINT64_C(127));
15876
      // op: Rn
15877
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15878
0
      op &= UINT64_C(15);
15879
0
      op <<= 16;
15880
0
      Value |= op;
15881
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
15882
0
      break;
15883
0
    }
15884
0
    case ARM::VMOVSRR: {
15885
      // op: p
15886
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15887
0
      op &= UINT64_C(15);
15888
0
      op <<= 28;
15889
0
      Value |= op;
15890
      // op: dst1
15891
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15892
0
      Value |= (op & UINT64_C(1)) << 5;
15893
0
      Value |= (op & UINT64_C(30)) >> 1;
15894
      // op: src1
15895
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15896
0
      op &= UINT64_C(15);
15897
0
      op <<= 12;
15898
0
      Value |= op;
15899
      // op: src2
15900
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15901
0
      op &= UINT64_C(15);
15902
0
      op <<= 16;
15903
0
      Value |= op;
15904
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
15905
0
      break;
15906
0
    }
15907
0
    case ARM::LDCL_POST:
15908
0
    case ARM::LDC_POST:
15909
0
    case ARM::STCL_POST:
15910
0
    case ARM::STC_POST: {
15911
      // op: p
15912
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15913
0
      op &= UINT64_C(15);
15914
0
      op <<= 28;
15915
0
      Value |= op;
15916
      // op: offset
15917
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15918
0
      Value |= (op & UINT64_C(256)) << 15;
15919
0
      Value |= (op & UINT64_C(255));
15920
      // op: addr
15921
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15922
0
      op &= UINT64_C(15);
15923
0
      op <<= 16;
15924
0
      Value |= op;
15925
      // op: cop
15926
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15927
0
      op &= UINT64_C(15);
15928
0
      op <<= 8;
15929
0
      Value |= op;
15930
      // op: CRd
15931
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15932
0
      op &= UINT64_C(15);
15933
0
      op <<= 12;
15934
0
      Value |= op;
15935
0
      break;
15936
0
    }
15937
0
    case ARM::LDCL_OPTION:
15938
0
    case ARM::LDC_OPTION:
15939
0
    case ARM::STCL_OPTION:
15940
0
    case ARM::STC_OPTION: {
15941
      // op: p
15942
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15943
0
      op &= UINT64_C(15);
15944
0
      op <<= 28;
15945
0
      Value |= op;
15946
      // op: option
15947
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
15948
0
      op &= UINT64_C(255);
15949
0
      Value |= op;
15950
      // op: addr
15951
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
15952
0
      op &= UINT64_C(15);
15953
0
      op <<= 16;
15954
0
      Value |= op;
15955
      // op: cop
15956
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15957
0
      op &= UINT64_C(15);
15958
0
      op <<= 8;
15959
0
      Value |= op;
15960
      // op: CRd
15961
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15962
0
      op &= UINT64_C(15);
15963
0
      op <<= 12;
15964
0
      Value |= op;
15965
0
      break;
15966
0
    }
15967
0
    case ARM::ADCrsi:
15968
0
    case ARM::ADDrsi:
15969
0
    case ARM::ANDrsi:
15970
0
    case ARM::BICrsi:
15971
0
    case ARM::EORrsi:
15972
0
    case ARM::ORRrsi:
15973
0
    case ARM::RSBrsi:
15974
0
    case ARM::RSCrsi:
15975
0
    case ARM::SBCrsi:
15976
0
    case ARM::SUBrsi: {
15977
      // op: p
15978
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
15979
0
      op &= UINT64_C(15);
15980
0
      op <<= 28;
15981
0
      Value |= op;
15982
      // op: s
15983
0
      op = getCCOutOpValue(MI, 6, Fixups, STI);
15984
0
      op &= UINT64_C(1);
15985
0
      op <<= 20;
15986
0
      Value |= op;
15987
      // op: Rd
15988
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
15989
0
      op &= UINT64_C(15);
15990
0
      op <<= 12;
15991
0
      Value |= op;
15992
      // op: Rn
15993
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
15994
0
      op &= UINT64_C(15);
15995
0
      op <<= 16;
15996
0
      Value |= op;
15997
      // op: shift
15998
0
      op = getSORegImmOpValue(MI, 2, Fixups, STI);
15999
0
      Value |= (op & UINT64_C(4064));
16000
0
      Value |= (op & UINT64_C(15));
16001
0
      break;
16002
0
    }
16003
0
    case ARM::MVNsr: {
16004
      // op: p
16005
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
16006
0
      op &= UINT64_C(15);
16007
0
      op <<= 28;
16008
0
      Value |= op;
16009
      // op: s
16010
0
      op = getCCOutOpValue(MI, 6, Fixups, STI);
16011
0
      op &= UINT64_C(1);
16012
0
      op <<= 20;
16013
0
      Value |= op;
16014
      // op: Rd
16015
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16016
0
      op &= UINT64_C(15);
16017
0
      op <<= 12;
16018
0
      Value |= op;
16019
      // op: shift
16020
0
      op = getSORegRegOpValue(MI, 1, Fixups, STI);
16021
0
      Value |= (op & UINT64_C(3840));
16022
0
      Value |= (op & UINT64_C(96));
16023
0
      Value |= (op & UINT64_C(15));
16024
0
      break;
16025
0
    }
16026
0
    case ARM::MOVsr: {
16027
      // op: p
16028
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
16029
0
      op &= UINT64_C(15);
16030
0
      op <<= 28;
16031
0
      Value |= op;
16032
      // op: s
16033
0
      op = getCCOutOpValue(MI, 6, Fixups, STI);
16034
0
      op &= UINT64_C(1);
16035
0
      op <<= 20;
16036
0
      Value |= op;
16037
      // op: Rd
16038
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16039
0
      op &= UINT64_C(15);
16040
0
      op <<= 12;
16041
0
      Value |= op;
16042
      // op: src
16043
0
      op = getSORegRegOpValue(MI, 1, Fixups, STI);
16044
0
      Value |= (op & UINT64_C(3840));
16045
0
      Value |= (op & UINT64_C(96));
16046
0
      Value |= (op & UINT64_C(15));
16047
0
      break;
16048
0
    }
16049
0
    case ARM::MLA: {
16050
      // op: p
16051
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
16052
0
      op &= UINT64_C(15);
16053
0
      op <<= 28;
16054
0
      Value |= op;
16055
      // op: s
16056
0
      op = getCCOutOpValue(MI, 6, Fixups, STI);
16057
0
      op &= UINT64_C(1);
16058
0
      op <<= 20;
16059
0
      Value |= op;
16060
      // op: Rd
16061
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16062
0
      op &= UINT64_C(15);
16063
0
      op <<= 16;
16064
0
      Value |= op;
16065
      // op: Rm
16066
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16067
0
      op &= UINT64_C(15);
16068
0
      op <<= 8;
16069
0
      Value |= op;
16070
      // op: Rn
16071
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16072
0
      op &= UINT64_C(15);
16073
0
      Value |= op;
16074
      // op: Ra
16075
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16076
0
      op &= UINT64_C(15);
16077
0
      op <<= 12;
16078
0
      Value |= op;
16079
0
      break;
16080
0
    }
16081
0
    case ARM::SMULL:
16082
0
    case ARM::UMULL: {
16083
      // op: p
16084
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
16085
0
      op &= UINT64_C(15);
16086
0
      op <<= 28;
16087
0
      Value |= op;
16088
      // op: s
16089
0
      op = getCCOutOpValue(MI, 6, Fixups, STI);
16090
0
      op &= UINT64_C(1);
16091
0
      op <<= 20;
16092
0
      Value |= op;
16093
      // op: RdLo
16094
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16095
0
      op &= UINT64_C(15);
16096
0
      op <<= 12;
16097
0
      Value |= op;
16098
      // op: RdHi
16099
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16100
0
      op &= UINT64_C(15);
16101
0
      op <<= 16;
16102
0
      Value |= op;
16103
      // op: Rm
16104
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16105
0
      op &= UINT64_C(15);
16106
0
      op <<= 8;
16107
0
      Value |= op;
16108
      // op: Rn
16109
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16110
0
      op &= UINT64_C(15);
16111
0
      Value |= op;
16112
0
      break;
16113
0
    }
16114
0
    case ARM::VMOVRRS: {
16115
      // op: p
16116
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
16117
0
      op &= UINT64_C(15);
16118
0
      op <<= 28;
16119
0
      Value |= op;
16120
      // op: src1
16121
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16122
0
      Value |= (op & UINT64_C(1)) << 5;
16123
0
      Value |= (op & UINT64_C(30)) >> 1;
16124
      // op: Rt
16125
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16126
0
      op &= UINT64_C(15);
16127
0
      op <<= 12;
16128
0
      Value |= op;
16129
      // op: Rt2
16130
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16131
0
      op &= UINT64_C(15);
16132
0
      op <<= 16;
16133
0
      Value |= op;
16134
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
16135
0
      break;
16136
0
    }
16137
0
    case ARM::MRRC: {
16138
      // op: p
16139
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16140
0
      op &= UINT64_C(15);
16141
0
      op <<= 28;
16142
0
      Value |= op;
16143
      // op: Rt
16144
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16145
0
      op &= UINT64_C(15);
16146
0
      op <<= 12;
16147
0
      Value |= op;
16148
      // op: Rt2
16149
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16150
0
      op &= UINT64_C(15);
16151
0
      op <<= 16;
16152
0
      Value |= op;
16153
      // op: cop
16154
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16155
0
      op &= UINT64_C(15);
16156
0
      op <<= 8;
16157
0
      Value |= op;
16158
      // op: opc1
16159
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16160
0
      op &= UINT64_C(15);
16161
0
      op <<= 4;
16162
0
      Value |= op;
16163
      // op: CRm
16164
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
16165
0
      op &= UINT64_C(15);
16166
0
      Value |= op;
16167
0
      break;
16168
0
    }
16169
0
    case ARM::LDRH_PRE:
16170
0
    case ARM::LDRSB_PRE:
16171
0
    case ARM::LDRSH_PRE: {
16172
      // op: p
16173
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16174
0
      op &= UINT64_C(15);
16175
0
      op <<= 28;
16176
0
      Value |= op;
16177
      // op: Rt
16178
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16179
0
      op &= UINT64_C(15);
16180
0
      op <<= 12;
16181
0
      Value |= op;
16182
      // op: addr
16183
0
      op = getAddrMode3OpValue(MI, 2, Fixups, STI);
16184
0
      Value |= (op & UINT64_C(256)) << 15;
16185
0
      Value |= (op & UINT64_C(8192)) << 9;
16186
0
      Value |= (op & UINT64_C(7680)) << 7;
16187
0
      Value |= (op & UINT64_C(240)) << 4;
16188
0
      Value |= (op & UINT64_C(15));
16189
0
      break;
16190
0
    }
16191
0
    case ARM::LDRB_PRE_REG:
16192
0
    case ARM::LDR_PRE_REG: {
16193
      // op: p
16194
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16195
0
      op &= UINT64_C(15);
16196
0
      op <<= 28;
16197
0
      Value |= op;
16198
      // op: Rt
16199
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16200
0
      op &= UINT64_C(15);
16201
0
      op <<= 12;
16202
0
      Value |= op;
16203
      // op: addr
16204
0
      op = getLdStSORegOpValue(MI, 2, Fixups, STI);
16205
0
      Value |= (op & UINT64_C(4096)) << 11;
16206
0
      Value |= (op & UINT64_C(122880)) << 3;
16207
0
      Value |= (op & UINT64_C(4064));
16208
0
      Value |= (op & UINT64_C(15));
16209
0
      break;
16210
0
    }
16211
0
    case ARM::LDRBT_POST_REG:
16212
0
    case ARM::LDRB_POST_REG:
16213
0
    case ARM::LDRT_POST_REG:
16214
0
    case ARM::LDR_POST_REG: {
16215
      // op: p
16216
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16217
0
      op &= UINT64_C(15);
16218
0
      op <<= 28;
16219
0
      Value |= op;
16220
      // op: Rt
16221
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16222
0
      op &= UINT64_C(15);
16223
0
      op <<= 12;
16224
0
      Value |= op;
16225
      // op: offset
16226
0
      op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI);
16227
0
      Value |= (op & UINT64_C(4096)) << 11;
16228
0
      Value |= (op & UINT64_C(4064));
16229
0
      Value |= (op & UINT64_C(15));
16230
      // op: addr
16231
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16232
0
      op &= UINT64_C(15);
16233
0
      op <<= 16;
16234
0
      Value |= op;
16235
0
      break;
16236
0
    }
16237
0
    case ARM::LDRBT_POST_IMM:
16238
0
    case ARM::LDRB_POST_IMM:
16239
0
    case ARM::LDRT_POST_IMM:
16240
0
    case ARM::LDR_POST_IMM: {
16241
      // op: p
16242
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16243
0
      op &= UINT64_C(15);
16244
0
      op <<= 28;
16245
0
      Value |= op;
16246
      // op: Rt
16247
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16248
0
      op &= UINT64_C(15);
16249
0
      op <<= 12;
16250
0
      Value |= op;
16251
      // op: offset
16252
0
      op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI);
16253
0
      Value |= (op & UINT64_C(4096)) << 11;
16254
0
      Value |= (op & UINT64_C(4095));
16255
      // op: addr
16256
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16257
0
      op &= UINT64_C(15);
16258
0
      op <<= 16;
16259
0
      Value |= op;
16260
0
      break;
16261
0
    }
16262
0
    case ARM::LDRH_POST:
16263
0
    case ARM::LDRSB_POST:
16264
0
    case ARM::LDRSH_POST: {
16265
      // op: p
16266
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16267
0
      op &= UINT64_C(15);
16268
0
      op <<= 28;
16269
0
      Value |= op;
16270
      // op: Rt
16271
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16272
0
      op &= UINT64_C(15);
16273
0
      op <<= 12;
16274
0
      Value |= op;
16275
      // op: offset
16276
0
      op = getAddrMode3OffsetOpValue(MI, 3, Fixups, STI);
16277
0
      Value |= (op & UINT64_C(256)) << 15;
16278
0
      Value |= (op & UINT64_C(512)) << 13;
16279
0
      Value |= (op & UINT64_C(240)) << 4;
16280
0
      Value |= (op & UINT64_C(15));
16281
      // op: addr
16282
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16283
0
      op &= UINT64_C(15);
16284
0
      op <<= 16;
16285
0
      Value |= op;
16286
0
      break;
16287
0
    }
16288
0
    case ARM::STRH_PRE: {
16289
      // op: p
16290
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16291
0
      op &= UINT64_C(15);
16292
0
      op <<= 28;
16293
0
      Value |= op;
16294
      // op: Rt
16295
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16296
0
      op &= UINT64_C(15);
16297
0
      op <<= 12;
16298
0
      Value |= op;
16299
      // op: addr
16300
0
      op = getAddrMode3OpValue(MI, 2, Fixups, STI);
16301
0
      Value |= (op & UINT64_C(256)) << 15;
16302
0
      Value |= (op & UINT64_C(8192)) << 9;
16303
0
      Value |= (op & UINT64_C(7680)) << 7;
16304
0
      Value |= (op & UINT64_C(240)) << 4;
16305
0
      Value |= (op & UINT64_C(15));
16306
0
      break;
16307
0
    }
16308
0
    case ARM::STRB_PRE_REG:
16309
0
    case ARM::STR_PRE_REG: {
16310
      // op: p
16311
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16312
0
      op &= UINT64_C(15);
16313
0
      op <<= 28;
16314
0
      Value |= op;
16315
      // op: Rt
16316
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16317
0
      op &= UINT64_C(15);
16318
0
      op <<= 12;
16319
0
      Value |= op;
16320
      // op: addr
16321
0
      op = getLdStSORegOpValue(MI, 2, Fixups, STI);
16322
0
      Value |= (op & UINT64_C(4096)) << 11;
16323
0
      Value |= (op & UINT64_C(122880)) << 3;
16324
0
      Value |= (op & UINT64_C(4064));
16325
0
      Value |= (op & UINT64_C(15));
16326
0
      break;
16327
0
    }
16328
0
    case ARM::STRBT_POST_REG:
16329
0
    case ARM::STRB_POST_REG:
16330
0
    case ARM::STRT_POST_REG:
16331
0
    case ARM::STR_POST_REG: {
16332
      // op: p
16333
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16334
0
      op &= UINT64_C(15);
16335
0
      op <<= 28;
16336
0
      Value |= op;
16337
      // op: Rt
16338
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16339
0
      op &= UINT64_C(15);
16340
0
      op <<= 12;
16341
0
      Value |= op;
16342
      // op: offset
16343
0
      op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI);
16344
0
      Value |= (op & UINT64_C(4096)) << 11;
16345
0
      Value |= (op & UINT64_C(4064));
16346
0
      Value |= (op & UINT64_C(15));
16347
      // op: addr
16348
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16349
0
      op &= UINT64_C(15);
16350
0
      op <<= 16;
16351
0
      Value |= op;
16352
0
      break;
16353
0
    }
16354
0
    case ARM::STRBT_POST_IMM:
16355
0
    case ARM::STRB_POST_IMM:
16356
0
    case ARM::STRT_POST_IMM:
16357
0
    case ARM::STR_POST_IMM: {
16358
      // op: p
16359
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16360
0
      op &= UINT64_C(15);
16361
0
      op <<= 28;
16362
0
      Value |= op;
16363
      // op: Rt
16364
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16365
0
      op &= UINT64_C(15);
16366
0
      op <<= 12;
16367
0
      Value |= op;
16368
      // op: offset
16369
0
      op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI);
16370
0
      Value |= (op & UINT64_C(4096)) << 11;
16371
0
      Value |= (op & UINT64_C(4095));
16372
      // op: addr
16373
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16374
0
      op &= UINT64_C(15);
16375
0
      op <<= 16;
16376
0
      Value |= op;
16377
0
      break;
16378
0
    }
16379
0
    case ARM::STRH_POST: {
16380
      // op: p
16381
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16382
0
      op &= UINT64_C(15);
16383
0
      op <<= 28;
16384
0
      Value |= op;
16385
      // op: Rt
16386
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16387
0
      op &= UINT64_C(15);
16388
0
      op <<= 12;
16389
0
      Value |= op;
16390
      // op: offset
16391
0
      op = getAddrMode3OffsetOpValue(MI, 3, Fixups, STI);
16392
0
      Value |= (op & UINT64_C(256)) << 15;
16393
0
      Value |= (op & UINT64_C(512)) << 13;
16394
0
      Value |= (op & UINT64_C(240)) << 4;
16395
0
      Value |= (op & UINT64_C(15));
16396
      // op: addr
16397
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16398
0
      op &= UINT64_C(15);
16399
0
      op <<= 16;
16400
0
      Value |= op;
16401
0
      break;
16402
0
    }
16403
0
    case ARM::MCRR: {
16404
      // op: p
16405
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16406
0
      op &= UINT64_C(15);
16407
0
      op <<= 28;
16408
0
      Value |= op;
16409
      // op: Rt
16410
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16411
0
      op &= UINT64_C(15);
16412
0
      op <<= 12;
16413
0
      Value |= op;
16414
      // op: Rt2
16415
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16416
0
      op &= UINT64_C(15);
16417
0
      op <<= 16;
16418
0
      Value |= op;
16419
      // op: cop
16420
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16421
0
      op &= UINT64_C(15);
16422
0
      op <<= 8;
16423
0
      Value |= op;
16424
      // op: opc1
16425
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16426
0
      op &= UINT64_C(15);
16427
0
      op <<= 4;
16428
0
      Value |= op;
16429
      // op: CRm
16430
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
16431
0
      op &= UINT64_C(15);
16432
0
      Value |= op;
16433
0
      break;
16434
0
    }
16435
0
    case ARM::LDRD:
16436
0
    case ARM::STRD: {
16437
      // op: p
16438
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16439
0
      op &= UINT64_C(15);
16440
0
      op <<= 28;
16441
0
      Value |= op;
16442
      // op: addr
16443
0
      op = getAddrMode3OpValue(MI, 2, Fixups, STI);
16444
0
      Value |= (op & UINT64_C(256)) << 15;
16445
0
      Value |= (op & UINT64_C(8192)) << 9;
16446
0
      Value |= (op & UINT64_C(7680)) << 7;
16447
0
      Value |= (op & UINT64_C(240)) << 4;
16448
0
      Value |= (op & UINT64_C(15));
16449
      // op: Rt
16450
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16451
0
      op &= UINT64_C(15);
16452
0
      op <<= 12;
16453
0
      Value |= op;
16454
0
      break;
16455
0
    }
16456
0
    case ARM::LDRHTr:
16457
0
    case ARM::LDRSBTr:
16458
0
    case ARM::LDRSHTr: {
16459
      // op: p
16460
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16461
0
      op &= UINT64_C(15);
16462
0
      op <<= 28;
16463
0
      Value |= op;
16464
      // op: addr
16465
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16466
0
      op &= UINT64_C(15);
16467
0
      op <<= 16;
16468
0
      Value |= op;
16469
      // op: Rt
16470
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16471
0
      op &= UINT64_C(15);
16472
0
      op <<= 12;
16473
0
      Value |= op;
16474
      // op: Rm
16475
0
      op = getPostIdxRegOpValue(MI, 3, Fixups, STI);
16476
0
      Value |= (op & UINT64_C(16)) << 19;
16477
0
      Value |= (op & UINT64_C(15));
16478
0
      break;
16479
0
    }
16480
0
    case ARM::STRHTr: {
16481
      // op: p
16482
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16483
0
      op &= UINT64_C(15);
16484
0
      op <<= 28;
16485
0
      Value |= op;
16486
      // op: addr
16487
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16488
0
      op &= UINT64_C(15);
16489
0
      op <<= 16;
16490
0
      Value |= op;
16491
      // op: Rt
16492
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16493
0
      op &= UINT64_C(15);
16494
0
      op <<= 12;
16495
0
      Value |= op;
16496
      // op: Rm
16497
0
      op = getPostIdxRegOpValue(MI, 3, Fixups, STI);
16498
0
      Value |= (op & UINT64_C(16)) << 19;
16499
0
      Value |= (op & UINT64_C(15));
16500
0
      break;
16501
0
    }
16502
0
    case ARM::ADCrsr:
16503
0
    case ARM::ADDrsr:
16504
0
    case ARM::ANDrsr:
16505
0
    case ARM::BICrsr:
16506
0
    case ARM::EORrsr:
16507
0
    case ARM::ORRrsr:
16508
0
    case ARM::RSBrsr:
16509
0
    case ARM::RSCrsr:
16510
0
    case ARM::SBCrsr:
16511
0
    case ARM::SUBrsr: {
16512
      // op: p
16513
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16514
0
      op &= UINT64_C(15);
16515
0
      op <<= 28;
16516
0
      Value |= op;
16517
      // op: s
16518
0
      op = getCCOutOpValue(MI, 7, Fixups, STI);
16519
0
      op &= UINT64_C(1);
16520
0
      op <<= 20;
16521
0
      Value |= op;
16522
      // op: Rd
16523
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16524
0
      op &= UINT64_C(15);
16525
0
      op <<= 12;
16526
0
      Value |= op;
16527
      // op: Rn
16528
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16529
0
      op &= UINT64_C(15);
16530
0
      op <<= 16;
16531
0
      Value |= op;
16532
      // op: shift
16533
0
      op = getSORegRegOpValue(MI, 2, Fixups, STI);
16534
0
      Value |= (op & UINT64_C(3840));
16535
0
      Value |= (op & UINT64_C(96));
16536
0
      Value |= (op & UINT64_C(15));
16537
0
      break;
16538
0
    }
16539
0
    case ARM::UMAAL: {
16540
      // op: p
16541
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
16542
0
      op &= UINT64_C(15);
16543
0
      op <<= 28;
16544
0
      Value |= op;
16545
      // op: RdLo
16546
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16547
0
      op &= UINT64_C(15);
16548
0
      op <<= 12;
16549
0
      Value |= op;
16550
      // op: RdHi
16551
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16552
0
      op &= UINT64_C(15);
16553
0
      op <<= 16;
16554
0
      Value |= op;
16555
      // op: Rm
16556
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16557
0
      op &= UINT64_C(15);
16558
0
      op <<= 8;
16559
0
      Value |= op;
16560
      // op: Rn
16561
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16562
0
      op &= UINT64_C(15);
16563
0
      Value |= op;
16564
0
      break;
16565
0
    }
16566
0
    case ARM::SMLALBB:
16567
0
    case ARM::SMLALBT:
16568
0
    case ARM::SMLALD:
16569
0
    case ARM::SMLALDX:
16570
0
    case ARM::SMLALTB:
16571
0
    case ARM::SMLALTT:
16572
0
    case ARM::SMLSLD:
16573
0
    case ARM::SMLSLDX: {
16574
      // op: p
16575
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
16576
0
      op &= UINT64_C(15);
16577
0
      op <<= 28;
16578
0
      Value |= op;
16579
      // op: Rn
16580
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16581
0
      op &= UINT64_C(15);
16582
0
      Value |= op;
16583
      // op: Rm
16584
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16585
0
      op &= UINT64_C(15);
16586
0
      op <<= 8;
16587
0
      Value |= op;
16588
      // op: RdLo
16589
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16590
0
      op &= UINT64_C(15);
16591
0
      op <<= 12;
16592
0
      Value |= op;
16593
      // op: RdHi
16594
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16595
0
      op &= UINT64_C(15);
16596
0
      op <<= 16;
16597
0
      Value |= op;
16598
0
      break;
16599
0
    }
16600
0
    case ARM::LDRD_PRE: {
16601
      // op: p
16602
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
16603
0
      op &= UINT64_C(15);
16604
0
      op <<= 28;
16605
0
      Value |= op;
16606
      // op: Rt
16607
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16608
0
      op &= UINT64_C(15);
16609
0
      op <<= 12;
16610
0
      Value |= op;
16611
      // op: addr
16612
0
      op = getAddrMode3OpValue(MI, 3, Fixups, STI);
16613
0
      Value |= (op & UINT64_C(256)) << 15;
16614
0
      Value |= (op & UINT64_C(8192)) << 9;
16615
0
      Value |= (op & UINT64_C(7680)) << 7;
16616
0
      Value |= (op & UINT64_C(240)) << 4;
16617
0
      Value |= (op & UINT64_C(15));
16618
0
      break;
16619
0
    }
16620
0
    case ARM::MRC: {
16621
      // op: p
16622
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
16623
0
      op &= UINT64_C(15);
16624
0
      op <<= 28;
16625
0
      Value |= op;
16626
      // op: Rt
16627
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16628
0
      op &= UINT64_C(15);
16629
0
      op <<= 12;
16630
0
      Value |= op;
16631
      // op: cop
16632
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16633
0
      op &= UINT64_C(15);
16634
0
      op <<= 8;
16635
0
      Value |= op;
16636
      // op: opc1
16637
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16638
0
      op &= UINT64_C(7);
16639
0
      op <<= 21;
16640
0
      Value |= op;
16641
      // op: opc2
16642
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16643
0
      op &= UINT64_C(7);
16644
0
      op <<= 5;
16645
0
      Value |= op;
16646
      // op: CRm
16647
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
16648
0
      op &= UINT64_C(15);
16649
0
      Value |= op;
16650
      // op: CRn
16651
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16652
0
      op &= UINT64_C(15);
16653
0
      op <<= 16;
16654
0
      Value |= op;
16655
0
      break;
16656
0
    }
16657
0
    case ARM::LDRD_POST: {
16658
      // op: p
16659
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
16660
0
      op &= UINT64_C(15);
16661
0
      op <<= 28;
16662
0
      Value |= op;
16663
      // op: Rt
16664
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16665
0
      op &= UINT64_C(15);
16666
0
      op <<= 12;
16667
0
      Value |= op;
16668
      // op: offset
16669
0
      op = getAddrMode3OffsetOpValue(MI, 4, Fixups, STI);
16670
0
      Value |= (op & UINT64_C(256)) << 15;
16671
0
      Value |= (op & UINT64_C(512)) << 13;
16672
0
      Value |= (op & UINT64_C(240)) << 4;
16673
0
      Value |= (op & UINT64_C(15));
16674
      // op: addr
16675
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16676
0
      op &= UINT64_C(15);
16677
0
      op <<= 16;
16678
0
      Value |= op;
16679
0
      break;
16680
0
    }
16681
0
    case ARM::STRD_PRE: {
16682
      // op: p
16683
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
16684
0
      op &= UINT64_C(15);
16685
0
      op <<= 28;
16686
0
      Value |= op;
16687
      // op: Rt
16688
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16689
0
      op &= UINT64_C(15);
16690
0
      op <<= 12;
16691
0
      Value |= op;
16692
      // op: addr
16693
0
      op = getAddrMode3OpValue(MI, 3, Fixups, STI);
16694
0
      Value |= (op & UINT64_C(256)) << 15;
16695
0
      Value |= (op & UINT64_C(8192)) << 9;
16696
0
      Value |= (op & UINT64_C(7680)) << 7;
16697
0
      Value |= (op & UINT64_C(240)) << 4;
16698
0
      Value |= (op & UINT64_C(15));
16699
0
      break;
16700
0
    }
16701
0
    case ARM::STRD_POST: {
16702
      // op: p
16703
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
16704
0
      op &= UINT64_C(15);
16705
0
      op <<= 28;
16706
0
      Value |= op;
16707
      // op: Rt
16708
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16709
0
      op &= UINT64_C(15);
16710
0
      op <<= 12;
16711
0
      Value |= op;
16712
      // op: offset
16713
0
      op = getAddrMode3OffsetOpValue(MI, 4, Fixups, STI);
16714
0
      Value |= (op & UINT64_C(256)) << 15;
16715
0
      Value |= (op & UINT64_C(512)) << 13;
16716
0
      Value |= (op & UINT64_C(240)) << 4;
16717
0
      Value |= (op & UINT64_C(15));
16718
      // op: addr
16719
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16720
0
      op &= UINT64_C(15);
16721
0
      op <<= 16;
16722
0
      Value |= op;
16723
0
      break;
16724
0
    }
16725
0
    case ARM::MCR: {
16726
      // op: p
16727
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
16728
0
      op &= UINT64_C(15);
16729
0
      op <<= 28;
16730
0
      Value |= op;
16731
      // op: Rt
16732
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16733
0
      op &= UINT64_C(15);
16734
0
      op <<= 12;
16735
0
      Value |= op;
16736
      // op: cop
16737
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16738
0
      op &= UINT64_C(15);
16739
0
      op <<= 8;
16740
0
      Value |= op;
16741
      // op: opc1
16742
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16743
0
      op &= UINT64_C(7);
16744
0
      op <<= 21;
16745
0
      Value |= op;
16746
      // op: opc2
16747
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16748
0
      op &= UINT64_C(7);
16749
0
      op <<= 5;
16750
0
      Value |= op;
16751
      // op: CRm
16752
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
16753
0
      op &= UINT64_C(15);
16754
0
      Value |= op;
16755
      // op: CRn
16756
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16757
0
      op &= UINT64_C(15);
16758
0
      op <<= 16;
16759
0
      Value |= op;
16760
0
      break;
16761
0
    }
16762
0
    case ARM::CDP: {
16763
      // op: p
16764
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
16765
0
      op &= UINT64_C(15);
16766
0
      op <<= 28;
16767
0
      Value |= op;
16768
      // op: opc1
16769
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16770
0
      op &= UINT64_C(15);
16771
0
      op <<= 20;
16772
0
      Value |= op;
16773
      // op: CRn
16774
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16775
0
      op &= UINT64_C(15);
16776
0
      op <<= 16;
16777
0
      Value |= op;
16778
      // op: CRd
16779
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16780
0
      op &= UINT64_C(15);
16781
0
      op <<= 12;
16782
0
      Value |= op;
16783
      // op: cop
16784
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16785
0
      op &= UINT64_C(15);
16786
0
      op <<= 8;
16787
0
      Value |= op;
16788
      // op: opc2
16789
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
16790
0
      op &= UINT64_C(7);
16791
0
      op <<= 5;
16792
0
      Value |= op;
16793
      // op: CRm
16794
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
16795
0
      op &= UINT64_C(15);
16796
0
      Value |= op;
16797
0
      break;
16798
0
    }
16799
0
    case ARM::SMLAL:
16800
0
    case ARM::UMLAL: {
16801
      // op: p
16802
0
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
16803
0
      op &= UINT64_C(15);
16804
0
      op <<= 28;
16805
0
      Value |= op;
16806
      // op: s
16807
0
      op = getCCOutOpValue(MI, 8, Fixups, STI);
16808
0
      op &= UINT64_C(1);
16809
0
      op <<= 20;
16810
0
      Value |= op;
16811
      // op: RdLo
16812
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16813
0
      op &= UINT64_C(15);
16814
0
      op <<= 12;
16815
0
      Value |= op;
16816
      // op: RdHi
16817
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16818
0
      op &= UINT64_C(15);
16819
0
      op <<= 16;
16820
0
      Value |= op;
16821
      // op: Rm
16822
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
16823
0
      op &= UINT64_C(15);
16824
0
      op <<= 8;
16825
0
      Value |= op;
16826
      // op: Rn
16827
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16828
0
      op &= UINT64_C(15);
16829
0
      Value |= op;
16830
0
      break;
16831
0
    }
16832
0
    case ARM::tPUSH: {
16833
      // op: regs
16834
0
      op = getRegisterListOpValue(MI, 2, Fixups, STI);
16835
0
      Value |= (op & UINT64_C(16384)) >> 6;
16836
0
      Value |= (op & UINT64_C(255));
16837
0
      break;
16838
0
    }
16839
0
    case ARM::VSCCLRMS: {
16840
      // op: regs
16841
0
      op = getRegisterListOpValue(MI, 2, Fixups, STI);
16842
0
      Value |= (op & UINT64_C(256)) << 14;
16843
0
      Value |= (op & UINT64_C(7680)) << 3;
16844
0
      Value |= (op & UINT64_C(255));
16845
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
16846
0
      break;
16847
0
    }
16848
0
    case ARM::tPOP: {
16849
      // op: regs
16850
0
      op = getRegisterListOpValue(MI, 2, Fixups, STI);
16851
0
      Value |= (op & UINT64_C(32768)) >> 7;
16852
0
      Value |= (op & UINT64_C(255));
16853
0
      break;
16854
0
    }
16855
0
    case ARM::VSCCLRMD: {
16856
      // op: regs
16857
0
      op = getRegisterListOpValue(MI, 2, Fixups, STI);
16858
0
      Value |= (op & UINT64_C(4096)) << 10;
16859
0
      Value |= (op & UINT64_C(3840)) << 4;
16860
0
      Value |= (op & UINT64_C(254));
16861
0
      Value = VFPThumb2PostEncoder(MI, Value, STI);
16862
0
      break;
16863
0
    }
16864
0
    case ARM::t2CLRM: {
16865
      // op: regs
16866
0
      op = getRegisterListOpValue(MI, 2, Fixups, STI);
16867
0
      Value |= (op & UINT64_C(49152));
16868
0
      Value |= (op & UINT64_C(8191));
16869
0
      break;
16870
0
    }
16871
0
    case ARM::t2MOVr:
16872
0
    case ARM::t2MVNr:
16873
0
    case ARM::t2RRX: {
16874
      // op: s
16875
0
      op = getCCOutOpValue(MI, 4, Fixups, STI);
16876
0
      op &= UINT64_C(1);
16877
0
      op <<= 20;
16878
0
      Value |= op;
16879
      // op: Rd
16880
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16881
0
      op &= UINT64_C(15);
16882
0
      op <<= 8;
16883
0
      Value |= op;
16884
      // op: Rm
16885
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16886
0
      op &= UINT64_C(15);
16887
0
      Value |= op;
16888
0
      break;
16889
0
    }
16890
0
    case ARM::t2MOVi:
16891
0
    case ARM::t2MVNi: {
16892
      // op: s
16893
0
      op = getCCOutOpValue(MI, 4, Fixups, STI);
16894
0
      op &= UINT64_C(1);
16895
0
      op <<= 20;
16896
0
      Value |= op;
16897
      // op: Rd
16898
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16899
0
      op &= UINT64_C(15);
16900
0
      op <<= 8;
16901
0
      Value |= op;
16902
      // op: imm
16903
0
      op = getT2SOImmOpValue(MI, 1, Fixups, STI);
16904
0
      Value |= (op & UINT64_C(2048)) << 15;
16905
0
      Value |= (op & UINT64_C(1792)) << 4;
16906
0
      Value |= (op & UINT64_C(255));
16907
0
      break;
16908
0
    }
16909
0
    case ARM::t2ASRri:
16910
0
    case ARM::t2LSLri:
16911
0
    case ARM::t2LSRri:
16912
0
    case ARM::t2RORri: {
16913
      // op: s
16914
0
      op = getCCOutOpValue(MI, 5, Fixups, STI);
16915
0
      op &= UINT64_C(1);
16916
0
      op <<= 20;
16917
0
      Value |= op;
16918
      // op: Rd
16919
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16920
0
      op &= UINT64_C(15);
16921
0
      op <<= 8;
16922
0
      Value |= op;
16923
      // op: Rm
16924
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16925
0
      op &= UINT64_C(15);
16926
0
      Value |= op;
16927
      // op: imm
16928
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16929
0
      Value |= (op & UINT64_C(28)) << 10;
16930
0
      Value |= (op & UINT64_C(3)) << 6;
16931
0
      break;
16932
0
    }
16933
0
    case ARM::t2ADCrr:
16934
0
    case ARM::t2ADDrr:
16935
0
    case ARM::t2ANDrr:
16936
0
    case ARM::t2ASRrr:
16937
0
    case ARM::t2BICrr:
16938
0
    case ARM::t2EORrr:
16939
0
    case ARM::t2LSLrr:
16940
0
    case ARM::t2LSRrr:
16941
0
    case ARM::t2ORNrr:
16942
0
    case ARM::t2ORRrr:
16943
0
    case ARM::t2RORrr:
16944
0
    case ARM::t2RSBrr:
16945
0
    case ARM::t2SBCrr:
16946
0
    case ARM::t2SUBrr: {
16947
      // op: s
16948
0
      op = getCCOutOpValue(MI, 5, Fixups, STI);
16949
0
      op &= UINT64_C(1);
16950
0
      op <<= 20;
16951
0
      Value |= op;
16952
      // op: Rd
16953
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16954
0
      op &= UINT64_C(15);
16955
0
      op <<= 8;
16956
0
      Value |= op;
16957
      // op: Rn
16958
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16959
0
      op &= UINT64_C(15);
16960
0
      op <<= 16;
16961
0
      Value |= op;
16962
      // op: Rm
16963
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
16964
0
      op &= UINT64_C(15);
16965
0
      Value |= op;
16966
0
      break;
16967
0
    }
16968
0
    case ARM::t2ADCri:
16969
0
    case ARM::t2ADDri:
16970
0
    case ARM::t2ANDri:
16971
0
    case ARM::t2BICri:
16972
0
    case ARM::t2EORri:
16973
0
    case ARM::t2ORNri:
16974
0
    case ARM::t2ORRri:
16975
0
    case ARM::t2RSBri:
16976
0
    case ARM::t2SBCri:
16977
0
    case ARM::t2SUBri: {
16978
      // op: s
16979
0
      op = getCCOutOpValue(MI, 5, Fixups, STI);
16980
0
      op &= UINT64_C(1);
16981
0
      op <<= 20;
16982
0
      Value |= op;
16983
      // op: Rd
16984
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
16985
0
      op &= UINT64_C(15);
16986
0
      op <<= 8;
16987
0
      Value |= op;
16988
      // op: Rn
16989
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
16990
0
      op &= UINT64_C(15);
16991
0
      op <<= 16;
16992
0
      Value |= op;
16993
      // op: imm
16994
0
      op = getT2SOImmOpValue(MI, 2, Fixups, STI);
16995
0
      Value |= (op & UINT64_C(2048)) << 15;
16996
0
      Value |= (op & UINT64_C(1792)) << 4;
16997
0
      Value |= (op & UINT64_C(255));
16998
0
      break;
16999
0
    }
17000
0
    case ARM::t2MVNs: {
17001
      // op: s
17002
0
      op = getCCOutOpValue(MI, 5, Fixups, STI);
17003
0
      op &= UINT64_C(1);
17004
0
      op <<= 20;
17005
0
      Value |= op;
17006
      // op: Rd
17007
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
17008
0
      op &= UINT64_C(15);
17009
0
      op <<= 8;
17010
0
      Value |= op;
17011
      // op: ShiftedRm
17012
0
      op = getT2SORegOpValue(MI, 1, Fixups, STI);
17013
0
      Value |= (op & UINT64_C(3584)) << 3;
17014
0
      Value |= (op & UINT64_C(480)) >> 1;
17015
0
      Value |= (op & UINT64_C(15));
17016
0
      break;
17017
0
    }
17018
0
    case ARM::t2ADDspImm:
17019
0
    case ARM::t2SUBspImm: {
17020
      // op: s
17021
0
      op = getCCOutOpValue(MI, 5, Fixups, STI);
17022
0
      op &= UINT64_C(1);
17023
0
      op <<= 20;
17024
0
      Value |= op;
17025
      // op: imm
17026
0
      op = getT2SOImmOpValue(MI, 2, Fixups, STI);
17027
0
      Value |= (op & UINT64_C(2048)) << 15;
17028
0
      Value |= (op & UINT64_C(1792)) << 4;
17029
0
      Value |= (op & UINT64_C(255));
17030
0
      break;
17031
0
    }
17032
0
    case ARM::t2ADCrs:
17033
0
    case ARM::t2ADDrs:
17034
0
    case ARM::t2ANDrs:
17035
0
    case ARM::t2BICrs:
17036
0
    case ARM::t2EORrs:
17037
0
    case ARM::t2ORNrs:
17038
0
    case ARM::t2ORRrs:
17039
0
    case ARM::t2RSBrs:
17040
0
    case ARM::t2SBCrs:
17041
0
    case ARM::t2SUBrs: {
17042
      // op: s
17043
0
      op = getCCOutOpValue(MI, 6, Fixups, STI);
17044
0
      op &= UINT64_C(1);
17045
0
      op <<= 20;
17046
0
      Value |= op;
17047
      // op: Rd
17048
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
17049
0
      op &= UINT64_C(15);
17050
0
      op <<= 8;
17051
0
      Value |= op;
17052
      // op: Rn
17053
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
17054
0
      op &= UINT64_C(15);
17055
0
      op <<= 16;
17056
0
      Value |= op;
17057
      // op: ShiftedRm
17058
0
      op = getT2SORegOpValue(MI, 2, Fixups, STI);
17059
0
      Value |= (op & UINT64_C(3584)) << 3;
17060
0
      Value |= (op & UINT64_C(480)) >> 1;
17061
0
      Value |= (op & UINT64_C(15));
17062
0
      break;
17063
0
    }
17064
0
    case ARM::PLDWrs:
17065
0
    case ARM::PLDrs:
17066
0
    case ARM::PLIrs: {
17067
      // op: shift
17068
0
      op = getLdStSORegOpValue(MI, 0, Fixups, STI);
17069
0
      Value |= (op & UINT64_C(4096)) << 11;
17070
0
      Value |= (op & UINT64_C(122880)) << 3;
17071
0
      Value |= (op & UINT64_C(4064));
17072
0
      Value |= (op & UINT64_C(15));
17073
0
      break;
17074
0
    }
17075
0
    case ARM::BLXi: {
17076
      // op: target
17077
0
      op = getARMBLXTargetOpValue(MI, 0, Fixups, STI);
17078
0
      Value |= (op & UINT64_C(1)) << 24;
17079
0
      Value |= (op & UINT64_C(33554430)) >> 1;
17080
0
      break;
17081
0
    }
17082
0
    case ARM::tB: {
17083
      // op: target
17084
0
      op = getThumbBRTargetOpValue(MI, 0, Fixups, STI);
17085
0
      op &= UINT64_C(2047);
17086
0
      Value |= op;
17087
0
      break;
17088
0
    }
17089
0
    case ARM::t2B: {
17090
      // op: target
17091
0
      op = getThumbBranchTargetOpValue(MI, 0, Fixups, STI);
17092
0
      Value |= (op & UINT64_C(8388608)) << 3;
17093
0
      Value |= (op & UINT64_C(2095104)) << 5;
17094
0
      Value |= (op & UINT64_C(4194304)) >> 9;
17095
0
      Value |= (op & UINT64_C(2097152)) >> 10;
17096
0
      Value |= (op & UINT64_C(2047));
17097
0
      break;
17098
0
    }
17099
0
    case ARM::tCBNZ:
17100
0
    case ARM::tCBZ: {
17101
      // op: target
17102
0
      op = getThumbCBTargetOpValue(MI, 1, Fixups, STI);
17103
0
      Value |= (op & UINT64_C(32)) << 4;
17104
0
      Value |= (op & UINT64_C(31)) << 3;
17105
      // op: Rn
17106
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
17107
0
      op &= UINT64_C(7);
17108
0
      Value |= op;
17109
0
      break;
17110
0
    }
17111
0
    case ARM::BKPT:
17112
0
    case ARM::HLT: {
17113
      // op: val
17114
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
17115
0
      Value |= (op & UINT64_C(65520)) << 4;
17116
0
      Value |= (op & UINT64_C(15));
17117
0
      break;
17118
0
    }
17119
0
    case ARM::tBKPT: {
17120
      // op: val
17121
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
17122
0
      op &= UINT64_C(255);
17123
0
      Value |= op;
17124
0
      break;
17125
0
    }
17126
0
    case ARM::tHLT: {
17127
      // op: val
17128
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
17129
0
      op &= UINT64_C(63);
17130
0
      Value |= op;
17131
0
      break;
17132
0
    }
17133
0
  default:
17134
0
    std::string msg;
17135
0
    raw_string_ostream Msg(msg);
17136
0
    Msg << "Not supported instr: " << MI;
17137
0
    report_fatal_error(Msg.str().c_str());
17138
0
  }
17139
0
  return Value;
17140
0
}
17141
17142
#ifdef GET_OPERAND_BIT_OFFSET
17143
#undef GET_OPERAND_BIT_OFFSET
17144
17145
uint32_t ARMMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
17146
    unsigned OpNum,
17147
    const MCSubtargetInfo &STI) const {
17148
  switch (MI.getOpcode()) {
17149
    case ARM::CLREX:
17150
    case ARM::MVE_LCTP:
17151
    case ARM::MVE_VPNOT:
17152
    case ARM::SB:
17153
    case ARM::TRAP:
17154
    case ARM::TRAPNaCl:
17155
    case ARM::TSB:
17156
    case ARM::VBSPd:
17157
    case ARM::VBSPq:
17158
    case ARM::VLD1LNq8Pseudo:
17159
    case ARM::VLD1LNq8Pseudo_UPD:
17160
    case ARM::VLD1LNq16Pseudo:
17161
    case ARM::VLD1LNq16Pseudo_UPD:
17162
    case ARM::VLD1LNq32Pseudo:
17163
    case ARM::VLD1LNq32Pseudo_UPD:
17164
    case ARM::VLD1d8QPseudo:
17165
    case ARM::VLD1d8QPseudoWB_fixed:
17166
    case ARM::VLD1d8QPseudoWB_register:
17167
    case ARM::VLD1d8TPseudo:
17168
    case ARM::VLD1d8TPseudoWB_fixed:
17169
    case ARM::VLD1d8TPseudoWB_register:
17170
    case ARM::VLD1d16QPseudo:
17171
    case ARM::VLD1d16QPseudoWB_fixed:
17172
    case ARM::VLD1d16QPseudoWB_register:
17173
    case ARM::VLD1d16TPseudo:
17174
    case ARM::VLD1d16TPseudoWB_fixed:
17175
    case ARM::VLD1d16TPseudoWB_register:
17176
    case ARM::VLD1d32QPseudo:
17177
    case ARM::VLD1d32QPseudoWB_fixed:
17178
    case ARM::VLD1d32QPseudoWB_register:
17179
    case ARM::VLD1d32TPseudo:
17180
    case ARM::VLD1d32TPseudoWB_fixed:
17181
    case ARM::VLD1d32TPseudoWB_register:
17182
    case ARM::VLD1d64QPseudo:
17183
    case ARM::VLD1d64QPseudoWB_fixed:
17184
    case ARM::VLD1d64QPseudoWB_register:
17185
    case ARM::VLD1d64TPseudo:
17186
    case ARM::VLD1d64TPseudoWB_fixed:
17187
    case ARM::VLD1d64TPseudoWB_register:
17188
    case ARM::VLD1q8HighQPseudo:
17189
    case ARM::VLD1q8HighQPseudo_UPD:
17190
    case ARM::VLD1q8HighTPseudo:
17191
    case ARM::VLD1q8HighTPseudo_UPD:
17192
    case ARM::VLD1q8LowQPseudo_UPD:
17193
    case ARM::VLD1q8LowTPseudo_UPD:
17194
    case ARM::VLD1q16HighQPseudo:
17195
    case ARM::VLD1q16HighQPseudo_UPD:
17196
    case ARM::VLD1q16HighTPseudo:
17197
    case ARM::VLD1q16HighTPseudo_UPD:
17198
    case ARM::VLD1q16LowQPseudo_UPD:
17199
    case ARM::VLD1q16LowTPseudo_UPD:
17200
    case ARM::VLD1q32HighQPseudo:
17201
    case ARM::VLD1q32HighQPseudo_UPD:
17202
    case ARM::VLD1q32HighTPseudo:
17203
    case ARM::VLD1q32HighTPseudo_UPD:
17204
    case ARM::VLD1q32LowQPseudo_UPD:
17205
    case ARM::VLD1q32LowTPseudo_UPD:
17206
    case ARM::VLD1q64HighQPseudo:
17207
    case ARM::VLD1q64HighQPseudo_UPD:
17208
    case ARM::VLD1q64HighTPseudo:
17209
    case ARM::VLD1q64HighTPseudo_UPD:
17210
    case ARM::VLD1q64LowQPseudo_UPD:
17211
    case ARM::VLD1q64LowTPseudo_UPD:
17212
    case ARM::VLD2DUPq8EvenPseudo:
17213
    case ARM::VLD2DUPq8OddPseudo:
17214
    case ARM::VLD2DUPq8OddPseudoWB_fixed:
17215
    case ARM::VLD2DUPq8OddPseudoWB_register:
17216
    case ARM::VLD2DUPq16EvenPseudo:
17217
    case ARM::VLD2DUPq16OddPseudo:
17218
    case ARM::VLD2DUPq16OddPseudoWB_fixed:
17219
    case ARM::VLD2DUPq16OddPseudoWB_register:
17220
    case ARM::VLD2DUPq32EvenPseudo:
17221
    case ARM::VLD2DUPq32OddPseudo:
17222
    case ARM::VLD2DUPq32OddPseudoWB_fixed:
17223
    case ARM::VLD2DUPq32OddPseudoWB_register:
17224
    case ARM::VLD2LNd8Pseudo:
17225
    case ARM::VLD2LNd8Pseudo_UPD:
17226
    case ARM::VLD2LNd16Pseudo:
17227
    case ARM::VLD2LNd16Pseudo_UPD:
17228
    case ARM::VLD2LNd32Pseudo:
17229
    case ARM::VLD2LNd32Pseudo_UPD:
17230
    case ARM::VLD2LNq16Pseudo:
17231
    case ARM::VLD2LNq16Pseudo_UPD:
17232
    case ARM::VLD2LNq32Pseudo:
17233
    case ARM::VLD2LNq32Pseudo_UPD:
17234
    case ARM::VLD2q8Pseudo:
17235
    case ARM::VLD2q8PseudoWB_fixed:
17236
    case ARM::VLD2q8PseudoWB_register:
17237
    case ARM::VLD2q16Pseudo:
17238
    case ARM::VLD2q16PseudoWB_fixed:
17239
    case ARM::VLD2q16PseudoWB_register:
17240
    case ARM::VLD2q32Pseudo:
17241
    case ARM::VLD2q32PseudoWB_fixed:
17242
    case ARM::VLD2q32PseudoWB_register:
17243
    case ARM::VLD3DUPd8Pseudo:
17244
    case ARM::VLD3DUPd8Pseudo_UPD:
17245
    case ARM::VLD3DUPd16Pseudo:
17246
    case ARM::VLD3DUPd16Pseudo_UPD:
17247
    case ARM::VLD3DUPd32Pseudo:
17248
    case ARM::VLD3DUPd32Pseudo_UPD:
17249
    case ARM::VLD3DUPq8EvenPseudo:
17250
    case ARM::VLD3DUPq8OddPseudo:
17251
    case ARM::VLD3DUPq8OddPseudo_UPD:
17252
    case ARM::VLD3DUPq16EvenPseudo:
17253
    case ARM::VLD3DUPq16OddPseudo:
17254
    case ARM::VLD3DUPq16OddPseudo_UPD:
17255
    case ARM::VLD3DUPq32EvenPseudo:
17256
    case ARM::VLD3DUPq32OddPseudo:
17257
    case ARM::VLD3DUPq32OddPseudo_UPD:
17258
    case ARM::VLD3LNd8Pseudo:
17259
    case ARM::VLD3LNd8Pseudo_UPD:
17260
    case ARM::VLD3LNd16Pseudo:
17261
    case ARM::VLD3LNd16Pseudo_UPD:
17262
    case ARM::VLD3LNd32Pseudo:
17263
    case ARM::VLD3LNd32Pseudo_UPD:
17264
    case ARM::VLD3LNq16Pseudo:
17265
    case ARM::VLD3LNq16Pseudo_UPD:
17266
    case ARM::VLD3LNq32Pseudo:
17267
    case ARM::VLD3LNq32Pseudo_UPD:
17268
    case ARM::VLD3d8Pseudo:
17269
    case ARM::VLD3d8Pseudo_UPD:
17270
    case ARM::VLD3d16Pseudo:
17271
    case ARM::VLD3d16Pseudo_UPD:
17272
    case ARM::VLD3d32Pseudo:
17273
    case ARM::VLD3d32Pseudo_UPD:
17274
    case ARM::VLD3q8Pseudo_UPD:
17275
    case ARM::VLD3q8oddPseudo:
17276
    case ARM::VLD3q8oddPseudo_UPD:
17277
    case ARM::VLD3q16Pseudo_UPD:
17278
    case ARM::VLD3q16oddPseudo:
17279
    case ARM::VLD3q16oddPseudo_UPD:
17280
    case ARM::VLD3q32Pseudo_UPD:
17281
    case ARM::VLD3q32oddPseudo:
17282
    case ARM::VLD3q32oddPseudo_UPD:
17283
    case ARM::VLD4DUPd8Pseudo:
17284
    case ARM::VLD4DUPd8Pseudo_UPD:
17285
    case ARM::VLD4DUPd16Pseudo:
17286
    case ARM::VLD4DUPd16Pseudo_UPD:
17287
    case ARM::VLD4DUPd32Pseudo:
17288
    case ARM::VLD4DUPd32Pseudo_UPD:
17289
    case ARM::VLD4DUPq8EvenPseudo:
17290
    case ARM::VLD4DUPq8OddPseudo:
17291
    case ARM::VLD4DUPq8OddPseudo_UPD:
17292
    case ARM::VLD4DUPq16EvenPseudo:
17293
    case ARM::VLD4DUPq16OddPseudo:
17294
    case ARM::VLD4DUPq16OddPseudo_UPD:
17295
    case ARM::VLD4DUPq32EvenPseudo:
17296
    case ARM::VLD4DUPq32OddPseudo:
17297
    case ARM::VLD4DUPq32OddPseudo_UPD:
17298
    case ARM::VLD4LNd8Pseudo:
17299
    case ARM::VLD4LNd8Pseudo_UPD:
17300
    case ARM::VLD4LNd16Pseudo:
17301
    case ARM::VLD4LNd16Pseudo_UPD:
17302
    case ARM::VLD4LNd32Pseudo:
17303
    case ARM::VLD4LNd32Pseudo_UPD:
17304
    case ARM::VLD4LNq16Pseudo:
17305
    case ARM::VLD4LNq16Pseudo_UPD:
17306
    case ARM::VLD4LNq32Pseudo:
17307
    case ARM::VLD4LNq32Pseudo_UPD:
17308
    case ARM::VLD4d8Pseudo:
17309
    case ARM::VLD4d8Pseudo_UPD:
17310
    case ARM::VLD4d16Pseudo:
17311
    case ARM::VLD4d16Pseudo_UPD:
17312
    case ARM::VLD4d32Pseudo:
17313
    case ARM::VLD4d32Pseudo_UPD:
17314
    case ARM::VLD4q8Pseudo_UPD:
17315
    case ARM::VLD4q8oddPseudo:
17316
    case ARM::VLD4q8oddPseudo_UPD:
17317
    case ARM::VLD4q16Pseudo_UPD:
17318
    case ARM::VLD4q16oddPseudo:
17319
    case ARM::VLD4q16oddPseudo_UPD:
17320
    case ARM::VLD4q32Pseudo_UPD:
17321
    case ARM::VLD4q32oddPseudo:
17322
    case ARM::VLD4q32oddPseudo_UPD:
17323
    case ARM::VLDMQIA:
17324
    case ARM::VST1LNq8Pseudo:
17325
    case ARM::VST1LNq8Pseudo_UPD:
17326
    case ARM::VST1LNq16Pseudo:
17327
    case ARM::VST1LNq16Pseudo_UPD:
17328
    case ARM::VST1LNq32Pseudo:
17329
    case ARM::VST1LNq32Pseudo_UPD:
17330
    case ARM::VST1d8QPseudo:
17331
    case ARM::VST1d8QPseudoWB_fixed:
17332
    case ARM::VST1d8QPseudoWB_register:
17333
    case ARM::VST1d8TPseudo:
17334
    case ARM::VST1d8TPseudoWB_fixed:
17335
    case ARM::VST1d8TPseudoWB_register:
17336
    case ARM::VST1d16QPseudo:
17337
    case ARM::VST1d16QPseudoWB_fixed:
17338
    case ARM::VST1d16QPseudoWB_register:
17339
    case ARM::VST1d16TPseudo:
17340
    case ARM::VST1d16TPseudoWB_fixed:
17341
    case ARM::VST1d16TPseudoWB_register:
17342
    case ARM::VST1d32QPseudo:
17343
    case ARM::VST1d32QPseudoWB_fixed:
17344
    case ARM::VST1d32QPseudoWB_register:
17345
    case ARM::VST1d32TPseudo:
17346
    case ARM::VST1d32TPseudoWB_fixed:
17347
    case ARM::VST1d32TPseudoWB_register:
17348
    case ARM::VST1d64QPseudo:
17349
    case ARM::VST1d64QPseudoWB_fixed:
17350
    case ARM::VST1d64QPseudoWB_register:
17351
    case ARM::VST1d64TPseudo:
17352
    case ARM::VST1d64TPseudoWB_fixed:
17353
    case ARM::VST1d64TPseudoWB_register:
17354
    case ARM::VST1q8HighQPseudo:
17355
    case ARM::VST1q8HighQPseudo_UPD:
17356
    case ARM::VST1q8HighTPseudo:
17357
    case ARM::VST1q8HighTPseudo_UPD:
17358
    case ARM::VST1q8LowQPseudo_UPD:
17359
    case ARM::VST1q8LowTPseudo_UPD:
17360
    case ARM::VST1q16HighQPseudo:
17361
    case ARM::VST1q16HighQPseudo_UPD:
17362
    case ARM::VST1q16HighTPseudo:
17363
    case ARM::VST1q16HighTPseudo_UPD:
17364
    case ARM::VST1q16LowQPseudo_UPD:
17365
    case ARM::VST1q16LowTPseudo_UPD:
17366
    case ARM::VST1q32HighQPseudo:
17367
    case ARM::VST1q32HighQPseudo_UPD:
17368
    case ARM::VST1q32HighTPseudo:
17369
    case ARM::VST1q32HighTPseudo_UPD:
17370
    case ARM::VST1q32LowQPseudo_UPD:
17371
    case ARM::VST1q32LowTPseudo_UPD:
17372
    case ARM::VST1q64HighQPseudo:
17373
    case ARM::VST1q64HighQPseudo_UPD:
17374
    case ARM::VST1q64HighTPseudo:
17375
    case ARM::VST1q64HighTPseudo_UPD:
17376
    case ARM::VST1q64LowQPseudo_UPD:
17377
    case ARM::VST1q64LowTPseudo_UPD:
17378
    case ARM::VST2LNd8Pseudo:
17379
    case ARM::VST2LNd8Pseudo_UPD:
17380
    case ARM::VST2LNd16Pseudo:
17381
    case ARM::VST2LNd16Pseudo_UPD:
17382
    case ARM::VST2LNd32Pseudo:
17383
    case ARM::VST2LNd32Pseudo_UPD:
17384
    case ARM::VST2LNq16Pseudo:
17385
    case ARM::VST2LNq16Pseudo_UPD:
17386
    case ARM::VST2LNq32Pseudo:
17387
    case ARM::VST2LNq32Pseudo_UPD:
17388
    case ARM::VST2q8Pseudo:
17389
    case ARM::VST2q8PseudoWB_fixed:
17390
    case ARM::VST2q8PseudoWB_register:
17391
    case ARM::VST2q16Pseudo:
17392
    case ARM::VST2q16PseudoWB_fixed:
17393
    case ARM::VST2q16PseudoWB_register:
17394
    case ARM::VST2q32Pseudo:
17395
    case ARM::VST2q32PseudoWB_fixed:
17396
    case ARM::VST2q32PseudoWB_register:
17397
    case ARM::VST3LNd8Pseudo:
17398
    case ARM::VST3LNd8Pseudo_UPD:
17399
    case ARM::VST3LNd16Pseudo:
17400
    case ARM::VST3LNd16Pseudo_UPD:
17401
    case ARM::VST3LNd32Pseudo:
17402
    case ARM::VST3LNd32Pseudo_UPD:
17403
    case ARM::VST3LNq16Pseudo:
17404
    case ARM::VST3LNq16Pseudo_UPD:
17405
    case ARM::VST3LNq32Pseudo:
17406
    case ARM::VST3LNq32Pseudo_UPD:
17407
    case ARM::VST3d8Pseudo:
17408
    case ARM::VST3d8Pseudo_UPD:
17409
    case ARM::VST3d16Pseudo:
17410
    case ARM::VST3d16Pseudo_UPD:
17411
    case ARM::VST3d32Pseudo:
17412
    case ARM::VST3d32Pseudo_UPD:
17413
    case ARM::VST3q8Pseudo_UPD:
17414
    case ARM::VST3q8oddPseudo:
17415
    case ARM::VST3q8oddPseudo_UPD:
17416
    case ARM::VST3q16Pseudo_UPD:
17417
    case ARM::VST3q16oddPseudo:
17418
    case ARM::VST3q16oddPseudo_UPD:
17419
    case ARM::VST3q32Pseudo_UPD:
17420
    case ARM::VST3q32oddPseudo:
17421
    case ARM::VST3q32oddPseudo_UPD:
17422
    case ARM::VST4LNd8Pseudo:
17423
    case ARM::VST4LNd8Pseudo_UPD:
17424
    case ARM::VST4LNd16Pseudo:
17425
    case ARM::VST4LNd16Pseudo_UPD:
17426
    case ARM::VST4LNd32Pseudo:
17427
    case ARM::VST4LNd32Pseudo_UPD:
17428
    case ARM::VST4LNq16Pseudo:
17429
    case ARM::VST4LNq16Pseudo_UPD:
17430
    case ARM::VST4LNq32Pseudo:
17431
    case ARM::VST4LNq32Pseudo_UPD:
17432
    case ARM::VST4d8Pseudo:
17433
    case ARM::VST4d8Pseudo_UPD:
17434
    case ARM::VST4d16Pseudo:
17435
    case ARM::VST4d16Pseudo_UPD:
17436
    case ARM::VST4d32Pseudo:
17437
    case ARM::VST4d32Pseudo_UPD:
17438
    case ARM::VST4q8Pseudo_UPD:
17439
    case ARM::VST4q8oddPseudo:
17440
    case ARM::VST4q8oddPseudo_UPD:
17441
    case ARM::VST4q16Pseudo_UPD:
17442
    case ARM::VST4q16oddPseudo:
17443
    case ARM::VST4q16oddPseudo_UPD:
17444
    case ARM::VST4q32Pseudo_UPD:
17445
    case ARM::VST4q32oddPseudo:
17446
    case ARM::VST4q32oddPseudo_UPD:
17447
    case ARM::VSTMQIA:
17448
    case ARM::VTBL3Pseudo:
17449
    case ARM::VTBL4Pseudo:
17450
    case ARM::VTBX3Pseudo:
17451
    case ARM::VTBX4Pseudo:
17452
    case ARM::t2AUT:
17453
    case ARM::t2BTI:
17454
    case ARM::t2CLREX:
17455
    case ARM::t2DCPS1:
17456
    case ARM::t2DCPS2:
17457
    case ARM::t2DCPS3:
17458
    case ARM::t2Int_eh_sjlj_setjmp:
17459
    case ARM::t2Int_eh_sjlj_setjmp_nofp:
17460
    case ARM::t2PAC:
17461
    case ARM::t2PACBTI:
17462
    case ARM::t2SB:
17463
    case ARM::t2SG:
17464
    case ARM::t2TSB:
17465
    case ARM::tInt_WIN_eh_sjlj_longjmp:
17466
    case ARM::tInt_eh_sjlj_longjmp:
17467
    case ARM::tInt_eh_sjlj_setjmp:
17468
    case ARM::tTRAP:
17469
    case ARM::t__brkdiv0: {
17470
      break;
17471
    }
17472
    case ARM::VRINTAD:
17473
    case ARM::VRINTMD:
17474
    case ARM::VRINTND:
17475
    case ARM::VRINTPD: {
17476
      switch (OpNum) {
17477
      case 0:
17478
        // op: Dd
17479
        return 12;
17480
      case 1:
17481
        // op: Dm
17482
        return 0;
17483
      }
17484
      break;
17485
    }
17486
    case ARM::VFP_VMAXNMD:
17487
    case ARM::VFP_VMINNMD:
17488
    case ARM::VSELEQD:
17489
    case ARM::VSELGED:
17490
    case ARM::VSELGTD:
17491
    case ARM::VSELVSD: {
17492
      switch (OpNum) {
17493
      case 0:
17494
        // op: Dd
17495
        return 12;
17496
      case 1:
17497
        // op: Dn
17498
        return 7;
17499
      case 2:
17500
        // op: Dm
17501
        return 0;
17502
      }
17503
      break;
17504
    }
17505
    case ARM::MVE_VPST: {
17506
      switch (OpNum) {
17507
      case 0:
17508
        // op: Mk
17509
        return 13;
17510
      }
17511
      break;
17512
    }
17513
    case ARM::MVE_VQRSHL_by_vecs8:
17514
    case ARM::MVE_VQRSHL_by_vecs16:
17515
    case ARM::MVE_VQRSHL_by_vecs32:
17516
    case ARM::MVE_VQRSHL_by_vecu8:
17517
    case ARM::MVE_VQRSHL_by_vecu16:
17518
    case ARM::MVE_VQRSHL_by_vecu32:
17519
    case ARM::MVE_VQSHL_by_vecs8:
17520
    case ARM::MVE_VQSHL_by_vecs16:
17521
    case ARM::MVE_VQSHL_by_vecs32:
17522
    case ARM::MVE_VQSHL_by_vecu8:
17523
    case ARM::MVE_VQSHL_by_vecu16:
17524
    case ARM::MVE_VQSHL_by_vecu32:
17525
    case ARM::MVE_VRSHL_by_vecs8:
17526
    case ARM::MVE_VRSHL_by_vecs16:
17527
    case ARM::MVE_VRSHL_by_vecs32:
17528
    case ARM::MVE_VRSHL_by_vecu8:
17529
    case ARM::MVE_VRSHL_by_vecu16:
17530
    case ARM::MVE_VRSHL_by_vecu32:
17531
    case ARM::MVE_VSHL_by_vecs8:
17532
    case ARM::MVE_VSHL_by_vecs16:
17533
    case ARM::MVE_VSHL_by_vecs32:
17534
    case ARM::MVE_VSHL_by_vecu8:
17535
    case ARM::MVE_VSHL_by_vecu16:
17536
    case ARM::MVE_VSHL_by_vecu32: {
17537
      switch (OpNum) {
17538
      case 0:
17539
        // op: Qd
17540
        return 13;
17541
      case 1:
17542
        // op: Qm
17543
        return 1;
17544
      case 2:
17545
        // op: Qn
17546
        return 7;
17547
      }
17548
      break;
17549
    }
17550
    case ARM::MVE_VQSHLU_imms8:
17551
    case ARM::MVE_VQSHLU_imms16:
17552
    case ARM::MVE_VQSHLU_imms32:
17553
    case ARM::MVE_VQSHLimms8:
17554
    case ARM::MVE_VQSHLimms16:
17555
    case ARM::MVE_VQSHLimms32:
17556
    case ARM::MVE_VQSHLimmu8:
17557
    case ARM::MVE_VQSHLimmu16:
17558
    case ARM::MVE_VQSHLimmu32:
17559
    case ARM::MVE_VRSHR_imms8:
17560
    case ARM::MVE_VRSHR_imms16:
17561
    case ARM::MVE_VRSHR_imms32:
17562
    case ARM::MVE_VRSHR_immu8:
17563
    case ARM::MVE_VRSHR_immu16:
17564
    case ARM::MVE_VRSHR_immu32:
17565
    case ARM::MVE_VSHLL_imms8bh:
17566
    case ARM::MVE_VSHLL_imms8th:
17567
    case ARM::MVE_VSHLL_imms16bh:
17568
    case ARM::MVE_VSHLL_imms16th:
17569
    case ARM::MVE_VSHLL_immu8bh:
17570
    case ARM::MVE_VSHLL_immu8th:
17571
    case ARM::MVE_VSHLL_immu16bh:
17572
    case ARM::MVE_VSHLL_immu16th:
17573
    case ARM::MVE_VSHL_immi8:
17574
    case ARM::MVE_VSHL_immi16:
17575
    case ARM::MVE_VSHL_immi32:
17576
    case ARM::MVE_VSHR_imms8:
17577
    case ARM::MVE_VSHR_imms16:
17578
    case ARM::MVE_VSHR_imms32:
17579
    case ARM::MVE_VSHR_immu8:
17580
    case ARM::MVE_VSHR_immu16:
17581
    case ARM::MVE_VSHR_immu32: {
17582
      switch (OpNum) {
17583
      case 0:
17584
        // op: Qd
17585
        return 13;
17586
      case 1:
17587
        // op: Qm
17588
        return 1;
17589
      case 2:
17590
        // op: imm
17591
        return 16;
17592
      }
17593
      break;
17594
    }
17595
    case ARM::MVE_VABSs8:
17596
    case ARM::MVE_VABSs16:
17597
    case ARM::MVE_VABSs32:
17598
    case ARM::MVE_VCLSs8:
17599
    case ARM::MVE_VCLSs16:
17600
    case ARM::MVE_VCLSs32:
17601
    case ARM::MVE_VCLZs8:
17602
    case ARM::MVE_VCLZs16:
17603
    case ARM::MVE_VCLZs32:
17604
    case ARM::MVE_VCVTf32f16bh:
17605
    case ARM::MVE_VCVTf32f16th:
17606
    case ARM::MVE_VMOVLs8bh:
17607
    case ARM::MVE_VMOVLs8th:
17608
    case ARM::MVE_VMOVLs16bh:
17609
    case ARM::MVE_VMOVLs16th:
17610
    case ARM::MVE_VMOVLu8bh:
17611
    case ARM::MVE_VMOVLu8th:
17612
    case ARM::MVE_VMOVLu16bh:
17613
    case ARM::MVE_VMOVLu16th:
17614
    case ARM::MVE_VMVN:
17615
    case ARM::MVE_VNEGs8:
17616
    case ARM::MVE_VNEGs16:
17617
    case ARM::MVE_VNEGs32:
17618
    case ARM::MVE_VQABSs8:
17619
    case ARM::MVE_VQABSs16:
17620
    case ARM::MVE_VQABSs32:
17621
    case ARM::MVE_VQNEGs8:
17622
    case ARM::MVE_VQNEGs16:
17623
    case ARM::MVE_VQNEGs32:
17624
    case ARM::MVE_VREV16_8:
17625
    case ARM::MVE_VREV32_8:
17626
    case ARM::MVE_VREV32_16:
17627
    case ARM::MVE_VREV64_8:
17628
    case ARM::MVE_VREV64_16:
17629
    case ARM::MVE_VREV64_32:
17630
    case ARM::MVE_VSHLL_lws8bh:
17631
    case ARM::MVE_VSHLL_lws8th:
17632
    case ARM::MVE_VSHLL_lws16bh:
17633
    case ARM::MVE_VSHLL_lws16th:
17634
    case ARM::MVE_VSHLL_lwu8bh:
17635
    case ARM::MVE_VSHLL_lwu8th:
17636
    case ARM::MVE_VSHLL_lwu16bh:
17637
    case ARM::MVE_VSHLL_lwu16th: {
17638
      switch (OpNum) {
17639
      case 0:
17640
        // op: Qd
17641
        return 13;
17642
      case 1:
17643
        // op: Qm
17644
        return 1;
17645
      }
17646
      break;
17647
    }
17648
    case ARM::MVE_VABDs8:
17649
    case ARM::MVE_VABDs16:
17650
    case ARM::MVE_VABDs32:
17651
    case ARM::MVE_VABDu8:
17652
    case ARM::MVE_VABDu16:
17653
    case ARM::MVE_VABDu32:
17654
    case ARM::MVE_VADDi8:
17655
    case ARM::MVE_VADDi16:
17656
    case ARM::MVE_VADDi32:
17657
    case ARM::MVE_VHADDs8:
17658
    case ARM::MVE_VHADDs16:
17659
    case ARM::MVE_VHADDs32:
17660
    case ARM::MVE_VHADDu8:
17661
    case ARM::MVE_VHADDu16:
17662
    case ARM::MVE_VHADDu32:
17663
    case ARM::MVE_VHSUBs8:
17664
    case ARM::MVE_VHSUBs16:
17665
    case ARM::MVE_VHSUBs32:
17666
    case ARM::MVE_VHSUBu8:
17667
    case ARM::MVE_VHSUBu16:
17668
    case ARM::MVE_VHSUBu32:
17669
    case ARM::MVE_VMAXNMf16:
17670
    case ARM::MVE_VMAXNMf32:
17671
    case ARM::MVE_VMAXs8:
17672
    case ARM::MVE_VMAXs16:
17673
    case ARM::MVE_VMAXs32:
17674
    case ARM::MVE_VMAXu8:
17675
    case ARM::MVE_VMAXu16:
17676
    case ARM::MVE_VMAXu32:
17677
    case ARM::MVE_VMINNMf16:
17678
    case ARM::MVE_VMINNMf32:
17679
    case ARM::MVE_VMINs8:
17680
    case ARM::MVE_VMINs16:
17681
    case ARM::MVE_VMINs32:
17682
    case ARM::MVE_VMINu8:
17683
    case ARM::MVE_VMINu16:
17684
    case ARM::MVE_VMINu32:
17685
    case ARM::MVE_VMULi8:
17686
    case ARM::MVE_VMULi16:
17687
    case ARM::MVE_VMULi32:
17688
    case ARM::MVE_VQADDs8:
17689
    case ARM::MVE_VQADDs16:
17690
    case ARM::MVE_VQADDs32:
17691
    case ARM::MVE_VQADDu8:
17692
    case ARM::MVE_VQADDu16:
17693
    case ARM::MVE_VQADDu32:
17694
    case ARM::MVE_VQDMULHi8:
17695
    case ARM::MVE_VQDMULHi16:
17696
    case ARM::MVE_VQDMULHi32:
17697
    case ARM::MVE_VQRDMULHi8:
17698
    case ARM::MVE_VQRDMULHi16:
17699
    case ARM::MVE_VQRDMULHi32:
17700
    case ARM::MVE_VQSUBs8:
17701
    case ARM::MVE_VQSUBs16:
17702
    case ARM::MVE_VQSUBs32:
17703
    case ARM::MVE_VQSUBu8:
17704
    case ARM::MVE_VQSUBu16:
17705
    case ARM::MVE_VQSUBu32:
17706
    case ARM::MVE_VRHADDs8:
17707
    case ARM::MVE_VRHADDs16:
17708
    case ARM::MVE_VRHADDs32:
17709
    case ARM::MVE_VRHADDu8:
17710
    case ARM::MVE_VRHADDu16:
17711
    case ARM::MVE_VRHADDu32:
17712
    case ARM::MVE_VSUBi8:
17713
    case ARM::MVE_VSUBi16:
17714
    case ARM::MVE_VSUBi32: {
17715
      switch (OpNum) {
17716
      case 0:
17717
        // op: Qd
17718
        return 13;
17719
      case 1:
17720
        // op: Qn
17721
        return 7;
17722
      case 2:
17723
        // op: Qm
17724
        return 1;
17725
      }
17726
      break;
17727
    }
17728
    case ARM::MVE_VADD_qr_f16:
17729
    case ARM::MVE_VADD_qr_f32:
17730
    case ARM::MVE_VADD_qr_i8:
17731
    case ARM::MVE_VADD_qr_i16:
17732
    case ARM::MVE_VADD_qr_i32:
17733
    case ARM::MVE_VBRSR8:
17734
    case ARM::MVE_VBRSR16:
17735
    case ARM::MVE_VBRSR32:
17736
    case ARM::MVE_VHADD_qr_s8:
17737
    case ARM::MVE_VHADD_qr_s16:
17738
    case ARM::MVE_VHADD_qr_s32:
17739
    case ARM::MVE_VHADD_qr_u8:
17740
    case ARM::MVE_VHADD_qr_u16:
17741
    case ARM::MVE_VHADD_qr_u32:
17742
    case ARM::MVE_VHSUB_qr_s8:
17743
    case ARM::MVE_VHSUB_qr_s16:
17744
    case ARM::MVE_VHSUB_qr_s32:
17745
    case ARM::MVE_VHSUB_qr_u8:
17746
    case ARM::MVE_VHSUB_qr_u16:
17747
    case ARM::MVE_VHSUB_qr_u32:
17748
    case ARM::MVE_VMUL_qr_f16:
17749
    case ARM::MVE_VMUL_qr_f32:
17750
    case ARM::MVE_VMUL_qr_i8:
17751
    case ARM::MVE_VMUL_qr_i16:
17752
    case ARM::MVE_VMUL_qr_i32:
17753
    case ARM::MVE_VQADD_qr_s8:
17754
    case ARM::MVE_VQADD_qr_s16:
17755
    case ARM::MVE_VQADD_qr_s32:
17756
    case ARM::MVE_VQADD_qr_u8:
17757
    case ARM::MVE_VQADD_qr_u16:
17758
    case ARM::MVE_VQADD_qr_u32:
17759
    case ARM::MVE_VQDMULH_qr_s8:
17760
    case ARM::MVE_VQDMULH_qr_s16:
17761
    case ARM::MVE_VQDMULH_qr_s32:
17762
    case ARM::MVE_VQDMULL_qr_s16bh:
17763
    case ARM::MVE_VQDMULL_qr_s16th:
17764
    case ARM::MVE_VQDMULL_qr_s32bh:
17765
    case ARM::MVE_VQDMULL_qr_s32th:
17766
    case ARM::MVE_VQRDMULH_qr_s8:
17767
    case ARM::MVE_VQRDMULH_qr_s16:
17768
    case ARM::MVE_VQRDMULH_qr_s32:
17769
    case ARM::MVE_VQSUB_qr_s8:
17770
    case ARM::MVE_VQSUB_qr_s16:
17771
    case ARM::MVE_VQSUB_qr_s32:
17772
    case ARM::MVE_VQSUB_qr_u8:
17773
    case ARM::MVE_VQSUB_qr_u16:
17774
    case ARM::MVE_VQSUB_qr_u32:
17775
    case ARM::MVE_VSUB_qr_f16:
17776
    case ARM::MVE_VSUB_qr_f32:
17777
    case ARM::MVE_VSUB_qr_i8:
17778
    case ARM::MVE_VSUB_qr_i16:
17779
    case ARM::MVE_VSUB_qr_i32: {
17780
      switch (OpNum) {
17781
      case 0:
17782
        // op: Qd
17783
        return 13;
17784
      case 1:
17785
        // op: Qn
17786
        return 7;
17787
      case 2:
17788
        // op: Rm
17789
        return 0;
17790
      }
17791
      break;
17792
    }
17793
    case ARM::MVE_VDDUPu8:
17794
    case ARM::MVE_VDDUPu16:
17795
    case ARM::MVE_VDDUPu32:
17796
    case ARM::MVE_VIDUPu8:
17797
    case ARM::MVE_VIDUPu16:
17798
    case ARM::MVE_VIDUPu32: {
17799
      switch (OpNum) {
17800
      case 0:
17801
        // op: Qd
17802
        return 13;
17803
      case 1:
17804
        // op: Rn
17805
        return 17;
17806
      case 3:
17807
        // op: imm
17808
        return 0;
17809
      }
17810
      break;
17811
    }
17812
    case ARM::MVE_VLDRBS16:
17813
    case ARM::MVE_VLDRBS32:
17814
    case ARM::MVE_VLDRBU8:
17815
    case ARM::MVE_VLDRBU16:
17816
    case ARM::MVE_VLDRBU32:
17817
    case ARM::MVE_VLDRDU64_qi:
17818
    case ARM::MVE_VLDRHS32:
17819
    case ARM::MVE_VLDRHU16:
17820
    case ARM::MVE_VLDRHU32:
17821
    case ARM::MVE_VLDRWU32:
17822
    case ARM::MVE_VLDRWU32_qi:
17823
    case ARM::MVE_VSTRB16:
17824
    case ARM::MVE_VSTRB32:
17825
    case ARM::MVE_VSTRBU8:
17826
    case ARM::MVE_VSTRD64_qi:
17827
    case ARM::MVE_VSTRH32:
17828
    case ARM::MVE_VSTRHU16:
17829
    case ARM::MVE_VSTRW32_qi:
17830
    case ARM::MVE_VSTRWU32: {
17831
      switch (OpNum) {
17832
      case 0:
17833
        // op: Qd
17834
        return 13;
17835
      case 1:
17836
        // op: addr
17837
        return 0;
17838
      }
17839
      break;
17840
    }
17841
    case ARM::MVE_VLDRBS16_rq:
17842
    case ARM::MVE_VLDRBS32_rq:
17843
    case ARM::MVE_VLDRBU8_rq:
17844
    case ARM::MVE_VLDRBU16_rq:
17845
    case ARM::MVE_VLDRBU32_rq:
17846
    case ARM::MVE_VLDRDU64_rq:
17847
    case ARM::MVE_VLDRDU64_rq_u:
17848
    case ARM::MVE_VLDRHS32_rq:
17849
    case ARM::MVE_VLDRHS32_rq_u:
17850
    case ARM::MVE_VLDRHU16_rq:
17851
    case ARM::MVE_VLDRHU16_rq_u:
17852
    case ARM::MVE_VLDRHU32_rq:
17853
    case ARM::MVE_VLDRHU32_rq_u:
17854
    case ARM::MVE_VLDRWU32_rq:
17855
    case ARM::MVE_VLDRWU32_rq_u:
17856
    case ARM::MVE_VSTRB8_rq:
17857
    case ARM::MVE_VSTRB16_rq:
17858
    case ARM::MVE_VSTRB32_rq:
17859
    case ARM::MVE_VSTRD64_rq:
17860
    case ARM::MVE_VSTRD64_rq_u:
17861
    case ARM::MVE_VSTRH16_rq:
17862
    case ARM::MVE_VSTRH16_rq_u:
17863
    case ARM::MVE_VSTRH32_rq:
17864
    case ARM::MVE_VSTRH32_rq_u:
17865
    case ARM::MVE_VSTRW32_rq:
17866
    case ARM::MVE_VSTRW32_rq_u: {
17867
      switch (OpNum) {
17868
      case 0:
17869
        // op: Qd
17870
        return 13;
17871
      case 1:
17872
        // op: addr
17873
        return 1;
17874
      }
17875
      break;
17876
    }
17877
    case ARM::MVE_VCMULf16:
17878
    case ARM::MVE_VCMULf32: {
17879
      switch (OpNum) {
17880
      case 0:
17881
        // op: Qd
17882
        return 13;
17883
      case 2:
17884
        // op: Qm
17885
        return 1;
17886
      case 1:
17887
        // op: Qn
17888
        return 7;
17889
      case 3:
17890
        // op: rot
17891
        return 0;
17892
      }
17893
      break;
17894
    }
17895
    case ARM::MVE_VCADDi8:
17896
    case ARM::MVE_VCADDi16:
17897
    case ARM::MVE_VCADDi32:
17898
    case ARM::MVE_VHCADDs8:
17899
    case ARM::MVE_VHCADDs16:
17900
    case ARM::MVE_VHCADDs32: {
17901
      switch (OpNum) {
17902
      case 0:
17903
        // op: Qd
17904
        return 13;
17905
      case 2:
17906
        // op: Qm
17907
        return 1;
17908
      case 1:
17909
        // op: Qn
17910
        return 7;
17911
      case 3:
17912
        // op: rot
17913
        return 12;
17914
      }
17915
      break;
17916
    }
17917
    case ARM::MVE_VAND:
17918
    case ARM::MVE_VBIC:
17919
    case ARM::MVE_VEOR:
17920
    case ARM::MVE_VMULHs8:
17921
    case ARM::MVE_VMULHs16:
17922
    case ARM::MVE_VMULHs32:
17923
    case ARM::MVE_VMULHu8:
17924
    case ARM::MVE_VMULHu16:
17925
    case ARM::MVE_VMULHu32:
17926
    case ARM::MVE_VMULLBp8:
17927
    case ARM::MVE_VMULLBp16:
17928
    case ARM::MVE_VMULLBs8:
17929
    case ARM::MVE_VMULLBs16:
17930
    case ARM::MVE_VMULLBs32:
17931
    case ARM::MVE_VMULLBu8:
17932
    case ARM::MVE_VMULLBu16:
17933
    case ARM::MVE_VMULLBu32:
17934
    case ARM::MVE_VMULLTp8:
17935
    case ARM::MVE_VMULLTp16:
17936
    case ARM::MVE_VMULLTs8:
17937
    case ARM::MVE_VMULLTs16:
17938
    case ARM::MVE_VMULLTs32:
17939
    case ARM::MVE_VMULLTu8:
17940
    case ARM::MVE_VMULLTu16:
17941
    case ARM::MVE_VMULLTu32:
17942
    case ARM::MVE_VORN:
17943
    case ARM::MVE_VORR:
17944
    case ARM::MVE_VQDMULLs16bh:
17945
    case ARM::MVE_VQDMULLs16th:
17946
    case ARM::MVE_VQDMULLs32bh:
17947
    case ARM::MVE_VQDMULLs32th:
17948
    case ARM::MVE_VRMULHs8:
17949
    case ARM::MVE_VRMULHs16:
17950
    case ARM::MVE_VRMULHs32:
17951
    case ARM::MVE_VRMULHu8:
17952
    case ARM::MVE_VRMULHu16:
17953
    case ARM::MVE_VRMULHu32: {
17954
      switch (OpNum) {
17955
      case 0:
17956
        // op: Qd
17957
        return 13;
17958
      case 2:
17959
        // op: Qm
17960
        return 1;
17961
      case 1:
17962
        // op: Qn
17963
        return 7;
17964
      }
17965
      break;
17966
    }
17967
    case ARM::MVE_VQRSHRNbhs16:
17968
    case ARM::MVE_VQRSHRNbhs32:
17969
    case ARM::MVE_VQRSHRNbhu16:
17970
    case ARM::MVE_VQRSHRNbhu32:
17971
    case ARM::MVE_VQRSHRNths16:
17972
    case ARM::MVE_VQRSHRNths32:
17973
    case ARM::MVE_VQRSHRNthu16:
17974
    case ARM::MVE_VQRSHRNthu32:
17975
    case ARM::MVE_VQRSHRUNs16bh:
17976
    case ARM::MVE_VQRSHRUNs16th:
17977
    case ARM::MVE_VQRSHRUNs32bh:
17978
    case ARM::MVE_VQRSHRUNs32th:
17979
    case ARM::MVE_VQSHRNbhs16:
17980
    case ARM::MVE_VQSHRNbhs32:
17981
    case ARM::MVE_VQSHRNbhu16:
17982
    case ARM::MVE_VQSHRNbhu32:
17983
    case ARM::MVE_VQSHRNths16:
17984
    case ARM::MVE_VQSHRNths32:
17985
    case ARM::MVE_VQSHRNthu16:
17986
    case ARM::MVE_VQSHRNthu32:
17987
    case ARM::MVE_VQSHRUNs16bh:
17988
    case ARM::MVE_VQSHRUNs16th:
17989
    case ARM::MVE_VQSHRUNs32bh:
17990
    case ARM::MVE_VQSHRUNs32th:
17991
    case ARM::MVE_VRSHRNi16bh:
17992
    case ARM::MVE_VRSHRNi16th:
17993
    case ARM::MVE_VRSHRNi32bh:
17994
    case ARM::MVE_VRSHRNi32th:
17995
    case ARM::MVE_VSHRNi16bh:
17996
    case ARM::MVE_VSHRNi16th:
17997
    case ARM::MVE_VSHRNi32bh:
17998
    case ARM::MVE_VSHRNi32th:
17999
    case ARM::MVE_VSLIimm8:
18000
    case ARM::MVE_VSLIimm16:
18001
    case ARM::MVE_VSLIimm32:
18002
    case ARM::MVE_VSRIimm8:
18003
    case ARM::MVE_VSRIimm16:
18004
    case ARM::MVE_VSRIimm32: {
18005
      switch (OpNum) {
18006
      case 0:
18007
        // op: Qd
18008
        return 13;
18009
      case 2:
18010
        // op: Qm
18011
        return 1;
18012
      case 3:
18013
        // op: imm
18014
        return 16;
18015
      }
18016
      break;
18017
    }
18018
    case ARM::MVE_VCVTf16f32bh:
18019
    case ARM::MVE_VCVTf16f32th:
18020
    case ARM::MVE_VMAXAs8:
18021
    case ARM::MVE_VMAXAs16:
18022
    case ARM::MVE_VMAXAs32:
18023
    case ARM::MVE_VMAXNMAf16:
18024
    case ARM::MVE_VMAXNMAf32:
18025
    case ARM::MVE_VMINAs8:
18026
    case ARM::MVE_VMINAs16:
18027
    case ARM::MVE_VMINAs32:
18028
    case ARM::MVE_VMINNMAf16:
18029
    case ARM::MVE_VMINNMAf32:
18030
    case ARM::MVE_VMOVNi16bh:
18031
    case ARM::MVE_VMOVNi16th:
18032
    case ARM::MVE_VMOVNi32bh:
18033
    case ARM::MVE_VMOVNi32th:
18034
    case ARM::MVE_VQMOVNs16bh:
18035
    case ARM::MVE_VQMOVNs16th:
18036
    case ARM::MVE_VQMOVNs32bh:
18037
    case ARM::MVE_VQMOVNs32th:
18038
    case ARM::MVE_VQMOVNu16bh:
18039
    case ARM::MVE_VQMOVNu16th:
18040
    case ARM::MVE_VQMOVNu32bh:
18041
    case ARM::MVE_VQMOVNu32th:
18042
    case ARM::MVE_VQMOVUNs16bh:
18043
    case ARM::MVE_VQMOVUNs16th:
18044
    case ARM::MVE_VQMOVUNs32bh:
18045
    case ARM::MVE_VQMOVUNs32th: {
18046
      switch (OpNum) {
18047
      case 0:
18048
        // op: Qd
18049
        return 13;
18050
      case 2:
18051
        // op: Qm
18052
        return 1;
18053
      }
18054
      break;
18055
    }
18056
    case ARM::MVE_VFMA_qr_Sf16:
18057
    case ARM::MVE_VFMA_qr_Sf32:
18058
    case ARM::MVE_VFMA_qr_f16:
18059
    case ARM::MVE_VFMA_qr_f32:
18060
    case ARM::MVE_VMLAS_qr_i8:
18061
    case ARM::MVE_VMLAS_qr_i16:
18062
    case ARM::MVE_VMLAS_qr_i32:
18063
    case ARM::MVE_VMLA_qr_i8:
18064
    case ARM::MVE_VMLA_qr_i16:
18065
    case ARM::MVE_VMLA_qr_i32:
18066
    case ARM::MVE_VQDMLAH_qrs8:
18067
    case ARM::MVE_VQDMLAH_qrs16:
18068
    case ARM::MVE_VQDMLAH_qrs32:
18069
    case ARM::MVE_VQDMLASH_qrs8:
18070
    case ARM::MVE_VQDMLASH_qrs16:
18071
    case ARM::MVE_VQDMLASH_qrs32:
18072
    case ARM::MVE_VQRDMLAH_qrs8:
18073
    case ARM::MVE_VQRDMLAH_qrs16:
18074
    case ARM::MVE_VQRDMLAH_qrs32:
18075
    case ARM::MVE_VQRDMLASH_qrs8:
18076
    case ARM::MVE_VQRDMLASH_qrs16:
18077
    case ARM::MVE_VQRDMLASH_qrs32: {
18078
      switch (OpNum) {
18079
      case 0:
18080
        // op: Qd
18081
        return 13;
18082
      case 2:
18083
        // op: Qn
18084
        return 7;
18085
      case 3:
18086
        // op: Rm
18087
        return 0;
18088
      }
18089
      break;
18090
    }
18091
    case ARM::MVE_VQRSHL_qrs8:
18092
    case ARM::MVE_VQRSHL_qrs16:
18093
    case ARM::MVE_VQRSHL_qrs32:
18094
    case ARM::MVE_VQRSHL_qru8:
18095
    case ARM::MVE_VQRSHL_qru16:
18096
    case ARM::MVE_VQRSHL_qru32:
18097
    case ARM::MVE_VQSHL_qrs8:
18098
    case ARM::MVE_VQSHL_qrs16:
18099
    case ARM::MVE_VQSHL_qrs32:
18100
    case ARM::MVE_VQSHL_qru8:
18101
    case ARM::MVE_VQSHL_qru16:
18102
    case ARM::MVE_VQSHL_qru32:
18103
    case ARM::MVE_VRSHL_qrs8:
18104
    case ARM::MVE_VRSHL_qrs16:
18105
    case ARM::MVE_VRSHL_qrs32:
18106
    case ARM::MVE_VRSHL_qru8:
18107
    case ARM::MVE_VRSHL_qru16:
18108
    case ARM::MVE_VRSHL_qru32:
18109
    case ARM::MVE_VSHL_qrs8:
18110
    case ARM::MVE_VSHL_qrs16:
18111
    case ARM::MVE_VSHL_qrs32:
18112
    case ARM::MVE_VSHL_qru8:
18113
    case ARM::MVE_VSHL_qru16:
18114
    case ARM::MVE_VSHL_qru32: {
18115
      switch (OpNum) {
18116
      case 0:
18117
        // op: Qd
18118
        return 13;
18119
      case 2:
18120
        // op: Rm
18121
        return 0;
18122
      }
18123
      break;
18124
    }
18125
    case ARM::MVE_VADC:
18126
    case ARM::MVE_VADCI:
18127
    case ARM::MVE_VQDMLADHXs8:
18128
    case ARM::MVE_VQDMLADHXs16:
18129
    case ARM::MVE_VQDMLADHXs32:
18130
    case ARM::MVE_VQDMLADHs8:
18131
    case ARM::MVE_VQDMLADHs16:
18132
    case ARM::MVE_VQDMLADHs32:
18133
    case ARM::MVE_VQDMLSDHXs8:
18134
    case ARM::MVE_VQDMLSDHXs16:
18135
    case ARM::MVE_VQDMLSDHXs32:
18136
    case ARM::MVE_VQDMLSDHs8:
18137
    case ARM::MVE_VQDMLSDHs16:
18138
    case ARM::MVE_VQDMLSDHs32:
18139
    case ARM::MVE_VQRDMLADHXs8:
18140
    case ARM::MVE_VQRDMLADHXs16:
18141
    case ARM::MVE_VQRDMLADHXs32:
18142
    case ARM::MVE_VQRDMLADHs8:
18143
    case ARM::MVE_VQRDMLADHs16:
18144
    case ARM::MVE_VQRDMLADHs32:
18145
    case ARM::MVE_VQRDMLSDHXs8:
18146
    case ARM::MVE_VQRDMLSDHXs16:
18147
    case ARM::MVE_VQRDMLSDHXs32:
18148
    case ARM::MVE_VQRDMLSDHs8:
18149
    case ARM::MVE_VQRDMLSDHs16:
18150
    case ARM::MVE_VQRDMLSDHs32:
18151
    case ARM::MVE_VSBC:
18152
    case ARM::MVE_VSBCI: {
18153
      switch (OpNum) {
18154
      case 0:
18155
        // op: Qd
18156
        return 13;
18157
      case 3:
18158
        // op: Qm
18159
        return 1;
18160
      case 2:
18161
        // op: Qn
18162
        return 7;
18163
      }
18164
      break;
18165
    }
18166
    case ARM::MVE_VDWDUPu8:
18167
    case ARM::MVE_VDWDUPu16:
18168
    case ARM::MVE_VDWDUPu32:
18169
    case ARM::MVE_VIWDUPu8:
18170
    case ARM::MVE_VIWDUPu16:
18171
    case ARM::MVE_VIWDUPu32: {
18172
      switch (OpNum) {
18173
      case 0:
18174
        // op: Qd
18175
        return 13;
18176
      case 3:
18177
        // op: Rm
18178
        return 1;
18179
      case 1:
18180
        // op: Rn
18181
        return 17;
18182
      case 4:
18183
        // op: imm
18184
        return 0;
18185
      }
18186
      break;
18187
    }
18188
    case ARM::MVE_VDUP8:
18189
    case ARM::MVE_VDUP16:
18190
    case ARM::MVE_VDUP32: {
18191
      switch (OpNum) {
18192
      case 0:
18193
        // op: Qd
18194
        return 7;
18195
      case 1:
18196
        // op: Rt
18197
        return 12;
18198
      }
18199
      break;
18200
    }
18201
    case ARM::MVE_VMOV_to_lane_32: {
18202
      switch (OpNum) {
18203
      case 0:
18204
        // op: Qd
18205
        return 7;
18206
      case 2:
18207
        // op: Rt
18208
        return 12;
18209
      case 3:
18210
        // op: Idx
18211
        return 16;
18212
      }
18213
      break;
18214
    }
18215
    case ARM::MVE_VMOV_to_lane_8: {
18216
      switch (OpNum) {
18217
      case 0:
18218
        // op: Qd
18219
        return 7;
18220
      case 2:
18221
        // op: Rt
18222
        return 12;
18223
      case 3:
18224
        // op: Idx
18225
        return 5;
18226
      }
18227
      break;
18228
    }
18229
    case ARM::MVE_VMOV_to_lane_16: {
18230
      switch (OpNum) {
18231
      case 0:
18232
        // op: Qd
18233
        return 7;
18234
      case 2:
18235
        // op: Rt
18236
        return 12;
18237
      case 3:
18238
        // op: Idx
18239
        return 6;
18240
      }
18241
      break;
18242
    }
18243
    case ARM::tMOVSr:
18244
    case ARM::tMOVr: {
18245
      switch (OpNum) {
18246
      case 0:
18247
        // op: Rd
18248
        return 0;
18249
      case 1:
18250
        // op: Rm
18251
        return 3;
18252
      }
18253
      break;
18254
    }
18255
    case ARM::t2STLEX: {
18256
      switch (OpNum) {
18257
      case 0:
18258
        // op: Rd
18259
        return 0;
18260
      case 1:
18261
        // op: Rt
18262
        return 12;
18263
      case 2:
18264
        // op: addr
18265
        return 16;
18266
      }
18267
      break;
18268
    }
18269
    case ARM::tADDi3:
18270
    case ARM::tSUBi3: {
18271
      switch (OpNum) {
18272
      case 0:
18273
        // op: Rd
18274
        return 0;
18275
      case 2:
18276
        // op: Rm
18277
        return 3;
18278
      case 3:
18279
        // op: imm3
18280
        return 6;
18281
      }
18282
      break;
18283
    }
18284
    case ARM::tASRri:
18285
    case ARM::tLSLri:
18286
    case ARM::tLSRri: {
18287
      switch (OpNum) {
18288
      case 0:
18289
        // op: Rd
18290
        return 0;
18291
      case 2:
18292
        // op: Rm
18293
        return 3;
18294
      case 3:
18295
        // op: imm5
18296
        return 6;
18297
      }
18298
      break;
18299
    }
18300
    case ARM::tMUL:
18301
    case ARM::tMVN:
18302
    case ARM::tRSB: {
18303
      switch (OpNum) {
18304
      case 0:
18305
        // op: Rd
18306
        return 0;
18307
      case 2:
18308
        // op: Rn
18309
        return 3;
18310
      }
18311
      break;
18312
    }
18313
    case ARM::t2STLEXB:
18314
    case ARM::t2STLEXH:
18315
    case ARM::t2STREXB:
18316
    case ARM::t2STREXH: {
18317
      switch (OpNum) {
18318
      case 0:
18319
        // op: Rd
18320
        return 0;
18321
      case 2:
18322
        // op: addr
18323
        return 16;
18324
      case 1:
18325
        // op: Rt
18326
        return 12;
18327
      }
18328
      break;
18329
    }
18330
    case ARM::t2STLEXD:
18331
    case ARM::t2STREXD: {
18332
      switch (OpNum) {
18333
      case 0:
18334
        // op: Rd
18335
        return 0;
18336
      case 3:
18337
        // op: addr
18338
        return 16;
18339
      case 1:
18340
        // op: Rt
18341
        return 12;
18342
      case 2:
18343
        // op: Rt2
18344
        return 8;
18345
      }
18346
      break;
18347
    }
18348
    case ARM::CRC32B:
18349
    case ARM::CRC32CB:
18350
    case ARM::CRC32CH:
18351
    case ARM::CRC32CW:
18352
    case ARM::CRC32H:
18353
    case ARM::CRC32W: {
18354
      switch (OpNum) {
18355
      case 0:
18356
        // op: Rd
18357
        return 12;
18358
      case 1:
18359
        // op: Rn
18360
        return 16;
18361
      case 2:
18362
        // op: Rm
18363
        return 0;
18364
      }
18365
      break;
18366
    }
18367
    case ARM::t2SXTB:
18368
    case ARM::t2SXTB16:
18369
    case ARM::t2SXTH:
18370
    case ARM::t2UXTB:
18371
    case ARM::t2UXTB16:
18372
    case ARM::t2UXTH: {
18373
      switch (OpNum) {
18374
      case 0:
18375
        // op: Rd
18376
        return 8;
18377
      case 1:
18378
        // op: Rm
18379
        return 0;
18380
      case 2:
18381
        // op: rot
18382
        return 4;
18383
      }
18384
      break;
18385
    }
18386
    case ARM::t2CLZ:
18387
    case ARM::t2MOVsra_glue:
18388
    case ARM::t2MOVsrl_glue:
18389
    case ARM::t2RBIT:
18390
    case ARM::t2REV:
18391
    case ARM::t2REV16:
18392
    case ARM::t2REVSH: {
18393
      switch (OpNum) {
18394
      case 0:
18395
        // op: Rd
18396
        return 8;
18397
      case 1:
18398
        // op: Rm
18399
        return 0;
18400
      }
18401
      break;
18402
    }
18403
    case ARM::t2MLA:
18404
    case ARM::t2MLS:
18405
    case ARM::t2SMLABB:
18406
    case ARM::t2SMLABT:
18407
    case ARM::t2SMLAD:
18408
    case ARM::t2SMLADX:
18409
    case ARM::t2SMLATB:
18410
    case ARM::t2SMLATT:
18411
    case ARM::t2SMLAWB:
18412
    case ARM::t2SMLAWT:
18413
    case ARM::t2SMLSD:
18414
    case ARM::t2SMLSDX:
18415
    case ARM::t2SMMLA:
18416
    case ARM::t2SMMLAR:
18417
    case ARM::t2SMMLS:
18418
    case ARM::t2SMMLSR:
18419
    case ARM::t2USADA8: {
18420
      switch (OpNum) {
18421
      case 0:
18422
        // op: Rd
18423
        return 8;
18424
      case 1:
18425
        // op: Rn
18426
        return 16;
18427
      case 2:
18428
        // op: Rm
18429
        return 0;
18430
      case 3:
18431
        // op: Ra
18432
        return 12;
18433
      }
18434
      break;
18435
    }
18436
    case ARM::t2SXTAB:
18437
    case ARM::t2SXTAB16:
18438
    case ARM::t2SXTAH:
18439
    case ARM::t2UXTAB:
18440
    case ARM::t2UXTAB16:
18441
    case ARM::t2UXTAH: {
18442
      switch (OpNum) {
18443
      case 0:
18444
        // op: Rd
18445
        return 8;
18446
      case 1:
18447
        // op: Rn
18448
        return 16;
18449
      case 2:
18450
        // op: Rm
18451
        return 0;
18452
      case 3:
18453
        // op: rot
18454
        return 4;
18455
      }
18456
      break;
18457
    }
18458
    case ARM::t2PKHBT:
18459
    case ARM::t2PKHTB: {
18460
      switch (OpNum) {
18461
      case 0:
18462
        // op: Rd
18463
        return 8;
18464
      case 1:
18465
        // op: Rn
18466
        return 16;
18467
      case 2:
18468
        // op: Rm
18469
        return 0;
18470
      case 3:
18471
        // op: sh
18472
        return 6;
18473
      }
18474
      break;
18475
    }
18476
    case ARM::t2CRC32B:
18477
    case ARM::t2CRC32CB:
18478
    case ARM::t2CRC32CH:
18479
    case ARM::t2CRC32CW:
18480
    case ARM::t2CRC32H:
18481
    case ARM::t2CRC32W:
18482
    case ARM::t2MUL:
18483
    case ARM::t2QADD8:
18484
    case ARM::t2QADD16:
18485
    case ARM::t2QASX:
18486
    case ARM::t2QSAX:
18487
    case ARM::t2QSUB8:
18488
    case ARM::t2QSUB16:
18489
    case ARM::t2SADD8:
18490
    case ARM::t2SADD16:
18491
    case ARM::t2SASX:
18492
    case ARM::t2SDIV:
18493
    case ARM::t2SEL:
18494
    case ARM::t2SHADD8:
18495
    case ARM::t2SHADD16:
18496
    case ARM::t2SHASX:
18497
    case ARM::t2SHSAX:
18498
    case ARM::t2SHSUB8:
18499
    case ARM::t2SHSUB16:
18500
    case ARM::t2SMMUL:
18501
    case ARM::t2SMMULR:
18502
    case ARM::t2SMUAD:
18503
    case ARM::t2SMUADX:
18504
    case ARM::t2SMULBB:
18505
    case ARM::t2SMULBT:
18506
    case ARM::t2SMULTB:
18507
    case ARM::t2SMULTT:
18508
    case ARM::t2SMULWB:
18509
    case ARM::t2SMULWT:
18510
    case ARM::t2SMUSD:
18511
    case ARM::t2SMUSDX:
18512
    case ARM::t2SSAX:
18513
    case ARM::t2SSUB8:
18514
    case ARM::t2SSUB16:
18515
    case ARM::t2UADD8:
18516
    case ARM::t2UADD16:
18517
    case ARM::t2UASX:
18518
    case ARM::t2UDIV:
18519
    case ARM::t2UHADD8:
18520
    case ARM::t2UHADD16:
18521
    case ARM::t2UHASX:
18522
    case ARM::t2UHSAX:
18523
    case ARM::t2UHSUB8:
18524
    case ARM::t2UHSUB16:
18525
    case ARM::t2UQADD8:
18526
    case ARM::t2UQADD16:
18527
    case ARM::t2UQASX:
18528
    case ARM::t2UQSAX:
18529
    case ARM::t2UQSUB8:
18530
    case ARM::t2UQSUB16:
18531
    case ARM::t2USAD8:
18532
    case ARM::t2USAX:
18533
    case ARM::t2USUB8:
18534
    case ARM::t2USUB16: {
18535
      switch (OpNum) {
18536
      case 0:
18537
        // op: Rd
18538
        return 8;
18539
      case 1:
18540
        // op: Rn
18541
        return 16;
18542
      case 2:
18543
        // op: Rm
18544
        return 0;
18545
      }
18546
      break;
18547
    }
18548
    case ARM::t2ADDri12:
18549
    case ARM::t2SUBri12: {
18550
      switch (OpNum) {
18551
      case 0:
18552
        // op: Rd
18553
        return 8;
18554
      case 1:
18555
        // op: Rn
18556
        return 16;
18557
      case 2:
18558
        // op: imm
18559
        return 0;
18560
      }
18561
      break;
18562
    }
18563
    case ARM::t2STREX: {
18564
      switch (OpNum) {
18565
      case 0:
18566
        // op: Rd
18567
        return 8;
18568
      case 1:
18569
        // op: Rt
18570
        return 12;
18571
      case 2:
18572
        // op: addr
18573
        return 0;
18574
      }
18575
      break;
18576
    }
18577
    case ARM::t2MRS_M: {
18578
      switch (OpNum) {
18579
      case 0:
18580
        // op: Rd
18581
        return 8;
18582
      case 1:
18583
        // op: SYSm
18584
        return 0;
18585
      }
18586
      break;
18587
    }
18588
    case ARM::t2ADR:
18589
    case ARM::tADR: {
18590
      switch (OpNum) {
18591
      case 0:
18592
        // op: Rd
18593
        return 8;
18594
      case 1:
18595
        // op: addr
18596
        return 0;
18597
      }
18598
      break;
18599
    }
18600
    case ARM::t2MOVi16: {
18601
      switch (OpNum) {
18602
      case 0:
18603
        // op: Rd
18604
        return 8;
18605
      case 1:
18606
        // op: imm
18607
        return 0;
18608
      }
18609
      break;
18610
    }
18611
    case ARM::t2CSEL:
18612
    case ARM::t2CSINC:
18613
    case ARM::t2CSINV:
18614
    case ARM::t2CSNEG: {
18615
      switch (OpNum) {
18616
      case 0:
18617
        // op: Rd
18618
        return 8;
18619
      case 2:
18620
        // op: Rm
18621
        return 0;
18622
      case 1:
18623
        // op: Rn
18624
        return 16;
18625
      case 3:
18626
        // op: fcond
18627
        return 4;
18628
      }
18629
      break;
18630
    }
18631
    case ARM::t2QADD:
18632
    case ARM::t2QDADD:
18633
    case ARM::t2QDSUB:
18634
    case ARM::t2QSUB: {
18635
      switch (OpNum) {
18636
      case 0:
18637
        // op: Rd
18638
        return 8;
18639
      case 2:
18640
        // op: Rn
18641
        return 16;
18642
      case 1:
18643
        // op: Rm
18644
        return 0;
18645
      }
18646
      break;
18647
    }
18648
    case ARM::t2SSAT:
18649
    case ARM::t2USAT: {
18650
      switch (OpNum) {
18651
      case 0:
18652
        // op: Rd
18653
        return 8;
18654
      case 2:
18655
        // op: Rn
18656
        return 16;
18657
      case 1:
18658
        // op: sat_imm
18659
        return 0;
18660
      case 3:
18661
        // op: sh
18662
        return 6;
18663
      }
18664
      break;
18665
    }
18666
    case ARM::t2SSAT16:
18667
    case ARM::t2USAT16: {
18668
      switch (OpNum) {
18669
      case 0:
18670
        // op: Rd
18671
        return 8;
18672
      case 2:
18673
        // op: Rn
18674
        return 16;
18675
      case 1:
18676
        // op: sat_imm
18677
        return 0;
18678
      }
18679
      break;
18680
    }
18681
    case ARM::t2BFI: {
18682
      switch (OpNum) {
18683
      case 0:
18684
        // op: Rd
18685
        return 8;
18686
      case 2:
18687
        // op: Rn
18688
        return 16;
18689
      case 3:
18690
        // op: imm
18691
        return 0;
18692
      }
18693
      break;
18694
    }
18695
    case ARM::t2BFC:
18696
    case ARM::t2MOVTi16: {
18697
      switch (OpNum) {
18698
      case 0:
18699
        // op: Rd
18700
        return 8;
18701
      case 2:
18702
        // op: imm
18703
        return 0;
18704
      }
18705
      break;
18706
    }
18707
    case ARM::tMOVi8: {
18708
      switch (OpNum) {
18709
      case 0:
18710
        // op: Rd
18711
        return 8;
18712
      case 2:
18713
        // op: imm8
18714
        return 0;
18715
      }
18716
      break;
18717
    }
18718
    case ARM::t2PACG: {
18719
      switch (OpNum) {
18720
      case 0:
18721
        // op: Rd
18722
        return 8;
18723
      case 3:
18724
        // op: Rn
18725
        return 16;
18726
      case 4:
18727
        // op: Rm
18728
        return 0;
18729
      }
18730
      break;
18731
    }
18732
    case ARM::t2SBFX:
18733
    case ARM::t2UBFX: {
18734
      switch (OpNum) {
18735
      case 0:
18736
        // op: Rd
18737
        return 8;
18738
      case 3:
18739
        // op: msb
18740
        return 0;
18741
      case 2:
18742
        // op: lsb
18743
        return 6;
18744
      case 1:
18745
        // op: Rn
18746
        return 16;
18747
      }
18748
      break;
18749
    }
18750
    case ARM::t2MRS_AR:
18751
    case ARM::t2MRSsys_AR: {
18752
      switch (OpNum) {
18753
      case 0:
18754
        // op: Rd
18755
        return 8;
18756
      }
18757
      break;
18758
    }
18759
    case ARM::t2SMLAL:
18760
    case ARM::t2SMLALBB:
18761
    case ARM::t2SMLALBT:
18762
    case ARM::t2SMLALTB:
18763
    case ARM::t2SMLALTT:
18764
    case ARM::t2SMULL:
18765
    case ARM::t2UMAAL:
18766
    case ARM::t2UMLAL:
18767
    case ARM::t2UMULL: {
18768
      switch (OpNum) {
18769
      case 0:
18770
        // op: RdLo
18771
        return 12;
18772
      case 1:
18773
        // op: RdHi
18774
        return 8;
18775
      case 2:
18776
        // op: Rn
18777
        return 16;
18778
      case 3:
18779
        // op: Rm
18780
        return 0;
18781
      }
18782
      break;
18783
    }
18784
    case ARM::MVE_VMLADAVs8:
18785
    case ARM::MVE_VMLADAVs16:
18786
    case ARM::MVE_VMLADAVs32:
18787
    case ARM::MVE_VMLADAVu8:
18788
    case ARM::MVE_VMLADAVu16:
18789
    case ARM::MVE_VMLADAVu32:
18790
    case ARM::MVE_VMLADAVxs8:
18791
    case ARM::MVE_VMLADAVxs16:
18792
    case ARM::MVE_VMLADAVxs32:
18793
    case ARM::MVE_VMLSDAVs8:
18794
    case ARM::MVE_VMLSDAVs16:
18795
    case ARM::MVE_VMLSDAVs32:
18796
    case ARM::MVE_VMLSDAVxs8:
18797
    case ARM::MVE_VMLSDAVxs16:
18798
    case ARM::MVE_VMLSDAVxs32: {
18799
      switch (OpNum) {
18800
      case 0:
18801
        // op: RdaDest
18802
        return 13;
18803
      case 2:
18804
        // op: Qm
18805
        return 1;
18806
      case 1:
18807
        // op: Qn
18808
        return 17;
18809
      }
18810
      break;
18811
    }
18812
    case ARM::MVE_VMLADAVas8:
18813
    case ARM::MVE_VMLADAVas16:
18814
    case ARM::MVE_VMLADAVas32:
18815
    case ARM::MVE_VMLADAVau8:
18816
    case ARM::MVE_VMLADAVau16:
18817
    case ARM::MVE_VMLADAVau32:
18818
    case ARM::MVE_VMLADAVaxs8:
18819
    case ARM::MVE_VMLADAVaxs16:
18820
    case ARM::MVE_VMLADAVaxs32:
18821
    case ARM::MVE_VMLSDAVas8:
18822
    case ARM::MVE_VMLSDAVas16:
18823
    case ARM::MVE_VMLSDAVas32:
18824
    case ARM::MVE_VMLSDAVaxs8:
18825
    case ARM::MVE_VMLSDAVaxs16:
18826
    case ARM::MVE_VMLSDAVaxs32: {
18827
      switch (OpNum) {
18828
      case 0:
18829
        // op: RdaDest
18830
        return 13;
18831
      case 3:
18832
        // op: Qm
18833
        return 1;
18834
      case 2:
18835
        // op: Qn
18836
        return 17;
18837
      }
18838
      break;
18839
    }
18840
    case ARM::MVE_SQRSHR:
18841
    case ARM::MVE_UQRSHL: {
18842
      switch (OpNum) {
18843
      case 0:
18844
        // op: RdaDest
18845
        return 16;
18846
      case 2:
18847
        // op: Rm
18848
        return 12;
18849
      }
18850
      break;
18851
    }
18852
    case ARM::MVE_SQSHL:
18853
    case ARM::MVE_SRSHR:
18854
    case ARM::MVE_UQSHL:
18855
    case ARM::MVE_URSHR: {
18856
      switch (OpNum) {
18857
      case 0:
18858
        // op: RdaDest
18859
        return 16;
18860
      case 2:
18861
        // op: imm
18862
        return 6;
18863
      }
18864
      break;
18865
    }
18866
    case ARM::MVE_SQRSHRL:
18867
    case ARM::MVE_UQRSHLL: {
18868
      switch (OpNum) {
18869
      case 0:
18870
        // op: RdaLo
18871
        return 17;
18872
      case 1:
18873
        // op: RdaHi
18874
        return 9;
18875
      case 4:
18876
        // op: Rm
18877
        return 12;
18878
      case 5:
18879
        // op: sat
18880
        return 7;
18881
      }
18882
      break;
18883
    }
18884
    case ARM::MVE_ASRLr:
18885
    case ARM::MVE_LSLLr: {
18886
      switch (OpNum) {
18887
      case 0:
18888
        // op: RdaLo
18889
        return 17;
18890
      case 1:
18891
        // op: RdaHi
18892
        return 9;
18893
      case 4:
18894
        // op: Rm
18895
        return 12;
18896
      }
18897
      break;
18898
    }
18899
    case ARM::MVE_ASRLi:
18900
    case ARM::MVE_LSLLi:
18901
    case ARM::MVE_LSRL:
18902
    case ARM::MVE_SQSHLL:
18903
    case ARM::MVE_SRSHRL:
18904
    case ARM::MVE_UQSHLL:
18905
    case ARM::MVE_URSHRL: {
18906
      switch (OpNum) {
18907
      case 0:
18908
        // op: RdaLo
18909
        return 17;
18910
      case 1:
18911
        // op: RdaHi
18912
        return 9;
18913
      case 4:
18914
        // op: imm
18915
        return 6;
18916
      }
18917
      break;
18918
    }
18919
    case ARM::MVE_VMLALDAVs16:
18920
    case ARM::MVE_VMLALDAVs32:
18921
    case ARM::MVE_VMLALDAVu16:
18922
    case ARM::MVE_VMLALDAVu32:
18923
    case ARM::MVE_VMLALDAVxs16:
18924
    case ARM::MVE_VMLALDAVxs32:
18925
    case ARM::MVE_VMLSLDAVs16:
18926
    case ARM::MVE_VMLSLDAVs32:
18927
    case ARM::MVE_VMLSLDAVxs16:
18928
    case ARM::MVE_VMLSLDAVxs32:
18929
    case ARM::MVE_VRMLALDAVHs32:
18930
    case ARM::MVE_VRMLALDAVHu32:
18931
    case ARM::MVE_VRMLALDAVHxs32:
18932
    case ARM::MVE_VRMLSLDAVHs32:
18933
    case ARM::MVE_VRMLSLDAVHxs32: {
18934
      switch (OpNum) {
18935
      case 0:
18936
        // op: RdaLoDest
18937
        return 13;
18938
      case 1:
18939
        // op: RdaHiDest
18940
        return 20;
18941
      case 3:
18942
        // op: Qm
18943
        return 1;
18944
      case 2:
18945
        // op: Qn
18946
        return 17;
18947
      }
18948
      break;
18949
    }
18950
    case ARM::MVE_VMLALDAVas16:
18951
    case ARM::MVE_VMLALDAVas32:
18952
    case ARM::MVE_VMLALDAVau16:
18953
    case ARM::MVE_VMLALDAVau32:
18954
    case ARM::MVE_VMLALDAVaxs16:
18955
    case ARM::MVE_VMLALDAVaxs32:
18956
    case ARM::MVE_VMLSLDAVas16:
18957
    case ARM::MVE_VMLSLDAVas32:
18958
    case ARM::MVE_VMLSLDAVaxs16:
18959
    case ARM::MVE_VMLSLDAVaxs32:
18960
    case ARM::MVE_VRMLALDAVHas32:
18961
    case ARM::MVE_VRMLALDAVHau32:
18962
    case ARM::MVE_VRMLALDAVHaxs32:
18963
    case ARM::MVE_VRMLSLDAVHas32:
18964
    case ARM::MVE_VRMLSLDAVHaxs32: {
18965
      switch (OpNum) {
18966
      case 0:
18967
        // op: RdaLoDest
18968
        return 13;
18969
      case 1:
18970
        // op: RdaHiDest
18971
        return 20;
18972
      case 5:
18973
        // op: Qm
18974
        return 1;
18975
      case 4:
18976
        // op: Qn
18977
        return 17;
18978
      }
18979
      break;
18980
    }
18981
    case ARM::tADDhirr: {
18982
      switch (OpNum) {
18983
      case 0:
18984
        // op: Rdn
18985
        return 0;
18986
      case 2:
18987
        // op: Rm
18988
        return 3;
18989
      }
18990
      break;
18991
    }
18992
    case ARM::tADC:
18993
    case ARM::tAND:
18994
    case ARM::tASRrr:
18995
    case ARM::tBIC:
18996
    case ARM::tEOR:
18997
    case ARM::tLSLrr:
18998
    case ARM::tLSRrr:
18999
    case ARM::tORR:
19000
    case ARM::tROR:
19001
    case ARM::tSBC: {
19002
      switch (OpNum) {
19003
      case 0:
19004
        // op: Rdn
19005
        return 0;
19006
      case 3:
19007
        // op: Rm
19008
        return 3;
19009
      }
19010
      break;
19011
    }
19012
    case ARM::tADDrSP: {
19013
      switch (OpNum) {
19014
      case 0:
19015
        // op: Rdn
19016
        return 0;
19017
      }
19018
      break;
19019
    }
19020
    case ARM::tADDi8:
19021
    case ARM::tSUBi8: {
19022
      switch (OpNum) {
19023
      case 0:
19024
        // op: Rdn
19025
        return 8;
19026
      case 3:
19027
        // op: imm8
19028
        return 0;
19029
      }
19030
      break;
19031
    }
19032
    case ARM::tBX:
19033
    case ARM::tBXNS: {
19034
      switch (OpNum) {
19035
      case 0:
19036
        // op: Rm
19037
        return 3;
19038
      }
19039
      break;
19040
    }
19041
    case ARM::t2CMNzrr:
19042
    case ARM::t2CMPrr:
19043
    case ARM::t2TBB:
19044
    case ARM::t2TBH:
19045
    case ARM::t2TEQrr:
19046
    case ARM::t2TSTrr: {
19047
      switch (OpNum) {
19048
      case 0:
19049
        // op: Rn
19050
        return 16;
19051
      case 1:
19052
        // op: Rm
19053
        return 0;
19054
      }
19055
      break;
19056
    }
19057
    case ARM::t2CMNzrs:
19058
    case ARM::t2CMPrs:
19059
    case ARM::t2TEQrs:
19060
    case ARM::t2TSTrs: {
19061
      switch (OpNum) {
19062
      case 0:
19063
        // op: Rn
19064
        return 16;
19065
      case 1:
19066
        // op: ShiftedRm
19067
        return 0;
19068
      }
19069
      break;
19070
    }
19071
    case ARM::t2CMNri:
19072
    case ARM::t2CMPri:
19073
    case ARM::t2TEQri:
19074
    case ARM::t2TSTri: {
19075
      switch (OpNum) {
19076
      case 0:
19077
        // op: Rn
19078
        return 16;
19079
      case 1:
19080
        // op: imm
19081
        return 0;
19082
      }
19083
      break;
19084
    }
19085
    case ARM::t2LDMDB:
19086
    case ARM::t2LDMIA:
19087
    case ARM::t2STMDB:
19088
    case ARM::t2STMIA: {
19089
      switch (OpNum) {
19090
      case 0:
19091
        // op: Rn
19092
        return 16;
19093
      case 3:
19094
        // op: regs
19095
        return 0;
19096
      }
19097
      break;
19098
    }
19099
    case ARM::RFEDA:
19100
    case ARM::RFEDA_UPD:
19101
    case ARM::RFEDB:
19102
    case ARM::RFEDB_UPD:
19103
    case ARM::RFEIA:
19104
    case ARM::RFEIA_UPD:
19105
    case ARM::RFEIB:
19106
    case ARM::RFEIB_UPD:
19107
    case ARM::t2RFEDB:
19108
    case ARM::t2RFEDBW:
19109
    case ARM::t2RFEIA:
19110
    case ARM::t2RFEIAW: {
19111
      switch (OpNum) {
19112
      case 0:
19113
        // op: Rn
19114
        return 16;
19115
      }
19116
      break;
19117
    }
19118
    case ARM::tCMPi8: {
19119
      switch (OpNum) {
19120
      case 0:
19121
        // op: Rn
19122
        return 8;
19123
      case 1:
19124
        // op: imm8
19125
        return 0;
19126
      }
19127
      break;
19128
    }
19129
    case ARM::tLDMIA: {
19130
      switch (OpNum) {
19131
      case 0:
19132
        // op: Rn
19133
        return 8;
19134
      case 3:
19135
        // op: regs
19136
        return 0;
19137
      }
19138
      break;
19139
    }
19140
    case ARM::MVE_VMOV_rr_q: {
19141
      switch (OpNum) {
19142
      case 0:
19143
        // op: Rt
19144
        return 0;
19145
      case 1:
19146
        // op: Rt2
19147
        return 16;
19148
      case 2:
19149
        // op: Qd
19150
        return 13;
19151
      case 4:
19152
        // op: idx2
19153
        return 4;
19154
      }
19155
      break;
19156
    }
19157
    case ARM::tLDRBi:
19158
    case ARM::tLDRBr:
19159
    case ARM::tLDRHi:
19160
    case ARM::tLDRHr:
19161
    case ARM::tLDRSB:
19162
    case ARM::tLDRSH:
19163
    case ARM::tLDRi:
19164
    case ARM::tLDRr:
19165
    case ARM::tSTRBi:
19166
    case ARM::tSTRBr:
19167
    case ARM::tSTRHi:
19168
    case ARM::tSTRHr:
19169
    case ARM::tSTRi:
19170
    case ARM::tSTRr: {
19171
      switch (OpNum) {
19172
      case 0:
19173
        // op: Rt
19174
        return 0;
19175
      case 1:
19176
        // op: addr
19177
        return 3;
19178
      }
19179
      break;
19180
    }
19181
    case ARM::MRRC2:
19182
    case ARM::t2MRRC:
19183
    case ARM::t2MRRC2: {
19184
      switch (OpNum) {
19185
      case 0:
19186
        // op: Rt
19187
        return 12;
19188
      case 1:
19189
        // op: Rt2
19190
        return 16;
19191
      case 2:
19192
        // op: cop
19193
        return 8;
19194
      case 3:
19195
        // op: opc1
19196
        return 4;
19197
      case 4:
19198
        // op: CRm
19199
        return 0;
19200
      }
19201
      break;
19202
    }
19203
    case ARM::t2LDRDi8:
19204
    case ARM::t2STRDi8: {
19205
      switch (OpNum) {
19206
      case 0:
19207
        // op: Rt
19208
        return 12;
19209
      case 1:
19210
        // op: Rt2
19211
        return 8;
19212
      case 2:
19213
        // op: addr
19214
        return 0;
19215
      }
19216
      break;
19217
    }
19218
    case ARM::t2LDRD_PRE: {
19219
      switch (OpNum) {
19220
      case 0:
19221
        // op: Rt
19222
        return 12;
19223
      case 1:
19224
        // op: Rt2
19225
        return 8;
19226
      case 3:
19227
        // op: addr
19228
        return 0;
19229
      }
19230
      break;
19231
    }
19232
    case ARM::t2LDRD_POST: {
19233
      switch (OpNum) {
19234
      case 0:
19235
        // op: Rt
19236
        return 12;
19237
      case 1:
19238
        // op: Rt2
19239
        return 8;
19240
      case 3:
19241
        // op: addr
19242
        return 16;
19243
      case 4:
19244
        // op: imm
19245
        return 0;
19246
      }
19247
      break;
19248
    }
19249
    case ARM::t2LDRBT:
19250
    case ARM::t2LDRBi8:
19251
    case ARM::t2LDRBi12:
19252
    case ARM::t2LDRBpci:
19253
    case ARM::t2LDRBs:
19254
    case ARM::t2LDREX:
19255
    case ARM::t2LDRHT:
19256
    case ARM::t2LDRHi8:
19257
    case ARM::t2LDRHi12:
19258
    case ARM::t2LDRHpci:
19259
    case ARM::t2LDRHs:
19260
    case ARM::t2LDRSBT:
19261
    case ARM::t2LDRSBi8:
19262
    case ARM::t2LDRSBi12:
19263
    case ARM::t2LDRSBpci:
19264
    case ARM::t2LDRSBs:
19265
    case ARM::t2LDRSHT:
19266
    case ARM::t2LDRSHi8:
19267
    case ARM::t2LDRSHi12:
19268
    case ARM::t2LDRSHpci:
19269
    case ARM::t2LDRSHs:
19270
    case ARM::t2LDRT:
19271
    case ARM::t2LDRi8:
19272
    case ARM::t2LDRi12:
19273
    case ARM::t2LDRpci:
19274
    case ARM::t2LDRs:
19275
    case ARM::t2STRBT:
19276
    case ARM::t2STRBi8:
19277
    case ARM::t2STRBi12:
19278
    case ARM::t2STRBs:
19279
    case ARM::t2STRHT:
19280
    case ARM::t2STRHi8:
19281
    case ARM::t2STRHi12:
19282
    case ARM::t2STRHs:
19283
    case ARM::t2STRT:
19284
    case ARM::t2STRi8:
19285
    case ARM::t2STRi12:
19286
    case ARM::t2STRs: {
19287
      switch (OpNum) {
19288
      case 0:
19289
        // op: Rt
19290
        return 12;
19291
      case 1:
19292
        // op: addr
19293
        return 0;
19294
      }
19295
      break;
19296
    }
19297
    case ARM::t2LDA:
19298
    case ARM::t2LDAB:
19299
    case ARM::t2LDAEX:
19300
    case ARM::t2LDAH:
19301
    case ARM::t2STL:
19302
    case ARM::t2STLB:
19303
    case ARM::t2STLH: {
19304
      switch (OpNum) {
19305
      case 0:
19306
        // op: Rt
19307
        return 12;
19308
      case 1:
19309
        // op: addr
19310
        return 16;
19311
      }
19312
      break;
19313
    }
19314
    case ARM::MRC2:
19315
    case ARM::t2MRC:
19316
    case ARM::t2MRC2: {
19317
      switch (OpNum) {
19318
      case 0:
19319
        // op: Rt
19320
        return 12;
19321
      case 1:
19322
        // op: cop
19323
        return 8;
19324
      case 2:
19325
        // op: opc1
19326
        return 21;
19327
      case 5:
19328
        // op: opc2
19329
        return 5;
19330
      case 4:
19331
        // op: CRm
19332
        return 0;
19333
      case 3:
19334
        // op: CRn
19335
        return 16;
19336
      }
19337
      break;
19338
    }
19339
    case ARM::t2LDRB_POST:
19340
    case ARM::t2LDRH_POST:
19341
    case ARM::t2LDRSB_POST:
19342
    case ARM::t2LDRSH_POST:
19343
    case ARM::t2LDR_POST: {
19344
      switch (OpNum) {
19345
      case 0:
19346
        // op: Rt
19347
        return 12;
19348
      case 2:
19349
        // op: Rn
19350
        return 16;
19351
      case 3:
19352
        // op: offset
19353
        return 0;
19354
      }
19355
      break;
19356
    }
19357
    case ARM::t2LDRB_PRE:
19358
    case ARM::t2LDRH_PRE:
19359
    case ARM::t2LDRSB_PRE:
19360
    case ARM::t2LDRSH_PRE:
19361
    case ARM::t2LDR_PRE: {
19362
      switch (OpNum) {
19363
      case 0:
19364
        // op: Rt
19365
        return 12;
19366
      case 2:
19367
        // op: addr
19368
        return 0;
19369
      }
19370
      break;
19371
    }
19372
    case ARM::tLDRpci:
19373
    case ARM::tLDRspi:
19374
    case ARM::tSTRspi: {
19375
      switch (OpNum) {
19376
      case 0:
19377
        // op: Rt
19378
        return 8;
19379
      case 1:
19380
        // op: addr
19381
        return 0;
19382
      }
19383
      break;
19384
    }
19385
    case ARM::t2MSR_M: {
19386
      switch (OpNum) {
19387
      case 0:
19388
        // op: SYSm
19389
        return 0;
19390
      case 1:
19391
        // op: Rn
19392
        return 16;
19393
      }
19394
      break;
19395
    }
19396
    case ARM::VCVTASD:
19397
    case ARM::VCVTAUD:
19398
    case ARM::VCVTMSD:
19399
    case ARM::VCVTMUD:
19400
    case ARM::VCVTNSD:
19401
    case ARM::VCVTNUD:
19402
    case ARM::VCVTPSD:
19403
    case ARM::VCVTPUD: {
19404
      switch (OpNum) {
19405
      case 0:
19406
        // op: Sd
19407
        return 12;
19408
      case 1:
19409
        // op: Dm
19410
        return 0;
19411
      }
19412
      break;
19413
    }
19414
    case ARM::VCVTASH:
19415
    case ARM::VCVTASS:
19416
    case ARM::VCVTAUH:
19417
    case ARM::VCVTAUS:
19418
    case ARM::VCVTMSH:
19419
    case ARM::VCVTMSS:
19420
    case ARM::VCVTMUH:
19421
    case ARM::VCVTMUS:
19422
    case ARM::VCVTNSH:
19423
    case ARM::VCVTNSS:
19424
    case ARM::VCVTNUH:
19425
    case ARM::VCVTNUS:
19426
    case ARM::VCVTPSH:
19427
    case ARM::VCVTPSS:
19428
    case ARM::VCVTPUH:
19429
    case ARM::VCVTPUS:
19430
    case ARM::VMOVH:
19431
    case ARM::VRINTAH:
19432
    case ARM::VRINTAS:
19433
    case ARM::VRINTMH:
19434
    case ARM::VRINTMS:
19435
    case ARM::VRINTNH:
19436
    case ARM::VRINTNS:
19437
    case ARM::VRINTPH:
19438
    case ARM::VRINTPS: {
19439
      switch (OpNum) {
19440
      case 0:
19441
        // op: Sd
19442
        return 12;
19443
      case 1:
19444
        // op: Sm
19445
        return 0;
19446
      }
19447
      break;
19448
    }
19449
    case ARM::VFP_VMAXNMH:
19450
    case ARM::VFP_VMAXNMS:
19451
    case ARM::VFP_VMINNMH:
19452
    case ARM::VFP_VMINNMS:
19453
    case ARM::VSELEQH:
19454
    case ARM::VSELEQS:
19455
    case ARM::VSELGEH:
19456
    case ARM::VSELGES:
19457
    case ARM::VSELGTH:
19458
    case ARM::VSELGTS:
19459
    case ARM::VSELVSH:
19460
    case ARM::VSELVSS: {
19461
      switch (OpNum) {
19462
      case 0:
19463
        // op: Sd
19464
        return 12;
19465
      case 1:
19466
        // op: Sn
19467
        return 7;
19468
      case 2:
19469
        // op: Sm
19470
        return 0;
19471
      }
19472
      break;
19473
    }
19474
    case ARM::VINSH: {
19475
      switch (OpNum) {
19476
      case 0:
19477
        // op: Sd
19478
        return 12;
19479
      case 2:
19480
        // op: Sm
19481
        return 0;
19482
      }
19483
      break;
19484
    }
19485
    case ARM::VDUP8d:
19486
    case ARM::VDUP8q:
19487
    case ARM::VDUP16d:
19488
    case ARM::VDUP16q:
19489
    case ARM::VDUP32d:
19490
    case ARM::VDUP32q: {
19491
      switch (OpNum) {
19492
      case 0:
19493
        // op: V
19494
        return 7;
19495
      case 1:
19496
        // op: R
19497
        return 12;
19498
      case 2:
19499
        // op: p
19500
        return 28;
19501
      }
19502
      break;
19503
    }
19504
    case ARM::VSETLNi32: {
19505
      switch (OpNum) {
19506
      case 0:
19507
        // op: V
19508
        return 7;
19509
      case 2:
19510
        // op: R
19511
        return 12;
19512
      case 4:
19513
        // op: p
19514
        return 28;
19515
      case 3:
19516
        // op: lane
19517
        return 21;
19518
      }
19519
      break;
19520
    }
19521
    case ARM::VSETLNi8: {
19522
      switch (OpNum) {
19523
      case 0:
19524
        // op: V
19525
        return 7;
19526
      case 2:
19527
        // op: R
19528
        return 12;
19529
      case 4:
19530
        // op: p
19531
        return 28;
19532
      case 3:
19533
        // op: lane
19534
        return 5;
19535
      }
19536
      break;
19537
    }
19538
    case ARM::VSETLNi16: {
19539
      switch (OpNum) {
19540
      case 0:
19541
        // op: V
19542
        return 7;
19543
      case 2:
19544
        // op: R
19545
        return 12;
19546
      case 4:
19547
        // op: p
19548
        return 28;
19549
      case 3:
19550
        // op: lane
19551
        return 6;
19552
      }
19553
      break;
19554
    }
19555
    case ARM::MVE_VST20_8:
19556
    case ARM::MVE_VST20_16:
19557
    case ARM::MVE_VST20_32:
19558
    case ARM::MVE_VST21_8:
19559
    case ARM::MVE_VST21_16:
19560
    case ARM::MVE_VST21_32:
19561
    case ARM::MVE_VST40_8:
19562
    case ARM::MVE_VST40_16:
19563
    case ARM::MVE_VST40_32:
19564
    case ARM::MVE_VST41_8:
19565
    case ARM::MVE_VST41_16:
19566
    case ARM::MVE_VST41_32:
19567
    case ARM::MVE_VST42_8:
19568
    case ARM::MVE_VST42_16:
19569
    case ARM::MVE_VST42_32:
19570
    case ARM::MVE_VST43_8:
19571
    case ARM::MVE_VST43_16:
19572
    case ARM::MVE_VST43_32: {
19573
      switch (OpNum) {
19574
      case 0:
19575
        // op: VQd
19576
        return 13;
19577
      case 1:
19578
        // op: Rn
19579
        return 16;
19580
      }
19581
      break;
19582
    }
19583
    case ARM::MVE_VLD20_8:
19584
    case ARM::MVE_VLD20_16:
19585
    case ARM::MVE_VLD20_32:
19586
    case ARM::MVE_VLD21_8:
19587
    case ARM::MVE_VLD21_16:
19588
    case ARM::MVE_VLD21_32:
19589
    case ARM::MVE_VLD40_8:
19590
    case ARM::MVE_VLD40_16:
19591
    case ARM::MVE_VLD40_32:
19592
    case ARM::MVE_VLD41_8:
19593
    case ARM::MVE_VLD41_16:
19594
    case ARM::MVE_VLD41_32:
19595
    case ARM::MVE_VLD42_8:
19596
    case ARM::MVE_VLD42_16:
19597
    case ARM::MVE_VLD42_32:
19598
    case ARM::MVE_VLD43_8:
19599
    case ARM::MVE_VLD43_16:
19600
    case ARM::MVE_VLD43_32: {
19601
      switch (OpNum) {
19602
      case 0:
19603
        // op: VQd
19604
        return 13;
19605
      case 2:
19606
        // op: Rn
19607
        return 16;
19608
      }
19609
      break;
19610
    }
19611
    case ARM::MVE_VLD20_8_wb:
19612
    case ARM::MVE_VLD20_16_wb:
19613
    case ARM::MVE_VLD20_32_wb:
19614
    case ARM::MVE_VLD21_8_wb:
19615
    case ARM::MVE_VLD21_16_wb:
19616
    case ARM::MVE_VLD21_32_wb:
19617
    case ARM::MVE_VLD40_8_wb:
19618
    case ARM::MVE_VLD40_16_wb:
19619
    case ARM::MVE_VLD40_32_wb:
19620
    case ARM::MVE_VLD41_8_wb:
19621
    case ARM::MVE_VLD41_16_wb:
19622
    case ARM::MVE_VLD41_32_wb:
19623
    case ARM::MVE_VLD42_8_wb:
19624
    case ARM::MVE_VLD42_16_wb:
19625
    case ARM::MVE_VLD42_32_wb:
19626
    case ARM::MVE_VLD43_8_wb:
19627
    case ARM::MVE_VLD43_16_wb:
19628
    case ARM::MVE_VLD43_32_wb: {
19629
      switch (OpNum) {
19630
      case 0:
19631
        // op: VQd
19632
        return 13;
19633
      case 3:
19634
        // op: Rn
19635
        return 16;
19636
      }
19637
      break;
19638
    }
19639
    case ARM::VLD1LNd8: {
19640
      switch (OpNum) {
19641
      case 0:
19642
        // op: Vd
19643
        return 12;
19644
      case 1:
19645
        // op: Rn
19646
        return 16;
19647
      case 4:
19648
        // op: lane
19649
        return 5;
19650
      }
19651
      break;
19652
    }
19653
    case ARM::VLD1LNd16: {
19654
      switch (OpNum) {
19655
      case 0:
19656
        // op: Vd
19657
        return 12;
19658
      case 1:
19659
        // op: Rn
19660
        return 4;
19661
      case 4:
19662
        // op: lane
19663
        return 6;
19664
      }
19665
      break;
19666
    }
19667
    case ARM::VLD1LNd32: {
19668
      switch (OpNum) {
19669
      case 0:
19670
        // op: Vd
19671
        return 12;
19672
      case 1:
19673
        // op: Rn
19674
        return 4;
19675
      case 4:
19676
        // op: lane
19677
        return 7;
19678
      }
19679
      break;
19680
    }
19681
    case ARM::VLD1DUPd8:
19682
    case ARM::VLD1DUPd16:
19683
    case ARM::VLD1DUPd32:
19684
    case ARM::VLD1DUPq8:
19685
    case ARM::VLD1DUPq16:
19686
    case ARM::VLD1DUPq32:
19687
    case ARM::VLD1d8:
19688
    case ARM::VLD1d8Q:
19689
    case ARM::VLD1d8T:
19690
    case ARM::VLD1d16:
19691
    case ARM::VLD1d16Q:
19692
    case ARM::VLD1d16T:
19693
    case ARM::VLD1d32:
19694
    case ARM::VLD1d32Q:
19695
    case ARM::VLD1d32T:
19696
    case ARM::VLD1d64:
19697
    case ARM::VLD1d64Q:
19698
    case ARM::VLD1d64T:
19699
    case ARM::VLD1q8:
19700
    case ARM::VLD1q16:
19701
    case ARM::VLD1q32:
19702
    case ARM::VLD1q64:
19703
    case ARM::VLD2DUPd8:
19704
    case ARM::VLD2DUPd8x2:
19705
    case ARM::VLD2DUPd16:
19706
    case ARM::VLD2DUPd16x2:
19707
    case ARM::VLD2DUPd32:
19708
    case ARM::VLD2DUPd32x2:
19709
    case ARM::VLD2b8:
19710
    case ARM::VLD2b16:
19711
    case ARM::VLD2b32:
19712
    case ARM::VLD2d8:
19713
    case ARM::VLD2d16:
19714
    case ARM::VLD2d32:
19715
    case ARM::VLD2q8:
19716
    case ARM::VLD2q16:
19717
    case ARM::VLD2q32: {
19718
      switch (OpNum) {
19719
      case 0:
19720
        // op: Vd
19721
        return 12;
19722
      case 1:
19723
        // op: Rn
19724
        return 4;
19725
      }
19726
      break;
19727
    }
19728
    case ARM::VBICiv2i32:
19729
    case ARM::VBICiv4i16:
19730
    case ARM::VBICiv4i32:
19731
    case ARM::VBICiv8i16:
19732
    case ARM::VMOVv1i64:
19733
    case ARM::VMOVv2f32:
19734
    case ARM::VMOVv2i32:
19735
    case ARM::VMOVv2i64:
19736
    case ARM::VMOVv4f32:
19737
    case ARM::VMOVv4i16:
19738
    case ARM::VMOVv4i32:
19739
    case ARM::VMOVv8i8:
19740
    case ARM::VMOVv8i16:
19741
    case ARM::VMOVv16i8:
19742
    case ARM::VMVNv2i32:
19743
    case ARM::VMVNv4i16:
19744
    case ARM::VMVNv4i32:
19745
    case ARM::VMVNv8i16:
19746
    case ARM::VORRiv2i32:
19747
    case ARM::VORRiv4i16:
19748
    case ARM::VORRiv4i32:
19749
    case ARM::VORRiv8i16: {
19750
      switch (OpNum) {
19751
      case 0:
19752
        // op: Vd
19753
        return 12;
19754
      case 1:
19755
        // op: SIMM
19756
        return 0;
19757
      }
19758
      break;
19759
    }
19760
    case ARM::VCVTf2xsd:
19761
    case ARM::VCVTf2xsq:
19762
    case ARM::VCVTf2xud:
19763
    case ARM::VCVTf2xuq:
19764
    case ARM::VCVTh2xsd:
19765
    case ARM::VCVTh2xsq:
19766
    case ARM::VCVTh2xud:
19767
    case ARM::VCVTh2xuq:
19768
    case ARM::VCVTxs2fd:
19769
    case ARM::VCVTxs2fq:
19770
    case ARM::VCVTxs2hd:
19771
    case ARM::VCVTxs2hq:
19772
    case ARM::VCVTxu2fd:
19773
    case ARM::VCVTxu2fq:
19774
    case ARM::VCVTxu2hd:
19775
    case ARM::VCVTxu2hq:
19776
    case ARM::VQRSHRNsv2i32:
19777
    case ARM::VQRSHRNsv4i16:
19778
    case ARM::VQRSHRNsv8i8:
19779
    case ARM::VQRSHRNuv2i32:
19780
    case ARM::VQRSHRNuv4i16:
19781
    case ARM::VQRSHRNuv8i8:
19782
    case ARM::VQRSHRUNv2i32:
19783
    case ARM::VQRSHRUNv4i16:
19784
    case ARM::VQRSHRUNv8i8:
19785
    case ARM::VQSHLsiv1i64:
19786
    case ARM::VQSHLsiv2i32:
19787
    case ARM::VQSHLsiv2i64:
19788
    case ARM::VQSHLsiv4i16:
19789
    case ARM::VQSHLsiv4i32:
19790
    case ARM::VQSHLsiv8i8:
19791
    case ARM::VQSHLsiv8i16:
19792
    case ARM::VQSHLsiv16i8:
19793
    case ARM::VQSHLsuv1i64:
19794
    case ARM::VQSHLsuv2i32:
19795
    case ARM::VQSHLsuv2i64:
19796
    case ARM::VQSHLsuv4i16:
19797
    case ARM::VQSHLsuv4i32:
19798
    case ARM::VQSHLsuv8i8:
19799
    case ARM::VQSHLsuv8i16:
19800
    case ARM::VQSHLsuv16i8:
19801
    case ARM::VQSHLuiv1i64:
19802
    case ARM::VQSHLuiv2i32:
19803
    case ARM::VQSHLuiv2i64:
19804
    case ARM::VQSHLuiv4i16:
19805
    case ARM::VQSHLuiv4i32:
19806
    case ARM::VQSHLuiv8i8:
19807
    case ARM::VQSHLuiv8i16:
19808
    case ARM::VQSHLuiv16i8:
19809
    case ARM::VQSHRNsv2i32:
19810
    case ARM::VQSHRNsv4i16:
19811
    case ARM::VQSHRNsv8i8:
19812
    case ARM::VQSHRNuv2i32:
19813
    case ARM::VQSHRNuv4i16:
19814
    case ARM::VQSHRNuv8i8:
19815
    case ARM::VQSHRUNv2i32:
19816
    case ARM::VQSHRUNv4i16:
19817
    case ARM::VQSHRUNv8i8:
19818
    case ARM::VRSHRNv2i32:
19819
    case ARM::VRSHRNv4i16:
19820
    case ARM::VRSHRNv8i8:
19821
    case ARM::VRSHRsv1i64:
19822
    case ARM::VRSHRsv2i32:
19823
    case ARM::VRSHRsv2i64:
19824
    case ARM::VRSHRsv4i16:
19825
    case ARM::VRSHRsv4i32:
19826
    case ARM::VRSHRsv8i8:
19827
    case ARM::VRSHRsv8i16:
19828
    case ARM::VRSHRsv16i8:
19829
    case ARM::VRSHRuv1i64:
19830
    case ARM::VRSHRuv2i32:
19831
    case ARM::VRSHRuv2i64:
19832
    case ARM::VRSHRuv4i16:
19833
    case ARM::VRSHRuv4i32:
19834
    case ARM::VRSHRuv8i8:
19835
    case ARM::VRSHRuv8i16:
19836
    case ARM::VRSHRuv16i8:
19837
    case ARM::VSHLLsv2i64:
19838
    case ARM::VSHLLsv4i32:
19839
    case ARM::VSHLLsv8i16:
19840
    case ARM::VSHLLuv2i64:
19841
    case ARM::VSHLLuv4i32:
19842
    case ARM::VSHLLuv8i16:
19843
    case ARM::VSHLiv1i64:
19844
    case ARM::VSHLiv2i32:
19845
    case ARM::VSHLiv2i64:
19846
    case ARM::VSHLiv4i16:
19847
    case ARM::VSHLiv4i32:
19848
    case ARM::VSHLiv8i8:
19849
    case ARM::VSHLiv8i16:
19850
    case ARM::VSHLiv16i8:
19851
    case ARM::VSHRNv2i32:
19852
    case ARM::VSHRNv4i16:
19853
    case ARM::VSHRNv8i8:
19854
    case ARM::VSHRsv1i64:
19855
    case ARM::VSHRsv2i32:
19856
    case ARM::VSHRsv2i64:
19857
    case ARM::VSHRsv4i16:
19858
    case ARM::VSHRsv4i32:
19859
    case ARM::VSHRsv8i8:
19860
    case ARM::VSHRsv8i16:
19861
    case ARM::VSHRsv16i8:
19862
    case ARM::VSHRuv1i64:
19863
    case ARM::VSHRuv2i32:
19864
    case ARM::VSHRuv2i64:
19865
    case ARM::VSHRuv4i16:
19866
    case ARM::VSHRuv4i32:
19867
    case ARM::VSHRuv8i8:
19868
    case ARM::VSHRuv8i16:
19869
    case ARM::VSHRuv16i8: {
19870
      switch (OpNum) {
19871
      case 0:
19872
        // op: Vd
19873
        return 12;
19874
      case 1:
19875
        // op: Vm
19876
        return 0;
19877
      case 2:
19878
        // op: SIMM
19879
        return 16;
19880
      }
19881
      break;
19882
    }
19883
    case ARM::VDUPLN8d:
19884
    case ARM::VDUPLN8q: {
19885
      switch (OpNum) {
19886
      case 0:
19887
        // op: Vd
19888
        return 12;
19889
      case 1:
19890
        // op: Vm
19891
        return 0;
19892
      case 2:
19893
        // op: lane
19894
        return 17;
19895
      }
19896
      break;
19897
    }
19898
    case ARM::VDUPLN16d:
19899
    case ARM::VDUPLN16q: {
19900
      switch (OpNum) {
19901
      case 0:
19902
        // op: Vd
19903
        return 12;
19904
      case 1:
19905
        // op: Vm
19906
        return 0;
19907
      case 2:
19908
        // op: lane
19909
        return 18;
19910
      }
19911
      break;
19912
    }
19913
    case ARM::VDUPLN32d:
19914
    case ARM::VDUPLN32q: {
19915
      switch (OpNum) {
19916
      case 0:
19917
        // op: Vd
19918
        return 12;
19919
      case 1:
19920
        // op: Vm
19921
        return 0;
19922
      case 2:
19923
        // op: lane
19924
        return 19;
19925
      }
19926
      break;
19927
    }
19928
    case ARM::AESIMC:
19929
    case ARM::AESMC:
19930
    case ARM::BF16_VCVT:
19931
    case ARM::SHA1H:
19932
    case ARM::VABSfd:
19933
    case ARM::VABSfq:
19934
    case ARM::VABShd:
19935
    case ARM::VABShq:
19936
    case ARM::VABSv2i32:
19937
    case ARM::VABSv4i16:
19938
    case ARM::VABSv4i32:
19939
    case ARM::VABSv8i8:
19940
    case ARM::VABSv8i16:
19941
    case ARM::VABSv16i8:
19942
    case ARM::VCEQzv2f32:
19943
    case ARM::VCEQzv2i32:
19944
    case ARM::VCEQzv4f16:
19945
    case ARM::VCEQzv4f32:
19946
    case ARM::VCEQzv4i16:
19947
    case ARM::VCEQzv4i32:
19948
    case ARM::VCEQzv8f16:
19949
    case ARM::VCEQzv8i8:
19950
    case ARM::VCEQzv8i16:
19951
    case ARM::VCEQzv16i8:
19952
    case ARM::VCGEzv2f32:
19953
    case ARM::VCGEzv2i32:
19954
    case ARM::VCGEzv4f16:
19955
    case ARM::VCGEzv4f32:
19956
    case ARM::VCGEzv4i16:
19957
    case ARM::VCGEzv4i32:
19958
    case ARM::VCGEzv8f16:
19959
    case ARM::VCGEzv8i8:
19960
    case ARM::VCGEzv8i16:
19961
    case ARM::VCGEzv16i8:
19962
    case ARM::VCGTzv2f32:
19963
    case ARM::VCGTzv2i32:
19964
    case ARM::VCGTzv4f16:
19965
    case ARM::VCGTzv4f32:
19966
    case ARM::VCGTzv4i16:
19967
    case ARM::VCGTzv4i32:
19968
    case ARM::VCGTzv8f16:
19969
    case ARM::VCGTzv8i8:
19970
    case ARM::VCGTzv8i16:
19971
    case ARM::VCGTzv16i8:
19972
    case ARM::VCLEzv2f32:
19973
    case ARM::VCLEzv2i32:
19974
    case ARM::VCLEzv4f16:
19975
    case ARM::VCLEzv4f32:
19976
    case ARM::VCLEzv4i16:
19977
    case ARM::VCLEzv4i32:
19978
    case ARM::VCLEzv8f16:
19979
    case ARM::VCLEzv8i8:
19980
    case ARM::VCLEzv8i16:
19981
    case ARM::VCLEzv16i8:
19982
    case ARM::VCLSv2i32:
19983
    case ARM::VCLSv4i16:
19984
    case ARM::VCLSv4i32:
19985
    case ARM::VCLSv8i8:
19986
    case ARM::VCLSv8i16:
19987
    case ARM::VCLSv16i8:
19988
    case ARM::VCLTzv2f32:
19989
    case ARM::VCLTzv2i32:
19990
    case ARM::VCLTzv4f16:
19991
    case ARM::VCLTzv4f32:
19992
    case ARM::VCLTzv4i16:
19993
    case ARM::VCLTzv4i32:
19994
    case ARM::VCLTzv8f16:
19995
    case ARM::VCLTzv8i8:
19996
    case ARM::VCLTzv8i16:
19997
    case ARM::VCLTzv16i8:
19998
    case ARM::VCLZv2i32:
19999
    case ARM::VCLZv4i16:
20000
    case ARM::VCLZv4i32:
20001
    case ARM::VCLZv8i8:
20002
    case ARM::VCLZv8i16:
20003
    case ARM::VCLZv16i8:
20004
    case ARM::VCNTd:
20005
    case ARM::VCNTq:
20006
    case ARM::VCVTANSDf:
20007
    case ARM::VCVTANSDh:
20008
    case ARM::VCVTANSQf:
20009
    case ARM::VCVTANSQh:
20010
    case ARM::VCVTANUDf:
20011
    case ARM::VCVTANUDh:
20012
    case ARM::VCVTANUQf:
20013
    case ARM::VCVTANUQh:
20014
    case ARM::VCVTMNSDf:
20015
    case ARM::VCVTMNSDh:
20016
    case ARM::VCVTMNSQf:
20017
    case ARM::VCVTMNSQh:
20018
    case ARM::VCVTMNUDf:
20019
    case ARM::VCVTMNUDh:
20020
    case ARM::VCVTMNUQf:
20021
    case ARM::VCVTMNUQh:
20022
    case ARM::VCVTNNSDf:
20023
    case ARM::VCVTNNSDh:
20024
    case ARM::VCVTNNSQf:
20025
    case ARM::VCVTNNSQh:
20026
    case ARM::VCVTNNUDf:
20027
    case ARM::VCVTNNUDh:
20028
    case ARM::VCVTNNUQf:
20029
    case ARM::VCVTNNUQh:
20030
    case ARM::VCVTPNSDf:
20031
    case ARM::VCVTPNSDh:
20032
    case ARM::VCVTPNSQf:
20033
    case ARM::VCVTPNSQh:
20034
    case ARM::VCVTPNUDf:
20035
    case ARM::VCVTPNUDh:
20036
    case ARM::VCVTPNUQf:
20037
    case ARM::VCVTPNUQh:
20038
    case ARM::VCVTf2h:
20039
    case ARM::VCVTf2sd:
20040
    case ARM::VCVTf2sq:
20041
    case ARM::VCVTf2ud:
20042
    case ARM::VCVTf2uq:
20043
    case ARM::VCVTh2f:
20044
    case ARM::VCVTh2sd:
20045
    case ARM::VCVTh2sq:
20046
    case ARM::VCVTh2ud:
20047
    case ARM::VCVTh2uq:
20048
    case ARM::VCVTs2fd:
20049
    case ARM::VCVTs2fq:
20050
    case ARM::VCVTs2hd:
20051
    case ARM::VCVTs2hq:
20052
    case ARM::VCVTu2fd:
20053
    case ARM::VCVTu2fq:
20054
    case ARM::VCVTu2hd:
20055
    case ARM::VCVTu2hq:
20056
    case ARM::VMOVLsv2i64:
20057
    case ARM::VMOVLsv4i32:
20058
    case ARM::VMOVLsv8i16:
20059
    case ARM::VMOVLuv2i64:
20060
    case ARM::VMOVLuv4i32:
20061
    case ARM::VMOVLuv8i16:
20062
    case ARM::VMOVNv2i32:
20063
    case ARM::VMOVNv4i16:
20064
    case ARM::VMOVNv8i8:
20065
    case ARM::VMVNd:
20066
    case ARM::VMVNq:
20067
    case ARM::VNEGf32q:
20068
    case ARM::VNEGfd:
20069
    case ARM::VNEGhd:
20070
    case ARM::VNEGhq:
20071
    case ARM::VNEGs8d:
20072
    case ARM::VNEGs8q:
20073
    case ARM::VNEGs16d:
20074
    case ARM::VNEGs16q:
20075
    case ARM::VNEGs32d:
20076
    case ARM::VNEGs32q:
20077
    case ARM::VPADDLsv2i32:
20078
    case ARM::VPADDLsv4i16:
20079
    case ARM::VPADDLsv4i32:
20080
    case ARM::VPADDLsv8i8:
20081
    case ARM::VPADDLsv8i16:
20082
    case ARM::VPADDLsv16i8:
20083
    case ARM::VPADDLuv2i32:
20084
    case ARM::VPADDLuv4i16:
20085
    case ARM::VPADDLuv4i32:
20086
    case ARM::VPADDLuv8i8:
20087
    case ARM::VPADDLuv8i16:
20088
    case ARM::VPADDLuv16i8:
20089
    case ARM::VQABSv2i32:
20090
    case ARM::VQABSv4i16:
20091
    case ARM::VQABSv4i32:
20092
    case ARM::VQABSv8i8:
20093
    case ARM::VQABSv8i16:
20094
    case ARM::VQABSv16i8:
20095
    case ARM::VQMOVNsuv2i32:
20096
    case ARM::VQMOVNsuv4i16:
20097
    case ARM::VQMOVNsuv8i8:
20098
    case ARM::VQMOVNsv2i32:
20099
    case ARM::VQMOVNsv4i16:
20100
    case ARM::VQMOVNsv8i8:
20101
    case ARM::VQMOVNuv2i32:
20102
    case ARM::VQMOVNuv4i16:
20103
    case ARM::VQMOVNuv8i8:
20104
    case ARM::VQNEGv2i32:
20105
    case ARM::VQNEGv4i16:
20106
    case ARM::VQNEGv4i32:
20107
    case ARM::VQNEGv8i8:
20108
    case ARM::VQNEGv8i16:
20109
    case ARM::VQNEGv16i8:
20110
    case ARM::VRECPEd:
20111
    case ARM::VRECPEfd:
20112
    case ARM::VRECPEfq:
20113
    case ARM::VRECPEhd:
20114
    case ARM::VRECPEhq:
20115
    case ARM::VRECPEq:
20116
    case ARM::VREV16d8:
20117
    case ARM::VREV16q8:
20118
    case ARM::VREV32d8:
20119
    case ARM::VREV32d16:
20120
    case ARM::VREV32q8:
20121
    case ARM::VREV32q16:
20122
    case ARM::VREV64d8:
20123
    case ARM::VREV64d16:
20124
    case ARM::VREV64d32:
20125
    case ARM::VREV64q8:
20126
    case ARM::VREV64q16:
20127
    case ARM::VREV64q32:
20128
    case ARM::VRINTANDf:
20129
    case ARM::VRINTANDh:
20130
    case ARM::VRINTANQf:
20131
    case ARM::VRINTANQh:
20132
    case ARM::VRINTMNDf:
20133
    case ARM::VRINTMNDh:
20134
    case ARM::VRINTMNQf:
20135
    case ARM::VRINTMNQh:
20136
    case ARM::VRINTNNDf:
20137
    case ARM::VRINTNNDh:
20138
    case ARM::VRINTNNQf:
20139
    case ARM::VRINTNNQh:
20140
    case ARM::VRINTPNDf:
20141
    case ARM::VRINTPNDh:
20142
    case ARM::VRINTPNQf:
20143
    case ARM::VRINTPNQh:
20144
    case ARM::VRINTXNDf:
20145
    case ARM::VRINTXNDh:
20146
    case ARM::VRINTXNQf:
20147
    case ARM::VRINTXNQh:
20148
    case ARM::VRINTZNDf:
20149
    case ARM::VRINTZNDh:
20150
    case ARM::VRINTZNQf:
20151
    case ARM::VRINTZNQh:
20152
    case ARM::VRSQRTEd:
20153
    case ARM::VRSQRTEfd:
20154
    case ARM::VRSQRTEfq:
20155
    case ARM::VRSQRTEhd:
20156
    case ARM::VRSQRTEhq:
20157
    case ARM::VRSQRTEq:
20158
    case ARM::VSHLLi8:
20159
    case ARM::VSHLLi16:
20160
    case ARM::VSHLLi32:
20161
    case ARM::VSWPd:
20162
    case ARM::VSWPq:
20163
    case ARM::VTRNd8:
20164
    case ARM::VTRNd16:
20165
    case ARM::VTRNd32:
20166
    case ARM::VTRNq8:
20167
    case ARM::VTRNq16:
20168
    case ARM::VTRNq32:
20169
    case ARM::VUZPd8:
20170
    case ARM::VUZPd16:
20171
    case ARM::VUZPq8:
20172
    case ARM::VUZPq16:
20173
    case ARM::VUZPq32:
20174
    case ARM::VZIPd8:
20175
    case ARM::VZIPd16:
20176
    case ARM::VZIPq8:
20177
    case ARM::VZIPq16:
20178
    case ARM::VZIPq32: {
20179
      switch (OpNum) {
20180
      case 0:
20181
        // op: Vd
20182
        return 12;
20183
      case 1:
20184
        // op: Vm
20185
        return 0;
20186
      }
20187
      break;
20188
    }
20189
    case ARM::VFMALDI:
20190
    case ARM::VFMALQI:
20191
    case ARM::VFMSLDI:
20192
    case ARM::VFMSLQI: {
20193
      switch (OpNum) {
20194
      case 0:
20195
        // op: Vd
20196
        return 12;
20197
      case 1:
20198
        // op: Vn
20199
        return 7;
20200
      case 2:
20201
        // op: Vm
20202
        return 0;
20203
      case 3:
20204
        // op: idx
20205
        return 3;
20206
      }
20207
      break;
20208
    }
20209
    case ARM::VEXTd32:
20210
    case ARM::VEXTq32: {
20211
      switch (OpNum) {
20212
      case 0:
20213
        // op: Vd
20214
        return 12;
20215
      case 1:
20216
        // op: Vn
20217
        return 7;
20218
      case 2:
20219
        // op: Vm
20220
        return 0;
20221
      case 3:
20222
        // op: index
20223
        return 10;
20224
      }
20225
      break;
20226
    }
20227
    case ARM::VEXTq64: {
20228
      switch (OpNum) {
20229
      case 0:
20230
        // op: Vd
20231
        return 12;
20232
      case 1:
20233
        // op: Vn
20234
        return 7;
20235
      case 2:
20236
        // op: Vm
20237
        return 0;
20238
      case 3:
20239
        // op: index
20240
        return 11;
20241
      }
20242
      break;
20243
    }
20244
    case ARM::VEXTd8:
20245
    case ARM::VEXTq8: {
20246
      switch (OpNum) {
20247
      case 0:
20248
        // op: Vd
20249
        return 12;
20250
      case 1:
20251
        // op: Vn
20252
        return 7;
20253
      case 2:
20254
        // op: Vm
20255
        return 0;
20256
      case 3:
20257
        // op: index
20258
        return 8;
20259
      }
20260
      break;
20261
    }
20262
    case ARM::VEXTd16:
20263
    case ARM::VEXTq16: {
20264
      switch (OpNum) {
20265
      case 0:
20266
        // op: Vd
20267
        return 12;
20268
      case 1:
20269
        // op: Vn
20270
        return 7;
20271
      case 2:
20272
        // op: Vm
20273
        return 0;
20274
      case 3:
20275
        // op: index
20276
        return 9;
20277
      }
20278
      break;
20279
    }
20280
    case ARM::VMULLslsv4i16:
20281
    case ARM::VMULLsluv4i16:
20282
    case ARM::VMULslhd:
20283
    case ARM::VMULslhq:
20284
    case ARM::VMULslv4i16:
20285
    case ARM::VMULslv8i16:
20286
    case ARM::VQDMULHslv4i16:
20287
    case ARM::VQDMULHslv8i16:
20288
    case ARM::VQDMULLslv4i16:
20289
    case ARM::VQRDMULHslv4i16:
20290
    case ARM::VQRDMULHslv8i16: {
20291
      switch (OpNum) {
20292
      case 0:
20293
        // op: Vd
20294
        return 12;
20295
      case 1:
20296
        // op: Vn
20297
        return 7;
20298
      case 2:
20299
        // op: Vm
20300
        return 0;
20301
      case 3:
20302
        // op: lane
20303
        return 3;
20304
      }
20305
      break;
20306
    }
20307
    case ARM::VMULLslsv2i32:
20308
    case ARM::VMULLsluv2i32:
20309
    case ARM::VMULslfd:
20310
    case ARM::VMULslfq:
20311
    case ARM::VMULslv2i32:
20312
    case ARM::VMULslv4i32:
20313
    case ARM::VQDMULHslv2i32:
20314
    case ARM::VQDMULHslv4i32:
20315
    case ARM::VQDMULLslv2i32:
20316
    case ARM::VQRDMULHslv2i32:
20317
    case ARM::VQRDMULHslv4i32: {
20318
      switch (OpNum) {
20319
      case 0:
20320
        // op: Vd
20321
        return 12;
20322
      case 1:
20323
        // op: Vn
20324
        return 7;
20325
      case 2:
20326
        // op: Vm
20327
        return 0;
20328
      case 3:
20329
        // op: lane
20330
        return 5;
20331
      }
20332
      break;
20333
    }
20334
    case ARM::VCADDv2f32:
20335
    case ARM::VCADDv4f16:
20336
    case ARM::VCADDv4f32:
20337
    case ARM::VCADDv8f16: {
20338
      switch (OpNum) {
20339
      case 0:
20340
        // op: Vd
20341
        return 12;
20342
      case 1:
20343
        // op: Vn
20344
        return 7;
20345
      case 2:
20346
        // op: Vm
20347
        return 0;
20348
      case 3:
20349
        // op: rot
20350
        return 24;
20351
      }
20352
      break;
20353
    }
20354
    case ARM::NEON_VMAXNMNDf:
20355
    case ARM::NEON_VMAXNMNDh:
20356
    case ARM::NEON_VMAXNMNQf:
20357
    case ARM::NEON_VMAXNMNQh:
20358
    case ARM::NEON_VMINNMNDf:
20359
    case ARM::NEON_VMINNMNDh:
20360
    case ARM::NEON_VMINNMNQf:
20361
    case ARM::NEON_VMINNMNQh:
20362
    case ARM::VABDLsv2i64:
20363
    case ARM::VABDLsv4i32:
20364
    case ARM::VABDLsv8i16:
20365
    case ARM::VABDLuv2i64:
20366
    case ARM::VABDLuv4i32:
20367
    case ARM::VABDLuv8i16:
20368
    case ARM::VABDfd:
20369
    case ARM::VABDfq:
20370
    case ARM::VABDhd:
20371
    case ARM::VABDhq:
20372
    case ARM::VABDsv2i32:
20373
    case ARM::VABDsv4i16:
20374
    case ARM::VABDsv4i32:
20375
    case ARM::VABDsv8i8:
20376
    case ARM::VABDsv8i16:
20377
    case ARM::VABDsv16i8:
20378
    case ARM::VABDuv2i32:
20379
    case ARM::VABDuv4i16:
20380
    case ARM::VABDuv4i32:
20381
    case ARM::VABDuv8i8:
20382
    case ARM::VABDuv8i16:
20383
    case ARM::VABDuv16i8:
20384
    case ARM::VACGEfd:
20385
    case ARM::VACGEfq:
20386
    case ARM::VACGEhd:
20387
    case ARM::VACGEhq:
20388
    case ARM::VACGTfd:
20389
    case ARM::VACGTfq:
20390
    case ARM::VACGThd:
20391
    case ARM::VACGThq:
20392
    case ARM::VADDHNv2i32:
20393
    case ARM::VADDHNv4i16:
20394
    case ARM::VADDHNv8i8:
20395
    case ARM::VADDLsv2i64:
20396
    case ARM::VADDLsv4i32:
20397
    case ARM::VADDLsv8i16:
20398
    case ARM::VADDLuv2i64:
20399
    case ARM::VADDLuv4i32:
20400
    case ARM::VADDLuv8i16:
20401
    case ARM::VADDWsv2i64:
20402
    case ARM::VADDWsv4i32:
20403
    case ARM::VADDWsv8i16:
20404
    case ARM::VADDWuv2i64:
20405
    case ARM::VADDWuv4i32:
20406
    case ARM::VADDWuv8i16:
20407
    case ARM::VADDfd:
20408
    case ARM::VADDfq:
20409
    case ARM::VADDhd:
20410
    case ARM::VADDhq:
20411
    case ARM::VADDv1i64:
20412
    case ARM::VADDv2i32:
20413
    case ARM::VADDv2i64:
20414
    case ARM::VADDv4i16:
20415
    case ARM::VADDv4i32:
20416
    case ARM::VADDv8i8:
20417
    case ARM::VADDv8i16:
20418
    case ARM::VADDv16i8:
20419
    case ARM::VANDd:
20420
    case ARM::VANDq:
20421
    case ARM::VBICd:
20422
    case ARM::VBICq:
20423
    case ARM::VCEQfd:
20424
    case ARM::VCEQfq:
20425
    case ARM::VCEQhd:
20426
    case ARM::VCEQhq:
20427
    case ARM::VCEQv2i32:
20428
    case ARM::VCEQv4i16:
20429
    case ARM::VCEQv4i32:
20430
    case ARM::VCEQv8i8:
20431
    case ARM::VCEQv8i16:
20432
    case ARM::VCEQv16i8:
20433
    case ARM::VCGEfd:
20434
    case ARM::VCGEfq:
20435
    case ARM::VCGEhd:
20436
    case ARM::VCGEhq:
20437
    case ARM::VCGEsv2i32:
20438
    case ARM::VCGEsv4i16:
20439
    case ARM::VCGEsv4i32:
20440
    case ARM::VCGEsv8i8:
20441
    case ARM::VCGEsv8i16:
20442
    case ARM::VCGEsv16i8:
20443
    case ARM::VCGEuv2i32:
20444
    case ARM::VCGEuv4i16:
20445
    case ARM::VCGEuv4i32:
20446
    case ARM::VCGEuv8i8:
20447
    case ARM::VCGEuv8i16:
20448
    case ARM::VCGEuv16i8:
20449
    case ARM::VCGTfd:
20450
    case ARM::VCGTfq:
20451
    case ARM::VCGThd:
20452
    case ARM::VCGThq:
20453
    case ARM::VCGTsv2i32:
20454
    case ARM::VCGTsv4i16:
20455
    case ARM::VCGTsv4i32:
20456
    case ARM::VCGTsv8i8:
20457
    case ARM::VCGTsv8i16:
20458
    case ARM::VCGTsv16i8:
20459
    case ARM::VCGTuv2i32:
20460
    case ARM::VCGTuv4i16:
20461
    case ARM::VCGTuv4i32:
20462
    case ARM::VCGTuv8i8:
20463
    case ARM::VCGTuv8i16:
20464
    case ARM::VCGTuv16i8:
20465
    case ARM::VEORd:
20466
    case ARM::VEORq:
20467
    case ARM::VFMALD:
20468
    case ARM::VFMALQ:
20469
    case ARM::VFMSLD:
20470
    case ARM::VFMSLQ:
20471
    case ARM::VHADDsv2i32:
20472
    case ARM::VHADDsv4i16:
20473
    case ARM::VHADDsv4i32:
20474
    case ARM::VHADDsv8i8:
20475
    case ARM::VHADDsv8i16:
20476
    case ARM::VHADDsv16i8:
20477
    case ARM::VHADDuv2i32:
20478
    case ARM::VHADDuv4i16:
20479
    case ARM::VHADDuv4i32:
20480
    case ARM::VHADDuv8i8:
20481
    case ARM::VHADDuv8i16:
20482
    case ARM::VHADDuv16i8:
20483
    case ARM::VHSUBsv2i32:
20484
    case ARM::VHSUBsv4i16:
20485
    case ARM::VHSUBsv4i32:
20486
    case ARM::VHSUBsv8i8:
20487
    case ARM::VHSUBsv8i16:
20488
    case ARM::VHSUBsv16i8:
20489
    case ARM::VHSUBuv2i32:
20490
    case ARM::VHSUBuv4i16:
20491
    case ARM::VHSUBuv4i32:
20492
    case ARM::VHSUBuv8i8:
20493
    case ARM::VHSUBuv8i16:
20494
    case ARM::VHSUBuv16i8:
20495
    case ARM::VMAXfd:
20496
    case ARM::VMAXfq:
20497
    case ARM::VMAXhd:
20498
    case ARM::VMAXhq:
20499
    case ARM::VMAXsv2i32:
20500
    case ARM::VMAXsv4i16:
20501
    case ARM::VMAXsv4i32:
20502
    case ARM::VMAXsv8i8:
20503
    case ARM::VMAXsv8i16:
20504
    case ARM::VMAXsv16i8:
20505
    case ARM::VMAXuv2i32:
20506
    case ARM::VMAXuv4i16:
20507
    case ARM::VMAXuv4i32:
20508
    case ARM::VMAXuv8i8:
20509
    case ARM::VMAXuv8i16:
20510
    case ARM::VMAXuv16i8:
20511
    case ARM::VMINfd:
20512
    case ARM::VMINfq:
20513
    case ARM::VMINhd:
20514
    case ARM::VMINhq:
20515
    case ARM::VMINsv2i32:
20516
    case ARM::VMINsv4i16:
20517
    case ARM::VMINsv4i32:
20518
    case ARM::VMINsv8i8:
20519
    case ARM::VMINsv8i16:
20520
    case ARM::VMINsv16i8:
20521
    case ARM::VMINuv2i32:
20522
    case ARM::VMINuv4i16:
20523
    case ARM::VMINuv4i32:
20524
    case ARM::VMINuv8i8:
20525
    case ARM::VMINuv8i16:
20526
    case ARM::VMINuv16i8:
20527
    case ARM::VMULLp8:
20528
    case ARM::VMULLp64:
20529
    case ARM::VMULLsv2i64:
20530
    case ARM::VMULLsv4i32:
20531
    case ARM::VMULLsv8i16:
20532
    case ARM::VMULLuv2i64:
20533
    case ARM::VMULLuv4i32:
20534
    case ARM::VMULLuv8i16:
20535
    case ARM::VMULfd:
20536
    case ARM::VMULfq:
20537
    case ARM::VMULhd:
20538
    case ARM::VMULhq:
20539
    case ARM::VMULpd:
20540
    case ARM::VMULpq:
20541
    case ARM::VMULv2i32:
20542
    case ARM::VMULv4i16:
20543
    case ARM::VMULv4i32:
20544
    case ARM::VMULv8i8:
20545
    case ARM::VMULv8i16:
20546
    case ARM::VMULv16i8:
20547
    case ARM::VORNd:
20548
    case ARM::VORNq:
20549
    case ARM::VORRd:
20550
    case ARM::VORRq:
20551
    case ARM::VPADDf:
20552
    case ARM::VPADDh:
20553
    case ARM::VPADDi8:
20554
    case ARM::VPADDi16:
20555
    case ARM::VPADDi32:
20556
    case ARM::VPMAXf:
20557
    case ARM::VPMAXh:
20558
    case ARM::VPMAXs8:
20559
    case ARM::VPMAXs16:
20560
    case ARM::VPMAXs32:
20561
    case ARM::VPMAXu8:
20562
    case ARM::VPMAXu16:
20563
    case ARM::VPMAXu32:
20564
    case ARM::VPMINf:
20565
    case ARM::VPMINh:
20566
    case ARM::VPMINs8:
20567
    case ARM::VPMINs16:
20568
    case ARM::VPMINs32:
20569
    case ARM::VPMINu8:
20570
    case ARM::VPMINu16:
20571
    case ARM::VPMINu32:
20572
    case ARM::VQADDsv1i64:
20573
    case ARM::VQADDsv2i32:
20574
    case ARM::VQADDsv2i64:
20575
    case ARM::VQADDsv4i16:
20576
    case ARM::VQADDsv4i32:
20577
    case ARM::VQADDsv8i8:
20578
    case ARM::VQADDsv8i16:
20579
    case ARM::VQADDsv16i8:
20580
    case ARM::VQADDuv1i64:
20581
    case ARM::VQADDuv2i32:
20582
    case ARM::VQADDuv2i64:
20583
    case ARM::VQADDuv4i16:
20584
    case ARM::VQADDuv4i32:
20585
    case ARM::VQADDuv8i8:
20586
    case ARM::VQADDuv8i16:
20587
    case ARM::VQADDuv16i8:
20588
    case ARM::VQDMULHv2i32:
20589
    case ARM::VQDMULHv4i16:
20590
    case ARM::VQDMULHv4i32:
20591
    case ARM::VQDMULHv8i16:
20592
    case ARM::VQDMULLv2i64:
20593
    case ARM::VQDMULLv4i32:
20594
    case ARM::VQRDMULHv2i32:
20595
    case ARM::VQRDMULHv4i16:
20596
    case ARM::VQRDMULHv4i32:
20597
    case ARM::VQRDMULHv8i16:
20598
    case ARM::VQSUBsv1i64:
20599
    case ARM::VQSUBsv2i32:
20600
    case ARM::VQSUBsv2i64:
20601
    case ARM::VQSUBsv4i16:
20602
    case ARM::VQSUBsv4i32:
20603
    case ARM::VQSUBsv8i8:
20604
    case ARM::VQSUBsv8i16:
20605
    case ARM::VQSUBsv16i8:
20606
    case ARM::VQSUBuv1i64:
20607
    case ARM::VQSUBuv2i32:
20608
    case ARM::VQSUBuv2i64:
20609
    case ARM::VQSUBuv4i16:
20610
    case ARM::VQSUBuv4i32:
20611
    case ARM::VQSUBuv8i8:
20612
    case ARM::VQSUBuv8i16:
20613
    case ARM::VQSUBuv16i8:
20614
    case ARM::VRADDHNv2i32:
20615
    case ARM::VRADDHNv4i16:
20616
    case ARM::VRADDHNv8i8:
20617
    case ARM::VRECPSfd:
20618
    case ARM::VRECPSfq:
20619
    case ARM::VRECPShd:
20620
    case ARM::VRECPShq:
20621
    case ARM::VRHADDsv2i32:
20622
    case ARM::VRHADDsv4i16:
20623
    case ARM::VRHADDsv4i32:
20624
    case ARM::VRHADDsv8i8:
20625
    case ARM::VRHADDsv8i16:
20626
    case ARM::VRHADDsv16i8:
20627
    case ARM::VRHADDuv2i32:
20628
    case ARM::VRHADDuv4i16:
20629
    case ARM::VRHADDuv4i32:
20630
    case ARM::VRHADDuv8i8:
20631
    case ARM::VRHADDuv8i16:
20632
    case ARM::VRHADDuv16i8:
20633
    case ARM::VRSQRTSfd:
20634
    case ARM::VRSQRTSfq:
20635
    case ARM::VRSQRTShd:
20636
    case ARM::VRSQRTShq:
20637
    case ARM::VRSUBHNv2i32:
20638
    case ARM::VRSUBHNv4i16:
20639
    case ARM::VRSUBHNv8i8:
20640
    case ARM::VSUBHNv2i32:
20641
    case ARM::VSUBHNv4i16:
20642
    case ARM::VSUBHNv8i8:
20643
    case ARM::VSUBLsv2i64:
20644
    case ARM::VSUBLsv4i32:
20645
    case ARM::VSUBLsv8i16:
20646
    case ARM::VSUBLuv2i64:
20647
    case ARM::VSUBLuv4i32:
20648
    case ARM::VSUBLuv8i16:
20649
    case ARM::VSUBWsv2i64:
20650
    case ARM::VSUBWsv4i32:
20651
    case ARM::VSUBWsv8i16:
20652
    case ARM::VSUBWuv2i64:
20653
    case ARM::VSUBWuv4i32:
20654
    case ARM::VSUBWuv8i16:
20655
    case ARM::VSUBfd:
20656
    case ARM::VSUBfq:
20657
    case ARM::VSUBhd:
20658
    case ARM::VSUBhq:
20659
    case ARM::VSUBv1i64:
20660
    case ARM::VSUBv2i32:
20661
    case ARM::VSUBv2i64:
20662
    case ARM::VSUBv4i16:
20663
    case ARM::VSUBv4i32:
20664
    case ARM::VSUBv8i8:
20665
    case ARM::VSUBv8i16:
20666
    case ARM::VSUBv16i8:
20667
    case ARM::VTBL1:
20668
    case ARM::VTBL2:
20669
    case ARM::VTBL3:
20670
    case ARM::VTBL4:
20671
    case ARM::VTSTv2i32:
20672
    case ARM::VTSTv4i16:
20673
    case ARM::VTSTv4i32:
20674
    case ARM::VTSTv8i8:
20675
    case ARM::VTSTv8i16:
20676
    case ARM::VTSTv16i8: {
20677
      switch (OpNum) {
20678
      case 0:
20679
        // op: Vd
20680
        return 12;
20681
      case 1:
20682
        // op: Vn
20683
        return 7;
20684
      case 2:
20685
        // op: Vm
20686
        return 0;
20687
      }
20688
      break;
20689
    }
20690
    case ARM::VLD1LNd8_UPD: {
20691
      switch (OpNum) {
20692
      case 0:
20693
        // op: Vd
20694
        return 12;
20695
      case 2:
20696
        // op: Rn
20697
        return 16;
20698
      case 4:
20699
        // op: Rm
20700
        return 0;
20701
      case 6:
20702
        // op: lane
20703
        return 5;
20704
      }
20705
      break;
20706
    }
20707
    case ARM::VLD1LNd16_UPD: {
20708
      switch (OpNum) {
20709
      case 0:
20710
        // op: Vd
20711
        return 12;
20712
      case 2:
20713
        // op: Rn
20714
        return 4;
20715
      case 4:
20716
        // op: Rm
20717
        return 0;
20718
      case 6:
20719
        // op: lane
20720
        return 6;
20721
      }
20722
      break;
20723
    }
20724
    case ARM::VLD1LNd32_UPD: {
20725
      switch (OpNum) {
20726
      case 0:
20727
        // op: Vd
20728
        return 12;
20729
      case 2:
20730
        // op: Rn
20731
        return 4;
20732
      case 4:
20733
        // op: Rm
20734
        return 0;
20735
      case 6:
20736
        // op: lane
20737
        return 7;
20738
      }
20739
      break;
20740
    }
20741
    case ARM::VLD1DUPd8wb_register:
20742
    case ARM::VLD1DUPd16wb_register:
20743
    case ARM::VLD1DUPd32wb_register:
20744
    case ARM::VLD1DUPq8wb_register:
20745
    case ARM::VLD1DUPq16wb_register:
20746
    case ARM::VLD1DUPq32wb_register:
20747
    case ARM::VLD1d8Qwb_register:
20748
    case ARM::VLD1d8Twb_register:
20749
    case ARM::VLD1d8wb_register:
20750
    case ARM::VLD1d16Qwb_register:
20751
    case ARM::VLD1d16Twb_register:
20752
    case ARM::VLD1d16wb_register:
20753
    case ARM::VLD1d32Qwb_register:
20754
    case ARM::VLD1d32Twb_register:
20755
    case ARM::VLD1d32wb_register:
20756
    case ARM::VLD1d64Qwb_register:
20757
    case ARM::VLD1d64Twb_register:
20758
    case ARM::VLD1d64wb_register:
20759
    case ARM::VLD1q8wb_register:
20760
    case ARM::VLD1q16wb_register:
20761
    case ARM::VLD1q32wb_register:
20762
    case ARM::VLD1q64wb_register:
20763
    case ARM::VLD2DUPd8wb_register:
20764
    case ARM::VLD2DUPd8x2wb_register:
20765
    case ARM::VLD2DUPd16wb_register:
20766
    case ARM::VLD2DUPd16x2wb_register:
20767
    case ARM::VLD2DUPd32wb_register:
20768
    case ARM::VLD2DUPd32x2wb_register:
20769
    case ARM::VLD2b8wb_register:
20770
    case ARM::VLD2b16wb_register:
20771
    case ARM::VLD2b32wb_register:
20772
    case ARM::VLD2d8wb_register:
20773
    case ARM::VLD2d16wb_register:
20774
    case ARM::VLD2d32wb_register:
20775
    case ARM::VLD2q8wb_register:
20776
    case ARM::VLD2q16wb_register:
20777
    case ARM::VLD2q32wb_register: {
20778
      switch (OpNum) {
20779
      case 0:
20780
        // op: Vd
20781
        return 12;
20782
      case 2:
20783
        // op: Rn
20784
        return 4;
20785
      case 4:
20786
        // op: Rm
20787
        return 0;
20788
      }
20789
      break;
20790
    }
20791
    case ARM::VLD2LNd8: {
20792
      switch (OpNum) {
20793
      case 0:
20794
        // op: Vd
20795
        return 12;
20796
      case 2:
20797
        // op: Rn
20798
        return 4;
20799
      case 6:
20800
        // op: lane
20801
        return 5;
20802
      }
20803
      break;
20804
    }
20805
    case ARM::VLD2LNd16:
20806
    case ARM::VLD2LNq16: {
20807
      switch (OpNum) {
20808
      case 0:
20809
        // op: Vd
20810
        return 12;
20811
      case 2:
20812
        // op: Rn
20813
        return 4;
20814
      case 6:
20815
        // op: lane
20816
        return 6;
20817
      }
20818
      break;
20819
    }
20820
    case ARM::VLD2LNd32:
20821
    case ARM::VLD2LNq32: {
20822
      switch (OpNum) {
20823
      case 0:
20824
        // op: Vd
20825
        return 12;
20826
      case 2:
20827
        // op: Rn
20828
        return 4;
20829
      case 6:
20830
        // op: lane
20831
        return 7;
20832
      }
20833
      break;
20834
    }
20835
    case ARM::VLD1DUPd8wb_fixed:
20836
    case ARM::VLD1DUPd16wb_fixed:
20837
    case ARM::VLD1DUPd32wb_fixed:
20838
    case ARM::VLD1DUPq8wb_fixed:
20839
    case ARM::VLD1DUPq16wb_fixed:
20840
    case ARM::VLD1DUPq32wb_fixed:
20841
    case ARM::VLD1d8Qwb_fixed:
20842
    case ARM::VLD1d8Twb_fixed:
20843
    case ARM::VLD1d8wb_fixed:
20844
    case ARM::VLD1d16Qwb_fixed:
20845
    case ARM::VLD1d16Twb_fixed:
20846
    case ARM::VLD1d16wb_fixed:
20847
    case ARM::VLD1d32Qwb_fixed:
20848
    case ARM::VLD1d32Twb_fixed:
20849
    case ARM::VLD1d32wb_fixed:
20850
    case ARM::VLD1d64Qwb_fixed:
20851
    case ARM::VLD1d64Twb_fixed:
20852
    case ARM::VLD1d64wb_fixed:
20853
    case ARM::VLD1q8wb_fixed:
20854
    case ARM::VLD1q16wb_fixed:
20855
    case ARM::VLD1q32wb_fixed:
20856
    case ARM::VLD1q64wb_fixed:
20857
    case ARM::VLD2DUPd8wb_fixed:
20858
    case ARM::VLD2DUPd8x2wb_fixed:
20859
    case ARM::VLD2DUPd16wb_fixed:
20860
    case ARM::VLD2DUPd16x2wb_fixed:
20861
    case ARM::VLD2DUPd32wb_fixed:
20862
    case ARM::VLD2DUPd32x2wb_fixed:
20863
    case ARM::VLD2b8wb_fixed:
20864
    case ARM::VLD2b16wb_fixed:
20865
    case ARM::VLD2b32wb_fixed:
20866
    case ARM::VLD2d8wb_fixed:
20867
    case ARM::VLD2d16wb_fixed:
20868
    case ARM::VLD2d32wb_fixed:
20869
    case ARM::VLD2q8wb_fixed:
20870
    case ARM::VLD2q16wb_fixed:
20871
    case ARM::VLD2q32wb_fixed: {
20872
      switch (OpNum) {
20873
      case 0:
20874
        // op: Vd
20875
        return 12;
20876
      case 2:
20877
        // op: Rn
20878
        return 4;
20879
      }
20880
      break;
20881
    }
20882
    case ARM::VRSRAsv1i64:
20883
    case ARM::VRSRAsv2i32:
20884
    case ARM::VRSRAsv2i64:
20885
    case ARM::VRSRAsv4i16:
20886
    case ARM::VRSRAsv4i32:
20887
    case ARM::VRSRAsv8i8:
20888
    case ARM::VRSRAsv8i16:
20889
    case ARM::VRSRAsv16i8:
20890
    case ARM::VRSRAuv1i64:
20891
    case ARM::VRSRAuv2i32:
20892
    case ARM::VRSRAuv2i64:
20893
    case ARM::VRSRAuv4i16:
20894
    case ARM::VRSRAuv4i32:
20895
    case ARM::VRSRAuv8i8:
20896
    case ARM::VRSRAuv8i16:
20897
    case ARM::VRSRAuv16i8:
20898
    case ARM::VSLIv1i64:
20899
    case ARM::VSLIv2i32:
20900
    case ARM::VSLIv2i64:
20901
    case ARM::VSLIv4i16:
20902
    case ARM::VSLIv4i32:
20903
    case ARM::VSLIv8i8:
20904
    case ARM::VSLIv8i16:
20905
    case ARM::VSLIv16i8:
20906
    case ARM::VSRAsv1i64:
20907
    case ARM::VSRAsv2i32:
20908
    case ARM::VSRAsv2i64:
20909
    case ARM::VSRAsv4i16:
20910
    case ARM::VSRAsv4i32:
20911
    case ARM::VSRAsv8i8:
20912
    case ARM::VSRAsv8i16:
20913
    case ARM::VSRAsv16i8:
20914
    case ARM::VSRAuv1i64:
20915
    case ARM::VSRAuv2i32:
20916
    case ARM::VSRAuv2i64:
20917
    case ARM::VSRAuv4i16:
20918
    case ARM::VSRAuv4i32:
20919
    case ARM::VSRAuv8i8:
20920
    case ARM::VSRAuv8i16:
20921
    case ARM::VSRAuv16i8:
20922
    case ARM::VSRIv1i64:
20923
    case ARM::VSRIv2i32:
20924
    case ARM::VSRIv2i64:
20925
    case ARM::VSRIv4i16:
20926
    case ARM::VSRIv4i32:
20927
    case ARM::VSRIv8i8:
20928
    case ARM::VSRIv8i16:
20929
    case ARM::VSRIv16i8: {
20930
      switch (OpNum) {
20931
      case 0:
20932
        // op: Vd
20933
        return 12;
20934
      case 2:
20935
        // op: Vm
20936
        return 0;
20937
      case 3:
20938
        // op: SIMM
20939
        return 16;
20940
      }
20941
      break;
20942
    }
20943
    case ARM::AESD:
20944
    case ARM::AESE:
20945
    case ARM::SHA1SU1:
20946
    case ARM::SHA256SU0:
20947
    case ARM::VPADALsv2i32:
20948
    case ARM::VPADALsv4i16:
20949
    case ARM::VPADALsv4i32:
20950
    case ARM::VPADALsv8i8:
20951
    case ARM::VPADALsv8i16:
20952
    case ARM::VPADALsv16i8:
20953
    case ARM::VPADALuv2i32:
20954
    case ARM::VPADALuv4i16:
20955
    case ARM::VPADALuv4i32:
20956
    case ARM::VPADALuv8i8:
20957
    case ARM::VPADALuv8i16:
20958
    case ARM::VPADALuv16i8: {
20959
      switch (OpNum) {
20960
      case 0:
20961
        // op: Vd
20962
        return 12;
20963
      case 2:
20964
        // op: Vm
20965
        return 0;
20966
      }
20967
      break;
20968
    }
20969
    case ARM::VQRSHLsv1i64:
20970
    case ARM::VQRSHLsv2i32:
20971
    case ARM::VQRSHLsv2i64:
20972
    case ARM::VQRSHLsv4i16:
20973
    case ARM::VQRSHLsv4i32:
20974
    case ARM::VQRSHLsv8i8:
20975
    case ARM::VQRSHLsv8i16:
20976
    case ARM::VQRSHLsv16i8:
20977
    case ARM::VQRSHLuv1i64:
20978
    case ARM::VQRSHLuv2i32:
20979
    case ARM::VQRSHLuv2i64:
20980
    case ARM::VQRSHLuv4i16:
20981
    case ARM::VQRSHLuv4i32:
20982
    case ARM::VQRSHLuv8i8:
20983
    case ARM::VQRSHLuv8i16:
20984
    case ARM::VQRSHLuv16i8:
20985
    case ARM::VQSHLsv1i64:
20986
    case ARM::VQSHLsv2i32:
20987
    case ARM::VQSHLsv2i64:
20988
    case ARM::VQSHLsv4i16:
20989
    case ARM::VQSHLsv4i32:
20990
    case ARM::VQSHLsv8i8:
20991
    case ARM::VQSHLsv8i16:
20992
    case ARM::VQSHLsv16i8:
20993
    case ARM::VQSHLuv1i64:
20994
    case ARM::VQSHLuv2i32:
20995
    case ARM::VQSHLuv2i64:
20996
    case ARM::VQSHLuv4i16:
20997
    case ARM::VQSHLuv4i32:
20998
    case ARM::VQSHLuv8i8:
20999
    case ARM::VQSHLuv8i16:
21000
    case ARM::VQSHLuv16i8:
21001
    case ARM::VRSHLsv1i64:
21002
    case ARM::VRSHLsv2i32:
21003
    case ARM::VRSHLsv2i64:
21004
    case ARM::VRSHLsv4i16:
21005
    case ARM::VRSHLsv4i32:
21006
    case ARM::VRSHLsv8i8:
21007
    case ARM::VRSHLsv8i16:
21008
    case ARM::VRSHLsv16i8:
21009
    case ARM::VRSHLuv1i64:
21010
    case ARM::VRSHLuv2i32:
21011
    case ARM::VRSHLuv2i64:
21012
    case ARM::VRSHLuv4i16:
21013
    case ARM::VRSHLuv4i32:
21014
    case ARM::VRSHLuv8i8:
21015
    case ARM::VRSHLuv8i16:
21016
    case ARM::VRSHLuv16i8:
21017
    case ARM::VSHLsv1i64:
21018
    case ARM::VSHLsv2i32:
21019
    case ARM::VSHLsv2i64:
21020
    case ARM::VSHLsv4i16:
21021
    case ARM::VSHLsv4i32:
21022
    case ARM::VSHLsv8i8:
21023
    case ARM::VSHLsv8i16:
21024
    case ARM::VSHLsv16i8:
21025
    case ARM::VSHLuv1i64:
21026
    case ARM::VSHLuv2i32:
21027
    case ARM::VSHLuv2i64:
21028
    case ARM::VSHLuv4i16:
21029
    case ARM::VSHLuv4i32:
21030
    case ARM::VSHLuv8i8:
21031
    case ARM::VSHLuv8i16:
21032
    case ARM::VSHLuv16i8: {
21033
      switch (OpNum) {
21034
      case 0:
21035
        // op: Vd
21036
        return 12;
21037
      case 2:
21038
        // op: Vn
21039
        return 7;
21040
      case 1:
21041
        // op: Vm
21042
        return 0;
21043
      }
21044
      break;
21045
    }
21046
    case ARM::VMLALslsv4i16:
21047
    case ARM::VMLALsluv4i16:
21048
    case ARM::VMLAslhd:
21049
    case ARM::VMLAslhq:
21050
    case ARM::VMLAslv4i16:
21051
    case ARM::VMLAslv8i16:
21052
    case ARM::VMLSLslsv4i16:
21053
    case ARM::VMLSLsluv4i16:
21054
    case ARM::VMLSslhd:
21055
    case ARM::VMLSslhq:
21056
    case ARM::VMLSslv4i16:
21057
    case ARM::VMLSslv8i16:
21058
    case ARM::VQDMLALslv4i16:
21059
    case ARM::VQDMLSLslv4i16:
21060
    case ARM::VQRDMLAHslv4i16:
21061
    case ARM::VQRDMLAHslv8i16:
21062
    case ARM::VQRDMLSHslv4i16:
21063
    case ARM::VQRDMLSHslv8i16: {
21064
      switch (OpNum) {
21065
      case 0:
21066
        // op: Vd
21067
        return 12;
21068
      case 2:
21069
        // op: Vn
21070
        return 7;
21071
      case 3:
21072
        // op: Vm
21073
        return 0;
21074
      case 4:
21075
        // op: lane
21076
        return 3;
21077
      }
21078
      break;
21079
    }
21080
    case ARM::VMLALslsv2i32:
21081
    case ARM::VMLALsluv2i32:
21082
    case ARM::VMLAslfd:
21083
    case ARM::VMLAslfq:
21084
    case ARM::VMLAslv2i32:
21085
    case ARM::VMLAslv4i32:
21086
    case ARM::VMLSLslsv2i32:
21087
    case ARM::VMLSLsluv2i32:
21088
    case ARM::VMLSslfd:
21089
    case ARM::VMLSslfq:
21090
    case ARM::VMLSslv2i32:
21091
    case ARM::VMLSslv4i32:
21092
    case ARM::VQDMLALslv2i32:
21093
    case ARM::VQDMLSLslv2i32:
21094
    case ARM::VQRDMLAHslv2i32:
21095
    case ARM::VQRDMLAHslv4i32:
21096
    case ARM::VQRDMLSHslv2i32:
21097
    case ARM::VQRDMLSHslv4i32: {
21098
      switch (OpNum) {
21099
      case 0:
21100
        // op: Vd
21101
        return 12;
21102
      case 2:
21103
        // op: Vn
21104
        return 7;
21105
      case 3:
21106
        // op: Vm
21107
        return 0;
21108
      case 4:
21109
        // op: lane
21110
        return 5;
21111
      }
21112
      break;
21113
    }
21114
    case ARM::VCMLAv2f32:
21115
    case ARM::VCMLAv4f16:
21116
    case ARM::VCMLAv4f32:
21117
    case ARM::VCMLAv8f16: {
21118
      switch (OpNum) {
21119
      case 0:
21120
        // op: Vd
21121
        return 12;
21122
      case 2:
21123
        // op: Vn
21124
        return 7;
21125
      case 3:
21126
        // op: Vm
21127
        return 0;
21128
      case 4:
21129
        // op: rot
21130
        return 23;
21131
      }
21132
      break;
21133
    }
21134
    case ARM::VCMLAv4f16_indexed:
21135
    case ARM::VCMLAv8f16_indexed: {
21136
      switch (OpNum) {
21137
      case 0:
21138
        // op: Vd
21139
        return 12;
21140
      case 2:
21141
        // op: Vn
21142
        return 7;
21143
      case 3:
21144
        // op: Vm
21145
        return 0;
21146
      case 5:
21147
        // op: rot
21148
        return 20;
21149
      case 4:
21150
        // op: lane
21151
        return 5;
21152
      }
21153
      break;
21154
    }
21155
    case ARM::VCMLAv2f32_indexed:
21156
    case ARM::VCMLAv4f32_indexed: {
21157
      switch (OpNum) {
21158
      case 0:
21159
        // op: Vd
21160
        return 12;
21161
      case 2:
21162
        // op: Vn
21163
        return 7;
21164
      case 3:
21165
        // op: Vm
21166
        return 0;
21167
      case 5:
21168
        // op: rot
21169
        return 20;
21170
      }
21171
      break;
21172
    }
21173
    case ARM::SHA1C:
21174
    case ARM::SHA1M:
21175
    case ARM::SHA1P:
21176
    case ARM::SHA1SU0:
21177
    case ARM::SHA256H:
21178
    case ARM::SHA256H2:
21179
    case ARM::SHA256SU1:
21180
    case ARM::VABALsv2i64:
21181
    case ARM::VABALsv4i32:
21182
    case ARM::VABALsv8i16:
21183
    case ARM::VABALuv2i64:
21184
    case ARM::VABALuv4i32:
21185
    case ARM::VABALuv8i16:
21186
    case ARM::VABAsv2i32:
21187
    case ARM::VABAsv4i16:
21188
    case ARM::VABAsv4i32:
21189
    case ARM::VABAsv8i8:
21190
    case ARM::VABAsv8i16:
21191
    case ARM::VABAsv16i8:
21192
    case ARM::VABAuv2i32:
21193
    case ARM::VABAuv4i16:
21194
    case ARM::VABAuv4i32:
21195
    case ARM::VABAuv8i8:
21196
    case ARM::VABAuv8i16:
21197
    case ARM::VABAuv16i8:
21198
    case ARM::VBIFd:
21199
    case ARM::VBIFq:
21200
    case ARM::VBITd:
21201
    case ARM::VBITq:
21202
    case ARM::VBSLd:
21203
    case ARM::VBSLq:
21204
    case ARM::VFMAfd:
21205
    case ARM::VFMAfq:
21206
    case ARM::VFMAhd:
21207
    case ARM::VFMAhq:
21208
    case ARM::VFMSfd:
21209
    case ARM::VFMSfq:
21210
    case ARM::VFMShd:
21211
    case ARM::VFMShq:
21212
    case ARM::VMLALsv2i64:
21213
    case ARM::VMLALsv4i32:
21214
    case ARM::VMLALsv8i16:
21215
    case ARM::VMLALuv2i64:
21216
    case ARM::VMLALuv4i32:
21217
    case ARM::VMLALuv8i16:
21218
    case ARM::VMLAfd:
21219
    case ARM::VMLAfq:
21220
    case ARM::VMLAhd:
21221
    case ARM::VMLAhq:
21222
    case ARM::VMLAv2i32:
21223
    case ARM::VMLAv4i16:
21224
    case ARM::VMLAv4i32:
21225
    case ARM::VMLAv8i8:
21226
    case ARM::VMLAv8i16:
21227
    case ARM::VMLAv16i8:
21228
    case ARM::VMLSLsv2i64:
21229
    case ARM::VMLSLsv4i32:
21230
    case ARM::VMLSLsv8i16:
21231
    case ARM::VMLSLuv2i64:
21232
    case ARM::VMLSLuv4i32:
21233
    case ARM::VMLSLuv8i16:
21234
    case ARM::VMLSfd:
21235
    case ARM::VMLSfq:
21236
    case ARM::VMLShd:
21237
    case ARM::VMLShq:
21238
    case ARM::VMLSv2i32:
21239
    case ARM::VMLSv4i16:
21240
    case ARM::VMLSv4i32:
21241
    case ARM::VMLSv8i8:
21242
    case ARM::VMLSv8i16:
21243
    case ARM::VMLSv16i8:
21244
    case ARM::VQDMLALv2i64:
21245
    case ARM::VQDMLALv4i32:
21246
    case ARM::VQDMLSLv2i64:
21247
    case ARM::VQDMLSLv4i32:
21248
    case ARM::VQRDMLAHv2i32:
21249
    case ARM::VQRDMLAHv4i16:
21250
    case ARM::VQRDMLAHv4i32:
21251
    case ARM::VQRDMLAHv8i16:
21252
    case ARM::VQRDMLSHv2i32:
21253
    case ARM::VQRDMLSHv4i16:
21254
    case ARM::VQRDMLSHv4i32:
21255
    case ARM::VQRDMLSHv8i16:
21256
    case ARM::VTBX1:
21257
    case ARM::VTBX2:
21258
    case ARM::VTBX3:
21259
    case ARM::VTBX4: {
21260
      switch (OpNum) {
21261
      case 0:
21262
        // op: Vd
21263
        return 12;
21264
      case 2:
21265
        // op: Vn
21266
        return 7;
21267
      case 3:
21268
        // op: Vm
21269
        return 0;
21270
      }
21271
      break;
21272
    }
21273
    case ARM::VLD3LNd8: {
21274
      switch (OpNum) {
21275
      case 0:
21276
        // op: Vd
21277
        return 12;
21278
      case 3:
21279
        // op: Rn
21280
        return 16;
21281
      case 8:
21282
        // op: lane
21283
        return 5;
21284
      }
21285
      break;
21286
    }
21287
    case ARM::VLD3LNd16:
21288
    case ARM::VLD3LNq16: {
21289
      switch (OpNum) {
21290
      case 0:
21291
        // op: Vd
21292
        return 12;
21293
      case 3:
21294
        // op: Rn
21295
        return 16;
21296
      case 8:
21297
        // op: lane
21298
        return 6;
21299
      }
21300
      break;
21301
    }
21302
    case ARM::VLD3LNd32:
21303
    case ARM::VLD3LNq32: {
21304
      switch (OpNum) {
21305
      case 0:
21306
        // op: Vd
21307
        return 12;
21308
      case 3:
21309
        // op: Rn
21310
        return 16;
21311
      case 8:
21312
        // op: lane
21313
        return 7;
21314
      }
21315
      break;
21316
    }
21317
    case ARM::VLD3DUPd8:
21318
    case ARM::VLD3DUPd16:
21319
    case ARM::VLD3DUPd32:
21320
    case ARM::VLD3DUPq8:
21321
    case ARM::VLD3DUPq16:
21322
    case ARM::VLD3DUPq32: {
21323
      switch (OpNum) {
21324
      case 0:
21325
        // op: Vd
21326
        return 12;
21327
      case 3:
21328
        // op: Rn
21329
        return 16;
21330
      }
21331
      break;
21332
    }
21333
    case ARM::VLD2LNd8_UPD: {
21334
      switch (OpNum) {
21335
      case 0:
21336
        // op: Vd
21337
        return 12;
21338
      case 3:
21339
        // op: Rn
21340
        return 4;
21341
      case 5:
21342
        // op: Rm
21343
        return 0;
21344
      case 8:
21345
        // op: lane
21346
        return 5;
21347
      }
21348
      break;
21349
    }
21350
    case ARM::VLD2LNd16_UPD:
21351
    case ARM::VLD2LNq16_UPD: {
21352
      switch (OpNum) {
21353
      case 0:
21354
        // op: Vd
21355
        return 12;
21356
      case 3:
21357
        // op: Rn
21358
        return 4;
21359
      case 5:
21360
        // op: Rm
21361
        return 0;
21362
      case 8:
21363
        // op: lane
21364
        return 6;
21365
      }
21366
      break;
21367
    }
21368
    case ARM::VLD2LNd32_UPD:
21369
    case ARM::VLD2LNq32_UPD: {
21370
      switch (OpNum) {
21371
      case 0:
21372
        // op: Vd
21373
        return 12;
21374
      case 3:
21375
        // op: Rn
21376
        return 4;
21377
      case 5:
21378
        // op: Rm
21379
        return 0;
21380
      case 8:
21381
        // op: lane
21382
        return 7;
21383
      }
21384
      break;
21385
    }
21386
    case ARM::VLD3d8:
21387
    case ARM::VLD3d16:
21388
    case ARM::VLD3d32:
21389
    case ARM::VLD3q8:
21390
    case ARM::VLD3q16:
21391
    case ARM::VLD3q32: {
21392
      switch (OpNum) {
21393
      case 0:
21394
        // op: Vd
21395
        return 12;
21396
      case 3:
21397
        // op: Rn
21398
        return 4;
21399
      }
21400
      break;
21401
    }
21402
    case ARM::VLD3LNd8_UPD: {
21403
      switch (OpNum) {
21404
      case 0:
21405
        // op: Vd
21406
        return 12;
21407
      case 4:
21408
        // op: Rn
21409
        return 16;
21410
      case 6:
21411
        // op: Rm
21412
        return 0;
21413
      case 10:
21414
        // op: lane
21415
        return 5;
21416
      }
21417
      break;
21418
    }
21419
    case ARM::VLD3LNd16_UPD:
21420
    case ARM::VLD3LNq16_UPD: {
21421
      switch (OpNum) {
21422
      case 0:
21423
        // op: Vd
21424
        return 12;
21425
      case 4:
21426
        // op: Rn
21427
        return 16;
21428
      case 6:
21429
        // op: Rm
21430
        return 0;
21431
      case 10:
21432
        // op: lane
21433
        return 6;
21434
      }
21435
      break;
21436
    }
21437
    case ARM::VLD3LNd32_UPD:
21438
    case ARM::VLD3LNq32_UPD: {
21439
      switch (OpNum) {
21440
      case 0:
21441
        // op: Vd
21442
        return 12;
21443
      case 4:
21444
        // op: Rn
21445
        return 16;
21446
      case 6:
21447
        // op: Rm
21448
        return 0;
21449
      case 10:
21450
        // op: lane
21451
        return 7;
21452
      }
21453
      break;
21454
    }
21455
    case ARM::VLD3DUPd8_UPD:
21456
    case ARM::VLD3DUPd16_UPD:
21457
    case ARM::VLD3DUPd32_UPD:
21458
    case ARM::VLD3DUPq8_UPD:
21459
    case ARM::VLD3DUPq16_UPD:
21460
    case ARM::VLD3DUPq32_UPD: {
21461
      switch (OpNum) {
21462
      case 0:
21463
        // op: Vd
21464
        return 12;
21465
      case 4:
21466
        // op: Rn
21467
        return 16;
21468
      case 6:
21469
        // op: Rm
21470
        return 0;
21471
      }
21472
      break;
21473
    }
21474
    case ARM::VLD4LNd8: {
21475
      switch (OpNum) {
21476
      case 0:
21477
        // op: Vd
21478
        return 12;
21479
      case 4:
21480
        // op: Rn
21481
        return 4;
21482
      case 10:
21483
        // op: lane
21484
        return 5;
21485
      }
21486
      break;
21487
    }
21488
    case ARM::VLD4LNd16:
21489
    case ARM::VLD4LNq16: {
21490
      switch (OpNum) {
21491
      case 0:
21492
        // op: Vd
21493
        return 12;
21494
      case 4:
21495
        // op: Rn
21496
        return 4;
21497
      case 10:
21498
        // op: lane
21499
        return 6;
21500
      }
21501
      break;
21502
    }
21503
    case ARM::VLD4LNd32:
21504
    case ARM::VLD4LNq32: {
21505
      switch (OpNum) {
21506
      case 0:
21507
        // op: Vd
21508
        return 12;
21509
      case 4:
21510
        // op: Rn
21511
        return 4;
21512
      case 10:
21513
        // op: lane
21514
        return 7;
21515
      }
21516
      break;
21517
    }
21518
    case ARM::VLD3d8_UPD:
21519
    case ARM::VLD3d16_UPD:
21520
    case ARM::VLD3d32_UPD:
21521
    case ARM::VLD3q8_UPD:
21522
    case ARM::VLD3q16_UPD:
21523
    case ARM::VLD3q32_UPD: {
21524
      switch (OpNum) {
21525
      case 0:
21526
        // op: Vd
21527
        return 12;
21528
      case 4:
21529
        // op: Rn
21530
        return 4;
21531
      case 6:
21532
        // op: Rm
21533
        return 0;
21534
      }
21535
      break;
21536
    }
21537
    case ARM::VLD4DUPd8:
21538
    case ARM::VLD4DUPd16:
21539
    case ARM::VLD4DUPd32:
21540
    case ARM::VLD4DUPq8:
21541
    case ARM::VLD4DUPq16:
21542
    case ARM::VLD4DUPq32:
21543
    case ARM::VLD4d8:
21544
    case ARM::VLD4d16:
21545
    case ARM::VLD4d32:
21546
    case ARM::VLD4q8:
21547
    case ARM::VLD4q16:
21548
    case ARM::VLD4q32: {
21549
      switch (OpNum) {
21550
      case 0:
21551
        // op: Vd
21552
        return 12;
21553
      case 4:
21554
        // op: Rn
21555
        return 4;
21556
      }
21557
      break;
21558
    }
21559
    case ARM::VLD4LNd8_UPD: {
21560
      switch (OpNum) {
21561
      case 0:
21562
        // op: Vd
21563
        return 12;
21564
      case 5:
21565
        // op: Rn
21566
        return 4;
21567
      case 7:
21568
        // op: Rm
21569
        return 0;
21570
      case 12:
21571
        // op: lane
21572
        return 5;
21573
      }
21574
      break;
21575
    }
21576
    case ARM::VLD4LNd16_UPD:
21577
    case ARM::VLD4LNq16_UPD: {
21578
      switch (OpNum) {
21579
      case 0:
21580
        // op: Vd
21581
        return 12;
21582
      case 5:
21583
        // op: Rn
21584
        return 4;
21585
      case 7:
21586
        // op: Rm
21587
        return 0;
21588
      case 12:
21589
        // op: lane
21590
        return 6;
21591
      }
21592
      break;
21593
    }
21594
    case ARM::VLD4LNd32_UPD:
21595
    case ARM::VLD4LNq32_UPD: {
21596
      switch (OpNum) {
21597
      case 0:
21598
        // op: Vd
21599
        return 12;
21600
      case 5:
21601
        // op: Rn
21602
        return 4;
21603
      case 7:
21604
        // op: Rm
21605
        return 0;
21606
      case 12:
21607
        // op: lane
21608
        return 7;
21609
      }
21610
      break;
21611
    }
21612
    case ARM::VLD4DUPd8_UPD:
21613
    case ARM::VLD4DUPd16_UPD:
21614
    case ARM::VLD4DUPd32_UPD:
21615
    case ARM::VLD4DUPq8_UPD:
21616
    case ARM::VLD4DUPq16_UPD:
21617
    case ARM::VLD4DUPq32_UPD:
21618
    case ARM::VLD4d8_UPD:
21619
    case ARM::VLD4d16_UPD:
21620
    case ARM::VLD4d32_UPD:
21621
    case ARM::VLD4q8_UPD:
21622
    case ARM::VLD4q16_UPD:
21623
    case ARM::VLD4q32_UPD: {
21624
      switch (OpNum) {
21625
      case 0:
21626
        // op: Vd
21627
        return 12;
21628
      case 5:
21629
        // op: Rn
21630
        return 4;
21631
      case 7:
21632
        // op: Rm
21633
        return 0;
21634
      }
21635
      break;
21636
    }
21637
    case ARM::PLDWi12:
21638
    case ARM::PLDi12:
21639
    case ARM::PLIi12:
21640
    case ARM::t2PLDWi8:
21641
    case ARM::t2PLDWi12:
21642
    case ARM::t2PLDWs:
21643
    case ARM::t2PLDi8:
21644
    case ARM::t2PLDi12:
21645
    case ARM::t2PLDpci:
21646
    case ARM::t2PLDs:
21647
    case ARM::t2PLIi8:
21648
    case ARM::t2PLIi12:
21649
    case ARM::t2PLIpci:
21650
    case ARM::t2PLIs: {
21651
      switch (OpNum) {
21652
      case 0:
21653
        // op: addr
21654
        return 0;
21655
      }
21656
      break;
21657
    }
21658
    case ARM::t2BFLr:
21659
    case ARM::t2BFr: {
21660
      switch (OpNum) {
21661
      case 0:
21662
        // op: b_label
21663
        return 23;
21664
      case 1:
21665
        // op: Rn
21666
        return 16;
21667
      }
21668
      break;
21669
    }
21670
    case ARM::t2BFLi:
21671
    case ARM::t2BFi: {
21672
      switch (OpNum) {
21673
      case 0:
21674
        // op: b_label
21675
        return 23;
21676
      case 1:
21677
        // op: label
21678
        return 1;
21679
      }
21680
      break;
21681
    }
21682
    case ARM::t2MSRbanked: {
21683
      switch (OpNum) {
21684
      case 0:
21685
        // op: banked
21686
        return 4;
21687
      case 1:
21688
        // op: Rn
21689
        return 16;
21690
      }
21691
      break;
21692
    }
21693
    case ARM::t2IT: {
21694
      switch (OpNum) {
21695
      case 0:
21696
        // op: cc
21697
        return 4;
21698
      case 1:
21699
        // op: mask
21700
        return 0;
21701
      }
21702
      break;
21703
    }
21704
    case ARM::BX:
21705
    case ARM::tPICADD: {
21706
      switch (OpNum) {
21707
      case 0:
21708
        // op: dst
21709
        return 0;
21710
      }
21711
      break;
21712
    }
21713
    case ARM::tADDrSPi: {
21714
      switch (OpNum) {
21715
      case 0:
21716
        // op: dst
21717
        return 8;
21718
      case 2:
21719
        // op: imm
21720
        return 0;
21721
      }
21722
      break;
21723
    }
21724
    case ARM::tSETEND: {
21725
      switch (OpNum) {
21726
      case 0:
21727
        // op: end
21728
        return 3;
21729
      }
21730
      break;
21731
    }
21732
    case ARM::SETEND: {
21733
      switch (OpNum) {
21734
      case 0:
21735
        // op: end
21736
        return 9;
21737
      }
21738
      break;
21739
    }
21740
    case ARM::BL:
21741
    case ARM::BLX: {
21742
      switch (OpNum) {
21743
      case 0:
21744
        // op: func
21745
        return 0;
21746
      }
21747
      break;
21748
    }
21749
    case ARM::t2BXJ: {
21750
      switch (OpNum) {
21751
      case 0:
21752
        // op: func
21753
        return 16;
21754
      }
21755
      break;
21756
    }
21757
    case ARM::HVC:
21758
    case ARM::t2HINT:
21759
    case ARM::t2SUBS_PC_LR:
21760
    case ARM::tSVC: {
21761
      switch (OpNum) {
21762
      case 0:
21763
        // op: imm
21764
        return 0;
21765
      }
21766
      break;
21767
    }
21768
    case ARM::t2SETPAN: {
21769
      switch (OpNum) {
21770
      case 0:
21771
        // op: imm
21772
        return 3;
21773
      }
21774
      break;
21775
    }
21776
    case ARM::tHINT: {
21777
      switch (OpNum) {
21778
      case 0:
21779
        // op: imm
21780
        return 4;
21781
      }
21782
      break;
21783
    }
21784
    case ARM::SETPAN: {
21785
      switch (OpNum) {
21786
      case 0:
21787
        // op: imm
21788
        return 9;
21789
      }
21790
      break;
21791
    }
21792
    case ARM::UDF:
21793
    case ARM::t2HVC:
21794
    case ARM::t2UDF: {
21795
      switch (OpNum) {
21796
      case 0:
21797
        // op: imm16
21798
        return 0;
21799
      }
21800
      break;
21801
    }
21802
    case ARM::tUDF: {
21803
      switch (OpNum) {
21804
      case 0:
21805
        // op: imm8
21806
        return 0;
21807
      }
21808
      break;
21809
    }
21810
    case ARM::CPS3p: {
21811
      switch (OpNum) {
21812
      case 0:
21813
        // op: imod
21814
        return 18;
21815
      case 1:
21816
        // op: iflags
21817
        return 6;
21818
      case 2:
21819
        // op: mode
21820
        return 0;
21821
      }
21822
      break;
21823
    }
21824
    case ARM::CPS2p: {
21825
      switch (OpNum) {
21826
      case 0:
21827
        // op: imod
21828
        return 18;
21829
      case 1:
21830
        // op: iflags
21831
        return 6;
21832
      }
21833
      break;
21834
    }
21835
    case ARM::tCPS: {
21836
      switch (OpNum) {
21837
      case 0:
21838
        // op: imod
21839
        return 4;
21840
      case 1:
21841
        // op: iflags
21842
        return 0;
21843
      }
21844
      break;
21845
    }
21846
    case ARM::t2CPS3p: {
21847
      switch (OpNum) {
21848
      case 0:
21849
        // op: imod
21850
        return 9;
21851
      case 1:
21852
        // op: iflags
21853
        return 5;
21854
      case 2:
21855
        // op: mode
21856
        return 0;
21857
      }
21858
      break;
21859
    }
21860
    case ARM::t2CPS2p: {
21861
      switch (OpNum) {
21862
      case 0:
21863
        // op: imod
21864
        return 9;
21865
      case 1:
21866
        // op: iflags
21867
        return 5;
21868
      }
21869
      break;
21870
    }
21871
    case ARM::t2LE: {
21872
      switch (OpNum) {
21873
      case 0:
21874
        // op: label
21875
        return 1;
21876
      }
21877
      break;
21878
    }
21879
    case ARM::t2MSR_AR: {
21880
      switch (OpNum) {
21881
      case 0:
21882
        // op: mask
21883
        return 8;
21884
      case 1:
21885
        // op: Rn
21886
        return 16;
21887
      }
21888
      break;
21889
    }
21890
    case ARM::CPS1p:
21891
    case ARM::SRSDA:
21892
    case ARM::SRSDA_UPD:
21893
    case ARM::SRSDB:
21894
    case ARM::SRSDB_UPD:
21895
    case ARM::SRSIA:
21896
    case ARM::SRSIA_UPD:
21897
    case ARM::SRSIB:
21898
    case ARM::SRSIB_UPD:
21899
    case ARM::t2CPS1p:
21900
    case ARM::t2SRSDB:
21901
    case ARM::t2SRSDB_UPD:
21902
    case ARM::t2SRSIA:
21903
    case ARM::t2SRSIA_UPD: {
21904
      switch (OpNum) {
21905
      case 0:
21906
        // op: mode
21907
        return 0;
21908
      }
21909
      break;
21910
    }
21911
    case ARM::DMB:
21912
    case ARM::DSB:
21913
    case ARM::ISB:
21914
    case ARM::t2DBG:
21915
    case ARM::t2DMB:
21916
    case ARM::t2DSB:
21917
    case ARM::t2ISB: {
21918
      switch (OpNum) {
21919
      case 0:
21920
        // op: opt
21921
        return 0;
21922
      }
21923
      break;
21924
    }
21925
    case ARM::t2SMC: {
21926
      switch (OpNum) {
21927
      case 0:
21928
        // op: opt
21929
        return 16;
21930
      }
21931
      break;
21932
    }
21933
    case ARM::BX_RET:
21934
    case ARM::ERET:
21935
    case ARM::FMSTAT:
21936
    case ARM::MOVPCLR: {
21937
      switch (OpNum) {
21938
      case 0:
21939
        // op: p
21940
        return 28;
21941
      }
21942
      break;
21943
    }
21944
    case ARM::PLDWrs:
21945
    case ARM::PLDrs:
21946
    case ARM::PLIrs: {
21947
      switch (OpNum) {
21948
      case 0:
21949
        // op: shift
21950
        return 0;
21951
      }
21952
      break;
21953
    }
21954
    case ARM::BLXi:
21955
    case ARM::t2B:
21956
    case ARM::tB: {
21957
      switch (OpNum) {
21958
      case 0:
21959
        // op: target
21960
        return 0;
21961
      }
21962
      break;
21963
    }
21964
    case ARM::BKPT:
21965
    case ARM::HLT:
21966
    case ARM::tBKPT:
21967
    case ARM::tHLT: {
21968
      switch (OpNum) {
21969
      case 0:
21970
        // op: val
21971
        return 0;
21972
      }
21973
      break;
21974
    }
21975
    case ARM::MVE_VLDRBS16_pre:
21976
    case ARM::MVE_VLDRBS32_pre:
21977
    case ARM::MVE_VLDRBU8_pre:
21978
    case ARM::MVE_VLDRBU16_pre:
21979
    case ARM::MVE_VLDRBU32_pre:
21980
    case ARM::MVE_VLDRDU64_qi_pre:
21981
    case ARM::MVE_VLDRHS32_pre:
21982
    case ARM::MVE_VLDRHU16_pre:
21983
    case ARM::MVE_VLDRHU32_pre:
21984
    case ARM::MVE_VLDRWU32_pre:
21985
    case ARM::MVE_VLDRWU32_qi_pre:
21986
    case ARM::MVE_VSTRB16_pre:
21987
    case ARM::MVE_VSTRB32_pre:
21988
    case ARM::MVE_VSTRBU8_pre:
21989
    case ARM::MVE_VSTRD64_qi_pre:
21990
    case ARM::MVE_VSTRH32_pre:
21991
    case ARM::MVE_VSTRHU16_pre:
21992
    case ARM::MVE_VSTRW32_qi_pre:
21993
    case ARM::MVE_VSTRWU32_pre: {
21994
      switch (OpNum) {
21995
      case 1:
21996
        // op: Qd
21997
        return 13;
21998
      case 2:
21999
        // op: addr
22000
        return 0;
22001
      }
22002
      break;
22003
    }
22004
    case ARM::MVE_VLDRBS16_post:
22005
    case ARM::MVE_VLDRBS32_post:
22006
    case ARM::MVE_VLDRBU8_post:
22007
    case ARM::MVE_VLDRBU16_post:
22008
    case ARM::MVE_VLDRBU32_post:
22009
    case ARM::MVE_VLDRHS32_post:
22010
    case ARM::MVE_VLDRHU16_post:
22011
    case ARM::MVE_VLDRHU32_post:
22012
    case ARM::MVE_VLDRWU32_post:
22013
    case ARM::MVE_VSTRB16_post:
22014
    case ARM::MVE_VSTRB32_post:
22015
    case ARM::MVE_VSTRBU8_post:
22016
    case ARM::MVE_VSTRH32_post:
22017
    case ARM::MVE_VSTRHU16_post:
22018
    case ARM::MVE_VSTRWU32_post: {
22019
      switch (OpNum) {
22020
      case 1:
22021
        // op: Qd
22022
        return 13;
22023
      case 3:
22024
        // op: addr
22025
        return 0;
22026
      case 2:
22027
        // op: Rn
22028
        return 16;
22029
      }
22030
      break;
22031
    }
22032
    case ARM::MVE_VMOV_from_lane_32: {
22033
      switch (OpNum) {
22034
      case 1:
22035
        // op: Qd
22036
        return 7;
22037
      case 0:
22038
        // op: Rt
22039
        return 12;
22040
      case 2:
22041
        // op: Idx
22042
        return 16;
22043
      }
22044
      break;
22045
    }
22046
    case ARM::MVE_VMOV_from_lane_s8:
22047
    case ARM::MVE_VMOV_from_lane_u8: {
22048
      switch (OpNum) {
22049
      case 1:
22050
        // op: Qd
22051
        return 7;
22052
      case 0:
22053
        // op: Rt
22054
        return 12;
22055
      case 2:
22056
        // op: Idx
22057
        return 5;
22058
      }
22059
      break;
22060
    }
22061
    case ARM::MVE_VMOV_from_lane_s16:
22062
    case ARM::MVE_VMOV_from_lane_u16: {
22063
      switch (OpNum) {
22064
      case 1:
22065
        // op: Qd
22066
        return 7;
22067
      case 0:
22068
        // op: Rt
22069
        return 12;
22070
      case 2:
22071
        // op: Idx
22072
        return 6;
22073
      }
22074
      break;
22075
    }
22076
    case ARM::MVE_VCVTf16s16_fix:
22077
    case ARM::MVE_VCVTf16u16_fix:
22078
    case ARM::MVE_VCVTf32s32_fix:
22079
    case ARM::MVE_VCVTf32u32_fix:
22080
    case ARM::MVE_VCVTs16f16_fix:
22081
    case ARM::MVE_VCVTs32f32_fix:
22082
    case ARM::MVE_VCVTu16f16_fix:
22083
    case ARM::MVE_VCVTu32f32_fix: {
22084
      switch (OpNum) {
22085
      case 1:
22086
        // op: Qm
22087
        return 1;
22088
      case 0:
22089
        // op: Qd
22090
        return 13;
22091
      case 2:
22092
        // op: imm6
22093
        return 16;
22094
      }
22095
      break;
22096
    }
22097
    case ARM::MVE_VABSf16:
22098
    case ARM::MVE_VABSf32:
22099
    case ARM::MVE_VCVTf16s16n:
22100
    case ARM::MVE_VCVTf16u16n:
22101
    case ARM::MVE_VCVTf32s32n:
22102
    case ARM::MVE_VCVTf32u32n:
22103
    case ARM::MVE_VCVTs16f16a:
22104
    case ARM::MVE_VCVTs16f16m:
22105
    case ARM::MVE_VCVTs16f16n:
22106
    case ARM::MVE_VCVTs16f16p:
22107
    case ARM::MVE_VCVTs16f16z:
22108
    case ARM::MVE_VCVTs32f32a:
22109
    case ARM::MVE_VCVTs32f32m:
22110
    case ARM::MVE_VCVTs32f32n:
22111
    case ARM::MVE_VCVTs32f32p:
22112
    case ARM::MVE_VCVTs32f32z:
22113
    case ARM::MVE_VCVTu16f16a:
22114
    case ARM::MVE_VCVTu16f16m:
22115
    case ARM::MVE_VCVTu16f16n:
22116
    case ARM::MVE_VCVTu16f16p:
22117
    case ARM::MVE_VCVTu16f16z:
22118
    case ARM::MVE_VCVTu32f32a:
22119
    case ARM::MVE_VCVTu32f32m:
22120
    case ARM::MVE_VCVTu32f32n:
22121
    case ARM::MVE_VCVTu32f32p:
22122
    case ARM::MVE_VCVTu32f32z:
22123
    case ARM::MVE_VNEGf16:
22124
    case ARM::MVE_VNEGf32:
22125
    case ARM::MVE_VRINTf16A:
22126
    case ARM::MVE_VRINTf16M:
22127
    case ARM::MVE_VRINTf16N:
22128
    case ARM::MVE_VRINTf16P:
22129
    case ARM::MVE_VRINTf16X:
22130
    case ARM::MVE_VRINTf16Z:
22131
    case ARM::MVE_VRINTf32A:
22132
    case ARM::MVE_VRINTf32M:
22133
    case ARM::MVE_VRINTf32N:
22134
    case ARM::MVE_VRINTf32P:
22135
    case ARM::MVE_VRINTf32X:
22136
    case ARM::MVE_VRINTf32Z: {
22137
      switch (OpNum) {
22138
      case 1:
22139
        // op: Qm
22140
        return 1;
22141
      case 0:
22142
        // op: Qd
22143
        return 13;
22144
      }
22145
      break;
22146
    }
22147
    case ARM::MVE_VADDVs8no_acc:
22148
    case ARM::MVE_VADDVs16no_acc:
22149
    case ARM::MVE_VADDVs32no_acc:
22150
    case ARM::MVE_VADDVu8no_acc:
22151
    case ARM::MVE_VADDVu16no_acc:
22152
    case ARM::MVE_VADDVu32no_acc: {
22153
      switch (OpNum) {
22154
      case 1:
22155
        // op: Qm
22156
        return 1;
22157
      case 0:
22158
        // op: Rda
22159
        return 13;
22160
      }
22161
      break;
22162
    }
22163
    case ARM::MVE_VPSEL: {
22164
      switch (OpNum) {
22165
      case 1:
22166
        // op: Qn
22167
        return 7;
22168
      case 0:
22169
        // op: Qd
22170
        return 13;
22171
      case 2:
22172
        // op: Qm
22173
        return 1;
22174
      }
22175
      break;
22176
    }
22177
    case ARM::t2SMLALD:
22178
    case ARM::t2SMLALDX:
22179
    case ARM::t2SMLSLD:
22180
    case ARM::t2SMLSLDX: {
22181
      switch (OpNum) {
22182
      case 1:
22183
        // op: Rd
22184
        return 8;
22185
      case 2:
22186
        // op: Rn
22187
        return 16;
22188
      case 3:
22189
        // op: Rm
22190
        return 0;
22191
      case 0:
22192
        // op: Ra
22193
        return 12;
22194
      }
22195
      break;
22196
    }
22197
    case ARM::tREV:
22198
    case ARM::tREV16:
22199
    case ARM::tREVSH:
22200
    case ARM::tSXTB:
22201
    case ARM::tSXTH:
22202
    case ARM::tUXTB:
22203
    case ARM::tUXTH: {
22204
      switch (OpNum) {
22205
      case 1:
22206
        // op: Rm
22207
        return 3;
22208
      case 0:
22209
        // op: Rd
22210
        return 0;
22211
      }
22212
      break;
22213
    }
22214
    case ARM::tCMNz:
22215
    case ARM::tCMPhir:
22216
    case ARM::tCMPr:
22217
    case ARM::tTST: {
22218
      switch (OpNum) {
22219
      case 1:
22220
        // op: Rm
22221
        return 3;
22222
      case 0:
22223
        // op: Rn
22224
        return 0;
22225
      }
22226
      break;
22227
    }
22228
    case ARM::t2TT:
22229
    case ARM::t2TTA:
22230
    case ARM::t2TTAT:
22231
    case ARM::t2TTT: {
22232
      switch (OpNum) {
22233
      case 1:
22234
        // op: Rn
22235
        return 16;
22236
      case 0:
22237
        // op: Rt
22238
        return 8;
22239
      }
22240
      break;
22241
    }
22242
    case ARM::MVE_WLSTP_8:
22243
    case ARM::MVE_WLSTP_16:
22244
    case ARM::MVE_WLSTP_32:
22245
    case ARM::MVE_WLSTP_64:
22246
    case ARM::t2WLS: {
22247
      switch (OpNum) {
22248
      case 1:
22249
        // op: Rn
22250
        return 16;
22251
      case 2:
22252
        // op: label
22253
        return 1;
22254
      }
22255
      break;
22256
    }
22257
    case ARM::t2LDMDB_UPD:
22258
    case ARM::t2LDMIA_UPD:
22259
    case ARM::t2STMDB_UPD:
22260
    case ARM::t2STMIA_UPD: {
22261
      switch (OpNum) {
22262
      case 1:
22263
        // op: Rn
22264
        return 16;
22265
      case 4:
22266
        // op: regs
22267
        return 0;
22268
      }
22269
      break;
22270
    }
22271
    case ARM::MVE_DLSTP_8:
22272
    case ARM::MVE_DLSTP_16:
22273
    case ARM::MVE_DLSTP_32:
22274
    case ARM::MVE_DLSTP_64:
22275
    case ARM::MVE_VCTP8:
22276
    case ARM::MVE_VCTP16:
22277
    case ARM::MVE_VCTP32:
22278
    case ARM::MVE_VCTP64:
22279
    case ARM::t2DLS: {
22280
      switch (OpNum) {
22281
      case 1:
22282
        // op: Rn
22283
        return 16;
22284
      }
22285
      break;
22286
    }
22287
    case ARM::tSTMIA_UPD: {
22288
      switch (OpNum) {
22289
      case 1:
22290
        // op: Rn
22291
        return 8;
22292
      case 4:
22293
        // op: regs
22294
        return 0;
22295
      }
22296
      break;
22297
    }
22298
    case ARM::t2STRB_POST:
22299
    case ARM::t2STRH_POST:
22300
    case ARM::t2STR_POST: {
22301
      switch (OpNum) {
22302
      case 1:
22303
        // op: Rt
22304
        return 12;
22305
      case 2:
22306
        // op: Rn
22307
        return 16;
22308
      case 3:
22309
        // op: offset
22310
        return 0;
22311
      }
22312
      break;
22313
    }
22314
    case ARM::t2STRD_PRE: {
22315
      switch (OpNum) {
22316
      case 1:
22317
        // op: Rt
22318
        return 12;
22319
      case 2:
22320
        // op: Rt2
22321
        return 8;
22322
      case 3:
22323
        // op: addr
22324
        return 0;
22325
      }
22326
      break;
22327
    }
22328
    case ARM::t2STRD_POST: {
22329
      switch (OpNum) {
22330
      case 1:
22331
        // op: Rt
22332
        return 12;
22333
      case 2:
22334
        // op: Rt2
22335
        return 8;
22336
      case 3:
22337
        // op: addr
22338
        return 16;
22339
      case 4:
22340
        // op: imm
22341
        return 0;
22342
      }
22343
      break;
22344
    }
22345
    case ARM::t2STRB_PRE:
22346
    case ARM::t2STRH_PRE:
22347
    case ARM::t2STR_PRE: {
22348
      switch (OpNum) {
22349
      case 1:
22350
        // op: Rt
22351
        return 12;
22352
      case 2:
22353
        // op: addr
22354
        return 0;
22355
      }
22356
      break;
22357
    }
22358
    case ARM::VGETLNi32: {
22359
      switch (OpNum) {
22360
      case 1:
22361
        // op: V
22362
        return 7;
22363
      case 0:
22364
        // op: R
22365
        return 12;
22366
      case 3:
22367
        // op: p
22368
        return 28;
22369
      case 2:
22370
        // op: lane
22371
        return 21;
22372
      }
22373
      break;
22374
    }
22375
    case ARM::VGETLNs8:
22376
    case ARM::VGETLNu8: {
22377
      switch (OpNum) {
22378
      case 1:
22379
        // op: V
22380
        return 7;
22381
      case 0:
22382
        // op: R
22383
        return 12;
22384
      case 3:
22385
        // op: p
22386
        return 28;
22387
      case 2:
22388
        // op: lane
22389
        return 5;
22390
      }
22391
      break;
22392
    }
22393
    case ARM::VGETLNs16:
22394
    case ARM::VGETLNu16: {
22395
      switch (OpNum) {
22396
      case 1:
22397
        // op: V
22398
        return 7;
22399
      case 0:
22400
        // op: R
22401
        return 12;
22402
      case 3:
22403
        // op: p
22404
        return 28;
22405
      case 2:
22406
        // op: lane
22407
        return 6;
22408
      }
22409
      break;
22410
    }
22411
    case ARM::MVE_VST20_8_wb:
22412
    case ARM::MVE_VST20_16_wb:
22413
    case ARM::MVE_VST20_32_wb:
22414
    case ARM::MVE_VST21_8_wb:
22415
    case ARM::MVE_VST21_16_wb:
22416
    case ARM::MVE_VST21_32_wb:
22417
    case ARM::MVE_VST40_8_wb:
22418
    case ARM::MVE_VST40_16_wb:
22419
    case ARM::MVE_VST40_32_wb:
22420
    case ARM::MVE_VST41_8_wb:
22421
    case ARM::MVE_VST41_16_wb:
22422
    case ARM::MVE_VST41_32_wb:
22423
    case ARM::MVE_VST42_8_wb:
22424
    case ARM::MVE_VST42_16_wb:
22425
    case ARM::MVE_VST42_32_wb:
22426
    case ARM::MVE_VST43_8_wb:
22427
    case ARM::MVE_VST43_16_wb:
22428
    case ARM::MVE_VST43_32_wb: {
22429
      switch (OpNum) {
22430
      case 1:
22431
        // op: VQd
22432
        return 13;
22433
      case 2:
22434
        // op: Rn
22435
        return 16;
22436
      }
22437
      break;
22438
    }
22439
    case ARM::VBF16MALBQI:
22440
    case ARM::VBF16MALTQI: {
22441
      switch (OpNum) {
22442
      case 1:
22443
        // op: Vd
22444
        return 12;
22445
      case 2:
22446
        // op: Vn
22447
        return 7;
22448
      case 3:
22449
        // op: Vm
22450
        return 0;
22451
      case 4:
22452
        // op: idx
22453
        return 3;
22454
      }
22455
      break;
22456
    }
22457
    case ARM::BF16VDOTI_VDOTD:
22458
    case ARM::BF16VDOTI_VDOTQ:
22459
    case ARM::VSDOTDI:
22460
    case ARM::VSDOTQI:
22461
    case ARM::VSUDOTDI:
22462
    case ARM::VSUDOTQI:
22463
    case ARM::VUDOTDI:
22464
    case ARM::VUDOTQI:
22465
    case ARM::VUSDOTDI:
22466
    case ARM::VUSDOTQI: {
22467
      switch (OpNum) {
22468
      case 1:
22469
        // op: Vd
22470
        return 12;
22471
      case 2:
22472
        // op: Vn
22473
        return 7;
22474
      case 3:
22475
        // op: Vm
22476
        return 0;
22477
      case 4:
22478
        // op: lane
22479
        return 5;
22480
      }
22481
      break;
22482
    }
22483
    case ARM::BF16VDOTS_VDOTD:
22484
    case ARM::BF16VDOTS_VDOTQ:
22485
    case ARM::VBF16MALBQ:
22486
    case ARM::VBF16MALTQ:
22487
    case ARM::VMMLA:
22488
    case ARM::VSDOTD:
22489
    case ARM::VSDOTQ:
22490
    case ARM::VSMMLA:
22491
    case ARM::VUDOTD:
22492
    case ARM::VUDOTQ:
22493
    case ARM::VUMMLA:
22494
    case ARM::VUSDOTD:
22495
    case ARM::VUSDOTQ:
22496
    case ARM::VUSMMLA: {
22497
      switch (OpNum) {
22498
      case 1:
22499
        // op: Vd
22500
        return 12;
22501
      case 2:
22502
        // op: Vn
22503
        return 7;
22504
      case 3:
22505
        // op: Vm
22506
        return 0;
22507
      }
22508
      break;
22509
    }
22510
    case ARM::t2LDAEXB:
22511
    case ARM::t2LDAEXH:
22512
    case ARM::t2LDREXB:
22513
    case ARM::t2LDREXH: {
22514
      switch (OpNum) {
22515
      case 1:
22516
        // op: addr
22517
        return 16;
22518
      case 0:
22519
        // op: Rt
22520
        return 12;
22521
      }
22522
      break;
22523
    }
22524
    case ARM::t2MRSbanked: {
22525
      switch (OpNum) {
22526
      case 1:
22527
        // op: banked
22528
        return 4;
22529
      case 0:
22530
        // op: Rd
22531
        return 8;
22532
      }
22533
      break;
22534
    }
22535
    case ARM::CDE_VCX1_vec: {
22536
      switch (OpNum) {
22537
      case 1:
22538
        // op: coproc
22539
        return 8;
22540
      case 2:
22541
        // op: imm
22542
        return 0;
22543
      case 0:
22544
        // op: Qd
22545
        return 13;
22546
      }
22547
      break;
22548
    }
22549
    case ARM::CDE_CX1:
22550
    case ARM::CDE_CX1D: {
22551
      switch (OpNum) {
22552
      case 1:
22553
        // op: coproc
22554
        return 8;
22555
      case 2:
22556
        // op: imm
22557
        return 0;
22558
      case 0:
22559
        // op: Rd
22560
        return 12;
22561
      }
22562
      break;
22563
    }
22564
    case ARM::CDE_VCX1_fpdp:
22565
    case ARM::CDE_VCX1_fpsp: {
22566
      switch (OpNum) {
22567
      case 1:
22568
        // op: coproc
22569
        return 8;
22570
      case 2:
22571
        // op: imm
22572
        return 0;
22573
      case 0:
22574
        // op: Vd
22575
        return 12;
22576
      }
22577
      break;
22578
    }
22579
    case ARM::CDE_VCX1A_vec: {
22580
      switch (OpNum) {
22581
      case 1:
22582
        // op: coproc
22583
        return 8;
22584
      case 3:
22585
        // op: imm
22586
        return 0;
22587
      case 0:
22588
        // op: Qd
22589
        return 13;
22590
      }
22591
      break;
22592
    }
22593
    case ARM::CDE_CX2:
22594
    case ARM::CDE_CX2D: {
22595
      switch (OpNum) {
22596
      case 1:
22597
        // op: coproc
22598
        return 8;
22599
      case 3:
22600
        // op: imm
22601
        return 0;
22602
      case 0:
22603
        // op: Rd
22604
        return 12;
22605
      case 2:
22606
        // op: Rn
22607
        return 16;
22608
      }
22609
      break;
22610
    }
22611
    case ARM::CDE_CX1A:
22612
    case ARM::CDE_CX1DA: {
22613
      switch (OpNum) {
22614
      case 1:
22615
        // op: coproc
22616
        return 8;
22617
      case 3:
22618
        // op: imm
22619
        return 0;
22620
      case 0:
22621
        // op: Rd
22622
        return 12;
22623
      }
22624
      break;
22625
    }
22626
    case ARM::CDE_VCX1A_fpdp:
22627
    case ARM::CDE_VCX1A_fpsp: {
22628
      switch (OpNum) {
22629
      case 1:
22630
        // op: coproc
22631
        return 8;
22632
      case 3:
22633
        // op: imm
22634
        return 0;
22635
      case 0:
22636
        // op: Vd
22637
        return 12;
22638
      }
22639
      break;
22640
    }
22641
    case ARM::CDE_VCX2_vec: {
22642
      switch (OpNum) {
22643
      case 1:
22644
        // op: coproc
22645
        return 8;
22646
      case 3:
22647
        // op: imm
22648
        return 4;
22649
      case 0:
22650
        // op: Qd
22651
        return 13;
22652
      case 2:
22653
        // op: Qm
22654
        return 1;
22655
      }
22656
      break;
22657
    }
22658
    case ARM::CDE_VCX2_fpdp:
22659
    case ARM::CDE_VCX2_fpsp: {
22660
      switch (OpNum) {
22661
      case 1:
22662
        // op: coproc
22663
        return 8;
22664
      case 3:
22665
        // op: imm
22666
        return 4;
22667
      case 0:
22668
        // op: Vd
22669
        return 12;
22670
      case 2:
22671
        // op: Vm
22672
        return 0;
22673
      }
22674
      break;
22675
    }
22676
    case ARM::CDE_CX2A:
22677
    case ARM::CDE_CX2DA: {
22678
      switch (OpNum) {
22679
      case 1:
22680
        // op: coproc
22681
        return 8;
22682
      case 4:
22683
        // op: imm
22684
        return 0;
22685
      case 0:
22686
        // op: Rd
22687
        return 12;
22688
      case 3:
22689
        // op: Rn
22690
        return 16;
22691
      }
22692
      break;
22693
    }
22694
    case ARM::CDE_VCX3_vec: {
22695
      switch (OpNum) {
22696
      case 1:
22697
        // op: coproc
22698
        return 8;
22699
      case 4:
22700
        // op: imm
22701
        return 4;
22702
      case 0:
22703
        // op: Qd
22704
        return 13;
22705
      case 3:
22706
        // op: Qm
22707
        return 1;
22708
      case 2:
22709
        // op: Qn
22710
        return 17;
22711
      }
22712
      break;
22713
    }
22714
    case ARM::CDE_VCX2A_vec: {
22715
      switch (OpNum) {
22716
      case 1:
22717
        // op: coproc
22718
        return 8;
22719
      case 4:
22720
        // op: imm
22721
        return 4;
22722
      case 0:
22723
        // op: Qd
22724
        return 13;
22725
      case 3:
22726
        // op: Qm
22727
        return 1;
22728
      }
22729
      break;
22730
    }
22731
    case ARM::CDE_CX3:
22732
    case ARM::CDE_CX3D: {
22733
      switch (OpNum) {
22734
      case 1:
22735
        // op: coproc
22736
        return 8;
22737
      case 4:
22738
        // op: imm
22739
        return 4;
22740
      case 0:
22741
        // op: Rd
22742
        return 0;
22743
      case 2:
22744
        // op: Rn
22745
        return 16;
22746
      case 3:
22747
        // op: Rm
22748
        return 12;
22749
      }
22750
      break;
22751
    }
22752
    case ARM::CDE_VCX3_fpdp:
22753
    case ARM::CDE_VCX3_fpsp: {
22754
      switch (OpNum) {
22755
      case 1:
22756
        // op: coproc
22757
        return 8;
22758
      case 4:
22759
        // op: imm
22760
        return 4;
22761
      case 0:
22762
        // op: Vd
22763
        return 12;
22764
      case 3:
22765
        // op: Vm
22766
        return 0;
22767
      case 2:
22768
        // op: Vn
22769
        return 7;
22770
      }
22771
      break;
22772
    }
22773
    case ARM::CDE_VCX2A_fpdp:
22774
    case ARM::CDE_VCX2A_fpsp: {
22775
      switch (OpNum) {
22776
      case 1:
22777
        // op: coproc
22778
        return 8;
22779
      case 4:
22780
        // op: imm
22781
        return 4;
22782
      case 0:
22783
        // op: Vd
22784
        return 12;
22785
      case 3:
22786
        // op: Vm
22787
        return 0;
22788
      }
22789
      break;
22790
    }
22791
    case ARM::CDE_VCX3A_vec: {
22792
      switch (OpNum) {
22793
      case 1:
22794
        // op: coproc
22795
        return 8;
22796
      case 5:
22797
        // op: imm
22798
        return 4;
22799
      case 0:
22800
        // op: Qd
22801
        return 13;
22802
      case 4:
22803
        // op: Qm
22804
        return 1;
22805
      case 3:
22806
        // op: Qn
22807
        return 17;
22808
      }
22809
      break;
22810
    }
22811
    case ARM::CDE_CX3A:
22812
    case ARM::CDE_CX3DA: {
22813
      switch (OpNum) {
22814
      case 1:
22815
        // op: coproc
22816
        return 8;
22817
      case 5:
22818
        // op: imm
22819
        return 4;
22820
      case 0:
22821
        // op: Rd
22822
        return 0;
22823
      case 3:
22824
        // op: Rn
22825
        return 16;
22826
      case 4:
22827
        // op: Rm
22828
        return 12;
22829
      }
22830
      break;
22831
    }
22832
    case ARM::CDE_VCX3A_fpdp:
22833
    case ARM::CDE_VCX3A_fpsp: {
22834
      switch (OpNum) {
22835
      case 1:
22836
        // op: coproc
22837
        return 8;
22838
      case 5:
22839
        // op: imm
22840
        return 4;
22841
      case 0:
22842
        // op: Vd
22843
        return 12;
22844
      case 4:
22845
        // op: Vm
22846
        return 0;
22847
      case 3:
22848
        // op: Vn
22849
        return 7;
22850
      }
22851
      break;
22852
    }
22853
    case ARM::MVE_VMOVimmf32:
22854
    case ARM::MVE_VMOVimmi8:
22855
    case ARM::MVE_VMOVimmi16:
22856
    case ARM::MVE_VMOVimmi32:
22857
    case ARM::MVE_VMOVimmi64:
22858
    case ARM::MVE_VMVNimmi16:
22859
    case ARM::MVE_VMVNimmi32: {
22860
      switch (OpNum) {
22861
      case 1:
22862
        // op: imm
22863
        return 0;
22864
      case 0:
22865
        // op: Qd
22866
        return 13;
22867
      }
22868
      break;
22869
    }
22870
    case ARM::CDP2:
22871
    case ARM::t2CDP:
22872
    case ARM::t2CDP2: {
22873
      switch (OpNum) {
22874
      case 1:
22875
        // op: opc1
22876
        return 20;
22877
      case 3:
22878
        // op: CRn
22879
        return 16;
22880
      case 2:
22881
        // op: CRd
22882
        return 12;
22883
      case 0:
22884
        // op: cop
22885
        return 8;
22886
      case 5:
22887
        // op: opc2
22888
        return 5;
22889
      case 4:
22890
        // op: CRm
22891
        return 0;
22892
      }
22893
      break;
22894
    }
22895
    case ARM::t2Bcc: {
22896
      switch (OpNum) {
22897
      case 1:
22898
        // op: p
22899
        return 22;
22900
      case 0:
22901
        // op: target
22902
        return 0;
22903
      }
22904
      break;
22905
    }
22906
    case ARM::VCMPEZD:
22907
    case ARM::VCMPZD: {
22908
      switch (OpNum) {
22909
      case 1:
22910
        // op: p
22911
        return 28;
22912
      case 0:
22913
        // op: Dd
22914
        return 12;
22915
      }
22916
      break;
22917
    }
22918
    case ARM::MRS:
22919
    case ARM::MRSsys: {
22920
      switch (OpNum) {
22921
      case 1:
22922
        // op: p
22923
        return 28;
22924
      case 0:
22925
        // op: Rd
22926
        return 12;
22927
      }
22928
      break;
22929
    }
22930
    case ARM::VLDMSIA:
22931
    case ARM::VSTMSIA: {
22932
      switch (OpNum) {
22933
      case 1:
22934
        // op: p
22935
        return 28;
22936
      case 0:
22937
        // op: Rn
22938
        return 16;
22939
      case 3:
22940
        // op: regs
22941
        return 0;
22942
      }
22943
      break;
22944
    }
22945
    case ARM::FLDMXIA:
22946
    case ARM::FSTMXIA:
22947
    case ARM::VLDMDIA:
22948
    case ARM::VSTMDIA: {
22949
      switch (OpNum) {
22950
      case 1:
22951
        // op: p
22952
        return 28;
22953
      case 0:
22954
        // op: Rn
22955
        return 16;
22956
      case 3:
22957
        // op: regs
22958
        return 1;
22959
      }
22960
      break;
22961
    }
22962
    case ARM::VLLDM:
22963
    case ARM::VLSTM: {
22964
      switch (OpNum) {
22965
      case 1:
22966
        // op: p
22967
        return 28;
22968
      case 0:
22969
        // op: Rn
22970
        return 16;
22971
      }
22972
      break;
22973
    }
22974
    case ARM::VMRS:
22975
    case ARM::VMRS_FPCXTNS:
22976
    case ARM::VMRS_FPCXTS:
22977
    case ARM::VMRS_FPEXC:
22978
    case ARM::VMRS_FPINST:
22979
    case ARM::VMRS_FPINST2:
22980
    case ARM::VMRS_FPSID:
22981
    case ARM::VMRS_MVFR0:
22982
    case ARM::VMRS_MVFR1:
22983
    case ARM::VMRS_MVFR2:
22984
    case ARM::VMRS_VPR:
22985
    case ARM::VMSR:
22986
    case ARM::VMSR_FPCXTNS:
22987
    case ARM::VMSR_FPCXTS:
22988
    case ARM::VMSR_FPEXC:
22989
    case ARM::VMSR_FPINST:
22990
    case ARM::VMSR_FPINST2:
22991
    case ARM::VMSR_FPSID:
22992
    case ARM::VMSR_VPR: {
22993
      switch (OpNum) {
22994
      case 1:
22995
        // op: p
22996
        return 28;
22997
      case 0:
22998
        // op: Rt
22999
        return 12;
23000
      }
23001
      break;
23002
    }
23003
    case ARM::VCMPEZH:
23004
    case ARM::VCMPEZS:
23005
    case ARM::VCMPZH:
23006
    case ARM::VCMPZS: {
23007
      switch (OpNum) {
23008
      case 1:
23009
        // op: p
23010
        return 28;
23011
      case 0:
23012
        // op: Sd
23013
        return 12;
23014
      }
23015
      break;
23016
    }
23017
    case ARM::BX_pred: {
23018
      switch (OpNum) {
23019
      case 1:
23020
        // op: p
23021
        return 28;
23022
      case 0:
23023
        // op: dst
23024
        return 0;
23025
      }
23026
      break;
23027
    }
23028
    case ARM::BLX_pred:
23029
    case ARM::BL_pred:
23030
    case ARM::BXJ: {
23031
      switch (OpNum) {
23032
      case 1:
23033
        // op: p
23034
        return 28;
23035
      case 0:
23036
        // op: func
23037
        return 0;
23038
      }
23039
      break;
23040
    }
23041
    case ARM::HINT: {
23042
      switch (OpNum) {
23043
      case 1:
23044
        // op: p
23045
        return 28;
23046
      case 0:
23047
        // op: imm
23048
        return 0;
23049
      }
23050
      break;
23051
    }
23052
    case ARM::DBG:
23053
    case ARM::SMC: {
23054
      switch (OpNum) {
23055
      case 1:
23056
        // op: p
23057
        return 28;
23058
      case 0:
23059
        // op: opt
23060
        return 0;
23061
      }
23062
      break;
23063
    }
23064
    case ARM::SVC: {
23065
      switch (OpNum) {
23066
      case 1:
23067
        // op: p
23068
        return 28;
23069
      case 0:
23070
        // op: svc
23071
        return 0;
23072
      }
23073
      break;
23074
    }
23075
    case ARM::Bcc: {
23076
      switch (OpNum) {
23077
      case 1:
23078
        // op: p
23079
        return 28;
23080
      case 0:
23081
        // op: target
23082
        return 0;
23083
      }
23084
      break;
23085
    }
23086
    case ARM::LDMDA:
23087
    case ARM::LDMDB:
23088
    case ARM::LDMIA:
23089
    case ARM::LDMIB:
23090
    case ARM::STMDA:
23091
    case ARM::STMDB:
23092
    case ARM::STMIA:
23093
    case ARM::STMIB:
23094
    case ARM::sysLDMDA:
23095
    case ARM::sysLDMDB:
23096
    case ARM::sysLDMIA:
23097
    case ARM::sysLDMIB:
23098
    case ARM::sysSTMDA:
23099
    case ARM::sysSTMDB:
23100
    case ARM::sysSTMIA:
23101
    case ARM::sysSTMIB: {
23102
      switch (OpNum) {
23103
      case 1:
23104
        // op: p
23105
        return 28;
23106
      case 3:
23107
        // op: regs
23108
        return 0;
23109
      case 0:
23110
        // op: Rn
23111
        return 16;
23112
      }
23113
      break;
23114
    }
23115
    case ARM::tBcc: {
23116
      switch (OpNum) {
23117
      case 1:
23118
        // op: p
23119
        return 8;
23120
      case 0:
23121
        // op: target
23122
        return 0;
23123
      }
23124
      break;
23125
    }
23126
    case ARM::tCBNZ:
23127
    case ARM::tCBZ: {
23128
      switch (OpNum) {
23129
      case 1:
23130
        // op: target
23131
        return 3;
23132
      case 0:
23133
        // op: Rn
23134
        return 0;
23135
      }
23136
      break;
23137
    }
23138
    case ARM::MVE_VCADDf16:
23139
    case ARM::MVE_VCADDf32: {
23140
      switch (OpNum) {
23141
      case 2:
23142
        // op: Qm
23143
        return 1;
23144
      case 0:
23145
        // op: Qd
23146
        return 13;
23147
      case 1:
23148
        // op: Qn
23149
        return 7;
23150
      case 3:
23151
        // op: rot
23152
        return 24;
23153
      }
23154
      break;
23155
    }
23156
    case ARM::MVE_VABDf16:
23157
    case ARM::MVE_VABDf32:
23158
    case ARM::MVE_VADDf16:
23159
    case ARM::MVE_VADDf32:
23160
    case ARM::MVE_VMULf16:
23161
    case ARM::MVE_VMULf32:
23162
    case ARM::MVE_VSUBf16:
23163
    case ARM::MVE_VSUBf32: {
23164
      switch (OpNum) {
23165
      case 2:
23166
        // op: Qm
23167
        return 1;
23168
      case 0:
23169
        // op: Qd
23170
        return 13;
23171
      case 1:
23172
        // op: Qn
23173
        return 7;
23174
      }
23175
      break;
23176
    }
23177
    case ARM::MVE_VADDVs8acc:
23178
    case ARM::MVE_VADDVs16acc:
23179
    case ARM::MVE_VADDVs32acc:
23180
    case ARM::MVE_VADDVu8acc:
23181
    case ARM::MVE_VADDVu16acc:
23182
    case ARM::MVE_VADDVu32acc: {
23183
      switch (OpNum) {
23184
      case 2:
23185
        // op: Qm
23186
        return 1;
23187
      case 0:
23188
        // op: Rda
23189
        return 13;
23190
      }
23191
      break;
23192
    }
23193
    case ARM::MVE_VMAXAVs8:
23194
    case ARM::MVE_VMAXAVs16:
23195
    case ARM::MVE_VMAXAVs32:
23196
    case ARM::MVE_VMAXNMAVf16:
23197
    case ARM::MVE_VMAXNMAVf32:
23198
    case ARM::MVE_VMAXNMVf16:
23199
    case ARM::MVE_VMAXNMVf32:
23200
    case ARM::MVE_VMAXVs8:
23201
    case ARM::MVE_VMAXVs16:
23202
    case ARM::MVE_VMAXVs32:
23203
    case ARM::MVE_VMAXVu8:
23204
    case ARM::MVE_VMAXVu16:
23205
    case ARM::MVE_VMAXVu32:
23206
    case ARM::MVE_VMINAVs8:
23207
    case ARM::MVE_VMINAVs16:
23208
    case ARM::MVE_VMINAVs32:
23209
    case ARM::MVE_VMINNMAVf16:
23210
    case ARM::MVE_VMINNMAVf32:
23211
    case ARM::MVE_VMINNMVf16:
23212
    case ARM::MVE_VMINNMVf32:
23213
    case ARM::MVE_VMINVs8:
23214
    case ARM::MVE_VMINVs16:
23215
    case ARM::MVE_VMINVs32:
23216
    case ARM::MVE_VMINVu8:
23217
    case ARM::MVE_VMINVu16:
23218
    case ARM::MVE_VMINVu32: {
23219
      switch (OpNum) {
23220
      case 2:
23221
        // op: Qm
23222
        return 1;
23223
      case 0:
23224
        // op: RdaDest
23225
        return 12;
23226
      }
23227
      break;
23228
    }
23229
    case ARM::MVE_VADDLVs32no_acc:
23230
    case ARM::MVE_VADDLVu32no_acc: {
23231
      switch (OpNum) {
23232
      case 2:
23233
        // op: Qm
23234
        return 1;
23235
      case 0:
23236
        // op: RdaLo
23237
        return 13;
23238
      case 1:
23239
        // op: RdaHi
23240
        return 20;
23241
      }
23242
      break;
23243
    }
23244
    case ARM::t2AUTG:
23245
    case ARM::t2BXAUT: {
23246
      switch (OpNum) {
23247
      case 2:
23248
        // op: Ra
23249
        return 12;
23250
      case 3:
23251
        // op: Rn
23252
        return 16;
23253
      case 4:
23254
        // op: Rm
23255
        return 0;
23256
      }
23257
      break;
23258
    }
23259
    case ARM::tADDspr: {
23260
      switch (OpNum) {
23261
      case 2:
23262
        // op: Rm
23263
        return 3;
23264
      }
23265
      break;
23266
    }
23267
    case ARM::MVE_VMOV_q_rr: {
23268
      switch (OpNum) {
23269
      case 2:
23270
        // op: Rt
23271
        return 0;
23272
      case 3:
23273
        // op: Rt2
23274
        return 16;
23275
      case 0:
23276
        // op: Qd
23277
        return 13;
23278
      case 5:
23279
        // op: idx2
23280
        return 4;
23281
      }
23282
      break;
23283
    }
23284
    case ARM::MCR2:
23285
    case ARM::t2MCR:
23286
    case ARM::t2MCR2: {
23287
      switch (OpNum) {
23288
      case 2:
23289
        // op: Rt
23290
        return 12;
23291
      case 0:
23292
        // op: cop
23293
        return 8;
23294
      case 1:
23295
        // op: opc1
23296
        return 21;
23297
      case 5:
23298
        // op: opc2
23299
        return 5;
23300
      case 4:
23301
        // op: CRm
23302
        return 0;
23303
      case 3:
23304
        // op: CRn
23305
        return 16;
23306
      }
23307
      break;
23308
    }
23309
    case ARM::MCRR2:
23310
    case ARM::t2MCRR:
23311
    case ARM::t2MCRR2: {
23312
      switch (OpNum) {
23313
      case 2:
23314
        // op: Rt
23315
        return 12;
23316
      case 3:
23317
        // op: Rt2
23318
        return 16;
23319
      case 0:
23320
        // op: cop
23321
        return 8;
23322
      case 1:
23323
        // op: opc1
23324
        return 4;
23325
      case 4:
23326
        // op: CRm
23327
        return 0;
23328
      }
23329
      break;
23330
    }
23331
    case ARM::VST1LNd8: {
23332
      switch (OpNum) {
23333
      case 2:
23334
        // op: Vd
23335
        return 12;
23336
      case 0:
23337
        // op: Rn
23338
        return 16;
23339
      case 3:
23340
        // op: lane
23341
        return 5;
23342
      }
23343
      break;
23344
    }
23345
    case ARM::VST3LNd8: {
23346
      switch (OpNum) {
23347
      case 2:
23348
        // op: Vd
23349
        return 12;
23350
      case 0:
23351
        // op: Rn
23352
        return 16;
23353
      case 5:
23354
        // op: lane
23355
        return 5;
23356
      }
23357
      break;
23358
    }
23359
    case ARM::VST3LNd16:
23360
    case ARM::VST3LNq16: {
23361
      switch (OpNum) {
23362
      case 2:
23363
        // op: Vd
23364
        return 12;
23365
      case 0:
23366
        // op: Rn
23367
        return 16;
23368
      case 5:
23369
        // op: lane
23370
        return 6;
23371
      }
23372
      break;
23373
    }
23374
    case ARM::VST3LNd32:
23375
    case ARM::VST3LNq32: {
23376
      switch (OpNum) {
23377
      case 2:
23378
        // op: Vd
23379
        return 12;
23380
      case 0:
23381
        // op: Rn
23382
        return 16;
23383
      case 5:
23384
        // op: lane
23385
        return 7;
23386
      }
23387
      break;
23388
    }
23389
    case ARM::VST1LNd16: {
23390
      switch (OpNum) {
23391
      case 2:
23392
        // op: Vd
23393
        return 12;
23394
      case 0:
23395
        // op: Rn
23396
        return 4;
23397
      case 3:
23398
        // op: lane
23399
        return 6;
23400
      }
23401
      break;
23402
    }
23403
    case ARM::VST1LNd32: {
23404
      switch (OpNum) {
23405
      case 2:
23406
        // op: Vd
23407
        return 12;
23408
      case 0:
23409
        // op: Rn
23410
        return 4;
23411
      case 3:
23412
        // op: lane
23413
        return 7;
23414
      }
23415
      break;
23416
    }
23417
    case ARM::VST2LNd8: {
23418
      switch (OpNum) {
23419
      case 2:
23420
        // op: Vd
23421
        return 12;
23422
      case 0:
23423
        // op: Rn
23424
        return 4;
23425
      case 4:
23426
        // op: lane
23427
        return 5;
23428
      }
23429
      break;
23430
    }
23431
    case ARM::VST2LNd16:
23432
    case ARM::VST2LNq16: {
23433
      switch (OpNum) {
23434
      case 2:
23435
        // op: Vd
23436
        return 12;
23437
      case 0:
23438
        // op: Rn
23439
        return 4;
23440
      case 4:
23441
        // op: lane
23442
        return 6;
23443
      }
23444
      break;
23445
    }
23446
    case ARM::VST2LNd32:
23447
    case ARM::VST2LNq32: {
23448
      switch (OpNum) {
23449
      case 2:
23450
        // op: Vd
23451
        return 12;
23452
      case 0:
23453
        // op: Rn
23454
        return 4;
23455
      case 4:
23456
        // op: lane
23457
        return 7;
23458
      }
23459
      break;
23460
    }
23461
    case ARM::VST4LNd8: {
23462
      switch (OpNum) {
23463
      case 2:
23464
        // op: Vd
23465
        return 12;
23466
      case 0:
23467
        // op: Rn
23468
        return 4;
23469
      case 6:
23470
        // op: lane
23471
        return 5;
23472
      }
23473
      break;
23474
    }
23475
    case ARM::VST4LNd16:
23476
    case ARM::VST4LNq16: {
23477
      switch (OpNum) {
23478
      case 2:
23479
        // op: Vd
23480
        return 12;
23481
      case 0:
23482
        // op: Rn
23483
        return 4;
23484
      case 6:
23485
        // op: lane
23486
        return 6;
23487
      }
23488
      break;
23489
    }
23490
    case ARM::VST4LNd32:
23491
    case ARM::VST4LNq32: {
23492
      switch (OpNum) {
23493
      case 2:
23494
        // op: Vd
23495
        return 12;
23496
      case 0:
23497
        // op: Rn
23498
        return 4;
23499
      case 6:
23500
        // op: lane
23501
        return 7;
23502
      }
23503
      break;
23504
    }
23505
    case ARM::VST1d8:
23506
    case ARM::VST1d8Q:
23507
    case ARM::VST1d8T:
23508
    case ARM::VST1d16:
23509
    case ARM::VST1d16Q:
23510
    case ARM::VST1d16T:
23511
    case ARM::VST1d32:
23512
    case ARM::VST1d32Q:
23513
    case ARM::VST1d32T:
23514
    case ARM::VST1d64:
23515
    case ARM::VST1d64Q:
23516
    case ARM::VST1d64T:
23517
    case ARM::VST1q8:
23518
    case ARM::VST1q16:
23519
    case ARM::VST1q32:
23520
    case ARM::VST1q64:
23521
    case ARM::VST2b8:
23522
    case ARM::VST2b16:
23523
    case ARM::VST2b32:
23524
    case ARM::VST2d8:
23525
    case ARM::VST2d16:
23526
    case ARM::VST2d32:
23527
    case ARM::VST2q8:
23528
    case ARM::VST2q16:
23529
    case ARM::VST2q32:
23530
    case ARM::VST3d8:
23531
    case ARM::VST3d16:
23532
    case ARM::VST3d32:
23533
    case ARM::VST3q8:
23534
    case ARM::VST3q16:
23535
    case ARM::VST3q32:
23536
    case ARM::VST4d8:
23537
    case ARM::VST4d16:
23538
    case ARM::VST4d32:
23539
    case ARM::VST4q8:
23540
    case ARM::VST4q16:
23541
    case ARM::VST4q32: {
23542
      switch (OpNum) {
23543
      case 2:
23544
        // op: Vd
23545
        return 12;
23546
      case 0:
23547
        // op: Rn
23548
        return 4;
23549
      }
23550
      break;
23551
    }
23552
    case ARM::LDC2L_OFFSET:
23553
    case ARM::LDC2L_PRE:
23554
    case ARM::LDC2_OFFSET:
23555
    case ARM::LDC2_PRE:
23556
    case ARM::STC2L_OFFSET:
23557
    case ARM::STC2L_PRE:
23558
    case ARM::STC2_OFFSET:
23559
    case ARM::STC2_PRE:
23560
    case ARM::t2LDC2L_OFFSET:
23561
    case ARM::t2LDC2L_PRE:
23562
    case ARM::t2LDC2_OFFSET:
23563
    case ARM::t2LDC2_PRE:
23564
    case ARM::t2LDCL_OFFSET:
23565
    case ARM::t2LDCL_PRE:
23566
    case ARM::t2LDC_OFFSET:
23567
    case ARM::t2LDC_PRE:
23568
    case ARM::t2STC2L_OFFSET:
23569
    case ARM::t2STC2L_PRE:
23570
    case ARM::t2STC2_OFFSET:
23571
    case ARM::t2STC2_PRE:
23572
    case ARM::t2STCL_OFFSET:
23573
    case ARM::t2STCL_PRE:
23574
    case ARM::t2STC_OFFSET:
23575
    case ARM::t2STC_PRE: {
23576
      switch (OpNum) {
23577
      case 2:
23578
        // op: addr
23579
        return 0;
23580
      case 0:
23581
        // op: cop
23582
        return 8;
23583
      case 1:
23584
        // op: CRd
23585
        return 12;
23586
      }
23587
      break;
23588
    }
23589
    case ARM::t2LDAEXD:
23590
    case ARM::t2LDREXD: {
23591
      switch (OpNum) {
23592
      case 2:
23593
        // op: addr
23594
        return 16;
23595
      case 0:
23596
        // op: Rt
23597
        return 12;
23598
      case 1:
23599
        // op: Rt2
23600
        return 8;
23601
      }
23602
      break;
23603
    }
23604
    case ARM::tBL: {
23605
      switch (OpNum) {
23606
      case 2:
23607
        // op: func
23608
        return 0;
23609
      }
23610
      break;
23611
    }
23612
    case ARM::tBLXi: {
23613
      switch (OpNum) {
23614
      case 2:
23615
        // op: func
23616
        return 1;
23617
      }
23618
      break;
23619
    }
23620
    case ARM::tBLXNSr:
23621
    case ARM::tBLXr: {
23622
      switch (OpNum) {
23623
      case 2:
23624
        // op: func
23625
        return 3;
23626
      }
23627
      break;
23628
    }
23629
    case ARM::MVE_VBICimmi16:
23630
    case ARM::MVE_VBICimmi32:
23631
    case ARM::MVE_VORRimmi16:
23632
    case ARM::MVE_VORRimmi32: {
23633
      switch (OpNum) {
23634
      case 2:
23635
        // op: imm
23636
        return 0;
23637
      case 0:
23638
        // op: Qd
23639
        return 13;
23640
      }
23641
      break;
23642
    }
23643
    case ARM::t2ADDspImm12:
23644
    case ARM::t2SUBspImm12:
23645
    case ARM::tADDspi:
23646
    case ARM::tSUBspi: {
23647
      switch (OpNum) {
23648
      case 2:
23649
        // op: imm
23650
        return 0;
23651
      }
23652
      break;
23653
    }
23654
    case ARM::MVE_LETP:
23655
    case ARM::t2LEUpdate: {
23656
      switch (OpNum) {
23657
      case 2:
23658
        // op: label
23659
        return 1;
23660
      }
23661
      break;
23662
    }
23663
    case ARM::VABSD:
23664
    case ARM::VCMPD:
23665
    case ARM::VCMPED:
23666
    case ARM::VMOVD:
23667
    case ARM::VNEGD:
23668
    case ARM::VRINTRD:
23669
    case ARM::VRINTXD:
23670
    case ARM::VRINTZD:
23671
    case ARM::VSQRTD: {
23672
      switch (OpNum) {
23673
      case 2:
23674
        // op: p
23675
        return 28;
23676
      case 0:
23677
        // op: Dd
23678
        return 12;
23679
      case 1:
23680
        // op: Dm
23681
        return 0;
23682
      }
23683
      break;
23684
    }
23685
    case ARM::VCVTBHD:
23686
    case ARM::VCVTTHD:
23687
    case ARM::VSITOD:
23688
    case ARM::VUITOD: {
23689
      switch (OpNum) {
23690
      case 2:
23691
        // op: p
23692
        return 28;
23693
      case 0:
23694
        // op: Dd
23695
        return 12;
23696
      case 1:
23697
        // op: Sm
23698
        return 0;
23699
      }
23700
      break;
23701
    }
23702
    case ARM::FCONSTD: {
23703
      switch (OpNum) {
23704
      case 2:
23705
        // op: p
23706
        return 28;
23707
      case 0:
23708
        // op: Dd
23709
        return 12;
23710
      case 1:
23711
        // op: imm
23712
        return 0;
23713
      }
23714
      break;
23715
    }
23716
    case ARM::CLZ:
23717
    case ARM::RBIT:
23718
    case ARM::REV:
23719
    case ARM::REV16:
23720
    case ARM::REVSH: {
23721
      switch (OpNum) {
23722
      case 2:
23723
        // op: p
23724
        return 28;
23725
      case 0:
23726
        // op: Rd
23727
        return 12;
23728
      case 1:
23729
        // op: Rm
23730
        return 0;
23731
      }
23732
      break;
23733
    }
23734
    case ARM::MOVi16: {
23735
      switch (OpNum) {
23736
      case 2:
23737
        // op: p
23738
        return 28;
23739
      case 0:
23740
        // op: Rd
23741
        return 12;
23742
      case 1:
23743
        // op: imm
23744
        return 0;
23745
      }
23746
      break;
23747
    }
23748
    case ARM::ADR: {
23749
      switch (OpNum) {
23750
      case 2:
23751
        // op: p
23752
        return 28;
23753
      case 0:
23754
        // op: Rd
23755
        return 12;
23756
      case 1:
23757
        // op: label
23758
        return 0;
23759
      }
23760
      break;
23761
    }
23762
    case ARM::CMNzrr:
23763
    case ARM::CMPrr:
23764
    case ARM::TEQrr:
23765
    case ARM::TSTrr: {
23766
      switch (OpNum) {
23767
      case 2:
23768
        // op: p
23769
        return 28;
23770
      case 0:
23771
        // op: Rn
23772
        return 16;
23773
      case 1:
23774
        // op: Rm
23775
        return 0;
23776
      }
23777
      break;
23778
    }
23779
    case ARM::CMNri:
23780
    case ARM::CMPri:
23781
    case ARM::TEQri:
23782
    case ARM::TSTri: {
23783
      switch (OpNum) {
23784
      case 2:
23785
        // op: p
23786
        return 28;
23787
      case 0:
23788
        // op: Rn
23789
        return 16;
23790
      case 1:
23791
        // op: imm
23792
        return 0;
23793
      }
23794
      break;
23795
    }
23796
    case ARM::STL:
23797
    case ARM::STLB:
23798
    case ARM::STLH: {
23799
      switch (OpNum) {
23800
      case 2:
23801
        // op: p
23802
        return 28;
23803
      case 0:
23804
        // op: Rt
23805
        return 0;
23806
      case 1:
23807
        // op: addr
23808
        return 16;
23809
      }
23810
      break;
23811
    }
23812
    case ARM::VMOVRH:
23813
    case ARM::VMOVRS: {
23814
      switch (OpNum) {
23815
      case 2:
23816
        // op: p
23817
        return 28;
23818
      case 0:
23819
        // op: Rt
23820
        return 12;
23821
      case 1:
23822
        // op: Sn
23823
        return 7;
23824
      }
23825
      break;
23826
    }
23827
    case ARM::LDA:
23828
    case ARM::LDAB:
23829
    case ARM::LDAEX:
23830
    case ARM::LDAEXB:
23831
    case ARM::LDAEXD:
23832
    case ARM::LDAEXH:
23833
    case ARM::LDAH:
23834
    case ARM::LDREX:
23835
    case ARM::LDREXB:
23836
    case ARM::LDREXD:
23837
    case ARM::LDREXH: {
23838
      switch (OpNum) {
23839
      case 2:
23840
        // op: p
23841
        return 28;
23842
      case 0:
23843
        // op: Rt
23844
        return 12;
23845
      case 1:
23846
        // op: addr
23847
        return 16;
23848
      }
23849
      break;
23850
    }
23851
    case ARM::VMRS_FPSCR_NZCVQC:
23852
    case ARM::VMRS_P0: {
23853
      switch (OpNum) {
23854
      case 2:
23855
        // op: p
23856
        return 28;
23857
      case 0:
23858
        // op: Rt
23859
        return 12;
23860
      }
23861
      break;
23862
    }
23863
    case ARM::VCVTSD:
23864
    case ARM::VJCVT:
23865
    case ARM::VTOSIRD:
23866
    case ARM::VTOSIZD:
23867
    case ARM::VTOUIRD:
23868
    case ARM::VTOUIZD: {
23869
      switch (OpNum) {
23870
      case 2:
23871
        // op: p
23872
        return 28;
23873
      case 0:
23874
        // op: Sd
23875
        return 12;
23876
      case 1:
23877
        // op: Dm
23878
        return 0;
23879
      }
23880
      break;
23881
    }
23882
    case ARM::VABSH:
23883
    case ARM::VABSS:
23884
    case ARM::VCMPEH:
23885
    case ARM::VCMPES:
23886
    case ARM::VCMPH:
23887
    case ARM::VCMPS:
23888
    case ARM::VCVTBHS:
23889
    case ARM::VCVTTHS:
23890
    case ARM::VMOVS:
23891
    case ARM::VNEGH:
23892
    case ARM::VNEGS:
23893
    case ARM::VRINTRH:
23894
    case ARM::VRINTRS:
23895
    case ARM::VRINTXH:
23896
    case ARM::VRINTXS:
23897
    case ARM::VRINTZH:
23898
    case ARM::VRINTZS:
23899
    case ARM::VSITOH:
23900
    case ARM::VSITOS:
23901
    case ARM::VSQRTH:
23902
    case ARM::VSQRTS:
23903
    case ARM::VTOSIRH:
23904
    case ARM::VTOSIRS:
23905
    case ARM::VTOSIZH:
23906
    case ARM::VTOSIZS:
23907
    case ARM::VTOUIRH:
23908
    case ARM::VTOUIRS:
23909
    case ARM::VTOUIZH:
23910
    case ARM::VTOUIZS:
23911
    case ARM::VUITOH:
23912
    case ARM::VUITOS: {
23913
      switch (OpNum) {
23914
      case 2:
23915
        // op: p
23916
        return 28;
23917
      case 0:
23918
        // op: Sd
23919
        return 12;
23920
      case 1:
23921
        // op: Sm
23922
        return 0;
23923
      }
23924
      break;
23925
    }
23926
    case ARM::FCONSTH:
23927
    case ARM::FCONSTS: {
23928
      switch (OpNum) {
23929
      case 2:
23930
        // op: p
23931
        return 28;
23932
      case 0:
23933
        // op: Sd
23934
        return 12;
23935
      case 1:
23936
        // op: imm
23937
        return 0;
23938
      }
23939
      break;
23940
    }
23941
    case ARM::VMOVHR:
23942
    case ARM::VMOVSR: {
23943
      switch (OpNum) {
23944
      case 2:
23945
        // op: p
23946
        return 28;
23947
      case 0:
23948
        // op: Sn
23949
        return 7;
23950
      case 1:
23951
        // op: Rt
23952
        return 12;
23953
      }
23954
      break;
23955
    }
23956
    case ARM::VLDR_FPCXTNS_off:
23957
    case ARM::VLDR_FPCXTS_off:
23958
    case ARM::VLDR_FPSCR_NZCVQC_off:
23959
    case ARM::VLDR_FPSCR_off:
23960
    case ARM::VLDR_VPR_off:
23961
    case ARM::VSTR_FPCXTNS_off:
23962
    case ARM::VSTR_FPCXTS_off:
23963
    case ARM::VSTR_FPSCR_NZCVQC_off:
23964
    case ARM::VSTR_FPSCR_off:
23965
    case ARM::VSTR_VPR_off: {
23966
      switch (OpNum) {
23967
      case 2:
23968
        // op: p
23969
        return 28;
23970
      case 0:
23971
        // op: addr
23972
        return 0;
23973
      }
23974
      break;
23975
    }
23976
    case ARM::MSRbanked: {
23977
      switch (OpNum) {
23978
      case 2:
23979
        // op: p
23980
        return 28;
23981
      case 0:
23982
        // op: banked
23983
        return 8;
23984
      case 1:
23985
        // op: Rn
23986
        return 0;
23987
      }
23988
      break;
23989
    }
23990
    case ARM::MSR: {
23991
      switch (OpNum) {
23992
      case 2:
23993
        // op: p
23994
        return 28;
23995
      case 0:
23996
        // op: mask
23997
        return 16;
23998
      case 1:
23999
        // op: Rn
24000
        return 0;
24001
      }
24002
      break;
24003
    }
24004
    case ARM::MSRi: {
24005
      switch (OpNum) {
24006
      case 2:
24007
        // op: p
24008
        return 28;
24009
      case 0:
24010
        // op: mask
24011
        return 16;
24012
      case 1:
24013
        // op: imm
24014
        return 0;
24015
      }
24016
      break;
24017
    }
24018
    case ARM::VLDMSDB_UPD:
24019
    case ARM::VLDMSIA_UPD:
24020
    case ARM::VSTMSDB_UPD:
24021
    case ARM::VSTMSIA_UPD: {
24022
      switch (OpNum) {
24023
      case 2:
24024
        // op: p
24025
        return 28;
24026
      case 1:
24027
        // op: Rn
24028
        return 16;
24029
      case 4:
24030
        // op: regs
24031
        return 0;
24032
      }
24033
      break;
24034
    }
24035
    case ARM::FLDMXDB_UPD:
24036
    case ARM::FLDMXIA_UPD:
24037
    case ARM::FSTMXDB_UPD:
24038
    case ARM::FSTMXIA_UPD:
24039
    case ARM::VLDMDDB_UPD:
24040
    case ARM::VLDMDIA_UPD:
24041
    case ARM::VSTMDDB_UPD:
24042
    case ARM::VSTMDIA_UPD: {
24043
      switch (OpNum) {
24044
      case 2:
24045
        // op: p
24046
        return 28;
24047
      case 1:
24048
        // op: Rn
24049
        return 16;
24050
      case 4:
24051
        // op: regs
24052
        return 1;
24053
      }
24054
      break;
24055
    }
24056
    case ARM::VMSR_FPSCR_NZCVQC:
24057
    case ARM::VMSR_P0: {
24058
      switch (OpNum) {
24059
      case 2:
24060
        // op: p
24061
        return 28;
24062
      case 1:
24063
        // op: Rt
24064
        return 12;
24065
      }
24066
      break;
24067
    }
24068
    case ARM::VCVTDS: {
24069
      switch (OpNum) {
24070
      case 2:
24071
        // op: p
24072
        return 28;
24073
      case 1:
24074
        // op: Sm
24075
        return 0;
24076
      case 0:
24077
        // op: Dd
24078
        return 12;
24079
      }
24080
      break;
24081
    }
24082
    case ARM::MRSbanked: {
24083
      switch (OpNum) {
24084
      case 2:
24085
        // op: p
24086
        return 28;
24087
      case 1:
24088
        // op: banked
24089
        return 8;
24090
      case 0:
24091
        // op: Rd
24092
        return 12;
24093
      }
24094
      break;
24095
    }
24096
    case ARM::LDMDA_UPD:
24097
    case ARM::LDMDB_UPD:
24098
    case ARM::LDMIA_UPD:
24099
    case ARM::LDMIB_UPD:
24100
    case ARM::STMDA_UPD:
24101
    case ARM::STMDB_UPD:
24102
    case ARM::STMIA_UPD:
24103
    case ARM::STMIB_UPD:
24104
    case ARM::sysLDMDA_UPD:
24105
    case ARM::sysLDMDB_UPD:
24106
    case ARM::sysLDMIA_UPD:
24107
    case ARM::sysLDMIB_UPD:
24108
    case ARM::sysSTMDA_UPD:
24109
    case ARM::sysSTMDB_UPD:
24110
    case ARM::sysSTMIA_UPD:
24111
    case ARM::sysSTMIB_UPD: {
24112
      switch (OpNum) {
24113
      case 2:
24114
        // op: p
24115
        return 28;
24116
      case 4:
24117
        // op: regs
24118
        return 0;
24119
      case 1:
24120
        // op: Rn
24121
        return 16;
24122
      }
24123
      break;
24124
    }
24125
    case ARM::MOVr:
24126
    case ARM::MOVr_TC:
24127
    case ARM::MVNr: {
24128
      switch (OpNum) {
24129
      case 2:
24130
        // op: p
24131
        return 28;
24132
      case 4:
24133
        // op: s
24134
        return 20;
24135
      case 0:
24136
        // op: Rd
24137
        return 12;
24138
      case 1:
24139
        // op: Rm
24140
        return 0;
24141
      }
24142
      break;
24143
    }
24144
    case ARM::MOVi:
24145
    case ARM::MVNi: {
24146
      switch (OpNum) {
24147
      case 2:
24148
        // op: p
24149
        return 28;
24150
      case 4:
24151
        // op: s
24152
        return 20;
24153
      case 0:
24154
        // op: Rd
24155
        return 12;
24156
      case 1:
24157
        // op: imm
24158
        return 0;
24159
      }
24160
      break;
24161
    }
24162
    case ARM::VSCCLRMS:
24163
    case ARM::t2CLRM:
24164
    case ARM::tPOP:
24165
    case ARM::tPUSH: {
24166
      switch (OpNum) {
24167
      case 2:
24168
        // op: regs
24169
        return 0;
24170
      }
24171
      break;
24172
    }
24173
    case ARM::VSCCLRMD: {
24174
      switch (OpNum) {
24175
      case 2:
24176
        // op: regs
24177
        return 1;
24178
      }
24179
      break;
24180
    }
24181
    case ARM::MVE_VCMLAf16:
24182
    case ARM::MVE_VCMLAf32: {
24183
      switch (OpNum) {
24184
      case 3:
24185
        // op: Qm
24186
        return 1;
24187
      case 0:
24188
        // op: Qd
24189
        return 13;
24190
      case 2:
24191
        // op: Qn
24192
        return 7;
24193
      case 4:
24194
        // op: rot
24195
        return 23;
24196
      }
24197
      break;
24198
    }
24199
    case ARM::MVE_VFMAf16:
24200
    case ARM::MVE_VFMAf32:
24201
    case ARM::MVE_VFMSf16:
24202
    case ARM::MVE_VFMSf32: {
24203
      switch (OpNum) {
24204
      case 3:
24205
        // op: Qm
24206
        return 1;
24207
      case 0:
24208
        // op: Qd
24209
        return 13;
24210
      case 2:
24211
        // op: Qn
24212
        return 7;
24213
      }
24214
      break;
24215
    }
24216
    case ARM::MVE_VABAVs8:
24217
    case ARM::MVE_VABAVs16:
24218
    case ARM::MVE_VABAVs32:
24219
    case ARM::MVE_VABAVu8:
24220
    case ARM::MVE_VABAVu16:
24221
    case ARM::MVE_VABAVu32: {
24222
      switch (OpNum) {
24223
      case 3:
24224
        // op: Qm
24225
        return 1;
24226
      case 2:
24227
        // op: Qn
24228
        return 7;
24229
      case 0:
24230
        // op: Rda
24231
        return 12;
24232
      }
24233
      break;
24234
    }
24235
    case ARM::tADDrr:
24236
    case ARM::tSUBrr: {
24237
      switch (OpNum) {
24238
      case 3:
24239
        // op: Rm
24240
        return 6;
24241
      case 2:
24242
        // op: Rn
24243
        return 3;
24244
      case 0:
24245
        // op: Rd
24246
        return 0;
24247
      }
24248
      break;
24249
    }
24250
    case ARM::VST1d8Qwb_fixed:
24251
    case ARM::VST1d8Twb_fixed:
24252
    case ARM::VST1d8wb_fixed:
24253
    case ARM::VST1d16Qwb_fixed:
24254
    case ARM::VST1d16Twb_fixed:
24255
    case ARM::VST1d16wb_fixed:
24256
    case ARM::VST1d32Qwb_fixed:
24257
    case ARM::VST1d32Twb_fixed:
24258
    case ARM::VST1d32wb_fixed:
24259
    case ARM::VST1d64Qwb_fixed:
24260
    case ARM::VST1d64Twb_fixed:
24261
    case ARM::VST1d64wb_fixed:
24262
    case ARM::VST1q8wb_fixed:
24263
    case ARM::VST1q16wb_fixed:
24264
    case ARM::VST1q32wb_fixed:
24265
    case ARM::VST1q64wb_fixed:
24266
    case ARM::VST2b8wb_fixed:
24267
    case ARM::VST2b16wb_fixed:
24268
    case ARM::VST2b32wb_fixed:
24269
    case ARM::VST2d8wb_fixed:
24270
    case ARM::VST2d16wb_fixed:
24271
    case ARM::VST2d32wb_fixed:
24272
    case ARM::VST2q8wb_fixed:
24273
    case ARM::VST2q16wb_fixed:
24274
    case ARM::VST2q32wb_fixed: {
24275
      switch (OpNum) {
24276
      case 3:
24277
        // op: Vd
24278
        return 12;
24279
      case 1:
24280
        // op: Rn
24281
        return 4;
24282
      }
24283
      break;
24284
    }
24285
    case ARM::t2BFic: {
24286
      switch (OpNum) {
24287
      case 3:
24288
        // op: bcond
24289
        return 18;
24290
      case 1:
24291
        // op: label
24292
        return 1;
24293
      case 2:
24294
        // op: ba_label
24295
        return 17;
24296
      case 0:
24297
        // op: b_label
24298
        return 23;
24299
      }
24300
      break;
24301
    }
24302
    case ARM::MVE_VPTv4f32:
24303
    case ARM::MVE_VPTv4s32:
24304
    case ARM::MVE_VPTv8f16:
24305
    case ARM::MVE_VPTv8s16:
24306
    case ARM::MVE_VPTv16s8: {
24307
      switch (OpNum) {
24308
      case 3:
24309
        // op: fc
24310
        return 0;
24311
      case 0:
24312
        // op: Mk
24313
        return 13;
24314
      case 1:
24315
        // op: Qn
24316
        return 17;
24317
      case 2:
24318
        // op: Qm
24319
        return 1;
24320
      }
24321
      break;
24322
    }
24323
    case ARM::MVE_VCMPf16:
24324
    case ARM::MVE_VCMPf32:
24325
    case ARM::MVE_VCMPs8:
24326
    case ARM::MVE_VCMPs16:
24327
    case ARM::MVE_VCMPs32: {
24328
      switch (OpNum) {
24329
      case 3:
24330
        // op: fc
24331
        return 0;
24332
      case 1:
24333
        // op: Qn
24334
        return 17;
24335
      case 2:
24336
        // op: Qm
24337
        return 1;
24338
      }
24339
      break;
24340
    }
24341
    case ARM::MVE_VPTv4f32r:
24342
    case ARM::MVE_VPTv4s32r:
24343
    case ARM::MVE_VPTv8f16r:
24344
    case ARM::MVE_VPTv8s16r:
24345
    case ARM::MVE_VPTv16s8r: {
24346
      switch (OpNum) {
24347
      case 3:
24348
        // op: fc
24349
        return 5;
24350
      case 0:
24351
        // op: Mk
24352
        return 13;
24353
      case 1:
24354
        // op: Qn
24355
        return 17;
24356
      case 2:
24357
        // op: Rm
24358
        return 0;
24359
      }
24360
      break;
24361
    }
24362
    case ARM::MVE_VCMPf16r:
24363
    case ARM::MVE_VCMPf32r:
24364
    case ARM::MVE_VCMPs8r:
24365
    case ARM::MVE_VCMPs16r:
24366
    case ARM::MVE_VCMPs32r: {
24367
      switch (OpNum) {
24368
      case 3:
24369
        // op: fc
24370
        return 5;
24371
      case 1:
24372
        // op: Qn
24373
        return 17;
24374
      case 2:
24375
        // op: Rm
24376
        return 0;
24377
      }
24378
      break;
24379
    }
24380
    case ARM::MVE_VPTv4i32:
24381
    case ARM::MVE_VPTv4u32:
24382
    case ARM::MVE_VPTv8i16:
24383
    case ARM::MVE_VPTv8u16:
24384
    case ARM::MVE_VPTv16i8:
24385
    case ARM::MVE_VPTv16u8: {
24386
      switch (OpNum) {
24387
      case 3:
24388
        // op: fc
24389
        return 7;
24390
      case 0:
24391
        // op: Mk
24392
        return 13;
24393
      case 1:
24394
        // op: Qn
24395
        return 17;
24396
      case 2:
24397
        // op: Qm
24398
        return 1;
24399
      }
24400
      break;
24401
    }
24402
    case ARM::MVE_VPTv4i32r:
24403
    case ARM::MVE_VPTv4u32r:
24404
    case ARM::MVE_VPTv8i16r:
24405
    case ARM::MVE_VPTv8u16r:
24406
    case ARM::MVE_VPTv16i8r:
24407
    case ARM::MVE_VPTv16u8r: {
24408
      switch (OpNum) {
24409
      case 3:
24410
        // op: fc
24411
        return 7;
24412
      case 0:
24413
        // op: Mk
24414
        return 13;
24415
      case 1:
24416
        // op: Qn
24417
        return 17;
24418
      case 2:
24419
        // op: Rm
24420
        return 0;
24421
      }
24422
      break;
24423
    }
24424
    case ARM::MVE_VCMPi8:
24425
    case ARM::MVE_VCMPi16:
24426
    case ARM::MVE_VCMPi32:
24427
    case ARM::MVE_VCMPu8:
24428
    case ARM::MVE_VCMPu16:
24429
    case ARM::MVE_VCMPu32: {
24430
      switch (OpNum) {
24431
      case 3:
24432
        // op: fc
24433
        return 7;
24434
      case 1:
24435
        // op: Qn
24436
        return 17;
24437
      case 2:
24438
        // op: Qm
24439
        return 1;
24440
      }
24441
      break;
24442
    }
24443
    case ARM::MVE_VCMPi8r:
24444
    case ARM::MVE_VCMPi16r:
24445
    case ARM::MVE_VCMPi32r:
24446
    case ARM::MVE_VCMPu8r:
24447
    case ARM::MVE_VCMPu16r:
24448
    case ARM::MVE_VCMPu32r: {
24449
      switch (OpNum) {
24450
      case 3:
24451
        // op: fc
24452
        return 7;
24453
      case 1:
24454
        // op: Qn
24455
        return 17;
24456
      case 2:
24457
        // op: Rm
24458
        return 0;
24459
      }
24460
      break;
24461
    }
24462
    case ARM::LDC2L_POST:
24463
    case ARM::LDC2_POST:
24464
    case ARM::STC2L_POST:
24465
    case ARM::STC2_POST:
24466
    case ARM::t2LDC2L_POST:
24467
    case ARM::t2LDC2_POST:
24468
    case ARM::t2LDCL_POST:
24469
    case ARM::t2LDC_POST:
24470
    case ARM::t2STC2L_POST:
24471
    case ARM::t2STC2_POST:
24472
    case ARM::t2STCL_POST:
24473
    case ARM::t2STC_POST: {
24474
      switch (OpNum) {
24475
      case 3:
24476
        // op: offset
24477
        return 0;
24478
      case 2:
24479
        // op: addr
24480
        return 16;
24481
      case 0:
24482
        // op: cop
24483
        return 8;
24484
      case 1:
24485
        // op: CRd
24486
        return 12;
24487
      }
24488
      break;
24489
    }
24490
    case ARM::LDC2L_OPTION:
24491
    case ARM::LDC2_OPTION:
24492
    case ARM::STC2L_OPTION:
24493
    case ARM::STC2_OPTION:
24494
    case ARM::t2LDC2L_OPTION:
24495
    case ARM::t2LDC2_OPTION:
24496
    case ARM::t2LDCL_OPTION:
24497
    case ARM::t2LDC_OPTION:
24498
    case ARM::t2STC2L_OPTION:
24499
    case ARM::t2STC2_OPTION:
24500
    case ARM::t2STCL_OPTION:
24501
    case ARM::t2STC_OPTION: {
24502
      switch (OpNum) {
24503
      case 3:
24504
        // op: option
24505
        return 0;
24506
      case 2:
24507
        // op: addr
24508
        return 16;
24509
      case 0:
24510
        // op: cop
24511
        return 8;
24512
      case 1:
24513
        // op: CRd
24514
        return 12;
24515
      }
24516
      break;
24517
    }
24518
    case ARM::VADDD:
24519
    case ARM::VDIVD:
24520
    case ARM::VMULD:
24521
    case ARM::VNMULD:
24522
    case ARM::VSUBD: {
24523
      switch (OpNum) {
24524
      case 3:
24525
        // op: p
24526
        return 28;
24527
      case 0:
24528
        // op: Dd
24529
        return 12;
24530
      case 1:
24531
        // op: Dn
24532
        return 7;
24533
      case 2:
24534
        // op: Dm
24535
        return 0;
24536
      }
24537
      break;
24538
    }
24539
    case ARM::VLDRD:
24540
    case ARM::VSTRD: {
24541
      switch (OpNum) {
24542
      case 3:
24543
        // op: p
24544
        return 28;
24545
      case 0:
24546
        // op: Dd
24547
        return 12;
24548
      case 1:
24549
        // op: addr
24550
        return 0;
24551
      }
24552
      break;
24553
    }
24554
    case ARM::VMOVDRR: {
24555
      switch (OpNum) {
24556
      case 3:
24557
        // op: p
24558
        return 28;
24559
      case 0:
24560
        // op: Dm
24561
        return 0;
24562
      case 1:
24563
        // op: Rt
24564
        return 12;
24565
      case 2:
24566
        // op: Rt2
24567
        return 16;
24568
      }
24569
      break;
24570
    }
24571
    case ARM::SXTB:
24572
    case ARM::SXTB16:
24573
    case ARM::SXTH:
24574
    case ARM::UXTB:
24575
    case ARM::UXTB16:
24576
    case ARM::UXTH: {
24577
      switch (OpNum) {
24578
      case 3:
24579
        // op: p
24580
        return 28;
24581
      case 0:
24582
        // op: Rd
24583
        return 12;
24584
      case 1:
24585
        // op: Rm
24586
        return 0;
24587
      case 2:
24588
        // op: rot
24589
        return 10;
24590
      }
24591
      break;
24592
    }
24593
    case ARM::SEL: {
24594
      switch (OpNum) {
24595
      case 3:
24596
        // op: p
24597
        return 28;
24598
      case 0:
24599
        // op: Rd
24600
        return 12;
24601
      case 1:
24602
        // op: Rn
24603
        return 16;
24604
      case 2:
24605
        // op: Rm
24606
        return 0;
24607
      }
24608
      break;
24609
    }
24610
    case ARM::SSAT16:
24611
    case ARM::USAT16: {
24612
      switch (OpNum) {
24613
      case 3:
24614
        // op: p
24615
        return 28;
24616
      case 0:
24617
        // op: Rd
24618
        return 12;
24619
      case 1:
24620
        // op: sat_imm
24621
        return 16;
24622
      case 2:
24623
        // op: Rn
24624
        return 0;
24625
      }
24626
      break;
24627
    }
24628
    case ARM::MOVTi16: {
24629
      switch (OpNum) {
24630
      case 3:
24631
        // op: p
24632
        return 28;
24633
      case 0:
24634
        // op: Rd
24635
        return 12;
24636
      case 2:
24637
        // op: imm
24638
        return 0;
24639
      }
24640
      break;
24641
    }
24642
    case ARM::BFC: {
24643
      switch (OpNum) {
24644
      case 3:
24645
        // op: p
24646
        return 28;
24647
      case 0:
24648
        // op: Rd
24649
        return 12;
24650
      case 2:
24651
        // op: imm
24652
        return 7;
24653
      }
24654
      break;
24655
    }
24656
    case ARM::SDIV:
24657
    case ARM::SMMUL:
24658
    case ARM::SMMULR:
24659
    case ARM::UDIV:
24660
    case ARM::USAD8: {
24661
      switch (OpNum) {
24662
      case 3:
24663
        // op: p
24664
        return 28;
24665
      case 0:
24666
        // op: Rd
24667
        return 16;
24668
      case 1:
24669
        // op: Rn
24670
        return 0;
24671
      case 2:
24672
        // op: Rm
24673
        return 8;
24674
      }
24675
      break;
24676
    }
24677
    case ARM::CMNzrsi:
24678
    case ARM::CMPrsi:
24679
    case ARM::TEQrsi:
24680
    case ARM::TSTrsi: {
24681
      switch (OpNum) {
24682
      case 3:
24683
        // op: p
24684
        return 28;
24685
      case 0:
24686
        // op: Rn
24687
        return 16;
24688
      case 1:
24689
        // op: shift
24690
        return 0;
24691
      }
24692
      break;
24693
    }
24694
    case ARM::SWP:
24695
    case ARM::SWPB: {
24696
      switch (OpNum) {
24697
      case 3:
24698
        // op: p
24699
        return 28;
24700
      case 0:
24701
        // op: Rt
24702
        return 12;
24703
      case 1:
24704
        // op: Rt2
24705
        return 0;
24706
      case 2:
24707
        // op: addr
24708
        return 16;
24709
      }
24710
      break;
24711
    }
24712
    case ARM::LDRBi12:
24713
    case ARM::LDRcp:
24714
    case ARM::LDRi12:
24715
    case ARM::STRBi12:
24716
    case ARM::STRi12: {
24717
      switch (OpNum) {
24718
      case 3:
24719
        // op: p
24720
        return 28;
24721
      case 0:
24722
        // op: Rt
24723
        return 12;
24724
      case 1:
24725
        // op: addr
24726
        return 0;
24727
      }
24728
      break;
24729
    }
24730
    case ARM::VADDH:
24731
    case ARM::VADDS:
24732
    case ARM::VDIVH:
24733
    case ARM::VDIVS:
24734
    case ARM::VMULH:
24735
    case ARM::VMULS:
24736
    case ARM::VNMULH:
24737
    case ARM::VNMULS:
24738
    case ARM::VSUBH:
24739
    case ARM::VSUBS: {
24740
      switch (OpNum) {
24741
      case 3:
24742
        // op: p
24743
        return 28;
24744
      case 0:
24745
        // op: Sd
24746
        return 12;
24747
      case 1:
24748
        // op: Sn
24749
        return 7;
24750
      case 2:
24751
        // op: Sm
24752
        return 0;
24753
      }
24754
      break;
24755
    }
24756
    case ARM::VLDRH:
24757
    case ARM::VLDRS:
24758
    case ARM::VSTRH:
24759
    case ARM::VSTRS: {
24760
      switch (OpNum) {
24761
      case 3:
24762
        // op: p
24763
        return 28;
24764
      case 0:
24765
        // op: Sd
24766
        return 12;
24767
      case 1:
24768
        // op: addr
24769
        return 0;
24770
      }
24771
      break;
24772
    }
24773
    case ARM::BF16_VCVTB:
24774
    case ARM::BF16_VCVTT:
24775
    case ARM::VCVTBSH:
24776
    case ARM::VCVTTSH: {
24777
      switch (OpNum) {
24778
      case 3:
24779
        // op: p
24780
        return 28;
24781
      case 0:
24782
        // op: Sd
24783
        return 12;
24784
      case 2:
24785
        // op: Sm
24786
        return 0;
24787
      }
24788
      break;
24789
    }
24790
    case ARM::SMUAD:
24791
    case ARM::SMUADX:
24792
    case ARM::SMULBB:
24793
    case ARM::SMULBT:
24794
    case ARM::SMULTB:
24795
    case ARM::SMULTT:
24796
    case ARM::SMULWB:
24797
    case ARM::SMULWT:
24798
    case ARM::SMUSD:
24799
    case ARM::SMUSDX: {
24800
      switch (OpNum) {
24801
      case 3:
24802
        // op: p
24803
        return 28;
24804
      case 1:
24805
        // op: Rn
24806
        return 0;
24807
      case 2:
24808
        // op: Rm
24809
        return 8;
24810
      case 0:
24811
        // op: Rd
24812
        return 16;
24813
      }
24814
      break;
24815
    }
24816
    case ARM::QADD8:
24817
    case ARM::QADD16:
24818
    case ARM::QASX:
24819
    case ARM::QSAX:
24820
    case ARM::QSUB8:
24821
    case ARM::QSUB16:
24822
    case ARM::SADD8:
24823
    case ARM::SADD16:
24824
    case ARM::SASX:
24825
    case ARM::SHADD8:
24826
    case ARM::SHADD16:
24827
    case ARM::SHASX:
24828
    case ARM::SHSAX:
24829
    case ARM::SHSUB8:
24830
    case ARM::SHSUB16:
24831
    case ARM::SSAX:
24832
    case ARM::SSUB8:
24833
    case ARM::SSUB16:
24834
    case ARM::UADD8:
24835
    case ARM::UADD16:
24836
    case ARM::UASX:
24837
    case ARM::UHADD8:
24838
    case ARM::UHADD16:
24839
    case ARM::UHASX:
24840
    case ARM::UHSAX:
24841
    case ARM::UHSUB8:
24842
    case ARM::UHSUB16:
24843
    case ARM::UQADD8:
24844
    case ARM::UQADD16:
24845
    case ARM::UQASX:
24846
    case ARM::UQSAX:
24847
    case ARM::UQSUB8:
24848
    case ARM::UQSUB16:
24849
    case ARM::USAX:
24850
    case ARM::USUB8:
24851
    case ARM::USUB16: {
24852
      switch (OpNum) {
24853
      case 3:
24854
        // op: p
24855
        return 28;
24856
      case 1:
24857
        // op: Rn
24858
        return 16;
24859
      case 0:
24860
        // op: Rd
24861
        return 12;
24862
      case 2:
24863
        // op: Rm
24864
        return 0;
24865
      }
24866
      break;
24867
    }
24868
    case ARM::STLEX:
24869
    case ARM::STLEXB:
24870
    case ARM::STLEXD:
24871
    case ARM::STLEXH:
24872
    case ARM::STREX:
24873
    case ARM::STREXB:
24874
    case ARM::STREXD:
24875
    case ARM::STREXH: {
24876
      switch (OpNum) {
24877
      case 3:
24878
        // op: p
24879
        return 28;
24880
      case 1:
24881
        // op: Rt
24882
        return 0;
24883
      case 2:
24884
        // op: addr
24885
        return 16;
24886
      case 0:
24887
        // op: Rd
24888
        return 12;
24889
      }
24890
      break;
24891
    }
24892
    case ARM::VLDR_FPCXTNS_pre:
24893
    case ARM::VLDR_FPCXTS_pre:
24894
    case ARM::VLDR_FPSCR_NZCVQC_pre:
24895
    case ARM::VLDR_FPSCR_pre:
24896
    case ARM::VLDR_P0_off:
24897
    case ARM::VLDR_VPR_pre:
24898
    case ARM::VSTR_FPCXTNS_pre:
24899
    case ARM::VSTR_FPCXTS_pre:
24900
    case ARM::VSTR_FPSCR_NZCVQC_pre:
24901
    case ARM::VSTR_FPSCR_pre:
24902
    case ARM::VSTR_P0_off:
24903
    case ARM::VSTR_VPR_pre: {
24904
      switch (OpNum) {
24905
      case 3:
24906
        // op: p
24907
        return 28;
24908
      case 1:
24909
        // op: addr
24910
        return 0;
24911
      }
24912
      break;
24913
    }
24914
    case ARM::VMOVRRD: {
24915
      switch (OpNum) {
24916
      case 3:
24917
        // op: p
24918
        return 28;
24919
      case 2:
24920
        // op: Dm
24921
        return 0;
24922
      case 0:
24923
        // op: Rt
24924
        return 12;
24925
      case 1:
24926
        // op: Rt2
24927
        return 16;
24928
      }
24929
      break;
24930
    }
24931
    case ARM::VCVTBDH:
24932
    case ARM::VCVTTDH: {
24933
      switch (OpNum) {
24934
      case 3:
24935
        // op: p
24936
        return 28;
24937
      case 2:
24938
        // op: Dm
24939
        return 0;
24940
      case 0:
24941
        // op: Sd
24942
        return 12;
24943
      }
24944
      break;
24945
    }
24946
    case ARM::QADD:
24947
    case ARM::QDADD:
24948
    case ARM::QDSUB:
24949
    case ARM::QSUB: {
24950
      switch (OpNum) {
24951
      case 3:
24952
        // op: p
24953
        return 28;
24954
      case 2:
24955
        // op: Rn
24956
        return 16;
24957
      case 0:
24958
        // op: Rd
24959
        return 12;
24960
      case 1:
24961
        // op: Rm
24962
        return 0;
24963
      }
24964
      break;
24965
    }
24966
    case ARM::VLDR_FPCXTNS_post:
24967
    case ARM::VLDR_FPCXTS_post:
24968
    case ARM::VLDR_FPSCR_NZCVQC_post:
24969
    case ARM::VLDR_FPSCR_post:
24970
    case ARM::VLDR_VPR_post:
24971
    case ARM::VSTR_FPCXTNS_post:
24972
    case ARM::VSTR_FPCXTS_post:
24973
    case ARM::VSTR_FPSCR_NZCVQC_post:
24974
    case ARM::VSTR_FPSCR_post:
24975
    case ARM::VSTR_VPR_post: {
24976
      switch (OpNum) {
24977
      case 3:
24978
        // op: p
24979
        return 28;
24980
      case 2:
24981
        // op: addr
24982
        return 0;
24983
      case 1:
24984
        // op: Rn
24985
        return 16;
24986
      }
24987
      break;
24988
    }
24989
    case ARM::VSHTOD:
24990
    case ARM::VSHTOH:
24991
    case ARM::VSHTOS:
24992
    case ARM::VSLTOD:
24993
    case ARM::VSLTOH:
24994
    case ARM::VSLTOS:
24995
    case ARM::VTOSHD:
24996
    case ARM::VTOSHH:
24997
    case ARM::VTOSHS:
24998
    case ARM::VTOSLD:
24999
    case ARM::VTOSLH:
25000
    case ARM::VTOSLS:
25001
    case ARM::VTOUHD:
25002
    case ARM::VTOUHH:
25003
    case ARM::VTOUHS:
25004
    case ARM::VTOULD:
25005
    case ARM::VTOULH:
25006
    case ARM::VTOULS:
25007
    case ARM::VUHTOD:
25008
    case ARM::VUHTOH:
25009
    case ARM::VUHTOS:
25010
    case ARM::VULTOD:
25011
    case ARM::VULTOH:
25012
    case ARM::VULTOS: {
25013
      switch (OpNum) {
25014
      case 3:
25015
        // op: p
25016
        return 28;
25017
      case 2:
25018
        // op: fbits
25019
        return 0;
25020
      case 0:
25021
        // op: dst
25022
        return 12;
25023
      }
25024
      break;
25025
    }
25026
    case ARM::ADCrr:
25027
    case ARM::ADDrr:
25028
    case ARM::ANDrr:
25029
    case ARM::BICrr:
25030
    case ARM::EORrr:
25031
    case ARM::ORRrr:
25032
    case ARM::RSBrr:
25033
    case ARM::RSCrr:
25034
    case ARM::SBCrr:
25035
    case ARM::SUBrr: {
25036
      switch (OpNum) {
25037
      case 3:
25038
        // op: p
25039
        return 28;
25040
      case 5:
25041
        // op: s
25042
        return 20;
25043
      case 0:
25044
        // op: Rd
25045
        return 12;
25046
      case 1:
25047
        // op: Rn
25048
        return 16;
25049
      case 2:
25050
        // op: Rm
25051
        return 0;
25052
      }
25053
      break;
25054
    }
25055
    case ARM::ADCri:
25056
    case ARM::ADDri:
25057
    case ARM::ANDri:
25058
    case ARM::BICri:
25059
    case ARM::EORri:
25060
    case ARM::ORRri:
25061
    case ARM::RSBri:
25062
    case ARM::RSCri:
25063
    case ARM::SBCri:
25064
    case ARM::SUBri: {
25065
      switch (OpNum) {
25066
      case 3:
25067
        // op: p
25068
        return 28;
25069
      case 5:
25070
        // op: s
25071
        return 20;
25072
      case 0:
25073
        // op: Rd
25074
        return 12;
25075
      case 1:
25076
        // op: Rn
25077
        return 16;
25078
      case 2:
25079
        // op: imm
25080
        return 0;
25081
      }
25082
      break;
25083
    }
25084
    case ARM::MVNsi: {
25085
      switch (OpNum) {
25086
      case 3:
25087
        // op: p
25088
        return 28;
25089
      case 5:
25090
        // op: s
25091
        return 20;
25092
      case 0:
25093
        // op: Rd
25094
        return 12;
25095
      case 1:
25096
        // op: shift
25097
        return 0;
25098
      }
25099
      break;
25100
    }
25101
    case ARM::MOVsi: {
25102
      switch (OpNum) {
25103
      case 3:
25104
        // op: p
25105
        return 28;
25106
      case 5:
25107
        // op: s
25108
        return 20;
25109
      case 0:
25110
        // op: Rd
25111
        return 12;
25112
      case 1:
25113
        // op: src
25114
        return 0;
25115
      }
25116
      break;
25117
    }
25118
    case ARM::MUL: {
25119
      switch (OpNum) {
25120
      case 3:
25121
        // op: p
25122
        return 28;
25123
      case 5:
25124
        // op: s
25125
        return 20;
25126
      case 0:
25127
        // op: Rd
25128
        return 16;
25129
      case 2:
25130
        // op: Rm
25131
        return 8;
25132
      case 1:
25133
        // op: Rn
25134
        return 0;
25135
      }
25136
      break;
25137
    }
25138
    case ARM::MVE_VADDLVs32acc:
25139
    case ARM::MVE_VADDLVu32acc: {
25140
      switch (OpNum) {
25141
      case 4:
25142
        // op: Qm
25143
        return 1;
25144
      case 0:
25145
        // op: RdaLo
25146
        return 13;
25147
      case 1:
25148
        // op: RdaHi
25149
        return 20;
25150
      }
25151
      break;
25152
    }
25153
    case ARM::VST1LNd8_UPD: {
25154
      switch (OpNum) {
25155
      case 4:
25156
        // op: Vd
25157
        return 12;
25158
      case 1:
25159
        // op: Rn
25160
        return 16;
25161
      case 3:
25162
        // op: Rm
25163
        return 0;
25164
      case 5:
25165
        // op: lane
25166
        return 5;
25167
      }
25168
      break;
25169
    }
25170
    case ARM::VST3LNd8_UPD: {
25171
      switch (OpNum) {
25172
      case 4:
25173
        // op: Vd
25174
        return 12;
25175
      case 1:
25176
        // op: Rn
25177
        return 16;
25178
      case 3:
25179
        // op: Rm
25180
        return 0;
25181
      case 7:
25182
        // op: lane
25183
        return 5;
25184
      }
25185
      break;
25186
    }
25187
    case ARM::VST3LNd16_UPD:
25188
    case ARM::VST3LNq16_UPD: {
25189
      switch (OpNum) {
25190
      case 4:
25191
        // op: Vd
25192
        return 12;
25193
      case 1:
25194
        // op: Rn
25195
        return 16;
25196
      case 3:
25197
        // op: Rm
25198
        return 0;
25199
      case 7:
25200
        // op: lane
25201
        return 6;
25202
      }
25203
      break;
25204
    }
25205
    case ARM::VST3LNd32_UPD:
25206
    case ARM::VST3LNq32_UPD: {
25207
      switch (OpNum) {
25208
      case 4:
25209
        // op: Vd
25210
        return 12;
25211
      case 1:
25212
        // op: Rn
25213
        return 16;
25214
      case 3:
25215
        // op: Rm
25216
        return 0;
25217
      case 7:
25218
        // op: lane
25219
        return 7;
25220
      }
25221
      break;
25222
    }
25223
    case ARM::VST1LNd16_UPD: {
25224
      switch (OpNum) {
25225
      case 4:
25226
        // op: Vd
25227
        return 12;
25228
      case 1:
25229
        // op: Rn
25230
        return 4;
25231
      case 3:
25232
        // op: Rm
25233
        return 0;
25234
      case 5:
25235
        // op: lane
25236
        return 6;
25237
      }
25238
      break;
25239
    }
25240
    case ARM::VST1LNd32_UPD: {
25241
      switch (OpNum) {
25242
      case 4:
25243
        // op: Vd
25244
        return 12;
25245
      case 1:
25246
        // op: Rn
25247
        return 4;
25248
      case 3:
25249
        // op: Rm
25250
        return 0;
25251
      case 5:
25252
        // op: lane
25253
        return 7;
25254
      }
25255
      break;
25256
    }
25257
    case ARM::VST2LNd8_UPD: {
25258
      switch (OpNum) {
25259
      case 4:
25260
        // op: Vd
25261
        return 12;
25262
      case 1:
25263
        // op: Rn
25264
        return 4;
25265
      case 3:
25266
        // op: Rm
25267
        return 0;
25268
      case 6:
25269
        // op: lane
25270
        return 5;
25271
      }
25272
      break;
25273
    }
25274
    case ARM::VST2LNd16_UPD:
25275
    case ARM::VST2LNq16_UPD: {
25276
      switch (OpNum) {
25277
      case 4:
25278
        // op: Vd
25279
        return 12;
25280
      case 1:
25281
        // op: Rn
25282
        return 4;
25283
      case 3:
25284
        // op: Rm
25285
        return 0;
25286
      case 6:
25287
        // op: lane
25288
        return 6;
25289
      }
25290
      break;
25291
    }
25292
    case ARM::VST2LNd32_UPD:
25293
    case ARM::VST2LNq32_UPD: {
25294
      switch (OpNum) {
25295
      case 4:
25296
        // op: Vd
25297
        return 12;
25298
      case 1:
25299
        // op: Rn
25300
        return 4;
25301
      case 3:
25302
        // op: Rm
25303
        return 0;
25304
      case 6:
25305
        // op: lane
25306
        return 7;
25307
      }
25308
      break;
25309
    }
25310
    case ARM::VST4LNd8_UPD: {
25311
      switch (OpNum) {
25312
      case 4:
25313
        // op: Vd
25314
        return 12;
25315
      case 1:
25316
        // op: Rn
25317
        return 4;
25318
      case 3:
25319
        // op: Rm
25320
        return 0;
25321
      case 8:
25322
        // op: lane
25323
        return 5;
25324
      }
25325
      break;
25326
    }
25327
    case ARM::VST4LNd16_UPD:
25328
    case ARM::VST4LNq16_UPD: {
25329
      switch (OpNum) {
25330
      case 4:
25331
        // op: Vd
25332
        return 12;
25333
      case 1:
25334
        // op: Rn
25335
        return 4;
25336
      case 3:
25337
        // op: Rm
25338
        return 0;
25339
      case 8:
25340
        // op: lane
25341
        return 6;
25342
      }
25343
      break;
25344
    }
25345
    case ARM::VST4LNd32_UPD:
25346
    case ARM::VST4LNq32_UPD: {
25347
      switch (OpNum) {
25348
      case 4:
25349
        // op: Vd
25350
        return 12;
25351
      case 1:
25352
        // op: Rn
25353
        return 4;
25354
      case 3:
25355
        // op: Rm
25356
        return 0;
25357
      case 8:
25358
        // op: lane
25359
        return 7;
25360
      }
25361
      break;
25362
    }
25363
    case ARM::VST1d8Qwb_register:
25364
    case ARM::VST1d8Twb_register:
25365
    case ARM::VST1d8wb_register:
25366
    case ARM::VST1d16Qwb_register:
25367
    case ARM::VST1d16Twb_register:
25368
    case ARM::VST1d16wb_register:
25369
    case ARM::VST1d32Qwb_register:
25370
    case ARM::VST1d32Twb_register:
25371
    case ARM::VST1d32wb_register:
25372
    case ARM::VST1d64Qwb_register:
25373
    case ARM::VST1d64Twb_register:
25374
    case ARM::VST1d64wb_register:
25375
    case ARM::VST1q8wb_register:
25376
    case ARM::VST1q16wb_register:
25377
    case ARM::VST1q32wb_register:
25378
    case ARM::VST1q64wb_register:
25379
    case ARM::VST2b8wb_register:
25380
    case ARM::VST2b16wb_register:
25381
    case ARM::VST2b32wb_register:
25382
    case ARM::VST2d8wb_register:
25383
    case ARM::VST2d16wb_register:
25384
    case ARM::VST2d32wb_register:
25385
    case ARM::VST2q8wb_register:
25386
    case ARM::VST2q16wb_register:
25387
    case ARM::VST2q32wb_register:
25388
    case ARM::VST3d8_UPD:
25389
    case ARM::VST3d16_UPD:
25390
    case ARM::VST3d32_UPD:
25391
    case ARM::VST3q8_UPD:
25392
    case ARM::VST3q16_UPD:
25393
    case ARM::VST3q32_UPD:
25394
    case ARM::VST4d8_UPD:
25395
    case ARM::VST4d16_UPD:
25396
    case ARM::VST4d32_UPD:
25397
    case ARM::VST4q8_UPD:
25398
    case ARM::VST4q16_UPD:
25399
    case ARM::VST4q32_UPD: {
25400
      switch (OpNum) {
25401
      case 4:
25402
        // op: Vd
25403
        return 12;
25404
      case 1:
25405
        // op: Rn
25406
        return 4;
25407
      case 3:
25408
        // op: Rm
25409
        return 0;
25410
      }
25411
      break;
25412
    }
25413
    case ARM::MVE_VSHLC: {
25414
      switch (OpNum) {
25415
      case 4:
25416
        // op: imm
25417
        return 16;
25418
      case 1:
25419
        // op: Qd
25420
        return 13;
25421
      case 0:
25422
        // op: RdmDest
25423
        return 0;
25424
      }
25425
      break;
25426
    }
25427
    case ARM::VFMAD:
25428
    case ARM::VFMSD:
25429
    case ARM::VFNMAD:
25430
    case ARM::VFNMSD:
25431
    case ARM::VMLAD:
25432
    case ARM::VMLSD:
25433
    case ARM::VNMLAD:
25434
    case ARM::VNMLSD: {
25435
      switch (OpNum) {
25436
      case 4:
25437
        // op: p
25438
        return 28;
25439
      case 0:
25440
        // op: Dd
25441
        return 12;
25442
      case 2:
25443
        // op: Dn
25444
        return 7;
25445
      case 3:
25446
        // op: Dm
25447
        return 0;
25448
      }
25449
      break;
25450
    }
25451
    case ARM::SBFX:
25452
    case ARM::UBFX: {
25453
      switch (OpNum) {
25454
      case 4:
25455
        // op: p
25456
        return 28;
25457
      case 0:
25458
        // op: Rd
25459
        return 12;
25460
      case 1:
25461
        // op: Rn
25462
        return 0;
25463
      case 2:
25464
        // op: lsb
25465
        return 7;
25466
      case 3:
25467
        // op: width
25468
        return 16;
25469
      }
25470
      break;
25471
    }
25472
    case ARM::PKHBT:
25473
    case ARM::PKHTB: {
25474
      switch (OpNum) {
25475
      case 4:
25476
        // op: p
25477
        return 28;
25478
      case 0:
25479
        // op: Rd
25480
        return 12;
25481
      case 1:
25482
        // op: Rn
25483
        return 16;
25484
      case 2:
25485
        // op: Rm
25486
        return 0;
25487
      case 3:
25488
        // op: sh
25489
        return 7;
25490
      }
25491
      break;
25492
    }
25493
    case ARM::SSAT:
25494
    case ARM::USAT: {
25495
      switch (OpNum) {
25496
      case 4:
25497
        // op: p
25498
        return 28;
25499
      case 0:
25500
        // op: Rd
25501
        return 12;
25502
      case 1:
25503
        // op: sat_imm
25504
        return 16;
25505
      case 2:
25506
        // op: Rn
25507
        return 0;
25508
      case 3:
25509
        // op: sh
25510
        return 6;
25511
      }
25512
      break;
25513
    }
25514
    case ARM::SXTAB:
25515
    case ARM::SXTAB16:
25516
    case ARM::SXTAH:
25517
    case ARM::UXTAB:
25518
    case ARM::UXTAB16:
25519
    case ARM::UXTAH: {
25520
      switch (OpNum) {
25521
      case 4:
25522
        // op: p
25523
        return 28;
25524
      case 0:
25525
        // op: Rd
25526
        return 12;
25527
      case 2:
25528
        // op: Rm
25529
        return 0;
25530
      case 1:
25531
        // op: Rn
25532
        return 16;
25533
      case 3:
25534
        // op: rot
25535
        return 10;
25536
      }
25537
      break;
25538
    }
25539
    case ARM::BFI: {
25540
      switch (OpNum) {
25541
      case 4:
25542
        // op: p
25543
        return 28;
25544
      case 0:
25545
        // op: Rd
25546
        return 12;
25547
      case 2:
25548
        // op: Rn
25549
        return 0;
25550
      case 3:
25551
        // op: imm
25552
        return 7;
25553
      }
25554
      break;
25555
    }
25556
    case ARM::SMMLA:
25557
    case ARM::SMMLAR:
25558
    case ARM::SMMLS:
25559
    case ARM::SMMLSR:
25560
    case ARM::USADA8: {
25561
      switch (OpNum) {
25562
      case 4:
25563
        // op: p
25564
        return 28;
25565
      case 0:
25566
        // op: Rd
25567
        return 16;
25568
      case 1:
25569
        // op: Rn
25570
        return 0;
25571
      case 2:
25572
        // op: Rm
25573
        return 8;
25574
      case 3:
25575
        // op: Ra
25576
        return 12;
25577
      }
25578
      break;
25579
    }
25580
    case ARM::MLS: {
25581
      switch (OpNum) {
25582
      case 4:
25583
        // op: p
25584
        return 28;
25585
      case 0:
25586
        // op: Rd
25587
        return 16;
25588
      case 2:
25589
        // op: Rm
25590
        return 8;
25591
      case 1:
25592
        // op: Rn
25593
        return 0;
25594
      case 3:
25595
        // op: Ra
25596
        return 12;
25597
      }
25598
      break;
25599
    }
25600
    case ARM::CMNzrsr:
25601
    case ARM::CMPrsr:
25602
    case ARM::TEQrsr:
25603
    case ARM::TSTrsr: {
25604
      switch (OpNum) {
25605
      case 4:
25606
        // op: p
25607
        return 28;
25608
      case 0:
25609
        // op: Rn
25610
        return 16;
25611
      case 1:
25612
        // op: shift
25613
        return 0;
25614
      }
25615
      break;
25616
    }
25617
    case ARM::LDRBrs:
25618
    case ARM::LDRrs:
25619
    case ARM::STRBrs:
25620
    case ARM::STRrs: {
25621
      switch (OpNum) {
25622
      case 4:
25623
        // op: p
25624
        return 28;
25625
      case 0:
25626
        // op: Rt
25627
        return 12;
25628
      case 1:
25629
        // op: shift
25630
        return 0;
25631
      }
25632
      break;
25633
    }
25634
    case ARM::LDRB_PRE_IMM:
25635
    case ARM::LDR_PRE_IMM: {
25636
      switch (OpNum) {
25637
      case 4:
25638
        // op: p
25639
        return 28;
25640
      case 0:
25641
        // op: Rt
25642
        return 12;
25643
      case 2:
25644
        // op: addr
25645
        return 0;
25646
      }
25647
      break;
25648
    }
25649
    case ARM::VFMAH:
25650
    case ARM::VFMAS:
25651
    case ARM::VFMSH:
25652
    case ARM::VFMSS:
25653
    case ARM::VFNMAH:
25654
    case ARM::VFNMAS:
25655
    case ARM::VFNMSH:
25656
    case ARM::VFNMSS:
25657
    case ARM::VMLAH:
25658
    case ARM::VMLAS:
25659
    case ARM::VMLSH:
25660
    case ARM::VMLSS:
25661
    case ARM::VNMLAH:
25662
    case ARM::VNMLAS:
25663
    case ARM::VNMLSH:
25664
    case ARM::VNMLSS: {
25665
      switch (OpNum) {
25666
      case 4:
25667
        // op: p
25668
        return 28;
25669
      case 0:
25670
        // op: Sd
25671
        return 12;
25672
      case 2:
25673
        // op: Sn
25674
        return 7;
25675
      case 3:
25676
        // op: Sm
25677
        return 0;
25678
      }
25679
      break;
25680
    }
25681
    case ARM::VMOVSRR: {
25682
      switch (OpNum) {
25683
      case 4:
25684
        // op: p
25685
        return 28;
25686
      case 0:
25687
        // op: dst1
25688
        return 0;
25689
      case 2:
25690
        // op: src1
25691
        return 12;
25692
      case 3:
25693
        // op: src2
25694
        return 16;
25695
      }
25696
      break;
25697
    }
25698
    case ARM::SMLABB:
25699
    case ARM::SMLABT:
25700
    case ARM::SMLATB:
25701
    case ARM::SMLATT:
25702
    case ARM::SMLAWB:
25703
    case ARM::SMLAWT: {
25704
      switch (OpNum) {
25705
      case 4:
25706
        // op: p
25707
        return 28;
25708
      case 1:
25709
        // op: Rn
25710
        return 0;
25711
      case 2:
25712
        // op: Rm
25713
        return 8;
25714
      case 0:
25715
        // op: Rd
25716
        return 16;
25717
      case 3:
25718
        // op: Ra
25719
        return 12;
25720
      }
25721
      break;
25722
    }
25723
    case ARM::SMLAD:
25724
    case ARM::SMLADX:
25725
    case ARM::SMLSD:
25726
    case ARM::SMLSDX: {
25727
      switch (OpNum) {
25728
      case 4:
25729
        // op: p
25730
        return 28;
25731
      case 1:
25732
        // op: Rn
25733
        return 0;
25734
      case 2:
25735
        // op: Rm
25736
        return 8;
25737
      case 3:
25738
        // op: Ra
25739
        return 12;
25740
      case 0:
25741
        // op: Rd
25742
        return 16;
25743
      }
25744
      break;
25745
    }
25746
    case ARM::STRB_PRE_IMM:
25747
    case ARM::STR_PRE_IMM: {
25748
      switch (OpNum) {
25749
      case 4:
25750
        // op: p
25751
        return 28;
25752
      case 1:
25753
        // op: Rt
25754
        return 12;
25755
      case 2:
25756
        // op: addr
25757
        return 0;
25758
      }
25759
      break;
25760
    }
25761
    case ARM::LDRH:
25762
    case ARM::LDRSB:
25763
    case ARM::LDRSH:
25764
    case ARM::STRH: {
25765
      switch (OpNum) {
25766
      case 4:
25767
        // op: p
25768
        return 28;
25769
      case 1:
25770
        // op: addr
25771
        return 0;
25772
      case 0:
25773
        // op: Rt
25774
        return 12;
25775
      }
25776
      break;
25777
    }
25778
    case ARM::LDCL_OFFSET:
25779
    case ARM::LDCL_PRE:
25780
    case ARM::LDC_OFFSET:
25781
    case ARM::LDC_PRE:
25782
    case ARM::STCL_OFFSET:
25783
    case ARM::STCL_PRE:
25784
    case ARM::STC_OFFSET:
25785
    case ARM::STC_PRE: {
25786
      switch (OpNum) {
25787
      case 4:
25788
        // op: p
25789
        return 28;
25790
      case 2:
25791
        // op: addr
25792
        return 0;
25793
      case 0:
25794
        // op: cop
25795
        return 8;
25796
      case 1:
25797
        // op: CRd
25798
        return 12;
25799
      }
25800
      break;
25801
    }
25802
    case ARM::VLDR_P0_pre:
25803
    case ARM::VSTR_P0_pre: {
25804
      switch (OpNum) {
25805
      case 4:
25806
        // op: p
25807
        return 28;
25808
      case 2:
25809
        // op: addr
25810
        return 0;
25811
      }
25812
      break;
25813
    }
25814
    case ARM::LDRHTi:
25815
    case ARM::LDRSBTi:
25816
    case ARM::LDRSHTi: {
25817
      switch (OpNum) {
25818
      case 4:
25819
        // op: p
25820
        return 28;
25821
      case 2:
25822
        // op: addr
25823
        return 16;
25824
      case 0:
25825
        // op: Rt
25826
        return 12;
25827
      case 3:
25828
        // op: offset
25829
        return 0;
25830
      }
25831
      break;
25832
    }
25833
    case ARM::STRHTi: {
25834
      switch (OpNum) {
25835
      case 4:
25836
        // op: p
25837
        return 28;
25838
      case 2:
25839
        // op: addr
25840
        return 16;
25841
      case 1:
25842
        // op: Rt
25843
        return 12;
25844
      case 3:
25845
        // op: offset
25846
        return 0;
25847
      }
25848
      break;
25849
    }
25850
    case ARM::VMOVRRS: {
25851
      switch (OpNum) {
25852
      case 4:
25853
        // op: p
25854
        return 28;
25855
      case 2:
25856
        // op: src1
25857
        return 0;
25858
      case 0:
25859
        // op: Rt
25860
        return 12;
25861
      case 1:
25862
        // op: Rt2
25863
        return 16;
25864
      }
25865
      break;
25866
    }
25867
    case ARM::VLDR_P0_post:
25868
    case ARM::VSTR_P0_post: {
25869
      switch (OpNum) {
25870
      case 4:
25871
        // op: p
25872
        return 28;
25873
      case 3:
25874
        // op: addr
25875
        return 0;
25876
      case 2:
25877
        // op: Rn
25878
        return 16;
25879
      }
25880
      break;
25881
    }
25882
    case ARM::LDCL_POST:
25883
    case ARM::LDC_POST:
25884
    case ARM::STCL_POST:
25885
    case ARM::STC_POST: {
25886
      switch (OpNum) {
25887
      case 4:
25888
        // op: p
25889
        return 28;
25890
      case 3:
25891
        // op: offset
25892
        return 0;
25893
      case 2:
25894
        // op: addr
25895
        return 16;
25896
      case 0:
25897
        // op: cop
25898
        return 8;
25899
      case 1:
25900
        // op: CRd
25901
        return 12;
25902
      }
25903
      break;
25904
    }
25905
    case ARM::LDCL_OPTION:
25906
    case ARM::LDC_OPTION:
25907
    case ARM::STCL_OPTION:
25908
    case ARM::STC_OPTION: {
25909
      switch (OpNum) {
25910
      case 4:
25911
        // op: p
25912
        return 28;
25913
      case 3:
25914
        // op: option
25915
        return 0;
25916
      case 2:
25917
        // op: addr
25918
        return 16;
25919
      case 0:
25920
        // op: cop
25921
        return 8;
25922
      case 1:
25923
        // op: CRd
25924
        return 12;
25925
      }
25926
      break;
25927
    }
25928
    case ARM::ADCrsi:
25929
    case ARM::ADDrsi:
25930
    case ARM::ANDrsi:
25931
    case ARM::BICrsi:
25932
    case ARM::EORrsi:
25933
    case ARM::ORRrsi:
25934
    case ARM::RSBrsi:
25935
    case ARM::RSCrsi:
25936
    case ARM::SBCrsi:
25937
    case ARM::SUBrsi: {
25938
      switch (OpNum) {
25939
      case 4:
25940
        // op: p
25941
        return 28;
25942
      case 6:
25943
        // op: s
25944
        return 20;
25945
      case 0:
25946
        // op: Rd
25947
        return 12;
25948
      case 1:
25949
        // op: Rn
25950
        return 16;
25951
      case 2:
25952
        // op: shift
25953
        return 0;
25954
      }
25955
      break;
25956
    }
25957
    case ARM::MVNsr: {
25958
      switch (OpNum) {
25959
      case 4:
25960
        // op: p
25961
        return 28;
25962
      case 6:
25963
        // op: s
25964
        return 20;
25965
      case 0:
25966
        // op: Rd
25967
        return 12;
25968
      case 1:
25969
        // op: shift
25970
        return 0;
25971
      }
25972
      break;
25973
    }
25974
    case ARM::MOVsr: {
25975
      switch (OpNum) {
25976
      case 4:
25977
        // op: p
25978
        return 28;
25979
      case 6:
25980
        // op: s
25981
        return 20;
25982
      case 0:
25983
        // op: Rd
25984
        return 12;
25985
      case 1:
25986
        // op: src
25987
        return 0;
25988
      }
25989
      break;
25990
    }
25991
    case ARM::MLA: {
25992
      switch (OpNum) {
25993
      case 4:
25994
        // op: p
25995
        return 28;
25996
      case 6:
25997
        // op: s
25998
        return 20;
25999
      case 0:
26000
        // op: Rd
26001
        return 16;
26002
      case 2:
26003
        // op: Rm
26004
        return 8;
26005
      case 1:
26006
        // op: Rn
26007
        return 0;
26008
      case 3:
26009
        // op: Ra
26010
        return 12;
26011
      }
26012
      break;
26013
    }
26014
    case ARM::SMULL:
26015
    case ARM::UMULL: {
26016
      switch (OpNum) {
26017
      case 4:
26018
        // op: p
26019
        return 28;
26020
      case 6:
26021
        // op: s
26022
        return 20;
26023
      case 0:
26024
        // op: RdLo
26025
        return 12;
26026
      case 1:
26027
        // op: RdHi
26028
        return 16;
26029
      case 3:
26030
        // op: Rm
26031
        return 8;
26032
      case 2:
26033
        // op: Rn
26034
        return 0;
26035
      }
26036
      break;
26037
    }
26038
    case ARM::t2MOVr:
26039
    case ARM::t2MVNr:
26040
    case ARM::t2RRX: {
26041
      switch (OpNum) {
26042
      case 4:
26043
        // op: s
26044
        return 20;
26045
      case 0:
26046
        // op: Rd
26047
        return 8;
26048
      case 1:
26049
        // op: Rm
26050
        return 0;
26051
      }
26052
      break;
26053
    }
26054
    case ARM::t2MOVi:
26055
    case ARM::t2MVNi: {
26056
      switch (OpNum) {
26057
      case 4:
26058
        // op: s
26059
        return 20;
26060
      case 0:
26061
        // op: Rd
26062
        return 8;
26063
      case 1:
26064
        // op: imm
26065
        return 0;
26066
      }
26067
      break;
26068
    }
26069
    case ARM::MRRC: {
26070
      switch (OpNum) {
26071
      case 5:
26072
        // op: p
26073
        return 28;
26074
      case 0:
26075
        // op: Rt
26076
        return 12;
26077
      case 1:
26078
        // op: Rt2
26079
        return 16;
26080
      case 2:
26081
        // op: cop
26082
        return 8;
26083
      case 3:
26084
        // op: opc1
26085
        return 4;
26086
      case 4:
26087
        // op: CRm
26088
        return 0;
26089
      }
26090
      break;
26091
    }
26092
    case ARM::LDRB_PRE_REG:
26093
    case ARM::LDRH_PRE:
26094
    case ARM::LDRSB_PRE:
26095
    case ARM::LDRSH_PRE:
26096
    case ARM::LDR_PRE_REG: {
26097
      switch (OpNum) {
26098
      case 5:
26099
        // op: p
26100
        return 28;
26101
      case 0:
26102
        // op: Rt
26103
        return 12;
26104
      case 2:
26105
        // op: addr
26106
        return 0;
26107
      }
26108
      break;
26109
    }
26110
    case ARM::LDRBT_POST_IMM:
26111
    case ARM::LDRBT_POST_REG:
26112
    case ARM::LDRB_POST_IMM:
26113
    case ARM::LDRB_POST_REG:
26114
    case ARM::LDRH_POST:
26115
    case ARM::LDRSB_POST:
26116
    case ARM::LDRSH_POST:
26117
    case ARM::LDRT_POST_IMM:
26118
    case ARM::LDRT_POST_REG:
26119
    case ARM::LDR_POST_IMM:
26120
    case ARM::LDR_POST_REG: {
26121
      switch (OpNum) {
26122
      case 5:
26123
        // op: p
26124
        return 28;
26125
      case 0:
26126
        // op: Rt
26127
        return 12;
26128
      case 3:
26129
        // op: offset
26130
        return 0;
26131
      case 2:
26132
        // op: addr
26133
        return 16;
26134
      }
26135
      break;
26136
    }
26137
    case ARM::STRB_PRE_REG:
26138
    case ARM::STRH_PRE:
26139
    case ARM::STR_PRE_REG: {
26140
      switch (OpNum) {
26141
      case 5:
26142
        // op: p
26143
        return 28;
26144
      case 1:
26145
        // op: Rt
26146
        return 12;
26147
      case 2:
26148
        // op: addr
26149
        return 0;
26150
      }
26151
      break;
26152
    }
26153
    case ARM::STRBT_POST_IMM:
26154
    case ARM::STRBT_POST_REG:
26155
    case ARM::STRB_POST_IMM:
26156
    case ARM::STRB_POST_REG:
26157
    case ARM::STRH_POST:
26158
    case ARM::STRT_POST_IMM:
26159
    case ARM::STRT_POST_REG:
26160
    case ARM::STR_POST_IMM:
26161
    case ARM::STR_POST_REG: {
26162
      switch (OpNum) {
26163
      case 5:
26164
        // op: p
26165
        return 28;
26166
      case 1:
26167
        // op: Rt
26168
        return 12;
26169
      case 3:
26170
        // op: offset
26171
        return 0;
26172
      case 2:
26173
        // op: addr
26174
        return 16;
26175
      }
26176
      break;
26177
    }
26178
    case ARM::MCRR: {
26179
      switch (OpNum) {
26180
      case 5:
26181
        // op: p
26182
        return 28;
26183
      case 2:
26184
        // op: Rt
26185
        return 12;
26186
      case 3:
26187
        // op: Rt2
26188
        return 16;
26189
      case 0:
26190
        // op: cop
26191
        return 8;
26192
      case 1:
26193
        // op: opc1
26194
        return 4;
26195
      case 4:
26196
        // op: CRm
26197
        return 0;
26198
      }
26199
      break;
26200
    }
26201
    case ARM::LDRD:
26202
    case ARM::STRD: {
26203
      switch (OpNum) {
26204
      case 5:
26205
        // op: p
26206
        return 28;
26207
      case 2:
26208
        // op: addr
26209
        return 0;
26210
      case 0:
26211
        // op: Rt
26212
        return 12;
26213
      }
26214
      break;
26215
    }
26216
    case ARM::LDRHTr:
26217
    case ARM::LDRSBTr:
26218
    case ARM::LDRSHTr: {
26219
      switch (OpNum) {
26220
      case 5:
26221
        // op: p
26222
        return 28;
26223
      case 2:
26224
        // op: addr
26225
        return 16;
26226
      case 0:
26227
        // op: Rt
26228
        return 12;
26229
      case 3:
26230
        // op: Rm
26231
        return 0;
26232
      }
26233
      break;
26234
    }
26235
    case ARM::STRHTr: {
26236
      switch (OpNum) {
26237
      case 5:
26238
        // op: p
26239
        return 28;
26240
      case 2:
26241
        // op: addr
26242
        return 16;
26243
      case 1:
26244
        // op: Rt
26245
        return 12;
26246
      case 3:
26247
        // op: Rm
26248
        return 0;
26249
      }
26250
      break;
26251
    }
26252
    case ARM::ADCrsr:
26253
    case ARM::ADDrsr:
26254
    case ARM::ANDrsr:
26255
    case ARM::BICrsr:
26256
    case ARM::EORrsr:
26257
    case ARM::ORRrsr:
26258
    case ARM::RSBrsr:
26259
    case ARM::RSCrsr:
26260
    case ARM::SBCrsr:
26261
    case ARM::SUBrsr: {
26262
      switch (OpNum) {
26263
      case 5:
26264
        // op: p
26265
        return 28;
26266
      case 7:
26267
        // op: s
26268
        return 20;
26269
      case 0:
26270
        // op: Rd
26271
        return 12;
26272
      case 1:
26273
        // op: Rn
26274
        return 16;
26275
      case 2:
26276
        // op: shift
26277
        return 0;
26278
      }
26279
      break;
26280
    }
26281
    case ARM::t2ASRri:
26282
    case ARM::t2LSLri:
26283
    case ARM::t2LSRri:
26284
    case ARM::t2RORri: {
26285
      switch (OpNum) {
26286
      case 5:
26287
        // op: s
26288
        return 20;
26289
      case 0:
26290
        // op: Rd
26291
        return 8;
26292
      case 1:
26293
        // op: Rm
26294
        return 0;
26295
      case 2:
26296
        // op: imm
26297
        return 6;
26298
      }
26299
      break;
26300
    }
26301
    case ARM::t2ADCrr:
26302
    case ARM::t2ADDrr:
26303
    case ARM::t2ANDrr:
26304
    case ARM::t2ASRrr:
26305
    case ARM::t2BICrr:
26306
    case ARM::t2EORrr:
26307
    case ARM::t2LSLrr:
26308
    case ARM::t2LSRrr:
26309
    case ARM::t2ORNrr:
26310
    case ARM::t2ORRrr:
26311
    case ARM::t2RORrr:
26312
    case ARM::t2RSBrr:
26313
    case ARM::t2SBCrr:
26314
    case ARM::t2SUBrr: {
26315
      switch (OpNum) {
26316
      case 5:
26317
        // op: s
26318
        return 20;
26319
      case 0:
26320
        // op: Rd
26321
        return 8;
26322
      case 1:
26323
        // op: Rn
26324
        return 16;
26325
      case 2:
26326
        // op: Rm
26327
        return 0;
26328
      }
26329
      break;
26330
    }
26331
    case ARM::t2ADCri:
26332
    case ARM::t2ADDri:
26333
    case ARM::t2ANDri:
26334
    case ARM::t2BICri:
26335
    case ARM::t2EORri:
26336
    case ARM::t2ORNri:
26337
    case ARM::t2ORRri:
26338
    case ARM::t2RSBri:
26339
    case ARM::t2SBCri:
26340
    case ARM::t2SUBri: {
26341
      switch (OpNum) {
26342
      case 5:
26343
        // op: s
26344
        return 20;
26345
      case 0:
26346
        // op: Rd
26347
        return 8;
26348
      case 1:
26349
        // op: Rn
26350
        return 16;
26351
      case 2:
26352
        // op: imm
26353
        return 0;
26354
      }
26355
      break;
26356
    }
26357
    case ARM::t2MVNs: {
26358
      switch (OpNum) {
26359
      case 5:
26360
        // op: s
26361
        return 20;
26362
      case 0:
26363
        // op: Rd
26364
        return 8;
26365
      case 1:
26366
        // op: ShiftedRm
26367
        return 0;
26368
      }
26369
      break;
26370
    }
26371
    case ARM::t2ADDspImm:
26372
    case ARM::t2SUBspImm: {
26373
      switch (OpNum) {
26374
      case 5:
26375
        // op: s
26376
        return 20;
26377
      case 2:
26378
        // op: imm
26379
        return 0;
26380
      }
26381
      break;
26382
    }
26383
    case ARM::UMAAL: {
26384
      switch (OpNum) {
26385
      case 6:
26386
        // op: p
26387
        return 28;
26388
      case 0:
26389
        // op: RdLo
26390
        return 12;
26391
      case 1:
26392
        // op: RdHi
26393
        return 16;
26394
      case 3:
26395
        // op: Rm
26396
        return 8;
26397
      case 2:
26398
        // op: Rn
26399
        return 0;
26400
      }
26401
      break;
26402
    }
26403
    case ARM::MRC: {
26404
      switch (OpNum) {
26405
      case 6:
26406
        // op: p
26407
        return 28;
26408
      case 0:
26409
        // op: Rt
26410
        return 12;
26411
      case 1:
26412
        // op: cop
26413
        return 8;
26414
      case 2:
26415
        // op: opc1
26416
        return 21;
26417
      case 5:
26418
        // op: opc2
26419
        return 5;
26420
      case 4:
26421
        // op: CRm
26422
        return 0;
26423
      case 3:
26424
        // op: CRn
26425
        return 16;
26426
      }
26427
      break;
26428
    }
26429
    case ARM::LDRD_PRE: {
26430
      switch (OpNum) {
26431
      case 6:
26432
        // op: p
26433
        return 28;
26434
      case 0:
26435
        // op: Rt
26436
        return 12;
26437
      case 3:
26438
        // op: addr
26439
        return 0;
26440
      }
26441
      break;
26442
    }
26443
    case ARM::LDRD_POST: {
26444
      switch (OpNum) {
26445
      case 6:
26446
        // op: p
26447
        return 28;
26448
      case 0:
26449
        // op: Rt
26450
        return 12;
26451
      case 4:
26452
        // op: offset
26453
        return 0;
26454
      case 3:
26455
        // op: addr
26456
        return 16;
26457
      }
26458
      break;
26459
    }
26460
    case ARM::STRD_PRE: {
26461
      switch (OpNum) {
26462
      case 6:
26463
        // op: p
26464
        return 28;
26465
      case 1:
26466
        // op: Rt
26467
        return 12;
26468
      case 3:
26469
        // op: addr
26470
        return 0;
26471
      }
26472
      break;
26473
    }
26474
    case ARM::STRD_POST: {
26475
      switch (OpNum) {
26476
      case 6:
26477
        // op: p
26478
        return 28;
26479
      case 1:
26480
        // op: Rt
26481
        return 12;
26482
      case 4:
26483
        // op: offset
26484
        return 0;
26485
      case 3:
26486
        // op: addr
26487
        return 16;
26488
      }
26489
      break;
26490
    }
26491
    case ARM::CDP: {
26492
      switch (OpNum) {
26493
      case 6:
26494
        // op: p
26495
        return 28;
26496
      case 1:
26497
        // op: opc1
26498
        return 20;
26499
      case 3:
26500
        // op: CRn
26501
        return 16;
26502
      case 2:
26503
        // op: CRd
26504
        return 12;
26505
      case 0:
26506
        // op: cop
26507
        return 8;
26508
      case 5:
26509
        // op: opc2
26510
        return 5;
26511
      case 4:
26512
        // op: CRm
26513
        return 0;
26514
      }
26515
      break;
26516
    }
26517
    case ARM::SMLALBB:
26518
    case ARM::SMLALBT:
26519
    case ARM::SMLALD:
26520
    case ARM::SMLALDX:
26521
    case ARM::SMLALTB:
26522
    case ARM::SMLALTT:
26523
    case ARM::SMLSLD:
26524
    case ARM::SMLSLDX: {
26525
      switch (OpNum) {
26526
      case 6:
26527
        // op: p
26528
        return 28;
26529
      case 2:
26530
        // op: Rn
26531
        return 0;
26532
      case 3:
26533
        // op: Rm
26534
        return 8;
26535
      case 0:
26536
        // op: RdLo
26537
        return 12;
26538
      case 1:
26539
        // op: RdHi
26540
        return 16;
26541
      }
26542
      break;
26543
    }
26544
    case ARM::MCR: {
26545
      switch (OpNum) {
26546
      case 6:
26547
        // op: p
26548
        return 28;
26549
      case 2:
26550
        // op: Rt
26551
        return 12;
26552
      case 0:
26553
        // op: cop
26554
        return 8;
26555
      case 1:
26556
        // op: opc1
26557
        return 21;
26558
      case 5:
26559
        // op: opc2
26560
        return 5;
26561
      case 4:
26562
        // op: CRm
26563
        return 0;
26564
      case 3:
26565
        // op: CRn
26566
        return 16;
26567
      }
26568
      break;
26569
    }
26570
    case ARM::SMLAL:
26571
    case ARM::UMLAL: {
26572
      switch (OpNum) {
26573
      case 6:
26574
        // op: p
26575
        return 28;
26576
      case 8:
26577
        // op: s
26578
        return 20;
26579
      case 0:
26580
        // op: RdLo
26581
        return 12;
26582
      case 1:
26583
        // op: RdHi
26584
        return 16;
26585
      case 3:
26586
        // op: Rm
26587
        return 8;
26588
      case 2:
26589
        // op: Rn
26590
        return 0;
26591
      }
26592
      break;
26593
    }
26594
    case ARM::t2ADCrs:
26595
    case ARM::t2ADDrs:
26596
    case ARM::t2ANDrs:
26597
    case ARM::t2BICrs:
26598
    case ARM::t2EORrs:
26599
    case ARM::t2ORNrs:
26600
    case ARM::t2ORRrs:
26601
    case ARM::t2RSBrs:
26602
    case ARM::t2SBCrs:
26603
    case ARM::t2SUBrs: {
26604
      switch (OpNum) {
26605
      case 6:
26606
        // op: s
26607
        return 20;
26608
      case 0:
26609
        // op: Rd
26610
        return 8;
26611
      case 1:
26612
        // op: Rn
26613
        return 16;
26614
      case 2:
26615
        // op: ShiftedRm
26616
        return 0;
26617
      }
26618
      break;
26619
    }
26620
  }
26621
  std::string msg;
26622
  raw_string_ostream Msg(msg);
26623
  Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
26624
  report_fatal_error(Msg.str().c_str());
26625
}
26626
26627
#endif // GET_OPERAND_BIT_OFFSET
26628