/src/build/lib/Target/ARM/ARMGenMCPseudoLowering.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Pseudo-instruction MC lowering Source Fragment *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | bool ARMAsmPrinter:: |
10 | | emitPseudoExpansionLowering(MCStreamer &OutStreamer, |
11 | 248k | const MachineInstr *MI) { |
12 | 248k | switch (MI->getOpcode()) { |
13 | 247k | default: return false; |
14 | 6 | case ARM::B: { |
15 | 6 | MCInst TmpInst; |
16 | 6 | MCOperand MCOp; |
17 | 6 | TmpInst.setOpcode(ARM::Bcc); |
18 | | // Operand: target |
19 | 6 | lowerOperand(MI->getOperand(0), MCOp); |
20 | 6 | TmpInst.addOperand(MCOp); |
21 | | // Operand: p |
22 | 6 | TmpInst.addOperand(MCOperand::createImm(14)); |
23 | 6 | TmpInst.addOperand(MCOperand::createReg(0)); |
24 | 6 | EmitToStreamer(OutStreamer, TmpInst); |
25 | 6 | break; |
26 | 0 | } |
27 | 0 | case ARM::BLX_noip: { |
28 | 0 | MCInst TmpInst; |
29 | 0 | MCOperand MCOp; |
30 | 0 | TmpInst.setOpcode(ARM::BLX); |
31 | | // Operand: func |
32 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
33 | 0 | TmpInst.addOperand(MCOp); |
34 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
35 | 0 | break; |
36 | 0 | } |
37 | 0 | case ARM::BLX_pred_noip: { |
38 | 0 | MCInst TmpInst; |
39 | 0 | MCOperand MCOp; |
40 | 0 | TmpInst.setOpcode(ARM::BLX_pred); |
41 | | // Operand: func |
42 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
43 | 0 | TmpInst.addOperand(MCOp); |
44 | | // Operand: p |
45 | 0 | TmpInst.addOperand(MCOperand::createImm(14)); |
46 | 0 | TmpInst.addOperand(MCOperand::createReg(0)); |
47 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
48 | 0 | break; |
49 | 0 | } |
50 | 0 | case ARM::LDMIA_RET: { |
51 | 0 | MCInst TmpInst; |
52 | 0 | MCOperand MCOp; |
53 | 0 | TmpInst.setOpcode(ARM::LDMIA_UPD); |
54 | | // Operand: wb |
55 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
56 | 0 | TmpInst.addOperand(MCOp); |
57 | | // Operand: Rn |
58 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
59 | 0 | TmpInst.addOperand(MCOp); |
60 | | // Operand: p |
61 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
62 | 0 | TmpInst.addOperand(MCOp); |
63 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
64 | 0 | TmpInst.addOperand(MCOp); |
65 | | // Operand: regs |
66 | 0 | lowerOperand(MI->getOperand(4), MCOp); |
67 | 0 | TmpInst.addOperand(MCOp); |
68 | | // variable_ops |
69 | 0 | for (unsigned i = 5, e = MI->getNumOperands(); i != e; ++i) |
70 | 0 | if (lowerOperand(MI->getOperand(i), MCOp)) |
71 | 0 | TmpInst.addOperand(MCOp); |
72 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
73 | 0 | break; |
74 | 0 | } |
75 | 435 | case ARM::MLAv5: { |
76 | 435 | MCInst TmpInst; |
77 | 435 | MCOperand MCOp; |
78 | 435 | TmpInst.setOpcode(ARM::MLA); |
79 | | // Operand: Rd |
80 | 435 | lowerOperand(MI->getOperand(0), MCOp); |
81 | 435 | TmpInst.addOperand(MCOp); |
82 | | // Operand: Rn |
83 | 435 | lowerOperand(MI->getOperand(1), MCOp); |
84 | 435 | TmpInst.addOperand(MCOp); |
85 | | // Operand: Rm |
86 | 435 | lowerOperand(MI->getOperand(2), MCOp); |
87 | 435 | TmpInst.addOperand(MCOp); |
88 | | // Operand: Ra |
89 | 435 | lowerOperand(MI->getOperand(3), MCOp); |
90 | 435 | TmpInst.addOperand(MCOp); |
91 | | // Operand: p |
92 | 435 | lowerOperand(MI->getOperand(4), MCOp); |
93 | 435 | TmpInst.addOperand(MCOp); |
94 | 435 | lowerOperand(MI->getOperand(5), MCOp); |
95 | 435 | TmpInst.addOperand(MCOp); |
96 | | // Operand: s |
97 | 435 | lowerOperand(MI->getOperand(6), MCOp); |
98 | 435 | TmpInst.addOperand(MCOp); |
99 | 435 | EmitToStreamer(OutStreamer, TmpInst); |
100 | 435 | break; |
101 | 0 | } |
102 | 0 | case ARM::MOVPCRX: { |
103 | 0 | MCInst TmpInst; |
104 | 0 | MCOperand MCOp; |
105 | 0 | TmpInst.setOpcode(ARM::MOVr); |
106 | | // Operand: Rd |
107 | 0 | TmpInst.addOperand(MCOperand::createReg(ARM::PC)); |
108 | | // Operand: Rm |
109 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
110 | 0 | TmpInst.addOperand(MCOp); |
111 | | // Operand: p |
112 | 0 | TmpInst.addOperand(MCOperand::createImm(14)); |
113 | 0 | TmpInst.addOperand(MCOperand::createReg(0)); |
114 | | // Operand: s |
115 | 0 | TmpInst.addOperand(MCOperand::createReg(0)); |
116 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
117 | 0 | break; |
118 | 0 | } |
119 | 515 | case ARM::MULv5: { |
120 | 515 | MCInst TmpInst; |
121 | 515 | MCOperand MCOp; |
122 | 515 | TmpInst.setOpcode(ARM::MUL); |
123 | | // Operand: Rd |
124 | 515 | lowerOperand(MI->getOperand(0), MCOp); |
125 | 515 | TmpInst.addOperand(MCOp); |
126 | | // Operand: Rn |
127 | 515 | lowerOperand(MI->getOperand(1), MCOp); |
128 | 515 | TmpInst.addOperand(MCOp); |
129 | | // Operand: Rm |
130 | 515 | lowerOperand(MI->getOperand(2), MCOp); |
131 | 515 | TmpInst.addOperand(MCOp); |
132 | | // Operand: p |
133 | 515 | lowerOperand(MI->getOperand(3), MCOp); |
134 | 515 | TmpInst.addOperand(MCOp); |
135 | 515 | lowerOperand(MI->getOperand(4), MCOp); |
136 | 515 | TmpInst.addOperand(MCOp); |
137 | | // Operand: s |
138 | 515 | lowerOperand(MI->getOperand(5), MCOp); |
139 | 515 | TmpInst.addOperand(MCOp); |
140 | 515 | EmitToStreamer(OutStreamer, TmpInst); |
141 | 515 | break; |
142 | 0 | } |
143 | 0 | case ARM::SMLALv5: { |
144 | 0 | MCInst TmpInst; |
145 | 0 | MCOperand MCOp; |
146 | 0 | TmpInst.setOpcode(ARM::SMLAL); |
147 | | // Operand: RdLo |
148 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
149 | 0 | TmpInst.addOperand(MCOp); |
150 | | // Operand: RdHi |
151 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
152 | 0 | TmpInst.addOperand(MCOp); |
153 | | // Operand: Rn |
154 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
155 | 0 | TmpInst.addOperand(MCOp); |
156 | | // Operand: Rm |
157 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
158 | 0 | TmpInst.addOperand(MCOp); |
159 | | // Operand: RLo |
160 | 0 | lowerOperand(MI->getOperand(4), MCOp); |
161 | 0 | TmpInst.addOperand(MCOp); |
162 | | // Operand: RHi |
163 | 0 | lowerOperand(MI->getOperand(5), MCOp); |
164 | 0 | TmpInst.addOperand(MCOp); |
165 | | // Operand: p |
166 | 0 | lowerOperand(MI->getOperand(6), MCOp); |
167 | 0 | TmpInst.addOperand(MCOp); |
168 | 0 | lowerOperand(MI->getOperand(7), MCOp); |
169 | 0 | TmpInst.addOperand(MCOp); |
170 | | // Operand: s |
171 | 0 | lowerOperand(MI->getOperand(8), MCOp); |
172 | 0 | TmpInst.addOperand(MCOp); |
173 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
174 | 0 | break; |
175 | 0 | } |
176 | 45 | case ARM::SMULLv5: { |
177 | 45 | MCInst TmpInst; |
178 | 45 | MCOperand MCOp; |
179 | 45 | TmpInst.setOpcode(ARM::SMULL); |
180 | | // Operand: RdLo |
181 | 45 | lowerOperand(MI->getOperand(0), MCOp); |
182 | 45 | TmpInst.addOperand(MCOp); |
183 | | // Operand: RdHi |
184 | 45 | lowerOperand(MI->getOperand(1), MCOp); |
185 | 45 | TmpInst.addOperand(MCOp); |
186 | | // Operand: Rn |
187 | 45 | lowerOperand(MI->getOperand(2), MCOp); |
188 | 45 | TmpInst.addOperand(MCOp); |
189 | | // Operand: Rm |
190 | 45 | lowerOperand(MI->getOperand(3), MCOp); |
191 | 45 | TmpInst.addOperand(MCOp); |
192 | | // Operand: p |
193 | 45 | lowerOperand(MI->getOperand(4), MCOp); |
194 | 45 | TmpInst.addOperand(MCOp); |
195 | 45 | lowerOperand(MI->getOperand(5), MCOp); |
196 | 45 | TmpInst.addOperand(MCOp); |
197 | | // Operand: s |
198 | 45 | lowerOperand(MI->getOperand(6), MCOp); |
199 | 45 | TmpInst.addOperand(MCOp); |
200 | 45 | EmitToStreamer(OutStreamer, TmpInst); |
201 | 45 | break; |
202 | 0 | } |
203 | 17 | case ARM::TAILJMPd: { |
204 | 17 | MCInst TmpInst; |
205 | 17 | MCOperand MCOp; |
206 | 17 | TmpInst.setOpcode(ARM::Bcc); |
207 | | // Operand: target |
208 | 17 | lowerOperand(MI->getOperand(0), MCOp); |
209 | 17 | TmpInst.addOperand(MCOp); |
210 | | // Operand: p |
211 | 17 | TmpInst.addOperand(MCOperand::createImm(14)); |
212 | 17 | TmpInst.addOperand(MCOperand::createReg(0)); |
213 | 17 | EmitToStreamer(OutStreamer, TmpInst); |
214 | 17 | break; |
215 | 0 | } |
216 | 0 | case ARM::TAILJMPr: { |
217 | 0 | MCInst TmpInst; |
218 | 0 | MCOperand MCOp; |
219 | 0 | TmpInst.setOpcode(ARM::BX); |
220 | | // Operand: dst |
221 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
222 | 0 | TmpInst.addOperand(MCOp); |
223 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
224 | 0 | break; |
225 | 0 | } |
226 | 0 | case ARM::TAILJMPr4: { |
227 | 0 | MCInst TmpInst; |
228 | 0 | MCOperand MCOp; |
229 | 0 | TmpInst.setOpcode(ARM::MOVr); |
230 | | // Operand: Rd |
231 | 0 | TmpInst.addOperand(MCOperand::createReg(ARM::PC)); |
232 | | // Operand: Rm |
233 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
234 | 0 | TmpInst.addOperand(MCOp); |
235 | | // Operand: p |
236 | 0 | TmpInst.addOperand(MCOperand::createImm(14)); |
237 | 0 | TmpInst.addOperand(MCOperand::createReg(0)); |
238 | | // Operand: s |
239 | 0 | TmpInst.addOperand(MCOperand::createReg(0)); |
240 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
241 | 0 | break; |
242 | 0 | } |
243 | 0 | case ARM::UMLALv5: { |
244 | 0 | MCInst TmpInst; |
245 | 0 | MCOperand MCOp; |
246 | 0 | TmpInst.setOpcode(ARM::UMLAL); |
247 | | // Operand: RdLo |
248 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
249 | 0 | TmpInst.addOperand(MCOp); |
250 | | // Operand: RdHi |
251 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
252 | 0 | TmpInst.addOperand(MCOp); |
253 | | // Operand: Rn |
254 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
255 | 0 | TmpInst.addOperand(MCOp); |
256 | | // Operand: Rm |
257 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
258 | 0 | TmpInst.addOperand(MCOp); |
259 | | // Operand: RLo |
260 | 0 | lowerOperand(MI->getOperand(4), MCOp); |
261 | 0 | TmpInst.addOperand(MCOp); |
262 | | // Operand: RHi |
263 | 0 | lowerOperand(MI->getOperand(5), MCOp); |
264 | 0 | TmpInst.addOperand(MCOp); |
265 | | // Operand: p |
266 | 0 | lowerOperand(MI->getOperand(6), MCOp); |
267 | 0 | TmpInst.addOperand(MCOp); |
268 | 0 | lowerOperand(MI->getOperand(7), MCOp); |
269 | 0 | TmpInst.addOperand(MCOp); |
270 | | // Operand: s |
271 | 0 | lowerOperand(MI->getOperand(8), MCOp); |
272 | 0 | TmpInst.addOperand(MCOp); |
273 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
274 | 0 | break; |
275 | 0 | } |
276 | 250 | case ARM::UMULLv5: { |
277 | 250 | MCInst TmpInst; |
278 | 250 | MCOperand MCOp; |
279 | 250 | TmpInst.setOpcode(ARM::UMULL); |
280 | | // Operand: RdLo |
281 | 250 | lowerOperand(MI->getOperand(0), MCOp); |
282 | 250 | TmpInst.addOperand(MCOp); |
283 | | // Operand: RdHi |
284 | 250 | lowerOperand(MI->getOperand(1), MCOp); |
285 | 250 | TmpInst.addOperand(MCOp); |
286 | | // Operand: Rn |
287 | 250 | lowerOperand(MI->getOperand(2), MCOp); |
288 | 250 | TmpInst.addOperand(MCOp); |
289 | | // Operand: Rm |
290 | 250 | lowerOperand(MI->getOperand(3), MCOp); |
291 | 250 | TmpInst.addOperand(MCOp); |
292 | | // Operand: p |
293 | 250 | lowerOperand(MI->getOperand(4), MCOp); |
294 | 250 | TmpInst.addOperand(MCOp); |
295 | 250 | lowerOperand(MI->getOperand(5), MCOp); |
296 | 250 | TmpInst.addOperand(MCOp); |
297 | | // Operand: s |
298 | 250 | lowerOperand(MI->getOperand(6), MCOp); |
299 | 250 | TmpInst.addOperand(MCOp); |
300 | 250 | EmitToStreamer(OutStreamer, TmpInst); |
301 | 250 | break; |
302 | 0 | } |
303 | 0 | case ARM::VMOVD0: { |
304 | 0 | MCInst TmpInst; |
305 | 0 | MCOperand MCOp; |
306 | 0 | TmpInst.setOpcode(ARM::VMOVv2i32); |
307 | | // Operand: Vd |
308 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
309 | 0 | TmpInst.addOperand(MCOp); |
310 | | // Operand: SIMM |
311 | 0 | TmpInst.addOperand(MCOperand::createImm(0)); |
312 | | // Operand: p |
313 | 0 | TmpInst.addOperand(MCOperand::createImm(14)); |
314 | 0 | TmpInst.addOperand(MCOperand::createReg(0)); |
315 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
316 | 0 | break; |
317 | 0 | } |
318 | 0 | case ARM::VMOVQ0: { |
319 | 0 | MCInst TmpInst; |
320 | 0 | MCOperand MCOp; |
321 | 0 | TmpInst.setOpcode(ARM::VMOVv4i32); |
322 | | // Operand: Vd |
323 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
324 | 0 | TmpInst.addOperand(MCOp); |
325 | | // Operand: SIMM |
326 | 0 | TmpInst.addOperand(MCOperand::createImm(0)); |
327 | | // Operand: p |
328 | 0 | TmpInst.addOperand(MCOperand::createImm(14)); |
329 | 0 | TmpInst.addOperand(MCOperand::createReg(0)); |
330 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
331 | 0 | break; |
332 | 0 | } |
333 | 0 | case ARM::t2LDMIA_RET: { |
334 | 0 | MCInst TmpInst; |
335 | 0 | MCOperand MCOp; |
336 | 0 | TmpInst.setOpcode(ARM::t2LDMIA_UPD); |
337 | | // Operand: wb |
338 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
339 | 0 | TmpInst.addOperand(MCOp); |
340 | | // Operand: Rn |
341 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
342 | 0 | TmpInst.addOperand(MCOp); |
343 | | // Operand: p |
344 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
345 | 0 | TmpInst.addOperand(MCOp); |
346 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
347 | 0 | TmpInst.addOperand(MCOp); |
348 | | // Operand: regs |
349 | 0 | lowerOperand(MI->getOperand(4), MCOp); |
350 | 0 | TmpInst.addOperand(MCOp); |
351 | | // variable_ops |
352 | 0 | for (unsigned i = 5, e = MI->getNumOperands(); i != e; ++i) |
353 | 0 | if (lowerOperand(MI->getOperand(i), MCOp)) |
354 | 0 | TmpInst.addOperand(MCOp); |
355 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
356 | 0 | break; |
357 | 0 | } |
358 | 0 | case ARM::tBLXr_noip: { |
359 | 0 | MCInst TmpInst; |
360 | 0 | MCOperand MCOp; |
361 | 0 | TmpInst.setOpcode(ARM::tBLXr); |
362 | | // Operand: p |
363 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
364 | 0 | TmpInst.addOperand(MCOp); |
365 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
366 | 0 | TmpInst.addOperand(MCOp); |
367 | | // Operand: func |
368 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
369 | 0 | TmpInst.addOperand(MCOp); |
370 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
371 | 0 | break; |
372 | 0 | } |
373 | 0 | case ARM::tBRIND: { |
374 | 0 | MCInst TmpInst; |
375 | 0 | MCOperand MCOp; |
376 | 0 | TmpInst.setOpcode(ARM::tMOVr); |
377 | | // Operand: Rd |
378 | 0 | TmpInst.addOperand(MCOperand::createReg(ARM::PC)); |
379 | | // Operand: Rm |
380 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
381 | 0 | TmpInst.addOperand(MCOp); |
382 | | // Operand: p |
383 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
384 | 0 | TmpInst.addOperand(MCOp); |
385 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
386 | 0 | TmpInst.addOperand(MCOp); |
387 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
388 | 0 | break; |
389 | 0 | } |
390 | 0 | case ARM::tBX_RET: { |
391 | 0 | MCInst TmpInst; |
392 | 0 | MCOperand MCOp; |
393 | 0 | TmpInst.setOpcode(ARM::tBX); |
394 | | // Operand: Rm |
395 | 0 | TmpInst.addOperand(MCOperand::createReg(ARM::LR)); |
396 | | // Operand: p |
397 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
398 | 0 | TmpInst.addOperand(MCOp); |
399 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
400 | 0 | TmpInst.addOperand(MCOp); |
401 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
402 | 0 | break; |
403 | 0 | } |
404 | 0 | case ARM::tBX_RET_vararg: { |
405 | 0 | MCInst TmpInst; |
406 | 0 | MCOperand MCOp; |
407 | 0 | TmpInst.setOpcode(ARM::tBX); |
408 | | // Operand: Rm |
409 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
410 | 0 | TmpInst.addOperand(MCOp); |
411 | | // Operand: p |
412 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
413 | 0 | TmpInst.addOperand(MCOp); |
414 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
415 | 0 | TmpInst.addOperand(MCOp); |
416 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
417 | 0 | break; |
418 | 0 | } |
419 | 0 | case ARM::tBfar: { |
420 | 0 | MCInst TmpInst; |
421 | 0 | MCOperand MCOp; |
422 | 0 | TmpInst.setOpcode(ARM::tBL); |
423 | | // Operand: p |
424 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
425 | 0 | TmpInst.addOperand(MCOp); |
426 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
427 | 0 | TmpInst.addOperand(MCOp); |
428 | | // Operand: func |
429 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
430 | 0 | TmpInst.addOperand(MCOp); |
431 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
432 | 0 | break; |
433 | 0 | } |
434 | 0 | case ARM::tLDMIA_UPD: { |
435 | 0 | MCInst TmpInst; |
436 | 0 | MCOperand MCOp; |
437 | 0 | TmpInst.setOpcode(ARM::tLDMIA); |
438 | | // Operand: Rn |
439 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
440 | 0 | TmpInst.addOperand(MCOp); |
441 | | // Operand: p |
442 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
443 | 0 | TmpInst.addOperand(MCOp); |
444 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
445 | 0 | TmpInst.addOperand(MCOp); |
446 | | // Operand: regs |
447 | 0 | lowerOperand(MI->getOperand(4), MCOp); |
448 | 0 | TmpInst.addOperand(MCOp); |
449 | | // variable_ops |
450 | 0 | for (unsigned i = 5, e = MI->getNumOperands(); i != e; ++i) |
451 | 0 | if (lowerOperand(MI->getOperand(i), MCOp)) |
452 | 0 | TmpInst.addOperand(MCOp); |
453 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
454 | 0 | break; |
455 | 0 | } |
456 | 0 | case ARM::tPOP_RET: { |
457 | 0 | MCInst TmpInst; |
458 | 0 | MCOperand MCOp; |
459 | 0 | TmpInst.setOpcode(ARM::tPOP); |
460 | | // Operand: p |
461 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
462 | 0 | TmpInst.addOperand(MCOp); |
463 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
464 | 0 | TmpInst.addOperand(MCOp); |
465 | | // Operand: regs |
466 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
467 | 0 | TmpInst.addOperand(MCOp); |
468 | | // variable_ops |
469 | 0 | for (unsigned i = 3, e = MI->getNumOperands(); i != e; ++i) |
470 | 0 | if (lowerOperand(MI->getOperand(i), MCOp)) |
471 | 0 | TmpInst.addOperand(MCOp); |
472 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
473 | 0 | break; |
474 | 0 | } |
475 | 0 | case ARM::tTAILJMPd: { |
476 | 0 | MCInst TmpInst; |
477 | 0 | MCOperand MCOp; |
478 | 0 | TmpInst.setOpcode(ARM::t2B); |
479 | | // Operand: target |
480 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
481 | 0 | TmpInst.addOperand(MCOp); |
482 | | // Operand: p |
483 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
484 | 0 | TmpInst.addOperand(MCOp); |
485 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
486 | 0 | TmpInst.addOperand(MCOp); |
487 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
488 | 0 | break; |
489 | 0 | } |
490 | 0 | case ARM::tTAILJMPdND: { |
491 | 0 | MCInst TmpInst; |
492 | 0 | MCOperand MCOp; |
493 | 0 | TmpInst.setOpcode(ARM::tB); |
494 | | // Operand: target |
495 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
496 | 0 | TmpInst.addOperand(MCOp); |
497 | | // Operand: p |
498 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
499 | 0 | TmpInst.addOperand(MCOp); |
500 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
501 | 0 | TmpInst.addOperand(MCOp); |
502 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
503 | 0 | break; |
504 | 0 | } |
505 | 0 | case ARM::tTAILJMPr: { |
506 | 0 | MCInst TmpInst; |
507 | 0 | MCOperand MCOp; |
508 | 0 | TmpInst.setOpcode(ARM::tBX); |
509 | | // Operand: Rm |
510 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
511 | 0 | TmpInst.addOperand(MCOp); |
512 | | // Operand: p |
513 | 0 | TmpInst.addOperand(MCOperand::createImm(14)); |
514 | 0 | TmpInst.addOperand(MCOperand::createReg(0)); |
515 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
516 | 0 | break; |
517 | 0 | } |
518 | 248k | } |
519 | 1.26k | return true; |
520 | 248k | } |
521 | | |