Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/ARM/ARMGenRegisterBank.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Register Bank Source Fragments                                             *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGBANK_DECLARATIONS
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#undef GET_REGBANK_DECLARATIONS
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namespace llvm {
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namespace ARM {
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enum : unsigned {
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  InvalidRegBankID = ~0u,
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  FPRRegBankID = 0,
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  GPRRegBankID = 1,
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  NumRegisterBanks,
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};
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} // end namespace ARM
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} // end namespace llvm
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#endif // GET_REGBANK_DECLARATIONS
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#ifdef GET_TARGET_REGBANK_CLASS
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#undef GET_TARGET_REGBANK_CLASS
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private:
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  static const RegisterBank *RegBanks[];
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  static const unsigned Sizes[];
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protected:
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  ARMGenRegisterBankInfo(unsigned HwMode = 0);
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#endif // GET_TARGET_REGBANK_CLASS
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#ifdef GET_TARGET_REGBANK_IMPL
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#undef GET_TARGET_REGBANK_IMPL
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namespace llvm {
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namespace ARM {
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const uint32_t FPRRegBankCoverageData[] = {
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    // 0-31
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    (1u << (ARM::HPRRegClassID - 0)) |
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    (1u << (ARM::SPRRegClassID - 0)) |
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    (1u << (ARM::SPR_8RegClassID - 0)) |
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    (1u << (ARM::FPWithVPRRegClassID - 0)) |
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    (1u << (ARM::FPWithVPR_with_ssub_0RegClassID - 0)) |
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    (1u << (ARM::FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID - 0)) |
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    0,
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    // 32-63
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    (1u << (ARM::DPRRegClassID - 32)) |
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    (1u << (ARM::DPR_VFP2RegClassID - 32)) |
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    (1u << (ARM::DPR_8RegClassID - 32)) |
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    0,
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    // 64-95
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    (1u << (ARM::QPRRegClassID - 64)) |
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    (1u << (ARM::MQPRRegClassID - 64)) |
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    (1u << (ARM::QPR_VFP2RegClassID - 64)) |
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    (1u << (ARM::QPR_8RegClassID - 64)) |
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    0,
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    // 96-127
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    0,
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    // 128-159
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    0,
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};
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const uint32_t GPRRegBankCoverageData[] = {
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    // 0-31
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    (1u << (ARM::GPRRegClassID - 0)) |
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    (1u << (ARM::GPRnopcRegClassID - 0)) |
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    (1u << (ARM::rGPRRegClassID - 0)) |
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    (1u << (ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID - 0)) |
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    (1u << (ARM::tGPRRegClassID - 0)) |
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    (1u << (ARM::GPRnoip_and_tGPREvenRegClassID - 0)) |
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    (1u << (ARM::tGPROddRegClassID - 0)) |
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    (1u << (ARM::tGPREvenRegClassID - 0)) |
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    (1u << (ARM::GPRnosp_and_GPRnopc_and_hGPRRegClassID - 0)) |
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    (1u << (ARM::tcGPRRegClassID - 0)) |
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    (1u << (ARM::GPRnoip_and_GPRnopcRegClassID - 0)) |
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    (1u << (ARM::GPRnopc_and_GPRnoip_and_hGPRRegClassID - 0)) |
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    (1u << (ARM::GPRnopc_and_hGPRRegClassID - 0)) |
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    (1u << (ARM::GPRnospRegClassID - 0)) |
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    (1u << (ARM::GPRnoip_and_GPRnospRegClassID - 0)) |
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    (1u << (ARM::tGPRwithpcRegClassID - 0)) |
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    (1u << (ARM::GPRnosp_and_GPRnoip_and_hGPRRegClassID - 0)) |
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    (1u << (ARM::GPRnosp_and_hGPRRegClassID - 0)) |
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    (1u << (ARM::GPRnoipRegClassID - 0)) |
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    (1u << (ARM::GPRnoip_and_hGPRRegClassID - 0)) |
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    (1u << (ARM::hGPRRegClassID - 0)) |
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    (1u << (ARM::GPRwithAPSRRegClassID - 0)) |
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    (1u << (ARM::GPRwithAPSR_NZCVnospRegClassID - 0)) |
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    0,
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    // 32-63
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    (1u << (ARM::GPRnoip_and_tcGPRRegClassID - 32)) |
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    (1u << (ARM::tGPREven_and_GPRnoip_and_tcGPRRegClassID - 32)) |
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    (1u << (ARM::tGPROdd_and_tcGPRRegClassID - 32)) |
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    (1u << (ARM::tGPR_and_tGPREvenRegClassID - 32)) |
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    (1u << (ARM::tGPR_and_tGPROddRegClassID - 32)) |
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    (1u << (ARM::hGPR_and_GPRnoip_and_tGPREvenRegClassID - 32)) |
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    (1u << (ARM::hGPR_and_tGPROddRegClassID - 32)) |
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    (1u << (ARM::GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRRegClassID - 32)) |
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    (1u << (ARM::hGPR_and_tGPREvenRegClassID - 32)) |
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    (1u << (ARM::GPRlrRegClassID - 32)) |
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    (1u << (ARM::hGPR_and_tcGPRRegClassID - 32)) |
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    (1u << (ARM::tGPREven_and_tcGPRRegClassID - 32)) |
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    (1u << (ARM::GPRspRegClassID - 32)) |
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    (1u << (ARM::hGPR_and_tGPRwithpcRegClassID - 32)) |
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    0,
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    // 64-95
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    0,
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    // 96-127
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    0,
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    // 128-159
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    0,
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};
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constexpr RegisterBank FPRRegBank(/* ID */ ARM::FPRRegBankID, /* Name */ "FPRB", /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 136);
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constexpr RegisterBank GPRRegBank(/* ID */ ARM::GPRRegBankID, /* Name */ "GPRB", /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 136);
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} // end namespace ARM
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const RegisterBank *ARMGenRegisterBankInfo::RegBanks[] = {
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    &ARM::FPRRegBank,
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    &ARM::GPRRegBank,
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};
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const unsigned ARMGenRegisterBankInfo::Sizes[] = {
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    // Mode = 0 (Default)
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    128,
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    32,
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};
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ARMGenRegisterBankInfo::ARMGenRegisterBankInfo(unsigned HwMode)
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2.47k
    : RegisterBankInfo(RegBanks, ARM::NumRegisterBanks, Sizes, HwMode) {
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  // Assert that RegBank indices match their ID's
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2.47k
#ifndef NDEBUG
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2.47k
  for (auto RB : enumerate(RegBanks))
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4.95k
    assert(RB.index() == RB.value()->getID() && "Index != ID");
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2.47k
#endif // NDEBUG
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2.47k
}
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} // end namespace llvm
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#endif // GET_TARGET_REGBANK_IMPL