Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/AVR/AVRGenInstrInfo.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Instruction Enum Values and Descriptors                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_INSTRINFO_ENUM
10
#undef GET_INSTRINFO_ENUM
11
namespace llvm {
12
13
namespace AVR {
14
  enum {
15
    PHI = 0,
16
    INLINEASM = 1,
17
    INLINEASM_BR  = 2,
18
    CFI_INSTRUCTION = 3,
19
    EH_LABEL  = 4,
20
    GC_LABEL  = 5,
21
    ANNOTATION_LABEL  = 6,
22
    KILL  = 7,
23
    EXTRACT_SUBREG  = 8,
24
    INSERT_SUBREG = 9,
25
    IMPLICIT_DEF  = 10,
26
    SUBREG_TO_REG = 11,
27
    COPY_TO_REGCLASS  = 12,
28
    DBG_VALUE = 13,
29
    DBG_VALUE_LIST  = 14,
30
    DBG_INSTR_REF = 15,
31
    DBG_PHI = 16,
32
    DBG_LABEL = 17,
33
    REG_SEQUENCE  = 18,
34
    COPY  = 19,
35
    BUNDLE  = 20,
36
    LIFETIME_START  = 21,
37
    LIFETIME_END  = 22,
38
    PSEUDO_PROBE  = 23,
39
    ARITH_FENCE = 24,
40
    STACKMAP  = 25,
41
    FENTRY_CALL = 26,
42
    PATCHPOINT  = 27,
43
    LOAD_STACK_GUARD  = 28,
44
    PREALLOCATED_SETUP  = 29,
45
    PREALLOCATED_ARG  = 30,
46
    STATEPOINT  = 31,
47
    LOCAL_ESCAPE  = 32,
48
    FAULTING_OP = 33,
49
    PATCHABLE_OP  = 34,
50
    PATCHABLE_FUNCTION_ENTER  = 35,
51
    PATCHABLE_RET = 36,
52
    PATCHABLE_FUNCTION_EXIT = 37,
53
    PATCHABLE_TAIL_CALL = 38,
54
    PATCHABLE_EVENT_CALL  = 39,
55
    PATCHABLE_TYPED_EVENT_CALL  = 40,
56
    ICALL_BRANCH_FUNNEL = 41,
57
    MEMBARRIER  = 42,
58
    JUMP_TABLE_DEBUG_INFO = 43,
59
    G_ASSERT_SEXT = 44,
60
    G_ASSERT_ZEXT = 45,
61
    G_ASSERT_ALIGN  = 46,
62
    G_ADD = 47,
63
    G_SUB = 48,
64
    G_MUL = 49,
65
    G_SDIV  = 50,
66
    G_UDIV  = 51,
67
    G_SREM  = 52,
68
    G_UREM  = 53,
69
    G_SDIVREM = 54,
70
    G_UDIVREM = 55,
71
    G_AND = 56,
72
    G_OR  = 57,
73
    G_XOR = 58,
74
    G_IMPLICIT_DEF  = 59,
75
    G_PHI = 60,
76
    G_FRAME_INDEX = 61,
77
    G_GLOBAL_VALUE  = 62,
78
    G_CONSTANT_POOL = 63,
79
    G_EXTRACT = 64,
80
    G_UNMERGE_VALUES  = 65,
81
    G_INSERT  = 66,
82
    G_MERGE_VALUES  = 67,
83
    G_BUILD_VECTOR  = 68,
84
    G_BUILD_VECTOR_TRUNC  = 69,
85
    G_CONCAT_VECTORS  = 70,
86
    G_PTRTOINT  = 71,
87
    G_INTTOPTR  = 72,
88
    G_BITCAST = 73,
89
    G_FREEZE  = 74,
90
    G_CONSTANT_FOLD_BARRIER = 75,
91
    G_INTRINSIC_FPTRUNC_ROUND = 76,
92
    G_INTRINSIC_TRUNC = 77,
93
    G_INTRINSIC_ROUND = 78,
94
    G_INTRINSIC_LRINT = 79,
95
    G_INTRINSIC_ROUNDEVEN = 80,
96
    G_READCYCLECOUNTER  = 81,
97
    G_LOAD  = 82,
98
    G_SEXTLOAD  = 83,
99
    G_ZEXTLOAD  = 84,
100
    G_INDEXED_LOAD  = 85,
101
    G_INDEXED_SEXTLOAD  = 86,
102
    G_INDEXED_ZEXTLOAD  = 87,
103
    G_STORE = 88,
104
    G_INDEXED_STORE = 89,
105
    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 90,
106
    G_ATOMIC_CMPXCHG  = 91,
107
    G_ATOMICRMW_XCHG  = 92,
108
    G_ATOMICRMW_ADD = 93,
109
    G_ATOMICRMW_SUB = 94,
110
    G_ATOMICRMW_AND = 95,
111
    G_ATOMICRMW_NAND  = 96,
112
    G_ATOMICRMW_OR  = 97,
113
    G_ATOMICRMW_XOR = 98,
114
    G_ATOMICRMW_MAX = 99,
115
    G_ATOMICRMW_MIN = 100,
116
    G_ATOMICRMW_UMAX  = 101,
117
    G_ATOMICRMW_UMIN  = 102,
118
    G_ATOMICRMW_FADD  = 103,
119
    G_ATOMICRMW_FSUB  = 104,
120
    G_ATOMICRMW_FMAX  = 105,
121
    G_ATOMICRMW_FMIN  = 106,
122
    G_ATOMICRMW_UINC_WRAP = 107,
123
    G_ATOMICRMW_UDEC_WRAP = 108,
124
    G_FENCE = 109,
125
    G_PREFETCH  = 110,
126
    G_BRCOND  = 111,
127
    G_BRINDIRECT  = 112,
128
    G_INVOKE_REGION_START = 113,
129
    G_INTRINSIC = 114,
130
    G_INTRINSIC_W_SIDE_EFFECTS  = 115,
131
    G_INTRINSIC_CONVERGENT  = 116,
132
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 117,
133
    G_ANYEXT  = 118,
134
    G_TRUNC = 119,
135
    G_CONSTANT  = 120,
136
    G_FCONSTANT = 121,
137
    G_VASTART = 122,
138
    G_VAARG = 123,
139
    G_SEXT  = 124,
140
    G_SEXT_INREG  = 125,
141
    G_ZEXT  = 126,
142
    G_SHL = 127,
143
    G_LSHR  = 128,
144
    G_ASHR  = 129,
145
    G_FSHL  = 130,
146
    G_FSHR  = 131,
147
    G_ROTR  = 132,
148
    G_ROTL  = 133,
149
    G_ICMP  = 134,
150
    G_FCMP  = 135,
151
    G_SELECT  = 136,
152
    G_UADDO = 137,
153
    G_UADDE = 138,
154
    G_USUBO = 139,
155
    G_USUBE = 140,
156
    G_SADDO = 141,
157
    G_SADDE = 142,
158
    G_SSUBO = 143,
159
    G_SSUBE = 144,
160
    G_UMULO = 145,
161
    G_SMULO = 146,
162
    G_UMULH = 147,
163
    G_SMULH = 148,
164
    G_UADDSAT = 149,
165
    G_SADDSAT = 150,
166
    G_USUBSAT = 151,
167
    G_SSUBSAT = 152,
168
    G_USHLSAT = 153,
169
    G_SSHLSAT = 154,
170
    G_SMULFIX = 155,
171
    G_UMULFIX = 156,
172
    G_SMULFIXSAT  = 157,
173
    G_UMULFIXSAT  = 158,
174
    G_SDIVFIX = 159,
175
    G_UDIVFIX = 160,
176
    G_SDIVFIXSAT  = 161,
177
    G_UDIVFIXSAT  = 162,
178
    G_FADD  = 163,
179
    G_FSUB  = 164,
180
    G_FMUL  = 165,
181
    G_FMA = 166,
182
    G_FMAD  = 167,
183
    G_FDIV  = 168,
184
    G_FREM  = 169,
185
    G_FPOW  = 170,
186
    G_FPOWI = 171,
187
    G_FEXP  = 172,
188
    G_FEXP2 = 173,
189
    G_FEXP10  = 174,
190
    G_FLOG  = 175,
191
    G_FLOG2 = 176,
192
    G_FLOG10  = 177,
193
    G_FLDEXP  = 178,
194
    G_FFREXP  = 179,
195
    G_FNEG  = 180,
196
    G_FPEXT = 181,
197
    G_FPTRUNC = 182,
198
    G_FPTOSI  = 183,
199
    G_FPTOUI  = 184,
200
    G_SITOFP  = 185,
201
    G_UITOFP  = 186,
202
    G_FABS  = 187,
203
    G_FCOPYSIGN = 188,
204
    G_IS_FPCLASS  = 189,
205
    G_FCANONICALIZE = 190,
206
    G_FMINNUM = 191,
207
    G_FMAXNUM = 192,
208
    G_FMINNUM_IEEE  = 193,
209
    G_FMAXNUM_IEEE  = 194,
210
    G_FMINIMUM  = 195,
211
    G_FMAXIMUM  = 196,
212
    G_GET_FPENV = 197,
213
    G_SET_FPENV = 198,
214
    G_RESET_FPENV = 199,
215
    G_GET_FPMODE  = 200,
216
    G_SET_FPMODE  = 201,
217
    G_RESET_FPMODE  = 202,
218
    G_PTR_ADD = 203,
219
    G_PTRMASK = 204,
220
    G_SMIN  = 205,
221
    G_SMAX  = 206,
222
    G_UMIN  = 207,
223
    G_UMAX  = 208,
224
    G_ABS = 209,
225
    G_LROUND  = 210,
226
    G_LLROUND = 211,
227
    G_BR  = 212,
228
    G_BRJT  = 213,
229
    G_INSERT_VECTOR_ELT = 214,
230
    G_EXTRACT_VECTOR_ELT  = 215,
231
    G_SHUFFLE_VECTOR  = 216,
232
    G_CTTZ  = 217,
233
    G_CTTZ_ZERO_UNDEF = 218,
234
    G_CTLZ  = 219,
235
    G_CTLZ_ZERO_UNDEF = 220,
236
    G_CTPOP = 221,
237
    G_BSWAP = 222,
238
    G_BITREVERSE  = 223,
239
    G_FCEIL = 224,
240
    G_FCOS  = 225,
241
    G_FSIN  = 226,
242
    G_FSQRT = 227,
243
    G_FFLOOR  = 228,
244
    G_FRINT = 229,
245
    G_FNEARBYINT  = 230,
246
    G_ADDRSPACE_CAST  = 231,
247
    G_BLOCK_ADDR  = 232,
248
    G_JUMP_TABLE  = 233,
249
    G_DYN_STACKALLOC  = 234,
250
    G_STACKSAVE = 235,
251
    G_STACKRESTORE  = 236,
252
    G_STRICT_FADD = 237,
253
    G_STRICT_FSUB = 238,
254
    G_STRICT_FMUL = 239,
255
    G_STRICT_FDIV = 240,
256
    G_STRICT_FREM = 241,
257
    G_STRICT_FMA  = 242,
258
    G_STRICT_FSQRT  = 243,
259
    G_STRICT_FLDEXP = 244,
260
    G_READ_REGISTER = 245,
261
    G_WRITE_REGISTER  = 246,
262
    G_MEMCPY  = 247,
263
    G_MEMCPY_INLINE = 248,
264
    G_MEMMOVE = 249,
265
    G_MEMSET  = 250,
266
    G_BZERO = 251,
267
    G_VECREDUCE_SEQ_FADD  = 252,
268
    G_VECREDUCE_SEQ_FMUL  = 253,
269
    G_VECREDUCE_FADD  = 254,
270
    G_VECREDUCE_FMUL  = 255,
271
    G_VECREDUCE_FMAX  = 256,
272
    G_VECREDUCE_FMIN  = 257,
273
    G_VECREDUCE_FMAXIMUM  = 258,
274
    G_VECREDUCE_FMINIMUM  = 259,
275
    G_VECREDUCE_ADD = 260,
276
    G_VECREDUCE_MUL = 261,
277
    G_VECREDUCE_AND = 262,
278
    G_VECREDUCE_OR  = 263,
279
    G_VECREDUCE_XOR = 264,
280
    G_VECREDUCE_SMAX  = 265,
281
    G_VECREDUCE_SMIN  = 266,
282
    G_VECREDUCE_UMAX  = 267,
283
    G_VECREDUCE_UMIN  = 268,
284
    G_SBFX  = 269,
285
    G_UBFX  = 270,
286
    ADCWRdRr  = 271,
287
    ADDWRdRr  = 272,
288
    ADJCALLSTACKDOWN  = 273,
289
    ADJCALLSTACKUP  = 274,
290
    ANDIWRdK  = 275,
291
    ANDWRdRr  = 276,
292
    ASRBNRd = 277,
293
    ASRWLoRd  = 278,
294
    ASRWNRd = 279,
295
    ASRWRd  = 280,
296
    Asr16 = 281,
297
    Asr32 = 282,
298
    Asr8  = 283,
299
    AtomicFence = 284,
300
    AtomicLoad16  = 285,
301
    AtomicLoad8 = 286,
302
    AtomicLoadAdd16 = 287,
303
    AtomicLoadAdd8  = 288,
304
    AtomicLoadAnd16 = 289,
305
    AtomicLoadAnd8  = 290,
306
    AtomicLoadOr16  = 291,
307
    AtomicLoadOr8 = 292,
308
    AtomicLoadSub16 = 293,
309
    AtomicLoadSub8  = 294,
310
    AtomicLoadXor16 = 295,
311
    AtomicLoadXor8  = 296,
312
    AtomicStore16 = 297,
313
    AtomicStore8  = 298,
314
    COMWRd  = 299,
315
    CPCWRdRr  = 300,
316
    CPWRdRr = 301,
317
    CopyZero  = 302,
318
    ELPMBRdZ  = 303,
319
    ELPMBRdZPi  = 304,
320
    ELPMWRdZ  = 305,
321
    ELPMWRdZPi  = 306,
322
    EORWRdRr  = 307,
323
    FRMIDX  = 308,
324
    INWRdA  = 309,
325
    LDDWRdPtrQ  = 310,
326
    LDDWRdYQ  = 311,
327
    LDIWRdK = 312,
328
    LDSWRdK = 313,
329
    LDWRdPtr  = 314,
330
    LDWRdPtrPd  = 315,
331
    LDWRdPtrPi  = 316,
332
    LPMBRdZ = 317,
333
    LPMWRdZ = 318,
334
    LPMWRdZPi = 319,
335
    LSLBNRd = 320,
336
    LSLWHiRd  = 321,
337
    LSLWNRd = 322,
338
    LSLWRd  = 323,
339
    LSRBNRd = 324,
340
    LSRWLoRd  = 325,
341
    LSRWNRd = 326,
342
    LSRWRd  = 327,
343
    Lsl16 = 328,
344
    Lsl32 = 329,
345
    Lsl8  = 330,
346
    Lsr16 = 331,
347
    Lsr32 = 332,
348
    Lsr8  = 333,
349
    NEGWRd  = 334,
350
    ORIWRdK = 335,
351
    ORWRdRr = 336,
352
    OUTWARr = 337,
353
    POPWRd  = 338,
354
    PUSHWRr = 339,
355
    ROLBRdR1  = 340,
356
    ROLBRdR17 = 341,
357
    ROLWRd  = 342,
358
    RORBRd  = 343,
359
    RORWRd  = 344,
360
    Rol16 = 345,
361
    Rol8  = 346,
362
    Ror16 = 347,
363
    Ror8  = 348,
364
    SBCIWRdK  = 349,
365
    SBCWRdRr  = 350,
366
    SEXT  = 351,
367
    SPREAD  = 352,
368
    SPWRITE = 353,
369
    STDSPQRr  = 354,
370
    STDWPtrQRr  = 355,
371
    STDWSPQRr = 356,
372
    STSWKRr = 357,
373
    STWPtrPdRr  = 358,
374
    STWPtrPiRr  = 359,
375
    STWPtrRr  = 360,
376
    SUBIWRdK  = 361,
377
    SUBWRdRr  = 362,
378
    Select16  = 363,
379
    Select8 = 364,
380
    ZEXT  = 365,
381
    ADCRdRr = 366,
382
    ADDRdRr = 367,
383
    ADIWRdK = 368,
384
    ANDIRdK = 369,
385
    ANDRdRr = 370,
386
    ASRRd = 371,
387
    BCLRs = 372,
388
    BLD = 373,
389
    BRBCsk  = 374,
390
    BRBSsk  = 375,
391
    BREAK = 376,
392
    BREQk = 377,
393
    BRGEk = 378,
394
    BRLOk = 379,
395
    BRLTk = 380,
396
    BRMIk = 381,
397
    BRNEk = 382,
398
    BRPLk = 383,
399
    BRSHk = 384,
400
    BSETs = 385,
401
    BST = 386,
402
    CALLk = 387,
403
    CBIAb = 388,
404
    COMRd = 389,
405
    CPCRdRr = 390,
406
    CPIRdK  = 391,
407
    CPRdRr  = 392,
408
    CPSE  = 393,
409
    DECRd = 394,
410
    DESK  = 395,
411
    EICALL  = 396,
412
    EIJMP = 397,
413
    ELPM  = 398,
414
    ELPMRdZ = 399,
415
    ELPMRdZPi = 400,
416
    EORRdRr = 401,
417
    FMUL  = 402,
418
    FMULS = 403,
419
    FMULSU  = 404,
420
    ICALL = 405,
421
    IJMP  = 406,
422
    INCRd = 407,
423
    INRdA = 408,
424
    JMPk  = 409,
425
    LACZRd  = 410,
426
    LASZRd  = 411,
427
    LATZRd  = 412,
428
    LDDRdPtrQ = 413,
429
    LDIRdK  = 414,
430
    LDRdPtr = 415,
431
    LDRdPtrPd = 416,
432
    LDRdPtrPi = 417,
433
    LDSRdK  = 418,
434
    LDSRdKTiny  = 419,
435
    LPM = 420,
436
    LPMRdZ  = 421,
437
    LPMRdZPi  = 422,
438
    LSRRd = 423,
439
    MOVRdRr = 424,
440
    MOVWRdRr  = 425,
441
    MULRdRr = 426,
442
    MULSRdRr  = 427,
443
    MULSURdRr = 428,
444
    NEGRd = 429,
445
    NOP = 430,
446
    ORIRdK  = 431,
447
    ORRdRr  = 432,
448
    OUTARr  = 433,
449
    POPRd = 434,
450
    PUSHRr  = 435,
451
    RCALLk  = 436,
452
    RET = 437,
453
    RETI  = 438,
454
    RJMPk = 439,
455
    RORRd = 440,
456
    SBCIRdK = 441,
457
    SBCRdRr = 442,
458
    SBIAb = 443,
459
    SBICAb  = 444,
460
    SBISAb  = 445,
461
    SBIWRdK = 446,
462
    SBRCRrB = 447,
463
    SBRSRrB = 448,
464
    SLEEP = 449,
465
    SPM = 450,
466
    SPMZPi  = 451,
467
    STDPtrQRr = 452,
468
    STPtrPdRr = 453,
469
    STPtrPiRr = 454,
470
    STPtrRr = 455,
471
    STSKRr  = 456,
472
    STSKRrTiny  = 457,
473
    SUBIRdK = 458,
474
    SUBRdRr = 459,
475
    SWAPRd  = 460,
476
    WDR = 461,
477
    XCHZRd  = 462,
478
    INSTRUCTION_LIST_END = 463
479
  };
480
481
} // end namespace AVR
482
} // end namespace llvm
483
#endif // GET_INSTRINFO_ENUM
484
485
#ifdef GET_INSTRINFO_SCHED_ENUM
486
#undef GET_INSTRINFO_SCHED_ENUM
487
namespace llvm {
488
489
namespace AVR {
490
namespace Sched {
491
  enum {
492
    NoInstrModel  = 0,
493
    SCHED_LIST_END = 1
494
  };
495
} // end namespace Sched
496
} // end namespace AVR
497
} // end namespace llvm
498
#endif // GET_INSTRINFO_SCHED_ENUM
499
500
#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
501
namespace llvm {
502
503
struct AVRInstrTable {
504
  MCInstrDesc Insts[463];
505
  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
506
  MCOperandInfo OperandInfo[307];
507
  static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
508
  MCPhysReg ImplicitOps[44];
509
};
510
511
} // end namespace llvm
512
#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
513
514
#ifdef GET_INSTRINFO_MC_DESC
515
#undef GET_INSTRINFO_MC_DESC
516
namespace llvm {
517
518
static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
519
static constexpr unsigned AVRImpOpBase = sizeof AVRInstrTable::OperandInfo / (sizeof(MCPhysReg));
520
521
extern const AVRInstrTable AVRDescs = {
522
  {
523
    { 462,  2,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 211,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #462 = XCHZRd
524
    { 461,  0,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #461 = WDR
525
    { 460,  2,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 226,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #460 = SWAPRd
526
    { 459,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 257,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #459 = SUBRdRr
527
    { 458,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 263,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #458 = SUBIRdK
528
    { 457,  2,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 305,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #457 = STSKRrTiny
529
    { 456,  2,  0,  4,  0,  0,  0,  AVRImpOpBase + 0, 293,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #456 = STSKRr
530
    { 455,  2,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 303,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #455 = STPtrRr
531
    { 454,  4,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 299,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #454 = STPtrPiRr
532
    { 453,  4,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 299,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #453 = STPtrPdRr
533
    { 452,  3,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 296,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #452 = STDPtrQRr
534
    { 451,  1,  0,  2,  0,  2,  1,  AVRImpOpBase + 41,  295,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #451 = SPMZPi
535
    { 450,  0,  0,  2,  0,  3,  0,  AVRImpOpBase + 38,  1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #450 = SPM
536
    { 449,  0,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #449 = SLEEP
537
    { 448,  2,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 271,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #448 = SBRSRrB
538
    { 447,  2,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 271,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #447 = SBRCRrB
539
    { 446,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 260,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #446 = SBIWRdK
540
    { 445,  2,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 273,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #445 = SBISAb
541
    { 444,  2,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 273,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #444 = SBICAb
542
    { 443,  2,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 273,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #443 = SBIAb
543
    { 442,  3,  1,  2,  0,  1,  1,  AVRImpOpBase + 0, 257,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #442 = SBCRdRr
544
    { 441,  3,  1,  2,  0,  1,  1,  AVRImpOpBase + 0, 263,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #441 = SBCIRdK
545
    { 440,  2,  1,  2,  0,  1,  1,  AVRImpOpBase + 0, 226,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #440 = RORRd
546
    { 439,  1,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #439 = RJMPk
547
    { 438,  0,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #438 = RETI
548
    { 437,  0,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #437 = RET
549
    { 436,  1,  0,  2,  0,  1,  0,  AVRImpOpBase + 16,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #436 = RCALLk
550
    { 435,  1,  0,  2,  0,  1,  1,  AVRImpOpBase + 10,  181,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #435 = PUSHRr
551
    { 434,  1,  1,  2,  0,  1,  1,  AVRImpOpBase + 10,  181,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #434 = POPRd
552
    { 433,  2,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 293,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #433 = OUTARr
553
    { 432,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 257,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #432 = ORRdRr
554
    { 431,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 263,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #431 = ORIRdK
555
    { 430,  0,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #430 = NOP
556
    { 429,  2,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 226,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #429 = NEGRd
557
    { 428,  2,  0,  2,  0,  0,  3,  AVRImpOpBase + 35,  279,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #428 = MULSURdRr
558
    { 427,  2,  0,  2,  0,  0,  3,  AVRImpOpBase + 35,  291,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #427 = MULSRdRr
559
    { 426,  2,  0,  2,  0,  0,  3,  AVRImpOpBase + 35,  275,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #426 = MULRdRr
560
    { 425,  2,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 179,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #425 = MOVWRdRr
561
    { 424,  2,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 275,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #424 = MOVRdRr
562
    { 423,  2,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 226,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #423 = LSRRd
563
    { 422,  2,  1,  2,  0,  0,  1,  AVRImpOpBase + 9, 211,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #422 = LPMRdZPi
564
    { 421,  2,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 211,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #421 = LPMRdZ
565
    { 420,  0,  0,  2,  0,  1,  1,  AVRImpOpBase + 33,  1,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #420 = LPM
566
    { 419,  2,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 277,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #419 = LDSRdKTiny
567
    { 418,  2,  1,  4,  0,  0,  0,  AVRImpOpBase + 0, 281,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #418 = LDSRdK
568
    { 417,  3,  2,  2,  0,  0,  0,  AVRImpOpBase + 0, 288,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #417 = LDRdPtrPi
569
    { 416,  3,  2,  2,  0,  0,  0,  AVRImpOpBase + 0, 288,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #416 = LDRdPtrPd
570
    { 415,  2,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 286,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #415 = LDRdPtr
571
    { 414,  2,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 277,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #414 = LDIRdK
572
    { 413,  3,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 283,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #413 = LDDRdPtrQ
573
    { 412,  2,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 211,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #412 = LATZRd
574
    { 411,  2,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 211,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #411 = LASZRd
575
    { 410,  2,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 211,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #410 = LACZRd
576
    { 409,  1,  0,  4,  0,  0,  0,  AVRImpOpBase + 0, 0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #409 = JMPk
577
    { 408,  2,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 281,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #408 = INRdA
578
    { 407,  2,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 226,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #407 = INCRd
579
    { 406,  0,  0,  2,  0,  1,  0,  AVRImpOpBase + 9, 1,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #406 = IJMP
580
    { 405,  0,  0,  2,  0,  2,  0,  AVRImpOpBase + 6, 1,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #405 = ICALL
581
    { 404,  2,  0,  2,  0,  0,  3,  AVRImpOpBase + 35,  279,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #404 = FMULSU
582
    { 403,  2,  0,  2,  0,  0,  3,  AVRImpOpBase + 35,  279,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #403 = FMULS
583
    { 402,  2,  0,  2,  0,  0,  3,  AVRImpOpBase + 35,  279,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #402 = FMUL
584
    { 401,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 257,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #401 = EORRdRr
585
    { 400,  2,  1,  2,  0,  0,  1,  AVRImpOpBase + 9, 211,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #400 = ELPMRdZPi
586
    { 399,  2,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 211,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #399 = ELPMRdZ
587
    { 398,  0,  0,  2,  0,  1,  1,  AVRImpOpBase + 33,  1,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #398 = ELPM
588
    { 397,  0,  0,  2,  0,  1,  0,  AVRImpOpBase + 9, 1,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #397 = EIJMP
589
    { 396,  0,  0,  2,  0,  2,  0,  AVRImpOpBase + 6, 1,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #396 = EICALL
590
    { 395,  1,  0,  2,  0,  0,  16, AVRImpOpBase + 17,  1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #395 = DESK
591
    { 394,  2,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 226,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #394 = DECRd
592
    { 393,  2,  0,  2,  0,  0,  1,  AVRImpOpBase + 2, 275,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #393 = CPSE
593
    { 392,  2,  0,  2,  0,  0,  1,  AVRImpOpBase + 2, 275,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #392 = CPRdRr
594
    { 391,  2,  0,  2,  0,  0,  1,  AVRImpOpBase + 2, 277,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #391 = CPIRdK
595
    { 390,  2,  0,  2,  0,  1,  1,  AVRImpOpBase + 0, 275,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #390 = CPCRdRr
596
    { 389,  2,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 226,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #389 = COMRd
597
    { 388,  2,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 273,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #388 = CBIAb
598
    { 387,  1,  0,  4,  0,  1,  0,  AVRImpOpBase + 16,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #387 = CALLk
599
    { 386,  2,  0,  2,  0,  0,  1,  AVRImpOpBase + 2, 271,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #386 = BST
600
    { 385,  1,  0,  2,  0,  0,  1,  AVRImpOpBase + 2, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #385 = BSETs
601
    { 384,  1,  0,  2,  0,  1,  0,  AVRImpOpBase + 2, 0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #384 = BRSHk
602
    { 383,  1,  0,  2,  0,  1,  0,  AVRImpOpBase + 2, 0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #383 = BRPLk
603
    { 382,  1,  0,  2,  0,  1,  0,  AVRImpOpBase + 2, 0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #382 = BRNEk
604
    { 381,  1,  0,  2,  0,  1,  0,  AVRImpOpBase + 2, 0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #381 = BRMIk
605
    { 380,  1,  0,  2,  0,  1,  0,  AVRImpOpBase + 2, 0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #380 = BRLTk
606
    { 379,  1,  0,  2,  0,  1,  0,  AVRImpOpBase + 2, 0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #379 = BRLOk
607
    { 378,  1,  0,  2,  0,  1,  0,  AVRImpOpBase + 2, 0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #378 = BRGEk
608
    { 377,  1,  0,  2,  0,  1,  0,  AVRImpOpBase + 2, 0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #377 = BREQk
609
    { 376,  0,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #376 = BREAK
610
    { 375,  2,  0,  2,  0,  1,  0,  AVRImpOpBase + 2, 269,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #375 = BRBSsk
611
    { 374,  2,  0,  2,  0,  1,  0,  AVRImpOpBase + 2, 269,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #374 = BRBCsk
612
    { 373,  3,  1,  2,  0,  1,  0,  AVRImpOpBase + 2, 266,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #373 = BLD
613
    { 372,  1,  0,  2,  0,  0,  1,  AVRImpOpBase + 2, 1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #372 = BCLRs
614
    { 371,  2,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 226,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #371 = ASRRd
615
    { 370,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 257,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #370 = ANDRdRr
616
    { 369,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 263,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #369 = ANDIRdK
617
    { 368,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 260,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #368 = ADIWRdK
618
    { 367,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 257,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #367 = ADDRdRr
619
    { 366,  3,  1,  2,  0,  1,  1,  AVRImpOpBase + 0, 257,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #366 = ADCRdRr
620
    { 365,  2,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 228,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #365 = ZEXT
621
    { 364,  4,  1,  2,  0,  1,  0,  AVRImpOpBase + 2, 253,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #364 = Select8
622
    { 363,  4,  1,  2,  0,  1,  0,  AVRImpOpBase + 2, 249,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #363 = Select16
623
    { 362,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #362 = SUBWRdRr
624
    { 361,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 143,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #361 = SUBIWRdK
625
    { 360,  2,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 175,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #360 = STWPtrRr
626
    { 359,  4,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 245,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #359 = STWPtrPiRr
627
    { 358,  4,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 245,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #358 = STWPtrPdRr
628
    { 357,  2,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 243,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #357 = STSWKRr
629
    { 356,  3,  0,  2,  0,  0,  1,  AVRImpOpBase + 16,  240,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #356 = STDWSPQRr
630
    { 355,  3,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 237,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #355 = STDWPtrQRr
631
    { 354,  3,  0,  2,  0,  0,  1,  AVRImpOpBase + 16,  234,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #354 = STDSPQRr
632
    { 353,  2,  1,  2,  0,  0,  1,  AVRImpOpBase + 16,  232,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #353 = SPWRITE
633
    { 352,  2,  1,  2,  0,  1,  0,  AVRImpOpBase + 16,  230,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #352 = SPREAD
634
    { 351,  2,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 228,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #351 = SEXT
635
    { 350,  3,  1,  2,  0,  1,  1,  AVRImpOpBase + 0, 140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #350 = SBCWRdRr
636
    { 349,  3,  1,  2,  0,  1,  1,  AVRImpOpBase + 0, 143,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #349 = SBCIWRdK
637
    { 348,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 162,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #348 = Ror8
638
    { 347,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 154,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #347 = Ror16
639
    { 346,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 162,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #346 = Rol8
640
    { 345,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 154,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #345 = Rol16
641
    { 344,  2,  1,  2,  0,  1,  1,  AVRImpOpBase + 0, 149,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #344 = RORWRd
642
    { 343,  2,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 226,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #343 = RORBRd
643
    { 342,  2,  1,  2,  0,  1,  1,  AVRImpOpBase + 0, 149,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #342 = ROLWRd
644
    { 341,  2,  1,  2,  0,  1,  1,  AVRImpOpBase + 14,  226,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #341 = ROLBRdR17
645
    { 340,  2,  1,  2,  0,  1,  1,  AVRImpOpBase + 12,  226,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #340 = ROLBRdR1
646
    { 339,  1,  0,  2,  0,  1,  1,  AVRImpOpBase + 10,  225,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #339 = PUSHWRr
647
    { 338,  1,  1,  2,  0,  1,  1,  AVRImpOpBase + 10,  225,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #338 = POPWRd
648
    { 337,  2,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 223,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #337 = OUTWARr
649
    { 336,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #336 = ORWRdRr
650
    { 335,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 143,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #335 = ORIWRdK
651
    { 334,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 220,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #334 = NEGWRd
652
    { 333,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 162,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #333 = Lsr8
653
    { 332,  5,  2,  2,  0,  0,  1,  AVRImpOpBase + 2, 157,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #332 = Lsr32
654
    { 331,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 154,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #331 = Lsr16
655
    { 330,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 162,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #330 = Lsl8
656
    { 329,  5,  2,  2,  0,  0,  1,  AVRImpOpBase + 2, 157,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #329 = Lsl32
657
    { 328,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 154,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #328 = Lsl16
658
    { 327,  2,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 149,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #327 = LSRWRd
659
    { 326,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 217,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #326 = LSRWNRd
660
    { 325,  2,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 149,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #325 = LSRWLoRd
661
    { 324,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 146,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #324 = LSRBNRd
662
    { 323,  2,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 149,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #323 = LSLWRd
663
    { 322,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 217,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #322 = LSLWNRd
664
    { 321,  2,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 149,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #321 = LSLWHiRd
665
    { 320,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 146,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #320 = LSLBNRd
666
    { 319,  2,  1,  2,  0,  0,  1,  AVRImpOpBase + 9, 215,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #319 = LPMWRdZPi
667
    { 318,  2,  1,  2,  0,  0,  1,  AVRImpOpBase + 8, 213,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #318 = LPMWRdZ
668
    { 317,  2,  1,  2,  0,  0,  1,  AVRImpOpBase + 8, 211,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #317 = LPMBRdZ
669
    { 316,  3,  2,  2,  0,  0,  0,  AVRImpOpBase + 0, 208,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #316 = LDWRdPtrPi
670
    { 315,  3,  2,  2,  0,  0,  0,  AVRImpOpBase + 0, 208,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #315 = LDWRdPtrPd
671
    { 314,  2,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 206,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #314 = LDWRdPtr
672
    { 313,  2,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 204,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #313 = LDSWRdK
673
    { 312,  2,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 202,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #312 = LDIWRdK
674
    { 311,  3,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 199,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #311 = LDDWRdYQ
675
    { 310,  3,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 196,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #310 = LDDWRdPtrQ
676
    { 309,  2,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 194,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #309 = INWRdA
677
    { 308,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 191,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #308 = FRMIDX
678
    { 307,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #307 = EORWRdRr
679
    { 306,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 9, 188,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #306 = ELPMWRdZPi
680
    { 305,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 8, 185,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #305 = ELPMWRdZ
681
    { 304,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 9, 182,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #304 = ELPMBRdZPi
682
    { 303,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 8, 182,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #303 = ELPMBRdZ
683
    { 302,  1,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 181,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #302 = CopyZero
684
    { 301,  2,  0,  2,  0,  0,  1,  AVRImpOpBase + 2, 179,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #301 = CPWRdRr
685
    { 300,  2,  0,  2,  0,  1,  1,  AVRImpOpBase + 0, 179,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #300 = CPCWRdRr
686
    { 299,  2,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 149,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #299 = COMWRd
687
    { 298,  2,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 177,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #298 = AtomicStore8
688
    { 297,  2,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 175,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #297 = AtomicStore16
689
    { 296,  3,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 172,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #296 = AtomicLoadXor8
690
    { 295,  3,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 169,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #295 = AtomicLoadXor16
691
    { 294,  3,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 172,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #294 = AtomicLoadSub8
692
    { 293,  3,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 169,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #293 = AtomicLoadSub16
693
    { 292,  3,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 172,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #292 = AtomicLoadOr8
694
    { 291,  3,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 169,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #291 = AtomicLoadOr16
695
    { 290,  3,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 172,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #290 = AtomicLoadAnd8
696
    { 289,  3,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 169,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #289 = AtomicLoadAnd16
697
    { 288,  3,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 172,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #288 = AtomicLoadAdd8
698
    { 287,  3,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 169,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #287 = AtomicLoadAdd16
699
    { 286,  2,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 167,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #286 = AtomicLoad8
700
    { 285,  2,  1,  2,  0,  0,  0,  AVRImpOpBase + 0, 165,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #285 = AtomicLoad16
701
    { 284,  0,  0,  2,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #284 = AtomicFence
702
    { 283,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 162,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #283 = Asr8
703
    { 282,  5,  2,  2,  0,  0,  1,  AVRImpOpBase + 2, 157,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #282 = Asr32
704
    { 281,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 154,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #281 = Asr16
705
    { 280,  2,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 149,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #280 = ASRWRd
706
    { 279,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 151,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #279 = ASRWNRd
707
    { 278,  2,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 149,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #278 = ASRWLoRd
708
    { 277,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 146,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #277 = ASRBNRd
709
    { 276,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #276 = ANDWRdRr
710
    { 275,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 143,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #275 = ANDIWRdK
711
    { 274,  2,  0,  2,  0,  1,  1,  AVRImpOpBase + 6, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #274 = ADJCALLSTACKUP
712
    { 273,  2,  0,  2,  0,  1,  2,  AVRImpOpBase + 3, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #273 = ADJCALLSTACKDOWN
713
    { 272,  3,  1,  2,  0,  0,  1,  AVRImpOpBase + 2, 140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #272 = ADDWRdRr
714
    { 271,  3,  1,  2,  0,  1,  1,  AVRImpOpBase + 0, 140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #271 = ADCWRdRr
715
    { 270,  4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 136,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #270 = G_UBFX
716
    { 269,  4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 136,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #269 = G_SBFX
717
    { 268,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #268 = G_VECREDUCE_UMIN
718
    { 267,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #267 = G_VECREDUCE_UMAX
719
    { 266,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #266 = G_VECREDUCE_SMIN
720
    { 265,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #265 = G_VECREDUCE_SMAX
721
    { 264,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #264 = G_VECREDUCE_XOR
722
    { 263,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #263 = G_VECREDUCE_OR
723
    { 262,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #262 = G_VECREDUCE_AND
724
    { 261,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #261 = G_VECREDUCE_MUL
725
    { 260,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #260 = G_VECREDUCE_ADD
726
    { 259,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #259 = G_VECREDUCE_FMINIMUM
727
    { 258,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #258 = G_VECREDUCE_FMAXIMUM
728
    { 257,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #257 = G_VECREDUCE_FMIN
729
    { 256,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #256 = G_VECREDUCE_FMAX
730
    { 255,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #255 = G_VECREDUCE_FMUL
731
    { 254,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #254 = G_VECREDUCE_FADD
732
    { 253,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #253 = G_VECREDUCE_SEQ_FMUL
733
    { 252,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #252 = G_VECREDUCE_SEQ_FADD
734
    { 251,  3,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #251 = G_BZERO
735
    { 250,  4,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #250 = G_MEMSET
736
    { 249,  4,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #249 = G_MEMMOVE
737
    { 248,  3,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #248 = G_MEMCPY_INLINE
738
    { 247,  4,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #247 = G_MEMCPY
739
    { 246,  2,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 130,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #246 = G_WRITE_REGISTER
740
    { 245,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #245 = G_READ_REGISTER
741
    { 244,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #244 = G_STRICT_FLDEXP
742
    { 243,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #243 = G_STRICT_FSQRT
743
    { 242,  4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #242 = G_STRICT_FMA
744
    { 241,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #241 = G_STRICT_FREM
745
    { 240,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #240 = G_STRICT_FDIV
746
    { 239,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #239 = G_STRICT_FMUL
747
    { 238,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #238 = G_STRICT_FSUB
748
    { 237,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #237 = G_STRICT_FADD
749
    { 236,  1,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #236 = G_STACKRESTORE
750
    { 235,  1,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #235 = G_STACKSAVE
751
    { 234,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 64, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #234 = G_DYN_STACKALLOC
752
    { 233,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #233 = G_JUMP_TABLE
753
    { 232,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #232 = G_BLOCK_ADDR
754
    { 231,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #231 = G_ADDRSPACE_CAST
755
    { 230,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #230 = G_FNEARBYINT
756
    { 229,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #229 = G_FRINT
757
    { 228,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #228 = G_FFLOOR
758
    { 227,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #227 = G_FSQRT
759
    { 226,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #226 = G_FSIN
760
    { 225,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #225 = G_FCOS
761
    { 224,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #224 = G_FCEIL
762
    { 223,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #223 = G_BITREVERSE
763
    { 222,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #222 = G_BSWAP
764
    { 221,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #221 = G_CTPOP
765
    { 220,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #220 = G_CTLZ_ZERO_UNDEF
766
    { 219,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #219 = G_CTLZ
767
    { 218,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #218 = G_CTTZ_ZERO_UNDEF
768
    { 217,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #217 = G_CTTZ
769
    { 216,  4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 126,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #216 = G_SHUFFLE_VECTOR
770
    { 215,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #215 = G_EXTRACT_VECTOR_ELT
771
    { 214,  4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 119,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #214 = G_INSERT_VECTOR_ELT
772
    { 213,  3,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 116,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #213 = G_BRJT
773
    { 212,  1,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #212 = G_BR
774
    { 211,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #211 = G_LLROUND
775
    { 210,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #210 = G_LROUND
776
    { 209,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #209 = G_ABS
777
    { 208,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #208 = G_UMAX
778
    { 207,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #207 = G_UMIN
779
    { 206,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #206 = G_SMAX
780
    { 205,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #205 = G_SMIN
781
    { 204,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #204 = G_PTRMASK
782
    { 203,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #203 = G_PTR_ADD
783
    { 202,  0,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #202 = G_RESET_FPMODE
784
    { 201,  1,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #201 = G_SET_FPMODE
785
    { 200,  1,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #200 = G_GET_FPMODE
786
    { 199,  0,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #199 = G_RESET_FPENV
787
    { 198,  1,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #198 = G_SET_FPENV
788
    { 197,  1,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #197 = G_GET_FPENV
789
    { 196,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #196 = G_FMAXIMUM
790
    { 195,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #195 = G_FMINIMUM
791
    { 194,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #194 = G_FMAXNUM_IEEE
792
    { 193,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #193 = G_FMINNUM_IEEE
793
    { 192,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #192 = G_FMAXNUM
794
    { 191,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #191 = G_FMINNUM
795
    { 190,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #190 = G_FCANONICALIZE
796
    { 189,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 93, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #189 = G_IS_FPCLASS
797
    { 188,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #188 = G_FCOPYSIGN
798
    { 187,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #187 = G_FABS
799
    { 186,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #186 = G_UITOFP
800
    { 185,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #185 = G_SITOFP
801
    { 184,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #184 = G_FPTOUI
802
    { 183,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #183 = G_FPTOSI
803
    { 182,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #182 = G_FPTRUNC
804
    { 181,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #181 = G_FPEXT
805
    { 180,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #180 = G_FNEG
806
    { 179,  3,  2,  0,  0,  0,  0,  AVRImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #179 = G_FFREXP
807
    { 178,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #178 = G_FLDEXP
808
    { 177,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #177 = G_FLOG10
809
    { 176,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #176 = G_FLOG2
810
    { 175,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #175 = G_FLOG
811
    { 174,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #174 = G_FEXP10
812
    { 173,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #173 = G_FEXP2
813
    { 172,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #172 = G_FEXP
814
    { 171,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #171 = G_FPOWI
815
    { 170,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #170 = G_FPOW
816
    { 169,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #169 = G_FREM
817
    { 168,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #168 = G_FDIV
818
    { 167,  4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #167 = G_FMAD
819
    { 166,  4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #166 = G_FMA
820
    { 165,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #165 = G_FMUL
821
    { 164,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #164 = G_FSUB
822
    { 163,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #163 = G_FADD
823
    { 162,  4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #162 = G_UDIVFIXSAT
824
    { 161,  4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #161 = G_SDIVFIXSAT
825
    { 160,  4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #160 = G_UDIVFIX
826
    { 159,  4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #159 = G_SDIVFIX
827
    { 158,  4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #158 = G_UMULFIXSAT
828
    { 157,  4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #157 = G_SMULFIXSAT
829
    { 156,  4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #156 = G_UMULFIX
830
    { 155,  4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #155 = G_SMULFIX
831
    { 154,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #154 = G_SSHLSAT
832
    { 153,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #153 = G_USHLSAT
833
    { 152,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #152 = G_SSUBSAT
834
    { 151,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #151 = G_USUBSAT
835
    { 150,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #150 = G_SADDSAT
836
    { 149,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #149 = G_UADDSAT
837
    { 148,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #148 = G_SMULH
838
    { 147,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #147 = G_UMULH
839
    { 146,  4,  2,  0,  0,  0,  0,  AVRImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #146 = G_SMULO
840
    { 145,  4,  2,  0,  0,  0,  0,  AVRImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #145 = G_UMULO
841
    { 144,  5,  2,  0,  0,  0,  0,  AVRImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #144 = G_SSUBE
842
    { 143,  4,  2,  0,  0,  0,  0,  AVRImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #143 = G_SSUBO
843
    { 142,  5,  2,  0,  0,  0,  0,  AVRImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #142 = G_SADDE
844
    { 141,  4,  2,  0,  0,  0,  0,  AVRImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #141 = G_SADDO
845
    { 140,  5,  2,  0,  0,  0,  0,  AVRImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #140 = G_USUBE
846
    { 139,  4,  2,  0,  0,  0,  0,  AVRImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #139 = G_USUBO
847
    { 138,  5,  2,  0,  0,  0,  0,  AVRImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #138 = G_UADDE
848
    { 137,  4,  2,  0,  0,  0,  0,  AVRImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #137 = G_UADDO
849
    { 136,  4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #136 = G_SELECT
850
    { 135,  4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 103,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #135 = G_FCMP
851
    { 134,  4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 103,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #134 = G_ICMP
852
    { 133,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #133 = G_ROTL
853
    { 132,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #132 = G_ROTR
854
    { 131,  4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 99, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #131 = G_FSHR
855
    { 130,  4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 99, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #130 = G_FSHL
856
    { 129,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #129 = G_ASHR
857
    { 128,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #128 = G_LSHR
858
    { 127,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #127 = G_SHL
859
    { 126,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #126 = G_ZEXT
860
    { 125,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #125 = G_SEXT_INREG
861
    { 124,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #124 = G_SEXT
862
    { 123,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 93, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #123 = G_VAARG
863
    { 122,  1,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #122 = G_VASTART
864
    { 121,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #121 = G_FCONSTANT
865
    { 120,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #120 = G_CONSTANT
866
    { 119,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #119 = G_TRUNC
867
    { 118,  2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #118 = G_ANYEXT
868
    { 117,  1,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #117 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
869
    { 116,  1,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #116 = G_INTRINSIC_CONVERGENT
870
    { 115,  1,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #115 = G_INTRINSIC_W_SIDE_EFFECTS
871
    { 114,  1,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #114 = G_INTRINSIC
872
    { 113,  0,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #113 = G_INVOKE_REGION_START
873
    { 112,  1,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #112 = G_BRINDIRECT
874
    { 111,  2,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #111 = G_BRCOND
875
    { 110,  4,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 89, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #110 = G_PREFETCH
876
    { 109,  2,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #109 = G_FENCE
877
    { 108,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #108 = G_ATOMICRMW_UDEC_WRAP
878
    { 107,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #107 = G_ATOMICRMW_UINC_WRAP
879
    { 106,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #106 = G_ATOMICRMW_FMIN
880
    { 105,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #105 = G_ATOMICRMW_FMAX
881
    { 104,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #104 = G_ATOMICRMW_FSUB
882
    { 103,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #103 = G_ATOMICRMW_FADD
883
    { 102,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #102 = G_ATOMICRMW_UMIN
884
    { 101,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #101 = G_ATOMICRMW_UMAX
885
    { 100,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #100 = G_ATOMICRMW_MIN
886
    { 99, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #99 = G_ATOMICRMW_MAX
887
    { 98, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #98 = G_ATOMICRMW_XOR
888
    { 97, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #97 = G_ATOMICRMW_OR
889
    { 96, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #96 = G_ATOMICRMW_NAND
890
    { 95, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #95 = G_ATOMICRMW_AND
891
    { 94, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #94 = G_ATOMICRMW_SUB
892
    { 93, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #93 = G_ATOMICRMW_ADD
893
    { 92, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #92 = G_ATOMICRMW_XCHG
894
    { 91, 4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #91 = G_ATOMIC_CMPXCHG
895
    { 90, 5,  2,  0,  0,  0,  0,  AVRImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #90 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
896
    { 89, 5,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #89 = G_INDEXED_STORE
897
    { 88, 2,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #88 = G_STORE
898
    { 87, 5,  2,  0,  0,  0,  0,  AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #87 = G_INDEXED_ZEXTLOAD
899
    { 86, 5,  2,  0,  0,  0,  0,  AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #86 = G_INDEXED_SEXTLOAD
900
    { 85, 5,  2,  0,  0,  0,  0,  AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #85 = G_INDEXED_LOAD
901
    { 84, 2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #84 = G_ZEXTLOAD
902
    { 83, 2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #83 = G_SEXTLOAD
903
    { 82, 2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #82 = G_LOAD
904
    { 81, 1,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #81 = G_READCYCLECOUNTER
905
    { 80, 2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #80 = G_INTRINSIC_ROUNDEVEN
906
    { 79, 2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #79 = G_INTRINSIC_LRINT
907
    { 78, 2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #78 = G_INTRINSIC_ROUND
908
    { 77, 2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #77 = G_INTRINSIC_TRUNC
909
    { 76, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 64, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #76 = G_INTRINSIC_FPTRUNC_ROUND
910
    { 75, 2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #75 = G_CONSTANT_FOLD_BARRIER
911
    { 74, 2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #74 = G_FREEZE
912
    { 73, 2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #73 = G_BITCAST
913
    { 72, 2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #72 = G_INTTOPTR
914
    { 71, 2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #71 = G_PTRTOINT
915
    { 70, 2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #70 = G_CONCAT_VECTORS
916
    { 69, 2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #69 = G_BUILD_VECTOR_TRUNC
917
    { 68, 2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #68 = G_BUILD_VECTOR
918
    { 67, 2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #67 = G_MERGE_VALUES
919
    { 66, 4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #66 = G_INSERT
920
    { 65, 2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #65 = G_UNMERGE_VALUES
921
    { 64, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #64 = G_EXTRACT
922
    { 63, 2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #63 = G_CONSTANT_POOL
923
    { 62, 2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #62 = G_GLOBAL_VALUE
924
    { 61, 2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #61 = G_FRAME_INDEX
925
    { 60, 1,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #60 = G_PHI
926
    { 59, 1,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #59 = G_IMPLICIT_DEF
927
    { 58, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #58 = G_XOR
928
    { 57, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #57 = G_OR
929
    { 56, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #56 = G_AND
930
    { 55, 4,  2,  0,  0,  0,  0,  AVRImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #55 = G_UDIVREM
931
    { 54, 4,  2,  0,  0,  0,  0,  AVRImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #54 = G_SDIVREM
932
    { 53, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #53 = G_UREM
933
    { 52, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #52 = G_SREM
934
    { 51, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #51 = G_UDIV
935
    { 50, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #50 = G_SDIV
936
    { 49, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #49 = G_MUL
937
    { 48, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #48 = G_SUB
938
    { 47, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #47 = G_ADD
939
    { 46, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #46 = G_ASSERT_ALIGN
940
    { 45, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #45 = G_ASSERT_ZEXT
941
    { 44, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #44 = G_ASSERT_SEXT
942
    { 43, 1,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #43 = JUMP_TABLE_DEBUG_INFO
943
    { 42, 0,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #42 = MEMBARRIER
944
    { 41, 0,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #41 = ICALL_BRANCH_FUNNEL
945
    { 40, 3,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
946
    { 39, 2,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #39 = PATCHABLE_EVENT_CALL
947
    { 38, 0,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #38 = PATCHABLE_TAIL_CALL
948
    { 37, 0,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #37 = PATCHABLE_FUNCTION_EXIT
949
    { 36, 0,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #36 = PATCHABLE_RET
950
    { 35, 0,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #35 = PATCHABLE_FUNCTION_ENTER
951
    { 34, 0,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #34 = PATCHABLE_OP
952
    { 33, 1,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #33 = FAULTING_OP
953
    { 32, 2,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #32 = LOCAL_ESCAPE
954
    { 31, 0,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #31 = STATEPOINT
955
    { 30, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #30 = PREALLOCATED_ARG
956
    { 29, 1,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #29 = PREALLOCATED_SETUP
957
    { 28, 1,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #28 = LOAD_STACK_GUARD
958
    { 27, 6,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #27 = PATCHPOINT
959
    { 26, 0,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #26 = FENTRY_CALL
960
    { 25, 2,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #25 = STACKMAP
961
    { 24, 2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #24 = ARITH_FENCE
962
    { 23, 4,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #23 = PSEUDO_PROBE
963
    { 22, 1,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #22 = LIFETIME_END
964
    { 21, 1,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #21 = LIFETIME_START
965
    { 20, 0,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #20 = BUNDLE
966
    { 19, 2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #19 = COPY
967
    { 18, 2,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #18 = REG_SEQUENCE
968
    { 17, 1,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #17 = DBG_LABEL
969
    { 16, 0,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #16 = DBG_PHI
970
    { 15, 0,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #15 = DBG_INSTR_REF
971
    { 14, 0,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #14 = DBG_VALUE_LIST
972
    { 13, 0,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #13 = DBG_VALUE
973
    { 12, 3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 2,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #12 = COPY_TO_REGCLASS
974
    { 11, 4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 9,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #11 = SUBREG_TO_REG
975
    { 10, 1,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #10 = IMPLICIT_DEF
976
    { 9,  4,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 5,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #9 = INSERT_SUBREG
977
    { 8,  3,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 2,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #8 = EXTRACT_SUBREG
978
    { 7,  0,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #7 = KILL
979
    { 6,  1,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #6 = ANNOTATION_LABEL
980
    { 5,  1,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #5 = GC_LABEL
981
    { 4,  1,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #4 = EH_LABEL
982
    { 3,  1,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #3 = CFI_INSTRUCTION
983
    { 2,  0,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #2 = INLINEASM_BR
984
    { 1,  0,  0,  0,  0,  0,  0,  AVRImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1 = INLINEASM
985
    { 0,  1,  1,  0,  0,  0,  0,  AVRImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #0 = PHI
986
  }, {
987
    /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
988
    /* 1 */
989
    /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
990
    /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
991
    /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
992
    /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
993
    /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
994
    /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
995
    /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
996
    /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
997
    /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
998
    /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
999
    /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1000
    /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1001
    /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1002
    /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1003
    /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1004
    /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1005
    /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1006
    /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1007
    /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1008
    /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1009
    /* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1010
    /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1011
    /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1012
    /* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1013
    /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1014
    /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1015
    /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1016
    /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1017
    /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1018
    /* 89 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1019
    /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1020
    /* 96 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1021
    /* 99 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1022
    /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1023
    /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1024
    /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1025
    /* 116 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1026
    /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1027
    /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1028
    /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1029
    /* 130 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1030
    /* 132 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1031
    /* 136 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1032
    /* 140 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1033
    /* 143 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1034
    /* 146 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1035
    /* 149 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1036
    /* 151 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1037
    /* 154 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1038
    /* 157 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1039
    /* 162 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1040
    /* 165 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1041
    /* 167 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1042
    /* 169 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1043
    /* 172 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1044
    /* 175 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1045
    /* 177 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1046
    /* 179 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1047
    /* 181 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1048
    /* 182 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1049
    /* 185 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1050
    /* 188 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1051
    /* 191 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1052
    /* 194 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1053
    /* 196 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1054
    /* 199 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1055
    /* 202 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1056
    /* 204 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1057
    /* 206 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1058
    /* 208 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) },
1059
    /* 211 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1060
    /* 213 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1061
    /* 215 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1062
    /* 217 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1063
    /* 220 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1064
    /* 223 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1065
    /* 225 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1066
    /* 226 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1067
    /* 228 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1068
    /* 230 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1069
    /* 232 */ { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1070
    /* 234 */ { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1071
    /* 237 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1072
    /* 240 */ { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1073
    /* 243 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1074
    /* 245 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1075
    /* 249 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1076
    /* 253 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1077
    /* 257 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1078
    /* 260 */ { AVR::IWREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::IWREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1079
    /* 263 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1080
    /* 266 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1081
    /* 269 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1082
    /* 271 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1083
    /* 273 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1084
    /* 275 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1085
    /* 277 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1086
    /* 279 */ { AVR::LD8loRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8loRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1087
    /* 281 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1088
    /* 283 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1089
    /* 286 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1090
    /* 288 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1091
    /* 291 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1092
    /* 293 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1093
    /* 295 */ { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1094
    /* 296 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1095
    /* 299 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1096
    /* 303 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1097
    /* 305 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1098
  }, {
1099
    /* 0 */
1100
    /* 0 */ AVR::SREG, AVR::SREG,
1101
    /* 2 */ AVR::SREG,
1102
    /* 3 */ AVR::SP, AVR::SP, AVR::SREG,
1103
    /* 6 */ AVR::SP, AVR::R31R30,
1104
    /* 8 */ AVR::R0,
1105
    /* 9 */ AVR::R31R30,
1106
    /* 10 */ AVR::SP, AVR::SP,
1107
    /* 12 */ AVR::R1, AVR::SREG,
1108
    /* 14 */ AVR::R17, AVR::SREG,
1109
    /* 16 */ AVR::SP,
1110
    /* 17 */ AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R1, AVR::R0,
1111
    /* 33 */ AVR::R31R30, AVR::R0,
1112
    /* 35 */ AVR::R1, AVR::R0, AVR::SREG,
1113
    /* 38 */ AVR::R31R30, AVR::R1, AVR::R0,
1114
    /* 41 */ AVR::R1, AVR::R0, AVR::R31R30,
1115
  }
1116
};
1117
1118
1119
#ifdef __GNUC__
1120
#pragma GCC diagnostic push
1121
#pragma GCC diagnostic ignored "-Woverlength-strings"
1122
#endif
1123
extern const char AVRInstrNameData[] = {
1124
  /* 0 */ "G_FLOG10\0"
1125
  /* 9 */ "G_FEXP10\0"
1126
  /* 18 */ "ROLBRdR1\0"
1127
  /* 27 */ "Lsl32\0"
1128
  /* 33 */ "Asr32\0"
1129
  /* 39 */ "Lsr32\0"
1130
  /* 45 */ "G_FLOG2\0"
1131
  /* 53 */ "G_FEXP2\0"
1132
  /* 61 */ "AtomicLoadSub16\0"
1133
  /* 77 */ "AtomicLoad16\0"
1134
  /* 90 */ "AtomicLoadAdd16\0"
1135
  /* 106 */ "AtomicLoadAnd16\0"
1136
  /* 122 */ "AtomicStore16\0"
1137
  /* 136 */ "Rol16\0"
1138
  /* 142 */ "Lsl16\0"
1139
  /* 148 */ "AtomicLoadOr16\0"
1140
  /* 163 */ "Ror16\0"
1141
  /* 169 */ "AtomicLoadXor16\0"
1142
  /* 185 */ "Asr16\0"
1143
  /* 191 */ "Lsr16\0"
1144
  /* 197 */ "Select16\0"
1145
  /* 206 */ "ROLBRdR17\0"
1146
  /* 216 */ "AtomicLoadSub8\0"
1147
  /* 231 */ "AtomicLoad8\0"
1148
  /* 243 */ "AtomicLoadAdd8\0"
1149
  /* 258 */ "AtomicLoadAnd8\0"
1150
  /* 273 */ "AtomicStore8\0"
1151
  /* 286 */ "Rol8\0"
1152
  /* 291 */ "Lsl8\0"
1153
  /* 296 */ "AtomicLoadOr8\0"
1154
  /* 310 */ "Ror8\0"
1155
  /* 315 */ "AtomicLoadXor8\0"
1156
  /* 330 */ "Asr8\0"
1157
  /* 335 */ "Lsr8\0"
1158
  /* 340 */ "Select8\0"
1159
  /* 348 */ "G_FMA\0"
1160
  /* 354 */ "G_STRICT_FMA\0"
1161
  /* 367 */ "INRdA\0"
1162
  /* 373 */ "INWRdA\0"
1163
  /* 380 */ "G_FSUB\0"
1164
  /* 387 */ "G_STRICT_FSUB\0"
1165
  /* 401 */ "G_ATOMICRMW_FSUB\0"
1166
  /* 418 */ "G_SUB\0"
1167
  /* 424 */ "G_ATOMICRMW_SUB\0"
1168
  /* 440 */ "SBRCRrB\0"
1169
  /* 448 */ "SBRSRrB\0"
1170
  /* 456 */ "G_INTRINSIC\0"
1171
  /* 468 */ "G_FPTRUNC\0"
1172
  /* 478 */ "G_INTRINSIC_TRUNC\0"
1173
  /* 496 */ "G_TRUNC\0"
1174
  /* 504 */ "G_BUILD_VECTOR_TRUNC\0"
1175
  /* 525 */ "G_DYN_STACKALLOC\0"
1176
  /* 542 */ "SPREAD\0"
1177
  /* 549 */ "G_FMAD\0"
1178
  /* 556 */ "G_INDEXED_SEXTLOAD\0"
1179
  /* 575 */ "G_SEXTLOAD\0"
1180
  /* 586 */ "G_INDEXED_ZEXTLOAD\0"
1181
  /* 605 */ "G_ZEXTLOAD\0"
1182
  /* 616 */ "G_INDEXED_LOAD\0"
1183
  /* 631 */ "G_LOAD\0"
1184
  /* 638 */ "G_VECREDUCE_FADD\0"
1185
  /* 655 */ "G_FADD\0"
1186
  /* 662 */ "G_VECREDUCE_SEQ_FADD\0"
1187
  /* 683 */ "G_STRICT_FADD\0"
1188
  /* 697 */ "G_ATOMICRMW_FADD\0"
1189
  /* 714 */ "G_VECREDUCE_ADD\0"
1190
  /* 730 */ "G_ADD\0"
1191
  /* 736 */ "G_PTR_ADD\0"
1192
  /* 746 */ "G_ATOMICRMW_ADD\0"
1193
  /* 762 */ "BLD\0"
1194
  /* 766 */ "G_ATOMICRMW_NAND\0"
1195
  /* 783 */ "G_VECREDUCE_AND\0"
1196
  /* 799 */ "G_AND\0"
1197
  /* 805 */ "G_ATOMICRMW_AND\0"
1198
  /* 821 */ "LIFETIME_END\0"
1199
  /* 834 */ "G_BRCOND\0"
1200
  /* 843 */ "G_LLROUND\0"
1201
  /* 853 */ "G_LROUND\0"
1202
  /* 862 */ "G_INTRINSIC_ROUND\0"
1203
  /* 880 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
1204
  /* 906 */ "LOAD_STACK_GUARD\0"
1205
  /* 923 */ "PSEUDO_PROBE\0"
1206
  /* 936 */ "G_SSUBE\0"
1207
  /* 944 */ "G_USUBE\0"
1208
  /* 952 */ "G_FENCE\0"
1209
  /* 960 */ "ARITH_FENCE\0"
1210
  /* 972 */ "REG_SEQUENCE\0"
1211
  /* 985 */ "G_SADDE\0"
1212
  /* 993 */ "G_UADDE\0"
1213
  /* 1001 */ "G_GET_FPMODE\0"
1214
  /* 1014 */ "G_RESET_FPMODE\0"
1215
  /* 1029 */ "G_SET_FPMODE\0"
1216
  /* 1042 */ "G_FMINNUM_IEEE\0"
1217
  /* 1057 */ "G_FMAXNUM_IEEE\0"
1218
  /* 1072 */ "G_JUMP_TABLE\0"
1219
  /* 1085 */ "BUNDLE\0"
1220
  /* 1092 */ "G_MEMCPY_INLINE\0"
1221
  /* 1108 */ "LOCAL_ESCAPE\0"
1222
  /* 1121 */ "G_STACKRESTORE\0"
1223
  /* 1136 */ "G_INDEXED_STORE\0"
1224
  /* 1152 */ "G_STORE\0"
1225
  /* 1160 */ "CPSE\0"
1226
  /* 1165 */ "G_BITREVERSE\0"
1227
  /* 1178 */ "SPWRITE\0"
1228
  /* 1186 */ "DBG_VALUE\0"
1229
  /* 1196 */ "G_GLOBAL_VALUE\0"
1230
  /* 1211 */ "G_STACKSAVE\0"
1231
  /* 1223 */ "G_MEMMOVE\0"
1232
  /* 1233 */ "G_FREEZE\0"
1233
  /* 1242 */ "G_FCANONICALIZE\0"
1234
  /* 1258 */ "G_CTLZ_ZERO_UNDEF\0"
1235
  /* 1276 */ "G_CTTZ_ZERO_UNDEF\0"
1236
  /* 1294 */ "G_IMPLICIT_DEF\0"
1237
  /* 1309 */ "DBG_INSTR_REF\0"
1238
  /* 1323 */ "G_FNEG\0"
1239
  /* 1330 */ "EXTRACT_SUBREG\0"
1240
  /* 1345 */ "INSERT_SUBREG\0"
1241
  /* 1359 */ "G_SEXT_INREG\0"
1242
  /* 1372 */ "SUBREG_TO_REG\0"
1243
  /* 1386 */ "G_ATOMIC_CMPXCHG\0"
1244
  /* 1403 */ "G_ATOMICRMW_XCHG\0"
1245
  /* 1420 */ "G_FLOG\0"
1246
  /* 1427 */ "G_VAARG\0"
1247
  /* 1435 */ "PREALLOCATED_ARG\0"
1248
  /* 1452 */ "G_PREFETCH\0"
1249
  /* 1463 */ "G_SMULH\0"
1250
  /* 1471 */ "G_UMULH\0"
1251
  /* 1479 */ "DBG_PHI\0"
1252
  /* 1487 */ "G_FPTOSI\0"
1253
  /* 1496 */ "RETI\0"
1254
  /* 1501 */ "G_FPTOUI\0"
1255
  /* 1510 */ "G_FPOWI\0"
1256
  /* 1518 */ "BREAK\0"
1257
  /* 1524 */ "G_PTRMASK\0"
1258
  /* 1534 */ "DESK\0"
1259
  /* 1539 */ "SUBIRdK\0"
1260
  /* 1547 */ "SBCIRdK\0"
1261
  /* 1555 */ "LDIRdK\0"
1262
  /* 1562 */ "ANDIRdK\0"
1263
  /* 1570 */ "CPIRdK\0"
1264
  /* 1577 */ "ORIRdK\0"
1265
  /* 1584 */ "LDSRdK\0"
1266
  /* 1591 */ "SBIWRdK\0"
1267
  /* 1599 */ "SUBIWRdK\0"
1268
  /* 1608 */ "SBCIWRdK\0"
1269
  /* 1617 */ "ADIWRdK\0"
1270
  /* 1625 */ "LDIWRdK\0"
1271
  /* 1633 */ "ANDIWRdK\0"
1272
  /* 1642 */ "ORIWRdK\0"
1273
  /* 1650 */ "LDSWRdK\0"
1274
  /* 1658 */ "GC_LABEL\0"
1275
  /* 1667 */ "DBG_LABEL\0"
1276
  /* 1677 */ "EH_LABEL\0"
1277
  /* 1686 */ "ANNOTATION_LABEL\0"
1278
  /* 1703 */ "ICALL_BRANCH_FUNNEL\0"
1279
  /* 1723 */ "G_FSHL\0"
1280
  /* 1730 */ "G_SHL\0"
1281
  /* 1736 */ "G_FCEIL\0"
1282
  /* 1744 */ "EICALL\0"
1283
  /* 1751 */ "PATCHABLE_TAIL_CALL\0"
1284
  /* 1771 */ "PATCHABLE_TYPED_EVENT_CALL\0"
1285
  /* 1798 */ "PATCHABLE_EVENT_CALL\0"
1286
  /* 1819 */ "FENTRY_CALL\0"
1287
  /* 1831 */ "KILL\0"
1288
  /* 1836 */ "G_CONSTANT_POOL\0"
1289
  /* 1852 */ "G_ROTL\0"
1290
  /* 1859 */ "G_VECREDUCE_FMUL\0"
1291
  /* 1876 */ "G_FMUL\0"
1292
  /* 1883 */ "G_VECREDUCE_SEQ_FMUL\0"
1293
  /* 1904 */ "G_STRICT_FMUL\0"
1294
  /* 1918 */ "G_VECREDUCE_MUL\0"
1295
  /* 1934 */ "G_MUL\0"
1296
  /* 1940 */ "G_FREM\0"
1297
  /* 1947 */ "G_STRICT_FREM\0"
1298
  /* 1961 */ "G_SREM\0"
1299
  /* 1968 */ "G_UREM\0"
1300
  /* 1975 */ "G_SDIVREM\0"
1301
  /* 1985 */ "G_UDIVREM\0"
1302
  /* 1995 */ "ELPM\0"
1303
  /* 2000 */ "SPM\0"
1304
  /* 2004 */ "INLINEASM\0"
1305
  /* 2014 */ "G_VECREDUCE_FMINIMUM\0"
1306
  /* 2035 */ "G_FMINIMUM\0"
1307
  /* 2046 */ "G_VECREDUCE_FMAXIMUM\0"
1308
  /* 2067 */ "G_FMAXIMUM\0"
1309
  /* 2078 */ "G_FMINNUM\0"
1310
  /* 2088 */ "G_FMAXNUM\0"
1311
  /* 2098 */ "G_INTRINSIC_ROUNDEVEN\0"
1312
  /* 2120 */ "G_ASSERT_ALIGN\0"
1313
  /* 2135 */ "G_FCOPYSIGN\0"
1314
  /* 2147 */ "G_VECREDUCE_FMIN\0"
1315
  /* 2164 */ "G_ATOMICRMW_FMIN\0"
1316
  /* 2181 */ "G_VECREDUCE_SMIN\0"
1317
  /* 2198 */ "G_SMIN\0"
1318
  /* 2205 */ "G_VECREDUCE_UMIN\0"
1319
  /* 2222 */ "G_UMIN\0"
1320
  /* 2229 */ "G_ATOMICRMW_UMIN\0"
1321
  /* 2246 */ "G_ATOMICRMW_MIN\0"
1322
  /* 2262 */ "G_FSIN\0"
1323
  /* 2269 */ "CFI_INSTRUCTION\0"
1324
  /* 2285 */ "ADJCALLSTACKDOWN\0"
1325
  /* 2302 */ "G_SSUBO\0"
1326
  /* 2310 */ "G_USUBO\0"
1327
  /* 2318 */ "G_SADDO\0"
1328
  /* 2326 */ "G_UADDO\0"
1329
  /* 2334 */ "JUMP_TABLE_DEBUG_INFO\0"
1330
  /* 2356 */ "G_SMULO\0"
1331
  /* 2364 */ "G_UMULO\0"
1332
  /* 2372 */ "G_BZERO\0"
1333
  /* 2380 */ "STACKMAP\0"
1334
  /* 2389 */ "G_ATOMICRMW_UDEC_WRAP\0"
1335
  /* 2411 */ "G_ATOMICRMW_UINC_WRAP\0"
1336
  /* 2433 */ "G_BSWAP\0"
1337
  /* 2441 */ "SLEEP\0"
1338
  /* 2447 */ "G_SITOFP\0"
1339
  /* 2456 */ "G_UITOFP\0"
1340
  /* 2465 */ "G_FCMP\0"
1341
  /* 2472 */ "G_ICMP\0"
1342
  /* 2479 */ "EIJMP\0"
1343
  /* 2485 */ "NOP\0"
1344
  /* 2489 */ "G_CTPOP\0"
1345
  /* 2497 */ "PATCHABLE_OP\0"
1346
  /* 2510 */ "FAULTING_OP\0"
1347
  /* 2522 */ "ADJCALLSTACKUP\0"
1348
  /* 2537 */ "PREALLOCATED_SETUP\0"
1349
  /* 2556 */ "G_FLDEXP\0"
1350
  /* 2565 */ "G_STRICT_FLDEXP\0"
1351
  /* 2581 */ "G_FEXP\0"
1352
  /* 2588 */ "G_FFREXP\0"
1353
  /* 2597 */ "LDDWRdYQ\0"
1354
  /* 2606 */ "LDDRdPtrQ\0"
1355
  /* 2616 */ "LDDWRdPtrQ\0"
1356
  /* 2627 */ "G_BR\0"
1357
  /* 2632 */ "INLINEASM_BR\0"
1358
  /* 2645 */ "G_BLOCK_ADDR\0"
1359
  /* 2658 */ "WDR\0"
1360
  /* 2662 */ "MEMBARRIER\0"
1361
  /* 2673 */ "G_CONSTANT_FOLD_BARRIER\0"
1362
  /* 2697 */ "PATCHABLE_FUNCTION_ENTER\0"
1363
  /* 2722 */ "G_READCYCLECOUNTER\0"
1364
  /* 2741 */ "G_READ_REGISTER\0"
1365
  /* 2757 */ "G_WRITE_REGISTER\0"
1366
  /* 2774 */ "G_ASHR\0"
1367
  /* 2781 */ "G_FSHR\0"
1368
  /* 2788 */ "G_LSHR\0"
1369
  /* 2795 */ "G_FFLOOR\0"
1370
  /* 2804 */ "G_BUILD_VECTOR\0"
1371
  /* 2819 */ "G_SHUFFLE_VECTOR\0"
1372
  /* 2836 */ "G_VECREDUCE_XOR\0"
1373
  /* 2852 */ "G_XOR\0"
1374
  /* 2858 */ "G_ATOMICRMW_XOR\0"
1375
  /* 2874 */ "G_VECREDUCE_OR\0"
1376
  /* 2889 */ "G_OR\0"
1377
  /* 2894 */ "G_ATOMICRMW_OR\0"
1378
  /* 2909 */ "G_ROTR\0"
1379
  /* 2916 */ "G_INTTOPTR\0"
1380
  /* 2927 */ "G_FABS\0"
1381
  /* 2934 */ "G_ABS\0"
1382
  /* 2940 */ "G_UNMERGE_VALUES\0"
1383
  /* 2957 */ "G_MERGE_VALUES\0"
1384
  /* 2972 */ "FMULS\0"
1385
  /* 2978 */ "G_FCOS\0"
1386
  /* 2985 */ "G_CONCAT_VECTORS\0"
1387
  /* 3002 */ "COPY_TO_REGCLASS\0"
1388
  /* 3019 */ "G_IS_FPCLASS\0"
1389
  /* 3032 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
1390
  /* 3062 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
1391
  /* 3089 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
1392
  /* 3127 */ "G_SSUBSAT\0"
1393
  /* 3137 */ "G_USUBSAT\0"
1394
  /* 3147 */ "G_SADDSAT\0"
1395
  /* 3157 */ "G_UADDSAT\0"
1396
  /* 3167 */ "G_SSHLSAT\0"
1397
  /* 3177 */ "G_USHLSAT\0"
1398
  /* 3187 */ "G_SMULFIXSAT\0"
1399
  /* 3200 */ "G_UMULFIXSAT\0"
1400
  /* 3213 */ "G_SDIVFIXSAT\0"
1401
  /* 3226 */ "G_UDIVFIXSAT\0"
1402
  /* 3239 */ "G_EXTRACT\0"
1403
  /* 3249 */ "G_SELECT\0"
1404
  /* 3258 */ "G_BRINDIRECT\0"
1405
  /* 3271 */ "PATCHABLE_RET\0"
1406
  /* 3285 */ "G_MEMSET\0"
1407
  /* 3294 */ "PATCHABLE_FUNCTION_EXIT\0"
1408
  /* 3318 */ "G_BRJT\0"
1409
  /* 3325 */ "G_EXTRACT_VECTOR_ELT\0"
1410
  /* 3346 */ "G_INSERT_VECTOR_ELT\0"
1411
  /* 3366 */ "G_FCONSTANT\0"
1412
  /* 3378 */ "G_CONSTANT\0"
1413
  /* 3389 */ "G_INTRINSIC_CONVERGENT\0"
1414
  /* 3412 */ "STATEPOINT\0"
1415
  /* 3423 */ "PATCHPOINT\0"
1416
  /* 3434 */ "G_PTRTOINT\0"
1417
  /* 3445 */ "G_FRINT\0"
1418
  /* 3453 */ "G_INTRINSIC_LRINT\0"
1419
  /* 3471 */ "G_FNEARBYINT\0"
1420
  /* 3484 */ "G_VASTART\0"
1421
  /* 3494 */ "LIFETIME_START\0"
1422
  /* 3509 */ "G_INVOKE_REGION_START\0"
1423
  /* 3531 */ "G_INSERT\0"
1424
  /* 3540 */ "G_FSQRT\0"
1425
  /* 3548 */ "G_STRICT_FSQRT\0"
1426
  /* 3563 */ "G_BITCAST\0"
1427
  /* 3573 */ "G_ADDRSPACE_CAST\0"
1428
  /* 3590 */ "BST\0"
1429
  /* 3594 */ "DBG_VALUE_LIST\0"
1430
  /* 3609 */ "G_FPEXT\0"
1431
  /* 3617 */ "G_SEXT\0"
1432
  /* 3624 */ "G_ASSERT_SEXT\0"
1433
  /* 3638 */ "G_ANYEXT\0"
1434
  /* 3647 */ "G_ZEXT\0"
1435
  /* 3654 */ "G_ASSERT_ZEXT\0"
1436
  /* 3668 */ "FMULSU\0"
1437
  /* 3675 */ "G_FDIV\0"
1438
  /* 3682 */ "G_STRICT_FDIV\0"
1439
  /* 3696 */ "G_SDIV\0"
1440
  /* 3703 */ "G_UDIV\0"
1441
  /* 3710 */ "G_GET_FPENV\0"
1442
  /* 3722 */ "G_RESET_FPENV\0"
1443
  /* 3736 */ "G_SET_FPENV\0"
1444
  /* 3748 */ "G_FPOW\0"
1445
  /* 3755 */ "G_VECREDUCE_FMAX\0"
1446
  /* 3772 */ "G_ATOMICRMW_FMAX\0"
1447
  /* 3789 */ "G_VECREDUCE_SMAX\0"
1448
  /* 3806 */ "G_SMAX\0"
1449
  /* 3813 */ "G_VECREDUCE_UMAX\0"
1450
  /* 3830 */ "G_UMAX\0"
1451
  /* 3837 */ "G_ATOMICRMW_UMAX\0"
1452
  /* 3854 */ "G_ATOMICRMW_MAX\0"
1453
  /* 3870 */ "FRMIDX\0"
1454
  /* 3877 */ "G_FRAME_INDEX\0"
1455
  /* 3891 */ "G_SBFX\0"
1456
  /* 3898 */ "G_UBFX\0"
1457
  /* 3905 */ "G_SMULFIX\0"
1458
  /* 3915 */ "G_UMULFIX\0"
1459
  /* 3925 */ "G_SDIVFIX\0"
1460
  /* 3935 */ "G_UDIVFIX\0"
1461
  /* 3945 */ "G_MEMCPY\0"
1462
  /* 3954 */ "COPY\0"
1463
  /* 3959 */ "G_CTLZ\0"
1464
  /* 3966 */ "G_CTTZ\0"
1465
  /* 3973 */ "ELPMBRdZ\0"
1466
  /* 3982 */ "ELPMRdZ\0"
1467
  /* 3990 */ "ELPMWRdZ\0"
1468
  /* 3999 */ "SBICAb\0"
1469
  /* 4006 */ "CBIAb\0"
1470
  /* 4012 */ "SBIAb\0"
1471
  /* 4018 */ "SBISAb\0"
1472
  /* 4025 */ "LDRdPtrPd\0"
1473
  /* 4035 */ "LDWRdPtrPd\0"
1474
  /* 4046 */ "RORBRd\0"
1475
  /* 4053 */ "DECRd\0"
1476
  /* 4059 */ "INCRd\0"
1477
  /* 4065 */ "NEGRd\0"
1478
  /* 4071 */ "COMRd\0"
1479
  /* 4077 */ "LSLBNRd\0"
1480
  /* 4085 */ "ASRBNRd\0"
1481
  /* 4093 */ "LSRBNRd\0"
1482
  /* 4101 */ "LSLWNRd\0"
1483
  /* 4109 */ "ASRWNRd\0"
1484
  /* 4117 */ "LSRWNRd\0"
1485
  /* 4125 */ "SWAPRd\0"
1486
  /* 4132 */ "POPRd\0"
1487
  /* 4138 */ "RORRd\0"
1488
  /* 4144 */ "ASRRd\0"
1489
  /* 4150 */ "LSRRd\0"
1490
  /* 4156 */ "NEGWRd\0"
1491
  /* 4163 */ "ROLWRd\0"
1492
  /* 4170 */ "LSLWRd\0"
1493
  /* 4177 */ "COMWRd\0"
1494
  /* 4184 */ "POPWRd\0"
1495
  /* 4191 */ "RORWRd\0"
1496
  /* 4198 */ "ASRWRd\0"
1497
  /* 4205 */ "LSRWRd\0"
1498
  /* 4212 */ "LACZRd\0"
1499
  /* 4219 */ "XCHZRd\0"
1500
  /* 4226 */ "LASZRd\0"
1501
  /* 4233 */ "LATZRd\0"
1502
  /* 4240 */ "LSLWHiRd\0"
1503
  /* 4249 */ "ASRWLoRd\0"
1504
  /* 4258 */ "LSRWLoRd\0"
1505
  /* 4267 */ "AtomicFence\0"
1506
  /* 4279 */ "SPMZPi\0"
1507
  /* 4286 */ "ELPMBRdZPi\0"
1508
  /* 4297 */ "ELPMRdZPi\0"
1509
  /* 4307 */ "ELPMWRdZPi\0"
1510
  /* 4318 */ "LDRdPtrPi\0"
1511
  /* 4328 */ "LDWRdPtrPi\0"
1512
  /* 4339 */ "BRGEk\0"
1513
  /* 4345 */ "BRNEk\0"
1514
  /* 4351 */ "BRSHk\0"
1515
  /* 4357 */ "BRMIk\0"
1516
  /* 4363 */ "RCALLk\0"
1517
  /* 4370 */ "BRPLk\0"
1518
  /* 4376 */ "BRLOk\0"
1519
  /* 4382 */ "RJMPk\0"
1520
  /* 4388 */ "BREQk\0"
1521
  /* 4394 */ "BRLTk\0"
1522
  /* 4400 */ "BRBCsk\0"
1523
  /* 4407 */ "BRBSsk\0"
1524
  /* 4414 */ "CopyZero\0"
1525
  /* 4423 */ "OUTARr\0"
1526
  /* 4430 */ "OUTWARr\0"
1527
  /* 4438 */ "PUSHRr\0"
1528
  /* 4445 */ "STSKRr\0"
1529
  /* 4452 */ "STSWKRr\0"
1530
  /* 4460 */ "STDSPQRr\0"
1531
  /* 4469 */ "STDWSPQRr\0"
1532
  /* 4479 */ "STDPtrQRr\0"
1533
  /* 4489 */ "STDWPtrQRr\0"
1534
  /* 4500 */ "PUSHWRr\0"
1535
  /* 4508 */ "STPtrPdRr\0"
1536
  /* 4518 */ "STWPtrPdRr\0"
1537
  /* 4529 */ "SUBRdRr\0"
1538
  /* 4537 */ "SBCRdRr\0"
1539
  /* 4545 */ "ADCRdRr\0"
1540
  /* 4553 */ "CPCRdRr\0"
1541
  /* 4561 */ "ADDRdRr\0"
1542
  /* 4569 */ "ANDRdRr\0"
1543
  /* 4577 */ "MULRdRr\0"
1544
  /* 4585 */ "CPRdRr\0"
1545
  /* 4592 */ "EORRdRr\0"
1546
  /* 4600 */ "MULSRdRr\0"
1547
  /* 4609 */ "MULSURdRr\0"
1548
  /* 4619 */ "MOVRdRr\0"
1549
  /* 4627 */ "SUBWRdRr\0"
1550
  /* 4636 */ "SBCWRdRr\0"
1551
  /* 4645 */ "ADCWRdRr\0"
1552
  /* 4654 */ "CPCWRdRr\0"
1553
  /* 4663 */ "ADDWRdRr\0"
1554
  /* 4672 */ "ANDWRdRr\0"
1555
  /* 4681 */ "CPWRdRr\0"
1556
  /* 4689 */ "EORWRdRr\0"
1557
  /* 4698 */ "MOVWRdRr\0"
1558
  /* 4707 */ "STPtrPiRr\0"
1559
  /* 4717 */ "STWPtrPiRr\0"
1560
  /* 4728 */ "STPtrRr\0"
1561
  /* 4736 */ "STWPtrRr\0"
1562
  /* 4745 */ "LDRdPtr\0"
1563
  /* 4753 */ "LDWRdPtr\0"
1564
  /* 4762 */ "BCLRs\0"
1565
  /* 4768 */ "BSETs\0"
1566
  /* 4774 */ "LDSRdKTiny\0"
1567
  /* 4785 */ "STSKRrTiny\0"
1568
};
1569
#ifdef __GNUC__
1570
#pragma GCC diagnostic pop
1571
#endif
1572
1573
extern const unsigned AVRInstrNameIndices[] = {
1574
    1483U, 2004U, 2632U, 2269U, 1677U, 1658U, 1686U, 1831U, 
1575
    1330U, 1345U, 1296U, 1372U, 3002U, 1186U, 3594U, 1309U, 
1576
    1479U, 1667U, 972U, 3954U, 1085U, 3494U, 821U, 923U, 
1577
    960U, 2380U, 1819U, 3423U, 906U, 2537U, 1435U, 3412U, 
1578
    1108U, 2510U, 2497U, 2697U, 3271U, 3294U, 1751U, 1798U, 
1579
    1771U, 1703U, 2662U, 2334U, 3624U, 3654U, 2120U, 730U, 
1580
    418U, 1934U, 3696U, 3703U, 1961U, 1968U, 1975U, 1985U, 
1581
    799U, 2889U, 2852U, 1294U, 1481U, 3877U, 1196U, 1836U, 
1582
    3239U, 2940U, 3531U, 2957U, 2804U, 504U, 2985U, 3434U, 
1583
    2916U, 3563U, 1233U, 2673U, 880U, 478U, 862U, 3453U, 
1584
    2098U, 2722U, 631U, 575U, 605U, 616U, 556U, 586U, 
1585
    1152U, 1136U, 3032U, 1386U, 1403U, 746U, 424U, 805U, 
1586
    766U, 2894U, 2858U, 3854U, 2246U, 3837U, 2229U, 697U, 
1587
    401U, 3772U, 2164U, 2411U, 2389U, 952U, 1452U, 834U, 
1588
    3258U, 3509U, 456U, 3062U, 3389U, 3089U, 3638U, 496U, 
1589
    3378U, 3366U, 3484U, 1427U, 3617U, 1359U, 3647U, 1730U, 
1590
    2788U, 2774U, 1723U, 2781U, 2909U, 1852U, 2472U, 2465U, 
1591
    3249U, 2326U, 993U, 2310U, 944U, 2318U, 985U, 2302U, 
1592
    936U, 2364U, 2356U, 1471U, 1463U, 3157U, 3147U, 3137U, 
1593
    3127U, 3177U, 3167U, 3905U, 3915U, 3187U, 3200U, 3925U, 
1594
    3935U, 3213U, 3226U, 655U, 380U, 1876U, 348U, 549U, 
1595
    3675U, 1940U, 3748U, 1510U, 2581U, 53U, 9U, 1420U, 
1596
    45U, 0U, 2556U, 2588U, 1323U, 3609U, 468U, 1487U, 
1597
    1501U, 2447U, 2456U, 2927U, 2135U, 3019U, 1242U, 2078U, 
1598
    2088U, 1042U, 1057U, 2035U, 2067U, 3710U, 3736U, 3722U, 
1599
    1001U, 1029U, 1014U, 736U, 1524U, 2198U, 3806U, 2222U, 
1600
    3830U, 2934U, 853U, 843U, 2627U, 3318U, 3346U, 3325U, 
1601
    2819U, 3966U, 1276U, 3959U, 1258U, 2489U, 2433U, 1165U, 
1602
    1736U, 2978U, 2262U, 3540U, 2795U, 3445U, 3471U, 3573U, 
1603
    2645U, 1072U, 525U, 1211U, 1121U, 683U, 387U, 1904U, 
1604
    3682U, 1947U, 354U, 3548U, 2565U, 2741U, 2757U, 3945U, 
1605
    1092U, 1223U, 3285U, 2372U, 662U, 1883U, 638U, 1859U, 
1606
    3755U, 2147U, 2046U, 2014U, 714U, 1918U, 783U, 2874U, 
1607
    2836U, 3789U, 2181U, 3813U, 2205U, 3891U, 3898U, 4645U, 
1608
    4663U, 2285U, 2522U, 1633U, 4672U, 4085U, 4249U, 4109U, 
1609
    4198U, 185U, 33U, 330U, 4267U, 77U, 231U, 90U, 
1610
    243U, 106U, 258U, 148U, 296U, 61U, 216U, 169U, 
1611
    315U, 122U, 273U, 4177U, 4654U, 4681U, 4414U, 3973U, 
1612
    4286U, 3990U, 4307U, 4689U, 3870U, 373U, 2616U, 2597U, 
1613
    1625U, 1650U, 4753U, 4035U, 4328U, 3974U, 3991U, 4308U, 
1614
    4077U, 4240U, 4101U, 4170U, 4093U, 4258U, 4117U, 4205U, 
1615
    142U, 27U, 291U, 191U, 39U, 335U, 4156U, 1642U, 
1616
    4690U, 4430U, 4184U, 4500U, 18U, 206U, 4163U, 4046U, 
1617
    4191U, 136U, 286U, 163U, 310U, 1608U, 4636U, 3619U, 
1618
    542U, 1178U, 4460U, 4489U, 4469U, 4452U, 4518U, 4717U, 
1619
    4736U, 1599U, 4627U, 197U, 340U, 3649U, 4545U, 4561U, 
1620
    1617U, 1562U, 4569U, 4144U, 4762U, 762U, 4400U, 4407U, 
1621
    1518U, 4388U, 4339U, 4376U, 4394U, 4357U, 4345U, 4370U, 
1622
    4351U, 4768U, 3590U, 4364U, 4006U, 4071U, 4553U, 1570U, 
1623
    4585U, 1160U, 4053U, 1534U, 1744U, 2479U, 1995U, 3982U, 
1624
    4297U, 4592U, 1871U, 2972U, 3668U, 1745U, 2480U, 4059U, 
1625
    367U, 4383U, 4212U, 4226U, 4233U, 2606U, 1555U, 4745U, 
1626
    4025U, 4318U, 1584U, 4774U, 1996U, 3983U, 4298U, 4150U, 
1627
    4619U, 4698U, 4577U, 4600U, 4609U, 4065U, 2485U, 1577U, 
1628
    4593U, 4423U, 4132U, 4438U, 4363U, 3281U, 1496U, 4382U, 
1629
    4138U, 1547U, 4537U, 4012U, 3999U, 4018U, 1591U, 440U, 
1630
    448U, 2441U, 2000U, 4279U, 4479U, 4508U, 4707U, 4728U, 
1631
    4445U, 4785U, 1539U, 4529U, 4125U, 2658U, 4219U, 
1632
};
1633
1634
0
static inline void InitAVRMCInstrInfo(MCInstrInfo *II) {
1635
0
  II->InitMCInstrInfo(AVRDescs.Insts, AVRInstrNameIndices, AVRInstrNameData, nullptr, nullptr, 463);
1636
0
}
1637
1638
} // end namespace llvm
1639
#endif // GET_INSTRINFO_MC_DESC
1640
1641
#ifdef GET_INSTRINFO_HEADER
1642
#undef GET_INSTRINFO_HEADER
1643
namespace llvm {
1644
struct AVRGenInstrInfo : public TargetInstrInfo {
1645
  explicit AVRGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1646
  ~AVRGenInstrInfo() override = default;
1647
1648
};
1649
} // end namespace llvm
1650
#endif // GET_INSTRINFO_HEADER
1651
1652
#ifdef GET_INSTRINFO_HELPER_DECLS
1653
#undef GET_INSTRINFO_HELPER_DECLS
1654
1655
1656
#endif // GET_INSTRINFO_HELPER_DECLS
1657
1658
#ifdef GET_INSTRINFO_HELPERS
1659
#undef GET_INSTRINFO_HELPERS
1660
1661
#endif // GET_INSTRINFO_HELPERS
1662
1663
#ifdef GET_INSTRINFO_CTOR_DTOR
1664
#undef GET_INSTRINFO_CTOR_DTOR
1665
namespace llvm {
1666
extern const AVRInstrTable AVRDescs;
1667
extern const unsigned AVRInstrNameIndices[];
1668
extern const char AVRInstrNameData[];
1669
AVRGenInstrInfo::AVRGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1670
0
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1671
0
  InitMCInstrInfo(AVRDescs.Insts, AVRInstrNameIndices, AVRInstrNameData, nullptr, nullptr, 463);
1672
0
}
1673
} // end namespace llvm
1674
#endif // GET_INSTRINFO_CTOR_DTOR
1675
1676
#ifdef GET_INSTRINFO_OPERAND_ENUM
1677
#undef GET_INSTRINFO_OPERAND_ENUM
1678
namespace llvm {
1679
namespace AVR {
1680
namespace OpName {
1681
enum {
1682
  OPERAND_LAST
1683
};
1684
} // end namespace OpName
1685
} // end namespace AVR
1686
} // end namespace llvm
1687
#endif //GET_INSTRINFO_OPERAND_ENUM
1688
1689
#ifdef GET_INSTRINFO_NAMED_OPS
1690
#undef GET_INSTRINFO_NAMED_OPS
1691
namespace llvm {
1692
namespace AVR {
1693
LLVM_READONLY
1694
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
1695
  return -1;
1696
}
1697
} // end namespace AVR
1698
} // end namespace llvm
1699
#endif //GET_INSTRINFO_NAMED_OPS
1700
1701
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
1702
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
1703
namespace llvm {
1704
namespace AVR {
1705
namespace OpTypes {
1706
enum OperandType {
1707
  LDDSTDPtrReg = 0,
1708
  LDSTPtrReg = 1,
1709
  brtarget_13 = 2,
1710
  call_target = 3,
1711
  f32imm = 4,
1712
  f64imm = 5,
1713
  i1imm = 6,
1714
  i8imm = 7,
1715
  i16imm = 8,
1716
  i32imm = 9,
1717
  i64imm = 10,
1718
  imm7tiny = 11,
1719
  imm16 = 12,
1720
  imm_arith6 = 13,
1721
  imm_com8 = 14,
1722
  imm_ldi8 = 15,
1723
  imm_port5 = 16,
1724
  imm_port6 = 17,
1725
  memri = 18,
1726
  memspi = 19,
1727
  ptype0 = 20,
1728
  ptype1 = 21,
1729
  ptype2 = 22,
1730
  ptype3 = 23,
1731
  ptype4 = 24,
1732
  ptype5 = 25,
1733
  rcalltarget_13 = 26,
1734
  relbrtarget_7 = 27,
1735
  type0 = 28,
1736
  type1 = 29,
1737
  type2 = 30,
1738
  type3 = 31,
1739
  type4 = 32,
1740
  type5 = 33,
1741
  untyped_imm_0 = 34,
1742
  CCR = 35,
1743
  DLDREGS = 36,
1744
  DREGS = 37,
1745
  DREGSLD8lo = 38,
1746
  DREGSMOVW = 39,
1747
  DREGSlo = 40,
1748
  GPR8 = 41,
1749
  GPR8lo = 42,
1750
  GPRSP = 43,
1751
  IWREGS = 44,
1752
  LD8 = 45,
1753
  LD8lo = 46,
1754
  PTRDISPREGS = 47,
1755
  PTRREGS = 48,
1756
  ZREG = 49,
1757
  OPERAND_TYPE_LIST_END
1758
};
1759
} // end namespace OpTypes
1760
} // end namespace AVR
1761
} // end namespace llvm
1762
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
1763
1764
#ifdef GET_INSTRINFO_OPERAND_TYPE
1765
#undef GET_INSTRINFO_OPERAND_TYPE
1766
namespace llvm {
1767
namespace AVR {
1768
LLVM_READONLY
1769
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
1770
  static const uint16_t Offsets[] = {
1771
    /* PHI */
1772
    0,
1773
    /* INLINEASM */
1774
    1,
1775
    /* INLINEASM_BR */
1776
    1,
1777
    /* CFI_INSTRUCTION */
1778
    1,
1779
    /* EH_LABEL */
1780
    2,
1781
    /* GC_LABEL */
1782
    3,
1783
    /* ANNOTATION_LABEL */
1784
    4,
1785
    /* KILL */
1786
    5,
1787
    /* EXTRACT_SUBREG */
1788
    5,
1789
    /* INSERT_SUBREG */
1790
    8,
1791
    /* IMPLICIT_DEF */
1792
    12,
1793
    /* SUBREG_TO_REG */
1794
    13,
1795
    /* COPY_TO_REGCLASS */
1796
    17,
1797
    /* DBG_VALUE */
1798
    20,
1799
    /* DBG_VALUE_LIST */
1800
    20,
1801
    /* DBG_INSTR_REF */
1802
    20,
1803
    /* DBG_PHI */
1804
    20,
1805
    /* DBG_LABEL */
1806
    20,
1807
    /* REG_SEQUENCE */
1808
    21,
1809
    /* COPY */
1810
    23,
1811
    /* BUNDLE */
1812
    25,
1813
    /* LIFETIME_START */
1814
    25,
1815
    /* LIFETIME_END */
1816
    26,
1817
    /* PSEUDO_PROBE */
1818
    27,
1819
    /* ARITH_FENCE */
1820
    31,
1821
    /* STACKMAP */
1822
    33,
1823
    /* FENTRY_CALL */
1824
    35,
1825
    /* PATCHPOINT */
1826
    35,
1827
    /* LOAD_STACK_GUARD */
1828
    41,
1829
    /* PREALLOCATED_SETUP */
1830
    42,
1831
    /* PREALLOCATED_ARG */
1832
    43,
1833
    /* STATEPOINT */
1834
    46,
1835
    /* LOCAL_ESCAPE */
1836
    46,
1837
    /* FAULTING_OP */
1838
    48,
1839
    /* PATCHABLE_OP */
1840
    49,
1841
    /* PATCHABLE_FUNCTION_ENTER */
1842
    49,
1843
    /* PATCHABLE_RET */
1844
    49,
1845
    /* PATCHABLE_FUNCTION_EXIT */
1846
    49,
1847
    /* PATCHABLE_TAIL_CALL */
1848
    49,
1849
    /* PATCHABLE_EVENT_CALL */
1850
    49,
1851
    /* PATCHABLE_TYPED_EVENT_CALL */
1852
    51,
1853
    /* ICALL_BRANCH_FUNNEL */
1854
    54,
1855
    /* MEMBARRIER */
1856
    54,
1857
    /* JUMP_TABLE_DEBUG_INFO */
1858
    54,
1859
    /* G_ASSERT_SEXT */
1860
    55,
1861
    /* G_ASSERT_ZEXT */
1862
    58,
1863
    /* G_ASSERT_ALIGN */
1864
    61,
1865
    /* G_ADD */
1866
    64,
1867
    /* G_SUB */
1868
    67,
1869
    /* G_MUL */
1870
    70,
1871
    /* G_SDIV */
1872
    73,
1873
    /* G_UDIV */
1874
    76,
1875
    /* G_SREM */
1876
    79,
1877
    /* G_UREM */
1878
    82,
1879
    /* G_SDIVREM */
1880
    85,
1881
    /* G_UDIVREM */
1882
    89,
1883
    /* G_AND */
1884
    93,
1885
    /* G_OR */
1886
    96,
1887
    /* G_XOR */
1888
    99,
1889
    /* G_IMPLICIT_DEF */
1890
    102,
1891
    /* G_PHI */
1892
    103,
1893
    /* G_FRAME_INDEX */
1894
    104,
1895
    /* G_GLOBAL_VALUE */
1896
    106,
1897
    /* G_CONSTANT_POOL */
1898
    108,
1899
    /* G_EXTRACT */
1900
    110,
1901
    /* G_UNMERGE_VALUES */
1902
    113,
1903
    /* G_INSERT */
1904
    115,
1905
    /* G_MERGE_VALUES */
1906
    119,
1907
    /* G_BUILD_VECTOR */
1908
    121,
1909
    /* G_BUILD_VECTOR_TRUNC */
1910
    123,
1911
    /* G_CONCAT_VECTORS */
1912
    125,
1913
    /* G_PTRTOINT */
1914
    127,
1915
    /* G_INTTOPTR */
1916
    129,
1917
    /* G_BITCAST */
1918
    131,
1919
    /* G_FREEZE */
1920
    133,
1921
    /* G_CONSTANT_FOLD_BARRIER */
1922
    135,
1923
    /* G_INTRINSIC_FPTRUNC_ROUND */
1924
    137,
1925
    /* G_INTRINSIC_TRUNC */
1926
    140,
1927
    /* G_INTRINSIC_ROUND */
1928
    142,
1929
    /* G_INTRINSIC_LRINT */
1930
    144,
1931
    /* G_INTRINSIC_ROUNDEVEN */
1932
    146,
1933
    /* G_READCYCLECOUNTER */
1934
    148,
1935
    /* G_LOAD */
1936
    149,
1937
    /* G_SEXTLOAD */
1938
    151,
1939
    /* G_ZEXTLOAD */
1940
    153,
1941
    /* G_INDEXED_LOAD */
1942
    155,
1943
    /* G_INDEXED_SEXTLOAD */
1944
    160,
1945
    /* G_INDEXED_ZEXTLOAD */
1946
    165,
1947
    /* G_STORE */
1948
    170,
1949
    /* G_INDEXED_STORE */
1950
    172,
1951
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
1952
    177,
1953
    /* G_ATOMIC_CMPXCHG */
1954
    182,
1955
    /* G_ATOMICRMW_XCHG */
1956
    186,
1957
    /* G_ATOMICRMW_ADD */
1958
    189,
1959
    /* G_ATOMICRMW_SUB */
1960
    192,
1961
    /* G_ATOMICRMW_AND */
1962
    195,
1963
    /* G_ATOMICRMW_NAND */
1964
    198,
1965
    /* G_ATOMICRMW_OR */
1966
    201,
1967
    /* G_ATOMICRMW_XOR */
1968
    204,
1969
    /* G_ATOMICRMW_MAX */
1970
    207,
1971
    /* G_ATOMICRMW_MIN */
1972
    210,
1973
    /* G_ATOMICRMW_UMAX */
1974
    213,
1975
    /* G_ATOMICRMW_UMIN */
1976
    216,
1977
    /* G_ATOMICRMW_FADD */
1978
    219,
1979
    /* G_ATOMICRMW_FSUB */
1980
    222,
1981
    /* G_ATOMICRMW_FMAX */
1982
    225,
1983
    /* G_ATOMICRMW_FMIN */
1984
    228,
1985
    /* G_ATOMICRMW_UINC_WRAP */
1986
    231,
1987
    /* G_ATOMICRMW_UDEC_WRAP */
1988
    234,
1989
    /* G_FENCE */
1990
    237,
1991
    /* G_PREFETCH */
1992
    239,
1993
    /* G_BRCOND */
1994
    243,
1995
    /* G_BRINDIRECT */
1996
    245,
1997
    /* G_INVOKE_REGION_START */
1998
    246,
1999
    /* G_INTRINSIC */
2000
    246,
2001
    /* G_INTRINSIC_W_SIDE_EFFECTS */
2002
    247,
2003
    /* G_INTRINSIC_CONVERGENT */
2004
    248,
2005
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
2006
    249,
2007
    /* G_ANYEXT */
2008
    250,
2009
    /* G_TRUNC */
2010
    252,
2011
    /* G_CONSTANT */
2012
    254,
2013
    /* G_FCONSTANT */
2014
    256,
2015
    /* G_VASTART */
2016
    258,
2017
    /* G_VAARG */
2018
    259,
2019
    /* G_SEXT */
2020
    262,
2021
    /* G_SEXT_INREG */
2022
    264,
2023
    /* G_ZEXT */
2024
    267,
2025
    /* G_SHL */
2026
    269,
2027
    /* G_LSHR */
2028
    272,
2029
    /* G_ASHR */
2030
    275,
2031
    /* G_FSHL */
2032
    278,
2033
    /* G_FSHR */
2034
    282,
2035
    /* G_ROTR */
2036
    286,
2037
    /* G_ROTL */
2038
    289,
2039
    /* G_ICMP */
2040
    292,
2041
    /* G_FCMP */
2042
    296,
2043
    /* G_SELECT */
2044
    300,
2045
    /* G_UADDO */
2046
    304,
2047
    /* G_UADDE */
2048
    308,
2049
    /* G_USUBO */
2050
    313,
2051
    /* G_USUBE */
2052
    317,
2053
    /* G_SADDO */
2054
    322,
2055
    /* G_SADDE */
2056
    326,
2057
    /* G_SSUBO */
2058
    331,
2059
    /* G_SSUBE */
2060
    335,
2061
    /* G_UMULO */
2062
    340,
2063
    /* G_SMULO */
2064
    344,
2065
    /* G_UMULH */
2066
    348,
2067
    /* G_SMULH */
2068
    351,
2069
    /* G_UADDSAT */
2070
    354,
2071
    /* G_SADDSAT */
2072
    357,
2073
    /* G_USUBSAT */
2074
    360,
2075
    /* G_SSUBSAT */
2076
    363,
2077
    /* G_USHLSAT */
2078
    366,
2079
    /* G_SSHLSAT */
2080
    369,
2081
    /* G_SMULFIX */
2082
    372,
2083
    /* G_UMULFIX */
2084
    376,
2085
    /* G_SMULFIXSAT */
2086
    380,
2087
    /* G_UMULFIXSAT */
2088
    384,
2089
    /* G_SDIVFIX */
2090
    388,
2091
    /* G_UDIVFIX */
2092
    392,
2093
    /* G_SDIVFIXSAT */
2094
    396,
2095
    /* G_UDIVFIXSAT */
2096
    400,
2097
    /* G_FADD */
2098
    404,
2099
    /* G_FSUB */
2100
    407,
2101
    /* G_FMUL */
2102
    410,
2103
    /* G_FMA */
2104
    413,
2105
    /* G_FMAD */
2106
    417,
2107
    /* G_FDIV */
2108
    421,
2109
    /* G_FREM */
2110
    424,
2111
    /* G_FPOW */
2112
    427,
2113
    /* G_FPOWI */
2114
    430,
2115
    /* G_FEXP */
2116
    433,
2117
    /* G_FEXP2 */
2118
    435,
2119
    /* G_FEXP10 */
2120
    437,
2121
    /* G_FLOG */
2122
    439,
2123
    /* G_FLOG2 */
2124
    441,
2125
    /* G_FLOG10 */
2126
    443,
2127
    /* G_FLDEXP */
2128
    445,
2129
    /* G_FFREXP */
2130
    448,
2131
    /* G_FNEG */
2132
    451,
2133
    /* G_FPEXT */
2134
    453,
2135
    /* G_FPTRUNC */
2136
    455,
2137
    /* G_FPTOSI */
2138
    457,
2139
    /* G_FPTOUI */
2140
    459,
2141
    /* G_SITOFP */
2142
    461,
2143
    /* G_UITOFP */
2144
    463,
2145
    /* G_FABS */
2146
    465,
2147
    /* G_FCOPYSIGN */
2148
    467,
2149
    /* G_IS_FPCLASS */
2150
    470,
2151
    /* G_FCANONICALIZE */
2152
    473,
2153
    /* G_FMINNUM */
2154
    475,
2155
    /* G_FMAXNUM */
2156
    478,
2157
    /* G_FMINNUM_IEEE */
2158
    481,
2159
    /* G_FMAXNUM_IEEE */
2160
    484,
2161
    /* G_FMINIMUM */
2162
    487,
2163
    /* G_FMAXIMUM */
2164
    490,
2165
    /* G_GET_FPENV */
2166
    493,
2167
    /* G_SET_FPENV */
2168
    494,
2169
    /* G_RESET_FPENV */
2170
    495,
2171
    /* G_GET_FPMODE */
2172
    495,
2173
    /* G_SET_FPMODE */
2174
    496,
2175
    /* G_RESET_FPMODE */
2176
    497,
2177
    /* G_PTR_ADD */
2178
    497,
2179
    /* G_PTRMASK */
2180
    500,
2181
    /* G_SMIN */
2182
    503,
2183
    /* G_SMAX */
2184
    506,
2185
    /* G_UMIN */
2186
    509,
2187
    /* G_UMAX */
2188
    512,
2189
    /* G_ABS */
2190
    515,
2191
    /* G_LROUND */
2192
    517,
2193
    /* G_LLROUND */
2194
    519,
2195
    /* G_BR */
2196
    521,
2197
    /* G_BRJT */
2198
    522,
2199
    /* G_INSERT_VECTOR_ELT */
2200
    525,
2201
    /* G_EXTRACT_VECTOR_ELT */
2202
    529,
2203
    /* G_SHUFFLE_VECTOR */
2204
    532,
2205
    /* G_CTTZ */
2206
    536,
2207
    /* G_CTTZ_ZERO_UNDEF */
2208
    538,
2209
    /* G_CTLZ */
2210
    540,
2211
    /* G_CTLZ_ZERO_UNDEF */
2212
    542,
2213
    /* G_CTPOP */
2214
    544,
2215
    /* G_BSWAP */
2216
    546,
2217
    /* G_BITREVERSE */
2218
    548,
2219
    /* G_FCEIL */
2220
    550,
2221
    /* G_FCOS */
2222
    552,
2223
    /* G_FSIN */
2224
    554,
2225
    /* G_FSQRT */
2226
    556,
2227
    /* G_FFLOOR */
2228
    558,
2229
    /* G_FRINT */
2230
    560,
2231
    /* G_FNEARBYINT */
2232
    562,
2233
    /* G_ADDRSPACE_CAST */
2234
    564,
2235
    /* G_BLOCK_ADDR */
2236
    566,
2237
    /* G_JUMP_TABLE */
2238
    568,
2239
    /* G_DYN_STACKALLOC */
2240
    570,
2241
    /* G_STACKSAVE */
2242
    573,
2243
    /* G_STACKRESTORE */
2244
    574,
2245
    /* G_STRICT_FADD */
2246
    575,
2247
    /* G_STRICT_FSUB */
2248
    578,
2249
    /* G_STRICT_FMUL */
2250
    581,
2251
    /* G_STRICT_FDIV */
2252
    584,
2253
    /* G_STRICT_FREM */
2254
    587,
2255
    /* G_STRICT_FMA */
2256
    590,
2257
    /* G_STRICT_FSQRT */
2258
    594,
2259
    /* G_STRICT_FLDEXP */
2260
    596,
2261
    /* G_READ_REGISTER */
2262
    599,
2263
    /* G_WRITE_REGISTER */
2264
    601,
2265
    /* G_MEMCPY */
2266
    603,
2267
    /* G_MEMCPY_INLINE */
2268
    607,
2269
    /* G_MEMMOVE */
2270
    610,
2271
    /* G_MEMSET */
2272
    614,
2273
    /* G_BZERO */
2274
    618,
2275
    /* G_VECREDUCE_SEQ_FADD */
2276
    621,
2277
    /* G_VECREDUCE_SEQ_FMUL */
2278
    624,
2279
    /* G_VECREDUCE_FADD */
2280
    627,
2281
    /* G_VECREDUCE_FMUL */
2282
    629,
2283
    /* G_VECREDUCE_FMAX */
2284
    631,
2285
    /* G_VECREDUCE_FMIN */
2286
    633,
2287
    /* G_VECREDUCE_FMAXIMUM */
2288
    635,
2289
    /* G_VECREDUCE_FMINIMUM */
2290
    637,
2291
    /* G_VECREDUCE_ADD */
2292
    639,
2293
    /* G_VECREDUCE_MUL */
2294
    641,
2295
    /* G_VECREDUCE_AND */
2296
    643,
2297
    /* G_VECREDUCE_OR */
2298
    645,
2299
    /* G_VECREDUCE_XOR */
2300
    647,
2301
    /* G_VECREDUCE_SMAX */
2302
    649,
2303
    /* G_VECREDUCE_SMIN */
2304
    651,
2305
    /* G_VECREDUCE_UMAX */
2306
    653,
2307
    /* G_VECREDUCE_UMIN */
2308
    655,
2309
    /* G_SBFX */
2310
    657,
2311
    /* G_UBFX */
2312
    661,
2313
    /* ADCWRdRr */
2314
    665,
2315
    /* ADDWRdRr */
2316
    668,
2317
    /* ADJCALLSTACKDOWN */
2318
    671,
2319
    /* ADJCALLSTACKUP */
2320
    673,
2321
    /* ANDIWRdK */
2322
    675,
2323
    /* ANDWRdRr */
2324
    678,
2325
    /* ASRBNRd */
2326
    681,
2327
    /* ASRWLoRd */
2328
    684,
2329
    /* ASRWNRd */
2330
    686,
2331
    /* ASRWRd */
2332
    689,
2333
    /* Asr16 */
2334
    691,
2335
    /* Asr32 */
2336
    694,
2337
    /* Asr8 */
2338
    699,
2339
    /* AtomicFence */
2340
    702,
2341
    /* AtomicLoad16 */
2342
    702,
2343
    /* AtomicLoad8 */
2344
    704,
2345
    /* AtomicLoadAdd16 */
2346
    706,
2347
    /* AtomicLoadAdd8 */
2348
    709,
2349
    /* AtomicLoadAnd16 */
2350
    712,
2351
    /* AtomicLoadAnd8 */
2352
    715,
2353
    /* AtomicLoadOr16 */
2354
    718,
2355
    /* AtomicLoadOr8 */
2356
    721,
2357
    /* AtomicLoadSub16 */
2358
    724,
2359
    /* AtomicLoadSub8 */
2360
    727,
2361
    /* AtomicLoadXor16 */
2362
    730,
2363
    /* AtomicLoadXor8 */
2364
    733,
2365
    /* AtomicStore16 */
2366
    736,
2367
    /* AtomicStore8 */
2368
    738,
2369
    /* COMWRd */
2370
    740,
2371
    /* CPCWRdRr */
2372
    742,
2373
    /* CPWRdRr */
2374
    744,
2375
    /* CopyZero */
2376
    746,
2377
    /* ELPMBRdZ */
2378
    747,
2379
    /* ELPMBRdZPi */
2380
    750,
2381
    /* ELPMWRdZ */
2382
    753,
2383
    /* ELPMWRdZPi */
2384
    756,
2385
    /* EORWRdRr */
2386
    759,
2387
    /* FRMIDX */
2388
    762,
2389
    /* INWRdA */
2390
    765,
2391
    /* LDDWRdPtrQ */
2392
    767,
2393
    /* LDDWRdYQ */
2394
    770,
2395
    /* LDIWRdK */
2396
    773,
2397
    /* LDSWRdK */
2398
    775,
2399
    /* LDWRdPtr */
2400
    777,
2401
    /* LDWRdPtrPd */
2402
    779,
2403
    /* LDWRdPtrPi */
2404
    782,
2405
    /* LPMBRdZ */
2406
    785,
2407
    /* LPMWRdZ */
2408
    787,
2409
    /* LPMWRdZPi */
2410
    789,
2411
    /* LSLBNRd */
2412
    791,
2413
    /* LSLWHiRd */
2414
    794,
2415
    /* LSLWNRd */
2416
    796,
2417
    /* LSLWRd */
2418
    799,
2419
    /* LSRBNRd */
2420
    801,
2421
    /* LSRWLoRd */
2422
    804,
2423
    /* LSRWNRd */
2424
    806,
2425
    /* LSRWRd */
2426
    809,
2427
    /* Lsl16 */
2428
    811,
2429
    /* Lsl32 */
2430
    814,
2431
    /* Lsl8 */
2432
    819,
2433
    /* Lsr16 */
2434
    822,
2435
    /* Lsr32 */
2436
    825,
2437
    /* Lsr8 */
2438
    830,
2439
    /* NEGWRd */
2440
    833,
2441
    /* ORIWRdK */
2442
    836,
2443
    /* ORWRdRr */
2444
    839,
2445
    /* OUTWARr */
2446
    842,
2447
    /* POPWRd */
2448
    844,
2449
    /* PUSHWRr */
2450
    845,
2451
    /* ROLBRdR1 */
2452
    846,
2453
    /* ROLBRdR17 */
2454
    848,
2455
    /* ROLWRd */
2456
    850,
2457
    /* RORBRd */
2458
    852,
2459
    /* RORWRd */
2460
    854,
2461
    /* Rol16 */
2462
    856,
2463
    /* Rol8 */
2464
    859,
2465
    /* Ror16 */
2466
    862,
2467
    /* Ror8 */
2468
    865,
2469
    /* SBCIWRdK */
2470
    868,
2471
    /* SBCWRdRr */
2472
    871,
2473
    /* SEXT */
2474
    874,
2475
    /* SPREAD */
2476
    876,
2477
    /* SPWRITE */
2478
    878,
2479
    /* STDSPQRr */
2480
    880,
2481
    /* STDWPtrQRr */
2482
    883,
2483
    /* STDWSPQRr */
2484
    886,
2485
    /* STSWKRr */
2486
    889,
2487
    /* STWPtrPdRr */
2488
    891,
2489
    /* STWPtrPiRr */
2490
    895,
2491
    /* STWPtrRr */
2492
    899,
2493
    /* SUBIWRdK */
2494
    901,
2495
    /* SUBWRdRr */
2496
    904,
2497
    /* Select16 */
2498
    907,
2499
    /* Select8 */
2500
    911,
2501
    /* ZEXT */
2502
    915,
2503
    /* ADCRdRr */
2504
    917,
2505
    /* ADDRdRr */
2506
    920,
2507
    /* ADIWRdK */
2508
    923,
2509
    /* ANDIRdK */
2510
    926,
2511
    /* ANDRdRr */
2512
    929,
2513
    /* ASRRd */
2514
    932,
2515
    /* BCLRs */
2516
    934,
2517
    /* BLD */
2518
    935,
2519
    /* BRBCsk */
2520
    938,
2521
    /* BRBSsk */
2522
    940,
2523
    /* BREAK */
2524
    942,
2525
    /* BREQk */
2526
    942,
2527
    /* BRGEk */
2528
    943,
2529
    /* BRLOk */
2530
    944,
2531
    /* BRLTk */
2532
    945,
2533
    /* BRMIk */
2534
    946,
2535
    /* BRNEk */
2536
    947,
2537
    /* BRPLk */
2538
    948,
2539
    /* BRSHk */
2540
    949,
2541
    /* BSETs */
2542
    950,
2543
    /* BST */
2544
    951,
2545
    /* CALLk */
2546
    953,
2547
    /* CBIAb */
2548
    954,
2549
    /* COMRd */
2550
    956,
2551
    /* CPCRdRr */
2552
    958,
2553
    /* CPIRdK */
2554
    960,
2555
    /* CPRdRr */
2556
    962,
2557
    /* CPSE */
2558
    964,
2559
    /* DECRd */
2560
    966,
2561
    /* DESK */
2562
    968,
2563
    /* EICALL */
2564
    969,
2565
    /* EIJMP */
2566
    969,
2567
    /* ELPM */
2568
    969,
2569
    /* ELPMRdZ */
2570
    969,
2571
    /* ELPMRdZPi */
2572
    971,
2573
    /* EORRdRr */
2574
    973,
2575
    /* FMUL */
2576
    976,
2577
    /* FMULS */
2578
    978,
2579
    /* FMULSU */
2580
    980,
2581
    /* ICALL */
2582
    982,
2583
    /* IJMP */
2584
    982,
2585
    /* INCRd */
2586
    982,
2587
    /* INRdA */
2588
    984,
2589
    /* JMPk */
2590
    986,
2591
    /* LACZRd */
2592
    987,
2593
    /* LASZRd */
2594
    989,
2595
    /* LATZRd */
2596
    991,
2597
    /* LDDRdPtrQ */
2598
    993,
2599
    /* LDIRdK */
2600
    996,
2601
    /* LDRdPtr */
2602
    998,
2603
    /* LDRdPtrPd */
2604
    1000,
2605
    /* LDRdPtrPi */
2606
    1003,
2607
    /* LDSRdK */
2608
    1006,
2609
    /* LDSRdKTiny */
2610
    1008,
2611
    /* LPM */
2612
    1010,
2613
    /* LPMRdZ */
2614
    1010,
2615
    /* LPMRdZPi */
2616
    1012,
2617
    /* LSRRd */
2618
    1014,
2619
    /* MOVRdRr */
2620
    1016,
2621
    /* MOVWRdRr */
2622
    1018,
2623
    /* MULRdRr */
2624
    1020,
2625
    /* MULSRdRr */
2626
    1022,
2627
    /* MULSURdRr */
2628
    1024,
2629
    /* NEGRd */
2630
    1026,
2631
    /* NOP */
2632
    1028,
2633
    /* ORIRdK */
2634
    1028,
2635
    /* ORRdRr */
2636
    1031,
2637
    /* OUTARr */
2638
    1034,
2639
    /* POPRd */
2640
    1036,
2641
    /* PUSHRr */
2642
    1037,
2643
    /* RCALLk */
2644
    1038,
2645
    /* RET */
2646
    1039,
2647
    /* RETI */
2648
    1039,
2649
    /* RJMPk */
2650
    1039,
2651
    /* RORRd */
2652
    1040,
2653
    /* SBCIRdK */
2654
    1042,
2655
    /* SBCRdRr */
2656
    1045,
2657
    /* SBIAb */
2658
    1048,
2659
    /* SBICAb */
2660
    1050,
2661
    /* SBISAb */
2662
    1052,
2663
    /* SBIWRdK */
2664
    1054,
2665
    /* SBRCRrB */
2666
    1057,
2667
    /* SBRSRrB */
2668
    1059,
2669
    /* SLEEP */
2670
    1061,
2671
    /* SPM */
2672
    1061,
2673
    /* SPMZPi */
2674
    1061,
2675
    /* STDPtrQRr */
2676
    1062,
2677
    /* STPtrPdRr */
2678
    1065,
2679
    /* STPtrPiRr */
2680
    1069,
2681
    /* STPtrRr */
2682
    1073,
2683
    /* STSKRr */
2684
    1075,
2685
    /* STSKRrTiny */
2686
    1077,
2687
    /* SUBIRdK */
2688
    1079,
2689
    /* SUBRdRr */
2690
    1082,
2691
    /* SWAPRd */
2692
    1085,
2693
    /* WDR */
2694
    1087,
2695
    /* XCHZRd */
2696
    1087,
2697
  };
2698
2699
  using namespace OpTypes;
2700
  static const int8_t OpcodeOperandTypes[] = {
2701
    
2702
    /* PHI */
2703
    -1, 
2704
    /* INLINEASM */
2705
    /* INLINEASM_BR */
2706
    /* CFI_INSTRUCTION */
2707
    i32imm, 
2708
    /* EH_LABEL */
2709
    i32imm, 
2710
    /* GC_LABEL */
2711
    i32imm, 
2712
    /* ANNOTATION_LABEL */
2713
    i32imm, 
2714
    /* KILL */
2715
    /* EXTRACT_SUBREG */
2716
    -1, -1, i32imm, 
2717
    /* INSERT_SUBREG */
2718
    -1, -1, -1, i32imm, 
2719
    /* IMPLICIT_DEF */
2720
    -1, 
2721
    /* SUBREG_TO_REG */
2722
    -1, -1, -1, i32imm, 
2723
    /* COPY_TO_REGCLASS */
2724
    -1, -1, i32imm, 
2725
    /* DBG_VALUE */
2726
    /* DBG_VALUE_LIST */
2727
    /* DBG_INSTR_REF */
2728
    /* DBG_PHI */
2729
    /* DBG_LABEL */
2730
    -1, 
2731
    /* REG_SEQUENCE */
2732
    -1, -1, 
2733
    /* COPY */
2734
    -1, -1, 
2735
    /* BUNDLE */
2736
    /* LIFETIME_START */
2737
    i32imm, 
2738
    /* LIFETIME_END */
2739
    i32imm, 
2740
    /* PSEUDO_PROBE */
2741
    i64imm, i64imm, i8imm, i32imm, 
2742
    /* ARITH_FENCE */
2743
    -1, -1, 
2744
    /* STACKMAP */
2745
    i64imm, i32imm, 
2746
    /* FENTRY_CALL */
2747
    /* PATCHPOINT */
2748
    -1, i64imm, i32imm, -1, i32imm, i32imm, 
2749
    /* LOAD_STACK_GUARD */
2750
    -1, 
2751
    /* PREALLOCATED_SETUP */
2752
    i32imm, 
2753
    /* PREALLOCATED_ARG */
2754
    -1, i32imm, i32imm, 
2755
    /* STATEPOINT */
2756
    /* LOCAL_ESCAPE */
2757
    -1, i32imm, 
2758
    /* FAULTING_OP */
2759
    -1, 
2760
    /* PATCHABLE_OP */
2761
    /* PATCHABLE_FUNCTION_ENTER */
2762
    /* PATCHABLE_RET */
2763
    /* PATCHABLE_FUNCTION_EXIT */
2764
    /* PATCHABLE_TAIL_CALL */
2765
    /* PATCHABLE_EVENT_CALL */
2766
    -1, -1, 
2767
    /* PATCHABLE_TYPED_EVENT_CALL */
2768
    -1, -1, -1, 
2769
    /* ICALL_BRANCH_FUNNEL */
2770
    /* MEMBARRIER */
2771
    /* JUMP_TABLE_DEBUG_INFO */
2772
    i64imm, 
2773
    /* G_ASSERT_SEXT */
2774
    type0, type0, untyped_imm_0, 
2775
    /* G_ASSERT_ZEXT */
2776
    type0, type0, untyped_imm_0, 
2777
    /* G_ASSERT_ALIGN */
2778
    type0, type0, untyped_imm_0, 
2779
    /* G_ADD */
2780
    type0, type0, type0, 
2781
    /* G_SUB */
2782
    type0, type0, type0, 
2783
    /* G_MUL */
2784
    type0, type0, type0, 
2785
    /* G_SDIV */
2786
    type0, type0, type0, 
2787
    /* G_UDIV */
2788
    type0, type0, type0, 
2789
    /* G_SREM */
2790
    type0, type0, type0, 
2791
    /* G_UREM */
2792
    type0, type0, type0, 
2793
    /* G_SDIVREM */
2794
    type0, type0, type0, type0, 
2795
    /* G_UDIVREM */
2796
    type0, type0, type0, type0, 
2797
    /* G_AND */
2798
    type0, type0, type0, 
2799
    /* G_OR */
2800
    type0, type0, type0, 
2801
    /* G_XOR */
2802
    type0, type0, type0, 
2803
    /* G_IMPLICIT_DEF */
2804
    type0, 
2805
    /* G_PHI */
2806
    type0, 
2807
    /* G_FRAME_INDEX */
2808
    type0, -1, 
2809
    /* G_GLOBAL_VALUE */
2810
    type0, -1, 
2811
    /* G_CONSTANT_POOL */
2812
    type0, -1, 
2813
    /* G_EXTRACT */
2814
    type0, type1, untyped_imm_0, 
2815
    /* G_UNMERGE_VALUES */
2816
    type0, type1, 
2817
    /* G_INSERT */
2818
    type0, type0, type1, untyped_imm_0, 
2819
    /* G_MERGE_VALUES */
2820
    type0, type1, 
2821
    /* G_BUILD_VECTOR */
2822
    type0, type1, 
2823
    /* G_BUILD_VECTOR_TRUNC */
2824
    type0, type1, 
2825
    /* G_CONCAT_VECTORS */
2826
    type0, type1, 
2827
    /* G_PTRTOINT */
2828
    type0, type1, 
2829
    /* G_INTTOPTR */
2830
    type0, type1, 
2831
    /* G_BITCAST */
2832
    type0, type1, 
2833
    /* G_FREEZE */
2834
    type0, type0, 
2835
    /* G_CONSTANT_FOLD_BARRIER */
2836
    type0, type0, 
2837
    /* G_INTRINSIC_FPTRUNC_ROUND */
2838
    type0, type1, i32imm, 
2839
    /* G_INTRINSIC_TRUNC */
2840
    type0, type0, 
2841
    /* G_INTRINSIC_ROUND */
2842
    type0, type0, 
2843
    /* G_INTRINSIC_LRINT */
2844
    type0, type1, 
2845
    /* G_INTRINSIC_ROUNDEVEN */
2846
    type0, type0, 
2847
    /* G_READCYCLECOUNTER */
2848
    type0, 
2849
    /* G_LOAD */
2850
    type0, ptype1, 
2851
    /* G_SEXTLOAD */
2852
    type0, ptype1, 
2853
    /* G_ZEXTLOAD */
2854
    type0, ptype1, 
2855
    /* G_INDEXED_LOAD */
2856
    type0, ptype1, ptype1, type2, -1, 
2857
    /* G_INDEXED_SEXTLOAD */
2858
    type0, ptype1, ptype1, type2, -1, 
2859
    /* G_INDEXED_ZEXTLOAD */
2860
    type0, ptype1, ptype1, type2, -1, 
2861
    /* G_STORE */
2862
    type0, ptype1, 
2863
    /* G_INDEXED_STORE */
2864
    ptype0, type1, ptype0, ptype2, -1, 
2865
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
2866
    type0, type1, type2, type0, type0, 
2867
    /* G_ATOMIC_CMPXCHG */
2868
    type0, ptype1, type0, type0, 
2869
    /* G_ATOMICRMW_XCHG */
2870
    type0, ptype1, type0, 
2871
    /* G_ATOMICRMW_ADD */
2872
    type0, ptype1, type0, 
2873
    /* G_ATOMICRMW_SUB */
2874
    type0, ptype1, type0, 
2875
    /* G_ATOMICRMW_AND */
2876
    type0, ptype1, type0, 
2877
    /* G_ATOMICRMW_NAND */
2878
    type0, ptype1, type0, 
2879
    /* G_ATOMICRMW_OR */
2880
    type0, ptype1, type0, 
2881
    /* G_ATOMICRMW_XOR */
2882
    type0, ptype1, type0, 
2883
    /* G_ATOMICRMW_MAX */
2884
    type0, ptype1, type0, 
2885
    /* G_ATOMICRMW_MIN */
2886
    type0, ptype1, type0, 
2887
    /* G_ATOMICRMW_UMAX */
2888
    type0, ptype1, type0, 
2889
    /* G_ATOMICRMW_UMIN */
2890
    type0, ptype1, type0, 
2891
    /* G_ATOMICRMW_FADD */
2892
    type0, ptype1, type0, 
2893
    /* G_ATOMICRMW_FSUB */
2894
    type0, ptype1, type0, 
2895
    /* G_ATOMICRMW_FMAX */
2896
    type0, ptype1, type0, 
2897
    /* G_ATOMICRMW_FMIN */
2898
    type0, ptype1, type0, 
2899
    /* G_ATOMICRMW_UINC_WRAP */
2900
    type0, ptype1, type0, 
2901
    /* G_ATOMICRMW_UDEC_WRAP */
2902
    type0, ptype1, type0, 
2903
    /* G_FENCE */
2904
    i32imm, i32imm, 
2905
    /* G_PREFETCH */
2906
    ptype0, i32imm, i32imm, i32imm, 
2907
    /* G_BRCOND */
2908
    type0, -1, 
2909
    /* G_BRINDIRECT */
2910
    type0, 
2911
    /* G_INVOKE_REGION_START */
2912
    /* G_INTRINSIC */
2913
    -1, 
2914
    /* G_INTRINSIC_W_SIDE_EFFECTS */
2915
    -1, 
2916
    /* G_INTRINSIC_CONVERGENT */
2917
    -1, 
2918
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
2919
    -1, 
2920
    /* G_ANYEXT */
2921
    type0, type1, 
2922
    /* G_TRUNC */
2923
    type0, type1, 
2924
    /* G_CONSTANT */
2925
    type0, -1, 
2926
    /* G_FCONSTANT */
2927
    type0, -1, 
2928
    /* G_VASTART */
2929
    type0, 
2930
    /* G_VAARG */
2931
    type0, type1, -1, 
2932
    /* G_SEXT */
2933
    type0, type1, 
2934
    /* G_SEXT_INREG */
2935
    type0, type0, untyped_imm_0, 
2936
    /* G_ZEXT */
2937
    type0, type1, 
2938
    /* G_SHL */
2939
    type0, type0, type1, 
2940
    /* G_LSHR */
2941
    type0, type0, type1, 
2942
    /* G_ASHR */
2943
    type0, type0, type1, 
2944
    /* G_FSHL */
2945
    type0, type0, type0, type1, 
2946
    /* G_FSHR */
2947
    type0, type0, type0, type1, 
2948
    /* G_ROTR */
2949
    type0, type0, type1, 
2950
    /* G_ROTL */
2951
    type0, type0, type1, 
2952
    /* G_ICMP */
2953
    type0, -1, type1, type1, 
2954
    /* G_FCMP */
2955
    type0, -1, type1, type1, 
2956
    /* G_SELECT */
2957
    type0, type1, type0, type0, 
2958
    /* G_UADDO */
2959
    type0, type1, type0, type0, 
2960
    /* G_UADDE */
2961
    type0, type1, type0, type0, type1, 
2962
    /* G_USUBO */
2963
    type0, type1, type0, type0, 
2964
    /* G_USUBE */
2965
    type0, type1, type0, type0, type1, 
2966
    /* G_SADDO */
2967
    type0, type1, type0, type0, 
2968
    /* G_SADDE */
2969
    type0, type1, type0, type0, type1, 
2970
    /* G_SSUBO */
2971
    type0, type1, type0, type0, 
2972
    /* G_SSUBE */
2973
    type0, type1, type0, type0, type1, 
2974
    /* G_UMULO */
2975
    type0, type1, type0, type0, 
2976
    /* G_SMULO */
2977
    type0, type1, type0, type0, 
2978
    /* G_UMULH */
2979
    type0, type0, type0, 
2980
    /* G_SMULH */
2981
    type0, type0, type0, 
2982
    /* G_UADDSAT */
2983
    type0, type0, type0, 
2984
    /* G_SADDSAT */
2985
    type0, type0, type0, 
2986
    /* G_USUBSAT */
2987
    type0, type0, type0, 
2988
    /* G_SSUBSAT */
2989
    type0, type0, type0, 
2990
    /* G_USHLSAT */
2991
    type0, type0, type1, 
2992
    /* G_SSHLSAT */
2993
    type0, type0, type1, 
2994
    /* G_SMULFIX */
2995
    type0, type0, type0, untyped_imm_0, 
2996
    /* G_UMULFIX */
2997
    type0, type0, type0, untyped_imm_0, 
2998
    /* G_SMULFIXSAT */
2999
    type0, type0, type0, untyped_imm_0, 
3000
    /* G_UMULFIXSAT */
3001
    type0, type0, type0, untyped_imm_0, 
3002
    /* G_SDIVFIX */
3003
    type0, type0, type0, untyped_imm_0, 
3004
    /* G_UDIVFIX */
3005
    type0, type0, type0, untyped_imm_0, 
3006
    /* G_SDIVFIXSAT */
3007
    type0, type0, type0, untyped_imm_0, 
3008
    /* G_UDIVFIXSAT */
3009
    type0, type0, type0, untyped_imm_0, 
3010
    /* G_FADD */
3011
    type0, type0, type0, 
3012
    /* G_FSUB */
3013
    type0, type0, type0, 
3014
    /* G_FMUL */
3015
    type0, type0, type0, 
3016
    /* G_FMA */
3017
    type0, type0, type0, type0, 
3018
    /* G_FMAD */
3019
    type0, type0, type0, type0, 
3020
    /* G_FDIV */
3021
    type0, type0, type0, 
3022
    /* G_FREM */
3023
    type0, type0, type0, 
3024
    /* G_FPOW */
3025
    type0, type0, type0, 
3026
    /* G_FPOWI */
3027
    type0, type0, type1, 
3028
    /* G_FEXP */
3029
    type0, type0, 
3030
    /* G_FEXP2 */
3031
    type0, type0, 
3032
    /* G_FEXP10 */
3033
    type0, type0, 
3034
    /* G_FLOG */
3035
    type0, type0, 
3036
    /* G_FLOG2 */
3037
    type0, type0, 
3038
    /* G_FLOG10 */
3039
    type0, type0, 
3040
    /* G_FLDEXP */
3041
    type0, type0, type1, 
3042
    /* G_FFREXP */
3043
    type0, type1, type0, 
3044
    /* G_FNEG */
3045
    type0, type0, 
3046
    /* G_FPEXT */
3047
    type0, type1, 
3048
    /* G_FPTRUNC */
3049
    type0, type1, 
3050
    /* G_FPTOSI */
3051
    type0, type1, 
3052
    /* G_FPTOUI */
3053
    type0, type1, 
3054
    /* G_SITOFP */
3055
    type0, type1, 
3056
    /* G_UITOFP */
3057
    type0, type1, 
3058
    /* G_FABS */
3059
    type0, type0, 
3060
    /* G_FCOPYSIGN */
3061
    type0, type0, type1, 
3062
    /* G_IS_FPCLASS */
3063
    type0, type1, -1, 
3064
    /* G_FCANONICALIZE */
3065
    type0, type0, 
3066
    /* G_FMINNUM */
3067
    type0, type0, type0, 
3068
    /* G_FMAXNUM */
3069
    type0, type0, type0, 
3070
    /* G_FMINNUM_IEEE */
3071
    type0, type0, type0, 
3072
    /* G_FMAXNUM_IEEE */
3073
    type0, type0, type0, 
3074
    /* G_FMINIMUM */
3075
    type0, type0, type0, 
3076
    /* G_FMAXIMUM */
3077
    type0, type0, type0, 
3078
    /* G_GET_FPENV */
3079
    type0, 
3080
    /* G_SET_FPENV */
3081
    type0, 
3082
    /* G_RESET_FPENV */
3083
    /* G_GET_FPMODE */
3084
    type0, 
3085
    /* G_SET_FPMODE */
3086
    type0, 
3087
    /* G_RESET_FPMODE */
3088
    /* G_PTR_ADD */
3089
    ptype0, ptype0, type1, 
3090
    /* G_PTRMASK */
3091
    ptype0, ptype0, type1, 
3092
    /* G_SMIN */
3093
    type0, type0, type0, 
3094
    /* G_SMAX */
3095
    type0, type0, type0, 
3096
    /* G_UMIN */
3097
    type0, type0, type0, 
3098
    /* G_UMAX */
3099
    type0, type0, type0, 
3100
    /* G_ABS */
3101
    type0, type0, 
3102
    /* G_LROUND */
3103
    type0, type1, 
3104
    /* G_LLROUND */
3105
    type0, type1, 
3106
    /* G_BR */
3107
    -1, 
3108
    /* G_BRJT */
3109
    ptype0, -1, type1, 
3110
    /* G_INSERT_VECTOR_ELT */
3111
    type0, type0, type1, type2, 
3112
    /* G_EXTRACT_VECTOR_ELT */
3113
    type0, type1, type2, 
3114
    /* G_SHUFFLE_VECTOR */
3115
    type0, type1, type1, -1, 
3116
    /* G_CTTZ */
3117
    type0, type1, 
3118
    /* G_CTTZ_ZERO_UNDEF */
3119
    type0, type1, 
3120
    /* G_CTLZ */
3121
    type0, type1, 
3122
    /* G_CTLZ_ZERO_UNDEF */
3123
    type0, type1, 
3124
    /* G_CTPOP */
3125
    type0, type1, 
3126
    /* G_BSWAP */
3127
    type0, type0, 
3128
    /* G_BITREVERSE */
3129
    type0, type0, 
3130
    /* G_FCEIL */
3131
    type0, type0, 
3132
    /* G_FCOS */
3133
    type0, type0, 
3134
    /* G_FSIN */
3135
    type0, type0, 
3136
    /* G_FSQRT */
3137
    type0, type0, 
3138
    /* G_FFLOOR */
3139
    type0, type0, 
3140
    /* G_FRINT */
3141
    type0, type0, 
3142
    /* G_FNEARBYINT */
3143
    type0, type0, 
3144
    /* G_ADDRSPACE_CAST */
3145
    type0, type1, 
3146
    /* G_BLOCK_ADDR */
3147
    type0, -1, 
3148
    /* G_JUMP_TABLE */
3149
    type0, -1, 
3150
    /* G_DYN_STACKALLOC */
3151
    ptype0, type1, i32imm, 
3152
    /* G_STACKSAVE */
3153
    ptype0, 
3154
    /* G_STACKRESTORE */
3155
    ptype0, 
3156
    /* G_STRICT_FADD */
3157
    type0, type0, type0, 
3158
    /* G_STRICT_FSUB */
3159
    type0, type0, type0, 
3160
    /* G_STRICT_FMUL */
3161
    type0, type0, type0, 
3162
    /* G_STRICT_FDIV */
3163
    type0, type0, type0, 
3164
    /* G_STRICT_FREM */
3165
    type0, type0, type0, 
3166
    /* G_STRICT_FMA */
3167
    type0, type0, type0, type0, 
3168
    /* G_STRICT_FSQRT */
3169
    type0, type0, 
3170
    /* G_STRICT_FLDEXP */
3171
    type0, type0, type1, 
3172
    /* G_READ_REGISTER */
3173
    type0, -1, 
3174
    /* G_WRITE_REGISTER */
3175
    -1, type0, 
3176
    /* G_MEMCPY */
3177
    ptype0, ptype1, type2, untyped_imm_0, 
3178
    /* G_MEMCPY_INLINE */
3179
    ptype0, ptype1, type2, 
3180
    /* G_MEMMOVE */
3181
    ptype0, ptype1, type2, untyped_imm_0, 
3182
    /* G_MEMSET */
3183
    ptype0, type1, type2, untyped_imm_0, 
3184
    /* G_BZERO */
3185
    ptype0, type1, untyped_imm_0, 
3186
    /* G_VECREDUCE_SEQ_FADD */
3187
    type0, type1, type2, 
3188
    /* G_VECREDUCE_SEQ_FMUL */
3189
    type0, type1, type2, 
3190
    /* G_VECREDUCE_FADD */
3191
    type0, type1, 
3192
    /* G_VECREDUCE_FMUL */
3193
    type0, type1, 
3194
    /* G_VECREDUCE_FMAX */
3195
    type0, type1, 
3196
    /* G_VECREDUCE_FMIN */
3197
    type0, type1, 
3198
    /* G_VECREDUCE_FMAXIMUM */
3199
    type0, type1, 
3200
    /* G_VECREDUCE_FMINIMUM */
3201
    type0, type1, 
3202
    /* G_VECREDUCE_ADD */
3203
    type0, type1, 
3204
    /* G_VECREDUCE_MUL */
3205
    type0, type1, 
3206
    /* G_VECREDUCE_AND */
3207
    type0, type1, 
3208
    /* G_VECREDUCE_OR */
3209
    type0, type1, 
3210
    /* G_VECREDUCE_XOR */
3211
    type0, type1, 
3212
    /* G_VECREDUCE_SMAX */
3213
    type0, type1, 
3214
    /* G_VECREDUCE_SMIN */
3215
    type0, type1, 
3216
    /* G_VECREDUCE_UMAX */
3217
    type0, type1, 
3218
    /* G_VECREDUCE_UMIN */
3219
    type0, type1, 
3220
    /* G_SBFX */
3221
    type0, type0, type1, type1, 
3222
    /* G_UBFX */
3223
    type0, type0, type1, type1, 
3224
    /* ADCWRdRr */
3225
    DREGS, DREGS, DREGS, 
3226
    /* ADDWRdRr */
3227
    DREGS, DREGS, DREGS, 
3228
    /* ADJCALLSTACKDOWN */
3229
    i16imm, i16imm, 
3230
    /* ADJCALLSTACKUP */
3231
    i16imm, i16imm, 
3232
    /* ANDIWRdK */
3233
    DLDREGS, DLDREGS, i16imm, 
3234
    /* ANDWRdRr */
3235
    DREGS, DREGS, DREGS, 
3236
    /* ASRBNRd */
3237
    LD8, GPR8, imm_ldi8, 
3238
    /* ASRWLoRd */
3239
    DREGS, DREGS, 
3240
    /* ASRWNRd */
3241
    DREGS, DREGS, imm16, 
3242
    /* ASRWRd */
3243
    DREGS, DREGS, 
3244
    /* Asr16 */
3245
    DREGS, DREGS, GPR8, 
3246
    /* Asr32 */
3247
    DREGS, DREGS, DREGS, DREGS, i8imm, 
3248
    /* Asr8 */
3249
    GPR8, GPR8, GPR8, 
3250
    /* AtomicFence */
3251
    /* AtomicLoad16 */
3252
    DREGS, PTRDISPREGS, 
3253
    /* AtomicLoad8 */
3254
    GPR8, PTRREGS, 
3255
    /* AtomicLoadAdd16 */
3256
    DREGS, PTRDISPREGS, DREGS, 
3257
    /* AtomicLoadAdd8 */
3258
    GPR8, PTRREGS, GPR8, 
3259
    /* AtomicLoadAnd16 */
3260
    DREGS, PTRDISPREGS, DREGS, 
3261
    /* AtomicLoadAnd8 */
3262
    GPR8, PTRREGS, GPR8, 
3263
    /* AtomicLoadOr16 */
3264
    DREGS, PTRDISPREGS, DREGS, 
3265
    /* AtomicLoadOr8 */
3266
    GPR8, PTRREGS, GPR8, 
3267
    /* AtomicLoadSub16 */
3268
    DREGS, PTRDISPREGS, DREGS, 
3269
    /* AtomicLoadSub8 */
3270
    GPR8, PTRREGS, GPR8, 
3271
    /* AtomicLoadXor16 */
3272
    DREGS, PTRDISPREGS, DREGS, 
3273
    /* AtomicLoadXor8 */
3274
    GPR8, PTRREGS, GPR8, 
3275
    /* AtomicStore16 */
3276
    PTRDISPREGS, DREGS, 
3277
    /* AtomicStore8 */
3278
    PTRREGS, GPR8, 
3279
    /* COMWRd */
3280
    DREGS, DREGS, 
3281
    /* CPCWRdRr */
3282
    DREGS, DREGS, 
3283
    /* CPWRdRr */
3284
    DREGS, DREGS, 
3285
    /* CopyZero */
3286
    GPR8, 
3287
    /* ELPMBRdZ */
3288
    GPR8, ZREG, LD8, 
3289
    /* ELPMBRdZPi */
3290
    GPR8, ZREG, LD8, 
3291
    /* ELPMWRdZ */
3292
    DREGS, ZREG, LD8, 
3293
    /* ELPMWRdZPi */
3294
    DREGS, ZREG, LD8, 
3295
    /* EORWRdRr */
3296
    DREGS, DREGS, DREGS, 
3297
    /* FRMIDX */
3298
    DLDREGS, DLDREGS, i16imm, 
3299
    /* INWRdA */
3300
    DREGS, imm_port6, 
3301
    /* LDDWRdPtrQ */
3302
    DREGS, PTRDISPREGS, i16imm, 
3303
    /* LDDWRdYQ */
3304
    DREGS, PTRDISPREGS, i16imm, 
3305
    /* LDIWRdK */
3306
    DLDREGS, i16imm, 
3307
    /* LDSWRdK */
3308
    DREGS, i16imm, 
3309
    /* LDWRdPtr */
3310
    DREGS, PTRDISPREGS, 
3311
    /* LDWRdPtrPd */
3312
    DREGS, PTRREGS, PTRREGS, 
3313
    /* LDWRdPtrPi */
3314
    DREGS, PTRREGS, PTRREGS, 
3315
    /* LPMBRdZ */
3316
    GPR8, ZREG, 
3317
    /* LPMWRdZ */
3318
    DREGS, ZREG, 
3319
    /* LPMWRdZPi */
3320
    DREGS, ZREG, 
3321
    /* LSLBNRd */
3322
    LD8, GPR8, imm_ldi8, 
3323
    /* LSLWHiRd */
3324
    DREGS, DREGS, 
3325
    /* LSLWNRd */
3326
    DLDREGS, DREGS, imm16, 
3327
    /* LSLWRd */
3328
    DREGS, DREGS, 
3329
    /* LSRBNRd */
3330
    LD8, GPR8, imm_ldi8, 
3331
    /* LSRWLoRd */
3332
    DREGS, DREGS, 
3333
    /* LSRWNRd */
3334
    DLDREGS, DREGS, imm16, 
3335
    /* LSRWRd */
3336
    DREGS, DREGS, 
3337
    /* Lsl16 */
3338
    DREGS, DREGS, GPR8, 
3339
    /* Lsl32 */
3340
    DREGS, DREGS, DREGS, DREGS, i8imm, 
3341
    /* Lsl8 */
3342
    GPR8, GPR8, GPR8, 
3343
    /* Lsr16 */
3344
    DREGS, DREGS, GPR8, 
3345
    /* Lsr32 */
3346
    DREGS, DREGS, DREGS, DREGS, i8imm, 
3347
    /* Lsr8 */
3348
    GPR8, GPR8, GPR8, 
3349
    /* NEGWRd */
3350
    DREGS, DREGS, GPR8, 
3351
    /* ORIWRdK */
3352
    DLDREGS, DLDREGS, i16imm, 
3353
    /* ORWRdRr */
3354
    DREGS, DREGS, DREGS, 
3355
    /* OUTWARr */
3356
    imm_port6, DREGS, 
3357
    /* POPWRd */
3358
    DREGS, 
3359
    /* PUSHWRr */
3360
    DREGS, 
3361
    /* ROLBRdR1 */
3362
    GPR8, GPR8, 
3363
    /* ROLBRdR17 */
3364
    GPR8, GPR8, 
3365
    /* ROLWRd */
3366
    DREGS, DREGS, 
3367
    /* RORBRd */
3368
    GPR8, GPR8, 
3369
    /* RORWRd */
3370
    DREGS, DREGS, 
3371
    /* Rol16 */
3372
    DREGS, DREGS, GPR8, 
3373
    /* Rol8 */
3374
    GPR8, GPR8, GPR8, 
3375
    /* Ror16 */
3376
    DREGS, DREGS, GPR8, 
3377
    /* Ror8 */
3378
    GPR8, GPR8, GPR8, 
3379
    /* SBCIWRdK */
3380
    DLDREGS, DLDREGS, i16imm, 
3381
    /* SBCWRdRr */
3382
    DREGS, DREGS, DREGS, 
3383
    /* SEXT */
3384
    DREGS, GPR8, 
3385
    /* SPREAD */
3386
    DREGS, GPRSP, 
3387
    /* SPWRITE */
3388
    GPRSP, DREGS, 
3389
    /* STDSPQRr */
3390
    GPRSP, i16imm, GPR8, 
3391
    /* STDWPtrQRr */
3392
    PTRDISPREGS, i16imm, DREGS, 
3393
    /* STDWSPQRr */
3394
    GPRSP, i16imm, DREGS, 
3395
    /* STSWKRr */
3396
    i16imm, DREGS, 
3397
    /* STWPtrPdRr */
3398
    PTRREGS, PTRREGS, DREGS, i8imm, 
3399
    /* STWPtrPiRr */
3400
    PTRREGS, PTRREGS, DREGS, i8imm, 
3401
    /* STWPtrRr */
3402
    PTRDISPREGS, DREGS, 
3403
    /* SUBIWRdK */
3404
    DLDREGS, DLDREGS, i16imm, 
3405
    /* SUBWRdRr */
3406
    DREGS, DREGS, DREGS, 
3407
    /* Select16 */
3408
    DREGS, DREGS, DREGS, i8imm, 
3409
    /* Select8 */
3410
    GPR8, GPR8, GPR8, i8imm, 
3411
    /* ZEXT */
3412
    DREGS, GPR8, 
3413
    /* ADCRdRr */
3414
    GPR8, GPR8, GPR8, 
3415
    /* ADDRdRr */
3416
    GPR8, GPR8, GPR8, 
3417
    /* ADIWRdK */
3418
    IWREGS, IWREGS, imm_arith6, 
3419
    /* ANDIRdK */
3420
    LD8, LD8, imm_ldi8, 
3421
    /* ANDRdRr */
3422
    GPR8, GPR8, GPR8, 
3423
    /* ASRRd */
3424
    GPR8, GPR8, 
3425
    /* BCLRs */
3426
    i8imm, 
3427
    /* BLD */
3428
    GPR8, GPR8, i8imm, 
3429
    /* BRBCsk */
3430
    i8imm, relbrtarget_7, 
3431
    /* BRBSsk */
3432
    i8imm, relbrtarget_7, 
3433
    /* BREAK */
3434
    /* BREQk */
3435
    relbrtarget_7, 
3436
    /* BRGEk */
3437
    relbrtarget_7, 
3438
    /* BRLOk */
3439
    relbrtarget_7, 
3440
    /* BRLTk */
3441
    relbrtarget_7, 
3442
    /* BRMIk */
3443
    relbrtarget_7, 
3444
    /* BRNEk */
3445
    relbrtarget_7, 
3446
    /* BRPLk */
3447
    relbrtarget_7, 
3448
    /* BRSHk */
3449
    relbrtarget_7, 
3450
    /* BSETs */
3451
    i8imm, 
3452
    /* BST */
3453
    GPR8, i8imm, 
3454
    /* CALLk */
3455
    call_target, 
3456
    /* CBIAb */
3457
    imm_port5, i8imm, 
3458
    /* COMRd */
3459
    GPR8, GPR8, 
3460
    /* CPCRdRr */
3461
    GPR8, GPR8, 
3462
    /* CPIRdK */
3463
    LD8, imm_ldi8, 
3464
    /* CPRdRr */
3465
    GPR8, GPR8, 
3466
    /* CPSE */
3467
    GPR8, GPR8, 
3468
    /* DECRd */
3469
    GPR8, GPR8, 
3470
    /* DESK */
3471
    i8imm, 
3472
    /* EICALL */
3473
    /* EIJMP */
3474
    /* ELPM */
3475
    /* ELPMRdZ */
3476
    GPR8, ZREG, 
3477
    /* ELPMRdZPi */
3478
    GPR8, ZREG, 
3479
    /* EORRdRr */
3480
    GPR8, GPR8, GPR8, 
3481
    /* FMUL */
3482
    LD8lo, LD8lo, 
3483
    /* FMULS */
3484
    LD8lo, LD8lo, 
3485
    /* FMULSU */
3486
    LD8lo, LD8lo, 
3487
    /* ICALL */
3488
    /* IJMP */
3489
    /* INCRd */
3490
    GPR8, GPR8, 
3491
    /* INRdA */
3492
    GPR8, imm_port6, 
3493
    /* JMPk */
3494
    call_target, 
3495
    /* LACZRd */
3496
    GPR8, ZREG, 
3497
    /* LASZRd */
3498
    GPR8, ZREG, 
3499
    /* LATZRd */
3500
    GPR8, ZREG, 
3501
    /* LDDRdPtrQ */
3502
    GPR8, PTRDISPREGS, i16imm, 
3503
    /* LDIRdK */
3504
    LD8, imm_ldi8, 
3505
    /* LDRdPtr */
3506
    GPR8, PTRREGS, 
3507
    /* LDRdPtrPd */
3508
    GPR8, PTRREGS, PTRREGS, 
3509
    /* LDRdPtrPi */
3510
    GPR8, PTRREGS, PTRREGS, 
3511
    /* LDSRdK */
3512
    GPR8, imm16, 
3513
    /* LDSRdKTiny */
3514
    LD8, imm7tiny, 
3515
    /* LPM */
3516
    /* LPMRdZ */
3517
    GPR8, ZREG, 
3518
    /* LPMRdZPi */
3519
    GPR8, ZREG, 
3520
    /* LSRRd */
3521
    GPR8, GPR8, 
3522
    /* MOVRdRr */
3523
    GPR8, GPR8, 
3524
    /* MOVWRdRr */
3525
    DREGS, DREGS, 
3526
    /* MULRdRr */
3527
    GPR8, GPR8, 
3528
    /* MULSRdRr */
3529
    LD8, LD8, 
3530
    /* MULSURdRr */
3531
    LD8lo, LD8lo, 
3532
    /* NEGRd */
3533
    GPR8, GPR8, 
3534
    /* NOP */
3535
    /* ORIRdK */
3536
    LD8, LD8, imm_ldi8, 
3537
    /* ORRdRr */
3538
    GPR8, GPR8, GPR8, 
3539
    /* OUTARr */
3540
    imm_port6, GPR8, 
3541
    /* POPRd */
3542
    GPR8, 
3543
    /* PUSHRr */
3544
    GPR8, 
3545
    /* RCALLk */
3546
    rcalltarget_13, 
3547
    /* RET */
3548
    /* RETI */
3549
    /* RJMPk */
3550
    brtarget_13, 
3551
    /* RORRd */
3552
    GPR8, GPR8, 
3553
    /* SBCIRdK */
3554
    LD8, LD8, imm_ldi8, 
3555
    /* SBCRdRr */
3556
    GPR8, GPR8, GPR8, 
3557
    /* SBIAb */
3558
    imm_port5, i8imm, 
3559
    /* SBICAb */
3560
    imm_port5, i8imm, 
3561
    /* SBISAb */
3562
    imm_port5, i8imm, 
3563
    /* SBIWRdK */
3564
    IWREGS, IWREGS, imm_arith6, 
3565
    /* SBRCRrB */
3566
    GPR8, i8imm, 
3567
    /* SBRSRrB */
3568
    GPR8, i8imm, 
3569
    /* SLEEP */
3570
    /* SPM */
3571
    /* SPMZPi */
3572
    ZREG, 
3573
    /* STDPtrQRr */
3574
    PTRDISPREGS, i16imm, GPR8, 
3575
    /* STPtrPdRr */
3576
    PTRREGS, PTRREGS, GPR8, i8imm, 
3577
    /* STPtrPiRr */
3578
    PTRREGS, PTRREGS, GPR8, i8imm, 
3579
    /* STPtrRr */
3580
    PTRREGS, GPR8, 
3581
    /* STSKRr */
3582
    imm16, GPR8, 
3583
    /* STSKRrTiny */
3584
    imm7tiny, LD8, 
3585
    /* SUBIRdK */
3586
    LD8, LD8, imm_ldi8, 
3587
    /* SUBRdRr */
3588
    GPR8, GPR8, GPR8, 
3589
    /* SWAPRd */
3590
    GPR8, GPR8, 
3591
    /* WDR */
3592
    /* XCHZRd */
3593
    GPR8, ZREG, 
3594
  };
3595
  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
3596
}
3597
} // end namespace AVR
3598
} // end namespace llvm
3599
#endif // GET_INSTRINFO_OPERAND_TYPE
3600
3601
#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
3602
#undef GET_INSTRINFO_MEM_OPERAND_SIZE
3603
namespace llvm {
3604
namespace AVR {
3605
LLVM_READONLY
3606
static int getMemOperandSize(int OpType) {
3607
  switch (OpType) {
3608
  default: return 0;
3609
  }
3610
}
3611
} // end namespace AVR
3612
} // end namespace llvm
3613
#endif // GET_INSTRINFO_MEM_OPERAND_SIZE
3614
3615
#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
3616
#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
3617
namespace llvm {
3618
namespace AVR {
3619
LLVM_READONLY static unsigned
3620
getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
3621
  return LogicalOpIdx;
3622
}
3623
LLVM_READONLY static inline unsigned
3624
getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
3625
  auto S = 0U;
3626
  for (auto i = 0U; i < LogicalOpIdx; ++i)
3627
    S += getLogicalOperandSize(Opcode, i);
3628
  return S;
3629
}
3630
} // end namespace AVR
3631
} // end namespace llvm
3632
#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
3633
3634
#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
3635
#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
3636
namespace llvm {
3637
namespace AVR {
3638
LLVM_READONLY static int
3639
getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
3640
  return -1;
3641
}
3642
} // end namespace AVR
3643
} // end namespace llvm
3644
#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
3645
3646
#ifdef GET_INSTRINFO_MC_HELPER_DECLS
3647
#undef GET_INSTRINFO_MC_HELPER_DECLS
3648
3649
namespace llvm {
3650
class MCInst;
3651
class FeatureBitset;
3652
3653
namespace AVR_MC {
3654
3655
void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
3656
3657
} // end namespace AVR_MC
3658
} // end namespace llvm
3659
3660
#endif // GET_INSTRINFO_MC_HELPER_DECLS
3661
3662
#ifdef GET_INSTRINFO_MC_HELPERS
3663
#undef GET_INSTRINFO_MC_HELPERS
3664
3665
namespace llvm {
3666
namespace AVR_MC {
3667
3668
} // end namespace AVR_MC
3669
} // end namespace llvm
3670
3671
#endif // GET_GENISTRINFO_MC_HELPERS
3672
3673
#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
3674
    defined(GET_AVAILABLE_OPCODE_CHECKER)
3675
#define GET_COMPUTE_FEATURES
3676
#endif
3677
#ifdef GET_COMPUTE_FEATURES
3678
#undef GET_COMPUTE_FEATURES
3679
namespace llvm {
3680
namespace AVR_MC {
3681
3682
// Bits for subtarget features that participate in instruction matching.
3683
enum SubtargetFeatureBits : uint8_t {
3684
  Feature_HasSRAMBit = 14,
3685
  Feature_HasJMPCALLBit = 7,
3686
  Feature_HasIJMPCALLBit = 6,
3687
  Feature_HasEIJMPCALLBit = 3,
3688
  Feature_HasADDSUBIWBit = 0,
3689
  Feature_HasSmallStackBit = 15,
3690
  Feature_HasMOVWBit = 10,
3691
  Feature_HasLPMBit = 8,
3692
  Feature_HasLPMXBit = 9,
3693
  Feature_HasELPMBit = 4,
3694
  Feature_HasELPMXBit = 5,
3695
  Feature_HasSPMBit = 12,
3696
  Feature_HasSPMXBit = 13,
3697
  Feature_HasDESBit = 2,
3698
  Feature_SupportsRMWBit = 18,
3699
  Feature_SupportsMultiplicationBit = 17,
3700
  Feature_HasBREAKBit = 1,
3701
  Feature_HasTinyEncodingBit = 16,
3702
  Feature_HasNonTinyEncodingBit = 11,
3703
};
3704
3705
0
inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
3706
0
  FeatureBitset Features;
3707
0
  if (FB[AVR::FeatureSRAM])
3708
0
    Features.set(Feature_HasSRAMBit);
3709
0
  if (FB[AVR::FeatureJMPCALL])
3710
0
    Features.set(Feature_HasJMPCALLBit);
3711
0
  if (FB[AVR::FeatureIJMPCALL])
3712
0
    Features.set(Feature_HasIJMPCALLBit);
3713
0
  if (FB[AVR::FeatureEIJMPCALL])
3714
0
    Features.set(Feature_HasEIJMPCALLBit);
3715
0
  if (FB[AVR::FeatureADDSUBIW])
3716
0
    Features.set(Feature_HasADDSUBIWBit);
3717
0
  if (FB[AVR::FeatureSmallStack])
3718
0
    Features.set(Feature_HasSmallStackBit);
3719
0
  if (FB[AVR::FeatureMOVW])
3720
0
    Features.set(Feature_HasMOVWBit);
3721
0
  if (FB[AVR::FeatureLPM])
3722
0
    Features.set(Feature_HasLPMBit);
3723
0
  if (FB[AVR::FeatureLPMX])
3724
0
    Features.set(Feature_HasLPMXBit);
3725
0
  if (FB[AVR::FeatureELPM])
3726
0
    Features.set(Feature_HasELPMBit);
3727
0
  if (FB[AVR::FeatureELPMX])
3728
0
    Features.set(Feature_HasELPMXBit);
3729
0
  if (FB[AVR::FeatureSPM])
3730
0
    Features.set(Feature_HasSPMBit);
3731
0
  if (FB[AVR::FeatureSPMX])
3732
0
    Features.set(Feature_HasSPMXBit);
3733
0
  if (FB[AVR::FeatureDES])
3734
0
    Features.set(Feature_HasDESBit);
3735
0
  if (FB[AVR::FeatureRMW])
3736
0
    Features.set(Feature_SupportsRMWBit);
3737
0
  if (FB[AVR::FeatureMultiplication])
3738
0
    Features.set(Feature_SupportsMultiplicationBit);
3739
0
  if (FB[AVR::FeatureBREAK])
3740
0
    Features.set(Feature_HasBREAKBit);
3741
0
  if (FB[AVR::FeatureTinyEncoding])
3742
0
    Features.set(Feature_HasTinyEncodingBit);
3743
0
  if (!FB[AVR::FeatureTinyEncoding])
3744
0
    Features.set(Feature_HasNonTinyEncodingBit);
3745
0
  return Features;
3746
0
}
3747
3748
0
inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
3749
0
  enum : uint8_t {
3750
0
    CEFBS_None,
3751
0
    CEFBS_HasADDSUBIW,
3752
0
    CEFBS_HasBREAK,
3753
0
    CEFBS_HasDES,
3754
0
    CEFBS_HasEIJMPCALL,
3755
0
    CEFBS_HasELPM,
3756
0
    CEFBS_HasELPMX,
3757
0
    CEFBS_HasIJMPCALL,
3758
0
    CEFBS_HasJMPCALL,
3759
0
    CEFBS_HasLPM,
3760
0
    CEFBS_HasLPMX,
3761
0
    CEFBS_HasMOVW,
3762
0
    CEFBS_HasNonTinyEncoding,
3763
0
    CEFBS_HasSPM,
3764
0
    CEFBS_HasSPMX,
3765
0
    CEFBS_HasSRAM,
3766
0
    CEFBS_HasTinyEncoding,
3767
0
    CEFBS_SupportsMultiplication,
3768
0
    CEFBS_SupportsRMW,
3769
0
    CEFBS_HasSRAM_HasNonTinyEncoding,
3770
0
    CEFBS_HasSRAM_HasTinyEncoding,
3771
0
  };
3772
3773
0
  static constexpr FeatureBitset FeatureBitsets[] = {
3774
0
    {}, // CEFBS_None
3775
0
    {Feature_HasADDSUBIWBit, },
3776
0
    {Feature_HasBREAKBit, },
3777
0
    {Feature_HasDESBit, },
3778
0
    {Feature_HasEIJMPCALLBit, },
3779
0
    {Feature_HasELPMBit, },
3780
0
    {Feature_HasELPMXBit, },
3781
0
    {Feature_HasIJMPCALLBit, },
3782
0
    {Feature_HasJMPCALLBit, },
3783
0
    {Feature_HasLPMBit, },
3784
0
    {Feature_HasLPMXBit, },
3785
0
    {Feature_HasMOVWBit, },
3786
0
    {Feature_HasNonTinyEncodingBit, },
3787
0
    {Feature_HasSPMBit, },
3788
0
    {Feature_HasSPMXBit, },
3789
0
    {Feature_HasSRAMBit, },
3790
0
    {Feature_HasTinyEncodingBit, },
3791
0
    {Feature_SupportsMultiplicationBit, },
3792
0
    {Feature_SupportsRMWBit, },
3793
0
    {Feature_HasSRAMBit, Feature_HasNonTinyEncodingBit, },
3794
0
    {Feature_HasSRAMBit, Feature_HasTinyEncodingBit, },
3795
0
  };
3796
0
  static constexpr uint8_t RequiredFeaturesRefs[] = {
3797
0
    CEFBS_None, // PHI = 0
3798
0
    CEFBS_None, // INLINEASM = 1
3799
0
    CEFBS_None, // INLINEASM_BR = 2
3800
0
    CEFBS_None, // CFI_INSTRUCTION = 3
3801
0
    CEFBS_None, // EH_LABEL = 4
3802
0
    CEFBS_None, // GC_LABEL = 5
3803
0
    CEFBS_None, // ANNOTATION_LABEL = 6
3804
0
    CEFBS_None, // KILL = 7
3805
0
    CEFBS_None, // EXTRACT_SUBREG = 8
3806
0
    CEFBS_None, // INSERT_SUBREG = 9
3807
0
    CEFBS_None, // IMPLICIT_DEF = 10
3808
0
    CEFBS_None, // SUBREG_TO_REG = 11
3809
0
    CEFBS_None, // COPY_TO_REGCLASS = 12
3810
0
    CEFBS_None, // DBG_VALUE = 13
3811
0
    CEFBS_None, // DBG_VALUE_LIST = 14
3812
0
    CEFBS_None, // DBG_INSTR_REF = 15
3813
0
    CEFBS_None, // DBG_PHI = 16
3814
0
    CEFBS_None, // DBG_LABEL = 17
3815
0
    CEFBS_None, // REG_SEQUENCE = 18
3816
0
    CEFBS_None, // COPY = 19
3817
0
    CEFBS_None, // BUNDLE = 20
3818
0
    CEFBS_None, // LIFETIME_START = 21
3819
0
    CEFBS_None, // LIFETIME_END = 22
3820
0
    CEFBS_None, // PSEUDO_PROBE = 23
3821
0
    CEFBS_None, // ARITH_FENCE = 24
3822
0
    CEFBS_None, // STACKMAP = 25
3823
0
    CEFBS_None, // FENTRY_CALL = 26
3824
0
    CEFBS_None, // PATCHPOINT = 27
3825
0
    CEFBS_None, // LOAD_STACK_GUARD = 28
3826
0
    CEFBS_None, // PREALLOCATED_SETUP = 29
3827
0
    CEFBS_None, // PREALLOCATED_ARG = 30
3828
0
    CEFBS_None, // STATEPOINT = 31
3829
0
    CEFBS_None, // LOCAL_ESCAPE = 32
3830
0
    CEFBS_None, // FAULTING_OP = 33
3831
0
    CEFBS_None, // PATCHABLE_OP = 34
3832
0
    CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
3833
0
    CEFBS_None, // PATCHABLE_RET = 36
3834
0
    CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
3835
0
    CEFBS_None, // PATCHABLE_TAIL_CALL = 38
3836
0
    CEFBS_None, // PATCHABLE_EVENT_CALL = 39
3837
0
    CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
3838
0
    CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
3839
0
    CEFBS_None, // MEMBARRIER = 42
3840
0
    CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 43
3841
0
    CEFBS_None, // G_ASSERT_SEXT = 44
3842
0
    CEFBS_None, // G_ASSERT_ZEXT = 45
3843
0
    CEFBS_None, // G_ASSERT_ALIGN = 46
3844
0
    CEFBS_None, // G_ADD = 47
3845
0
    CEFBS_None, // G_SUB = 48
3846
0
    CEFBS_None, // G_MUL = 49
3847
0
    CEFBS_None, // G_SDIV = 50
3848
0
    CEFBS_None, // G_UDIV = 51
3849
0
    CEFBS_None, // G_SREM = 52
3850
0
    CEFBS_None, // G_UREM = 53
3851
0
    CEFBS_None, // G_SDIVREM = 54
3852
0
    CEFBS_None, // G_UDIVREM = 55
3853
0
    CEFBS_None, // G_AND = 56
3854
0
    CEFBS_None, // G_OR = 57
3855
0
    CEFBS_None, // G_XOR = 58
3856
0
    CEFBS_None, // G_IMPLICIT_DEF = 59
3857
0
    CEFBS_None, // G_PHI = 60
3858
0
    CEFBS_None, // G_FRAME_INDEX = 61
3859
0
    CEFBS_None, // G_GLOBAL_VALUE = 62
3860
0
    CEFBS_None, // G_CONSTANT_POOL = 63
3861
0
    CEFBS_None, // G_EXTRACT = 64
3862
0
    CEFBS_None, // G_UNMERGE_VALUES = 65
3863
0
    CEFBS_None, // G_INSERT = 66
3864
0
    CEFBS_None, // G_MERGE_VALUES = 67
3865
0
    CEFBS_None, // G_BUILD_VECTOR = 68
3866
0
    CEFBS_None, // G_BUILD_VECTOR_TRUNC = 69
3867
0
    CEFBS_None, // G_CONCAT_VECTORS = 70
3868
0
    CEFBS_None, // G_PTRTOINT = 71
3869
0
    CEFBS_None, // G_INTTOPTR = 72
3870
0
    CEFBS_None, // G_BITCAST = 73
3871
0
    CEFBS_None, // G_FREEZE = 74
3872
0
    CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 75
3873
0
    CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 76
3874
0
    CEFBS_None, // G_INTRINSIC_TRUNC = 77
3875
0
    CEFBS_None, // G_INTRINSIC_ROUND = 78
3876
0
    CEFBS_None, // G_INTRINSIC_LRINT = 79
3877
0
    CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 80
3878
0
    CEFBS_None, // G_READCYCLECOUNTER = 81
3879
0
    CEFBS_None, // G_LOAD = 82
3880
0
    CEFBS_None, // G_SEXTLOAD = 83
3881
0
    CEFBS_None, // G_ZEXTLOAD = 84
3882
0
    CEFBS_None, // G_INDEXED_LOAD = 85
3883
0
    CEFBS_None, // G_INDEXED_SEXTLOAD = 86
3884
0
    CEFBS_None, // G_INDEXED_ZEXTLOAD = 87
3885
0
    CEFBS_None, // G_STORE = 88
3886
0
    CEFBS_None, // G_INDEXED_STORE = 89
3887
0
    CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 90
3888
0
    CEFBS_None, // G_ATOMIC_CMPXCHG = 91
3889
0
    CEFBS_None, // G_ATOMICRMW_XCHG = 92
3890
0
    CEFBS_None, // G_ATOMICRMW_ADD = 93
3891
0
    CEFBS_None, // G_ATOMICRMW_SUB = 94
3892
0
    CEFBS_None, // G_ATOMICRMW_AND = 95
3893
0
    CEFBS_None, // G_ATOMICRMW_NAND = 96
3894
0
    CEFBS_None, // G_ATOMICRMW_OR = 97
3895
0
    CEFBS_None, // G_ATOMICRMW_XOR = 98
3896
0
    CEFBS_None, // G_ATOMICRMW_MAX = 99
3897
0
    CEFBS_None, // G_ATOMICRMW_MIN = 100
3898
0
    CEFBS_None, // G_ATOMICRMW_UMAX = 101
3899
0
    CEFBS_None, // G_ATOMICRMW_UMIN = 102
3900
0
    CEFBS_None, // G_ATOMICRMW_FADD = 103
3901
0
    CEFBS_None, // G_ATOMICRMW_FSUB = 104
3902
0
    CEFBS_None, // G_ATOMICRMW_FMAX = 105
3903
0
    CEFBS_None, // G_ATOMICRMW_FMIN = 106
3904
0
    CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 107
3905
0
    CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 108
3906
0
    CEFBS_None, // G_FENCE = 109
3907
0
    CEFBS_None, // G_PREFETCH = 110
3908
0
    CEFBS_None, // G_BRCOND = 111
3909
0
    CEFBS_None, // G_BRINDIRECT = 112
3910
0
    CEFBS_None, // G_INVOKE_REGION_START = 113
3911
0
    CEFBS_None, // G_INTRINSIC = 114
3912
0
    CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 115
3913
0
    CEFBS_None, // G_INTRINSIC_CONVERGENT = 116
3914
0
    CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 117
3915
0
    CEFBS_None, // G_ANYEXT = 118
3916
0
    CEFBS_None, // G_TRUNC = 119
3917
0
    CEFBS_None, // G_CONSTANT = 120
3918
0
    CEFBS_None, // G_FCONSTANT = 121
3919
0
    CEFBS_None, // G_VASTART = 122
3920
0
    CEFBS_None, // G_VAARG = 123
3921
0
    CEFBS_None, // G_SEXT = 124
3922
0
    CEFBS_None, // G_SEXT_INREG = 125
3923
0
    CEFBS_None, // G_ZEXT = 126
3924
0
    CEFBS_None, // G_SHL = 127
3925
0
    CEFBS_None, // G_LSHR = 128
3926
0
    CEFBS_None, // G_ASHR = 129
3927
0
    CEFBS_None, // G_FSHL = 130
3928
0
    CEFBS_None, // G_FSHR = 131
3929
0
    CEFBS_None, // G_ROTR = 132
3930
0
    CEFBS_None, // G_ROTL = 133
3931
0
    CEFBS_None, // G_ICMP = 134
3932
0
    CEFBS_None, // G_FCMP = 135
3933
0
    CEFBS_None, // G_SELECT = 136
3934
0
    CEFBS_None, // G_UADDO = 137
3935
0
    CEFBS_None, // G_UADDE = 138
3936
0
    CEFBS_None, // G_USUBO = 139
3937
0
    CEFBS_None, // G_USUBE = 140
3938
0
    CEFBS_None, // G_SADDO = 141
3939
0
    CEFBS_None, // G_SADDE = 142
3940
0
    CEFBS_None, // G_SSUBO = 143
3941
0
    CEFBS_None, // G_SSUBE = 144
3942
0
    CEFBS_None, // G_UMULO = 145
3943
0
    CEFBS_None, // G_SMULO = 146
3944
0
    CEFBS_None, // G_UMULH = 147
3945
0
    CEFBS_None, // G_SMULH = 148
3946
0
    CEFBS_None, // G_UADDSAT = 149
3947
0
    CEFBS_None, // G_SADDSAT = 150
3948
0
    CEFBS_None, // G_USUBSAT = 151
3949
0
    CEFBS_None, // G_SSUBSAT = 152
3950
0
    CEFBS_None, // G_USHLSAT = 153
3951
0
    CEFBS_None, // G_SSHLSAT = 154
3952
0
    CEFBS_None, // G_SMULFIX = 155
3953
0
    CEFBS_None, // G_UMULFIX = 156
3954
0
    CEFBS_None, // G_SMULFIXSAT = 157
3955
0
    CEFBS_None, // G_UMULFIXSAT = 158
3956
0
    CEFBS_None, // G_SDIVFIX = 159
3957
0
    CEFBS_None, // G_UDIVFIX = 160
3958
0
    CEFBS_None, // G_SDIVFIXSAT = 161
3959
0
    CEFBS_None, // G_UDIVFIXSAT = 162
3960
0
    CEFBS_None, // G_FADD = 163
3961
0
    CEFBS_None, // G_FSUB = 164
3962
0
    CEFBS_None, // G_FMUL = 165
3963
0
    CEFBS_None, // G_FMA = 166
3964
0
    CEFBS_None, // G_FMAD = 167
3965
0
    CEFBS_None, // G_FDIV = 168
3966
0
    CEFBS_None, // G_FREM = 169
3967
0
    CEFBS_None, // G_FPOW = 170
3968
0
    CEFBS_None, // G_FPOWI = 171
3969
0
    CEFBS_None, // G_FEXP = 172
3970
0
    CEFBS_None, // G_FEXP2 = 173
3971
0
    CEFBS_None, // G_FEXP10 = 174
3972
0
    CEFBS_None, // G_FLOG = 175
3973
0
    CEFBS_None, // G_FLOG2 = 176
3974
0
    CEFBS_None, // G_FLOG10 = 177
3975
0
    CEFBS_None, // G_FLDEXP = 178
3976
0
    CEFBS_None, // G_FFREXP = 179
3977
0
    CEFBS_None, // G_FNEG = 180
3978
0
    CEFBS_None, // G_FPEXT = 181
3979
0
    CEFBS_None, // G_FPTRUNC = 182
3980
0
    CEFBS_None, // G_FPTOSI = 183
3981
0
    CEFBS_None, // G_FPTOUI = 184
3982
0
    CEFBS_None, // G_SITOFP = 185
3983
0
    CEFBS_None, // G_UITOFP = 186
3984
0
    CEFBS_None, // G_FABS = 187
3985
0
    CEFBS_None, // G_FCOPYSIGN = 188
3986
0
    CEFBS_None, // G_IS_FPCLASS = 189
3987
0
    CEFBS_None, // G_FCANONICALIZE = 190
3988
0
    CEFBS_None, // G_FMINNUM = 191
3989
0
    CEFBS_None, // G_FMAXNUM = 192
3990
0
    CEFBS_None, // G_FMINNUM_IEEE = 193
3991
0
    CEFBS_None, // G_FMAXNUM_IEEE = 194
3992
0
    CEFBS_None, // G_FMINIMUM = 195
3993
0
    CEFBS_None, // G_FMAXIMUM = 196
3994
0
    CEFBS_None, // G_GET_FPENV = 197
3995
0
    CEFBS_None, // G_SET_FPENV = 198
3996
0
    CEFBS_None, // G_RESET_FPENV = 199
3997
0
    CEFBS_None, // G_GET_FPMODE = 200
3998
0
    CEFBS_None, // G_SET_FPMODE = 201
3999
0
    CEFBS_None, // G_RESET_FPMODE = 202
4000
0
    CEFBS_None, // G_PTR_ADD = 203
4001
0
    CEFBS_None, // G_PTRMASK = 204
4002
0
    CEFBS_None, // G_SMIN = 205
4003
0
    CEFBS_None, // G_SMAX = 206
4004
0
    CEFBS_None, // G_UMIN = 207
4005
0
    CEFBS_None, // G_UMAX = 208
4006
0
    CEFBS_None, // G_ABS = 209
4007
0
    CEFBS_None, // G_LROUND = 210
4008
0
    CEFBS_None, // G_LLROUND = 211
4009
0
    CEFBS_None, // G_BR = 212
4010
0
    CEFBS_None, // G_BRJT = 213
4011
0
    CEFBS_None, // G_INSERT_VECTOR_ELT = 214
4012
0
    CEFBS_None, // G_EXTRACT_VECTOR_ELT = 215
4013
0
    CEFBS_None, // G_SHUFFLE_VECTOR = 216
4014
0
    CEFBS_None, // G_CTTZ = 217
4015
0
    CEFBS_None, // G_CTTZ_ZERO_UNDEF = 218
4016
0
    CEFBS_None, // G_CTLZ = 219
4017
0
    CEFBS_None, // G_CTLZ_ZERO_UNDEF = 220
4018
0
    CEFBS_None, // G_CTPOP = 221
4019
0
    CEFBS_None, // G_BSWAP = 222
4020
0
    CEFBS_None, // G_BITREVERSE = 223
4021
0
    CEFBS_None, // G_FCEIL = 224
4022
0
    CEFBS_None, // G_FCOS = 225
4023
0
    CEFBS_None, // G_FSIN = 226
4024
0
    CEFBS_None, // G_FSQRT = 227
4025
0
    CEFBS_None, // G_FFLOOR = 228
4026
0
    CEFBS_None, // G_FRINT = 229
4027
0
    CEFBS_None, // G_FNEARBYINT = 230
4028
0
    CEFBS_None, // G_ADDRSPACE_CAST = 231
4029
0
    CEFBS_None, // G_BLOCK_ADDR = 232
4030
0
    CEFBS_None, // G_JUMP_TABLE = 233
4031
0
    CEFBS_None, // G_DYN_STACKALLOC = 234
4032
0
    CEFBS_None, // G_STACKSAVE = 235
4033
0
    CEFBS_None, // G_STACKRESTORE = 236
4034
0
    CEFBS_None, // G_STRICT_FADD = 237
4035
0
    CEFBS_None, // G_STRICT_FSUB = 238
4036
0
    CEFBS_None, // G_STRICT_FMUL = 239
4037
0
    CEFBS_None, // G_STRICT_FDIV = 240
4038
0
    CEFBS_None, // G_STRICT_FREM = 241
4039
0
    CEFBS_None, // G_STRICT_FMA = 242
4040
0
    CEFBS_None, // G_STRICT_FSQRT = 243
4041
0
    CEFBS_None, // G_STRICT_FLDEXP = 244
4042
0
    CEFBS_None, // G_READ_REGISTER = 245
4043
0
    CEFBS_None, // G_WRITE_REGISTER = 246
4044
0
    CEFBS_None, // G_MEMCPY = 247
4045
0
    CEFBS_None, // G_MEMCPY_INLINE = 248
4046
0
    CEFBS_None, // G_MEMMOVE = 249
4047
0
    CEFBS_None, // G_MEMSET = 250
4048
0
    CEFBS_None, // G_BZERO = 251
4049
0
    CEFBS_None, // G_VECREDUCE_SEQ_FADD = 252
4050
0
    CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 253
4051
0
    CEFBS_None, // G_VECREDUCE_FADD = 254
4052
0
    CEFBS_None, // G_VECREDUCE_FMUL = 255
4053
0
    CEFBS_None, // G_VECREDUCE_FMAX = 256
4054
0
    CEFBS_None, // G_VECREDUCE_FMIN = 257
4055
0
    CEFBS_None, // G_VECREDUCE_FMAXIMUM = 258
4056
0
    CEFBS_None, // G_VECREDUCE_FMINIMUM = 259
4057
0
    CEFBS_None, // G_VECREDUCE_ADD = 260
4058
0
    CEFBS_None, // G_VECREDUCE_MUL = 261
4059
0
    CEFBS_None, // G_VECREDUCE_AND = 262
4060
0
    CEFBS_None, // G_VECREDUCE_OR = 263
4061
0
    CEFBS_None, // G_VECREDUCE_XOR = 264
4062
0
    CEFBS_None, // G_VECREDUCE_SMAX = 265
4063
0
    CEFBS_None, // G_VECREDUCE_SMIN = 266
4064
0
    CEFBS_None, // G_VECREDUCE_UMAX = 267
4065
0
    CEFBS_None, // G_VECREDUCE_UMIN = 268
4066
0
    CEFBS_None, // G_SBFX = 269
4067
0
    CEFBS_None, // G_UBFX = 270
4068
0
    CEFBS_None, // ADCWRdRr = 271
4069
0
    CEFBS_None, // ADDWRdRr = 272
4070
0
    CEFBS_None, // ADJCALLSTACKDOWN = 273
4071
0
    CEFBS_None, // ADJCALLSTACKUP = 274
4072
0
    CEFBS_None, // ANDIWRdK = 275
4073
0
    CEFBS_None, // ANDWRdRr = 276
4074
0
    CEFBS_None, // ASRBNRd = 277
4075
0
    CEFBS_None, // ASRWLoRd = 278
4076
0
    CEFBS_None, // ASRWNRd = 279
4077
0
    CEFBS_None, // ASRWRd = 280
4078
0
    CEFBS_None, // Asr16 = 281
4079
0
    CEFBS_None, // Asr32 = 282
4080
0
    CEFBS_None, // Asr8 = 283
4081
0
    CEFBS_None, // AtomicFence = 284
4082
0
    CEFBS_None, // AtomicLoad16 = 285
4083
0
    CEFBS_None, // AtomicLoad8 = 286
4084
0
    CEFBS_None, // AtomicLoadAdd16 = 287
4085
0
    CEFBS_None, // AtomicLoadAdd8 = 288
4086
0
    CEFBS_None, // AtomicLoadAnd16 = 289
4087
0
    CEFBS_None, // AtomicLoadAnd8 = 290
4088
0
    CEFBS_None, // AtomicLoadOr16 = 291
4089
0
    CEFBS_None, // AtomicLoadOr8 = 292
4090
0
    CEFBS_None, // AtomicLoadSub16 = 293
4091
0
    CEFBS_None, // AtomicLoadSub8 = 294
4092
0
    CEFBS_None, // AtomicLoadXor16 = 295
4093
0
    CEFBS_None, // AtomicLoadXor8 = 296
4094
0
    CEFBS_None, // AtomicStore16 = 297
4095
0
    CEFBS_None, // AtomicStore8 = 298
4096
0
    CEFBS_None, // COMWRd = 299
4097
0
    CEFBS_None, // CPCWRdRr = 300
4098
0
    CEFBS_None, // CPWRdRr = 301
4099
0
    CEFBS_None, // CopyZero = 302
4100
0
    CEFBS_HasELPM, // ELPMBRdZ = 303
4101
0
    CEFBS_HasELPMX, // ELPMBRdZPi = 304
4102
0
    CEFBS_HasELPM, // ELPMWRdZ = 305
4103
0
    CEFBS_HasELPMX, // ELPMWRdZPi = 306
4104
0
    CEFBS_None, // EORWRdRr = 307
4105
0
    CEFBS_None, // FRMIDX = 308
4106
0
    CEFBS_None, // INWRdA = 309
4107
0
    CEFBS_HasSRAM, // LDDWRdPtrQ = 310
4108
0
    CEFBS_HasSRAM, // LDDWRdYQ = 311
4109
0
    CEFBS_None, // LDIWRdK = 312
4110
0
    CEFBS_HasSRAM_HasNonTinyEncoding, // LDSWRdK = 313
4111
0
    CEFBS_HasSRAM, // LDWRdPtr = 314
4112
0
    CEFBS_HasSRAM, // LDWRdPtrPd = 315
4113
0
    CEFBS_HasSRAM, // LDWRdPtrPi = 316
4114
0
    CEFBS_HasLPM, // LPMBRdZ = 317
4115
0
    CEFBS_HasLPM, // LPMWRdZ = 318
4116
0
    CEFBS_HasLPMX, // LPMWRdZPi = 319
4117
0
    CEFBS_None, // LSLBNRd = 320
4118
0
    CEFBS_None, // LSLWHiRd = 321
4119
0
    CEFBS_None, // LSLWNRd = 322
4120
0
    CEFBS_None, // LSLWRd = 323
4121
0
    CEFBS_None, // LSRBNRd = 324
4122
0
    CEFBS_None, // LSRWLoRd = 325
4123
0
    CEFBS_None, // LSRWNRd = 326
4124
0
    CEFBS_None, // LSRWRd = 327
4125
0
    CEFBS_None, // Lsl16 = 328
4126
0
    CEFBS_None, // Lsl32 = 329
4127
0
    CEFBS_None, // Lsl8 = 330
4128
0
    CEFBS_None, // Lsr16 = 331
4129
0
    CEFBS_None, // Lsr32 = 332
4130
0
    CEFBS_None, // Lsr8 = 333
4131
0
    CEFBS_None, // NEGWRd = 334
4132
0
    CEFBS_None, // ORIWRdK = 335
4133
0
    CEFBS_None, // ORWRdRr = 336
4134
0
    CEFBS_None, // OUTWARr = 337
4135
0
    CEFBS_HasSRAM, // POPWRd = 338
4136
0
    CEFBS_HasSRAM, // PUSHWRr = 339
4137
0
    CEFBS_HasNonTinyEncoding, // ROLBRdR1 = 340
4138
0
    CEFBS_HasTinyEncoding, // ROLBRdR17 = 341
4139
0
    CEFBS_None, // ROLWRd = 342
4140
0
    CEFBS_None, // RORBRd = 343
4141
0
    CEFBS_None, // RORWRd = 344
4142
0
    CEFBS_None, // Rol16 = 345
4143
0
    CEFBS_None, // Rol8 = 346
4144
0
    CEFBS_None, // Ror16 = 347
4145
0
    CEFBS_None, // Ror8 = 348
4146
0
    CEFBS_None, // SBCIWRdK = 349
4147
0
    CEFBS_None, // SBCWRdRr = 350
4148
0
    CEFBS_None, // SEXT = 351
4149
0
    CEFBS_None, // SPREAD = 352
4150
0
    CEFBS_None, // SPWRITE = 353
4151
0
    CEFBS_None, // STDSPQRr = 354
4152
0
    CEFBS_HasSRAM, // STDWPtrQRr = 355
4153
0
    CEFBS_None, // STDWSPQRr = 356
4154
0
    CEFBS_HasSRAM_HasNonTinyEncoding, // STSWKRr = 357
4155
0
    CEFBS_HasSRAM, // STWPtrPdRr = 358
4156
0
    CEFBS_HasSRAM, // STWPtrPiRr = 359
4157
0
    CEFBS_HasSRAM, // STWPtrRr = 360
4158
0
    CEFBS_None, // SUBIWRdK = 361
4159
0
    CEFBS_None, // SUBWRdRr = 362
4160
0
    CEFBS_None, // Select16 = 363
4161
0
    CEFBS_None, // Select8 = 364
4162
0
    CEFBS_None, // ZEXT = 365
4163
0
    CEFBS_None, // ADCRdRr = 366
4164
0
    CEFBS_None, // ADDRdRr = 367
4165
0
    CEFBS_HasADDSUBIW, // ADIWRdK = 368
4166
0
    CEFBS_None, // ANDIRdK = 369
4167
0
    CEFBS_None, // ANDRdRr = 370
4168
0
    CEFBS_None, // ASRRd = 371
4169
0
    CEFBS_None, // BCLRs = 372
4170
0
    CEFBS_None, // BLD = 373
4171
0
    CEFBS_None, // BRBCsk = 374
4172
0
    CEFBS_None, // BRBSsk = 375
4173
0
    CEFBS_HasBREAK, // BREAK = 376
4174
0
    CEFBS_None, // BREQk = 377
4175
0
    CEFBS_None, // BRGEk = 378
4176
0
    CEFBS_None, // BRLOk = 379
4177
0
    CEFBS_None, // BRLTk = 380
4178
0
    CEFBS_None, // BRMIk = 381
4179
0
    CEFBS_None, // BRNEk = 382
4180
0
    CEFBS_None, // BRPLk = 383
4181
0
    CEFBS_None, // BRSHk = 384
4182
0
    CEFBS_None, // BSETs = 385
4183
0
    CEFBS_None, // BST = 386
4184
0
    CEFBS_HasJMPCALL, // CALLk = 387
4185
0
    CEFBS_None, // CBIAb = 388
4186
0
    CEFBS_None, // COMRd = 389
4187
0
    CEFBS_None, // CPCRdRr = 390
4188
0
    CEFBS_None, // CPIRdK = 391
4189
0
    CEFBS_None, // CPRdRr = 392
4190
0
    CEFBS_None, // CPSE = 393
4191
0
    CEFBS_None, // DECRd = 394
4192
0
    CEFBS_HasDES, // DESK = 395
4193
0
    CEFBS_HasEIJMPCALL, // EICALL = 396
4194
0
    CEFBS_HasEIJMPCALL, // EIJMP = 397
4195
0
    CEFBS_HasELPM, // ELPM = 398
4196
0
    CEFBS_HasELPMX, // ELPMRdZ = 399
4197
0
    CEFBS_HasELPMX, // ELPMRdZPi = 400
4198
0
    CEFBS_None, // EORRdRr = 401
4199
0
    CEFBS_SupportsMultiplication, // FMUL = 402
4200
0
    CEFBS_SupportsMultiplication, // FMULS = 403
4201
0
    CEFBS_SupportsMultiplication, // FMULSU = 404
4202
0
    CEFBS_HasIJMPCALL, // ICALL = 405
4203
0
    CEFBS_HasIJMPCALL, // IJMP = 406
4204
0
    CEFBS_None, // INCRd = 407
4205
0
    CEFBS_None, // INRdA = 408
4206
0
    CEFBS_HasJMPCALL, // JMPk = 409
4207
0
    CEFBS_SupportsRMW, // LACZRd = 410
4208
0
    CEFBS_SupportsRMW, // LASZRd = 411
4209
0
    CEFBS_SupportsRMW, // LATZRd = 412
4210
0
    CEFBS_HasSRAM_HasNonTinyEncoding, // LDDRdPtrQ = 413
4211
0
    CEFBS_None, // LDIRdK = 414
4212
0
    CEFBS_HasSRAM, // LDRdPtr = 415
4213
0
    CEFBS_HasSRAM, // LDRdPtrPd = 416
4214
0
    CEFBS_HasSRAM, // LDRdPtrPi = 417
4215
0
    CEFBS_HasSRAM_HasNonTinyEncoding, // LDSRdK = 418
4216
0
    CEFBS_HasSRAM_HasTinyEncoding, // LDSRdKTiny = 419
4217
0
    CEFBS_HasLPM, // LPM = 420
4218
0
    CEFBS_HasLPMX, // LPMRdZ = 421
4219
0
    CEFBS_HasLPMX, // LPMRdZPi = 422
4220
0
    CEFBS_None, // LSRRd = 423
4221
0
    CEFBS_None, // MOVRdRr = 424
4222
0
    CEFBS_HasMOVW, // MOVWRdRr = 425
4223
0
    CEFBS_SupportsMultiplication, // MULRdRr = 426
4224
0
    CEFBS_SupportsMultiplication, // MULSRdRr = 427
4225
0
    CEFBS_SupportsMultiplication, // MULSURdRr = 428
4226
0
    CEFBS_None, // NEGRd = 429
4227
0
    CEFBS_None, // NOP = 430
4228
0
    CEFBS_None, // ORIRdK = 431
4229
0
    CEFBS_None, // ORRdRr = 432
4230
0
    CEFBS_None, // OUTARr = 433
4231
0
    CEFBS_HasSRAM, // POPRd = 434
4232
0
    CEFBS_HasSRAM, // PUSHRr = 435
4233
0
    CEFBS_None, // RCALLk = 436
4234
0
    CEFBS_None, // RET = 437
4235
0
    CEFBS_None, // RETI = 438
4236
0
    CEFBS_None, // RJMPk = 439
4237
0
    CEFBS_None, // RORRd = 440
4238
0
    CEFBS_None, // SBCIRdK = 441
4239
0
    CEFBS_None, // SBCRdRr = 442
4240
0
    CEFBS_None, // SBIAb = 443
4241
0
    CEFBS_None, // SBICAb = 444
4242
0
    CEFBS_None, // SBISAb = 445
4243
0
    CEFBS_HasADDSUBIW, // SBIWRdK = 446
4244
0
    CEFBS_None, // SBRCRrB = 447
4245
0
    CEFBS_None, // SBRSRrB = 448
4246
0
    CEFBS_None, // SLEEP = 449
4247
0
    CEFBS_HasSPM, // SPM = 450
4248
0
    CEFBS_HasSPMX, // SPMZPi = 451
4249
0
    CEFBS_HasSRAM_HasNonTinyEncoding, // STDPtrQRr = 452
4250
0
    CEFBS_HasSRAM, // STPtrPdRr = 453
4251
0
    CEFBS_HasSRAM, // STPtrPiRr = 454
4252
0
    CEFBS_HasSRAM, // STPtrRr = 455
4253
0
    CEFBS_HasSRAM_HasNonTinyEncoding, // STSKRr = 456
4254
0
    CEFBS_HasSRAM_HasTinyEncoding, // STSKRrTiny = 457
4255
0
    CEFBS_None, // SUBIRdK = 458
4256
0
    CEFBS_None, // SUBRdRr = 459
4257
0
    CEFBS_None, // SWAPRd = 460
4258
0
    CEFBS_None, // WDR = 461
4259
0
    CEFBS_SupportsRMW, // XCHZRd = 462
4260
0
  };
4261
4262
0
  assert(Opcode < 463);
4263
0
  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
4264
0
}
4265
4266
} // end namespace AVR_MC
4267
} // end namespace llvm
4268
#endif // GET_COMPUTE_FEATURES
4269
4270
#ifdef GET_AVAILABLE_OPCODE_CHECKER
4271
#undef GET_AVAILABLE_OPCODE_CHECKER
4272
namespace llvm {
4273
namespace AVR_MC {
4274
bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
4275
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
4276
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
4277
  FeatureBitset MissingFeatures =
4278
      (AvailableFeatures & RequiredFeatures) ^
4279
      RequiredFeatures;
4280
  return !MissingFeatures.any();
4281
}
4282
} // end namespace AVR_MC
4283
} // end namespace llvm
4284
#endif // GET_AVAILABLE_OPCODE_CHECKER
4285
4286
#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
4287
#undef ENABLE_INSTR_PREDICATE_VERIFIER
4288
#include <sstream>
4289
4290
namespace llvm {
4291
namespace AVR_MC {
4292
4293
#ifndef NDEBUG
4294
static const char *SubtargetFeatureNames[] = {
4295
  "Feature_HasADDSUBIW",
4296
  "Feature_HasBREAK",
4297
  "Feature_HasDES",
4298
  "Feature_HasEIJMPCALL",
4299
  "Feature_HasELPM",
4300
  "Feature_HasELPMX",
4301
  "Feature_HasIJMPCALL",
4302
  "Feature_HasJMPCALL",
4303
  "Feature_HasLPM",
4304
  "Feature_HasLPMX",
4305
  "Feature_HasMOVW",
4306
  "Feature_HasNonTinyEncoding",
4307
  "Feature_HasSPM",
4308
  "Feature_HasSPMX",
4309
  "Feature_HasSRAM",
4310
  "Feature_HasSmallStack",
4311
  "Feature_HasTinyEncoding",
4312
  "Feature_SupportsMultiplication",
4313
  "Feature_SupportsRMW",
4314
  nullptr
4315
};
4316
4317
#endif // NDEBUG
4318
4319
void verifyInstructionPredicates(
4320
0
    unsigned Opcode, const FeatureBitset &Features) {
4321
0
#ifndef NDEBUG
4322
0
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
4323
0
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
4324
0
  FeatureBitset MissingFeatures =
4325
0
      (AvailableFeatures & RequiredFeatures) ^
4326
0
      RequiredFeatures;
4327
0
  if (MissingFeatures.any()) {
4328
0
    std::ostringstream Msg;
4329
0
    Msg << "Attempting to emit " << &AVRInstrNameData[AVRInstrNameIndices[Opcode]]
4330
0
        << " instruction but the ";
4331
0
    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
4332
0
      if (MissingFeatures.test(i))
4333
0
        Msg << SubtargetFeatureNames[i] << " ";
4334
0
    Msg << "predicate(s) are not met";
4335
0
    report_fatal_error(Msg.str().c_str());
4336
0
  }
4337
0
#endif // NDEBUG
4338
0
}
4339
} // end namespace AVR_MC
4340
} // end namespace llvm
4341
#endif // ENABLE_INSTR_PREDICATE_VERIFIER
4342