/src/build/lib/Target/AVR/AVRGenMCCodeEmitter.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Machine Code Emitter *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | uint64_t AVRMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, |
10 | | SmallVectorImpl<MCFixup> &Fixups, |
11 | 0 | const MCSubtargetInfo &STI) const { |
12 | 0 | static const uint64_t InstBits[] = { |
13 | 0 | UINT64_C(0), |
14 | 0 | UINT64_C(0), |
15 | 0 | UINT64_C(0), |
16 | 0 | UINT64_C(0), |
17 | 0 | UINT64_C(0), |
18 | 0 | UINT64_C(0), |
19 | 0 | UINT64_C(0), |
20 | 0 | UINT64_C(0), |
21 | 0 | UINT64_C(0), |
22 | 0 | UINT64_C(0), |
23 | 0 | UINT64_C(0), |
24 | 0 | UINT64_C(0), |
25 | 0 | UINT64_C(0), |
26 | 0 | UINT64_C(0), |
27 | 0 | UINT64_C(0), |
28 | 0 | UINT64_C(0), |
29 | 0 | UINT64_C(0), |
30 | 0 | UINT64_C(0), |
31 | 0 | UINT64_C(0), |
32 | 0 | UINT64_C(0), |
33 | 0 | UINT64_C(0), |
34 | 0 | UINT64_C(0), |
35 | 0 | UINT64_C(0), |
36 | 0 | UINT64_C(0), |
37 | 0 | UINT64_C(0), |
38 | 0 | UINT64_C(0), |
39 | 0 | UINT64_C(0), |
40 | 0 | UINT64_C(0), |
41 | 0 | UINT64_C(0), |
42 | 0 | UINT64_C(0), |
43 | 0 | UINT64_C(0), |
44 | 0 | UINT64_C(0), |
45 | 0 | UINT64_C(0), |
46 | 0 | UINT64_C(0), |
47 | 0 | UINT64_C(0), |
48 | 0 | UINT64_C(0), |
49 | 0 | UINT64_C(0), |
50 | 0 | UINT64_C(0), |
51 | 0 | UINT64_C(0), |
52 | 0 | UINT64_C(0), |
53 | 0 | UINT64_C(0), |
54 | 0 | UINT64_C(0), |
55 | 0 | UINT64_C(0), |
56 | 0 | UINT64_C(0), |
57 | 0 | UINT64_C(0), |
58 | 0 | UINT64_C(0), |
59 | 0 | UINT64_C(0), |
60 | 0 | UINT64_C(0), |
61 | 0 | UINT64_C(0), |
62 | 0 | UINT64_C(0), |
63 | 0 | UINT64_C(0), |
64 | 0 | UINT64_C(0), |
65 | 0 | UINT64_C(0), |
66 | 0 | UINT64_C(0), |
67 | 0 | UINT64_C(0), |
68 | 0 | UINT64_C(0), |
69 | 0 | UINT64_C(0), |
70 | 0 | UINT64_C(0), |
71 | 0 | UINT64_C(0), |
72 | 0 | UINT64_C(0), |
73 | 0 | UINT64_C(0), |
74 | 0 | UINT64_C(0), |
75 | 0 | UINT64_C(0), |
76 | 0 | UINT64_C(0), |
77 | 0 | UINT64_C(0), |
78 | 0 | UINT64_C(0), |
79 | 0 | UINT64_C(0), |
80 | 0 | UINT64_C(0), |
81 | 0 | UINT64_C(0), |
82 | 0 | UINT64_C(0), |
83 | 0 | UINT64_C(0), |
84 | 0 | UINT64_C(0), |
85 | 0 | UINT64_C(0), |
86 | 0 | UINT64_C(0), |
87 | 0 | UINT64_C(0), |
88 | 0 | UINT64_C(0), |
89 | 0 | UINT64_C(0), |
90 | 0 | UINT64_C(0), |
91 | 0 | UINT64_C(0), |
92 | 0 | UINT64_C(0), |
93 | 0 | UINT64_C(0), |
94 | 0 | UINT64_C(0), |
95 | 0 | UINT64_C(0), |
96 | 0 | UINT64_C(0), |
97 | 0 | UINT64_C(0), |
98 | 0 | UINT64_C(0), |
99 | 0 | UINT64_C(0), |
100 | 0 | UINT64_C(0), |
101 | 0 | UINT64_C(0), |
102 | 0 | UINT64_C(0), |
103 | 0 | UINT64_C(0), |
104 | 0 | UINT64_C(0), |
105 | 0 | UINT64_C(0), |
106 | 0 | UINT64_C(0), |
107 | 0 | UINT64_C(0), |
108 | 0 | UINT64_C(0), |
109 | 0 | UINT64_C(0), |
110 | 0 | UINT64_C(0), |
111 | 0 | UINT64_C(0), |
112 | 0 | UINT64_C(0), |
113 | 0 | UINT64_C(0), |
114 | 0 | UINT64_C(0), |
115 | 0 | UINT64_C(0), |
116 | 0 | UINT64_C(0), |
117 | 0 | UINT64_C(0), |
118 | 0 | UINT64_C(0), |
119 | 0 | UINT64_C(0), |
120 | 0 | UINT64_C(0), |
121 | 0 | UINT64_C(0), |
122 | 0 | UINT64_C(0), |
123 | 0 | UINT64_C(0), |
124 | 0 | UINT64_C(0), |
125 | 0 | UINT64_C(0), |
126 | 0 | UINT64_C(0), |
127 | 0 | UINT64_C(0), |
128 | 0 | UINT64_C(0), |
129 | 0 | UINT64_C(0), |
130 | 0 | UINT64_C(0), |
131 | 0 | UINT64_C(0), |
132 | 0 | UINT64_C(0), |
133 | 0 | UINT64_C(0), |
134 | 0 | UINT64_C(0), |
135 | 0 | UINT64_C(0), |
136 | 0 | UINT64_C(0), |
137 | 0 | UINT64_C(0), |
138 | 0 | UINT64_C(0), |
139 | 0 | UINT64_C(0), |
140 | 0 | UINT64_C(0), |
141 | 0 | UINT64_C(0), |
142 | 0 | UINT64_C(0), |
143 | 0 | UINT64_C(0), |
144 | 0 | UINT64_C(0), |
145 | 0 | UINT64_C(0), |
146 | 0 | UINT64_C(0), |
147 | 0 | UINT64_C(0), |
148 | 0 | UINT64_C(0), |
149 | 0 | UINT64_C(0), |
150 | 0 | UINT64_C(0), |
151 | 0 | UINT64_C(0), |
152 | 0 | UINT64_C(0), |
153 | 0 | UINT64_C(0), |
154 | 0 | UINT64_C(0), |
155 | 0 | UINT64_C(0), |
156 | 0 | UINT64_C(0), |
157 | 0 | UINT64_C(0), |
158 | 0 | UINT64_C(0), |
159 | 0 | UINT64_C(0), |
160 | 0 | UINT64_C(0), |
161 | 0 | UINT64_C(0), |
162 | 0 | UINT64_C(0), |
163 | 0 | UINT64_C(0), |
164 | 0 | UINT64_C(0), |
165 | 0 | UINT64_C(0), |
166 | 0 | UINT64_C(0), |
167 | 0 | UINT64_C(0), |
168 | 0 | UINT64_C(0), |
169 | 0 | UINT64_C(0), |
170 | 0 | UINT64_C(0), |
171 | 0 | UINT64_C(0), |
172 | 0 | UINT64_C(0), |
173 | 0 | UINT64_C(0), |
174 | 0 | UINT64_C(0), |
175 | 0 | UINT64_C(0), |
176 | 0 | UINT64_C(0), |
177 | 0 | UINT64_C(0), |
178 | 0 | UINT64_C(0), |
179 | 0 | UINT64_C(0), |
180 | 0 | UINT64_C(0), |
181 | 0 | UINT64_C(0), |
182 | 0 | UINT64_C(0), |
183 | 0 | UINT64_C(0), |
184 | 0 | UINT64_C(0), |
185 | 0 | UINT64_C(0), |
186 | 0 | UINT64_C(0), |
187 | 0 | UINT64_C(0), |
188 | 0 | UINT64_C(0), |
189 | 0 | UINT64_C(0), |
190 | 0 | UINT64_C(0), |
191 | 0 | UINT64_C(0), |
192 | 0 | UINT64_C(0), |
193 | 0 | UINT64_C(0), |
194 | 0 | UINT64_C(0), |
195 | 0 | UINT64_C(0), |
196 | 0 | UINT64_C(0), |
197 | 0 | UINT64_C(0), |
198 | 0 | UINT64_C(0), |
199 | 0 | UINT64_C(0), |
200 | 0 | UINT64_C(0), |
201 | 0 | UINT64_C(0), |
202 | 0 | UINT64_C(0), |
203 | 0 | UINT64_C(0), |
204 | 0 | UINT64_C(0), |
205 | 0 | UINT64_C(0), |
206 | 0 | UINT64_C(0), |
207 | 0 | UINT64_C(0), |
208 | 0 | UINT64_C(0), |
209 | 0 | UINT64_C(0), |
210 | 0 | UINT64_C(0), |
211 | 0 | UINT64_C(0), |
212 | 0 | UINT64_C(0), |
213 | 0 | UINT64_C(0), |
214 | 0 | UINT64_C(0), |
215 | 0 | UINT64_C(0), |
216 | 0 | UINT64_C(0), |
217 | 0 | UINT64_C(0), |
218 | 0 | UINT64_C(0), |
219 | 0 | UINT64_C(0), |
220 | 0 | UINT64_C(0), |
221 | 0 | UINT64_C(0), |
222 | 0 | UINT64_C(0), |
223 | 0 | UINT64_C(0), |
224 | 0 | UINT64_C(0), |
225 | 0 | UINT64_C(0), |
226 | 0 | UINT64_C(0), |
227 | 0 | UINT64_C(0), |
228 | 0 | UINT64_C(0), |
229 | 0 | UINT64_C(0), |
230 | 0 | UINT64_C(0), |
231 | 0 | UINT64_C(0), |
232 | 0 | UINT64_C(0), |
233 | 0 | UINT64_C(0), |
234 | 0 | UINT64_C(0), |
235 | 0 | UINT64_C(0), |
236 | 0 | UINT64_C(0), |
237 | 0 | UINT64_C(0), |
238 | 0 | UINT64_C(0), |
239 | 0 | UINT64_C(0), |
240 | 0 | UINT64_C(0), |
241 | 0 | UINT64_C(0), |
242 | 0 | UINT64_C(0), |
243 | 0 | UINT64_C(0), |
244 | 0 | UINT64_C(0), |
245 | 0 | UINT64_C(0), |
246 | 0 | UINT64_C(0), |
247 | 0 | UINT64_C(0), |
248 | 0 | UINT64_C(0), |
249 | 0 | UINT64_C(0), |
250 | 0 | UINT64_C(0), |
251 | 0 | UINT64_C(0), |
252 | 0 | UINT64_C(0), |
253 | 0 | UINT64_C(0), |
254 | 0 | UINT64_C(0), |
255 | 0 | UINT64_C(0), |
256 | 0 | UINT64_C(0), |
257 | 0 | UINT64_C(0), |
258 | 0 | UINT64_C(0), |
259 | 0 | UINT64_C(0), |
260 | 0 | UINT64_C(0), |
261 | 0 | UINT64_C(0), |
262 | 0 | UINT64_C(0), |
263 | 0 | UINT64_C(0), |
264 | 0 | UINT64_C(0), |
265 | 0 | UINT64_C(0), |
266 | 0 | UINT64_C(0), |
267 | 0 | UINT64_C(0), |
268 | 0 | UINT64_C(0), |
269 | 0 | UINT64_C(0), |
270 | 0 | UINT64_C(0), |
271 | 0 | UINT64_C(0), |
272 | 0 | UINT64_C(0), |
273 | 0 | UINT64_C(0), |
274 | 0 | UINT64_C(0), |
275 | 0 | UINT64_C(0), |
276 | 0 | UINT64_C(0), |
277 | 0 | UINT64_C(0), |
278 | 0 | UINT64_C(0), |
279 | 0 | UINT64_C(0), |
280 | 0 | UINT64_C(0), |
281 | 0 | UINT64_C(0), |
282 | 0 | UINT64_C(0), |
283 | 0 | UINT64_C(0), |
284 | 0 | UINT64_C(0), |
285 | 0 | UINT64_C(0), |
286 | 0 | UINT64_C(0), |
287 | 0 | UINT64_C(0), |
288 | 0 | UINT64_C(0), |
289 | 0 | UINT64_C(0), |
290 | 0 | UINT64_C(0), |
291 | 0 | UINT64_C(0), |
292 | 0 | UINT64_C(0), |
293 | 0 | UINT64_C(0), |
294 | 0 | UINT64_C(0), |
295 | 0 | UINT64_C(0), |
296 | 0 | UINT64_C(0), |
297 | 0 | UINT64_C(0), |
298 | 0 | UINT64_C(0), |
299 | 0 | UINT64_C(0), |
300 | 0 | UINT64_C(0), |
301 | 0 | UINT64_C(0), |
302 | 0 | UINT64_C(0), |
303 | 0 | UINT64_C(0), |
304 | 0 | UINT64_C(0), |
305 | 0 | UINT64_C(0), |
306 | 0 | UINT64_C(0), |
307 | 0 | UINT64_C(0), |
308 | 0 | UINT64_C(0), |
309 | 0 | UINT64_C(0), |
310 | 0 | UINT64_C(0), |
311 | 0 | UINT64_C(0), |
312 | 0 | UINT64_C(0), |
313 | 0 | UINT64_C(0), |
314 | 0 | UINT64_C(0), |
315 | 0 | UINT64_C(0), |
316 | 0 | UINT64_C(0), |
317 | 0 | UINT64_C(0), |
318 | 0 | UINT64_C(0), |
319 | 0 | UINT64_C(0), |
320 | 0 | UINT64_C(0), |
321 | 0 | UINT64_C(0), |
322 | 0 | UINT64_C(0), |
323 | 0 | UINT64_C(0), |
324 | 0 | UINT64_C(0), |
325 | 0 | UINT64_C(0), |
326 | 0 | UINT64_C(0), |
327 | 0 | UINT64_C(0), |
328 | 0 | UINT64_C(0), |
329 | 0 | UINT64_C(0), |
330 | 0 | UINT64_C(0), |
331 | 0 | UINT64_C(0), |
332 | 0 | UINT64_C(0), |
333 | 0 | UINT64_C(0), |
334 | 0 | UINT64_C(0), |
335 | 0 | UINT64_C(0), |
336 | 0 | UINT64_C(0), |
337 | 0 | UINT64_C(0), |
338 | 0 | UINT64_C(0), |
339 | 0 | UINT64_C(0), |
340 | 0 | UINT64_C(0), |
341 | 0 | UINT64_C(0), |
342 | 0 | UINT64_C(0), |
343 | 0 | UINT64_C(0), |
344 | 0 | UINT64_C(0), |
345 | 0 | UINT64_C(0), |
346 | 0 | UINT64_C(0), |
347 | 0 | UINT64_C(0), |
348 | 0 | UINT64_C(0), |
349 | 0 | UINT64_C(0), |
350 | 0 | UINT64_C(0), |
351 | 0 | UINT64_C(0), |
352 | 0 | UINT64_C(0), |
353 | 0 | UINT64_C(0), |
354 | 0 | UINT64_C(0), |
355 | 0 | UINT64_C(0), |
356 | 0 | UINT64_C(0), |
357 | 0 | UINT64_C(0), |
358 | 0 | UINT64_C(0), |
359 | 0 | UINT64_C(0), |
360 | 0 | UINT64_C(0), |
361 | 0 | UINT64_C(0), |
362 | 0 | UINT64_C(0), |
363 | 0 | UINT64_C(0), |
364 | 0 | UINT64_C(0), |
365 | 0 | UINT64_C(0), |
366 | 0 | UINT64_C(0), |
367 | 0 | UINT64_C(0), |
368 | 0 | UINT64_C(0), |
369 | 0 | UINT64_C(0), |
370 | 0 | UINT64_C(0), |
371 | 0 | UINT64_C(0), |
372 | 0 | UINT64_C(0), |
373 | 0 | UINT64_C(0), |
374 | 0 | UINT64_C(0), |
375 | 0 | UINT64_C(0), |
376 | 0 | UINT64_C(0), |
377 | 0 | UINT64_C(0), |
378 | 0 | UINT64_C(0), |
379 | 0 | UINT64_C(7168), // ADCRdRr |
380 | 0 | UINT64_C(3072), // ADDRdRr |
381 | 0 | UINT64_C(38400), // ADIWRdK |
382 | 0 | UINT64_C(28672), // ANDIRdK |
383 | 0 | UINT64_C(8192), // ANDRdRr |
384 | 0 | UINT64_C(37893), // ASRRd |
385 | 0 | UINT64_C(38024), // BCLRs |
386 | 0 | UINT64_C(63488), // BLD |
387 | 0 | UINT64_C(62464), // BRBCsk |
388 | 0 | UINT64_C(61440), // BRBSsk |
389 | 0 | UINT64_C(38296), // BREAK |
390 | 0 | UINT64_C(61441), // BREQk |
391 | 0 | UINT64_C(62468), // BRGEk |
392 | 0 | UINT64_C(61440), // BRLOk |
393 | 0 | UINT64_C(61444), // BRLTk |
394 | 0 | UINT64_C(61442), // BRMIk |
395 | 0 | UINT64_C(62465), // BRNEk |
396 | 0 | UINT64_C(62466), // BRPLk |
397 | 0 | UINT64_C(62464), // BRSHk |
398 | 0 | UINT64_C(37896), // BSETs |
399 | 0 | UINT64_C(64000), // BST |
400 | 0 | UINT64_C(2483945472), // CALLk |
401 | 0 | UINT64_C(38912), // CBIAb |
402 | 0 | UINT64_C(37888), // COMRd |
403 | 0 | UINT64_C(1024), // CPCRdRr |
404 | 0 | UINT64_C(12288), // CPIRdK |
405 | 0 | UINT64_C(5120), // CPRdRr |
406 | 0 | UINT64_C(4096), // CPSE |
407 | 0 | UINT64_C(37898), // DECRd |
408 | 0 | UINT64_C(37899), // DESK |
409 | 0 | UINT64_C(38169), // EICALL |
410 | 0 | UINT64_C(37913), // EIJMP |
411 | 0 | UINT64_C(38360), // ELPM |
412 | 0 | UINT64_C(36870), // ELPMRdZ |
413 | 0 | UINT64_C(36871), // ELPMRdZPi |
414 | 0 | UINT64_C(9216), // EORRdRr |
415 | 0 | UINT64_C(776), // FMUL |
416 | 0 | UINT64_C(896), // FMULS |
417 | 0 | UINT64_C(904), // FMULSU |
418 | 0 | UINT64_C(38153), // ICALL |
419 | 0 | UINT64_C(37897), // IJMP |
420 | 0 | UINT64_C(37891), // INCRd |
421 | 0 | UINT64_C(45056), // INRdA |
422 | 0 | UINT64_C(2483814400), // JMPk |
423 | 0 | UINT64_C(37382), // LACZRd |
424 | 0 | UINT64_C(37381), // LASZRd |
425 | 0 | UINT64_C(37383), // LATZRd |
426 | 0 | UINT64_C(32768), // LDDRdPtrQ |
427 | 0 | UINT64_C(57344), // LDIRdK |
428 | 0 | UINT64_C(32768), // LDRdPtr |
429 | 0 | UINT64_C(32770), // LDRdPtrPd |
430 | 0 | UINT64_C(32769), // LDRdPtrPi |
431 | 0 | UINT64_C(2415919104), // LDSRdK |
432 | 0 | UINT64_C(40960), // LDSRdKTiny |
433 | 0 | UINT64_C(38344), // LPM |
434 | 0 | UINT64_C(36868), // LPMRdZ |
435 | 0 | UINT64_C(36869), // LPMRdZPi |
436 | 0 | UINT64_C(37894), // LSRRd |
437 | 0 | UINT64_C(11264), // MOVRdRr |
438 | 0 | UINT64_C(256), // MOVWRdRr |
439 | 0 | UINT64_C(39936), // MULRdRr |
440 | 0 | UINT64_C(512), // MULSRdRr |
441 | 0 | UINT64_C(768), // MULSURdRr |
442 | 0 | UINT64_C(37889), // NEGRd |
443 | 0 | UINT64_C(0), // NOP |
444 | 0 | UINT64_C(24576), // ORIRdK |
445 | 0 | UINT64_C(10240), // ORRdRr |
446 | 0 | UINT64_C(47104), // OUTARr |
447 | 0 | UINT64_C(36879), // POPRd |
448 | 0 | UINT64_C(37391), // PUSHRr |
449 | 0 | UINT64_C(53248), // RCALLk |
450 | 0 | UINT64_C(38152), // RET |
451 | 0 | UINT64_C(38168), // RETI |
452 | 0 | UINT64_C(49152), // RJMPk |
453 | 0 | UINT64_C(37895), // RORRd |
454 | 0 | UINT64_C(16384), // SBCIRdK |
455 | 0 | UINT64_C(2048), // SBCRdRr |
456 | 0 | UINT64_C(39424), // SBIAb |
457 | 0 | UINT64_C(39168), // SBICAb |
458 | 0 | UINT64_C(39680), // SBISAb |
459 | 0 | UINT64_C(38656), // SBIWRdK |
460 | 0 | UINT64_C(64512), // SBRCRrB |
461 | 0 | UINT64_C(65024), // SBRSRrB |
462 | 0 | UINT64_C(38280), // SLEEP |
463 | 0 | UINT64_C(38376), // SPM |
464 | 0 | UINT64_C(38392), // SPMZPi |
465 | 0 | UINT64_C(33280), // STDPtrQRr |
466 | 0 | UINT64_C(33282), // STPtrPdRr |
467 | 0 | UINT64_C(33281), // STPtrPiRr |
468 | 0 | UINT64_C(33280), // STPtrRr |
469 | 0 | UINT64_C(2449473536), // STSKRr |
470 | 0 | UINT64_C(43008), // STSKRrTiny |
471 | 0 | UINT64_C(20480), // SUBIRdK |
472 | 0 | UINT64_C(6144), // SUBRdRr |
473 | 0 | UINT64_C(37890), // SWAPRd |
474 | 0 | UINT64_C(38312), // WDR |
475 | 0 | UINT64_C(37380), // XCHZRd |
476 | 0 | UINT64_C(0) |
477 | 0 | }; |
478 | 0 | const unsigned opcode = MI.getOpcode(); |
479 | 0 | uint64_t Value = InstBits[opcode]; |
480 | 0 | uint64_t op = 0; |
481 | 0 | (void)op; // suppress warning |
482 | 0 | switch (opcode) { |
483 | 0 | case AVR::BREAK: |
484 | 0 | case AVR::EICALL: |
485 | 0 | case AVR::EIJMP: |
486 | 0 | case AVR::ELPM: |
487 | 0 | case AVR::ICALL: |
488 | 0 | case AVR::IJMP: |
489 | 0 | case AVR::LPM: |
490 | 0 | case AVR::NOP: |
491 | 0 | case AVR::RET: |
492 | 0 | case AVR::RETI: |
493 | 0 | case AVR::SLEEP: |
494 | 0 | case AVR::SPM: |
495 | 0 | case AVR::SPMZPi: |
496 | 0 | case AVR::WDR: { |
497 | 0 | break; |
498 | 0 | } |
499 | 0 | case AVR::OUTARr: { |
500 | | // op: A |
501 | 0 | op = encodeImm<AVR::fixup_port6, 0>(MI, 0, Fixups, STI); |
502 | 0 | Value |= (op & UINT64_C(48)) << 5; |
503 | 0 | Value |= (op & UINT64_C(15)); |
504 | | // op: rr |
505 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
506 | 0 | op &= UINT64_C(31); |
507 | 0 | op <<= 4; |
508 | 0 | Value |= op; |
509 | 0 | break; |
510 | 0 | } |
511 | 0 | case AVR::CBIAb: |
512 | 0 | case AVR::SBIAb: |
513 | 0 | case AVR::SBICAb: |
514 | 0 | case AVR::SBISAb: { |
515 | | // op: addr |
516 | 0 | op = encodeImm<AVR::fixup_port5, 0>(MI, 0, Fixups, STI); |
517 | 0 | op &= UINT64_C(31); |
518 | 0 | op <<= 3; |
519 | 0 | Value |= op; |
520 | | // op: b |
521 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
522 | 0 | op &= UINT64_C(7); |
523 | 0 | Value |= op; |
524 | 0 | break; |
525 | 0 | } |
526 | 0 | case AVR::CALLk: |
527 | 0 | case AVR::JMPk: { |
528 | | // op: k |
529 | 0 | op = encodeCallTarget(MI, 0, Fixups, STI); |
530 | 0 | Value |= (op & UINT64_C(4063232)) << 3; |
531 | 0 | Value |= (op & UINT64_C(131071)); |
532 | 0 | break; |
533 | 0 | } |
534 | 0 | case AVR::RCALLk: |
535 | 0 | case AVR::RJMPk: { |
536 | | // op: k |
537 | 0 | op = encodeRelCondBrTarget<AVR::fixup_13_pcrel>(MI, 0, Fixups, STI); |
538 | 0 | op &= UINT64_C(4095); |
539 | 0 | Value |= op; |
540 | 0 | break; |
541 | 0 | } |
542 | 0 | case AVR::BREQk: |
543 | 0 | case AVR::BRGEk: |
544 | 0 | case AVR::BRLOk: |
545 | 0 | case AVR::BRLTk: |
546 | 0 | case AVR::BRMIk: |
547 | 0 | case AVR::BRNEk: |
548 | 0 | case AVR::BRPLk: |
549 | 0 | case AVR::BRSHk: { |
550 | | // op: k |
551 | 0 | op = encodeRelCondBrTarget<AVR::fixup_7_pcrel>(MI, 0, Fixups, STI); |
552 | 0 | op &= UINT64_C(127); |
553 | 0 | op <<= 3; |
554 | 0 | Value |= op; |
555 | 0 | break; |
556 | 0 | } |
557 | 0 | case AVR::BRBCsk: |
558 | 0 | case AVR::BRBSsk: { |
559 | | // op: k |
560 | 0 | op = encodeRelCondBrTarget<AVR::fixup_7_pcrel>(MI, 1, Fixups, STI); |
561 | 0 | op &= UINT64_C(127); |
562 | 0 | op <<= 3; |
563 | 0 | Value |= op; |
564 | | // op: s |
565 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
566 | 0 | op &= UINT64_C(7); |
567 | 0 | Value |= op; |
568 | 0 | break; |
569 | 0 | } |
570 | 0 | case AVR::DESK: { |
571 | | // op: k |
572 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
573 | 0 | op &= UINT64_C(15); |
574 | 0 | op <<= 4; |
575 | 0 | Value |= op; |
576 | 0 | break; |
577 | 0 | } |
578 | 0 | case AVR::STDPtrQRr: { |
579 | | // op: memri |
580 | 0 | op = encodeMemri(MI, 0, Fixups, STI); |
581 | 0 | Value |= (op & UINT64_C(32)) << 8; |
582 | 0 | Value |= (op & UINT64_C(24)) << 7; |
583 | 0 | Value |= (op & UINT64_C(64)) >> 3; |
584 | 0 | Value |= (op & UINT64_C(7)); |
585 | | // op: reg |
586 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
587 | 0 | op &= UINT64_C(31); |
588 | 0 | op <<= 4; |
589 | 0 | Value |= op; |
590 | 0 | break; |
591 | 0 | } |
592 | 0 | case AVR::LDDRdPtrQ: { |
593 | | // op: memri |
594 | 0 | op = encodeMemri(MI, 1, Fixups, STI); |
595 | 0 | Value |= (op & UINT64_C(32)) << 8; |
596 | 0 | Value |= (op & UINT64_C(24)) << 7; |
597 | 0 | Value |= (op & UINT64_C(64)) >> 3; |
598 | 0 | Value |= (op & UINT64_C(7)); |
599 | | // op: reg |
600 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
601 | 0 | op &= UINT64_C(31); |
602 | 0 | op <<= 4; |
603 | 0 | Value |= op; |
604 | 0 | break; |
605 | 0 | } |
606 | 0 | case AVR::STPtrRr: { |
607 | | // op: ptrreg |
608 | 0 | op = encodeLDSTPtrReg(MI, 0, Fixups, STI); |
609 | 0 | op &= UINT64_C(3); |
610 | 0 | op <<= 2; |
611 | 0 | Value |= op; |
612 | | // op: reg |
613 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
614 | 0 | op &= UINT64_C(31); |
615 | 0 | op <<= 4; |
616 | 0 | Value |= op; |
617 | 0 | Value = loadStorePostEncoder(MI, Value, STI); |
618 | 0 | break; |
619 | 0 | } |
620 | 0 | case AVR::LDRdPtr: { |
621 | | // op: ptrreg |
622 | 0 | op = encodeLDSTPtrReg(MI, 1, Fixups, STI); |
623 | 0 | op &= UINT64_C(3); |
624 | 0 | op <<= 2; |
625 | 0 | Value |= op; |
626 | | // op: reg |
627 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
628 | 0 | op &= UINT64_C(31); |
629 | 0 | op <<= 4; |
630 | 0 | Value |= op; |
631 | 0 | Value = loadStorePostEncoder(MI, Value, STI); |
632 | 0 | break; |
633 | 0 | } |
634 | 0 | case AVR::STPtrPdRr: |
635 | 0 | case AVR::STPtrPiRr: { |
636 | | // op: ptrreg |
637 | 0 | op = encodeLDSTPtrReg(MI, 1, Fixups, STI); |
638 | 0 | op &= UINT64_C(3); |
639 | 0 | op <<= 2; |
640 | 0 | Value |= op; |
641 | | // op: reg |
642 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
643 | 0 | op &= UINT64_C(31); |
644 | 0 | op <<= 4; |
645 | 0 | Value |= op; |
646 | 0 | Value = loadStorePostEncoder(MI, Value, STI); |
647 | 0 | break; |
648 | 0 | } |
649 | 0 | case AVR::LDRdPtrPd: |
650 | 0 | case AVR::LDRdPtrPi: { |
651 | | // op: ptrreg |
652 | 0 | op = encodeLDSTPtrReg(MI, 2, Fixups, STI); |
653 | 0 | op &= UINT64_C(3); |
654 | 0 | op <<= 2; |
655 | 0 | Value |= op; |
656 | | // op: reg |
657 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
658 | 0 | op &= UINT64_C(31); |
659 | 0 | op <<= 4; |
660 | 0 | Value |= op; |
661 | 0 | Value = loadStorePostEncoder(MI, Value, STI); |
662 | 0 | break; |
663 | 0 | } |
664 | 0 | case AVR::CPIRdK: |
665 | 0 | case AVR::LDIRdK: { |
666 | | // op: rd |
667 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
668 | 0 | op &= UINT64_C(15); |
669 | 0 | op <<= 4; |
670 | 0 | Value |= op; |
671 | | // op: k |
672 | 0 | op = encodeImm<AVR::fixup_ldi, 0>(MI, 1, Fixups, STI); |
673 | 0 | Value |= (op & UINT64_C(240)) << 4; |
674 | 0 | Value |= (op & UINT64_C(15)); |
675 | 0 | break; |
676 | 0 | } |
677 | 0 | case AVR::ANDIRdK: |
678 | 0 | case AVR::ORIRdK: |
679 | 0 | case AVR::SBCIRdK: |
680 | 0 | case AVR::SUBIRdK: { |
681 | | // op: rd |
682 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
683 | 0 | op &= UINT64_C(15); |
684 | 0 | op <<= 4; |
685 | 0 | Value |= op; |
686 | | // op: k |
687 | 0 | op = encodeImm<AVR::fixup_ldi, 0>(MI, 2, Fixups, STI); |
688 | 0 | Value |= (op & UINT64_C(240)) << 4; |
689 | 0 | Value |= (op & UINT64_C(15)); |
690 | 0 | break; |
691 | 0 | } |
692 | 0 | case AVR::LDSRdKTiny: { |
693 | | // op: rd |
694 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
695 | 0 | op &= UINT64_C(15); |
696 | 0 | op <<= 4; |
697 | 0 | Value |= op; |
698 | | // op: k |
699 | 0 | op = encodeImm<AVR::fixup_lds_sts_16, 0>(MI, 1, Fixups, STI); |
700 | 0 | Value |= (op & UINT64_C(112)) << 4; |
701 | 0 | Value |= (op & UINT64_C(15)); |
702 | 0 | break; |
703 | 0 | } |
704 | 0 | case AVR::MULSRdRr: |
705 | 0 | case AVR::MULSURdRr: { |
706 | | // op: rd |
707 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
708 | 0 | op &= UINT64_C(15); |
709 | 0 | op <<= 4; |
710 | 0 | Value |= op; |
711 | | // op: rr |
712 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
713 | 0 | op &= UINT64_C(15); |
714 | 0 | Value |= op; |
715 | 0 | break; |
716 | 0 | } |
717 | 0 | case AVR::MOVWRdRr: { |
718 | | // op: rd |
719 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
720 | 0 | op &= UINT64_C(30); |
721 | 0 | op <<= 3; |
722 | 0 | Value |= op; |
723 | | // op: rr |
724 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
725 | 0 | op &= UINT64_C(30); |
726 | 0 | op >>= 1; |
727 | 0 | Value |= op; |
728 | 0 | break; |
729 | 0 | } |
730 | 0 | case AVR::LDSRdK: { |
731 | | // op: rd |
732 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
733 | 0 | op &= UINT64_C(31); |
734 | 0 | op <<= 20; |
735 | 0 | Value |= op; |
736 | | // op: k |
737 | 0 | op = encodeImm<AVR::fixup_16, 2>(MI, 1, Fixups, STI); |
738 | 0 | op &= UINT64_C(65535); |
739 | 0 | Value |= op; |
740 | 0 | break; |
741 | 0 | } |
742 | 0 | case AVR::ASRRd: |
743 | 0 | case AVR::COMRd: |
744 | 0 | case AVR::DECRd: |
745 | 0 | case AVR::ELPMRdZ: |
746 | 0 | case AVR::ELPMRdZPi: |
747 | 0 | case AVR::INCRd: |
748 | 0 | case AVR::LACZRd: |
749 | 0 | case AVR::LASZRd: |
750 | 0 | case AVR::LATZRd: |
751 | 0 | case AVR::LPMRdZ: |
752 | 0 | case AVR::LPMRdZPi: |
753 | 0 | case AVR::LSRRd: |
754 | 0 | case AVR::NEGRd: |
755 | 0 | case AVR::POPRd: |
756 | 0 | case AVR::PUSHRr: |
757 | 0 | case AVR::RORRd: |
758 | 0 | case AVR::SWAPRd: |
759 | 0 | case AVR::XCHZRd: { |
760 | | // op: rd |
761 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
762 | 0 | op &= UINT64_C(31); |
763 | 0 | op <<= 4; |
764 | 0 | Value |= op; |
765 | 0 | break; |
766 | 0 | } |
767 | 0 | case AVR::INRdA: { |
768 | | // op: rd |
769 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
770 | 0 | op &= UINT64_C(31); |
771 | 0 | op <<= 4; |
772 | 0 | Value |= op; |
773 | | // op: A |
774 | 0 | op = encodeImm<AVR::fixup_port6, 0>(MI, 1, Fixups, STI); |
775 | 0 | Value |= (op & UINT64_C(48)) << 5; |
776 | 0 | Value |= (op & UINT64_C(15)); |
777 | 0 | break; |
778 | 0 | } |
779 | 0 | case AVR::BST: |
780 | 0 | case AVR::SBRCRrB: |
781 | 0 | case AVR::SBRSRrB: { |
782 | | // op: rd |
783 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
784 | 0 | op &= UINT64_C(31); |
785 | 0 | op <<= 4; |
786 | 0 | Value |= op; |
787 | | // op: b |
788 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
789 | 0 | op &= UINT64_C(7); |
790 | 0 | Value |= op; |
791 | 0 | break; |
792 | 0 | } |
793 | 0 | case AVR::BLD: { |
794 | | // op: rd |
795 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
796 | 0 | op &= UINT64_C(31); |
797 | 0 | op <<= 4; |
798 | 0 | Value |= op; |
799 | | // op: b |
800 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
801 | 0 | op &= UINT64_C(7); |
802 | 0 | Value |= op; |
803 | 0 | break; |
804 | 0 | } |
805 | 0 | case AVR::CPCRdRr: |
806 | 0 | case AVR::CPRdRr: |
807 | 0 | case AVR::CPSE: |
808 | 0 | case AVR::MOVRdRr: |
809 | 0 | case AVR::MULRdRr: { |
810 | | // op: rd |
811 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
812 | 0 | op &= UINT64_C(31); |
813 | 0 | op <<= 4; |
814 | 0 | Value |= op; |
815 | | // op: rr |
816 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
817 | 0 | Value |= (op & UINT64_C(16)) << 5; |
818 | 0 | Value |= (op & UINT64_C(15)); |
819 | 0 | break; |
820 | 0 | } |
821 | 0 | case AVR::ADCRdRr: |
822 | 0 | case AVR::ADDRdRr: |
823 | 0 | case AVR::ANDRdRr: |
824 | 0 | case AVR::EORRdRr: |
825 | 0 | case AVR::ORRdRr: |
826 | 0 | case AVR::SBCRdRr: |
827 | 0 | case AVR::SUBRdRr: { |
828 | | // op: rd |
829 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
830 | 0 | op &= UINT64_C(31); |
831 | 0 | op <<= 4; |
832 | 0 | Value |= op; |
833 | | // op: rr |
834 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
835 | 0 | Value |= (op & UINT64_C(16)) << 5; |
836 | 0 | Value |= (op & UINT64_C(15)); |
837 | 0 | break; |
838 | 0 | } |
839 | 0 | case AVR::ADIWRdK: |
840 | 0 | case AVR::SBIWRdK: { |
841 | | // op: rd |
842 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
843 | 0 | op &= UINT64_C(6); |
844 | 0 | op <<= 3; |
845 | 0 | Value |= op; |
846 | | // op: k |
847 | 0 | op = encodeImm<AVR::fixup_6_adiw, 0>(MI, 2, Fixups, STI); |
848 | 0 | Value |= (op & UINT64_C(48)) << 2; |
849 | 0 | Value |= (op & UINT64_C(15)); |
850 | 0 | break; |
851 | 0 | } |
852 | 0 | case AVR::FMUL: |
853 | 0 | case AVR::FMULS: |
854 | 0 | case AVR::FMULSU: { |
855 | | // op: rd |
856 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
857 | 0 | op &= UINT64_C(7); |
858 | 0 | op <<= 4; |
859 | 0 | Value |= op; |
860 | | // op: rr |
861 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
862 | 0 | op &= UINT64_C(7); |
863 | 0 | Value |= op; |
864 | 0 | break; |
865 | 0 | } |
866 | 0 | case AVR::STSKRrTiny: { |
867 | | // op: rd |
868 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
869 | 0 | op &= UINT64_C(15); |
870 | 0 | op <<= 4; |
871 | 0 | Value |= op; |
872 | | // op: k |
873 | 0 | op = encodeImm<AVR::fixup_lds_sts_16, 0>(MI, 0, Fixups, STI); |
874 | 0 | Value |= (op & UINT64_C(112)) << 4; |
875 | 0 | Value |= (op & UINT64_C(15)); |
876 | 0 | break; |
877 | 0 | } |
878 | 0 | case AVR::STSKRr: { |
879 | | // op: rd |
880 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
881 | 0 | op &= UINT64_C(31); |
882 | 0 | op <<= 20; |
883 | 0 | Value |= op; |
884 | | // op: k |
885 | 0 | op = encodeImm<AVR::fixup_16, 2>(MI, 0, Fixups, STI); |
886 | 0 | op &= UINT64_C(65535); |
887 | 0 | Value |= op; |
888 | 0 | break; |
889 | 0 | } |
890 | 0 | case AVR::BCLRs: |
891 | 0 | case AVR::BSETs: { |
892 | | // op: s |
893 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
894 | 0 | op &= UINT64_C(7); |
895 | 0 | op <<= 4; |
896 | 0 | Value |= op; |
897 | 0 | break; |
898 | 0 | } |
899 | 0 | default: |
900 | 0 | std::string msg; |
901 | 0 | raw_string_ostream Msg(msg); |
902 | 0 | Msg << "Not supported instr: " << MI; |
903 | 0 | report_fatal_error(Msg.str().c_str()); |
904 | 0 | } |
905 | 0 | return Value; |
906 | 0 | } |
907 | | |
908 | | #ifdef GET_OPERAND_BIT_OFFSET |
909 | | #undef GET_OPERAND_BIT_OFFSET |
910 | | |
911 | | uint32_t AVRMCCodeEmitter::getOperandBitOffset(const MCInst &MI, |
912 | | unsigned OpNum, |
913 | | const MCSubtargetInfo &STI) const { |
914 | | switch (MI.getOpcode()) { |
915 | | case AVR::BREAK: |
916 | | case AVR::EICALL: |
917 | | case AVR::EIJMP: |
918 | | case AVR::ELPM: |
919 | | case AVR::ICALL: |
920 | | case AVR::IJMP: |
921 | | case AVR::LPM: |
922 | | case AVR::NOP: |
923 | | case AVR::RET: |
924 | | case AVR::RETI: |
925 | | case AVR::SLEEP: |
926 | | case AVR::SPM: |
927 | | case AVR::SPMZPi: |
928 | | case AVR::WDR: { |
929 | | break; |
930 | | } |
931 | | case AVR::OUTARr: { |
932 | | switch (OpNum) { |
933 | | case 0: |
934 | | // op: A |
935 | | return 0; |
936 | | case 1: |
937 | | // op: rr |
938 | | return 4; |
939 | | } |
940 | | break; |
941 | | } |
942 | | case AVR::CBIAb: |
943 | | case AVR::SBIAb: |
944 | | case AVR::SBICAb: |
945 | | case AVR::SBISAb: { |
946 | | switch (OpNum) { |
947 | | case 0: |
948 | | // op: addr |
949 | | return 3; |
950 | | case 1: |
951 | | // op: b |
952 | | return 0; |
953 | | } |
954 | | break; |
955 | | } |
956 | | case AVR::CALLk: |
957 | | case AVR::JMPk: |
958 | | case AVR::RCALLk: |
959 | | case AVR::RJMPk: { |
960 | | switch (OpNum) { |
961 | | case 0: |
962 | | // op: k |
963 | | return 0; |
964 | | } |
965 | | break; |
966 | | } |
967 | | case AVR::BREQk: |
968 | | case AVR::BRGEk: |
969 | | case AVR::BRLOk: |
970 | | case AVR::BRLTk: |
971 | | case AVR::BRMIk: |
972 | | case AVR::BRNEk: |
973 | | case AVR::BRPLk: |
974 | | case AVR::BRSHk: { |
975 | | switch (OpNum) { |
976 | | case 0: |
977 | | // op: k |
978 | | return 3; |
979 | | } |
980 | | break; |
981 | | } |
982 | | case AVR::DESK: { |
983 | | switch (OpNum) { |
984 | | case 0: |
985 | | // op: k |
986 | | return 4; |
987 | | } |
988 | | break; |
989 | | } |
990 | | case AVR::STDPtrQRr: { |
991 | | switch (OpNum) { |
992 | | case 0: |
993 | | // op: memri |
994 | | return 0; |
995 | | case 2: |
996 | | // op: reg |
997 | | return 4; |
998 | | } |
999 | | break; |
1000 | | } |
1001 | | case AVR::STPtrRr: { |
1002 | | switch (OpNum) { |
1003 | | case 0: |
1004 | | // op: ptrreg |
1005 | | return 2; |
1006 | | case 1: |
1007 | | // op: reg |
1008 | | return 4; |
1009 | | } |
1010 | | break; |
1011 | | } |
1012 | | case AVR::LDSRdK: { |
1013 | | switch (OpNum) { |
1014 | | case 0: |
1015 | | // op: rd |
1016 | | return 20; |
1017 | | case 1: |
1018 | | // op: k |
1019 | | return 0; |
1020 | | } |
1021 | | break; |
1022 | | } |
1023 | | case AVR::INRdA: { |
1024 | | switch (OpNum) { |
1025 | | case 0: |
1026 | | // op: rd |
1027 | | return 4; |
1028 | | case 1: |
1029 | | // op: A |
1030 | | return 0; |
1031 | | } |
1032 | | break; |
1033 | | } |
1034 | | case AVR::BST: |
1035 | | case AVR::SBRCRrB: |
1036 | | case AVR::SBRSRrB: { |
1037 | | switch (OpNum) { |
1038 | | case 0: |
1039 | | // op: rd |
1040 | | return 4; |
1041 | | case 1: |
1042 | | // op: b |
1043 | | return 0; |
1044 | | } |
1045 | | break; |
1046 | | } |
1047 | | case AVR::CPIRdK: |
1048 | | case AVR::LDIRdK: |
1049 | | case AVR::LDSRdKTiny: { |
1050 | | switch (OpNum) { |
1051 | | case 0: |
1052 | | // op: rd |
1053 | | return 4; |
1054 | | case 1: |
1055 | | // op: k |
1056 | | return 0; |
1057 | | } |
1058 | | break; |
1059 | | } |
1060 | | case AVR::CPCRdRr: |
1061 | | case AVR::CPRdRr: |
1062 | | case AVR::CPSE: |
1063 | | case AVR::FMUL: |
1064 | | case AVR::FMULS: |
1065 | | case AVR::FMULSU: |
1066 | | case AVR::MOVRdRr: |
1067 | | case AVR::MOVWRdRr: |
1068 | | case AVR::MULRdRr: |
1069 | | case AVR::MULSRdRr: |
1070 | | case AVR::MULSURdRr: { |
1071 | | switch (OpNum) { |
1072 | | case 0: |
1073 | | // op: rd |
1074 | | return 4; |
1075 | | case 1: |
1076 | | // op: rr |
1077 | | return 0; |
1078 | | } |
1079 | | break; |
1080 | | } |
1081 | | case AVR::BLD: { |
1082 | | switch (OpNum) { |
1083 | | case 0: |
1084 | | // op: rd |
1085 | | return 4; |
1086 | | case 2: |
1087 | | // op: b |
1088 | | return 0; |
1089 | | } |
1090 | | break; |
1091 | | } |
1092 | | case AVR::ADIWRdK: |
1093 | | case AVR::ANDIRdK: |
1094 | | case AVR::ORIRdK: |
1095 | | case AVR::SBCIRdK: |
1096 | | case AVR::SBIWRdK: |
1097 | | case AVR::SUBIRdK: { |
1098 | | switch (OpNum) { |
1099 | | case 0: |
1100 | | // op: rd |
1101 | | return 4; |
1102 | | case 2: |
1103 | | // op: k |
1104 | | return 0; |
1105 | | } |
1106 | | break; |
1107 | | } |
1108 | | case AVR::ADCRdRr: |
1109 | | case AVR::ADDRdRr: |
1110 | | case AVR::ANDRdRr: |
1111 | | case AVR::EORRdRr: |
1112 | | case AVR::ORRdRr: |
1113 | | case AVR::SBCRdRr: |
1114 | | case AVR::SUBRdRr: { |
1115 | | switch (OpNum) { |
1116 | | case 0: |
1117 | | // op: rd |
1118 | | return 4; |
1119 | | case 2: |
1120 | | // op: rr |
1121 | | return 0; |
1122 | | } |
1123 | | break; |
1124 | | } |
1125 | | case AVR::ASRRd: |
1126 | | case AVR::COMRd: |
1127 | | case AVR::DECRd: |
1128 | | case AVR::ELPMRdZ: |
1129 | | case AVR::ELPMRdZPi: |
1130 | | case AVR::INCRd: |
1131 | | case AVR::LACZRd: |
1132 | | case AVR::LASZRd: |
1133 | | case AVR::LATZRd: |
1134 | | case AVR::LPMRdZ: |
1135 | | case AVR::LPMRdZPi: |
1136 | | case AVR::LSRRd: |
1137 | | case AVR::NEGRd: |
1138 | | case AVR::POPRd: |
1139 | | case AVR::PUSHRr: |
1140 | | case AVR::RORRd: |
1141 | | case AVR::SWAPRd: |
1142 | | case AVR::XCHZRd: { |
1143 | | switch (OpNum) { |
1144 | | case 0: |
1145 | | // op: rd |
1146 | | return 4; |
1147 | | } |
1148 | | break; |
1149 | | } |
1150 | | case AVR::BCLRs: |
1151 | | case AVR::BSETs: { |
1152 | | switch (OpNum) { |
1153 | | case 0: |
1154 | | // op: s |
1155 | | return 4; |
1156 | | } |
1157 | | break; |
1158 | | } |
1159 | | case AVR::BRBCsk: |
1160 | | case AVR::BRBSsk: { |
1161 | | switch (OpNum) { |
1162 | | case 1: |
1163 | | // op: k |
1164 | | return 3; |
1165 | | case 0: |
1166 | | // op: s |
1167 | | return 0; |
1168 | | } |
1169 | | break; |
1170 | | } |
1171 | | case AVR::LDDRdPtrQ: { |
1172 | | switch (OpNum) { |
1173 | | case 1: |
1174 | | // op: memri |
1175 | | return 0; |
1176 | | case 0: |
1177 | | // op: reg |
1178 | | return 4; |
1179 | | } |
1180 | | break; |
1181 | | } |
1182 | | case AVR::LDRdPtr: { |
1183 | | switch (OpNum) { |
1184 | | case 1: |
1185 | | // op: ptrreg |
1186 | | return 2; |
1187 | | case 0: |
1188 | | // op: reg |
1189 | | return 4; |
1190 | | } |
1191 | | break; |
1192 | | } |
1193 | | case AVR::STPtrPdRr: |
1194 | | case AVR::STPtrPiRr: { |
1195 | | switch (OpNum) { |
1196 | | case 1: |
1197 | | // op: ptrreg |
1198 | | return 2; |
1199 | | case 2: |
1200 | | // op: reg |
1201 | | return 4; |
1202 | | } |
1203 | | break; |
1204 | | } |
1205 | | case AVR::STSKRr: { |
1206 | | switch (OpNum) { |
1207 | | case 1: |
1208 | | // op: rd |
1209 | | return 20; |
1210 | | case 0: |
1211 | | // op: k |
1212 | | return 0; |
1213 | | } |
1214 | | break; |
1215 | | } |
1216 | | case AVR::STSKRrTiny: { |
1217 | | switch (OpNum) { |
1218 | | case 1: |
1219 | | // op: rd |
1220 | | return 4; |
1221 | | case 0: |
1222 | | // op: k |
1223 | | return 0; |
1224 | | } |
1225 | | break; |
1226 | | } |
1227 | | case AVR::LDRdPtrPd: |
1228 | | case AVR::LDRdPtrPi: { |
1229 | | switch (OpNum) { |
1230 | | case 2: |
1231 | | // op: ptrreg |
1232 | | return 2; |
1233 | | case 0: |
1234 | | // op: reg |
1235 | | return 4; |
1236 | | } |
1237 | | break; |
1238 | | } |
1239 | | } |
1240 | | std::string msg; |
1241 | | raw_string_ostream Msg(msg); |
1242 | | Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]"; |
1243 | | report_fatal_error(Msg.str().c_str()); |
1244 | | } |
1245 | | |
1246 | | #endif // GET_OPERAND_BIT_OFFSET |
1247 | | |