Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/BPF/BPFGenInstrInfo.inc
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Count
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1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Instruction Enum Values and Descriptors                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_INSTRINFO_ENUM
10
#undef GET_INSTRINFO_ENUM
11
namespace llvm {
12
13
namespace BPF {
14
  enum {
15
    PHI = 0,
16
    INLINEASM = 1,
17
    INLINEASM_BR  = 2,
18
    CFI_INSTRUCTION = 3,
19
    EH_LABEL  = 4,
20
    GC_LABEL  = 5,
21
    ANNOTATION_LABEL  = 6,
22
    KILL  = 7,
23
    EXTRACT_SUBREG  = 8,
24
    INSERT_SUBREG = 9,
25
    IMPLICIT_DEF  = 10,
26
    SUBREG_TO_REG = 11,
27
    COPY_TO_REGCLASS  = 12,
28
    DBG_VALUE = 13,
29
    DBG_VALUE_LIST  = 14,
30
    DBG_INSTR_REF = 15,
31
    DBG_PHI = 16,
32
    DBG_LABEL = 17,
33
    REG_SEQUENCE  = 18,
34
    COPY  = 19,
35
    BUNDLE  = 20,
36
    LIFETIME_START  = 21,
37
    LIFETIME_END  = 22,
38
    PSEUDO_PROBE  = 23,
39
    ARITH_FENCE = 24,
40
    STACKMAP  = 25,
41
    FENTRY_CALL = 26,
42
    PATCHPOINT  = 27,
43
    LOAD_STACK_GUARD  = 28,
44
    PREALLOCATED_SETUP  = 29,
45
    PREALLOCATED_ARG  = 30,
46
    STATEPOINT  = 31,
47
    LOCAL_ESCAPE  = 32,
48
    FAULTING_OP = 33,
49
    PATCHABLE_OP  = 34,
50
    PATCHABLE_FUNCTION_ENTER  = 35,
51
    PATCHABLE_RET = 36,
52
    PATCHABLE_FUNCTION_EXIT = 37,
53
    PATCHABLE_TAIL_CALL = 38,
54
    PATCHABLE_EVENT_CALL  = 39,
55
    PATCHABLE_TYPED_EVENT_CALL  = 40,
56
    ICALL_BRANCH_FUNNEL = 41,
57
    MEMBARRIER  = 42,
58
    JUMP_TABLE_DEBUG_INFO = 43,
59
    G_ASSERT_SEXT = 44,
60
    G_ASSERT_ZEXT = 45,
61
    G_ASSERT_ALIGN  = 46,
62
    G_ADD = 47,
63
    G_SUB = 48,
64
    G_MUL = 49,
65
    G_SDIV  = 50,
66
    G_UDIV  = 51,
67
    G_SREM  = 52,
68
    G_UREM  = 53,
69
    G_SDIVREM = 54,
70
    G_UDIVREM = 55,
71
    G_AND = 56,
72
    G_OR  = 57,
73
    G_XOR = 58,
74
    G_IMPLICIT_DEF  = 59,
75
    G_PHI = 60,
76
    G_FRAME_INDEX = 61,
77
    G_GLOBAL_VALUE  = 62,
78
    G_CONSTANT_POOL = 63,
79
    G_EXTRACT = 64,
80
    G_UNMERGE_VALUES  = 65,
81
    G_INSERT  = 66,
82
    G_MERGE_VALUES  = 67,
83
    G_BUILD_VECTOR  = 68,
84
    G_BUILD_VECTOR_TRUNC  = 69,
85
    G_CONCAT_VECTORS  = 70,
86
    G_PTRTOINT  = 71,
87
    G_INTTOPTR  = 72,
88
    G_BITCAST = 73,
89
    G_FREEZE  = 74,
90
    G_CONSTANT_FOLD_BARRIER = 75,
91
    G_INTRINSIC_FPTRUNC_ROUND = 76,
92
    G_INTRINSIC_TRUNC = 77,
93
    G_INTRINSIC_ROUND = 78,
94
    G_INTRINSIC_LRINT = 79,
95
    G_INTRINSIC_ROUNDEVEN = 80,
96
    G_READCYCLECOUNTER  = 81,
97
    G_LOAD  = 82,
98
    G_SEXTLOAD  = 83,
99
    G_ZEXTLOAD  = 84,
100
    G_INDEXED_LOAD  = 85,
101
    G_INDEXED_SEXTLOAD  = 86,
102
    G_INDEXED_ZEXTLOAD  = 87,
103
    G_STORE = 88,
104
    G_INDEXED_STORE = 89,
105
    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 90,
106
    G_ATOMIC_CMPXCHG  = 91,
107
    G_ATOMICRMW_XCHG  = 92,
108
    G_ATOMICRMW_ADD = 93,
109
    G_ATOMICRMW_SUB = 94,
110
    G_ATOMICRMW_AND = 95,
111
    G_ATOMICRMW_NAND  = 96,
112
    G_ATOMICRMW_OR  = 97,
113
    G_ATOMICRMW_XOR = 98,
114
    G_ATOMICRMW_MAX = 99,
115
    G_ATOMICRMW_MIN = 100,
116
    G_ATOMICRMW_UMAX  = 101,
117
    G_ATOMICRMW_UMIN  = 102,
118
    G_ATOMICRMW_FADD  = 103,
119
    G_ATOMICRMW_FSUB  = 104,
120
    G_ATOMICRMW_FMAX  = 105,
121
    G_ATOMICRMW_FMIN  = 106,
122
    G_ATOMICRMW_UINC_WRAP = 107,
123
    G_ATOMICRMW_UDEC_WRAP = 108,
124
    G_FENCE = 109,
125
    G_PREFETCH  = 110,
126
    G_BRCOND  = 111,
127
    G_BRINDIRECT  = 112,
128
    G_INVOKE_REGION_START = 113,
129
    G_INTRINSIC = 114,
130
    G_INTRINSIC_W_SIDE_EFFECTS  = 115,
131
    G_INTRINSIC_CONVERGENT  = 116,
132
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 117,
133
    G_ANYEXT  = 118,
134
    G_TRUNC = 119,
135
    G_CONSTANT  = 120,
136
    G_FCONSTANT = 121,
137
    G_VASTART = 122,
138
    G_VAARG = 123,
139
    G_SEXT  = 124,
140
    G_SEXT_INREG  = 125,
141
    G_ZEXT  = 126,
142
    G_SHL = 127,
143
    G_LSHR  = 128,
144
    G_ASHR  = 129,
145
    G_FSHL  = 130,
146
    G_FSHR  = 131,
147
    G_ROTR  = 132,
148
    G_ROTL  = 133,
149
    G_ICMP  = 134,
150
    G_FCMP  = 135,
151
    G_SELECT  = 136,
152
    G_UADDO = 137,
153
    G_UADDE = 138,
154
    G_USUBO = 139,
155
    G_USUBE = 140,
156
    G_SADDO = 141,
157
    G_SADDE = 142,
158
    G_SSUBO = 143,
159
    G_SSUBE = 144,
160
    G_UMULO = 145,
161
    G_SMULO = 146,
162
    G_UMULH = 147,
163
    G_SMULH = 148,
164
    G_UADDSAT = 149,
165
    G_SADDSAT = 150,
166
    G_USUBSAT = 151,
167
    G_SSUBSAT = 152,
168
    G_USHLSAT = 153,
169
    G_SSHLSAT = 154,
170
    G_SMULFIX = 155,
171
    G_UMULFIX = 156,
172
    G_SMULFIXSAT  = 157,
173
    G_UMULFIXSAT  = 158,
174
    G_SDIVFIX = 159,
175
    G_UDIVFIX = 160,
176
    G_SDIVFIXSAT  = 161,
177
    G_UDIVFIXSAT  = 162,
178
    G_FADD  = 163,
179
    G_FSUB  = 164,
180
    G_FMUL  = 165,
181
    G_FMA = 166,
182
    G_FMAD  = 167,
183
    G_FDIV  = 168,
184
    G_FREM  = 169,
185
    G_FPOW  = 170,
186
    G_FPOWI = 171,
187
    G_FEXP  = 172,
188
    G_FEXP2 = 173,
189
    G_FEXP10  = 174,
190
    G_FLOG  = 175,
191
    G_FLOG2 = 176,
192
    G_FLOG10  = 177,
193
    G_FLDEXP  = 178,
194
    G_FFREXP  = 179,
195
    G_FNEG  = 180,
196
    G_FPEXT = 181,
197
    G_FPTRUNC = 182,
198
    G_FPTOSI  = 183,
199
    G_FPTOUI  = 184,
200
    G_SITOFP  = 185,
201
    G_UITOFP  = 186,
202
    G_FABS  = 187,
203
    G_FCOPYSIGN = 188,
204
    G_IS_FPCLASS  = 189,
205
    G_FCANONICALIZE = 190,
206
    G_FMINNUM = 191,
207
    G_FMAXNUM = 192,
208
    G_FMINNUM_IEEE  = 193,
209
    G_FMAXNUM_IEEE  = 194,
210
    G_FMINIMUM  = 195,
211
    G_FMAXIMUM  = 196,
212
    G_GET_FPENV = 197,
213
    G_SET_FPENV = 198,
214
    G_RESET_FPENV = 199,
215
    G_GET_FPMODE  = 200,
216
    G_SET_FPMODE  = 201,
217
    G_RESET_FPMODE  = 202,
218
    G_PTR_ADD = 203,
219
    G_PTRMASK = 204,
220
    G_SMIN  = 205,
221
    G_SMAX  = 206,
222
    G_UMIN  = 207,
223
    G_UMAX  = 208,
224
    G_ABS = 209,
225
    G_LROUND  = 210,
226
    G_LLROUND = 211,
227
    G_BR  = 212,
228
    G_BRJT  = 213,
229
    G_INSERT_VECTOR_ELT = 214,
230
    G_EXTRACT_VECTOR_ELT  = 215,
231
    G_SHUFFLE_VECTOR  = 216,
232
    G_CTTZ  = 217,
233
    G_CTTZ_ZERO_UNDEF = 218,
234
    G_CTLZ  = 219,
235
    G_CTLZ_ZERO_UNDEF = 220,
236
    G_CTPOP = 221,
237
    G_BSWAP = 222,
238
    G_BITREVERSE  = 223,
239
    G_FCEIL = 224,
240
    G_FCOS  = 225,
241
    G_FSIN  = 226,
242
    G_FSQRT = 227,
243
    G_FFLOOR  = 228,
244
    G_FRINT = 229,
245
    G_FNEARBYINT  = 230,
246
    G_ADDRSPACE_CAST  = 231,
247
    G_BLOCK_ADDR  = 232,
248
    G_JUMP_TABLE  = 233,
249
    G_DYN_STACKALLOC  = 234,
250
    G_STACKSAVE = 235,
251
    G_STACKRESTORE  = 236,
252
    G_STRICT_FADD = 237,
253
    G_STRICT_FSUB = 238,
254
    G_STRICT_FMUL = 239,
255
    G_STRICT_FDIV = 240,
256
    G_STRICT_FREM = 241,
257
    G_STRICT_FMA  = 242,
258
    G_STRICT_FSQRT  = 243,
259
    G_STRICT_FLDEXP = 244,
260
    G_READ_REGISTER = 245,
261
    G_WRITE_REGISTER  = 246,
262
    G_MEMCPY  = 247,
263
    G_MEMCPY_INLINE = 248,
264
    G_MEMMOVE = 249,
265
    G_MEMSET  = 250,
266
    G_BZERO = 251,
267
    G_VECREDUCE_SEQ_FADD  = 252,
268
    G_VECREDUCE_SEQ_FMUL  = 253,
269
    G_VECREDUCE_FADD  = 254,
270
    G_VECREDUCE_FMUL  = 255,
271
    G_VECREDUCE_FMAX  = 256,
272
    G_VECREDUCE_FMIN  = 257,
273
    G_VECREDUCE_FMAXIMUM  = 258,
274
    G_VECREDUCE_FMINIMUM  = 259,
275
    G_VECREDUCE_ADD = 260,
276
    G_VECREDUCE_MUL = 261,
277
    G_VECREDUCE_AND = 262,
278
    G_VECREDUCE_OR  = 263,
279
    G_VECREDUCE_XOR = 264,
280
    G_VECREDUCE_SMAX  = 265,
281
    G_VECREDUCE_SMIN  = 266,
282
    G_VECREDUCE_UMAX  = 267,
283
    G_VECREDUCE_UMIN  = 268,
284
    G_SBFX  = 269,
285
    G_UBFX  = 270,
286
    ADJCALLSTACKDOWN  = 271,
287
    ADJCALLSTACKUP  = 272,
288
    FI_ri = 273,
289
    MEMCPY  = 274,
290
    Select  = 275,
291
    Select_32 = 276,
292
    Select_32_64  = 277,
293
    Select_64_32  = 278,
294
    Select_Ri = 279,
295
    Select_Ri_32  = 280,
296
    Select_Ri_32_64 = 281,
297
    Select_Ri_64_32 = 282,
298
    ADD_ri  = 283,
299
    ADD_ri_32 = 284,
300
    ADD_rr  = 285,
301
    ADD_rr_32 = 286,
302
    AND_ri  = 287,
303
    AND_ri_32 = 288,
304
    AND_rr  = 289,
305
    AND_rr_32 = 290,
306
    BE16  = 291,
307
    BE32  = 292,
308
    BE64  = 293,
309
    BSWAP16 = 294,
310
    BSWAP32 = 295,
311
    BSWAP64 = 296,
312
    CMPXCHGD  = 297,
313
    CMPXCHGW32  = 298,
314
    CORE_LD32 = 299,
315
    CORE_LD64 = 300,
316
    CORE_SHIFT  = 301,
317
    CORE_ST = 302,
318
    DIV_ri  = 303,
319
    DIV_ri_32 = 304,
320
    DIV_rr  = 305,
321
    DIV_rr_32 = 306,
322
    JAL = 307,
323
    JALX  = 308,
324
    JEQ_ri  = 309,
325
    JEQ_ri_32 = 310,
326
    JEQ_rr  = 311,
327
    JEQ_rr_32 = 312,
328
    JMP = 313,
329
    JMPL  = 314,
330
    JNE_ri  = 315,
331
    JNE_ri_32 = 316,
332
    JNE_rr  = 317,
333
    JNE_rr_32 = 318,
334
    JSET_ri = 319,
335
    JSET_ri_32  = 320,
336
    JSET_rr = 321,
337
    JSET_rr_32  = 322,
338
    JSGE_ri = 323,
339
    JSGE_ri_32  = 324,
340
    JSGE_rr = 325,
341
    JSGE_rr_32  = 326,
342
    JSGT_ri = 327,
343
    JSGT_ri_32  = 328,
344
    JSGT_rr = 329,
345
    JSGT_rr_32  = 330,
346
    JSLE_ri = 331,
347
    JSLE_ri_32  = 332,
348
    JSLE_rr = 333,
349
    JSLE_rr_32  = 334,
350
    JSLT_ri = 335,
351
    JSLT_ri_32  = 336,
352
    JSLT_rr = 337,
353
    JSLT_rr_32  = 338,
354
    JUGE_ri = 339,
355
    JUGE_ri_32  = 340,
356
    JUGE_rr = 341,
357
    JUGE_rr_32  = 342,
358
    JUGT_ri = 343,
359
    JUGT_ri_32  = 344,
360
    JUGT_rr = 345,
361
    JUGT_rr_32  = 346,
362
    JULE_ri = 347,
363
    JULE_ri_32  = 348,
364
    JULE_rr = 349,
365
    JULE_rr_32  = 350,
366
    JULT_ri = 351,
367
    JULT_ri_32  = 352,
368
    JULT_rr = 353,
369
    JULT_rr_32  = 354,
370
    LDB = 355,
371
    LDB32 = 356,
372
    LDBSX = 357,
373
    LDD = 358,
374
    LDH = 359,
375
    LDH32 = 360,
376
    LDHSX = 361,
377
    LDW = 362,
378
    LDW32 = 363,
379
    LDWSX = 364,
380
    LD_ABS_B  = 365,
381
    LD_ABS_H  = 366,
382
    LD_ABS_W  = 367,
383
    LD_IND_B  = 368,
384
    LD_IND_H  = 369,
385
    LD_IND_W  = 370,
386
    LD_imm64  = 371,
387
    LD_pseudo = 372,
388
    LE16  = 373,
389
    LE32  = 374,
390
    LE64  = 375,
391
    MOD_ri  = 376,
392
    MOD_ri_32 = 377,
393
    MOD_rr  = 378,
394
    MOD_rr_32 = 379,
395
    MOVSX_rr_16 = 380,
396
    MOVSX_rr_32 = 381,
397
    MOVSX_rr_32_16  = 382,
398
    MOVSX_rr_32_8 = 383,
399
    MOVSX_rr_8  = 384,
400
    MOV_32_64 = 385,
401
    MOV_ri  = 386,
402
    MOV_ri_32 = 387,
403
    MOV_rr  = 388,
404
    MOV_rr_32 = 389,
405
    MUL_ri  = 390,
406
    MUL_ri_32 = 391,
407
    MUL_rr  = 392,
408
    MUL_rr_32 = 393,
409
    NEG_32  = 394,
410
    NEG_64  = 395,
411
    NOP = 396,
412
    OR_ri = 397,
413
    OR_ri_32  = 398,
414
    OR_rr = 399,
415
    OR_rr_32  = 400,
416
    RET = 401,
417
    SDIV_ri = 402,
418
    SDIV_ri_32  = 403,
419
    SDIV_rr = 404,
420
    SDIV_rr_32  = 405,
421
    SLL_ri  = 406,
422
    SLL_ri_32 = 407,
423
    SLL_rr  = 408,
424
    SLL_rr_32 = 409,
425
    SMOD_ri = 410,
426
    SMOD_ri_32  = 411,
427
    SMOD_rr = 412,
428
    SMOD_rr_32  = 413,
429
    SRA_ri  = 414,
430
    SRA_ri_32 = 415,
431
    SRA_rr  = 416,
432
    SRA_rr_32 = 417,
433
    SRL_ri  = 418,
434
    SRL_ri_32 = 419,
435
    SRL_rr  = 420,
436
    SRL_rr_32 = 421,
437
    STB = 422,
438
    STB32 = 423,
439
    STB_imm = 424,
440
    STD = 425,
441
    STD_imm = 426,
442
    STH = 427,
443
    STH32 = 428,
444
    STH_imm = 429,
445
    STW = 430,
446
    STW32 = 431,
447
    STW_imm = 432,
448
    SUB_ri  = 433,
449
    SUB_ri_32 = 434,
450
    SUB_rr  = 435,
451
    SUB_rr_32 = 436,
452
    XADDD = 437,
453
    XADDW = 438,
454
    XADDW32 = 439,
455
    XANDD = 440,
456
    XANDW32 = 441,
457
    XCHGD = 442,
458
    XCHGW32 = 443,
459
    XFADDD  = 444,
460
    XFADDW32  = 445,
461
    XFANDD  = 446,
462
    XFANDW32  = 447,
463
    XFORD = 448,
464
    XFORW32 = 449,
465
    XFXORD  = 450,
466
    XFXORW32  = 451,
467
    XORD  = 452,
468
    XORW32  = 453,
469
    XOR_ri  = 454,
470
    XOR_ri_32 = 455,
471
    XOR_rr  = 456,
472
    XOR_rr_32 = 457,
473
    XXORD = 458,
474
    XXORW32 = 459,
475
    INSTRUCTION_LIST_END = 460
476
  };
477
478
} // end namespace BPF
479
} // end namespace llvm
480
#endif // GET_INSTRINFO_ENUM
481
482
#ifdef GET_INSTRINFO_SCHED_ENUM
483
#undef GET_INSTRINFO_SCHED_ENUM
484
namespace llvm {
485
486
namespace BPF {
487
namespace Sched {
488
  enum {
489
    NoInstrModel  = 0,
490
    SCHED_LIST_END = 1
491
  };
492
} // end namespace Sched
493
} // end namespace BPF
494
} // end namespace llvm
495
#endif // GET_INSTRINFO_SCHED_ENUM
496
497
#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
498
namespace llvm {
499
500
struct BPFInstrTable {
501
  MCInstrDesc Insts[460];
502
  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
503
  MCOperandInfo OperandInfo[272];
504
  static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
505
  MCPhysReg ImplicitOps[20];
506
};
507
508
} // end namespace llvm
509
#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
510
511
#ifdef GET_INSTRINFO_MC_DESC
512
#undef GET_INSTRINFO_MC_DESC
513
namespace llvm {
514
515
static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
516
static constexpr unsigned BPFImpOpBase = sizeof BPFInstrTable::OperandInfo / (sizeof(MCPhysReg));
517
518
extern const BPFInstrTable BPFDescs = {
519
  {
520
    { 459,  4,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 268,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #459 = XXORW32
521
    { 458,  4,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 264,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #458 = XXORD
522
    { 457,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 204,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #457 = XOR_rr_32
523
    { 456,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 201,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #456 = XOR_rr
524
    { 455,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 198,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #455 = XOR_ri_32
525
    { 454,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 195,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #454 = XOR_ri
526
    { 453,  4,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 268,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #453 = XORW32
527
    { 452,  4,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 264,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #452 = XORD
528
    { 451,  4,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 268,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #451 = XFXORW32
529
    { 450,  4,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 264,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #450 = XFXORD
530
    { 449,  4,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 268,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #449 = XFORW32
531
    { 448,  4,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 264,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #448 = XFORD
532
    { 447,  4,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 268,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #447 = XFANDW32
533
    { 446,  4,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 264,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #446 = XFANDD
534
    { 445,  4,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 268,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #445 = XFADDW32
535
    { 444,  4,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 264,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #444 = XFADDD
536
    { 443,  4,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 268,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #443 = XCHGW32
537
    { 442,  4,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 264,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #442 = XCHGD
538
    { 441,  4,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 268,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #441 = XANDW32
539
    { 440,  4,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 264,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #440 = XANDD
540
    { 439,  4,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 268,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #439 = XADDW32
541
    { 438,  4,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 264,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #438 = XADDW
542
    { 437,  4,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 264,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #437 = XADDD
543
    { 436,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 204,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #436 = SUB_rr_32
544
    { 435,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 201,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #435 = SUB_rr
545
    { 434,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 198,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #434 = SUB_ri_32
546
    { 433,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 195,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #433 = SUB_ri
547
    { 432,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 261,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #432 = STW_imm
548
    { 431,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 244,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #431 = STW32
549
    { 430,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 140,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #430 = STW
550
    { 429,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 261,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #429 = STH_imm
551
    { 428,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 244,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #428 = STH32
552
    { 427,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 140,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #427 = STH
553
    { 426,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 261,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #426 = STD_imm
554
    { 425,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 140,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #425 = STD
555
    { 424,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 261,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #424 = STB_imm
556
    { 423,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 244,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #423 = STB32
557
    { 422,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 140,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #422 = STB
558
    { 421,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 204,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #421 = SRL_rr_32
559
    { 420,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 201,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #420 = SRL_rr
560
    { 419,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 198,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #419 = SRL_ri_32
561
    { 418,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 195,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #418 = SRL_ri
562
    { 417,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 204,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #417 = SRA_rr_32
563
    { 416,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 201,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #416 = SRA_rr
564
    { 415,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 198,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #415 = SRA_ri_32
565
    { 414,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 195,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #414 = SRA_ri
566
    { 413,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 204,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #413 = SMOD_rr_32
567
    { 412,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 201,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #412 = SMOD_rr
568
    { 411,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 198,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #411 = SMOD_ri_32
569
    { 410,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 195,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #410 = SMOD_ri
570
    { 409,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 204,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #409 = SLL_rr_32
571
    { 408,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 201,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #408 = SLL_rr
572
    { 407,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 198,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #407 = SLL_ri_32
573
    { 406,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 195,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #406 = SLL_ri
574
    { 405,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 204,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #405 = SDIV_rr_32
575
    { 404,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 201,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #404 = SDIV_rr
576
    { 403,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 198,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #403 = SDIV_ri_32
577
    { 402,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 195,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #402 = SDIV_ri
578
    { 401,  0,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #401 = RET
579
    { 400,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 204,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #400 = OR_rr_32
580
    { 399,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 201,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #399 = OR_rr
581
    { 398,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 198,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #398 = OR_ri_32
582
    { 397,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 195,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #397 = OR_ri
583
    { 396,  1,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #396 = NOP
584
    { 395,  2,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 207,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #395 = NEG_64
585
    { 394,  2,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 259,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #394 = NEG_32
586
    { 393,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 204,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #393 = MUL_rr_32
587
    { 392,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 201,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #392 = MUL_rr
588
    { 391,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 198,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #391 = MUL_ri_32
589
    { 390,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 195,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #390 = MUL_ri
590
    { 389,  2,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 253,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #389 = MOV_rr_32
591
    { 388,  2,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 249,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #388 = MOV_rr
592
    { 387,  2,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 257,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #387 = MOV_ri_32
593
    { 386,  2,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 247,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #386 = MOV_ri
594
    { 385,  2,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 255,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #385 = MOV_32_64
595
    { 384,  2,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 249,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #384 = MOVSX_rr_8
596
    { 383,  2,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 253,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #383 = MOVSX_rr_32_8
597
    { 382,  2,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 253,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #382 = MOVSX_rr_32_16
598
    { 381,  2,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 249,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #381 = MOVSX_rr_32
599
    { 380,  2,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 249,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #380 = MOVSX_rr_16
600
    { 379,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 204,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #379 = MOD_rr_32
601
    { 378,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 201,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #378 = MOD_rr
602
    { 377,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 198,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #377 = MOD_ri_32
603
    { 376,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 195,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #376 = MOD_ri
604
    { 375,  2,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 207,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #375 = LE64
605
    { 374,  2,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 207,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #374 = LE32
606
    { 373,  2,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 207,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #373 = LE16
607
    { 372,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 232,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #372 = LD_pseudo
608
    { 371,  2,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 251,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #371 = LD_imm64
609
    { 370,  2,  0,  8,  0,  1,  6,  BPFImpOpBase + 13,  249,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #370 = LD_IND_W
610
    { 369,  2,  0,  8,  0,  1,  6,  BPFImpOpBase + 13,  249,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #369 = LD_IND_H
611
    { 368,  2,  0,  8,  0,  1,  6,  BPFImpOpBase + 13,  249,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #368 = LD_IND_B
612
    { 367,  2,  0,  8,  0,  1,  6,  BPFImpOpBase + 13,  247,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #367 = LD_ABS_W
613
    { 366,  2,  0,  8,  0,  1,  6,  BPFImpOpBase + 13,  247,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #366 = LD_ABS_H
614
    { 365,  2,  0,  8,  0,  1,  6,  BPFImpOpBase + 13,  247,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #365 = LD_ABS_B
615
    { 364,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #364 = LDWSX
616
    { 363,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 244,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #363 = LDW32
617
    { 362,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #362 = LDW
618
    { 361,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #361 = LDHSX
619
    { 360,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 244,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #360 = LDH32
620
    { 359,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #359 = LDH
621
    { 358,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #358 = LDD
622
    { 357,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #357 = LDBSX
623
    { 356,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 244,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #356 = LDB32
624
    { 355,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #355 = LDB
625
    { 354,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 241,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #354 = JULT_rr_32
626
    { 353,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 238,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #353 = JULT_rr
627
    { 352,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 235,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #352 = JULT_ri_32
628
    { 351,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 232,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #351 = JULT_ri
629
    { 350,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 241,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #350 = JULE_rr_32
630
    { 349,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 238,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #349 = JULE_rr
631
    { 348,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 235,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #348 = JULE_ri_32
632
    { 347,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 232,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #347 = JULE_ri
633
    { 346,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 241,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #346 = JUGT_rr_32
634
    { 345,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 238,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #345 = JUGT_rr
635
    { 344,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 235,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #344 = JUGT_ri_32
636
    { 343,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 232,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #343 = JUGT_ri
637
    { 342,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 241,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #342 = JUGE_rr_32
638
    { 341,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 238,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #341 = JUGE_rr
639
    { 340,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 235,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #340 = JUGE_ri_32
640
    { 339,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 232,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #339 = JUGE_ri
641
    { 338,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 241,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #338 = JSLT_rr_32
642
    { 337,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 238,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #337 = JSLT_rr
643
    { 336,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 235,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #336 = JSLT_ri_32
644
    { 335,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 232,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #335 = JSLT_ri
645
    { 334,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 241,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #334 = JSLE_rr_32
646
    { 333,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 238,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #333 = JSLE_rr
647
    { 332,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 235,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #332 = JSLE_ri_32
648
    { 331,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 232,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #331 = JSLE_ri
649
    { 330,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 241,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #330 = JSGT_rr_32
650
    { 329,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 238,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #329 = JSGT_rr
651
    { 328,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 235,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #328 = JSGT_ri_32
652
    { 327,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 232,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #327 = JSGT_ri
653
    { 326,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 241,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #326 = JSGE_rr_32
654
    { 325,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 238,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #325 = JSGE_rr
655
    { 324,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 235,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #324 = JSGE_ri_32
656
    { 323,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 232,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #323 = JSGE_ri
657
    { 322,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 241,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #322 = JSET_rr_32
658
    { 321,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 238,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #321 = JSET_rr
659
    { 320,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 235,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #320 = JSET_ri_32
660
    { 319,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 232,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #319 = JSET_ri
661
    { 318,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 241,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #318 = JNE_rr_32
662
    { 317,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 238,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #317 = JNE_rr
663
    { 316,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 235,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #316 = JNE_ri_32
664
    { 315,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 232,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #315 = JNE_ri
665
    { 314,  1,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #314 = JMPL
666
    { 313,  1,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #313 = JMP
667
    { 312,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 241,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #312 = JEQ_rr_32
668
    { 311,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 238,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #311 = JEQ_rr
669
    { 310,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 235,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #310 = JEQ_ri_32
670
    { 309,  3,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 232,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #309 = JEQ_ri
671
    { 308,  1,  0,  8,  0,  1,  6,  BPFImpOpBase + 6, 231,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #308 = JALX
672
    { 307,  1,  0,  8,  0,  1,  6,  BPFImpOpBase + 6, 0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #307 = JAL
673
    { 306,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 204,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #306 = DIV_rr_32
674
    { 305,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 201,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #305 = DIV_rr
675
    { 304,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 198,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #304 = DIV_ri_32
676
    { 303,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 195,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #303 = DIV_ri
677
    { 302,  4,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 227,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #302 = CORE_ST
678
    { 301,  4,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 223,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #301 = CORE_SHIFT
679
    { 300,  4,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 219,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #300 = CORE_LD64
680
    { 299,  4,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 215,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #299 = CORE_LD32
681
    { 298,  3,  0,  8,  0,  1,  1,  BPFImpOpBase + 4, 212,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #298 = CMPXCHGW32
682
    { 297,  3,  0,  8,  0,  1,  1,  BPFImpOpBase + 2, 209,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #297 = CMPXCHGD
683
    { 296,  2,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 207,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #296 = BSWAP64
684
    { 295,  2,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 207,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #295 = BSWAP32
685
    { 294,  2,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 207,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #294 = BSWAP16
686
    { 293,  2,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 207,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #293 = BE64
687
    { 292,  2,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 207,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #292 = BE32
688
    { 291,  2,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 207,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #291 = BE16
689
    { 290,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 204,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #290 = AND_rr_32
690
    { 289,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 201,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #289 = AND_rr
691
    { 288,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 198,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #288 = AND_ri_32
692
    { 287,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 195,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #287 = AND_ri
693
    { 286,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 204,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #286 = ADD_rr_32
694
    { 285,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 201,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #285 = ADD_rr
695
    { 284,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 198,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #284 = ADD_ri_32
696
    { 283,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 195,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #283 = ADD_ri
697
    { 282,  6,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 189,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #282 = Select_Ri_64_32
698
    { 281,  6,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 183,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #281 = Select_Ri_32_64
699
    { 280,  6,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 177,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #280 = Select_Ri_32
700
    { 279,  6,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 171,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #279 = Select_Ri
701
    { 278,  6,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 165,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #278 = Select_64_32
702
    { 277,  6,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 159,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #277 = Select_32_64
703
    { 276,  6,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 153,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #276 = Select_32
704
    { 275,  6,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 147,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #275 = Select
705
    { 274,  4,  0,  8,  0,  0,  0,  BPFImpOpBase + 0, 143,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #274 = MEMCPY
706
    { 273,  3,  1,  8,  0,  0,  0,  BPFImpOpBase + 0, 140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #273 = FI_ri
707
    { 272,  2,  0,  8,  0,  1,  1,  BPFImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #272 = ADJCALLSTACKUP
708
    { 271,  2,  0,  8,  0,  1,  1,  BPFImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #271 = ADJCALLSTACKDOWN
709
    { 270,  4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 136,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #270 = G_UBFX
710
    { 269,  4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 136,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #269 = G_SBFX
711
    { 268,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #268 = G_VECREDUCE_UMIN
712
    { 267,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #267 = G_VECREDUCE_UMAX
713
    { 266,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #266 = G_VECREDUCE_SMIN
714
    { 265,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #265 = G_VECREDUCE_SMAX
715
    { 264,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #264 = G_VECREDUCE_XOR
716
    { 263,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #263 = G_VECREDUCE_OR
717
    { 262,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #262 = G_VECREDUCE_AND
718
    { 261,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #261 = G_VECREDUCE_MUL
719
    { 260,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #260 = G_VECREDUCE_ADD
720
    { 259,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #259 = G_VECREDUCE_FMINIMUM
721
    { 258,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #258 = G_VECREDUCE_FMAXIMUM
722
    { 257,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #257 = G_VECREDUCE_FMIN
723
    { 256,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #256 = G_VECREDUCE_FMAX
724
    { 255,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #255 = G_VECREDUCE_FMUL
725
    { 254,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #254 = G_VECREDUCE_FADD
726
    { 253,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #253 = G_VECREDUCE_SEQ_FMUL
727
    { 252,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #252 = G_VECREDUCE_SEQ_FADD
728
    { 251,  3,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #251 = G_BZERO
729
    { 250,  4,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #250 = G_MEMSET
730
    { 249,  4,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #249 = G_MEMMOVE
731
    { 248,  3,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #248 = G_MEMCPY_INLINE
732
    { 247,  4,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #247 = G_MEMCPY
733
    { 246,  2,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 130,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #246 = G_WRITE_REGISTER
734
    { 245,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #245 = G_READ_REGISTER
735
    { 244,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #244 = G_STRICT_FLDEXP
736
    { 243,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #243 = G_STRICT_FSQRT
737
    { 242,  4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #242 = G_STRICT_FMA
738
    { 241,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #241 = G_STRICT_FREM
739
    { 240,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #240 = G_STRICT_FDIV
740
    { 239,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #239 = G_STRICT_FMUL
741
    { 238,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #238 = G_STRICT_FSUB
742
    { 237,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #237 = G_STRICT_FADD
743
    { 236,  1,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #236 = G_STACKRESTORE
744
    { 235,  1,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #235 = G_STACKSAVE
745
    { 234,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 64, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #234 = G_DYN_STACKALLOC
746
    { 233,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #233 = G_JUMP_TABLE
747
    { 232,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #232 = G_BLOCK_ADDR
748
    { 231,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #231 = G_ADDRSPACE_CAST
749
    { 230,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #230 = G_FNEARBYINT
750
    { 229,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #229 = G_FRINT
751
    { 228,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #228 = G_FFLOOR
752
    { 227,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #227 = G_FSQRT
753
    { 226,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #226 = G_FSIN
754
    { 225,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #225 = G_FCOS
755
    { 224,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #224 = G_FCEIL
756
    { 223,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #223 = G_BITREVERSE
757
    { 222,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #222 = G_BSWAP
758
    { 221,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #221 = G_CTPOP
759
    { 220,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #220 = G_CTLZ_ZERO_UNDEF
760
    { 219,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #219 = G_CTLZ
761
    { 218,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #218 = G_CTTZ_ZERO_UNDEF
762
    { 217,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #217 = G_CTTZ
763
    { 216,  4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 126,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #216 = G_SHUFFLE_VECTOR
764
    { 215,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #215 = G_EXTRACT_VECTOR_ELT
765
    { 214,  4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 119,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #214 = G_INSERT_VECTOR_ELT
766
    { 213,  3,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 116,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #213 = G_BRJT
767
    { 212,  1,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #212 = G_BR
768
    { 211,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #211 = G_LLROUND
769
    { 210,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #210 = G_LROUND
770
    { 209,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #209 = G_ABS
771
    { 208,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #208 = G_UMAX
772
    { 207,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #207 = G_UMIN
773
    { 206,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #206 = G_SMAX
774
    { 205,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #205 = G_SMIN
775
    { 204,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #204 = G_PTRMASK
776
    { 203,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #203 = G_PTR_ADD
777
    { 202,  0,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #202 = G_RESET_FPMODE
778
    { 201,  1,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #201 = G_SET_FPMODE
779
    { 200,  1,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #200 = G_GET_FPMODE
780
    { 199,  0,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #199 = G_RESET_FPENV
781
    { 198,  1,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #198 = G_SET_FPENV
782
    { 197,  1,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #197 = G_GET_FPENV
783
    { 196,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #196 = G_FMAXIMUM
784
    { 195,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #195 = G_FMINIMUM
785
    { 194,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #194 = G_FMAXNUM_IEEE
786
    { 193,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #193 = G_FMINNUM_IEEE
787
    { 192,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #192 = G_FMAXNUM
788
    { 191,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #191 = G_FMINNUM
789
    { 190,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #190 = G_FCANONICALIZE
790
    { 189,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 93, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #189 = G_IS_FPCLASS
791
    { 188,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #188 = G_FCOPYSIGN
792
    { 187,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #187 = G_FABS
793
    { 186,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #186 = G_UITOFP
794
    { 185,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #185 = G_SITOFP
795
    { 184,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #184 = G_FPTOUI
796
    { 183,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #183 = G_FPTOSI
797
    { 182,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #182 = G_FPTRUNC
798
    { 181,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #181 = G_FPEXT
799
    { 180,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #180 = G_FNEG
800
    { 179,  3,  2,  0,  0,  0,  0,  BPFImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #179 = G_FFREXP
801
    { 178,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #178 = G_FLDEXP
802
    { 177,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #177 = G_FLOG10
803
    { 176,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #176 = G_FLOG2
804
    { 175,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #175 = G_FLOG
805
    { 174,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #174 = G_FEXP10
806
    { 173,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #173 = G_FEXP2
807
    { 172,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #172 = G_FEXP
808
    { 171,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #171 = G_FPOWI
809
    { 170,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #170 = G_FPOW
810
    { 169,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #169 = G_FREM
811
    { 168,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #168 = G_FDIV
812
    { 167,  4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #167 = G_FMAD
813
    { 166,  4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #166 = G_FMA
814
    { 165,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #165 = G_FMUL
815
    { 164,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #164 = G_FSUB
816
    { 163,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #163 = G_FADD
817
    { 162,  4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #162 = G_UDIVFIXSAT
818
    { 161,  4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #161 = G_SDIVFIXSAT
819
    { 160,  4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #160 = G_UDIVFIX
820
    { 159,  4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #159 = G_SDIVFIX
821
    { 158,  4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #158 = G_UMULFIXSAT
822
    { 157,  4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #157 = G_SMULFIXSAT
823
    { 156,  4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #156 = G_UMULFIX
824
    { 155,  4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #155 = G_SMULFIX
825
    { 154,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #154 = G_SSHLSAT
826
    { 153,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #153 = G_USHLSAT
827
    { 152,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #152 = G_SSUBSAT
828
    { 151,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #151 = G_USUBSAT
829
    { 150,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #150 = G_SADDSAT
830
    { 149,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #149 = G_UADDSAT
831
    { 148,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #148 = G_SMULH
832
    { 147,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #147 = G_UMULH
833
    { 146,  4,  2,  0,  0,  0,  0,  BPFImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #146 = G_SMULO
834
    { 145,  4,  2,  0,  0,  0,  0,  BPFImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #145 = G_UMULO
835
    { 144,  5,  2,  0,  0,  0,  0,  BPFImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #144 = G_SSUBE
836
    { 143,  4,  2,  0,  0,  0,  0,  BPFImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #143 = G_SSUBO
837
    { 142,  5,  2,  0,  0,  0,  0,  BPFImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #142 = G_SADDE
838
    { 141,  4,  2,  0,  0,  0,  0,  BPFImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #141 = G_SADDO
839
    { 140,  5,  2,  0,  0,  0,  0,  BPFImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #140 = G_USUBE
840
    { 139,  4,  2,  0,  0,  0,  0,  BPFImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #139 = G_USUBO
841
    { 138,  5,  2,  0,  0,  0,  0,  BPFImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #138 = G_UADDE
842
    { 137,  4,  2,  0,  0,  0,  0,  BPFImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #137 = G_UADDO
843
    { 136,  4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #136 = G_SELECT
844
    { 135,  4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 103,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #135 = G_FCMP
845
    { 134,  4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 103,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #134 = G_ICMP
846
    { 133,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #133 = G_ROTL
847
    { 132,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #132 = G_ROTR
848
    { 131,  4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 99, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #131 = G_FSHR
849
    { 130,  4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 99, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #130 = G_FSHL
850
    { 129,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #129 = G_ASHR
851
    { 128,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #128 = G_LSHR
852
    { 127,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #127 = G_SHL
853
    { 126,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #126 = G_ZEXT
854
    { 125,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #125 = G_SEXT_INREG
855
    { 124,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #124 = G_SEXT
856
    { 123,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 93, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #123 = G_VAARG
857
    { 122,  1,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #122 = G_VASTART
858
    { 121,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #121 = G_FCONSTANT
859
    { 120,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #120 = G_CONSTANT
860
    { 119,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #119 = G_TRUNC
861
    { 118,  2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #118 = G_ANYEXT
862
    { 117,  1,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #117 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
863
    { 116,  1,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #116 = G_INTRINSIC_CONVERGENT
864
    { 115,  1,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #115 = G_INTRINSIC_W_SIDE_EFFECTS
865
    { 114,  1,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #114 = G_INTRINSIC
866
    { 113,  0,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #113 = G_INVOKE_REGION_START
867
    { 112,  1,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #112 = G_BRINDIRECT
868
    { 111,  2,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #111 = G_BRCOND
869
    { 110,  4,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 89, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #110 = G_PREFETCH
870
    { 109,  2,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #109 = G_FENCE
871
    { 108,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #108 = G_ATOMICRMW_UDEC_WRAP
872
    { 107,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #107 = G_ATOMICRMW_UINC_WRAP
873
    { 106,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #106 = G_ATOMICRMW_FMIN
874
    { 105,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #105 = G_ATOMICRMW_FMAX
875
    { 104,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #104 = G_ATOMICRMW_FSUB
876
    { 103,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #103 = G_ATOMICRMW_FADD
877
    { 102,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #102 = G_ATOMICRMW_UMIN
878
    { 101,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #101 = G_ATOMICRMW_UMAX
879
    { 100,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #100 = G_ATOMICRMW_MIN
880
    { 99, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #99 = G_ATOMICRMW_MAX
881
    { 98, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #98 = G_ATOMICRMW_XOR
882
    { 97, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #97 = G_ATOMICRMW_OR
883
    { 96, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #96 = G_ATOMICRMW_NAND
884
    { 95, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #95 = G_ATOMICRMW_AND
885
    { 94, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #94 = G_ATOMICRMW_SUB
886
    { 93, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #93 = G_ATOMICRMW_ADD
887
    { 92, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #92 = G_ATOMICRMW_XCHG
888
    { 91, 4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #91 = G_ATOMIC_CMPXCHG
889
    { 90, 5,  2,  0,  0,  0,  0,  BPFImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #90 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
890
    { 89, 5,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #89 = G_INDEXED_STORE
891
    { 88, 2,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #88 = G_STORE
892
    { 87, 5,  2,  0,  0,  0,  0,  BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #87 = G_INDEXED_ZEXTLOAD
893
    { 86, 5,  2,  0,  0,  0,  0,  BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #86 = G_INDEXED_SEXTLOAD
894
    { 85, 5,  2,  0,  0,  0,  0,  BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #85 = G_INDEXED_LOAD
895
    { 84, 2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #84 = G_ZEXTLOAD
896
    { 83, 2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #83 = G_SEXTLOAD
897
    { 82, 2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #82 = G_LOAD
898
    { 81, 1,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #81 = G_READCYCLECOUNTER
899
    { 80, 2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #80 = G_INTRINSIC_ROUNDEVEN
900
    { 79, 2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #79 = G_INTRINSIC_LRINT
901
    { 78, 2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #78 = G_INTRINSIC_ROUND
902
    { 77, 2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #77 = G_INTRINSIC_TRUNC
903
    { 76, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 64, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #76 = G_INTRINSIC_FPTRUNC_ROUND
904
    { 75, 2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #75 = G_CONSTANT_FOLD_BARRIER
905
    { 74, 2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #74 = G_FREEZE
906
    { 73, 2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #73 = G_BITCAST
907
    { 72, 2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #72 = G_INTTOPTR
908
    { 71, 2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #71 = G_PTRTOINT
909
    { 70, 2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #70 = G_CONCAT_VECTORS
910
    { 69, 2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #69 = G_BUILD_VECTOR_TRUNC
911
    { 68, 2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #68 = G_BUILD_VECTOR
912
    { 67, 2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #67 = G_MERGE_VALUES
913
    { 66, 4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #66 = G_INSERT
914
    { 65, 2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #65 = G_UNMERGE_VALUES
915
    { 64, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #64 = G_EXTRACT
916
    { 63, 2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #63 = G_CONSTANT_POOL
917
    { 62, 2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #62 = G_GLOBAL_VALUE
918
    { 61, 2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #61 = G_FRAME_INDEX
919
    { 60, 1,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #60 = G_PHI
920
    { 59, 1,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #59 = G_IMPLICIT_DEF
921
    { 58, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #58 = G_XOR
922
    { 57, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #57 = G_OR
923
    { 56, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #56 = G_AND
924
    { 55, 4,  2,  0,  0,  0,  0,  BPFImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #55 = G_UDIVREM
925
    { 54, 4,  2,  0,  0,  0,  0,  BPFImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #54 = G_SDIVREM
926
    { 53, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #53 = G_UREM
927
    { 52, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #52 = G_SREM
928
    { 51, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #51 = G_UDIV
929
    { 50, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #50 = G_SDIV
930
    { 49, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #49 = G_MUL
931
    { 48, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #48 = G_SUB
932
    { 47, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #47 = G_ADD
933
    { 46, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #46 = G_ASSERT_ALIGN
934
    { 45, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #45 = G_ASSERT_ZEXT
935
    { 44, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #44 = G_ASSERT_SEXT
936
    { 43, 1,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #43 = JUMP_TABLE_DEBUG_INFO
937
    { 42, 0,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #42 = MEMBARRIER
938
    { 41, 0,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #41 = ICALL_BRANCH_FUNNEL
939
    { 40, 3,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
940
    { 39, 2,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #39 = PATCHABLE_EVENT_CALL
941
    { 38, 0,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #38 = PATCHABLE_TAIL_CALL
942
    { 37, 0,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #37 = PATCHABLE_FUNCTION_EXIT
943
    { 36, 0,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #36 = PATCHABLE_RET
944
    { 35, 0,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #35 = PATCHABLE_FUNCTION_ENTER
945
    { 34, 0,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #34 = PATCHABLE_OP
946
    { 33, 1,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #33 = FAULTING_OP
947
    { 32, 2,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #32 = LOCAL_ESCAPE
948
    { 31, 0,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #31 = STATEPOINT
949
    { 30, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #30 = PREALLOCATED_ARG
950
    { 29, 1,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #29 = PREALLOCATED_SETUP
951
    { 28, 1,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #28 = LOAD_STACK_GUARD
952
    { 27, 6,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #27 = PATCHPOINT
953
    { 26, 0,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #26 = FENTRY_CALL
954
    { 25, 2,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #25 = STACKMAP
955
    { 24, 2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #24 = ARITH_FENCE
956
    { 23, 4,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #23 = PSEUDO_PROBE
957
    { 22, 1,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #22 = LIFETIME_END
958
    { 21, 1,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #21 = LIFETIME_START
959
    { 20, 0,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #20 = BUNDLE
960
    { 19, 2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #19 = COPY
961
    { 18, 2,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #18 = REG_SEQUENCE
962
    { 17, 1,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #17 = DBG_LABEL
963
    { 16, 0,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #16 = DBG_PHI
964
    { 15, 0,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #15 = DBG_INSTR_REF
965
    { 14, 0,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #14 = DBG_VALUE_LIST
966
    { 13, 0,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #13 = DBG_VALUE
967
    { 12, 3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 2,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #12 = COPY_TO_REGCLASS
968
    { 11, 4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 9,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #11 = SUBREG_TO_REG
969
    { 10, 1,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #10 = IMPLICIT_DEF
970
    { 9,  4,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 5,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #9 = INSERT_SUBREG
971
    { 8,  3,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 2,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #8 = EXTRACT_SUBREG
972
    { 7,  0,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #7 = KILL
973
    { 6,  1,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #6 = ANNOTATION_LABEL
974
    { 5,  1,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #5 = GC_LABEL
975
    { 4,  1,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #4 = EH_LABEL
976
    { 3,  1,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #3 = CFI_INSTRUCTION
977
    { 2,  0,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #2 = INLINEASM_BR
978
    { 1,  0,  0,  0,  0,  0,  0,  BPFImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1 = INLINEASM
979
    { 0,  1,  1,  0,  0,  0,  0,  BPFImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #0 = PHI
980
  }, {
981
    /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
982
    /* 1 */
983
    /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
984
    /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
985
    /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
986
    /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
987
    /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
988
    /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
989
    /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
990
    /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
991
    /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
992
    /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
993
    /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
994
    /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
995
    /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
996
    /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
997
    /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
998
    /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
999
    /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1000
    /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1001
    /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1002
    /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1003
    /* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1004
    /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1005
    /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1006
    /* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1007
    /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1008
    /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1009
    /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1010
    /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1011
    /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1012
    /* 89 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1013
    /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1014
    /* 96 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1015
    /* 99 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1016
    /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1017
    /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1018
    /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1019
    /* 116 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1020
    /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1021
    /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1022
    /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1023
    /* 130 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1024
    /* 132 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1025
    /* 136 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1026
    /* 140 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1027
    /* 143 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1028
    /* 147 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1029
    /* 153 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1030
    /* 159 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1031
    /* 165 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1032
    /* 171 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1033
    /* 177 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1034
    /* 183 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1035
    /* 189 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1036
    /* 195 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1037
    /* 198 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1038
    /* 201 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1039
    /* 204 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1040
    /* 207 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1041
    /* 209 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1042
    /* 212 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1043
    /* 215 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1044
    /* 219 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1045
    /* 223 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1046
    /* 227 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1047
    /* 231 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1048
    /* 232 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1049
    /* 235 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1050
    /* 238 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1051
    /* 241 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1052
    /* 244 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1053
    /* 247 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1054
    /* 249 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1055
    /* 251 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1056
    /* 253 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1057
    /* 255 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1058
    /* 257 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1059
    /* 259 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1060
    /* 261 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1061
    /* 264 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1062
    /* 268 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1063
  }, {
1064
    /* 0 */
1065
    /* 0 */ BPF::R11, BPF::R11,
1066
    /* 2 */ BPF::R0, BPF::R0,
1067
    /* 4 */ BPF::W0, BPF::W0,
1068
    /* 6 */ BPF::R11, BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5,
1069
    /* 13 */ BPF::R6, BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5,
1070
  }
1071
};
1072
1073
1074
#ifdef __GNUC__
1075
#pragma GCC diagnostic push
1076
#pragma GCC diagnostic ignored "-Woverlength-strings"
1077
#endif
1078
extern const char BPFInstrNameData[] = {
1079
  /* 0 */ "G_FLOG10\0"
1080
  /* 9 */ "G_FEXP10\0"
1081
  /* 18 */ "LDB32\0"
1082
  /* 24 */ "STB32\0"
1083
  /* 30 */ "CORE_LD32\0"
1084
  /* 40 */ "BE32\0"
1085
  /* 45 */ "LE32\0"
1086
  /* 50 */ "LDH32\0"
1087
  /* 56 */ "STH32\0"
1088
  /* 62 */ "BSWAP32\0"
1089
  /* 70 */ "XFADDW32\0"
1090
  /* 79 */ "XADDW32\0"
1091
  /* 87 */ "LDW32\0"
1092
  /* 93 */ "XFANDW32\0"
1093
  /* 102 */ "XANDW32\0"
1094
  /* 110 */ "CMPXCHGW32\0"
1095
  /* 121 */ "XFORW32\0"
1096
  /* 129 */ "XFXORW32\0"
1097
  /* 138 */ "XXORW32\0"
1098
  /* 146 */ "STW32\0"
1099
  /* 152 */ "Select_Ri_64_32\0"
1100
  /* 168 */ "Select_64_32\0"
1101
  /* 181 */ "NEG_32\0"
1102
  /* 188 */ "Select_Ri_32\0"
1103
  /* 201 */ "SRA_ri_32\0"
1104
  /* 211 */ "SUB_ri_32\0"
1105
  /* 221 */ "ADD_ri_32\0"
1106
  /* 231 */ "AND_ri_32\0"
1107
  /* 241 */ "SMOD_ri_32\0"
1108
  /* 252 */ "JSGE_ri_32\0"
1109
  /* 263 */ "JUGE_ri_32\0"
1110
  /* 274 */ "JSLE_ri_32\0"
1111
  /* 285 */ "JULE_ri_32\0"
1112
  /* 296 */ "JNE_ri_32\0"
1113
  /* 306 */ "SLL_ri_32\0"
1114
  /* 316 */ "SRL_ri_32\0"
1115
  /* 326 */ "MUL_ri_32\0"
1116
  /* 336 */ "JEQ_ri_32\0"
1117
  /* 346 */ "XOR_ri_32\0"
1118
  /* 356 */ "JSET_ri_32\0"
1119
  /* 367 */ "JSGT_ri_32\0"
1120
  /* 378 */ "JUGT_ri_32\0"
1121
  /* 389 */ "JSLT_ri_32\0"
1122
  /* 400 */ "JULT_ri_32\0"
1123
  /* 411 */ "SDIV_ri_32\0"
1124
  /* 422 */ "MOV_ri_32\0"
1125
  /* 432 */ "SRA_rr_32\0"
1126
  /* 442 */ "SUB_rr_32\0"
1127
  /* 452 */ "ADD_rr_32\0"
1128
  /* 462 */ "AND_rr_32\0"
1129
  /* 472 */ "SMOD_rr_32\0"
1130
  /* 483 */ "JSGE_rr_32\0"
1131
  /* 494 */ "JUGE_rr_32\0"
1132
  /* 505 */ "JSLE_rr_32\0"
1133
  /* 516 */ "JULE_rr_32\0"
1134
  /* 527 */ "JNE_rr_32\0"
1135
  /* 537 */ "SLL_rr_32\0"
1136
  /* 547 */ "SRL_rr_32\0"
1137
  /* 557 */ "MUL_rr_32\0"
1138
  /* 567 */ "JEQ_rr_32\0"
1139
  /* 577 */ "XOR_rr_32\0"
1140
  /* 587 */ "JSET_rr_32\0"
1141
  /* 598 */ "JSGT_rr_32\0"
1142
  /* 609 */ "JUGT_rr_32\0"
1143
  /* 620 */ "JSLT_rr_32\0"
1144
  /* 631 */ "JULT_rr_32\0"
1145
  /* 642 */ "SDIV_rr_32\0"
1146
  /* 653 */ "MOV_rr_32\0"
1147
  /* 663 */ "MOVSX_rr_32\0"
1148
  /* 675 */ "Select_32\0"
1149
  /* 685 */ "G_FLOG2\0"
1150
  /* 693 */ "G_FEXP2\0"
1151
  /* 701 */ "CORE_LD64\0"
1152
  /* 711 */ "BE64\0"
1153
  /* 716 */ "LE64\0"
1154
  /* 721 */ "BSWAP64\0"
1155
  /* 729 */ "MOV_32_64\0"
1156
  /* 739 */ "Select_Ri_32_64\0"
1157
  /* 755 */ "Select_32_64\0"
1158
  /* 768 */ "NEG_64\0"
1159
  /* 775 */ "LD_imm64\0"
1160
  /* 784 */ "BE16\0"
1161
  /* 789 */ "LE16\0"
1162
  /* 794 */ "BSWAP16\0"
1163
  /* 802 */ "MOVSX_rr_32_16\0"
1164
  /* 817 */ "MOVSX_rr_16\0"
1165
  /* 829 */ "MOVSX_rr_32_8\0"
1166
  /* 843 */ "MOVSX_rr_8\0"
1167
  /* 854 */ "G_FMA\0"
1168
  /* 860 */ "G_STRICT_FMA\0"
1169
  /* 873 */ "LDB\0"
1170
  /* 877 */ "STB\0"
1171
  /* 881 */ "G_FSUB\0"
1172
  /* 888 */ "G_STRICT_FSUB\0"
1173
  /* 902 */ "G_ATOMICRMW_FSUB\0"
1174
  /* 919 */ "G_SUB\0"
1175
  /* 925 */ "G_ATOMICRMW_SUB\0"
1176
  /* 941 */ "LD_IND_B\0"
1177
  /* 950 */ "LD_ABS_B\0"
1178
  /* 959 */ "G_INTRINSIC\0"
1179
  /* 971 */ "G_FPTRUNC\0"
1180
  /* 981 */ "G_INTRINSIC_TRUNC\0"
1181
  /* 999 */ "G_TRUNC\0"
1182
  /* 1007 */ "G_BUILD_VECTOR_TRUNC\0"
1183
  /* 1028 */ "G_DYN_STACKALLOC\0"
1184
  /* 1045 */ "G_FMAD\0"
1185
  /* 1052 */ "G_INDEXED_SEXTLOAD\0"
1186
  /* 1071 */ "G_SEXTLOAD\0"
1187
  /* 1082 */ "G_INDEXED_ZEXTLOAD\0"
1188
  /* 1101 */ "G_ZEXTLOAD\0"
1189
  /* 1112 */ "G_INDEXED_LOAD\0"
1190
  /* 1127 */ "G_LOAD\0"
1191
  /* 1134 */ "G_VECREDUCE_FADD\0"
1192
  /* 1151 */ "G_FADD\0"
1193
  /* 1158 */ "G_VECREDUCE_SEQ_FADD\0"
1194
  /* 1179 */ "G_STRICT_FADD\0"
1195
  /* 1193 */ "G_ATOMICRMW_FADD\0"
1196
  /* 1210 */ "G_VECREDUCE_ADD\0"
1197
  /* 1226 */ "G_ADD\0"
1198
  /* 1232 */ "G_PTR_ADD\0"
1199
  /* 1242 */ "G_ATOMICRMW_ADD\0"
1200
  /* 1258 */ "XFADDD\0"
1201
  /* 1265 */ "XADDD\0"
1202
  /* 1271 */ "LDD\0"
1203
  /* 1275 */ "XFANDD\0"
1204
  /* 1282 */ "XANDD\0"
1205
  /* 1288 */ "CMPXCHGD\0"
1206
  /* 1297 */ "G_ATOMICRMW_NAND\0"
1207
  /* 1314 */ "G_VECREDUCE_AND\0"
1208
  /* 1330 */ "G_AND\0"
1209
  /* 1336 */ "G_ATOMICRMW_AND\0"
1210
  /* 1352 */ "LIFETIME_END\0"
1211
  /* 1365 */ "G_BRCOND\0"
1212
  /* 1374 */ "G_LLROUND\0"
1213
  /* 1384 */ "G_LROUND\0"
1214
  /* 1393 */ "G_INTRINSIC_ROUND\0"
1215
  /* 1411 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
1216
  /* 1437 */ "LOAD_STACK_GUARD\0"
1217
  /* 1454 */ "XFORD\0"
1218
  /* 1460 */ "XFXORD\0"
1219
  /* 1467 */ "XXORD\0"
1220
  /* 1473 */ "STD\0"
1221
  /* 1477 */ "PSEUDO_PROBE\0"
1222
  /* 1490 */ "G_SSUBE\0"
1223
  /* 1498 */ "G_USUBE\0"
1224
  /* 1506 */ "G_FENCE\0"
1225
  /* 1514 */ "ARITH_FENCE\0"
1226
  /* 1526 */ "REG_SEQUENCE\0"
1227
  /* 1539 */ "G_SADDE\0"
1228
  /* 1547 */ "G_UADDE\0"
1229
  /* 1555 */ "G_GET_FPMODE\0"
1230
  /* 1568 */ "G_RESET_FPMODE\0"
1231
  /* 1583 */ "G_SET_FPMODE\0"
1232
  /* 1596 */ "G_FMINNUM_IEEE\0"
1233
  /* 1611 */ "G_FMAXNUM_IEEE\0"
1234
  /* 1626 */ "G_JUMP_TABLE\0"
1235
  /* 1639 */ "BUNDLE\0"
1236
  /* 1646 */ "G_MEMCPY_INLINE\0"
1237
  /* 1662 */ "LOCAL_ESCAPE\0"
1238
  /* 1675 */ "G_STACKRESTORE\0"
1239
  /* 1690 */ "G_INDEXED_STORE\0"
1240
  /* 1706 */ "G_STORE\0"
1241
  /* 1714 */ "G_BITREVERSE\0"
1242
  /* 1727 */ "DBG_VALUE\0"
1243
  /* 1737 */ "G_GLOBAL_VALUE\0"
1244
  /* 1752 */ "G_STACKSAVE\0"
1245
  /* 1764 */ "G_MEMMOVE\0"
1246
  /* 1774 */ "G_FREEZE\0"
1247
  /* 1783 */ "G_FCANONICALIZE\0"
1248
  /* 1799 */ "G_CTLZ_ZERO_UNDEF\0"
1249
  /* 1817 */ "G_CTTZ_ZERO_UNDEF\0"
1250
  /* 1835 */ "G_IMPLICIT_DEF\0"
1251
  /* 1850 */ "DBG_INSTR_REF\0"
1252
  /* 1864 */ "G_FNEG\0"
1253
  /* 1871 */ "EXTRACT_SUBREG\0"
1254
  /* 1886 */ "INSERT_SUBREG\0"
1255
  /* 1900 */ "G_SEXT_INREG\0"
1256
  /* 1913 */ "SUBREG_TO_REG\0"
1257
  /* 1927 */ "G_ATOMIC_CMPXCHG\0"
1258
  /* 1944 */ "G_ATOMICRMW_XCHG\0"
1259
  /* 1961 */ "G_FLOG\0"
1260
  /* 1968 */ "G_VAARG\0"
1261
  /* 1976 */ "PREALLOCATED_ARG\0"
1262
  /* 1993 */ "G_PREFETCH\0"
1263
  /* 2004 */ "LDH\0"
1264
  /* 2008 */ "G_SMULH\0"
1265
  /* 2016 */ "G_UMULH\0"
1266
  /* 2024 */ "STH\0"
1267
  /* 2028 */ "LD_IND_H\0"
1268
  /* 2037 */ "LD_ABS_H\0"
1269
  /* 2046 */ "DBG_PHI\0"
1270
  /* 2054 */ "G_FPTOSI\0"
1271
  /* 2063 */ "G_FPTOUI\0"
1272
  /* 2072 */ "G_FPOWI\0"
1273
  /* 2080 */ "G_PTRMASK\0"
1274
  /* 2090 */ "JAL\0"
1275
  /* 2094 */ "GC_LABEL\0"
1276
  /* 2103 */ "DBG_LABEL\0"
1277
  /* 2113 */ "EH_LABEL\0"
1278
  /* 2122 */ "ANNOTATION_LABEL\0"
1279
  /* 2139 */ "ICALL_BRANCH_FUNNEL\0"
1280
  /* 2159 */ "G_FSHL\0"
1281
  /* 2166 */ "G_SHL\0"
1282
  /* 2172 */ "G_FCEIL\0"
1283
  /* 2180 */ "PATCHABLE_TAIL_CALL\0"
1284
  /* 2200 */ "PATCHABLE_TYPED_EVENT_CALL\0"
1285
  /* 2227 */ "PATCHABLE_EVENT_CALL\0"
1286
  /* 2248 */ "FENTRY_CALL\0"
1287
  /* 2260 */ "KILL\0"
1288
  /* 2265 */ "G_CONSTANT_POOL\0"
1289
  /* 2281 */ "JMPL\0"
1290
  /* 2286 */ "G_ROTL\0"
1291
  /* 2293 */ "G_VECREDUCE_FMUL\0"
1292
  /* 2310 */ "G_FMUL\0"
1293
  /* 2317 */ "G_VECREDUCE_SEQ_FMUL\0"
1294
  /* 2338 */ "G_STRICT_FMUL\0"
1295
  /* 2352 */ "G_VECREDUCE_MUL\0"
1296
  /* 2368 */ "G_MUL\0"
1297
  /* 2374 */ "G_FREM\0"
1298
  /* 2381 */ "G_STRICT_FREM\0"
1299
  /* 2395 */ "G_SREM\0"
1300
  /* 2402 */ "G_UREM\0"
1301
  /* 2409 */ "G_SDIVREM\0"
1302
  /* 2419 */ "G_UDIVREM\0"
1303
  /* 2429 */ "INLINEASM\0"
1304
  /* 2439 */ "G_VECREDUCE_FMINIMUM\0"
1305
  /* 2460 */ "G_FMINIMUM\0"
1306
  /* 2471 */ "G_VECREDUCE_FMAXIMUM\0"
1307
  /* 2492 */ "G_FMAXIMUM\0"
1308
  /* 2503 */ "G_FMINNUM\0"
1309
  /* 2513 */ "G_FMAXNUM\0"
1310
  /* 2523 */ "G_INTRINSIC_ROUNDEVEN\0"
1311
  /* 2545 */ "G_ASSERT_ALIGN\0"
1312
  /* 2560 */ "G_FCOPYSIGN\0"
1313
  /* 2572 */ "G_VECREDUCE_FMIN\0"
1314
  /* 2589 */ "G_ATOMICRMW_FMIN\0"
1315
  /* 2606 */ "G_VECREDUCE_SMIN\0"
1316
  /* 2623 */ "G_SMIN\0"
1317
  /* 2630 */ "G_VECREDUCE_UMIN\0"
1318
  /* 2647 */ "G_UMIN\0"
1319
  /* 2654 */ "G_ATOMICRMW_UMIN\0"
1320
  /* 2671 */ "G_ATOMICRMW_MIN\0"
1321
  /* 2687 */ "G_FSIN\0"
1322
  /* 2694 */ "CFI_INSTRUCTION\0"
1323
  /* 2710 */ "ADJCALLSTACKDOWN\0"
1324
  /* 2727 */ "G_SSUBO\0"
1325
  /* 2735 */ "G_USUBO\0"
1326
  /* 2743 */ "G_SADDO\0"
1327
  /* 2751 */ "G_UADDO\0"
1328
  /* 2759 */ "JUMP_TABLE_DEBUG_INFO\0"
1329
  /* 2781 */ "G_SMULO\0"
1330
  /* 2789 */ "G_UMULO\0"
1331
  /* 2797 */ "G_BZERO\0"
1332
  /* 2805 */ "STACKMAP\0"
1333
  /* 2814 */ "G_ATOMICRMW_UDEC_WRAP\0"
1334
  /* 2836 */ "G_ATOMICRMW_UINC_WRAP\0"
1335
  /* 2858 */ "G_BSWAP\0"
1336
  /* 2866 */ "G_SITOFP\0"
1337
  /* 2875 */ "G_UITOFP\0"
1338
  /* 2884 */ "G_FCMP\0"
1339
  /* 2891 */ "G_ICMP\0"
1340
  /* 2898 */ "JMP\0"
1341
  /* 2902 */ "NOP\0"
1342
  /* 2906 */ "G_CTPOP\0"
1343
  /* 2914 */ "PATCHABLE_OP\0"
1344
  /* 2927 */ "FAULTING_OP\0"
1345
  /* 2939 */ "ADJCALLSTACKUP\0"
1346
  /* 2954 */ "PREALLOCATED_SETUP\0"
1347
  /* 2973 */ "G_FLDEXP\0"
1348
  /* 2982 */ "G_STRICT_FLDEXP\0"
1349
  /* 2998 */ "G_FEXP\0"
1350
  /* 3005 */ "G_FFREXP\0"
1351
  /* 3014 */ "G_BR\0"
1352
  /* 3019 */ "INLINEASM_BR\0"
1353
  /* 3032 */ "G_BLOCK_ADDR\0"
1354
  /* 3045 */ "MEMBARRIER\0"
1355
  /* 3056 */ "G_CONSTANT_FOLD_BARRIER\0"
1356
  /* 3080 */ "PATCHABLE_FUNCTION_ENTER\0"
1357
  /* 3105 */ "G_READCYCLECOUNTER\0"
1358
  /* 3124 */ "G_READ_REGISTER\0"
1359
  /* 3140 */ "G_WRITE_REGISTER\0"
1360
  /* 3157 */ "G_ASHR\0"
1361
  /* 3164 */ "G_FSHR\0"
1362
  /* 3171 */ "G_LSHR\0"
1363
  /* 3178 */ "G_FFLOOR\0"
1364
  /* 3187 */ "G_BUILD_VECTOR\0"
1365
  /* 3202 */ "G_SHUFFLE_VECTOR\0"
1366
  /* 3219 */ "G_VECREDUCE_XOR\0"
1367
  /* 3235 */ "G_XOR\0"
1368
  /* 3241 */ "G_ATOMICRMW_XOR\0"
1369
  /* 3257 */ "G_VECREDUCE_OR\0"
1370
  /* 3272 */ "G_OR\0"
1371
  /* 3277 */ "G_ATOMICRMW_OR\0"
1372
  /* 3292 */ "G_ROTR\0"
1373
  /* 3299 */ "G_INTTOPTR\0"
1374
  /* 3310 */ "G_FABS\0"
1375
  /* 3317 */ "G_ABS\0"
1376
  /* 3323 */ "G_UNMERGE_VALUES\0"
1377
  /* 3340 */ "G_MERGE_VALUES\0"
1378
  /* 3355 */ "G_FCOS\0"
1379
  /* 3362 */ "G_CONCAT_VECTORS\0"
1380
  /* 3379 */ "COPY_TO_REGCLASS\0"
1381
  /* 3396 */ "G_IS_FPCLASS\0"
1382
  /* 3409 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
1383
  /* 3439 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
1384
  /* 3466 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
1385
  /* 3504 */ "G_SSUBSAT\0"
1386
  /* 3514 */ "G_USUBSAT\0"
1387
  /* 3524 */ "G_SADDSAT\0"
1388
  /* 3534 */ "G_UADDSAT\0"
1389
  /* 3544 */ "G_SSHLSAT\0"
1390
  /* 3554 */ "G_USHLSAT\0"
1391
  /* 3564 */ "G_SMULFIXSAT\0"
1392
  /* 3577 */ "G_UMULFIXSAT\0"
1393
  /* 3590 */ "G_SDIVFIXSAT\0"
1394
  /* 3603 */ "G_UDIVFIXSAT\0"
1395
  /* 3616 */ "G_EXTRACT\0"
1396
  /* 3626 */ "G_SELECT\0"
1397
  /* 3635 */ "G_BRINDIRECT\0"
1398
  /* 3648 */ "PATCHABLE_RET\0"
1399
  /* 3662 */ "G_MEMSET\0"
1400
  /* 3671 */ "CORE_SHIFT\0"
1401
  /* 3682 */ "PATCHABLE_FUNCTION_EXIT\0"
1402
  /* 3706 */ "G_BRJT\0"
1403
  /* 3713 */ "G_EXTRACT_VECTOR_ELT\0"
1404
  /* 3734 */ "G_INSERT_VECTOR_ELT\0"
1405
  /* 3754 */ "G_FCONSTANT\0"
1406
  /* 3766 */ "G_CONSTANT\0"
1407
  /* 3777 */ "G_INTRINSIC_CONVERGENT\0"
1408
  /* 3800 */ "STATEPOINT\0"
1409
  /* 3811 */ "PATCHPOINT\0"
1410
  /* 3822 */ "G_PTRTOINT\0"
1411
  /* 3833 */ "G_FRINT\0"
1412
  /* 3841 */ "G_INTRINSIC_LRINT\0"
1413
  /* 3859 */ "G_FNEARBYINT\0"
1414
  /* 3872 */ "G_VASTART\0"
1415
  /* 3882 */ "LIFETIME_START\0"
1416
  /* 3897 */ "G_INVOKE_REGION_START\0"
1417
  /* 3919 */ "G_INSERT\0"
1418
  /* 3928 */ "G_FSQRT\0"
1419
  /* 3936 */ "G_STRICT_FSQRT\0"
1420
  /* 3951 */ "G_BITCAST\0"
1421
  /* 3961 */ "G_ADDRSPACE_CAST\0"
1422
  /* 3978 */ "DBG_VALUE_LIST\0"
1423
  /* 3993 */ "CORE_ST\0"
1424
  /* 4001 */ "G_FPEXT\0"
1425
  /* 4009 */ "G_SEXT\0"
1426
  /* 4016 */ "G_ASSERT_SEXT\0"
1427
  /* 4030 */ "G_ANYEXT\0"
1428
  /* 4039 */ "G_ZEXT\0"
1429
  /* 4046 */ "G_ASSERT_ZEXT\0"
1430
  /* 4060 */ "G_FDIV\0"
1431
  /* 4067 */ "G_STRICT_FDIV\0"
1432
  /* 4081 */ "G_SDIV\0"
1433
  /* 4088 */ "G_UDIV\0"
1434
  /* 4095 */ "G_GET_FPENV\0"
1435
  /* 4107 */ "G_RESET_FPENV\0"
1436
  /* 4121 */ "G_SET_FPENV\0"
1437
  /* 4133 */ "XADDW\0"
1438
  /* 4139 */ "LDW\0"
1439
  /* 4143 */ "G_FPOW\0"
1440
  /* 4150 */ "STW\0"
1441
  /* 4154 */ "LD_IND_W\0"
1442
  /* 4163 */ "LD_ABS_W\0"
1443
  /* 4172 */ "G_VECREDUCE_FMAX\0"
1444
  /* 4189 */ "G_ATOMICRMW_FMAX\0"
1445
  /* 4206 */ "G_VECREDUCE_SMAX\0"
1446
  /* 4223 */ "G_SMAX\0"
1447
  /* 4230 */ "G_VECREDUCE_UMAX\0"
1448
  /* 4247 */ "G_UMAX\0"
1449
  /* 4254 */ "G_ATOMICRMW_UMAX\0"
1450
  /* 4271 */ "G_ATOMICRMW_MAX\0"
1451
  /* 4287 */ "G_FRAME_INDEX\0"
1452
  /* 4301 */ "G_SBFX\0"
1453
  /* 4308 */ "G_UBFX\0"
1454
  /* 4315 */ "G_SMULFIX\0"
1455
  /* 4325 */ "G_UMULFIX\0"
1456
  /* 4335 */ "G_SDIVFIX\0"
1457
  /* 4345 */ "G_UDIVFIX\0"
1458
  /* 4355 */ "JALX\0"
1459
  /* 4360 */ "LDBSX\0"
1460
  /* 4366 */ "LDHSX\0"
1461
  /* 4372 */ "LDWSX\0"
1462
  /* 4378 */ "G_MEMCPY\0"
1463
  /* 4387 */ "COPY\0"
1464
  /* 4392 */ "G_CTLZ\0"
1465
  /* 4399 */ "G_CTTZ\0"
1466
  /* 4406 */ "Select_Ri\0"
1467
  /* 4416 */ "SRA_ri\0"
1468
  /* 4423 */ "SUB_ri\0"
1469
  /* 4430 */ "ADD_ri\0"
1470
  /* 4437 */ "AND_ri\0"
1471
  /* 4444 */ "SMOD_ri\0"
1472
  /* 4452 */ "JSGE_ri\0"
1473
  /* 4460 */ "JUGE_ri\0"
1474
  /* 4468 */ "JSLE_ri\0"
1475
  /* 4476 */ "JULE_ri\0"
1476
  /* 4484 */ "JNE_ri\0"
1477
  /* 4491 */ "FI_ri\0"
1478
  /* 4497 */ "SLL_ri\0"
1479
  /* 4504 */ "SRL_ri\0"
1480
  /* 4511 */ "MUL_ri\0"
1481
  /* 4518 */ "JEQ_ri\0"
1482
  /* 4525 */ "XOR_ri\0"
1483
  /* 4532 */ "JSET_ri\0"
1484
  /* 4540 */ "JSGT_ri\0"
1485
  /* 4548 */ "JUGT_ri\0"
1486
  /* 4556 */ "JSLT_ri\0"
1487
  /* 4564 */ "JULT_ri\0"
1488
  /* 4572 */ "SDIV_ri\0"
1489
  /* 4580 */ "MOV_ri\0"
1490
  /* 4587 */ "STB_imm\0"
1491
  /* 4595 */ "STD_imm\0"
1492
  /* 4603 */ "STH_imm\0"
1493
  /* 4611 */ "STW_imm\0"
1494
  /* 4619 */ "LD_pseudo\0"
1495
  /* 4629 */ "SRA_rr\0"
1496
  /* 4636 */ "SUB_rr\0"
1497
  /* 4643 */ "ADD_rr\0"
1498
  /* 4650 */ "AND_rr\0"
1499
  /* 4657 */ "SMOD_rr\0"
1500
  /* 4665 */ "JSGE_rr\0"
1501
  /* 4673 */ "JUGE_rr\0"
1502
  /* 4681 */ "JSLE_rr\0"
1503
  /* 4689 */ "JULE_rr\0"
1504
  /* 4697 */ "JNE_rr\0"
1505
  /* 4704 */ "SLL_rr\0"
1506
  /* 4711 */ "SRL_rr\0"
1507
  /* 4718 */ "MUL_rr\0"
1508
  /* 4725 */ "JEQ_rr\0"
1509
  /* 4732 */ "XOR_rr\0"
1510
  /* 4739 */ "JSET_rr\0"
1511
  /* 4747 */ "JSGT_rr\0"
1512
  /* 4755 */ "JUGT_rr\0"
1513
  /* 4763 */ "JSLT_rr\0"
1514
  /* 4771 */ "JULT_rr\0"
1515
  /* 4779 */ "SDIV_rr\0"
1516
  /* 4787 */ "MOV_rr\0"
1517
  /* 4794 */ "Select\0"
1518
};
1519
#ifdef __GNUC__
1520
#pragma GCC diagnostic pop
1521
#endif
1522
1523
extern const unsigned BPFInstrNameIndices[] = {
1524
    2050U, 2429U, 3019U, 2694U, 2113U, 2094U, 2122U, 2260U, 
1525
    1871U, 1886U, 1837U, 1913U, 3379U, 1727U, 3978U, 1850U, 
1526
    2046U, 2103U, 1526U, 4387U, 1639U, 3882U, 1352U, 1477U, 
1527
    1514U, 2805U, 2248U, 3811U, 1437U, 2954U, 1976U, 3800U, 
1528
    1662U, 2927U, 2914U, 3080U, 3648U, 3682U, 2180U, 2227U, 
1529
    2200U, 2139U, 3045U, 2759U, 4016U, 4046U, 2545U, 1226U, 
1530
    919U, 2368U, 4081U, 4088U, 2395U, 2402U, 2409U, 2419U, 
1531
    1330U, 3272U, 3235U, 1835U, 2048U, 4287U, 1737U, 2265U, 
1532
    3616U, 3323U, 3919U, 3340U, 3187U, 1007U, 3362U, 3822U, 
1533
    3299U, 3951U, 1774U, 3056U, 1411U, 981U, 1393U, 3841U, 
1534
    2523U, 3105U, 1127U, 1071U, 1101U, 1112U, 1052U, 1082U, 
1535
    1706U, 1690U, 3409U, 1927U, 1944U, 1242U, 925U, 1336U, 
1536
    1297U, 3277U, 3241U, 4271U, 2671U, 4254U, 2654U, 1193U, 
1537
    902U, 4189U, 2589U, 2836U, 2814U, 1506U, 1993U, 1365U, 
1538
    3635U, 3897U, 959U, 3439U, 3777U, 3466U, 4030U, 999U, 
1539
    3766U, 3754U, 3872U, 1968U, 4009U, 1900U, 4039U, 2166U, 
1540
    3171U, 3157U, 2159U, 3164U, 3292U, 2286U, 2891U, 2884U, 
1541
    3626U, 2751U, 1547U, 2735U, 1498U, 2743U, 1539U, 2727U, 
1542
    1490U, 2789U, 2781U, 2016U, 2008U, 3534U, 3524U, 3514U, 
1543
    3504U, 3554U, 3544U, 4315U, 4325U, 3564U, 3577U, 4335U, 
1544
    4345U, 3590U, 3603U, 1151U, 881U, 2310U, 854U, 1045U, 
1545
    4060U, 2374U, 4143U, 2072U, 2998U, 693U, 9U, 1961U, 
1546
    685U, 0U, 2973U, 3005U, 1864U, 4001U, 971U, 2054U, 
1547
    2063U, 2866U, 2875U, 3310U, 2560U, 3396U, 1783U, 2503U, 
1548
    2513U, 1596U, 1611U, 2460U, 2492U, 4095U, 4121U, 4107U, 
1549
    1555U, 1583U, 1568U, 1232U, 2080U, 2623U, 4223U, 2647U, 
1550
    4247U, 3317U, 1384U, 1374U, 3014U, 3706U, 3734U, 3713U, 
1551
    3202U, 4399U, 1817U, 4392U, 1799U, 2906U, 2858U, 1714U, 
1552
    2172U, 3355U, 2687U, 3928U, 3178U, 3833U, 3859U, 3961U, 
1553
    3032U, 1626U, 1028U, 1752U, 1675U, 1179U, 888U, 2338U, 
1554
    4067U, 2381U, 860U, 3936U, 2982U, 3124U, 3140U, 4378U, 
1555
    1646U, 1764U, 3662U, 2797U, 1158U, 2317U, 1134U, 2293U, 
1556
    4172U, 2572U, 2471U, 2439U, 1210U, 2352U, 1314U, 3257U, 
1557
    3219U, 4206U, 2606U, 4230U, 2630U, 4301U, 4308U, 2710U, 
1558
    2939U, 4491U, 4380U, 4794U, 675U, 755U, 168U, 4406U, 
1559
    188U, 739U, 152U, 4430U, 221U, 4643U, 452U, 4437U, 
1560
    231U, 4650U, 462U, 784U, 40U, 711U, 794U, 62U, 
1561
    721U, 1288U, 110U, 30U, 701U, 3671U, 3993U, 4573U, 
1562
    412U, 4780U, 643U, 2090U, 4355U, 4518U, 336U, 4725U, 
1563
    567U, 2898U, 2281U, 4484U, 296U, 4697U, 527U, 4532U, 
1564
    356U, 4739U, 587U, 4452U, 252U, 4665U, 483U, 4540U, 
1565
    367U, 4747U, 598U, 4468U, 274U, 4681U, 505U, 4556U, 
1566
    389U, 4763U, 620U, 4460U, 263U, 4673U, 494U, 4548U, 
1567
    378U, 4755U, 609U, 4476U, 285U, 4689U, 516U, 4564U, 
1568
    400U, 4771U, 631U, 873U, 18U, 4360U, 1271U, 2004U, 
1569
    50U, 4366U, 4139U, 87U, 4372U, 950U, 2037U, 4163U, 
1570
    941U, 2028U, 4154U, 775U, 4619U, 789U, 45U, 716U, 
1571
    4445U, 242U, 4658U, 473U, 817U, 663U, 802U, 829U, 
1572
    843U, 729U, 4580U, 422U, 4787U, 653U, 4511U, 326U, 
1573
    4718U, 557U, 181U, 768U, 2902U, 4526U, 347U, 4733U, 
1574
    578U, 3658U, 4572U, 411U, 4779U, 642U, 4497U, 306U, 
1575
    4704U, 537U, 4444U, 241U, 4657U, 472U, 4416U, 201U, 
1576
    4629U, 432U, 4504U, 316U, 4711U, 547U, 877U, 24U, 
1577
    4587U, 1473U, 4595U, 2024U, 56U, 4603U, 4150U, 146U, 
1578
    4611U, 4423U, 211U, 4636U, 442U, 1265U, 4133U, 79U, 
1579
    1282U, 102U, 1291U, 113U, 1258U, 70U, 1275U, 93U, 
1580
    1454U, 121U, 1460U, 129U, 1462U, 131U, 4525U, 346U, 
1581
    4732U, 577U, 1467U, 138U, 
1582
};
1583
1584
5
static inline void InitBPFMCInstrInfo(MCInstrInfo *II) {
1585
5
  II->InitMCInstrInfo(BPFDescs.Insts, BPFInstrNameIndices, BPFInstrNameData, nullptr, nullptr, 460);
1586
5
}
1587
1588
} // end namespace llvm
1589
#endif // GET_INSTRINFO_MC_DESC
1590
1591
#ifdef GET_INSTRINFO_HEADER
1592
#undef GET_INSTRINFO_HEADER
1593
namespace llvm {
1594
struct BPFGenInstrInfo : public TargetInstrInfo {
1595
  explicit BPFGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1596
  ~BPFGenInstrInfo() override = default;
1597
1598
};
1599
} // end namespace llvm
1600
#endif // GET_INSTRINFO_HEADER
1601
1602
#ifdef GET_INSTRINFO_HELPER_DECLS
1603
#undef GET_INSTRINFO_HELPER_DECLS
1604
1605
1606
#endif // GET_INSTRINFO_HELPER_DECLS
1607
1608
#ifdef GET_INSTRINFO_HELPERS
1609
#undef GET_INSTRINFO_HELPERS
1610
1611
#endif // GET_INSTRINFO_HELPERS
1612
1613
#ifdef GET_INSTRINFO_CTOR_DTOR
1614
#undef GET_INSTRINFO_CTOR_DTOR
1615
namespace llvm {
1616
extern const BPFInstrTable BPFDescs;
1617
extern const unsigned BPFInstrNameIndices[];
1618
extern const char BPFInstrNameData[];
1619
BPFGenInstrInfo::BPFGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1620
2
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1621
2
  InitMCInstrInfo(BPFDescs.Insts, BPFInstrNameIndices, BPFInstrNameData, nullptr, nullptr, 460);
1622
2
}
1623
} // end namespace llvm
1624
#endif // GET_INSTRINFO_CTOR_DTOR
1625
1626
#ifdef GET_INSTRINFO_OPERAND_ENUM
1627
#undef GET_INSTRINFO_OPERAND_ENUM
1628
namespace llvm {
1629
namespace BPF {
1630
namespace OpName {
1631
enum {
1632
  OPERAND_LAST
1633
};
1634
} // end namespace OpName
1635
} // end namespace BPF
1636
} // end namespace llvm
1637
#endif //GET_INSTRINFO_OPERAND_ENUM
1638
1639
#ifdef GET_INSTRINFO_NAMED_OPS
1640
#undef GET_INSTRINFO_NAMED_OPS
1641
namespace llvm {
1642
namespace BPF {
1643
LLVM_READONLY
1644
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
1645
  return -1;
1646
}
1647
} // end namespace BPF
1648
} // end namespace llvm
1649
#endif //GET_INSTRINFO_NAMED_OPS
1650
1651
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
1652
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
1653
namespace llvm {
1654
namespace BPF {
1655
namespace OpTypes {
1656
enum OperandType {
1657
  MEMri = 0,
1658
  brtarget = 1,
1659
  calltarget = 2,
1660
  f32imm = 3,
1661
  f64imm = 4,
1662
  gpr_or_imm = 5,
1663
  i1imm = 6,
1664
  i8imm = 7,
1665
  i16imm = 8,
1666
  i32imm = 9,
1667
  i64imm = 10,
1668
  ptype0 = 11,
1669
  ptype1 = 12,
1670
  ptype2 = 13,
1671
  ptype3 = 14,
1672
  ptype4 = 15,
1673
  ptype5 = 16,
1674
  s16imm = 17,
1675
  type0 = 18,
1676
  type1 = 19,
1677
  type2 = 20,
1678
  type3 = 21,
1679
  type4 = 22,
1680
  type5 = 23,
1681
  u64imm = 24,
1682
  untyped_imm_0 = 25,
1683
  GPR = 26,
1684
  GPR32 = 27,
1685
  OPERAND_TYPE_LIST_END
1686
};
1687
} // end namespace OpTypes
1688
} // end namespace BPF
1689
} // end namespace llvm
1690
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
1691
1692
#ifdef GET_INSTRINFO_OPERAND_TYPE
1693
#undef GET_INSTRINFO_OPERAND_TYPE
1694
namespace llvm {
1695
namespace BPF {
1696
LLVM_READONLY
1697
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
1698
  static const uint16_t Offsets[] = {
1699
    /* PHI */
1700
    0,
1701
    /* INLINEASM */
1702
    1,
1703
    /* INLINEASM_BR */
1704
    1,
1705
    /* CFI_INSTRUCTION */
1706
    1,
1707
    /* EH_LABEL */
1708
    2,
1709
    /* GC_LABEL */
1710
    3,
1711
    /* ANNOTATION_LABEL */
1712
    4,
1713
    /* KILL */
1714
    5,
1715
    /* EXTRACT_SUBREG */
1716
    5,
1717
    /* INSERT_SUBREG */
1718
    8,
1719
    /* IMPLICIT_DEF */
1720
    12,
1721
    /* SUBREG_TO_REG */
1722
    13,
1723
    /* COPY_TO_REGCLASS */
1724
    17,
1725
    /* DBG_VALUE */
1726
    20,
1727
    /* DBG_VALUE_LIST */
1728
    20,
1729
    /* DBG_INSTR_REF */
1730
    20,
1731
    /* DBG_PHI */
1732
    20,
1733
    /* DBG_LABEL */
1734
    20,
1735
    /* REG_SEQUENCE */
1736
    21,
1737
    /* COPY */
1738
    23,
1739
    /* BUNDLE */
1740
    25,
1741
    /* LIFETIME_START */
1742
    25,
1743
    /* LIFETIME_END */
1744
    26,
1745
    /* PSEUDO_PROBE */
1746
    27,
1747
    /* ARITH_FENCE */
1748
    31,
1749
    /* STACKMAP */
1750
    33,
1751
    /* FENTRY_CALL */
1752
    35,
1753
    /* PATCHPOINT */
1754
    35,
1755
    /* LOAD_STACK_GUARD */
1756
    41,
1757
    /* PREALLOCATED_SETUP */
1758
    42,
1759
    /* PREALLOCATED_ARG */
1760
    43,
1761
    /* STATEPOINT */
1762
    46,
1763
    /* LOCAL_ESCAPE */
1764
    46,
1765
    /* FAULTING_OP */
1766
    48,
1767
    /* PATCHABLE_OP */
1768
    49,
1769
    /* PATCHABLE_FUNCTION_ENTER */
1770
    49,
1771
    /* PATCHABLE_RET */
1772
    49,
1773
    /* PATCHABLE_FUNCTION_EXIT */
1774
    49,
1775
    /* PATCHABLE_TAIL_CALL */
1776
    49,
1777
    /* PATCHABLE_EVENT_CALL */
1778
    49,
1779
    /* PATCHABLE_TYPED_EVENT_CALL */
1780
    51,
1781
    /* ICALL_BRANCH_FUNNEL */
1782
    54,
1783
    /* MEMBARRIER */
1784
    54,
1785
    /* JUMP_TABLE_DEBUG_INFO */
1786
    54,
1787
    /* G_ASSERT_SEXT */
1788
    55,
1789
    /* G_ASSERT_ZEXT */
1790
    58,
1791
    /* G_ASSERT_ALIGN */
1792
    61,
1793
    /* G_ADD */
1794
    64,
1795
    /* G_SUB */
1796
    67,
1797
    /* G_MUL */
1798
    70,
1799
    /* G_SDIV */
1800
    73,
1801
    /* G_UDIV */
1802
    76,
1803
    /* G_SREM */
1804
    79,
1805
    /* G_UREM */
1806
    82,
1807
    /* G_SDIVREM */
1808
    85,
1809
    /* G_UDIVREM */
1810
    89,
1811
    /* G_AND */
1812
    93,
1813
    /* G_OR */
1814
    96,
1815
    /* G_XOR */
1816
    99,
1817
    /* G_IMPLICIT_DEF */
1818
    102,
1819
    /* G_PHI */
1820
    103,
1821
    /* G_FRAME_INDEX */
1822
    104,
1823
    /* G_GLOBAL_VALUE */
1824
    106,
1825
    /* G_CONSTANT_POOL */
1826
    108,
1827
    /* G_EXTRACT */
1828
    110,
1829
    /* G_UNMERGE_VALUES */
1830
    113,
1831
    /* G_INSERT */
1832
    115,
1833
    /* G_MERGE_VALUES */
1834
    119,
1835
    /* G_BUILD_VECTOR */
1836
    121,
1837
    /* G_BUILD_VECTOR_TRUNC */
1838
    123,
1839
    /* G_CONCAT_VECTORS */
1840
    125,
1841
    /* G_PTRTOINT */
1842
    127,
1843
    /* G_INTTOPTR */
1844
    129,
1845
    /* G_BITCAST */
1846
    131,
1847
    /* G_FREEZE */
1848
    133,
1849
    /* G_CONSTANT_FOLD_BARRIER */
1850
    135,
1851
    /* G_INTRINSIC_FPTRUNC_ROUND */
1852
    137,
1853
    /* G_INTRINSIC_TRUNC */
1854
    140,
1855
    /* G_INTRINSIC_ROUND */
1856
    142,
1857
    /* G_INTRINSIC_LRINT */
1858
    144,
1859
    /* G_INTRINSIC_ROUNDEVEN */
1860
    146,
1861
    /* G_READCYCLECOUNTER */
1862
    148,
1863
    /* G_LOAD */
1864
    149,
1865
    /* G_SEXTLOAD */
1866
    151,
1867
    /* G_ZEXTLOAD */
1868
    153,
1869
    /* G_INDEXED_LOAD */
1870
    155,
1871
    /* G_INDEXED_SEXTLOAD */
1872
    160,
1873
    /* G_INDEXED_ZEXTLOAD */
1874
    165,
1875
    /* G_STORE */
1876
    170,
1877
    /* G_INDEXED_STORE */
1878
    172,
1879
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
1880
    177,
1881
    /* G_ATOMIC_CMPXCHG */
1882
    182,
1883
    /* G_ATOMICRMW_XCHG */
1884
    186,
1885
    /* G_ATOMICRMW_ADD */
1886
    189,
1887
    /* G_ATOMICRMW_SUB */
1888
    192,
1889
    /* G_ATOMICRMW_AND */
1890
    195,
1891
    /* G_ATOMICRMW_NAND */
1892
    198,
1893
    /* G_ATOMICRMW_OR */
1894
    201,
1895
    /* G_ATOMICRMW_XOR */
1896
    204,
1897
    /* G_ATOMICRMW_MAX */
1898
    207,
1899
    /* G_ATOMICRMW_MIN */
1900
    210,
1901
    /* G_ATOMICRMW_UMAX */
1902
    213,
1903
    /* G_ATOMICRMW_UMIN */
1904
    216,
1905
    /* G_ATOMICRMW_FADD */
1906
    219,
1907
    /* G_ATOMICRMW_FSUB */
1908
    222,
1909
    /* G_ATOMICRMW_FMAX */
1910
    225,
1911
    /* G_ATOMICRMW_FMIN */
1912
    228,
1913
    /* G_ATOMICRMW_UINC_WRAP */
1914
    231,
1915
    /* G_ATOMICRMW_UDEC_WRAP */
1916
    234,
1917
    /* G_FENCE */
1918
    237,
1919
    /* G_PREFETCH */
1920
    239,
1921
    /* G_BRCOND */
1922
    243,
1923
    /* G_BRINDIRECT */
1924
    245,
1925
    /* G_INVOKE_REGION_START */
1926
    246,
1927
    /* G_INTRINSIC */
1928
    246,
1929
    /* G_INTRINSIC_W_SIDE_EFFECTS */
1930
    247,
1931
    /* G_INTRINSIC_CONVERGENT */
1932
    248,
1933
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
1934
    249,
1935
    /* G_ANYEXT */
1936
    250,
1937
    /* G_TRUNC */
1938
    252,
1939
    /* G_CONSTANT */
1940
    254,
1941
    /* G_FCONSTANT */
1942
    256,
1943
    /* G_VASTART */
1944
    258,
1945
    /* G_VAARG */
1946
    259,
1947
    /* G_SEXT */
1948
    262,
1949
    /* G_SEXT_INREG */
1950
    264,
1951
    /* G_ZEXT */
1952
    267,
1953
    /* G_SHL */
1954
    269,
1955
    /* G_LSHR */
1956
    272,
1957
    /* G_ASHR */
1958
    275,
1959
    /* G_FSHL */
1960
    278,
1961
    /* G_FSHR */
1962
    282,
1963
    /* G_ROTR */
1964
    286,
1965
    /* G_ROTL */
1966
    289,
1967
    /* G_ICMP */
1968
    292,
1969
    /* G_FCMP */
1970
    296,
1971
    /* G_SELECT */
1972
    300,
1973
    /* G_UADDO */
1974
    304,
1975
    /* G_UADDE */
1976
    308,
1977
    /* G_USUBO */
1978
    313,
1979
    /* G_USUBE */
1980
    317,
1981
    /* G_SADDO */
1982
    322,
1983
    /* G_SADDE */
1984
    326,
1985
    /* G_SSUBO */
1986
    331,
1987
    /* G_SSUBE */
1988
    335,
1989
    /* G_UMULO */
1990
    340,
1991
    /* G_SMULO */
1992
    344,
1993
    /* G_UMULH */
1994
    348,
1995
    /* G_SMULH */
1996
    351,
1997
    /* G_UADDSAT */
1998
    354,
1999
    /* G_SADDSAT */
2000
    357,
2001
    /* G_USUBSAT */
2002
    360,
2003
    /* G_SSUBSAT */
2004
    363,
2005
    /* G_USHLSAT */
2006
    366,
2007
    /* G_SSHLSAT */
2008
    369,
2009
    /* G_SMULFIX */
2010
    372,
2011
    /* G_UMULFIX */
2012
    376,
2013
    /* G_SMULFIXSAT */
2014
    380,
2015
    /* G_UMULFIXSAT */
2016
    384,
2017
    /* G_SDIVFIX */
2018
    388,
2019
    /* G_UDIVFIX */
2020
    392,
2021
    /* G_SDIVFIXSAT */
2022
    396,
2023
    /* G_UDIVFIXSAT */
2024
    400,
2025
    /* G_FADD */
2026
    404,
2027
    /* G_FSUB */
2028
    407,
2029
    /* G_FMUL */
2030
    410,
2031
    /* G_FMA */
2032
    413,
2033
    /* G_FMAD */
2034
    417,
2035
    /* G_FDIV */
2036
    421,
2037
    /* G_FREM */
2038
    424,
2039
    /* G_FPOW */
2040
    427,
2041
    /* G_FPOWI */
2042
    430,
2043
    /* G_FEXP */
2044
    433,
2045
    /* G_FEXP2 */
2046
    435,
2047
    /* G_FEXP10 */
2048
    437,
2049
    /* G_FLOG */
2050
    439,
2051
    /* G_FLOG2 */
2052
    441,
2053
    /* G_FLOG10 */
2054
    443,
2055
    /* G_FLDEXP */
2056
    445,
2057
    /* G_FFREXP */
2058
    448,
2059
    /* G_FNEG */
2060
    451,
2061
    /* G_FPEXT */
2062
    453,
2063
    /* G_FPTRUNC */
2064
    455,
2065
    /* G_FPTOSI */
2066
    457,
2067
    /* G_FPTOUI */
2068
    459,
2069
    /* G_SITOFP */
2070
    461,
2071
    /* G_UITOFP */
2072
    463,
2073
    /* G_FABS */
2074
    465,
2075
    /* G_FCOPYSIGN */
2076
    467,
2077
    /* G_IS_FPCLASS */
2078
    470,
2079
    /* G_FCANONICALIZE */
2080
    473,
2081
    /* G_FMINNUM */
2082
    475,
2083
    /* G_FMAXNUM */
2084
    478,
2085
    /* G_FMINNUM_IEEE */
2086
    481,
2087
    /* G_FMAXNUM_IEEE */
2088
    484,
2089
    /* G_FMINIMUM */
2090
    487,
2091
    /* G_FMAXIMUM */
2092
    490,
2093
    /* G_GET_FPENV */
2094
    493,
2095
    /* G_SET_FPENV */
2096
    494,
2097
    /* G_RESET_FPENV */
2098
    495,
2099
    /* G_GET_FPMODE */
2100
    495,
2101
    /* G_SET_FPMODE */
2102
    496,
2103
    /* G_RESET_FPMODE */
2104
    497,
2105
    /* G_PTR_ADD */
2106
    497,
2107
    /* G_PTRMASK */
2108
    500,
2109
    /* G_SMIN */
2110
    503,
2111
    /* G_SMAX */
2112
    506,
2113
    /* G_UMIN */
2114
    509,
2115
    /* G_UMAX */
2116
    512,
2117
    /* G_ABS */
2118
    515,
2119
    /* G_LROUND */
2120
    517,
2121
    /* G_LLROUND */
2122
    519,
2123
    /* G_BR */
2124
    521,
2125
    /* G_BRJT */
2126
    522,
2127
    /* G_INSERT_VECTOR_ELT */
2128
    525,
2129
    /* G_EXTRACT_VECTOR_ELT */
2130
    529,
2131
    /* G_SHUFFLE_VECTOR */
2132
    532,
2133
    /* G_CTTZ */
2134
    536,
2135
    /* G_CTTZ_ZERO_UNDEF */
2136
    538,
2137
    /* G_CTLZ */
2138
    540,
2139
    /* G_CTLZ_ZERO_UNDEF */
2140
    542,
2141
    /* G_CTPOP */
2142
    544,
2143
    /* G_BSWAP */
2144
    546,
2145
    /* G_BITREVERSE */
2146
    548,
2147
    /* G_FCEIL */
2148
    550,
2149
    /* G_FCOS */
2150
    552,
2151
    /* G_FSIN */
2152
    554,
2153
    /* G_FSQRT */
2154
    556,
2155
    /* G_FFLOOR */
2156
    558,
2157
    /* G_FRINT */
2158
    560,
2159
    /* G_FNEARBYINT */
2160
    562,
2161
    /* G_ADDRSPACE_CAST */
2162
    564,
2163
    /* G_BLOCK_ADDR */
2164
    566,
2165
    /* G_JUMP_TABLE */
2166
    568,
2167
    /* G_DYN_STACKALLOC */
2168
    570,
2169
    /* G_STACKSAVE */
2170
    573,
2171
    /* G_STACKRESTORE */
2172
    574,
2173
    /* G_STRICT_FADD */
2174
    575,
2175
    /* G_STRICT_FSUB */
2176
    578,
2177
    /* G_STRICT_FMUL */
2178
    581,
2179
    /* G_STRICT_FDIV */
2180
    584,
2181
    /* G_STRICT_FREM */
2182
    587,
2183
    /* G_STRICT_FMA */
2184
    590,
2185
    /* G_STRICT_FSQRT */
2186
    594,
2187
    /* G_STRICT_FLDEXP */
2188
    596,
2189
    /* G_READ_REGISTER */
2190
    599,
2191
    /* G_WRITE_REGISTER */
2192
    601,
2193
    /* G_MEMCPY */
2194
    603,
2195
    /* G_MEMCPY_INLINE */
2196
    607,
2197
    /* G_MEMMOVE */
2198
    610,
2199
    /* G_MEMSET */
2200
    614,
2201
    /* G_BZERO */
2202
    618,
2203
    /* G_VECREDUCE_SEQ_FADD */
2204
    621,
2205
    /* G_VECREDUCE_SEQ_FMUL */
2206
    624,
2207
    /* G_VECREDUCE_FADD */
2208
    627,
2209
    /* G_VECREDUCE_FMUL */
2210
    629,
2211
    /* G_VECREDUCE_FMAX */
2212
    631,
2213
    /* G_VECREDUCE_FMIN */
2214
    633,
2215
    /* G_VECREDUCE_FMAXIMUM */
2216
    635,
2217
    /* G_VECREDUCE_FMINIMUM */
2218
    637,
2219
    /* G_VECREDUCE_ADD */
2220
    639,
2221
    /* G_VECREDUCE_MUL */
2222
    641,
2223
    /* G_VECREDUCE_AND */
2224
    643,
2225
    /* G_VECREDUCE_OR */
2226
    645,
2227
    /* G_VECREDUCE_XOR */
2228
    647,
2229
    /* G_VECREDUCE_SMAX */
2230
    649,
2231
    /* G_VECREDUCE_SMIN */
2232
    651,
2233
    /* G_VECREDUCE_UMAX */
2234
    653,
2235
    /* G_VECREDUCE_UMIN */
2236
    655,
2237
    /* G_SBFX */
2238
    657,
2239
    /* G_UBFX */
2240
    661,
2241
    /* ADJCALLSTACKDOWN */
2242
    665,
2243
    /* ADJCALLSTACKUP */
2244
    667,
2245
    /* FI_ri */
2246
    669,
2247
    /* MEMCPY */
2248
    672,
2249
    /* Select */
2250
    676,
2251
    /* Select_32 */
2252
    682,
2253
    /* Select_32_64 */
2254
    688,
2255
    /* Select_64_32 */
2256
    694,
2257
    /* Select_Ri */
2258
    700,
2259
    /* Select_Ri_32 */
2260
    706,
2261
    /* Select_Ri_32_64 */
2262
    712,
2263
    /* Select_Ri_64_32 */
2264
    718,
2265
    /* ADD_ri */
2266
    724,
2267
    /* ADD_ri_32 */
2268
    727,
2269
    /* ADD_rr */
2270
    730,
2271
    /* ADD_rr_32 */
2272
    733,
2273
    /* AND_ri */
2274
    736,
2275
    /* AND_ri_32 */
2276
    739,
2277
    /* AND_rr */
2278
    742,
2279
    /* AND_rr_32 */
2280
    745,
2281
    /* BE16 */
2282
    748,
2283
    /* BE32 */
2284
    750,
2285
    /* BE64 */
2286
    752,
2287
    /* BSWAP16 */
2288
    754,
2289
    /* BSWAP32 */
2290
    756,
2291
    /* BSWAP64 */
2292
    758,
2293
    /* CMPXCHGD */
2294
    760,
2295
    /* CMPXCHGW32 */
2296
    763,
2297
    /* CORE_LD32 */
2298
    766,
2299
    /* CORE_LD64 */
2300
    770,
2301
    /* CORE_SHIFT */
2302
    774,
2303
    /* CORE_ST */
2304
    778,
2305
    /* DIV_ri */
2306
    782,
2307
    /* DIV_ri_32 */
2308
    785,
2309
    /* DIV_rr */
2310
    788,
2311
    /* DIV_rr_32 */
2312
    791,
2313
    /* JAL */
2314
    794,
2315
    /* JALX */
2316
    795,
2317
    /* JEQ_ri */
2318
    796,
2319
    /* JEQ_ri_32 */
2320
    799,
2321
    /* JEQ_rr */
2322
    802,
2323
    /* JEQ_rr_32 */
2324
    805,
2325
    /* JMP */
2326
    808,
2327
    /* JMPL */
2328
    809,
2329
    /* JNE_ri */
2330
    810,
2331
    /* JNE_ri_32 */
2332
    813,
2333
    /* JNE_rr */
2334
    816,
2335
    /* JNE_rr_32 */
2336
    819,
2337
    /* JSET_ri */
2338
    822,
2339
    /* JSET_ri_32 */
2340
    825,
2341
    /* JSET_rr */
2342
    828,
2343
    /* JSET_rr_32 */
2344
    831,
2345
    /* JSGE_ri */
2346
    834,
2347
    /* JSGE_ri_32 */
2348
    837,
2349
    /* JSGE_rr */
2350
    840,
2351
    /* JSGE_rr_32 */
2352
    843,
2353
    /* JSGT_ri */
2354
    846,
2355
    /* JSGT_ri_32 */
2356
    849,
2357
    /* JSGT_rr */
2358
    852,
2359
    /* JSGT_rr_32 */
2360
    855,
2361
    /* JSLE_ri */
2362
    858,
2363
    /* JSLE_ri_32 */
2364
    861,
2365
    /* JSLE_rr */
2366
    864,
2367
    /* JSLE_rr_32 */
2368
    867,
2369
    /* JSLT_ri */
2370
    870,
2371
    /* JSLT_ri_32 */
2372
    873,
2373
    /* JSLT_rr */
2374
    876,
2375
    /* JSLT_rr_32 */
2376
    879,
2377
    /* JUGE_ri */
2378
    882,
2379
    /* JUGE_ri_32 */
2380
    885,
2381
    /* JUGE_rr */
2382
    888,
2383
    /* JUGE_rr_32 */
2384
    891,
2385
    /* JUGT_ri */
2386
    894,
2387
    /* JUGT_ri_32 */
2388
    897,
2389
    /* JUGT_rr */
2390
    900,
2391
    /* JUGT_rr_32 */
2392
    903,
2393
    /* JULE_ri */
2394
    906,
2395
    /* JULE_ri_32 */
2396
    909,
2397
    /* JULE_rr */
2398
    912,
2399
    /* JULE_rr_32 */
2400
    915,
2401
    /* JULT_ri */
2402
    918,
2403
    /* JULT_ri_32 */
2404
    921,
2405
    /* JULT_rr */
2406
    924,
2407
    /* JULT_rr_32 */
2408
    927,
2409
    /* LDB */
2410
    930,
2411
    /* LDB32 */
2412
    933,
2413
    /* LDBSX */
2414
    936,
2415
    /* LDD */
2416
    939,
2417
    /* LDH */
2418
    942,
2419
    /* LDH32 */
2420
    945,
2421
    /* LDHSX */
2422
    948,
2423
    /* LDW */
2424
    951,
2425
    /* LDW32 */
2426
    954,
2427
    /* LDWSX */
2428
    957,
2429
    /* LD_ABS_B */
2430
    960,
2431
    /* LD_ABS_H */
2432
    962,
2433
    /* LD_ABS_W */
2434
    964,
2435
    /* LD_IND_B */
2436
    966,
2437
    /* LD_IND_H */
2438
    968,
2439
    /* LD_IND_W */
2440
    970,
2441
    /* LD_imm64 */
2442
    972,
2443
    /* LD_pseudo */
2444
    974,
2445
    /* LE16 */
2446
    977,
2447
    /* LE32 */
2448
    979,
2449
    /* LE64 */
2450
    981,
2451
    /* MOD_ri */
2452
    983,
2453
    /* MOD_ri_32 */
2454
    986,
2455
    /* MOD_rr */
2456
    989,
2457
    /* MOD_rr_32 */
2458
    992,
2459
    /* MOVSX_rr_16 */
2460
    995,
2461
    /* MOVSX_rr_32 */
2462
    997,
2463
    /* MOVSX_rr_32_16 */
2464
    999,
2465
    /* MOVSX_rr_32_8 */
2466
    1001,
2467
    /* MOVSX_rr_8 */
2468
    1003,
2469
    /* MOV_32_64 */
2470
    1005,
2471
    /* MOV_ri */
2472
    1007,
2473
    /* MOV_ri_32 */
2474
    1009,
2475
    /* MOV_rr */
2476
    1011,
2477
    /* MOV_rr_32 */
2478
    1013,
2479
    /* MUL_ri */
2480
    1015,
2481
    /* MUL_ri_32 */
2482
    1018,
2483
    /* MUL_rr */
2484
    1021,
2485
    /* MUL_rr_32 */
2486
    1024,
2487
    /* NEG_32 */
2488
    1027,
2489
    /* NEG_64 */
2490
    1029,
2491
    /* NOP */
2492
    1031,
2493
    /* OR_ri */
2494
    1032,
2495
    /* OR_ri_32 */
2496
    1035,
2497
    /* OR_rr */
2498
    1038,
2499
    /* OR_rr_32 */
2500
    1041,
2501
    /* RET */
2502
    1044,
2503
    /* SDIV_ri */
2504
    1044,
2505
    /* SDIV_ri_32 */
2506
    1047,
2507
    /* SDIV_rr */
2508
    1050,
2509
    /* SDIV_rr_32 */
2510
    1053,
2511
    /* SLL_ri */
2512
    1056,
2513
    /* SLL_ri_32 */
2514
    1059,
2515
    /* SLL_rr */
2516
    1062,
2517
    /* SLL_rr_32 */
2518
    1065,
2519
    /* SMOD_ri */
2520
    1068,
2521
    /* SMOD_ri_32 */
2522
    1071,
2523
    /* SMOD_rr */
2524
    1074,
2525
    /* SMOD_rr_32 */
2526
    1077,
2527
    /* SRA_ri */
2528
    1080,
2529
    /* SRA_ri_32 */
2530
    1083,
2531
    /* SRA_rr */
2532
    1086,
2533
    /* SRA_rr_32 */
2534
    1089,
2535
    /* SRL_ri */
2536
    1092,
2537
    /* SRL_ri_32 */
2538
    1095,
2539
    /* SRL_rr */
2540
    1098,
2541
    /* SRL_rr_32 */
2542
    1101,
2543
    /* STB */
2544
    1104,
2545
    /* STB32 */
2546
    1107,
2547
    /* STB_imm */
2548
    1110,
2549
    /* STD */
2550
    1113,
2551
    /* STD_imm */
2552
    1116,
2553
    /* STH */
2554
    1119,
2555
    /* STH32 */
2556
    1122,
2557
    /* STH_imm */
2558
    1125,
2559
    /* STW */
2560
    1128,
2561
    /* STW32 */
2562
    1131,
2563
    /* STW_imm */
2564
    1134,
2565
    /* SUB_ri */
2566
    1137,
2567
    /* SUB_ri_32 */
2568
    1140,
2569
    /* SUB_rr */
2570
    1143,
2571
    /* SUB_rr_32 */
2572
    1146,
2573
    /* XADDD */
2574
    1149,
2575
    /* XADDW */
2576
    1153,
2577
    /* XADDW32 */
2578
    1157,
2579
    /* XANDD */
2580
    1161,
2581
    /* XANDW32 */
2582
    1165,
2583
    /* XCHGD */
2584
    1169,
2585
    /* XCHGW32 */
2586
    1173,
2587
    /* XFADDD */
2588
    1177,
2589
    /* XFADDW32 */
2590
    1181,
2591
    /* XFANDD */
2592
    1185,
2593
    /* XFANDW32 */
2594
    1189,
2595
    /* XFORD */
2596
    1193,
2597
    /* XFORW32 */
2598
    1197,
2599
    /* XFXORD */
2600
    1201,
2601
    /* XFXORW32 */
2602
    1205,
2603
    /* XORD */
2604
    1209,
2605
    /* XORW32 */
2606
    1213,
2607
    /* XOR_ri */
2608
    1217,
2609
    /* XOR_ri_32 */
2610
    1220,
2611
    /* XOR_rr */
2612
    1223,
2613
    /* XOR_rr_32 */
2614
    1226,
2615
    /* XXORD */
2616
    1229,
2617
    /* XXORW32 */
2618
    1233,
2619
  };
2620
2621
  using namespace OpTypes;
2622
  static const int8_t OpcodeOperandTypes[] = {
2623
    
2624
    /* PHI */
2625
    -1, 
2626
    /* INLINEASM */
2627
    /* INLINEASM_BR */
2628
    /* CFI_INSTRUCTION */
2629
    i32imm, 
2630
    /* EH_LABEL */
2631
    i32imm, 
2632
    /* GC_LABEL */
2633
    i32imm, 
2634
    /* ANNOTATION_LABEL */
2635
    i32imm, 
2636
    /* KILL */
2637
    /* EXTRACT_SUBREG */
2638
    -1, -1, i32imm, 
2639
    /* INSERT_SUBREG */
2640
    -1, -1, -1, i32imm, 
2641
    /* IMPLICIT_DEF */
2642
    -1, 
2643
    /* SUBREG_TO_REG */
2644
    -1, -1, -1, i32imm, 
2645
    /* COPY_TO_REGCLASS */
2646
    -1, -1, i32imm, 
2647
    /* DBG_VALUE */
2648
    /* DBG_VALUE_LIST */
2649
    /* DBG_INSTR_REF */
2650
    /* DBG_PHI */
2651
    /* DBG_LABEL */
2652
    -1, 
2653
    /* REG_SEQUENCE */
2654
    -1, -1, 
2655
    /* COPY */
2656
    -1, -1, 
2657
    /* BUNDLE */
2658
    /* LIFETIME_START */
2659
    i32imm, 
2660
    /* LIFETIME_END */
2661
    i32imm, 
2662
    /* PSEUDO_PROBE */
2663
    i64imm, i64imm, i8imm, i32imm, 
2664
    /* ARITH_FENCE */
2665
    -1, -1, 
2666
    /* STACKMAP */
2667
    i64imm, i32imm, 
2668
    /* FENTRY_CALL */
2669
    /* PATCHPOINT */
2670
    -1, i64imm, i32imm, -1, i32imm, i32imm, 
2671
    /* LOAD_STACK_GUARD */
2672
    -1, 
2673
    /* PREALLOCATED_SETUP */
2674
    i32imm, 
2675
    /* PREALLOCATED_ARG */
2676
    -1, i32imm, i32imm, 
2677
    /* STATEPOINT */
2678
    /* LOCAL_ESCAPE */
2679
    -1, i32imm, 
2680
    /* FAULTING_OP */
2681
    -1, 
2682
    /* PATCHABLE_OP */
2683
    /* PATCHABLE_FUNCTION_ENTER */
2684
    /* PATCHABLE_RET */
2685
    /* PATCHABLE_FUNCTION_EXIT */
2686
    /* PATCHABLE_TAIL_CALL */
2687
    /* PATCHABLE_EVENT_CALL */
2688
    -1, -1, 
2689
    /* PATCHABLE_TYPED_EVENT_CALL */
2690
    -1, -1, -1, 
2691
    /* ICALL_BRANCH_FUNNEL */
2692
    /* MEMBARRIER */
2693
    /* JUMP_TABLE_DEBUG_INFO */
2694
    i64imm, 
2695
    /* G_ASSERT_SEXT */
2696
    type0, type0, untyped_imm_0, 
2697
    /* G_ASSERT_ZEXT */
2698
    type0, type0, untyped_imm_0, 
2699
    /* G_ASSERT_ALIGN */
2700
    type0, type0, untyped_imm_0, 
2701
    /* G_ADD */
2702
    type0, type0, type0, 
2703
    /* G_SUB */
2704
    type0, type0, type0, 
2705
    /* G_MUL */
2706
    type0, type0, type0, 
2707
    /* G_SDIV */
2708
    type0, type0, type0, 
2709
    /* G_UDIV */
2710
    type0, type0, type0, 
2711
    /* G_SREM */
2712
    type0, type0, type0, 
2713
    /* G_UREM */
2714
    type0, type0, type0, 
2715
    /* G_SDIVREM */
2716
    type0, type0, type0, type0, 
2717
    /* G_UDIVREM */
2718
    type0, type0, type0, type0, 
2719
    /* G_AND */
2720
    type0, type0, type0, 
2721
    /* G_OR */
2722
    type0, type0, type0, 
2723
    /* G_XOR */
2724
    type0, type0, type0, 
2725
    /* G_IMPLICIT_DEF */
2726
    type0, 
2727
    /* G_PHI */
2728
    type0, 
2729
    /* G_FRAME_INDEX */
2730
    type0, -1, 
2731
    /* G_GLOBAL_VALUE */
2732
    type0, -1, 
2733
    /* G_CONSTANT_POOL */
2734
    type0, -1, 
2735
    /* G_EXTRACT */
2736
    type0, type1, untyped_imm_0, 
2737
    /* G_UNMERGE_VALUES */
2738
    type0, type1, 
2739
    /* G_INSERT */
2740
    type0, type0, type1, untyped_imm_0, 
2741
    /* G_MERGE_VALUES */
2742
    type0, type1, 
2743
    /* G_BUILD_VECTOR */
2744
    type0, type1, 
2745
    /* G_BUILD_VECTOR_TRUNC */
2746
    type0, type1, 
2747
    /* G_CONCAT_VECTORS */
2748
    type0, type1, 
2749
    /* G_PTRTOINT */
2750
    type0, type1, 
2751
    /* G_INTTOPTR */
2752
    type0, type1, 
2753
    /* G_BITCAST */
2754
    type0, type1, 
2755
    /* G_FREEZE */
2756
    type0, type0, 
2757
    /* G_CONSTANT_FOLD_BARRIER */
2758
    type0, type0, 
2759
    /* G_INTRINSIC_FPTRUNC_ROUND */
2760
    type0, type1, i32imm, 
2761
    /* G_INTRINSIC_TRUNC */
2762
    type0, type0, 
2763
    /* G_INTRINSIC_ROUND */
2764
    type0, type0, 
2765
    /* G_INTRINSIC_LRINT */
2766
    type0, type1, 
2767
    /* G_INTRINSIC_ROUNDEVEN */
2768
    type0, type0, 
2769
    /* G_READCYCLECOUNTER */
2770
    type0, 
2771
    /* G_LOAD */
2772
    type0, ptype1, 
2773
    /* G_SEXTLOAD */
2774
    type0, ptype1, 
2775
    /* G_ZEXTLOAD */
2776
    type0, ptype1, 
2777
    /* G_INDEXED_LOAD */
2778
    type0, ptype1, ptype1, type2, -1, 
2779
    /* G_INDEXED_SEXTLOAD */
2780
    type0, ptype1, ptype1, type2, -1, 
2781
    /* G_INDEXED_ZEXTLOAD */
2782
    type0, ptype1, ptype1, type2, -1, 
2783
    /* G_STORE */
2784
    type0, ptype1, 
2785
    /* G_INDEXED_STORE */
2786
    ptype0, type1, ptype0, ptype2, -1, 
2787
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
2788
    type0, type1, type2, type0, type0, 
2789
    /* G_ATOMIC_CMPXCHG */
2790
    type0, ptype1, type0, type0, 
2791
    /* G_ATOMICRMW_XCHG */
2792
    type0, ptype1, type0, 
2793
    /* G_ATOMICRMW_ADD */
2794
    type0, ptype1, type0, 
2795
    /* G_ATOMICRMW_SUB */
2796
    type0, ptype1, type0, 
2797
    /* G_ATOMICRMW_AND */
2798
    type0, ptype1, type0, 
2799
    /* G_ATOMICRMW_NAND */
2800
    type0, ptype1, type0, 
2801
    /* G_ATOMICRMW_OR */
2802
    type0, ptype1, type0, 
2803
    /* G_ATOMICRMW_XOR */
2804
    type0, ptype1, type0, 
2805
    /* G_ATOMICRMW_MAX */
2806
    type0, ptype1, type0, 
2807
    /* G_ATOMICRMW_MIN */
2808
    type0, ptype1, type0, 
2809
    /* G_ATOMICRMW_UMAX */
2810
    type0, ptype1, type0, 
2811
    /* G_ATOMICRMW_UMIN */
2812
    type0, ptype1, type0, 
2813
    /* G_ATOMICRMW_FADD */
2814
    type0, ptype1, type0, 
2815
    /* G_ATOMICRMW_FSUB */
2816
    type0, ptype1, type0, 
2817
    /* G_ATOMICRMW_FMAX */
2818
    type0, ptype1, type0, 
2819
    /* G_ATOMICRMW_FMIN */
2820
    type0, ptype1, type0, 
2821
    /* G_ATOMICRMW_UINC_WRAP */
2822
    type0, ptype1, type0, 
2823
    /* G_ATOMICRMW_UDEC_WRAP */
2824
    type0, ptype1, type0, 
2825
    /* G_FENCE */
2826
    i32imm, i32imm, 
2827
    /* G_PREFETCH */
2828
    ptype0, i32imm, i32imm, i32imm, 
2829
    /* G_BRCOND */
2830
    type0, -1, 
2831
    /* G_BRINDIRECT */
2832
    type0, 
2833
    /* G_INVOKE_REGION_START */
2834
    /* G_INTRINSIC */
2835
    -1, 
2836
    /* G_INTRINSIC_W_SIDE_EFFECTS */
2837
    -1, 
2838
    /* G_INTRINSIC_CONVERGENT */
2839
    -1, 
2840
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
2841
    -1, 
2842
    /* G_ANYEXT */
2843
    type0, type1, 
2844
    /* G_TRUNC */
2845
    type0, type1, 
2846
    /* G_CONSTANT */
2847
    type0, -1, 
2848
    /* G_FCONSTANT */
2849
    type0, -1, 
2850
    /* G_VASTART */
2851
    type0, 
2852
    /* G_VAARG */
2853
    type0, type1, -1, 
2854
    /* G_SEXT */
2855
    type0, type1, 
2856
    /* G_SEXT_INREG */
2857
    type0, type0, untyped_imm_0, 
2858
    /* G_ZEXT */
2859
    type0, type1, 
2860
    /* G_SHL */
2861
    type0, type0, type1, 
2862
    /* G_LSHR */
2863
    type0, type0, type1, 
2864
    /* G_ASHR */
2865
    type0, type0, type1, 
2866
    /* G_FSHL */
2867
    type0, type0, type0, type1, 
2868
    /* G_FSHR */
2869
    type0, type0, type0, type1, 
2870
    /* G_ROTR */
2871
    type0, type0, type1, 
2872
    /* G_ROTL */
2873
    type0, type0, type1, 
2874
    /* G_ICMP */
2875
    type0, -1, type1, type1, 
2876
    /* G_FCMP */
2877
    type0, -1, type1, type1, 
2878
    /* G_SELECT */
2879
    type0, type1, type0, type0, 
2880
    /* G_UADDO */
2881
    type0, type1, type0, type0, 
2882
    /* G_UADDE */
2883
    type0, type1, type0, type0, type1, 
2884
    /* G_USUBO */
2885
    type0, type1, type0, type0, 
2886
    /* G_USUBE */
2887
    type0, type1, type0, type0, type1, 
2888
    /* G_SADDO */
2889
    type0, type1, type0, type0, 
2890
    /* G_SADDE */
2891
    type0, type1, type0, type0, type1, 
2892
    /* G_SSUBO */
2893
    type0, type1, type0, type0, 
2894
    /* G_SSUBE */
2895
    type0, type1, type0, type0, type1, 
2896
    /* G_UMULO */
2897
    type0, type1, type0, type0, 
2898
    /* G_SMULO */
2899
    type0, type1, type0, type0, 
2900
    /* G_UMULH */
2901
    type0, type0, type0, 
2902
    /* G_SMULH */
2903
    type0, type0, type0, 
2904
    /* G_UADDSAT */
2905
    type0, type0, type0, 
2906
    /* G_SADDSAT */
2907
    type0, type0, type0, 
2908
    /* G_USUBSAT */
2909
    type0, type0, type0, 
2910
    /* G_SSUBSAT */
2911
    type0, type0, type0, 
2912
    /* G_USHLSAT */
2913
    type0, type0, type1, 
2914
    /* G_SSHLSAT */
2915
    type0, type0, type1, 
2916
    /* G_SMULFIX */
2917
    type0, type0, type0, untyped_imm_0, 
2918
    /* G_UMULFIX */
2919
    type0, type0, type0, untyped_imm_0, 
2920
    /* G_SMULFIXSAT */
2921
    type0, type0, type0, untyped_imm_0, 
2922
    /* G_UMULFIXSAT */
2923
    type0, type0, type0, untyped_imm_0, 
2924
    /* G_SDIVFIX */
2925
    type0, type0, type0, untyped_imm_0, 
2926
    /* G_UDIVFIX */
2927
    type0, type0, type0, untyped_imm_0, 
2928
    /* G_SDIVFIXSAT */
2929
    type0, type0, type0, untyped_imm_0, 
2930
    /* G_UDIVFIXSAT */
2931
    type0, type0, type0, untyped_imm_0, 
2932
    /* G_FADD */
2933
    type0, type0, type0, 
2934
    /* G_FSUB */
2935
    type0, type0, type0, 
2936
    /* G_FMUL */
2937
    type0, type0, type0, 
2938
    /* G_FMA */
2939
    type0, type0, type0, type0, 
2940
    /* G_FMAD */
2941
    type0, type0, type0, type0, 
2942
    /* G_FDIV */
2943
    type0, type0, type0, 
2944
    /* G_FREM */
2945
    type0, type0, type0, 
2946
    /* G_FPOW */
2947
    type0, type0, type0, 
2948
    /* G_FPOWI */
2949
    type0, type0, type1, 
2950
    /* G_FEXP */
2951
    type0, type0, 
2952
    /* G_FEXP2 */
2953
    type0, type0, 
2954
    /* G_FEXP10 */
2955
    type0, type0, 
2956
    /* G_FLOG */
2957
    type0, type0, 
2958
    /* G_FLOG2 */
2959
    type0, type0, 
2960
    /* G_FLOG10 */
2961
    type0, type0, 
2962
    /* G_FLDEXP */
2963
    type0, type0, type1, 
2964
    /* G_FFREXP */
2965
    type0, type1, type0, 
2966
    /* G_FNEG */
2967
    type0, type0, 
2968
    /* G_FPEXT */
2969
    type0, type1, 
2970
    /* G_FPTRUNC */
2971
    type0, type1, 
2972
    /* G_FPTOSI */
2973
    type0, type1, 
2974
    /* G_FPTOUI */
2975
    type0, type1, 
2976
    /* G_SITOFP */
2977
    type0, type1, 
2978
    /* G_UITOFP */
2979
    type0, type1, 
2980
    /* G_FABS */
2981
    type0, type0, 
2982
    /* G_FCOPYSIGN */
2983
    type0, type0, type1, 
2984
    /* G_IS_FPCLASS */
2985
    type0, type1, -1, 
2986
    /* G_FCANONICALIZE */
2987
    type0, type0, 
2988
    /* G_FMINNUM */
2989
    type0, type0, type0, 
2990
    /* G_FMAXNUM */
2991
    type0, type0, type0, 
2992
    /* G_FMINNUM_IEEE */
2993
    type0, type0, type0, 
2994
    /* G_FMAXNUM_IEEE */
2995
    type0, type0, type0, 
2996
    /* G_FMINIMUM */
2997
    type0, type0, type0, 
2998
    /* G_FMAXIMUM */
2999
    type0, type0, type0, 
3000
    /* G_GET_FPENV */
3001
    type0, 
3002
    /* G_SET_FPENV */
3003
    type0, 
3004
    /* G_RESET_FPENV */
3005
    /* G_GET_FPMODE */
3006
    type0, 
3007
    /* G_SET_FPMODE */
3008
    type0, 
3009
    /* G_RESET_FPMODE */
3010
    /* G_PTR_ADD */
3011
    ptype0, ptype0, type1, 
3012
    /* G_PTRMASK */
3013
    ptype0, ptype0, type1, 
3014
    /* G_SMIN */
3015
    type0, type0, type0, 
3016
    /* G_SMAX */
3017
    type0, type0, type0, 
3018
    /* G_UMIN */
3019
    type0, type0, type0, 
3020
    /* G_UMAX */
3021
    type0, type0, type0, 
3022
    /* G_ABS */
3023
    type0, type0, 
3024
    /* G_LROUND */
3025
    type0, type1, 
3026
    /* G_LLROUND */
3027
    type0, type1, 
3028
    /* G_BR */
3029
    -1, 
3030
    /* G_BRJT */
3031
    ptype0, -1, type1, 
3032
    /* G_INSERT_VECTOR_ELT */
3033
    type0, type0, type1, type2, 
3034
    /* G_EXTRACT_VECTOR_ELT */
3035
    type0, type1, type2, 
3036
    /* G_SHUFFLE_VECTOR */
3037
    type0, type1, type1, -1, 
3038
    /* G_CTTZ */
3039
    type0, type1, 
3040
    /* G_CTTZ_ZERO_UNDEF */
3041
    type0, type1, 
3042
    /* G_CTLZ */
3043
    type0, type1, 
3044
    /* G_CTLZ_ZERO_UNDEF */
3045
    type0, type1, 
3046
    /* G_CTPOP */
3047
    type0, type1, 
3048
    /* G_BSWAP */
3049
    type0, type0, 
3050
    /* G_BITREVERSE */
3051
    type0, type0, 
3052
    /* G_FCEIL */
3053
    type0, type0, 
3054
    /* G_FCOS */
3055
    type0, type0, 
3056
    /* G_FSIN */
3057
    type0, type0, 
3058
    /* G_FSQRT */
3059
    type0, type0, 
3060
    /* G_FFLOOR */
3061
    type0, type0, 
3062
    /* G_FRINT */
3063
    type0, type0, 
3064
    /* G_FNEARBYINT */
3065
    type0, type0, 
3066
    /* G_ADDRSPACE_CAST */
3067
    type0, type1, 
3068
    /* G_BLOCK_ADDR */
3069
    type0, -1, 
3070
    /* G_JUMP_TABLE */
3071
    type0, -1, 
3072
    /* G_DYN_STACKALLOC */
3073
    ptype0, type1, i32imm, 
3074
    /* G_STACKSAVE */
3075
    ptype0, 
3076
    /* G_STACKRESTORE */
3077
    ptype0, 
3078
    /* G_STRICT_FADD */
3079
    type0, type0, type0, 
3080
    /* G_STRICT_FSUB */
3081
    type0, type0, type0, 
3082
    /* G_STRICT_FMUL */
3083
    type0, type0, type0, 
3084
    /* G_STRICT_FDIV */
3085
    type0, type0, type0, 
3086
    /* G_STRICT_FREM */
3087
    type0, type0, type0, 
3088
    /* G_STRICT_FMA */
3089
    type0, type0, type0, type0, 
3090
    /* G_STRICT_FSQRT */
3091
    type0, type0, 
3092
    /* G_STRICT_FLDEXP */
3093
    type0, type0, type1, 
3094
    /* G_READ_REGISTER */
3095
    type0, -1, 
3096
    /* G_WRITE_REGISTER */
3097
    -1, type0, 
3098
    /* G_MEMCPY */
3099
    ptype0, ptype1, type2, untyped_imm_0, 
3100
    /* G_MEMCPY_INLINE */
3101
    ptype0, ptype1, type2, 
3102
    /* G_MEMMOVE */
3103
    ptype0, ptype1, type2, untyped_imm_0, 
3104
    /* G_MEMSET */
3105
    ptype0, type1, type2, untyped_imm_0, 
3106
    /* G_BZERO */
3107
    ptype0, type1, untyped_imm_0, 
3108
    /* G_VECREDUCE_SEQ_FADD */
3109
    type0, type1, type2, 
3110
    /* G_VECREDUCE_SEQ_FMUL */
3111
    type0, type1, type2, 
3112
    /* G_VECREDUCE_FADD */
3113
    type0, type1, 
3114
    /* G_VECREDUCE_FMUL */
3115
    type0, type1, 
3116
    /* G_VECREDUCE_FMAX */
3117
    type0, type1, 
3118
    /* G_VECREDUCE_FMIN */
3119
    type0, type1, 
3120
    /* G_VECREDUCE_FMAXIMUM */
3121
    type0, type1, 
3122
    /* G_VECREDUCE_FMINIMUM */
3123
    type0, type1, 
3124
    /* G_VECREDUCE_ADD */
3125
    type0, type1, 
3126
    /* G_VECREDUCE_MUL */
3127
    type0, type1, 
3128
    /* G_VECREDUCE_AND */
3129
    type0, type1, 
3130
    /* G_VECREDUCE_OR */
3131
    type0, type1, 
3132
    /* G_VECREDUCE_XOR */
3133
    type0, type1, 
3134
    /* G_VECREDUCE_SMAX */
3135
    type0, type1, 
3136
    /* G_VECREDUCE_SMIN */
3137
    type0, type1, 
3138
    /* G_VECREDUCE_UMAX */
3139
    type0, type1, 
3140
    /* G_VECREDUCE_UMIN */
3141
    type0, type1, 
3142
    /* G_SBFX */
3143
    type0, type0, type1, type1, 
3144
    /* G_UBFX */
3145
    type0, type0, type1, type1, 
3146
    /* ADJCALLSTACKDOWN */
3147
    i64imm, i64imm, 
3148
    /* ADJCALLSTACKUP */
3149
    i64imm, i64imm, 
3150
    /* FI_ri */
3151
    GPR, GPR, s16imm, 
3152
    /* MEMCPY */
3153
    GPR, GPR, i64imm, i64imm, 
3154
    /* Select */
3155
    GPR, GPR, GPR, i64imm, GPR, GPR, 
3156
    /* Select_32 */
3157
    GPR32, GPR32, GPR32, i32imm, GPR32, GPR32, 
3158
    /* Select_32_64 */
3159
    GPR, GPR32, GPR32, i32imm, GPR, GPR, 
3160
    /* Select_64_32 */
3161
    GPR32, GPR, GPR, i64imm, GPR32, GPR32, 
3162
    /* Select_Ri */
3163
    GPR, GPR, i64imm, i64imm, GPR, GPR, 
3164
    /* Select_Ri_32 */
3165
    GPR32, GPR32, i32imm, i32imm, GPR32, GPR32, 
3166
    /* Select_Ri_32_64 */
3167
    GPR, GPR32, i32imm, i32imm, GPR, GPR, 
3168
    /* Select_Ri_64_32 */
3169
    GPR32, GPR, i64imm, i64imm, GPR32, GPR32, 
3170
    /* ADD_ri */
3171
    GPR, GPR, i64imm, 
3172
    /* ADD_ri_32 */
3173
    GPR32, GPR32, i32imm, 
3174
    /* ADD_rr */
3175
    GPR, GPR, GPR, 
3176
    /* ADD_rr_32 */
3177
    GPR32, GPR32, GPR32, 
3178
    /* AND_ri */
3179
    GPR, GPR, i64imm, 
3180
    /* AND_ri_32 */
3181
    GPR32, GPR32, i32imm, 
3182
    /* AND_rr */
3183
    GPR, GPR, GPR, 
3184
    /* AND_rr_32 */
3185
    GPR32, GPR32, GPR32, 
3186
    /* BE16 */
3187
    GPR, GPR, 
3188
    /* BE32 */
3189
    GPR, GPR, 
3190
    /* BE64 */
3191
    GPR, GPR, 
3192
    /* BSWAP16 */
3193
    GPR, GPR, 
3194
    /* BSWAP32 */
3195
    GPR, GPR, 
3196
    /* BSWAP64 */
3197
    GPR, GPR, 
3198
    /* CMPXCHGD */
3199
    GPR, s16imm, GPR, 
3200
    /* CMPXCHGW32 */
3201
    GPR, s16imm, GPR32, 
3202
    /* CORE_LD32 */
3203
    GPR32, u64imm, GPR, u64imm, 
3204
    /* CORE_LD64 */
3205
    GPR, u64imm, GPR, u64imm, 
3206
    /* CORE_SHIFT */
3207
    GPR, u64imm, GPR, u64imm, 
3208
    /* CORE_ST */
3209
    gpr_or_imm, u64imm, GPR, u64imm, 
3210
    /* DIV_ri */
3211
    GPR, GPR, i64imm, 
3212
    /* DIV_ri_32 */
3213
    GPR32, GPR32, i32imm, 
3214
    /* DIV_rr */
3215
    GPR, GPR, GPR, 
3216
    /* DIV_rr_32 */
3217
    GPR32, GPR32, GPR32, 
3218
    /* JAL */
3219
    calltarget, 
3220
    /* JALX */
3221
    GPR, 
3222
    /* JEQ_ri */
3223
    GPR, i64imm, brtarget, 
3224
    /* JEQ_ri_32 */
3225
    GPR32, i32imm, brtarget, 
3226
    /* JEQ_rr */
3227
    GPR, GPR, brtarget, 
3228
    /* JEQ_rr_32 */
3229
    GPR32, GPR32, brtarget, 
3230
    /* JMP */
3231
    brtarget, 
3232
    /* JMPL */
3233
    brtarget, 
3234
    /* JNE_ri */
3235
    GPR, i64imm, brtarget, 
3236
    /* JNE_ri_32 */
3237
    GPR32, i32imm, brtarget, 
3238
    /* JNE_rr */
3239
    GPR, GPR, brtarget, 
3240
    /* JNE_rr_32 */
3241
    GPR32, GPR32, brtarget, 
3242
    /* JSET_ri */
3243
    GPR, i64imm, brtarget, 
3244
    /* JSET_ri_32 */
3245
    GPR32, i32imm, brtarget, 
3246
    /* JSET_rr */
3247
    GPR, GPR, brtarget, 
3248
    /* JSET_rr_32 */
3249
    GPR32, GPR32, brtarget, 
3250
    /* JSGE_ri */
3251
    GPR, i64imm, brtarget, 
3252
    /* JSGE_ri_32 */
3253
    GPR32, i32imm, brtarget, 
3254
    /* JSGE_rr */
3255
    GPR, GPR, brtarget, 
3256
    /* JSGE_rr_32 */
3257
    GPR32, GPR32, brtarget, 
3258
    /* JSGT_ri */
3259
    GPR, i64imm, brtarget, 
3260
    /* JSGT_ri_32 */
3261
    GPR32, i32imm, brtarget, 
3262
    /* JSGT_rr */
3263
    GPR, GPR, brtarget, 
3264
    /* JSGT_rr_32 */
3265
    GPR32, GPR32, brtarget, 
3266
    /* JSLE_ri */
3267
    GPR, i64imm, brtarget, 
3268
    /* JSLE_ri_32 */
3269
    GPR32, i32imm, brtarget, 
3270
    /* JSLE_rr */
3271
    GPR, GPR, brtarget, 
3272
    /* JSLE_rr_32 */
3273
    GPR32, GPR32, brtarget, 
3274
    /* JSLT_ri */
3275
    GPR, i64imm, brtarget, 
3276
    /* JSLT_ri_32 */
3277
    GPR32, i32imm, brtarget, 
3278
    /* JSLT_rr */
3279
    GPR, GPR, brtarget, 
3280
    /* JSLT_rr_32 */
3281
    GPR32, GPR32, brtarget, 
3282
    /* JUGE_ri */
3283
    GPR, i64imm, brtarget, 
3284
    /* JUGE_ri_32 */
3285
    GPR32, i32imm, brtarget, 
3286
    /* JUGE_rr */
3287
    GPR, GPR, brtarget, 
3288
    /* JUGE_rr_32 */
3289
    GPR32, GPR32, brtarget, 
3290
    /* JUGT_ri */
3291
    GPR, i64imm, brtarget, 
3292
    /* JUGT_ri_32 */
3293
    GPR32, i32imm, brtarget, 
3294
    /* JUGT_rr */
3295
    GPR, GPR, brtarget, 
3296
    /* JUGT_rr_32 */
3297
    GPR32, GPR32, brtarget, 
3298
    /* JULE_ri */
3299
    GPR, i64imm, brtarget, 
3300
    /* JULE_ri_32 */
3301
    GPR32, i32imm, brtarget, 
3302
    /* JULE_rr */
3303
    GPR, GPR, brtarget, 
3304
    /* JULE_rr_32 */
3305
    GPR32, GPR32, brtarget, 
3306
    /* JULT_ri */
3307
    GPR, i64imm, brtarget, 
3308
    /* JULT_ri_32 */
3309
    GPR32, i32imm, brtarget, 
3310
    /* JULT_rr */
3311
    GPR, GPR, brtarget, 
3312
    /* JULT_rr_32 */
3313
    GPR32, GPR32, brtarget, 
3314
    /* LDB */
3315
    GPR, GPR, s16imm, 
3316
    /* LDB32 */
3317
    GPR32, GPR, s16imm, 
3318
    /* LDBSX */
3319
    GPR, GPR, s16imm, 
3320
    /* LDD */
3321
    GPR, GPR, s16imm, 
3322
    /* LDH */
3323
    GPR, GPR, s16imm, 
3324
    /* LDH32 */
3325
    GPR32, GPR, s16imm, 
3326
    /* LDHSX */
3327
    GPR, GPR, s16imm, 
3328
    /* LDW */
3329
    GPR, GPR, s16imm, 
3330
    /* LDW32 */
3331
    GPR32, GPR, s16imm, 
3332
    /* LDWSX */
3333
    GPR, GPR, s16imm, 
3334
    /* LD_ABS_B */
3335
    GPR, i64imm, 
3336
    /* LD_ABS_H */
3337
    GPR, i64imm, 
3338
    /* LD_ABS_W */
3339
    GPR, i64imm, 
3340
    /* LD_IND_B */
3341
    GPR, GPR, 
3342
    /* LD_IND_H */
3343
    GPR, GPR, 
3344
    /* LD_IND_W */
3345
    GPR, GPR, 
3346
    /* LD_imm64 */
3347
    GPR, u64imm, 
3348
    /* LD_pseudo */
3349
    GPR, i64imm, u64imm, 
3350
    /* LE16 */
3351
    GPR, GPR, 
3352
    /* LE32 */
3353
    GPR, GPR, 
3354
    /* LE64 */
3355
    GPR, GPR, 
3356
    /* MOD_ri */
3357
    GPR, GPR, i64imm, 
3358
    /* MOD_ri_32 */
3359
    GPR32, GPR32, i32imm, 
3360
    /* MOD_rr */
3361
    GPR, GPR, GPR, 
3362
    /* MOD_rr_32 */
3363
    GPR32, GPR32, GPR32, 
3364
    /* MOVSX_rr_16 */
3365
    GPR, GPR, 
3366
    /* MOVSX_rr_32 */
3367
    GPR, GPR, 
3368
    /* MOVSX_rr_32_16 */
3369
    GPR32, GPR32, 
3370
    /* MOVSX_rr_32_8 */
3371
    GPR32, GPR32, 
3372
    /* MOVSX_rr_8 */
3373
    GPR, GPR, 
3374
    /* MOV_32_64 */
3375
    GPR, GPR32, 
3376
    /* MOV_ri */
3377
    GPR, i64imm, 
3378
    /* MOV_ri_32 */
3379
    GPR32, i32imm, 
3380
    /* MOV_rr */
3381
    GPR, GPR, 
3382
    /* MOV_rr_32 */
3383
    GPR32, GPR32, 
3384
    /* MUL_ri */
3385
    GPR, GPR, i64imm, 
3386
    /* MUL_ri_32 */
3387
    GPR32, GPR32, i32imm, 
3388
    /* MUL_rr */
3389
    GPR, GPR, GPR, 
3390
    /* MUL_rr_32 */
3391
    GPR32, GPR32, GPR32, 
3392
    /* NEG_32 */
3393
    GPR32, GPR32, 
3394
    /* NEG_64 */
3395
    GPR, GPR, 
3396
    /* NOP */
3397
    i32imm, 
3398
    /* OR_ri */
3399
    GPR, GPR, i64imm, 
3400
    /* OR_ri_32 */
3401
    GPR32, GPR32, i32imm, 
3402
    /* OR_rr */
3403
    GPR, GPR, GPR, 
3404
    /* OR_rr_32 */
3405
    GPR32, GPR32, GPR32, 
3406
    /* RET */
3407
    /* SDIV_ri */
3408
    GPR, GPR, i64imm, 
3409
    /* SDIV_ri_32 */
3410
    GPR32, GPR32, i32imm, 
3411
    /* SDIV_rr */
3412
    GPR, GPR, GPR, 
3413
    /* SDIV_rr_32 */
3414
    GPR32, GPR32, GPR32, 
3415
    /* SLL_ri */
3416
    GPR, GPR, i64imm, 
3417
    /* SLL_ri_32 */
3418
    GPR32, GPR32, i32imm, 
3419
    /* SLL_rr */
3420
    GPR, GPR, GPR, 
3421
    /* SLL_rr_32 */
3422
    GPR32, GPR32, GPR32, 
3423
    /* SMOD_ri */
3424
    GPR, GPR, i64imm, 
3425
    /* SMOD_ri_32 */
3426
    GPR32, GPR32, i32imm, 
3427
    /* SMOD_rr */
3428
    GPR, GPR, GPR, 
3429
    /* SMOD_rr_32 */
3430
    GPR32, GPR32, GPR32, 
3431
    /* SRA_ri */
3432
    GPR, GPR, i64imm, 
3433
    /* SRA_ri_32 */
3434
    GPR32, GPR32, i32imm, 
3435
    /* SRA_rr */
3436
    GPR, GPR, GPR, 
3437
    /* SRA_rr_32 */
3438
    GPR32, GPR32, GPR32, 
3439
    /* SRL_ri */
3440
    GPR, GPR, i64imm, 
3441
    /* SRL_ri_32 */
3442
    GPR32, GPR32, i32imm, 
3443
    /* SRL_rr */
3444
    GPR, GPR, GPR, 
3445
    /* SRL_rr_32 */
3446
    GPR32, GPR32, GPR32, 
3447
    /* STB */
3448
    GPR, GPR, s16imm, 
3449
    /* STB32 */
3450
    GPR32, GPR, s16imm, 
3451
    /* STB_imm */
3452
    i64imm, GPR, s16imm, 
3453
    /* STD */
3454
    GPR, GPR, s16imm, 
3455
    /* STD_imm */
3456
    i64imm, GPR, s16imm, 
3457
    /* STH */
3458
    GPR, GPR, s16imm, 
3459
    /* STH32 */
3460
    GPR32, GPR, s16imm, 
3461
    /* STH_imm */
3462
    i64imm, GPR, s16imm, 
3463
    /* STW */
3464
    GPR, GPR, s16imm, 
3465
    /* STW32 */
3466
    GPR32, GPR, s16imm, 
3467
    /* STW_imm */
3468
    i64imm, GPR, s16imm, 
3469
    /* SUB_ri */
3470
    GPR, GPR, i64imm, 
3471
    /* SUB_ri_32 */
3472
    GPR32, GPR32, i32imm, 
3473
    /* SUB_rr */
3474
    GPR, GPR, GPR, 
3475
    /* SUB_rr_32 */
3476
    GPR32, GPR32, GPR32, 
3477
    /* XADDD */
3478
    GPR, GPR, s16imm, GPR, 
3479
    /* XADDW */
3480
    GPR, GPR, s16imm, GPR, 
3481
    /* XADDW32 */
3482
    GPR32, GPR, s16imm, GPR32, 
3483
    /* XANDD */
3484
    GPR, GPR, s16imm, GPR, 
3485
    /* XANDW32 */
3486
    GPR32, GPR, s16imm, GPR32, 
3487
    /* XCHGD */
3488
    GPR, GPR, s16imm, GPR, 
3489
    /* XCHGW32 */
3490
    GPR32, GPR, s16imm, GPR32, 
3491
    /* XFADDD */
3492
    GPR, GPR, s16imm, GPR, 
3493
    /* XFADDW32 */
3494
    GPR32, GPR, s16imm, GPR32, 
3495
    /* XFANDD */
3496
    GPR, GPR, s16imm, GPR, 
3497
    /* XFANDW32 */
3498
    GPR32, GPR, s16imm, GPR32, 
3499
    /* XFORD */
3500
    GPR, GPR, s16imm, GPR, 
3501
    /* XFORW32 */
3502
    GPR32, GPR, s16imm, GPR32, 
3503
    /* XFXORD */
3504
    GPR, GPR, s16imm, GPR, 
3505
    /* XFXORW32 */
3506
    GPR32, GPR, s16imm, GPR32, 
3507
    /* XORD */
3508
    GPR, GPR, s16imm, GPR, 
3509
    /* XORW32 */
3510
    GPR32, GPR, s16imm, GPR32, 
3511
    /* XOR_ri */
3512
    GPR, GPR, i64imm, 
3513
    /* XOR_ri_32 */
3514
    GPR32, GPR32, i32imm, 
3515
    /* XOR_rr */
3516
    GPR, GPR, GPR, 
3517
    /* XOR_rr_32 */
3518
    GPR32, GPR32, GPR32, 
3519
    /* XXORD */
3520
    GPR, GPR, s16imm, GPR, 
3521
    /* XXORW32 */
3522
    GPR32, GPR, s16imm, GPR32, 
3523
  };
3524
  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
3525
}
3526
} // end namespace BPF
3527
} // end namespace llvm
3528
#endif // GET_INSTRINFO_OPERAND_TYPE
3529
3530
#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
3531
#undef GET_INSTRINFO_MEM_OPERAND_SIZE
3532
namespace llvm {
3533
namespace BPF {
3534
LLVM_READONLY
3535
static int getMemOperandSize(int OpType) {
3536
  switch (OpType) {
3537
  default: return 0;
3538
  }
3539
}
3540
} // end namespace BPF
3541
} // end namespace llvm
3542
#endif // GET_INSTRINFO_MEM_OPERAND_SIZE
3543
3544
#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
3545
#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
3546
namespace llvm {
3547
namespace BPF {
3548
LLVM_READONLY static unsigned
3549
getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
3550
  return LogicalOpIdx;
3551
}
3552
LLVM_READONLY static inline unsigned
3553
getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
3554
  auto S = 0U;
3555
  for (auto i = 0U; i < LogicalOpIdx; ++i)
3556
    S += getLogicalOperandSize(Opcode, i);
3557
  return S;
3558
}
3559
} // end namespace BPF
3560
} // end namespace llvm
3561
#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
3562
3563
#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
3564
#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
3565
namespace llvm {
3566
namespace BPF {
3567
LLVM_READONLY static int
3568
getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
3569
  return -1;
3570
}
3571
} // end namespace BPF
3572
} // end namespace llvm
3573
#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
3574
3575
#ifdef GET_INSTRINFO_MC_HELPER_DECLS
3576
#undef GET_INSTRINFO_MC_HELPER_DECLS
3577
3578
namespace llvm {
3579
class MCInst;
3580
class FeatureBitset;
3581
3582
namespace BPF_MC {
3583
3584
void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
3585
3586
} // end namespace BPF_MC
3587
} // end namespace llvm
3588
3589
#endif // GET_INSTRINFO_MC_HELPER_DECLS
3590
3591
#ifdef GET_INSTRINFO_MC_HELPERS
3592
#undef GET_INSTRINFO_MC_HELPERS
3593
3594
namespace llvm {
3595
namespace BPF_MC {
3596
3597
} // end namespace BPF_MC
3598
} // end namespace llvm
3599
3600
#endif // GET_GENISTRINFO_MC_HELPERS
3601
3602
#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
3603
    defined(GET_AVAILABLE_OPCODE_CHECKER)
3604
#define GET_COMPUTE_FEATURES
3605
#endif
3606
#ifdef GET_COMPUTE_FEATURES
3607
#undef GET_COMPUTE_FEATURES
3608
namespace llvm {
3609
namespace BPF_MC {
3610
3611
// Bits for subtarget features that participate in instruction matching.
3612
enum SubtargetFeatureBits : uint8_t {
3613
};
3614
3615
14
inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
3616
14
  FeatureBitset Features;
3617
14
  return Features;
3618
14
}
3619
3620
14
inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
3621
14
  enum : uint8_t {
3622
14
    CEFBS_None,
3623
14
  };
3624
3625
14
  static constexpr FeatureBitset FeatureBitsets[] = {
3626
14
    {}, // CEFBS_None
3627
14
  };
3628
14
  static constexpr uint8_t RequiredFeaturesRefs[] = {
3629
14
    CEFBS_None, // PHI = 0
3630
14
    CEFBS_None, // INLINEASM = 1
3631
14
    CEFBS_None, // INLINEASM_BR = 2
3632
14
    CEFBS_None, // CFI_INSTRUCTION = 3
3633
14
    CEFBS_None, // EH_LABEL = 4
3634
14
    CEFBS_None, // GC_LABEL = 5
3635
14
    CEFBS_None, // ANNOTATION_LABEL = 6
3636
14
    CEFBS_None, // KILL = 7
3637
14
    CEFBS_None, // EXTRACT_SUBREG = 8
3638
14
    CEFBS_None, // INSERT_SUBREG = 9
3639
14
    CEFBS_None, // IMPLICIT_DEF = 10
3640
14
    CEFBS_None, // SUBREG_TO_REG = 11
3641
14
    CEFBS_None, // COPY_TO_REGCLASS = 12
3642
14
    CEFBS_None, // DBG_VALUE = 13
3643
14
    CEFBS_None, // DBG_VALUE_LIST = 14
3644
14
    CEFBS_None, // DBG_INSTR_REF = 15
3645
14
    CEFBS_None, // DBG_PHI = 16
3646
14
    CEFBS_None, // DBG_LABEL = 17
3647
14
    CEFBS_None, // REG_SEQUENCE = 18
3648
14
    CEFBS_None, // COPY = 19
3649
14
    CEFBS_None, // BUNDLE = 20
3650
14
    CEFBS_None, // LIFETIME_START = 21
3651
14
    CEFBS_None, // LIFETIME_END = 22
3652
14
    CEFBS_None, // PSEUDO_PROBE = 23
3653
14
    CEFBS_None, // ARITH_FENCE = 24
3654
14
    CEFBS_None, // STACKMAP = 25
3655
14
    CEFBS_None, // FENTRY_CALL = 26
3656
14
    CEFBS_None, // PATCHPOINT = 27
3657
14
    CEFBS_None, // LOAD_STACK_GUARD = 28
3658
14
    CEFBS_None, // PREALLOCATED_SETUP = 29
3659
14
    CEFBS_None, // PREALLOCATED_ARG = 30
3660
14
    CEFBS_None, // STATEPOINT = 31
3661
14
    CEFBS_None, // LOCAL_ESCAPE = 32
3662
14
    CEFBS_None, // FAULTING_OP = 33
3663
14
    CEFBS_None, // PATCHABLE_OP = 34
3664
14
    CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
3665
14
    CEFBS_None, // PATCHABLE_RET = 36
3666
14
    CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
3667
14
    CEFBS_None, // PATCHABLE_TAIL_CALL = 38
3668
14
    CEFBS_None, // PATCHABLE_EVENT_CALL = 39
3669
14
    CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
3670
14
    CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
3671
14
    CEFBS_None, // MEMBARRIER = 42
3672
14
    CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 43
3673
14
    CEFBS_None, // G_ASSERT_SEXT = 44
3674
14
    CEFBS_None, // G_ASSERT_ZEXT = 45
3675
14
    CEFBS_None, // G_ASSERT_ALIGN = 46
3676
14
    CEFBS_None, // G_ADD = 47
3677
14
    CEFBS_None, // G_SUB = 48
3678
14
    CEFBS_None, // G_MUL = 49
3679
14
    CEFBS_None, // G_SDIV = 50
3680
14
    CEFBS_None, // G_UDIV = 51
3681
14
    CEFBS_None, // G_SREM = 52
3682
14
    CEFBS_None, // G_UREM = 53
3683
14
    CEFBS_None, // G_SDIVREM = 54
3684
14
    CEFBS_None, // G_UDIVREM = 55
3685
14
    CEFBS_None, // G_AND = 56
3686
14
    CEFBS_None, // G_OR = 57
3687
14
    CEFBS_None, // G_XOR = 58
3688
14
    CEFBS_None, // G_IMPLICIT_DEF = 59
3689
14
    CEFBS_None, // G_PHI = 60
3690
14
    CEFBS_None, // G_FRAME_INDEX = 61
3691
14
    CEFBS_None, // G_GLOBAL_VALUE = 62
3692
14
    CEFBS_None, // G_CONSTANT_POOL = 63
3693
14
    CEFBS_None, // G_EXTRACT = 64
3694
14
    CEFBS_None, // G_UNMERGE_VALUES = 65
3695
14
    CEFBS_None, // G_INSERT = 66
3696
14
    CEFBS_None, // G_MERGE_VALUES = 67
3697
14
    CEFBS_None, // G_BUILD_VECTOR = 68
3698
14
    CEFBS_None, // G_BUILD_VECTOR_TRUNC = 69
3699
14
    CEFBS_None, // G_CONCAT_VECTORS = 70
3700
14
    CEFBS_None, // G_PTRTOINT = 71
3701
14
    CEFBS_None, // G_INTTOPTR = 72
3702
14
    CEFBS_None, // G_BITCAST = 73
3703
14
    CEFBS_None, // G_FREEZE = 74
3704
14
    CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 75
3705
14
    CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 76
3706
14
    CEFBS_None, // G_INTRINSIC_TRUNC = 77
3707
14
    CEFBS_None, // G_INTRINSIC_ROUND = 78
3708
14
    CEFBS_None, // G_INTRINSIC_LRINT = 79
3709
14
    CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 80
3710
14
    CEFBS_None, // G_READCYCLECOUNTER = 81
3711
14
    CEFBS_None, // G_LOAD = 82
3712
14
    CEFBS_None, // G_SEXTLOAD = 83
3713
14
    CEFBS_None, // G_ZEXTLOAD = 84
3714
14
    CEFBS_None, // G_INDEXED_LOAD = 85
3715
14
    CEFBS_None, // G_INDEXED_SEXTLOAD = 86
3716
14
    CEFBS_None, // G_INDEXED_ZEXTLOAD = 87
3717
14
    CEFBS_None, // G_STORE = 88
3718
14
    CEFBS_None, // G_INDEXED_STORE = 89
3719
14
    CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 90
3720
14
    CEFBS_None, // G_ATOMIC_CMPXCHG = 91
3721
14
    CEFBS_None, // G_ATOMICRMW_XCHG = 92
3722
14
    CEFBS_None, // G_ATOMICRMW_ADD = 93
3723
14
    CEFBS_None, // G_ATOMICRMW_SUB = 94
3724
14
    CEFBS_None, // G_ATOMICRMW_AND = 95
3725
14
    CEFBS_None, // G_ATOMICRMW_NAND = 96
3726
14
    CEFBS_None, // G_ATOMICRMW_OR = 97
3727
14
    CEFBS_None, // G_ATOMICRMW_XOR = 98
3728
14
    CEFBS_None, // G_ATOMICRMW_MAX = 99
3729
14
    CEFBS_None, // G_ATOMICRMW_MIN = 100
3730
14
    CEFBS_None, // G_ATOMICRMW_UMAX = 101
3731
14
    CEFBS_None, // G_ATOMICRMW_UMIN = 102
3732
14
    CEFBS_None, // G_ATOMICRMW_FADD = 103
3733
14
    CEFBS_None, // G_ATOMICRMW_FSUB = 104
3734
14
    CEFBS_None, // G_ATOMICRMW_FMAX = 105
3735
14
    CEFBS_None, // G_ATOMICRMW_FMIN = 106
3736
14
    CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 107
3737
14
    CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 108
3738
14
    CEFBS_None, // G_FENCE = 109
3739
14
    CEFBS_None, // G_PREFETCH = 110
3740
14
    CEFBS_None, // G_BRCOND = 111
3741
14
    CEFBS_None, // G_BRINDIRECT = 112
3742
14
    CEFBS_None, // G_INVOKE_REGION_START = 113
3743
14
    CEFBS_None, // G_INTRINSIC = 114
3744
14
    CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 115
3745
14
    CEFBS_None, // G_INTRINSIC_CONVERGENT = 116
3746
14
    CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 117
3747
14
    CEFBS_None, // G_ANYEXT = 118
3748
14
    CEFBS_None, // G_TRUNC = 119
3749
14
    CEFBS_None, // G_CONSTANT = 120
3750
14
    CEFBS_None, // G_FCONSTANT = 121
3751
14
    CEFBS_None, // G_VASTART = 122
3752
14
    CEFBS_None, // G_VAARG = 123
3753
14
    CEFBS_None, // G_SEXT = 124
3754
14
    CEFBS_None, // G_SEXT_INREG = 125
3755
14
    CEFBS_None, // G_ZEXT = 126
3756
14
    CEFBS_None, // G_SHL = 127
3757
14
    CEFBS_None, // G_LSHR = 128
3758
14
    CEFBS_None, // G_ASHR = 129
3759
14
    CEFBS_None, // G_FSHL = 130
3760
14
    CEFBS_None, // G_FSHR = 131
3761
14
    CEFBS_None, // G_ROTR = 132
3762
14
    CEFBS_None, // G_ROTL = 133
3763
14
    CEFBS_None, // G_ICMP = 134
3764
14
    CEFBS_None, // G_FCMP = 135
3765
14
    CEFBS_None, // G_SELECT = 136
3766
14
    CEFBS_None, // G_UADDO = 137
3767
14
    CEFBS_None, // G_UADDE = 138
3768
14
    CEFBS_None, // G_USUBO = 139
3769
14
    CEFBS_None, // G_USUBE = 140
3770
14
    CEFBS_None, // G_SADDO = 141
3771
14
    CEFBS_None, // G_SADDE = 142
3772
14
    CEFBS_None, // G_SSUBO = 143
3773
14
    CEFBS_None, // G_SSUBE = 144
3774
14
    CEFBS_None, // G_UMULO = 145
3775
14
    CEFBS_None, // G_SMULO = 146
3776
14
    CEFBS_None, // G_UMULH = 147
3777
14
    CEFBS_None, // G_SMULH = 148
3778
14
    CEFBS_None, // G_UADDSAT = 149
3779
14
    CEFBS_None, // G_SADDSAT = 150
3780
14
    CEFBS_None, // G_USUBSAT = 151
3781
14
    CEFBS_None, // G_SSUBSAT = 152
3782
14
    CEFBS_None, // G_USHLSAT = 153
3783
14
    CEFBS_None, // G_SSHLSAT = 154
3784
14
    CEFBS_None, // G_SMULFIX = 155
3785
14
    CEFBS_None, // G_UMULFIX = 156
3786
14
    CEFBS_None, // G_SMULFIXSAT = 157
3787
14
    CEFBS_None, // G_UMULFIXSAT = 158
3788
14
    CEFBS_None, // G_SDIVFIX = 159
3789
14
    CEFBS_None, // G_UDIVFIX = 160
3790
14
    CEFBS_None, // G_SDIVFIXSAT = 161
3791
14
    CEFBS_None, // G_UDIVFIXSAT = 162
3792
14
    CEFBS_None, // G_FADD = 163
3793
14
    CEFBS_None, // G_FSUB = 164
3794
14
    CEFBS_None, // G_FMUL = 165
3795
14
    CEFBS_None, // G_FMA = 166
3796
14
    CEFBS_None, // G_FMAD = 167
3797
14
    CEFBS_None, // G_FDIV = 168
3798
14
    CEFBS_None, // G_FREM = 169
3799
14
    CEFBS_None, // G_FPOW = 170
3800
14
    CEFBS_None, // G_FPOWI = 171
3801
14
    CEFBS_None, // G_FEXP = 172
3802
14
    CEFBS_None, // G_FEXP2 = 173
3803
14
    CEFBS_None, // G_FEXP10 = 174
3804
14
    CEFBS_None, // G_FLOG = 175
3805
14
    CEFBS_None, // G_FLOG2 = 176
3806
14
    CEFBS_None, // G_FLOG10 = 177
3807
14
    CEFBS_None, // G_FLDEXP = 178
3808
14
    CEFBS_None, // G_FFREXP = 179
3809
14
    CEFBS_None, // G_FNEG = 180
3810
14
    CEFBS_None, // G_FPEXT = 181
3811
14
    CEFBS_None, // G_FPTRUNC = 182
3812
14
    CEFBS_None, // G_FPTOSI = 183
3813
14
    CEFBS_None, // G_FPTOUI = 184
3814
14
    CEFBS_None, // G_SITOFP = 185
3815
14
    CEFBS_None, // G_UITOFP = 186
3816
14
    CEFBS_None, // G_FABS = 187
3817
14
    CEFBS_None, // G_FCOPYSIGN = 188
3818
14
    CEFBS_None, // G_IS_FPCLASS = 189
3819
14
    CEFBS_None, // G_FCANONICALIZE = 190
3820
14
    CEFBS_None, // G_FMINNUM = 191
3821
14
    CEFBS_None, // G_FMAXNUM = 192
3822
14
    CEFBS_None, // G_FMINNUM_IEEE = 193
3823
14
    CEFBS_None, // G_FMAXNUM_IEEE = 194
3824
14
    CEFBS_None, // G_FMINIMUM = 195
3825
14
    CEFBS_None, // G_FMAXIMUM = 196
3826
14
    CEFBS_None, // G_GET_FPENV = 197
3827
14
    CEFBS_None, // G_SET_FPENV = 198
3828
14
    CEFBS_None, // G_RESET_FPENV = 199
3829
14
    CEFBS_None, // G_GET_FPMODE = 200
3830
14
    CEFBS_None, // G_SET_FPMODE = 201
3831
14
    CEFBS_None, // G_RESET_FPMODE = 202
3832
14
    CEFBS_None, // G_PTR_ADD = 203
3833
14
    CEFBS_None, // G_PTRMASK = 204
3834
14
    CEFBS_None, // G_SMIN = 205
3835
14
    CEFBS_None, // G_SMAX = 206
3836
14
    CEFBS_None, // G_UMIN = 207
3837
14
    CEFBS_None, // G_UMAX = 208
3838
14
    CEFBS_None, // G_ABS = 209
3839
14
    CEFBS_None, // G_LROUND = 210
3840
14
    CEFBS_None, // G_LLROUND = 211
3841
14
    CEFBS_None, // G_BR = 212
3842
14
    CEFBS_None, // G_BRJT = 213
3843
14
    CEFBS_None, // G_INSERT_VECTOR_ELT = 214
3844
14
    CEFBS_None, // G_EXTRACT_VECTOR_ELT = 215
3845
14
    CEFBS_None, // G_SHUFFLE_VECTOR = 216
3846
14
    CEFBS_None, // G_CTTZ = 217
3847
14
    CEFBS_None, // G_CTTZ_ZERO_UNDEF = 218
3848
14
    CEFBS_None, // G_CTLZ = 219
3849
14
    CEFBS_None, // G_CTLZ_ZERO_UNDEF = 220
3850
14
    CEFBS_None, // G_CTPOP = 221
3851
14
    CEFBS_None, // G_BSWAP = 222
3852
14
    CEFBS_None, // G_BITREVERSE = 223
3853
14
    CEFBS_None, // G_FCEIL = 224
3854
14
    CEFBS_None, // G_FCOS = 225
3855
14
    CEFBS_None, // G_FSIN = 226
3856
14
    CEFBS_None, // G_FSQRT = 227
3857
14
    CEFBS_None, // G_FFLOOR = 228
3858
14
    CEFBS_None, // G_FRINT = 229
3859
14
    CEFBS_None, // G_FNEARBYINT = 230
3860
14
    CEFBS_None, // G_ADDRSPACE_CAST = 231
3861
14
    CEFBS_None, // G_BLOCK_ADDR = 232
3862
14
    CEFBS_None, // G_JUMP_TABLE = 233
3863
14
    CEFBS_None, // G_DYN_STACKALLOC = 234
3864
14
    CEFBS_None, // G_STACKSAVE = 235
3865
14
    CEFBS_None, // G_STACKRESTORE = 236
3866
14
    CEFBS_None, // G_STRICT_FADD = 237
3867
14
    CEFBS_None, // G_STRICT_FSUB = 238
3868
14
    CEFBS_None, // G_STRICT_FMUL = 239
3869
14
    CEFBS_None, // G_STRICT_FDIV = 240
3870
14
    CEFBS_None, // G_STRICT_FREM = 241
3871
14
    CEFBS_None, // G_STRICT_FMA = 242
3872
14
    CEFBS_None, // G_STRICT_FSQRT = 243
3873
14
    CEFBS_None, // G_STRICT_FLDEXP = 244
3874
14
    CEFBS_None, // G_READ_REGISTER = 245
3875
14
    CEFBS_None, // G_WRITE_REGISTER = 246
3876
14
    CEFBS_None, // G_MEMCPY = 247
3877
14
    CEFBS_None, // G_MEMCPY_INLINE = 248
3878
14
    CEFBS_None, // G_MEMMOVE = 249
3879
14
    CEFBS_None, // G_MEMSET = 250
3880
14
    CEFBS_None, // G_BZERO = 251
3881
14
    CEFBS_None, // G_VECREDUCE_SEQ_FADD = 252
3882
14
    CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 253
3883
14
    CEFBS_None, // G_VECREDUCE_FADD = 254
3884
14
    CEFBS_None, // G_VECREDUCE_FMUL = 255
3885
14
    CEFBS_None, // G_VECREDUCE_FMAX = 256
3886
14
    CEFBS_None, // G_VECREDUCE_FMIN = 257
3887
14
    CEFBS_None, // G_VECREDUCE_FMAXIMUM = 258
3888
14
    CEFBS_None, // G_VECREDUCE_FMINIMUM = 259
3889
14
    CEFBS_None, // G_VECREDUCE_ADD = 260
3890
14
    CEFBS_None, // G_VECREDUCE_MUL = 261
3891
14
    CEFBS_None, // G_VECREDUCE_AND = 262
3892
14
    CEFBS_None, // G_VECREDUCE_OR = 263
3893
14
    CEFBS_None, // G_VECREDUCE_XOR = 264
3894
14
    CEFBS_None, // G_VECREDUCE_SMAX = 265
3895
14
    CEFBS_None, // G_VECREDUCE_SMIN = 266
3896
14
    CEFBS_None, // G_VECREDUCE_UMAX = 267
3897
14
    CEFBS_None, // G_VECREDUCE_UMIN = 268
3898
14
    CEFBS_None, // G_SBFX = 269
3899
14
    CEFBS_None, // G_UBFX = 270
3900
14
    CEFBS_None, // ADJCALLSTACKDOWN = 271
3901
14
    CEFBS_None, // ADJCALLSTACKUP = 272
3902
14
    CEFBS_None, // FI_ri = 273
3903
14
    CEFBS_None, // MEMCPY = 274
3904
14
    CEFBS_None, // Select = 275
3905
14
    CEFBS_None, // Select_32 = 276
3906
14
    CEFBS_None, // Select_32_64 = 277
3907
14
    CEFBS_None, // Select_64_32 = 278
3908
14
    CEFBS_None, // Select_Ri = 279
3909
14
    CEFBS_None, // Select_Ri_32 = 280
3910
14
    CEFBS_None, // Select_Ri_32_64 = 281
3911
14
    CEFBS_None, // Select_Ri_64_32 = 282
3912
14
    CEFBS_None, // ADD_ri = 283
3913
14
    CEFBS_None, // ADD_ri_32 = 284
3914
14
    CEFBS_None, // ADD_rr = 285
3915
14
    CEFBS_None, // ADD_rr_32 = 286
3916
14
    CEFBS_None, // AND_ri = 287
3917
14
    CEFBS_None, // AND_ri_32 = 288
3918
14
    CEFBS_None, // AND_rr = 289
3919
14
    CEFBS_None, // AND_rr_32 = 290
3920
14
    CEFBS_None, // BE16 = 291
3921
14
    CEFBS_None, // BE32 = 292
3922
14
    CEFBS_None, // BE64 = 293
3923
14
    CEFBS_None, // BSWAP16 = 294
3924
14
    CEFBS_None, // BSWAP32 = 295
3925
14
    CEFBS_None, // BSWAP64 = 296
3926
14
    CEFBS_None, // CMPXCHGD = 297
3927
14
    CEFBS_None, // CMPXCHGW32 = 298
3928
14
    CEFBS_None, // CORE_LD32 = 299
3929
14
    CEFBS_None, // CORE_LD64 = 300
3930
14
    CEFBS_None, // CORE_SHIFT = 301
3931
14
    CEFBS_None, // CORE_ST = 302
3932
14
    CEFBS_None, // DIV_ri = 303
3933
14
    CEFBS_None, // DIV_ri_32 = 304
3934
14
    CEFBS_None, // DIV_rr = 305
3935
14
    CEFBS_None, // DIV_rr_32 = 306
3936
14
    CEFBS_None, // JAL = 307
3937
14
    CEFBS_None, // JALX = 308
3938
14
    CEFBS_None, // JEQ_ri = 309
3939
14
    CEFBS_None, // JEQ_ri_32 = 310
3940
14
    CEFBS_None, // JEQ_rr = 311
3941
14
    CEFBS_None, // JEQ_rr_32 = 312
3942
14
    CEFBS_None, // JMP = 313
3943
14
    CEFBS_None, // JMPL = 314
3944
14
    CEFBS_None, // JNE_ri = 315
3945
14
    CEFBS_None, // JNE_ri_32 = 316
3946
14
    CEFBS_None, // JNE_rr = 317
3947
14
    CEFBS_None, // JNE_rr_32 = 318
3948
14
    CEFBS_None, // JSET_ri = 319
3949
14
    CEFBS_None, // JSET_ri_32 = 320
3950
14
    CEFBS_None, // JSET_rr = 321
3951
14
    CEFBS_None, // JSET_rr_32 = 322
3952
14
    CEFBS_None, // JSGE_ri = 323
3953
14
    CEFBS_None, // JSGE_ri_32 = 324
3954
14
    CEFBS_None, // JSGE_rr = 325
3955
14
    CEFBS_None, // JSGE_rr_32 = 326
3956
14
    CEFBS_None, // JSGT_ri = 327
3957
14
    CEFBS_None, // JSGT_ri_32 = 328
3958
14
    CEFBS_None, // JSGT_rr = 329
3959
14
    CEFBS_None, // JSGT_rr_32 = 330
3960
14
    CEFBS_None, // JSLE_ri = 331
3961
14
    CEFBS_None, // JSLE_ri_32 = 332
3962
14
    CEFBS_None, // JSLE_rr = 333
3963
14
    CEFBS_None, // JSLE_rr_32 = 334
3964
14
    CEFBS_None, // JSLT_ri = 335
3965
14
    CEFBS_None, // JSLT_ri_32 = 336
3966
14
    CEFBS_None, // JSLT_rr = 337
3967
14
    CEFBS_None, // JSLT_rr_32 = 338
3968
14
    CEFBS_None, // JUGE_ri = 339
3969
14
    CEFBS_None, // JUGE_ri_32 = 340
3970
14
    CEFBS_None, // JUGE_rr = 341
3971
14
    CEFBS_None, // JUGE_rr_32 = 342
3972
14
    CEFBS_None, // JUGT_ri = 343
3973
14
    CEFBS_None, // JUGT_ri_32 = 344
3974
14
    CEFBS_None, // JUGT_rr = 345
3975
14
    CEFBS_None, // JUGT_rr_32 = 346
3976
14
    CEFBS_None, // JULE_ri = 347
3977
14
    CEFBS_None, // JULE_ri_32 = 348
3978
14
    CEFBS_None, // JULE_rr = 349
3979
14
    CEFBS_None, // JULE_rr_32 = 350
3980
14
    CEFBS_None, // JULT_ri = 351
3981
14
    CEFBS_None, // JULT_ri_32 = 352
3982
14
    CEFBS_None, // JULT_rr = 353
3983
14
    CEFBS_None, // JULT_rr_32 = 354
3984
14
    CEFBS_None, // LDB = 355
3985
14
    CEFBS_None, // LDB32 = 356
3986
14
    CEFBS_None, // LDBSX = 357
3987
14
    CEFBS_None, // LDD = 358
3988
14
    CEFBS_None, // LDH = 359
3989
14
    CEFBS_None, // LDH32 = 360
3990
14
    CEFBS_None, // LDHSX = 361
3991
14
    CEFBS_None, // LDW = 362
3992
14
    CEFBS_None, // LDW32 = 363
3993
14
    CEFBS_None, // LDWSX = 364
3994
14
    CEFBS_None, // LD_ABS_B = 365
3995
14
    CEFBS_None, // LD_ABS_H = 366
3996
14
    CEFBS_None, // LD_ABS_W = 367
3997
14
    CEFBS_None, // LD_IND_B = 368
3998
14
    CEFBS_None, // LD_IND_H = 369
3999
14
    CEFBS_None, // LD_IND_W = 370
4000
14
    CEFBS_None, // LD_imm64 = 371
4001
14
    CEFBS_None, // LD_pseudo = 372
4002
14
    CEFBS_None, // LE16 = 373
4003
14
    CEFBS_None, // LE32 = 374
4004
14
    CEFBS_None, // LE64 = 375
4005
14
    CEFBS_None, // MOD_ri = 376
4006
14
    CEFBS_None, // MOD_ri_32 = 377
4007
14
    CEFBS_None, // MOD_rr = 378
4008
14
    CEFBS_None, // MOD_rr_32 = 379
4009
14
    CEFBS_None, // MOVSX_rr_16 = 380
4010
14
    CEFBS_None, // MOVSX_rr_32 = 381
4011
14
    CEFBS_None, // MOVSX_rr_32_16 = 382
4012
14
    CEFBS_None, // MOVSX_rr_32_8 = 383
4013
14
    CEFBS_None, // MOVSX_rr_8 = 384
4014
14
    CEFBS_None, // MOV_32_64 = 385
4015
14
    CEFBS_None, // MOV_ri = 386
4016
14
    CEFBS_None, // MOV_ri_32 = 387
4017
14
    CEFBS_None, // MOV_rr = 388
4018
14
    CEFBS_None, // MOV_rr_32 = 389
4019
14
    CEFBS_None, // MUL_ri = 390
4020
14
    CEFBS_None, // MUL_ri_32 = 391
4021
14
    CEFBS_None, // MUL_rr = 392
4022
14
    CEFBS_None, // MUL_rr_32 = 393
4023
14
    CEFBS_None, // NEG_32 = 394
4024
14
    CEFBS_None, // NEG_64 = 395
4025
14
    CEFBS_None, // NOP = 396
4026
14
    CEFBS_None, // OR_ri = 397
4027
14
    CEFBS_None, // OR_ri_32 = 398
4028
14
    CEFBS_None, // OR_rr = 399
4029
14
    CEFBS_None, // OR_rr_32 = 400
4030
14
    CEFBS_None, // RET = 401
4031
14
    CEFBS_None, // SDIV_ri = 402
4032
14
    CEFBS_None, // SDIV_ri_32 = 403
4033
14
    CEFBS_None, // SDIV_rr = 404
4034
14
    CEFBS_None, // SDIV_rr_32 = 405
4035
14
    CEFBS_None, // SLL_ri = 406
4036
14
    CEFBS_None, // SLL_ri_32 = 407
4037
14
    CEFBS_None, // SLL_rr = 408
4038
14
    CEFBS_None, // SLL_rr_32 = 409
4039
14
    CEFBS_None, // SMOD_ri = 410
4040
14
    CEFBS_None, // SMOD_ri_32 = 411
4041
14
    CEFBS_None, // SMOD_rr = 412
4042
14
    CEFBS_None, // SMOD_rr_32 = 413
4043
14
    CEFBS_None, // SRA_ri = 414
4044
14
    CEFBS_None, // SRA_ri_32 = 415
4045
14
    CEFBS_None, // SRA_rr = 416
4046
14
    CEFBS_None, // SRA_rr_32 = 417
4047
14
    CEFBS_None, // SRL_ri = 418
4048
14
    CEFBS_None, // SRL_ri_32 = 419
4049
14
    CEFBS_None, // SRL_rr = 420
4050
14
    CEFBS_None, // SRL_rr_32 = 421
4051
14
    CEFBS_None, // STB = 422
4052
14
    CEFBS_None, // STB32 = 423
4053
14
    CEFBS_None, // STB_imm = 424
4054
14
    CEFBS_None, // STD = 425
4055
14
    CEFBS_None, // STD_imm = 426
4056
14
    CEFBS_None, // STH = 427
4057
14
    CEFBS_None, // STH32 = 428
4058
14
    CEFBS_None, // STH_imm = 429
4059
14
    CEFBS_None, // STW = 430
4060
14
    CEFBS_None, // STW32 = 431
4061
14
    CEFBS_None, // STW_imm = 432
4062
14
    CEFBS_None, // SUB_ri = 433
4063
14
    CEFBS_None, // SUB_ri_32 = 434
4064
14
    CEFBS_None, // SUB_rr = 435
4065
14
    CEFBS_None, // SUB_rr_32 = 436
4066
14
    CEFBS_None, // XADDD = 437
4067
14
    CEFBS_None, // XADDW = 438
4068
14
    CEFBS_None, // XADDW32 = 439
4069
14
    CEFBS_None, // XANDD = 440
4070
14
    CEFBS_None, // XANDW32 = 441
4071
14
    CEFBS_None, // XCHGD = 442
4072
14
    CEFBS_None, // XCHGW32 = 443
4073
14
    CEFBS_None, // XFADDD = 444
4074
14
    CEFBS_None, // XFADDW32 = 445
4075
14
    CEFBS_None, // XFANDD = 446
4076
14
    CEFBS_None, // XFANDW32 = 447
4077
14
    CEFBS_None, // XFORD = 448
4078
14
    CEFBS_None, // XFORW32 = 449
4079
14
    CEFBS_None, // XFXORD = 450
4080
14
    CEFBS_None, // XFXORW32 = 451
4081
14
    CEFBS_None, // XORD = 452
4082
14
    CEFBS_None, // XORW32 = 453
4083
14
    CEFBS_None, // XOR_ri = 454
4084
14
    CEFBS_None, // XOR_ri_32 = 455
4085
14
    CEFBS_None, // XOR_rr = 456
4086
14
    CEFBS_None, // XOR_rr_32 = 457
4087
14
    CEFBS_None, // XXORD = 458
4088
14
    CEFBS_None, // XXORW32 = 459
4089
14
  };
4090
4091
14
  assert(Opcode < 460);
4092
0
  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
4093
14
}
4094
4095
} // end namespace BPF_MC
4096
} // end namespace llvm
4097
#endif // GET_COMPUTE_FEATURES
4098
4099
#ifdef GET_AVAILABLE_OPCODE_CHECKER
4100
#undef GET_AVAILABLE_OPCODE_CHECKER
4101
namespace llvm {
4102
namespace BPF_MC {
4103
bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
4104
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
4105
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
4106
  FeatureBitset MissingFeatures =
4107
      (AvailableFeatures & RequiredFeatures) ^
4108
      RequiredFeatures;
4109
  return !MissingFeatures.any();
4110
}
4111
} // end namespace BPF_MC
4112
} // end namespace llvm
4113
#endif // GET_AVAILABLE_OPCODE_CHECKER
4114
4115
#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
4116
#undef ENABLE_INSTR_PREDICATE_VERIFIER
4117
#include <sstream>
4118
4119
namespace llvm {
4120
namespace BPF_MC {
4121
4122
#ifndef NDEBUG
4123
static const char *SubtargetFeatureNames[] = {
4124
  nullptr
4125
};
4126
4127
#endif // NDEBUG
4128
4129
void verifyInstructionPredicates(
4130
14
    unsigned Opcode, const FeatureBitset &Features) {
4131
14
#ifndef NDEBUG
4132
14
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
4133
14
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
4134
14
  FeatureBitset MissingFeatures =
4135
14
      (AvailableFeatures & RequiredFeatures) ^
4136
14
      RequiredFeatures;
4137
14
  if (MissingFeatures.any()) {
4138
0
    std::ostringstream Msg;
4139
0
    Msg << "Attempting to emit " << &BPFInstrNameData[BPFInstrNameIndices[Opcode]]
4140
0
        << " instruction but the ";
4141
0
    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
4142
0
      if (MissingFeatures.test(i))
4143
0
        Msg << SubtargetFeatureNames[i] << " ";
4144
0
    Msg << "predicate(s) are not met";
4145
0
    report_fatal_error(Msg.str().c_str());
4146
0
  }
4147
14
#endif // NDEBUG
4148
14
}
4149
} // end namespace BPF_MC
4150
} // end namespace llvm
4151
#endif // ENABLE_INSTR_PREDICATE_VERIFIER
4152