/src/build/lib/Target/BPF/BPFGenMCCodeEmitter.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Machine Code Emitter *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | uint64_t BPFMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, |
10 | | SmallVectorImpl<MCFixup> &Fixups, |
11 | 0 | const MCSubtargetInfo &STI) const { |
12 | 0 | static const uint64_t InstBits[] = { |
13 | 0 | UINT64_C(0), |
14 | 0 | UINT64_C(0), |
15 | 0 | UINT64_C(0), |
16 | 0 | UINT64_C(0), |
17 | 0 | UINT64_C(0), |
18 | 0 | UINT64_C(0), |
19 | 0 | UINT64_C(0), |
20 | 0 | UINT64_C(0), |
21 | 0 | UINT64_C(0), |
22 | 0 | UINT64_C(0), |
23 | 0 | UINT64_C(0), |
24 | 0 | UINT64_C(0), |
25 | 0 | UINT64_C(0), |
26 | 0 | UINT64_C(0), |
27 | 0 | UINT64_C(0), |
28 | 0 | UINT64_C(0), |
29 | 0 | UINT64_C(0), |
30 | 0 | UINT64_C(0), |
31 | 0 | UINT64_C(0), |
32 | 0 | UINT64_C(0), |
33 | 0 | UINT64_C(0), |
34 | 0 | UINT64_C(0), |
35 | 0 | UINT64_C(0), |
36 | 0 | UINT64_C(0), |
37 | 0 | UINT64_C(0), |
38 | 0 | UINT64_C(0), |
39 | 0 | UINT64_C(0), |
40 | 0 | UINT64_C(0), |
41 | 0 | UINT64_C(0), |
42 | 0 | UINT64_C(0), |
43 | 0 | UINT64_C(0), |
44 | 0 | UINT64_C(0), |
45 | 0 | UINT64_C(0), |
46 | 0 | UINT64_C(0), |
47 | 0 | UINT64_C(0), |
48 | 0 | UINT64_C(0), |
49 | 0 | UINT64_C(0), |
50 | 0 | UINT64_C(0), |
51 | 0 | UINT64_C(0), |
52 | 0 | UINT64_C(0), |
53 | 0 | UINT64_C(0), |
54 | 0 | UINT64_C(0), |
55 | 0 | UINT64_C(0), |
56 | 0 | UINT64_C(0), |
57 | 0 | UINT64_C(0), |
58 | 0 | UINT64_C(0), |
59 | 0 | UINT64_C(0), |
60 | 0 | UINT64_C(0), |
61 | 0 | UINT64_C(0), |
62 | 0 | UINT64_C(0), |
63 | 0 | UINT64_C(0), |
64 | 0 | UINT64_C(0), |
65 | 0 | UINT64_C(0), |
66 | 0 | UINT64_C(0), |
67 | 0 | UINT64_C(0), |
68 | 0 | UINT64_C(0), |
69 | 0 | UINT64_C(0), |
70 | 0 | UINT64_C(0), |
71 | 0 | UINT64_C(0), |
72 | 0 | UINT64_C(0), |
73 | 0 | UINT64_C(0), |
74 | 0 | UINT64_C(0), |
75 | 0 | UINT64_C(0), |
76 | 0 | UINT64_C(0), |
77 | 0 | UINT64_C(0), |
78 | 0 | UINT64_C(0), |
79 | 0 | UINT64_C(0), |
80 | 0 | UINT64_C(0), |
81 | 0 | UINT64_C(0), |
82 | 0 | UINT64_C(0), |
83 | 0 | UINT64_C(0), |
84 | 0 | UINT64_C(0), |
85 | 0 | UINT64_C(0), |
86 | 0 | UINT64_C(0), |
87 | 0 | UINT64_C(0), |
88 | 0 | UINT64_C(0), |
89 | 0 | UINT64_C(0), |
90 | 0 | UINT64_C(0), |
91 | 0 | UINT64_C(0), |
92 | 0 | UINT64_C(0), |
93 | 0 | UINT64_C(0), |
94 | 0 | UINT64_C(0), |
95 | 0 | UINT64_C(0), |
96 | 0 | UINT64_C(0), |
97 | 0 | UINT64_C(0), |
98 | 0 | UINT64_C(0), |
99 | 0 | UINT64_C(0), |
100 | 0 | UINT64_C(0), |
101 | 0 | UINT64_C(0), |
102 | 0 | UINT64_C(0), |
103 | 0 | UINT64_C(0), |
104 | 0 | UINT64_C(0), |
105 | 0 | UINT64_C(0), |
106 | 0 | UINT64_C(0), |
107 | 0 | UINT64_C(0), |
108 | 0 | UINT64_C(0), |
109 | 0 | UINT64_C(0), |
110 | 0 | UINT64_C(0), |
111 | 0 | UINT64_C(0), |
112 | 0 | UINT64_C(0), |
113 | 0 | UINT64_C(0), |
114 | 0 | UINT64_C(0), |
115 | 0 | UINT64_C(0), |
116 | 0 | UINT64_C(0), |
117 | 0 | UINT64_C(0), |
118 | 0 | UINT64_C(0), |
119 | 0 | UINT64_C(0), |
120 | 0 | UINT64_C(0), |
121 | 0 | UINT64_C(0), |
122 | 0 | UINT64_C(0), |
123 | 0 | UINT64_C(0), |
124 | 0 | UINT64_C(0), |
125 | 0 | UINT64_C(0), |
126 | 0 | UINT64_C(0), |
127 | 0 | UINT64_C(0), |
128 | 0 | UINT64_C(0), |
129 | 0 | UINT64_C(0), |
130 | 0 | UINT64_C(0), |
131 | 0 | UINT64_C(0), |
132 | 0 | UINT64_C(0), |
133 | 0 | UINT64_C(0), |
134 | 0 | UINT64_C(0), |
135 | 0 | UINT64_C(0), |
136 | 0 | UINT64_C(0), |
137 | 0 | UINT64_C(0), |
138 | 0 | UINT64_C(0), |
139 | 0 | UINT64_C(0), |
140 | 0 | UINT64_C(0), |
141 | 0 | UINT64_C(0), |
142 | 0 | UINT64_C(0), |
143 | 0 | UINT64_C(0), |
144 | 0 | UINT64_C(0), |
145 | 0 | UINT64_C(0), |
146 | 0 | UINT64_C(0), |
147 | 0 | UINT64_C(0), |
148 | 0 | UINT64_C(0), |
149 | 0 | UINT64_C(0), |
150 | 0 | UINT64_C(0), |
151 | 0 | UINT64_C(0), |
152 | 0 | UINT64_C(0), |
153 | 0 | UINT64_C(0), |
154 | 0 | UINT64_C(0), |
155 | 0 | UINT64_C(0), |
156 | 0 | UINT64_C(0), |
157 | 0 | UINT64_C(0), |
158 | 0 | UINT64_C(0), |
159 | 0 | UINT64_C(0), |
160 | 0 | UINT64_C(0), |
161 | 0 | UINT64_C(0), |
162 | 0 | UINT64_C(0), |
163 | 0 | UINT64_C(0), |
164 | 0 | UINT64_C(0), |
165 | 0 | UINT64_C(0), |
166 | 0 | UINT64_C(0), |
167 | 0 | UINT64_C(0), |
168 | 0 | UINT64_C(0), |
169 | 0 | UINT64_C(0), |
170 | 0 | UINT64_C(0), |
171 | 0 | UINT64_C(0), |
172 | 0 | UINT64_C(0), |
173 | 0 | UINT64_C(0), |
174 | 0 | UINT64_C(0), |
175 | 0 | UINT64_C(0), |
176 | 0 | UINT64_C(0), |
177 | 0 | UINT64_C(0), |
178 | 0 | UINT64_C(0), |
179 | 0 | UINT64_C(0), |
180 | 0 | UINT64_C(0), |
181 | 0 | UINT64_C(0), |
182 | 0 | UINT64_C(0), |
183 | 0 | UINT64_C(0), |
184 | 0 | UINT64_C(0), |
185 | 0 | UINT64_C(0), |
186 | 0 | UINT64_C(0), |
187 | 0 | UINT64_C(0), |
188 | 0 | UINT64_C(0), |
189 | 0 | UINT64_C(0), |
190 | 0 | UINT64_C(0), |
191 | 0 | UINT64_C(0), |
192 | 0 | UINT64_C(0), |
193 | 0 | UINT64_C(0), |
194 | 0 | UINT64_C(0), |
195 | 0 | UINT64_C(0), |
196 | 0 | UINT64_C(0), |
197 | 0 | UINT64_C(0), |
198 | 0 | UINT64_C(0), |
199 | 0 | UINT64_C(0), |
200 | 0 | UINT64_C(0), |
201 | 0 | UINT64_C(0), |
202 | 0 | UINT64_C(0), |
203 | 0 | UINT64_C(0), |
204 | 0 | UINT64_C(0), |
205 | 0 | UINT64_C(0), |
206 | 0 | UINT64_C(0), |
207 | 0 | UINT64_C(0), |
208 | 0 | UINT64_C(0), |
209 | 0 | UINT64_C(0), |
210 | 0 | UINT64_C(0), |
211 | 0 | UINT64_C(0), |
212 | 0 | UINT64_C(0), |
213 | 0 | UINT64_C(0), |
214 | 0 | UINT64_C(0), |
215 | 0 | UINT64_C(0), |
216 | 0 | UINT64_C(0), |
217 | 0 | UINT64_C(0), |
218 | 0 | UINT64_C(0), |
219 | 0 | UINT64_C(0), |
220 | 0 | UINT64_C(0), |
221 | 0 | UINT64_C(0), |
222 | 0 | UINT64_C(0), |
223 | 0 | UINT64_C(0), |
224 | 0 | UINT64_C(0), |
225 | 0 | UINT64_C(0), |
226 | 0 | UINT64_C(0), |
227 | 0 | UINT64_C(0), |
228 | 0 | UINT64_C(0), |
229 | 0 | UINT64_C(0), |
230 | 0 | UINT64_C(0), |
231 | 0 | UINT64_C(0), |
232 | 0 | UINT64_C(0), |
233 | 0 | UINT64_C(0), |
234 | 0 | UINT64_C(0), |
235 | 0 | UINT64_C(0), |
236 | 0 | UINT64_C(0), |
237 | 0 | UINT64_C(0), |
238 | 0 | UINT64_C(0), |
239 | 0 | UINT64_C(0), |
240 | 0 | UINT64_C(0), |
241 | 0 | UINT64_C(0), |
242 | 0 | UINT64_C(0), |
243 | 0 | UINT64_C(0), |
244 | 0 | UINT64_C(0), |
245 | 0 | UINT64_C(0), |
246 | 0 | UINT64_C(0), |
247 | 0 | UINT64_C(0), |
248 | 0 | UINT64_C(0), |
249 | 0 | UINT64_C(0), |
250 | 0 | UINT64_C(0), |
251 | 0 | UINT64_C(0), |
252 | 0 | UINT64_C(0), |
253 | 0 | UINT64_C(0), |
254 | 0 | UINT64_C(0), |
255 | 0 | UINT64_C(0), |
256 | 0 | UINT64_C(0), |
257 | 0 | UINT64_C(0), |
258 | 0 | UINT64_C(0), |
259 | 0 | UINT64_C(0), |
260 | 0 | UINT64_C(0), |
261 | 0 | UINT64_C(0), |
262 | 0 | UINT64_C(0), |
263 | 0 | UINT64_C(0), |
264 | 0 | UINT64_C(0), |
265 | 0 | UINT64_C(0), |
266 | 0 | UINT64_C(0), |
267 | 0 | UINT64_C(0), |
268 | 0 | UINT64_C(0), |
269 | 0 | UINT64_C(0), |
270 | 0 | UINT64_C(0), |
271 | 0 | UINT64_C(0), |
272 | 0 | UINT64_C(0), |
273 | 0 | UINT64_C(0), |
274 | 0 | UINT64_C(0), |
275 | 0 | UINT64_C(0), |
276 | 0 | UINT64_C(0), |
277 | 0 | UINT64_C(0), |
278 | 0 | UINT64_C(0), |
279 | 0 | UINT64_C(0), |
280 | 0 | UINT64_C(0), |
281 | 0 | UINT64_C(0), |
282 | 0 | UINT64_C(0), |
283 | 0 | UINT64_C(0), |
284 | 0 | UINT64_C(0), |
285 | 0 | UINT64_C(0), |
286 | 0 | UINT64_C(0), |
287 | 0 | UINT64_C(0), |
288 | 0 | UINT64_C(0), |
289 | 0 | UINT64_C(0), |
290 | 0 | UINT64_C(0), |
291 | 0 | UINT64_C(0), |
292 | 0 | UINT64_C(0), |
293 | 0 | UINT64_C(0), |
294 | 0 | UINT64_C(0), |
295 | 0 | UINT64_C(0), |
296 | 0 | UINT64_C(504403158265495552), // ADD_ri |
297 | 0 | UINT64_C(288230376151711744), // ADD_ri_32 |
298 | 0 | UINT64_C(1080863910568919040), // ADD_rr |
299 | 0 | UINT64_C(864691128455135232), // ADD_rr_32 |
300 | 0 | UINT64_C(6269010681299730432), // AND_ri |
301 | 0 | UINT64_C(6052837899185946624), // AND_ri_32 |
302 | 0 | UINT64_C(6845471433603153920), // AND_rr |
303 | 0 | UINT64_C(6629298651489370112), // AND_rr_32 |
304 | 0 | UINT64_C(15852670688344145936), // BE16 |
305 | 0 | UINT64_C(15852670688344145952), // BE32 |
306 | 0 | UINT64_C(15852670688344145984), // BE64 |
307 | 0 | UINT64_C(15492382718154506256), // BSWAP16 |
308 | 0 | UINT64_C(15492382718154506272), // BSWAP32 |
309 | 0 | UINT64_C(15492382718154506304), // BSWAP64 |
310 | 0 | UINT64_C(15780613094306218225), // CMPXCHGD |
311 | 0 | UINT64_C(14051230837395947761), // CMPXCHGW32 |
312 | 0 | UINT64_C(6917529027641081856), // CORE_LD32 |
313 | 0 | UINT64_C(6917529027641081856), // CORE_LD64 |
314 | 0 | UINT64_C(7998392938210000896), // CORE_SHIFT |
315 | 0 | UINT64_C(6917529027641081856), // CORE_ST |
316 | 0 | UINT64_C(3963167672086036480), // DIV_ri |
317 | 0 | UINT64_C(3746994889972252672), // DIV_ri_32 |
318 | 0 | UINT64_C(4539628424389459968), // DIV_rr |
319 | 0 | UINT64_C(4323455642275676160), // DIV_rr_32 |
320 | 0 | UINT64_C(9583660007044415488), // JAL |
321 | 0 | UINT64_C(10160120759347838976), // JALX |
322 | 0 | UINT64_C(1513209474796486656), // JEQ_ri |
323 | 0 | UINT64_C(1585267068834414592), // JEQ_ri_32 |
324 | 0 | UINT64_C(2089670227099910144), // JEQ_rr |
325 | 0 | UINT64_C(2161727821137838080), // JEQ_rr_32 |
326 | 0 | UINT64_C(360287970189639680), // JMP |
327 | 0 | UINT64_C(432345564227567616), // JMPL |
328 | 0 | UINT64_C(6124895493223874560), // JNE_ri |
329 | 0 | UINT64_C(6196953087261802496), // JNE_ri_32 |
330 | 0 | UINT64_C(6701356245527298048), // JNE_rr |
331 | 0 | UINT64_C(6773413839565225984), // JNE_rr_32 |
332 | 0 | UINT64_C(4971973988617027584), // JSET_ri |
333 | 0 | UINT64_C(5044031582654955520), // JSET_ri_32 |
334 | 0 | UINT64_C(5548434740920451072), // JSET_rr |
335 | 0 | UINT64_C(5620492334958379008), // JSET_rr_32 |
336 | 0 | UINT64_C(8430738502437568512), // JSGE_ri |
337 | 0 | UINT64_C(8502796096475496448), // JSGE_ri_32 |
338 | 0 | UINT64_C(9007199254740992000), // JSGE_rr |
339 | 0 | UINT64_C(9079256848778919936), // JSGE_rr_32 |
340 | 0 | UINT64_C(7277816997830721536), // JSGT_ri |
341 | 0 | UINT64_C(7349874591868649472), // JSGT_ri_32 |
342 | 0 | UINT64_C(7854277750134145024), // JSGT_rr |
343 | 0 | UINT64_C(7926335344172072960), // JSGT_rr_32 |
344 | 0 | UINT64_C(15348267530078650368), // JSLE_ri |
345 | 0 | UINT64_C(15420325124116578304), // JSLE_ri_32 |
346 | 0 | UINT64_C(15924728282382073856), // JSLE_rr |
347 | 0 | UINT64_C(15996785876420001792), // JSLE_rr_32 |
348 | 0 | UINT64_C(14195346025471803392), // JSLT_ri |
349 | 0 | UINT64_C(14267403619509731328), // JSLT_ri_32 |
350 | 0 | UINT64_C(14771806777775226880), // JSLT_rr |
351 | 0 | UINT64_C(14843864371813154816), // JSLT_rr_32 |
352 | 0 | UINT64_C(3819052484010180608), // JUGE_ri |
353 | 0 | UINT64_C(3891110078048108544), // JUGE_ri_32 |
354 | 0 | UINT64_C(4395513236313604096), // JUGE_rr |
355 | 0 | UINT64_C(4467570830351532032), // JUGE_rr_32 |
356 | 0 | UINT64_C(2666130979403333632), // JUGT_ri |
357 | 0 | UINT64_C(2738188573441261568), // JUGT_ri_32 |
358 | 0 | UINT64_C(3242591731706757120), // JUGT_rr |
359 | 0 | UINT64_C(3314649325744685056), // JUGT_rr_32 |
360 | 0 | UINT64_C(13042424520864956416), // JULE_ri |
361 | 0 | UINT64_C(13114482114902884352), // JULE_ri_32 |
362 | 0 | UINT64_C(13618885273168379904), // JULE_rr |
363 | 0 | UINT64_C(13690942867206307840), // JULE_rr_32 |
364 | 0 | UINT64_C(11889503016258109440), // JULT_ri |
365 | 0 | UINT64_C(11961560610296037376), // JULT_ri_32 |
366 | 0 | UINT64_C(12465963768561532928), // JULT_rr |
367 | 0 | UINT64_C(12538021362599460864), // JULT_rr_32 |
368 | 0 | UINT64_C(8142508126285856768), // LDB |
369 | 0 | UINT64_C(8142508126285856768), // LDB32 |
370 | 0 | UINT64_C(10448351135499550720), // LDBSX |
371 | 0 | UINT64_C(8718968878589280256), // LDD |
372 | 0 | UINT64_C(7566047373982433280), // LDH |
373 | 0 | UINT64_C(7566047373982433280), // LDH32 |
374 | 0 | UINT64_C(9871890383196127232), // LDHSX |
375 | 0 | UINT64_C(6989586621679009792), // LDW |
376 | 0 | UINT64_C(6989586621679009792), // LDW32 |
377 | 0 | UINT64_C(9295429630892703744), // LDWSX |
378 | 0 | UINT64_C(3458764513820540928), // LD_ABS_B |
379 | 0 | UINT64_C(2882303761517117440), // LD_ABS_H |
380 | 0 | UINT64_C(2305843009213693952), // LD_ABS_W |
381 | 0 | UINT64_C(5764607523034234880), // LD_IND_B |
382 | 0 | UINT64_C(5188146770730811392), // LD_IND_H |
383 | 0 | UINT64_C(4611686018427387904), // LD_IND_W |
384 | 0 | UINT64_C(1729382256910270464), // LD_imm64 |
385 | 0 | UINT64_C(1729382256910270464), // LD_pseudo |
386 | 0 | UINT64_C(15276209936040722448), // LE16 |
387 | 0 | UINT64_C(15276209936040722464), // LE32 |
388 | 0 | UINT64_C(15276209936040722496), // LE64 |
389 | 0 | UINT64_C(10880696699727118336), // MOD_ri |
390 | 0 | UINT64_C(10664523917613334528), // MOD_ri_32 |
391 | 0 | UINT64_C(11457157452030541824), // MOD_rr |
392 | 0 | UINT64_C(11240984669916758016), // MOD_rr_32 |
393 | 0 | UINT64_C(13763000529963712512), // MOVSX_rr_16 |
394 | 0 | UINT64_C(13763000598683189248), // MOVSX_rr_32 |
395 | 0 | UINT64_C(13546827747849928704), // MOVSX_rr_32_16 |
396 | 0 | UINT64_C(13546827713490190336), // MOVSX_rr_32_8 |
397 | 0 | UINT64_C(13763000495603974144), // MOVSX_rr_8 |
398 | 0 | UINT64_C(13546827679130451968), // MOV_32_64 |
399 | 0 | UINT64_C(13186539708940812288), // MOV_ri |
400 | 0 | UINT64_C(12970366926827028480), // MOV_ri_32 |
401 | 0 | UINT64_C(13763000461244235776), // MOV_rr |
402 | 0 | UINT64_C(13546827679130451968), // MOV_rr_32 |
403 | 0 | UINT64_C(2810246167479189504), // MUL_ri |
404 | 0 | UINT64_C(2594073385365405696), // MUL_ri_32 |
405 | 0 | UINT64_C(3386706919782612992), // MUL_rr |
406 | 0 | UINT64_C(3170534137668829184), // MUL_rr_32 |
407 | 0 | UINT64_C(9511602413006487552), // NEG_32 |
408 | 0 | UINT64_C(9727775195120271360), // NEG_64 |
409 | 0 | UINT64_C(13763000461244235776), // NOP |
410 | 0 | UINT64_C(5116089176692883456), // OR_ri |
411 | 0 | UINT64_C(4899916394579099648), // OR_ri_32 |
412 | 0 | UINT64_C(5692549928996306944), // OR_rr |
413 | 0 | UINT64_C(5476377146882523136), // OR_rr_32 |
414 | 0 | UINT64_C(10736581511651262464), // RET |
415 | 0 | UINT64_C(3963167676381003776), // SDIV_ri |
416 | 0 | UINT64_C(3746994894267219968), // SDIV_ri_32 |
417 | 0 | UINT64_C(4539628428684427264), // SDIV_rr |
418 | 0 | UINT64_C(4323455646570643456), // SDIV_rr_32 |
419 | 0 | UINT64_C(7421932185906577408), // SLL_ri |
420 | 0 | UINT64_C(7205759403792793600), // SLL_ri_32 |
421 | 0 | UINT64_C(7998392938210000896), // SLL_rr |
422 | 0 | UINT64_C(7782220156096217088), // SLL_rr_32 |
423 | 0 | UINT64_C(10880696704022085632), // SMOD_ri |
424 | 0 | UINT64_C(10664523921908301824), // SMOD_ri_32 |
425 | 0 | UINT64_C(11457157456325509120), // SMOD_rr |
426 | 0 | UINT64_C(11240984674211725312), // SMOD_rr_32 |
427 | 0 | UINT64_C(14339461213547659264), // SRA_ri |
428 | 0 | UINT64_C(14123288431433875456), // SRA_ri_32 |
429 | 0 | UINT64_C(14915921965851082752), // SRA_rr |
430 | 0 | UINT64_C(14699749183737298944), // SRA_rr_32 |
431 | 0 | UINT64_C(8574853690513424384), // SRL_ri |
432 | 0 | UINT64_C(8358680908399640576), // SRL_ri_32 |
433 | 0 | UINT64_C(9151314442816847872), // SRL_rr |
434 | 0 | UINT64_C(8935141660703064064), // SRL_rr_32 |
435 | 0 | UINT64_C(8286623314361712640), // STB |
436 | 0 | UINT64_C(8286623314361712640), // STB32 |
437 | 0 | UINT64_C(8214565720323784704), // STB_imm |
438 | 0 | UINT64_C(8863084066665136128), // STD |
439 | 0 | UINT64_C(8791026472627208192), // STD_imm |
440 | 0 | UINT64_C(7710162562058289152), // STH |
441 | 0 | UINT64_C(7710162562058289152), // STH32 |
442 | 0 | UINT64_C(7638104968020361216), // STH_imm |
443 | 0 | UINT64_C(7133701809754865664), // STW |
444 | 0 | UINT64_C(7133701809754865664), // STW32 |
445 | 0 | UINT64_C(7061644215716937728), // STW_imm |
446 | 0 | UINT64_C(1657324662872342528), // SUB_ri |
447 | 0 | UINT64_C(1441151880758558720), // SUB_ri_32 |
448 | 0 | UINT64_C(2233785415175766016), // SUB_rr |
449 | 0 | UINT64_C(2017612633061982208), // SUB_rr_32 |
450 | 0 | UINT64_C(15780613094306217984), // XADDD |
451 | 0 | UINT64_C(14051230837395947520), // XADDW |
452 | 0 | UINT64_C(14051230837395947520), // XADDW32 |
453 | 0 | UINT64_C(15780613094306218064), // XANDD |
454 | 0 | UINT64_C(14051230837395947600), // XANDW32 |
455 | 0 | UINT64_C(15780613094306218209), // XCHGD |
456 | 0 | UINT64_C(14051230837395947745), // XCHGW32 |
457 | 0 | UINT64_C(15780613094306217985), // XFADDD |
458 | 0 | UINT64_C(14051230837395947521), // XFADDW32 |
459 | 0 | UINT64_C(15780613094306218065), // XFANDD |
460 | 0 | UINT64_C(14051230837395947601), // XFANDW32 |
461 | 0 | UINT64_C(15780613094306218049), // XFORD |
462 | 0 | UINT64_C(14051230837395947585), // XFORW32 |
463 | 0 | UINT64_C(15780613094306218145), // XFXORD |
464 | 0 | UINT64_C(14051230837395947681), // XFXORW32 |
465 | 0 | UINT64_C(15780613094306218048), // XORD |
466 | 0 | UINT64_C(14051230837395947584), // XORW32 |
467 | 0 | UINT64_C(12033618204333965312), // XOR_ri |
468 | 0 | UINT64_C(11817445422220181504), // XOR_ri_32 |
469 | 0 | UINT64_C(12610078956637388800), // XOR_rr |
470 | 0 | UINT64_C(12393906174523604992), // XOR_rr_32 |
471 | 0 | UINT64_C(15780613094306218144), // XXORD |
472 | 0 | UINT64_C(14051230837395947680), // XXORW32 |
473 | 0 | UINT64_C(0) |
474 | 0 | }; |
475 | 0 | const unsigned opcode = MI.getOpcode(); |
476 | 0 | uint64_t Value = InstBits[opcode]; |
477 | 0 | uint64_t op = 0; |
478 | 0 | (void)op; // suppress warning |
479 | 0 | switch (opcode) { |
480 | 0 | case BPF::CORE_LD32: |
481 | 0 | case BPF::CORE_LD64: |
482 | 0 | case BPF::CORE_ST: |
483 | 0 | case BPF::NOP: |
484 | 0 | case BPF::RET: { |
485 | 0 | break; |
486 | 0 | } |
487 | 0 | case BPF::JAL: |
488 | 0 | case BPF::JALX: |
489 | 0 | case BPF::JMPL: { |
490 | | // op: BrDst |
491 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
492 | 0 | op &= UINT64_C(4294967295); |
493 | 0 | Value |= op; |
494 | 0 | break; |
495 | 0 | } |
496 | 0 | case BPF::JMP: { |
497 | | // op: BrDst |
498 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
499 | 0 | op &= UINT64_C(65535); |
500 | 0 | op <<= 32; |
501 | 0 | Value |= op; |
502 | 0 | break; |
503 | 0 | } |
504 | 0 | case BPF::STB_imm: |
505 | 0 | case BPF::STD_imm: |
506 | 0 | case BPF::STH_imm: |
507 | 0 | case BPF::STW_imm: { |
508 | | // op: addr |
509 | 0 | op = getMemoryOpValue(MI, 1, Fixups, STI); |
510 | 0 | op &= UINT64_C(1048575); |
511 | 0 | op <<= 32; |
512 | 0 | Value |= op; |
513 | | // op: imm |
514 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
515 | 0 | op &= UINT64_C(4294967295); |
516 | 0 | Value |= op; |
517 | 0 | break; |
518 | 0 | } |
519 | 0 | case BPF::BE16: |
520 | 0 | case BPF::BE32: |
521 | 0 | case BPF::BE64: |
522 | 0 | case BPF::BSWAP16: |
523 | 0 | case BPF::BSWAP32: |
524 | 0 | case BPF::BSWAP64: |
525 | 0 | case BPF::LE16: |
526 | 0 | case BPF::LE32: |
527 | 0 | case BPF::LE64: |
528 | 0 | case BPF::NEG_32: |
529 | 0 | case BPF::NEG_64: { |
530 | | // op: dst |
531 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
532 | 0 | op &= UINT64_C(15); |
533 | 0 | op <<= 48; |
534 | 0 | Value |= op; |
535 | 0 | break; |
536 | 0 | } |
537 | 0 | case BPF::JEQ_ri: |
538 | 0 | case BPF::JEQ_ri_32: |
539 | 0 | case BPF::JNE_ri: |
540 | 0 | case BPF::JNE_ri_32: |
541 | 0 | case BPF::JSET_ri: |
542 | 0 | case BPF::JSET_ri_32: |
543 | 0 | case BPF::JSGE_ri: |
544 | 0 | case BPF::JSGE_ri_32: |
545 | 0 | case BPF::JSGT_ri: |
546 | 0 | case BPF::JSGT_ri_32: |
547 | 0 | case BPF::JSLE_ri: |
548 | 0 | case BPF::JSLE_ri_32: |
549 | 0 | case BPF::JSLT_ri: |
550 | 0 | case BPF::JSLT_ri_32: |
551 | 0 | case BPF::JUGE_ri: |
552 | 0 | case BPF::JUGE_ri_32: |
553 | 0 | case BPF::JUGT_ri: |
554 | 0 | case BPF::JUGT_ri_32: |
555 | 0 | case BPF::JULE_ri: |
556 | 0 | case BPF::JULE_ri_32: |
557 | 0 | case BPF::JULT_ri: |
558 | 0 | case BPF::JULT_ri_32: { |
559 | | // op: dst |
560 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
561 | 0 | op &= UINT64_C(15); |
562 | 0 | op <<= 48; |
563 | 0 | Value |= op; |
564 | | // op: BrDst |
565 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
566 | 0 | op &= UINT64_C(65535); |
567 | 0 | op <<= 32; |
568 | 0 | Value |= op; |
569 | | // op: imm |
570 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
571 | 0 | op &= UINT64_C(4294967295); |
572 | 0 | Value |= op; |
573 | 0 | break; |
574 | 0 | } |
575 | 0 | case BPF::LDB: |
576 | 0 | case BPF::LDB32: |
577 | 0 | case BPF::LDBSX: |
578 | 0 | case BPF::LDD: |
579 | 0 | case BPF::LDH: |
580 | 0 | case BPF::LDH32: |
581 | 0 | case BPF::LDHSX: |
582 | 0 | case BPF::LDW: |
583 | 0 | case BPF::LDW32: |
584 | 0 | case BPF::LDWSX: { |
585 | | // op: dst |
586 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
587 | 0 | op &= UINT64_C(15); |
588 | 0 | op <<= 48; |
589 | 0 | Value |= op; |
590 | | // op: addr |
591 | 0 | op = getMemoryOpValue(MI, 1, Fixups, STI); |
592 | 0 | Value |= (op & UINT64_C(983040)) << 36; |
593 | 0 | Value |= (op & UINT64_C(65535)) << 32; |
594 | 0 | break; |
595 | 0 | } |
596 | 0 | case BPF::LD_imm64: |
597 | 0 | case BPF::MOV_ri: |
598 | 0 | case BPF::MOV_ri_32: { |
599 | | // op: dst |
600 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
601 | 0 | op &= UINT64_C(15); |
602 | 0 | op <<= 48; |
603 | 0 | Value |= op; |
604 | | // op: imm |
605 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
606 | 0 | op &= UINT64_C(4294967295); |
607 | 0 | Value |= op; |
608 | 0 | break; |
609 | 0 | } |
610 | 0 | case BPF::ADD_ri: |
611 | 0 | case BPF::ADD_ri_32: |
612 | 0 | case BPF::AND_ri: |
613 | 0 | case BPF::AND_ri_32: |
614 | 0 | case BPF::DIV_ri: |
615 | 0 | case BPF::DIV_ri_32: |
616 | 0 | case BPF::MOD_ri: |
617 | 0 | case BPF::MOD_ri_32: |
618 | 0 | case BPF::MUL_ri: |
619 | 0 | case BPF::MUL_ri_32: |
620 | 0 | case BPF::OR_ri: |
621 | 0 | case BPF::OR_ri_32: |
622 | 0 | case BPF::SDIV_ri: |
623 | 0 | case BPF::SDIV_ri_32: |
624 | 0 | case BPF::SLL_ri: |
625 | 0 | case BPF::SLL_ri_32: |
626 | 0 | case BPF::SMOD_ri: |
627 | 0 | case BPF::SMOD_ri_32: |
628 | 0 | case BPF::SRA_ri: |
629 | 0 | case BPF::SRA_ri_32: |
630 | 0 | case BPF::SRL_ri: |
631 | 0 | case BPF::SRL_ri_32: |
632 | 0 | case BPF::SUB_ri: |
633 | 0 | case BPF::SUB_ri_32: |
634 | 0 | case BPF::XOR_ri: |
635 | 0 | case BPF::XOR_ri_32: { |
636 | | // op: dst |
637 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
638 | 0 | op &= UINT64_C(15); |
639 | 0 | op <<= 48; |
640 | 0 | Value |= op; |
641 | | // op: imm |
642 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
643 | 0 | op &= UINT64_C(4294967295); |
644 | 0 | Value |= op; |
645 | 0 | break; |
646 | 0 | } |
647 | 0 | case BPF::LD_pseudo: { |
648 | | // op: dst |
649 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
650 | 0 | op &= UINT64_C(15); |
651 | 0 | op <<= 48; |
652 | 0 | Value |= op; |
653 | | // op: imm |
654 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
655 | 0 | op &= UINT64_C(4294967295); |
656 | 0 | Value |= op; |
657 | | // op: pseudo |
658 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
659 | 0 | op &= UINT64_C(15); |
660 | 0 | op <<= 52; |
661 | 0 | Value |= op; |
662 | 0 | break; |
663 | 0 | } |
664 | 0 | case BPF::MOVSX_rr_8: |
665 | 0 | case BPF::MOVSX_rr_16: |
666 | 0 | case BPF::MOVSX_rr_32: |
667 | 0 | case BPF::MOVSX_rr_32_8: |
668 | 0 | case BPF::MOVSX_rr_32_16: |
669 | 0 | case BPF::MOV_32_64: |
670 | 0 | case BPF::MOV_rr: |
671 | 0 | case BPF::MOV_rr_32: { |
672 | | // op: dst |
673 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
674 | 0 | op &= UINT64_C(15); |
675 | 0 | op <<= 48; |
676 | 0 | Value |= op; |
677 | | // op: src |
678 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
679 | 0 | op &= UINT64_C(15); |
680 | 0 | op <<= 52; |
681 | 0 | Value |= op; |
682 | 0 | break; |
683 | 0 | } |
684 | 0 | case BPF::JEQ_rr: |
685 | 0 | case BPF::JEQ_rr_32: |
686 | 0 | case BPF::JNE_rr: |
687 | 0 | case BPF::JNE_rr_32: |
688 | 0 | case BPF::JSET_rr: |
689 | 0 | case BPF::JSET_rr_32: |
690 | 0 | case BPF::JSGE_rr: |
691 | 0 | case BPF::JSGE_rr_32: |
692 | 0 | case BPF::JSGT_rr: |
693 | 0 | case BPF::JSGT_rr_32: |
694 | 0 | case BPF::JSLE_rr: |
695 | 0 | case BPF::JSLE_rr_32: |
696 | 0 | case BPF::JSLT_rr: |
697 | 0 | case BPF::JSLT_rr_32: |
698 | 0 | case BPF::JUGE_rr: |
699 | 0 | case BPF::JUGE_rr_32: |
700 | 0 | case BPF::JUGT_rr: |
701 | 0 | case BPF::JUGT_rr_32: |
702 | 0 | case BPF::JULE_rr: |
703 | 0 | case BPF::JULE_rr_32: |
704 | 0 | case BPF::JULT_rr: |
705 | 0 | case BPF::JULT_rr_32: { |
706 | | // op: dst |
707 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
708 | 0 | op &= UINT64_C(15); |
709 | 0 | op <<= 48; |
710 | 0 | Value |= op; |
711 | | // op: src |
712 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
713 | 0 | op &= UINT64_C(15); |
714 | 0 | op <<= 52; |
715 | 0 | Value |= op; |
716 | | // op: BrDst |
717 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
718 | 0 | op &= UINT64_C(65535); |
719 | 0 | op <<= 32; |
720 | 0 | Value |= op; |
721 | 0 | break; |
722 | 0 | } |
723 | 0 | case BPF::ADD_rr: |
724 | 0 | case BPF::ADD_rr_32: |
725 | 0 | case BPF::AND_rr: |
726 | 0 | case BPF::AND_rr_32: |
727 | 0 | case BPF::CORE_SHIFT: |
728 | 0 | case BPF::DIV_rr: |
729 | 0 | case BPF::DIV_rr_32: |
730 | 0 | case BPF::MOD_rr: |
731 | 0 | case BPF::MOD_rr_32: |
732 | 0 | case BPF::MUL_rr: |
733 | 0 | case BPF::MUL_rr_32: |
734 | 0 | case BPF::OR_rr: |
735 | 0 | case BPF::OR_rr_32: |
736 | 0 | case BPF::SDIV_rr: |
737 | 0 | case BPF::SDIV_rr_32: |
738 | 0 | case BPF::SLL_rr: |
739 | 0 | case BPF::SLL_rr_32: |
740 | 0 | case BPF::SMOD_rr: |
741 | 0 | case BPF::SMOD_rr_32: |
742 | 0 | case BPF::SRA_rr: |
743 | 0 | case BPF::SRA_rr_32: |
744 | 0 | case BPF::SRL_rr: |
745 | 0 | case BPF::SRL_rr_32: |
746 | 0 | case BPF::SUB_rr: |
747 | 0 | case BPF::SUB_rr_32: |
748 | 0 | case BPF::XOR_rr: |
749 | 0 | case BPF::XOR_rr_32: { |
750 | | // op: dst |
751 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
752 | 0 | op &= UINT64_C(15); |
753 | 0 | op <<= 48; |
754 | 0 | Value |= op; |
755 | | // op: src |
756 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
757 | 0 | op &= UINT64_C(15); |
758 | 0 | op <<= 52; |
759 | 0 | Value |= op; |
760 | 0 | break; |
761 | 0 | } |
762 | 0 | case BPF::XADDD: |
763 | 0 | case BPF::XADDW: |
764 | 0 | case BPF::XADDW32: |
765 | 0 | case BPF::XANDD: |
766 | 0 | case BPF::XANDW32: |
767 | 0 | case BPF::XCHGD: |
768 | 0 | case BPF::XCHGW32: |
769 | 0 | case BPF::XFADDD: |
770 | 0 | case BPF::XFADDW32: |
771 | 0 | case BPF::XFANDD: |
772 | 0 | case BPF::XFANDW32: |
773 | 0 | case BPF::XFORD: |
774 | 0 | case BPF::XFORW32: |
775 | 0 | case BPF::XFXORD: |
776 | 0 | case BPF::XFXORW32: |
777 | 0 | case BPF::XORD: |
778 | 0 | case BPF::XORW32: |
779 | 0 | case BPF::XXORD: |
780 | 0 | case BPF::XXORW32: { |
781 | | // op: dst |
782 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
783 | 0 | op &= UINT64_C(15); |
784 | 0 | op <<= 52; |
785 | 0 | Value |= op; |
786 | | // op: addr |
787 | 0 | op = getMemoryOpValue(MI, 1, Fixups, STI); |
788 | 0 | op &= UINT64_C(1048575); |
789 | 0 | op <<= 32; |
790 | 0 | Value |= op; |
791 | 0 | break; |
792 | 0 | } |
793 | 0 | case BPF::LD_ABS_B: |
794 | 0 | case BPF::LD_ABS_H: |
795 | 0 | case BPF::LD_ABS_W: { |
796 | | // op: imm |
797 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
798 | 0 | op &= UINT64_C(4294967295); |
799 | 0 | Value |= op; |
800 | 0 | break; |
801 | 0 | } |
802 | 0 | case BPF::CMPXCHGD: |
803 | 0 | case BPF::CMPXCHGW32: { |
804 | | // op: new |
805 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
806 | 0 | op &= UINT64_C(15); |
807 | 0 | op <<= 52; |
808 | 0 | Value |= op; |
809 | | // op: addr |
810 | 0 | op = getMemoryOpValue(MI, 0, Fixups, STI); |
811 | 0 | op &= UINT64_C(1048575); |
812 | 0 | op <<= 32; |
813 | 0 | Value |= op; |
814 | 0 | break; |
815 | 0 | } |
816 | 0 | case BPF::STB: |
817 | 0 | case BPF::STB32: |
818 | 0 | case BPF::STD: |
819 | 0 | case BPF::STH: |
820 | 0 | case BPF::STH32: |
821 | 0 | case BPF::STW: |
822 | 0 | case BPF::STW32: { |
823 | | // op: src |
824 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
825 | 0 | op &= UINT64_C(15); |
826 | 0 | op <<= 52; |
827 | 0 | Value |= op; |
828 | | // op: addr |
829 | 0 | op = getMemoryOpValue(MI, 1, Fixups, STI); |
830 | 0 | op &= UINT64_C(1048575); |
831 | 0 | op <<= 32; |
832 | 0 | Value |= op; |
833 | 0 | break; |
834 | 0 | } |
835 | 0 | case BPF::LD_IND_B: |
836 | 0 | case BPF::LD_IND_H: |
837 | 0 | case BPF::LD_IND_W: { |
838 | | // op: val |
839 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
840 | 0 | op &= UINT64_C(15); |
841 | 0 | op <<= 52; |
842 | 0 | Value |= op; |
843 | 0 | break; |
844 | 0 | } |
845 | 0 | default: |
846 | 0 | std::string msg; |
847 | 0 | raw_string_ostream Msg(msg); |
848 | 0 | Msg << "Not supported instr: " << MI; |
849 | 0 | report_fatal_error(Msg.str().c_str()); |
850 | 0 | } |
851 | 0 | return Value; |
852 | 0 | } |
853 | | |
854 | | #ifdef GET_OPERAND_BIT_OFFSET |
855 | | #undef GET_OPERAND_BIT_OFFSET |
856 | | |
857 | | uint32_t BPFMCCodeEmitter::getOperandBitOffset(const MCInst &MI, |
858 | | unsigned OpNum, |
859 | | const MCSubtargetInfo &STI) const { |
860 | | switch (MI.getOpcode()) { |
861 | | case BPF::CORE_LD32: |
862 | | case BPF::CORE_LD64: |
863 | | case BPF::CORE_ST: |
864 | | case BPF::NOP: |
865 | | case BPF::RET: { |
866 | | break; |
867 | | } |
868 | | case BPF::JAL: |
869 | | case BPF::JALX: |
870 | | case BPF::JMPL: { |
871 | | switch (OpNum) { |
872 | | case 0: |
873 | | // op: BrDst |
874 | | return 0; |
875 | | } |
876 | | break; |
877 | | } |
878 | | case BPF::JMP: { |
879 | | switch (OpNum) { |
880 | | case 0: |
881 | | // op: BrDst |
882 | | return 32; |
883 | | } |
884 | | break; |
885 | | } |
886 | | case BPF::LDB: |
887 | | case BPF::LDB32: |
888 | | case BPF::LDBSX: |
889 | | case BPF::LDD: |
890 | | case BPF::LDH: |
891 | | case BPF::LDH32: |
892 | | case BPF::LDHSX: |
893 | | case BPF::LDW: |
894 | | case BPF::LDW32: |
895 | | case BPF::LDWSX: { |
896 | | switch (OpNum) { |
897 | | case 0: |
898 | | // op: dst |
899 | | return 48; |
900 | | case 1: |
901 | | // op: addr |
902 | | return 32; |
903 | | } |
904 | | break; |
905 | | } |
906 | | case BPF::LD_imm64: |
907 | | case BPF::MOV_ri: |
908 | | case BPF::MOV_ri_32: { |
909 | | switch (OpNum) { |
910 | | case 0: |
911 | | // op: dst |
912 | | return 48; |
913 | | case 1: |
914 | | // op: imm |
915 | | return 0; |
916 | | } |
917 | | break; |
918 | | } |
919 | | case BPF::JEQ_rr: |
920 | | case BPF::JEQ_rr_32: |
921 | | case BPF::JNE_rr: |
922 | | case BPF::JNE_rr_32: |
923 | | case BPF::JSET_rr: |
924 | | case BPF::JSET_rr_32: |
925 | | case BPF::JSGE_rr: |
926 | | case BPF::JSGE_rr_32: |
927 | | case BPF::JSGT_rr: |
928 | | case BPF::JSGT_rr_32: |
929 | | case BPF::JSLE_rr: |
930 | | case BPF::JSLE_rr_32: |
931 | | case BPF::JSLT_rr: |
932 | | case BPF::JSLT_rr_32: |
933 | | case BPF::JUGE_rr: |
934 | | case BPF::JUGE_rr_32: |
935 | | case BPF::JUGT_rr: |
936 | | case BPF::JUGT_rr_32: |
937 | | case BPF::JULE_rr: |
938 | | case BPF::JULE_rr_32: |
939 | | case BPF::JULT_rr: |
940 | | case BPF::JULT_rr_32: { |
941 | | switch (OpNum) { |
942 | | case 0: |
943 | | // op: dst |
944 | | return 48; |
945 | | case 1: |
946 | | // op: src |
947 | | return 52; |
948 | | case 2: |
949 | | // op: BrDst |
950 | | return 32; |
951 | | } |
952 | | break; |
953 | | } |
954 | | case BPF::MOVSX_rr_8: |
955 | | case BPF::MOVSX_rr_16: |
956 | | case BPF::MOVSX_rr_32: |
957 | | case BPF::MOVSX_rr_32_8: |
958 | | case BPF::MOVSX_rr_32_16: |
959 | | case BPF::MOV_32_64: |
960 | | case BPF::MOV_rr: |
961 | | case BPF::MOV_rr_32: { |
962 | | switch (OpNum) { |
963 | | case 0: |
964 | | // op: dst |
965 | | return 48; |
966 | | case 1: |
967 | | // op: src |
968 | | return 52; |
969 | | } |
970 | | break; |
971 | | } |
972 | | case BPF::JEQ_ri: |
973 | | case BPF::JEQ_ri_32: |
974 | | case BPF::JNE_ri: |
975 | | case BPF::JNE_ri_32: |
976 | | case BPF::JSET_ri: |
977 | | case BPF::JSET_ri_32: |
978 | | case BPF::JSGE_ri: |
979 | | case BPF::JSGE_ri_32: |
980 | | case BPF::JSGT_ri: |
981 | | case BPF::JSGT_ri_32: |
982 | | case BPF::JSLE_ri: |
983 | | case BPF::JSLE_ri_32: |
984 | | case BPF::JSLT_ri: |
985 | | case BPF::JSLT_ri_32: |
986 | | case BPF::JUGE_ri: |
987 | | case BPF::JUGE_ri_32: |
988 | | case BPF::JUGT_ri: |
989 | | case BPF::JUGT_ri_32: |
990 | | case BPF::JULE_ri: |
991 | | case BPF::JULE_ri_32: |
992 | | case BPF::JULT_ri: |
993 | | case BPF::JULT_ri_32: { |
994 | | switch (OpNum) { |
995 | | case 0: |
996 | | // op: dst |
997 | | return 48; |
998 | | case 2: |
999 | | // op: BrDst |
1000 | | return 32; |
1001 | | case 1: |
1002 | | // op: imm |
1003 | | return 0; |
1004 | | } |
1005 | | break; |
1006 | | } |
1007 | | case BPF::LD_pseudo: { |
1008 | | switch (OpNum) { |
1009 | | case 0: |
1010 | | // op: dst |
1011 | | return 48; |
1012 | | case 2: |
1013 | | // op: imm |
1014 | | return 0; |
1015 | | case 1: |
1016 | | // op: pseudo |
1017 | | return 52; |
1018 | | } |
1019 | | break; |
1020 | | } |
1021 | | case BPF::ADD_ri: |
1022 | | case BPF::ADD_ri_32: |
1023 | | case BPF::AND_ri: |
1024 | | case BPF::AND_ri_32: |
1025 | | case BPF::DIV_ri: |
1026 | | case BPF::DIV_ri_32: |
1027 | | case BPF::MOD_ri: |
1028 | | case BPF::MOD_ri_32: |
1029 | | case BPF::MUL_ri: |
1030 | | case BPF::MUL_ri_32: |
1031 | | case BPF::OR_ri: |
1032 | | case BPF::OR_ri_32: |
1033 | | case BPF::SDIV_ri: |
1034 | | case BPF::SDIV_ri_32: |
1035 | | case BPF::SLL_ri: |
1036 | | case BPF::SLL_ri_32: |
1037 | | case BPF::SMOD_ri: |
1038 | | case BPF::SMOD_ri_32: |
1039 | | case BPF::SRA_ri: |
1040 | | case BPF::SRA_ri_32: |
1041 | | case BPF::SRL_ri: |
1042 | | case BPF::SRL_ri_32: |
1043 | | case BPF::SUB_ri: |
1044 | | case BPF::SUB_ri_32: |
1045 | | case BPF::XOR_ri: |
1046 | | case BPF::XOR_ri_32: { |
1047 | | switch (OpNum) { |
1048 | | case 0: |
1049 | | // op: dst |
1050 | | return 48; |
1051 | | case 2: |
1052 | | // op: imm |
1053 | | return 0; |
1054 | | } |
1055 | | break; |
1056 | | } |
1057 | | case BPF::ADD_rr: |
1058 | | case BPF::ADD_rr_32: |
1059 | | case BPF::AND_rr: |
1060 | | case BPF::AND_rr_32: |
1061 | | case BPF::CORE_SHIFT: |
1062 | | case BPF::DIV_rr: |
1063 | | case BPF::DIV_rr_32: |
1064 | | case BPF::MOD_rr: |
1065 | | case BPF::MOD_rr_32: |
1066 | | case BPF::MUL_rr: |
1067 | | case BPF::MUL_rr_32: |
1068 | | case BPF::OR_rr: |
1069 | | case BPF::OR_rr_32: |
1070 | | case BPF::SDIV_rr: |
1071 | | case BPF::SDIV_rr_32: |
1072 | | case BPF::SLL_rr: |
1073 | | case BPF::SLL_rr_32: |
1074 | | case BPF::SMOD_rr: |
1075 | | case BPF::SMOD_rr_32: |
1076 | | case BPF::SRA_rr: |
1077 | | case BPF::SRA_rr_32: |
1078 | | case BPF::SRL_rr: |
1079 | | case BPF::SRL_rr_32: |
1080 | | case BPF::SUB_rr: |
1081 | | case BPF::SUB_rr_32: |
1082 | | case BPF::XOR_rr: |
1083 | | case BPF::XOR_rr_32: { |
1084 | | switch (OpNum) { |
1085 | | case 0: |
1086 | | // op: dst |
1087 | | return 48; |
1088 | | case 2: |
1089 | | // op: src |
1090 | | return 52; |
1091 | | } |
1092 | | break; |
1093 | | } |
1094 | | case BPF::BE16: |
1095 | | case BPF::BE32: |
1096 | | case BPF::BE64: |
1097 | | case BPF::BSWAP16: |
1098 | | case BPF::BSWAP32: |
1099 | | case BPF::BSWAP64: |
1100 | | case BPF::LE16: |
1101 | | case BPF::LE32: |
1102 | | case BPF::LE64: |
1103 | | case BPF::NEG_32: |
1104 | | case BPF::NEG_64: { |
1105 | | switch (OpNum) { |
1106 | | case 0: |
1107 | | // op: dst |
1108 | | return 48; |
1109 | | } |
1110 | | break; |
1111 | | } |
1112 | | case BPF::XADDD: |
1113 | | case BPF::XADDW: |
1114 | | case BPF::XADDW32: |
1115 | | case BPF::XANDD: |
1116 | | case BPF::XANDW32: |
1117 | | case BPF::XCHGD: |
1118 | | case BPF::XCHGW32: |
1119 | | case BPF::XFADDD: |
1120 | | case BPF::XFADDW32: |
1121 | | case BPF::XFANDD: |
1122 | | case BPF::XFANDW32: |
1123 | | case BPF::XFORD: |
1124 | | case BPF::XFORW32: |
1125 | | case BPF::XFXORD: |
1126 | | case BPF::XFXORW32: |
1127 | | case BPF::XORD: |
1128 | | case BPF::XORW32: |
1129 | | case BPF::XXORD: |
1130 | | case BPF::XXORW32: { |
1131 | | switch (OpNum) { |
1132 | | case 0: |
1133 | | // op: dst |
1134 | | return 52; |
1135 | | case 1: |
1136 | | // op: addr |
1137 | | return 32; |
1138 | | } |
1139 | | break; |
1140 | | } |
1141 | | case BPF::STB: |
1142 | | case BPF::STB32: |
1143 | | case BPF::STD: |
1144 | | case BPF::STH: |
1145 | | case BPF::STH32: |
1146 | | case BPF::STW: |
1147 | | case BPF::STW32: { |
1148 | | switch (OpNum) { |
1149 | | case 0: |
1150 | | // op: src |
1151 | | return 52; |
1152 | | case 1: |
1153 | | // op: addr |
1154 | | return 32; |
1155 | | } |
1156 | | break; |
1157 | | } |
1158 | | case BPF::STB_imm: |
1159 | | case BPF::STD_imm: |
1160 | | case BPF::STH_imm: |
1161 | | case BPF::STW_imm: { |
1162 | | switch (OpNum) { |
1163 | | case 1: |
1164 | | // op: addr |
1165 | | return 32; |
1166 | | case 0: |
1167 | | // op: imm |
1168 | | return 0; |
1169 | | } |
1170 | | break; |
1171 | | } |
1172 | | case BPF::LD_ABS_B: |
1173 | | case BPF::LD_ABS_H: |
1174 | | case BPF::LD_ABS_W: { |
1175 | | switch (OpNum) { |
1176 | | case 1: |
1177 | | // op: imm |
1178 | | return 0; |
1179 | | } |
1180 | | break; |
1181 | | } |
1182 | | case BPF::LD_IND_B: |
1183 | | case BPF::LD_IND_H: |
1184 | | case BPF::LD_IND_W: { |
1185 | | switch (OpNum) { |
1186 | | case 1: |
1187 | | // op: val |
1188 | | return 52; |
1189 | | } |
1190 | | break; |
1191 | | } |
1192 | | case BPF::CMPXCHGD: |
1193 | | case BPF::CMPXCHGW32: { |
1194 | | switch (OpNum) { |
1195 | | case 2: |
1196 | | // op: new |
1197 | | return 52; |
1198 | | case 0: |
1199 | | // op: addr |
1200 | | return 32; |
1201 | | } |
1202 | | break; |
1203 | | } |
1204 | | } |
1205 | | std::string msg; |
1206 | | raw_string_ostream Msg(msg); |
1207 | | Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]"; |
1208 | | report_fatal_error(Msg.str().c_str()); |
1209 | | } |
1210 | | |
1211 | | #endif // GET_OPERAND_BIT_OFFSET |
1212 | | |