/src/build/lib/Target/BPF/BPFGenRegisterBank.inc
Line | Count | Source |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Register Bank Source Fragments *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | #ifdef GET_REGBANK_DECLARATIONS |
10 | | #undef GET_REGBANK_DECLARATIONS |
11 | | namespace llvm { |
12 | | namespace BPF { |
13 | | enum : unsigned { |
14 | | InvalidRegBankID = ~0u, |
15 | | GPRRegBankID = 0, |
16 | | NumRegisterBanks, |
17 | | }; |
18 | | } // end namespace BPF |
19 | | } // end namespace llvm |
20 | | #endif // GET_REGBANK_DECLARATIONS |
21 | | |
22 | | #ifdef GET_TARGET_REGBANK_CLASS |
23 | | #undef GET_TARGET_REGBANK_CLASS |
24 | | private: |
25 | | static const RegisterBank *RegBanks[]; |
26 | | static const unsigned Sizes[]; |
27 | | |
28 | | protected: |
29 | | BPFGenRegisterBankInfo(unsigned HwMode = 0); |
30 | | |
31 | | #endif // GET_TARGET_REGBANK_CLASS |
32 | | |
33 | | #ifdef GET_TARGET_REGBANK_IMPL |
34 | | #undef GET_TARGET_REGBANK_IMPL |
35 | | namespace llvm { |
36 | | namespace BPF { |
37 | | const uint32_t GPRRegBankCoverageData[] = { |
38 | | // 0-31 |
39 | | (1u << (BPF::GPRRegClassID - 0)) | |
40 | | (1u << (BPF::GPR32RegClassID - 0)) | |
41 | | 0, |
42 | | }; |
43 | | |
44 | | constexpr RegisterBank GPRRegBank(/* ID */ BPF::GPRRegBankID, /* Name */ "GPRB", /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 2); |
45 | | } // end namespace BPF |
46 | | |
47 | | const RegisterBank *BPFGenRegisterBankInfo::RegBanks[] = { |
48 | | &BPF::GPRRegBank, |
49 | | }; |
50 | | |
51 | | const unsigned BPFGenRegisterBankInfo::Sizes[] = { |
52 | | // Mode = 0 (Default) |
53 | | 64, |
54 | | }; |
55 | | |
56 | | BPFGenRegisterBankInfo::BPFGenRegisterBankInfo(unsigned HwMode) |
57 | 2 | : RegisterBankInfo(RegBanks, BPF::NumRegisterBanks, Sizes, HwMode) { |
58 | | // Assert that RegBank indices match their ID's |
59 | 2 | #ifndef NDEBUG |
60 | 2 | for (auto RB : enumerate(RegBanks)) |
61 | 2 | assert(RB.index() == RB.value()->getID() && "Index != ID"); |
62 | 2 | #endif // NDEBUG |
63 | 2 | } |
64 | | } // end namespace llvm |
65 | | #endif // GET_TARGET_REGBANK_IMPL |