/src/build/lib/Target/BPF/BPFGenRegisterInfo.inc

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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register Enum Values                                                *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM

namespace llvm {

class MCRegisterClass;
extern const MCRegisterClass BPFMCRegisterClasses[];

namespace BPF {
enum {
  NoRegister,
  R0 = 1,
  R1 = 2,
  R2 = 3,
  R3 = 4,
  R4 = 5,
  R5 = 6,
  R6 = 7,
  R7 = 8,
  R8 = 9,
  R9 = 10,
  R10 = 11,
  R11 = 12,
  W0 = 13,
  W1 = 14,
  W2 = 15,
  W3 = 16,
  W4 = 17,
  W5 = 18,
  W6 = 19,
  W7 = 20,
  W8 = 21,
  W9 = 22,
  W10 = 23,
  W11 = 24,
  NUM_TARGET_REGS // 25
};
} // end namespace BPF

// Register classes

namespace BPF {
enum {
  GPR32RegClassID = 0,
  GPRRegClassID = 1,

};
} // end namespace BPF


// Subregister indices

namespace BPF {
enum : uint16_t {
  NoSubRegister,
  sub_32, // 1
  NUM_TARGET_SUBREGS
};
} // end namespace BPF

// Register pressure sets enum.
namespace BPF {
enum RegisterPressureSets {
  GPR32 = 0,
};
} // end namespace BPF

} // end namespace llvm

#endif // GET_REGINFO_ENUM

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* MC Register Information                                                    *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC

namespace llvm {

extern const int16_t BPFRegDiffLists[] = {
  /* 0 */ -12, 0,
  /* 2 */ 12, 0,
};

extern const LaneBitmask BPFLaneMaskLists[] = {
  /* 0 */ LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
  /* 2 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
};

extern const uint16_t BPFSubRegIdxLists[] = {
  /* 0 */ 1, 0,
};

extern const MCRegisterInfo::SubRegCoveredBits BPFSubRegIdxRanges[] = {
  { 65535, 65535 },
  { 0, 32 },  // sub_32
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char BPFRegStrings[] = {
  /* 0 */ "R10\0"
  /* 4 */ "W10\0"
  /* 8 */ "R0\0"
  /* 11 */ "W0\0"
  /* 14 */ "R11\0"
  /* 18 */ "W11\0"
  /* 22 */ "R1\0"
  /* 25 */ "W1\0"
  /* 28 */ "R2\0"
  /* 31 */ "W2\0"
  /* 34 */ "R3\0"
  /* 37 */ "W3\0"
  /* 40 */ "R4\0"
  /* 43 */ "W4\0"
  /* 46 */ "R5\0"
  /* 49 */ "W5\0"
  /* 52 */ "R6\0"
  /* 55 */ "W6\0"
  /* 58 */ "R7\0"
  /* 61 */ "W7\0"
  /* 64 */ "R8\0"
  /* 67 */ "W8\0"
  /* 70 */ "R9\0"
  /* 73 */ "W9\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const MCRegisterDesc BPFRegDesc[] = { // Descriptors
  { 3, 0, 0, 0, 0, 0 },
  { 8, 2, 1, 0, 4096, 0 },
  { 22, 2, 1, 0, 4097, 0 },
  { 28, 2, 1, 0, 4098, 0 },
  { 34, 2, 1, 0, 4099, 0 },
  { 40, 2, 1, 0, 4100, 0 },
  { 46, 2, 1, 0, 4101, 0 },
  { 52, 2, 1, 0, 4102, 0 },
  { 58, 2, 1, 0, 4103, 0 },
  { 64, 2, 1, 0, 4104, 0 },
  { 70, 2, 1, 0, 4105, 0 },
  { 0, 2, 1, 0, 4106, 0 },
  { 14, 2, 1, 0, 4107, 0 },
  { 11, 1, 0, 1, 4096, 2 },
  { 25, 1, 0, 1, 4097, 2 },
  { 31, 1, 0, 1, 4098, 2 },
  { 37, 1, 0, 1, 4099, 2 },
  { 43, 1, 0, 1, 4100, 2 },
  { 49, 1, 0, 1, 4101, 2 },
  { 55, 1, 0, 1, 4102, 2 },
  { 61, 1, 0, 1, 4103, 2 },
  { 67, 1, 0, 1, 4104, 2 },
  { 73, 1, 0, 1, 4105, 2 },
  { 4, 1, 0, 1, 4106, 2 },
  { 18, 1, 0, 1, 4107, 2 },
};

extern const MCPhysReg BPFRegUnitRoots[][2] = {
  { BPF::W0 },
  { BPF::W1 },
  { BPF::W2 },
  { BPF::W3 },
  { BPF::W4 },
  { BPF::W5 },
  { BPF::W6 },
  { BPF::W7 },
  { BPF::W8 },
  { BPF::W9 },
  { BPF::W10 },
  { BPF::W11 },
};

namespace {     // Register classes...
  // GPR32 Register Class...
  const MCPhysReg GPR32[] = {
    BPF::W1, BPF::W2, BPF::W3, BPF::W4, BPF::W5, BPF::W6, BPF::W7, BPF::W8, BPF::W9, BPF::W0, BPF::W11, BPF::W10, 
  };

  // GPR32 Bit set.
  const uint8_t GPR32Bits[] = {
    0x00, 0xe0, 0xff, 0x01, 
  };

  // GPR Register Class...
  const MCPhysReg GPR[] = {
    BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5, BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R0, BPF::R11, BPF::R10, 
  };

  // GPR Bit set.
  const uint8_t GPRBits[] = {
    0xfe, 0x1f, 
  };

} // end anonymous namespace


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char BPFRegClassStrings[] = {
  /* 0 */ "GPR32\0"
  /* 6 */ "GPR\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const MCRegisterClass BPFMCRegisterClasses[] = {
  { GPR32, GPR32Bits, 0, 12, sizeof(GPR32Bits), BPF::GPR32RegClassID, 32, 1, true },
  { GPR, GPRBits, 6, 12, sizeof(GPRBits), BPF::GPRRegClassID, 64, 1, true },
};

// BPF Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0Dwarf2L[] = {
  { 0U, BPF::W0 },
  { 1U, BPF::W1 },
  { 2U, BPF::W2 },
  { 3U, BPF::W3 },
  { 4U, BPF::W4 },
  { 5U, BPF::W5 },
  { 6U, BPF::W6 },
  { 7U, BPF::W7 },
  { 8U, BPF::W8 },
  { 9U, BPF::W9 },
  { 10U, BPF::W10 },
  { 11U, BPF::W11 },
};
extern const unsigned BPFDwarfFlavour0Dwarf2LSize = std::size(BPFDwarfFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0Dwarf2L[] = {
  { 0U, BPF::W0 },
  { 1U, BPF::W1 },
  { 2U, BPF::W2 },
  { 3U, BPF::W3 },
  { 4U, BPF::W4 },
  { 5U, BPF::W5 },
  { 6U, BPF::W6 },
  { 7U, BPF::W7 },
  { 8U, BPF::W8 },
  { 9U, BPF::W9 },
  { 10U, BPF::W10 },
  { 11U, BPF::W11 },
};
extern const unsigned BPFEHFlavour0Dwarf2LSize = std::size(BPFEHFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0L2Dwarf[] = {
  { BPF::R0, 0U },
  { BPF::R1, 1U },
  { BPF::R2, 2U },
  { BPF::R3, 3U },
  { BPF::R4, 4U },
  { BPF::R5, 5U },
  { BPF::R6, 6U },
  { BPF::R7, 7U },
  { BPF::R8, 8U },
  { BPF::R9, 9U },
  { BPF::R10, 10U },
  { BPF::R11, 11U },
  { BPF::W0, 0U },
  { BPF::W1, 1U },
  { BPF::W2, 2U },
  { BPF::W3, 3U },
  { BPF::W4, 4U },
  { BPF::W5, 5U },
  { BPF::W6, 6U },
  { BPF::W7, 7U },
  { BPF::W8, 8U },
  { BPF::W9, 9U },
  { BPF::W10, 10U },
  { BPF::W11, 11U },
};
extern const unsigned BPFDwarfFlavour0L2DwarfSize = std::size(BPFDwarfFlavour0L2Dwarf);

extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0L2Dwarf[] = {
  { BPF::R0, 0U },
  { BPF::R1, 1U },
  { BPF::R2, 2U },
  { BPF::R3, 3U },
  { BPF::R4, 4U },
  { BPF::R5, 5U },
  { BPF::R6, 6U },
  { BPF::R7, 7U },
  { BPF::R8, 8U },
  { BPF::R9, 9U },
  { BPF::R10, 10U },
  { BPF::R11, 11U },
  { BPF::W0, 0U },
  { BPF::W1, 1U },
  { BPF::W2, 2U },
  { BPF::W3, 3U },
  { BPF::W4, 4U },
  { BPF::W5, 5U },
  { BPF::W6, 6U },
  { BPF::W7, 7U },
  { BPF::W8, 8U },
  { BPF::W9, 9U },
  { BPF::W10, 10U },
  { BPF::W11, 11U },
};
extern const unsigned BPFEHFlavour0L2DwarfSize = std::size(BPFEHFlavour0L2Dwarf);

extern const uint16_t BPFRegEncodingTable[] = {
  0,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
};
static inline void InitBPFMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
  RI->InitMCRegisterInfo(BPFRegDesc, 25, RA, PC, BPFMCRegisterClasses, 2, BPFRegUnitRoots, 12, BPFRegDiffLists, BPFLaneMaskLists, BPFRegStrings, BPFRegClassStrings, BPFSubRegIdxLists, 2,
BPFSubRegIdxRanges, BPFRegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(BPFDwarfFlavour0Dwarf2L, BPFDwarfFlavour0Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(BPFEHFlavour0Dwarf2L, BPFEHFlavour0Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(BPFDwarfFlavour0L2Dwarf, BPFDwarfFlavour0L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(BPFEHFlavour0L2Dwarf, BPFEHFlavour0L2DwarfSize, true);
    break;
  }
}

} // end namespace llvm

#endif // GET_REGINFO_MC_DESC

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Register Information Header Fragment                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_HEADER
#undef GET_REGINFO_HEADER

#include "llvm/CodeGen/TargetRegisterInfo.h"

namespace llvm {

class BPFFrameLowering;

struct BPFGenRegisterInfo : public TargetRegisterInfo {
  explicit BPFGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
      unsigned PC = 0, unsigned HwMode = 0);
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
  const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
  unsigned getNumRegPressureSets() const override;
  const char *getRegPressureSetName(unsigned Idx) const override;
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
  ArrayRef<const char *> getRegMaskNames() const override;
  ArrayRef<const uint32_t *> getRegMasks() const override;
  bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
  bool isFixedRegister(const MachineFunction &, MCRegister) const override;
  bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
  bool isConstantPhysReg(MCRegister PhysReg) const override final;
  /// Devirtualized TargetFrameLowering.
  static const BPFFrameLowering *getFrameLowering(
      const MachineFunction &MF);
};

namespace BPF { // Register classes
  extern const TargetRegisterClass GPR32RegClass;
  extern const TargetRegisterClass GPRRegClass;
} // end namespace BPF

} // end namespace llvm

#endif // GET_REGINFO_HEADER

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register and Register Classes Information                           *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_TARGET_DESC
#undef GET_REGINFO_TARGET_DESC

namespace llvm {

extern const MCRegisterClass BPFMCRegisterClasses[];

static const MVT::SimpleValueType VTLists[] = {
  /* 0 */ MVT::i32, MVT::Other,
  /* 2 */ MVT::i64, MVT::Other,
};

static const char *SubRegIndexNameTable[] = { "sub_32", "" };


static const LaneBitmask SubRegIndexLaneMaskTable[] = {
  LaneBitmask::getAll(),
  LaneBitmask(0x0000000000000001), // sub_32
 };



static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
  // Mode = 0 (Default)
  { 32, 32, 64, /*VTLists+*/0 },    // GPR32
  { 64, 64, 64, /*VTLists+*/2 },    // GPR
};

static const TargetRegisterClass *const NullRegClasses[] = { nullptr };

static const uint32_t GPR32SubClassMask[] = {
  0x00000001, 
  0x00000002, // sub_32
};

static const uint32_t GPRSubClassMask[] = {
  0x00000002, 
};

static const uint16_t SuperRegIdxSeqs[] = {
  /* 0 */ 1, 0,
};


namespace BPF {   // Register class instances
  extern const TargetRegisterClass GPR32RegClass = {
    &BPFMCRegisterClasses[GPR32RegClassID],
    GPR32SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GPRRegClass = {
    &BPFMCRegisterClasses[GPRRegClassID],
    GPRSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

} // end namespace BPF

namespace {
  const TargetRegisterClass *const RegisterClasses[] = {
    &BPF::GPR32RegClass,
    &BPF::GPRRegClass,
  };
} // end anonymous namespace

static const uint8_t CostPerUseTable[] = { 
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };


static const bool InAllocatableClassTable[] = { 
false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };


static const TargetRegisterInfoDesc BPFRegInfoDesc = { // Extra Descriptors
CostPerUseTable, 1, InAllocatableClassTable};

unsigned BPFGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
  static const uint8_t Rows[1][1] = {
    { 0, },
  };

  --IdxA; assert(IdxA < 1); (void) IdxA;
  --IdxB; assert(IdxB < 1);
  return Rows[0][IdxB];
}

  struct MaskRolOp {
    LaneBitmask Mask;
    uint8_t  RotateLeft;
  };
  static const MaskRolOp LaneMaskComposeSequences[] = {
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 }  // Sequence 0
  };
  static const uint8_t CompositeSequences[] = {
    0 // to sub_32
  };

LaneBitmask BPFGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
  --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops =
       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
       Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

LaneBitmask BPFGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
  LaneMask &= getSubRegIndexLaneMask(IdxA);
  --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops =
       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
       Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

const TargetRegisterClass *BPFGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
  static const uint8_t Table[2][1] = {
    { // GPR32
      0,  // sub_32
    },
    { // GPR
      2,  // sub_32 -> GPR
    },
  };
  assert(RC && "Missing regclass");
  if (!Idx) return RC;
  --Idx;
  assert(Idx < 1 && "Bad subreg");
  unsigned TV = Table[RC->getID()][Idx];
  return TV ? getRegClass(TV - 1) : nullptr;
}

const TargetRegisterClass *BPFGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
  static const uint8_t Table[2][1] = {
    { // GPR32
      0,  // GPR32:sub_32
    },
    { // GPR
      1,  // GPR:sub_32 -> GPR32
    },
  };
  assert(RC && "Missing regclass");
  if (!Idx) return RC;
  --Idx;
  assert(Idx < 1 && "Bad subreg");
  unsigned TV = Table[RC->getID()][Idx];
  return TV ? getRegClass(TV - 1) : nullptr;
}

/// Get the weight in units of pressure for this register class.
const RegClassWeight &BPFGenRegisterInfo::
getRegClassWeight(const TargetRegisterClass *RC) const {
  static const RegClassWeight RCWeightTable[] = {
    {1, 12},    // GPR32
    {1, 12},    // GPR
  };
  return RCWeightTable[RC->getID()];
}

/// Get the weight in units of pressure for this register unit.
unsigned BPFGenRegisterInfo::
getRegUnitWeight(unsigned RegUnit) const {
  assert(RegUnit < 12 && "invalid register unit");
  // All register units have unit weight.
  return 1;
}


// Get the number of dimensions of register pressure.
unsigned BPFGenRegisterInfo::getNumRegPressureSets() const {
  return 1;
}

// Get the name of this register unit pressure set.
const char *BPFGenRegisterInfo::
getRegPressureSetName(unsigned Idx) const {
  static const char *PressureNameTable[] = {
    "GPR32",
  };
  return PressureNameTable[Idx];
}

// Get the register unit pressure limit for this dimension.
// This limit must be adjusted dynamically for reserved registers.
unsigned BPFGenRegisterInfo::
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
  static const uint8_t PressureLimitTable[] = {
    12,   // 0: GPR32
  };
  return PressureLimitTable[Idx];
}

/// Table of pressure sets per register class or unit.
static const int RCSetsTable[] = {
  /* 0 */ 0, -1,
};

/// Get the dimensions of register pressure impacted by this register class.
/// Returns a -1 terminated array of pressure set IDs
const int *BPFGenRegisterInfo::
getRegClassPressureSets(const TargetRegisterClass *RC) const {
  static const uint8_t RCSetStartTable[] = {
    0,0,};
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
}

/// Get the dimensions of register pressure impacted by this register unit.
/// Returns a -1 terminated array of pressure set IDs
const int *BPFGenRegisterInfo::
getRegUnitPressureSets(unsigned RegUnit) const {
  assert(RegUnit < 12 && "invalid register unit");
  static const uint8_t RUSetStartTable[] = {
    0,0,0,0,0,0,0,0,0,0,0,0,};
  return &RCSetsTable[RUSetStartTable[RegUnit]];
}

extern const MCRegisterDesc BPFRegDesc[];
extern const int16_t BPFRegDiffLists[];
extern const LaneBitmask BPFLaneMaskLists[];
extern const char BPFRegStrings[];
extern const char BPFRegClassStrings[];
extern const MCPhysReg BPFRegUnitRoots[][2];
extern const uint16_t BPFSubRegIdxLists[];
extern const MCRegisterInfo::SubRegCoveredBits BPFSubRegIdxRanges[];
extern const uint16_t BPFRegEncodingTable[];
// BPF Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0Dwarf2L[];
extern const unsigned BPFDwarfFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0Dwarf2L[];
extern const unsigned BPFEHFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0L2Dwarf[];
extern const unsigned BPFDwarfFlavour0L2DwarfSize;

extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0L2Dwarf[];
extern const unsigned BPFEHFlavour0L2DwarfSize;

BPFGenRegisterInfo::
BPFGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
      unsigned PC, unsigned HwMode)
  : TargetRegisterInfo(&BPFRegInfoDesc, RegisterClasses, RegisterClasses+2,
             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
             LaneBitmask(0xFFFFFFFFFFFFFFFE), RegClassInfos, VTLists, HwMode) {
  InitMCRegisterInfo(BPFRegDesc, 25, RA, PC,
                     BPFMCRegisterClasses, 2,
                     BPFRegUnitRoots,
                     12,
                     BPFRegDiffLists,
                     BPFLaneMaskLists,
                     BPFRegStrings,
                     BPFRegClassStrings,
                     BPFSubRegIdxLists,
                     2,
                     BPFSubRegIdxRanges,
                     BPFRegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(BPFDwarfFlavour0Dwarf2L, BPFDwarfFlavour0Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(BPFEHFlavour0Dwarf2L, BPFEHFlavour0Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(BPFDwarfFlavour0L2Dwarf, BPFDwarfFlavour0L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(BPFEHFlavour0L2Dwarf, BPFEHFlavour0L2DwarfSize, true);
    break;
  }
}

static const MCPhysReg CSR_SaveList[] = { BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, 0 };
static const uint32_t CSR_RegMask[] = { 0x00f80f80, };


ArrayRef<const uint32_t *> BPFGenRegisterInfo::getRegMasks() const {
  static const uint32_t *const Masks[] = {
    CSR_RegMask,
  };
  return ArrayRef(Masks);
}

bool BPFGenRegisterInfo::
isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool BPFGenRegisterInfo::
isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool BPFGenRegisterInfo::
isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool BPFGenRegisterInfo::
isConstantPhysReg(MCRegister PhysReg) const {
  return
      false;
}

ArrayRef<const char *> BPFGenRegisterInfo::getRegMaskNames() const {
  static const char *Names[] = {
    "CSR",
  };
  return ArrayRef(Names);
}

const BPFFrameLowering *
BPFGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
  return static_cast<const BPFFrameLowering *>(
      MF.getSubtarget().getFrameLowering());
}

} // end namespace llvm

#endif // GET_REGINFO_TARGET_DESC


Coverage Report

Created: 2024-01-17 10:31