/src/build/lib/Target/Hexagon/HexagonGenAsmWriter.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Assembly Writer Source Fragment *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* From: Hexagon.td *| |
7 | | |* *| |
8 | | \*===----------------------------------------------------------------------===*/ |
9 | | |
10 | | /// getMnemonic - This method is automatically generated by tablegen |
11 | | /// from the instruction set description. |
12 | 0 | std::pair<const char *, uint64_t> HexagonInstPrinter::getMnemonic(const MCInst *MI) { |
13 | |
|
14 | 0 | #ifdef __GNUC__ |
15 | 0 | #pragma GCC diagnostic push |
16 | 0 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
17 | 0 | #endif |
18 | 0 | static const char AsmStrs[] = { |
19 | 0 | /* 0 */ ".error \"should not emit\" \0" |
20 | 0 | /* 26 */ "if (!p0) \0" |
21 | 0 | /* 36 */ "if (p0) \0" |
22 | 0 | /* 45 */ "if (!p0.new) \0" |
23 | 0 | /* 59 */ "if (p0.new) \0" |
24 | 0 | /* 72 */ "callrh \0" |
25 | 0 | /* 80 */ "jumprh \0" |
26 | 0 | /* 88 */ "call \0" |
27 | 0 | /* 94 */ "jump \0" |
28 | 0 | /* 100 */ "callr \0" |
29 | 0 | /* 107 */ "jumpr \0" |
30 | 0 | /* 114 */ "if (!\0" |
31 | 0 | /* 120 */ ".error \"should not emit\"\0" |
32 | 0 | /* 145 */ "trap0(#\0" |
33 | 0 | /* 153 */ "trap1(#\0" |
34 | 0 | /* 161 */ "vwhist128(#\0" |
35 | 0 | /* 173 */ "memb(#\0" |
36 | 0 | /* 180 */ "memd(#\0" |
37 | 0 | /* 187 */ "allocframe(#\0" |
38 | 0 | /* 200 */ "pause(#\0" |
39 | 0 | /* 208 */ "memh(#\0" |
40 | 0 | /* 215 */ "immext(#\0" |
41 | 0 | /* 224 */ "memw(#\0" |
42 | 0 | /* 231 */ "memd(r29+#\0" |
43 | 0 | /* 242 */ "memw(r29+#\0" |
44 | 0 | /* 253 */ "memb(gp+#\0" |
45 | 0 | /* 263 */ "memd(gp+#\0" |
46 | 0 | /* 273 */ "memh(gp+#\0" |
47 | 0 | /* 283 */ "memw(gp+#\0" |
48 | 0 | /* 293 */ "if (\0" |
49 | 0 | /* 298 */ "diag0(\0" |
50 | 0 | /* 305 */ "p3 = sp1loop0(\0" |
51 | 0 | /* 320 */ "p3 = sp2loop0(\0" |
52 | 0 | /* 335 */ "p3 = sp3loop0(\0" |
53 | 0 | /* 350 */ "diag1(\0" |
54 | 0 | /* 357 */ "trap1(\0" |
55 | 0 | /* 364 */ "loop1(\0" |
56 | 0 | /* 371 */ "vtrans2x2(\0" |
57 | 0 | /* 382 */ "vwhist256(\0" |
58 | 0 | /* 393 */ "vwhist128(\0" |
59 | 0 | /* 404 */ "l2unlocka(\0" |
60 | 0 | /* 415 */ "dccleana(\0" |
61 | 0 | /* 425 */ "dczeroa(\0" |
62 | 0 | /* 434 */ "dcinva(\0" |
63 | 0 | /* 442 */ "icinva(\0" |
64 | 0 | /* 450 */ "dccleaninva(\0" |
65 | 0 | /* 463 */ "memb(\0" |
66 | 0 | /* 469 */ "ciad(\0" |
67 | 0 | /* 475 */ "siad(\0" |
68 | 0 | /* 481 */ "memd_locked(\0" |
69 | 0 | /* 494 */ "memw_locked(\0" |
70 | 0 | /* 507 */ "tlbinvasid(\0" |
71 | 0 | /* 519 */ "memd(\0" |
72 | 0 | /* 525 */ "trace(\0" |
73 | 0 | /* 532 */ "allocframe(\0" |
74 | 0 | /* 544 */ "dmresume(\0" |
75 | 0 | /* 554 */ "release(\0" |
76 | 0 | /* 563 */ "vshuff(\0" |
77 | 0 | /* 571 */ "diag(\0" |
78 | 0 | /* 577 */ "l2fetch(\0" |
79 | 0 | /* 586 */ "dcfetch(\0" |
80 | 0 | /* 595 */ "memh(\0" |
81 | 0 | /* 601 */ "nmi(\0" |
82 | 0 | /* 606 */ "cswi(\0" |
83 | 0 | /* 612 */ "dmlink(\0" |
84 | 0 | /* 620 */ "setimask(\0" |
85 | 0 | /* 630 */ "vdeal(\0" |
86 | 0 | /* 637 */ "memd_rl(\0" |
87 | 0 | /* 646 */ "memw_rl(\0" |
88 | 0 | /* 655 */ "z = vmem(\0" |
89 | 0 | /* 665 */ "l2gclean(\0" |
90 | 0 | /* 675 */ "setprio(\0" |
91 | 0 | /* 684 */ "crswap(\0" |
92 | 0 | /* 692 */ "stop(\0" |
93 | 0 | /* 698 */ "p0 = cmp.eq(\0" |
94 | 0 | /* 711 */ "p1 = cmp.eq(\0" |
95 | 0 | /* 724 */ "if (!cmp.eq(\0" |
96 | 0 | /* 737 */ "if (cmp.eq(\0" |
97 | 0 | /* 749 */ "vtmp.h = vgather(\0" |
98 | 0 | /* 767 */ "vtmp.w = vgather(\0" |
99 | 0 | /* 785 */ "vscatter(\0" |
100 | 0 | /* 795 */ "hintjr(\0" |
101 | 0 | /* 803 */ "p0 = cmp.gt(\0" |
102 | 0 | /* 816 */ "p1 = cmp.gt(\0" |
103 | 0 | /* 829 */ "if (!cmp.gt(\0" |
104 | 0 | /* 842 */ "if (cmp.gt(\0" |
105 | 0 | /* 854 */ "wait(\0" |
106 | 0 | /* 860 */ "p0 = tstbit(\0" |
107 | 0 | /* 873 */ "p1 = tstbit(\0" |
108 | 0 | /* 886 */ "if (!tstbit(\0" |
109 | 0 | /* 899 */ "if (tstbit(\0" |
110 | 0 | /* 911 */ "dmstart(\0" |
111 | 0 | /* 920 */ "vhist(\0" |
112 | 0 | /* 927 */ "vmemu(\0" |
113 | 0 | /* 934 */ "p0 = cmp.gtu(\0" |
114 | 0 | /* 948 */ "p1 = cmp.gtu(\0" |
115 | 0 | /* 962 */ "if (!cmp.gtu(\0" |
116 | 0 | /* 976 */ "if (cmp.gtu(\0" |
117 | 0 | /* 989 */ "l2gcleaninv(\0" |
118 | 0 | /* 1002 */ "icdataw(\0" |
119 | 0 | /* 1011 */ "tlbw(\0" |
120 | 0 | /* 1017 */ "l2tagw(\0" |
121 | 0 | /* 1025 */ "dctagw(\0" |
122 | 0 | /* 1033 */ "ictagw(\0" |
123 | 0 | /* 1041 */ "memw(\0" |
124 | 0 | /* 1047 */ "iassignw(\0" |
125 | 0 | /* 1057 */ "l2cleanidx(\0" |
126 | 0 | /* 1069 */ "dccleanidx(\0" |
127 | 0 | /* 1081 */ "l2invidx(\0" |
128 | 0 | /* 1091 */ "dcinvidx(\0" |
129 | 0 | /* 1101 */ "icinvidx(\0" |
130 | 0 | /* 1111 */ "l2cleaninvidx(\0" |
131 | 0 | /* 1126 */ "dccleaninvidx(\0" |
132 | 0 | /* 1141 */ "memcpy(\0" |
133 | 0 | /* 1149 */ "# XRay Function Patchable RET.\0" |
134 | 0 | /* 1180 */ "# XRay Typed Event Log.\0" |
135 | 0 | /* 1204 */ "# XRay Custom Event Log.\0" |
136 | 0 | /* 1229 */ "# XRay Function Enter.\0" |
137 | 0 | /* 1252 */ "# XRay Tail Call Exit.\0" |
138 | 0 | /* 1275 */ "# XRay Function Exit.\0" |
139 | 0 | /* 1297 */ ":endloop0\0" |
140 | 0 | /* 1307 */ ":endloop01\0" |
141 | 0 | /* 1318 */ "if (!p0) jumpr r31\0" |
142 | 0 | /* 1337 */ "if (p0) jumpr r31\0" |
143 | 0 | /* 1355 */ "if (!p0.new) jumpr:nt r31\0" |
144 | 0 | /* 1381 */ "if (p0.new) jumpr:nt r31\0" |
145 | 0 | /* 1406 */ ":endloop1\0" |
146 | 0 | /* 1416 */ "vwhist256\0" |
147 | 0 | /* 1426 */ "vwhist128\0" |
148 | 0 | /* 1436 */ "<invalid>\0" |
149 | 0 | /* 1446 */ "LIFETIME_END\0" |
150 | 0 | /* 1459 */ "PSEUDO_PROBE\0" |
151 | 0 | /* 1472 */ "BUNDLE\0" |
152 | 0 | /* 1479 */ "DBG_VALUE\0" |
153 | 0 | /* 1489 */ "DBG_INSTR_REF\0" |
154 | 0 | /* 1503 */ "DBG_PHI\0" |
155 | 0 | /* 1511 */ "DBG_LABEL\0" |
156 | 0 | /* 1521 */ "LIFETIME_START\0" |
157 | 0 | /* 1536 */ "DBG_VALUE_LIST\0" |
158 | 0 | /* 1551 */ "DUPLEX\0" |
159 | 0 | /* 1558 */ "isync\0" |
160 | 0 | /* 1564 */ "deallocframe\0" |
161 | 0 | /* 1577 */ "unpause\0" |
162 | 0 | /* 1585 */ "rte\0" |
163 | 0 | /* 1589 */ "k0lock\0" |
164 | 0 | /* 1596 */ "k1lock\0" |
165 | 0 | /* 1603 */ "tlblock\0" |
166 | 0 | /* 1611 */ "k0unlock\0" |
167 | 0 | /* 1620 */ "k1unlock\0" |
168 | 0 | /* 1629 */ "tlbunlock\0" |
169 | 0 | /* 1639 */ "l2gunlock\0" |
170 | 0 | /* 1649 */ "# FEntry call\0" |
171 | 0 | /* 1663 */ "l2kill\0" |
172 | 0 | /* 1670 */ "dckill\0" |
173 | 0 | /* 1677 */ "ickill\0" |
174 | 0 | /* 1684 */ "l2gclean\0" |
175 | 0 | /* 1693 */ "if (!p0) dealloc_return\0" |
176 | 0 | /* 1717 */ "if (p0) dealloc_return\0" |
177 | 0 | /* 1740 */ "nop\0" |
178 | 0 | /* 1744 */ "barrier\0" |
179 | 0 | /* 1752 */ "vwhist256:sat\0" |
180 | 0 | /* 1766 */ "syncht\0" |
181 | 0 | /* 1773 */ "if (!p0.new) dealloc_return:nt\0" |
182 | 0 | /* 1804 */ "if (p0.new) dealloc_return:nt\0" |
183 | 0 | /* 1834 */ "brkpt\0" |
184 | 0 | /* 1840 */ "vhist\0" |
185 | 0 | /* 1846 */ "l2gcleaninv\0" |
186 | 0 | }; |
187 | 0 | #ifdef __GNUC__ |
188 | 0 | #pragma GCC diagnostic pop |
189 | 0 | #endif |
190 | |
|
191 | 0 | static const uint32_t OpInfo0[] = { |
192 | 0 | 0U, // PHI |
193 | 0 | 0U, // INLINEASM |
194 | 0 | 0U, // INLINEASM_BR |
195 | 0 | 0U, // CFI_INSTRUCTION |
196 | 0 | 0U, // EH_LABEL |
197 | 0 | 0U, // GC_LABEL |
198 | 0 | 0U, // ANNOTATION_LABEL |
199 | 0 | 0U, // KILL |
200 | 0 | 0U, // EXTRACT_SUBREG |
201 | 0 | 0U, // INSERT_SUBREG |
202 | 0 | 0U, // IMPLICIT_DEF |
203 | 0 | 0U, // SUBREG_TO_REG |
204 | 0 | 0U, // COPY_TO_REGCLASS |
205 | 0 | 1480U, // DBG_VALUE |
206 | 0 | 1537U, // DBG_VALUE_LIST |
207 | 0 | 1490U, // DBG_INSTR_REF |
208 | 0 | 1504U, // DBG_PHI |
209 | 0 | 1512U, // DBG_LABEL |
210 | 0 | 0U, // REG_SEQUENCE |
211 | 0 | 0U, // COPY |
212 | 0 | 1473U, // BUNDLE |
213 | 0 | 1522U, // LIFETIME_START |
214 | 0 | 1447U, // LIFETIME_END |
215 | 0 | 1460U, // PSEUDO_PROBE |
216 | 0 | 0U, // ARITH_FENCE |
217 | 0 | 0U, // STACKMAP |
218 | 0 | 1650U, // FENTRY_CALL |
219 | 0 | 0U, // PATCHPOINT |
220 | 0 | 0U, // LOAD_STACK_GUARD |
221 | 0 | 0U, // PREALLOCATED_SETUP |
222 | 0 | 0U, // PREALLOCATED_ARG |
223 | 0 | 0U, // STATEPOINT |
224 | 0 | 0U, // LOCAL_ESCAPE |
225 | 0 | 0U, // FAULTING_OP |
226 | 0 | 0U, // PATCHABLE_OP |
227 | 0 | 1230U, // PATCHABLE_FUNCTION_ENTER |
228 | 0 | 1150U, // PATCHABLE_RET |
229 | 0 | 1276U, // PATCHABLE_FUNCTION_EXIT |
230 | 0 | 1253U, // PATCHABLE_TAIL_CALL |
231 | 0 | 1205U, // PATCHABLE_EVENT_CALL |
232 | 0 | 1181U, // PATCHABLE_TYPED_EVENT_CALL |
233 | 0 | 0U, // ICALL_BRANCH_FUNNEL |
234 | 0 | 0U, // MEMBARRIER |
235 | 0 | 0U, // JUMP_TABLE_DEBUG_INFO |
236 | 0 | 0U, // G_ASSERT_SEXT |
237 | 0 | 0U, // G_ASSERT_ZEXT |
238 | 0 | 0U, // G_ASSERT_ALIGN |
239 | 0 | 0U, // G_ADD |
240 | 0 | 0U, // G_SUB |
241 | 0 | 0U, // G_MUL |
242 | 0 | 0U, // G_SDIV |
243 | 0 | 0U, // G_UDIV |
244 | 0 | 0U, // G_SREM |
245 | 0 | 0U, // G_UREM |
246 | 0 | 0U, // G_SDIVREM |
247 | 0 | 0U, // G_UDIVREM |
248 | 0 | 0U, // G_AND |
249 | 0 | 0U, // G_OR |
250 | 0 | 0U, // G_XOR |
251 | 0 | 0U, // G_IMPLICIT_DEF |
252 | 0 | 0U, // G_PHI |
253 | 0 | 0U, // G_FRAME_INDEX |
254 | 0 | 0U, // G_GLOBAL_VALUE |
255 | 0 | 0U, // G_CONSTANT_POOL |
256 | 0 | 0U, // G_EXTRACT |
257 | 0 | 0U, // G_UNMERGE_VALUES |
258 | 0 | 0U, // G_INSERT |
259 | 0 | 0U, // G_MERGE_VALUES |
260 | 0 | 0U, // G_BUILD_VECTOR |
261 | 0 | 0U, // G_BUILD_VECTOR_TRUNC |
262 | 0 | 0U, // G_CONCAT_VECTORS |
263 | 0 | 0U, // G_PTRTOINT |
264 | 0 | 0U, // G_INTTOPTR |
265 | 0 | 0U, // G_BITCAST |
266 | 0 | 0U, // G_FREEZE |
267 | 0 | 0U, // G_CONSTANT_FOLD_BARRIER |
268 | 0 | 0U, // G_INTRINSIC_FPTRUNC_ROUND |
269 | 0 | 0U, // G_INTRINSIC_TRUNC |
270 | 0 | 0U, // G_INTRINSIC_ROUND |
271 | 0 | 0U, // G_INTRINSIC_LRINT |
272 | 0 | 0U, // G_INTRINSIC_ROUNDEVEN |
273 | 0 | 0U, // G_READCYCLECOUNTER |
274 | 0 | 0U, // G_LOAD |
275 | 0 | 0U, // G_SEXTLOAD |
276 | 0 | 0U, // G_ZEXTLOAD |
277 | 0 | 0U, // G_INDEXED_LOAD |
278 | 0 | 0U, // G_INDEXED_SEXTLOAD |
279 | 0 | 0U, // G_INDEXED_ZEXTLOAD |
280 | 0 | 0U, // G_STORE |
281 | 0 | 0U, // G_INDEXED_STORE |
282 | 0 | 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
283 | 0 | 0U, // G_ATOMIC_CMPXCHG |
284 | 0 | 0U, // G_ATOMICRMW_XCHG |
285 | 0 | 0U, // G_ATOMICRMW_ADD |
286 | 0 | 0U, // G_ATOMICRMW_SUB |
287 | 0 | 0U, // G_ATOMICRMW_AND |
288 | 0 | 0U, // G_ATOMICRMW_NAND |
289 | 0 | 0U, // G_ATOMICRMW_OR |
290 | 0 | 0U, // G_ATOMICRMW_XOR |
291 | 0 | 0U, // G_ATOMICRMW_MAX |
292 | 0 | 0U, // G_ATOMICRMW_MIN |
293 | 0 | 0U, // G_ATOMICRMW_UMAX |
294 | 0 | 0U, // G_ATOMICRMW_UMIN |
295 | 0 | 0U, // G_ATOMICRMW_FADD |
296 | 0 | 0U, // G_ATOMICRMW_FSUB |
297 | 0 | 0U, // G_ATOMICRMW_FMAX |
298 | 0 | 0U, // G_ATOMICRMW_FMIN |
299 | 0 | 0U, // G_ATOMICRMW_UINC_WRAP |
300 | 0 | 0U, // G_ATOMICRMW_UDEC_WRAP |
301 | 0 | 0U, // G_FENCE |
302 | 0 | 0U, // G_PREFETCH |
303 | 0 | 0U, // G_BRCOND |
304 | 0 | 0U, // G_BRINDIRECT |
305 | 0 | 0U, // G_INVOKE_REGION_START |
306 | 0 | 0U, // G_INTRINSIC |
307 | 0 | 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
308 | 0 | 0U, // G_INTRINSIC_CONVERGENT |
309 | 0 | 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
310 | 0 | 0U, // G_ANYEXT |
311 | 0 | 0U, // G_TRUNC |
312 | 0 | 0U, // G_CONSTANT |
313 | 0 | 0U, // G_FCONSTANT |
314 | 0 | 0U, // G_VASTART |
315 | 0 | 0U, // G_VAARG |
316 | 0 | 0U, // G_SEXT |
317 | 0 | 0U, // G_SEXT_INREG |
318 | 0 | 0U, // G_ZEXT |
319 | 0 | 0U, // G_SHL |
320 | 0 | 0U, // G_LSHR |
321 | 0 | 0U, // G_ASHR |
322 | 0 | 0U, // G_FSHL |
323 | 0 | 0U, // G_FSHR |
324 | 0 | 0U, // G_ROTR |
325 | 0 | 0U, // G_ROTL |
326 | 0 | 0U, // G_ICMP |
327 | 0 | 0U, // G_FCMP |
328 | 0 | 0U, // G_SELECT |
329 | 0 | 0U, // G_UADDO |
330 | 0 | 0U, // G_UADDE |
331 | 0 | 0U, // G_USUBO |
332 | 0 | 0U, // G_USUBE |
333 | 0 | 0U, // G_SADDO |
334 | 0 | 0U, // G_SADDE |
335 | 0 | 0U, // G_SSUBO |
336 | 0 | 0U, // G_SSUBE |
337 | 0 | 0U, // G_UMULO |
338 | 0 | 0U, // G_SMULO |
339 | 0 | 0U, // G_UMULH |
340 | 0 | 0U, // G_SMULH |
341 | 0 | 0U, // G_UADDSAT |
342 | 0 | 0U, // G_SADDSAT |
343 | 0 | 0U, // G_USUBSAT |
344 | 0 | 0U, // G_SSUBSAT |
345 | 0 | 0U, // G_USHLSAT |
346 | 0 | 0U, // G_SSHLSAT |
347 | 0 | 0U, // G_SMULFIX |
348 | 0 | 0U, // G_UMULFIX |
349 | 0 | 0U, // G_SMULFIXSAT |
350 | 0 | 0U, // G_UMULFIXSAT |
351 | 0 | 0U, // G_SDIVFIX |
352 | 0 | 0U, // G_UDIVFIX |
353 | 0 | 0U, // G_SDIVFIXSAT |
354 | 0 | 0U, // G_UDIVFIXSAT |
355 | 0 | 0U, // G_FADD |
356 | 0 | 0U, // G_FSUB |
357 | 0 | 0U, // G_FMUL |
358 | 0 | 0U, // G_FMA |
359 | 0 | 0U, // G_FMAD |
360 | 0 | 0U, // G_FDIV |
361 | 0 | 0U, // G_FREM |
362 | 0 | 0U, // G_FPOW |
363 | 0 | 0U, // G_FPOWI |
364 | 0 | 0U, // G_FEXP |
365 | 0 | 0U, // G_FEXP2 |
366 | 0 | 0U, // G_FEXP10 |
367 | 0 | 0U, // G_FLOG |
368 | 0 | 0U, // G_FLOG2 |
369 | 0 | 0U, // G_FLOG10 |
370 | 0 | 0U, // G_FLDEXP |
371 | 0 | 0U, // G_FFREXP |
372 | 0 | 0U, // G_FNEG |
373 | 0 | 0U, // G_FPEXT |
374 | 0 | 0U, // G_FPTRUNC |
375 | 0 | 0U, // G_FPTOSI |
376 | 0 | 0U, // G_FPTOUI |
377 | 0 | 0U, // G_SITOFP |
378 | 0 | 0U, // G_UITOFP |
379 | 0 | 0U, // G_FABS |
380 | 0 | 0U, // G_FCOPYSIGN |
381 | 0 | 0U, // G_IS_FPCLASS |
382 | 0 | 0U, // G_FCANONICALIZE |
383 | 0 | 0U, // G_FMINNUM |
384 | 0 | 0U, // G_FMAXNUM |
385 | 0 | 0U, // G_FMINNUM_IEEE |
386 | 0 | 0U, // G_FMAXNUM_IEEE |
387 | 0 | 0U, // G_FMINIMUM |
388 | 0 | 0U, // G_FMAXIMUM |
389 | 0 | 0U, // G_GET_FPENV |
390 | 0 | 0U, // G_SET_FPENV |
391 | 0 | 0U, // G_RESET_FPENV |
392 | 0 | 0U, // G_GET_FPMODE |
393 | 0 | 0U, // G_SET_FPMODE |
394 | 0 | 0U, // G_RESET_FPMODE |
395 | 0 | 0U, // G_PTR_ADD |
396 | 0 | 0U, // G_PTRMASK |
397 | 0 | 0U, // G_SMIN |
398 | 0 | 0U, // G_SMAX |
399 | 0 | 0U, // G_UMIN |
400 | 0 | 0U, // G_UMAX |
401 | 0 | 0U, // G_ABS |
402 | 0 | 0U, // G_LROUND |
403 | 0 | 0U, // G_LLROUND |
404 | 0 | 0U, // G_BR |
405 | 0 | 0U, // G_BRJT |
406 | 0 | 0U, // G_INSERT_VECTOR_ELT |
407 | 0 | 0U, // G_EXTRACT_VECTOR_ELT |
408 | 0 | 0U, // G_SHUFFLE_VECTOR |
409 | 0 | 0U, // G_CTTZ |
410 | 0 | 0U, // G_CTTZ_ZERO_UNDEF |
411 | 0 | 0U, // G_CTLZ |
412 | 0 | 0U, // G_CTLZ_ZERO_UNDEF |
413 | 0 | 0U, // G_CTPOP |
414 | 0 | 0U, // G_BSWAP |
415 | 0 | 0U, // G_BITREVERSE |
416 | 0 | 0U, // G_FCEIL |
417 | 0 | 0U, // G_FCOS |
418 | 0 | 0U, // G_FSIN |
419 | 0 | 0U, // G_FSQRT |
420 | 0 | 0U, // G_FFLOOR |
421 | 0 | 0U, // G_FRINT |
422 | 0 | 0U, // G_FNEARBYINT |
423 | 0 | 0U, // G_ADDRSPACE_CAST |
424 | 0 | 0U, // G_BLOCK_ADDR |
425 | 0 | 0U, // G_JUMP_TABLE |
426 | 0 | 0U, // G_DYN_STACKALLOC |
427 | 0 | 0U, // G_STACKSAVE |
428 | 0 | 0U, // G_STACKRESTORE |
429 | 0 | 0U, // G_STRICT_FADD |
430 | 0 | 0U, // G_STRICT_FSUB |
431 | 0 | 0U, // G_STRICT_FMUL |
432 | 0 | 0U, // G_STRICT_FDIV |
433 | 0 | 0U, // G_STRICT_FREM |
434 | 0 | 0U, // G_STRICT_FMA |
435 | 0 | 0U, // G_STRICT_FSQRT |
436 | 0 | 0U, // G_STRICT_FLDEXP |
437 | 0 | 0U, // G_READ_REGISTER |
438 | 0 | 0U, // G_WRITE_REGISTER |
439 | 0 | 0U, // G_MEMCPY |
440 | 0 | 0U, // G_MEMCPY_INLINE |
441 | 0 | 0U, // G_MEMMOVE |
442 | 0 | 0U, // G_MEMSET |
443 | 0 | 0U, // G_BZERO |
444 | 0 | 0U, // G_VECREDUCE_SEQ_FADD |
445 | 0 | 0U, // G_VECREDUCE_SEQ_FMUL |
446 | 0 | 0U, // G_VECREDUCE_FADD |
447 | 0 | 0U, // G_VECREDUCE_FMUL |
448 | 0 | 0U, // G_VECREDUCE_FMAX |
449 | 0 | 0U, // G_VECREDUCE_FMIN |
450 | 0 | 0U, // G_VECREDUCE_FMAXIMUM |
451 | 0 | 0U, // G_VECREDUCE_FMINIMUM |
452 | 0 | 0U, // G_VECREDUCE_ADD |
453 | 0 | 0U, // G_VECREDUCE_MUL |
454 | 0 | 0U, // G_VECREDUCE_AND |
455 | 0 | 0U, // G_VECREDUCE_OR |
456 | 0 | 0U, // G_VECREDUCE_XOR |
457 | 0 | 0U, // G_VECREDUCE_SMAX |
458 | 0 | 0U, // G_VECREDUCE_SMIN |
459 | 0 | 0U, // G_VECREDUCE_UMAX |
460 | 0 | 0U, // G_VECREDUCE_UMIN |
461 | 0 | 0U, // G_SBFX |
462 | 0 | 0U, // G_UBFX |
463 | 0 | 2074U, // A2_addsp |
464 | 0 | 18458U, // A2_iconst |
465 | 0 | 16812058U, // A2_neg |
466 | 0 | 51226U, // A2_not |
467 | 0 | 33624179U, // A2_tfrf |
468 | 0 | 33640563U, // A2_tfrfnew |
469 | 0 | 50432026U, // A2_tfrp |
470 | 0 | 33624179U, // A2_tfrpf |
471 | 0 | 33640563U, // A2_tfrpfnew |
472 | 0 | 50448410U, // A2_tfrpi |
473 | 0 | 33624358U, // A2_tfrpt |
474 | 0 | 33640742U, // A2_tfrptnew |
475 | 0 | 33624358U, // A2_tfrt |
476 | 0 | 33640742U, // A2_tfrtnew |
477 | 0 | 16910362U, // A2_vaddb_map |
478 | 0 | 16926746U, // A2_vsubb_map |
479 | 0 | 165914U, // A2_zxtb |
480 | 0 | 16959514U, // A4_boundscheck |
481 | 0 | 1U, // ADJCALLSTACKDOWN |
482 | 0 | 1U, // ADJCALLSTACKUP |
483 | 0 | 198682U, // C2_cmpgei |
484 | 0 | 215066U, // C2_cmpgeui |
485 | 0 | 231450U, // C2_cmplt |
486 | 0 | 247834U, // C2_cmpltu |
487 | 0 | 50432026U, // C2_pxfer_map |
488 | 0 | 1552U, // DUPLEX_Pseudo |
489 | 0 | 1298U, // ENDLOOP0 |
490 | 0 | 1308U, // ENDLOOP01 |
491 | 0 | 1407U, // ENDLOOP1 |
492 | 0 | 1299U, // J2_endloop0 |
493 | 0 | 1309U, // J2_endloop01 |
494 | 0 | 1408U, // J2_endloop1 |
495 | 0 | 264307U, // J2_jumpf_nopred_map |
496 | 0 | 280691U, // J2_jumprf_nopred_map |
497 | 0 | 280870U, // J2_jumprt_nopred_map |
498 | 0 | 264486U, // J2_jumpt_nopred_map |
499 | 0 | 297114U, // J2_trap1_noregmap |
500 | 0 | 67422234U, // L2_loadalignb_zomap |
501 | 0 | 67438618U, // L2_loadalignh_zomap |
502 | 0 | 17123354U, // L2_loadbsw2_zomap |
503 | 0 | 17123354U, // L2_loadbsw4_zomap |
504 | 0 | 17139738U, // L2_loadbzw2_zomap |
505 | 0 | 17139738U, // L2_loadbzw4_zomap |
506 | 0 | 17156122U, // L2_loadrb_zomap |
507 | 0 | 17172506U, // L2_loadrd_zomap |
508 | 0 | 17188890U, // L2_loadrh_zomap |
509 | 0 | 17205274U, // L2_loadri_zomap |
510 | 0 | 17221658U, // L2_loadrub_zomap |
511 | 0 | 17238042U, // L2_loadruh_zomap |
512 | 0 | 83955827U, // L2_ploadrbf_zomap |
513 | 0 | 83972211U, // L2_ploadrbfnew_zomap |
514 | 0 | 83956006U, // L2_ploadrbt_zomap |
515 | 0 | 83972390U, // L2_ploadrbtnew_zomap |
516 | 0 | 100733043U, // L2_ploadrdf_zomap |
517 | 0 | 100749427U, // L2_ploadrdfnew_zomap |
518 | 0 | 100733222U, // L2_ploadrdt_zomap |
519 | 0 | 100749606U, // L2_ploadrdtnew_zomap |
520 | 0 | 117510259U, // L2_ploadrhf_zomap |
521 | 0 | 117526643U, // L2_ploadrhfnew_zomap |
522 | 0 | 117510438U, // L2_ploadrht_zomap |
523 | 0 | 117526822U, // L2_ploadrhtnew_zomap |
524 | 0 | 134287475U, // L2_ploadrif_zomap |
525 | 0 | 134303859U, // L2_ploadrifnew_zomap |
526 | 0 | 134287654U, // L2_ploadrit_zomap |
527 | 0 | 134304038U, // L2_ploadritnew_zomap |
528 | 0 | 151064691U, // L2_ploadrubf_zomap |
529 | 0 | 151081075U, // L2_ploadrubfnew_zomap |
530 | 0 | 151064870U, // L2_ploadrubt_zomap |
531 | 0 | 151081254U, // L2_ploadrubtnew_zomap |
532 | 0 | 167841907U, // L2_ploadruhf_zomap |
533 | 0 | 167858291U, // L2_ploadruhfnew_zomap |
534 | 0 | 167842086U, // L2_ploadruht_zomap |
535 | 0 | 167858470U, // L2_ploadruhtnew_zomap |
536 | 0 | 477648U, // L4_add_memopb_zomap |
537 | 0 | 477780U, // L4_add_memoph_zomap |
538 | 0 | 478226U, // L4_add_memopw_zomap |
539 | 0 | 494032U, // L4_and_memopb_zomap |
540 | 0 | 494164U, // L4_and_memoph_zomap |
541 | 0 | 494610U, // L4_and_memopw_zomap |
542 | 0 | 510416U, // L4_iadd_memopb_zomap |
543 | 0 | 510548U, // L4_iadd_memoph_zomap |
544 | 0 | 510994U, // L4_iadd_memopw_zomap |
545 | 0 | 526800U, // L4_iand_memopb_zomap |
546 | 0 | 526932U, // L4_iand_memoph_zomap |
547 | 0 | 527378U, // L4_iand_memopw_zomap |
548 | 0 | 543184U, // L4_ior_memopb_zomap |
549 | 0 | 543316U, // L4_ior_memoph_zomap |
550 | 0 | 543762U, // L4_ior_memopw_zomap |
551 | 0 | 559568U, // L4_isub_memopb_zomap |
552 | 0 | 559700U, // L4_isub_memoph_zomap |
553 | 0 | 560146U, // L4_isub_memopw_zomap |
554 | 0 | 575952U, // L4_or_memopb_zomap |
555 | 0 | 576084U, // L4_or_memoph_zomap |
556 | 0 | 576530U, // L4_or_memopw_zomap |
557 | 0 | 591987U, // L4_return_map_to_raw_f |
558 | 0 | 608371U, // L4_return_map_to_raw_fnew_pnt |
559 | 0 | 624755U, // L4_return_map_to_raw_fnew_pt |
560 | 0 | 592166U, // L4_return_map_to_raw_t |
561 | 0 | 608550U, // L4_return_map_to_raw_tnew_pnt |
562 | 0 | 624934U, // L4_return_map_to_raw_tnew_pt |
563 | 0 | 641488U, // L4_sub_memopb_zomap |
564 | 0 | 641620U, // L4_sub_memoph_zomap |
565 | 0 | 642066U, // L4_sub_memopw_zomap |
566 | 0 | 1565U, // L6_deallocframe_map_to_raw |
567 | 0 | 1703U, // L6_return_map_to_raw |
568 | 0 | 121U, // LDriw_ctr |
569 | 0 | 121U, // LDriw_pred |
570 | 0 | 185206810U, // M2_mpysmi |
571 | 0 | 673818U, // M2_mpyui |
572 | 0 | 202016794U, // M2_vrcmpys_acc_s1 |
573 | 0 | 202033178U, // M2_vrcmpys_s1 |
574 | 0 | 218810394U, // M2_vrcmpys_s1rp |
575 | 0 | 722970U, // M7_vdmpy |
576 | 0 | 739354U, // M7_vdmpy_acc |
577 | 0 | 0U, // PS_aligna |
578 | 0 | 0U, // PS_alloca |
579 | 0 | 0U, // PS_call_instrprof_custom |
580 | 0 | 0U, // PS_call_nr |
581 | 0 | 0U, // PS_crash |
582 | 0 | 0U, // PS_false |
583 | 0 | 0U, // PS_fi |
584 | 0 | 0U, // PS_fia |
585 | 0 | 1U, // PS_loadrb_pci |
586 | 0 | 1U, // PS_loadrb_pcr |
587 | 0 | 1U, // PS_loadrd_pci |
588 | 0 | 1U, // PS_loadrd_pcr |
589 | 0 | 1U, // PS_loadrh_pci |
590 | 0 | 1U, // PS_loadrh_pcr |
591 | 0 | 1U, // PS_loadri_pci |
592 | 0 | 1U, // PS_loadri_pcr |
593 | 0 | 1U, // PS_loadrub_pci |
594 | 0 | 1U, // PS_loadrub_pcr |
595 | 0 | 1U, // PS_loadruh_pci |
596 | 0 | 1U, // PS_loadruh_pcr |
597 | 0 | 1U, // PS_pselect |
598 | 0 | 0U, // PS_qfalse |
599 | 0 | 0U, // PS_qtrue |
600 | 0 | 1U, // PS_storerb_pci |
601 | 0 | 1U, // PS_storerb_pcr |
602 | 0 | 1U, // PS_storerd_pci |
603 | 0 | 1U, // PS_storerd_pcr |
604 | 0 | 1U, // PS_storerf_pci |
605 | 0 | 1U, // PS_storerf_pcr |
606 | 0 | 1U, // PS_storerh_pci |
607 | 0 | 1U, // PS_storerh_pcr |
608 | 0 | 1U, // PS_storeri_pci |
609 | 0 | 1U, // PS_storeri_pcr |
610 | 0 | 0U, // PS_tailcall_i |
611 | 0 | 755820U, // PS_tailcall_r |
612 | 0 | 0U, // PS_true |
613 | 0 | 0U, // PS_vdd0 |
614 | 0 | 0U, // PS_vloadrq_ai |
615 | 0 | 0U, // PS_vloadrv_ai |
616 | 0 | 0U, // PS_vloadrv_nt_ai |
617 | 0 | 0U, // PS_vloadrw_ai |
618 | 0 | 0U, // PS_vloadrw_nt_ai |
619 | 0 | 0U, // PS_vmulw |
620 | 0 | 0U, // PS_vmulw_acc |
621 | 0 | 0U, // PS_vselect |
622 | 0 | 0U, // PS_vsplatib |
623 | 0 | 0U, // PS_vsplatih |
624 | 0 | 0U, // PS_vsplatiw |
625 | 0 | 0U, // PS_vsplatrb |
626 | 0 | 0U, // PS_vsplatrh |
627 | 0 | 0U, // PS_vsplatrw |
628 | 0 | 0U, // PS_vstorerq_ai |
629 | 0 | 0U, // PS_vstorerv_ai |
630 | 0 | 0U, // PS_vstorerv_nt_ai |
631 | 0 | 0U, // PS_vstorerw_ai |
632 | 0 | 0U, // PS_vstorerw_nt_ai |
633 | 0 | 0U, // PS_wselect |
634 | 0 | 772122U, // S2_asr_i_p_rnd_goodsyntax |
635 | 0 | 772122U, // S2_asr_i_r_rnd_goodsyntax |
636 | 0 | 788595U, // S2_pstorerbf_zomap |
637 | 0 | 788595U, // S2_pstorerbnewf_zomap |
638 | 0 | 788774U, // S2_pstorerbnewt_zomap |
639 | 0 | 788774U, // S2_pstorerbt_zomap |
640 | 0 | 804979U, // S2_pstorerdf_zomap |
641 | 0 | 805158U, // S2_pstorerdt_zomap |
642 | 0 | 821363U, // S2_pstorerff_zomap |
643 | 0 | 821542U, // S2_pstorerft_zomap |
644 | 0 | 821363U, // S2_pstorerhf_zomap |
645 | 0 | 821363U, // S2_pstorerhnewf_zomap |
646 | 0 | 821542U, // S2_pstorerhnewt_zomap |
647 | 0 | 821542U, // S2_pstorerht_zomap |
648 | 0 | 837747U, // S2_pstorerif_zomap |
649 | 0 | 837747U, // S2_pstorerinewf_zomap |
650 | 0 | 837926U, // S2_pstorerinewt_zomap |
651 | 0 | 837926U, // S2_pstorerit_zomap |
652 | 0 | 51186128U, // S2_storerb_zomap |
653 | 0 | 235735504U, // S2_storerbnew_zomap |
654 | 0 | 51186184U, // S2_storerd_zomap |
655 | 0 | 252512852U, // S2_storerf_zomap |
656 | 0 | 51186260U, // S2_storerh_zomap |
657 | 0 | 235735636U, // S2_storerhnew_zomap |
658 | 0 | 51186706U, // S2_storeri_zomap |
659 | 0 | 235736082U, // S2_storerinew_zomap |
660 | 0 | 17647642U, // S2_tableidxb_goodsyntax |
661 | 0 | 17664026U, // S2_tableidxd_goodsyntax |
662 | 0 | 17680410U, // S2_tableidxh_goodsyntax |
663 | 0 | 17696794U, // S2_tableidxw_goodsyntax |
664 | 0 | 936051U, // S4_pstorerbfnew_zomap |
665 | 0 | 936051U, // S4_pstorerbnewfnew_zomap |
666 | 0 | 936230U, // S4_pstorerbnewtnew_zomap |
667 | 0 | 936230U, // S4_pstorerbtnew_zomap |
668 | 0 | 952435U, // S4_pstorerdfnew_zomap |
669 | 0 | 952614U, // S4_pstorerdtnew_zomap |
670 | 0 | 968819U, // S4_pstorerffnew_zomap |
671 | 0 | 968998U, // S4_pstorerftnew_zomap |
672 | 0 | 968819U, // S4_pstorerhfnew_zomap |
673 | 0 | 968819U, // S4_pstorerhnewfnew_zomap |
674 | 0 | 968998U, // S4_pstorerhnewtnew_zomap |
675 | 0 | 968998U, // S4_pstorerhtnew_zomap |
676 | 0 | 985203U, // S4_pstorerifnew_zomap |
677 | 0 | 985203U, // S4_pstorerinewfnew_zomap |
678 | 0 | 985382U, // S4_pstorerinewtnew_zomap |
679 | 0 | 985382U, // S4_pstoreritnew_zomap |
680 | 0 | 1001936U, // S4_storeirb_zomap |
681 | 0 | 788595U, // S4_storeirbf_zomap |
682 | 0 | 936051U, // S4_storeirbfnew_zomap |
683 | 0 | 788774U, // S4_storeirbt_zomap |
684 | 0 | 936230U, // S4_storeirbtnew_zomap |
685 | 0 | 1002068U, // S4_storeirh_zomap |
686 | 0 | 821363U, // S4_storeirhf_zomap |
687 | 0 | 968819U, // S4_storeirhfnew_zomap |
688 | 0 | 821542U, // S4_storeirht_zomap |
689 | 0 | 968998U, // S4_storeirhtnew_zomap |
690 | 0 | 1002514U, // S4_storeiri_zomap |
691 | 0 | 837747U, // S4_storeirif_zomap |
692 | 0 | 985203U, // S4_storeirifnew_zomap |
693 | 0 | 837926U, // S4_storeirit_zomap |
694 | 0 | 985382U, // S4_storeiritnew_zomap |
695 | 0 | 269453338U, // S5_asrhub_rnd_sat_goodsyntax |
696 | 0 | 185583642U, // S5_vasrhrnd_goodsyntax |
697 | 0 | 297148U, // S6_allocframe_to_raw |
698 | 0 | 121U, // STriw_ctr |
699 | 0 | 121U, // STriw_pred |
700 | 0 | 286263322U, // V6_MAP_equb |
701 | 0 | 286279706U, // V6_MAP_equb_and |
702 | 0 | 286296090U, // V6_MAP_equb_ior |
703 | 0 | 286312474U, // V6_MAP_equb_xor |
704 | 0 | 303040538U, // V6_MAP_equh |
705 | 0 | 303056922U, // V6_MAP_equh_and |
706 | 0 | 303073306U, // V6_MAP_equh_ior |
707 | 0 | 303089690U, // V6_MAP_equh_xor |
708 | 0 | 319817754U, // V6_MAP_equw |
709 | 0 | 319834138U, // V6_MAP_equw_and |
710 | 0 | 319850522U, // V6_MAP_equw_ior |
711 | 0 | 319866906U, // V6_MAP_equw_xor |
712 | 0 | 17893402U, // V6_dbl_ld0 |
713 | 0 | 51186324U, // V6_dbl_st0 |
714 | 0 | 1132570U, // V6_extractw_alt |
715 | 0 | 1148954U, // V6_hi |
716 | 0 | 17893402U, // V6_ld0 |
717 | 0 | 335614067U, // V6_ldcnp0 |
718 | 0 | 335614067U, // V6_ldcnpnt0 |
719 | 0 | 335614246U, // V6_ldcp0 |
720 | 0 | 335614246U, // V6_ldcpnt0 |
721 | 0 | 352391283U, // V6_ldnp0 |
722 | 0 | 352391283U, // V6_ldnpnt0 |
723 | 0 | 370214938U, // V6_ldnt0 |
724 | 0 | 352391462U, // V6_ldp0 |
725 | 0 | 352391462U, // V6_ldpnt0 |
726 | 0 | 385945715U, // V6_ldtnp0 |
727 | 0 | 385945715U, // V6_ldtnpnt0 |
728 | 0 | 385945894U, // V6_ldtp0 |
729 | 0 | 385945894U, // V6_ldtpnt0 |
730 | 0 | 17942554U, // V6_ldu0 |
731 | 0 | 1181722U, // V6_lo |
732 | 0 | 51186324U, // V6_st0 |
733 | 0 | 235735700U, // V6_stn0 |
734 | 0 | 236079764U, // V6_stnnt0 |
735 | 0 | 1214579U, // V6_stnp0 |
736 | 0 | 1214579U, // V6_stnpnt0 |
737 | 0 | 1214579U, // V6_stnq0 |
738 | 0 | 1214579U, // V6_stnqnt0 |
739 | 0 | 51530388U, // V6_stnt0 |
740 | 0 | 1214758U, // V6_stp0 |
741 | 0 | 1214758U, // V6_stpnt0 |
742 | 0 | 1214758U, // V6_stq0 |
743 | 0 | 1214758U, // V6_stqnt0 |
744 | 0 | 51186592U, // V6_stu0 |
745 | 0 | 1230963U, // V6_stunp0 |
746 | 0 | 1231142U, // V6_stup0 |
747 | 0 | 1247258U, // V6_v10mpyubs10 |
748 | 0 | 1263642U, // V6_v10mpyubs10_vxx |
749 | 0 | 403933210U, // V6_v6mpyhubs10_alt |
750 | 0 | 403933210U, // V6_v6mpyvubs10_alt |
751 | 0 | 18073626U, // V6_vabsb_alt |
752 | 0 | 420726810U, // V6_vabsb_sat_alt |
753 | 0 | 1312794U, // V6_vabsdiffh_alt |
754 | 0 | 1329178U, // V6_vabsdiffub_alt |
755 | 0 | 1345562U, // V6_vabsdiffuh_alt |
756 | 0 | 1361946U, // V6_vabsdiffw_alt |
757 | 0 | 18155546U, // V6_vabsh_alt |
758 | 0 | 420808730U, // V6_vabsh_sat_alt |
759 | 0 | 1394714U, // V6_vabsub_alt |
760 | 0 | 1411098U, // V6_vabsuh_alt |
761 | 0 | 1427482U, // V6_vabsuw_alt |
762 | 0 | 18221082U, // V6_vabsw_alt |
763 | 0 | 420874266U, // V6_vabsw_sat_alt |
764 | 0 | 16910362U, // V6_vaddb_alt |
765 | 0 | 16910362U, // V6_vaddb_dv_alt |
766 | 0 | 437670003U, // V6_vaddbnq_alt |
767 | 0 | 437670182U, // V6_vaddbq_alt |
768 | 0 | 419563546U, // V6_vaddbsat_alt |
769 | 0 | 419563546U, // V6_vaddbsat_dv_alt |
770 | 0 | 18253850U, // V6_vaddh_alt |
771 | 0 | 18253850U, // V6_vaddh_dv_alt |
772 | 0 | 454479987U, // V6_vaddhnq_alt |
773 | 0 | 454480166U, // V6_vaddhq_alt |
774 | 0 | 420907034U, // V6_vaddhsat_alt |
775 | 0 | 420907034U, // V6_vaddhsat_dv_alt |
776 | 0 | 1509402U, // V6_vaddhw_acc_alt |
777 | 0 | 18253850U, // V6_vaddhw_alt |
778 | 0 | 1525786U, // V6_vaddubh_acc_alt |
779 | 0 | 18319386U, // V6_vaddubh_alt |
780 | 0 | 420972570U, // V6_vaddubsat_alt |
781 | 0 | 420972570U, // V6_vaddubsat_dv_alt |
782 | 0 | 420988954U, // V6_vadduhsat_alt |
783 | 0 | 420988954U, // V6_vadduhsat_dv_alt |
784 | 0 | 1574938U, // V6_vadduhw_acc_alt |
785 | 0 | 18335770U, // V6_vadduhw_alt |
786 | 0 | 1591322U, // V6_vadduwsat_alt |
787 | 0 | 1591322U, // V6_vadduwsat_dv_alt |
788 | 0 | 18384922U, // V6_vaddw_alt |
789 | 0 | 18384922U, // V6_vaddw_dv_alt |
790 | 0 | 471388275U, // V6_vaddwnq_alt |
791 | 0 | 471388454U, // V6_vaddwq_alt |
792 | 0 | 421038106U, // V6_vaddwsat_alt |
793 | 0 | 421038106U, // V6_vaddwsat_dv_alt |
794 | 0 | 1640474U, // V6_vandnqrt_acc_alt |
795 | 0 | 1656858U, // V6_vandnqrt_alt |
796 | 0 | 1673242U, // V6_vandqrt_acc_alt |
797 | 0 | 1689626U, // V6_vandqrt_alt |
798 | 0 | 1673242U, // V6_vandvrt_acc_alt |
799 | 0 | 1689626U, // V6_vandvrt_alt |
800 | 0 | 1706010U, // V6_vaslh_acc_alt |
801 | 0 | 488261658U, // V6_vaslh_alt |
802 | 0 | 488261658U, // V6_vaslhv_alt |
803 | 0 | 1738778U, // V6_vaslw_acc_alt |
804 | 0 | 488294426U, // V6_vaslw_alt |
805 | 0 | 488294426U, // V6_vaslwv_alt |
806 | 0 | 1771546U, // V6_vasr_into_alt |
807 | 0 | 1787930U, // V6_vasrh_acc_alt |
808 | 0 | 487573530U, // V6_vasrh_alt |
809 | 0 | 487573530U, // V6_vasrhv_alt |
810 | 0 | 1804314U, // V6_vasrw_acc_alt |
811 | 0 | 488359962U, // V6_vasrw_alt |
812 | 0 | 488359962U, // V6_vasrwv_alt |
813 | 0 | 50432026U, // V6_vassignp |
814 | 0 | 18614298U, // V6_vavgb_alt |
815 | 0 | 505153562U, // V6_vavgbrnd_alt |
816 | 0 | 18630682U, // V6_vavgh_alt |
817 | 0 | 505169946U, // V6_vavghrnd_alt |
818 | 0 | 18647066U, // V6_vavgub_alt |
819 | 0 | 505186330U, // V6_vavgubrnd_alt |
820 | 0 | 18663450U, // V6_vavguh_alt |
821 | 0 | 505202714U, // V6_vavguhrnd_alt |
822 | 0 | 18679834U, // V6_vavguw_alt |
823 | 0 | 505219098U, // V6_vavguwrnd_alt |
824 | 0 | 18696218U, // V6_vavgw_alt |
825 | 0 | 505235482U, // V6_vavgwrnd_alt |
826 | 0 | 1935386U, // V6_vcl0h_alt |
827 | 0 | 1951770U, // V6_vcl0w_alt |
828 | 0 | 1968154U, // V6_vd0 |
829 | 0 | 1968154U, // V6_vdd0 |
830 | 0 | 1984538U, // V6_vdealb4w_alt |
831 | 0 | 2000922U, // V6_vdealb_alt |
832 | 0 | 2017306U, // V6_vdealh_alt |
833 | 0 | 2033690U, // V6_vdmpybus_acc_alt |
834 | 0 | 2050074U, // V6_vdmpybus_alt |
835 | 0 | 2033690U, // V6_vdmpybus_dv_acc_alt |
836 | 0 | 2050074U, // V6_vdmpybus_dv_alt |
837 | 0 | 2066458U, // V6_vdmpyhb_acc_alt |
838 | 0 | 2082842U, // V6_vdmpyhb_alt |
839 | 0 | 2066458U, // V6_vdmpyhb_dv_acc_alt |
840 | 0 | 2082842U, // V6_vdmpyhb_dv_alt |
841 | 0 | 2099226U, // V6_vdmpyhisat_acc_alt |
842 | 0 | 2115610U, // V6_vdmpyhisat_alt |
843 | 0 | 2099226U, // V6_vdmpyhsat_acc_alt |
844 | 0 | 2115610U, // V6_vdmpyhsat_alt |
845 | 0 | 522225690U, // V6_vdmpyhsuisat_acc_alt |
846 | 0 | 522242074U, // V6_vdmpyhsuisat_alt |
847 | 0 | 421562394U, // V6_vdmpyhsusat_acc_alt |
848 | 0 | 421578778U, // V6_vdmpyhsusat_alt |
849 | 0 | 2099226U, // V6_vdmpyhvsat_acc_alt |
850 | 0 | 2115610U, // V6_vdmpyhvsat_alt |
851 | 0 | 2164762U, // V6_vdsaduh_acc_alt |
852 | 0 | 2181146U, // V6_vdsaduh_alt |
853 | 0 | 1U, // V6_vgathermh_pseudo |
854 | 0 | 1U, // V6_vgathermhq_pseudo |
855 | 0 | 1U, // V6_vgathermhw_pseudo |
856 | 0 | 1U, // V6_vgathermhwq_pseudo |
857 | 0 | 1U, // V6_vgathermw_pseudo |
858 | 0 | 1U, // V6_vgathermwq_pseudo |
859 | 0 | 488736794U, // V6_vlsrh_alt |
860 | 0 | 488736794U, // V6_vlsrhv_alt |
861 | 0 | 488753178U, // V6_vlsrw_alt |
862 | 0 | 488753178U, // V6_vlsrwv_alt |
863 | 0 | 2230298U, // V6_vmaxb_alt |
864 | 0 | 2246682U, // V6_vmaxh_alt |
865 | 0 | 2263066U, // V6_vmaxub_alt |
866 | 0 | 2279450U, // V6_vmaxuh_alt |
867 | 0 | 2295834U, // V6_vmaxw_alt |
868 | 0 | 2312218U, // V6_vminb_alt |
869 | 0 | 2328602U, // V6_vminh_alt |
870 | 0 | 2344986U, // V6_vminub_alt |
871 | 0 | 2361370U, // V6_vminuh_alt |
872 | 0 | 2377754U, // V6_vminw_alt |
873 | 0 | 2394138U, // V6_vmpabus_acc_alt |
874 | 0 | 2410522U, // V6_vmpabus_alt |
875 | 0 | 2410522U, // V6_vmpabusv_alt |
876 | 0 | 2426906U, // V6_vmpabuu_acc_alt |
877 | 0 | 2443290U, // V6_vmpabuu_alt |
878 | 0 | 2443290U, // V6_vmpabuuv_alt |
879 | 0 | 2459674U, // V6_vmpahb_acc_alt |
880 | 0 | 2476058U, // V6_vmpahb_alt |
881 | 0 | 2492442U, // V6_vmpauhb_acc_alt |
882 | 0 | 2508826U, // V6_vmpauhb_alt |
883 | 0 | 2525210U, // V6_vmpybus_acc_alt |
884 | 0 | 2541594U, // V6_vmpybus_alt |
885 | 0 | 2525210U, // V6_vmpybusv_acc_alt |
886 | 0 | 2541594U, // V6_vmpybusv_alt |
887 | 0 | 2557978U, // V6_vmpybv_acc_alt |
888 | 0 | 2574362U, // V6_vmpybv_alt |
889 | 0 | 2590746U, // V6_vmpyewuh_alt |
890 | 0 | 19384346U, // V6_vmpyh_acc_alt |
891 | 0 | 19400730U, // V6_vmpyh_alt |
892 | 0 | 422037530U, // V6_vmpyhsat_acc_alt |
893 | 0 | 220727322U, // V6_vmpyhsrs_alt |
894 | 0 | 203950106U, // V6_vmpyhss_alt |
895 | 0 | 2639898U, // V6_vmpyhus_acc_alt |
896 | 0 | 2656282U, // V6_vmpyhus_alt |
897 | 0 | 19384346U, // V6_vmpyhv_acc_alt |
898 | 0 | 19400730U, // V6_vmpyhv_alt |
899 | 0 | 220727322U, // V6_vmpyhvsrs_alt |
900 | 0 | 2672666U, // V6_vmpyiewh_acc_alt |
901 | 0 | 2689050U, // V6_vmpyiewuh_acc_alt |
902 | 0 | 2705434U, // V6_vmpyiewuh_alt |
903 | 0 | 2721818U, // V6_vmpyih_acc_alt |
904 | 0 | 2738202U, // V6_vmpyih_alt |
905 | 0 | 2754586U, // V6_vmpyihb_acc_alt |
906 | 0 | 2770970U, // V6_vmpyihb_alt |
907 | 0 | 2787354U, // V6_vmpyiowh_alt |
908 | 0 | 2803738U, // V6_vmpyiwb_acc_alt |
909 | 0 | 2820122U, // V6_vmpyiwb_alt |
910 | 0 | 2836506U, // V6_vmpyiwh_acc_alt |
911 | 0 | 2852890U, // V6_vmpyiwh_alt |
912 | 0 | 2869274U, // V6_vmpyiwub_acc_alt |
913 | 0 | 2885658U, // V6_vmpyiwub_alt |
914 | 0 | 204228634U, // V6_vmpyowh_alt |
915 | 0 | 221005850U, // V6_vmpyowh_rnd_alt |
916 | 0 | 539789338U, // V6_vmpyowh_rnd_sacc_alt |
917 | 0 | 556566554U, // V6_vmpyowh_sacc_alt |
918 | 0 | 2934810U, // V6_vmpyub_acc_alt |
919 | 0 | 2951194U, // V6_vmpyub_alt |
920 | 0 | 2934810U, // V6_vmpyubv_acc_alt |
921 | 0 | 2951194U, // V6_vmpyubv_alt |
922 | 0 | 2967578U, // V6_vmpyuh_acc_alt |
923 | 0 | 2983962U, // V6_vmpyuh_alt |
924 | 0 | 2967578U, // V6_vmpyuhv_acc_alt |
925 | 0 | 2983962U, // V6_vmpyuhv_alt |
926 | 0 | 3000346U, // V6_vnavgb_alt |
927 | 0 | 19793946U, // V6_vnavgh_alt |
928 | 0 | 3033114U, // V6_vnavgub_alt |
929 | 0 | 19826714U, // V6_vnavgw_alt |
930 | 0 | 3065882U, // V6_vnormamth_alt |
931 | 0 | 3082266U, // V6_vnormamtw_alt |
932 | 0 | 3098650U, // V6_vpackeb_alt |
933 | 0 | 3115034U, // V6_vpackeh_alt |
934 | 0 | 3131418U, // V6_vpackhb_sat_alt |
935 | 0 | 3147802U, // V6_vpackhub_sat_alt |
936 | 0 | 3164186U, // V6_vpackob_alt |
937 | 0 | 3180570U, // V6_vpackoh_alt |
938 | 0 | 3196954U, // V6_vpackwh_sat_alt |
939 | 0 | 3213338U, // V6_vpackwuh_sat_alt |
940 | 0 | 3229722U, // V6_vpopcounth_alt |
941 | 0 | 573671450U, // V6_vrmpybub_rtt_acc_alt |
942 | 0 | 573687834U, // V6_vrmpybub_rtt_alt |
943 | 0 | 20056090U, // V6_vrmpybus_acc_alt |
944 | 0 | 20072474U, // V6_vrmpybus_alt |
945 | 0 | 187828250U, // V6_vrmpybusi_acc_alt |
946 | 0 | 187844634U, // V6_vrmpybusi_alt |
947 | 0 | 20056090U, // V6_vrmpybusv_acc_alt |
948 | 0 | 20072474U, // V6_vrmpybusv_alt |
949 | 0 | 3311642U, // V6_vrmpybv_acc_alt |
950 | 0 | 3328026U, // V6_vrmpybv_alt |
951 | 0 | 20121626U, // V6_vrmpyub_acc_alt |
952 | 0 | 20138010U, // V6_vrmpyub_alt |
953 | 0 | 590579738U, // V6_vrmpyub_rtt_acc_alt |
954 | 0 | 590596122U, // V6_vrmpyub_rtt_alt |
955 | 0 | 187893786U, // V6_vrmpyubi_acc_alt |
956 | 0 | 187910170U, // V6_vrmpyubi_alt |
957 | 0 | 20121626U, // V6_vrmpyubv_acc_alt |
958 | 0 | 20138010U, // V6_vrmpyubv_alt |
959 | 0 | 3409946U, // V6_vrotr_alt |
960 | 0 | 3426330U, // V6_vroundhb_alt |
961 | 0 | 3442714U, // V6_vroundhub_alt |
962 | 0 | 3459098U, // V6_vrounduhub_alt |
963 | 0 | 3475482U, // V6_vrounduwuh_alt |
964 | 0 | 3491866U, // V6_vroundwh_alt |
965 | 0 | 3508250U, // V6_vroundwuh_alt |
966 | 0 | 188074010U, // V6_vrsadubi_acc_alt |
967 | 0 | 188090394U, // V6_vrsadubi_alt |
968 | 0 | 490096666U, // V6_vsathub_alt |
969 | 0 | 3573786U, // V6_vsatuwuh_alt |
970 | 0 | 490129434U, // V6_vsatwh_alt |
971 | 0 | 3606554U, // V6_vsb_alt |
972 | 0 | 3623698U, // V6_vscattermh_add_alt |
973 | 0 | 3623698U, // V6_vscattermh_alt |
974 | 0 | 607619366U, // V6_vscattermhq_alt |
975 | 0 | 3623698U, // V6_vscattermw_add_alt |
976 | 0 | 3623698U, // V6_vscattermw_alt |
977 | 0 | 3623698U, // V6_vscattermwh_add_alt |
978 | 0 | 3623698U, // V6_vscattermwh_alt |
979 | 0 | 624396582U, // V6_vscattermwhq_alt |
980 | 0 | 624396582U, // V6_vscattermwq_alt |
981 | 0 | 3655706U, // V6_vsh_alt |
982 | 0 | 3672090U, // V6_vshufeh_alt |
983 | 0 | 3688474U, // V6_vshuffb_alt |
984 | 0 | 3704858U, // V6_vshuffeb_alt |
985 | 0 | 3721242U, // V6_vshuffh_alt |
986 | 0 | 3737626U, // V6_vshuffob_alt |
987 | 0 | 3754010U, // V6_vshufoeb_alt |
988 | 0 | 3770394U, // V6_vshufoeh_alt |
989 | 0 | 3786778U, // V6_vshufoh_alt |
990 | 0 | 16926746U, // V6_vsubb_alt |
991 | 0 | 16926746U, // V6_vsubb_dv_alt |
992 | 0 | 638996595U, // V6_vsubbnq_alt |
993 | 0 | 638996774U, // V6_vsubbq_alt |
994 | 0 | 419579930U, // V6_vsubbsat_alt |
995 | 0 | 419579930U, // V6_vsubbsat_dv_alt |
996 | 0 | 20580378U, // V6_vsubh_alt |
997 | 0 | 20580378U, // V6_vsubh_dv_alt |
998 | 0 | 655806579U, // V6_vsubhnq_alt |
999 | 0 | 655806758U, // V6_vsubhq_alt |
1000 | 0 | 423233562U, // V6_vsubhsat_alt |
1001 | 0 | 423233562U, // V6_vsubhsat_dv_alt |
1002 | 0 | 20580378U, // V6_vsubhw_alt |
1003 | 0 | 20596762U, // V6_vsububh_alt |
1004 | 0 | 423249946U, // V6_vsububsat_alt |
1005 | 0 | 423249946U, // V6_vsububsat_dv_alt |
1006 | 0 | 423266330U, // V6_vsubuhsat_alt |
1007 | 0 | 423266330U, // V6_vsubuhsat_dv_alt |
1008 | 0 | 20613146U, // V6_vsubuhw_alt |
1009 | 0 | 3852314U, // V6_vsubuwsat_alt |
1010 | 0 | 3852314U, // V6_vsubuwsat_dv_alt |
1011 | 0 | 20645914U, // V6_vsubw_alt |
1012 | 0 | 20645914U, // V6_vsubw_dv_alt |
1013 | 0 | 672714867U, // V6_vsubwnq_alt |
1014 | 0 | 672715046U, // V6_vsubwq_alt |
1015 | 0 | 423299098U, // V6_vsubwsat_alt |
1016 | 0 | 423299098U, // V6_vsubwsat_dv_alt |
1017 | 0 | 3885082U, // V6_vtmpyb_acc_alt |
1018 | 0 | 3901466U, // V6_vtmpyb_alt |
1019 | 0 | 3917850U, // V6_vtmpybus_acc_alt |
1020 | 0 | 3934234U, // V6_vtmpybus_alt |
1021 | 0 | 3950618U, // V6_vtmpyhb_acc_alt |
1022 | 0 | 3967002U, // V6_vtmpyhb_alt |
1023 | 0 | 3623284U, // V6_vtran2x2_map |
1024 | 0 | 3983386U, // V6_vunpackb_alt |
1025 | 0 | 3999770U, // V6_vunpackh_alt |
1026 | 0 | 4016154U, // V6_vunpackob_alt |
1027 | 0 | 4032538U, // V6_vunpackoh_alt |
1028 | 0 | 4048922U, // V6_vunpackub_alt |
1029 | 0 | 4065306U, // V6_vunpackuh_alt |
1030 | 0 | 4081690U, // V6_vzb_alt |
1031 | 0 | 4098074U, // V6_vzh_alt |
1032 | 0 | 297616U, // V6_zld0 |
1033 | 0 | 4114726U, // V6_zldp0 |
1034 | 0 | 4131501U, // Y2_crswap_old |
1035 | 0 | 297547U, // Y2_dcfetch |
1036 | 0 | 1597U, // Y2_k1lock_map |
1037 | 0 | 1621U, // Y2_k1unlock_map |
1038 | 0 | 2074U, // dup_A2_add |
1039 | 0 | 2074U, // dup_A2_addi |
1040 | 0 | 188696602U, // dup_A2_andir |
1041 | 0 | 188712986U, // dup_A2_combineii |
1042 | 0 | 4179994U, // dup_A2_sxtb |
1043 | 0 | 4196378U, // dup_A2_sxth |
1044 | 0 | 50432026U, // dup_A2_tfr |
1045 | 0 | 50448410U, // dup_A2_tfrsi |
1046 | 0 | 165914U, // dup_A2_zxtb |
1047 | 0 | 4212762U, // dup_A2_zxth |
1048 | 0 | 188712986U, // dup_A4_combineii |
1049 | 0 | 490702874U, // dup_A4_combineir |
1050 | 0 | 188778522U, // dup_A4_combineri |
1051 | 0 | 687935603U, // dup_C2_cmoveif |
1052 | 0 | 687935782U, // dup_C2_cmoveit |
1053 | 0 | 687951987U, // dup_C2_cmovenewif |
1054 | 0 | 687952166U, // dup_C2_cmovenewit |
1055 | 0 | 188794906U, // dup_C2_cmpeqi |
1056 | 0 | 4261914U, // dup_L2_deallocframe |
1057 | 0 | 705021978U, // dup_L2_loadrb_io |
1058 | 0 | 705038362U, // dup_L2_loadrd_io |
1059 | 0 | 705054746U, // dup_L2_loadrh_io |
1060 | 0 | 705071130U, // dup_L2_loadri_io |
1061 | 0 | 705087514U, // dup_L2_loadrub_io |
1062 | 0 | 705103898U, // dup_L2_loadruh_io |
1063 | 0 | 71387669U, // dup_S2_allocframe |
1064 | 0 | 725715408U, // dup_S2_storerb_io |
1065 | 0 | 725715464U, // dup_S2_storerd_io |
1066 | 0 | 725715540U, // dup_S2_storerh_io |
1067 | 0 | 725715986U, // dup_S2_storeri_io |
1068 | 0 | 742492624U, // dup_S4_storeirb_io |
1069 | 0 | 742493202U, // dup_S4_storeiri_io |
1070 | 0 | 21088282U, // A2_abs |
1071 | 0 | 21088282U, // A2_absp |
1072 | 0 | 423741466U, // A2_abssat |
1073 | 0 | 2074U, // A2_add |
1074 | 0 | 2074U, // A2_addh_h16_hh |
1075 | 0 | 2074U, // A2_addh_h16_hl |
1076 | 0 | 2074U, // A2_addh_h16_lh |
1077 | 0 | 2074U, // A2_addh_h16_ll |
1078 | 0 | 2074U, // A2_addh_h16_sat_hh |
1079 | 0 | 2074U, // A2_addh_h16_sat_hl |
1080 | 0 | 2074U, // A2_addh_h16_sat_lh |
1081 | 0 | 2074U, // A2_addh_h16_sat_ll |
1082 | 0 | 2074U, // A2_addh_l16_hl |
1083 | 0 | 2074U, // A2_addh_l16_ll |
1084 | 0 | 2074U, // A2_addh_l16_sat_hl |
1085 | 0 | 2074U, // A2_addh_l16_sat_ll |
1086 | 0 | 2074U, // A2_addi |
1087 | 0 | 2074U, // A2_addp |
1088 | 0 | 2074U, // A2_addpsat |
1089 | 0 | 2074U, // A2_addsat |
1090 | 0 | 2074U, // A2_addsph |
1091 | 0 | 2074U, // A2_addspl |
1092 | 0 | 490686490U, // A2_and |
1093 | 0 | 188696602U, // A2_andir |
1094 | 0 | 490686490U, // A2_andp |
1095 | 0 | 4327450U, // A2_aslh |
1096 | 0 | 4343834U, // A2_asrh |
1097 | 0 | 759203866U, // A2_combine_hh |
1098 | 0 | 759203866U, // A2_combine_hl |
1099 | 0 | 775981082U, // A2_combine_lh |
1100 | 0 | 775981082U, // A2_combine_ll |
1101 | 0 | 188712986U, // A2_combineii |
1102 | 0 | 490768410U, // A2_combinew |
1103 | 0 | 4360218U, // A2_max |
1104 | 0 | 4360218U, // A2_maxp |
1105 | 0 | 4376602U, // A2_maxu |
1106 | 0 | 4376602U, // A2_maxup |
1107 | 0 | 4392986U, // A2_min |
1108 | 0 | 4392986U, // A2_minp |
1109 | 0 | 4409370U, // A2_minu |
1110 | 0 | 4409370U, // A2_minup |
1111 | 0 | 16812058U, // A2_negp |
1112 | 0 | 419465242U, // A2_negsat |
1113 | 0 | 1741U, // A2_nop |
1114 | 0 | 51226U, // A2_notp |
1115 | 0 | 490965018U, // A2_or |
1116 | 0 | 188975130U, // A2_orir |
1117 | 0 | 490965018U, // A2_orp |
1118 | 0 | 788598899U, // A2_paddf |
1119 | 0 | 788615283U, // A2_paddfnew |
1120 | 0 | 788598899U, // A2_paddif |
1121 | 0 | 788615283U, // A2_paddifnew |
1122 | 0 | 788599078U, // A2_paddit |
1123 | 0 | 788615462U, // A2_padditnew |
1124 | 0 | 788599078U, // A2_paddt |
1125 | 0 | 788615462U, // A2_paddtnew |
1126 | 0 | 805376115U, // A2_pandf |
1127 | 0 | 805392499U, // A2_pandfnew |
1128 | 0 | 805376294U, // A2_pandt |
1129 | 0 | 805392678U, // A2_pandtnew |
1130 | 0 | 822153331U, // A2_porf |
1131 | 0 | 822169715U, // A2_porfnew |
1132 | 0 | 822153510U, // A2_port |
1133 | 0 | 822169894U, // A2_portnew |
1134 | 0 | 838930547U, // A2_psubf |
1135 | 0 | 838946931U, // A2_psubfnew |
1136 | 0 | 838930726U, // A2_psubt |
1137 | 0 | 838947110U, // A2_psubtnew |
1138 | 0 | 855707763U, // A2_pxorf |
1139 | 0 | 855724147U, // A2_pxorfnew |
1140 | 0 | 855707942U, // A2_pxort |
1141 | 0 | 855724326U, // A2_pxortnew |
1142 | 0 | 423872538U, // A2_roundsat |
1143 | 0 | 4458522U, // A2_sat |
1144 | 0 | 4474906U, // A2_satb |
1145 | 0 | 4491290U, // A2_sath |
1146 | 0 | 4507674U, // A2_satub |
1147 | 0 | 4524058U, // A2_satuh |
1148 | 0 | 4540442U, // A2_sub |
1149 | 0 | 4540442U, // A2_subh_h16_hh |
1150 | 0 | 4540442U, // A2_subh_h16_hl |
1151 | 0 | 4540442U, // A2_subh_h16_lh |
1152 | 0 | 4540442U, // A2_subh_h16_ll |
1153 | 0 | 4540442U, // A2_subh_h16_sat_hh |
1154 | 0 | 4540442U, // A2_subh_h16_sat_hl |
1155 | 0 | 4540442U, // A2_subh_h16_sat_lh |
1156 | 0 | 4540442U, // A2_subh_h16_sat_ll |
1157 | 0 | 4540442U, // A2_subh_l16_hl |
1158 | 0 | 4540442U, // A2_subh_l16_ll |
1159 | 0 | 4540442U, // A2_subh_l16_sat_hl |
1160 | 0 | 4540442U, // A2_subh_l16_sat_ll |
1161 | 0 | 4540442U, // A2_subp |
1162 | 0 | 491096090U, // A2_subri |
1163 | 0 | 4540442U, // A2_subsat |
1164 | 0 | 18253850U, // A2_svaddh |
1165 | 0 | 420907034U, // A2_svaddhs |
1166 | 0 | 420988954U, // A2_svadduhs |
1167 | 0 | 18630682U, // A2_svavgh |
1168 | 0 | 505169946U, // A2_svavghs |
1169 | 0 | 19793946U, // A2_svnavgh |
1170 | 0 | 20580378U, // A2_svsubh |
1171 | 0 | 423233562U, // A2_svsubhs |
1172 | 0 | 423266330U, // A2_svsubuhs |
1173 | 0 | 4573210U, // A2_swiz |
1174 | 0 | 4179994U, // A2_sxtb |
1175 | 0 | 4196378U, // A2_sxth |
1176 | 0 | 4589594U, // A2_sxtw |
1177 | 0 | 50432026U, // A2_tfr |
1178 | 0 | 50432026U, // A2_tfrcrr |
1179 | 0 | 71714842U, // A2_tfrih |
1180 | 0 | 71731226U, // A2_tfril |
1181 | 0 | 50432026U, // A2_tfrrcr |
1182 | 0 | 50448410U, // A2_tfrsi |
1183 | 0 | 18155546U, // A2_vabsh |
1184 | 0 | 420808730U, // A2_vabshsat |
1185 | 0 | 18221082U, // A2_vabsw |
1186 | 0 | 420874266U, // A2_vabswsat |
1187 | 0 | 18253850U, // A2_vaddh |
1188 | 0 | 420907034U, // A2_vaddhs |
1189 | 0 | 18319386U, // A2_vaddub |
1190 | 0 | 420972570U, // A2_vaddubs |
1191 | 0 | 420988954U, // A2_vadduhs |
1192 | 0 | 18384922U, // A2_vaddw |
1193 | 0 | 421038106U, // A2_vaddws |
1194 | 0 | 18630682U, // A2_vavgh |
1195 | 0 | 874268698U, // A2_vavghcr |
1196 | 0 | 505169946U, // A2_vavghr |
1197 | 0 | 18647066U, // A2_vavgub |
1198 | 0 | 505186330U, // A2_vavgubr |
1199 | 0 | 18663450U, // A2_vavguh |
1200 | 0 | 505202714U, // A2_vavguhr |
1201 | 0 | 18679834U, // A2_vavguw |
1202 | 0 | 505219098U, // A2_vavguwr |
1203 | 0 | 18696218U, // A2_vavgw |
1204 | 0 | 874334234U, // A2_vavgwcr |
1205 | 0 | 505235482U, // A2_vavgwr |
1206 | 0 | 491178010U, // A2_vcmpbeq |
1207 | 0 | 491194394U, // A2_vcmpbgtu |
1208 | 0 | 491210778U, // A2_vcmpheq |
1209 | 0 | 491227162U, // A2_vcmphgt |
1210 | 0 | 491243546U, // A2_vcmphgtu |
1211 | 0 | 491259930U, // A2_vcmpweq |
1212 | 0 | 491276314U, // A2_vcmpwgt |
1213 | 0 | 491292698U, // A2_vcmpwgtu |
1214 | 0 | 4769818U, // A2_vconj |
1215 | 0 | 2230298U, // A2_vmaxb |
1216 | 0 | 2246682U, // A2_vmaxh |
1217 | 0 | 2263066U, // A2_vmaxub |
1218 | 0 | 2279450U, // A2_vmaxuh |
1219 | 0 | 4786202U, // A2_vmaxuw |
1220 | 0 | 2295834U, // A2_vmaxw |
1221 | 0 | 2312218U, // A2_vminb |
1222 | 0 | 2328602U, // A2_vminh |
1223 | 0 | 2344986U, // A2_vminub |
1224 | 0 | 2361370U, // A2_vminuh |
1225 | 0 | 4802586U, // A2_vminuw |
1226 | 0 | 2377754U, // A2_vminw |
1227 | 0 | 19793946U, // A2_vnavgh |
1228 | 0 | 892209178U, // A2_vnavghcr |
1229 | 0 | 271452186U, // A2_vnavghr |
1230 | 0 | 19826714U, // A2_vnavgw |
1231 | 0 | 892241946U, // A2_vnavgwcr |
1232 | 0 | 271484954U, // A2_vnavgwr |
1233 | 0 | 4818970U, // A2_vraddub |
1234 | 0 | 4835354U, // A2_vraddub_acc |
1235 | 0 | 20318234U, // A2_vrsadub |
1236 | 0 | 20301850U, // A2_vrsadub_acc |
1237 | 0 | 20580378U, // A2_vsubh |
1238 | 0 | 423233562U, // A2_vsubhs |
1239 | 0 | 20596762U, // A2_vsubub |
1240 | 0 | 423249946U, // A2_vsububs |
1241 | 0 | 423266330U, // A2_vsubuhs |
1242 | 0 | 20645914U, // A2_vsubw |
1243 | 0 | 423299098U, // A2_vsubws |
1244 | 0 | 4851738U, // A2_xor |
1245 | 0 | 4851738U, // A2_xorp |
1246 | 0 | 4212762U, // A2_zxth |
1247 | 0 | 67110938U, // A4_addp_c |
1248 | 0 | 910116890U, // A4_andn |
1249 | 0 | 910116890U, // A4_andnp |
1250 | 0 | 491407386U, // A4_bitsplit |
1251 | 0 | 189417498U, // A4_bitspliti |
1252 | 0 | 922929178U, // A4_boundscheck_hi |
1253 | 0 | 939706394U, // A4_boundscheck_lo |
1254 | 0 | 491423770U, // A4_cmpbeq |
1255 | 0 | 189433882U, // A4_cmpbeqi |
1256 | 0 | 491440154U, // A4_cmpbgt |
1257 | 0 | 189450266U, // A4_cmpbgti |
1258 | 0 | 491456538U, // A4_cmpbgtu |
1259 | 0 | 189466650U, // A4_cmpbgtui |
1260 | 0 | 491472922U, // A4_cmpheq |
1261 | 0 | 189483034U, // A4_cmpheqi |
1262 | 0 | 491489306U, // A4_cmphgt |
1263 | 0 | 189499418U, // A4_cmphgti |
1264 | 0 | 491505690U, // A4_cmphgtu |
1265 | 0 | 189515802U, // A4_cmphgtui |
1266 | 0 | 188712986U, // A4_combineii |
1267 | 0 | 490702874U, // A4_combineir |
1268 | 0 | 188778522U, // A4_combineri |
1269 | 0 | 189532186U, // A4_cround_ri |
1270 | 0 | 491522074U, // A4_cround_rr |
1271 | 0 | 297176U, // A4_ext |
1272 | 0 | 4999194U, // A4_modwrapu |
1273 | 0 | 910395418U, // A4_orn |
1274 | 0 | 910395418U, // A4_ornp |
1275 | 0 | 956371059U, // A4_paslhf |
1276 | 0 | 956387443U, // A4_paslhfnew |
1277 | 0 | 956371238U, // A4_paslht |
1278 | 0 | 956387622U, // A4_paslhtnew |
1279 | 0 | 973148275U, // A4_pasrhf |
1280 | 0 | 973164659U, // A4_pasrhfnew |
1281 | 0 | 973148454U, // A4_pasrht |
1282 | 0 | 973164838U, // A4_pasrhtnew |
1283 | 0 | 989925491U, // A4_psxtbf |
1284 | 0 | 989941875U, // A4_psxtbfnew |
1285 | 0 | 989925670U, // A4_psxtbt |
1286 | 0 | 989942054U, // A4_psxtbtnew |
1287 | 0 | 1006702707U, // A4_psxthf |
1288 | 0 | 1006719091U, // A4_psxthfnew |
1289 | 0 | 1006702886U, // A4_psxtht |
1290 | 0 | 1006719270U, // A4_psxthtnew |
1291 | 0 | 1023479923U, // A4_pzxtbf |
1292 | 0 | 1023496307U, // A4_pzxtbfnew |
1293 | 0 | 1023480102U, // A4_pzxtbt |
1294 | 0 | 1023496486U, // A4_pzxtbtnew |
1295 | 0 | 1040257139U, // A4_pzxthf |
1296 | 0 | 1040273523U, // A4_pzxthfnew |
1297 | 0 | 1040257318U, // A4_pzxtht |
1298 | 0 | 1040273702U, // A4_pzxthtnew |
1299 | 0 | 490784794U, // A4_rcmpeq |
1300 | 0 | 188794906U, // A4_rcmpeqi |
1301 | 0 | 491554842U, // A4_rcmpneq |
1302 | 0 | 189564954U, // A4_rcmpneqi |
1303 | 0 | 188991514U, // A4_round_ri |
1304 | 0 | 188991514U, // A4_round_ri_sat |
1305 | 0 | 490981402U, // A4_round_rr |
1306 | 0 | 490981402U, // A4_round_rr_sat |
1307 | 0 | 71649306U, // A4_subp_c |
1308 | 0 | 50432026U, // A4_tfrcpp |
1309 | 0 | 50432026U, // A4_tfrpcp |
1310 | 0 | 5031962U, // A4_tlbmatch |
1311 | 0 | 5048346U, // A4_vcmpbeq_any |
1312 | 0 | 189188122U, // A4_vcmpbeqi |
1313 | 0 | 491603994U, // A4_vcmpbgt |
1314 | 0 | 189614106U, // A4_vcmpbgti |
1315 | 0 | 189204506U, // A4_vcmpbgtui |
1316 | 0 | 189220890U, // A4_vcmpheqi |
1317 | 0 | 189237274U, // A4_vcmphgti |
1318 | 0 | 189253658U, // A4_vcmphgtui |
1319 | 0 | 189270042U, // A4_vcmpweqi |
1320 | 0 | 189286426U, // A4_vcmpwgti |
1321 | 0 | 189302810U, // A4_vcmpwgtui |
1322 | 0 | 5081114U, // A4_vrmaxh |
1323 | 0 | 5097498U, // A4_vrmaxuh |
1324 | 0 | 5113882U, // A4_vrmaxuw |
1325 | 0 | 5130266U, // A4_vrmaxw |
1326 | 0 | 5146650U, // A4_vrminh |
1327 | 0 | 5163034U, // A4_vrminuh |
1328 | 0 | 5179418U, // A4_vrminuw |
1329 | 0 | 5195802U, // A4_vrminw |
1330 | 0 | 3622938U, // A5_ACS |
1331 | 0 | 5212186U, // A5_vaddhubs |
1332 | 0 | 5228570U, // A6_vcmpbeq_notany |
1333 | 0 | 3622938U, // A6_vminub_RdP |
1334 | 0 | 5244954U, // A7_clip |
1335 | 0 | 189532186U, // A7_croundd_ri |
1336 | 0 | 491522074U, // A7_croundd_rr |
1337 | 0 | 5261338U, // A7_vclip |
1338 | 0 | 5277722U, // C2_all8 |
1339 | 0 | 490686490U, // C2_and |
1340 | 0 | 1061111834U, // C2_andn |
1341 | 0 | 5294106U, // C2_any8 |
1342 | 0 | 491849754U, // C2_bitsclr |
1343 | 0 | 189859866U, // C2_bitsclri |
1344 | 0 | 5326874U, // C2_bitsset |
1345 | 0 | 1073811571U, // C2_ccombinewf |
1346 | 0 | 1073827955U, // C2_ccombinewnewf |
1347 | 0 | 1073828134U, // C2_ccombinewnewt |
1348 | 0 | 1073811750U, // C2_ccombinewt |
1349 | 0 | 687935603U, // C2_cmoveif |
1350 | 0 | 687935782U, // C2_cmoveit |
1351 | 0 | 687951987U, // C2_cmovenewif |
1352 | 0 | 687952166U, // C2_cmovenewit |
1353 | 0 | 490784794U, // C2_cmpeq |
1354 | 0 | 188794906U, // C2_cmpeqi |
1355 | 0 | 490784794U, // C2_cmpeqp |
1356 | 0 | 491882522U, // C2_cmpgt |
1357 | 0 | 189892634U, // C2_cmpgti |
1358 | 0 | 491882522U, // C2_cmpgtp |
1359 | 0 | 491898906U, // C2_cmpgtu |
1360 | 0 | 189909018U, // C2_cmpgtui |
1361 | 0 | 491898906U, // C2_cmpgtup |
1362 | 0 | 5376026U, // C2_mask |
1363 | 0 | 491931674U, // C2_mux |
1364 | 0 | 189941786U, // C2_muxii |
1365 | 0 | 491931674U, // C2_muxir |
1366 | 0 | 189941786U, // C2_muxri |
1367 | 0 | 51226U, // C2_not |
1368 | 0 | 490965018U, // C2_or |
1369 | 0 | 1061390362U, // C2_orn |
1370 | 0 | 50432026U, // C2_tfrpr |
1371 | 0 | 50432026U, // C2_tfrrp |
1372 | 0 | 5408794U, // C2_vitpack |
1373 | 0 | 5425178U, // C2_vmux |
1374 | 0 | 4851738U, // C2_xor |
1375 | 0 | 5441562U, // C4_addipc |
1376 | 0 | 1094666266U, // C4_and_and |
1377 | 0 | 1094666266U, // C4_and_andn |
1378 | 0 | 1111443482U, // C4_and_or |
1379 | 0 | 1111443482U, // C4_and_orn |
1380 | 0 | 491997210U, // C4_cmplte |
1381 | 0 | 190007322U, // C4_cmpltei |
1382 | 0 | 492013594U, // C4_cmplteu |
1383 | 0 | 190023706U, // C4_cmplteui |
1384 | 0 | 491554842U, // C4_cmpneq |
1385 | 0 | 189564954U, // C4_cmpneqi |
1386 | 0 | 5490714U, // C4_fastcorner9 |
1387 | 0 | 5507098U, // C4_fastcorner9_not |
1388 | 0 | 492062746U, // C4_nbitsclr |
1389 | 0 | 190072858U, // C4_nbitsclri |
1390 | 0 | 5539866U, // C4_nbitsset |
1391 | 0 | 1094944794U, // C4_or_and |
1392 | 0 | 1094944794U, // C4_or_andn |
1393 | 0 | 1111722010U, // C4_or_or |
1394 | 0 | 1111722010U, // C4_or_orn |
1395 | 0 | 759897U, // CALLProfile |
1396 | 0 | 5556250U, // CONST32 |
1397 | 0 | 5572634U, // CONST64 |
1398 | 0 | 0U, // DuplexIClass0 |
1399 | 0 | 0U, // DuplexIClass1 |
1400 | 0 | 0U, // DuplexIClass2 |
1401 | 0 | 0U, // DuplexIClass3 |
1402 | 0 | 0U, // DuplexIClass4 |
1403 | 0 | 0U, // DuplexIClass5 |
1404 | 0 | 0U, // DuplexIClass6 |
1405 | 0 | 0U, // DuplexIClass7 |
1406 | 0 | 0U, // DuplexIClass8 |
1407 | 0 | 0U, // DuplexIClass9 |
1408 | 0 | 0U, // DuplexIClassA |
1409 | 0 | 0U, // DuplexIClassB |
1410 | 0 | 0U, // DuplexIClassC |
1411 | 0 | 0U, // DuplexIClassD |
1412 | 0 | 0U, // DuplexIClassE |
1413 | 0 | 0U, // DuplexIClassF |
1414 | 0 | 755820U, // EH_RETURN_JMPR |
1415 | 0 | 5589018U, // F2_conv_d2df |
1416 | 0 | 5605402U, // F2_conv_d2sf |
1417 | 0 | 22399002U, // F2_conv_df2d |
1418 | 0 | 1129695258U, // F2_conv_df2d_chop |
1419 | 0 | 5638170U, // F2_conv_df2sf |
1420 | 0 | 22431770U, // F2_conv_df2ud |
1421 | 0 | 1129728026U, // F2_conv_df2ud_chop |
1422 | 0 | 22448154U, // F2_conv_df2uw |
1423 | 0 | 1129744410U, // F2_conv_df2uw_chop |
1424 | 0 | 22464538U, // F2_conv_df2w |
1425 | 0 | 1129760794U, // F2_conv_df2w_chop |
1426 | 0 | 22480922U, // F2_conv_sf2d |
1427 | 0 | 1129777178U, // F2_conv_sf2d_chop |
1428 | 0 | 5720090U, // F2_conv_sf2df |
1429 | 0 | 22513690U, // F2_conv_sf2ud |
1430 | 0 | 1129809946U, // F2_conv_sf2ud_chop |
1431 | 0 | 22530074U, // F2_conv_sf2uw |
1432 | 0 | 1129826330U, // F2_conv_sf2uw_chop |
1433 | 0 | 22546458U, // F2_conv_sf2w |
1434 | 0 | 1129842714U, // F2_conv_sf2w_chop |
1435 | 0 | 5785626U, // F2_conv_ud2df |
1436 | 0 | 5802010U, // F2_conv_ud2sf |
1437 | 0 | 5818394U, // F2_conv_uw2df |
1438 | 0 | 5834778U, // F2_conv_uw2sf |
1439 | 0 | 5851162U, // F2_conv_w2df |
1440 | 0 | 5867546U, // F2_conv_w2sf |
1441 | 0 | 5883930U, // F2_dfadd |
1442 | 0 | 5900314U, // F2_dfclass |
1443 | 0 | 5916698U, // F2_dfcmpeq |
1444 | 0 | 5933082U, // F2_dfcmpge |
1445 | 0 | 5949466U, // F2_dfcmpgt |
1446 | 0 | 5965850U, // F2_dfcmpuo |
1447 | 0 | 1146832922U, // F2_dfimm_n |
1448 | 0 | 1163610138U, // F2_dfimm_p |
1449 | 0 | 5998618U, // F2_dfmax |
1450 | 0 | 6015002U, // F2_dfmin |
1451 | 0 | 6031386U, // F2_dfmpyfix |
1452 | 0 | 6047770U, // F2_dfmpyhh |
1453 | 0 | 6064154U, // F2_dfmpylh |
1454 | 0 | 6080538U, // F2_dfmpyll |
1455 | 0 | 6096922U, // F2_dfsub |
1456 | 0 | 6113306U, // F2_sfadd |
1457 | 0 | 6129690U, // F2_sfclass |
1458 | 0 | 6146074U, // F2_sfcmpeq |
1459 | 0 | 6162458U, // F2_sfcmpge |
1460 | 0 | 6178842U, // F2_sfcmpgt |
1461 | 0 | 6195226U, // F2_sfcmpuo |
1462 | 0 | 6211610U, // F2_sffixupd |
1463 | 0 | 6227994U, // F2_sffixupn |
1464 | 0 | 6244378U, // F2_sffixupr |
1465 | 0 | 23037978U, // F2_sffma |
1466 | 0 | 1180665882U, // F2_sffma_lib |
1467 | 0 | 492800026U, // F2_sffma_sc |
1468 | 0 | 23054362U, // F2_sffms |
1469 | 0 | 1180682266U, // F2_sffms_lib |
1470 | 0 | 1147144218U, // F2_sfimm_n |
1471 | 0 | 1163921434U, // F2_sfimm_p |
1472 | 0 | 3622938U, // F2_sfinvsqrta |
1473 | 0 | 6309914U, // F2_sfmax |
1474 | 0 | 6326298U, // F2_sfmin |
1475 | 0 | 6342682U, // F2_sfmpy |
1476 | 0 | 3622938U, // F2_sfrecipa |
1477 | 0 | 6359066U, // F2_sfsub |
1478 | 0 | 50432026U, // G4_tfrgcpp |
1479 | 0 | 50432026U, // G4_tfrgcrr |
1480 | 0 | 50432026U, // G4_tfrgpcp |
1481 | 0 | 50432026U, // G4_tfrgrcr |
1482 | 0 | 4605978U, // HI |
1483 | 0 | 759897U, // J2_call |
1484 | 0 | 6375539U, // J2_callf |
1485 | 0 | 755813U, // J2_callr |
1486 | 0 | 6391923U, // J2_callrf |
1487 | 0 | 755785U, // J2_callrh |
1488 | 0 | 6392102U, // J2_callrt |
1489 | 0 | 6375718U, // J2_callt |
1490 | 0 | 759903U, // J2_jump |
1491 | 0 | 6408307U, // J2_jumpf |
1492 | 0 | 6424691U, // J2_jumpfnew |
1493 | 0 | 6441075U, // J2_jumpfnewpt |
1494 | 0 | 6457459U, // J2_jumpfpt |
1495 | 0 | 755820U, // J2_jumpr |
1496 | 0 | 6473843U, // J2_jumprf |
1497 | 0 | 6490227U, // J2_jumprfnew |
1498 | 0 | 6506611U, // J2_jumprfnewpt |
1499 | 0 | 6522995U, // J2_jumprfpt |
1500 | 0 | 6539558U, // J2_jumprgtez |
1501 | 0 | 6555942U, // J2_jumprgtezpt |
1502 | 0 | 755793U, // J2_jumprh |
1503 | 0 | 6572326U, // J2_jumprltez |
1504 | 0 | 6588710U, // J2_jumprltezpt |
1505 | 0 | 6605094U, // J2_jumprnz |
1506 | 0 | 6621478U, // J2_jumprnzpt |
1507 | 0 | 6474022U, // J2_jumprt |
1508 | 0 | 6490406U, // J2_jumprtnew |
1509 | 0 | 6506790U, // J2_jumprtnewpt |
1510 | 0 | 6523174U, // J2_jumprtpt |
1511 | 0 | 6637862U, // J2_jumprz |
1512 | 0 | 6654246U, // J2_jumprzpt |
1513 | 0 | 6408486U, // J2_jumpt |
1514 | 0 | 6424870U, // J2_jumptnew |
1515 | 0 | 6441254U, // J2_jumptnewpt |
1516 | 0 | 6457638U, // J2_jumptpt |
1517 | 0 | 4282682U, // J2_loop0i |
1518 | 0 | 4282682U, // J2_loop0iext |
1519 | 0 | 3627322U, // J2_loop0r |
1520 | 0 | 3627322U, // J2_loop0rext |
1521 | 0 | 4282733U, // J2_loop1i |
1522 | 0 | 4282733U, // J2_loop1iext |
1523 | 0 | 3627373U, // J2_loop1r |
1524 | 0 | 3627373U, // J2_loop1rext |
1525 | 0 | 297161U, // J2_pause |
1526 | 0 | 4282674U, // J2_ploop1si |
1527 | 0 | 3627314U, // J2_ploop1sr |
1528 | 0 | 4282689U, // J2_ploop2si |
1529 | 0 | 3627329U, // J2_ploop2sr |
1530 | 0 | 4282704U, // J2_ploop3si |
1531 | 0 | 3627344U, // J2_ploop3sr |
1532 | 0 | 1586U, // J2_rte |
1533 | 0 | 297106U, // J2_trap0 |
1534 | 0 | 71387494U, // J2_trap1 |
1535 | 0 | 1578U, // J2_unpause |
1536 | 0 | 1197853397U, // J4_cmpeq_f_jumpnv_nt |
1537 | 0 | 1214630613U, // J4_cmpeq_f_jumpnv_t |
1538 | 0 | 3623611U, // J4_cmpeq_fp0_jump_nt |
1539 | 0 | 3623611U, // J4_cmpeq_fp0_jump_t |
1540 | 0 | 3623624U, // J4_cmpeq_fp1_jump_nt |
1541 | 0 | 3623624U, // J4_cmpeq_fp1_jump_t |
1542 | 0 | 1197853410U, // J4_cmpeq_t_jumpnv_nt |
1543 | 0 | 1214630626U, // J4_cmpeq_t_jumpnv_t |
1544 | 0 | 3623611U, // J4_cmpeq_tp0_jump_nt |
1545 | 0 | 3623611U, // J4_cmpeq_tp0_jump_t |
1546 | 0 | 3623624U, // J4_cmpeq_tp1_jump_nt |
1547 | 0 | 3623624U, // J4_cmpeq_tp1_jump_t |
1548 | 0 | 1197869781U, // J4_cmpeqi_f_jumpnv_nt |
1549 | 0 | 1214646997U, // J4_cmpeqi_f_jumpnv_t |
1550 | 0 | 4278971U, // J4_cmpeqi_fp0_jump_nt |
1551 | 0 | 4278971U, // J4_cmpeqi_fp0_jump_t |
1552 | 0 | 4278984U, // J4_cmpeqi_fp1_jump_nt |
1553 | 0 | 4278984U, // J4_cmpeqi_fp1_jump_t |
1554 | 0 | 1197869794U, // J4_cmpeqi_t_jumpnv_nt |
1555 | 0 | 1214647010U, // J4_cmpeqi_t_jumpnv_t |
1556 | 0 | 4278971U, // J4_cmpeqi_tp0_jump_nt |
1557 | 0 | 4278971U, // J4_cmpeqi_tp0_jump_t |
1558 | 0 | 4278984U, // J4_cmpeqi_tp1_jump_nt |
1559 | 0 | 4278984U, // J4_cmpeqi_tp1_jump_t |
1560 | 0 | 1197869781U, // J4_cmpeqn1_f_jumpnv_nt |
1561 | 0 | 1214646997U, // J4_cmpeqn1_f_jumpnv_t |
1562 | 0 | 4278971U, // J4_cmpeqn1_fp0_jump_nt |
1563 | 0 | 4278971U, // J4_cmpeqn1_fp0_jump_t |
1564 | 0 | 4278984U, // J4_cmpeqn1_fp1_jump_nt |
1565 | 0 | 4278984U, // J4_cmpeqn1_fp1_jump_t |
1566 | 0 | 1197869794U, // J4_cmpeqn1_t_jumpnv_nt |
1567 | 0 | 1214647010U, // J4_cmpeqn1_t_jumpnv_t |
1568 | 0 | 4278971U, // J4_cmpeqn1_tp0_jump_nt |
1569 | 0 | 4278971U, // J4_cmpeqn1_tp0_jump_t |
1570 | 0 | 4278984U, // J4_cmpeqn1_tp1_jump_nt |
1571 | 0 | 4278984U, // J4_cmpeqn1_tp1_jump_t |
1572 | 0 | 1197853502U, // J4_cmpgt_f_jumpnv_nt |
1573 | 0 | 1214630718U, // J4_cmpgt_f_jumpnv_t |
1574 | 0 | 3623716U, // J4_cmpgt_fp0_jump_nt |
1575 | 0 | 3623716U, // J4_cmpgt_fp0_jump_t |
1576 | 0 | 3623729U, // J4_cmpgt_fp1_jump_nt |
1577 | 0 | 3623729U, // J4_cmpgt_fp1_jump_t |
1578 | 0 | 1197853515U, // J4_cmpgt_t_jumpnv_nt |
1579 | 0 | 1214630731U, // J4_cmpgt_t_jumpnv_t |
1580 | 0 | 3623716U, // J4_cmpgt_tp0_jump_nt |
1581 | 0 | 3623716U, // J4_cmpgt_tp0_jump_t |
1582 | 0 | 3623729U, // J4_cmpgt_tp1_jump_nt |
1583 | 0 | 3623729U, // J4_cmpgt_tp1_jump_t |
1584 | 0 | 1197869886U, // J4_cmpgti_f_jumpnv_nt |
1585 | 0 | 1214647102U, // J4_cmpgti_f_jumpnv_t |
1586 | 0 | 4279076U, // J4_cmpgti_fp0_jump_nt |
1587 | 0 | 4279076U, // J4_cmpgti_fp0_jump_t |
1588 | 0 | 4279089U, // J4_cmpgti_fp1_jump_nt |
1589 | 0 | 4279089U, // J4_cmpgti_fp1_jump_t |
1590 | 0 | 1197869899U, // J4_cmpgti_t_jumpnv_nt |
1591 | 0 | 1214647115U, // J4_cmpgti_t_jumpnv_t |
1592 | 0 | 4279076U, // J4_cmpgti_tp0_jump_nt |
1593 | 0 | 4279076U, // J4_cmpgti_tp0_jump_t |
1594 | 0 | 4279089U, // J4_cmpgti_tp1_jump_nt |
1595 | 0 | 4279089U, // J4_cmpgti_tp1_jump_t |
1596 | 0 | 1197869886U, // J4_cmpgtn1_f_jumpnv_nt |
1597 | 0 | 1214647102U, // J4_cmpgtn1_f_jumpnv_t |
1598 | 0 | 4279076U, // J4_cmpgtn1_fp0_jump_nt |
1599 | 0 | 4279076U, // J4_cmpgtn1_fp0_jump_t |
1600 | 0 | 4279089U, // J4_cmpgtn1_fp1_jump_nt |
1601 | 0 | 4279089U, // J4_cmpgtn1_fp1_jump_t |
1602 | 0 | 1197869899U, // J4_cmpgtn1_t_jumpnv_nt |
1603 | 0 | 1214647115U, // J4_cmpgtn1_t_jumpnv_t |
1604 | 0 | 4279076U, // J4_cmpgtn1_tp0_jump_nt |
1605 | 0 | 4279076U, // J4_cmpgtn1_tp0_jump_t |
1606 | 0 | 4279089U, // J4_cmpgtn1_tp1_jump_nt |
1607 | 0 | 4279089U, // J4_cmpgtn1_tp1_jump_t |
1608 | 0 | 1197853635U, // J4_cmpgtu_f_jumpnv_nt |
1609 | 0 | 1214630851U, // J4_cmpgtu_f_jumpnv_t |
1610 | 0 | 3623847U, // J4_cmpgtu_fp0_jump_nt |
1611 | 0 | 3623847U, // J4_cmpgtu_fp0_jump_t |
1612 | 0 | 3623861U, // J4_cmpgtu_fp1_jump_nt |
1613 | 0 | 3623861U, // J4_cmpgtu_fp1_jump_t |
1614 | 0 | 1197853649U, // J4_cmpgtu_t_jumpnv_nt |
1615 | 0 | 1214630865U, // J4_cmpgtu_t_jumpnv_t |
1616 | 0 | 3623847U, // J4_cmpgtu_tp0_jump_nt |
1617 | 0 | 3623847U, // J4_cmpgtu_tp0_jump_t |
1618 | 0 | 3623861U, // J4_cmpgtu_tp1_jump_nt |
1619 | 0 | 3623861U, // J4_cmpgtu_tp1_jump_t |
1620 | 0 | 1197870019U, // J4_cmpgtui_f_jumpnv_nt |
1621 | 0 | 1214647235U, // J4_cmpgtui_f_jumpnv_t |
1622 | 0 | 4279207U, // J4_cmpgtui_fp0_jump_nt |
1623 | 0 | 4279207U, // J4_cmpgtui_fp0_jump_t |
1624 | 0 | 4279221U, // J4_cmpgtui_fp1_jump_nt |
1625 | 0 | 4279221U, // J4_cmpgtui_fp1_jump_t |
1626 | 0 | 1197870033U, // J4_cmpgtui_t_jumpnv_nt |
1627 | 0 | 1214647249U, // J4_cmpgtui_t_jumpnv_t |
1628 | 0 | 4279207U, // J4_cmpgtui_tp0_jump_nt |
1629 | 0 | 4279207U, // J4_cmpgtui_tp0_jump_t |
1630 | 0 | 4279221U, // J4_cmpgtui_tp1_jump_nt |
1631 | 0 | 4279221U, // J4_cmpgtui_tp1_jump_t |
1632 | 0 | 3623742U, // J4_cmplt_f_jumpnv_nt |
1633 | 0 | 3623742U, // J4_cmplt_f_jumpnv_t |
1634 | 0 | 3623755U, // J4_cmplt_t_jumpnv_nt |
1635 | 0 | 3623755U, // J4_cmplt_t_jumpnv_t |
1636 | 0 | 3623875U, // J4_cmpltu_f_jumpnv_nt |
1637 | 0 | 3623875U, // J4_cmpltu_f_jumpnv_t |
1638 | 0 | 3623889U, // J4_cmpltu_t_jumpnv_nt |
1639 | 0 | 3623889U, // J4_cmpltu_t_jumpnv_t |
1640 | 0 | 297756U, // J4_hintjumpr |
1641 | 0 | 1224853530U, // J4_jumpseti |
1642 | 0 | 1224837146U, // J4_jumpsetr |
1643 | 0 | 6703991U, // J4_tstbit0_f_jumpnv_nt |
1644 | 0 | 6720375U, // J4_tstbit0_f_jumpnv_t |
1645 | 0 | 6736733U, // J4_tstbit0_fp0_jump_nt |
1646 | 0 | 6753117U, // J4_tstbit0_fp0_jump_t |
1647 | 0 | 6769514U, // J4_tstbit0_fp1_jump_nt |
1648 | 0 | 6785898U, // J4_tstbit0_fp1_jump_t |
1649 | 0 | 6704004U, // J4_tstbit0_t_jumpnv_nt |
1650 | 0 | 6720388U, // J4_tstbit0_t_jumpnv_t |
1651 | 0 | 6802269U, // J4_tstbit0_tp0_jump_nt |
1652 | 0 | 6818653U, // J4_tstbit0_tp0_jump_t |
1653 | 0 | 6835050U, // J4_tstbit0_tp1_jump_nt |
1654 | 0 | 6851434U, // J4_tstbit0_tp1_jump_t |
1655 | 0 | 4261914U, // L2_deallocframe |
1656 | 0 | 67422234U, // L2_loadalignb_io |
1657 | 0 | 313370U, // L2_loadalignb_pbr |
1658 | 0 | 313370U, // L2_loadalignb_pci |
1659 | 0 | 313370U, // L2_loadalignb_pcr |
1660 | 0 | 313370U, // L2_loadalignb_pi |
1661 | 0 | 313370U, // L2_loadalignb_pr |
1662 | 0 | 67438618U, // L2_loadalignh_io |
1663 | 0 | 329754U, // L2_loadalignh_pbr |
1664 | 0 | 329754U, // L2_loadalignh_pci |
1665 | 0 | 329754U, // L2_loadalignh_pcr |
1666 | 0 | 329754U, // L2_loadalignh_pi |
1667 | 0 | 329754U, // L2_loadalignh_pr |
1668 | 0 | 704989210U, // L2_loadbsw2_io |
1669 | 0 | 1241860122U, // L2_loadbsw2_pbr |
1670 | 0 | 1258637338U, // L2_loadbsw2_pci |
1671 | 0 | 1275414554U, // L2_loadbsw2_pcr |
1672 | 0 | 1258637338U, // L2_loadbsw2_pi |
1673 | 0 | 1241860122U, // L2_loadbsw2_pr |
1674 | 0 | 704989210U, // L2_loadbsw4_io |
1675 | 0 | 1241860122U, // L2_loadbsw4_pbr |
1676 | 0 | 1258637338U, // L2_loadbsw4_pci |
1677 | 0 | 1275414554U, // L2_loadbsw4_pcr |
1678 | 0 | 1258637338U, // L2_loadbsw4_pi |
1679 | 0 | 1241860122U, // L2_loadbsw4_pr |
1680 | 0 | 705005594U, // L2_loadbzw2_io |
1681 | 0 | 1241876506U, // L2_loadbzw2_pbr |
1682 | 0 | 1258653722U, // L2_loadbzw2_pci |
1683 | 0 | 1275430938U, // L2_loadbzw2_pcr |
1684 | 0 | 1258653722U, // L2_loadbzw2_pi |
1685 | 0 | 1241876506U, // L2_loadbzw2_pr |
1686 | 0 | 705005594U, // L2_loadbzw4_io |
1687 | 0 | 1241876506U, // L2_loadbzw4_pbr |
1688 | 0 | 1258653722U, // L2_loadbzw4_pci |
1689 | 0 | 1275430938U, // L2_loadbzw4_pcr |
1690 | 0 | 1258653722U, // L2_loadbzw4_pi |
1691 | 0 | 1241876506U, // L2_loadbzw4_pr |
1692 | 0 | 705021978U, // L2_loadrb_io |
1693 | 0 | 1241892890U, // L2_loadrb_pbr |
1694 | 0 | 1258670106U, // L2_loadrb_pci |
1695 | 0 | 1275447322U, // L2_loadrb_pcr |
1696 | 0 | 1258670106U, // L2_loadrb_pi |
1697 | 0 | 1241892890U, // L2_loadrb_pr |
1698 | 0 | 6866970U, // L2_loadrbgp |
1699 | 0 | 705038362U, // L2_loadrd_io |
1700 | 0 | 1241909274U, // L2_loadrd_pbr |
1701 | 0 | 1258686490U, // L2_loadrd_pci |
1702 | 0 | 1275463706U, // L2_loadrd_pcr |
1703 | 0 | 1258686490U, // L2_loadrd_pi |
1704 | 0 | 1241909274U, // L2_loadrd_pr |
1705 | 0 | 6883354U, // L2_loadrdgp |
1706 | 0 | 705054746U, // L2_loadrh_io |
1707 | 0 | 1241925658U, // L2_loadrh_pbr |
1708 | 0 | 1258702874U, // L2_loadrh_pci |
1709 | 0 | 1275480090U, // L2_loadrh_pcr |
1710 | 0 | 1258702874U, // L2_loadrh_pi |
1711 | 0 | 1241925658U, // L2_loadrh_pr |
1712 | 0 | 6899738U, // L2_loadrhgp |
1713 | 0 | 705071130U, // L2_loadri_io |
1714 | 0 | 1241942042U, // L2_loadri_pbr |
1715 | 0 | 1258719258U, // L2_loadri_pci |
1716 | 0 | 1275496474U, // L2_loadri_pcr |
1717 | 0 | 1258719258U, // L2_loadri_pi |
1718 | 0 | 1241942042U, // L2_loadri_pr |
1719 | 0 | 6916122U, // L2_loadrigp |
1720 | 0 | 705087514U, // L2_loadrub_io |
1721 | 0 | 1241958426U, // L2_loadrub_pbr |
1722 | 0 | 1258735642U, // L2_loadrub_pci |
1723 | 0 | 1275512858U, // L2_loadrub_pcr |
1724 | 0 | 1258735642U, // L2_loadrub_pi |
1725 | 0 | 1241958426U, // L2_loadrub_pr |
1726 | 0 | 6932506U, // L2_loadrubgp |
1727 | 0 | 705103898U, // L2_loadruh_io |
1728 | 0 | 1241974810U, // L2_loadruh_pbr |
1729 | 0 | 1258752026U, // L2_loadruh_pci |
1730 | 0 | 1275529242U, // L2_loadruh_pcr |
1731 | 0 | 1258752026U, // L2_loadruh_pi |
1732 | 0 | 1241974810U, // L2_loadruh_pr |
1733 | 0 | 6948890U, // L2_loadruhgp |
1734 | 0 | 6965274U, // L2_loadw_aq |
1735 | 0 | 6981658U, // L2_loadw_locked |
1736 | 0 | 83955827U, // L2_ploadrbf_io |
1737 | 0 | 83959923U, // L2_ploadrbf_pi |
1738 | 0 | 83972211U, // L2_ploadrbfnew_io |
1739 | 0 | 83976307U, // L2_ploadrbfnew_pi |
1740 | 0 | 83956006U, // L2_ploadrbt_io |
1741 | 0 | 83960102U, // L2_ploadrbt_pi |
1742 | 0 | 83972390U, // L2_ploadrbtnew_io |
1743 | 0 | 83976486U, // L2_ploadrbtnew_pi |
1744 | 0 | 100733043U, // L2_ploadrdf_io |
1745 | 0 | 100737139U, // L2_ploadrdf_pi |
1746 | 0 | 100749427U, // L2_ploadrdfnew_io |
1747 | 0 | 100753523U, // L2_ploadrdfnew_pi |
1748 | 0 | 100733222U, // L2_ploadrdt_io |
1749 | 0 | 100737318U, // L2_ploadrdt_pi |
1750 | 0 | 100749606U, // L2_ploadrdtnew_io |
1751 | 0 | 100753702U, // L2_ploadrdtnew_pi |
1752 | 0 | 117510259U, // L2_ploadrhf_io |
1753 | 0 | 117514355U, // L2_ploadrhf_pi |
1754 | 0 | 117526643U, // L2_ploadrhfnew_io |
1755 | 0 | 117530739U, // L2_ploadrhfnew_pi |
1756 | 0 | 117510438U, // L2_ploadrht_io |
1757 | 0 | 117514534U, // L2_ploadrht_pi |
1758 | 0 | 117526822U, // L2_ploadrhtnew_io |
1759 | 0 | 117530918U, // L2_ploadrhtnew_pi |
1760 | 0 | 134287475U, // L2_ploadrif_io |
1761 | 0 | 134291571U, // L2_ploadrif_pi |
1762 | 0 | 134303859U, // L2_ploadrifnew_io |
1763 | 0 | 134307955U, // L2_ploadrifnew_pi |
1764 | 0 | 134287654U, // L2_ploadrit_io |
1765 | 0 | 134291750U, // L2_ploadrit_pi |
1766 | 0 | 134304038U, // L2_ploadritnew_io |
1767 | 0 | 134308134U, // L2_ploadritnew_pi |
1768 | 0 | 151064691U, // L2_ploadrubf_io |
1769 | 0 | 151068787U, // L2_ploadrubf_pi |
1770 | 0 | 151081075U, // L2_ploadrubfnew_io |
1771 | 0 | 151085171U, // L2_ploadrubfnew_pi |
1772 | 0 | 151064870U, // L2_ploadrubt_io |
1773 | 0 | 151068966U, // L2_ploadrubt_pi |
1774 | 0 | 151081254U, // L2_ploadrubtnew_io |
1775 | 0 | 151085350U, // L2_ploadrubtnew_pi |
1776 | 0 | 167841907U, // L2_ploadruhf_io |
1777 | 0 | 167846003U, // L2_ploadruhf_pi |
1778 | 0 | 167858291U, // L2_ploadruhfnew_io |
1779 | 0 | 167862387U, // L2_ploadruhfnew_pi |
1780 | 0 | 167842086U, // L2_ploadruht_io |
1781 | 0 | 167846182U, // L2_ploadruht_pi |
1782 | 0 | 167858470U, // L2_ploadruhtnew_io |
1783 | 0 | 167862566U, // L2_ploadruhtnew_pi |
1784 | 0 | 1296140752U, // L4_add_memopb_io |
1785 | 0 | 1296140884U, // L4_add_memoph_io |
1786 | 0 | 1296141330U, // L4_add_memopw_io |
1787 | 0 | 1312917968U, // L4_and_memopb_io |
1788 | 0 | 1312918100U, // L4_and_memoph_io |
1789 | 0 | 1312918546U, // L4_and_memopw_io |
1790 | 0 | 1329695184U, // L4_iadd_memopb_io |
1791 | 0 | 1329695316U, // L4_iadd_memoph_io |
1792 | 0 | 1329695762U, // L4_iadd_memopw_io |
1793 | 0 | 1346472400U, // L4_iand_memopb_io |
1794 | 0 | 1346472532U, // L4_iand_memoph_io |
1795 | 0 | 1346472978U, // L4_iand_memopw_io |
1796 | 0 | 1363249616U, // L4_ior_memopb_io |
1797 | 0 | 1363249748U, // L4_ior_memoph_io |
1798 | 0 | 1363250194U, // L4_ior_memopw_io |
1799 | 0 | 1380026832U, // L4_isub_memopb_io |
1800 | 0 | 1380026964U, // L4_isub_memoph_io |
1801 | 0 | 1380027410U, // L4_isub_memopw_io |
1802 | 0 | 313370U, // L4_loadalignb_ap |
1803 | 0 | 67422234U, // L4_loadalignb_ur |
1804 | 0 | 329754U, // L4_loadalignh_ap |
1805 | 0 | 67438618U, // L4_loadalignh_ur |
1806 | 0 | 1392855066U, // L4_loadbsw2_ap |
1807 | 0 | 1409632282U, // L4_loadbsw2_ur |
1808 | 0 | 1392855066U, // L4_loadbsw4_ap |
1809 | 0 | 1409632282U, // L4_loadbsw4_ur |
1810 | 0 | 1392871450U, // L4_loadbzw2_ap |
1811 | 0 | 1409648666U, // L4_loadbzw2_ur |
1812 | 0 | 1392871450U, // L4_loadbzw4_ap |
1813 | 0 | 1409648666U, // L4_loadbzw4_ur |
1814 | 0 | 6998042U, // L4_loadd_aq |
1815 | 0 | 7014426U, // L4_loadd_locked |
1816 | 0 | 1392887834U, // L4_loadrb_ap |
1817 | 0 | 1426442266U, // L4_loadrb_rr |
1818 | 0 | 1409665050U, // L4_loadrb_ur |
1819 | 0 | 1392904218U, // L4_loadrd_ap |
1820 | 0 | 1426458650U, // L4_loadrd_rr |
1821 | 0 | 1409681434U, // L4_loadrd_ur |
1822 | 0 | 1392920602U, // L4_loadrh_ap |
1823 | 0 | 1426475034U, // L4_loadrh_rr |
1824 | 0 | 1409697818U, // L4_loadrh_ur |
1825 | 0 | 1392936986U, // L4_loadri_ap |
1826 | 0 | 1426491418U, // L4_loadri_rr |
1827 | 0 | 1409714202U, // L4_loadri_ur |
1828 | 0 | 1392953370U, // L4_loadrub_ap |
1829 | 0 | 1426507802U, // L4_loadrub_rr |
1830 | 0 | 1409730586U, // L4_loadrub_ur |
1831 | 0 | 1392969754U, // L4_loadruh_ap |
1832 | 0 | 1426524186U, // L4_loadruh_rr |
1833 | 0 | 1409746970U, // L4_loadruh_ur |
1834 | 0 | 7030810U, // L4_loadw_phys |
1835 | 0 | 1447135696U, // L4_or_memopb_io |
1836 | 0 | 1447135828U, // L4_or_memoph_io |
1837 | 0 | 1447136274U, // L4_or_memopw_io |
1838 | 0 | 1459687539U, // L4_ploadrbf_abs |
1839 | 0 | 83955827U, // L4_ploadrbf_rr |
1840 | 0 | 1459703923U, // L4_ploadrbfnew_abs |
1841 | 0 | 83972211U, // L4_ploadrbfnew_rr |
1842 | 0 | 1459687718U, // L4_ploadrbt_abs |
1843 | 0 | 83956006U, // L4_ploadrbt_rr |
1844 | 0 | 1459704102U, // L4_ploadrbtnew_abs |
1845 | 0 | 83972390U, // L4_ploadrbtnew_rr |
1846 | 0 | 1476464755U, // L4_ploadrdf_abs |
1847 | 0 | 100733043U, // L4_ploadrdf_rr |
1848 | 0 | 1476481139U, // L4_ploadrdfnew_abs |
1849 | 0 | 100749427U, // L4_ploadrdfnew_rr |
1850 | 0 | 1476464934U, // L4_ploadrdt_abs |
1851 | 0 | 100733222U, // L4_ploadrdt_rr |
1852 | 0 | 1476481318U, // L4_ploadrdtnew_abs |
1853 | 0 | 100749606U, // L4_ploadrdtnew_rr |
1854 | 0 | 1493241971U, // L4_ploadrhf_abs |
1855 | 0 | 117510259U, // L4_ploadrhf_rr |
1856 | 0 | 1493258355U, // L4_ploadrhfnew_abs |
1857 | 0 | 117526643U, // L4_ploadrhfnew_rr |
1858 | 0 | 1493242150U, // L4_ploadrht_abs |
1859 | 0 | 117510438U, // L4_ploadrht_rr |
1860 | 0 | 1493258534U, // L4_ploadrhtnew_abs |
1861 | 0 | 117526822U, // L4_ploadrhtnew_rr |
1862 | 0 | 1510019187U, // L4_ploadrif_abs |
1863 | 0 | 134287475U, // L4_ploadrif_rr |
1864 | 0 | 1510035571U, // L4_ploadrifnew_abs |
1865 | 0 | 134303859U, // L4_ploadrifnew_rr |
1866 | 0 | 1510019366U, // L4_ploadrit_abs |
1867 | 0 | 134287654U, // L4_ploadrit_rr |
1868 | 0 | 1510035750U, // L4_ploadritnew_abs |
1869 | 0 | 134304038U, // L4_ploadritnew_rr |
1870 | 0 | 1526796403U, // L4_ploadrubf_abs |
1871 | 0 | 151064691U, // L4_ploadrubf_rr |
1872 | 0 | 1526812787U, // L4_ploadrubfnew_abs |
1873 | 0 | 151081075U, // L4_ploadrubfnew_rr |
1874 | 0 | 1526796582U, // L4_ploadrubt_abs |
1875 | 0 | 151064870U, // L4_ploadrubt_rr |
1876 | 0 | 1526812966U, // L4_ploadrubtnew_abs |
1877 | 0 | 151081254U, // L4_ploadrubtnew_rr |
1878 | 0 | 1543573619U, // L4_ploadruhf_abs |
1879 | 0 | 167841907U, // L4_ploadruhf_rr |
1880 | 0 | 1543590003U, // L4_ploadruhfnew_abs |
1881 | 0 | 167858291U, // L4_ploadruhfnew_rr |
1882 | 0 | 1543573798U, // L4_ploadruht_abs |
1883 | 0 | 167842086U, // L4_ploadruht_rr |
1884 | 0 | 1543590182U, // L4_ploadruhtnew_abs |
1885 | 0 | 167858470U, // L4_ploadruhtnew_rr |
1886 | 0 | 7047194U, // L4_return |
1887 | 0 | 1560350835U, // L4_return_f |
1888 | 0 | 1560367219U, // L4_return_fnew_pnt |
1889 | 0 | 1560367219U, // L4_return_fnew_pt |
1890 | 0 | 1560351014U, // L4_return_t |
1891 | 0 | 1560367398U, // L4_return_tnew_pnt |
1892 | 0 | 1560367398U, // L4_return_tnew_pt |
1893 | 0 | 1581353424U, // L4_sub_memopb_io |
1894 | 0 | 1581353556U, // L4_sub_memoph_io |
1895 | 0 | 1581354002U, // L4_sub_memopw_io |
1896 | 0 | 3624054U, // L6_memcpy |
1897 | 0 | 4622362U, // LO |
1898 | 0 | 493602842U, // M2_acci |
1899 | 0 | 191612954U, // M2_accii |
1900 | 0 | 7079962U, // M2_cmaci_s0 |
1901 | 0 | 7096346U, // M2_cmacr_s0 |
1902 | 0 | 426543130U, // M2_cmacs_s0 |
1903 | 0 | 208439322U, // M2_cmacs_s1 |
1904 | 0 | 1600948250U, // M2_cmacsc_s0 |
1905 | 0 | 1617725466U, // M2_cmacsc_s1 |
1906 | 0 | 7129114U, // M2_cmpyi_s0 |
1907 | 0 | 7145498U, // M2_cmpyr_s0 |
1908 | 0 | 275597338U, // M2_cmpyrs_s0 |
1909 | 0 | 225265690U, // M2_cmpyrs_s1 |
1910 | 0 | 1634551834U, // M2_cmpyrsc_s0 |
1911 | 0 | 1651329050U, // M2_cmpyrsc_s1 |
1912 | 0 | 426592282U, // M2_cmpys_s0 |
1913 | 0 | 208488474U, // M2_cmpys_s1 |
1914 | 0 | 1600997402U, // M2_cmpysc_s0 |
1915 | 0 | 1617774618U, // M2_cmpysc_s1 |
1916 | 0 | 426608666U, // M2_cnacs_s0 |
1917 | 0 | 208504858U, // M2_cnacs_s1 |
1918 | 0 | 1601013786U, // M2_cnacsc_s0 |
1919 | 0 | 1617791002U, // M2_cnacsc_s1 |
1920 | 0 | 493733914U, // M2_dpmpyss_acc_s0 |
1921 | 0 | 493750298U, // M2_dpmpyss_nac_s0 |
1922 | 0 | 493766682U, // M2_dpmpyss_rnd_s0 |
1923 | 0 | 493766682U, // M2_dpmpyss_s0 |
1924 | 0 | 493783066U, // M2_dpmpyuu_acc_s0 |
1925 | 0 | 493799450U, // M2_dpmpyuu_nac_s0 |
1926 | 0 | 493815834U, // M2_dpmpyuu_s0 |
1927 | 0 | 493766682U, // M2_hmmpyh_rs1 |
1928 | 0 | 493766682U, // M2_hmmpyh_s1 |
1929 | 0 | 493766682U, // M2_hmmpyl_rs1 |
1930 | 0 | 493766682U, // M2_hmmpyl_s1 |
1931 | 0 | 493832218U, // M2_maci |
1932 | 0 | 191858714U, // M2_macsin |
1933 | 0 | 191842330U, // M2_macsip |
1934 | 0 | 275761178U, // M2_mmachs_rs0 |
1935 | 0 | 225429530U, // M2_mmachs_rs1 |
1936 | 0 | 426756122U, // M2_mmachs_s0 |
1937 | 0 | 208652314U, // M2_mmachs_s1 |
1938 | 0 | 275777562U, // M2_mmacls_rs0 |
1939 | 0 | 225445914U, // M2_mmacls_rs1 |
1940 | 0 | 426772506U, // M2_mmacls_s0 |
1941 | 0 | 208668698U, // M2_mmacls_s1 |
1942 | 0 | 275793946U, // M2_mmacuhs_rs0 |
1943 | 0 | 225462298U, // M2_mmacuhs_rs1 |
1944 | 0 | 426788890U, // M2_mmacuhs_s0 |
1945 | 0 | 208685082U, // M2_mmacuhs_s1 |
1946 | 0 | 275810330U, // M2_mmaculs_rs0 |
1947 | 0 | 225478682U, // M2_mmaculs_rs1 |
1948 | 0 | 426805274U, // M2_mmaculs_s0 |
1949 | 0 | 208701466U, // M2_mmaculs_s1 |
1950 | 0 | 275826714U, // M2_mmpyh_rs0 |
1951 | 0 | 225495066U, // M2_mmpyh_rs1 |
1952 | 0 | 426821658U, // M2_mmpyh_s0 |
1953 | 0 | 208717850U, // M2_mmpyh_s1 |
1954 | 0 | 275843098U, // M2_mmpyl_rs0 |
1955 | 0 | 225511450U, // M2_mmpyl_rs1 |
1956 | 0 | 426838042U, // M2_mmpyl_s0 |
1957 | 0 | 208734234U, // M2_mmpyl_s1 |
1958 | 0 | 275859482U, // M2_mmpyuh_rs0 |
1959 | 0 | 225527834U, // M2_mmpyuh_rs1 |
1960 | 0 | 426854426U, // M2_mmpyuh_s0 |
1961 | 0 | 208750618U, // M2_mmpyuh_s1 |
1962 | 0 | 275875866U, // M2_mmpyul_rs0 |
1963 | 0 | 225544218U, // M2_mmpyul_rs1 |
1964 | 0 | 426870810U, // M2_mmpyul_s0 |
1965 | 0 | 208767002U, // M2_mmpyul_s1 |
1966 | 0 | 493848602U, // M2_mnaci |
1967 | 0 | 762169370U, // M2_mpy_acc_hh_s0 |
1968 | 0 | 762169370U, // M2_mpy_acc_hh_s1 |
1969 | 0 | 762169370U, // M2_mpy_acc_hl_s0 |
1970 | 0 | 762169370U, // M2_mpy_acc_hl_s1 |
1971 | 0 | 778946586U, // M2_mpy_acc_lh_s0 |
1972 | 0 | 778946586U, // M2_mpy_acc_lh_s1 |
1973 | 0 | 778946586U, // M2_mpy_acc_ll_s0 |
1974 | 0 | 778946586U, // M2_mpy_acc_ll_s1 |
1975 | 0 | 762169370U, // M2_mpy_acc_sat_hh_s0 |
1976 | 0 | 762169370U, // M2_mpy_acc_sat_hh_s1 |
1977 | 0 | 762169370U, // M2_mpy_acc_sat_hl_s0 |
1978 | 0 | 762169370U, // M2_mpy_acc_sat_hl_s1 |
1979 | 0 | 778946586U, // M2_mpy_acc_sat_lh_s0 |
1980 | 0 | 778946586U, // M2_mpy_acc_sat_lh_s1 |
1981 | 0 | 778946586U, // M2_mpy_acc_sat_ll_s0 |
1982 | 0 | 778946586U, // M2_mpy_acc_sat_ll_s1 |
1983 | 0 | 762202138U, // M2_mpy_hh_s0 |
1984 | 0 | 762202138U, // M2_mpy_hh_s1 |
1985 | 0 | 762202138U, // M2_mpy_hl_s0 |
1986 | 0 | 762202138U, // M2_mpy_hl_s1 |
1987 | 0 | 778979354U, // M2_mpy_lh_s0 |
1988 | 0 | 778979354U, // M2_mpy_lh_s1 |
1989 | 0 | 778979354U, // M2_mpy_ll_s0 |
1990 | 0 | 778979354U, // M2_mpy_ll_s1 |
1991 | 0 | 762185754U, // M2_mpy_nac_hh_s0 |
1992 | 0 | 762185754U, // M2_mpy_nac_hh_s1 |
1993 | 0 | 762185754U, // M2_mpy_nac_hl_s0 |
1994 | 0 | 762185754U, // M2_mpy_nac_hl_s1 |
1995 | 0 | 778962970U, // M2_mpy_nac_lh_s0 |
1996 | 0 | 778962970U, // M2_mpy_nac_lh_s1 |
1997 | 0 | 778962970U, // M2_mpy_nac_ll_s0 |
1998 | 0 | 778962970U, // M2_mpy_nac_ll_s1 |
1999 | 0 | 762185754U, // M2_mpy_nac_sat_hh_s0 |
2000 | 0 | 762185754U, // M2_mpy_nac_sat_hh_s1 |
2001 | 0 | 762185754U, // M2_mpy_nac_sat_hl_s0 |
2002 | 0 | 762185754U, // M2_mpy_nac_sat_hl_s1 |
2003 | 0 | 778962970U, // M2_mpy_nac_sat_lh_s0 |
2004 | 0 | 778962970U, // M2_mpy_nac_sat_lh_s1 |
2005 | 0 | 778962970U, // M2_mpy_nac_sat_ll_s0 |
2006 | 0 | 778962970U, // M2_mpy_nac_sat_ll_s1 |
2007 | 0 | 762202138U, // M2_mpy_rnd_hh_s0 |
2008 | 0 | 762202138U, // M2_mpy_rnd_hh_s1 |
2009 | 0 | 762202138U, // M2_mpy_rnd_hl_s0 |
2010 | 0 | 762202138U, // M2_mpy_rnd_hl_s1 |
2011 | 0 | 778979354U, // M2_mpy_rnd_lh_s0 |
2012 | 0 | 778979354U, // M2_mpy_rnd_lh_s1 |
2013 | 0 | 778979354U, // M2_mpy_rnd_ll_s0 |
2014 | 0 | 778979354U, // M2_mpy_rnd_ll_s1 |
2015 | 0 | 762202138U, // M2_mpy_sat_hh_s0 |
2016 | 0 | 762202138U, // M2_mpy_sat_hh_s1 |
2017 | 0 | 762202138U, // M2_mpy_sat_hl_s0 |
2018 | 0 | 762202138U, // M2_mpy_sat_hl_s1 |
2019 | 0 | 778979354U, // M2_mpy_sat_lh_s0 |
2020 | 0 | 778979354U, // M2_mpy_sat_lh_s1 |
2021 | 0 | 778979354U, // M2_mpy_sat_ll_s0 |
2022 | 0 | 778979354U, // M2_mpy_sat_ll_s1 |
2023 | 0 | 762202138U, // M2_mpy_sat_rnd_hh_s0 |
2024 | 0 | 762202138U, // M2_mpy_sat_rnd_hh_s1 |
2025 | 0 | 762202138U, // M2_mpy_sat_rnd_hl_s0 |
2026 | 0 | 762202138U, // M2_mpy_sat_rnd_hl_s1 |
2027 | 0 | 778979354U, // M2_mpy_sat_rnd_lh_s0 |
2028 | 0 | 778979354U, // M2_mpy_sat_rnd_lh_s1 |
2029 | 0 | 778979354U, // M2_mpy_sat_rnd_ll_s0 |
2030 | 0 | 778979354U, // M2_mpy_sat_rnd_ll_s1 |
2031 | 0 | 493766682U, // M2_mpy_up |
2032 | 0 | 493766682U, // M2_mpy_up_s1 |
2033 | 0 | 493766682U, // M2_mpy_up_s1_sat |
2034 | 0 | 762169370U, // M2_mpyd_acc_hh_s0 |
2035 | 0 | 762169370U, // M2_mpyd_acc_hh_s1 |
2036 | 0 | 762169370U, // M2_mpyd_acc_hl_s0 |
2037 | 0 | 762169370U, // M2_mpyd_acc_hl_s1 |
2038 | 0 | 778946586U, // M2_mpyd_acc_lh_s0 |
2039 | 0 | 778946586U, // M2_mpyd_acc_lh_s1 |
2040 | 0 | 778946586U, // M2_mpyd_acc_ll_s0 |
2041 | 0 | 778946586U, // M2_mpyd_acc_ll_s1 |
2042 | 0 | 762202138U, // M2_mpyd_hh_s0 |
2043 | 0 | 762202138U, // M2_mpyd_hh_s1 |
2044 | 0 | 762202138U, // M2_mpyd_hl_s0 |
2045 | 0 | 762202138U, // M2_mpyd_hl_s1 |
2046 | 0 | 778979354U, // M2_mpyd_lh_s0 |
2047 | 0 | 778979354U, // M2_mpyd_lh_s1 |
2048 | 0 | 778979354U, // M2_mpyd_ll_s0 |
2049 | 0 | 778979354U, // M2_mpyd_ll_s1 |
2050 | 0 | 762185754U, // M2_mpyd_nac_hh_s0 |
2051 | 0 | 762185754U, // M2_mpyd_nac_hh_s1 |
2052 | 0 | 762185754U, // M2_mpyd_nac_hl_s0 |
2053 | 0 | 762185754U, // M2_mpyd_nac_hl_s1 |
2054 | 0 | 778962970U, // M2_mpyd_nac_lh_s0 |
2055 | 0 | 778962970U, // M2_mpyd_nac_lh_s1 |
2056 | 0 | 778962970U, // M2_mpyd_nac_ll_s0 |
2057 | 0 | 778962970U, // M2_mpyd_nac_ll_s1 |
2058 | 0 | 762202138U, // M2_mpyd_rnd_hh_s0 |
2059 | 0 | 762202138U, // M2_mpyd_rnd_hh_s1 |
2060 | 0 | 762202138U, // M2_mpyd_rnd_hl_s0 |
2061 | 0 | 762202138U, // M2_mpyd_rnd_hl_s1 |
2062 | 0 | 778979354U, // M2_mpyd_rnd_lh_s0 |
2063 | 0 | 778979354U, // M2_mpyd_rnd_lh_s1 |
2064 | 0 | 778979354U, // M2_mpyd_rnd_ll_s0 |
2065 | 0 | 778979354U, // M2_mpyd_rnd_ll_s1 |
2066 | 0 | 487196698U, // M2_mpyi |
2067 | 0 | 7456794U, // M2_mpysin |
2068 | 0 | 7473178U, // M2_mpysip |
2069 | 0 | 7489562U, // M2_mpysu_up |
2070 | 0 | 762218522U, // M2_mpyu_acc_hh_s0 |
2071 | 0 | 762218522U, // M2_mpyu_acc_hh_s1 |
2072 | 0 | 762218522U, // M2_mpyu_acc_hl_s0 |
2073 | 0 | 762218522U, // M2_mpyu_acc_hl_s1 |
2074 | 0 | 778995738U, // M2_mpyu_acc_lh_s0 |
2075 | 0 | 778995738U, // M2_mpyu_acc_lh_s1 |
2076 | 0 | 778995738U, // M2_mpyu_acc_ll_s0 |
2077 | 0 | 778995738U, // M2_mpyu_acc_ll_s1 |
2078 | 0 | 762251290U, // M2_mpyu_hh_s0 |
2079 | 0 | 762251290U, // M2_mpyu_hh_s1 |
2080 | 0 | 762251290U, // M2_mpyu_hl_s0 |
2081 | 0 | 762251290U, // M2_mpyu_hl_s1 |
2082 | 0 | 779028506U, // M2_mpyu_lh_s0 |
2083 | 0 | 779028506U, // M2_mpyu_lh_s1 |
2084 | 0 | 779028506U, // M2_mpyu_ll_s0 |
2085 | 0 | 779028506U, // M2_mpyu_ll_s1 |
2086 | 0 | 762234906U, // M2_mpyu_nac_hh_s0 |
2087 | 0 | 762234906U, // M2_mpyu_nac_hh_s1 |
2088 | 0 | 762234906U, // M2_mpyu_nac_hl_s0 |
2089 | 0 | 762234906U, // M2_mpyu_nac_hl_s1 |
2090 | 0 | 779012122U, // M2_mpyu_nac_lh_s0 |
2091 | 0 | 779012122U, // M2_mpyu_nac_lh_s1 |
2092 | 0 | 779012122U, // M2_mpyu_nac_ll_s0 |
2093 | 0 | 779012122U, // M2_mpyu_nac_ll_s1 |
2094 | 0 | 493815834U, // M2_mpyu_up |
2095 | 0 | 762218522U, // M2_mpyud_acc_hh_s0 |
2096 | 0 | 762218522U, // M2_mpyud_acc_hh_s1 |
2097 | 0 | 762218522U, // M2_mpyud_acc_hl_s0 |
2098 | 0 | 762218522U, // M2_mpyud_acc_hl_s1 |
2099 | 0 | 778995738U, // M2_mpyud_acc_lh_s0 |
2100 | 0 | 778995738U, // M2_mpyud_acc_lh_s1 |
2101 | 0 | 778995738U, // M2_mpyud_acc_ll_s0 |
2102 | 0 | 778995738U, // M2_mpyud_acc_ll_s1 |
2103 | 0 | 762251290U, // M2_mpyud_hh_s0 |
2104 | 0 | 762251290U, // M2_mpyud_hh_s1 |
2105 | 0 | 762251290U, // M2_mpyud_hl_s0 |
2106 | 0 | 762251290U, // M2_mpyud_hl_s1 |
2107 | 0 | 779028506U, // M2_mpyud_lh_s0 |
2108 | 0 | 779028506U, // M2_mpyud_lh_s1 |
2109 | 0 | 779028506U, // M2_mpyud_ll_s0 |
2110 | 0 | 779028506U, // M2_mpyud_ll_s1 |
2111 | 0 | 762234906U, // M2_mpyud_nac_hh_s0 |
2112 | 0 | 762234906U, // M2_mpyud_nac_hh_s1 |
2113 | 0 | 762234906U, // M2_mpyud_nac_hl_s0 |
2114 | 0 | 762234906U, // M2_mpyud_nac_hl_s1 |
2115 | 0 | 779012122U, // M2_mpyud_nac_lh_s0 |
2116 | 0 | 779012122U, // M2_mpyud_nac_lh_s1 |
2117 | 0 | 779012122U, // M2_mpyud_nac_ll_s0 |
2118 | 0 | 779012122U, // M2_mpyud_nac_ll_s1 |
2119 | 0 | 494045210U, // M2_nacci |
2120 | 0 | 192055322U, // M2_naccii |
2121 | 0 | 7522330U, // M2_subacc |
2122 | 0 | 1312794U, // M2_vabsdiffh |
2123 | 0 | 1361946U, // M2_vabsdiffw |
2124 | 0 | 7538714U, // M2_vcmac_s0_sat_i |
2125 | 0 | 7555098U, // M2_vcmac_s0_sat_r |
2126 | 0 | 427001882U, // M2_vcmpy_s0_sat_i |
2127 | 0 | 427018266U, // M2_vcmpy_s0_sat_r |
2128 | 0 | 208898074U, // M2_vcmpy_s1_sat_i |
2129 | 0 | 208914458U, // M2_vcmpy_s1_sat_r |
2130 | 0 | 427034650U, // M2_vdmacs_s0 |
2131 | 0 | 208930842U, // M2_vdmacs_s1 |
2132 | 0 | 276056090U, // M2_vdmpyrs_s0 |
2133 | 0 | 225724442U, // M2_vdmpyrs_s1 |
2134 | 0 | 427051034U, // M2_vdmpys_s0 |
2135 | 0 | 208947226U, // M2_vdmpys_s1 |
2136 | 0 | 19384346U, // M2_vmac2 |
2137 | 0 | 24414234U, // M2_vmac2es |
2138 | 0 | 427067418U, // M2_vmac2es_s0 |
2139 | 0 | 208963610U, // M2_vmac2es_s1 |
2140 | 0 | 422037530U, // M2_vmac2s_s0 |
2141 | 0 | 203933722U, // M2_vmac2s_s1 |
2142 | 0 | 427083802U, // M2_vmac2su_s0 |
2143 | 0 | 208979994U, // M2_vmac2su_s1 |
2144 | 0 | 427100186U, // M2_vmpy2es_s0 |
2145 | 0 | 208996378U, // M2_vmpy2es_s1 |
2146 | 0 | 422053914U, // M2_vmpy2s_s0 |
2147 | 0 | 271058970U, // M2_vmpy2s_s0pack |
2148 | 0 | 203950106U, // M2_vmpy2s_s1 |
2149 | 0 | 220727322U, // M2_vmpy2s_s1pack |
2150 | 0 | 427116570U, // M2_vmpy2su_s0 |
2151 | 0 | 209012762U, // M2_vmpy2su_s1 |
2152 | 0 | 7702554U, // M2_vraddh |
2153 | 0 | 7718938U, // M2_vradduh |
2154 | 0 | 24512538U, // M2_vrcmaci_s0 |
2155 | 0 | 1668679706U, // M2_vrcmaci_s0c |
2156 | 0 | 24528922U, // M2_vrcmacr_s0 |
2157 | 0 | 1668696090U, // M2_vrcmacr_s0c |
2158 | 0 | 24545306U, // M2_vrcmpyi_s0 |
2159 | 0 | 1668712474U, // M2_vrcmpyi_s0c |
2160 | 0 | 24561690U, // M2_vrcmpyr_s0 |
2161 | 0 | 1668728858U, // M2_vrcmpyr_s0c |
2162 | 0 | 1678411802U, // M2_vrcmpys_acc_s1_h |
2163 | 0 | 1695189018U, // M2_vrcmpys_acc_s1_l |
2164 | 0 | 1678428186U, // M2_vrcmpys_s1_h |
2165 | 0 | 1695205402U, // M2_vrcmpys_s1_l |
2166 | 0 | 1711982618U, // M2_vrcmpys_s1rp_h |
2167 | 0 | 1728759834U, // M2_vrcmpys_s1rp_l |
2168 | 0 | 7800858U, // M2_vrmac_s0 |
2169 | 0 | 7817242U, // M2_vrmpy_s0 |
2170 | 0 | 7833626U, // M2_xor_xacc |
2171 | 0 | 494389274U, // M4_and_and |
2172 | 0 | 913819674U, // M4_and_andn |
2173 | 0 | 7866394U, // M4_and_or |
2174 | 0 | 7882778U, // M4_and_xor |
2175 | 0 | 226002970U, // M4_cmpyi_wh |
2176 | 0 | 1652066330U, // M4_cmpyi_whc |
2177 | 0 | 226019354U, // M4_cmpyr_wh |
2178 | 0 | 1652082714U, // M4_cmpyr_whc |
2179 | 0 | 493733914U, // M4_mac_up_s1_sat |
2180 | 0 | 1752762394U, // M4_mpyri_addi |
2181 | 0 | 2074U, // M4_mpyri_addr |
2182 | 0 | 2074U, // M4_mpyri_addr_u2 |
2183 | 0 | 1752762394U, // M4_mpyrr_addi |
2184 | 0 | 2074U, // M4_mpyrr_addr |
2185 | 0 | 493750298U, // M4_nac_up_s1_sat |
2186 | 0 | 494487578U, // M4_or_and |
2187 | 0 | 913917978U, // M4_or_andn |
2188 | 0 | 494503962U, // M4_or_or |
2189 | 0 | 7981082U, // M4_or_xor |
2190 | 0 | 7997466U, // M4_pmpyw |
2191 | 0 | 8013850U, // M4_pmpyw_acc |
2192 | 0 | 8030234U, // M4_vpmpyh |
2193 | 0 | 8046618U, // M4_vpmpyh_acc |
2194 | 0 | 24840218U, // M4_vrmpyeh_acc_s0 |
2195 | 0 | 1769670682U, // M4_vrmpyeh_acc_s1 |
2196 | 0 | 24856602U, // M4_vrmpyeh_s0 |
2197 | 0 | 1769687066U, // M4_vrmpyeh_s1 |
2198 | 0 | 24872986U, // M4_vrmpyoh_acc_s0 |
2199 | 0 | 1769703450U, // M4_vrmpyoh_acc_s1 |
2200 | 0 | 24889370U, // M4_vrmpyoh_s0 |
2201 | 0 | 1769719834U, // M4_vrmpyoh_s1 |
2202 | 0 | 494667802U, // M4_xor_and |
2203 | 0 | 914098202U, // M4_xor_andn |
2204 | 0 | 8144922U, // M4_xor_or |
2205 | 0 | 7833626U, // M4_xor_xacc |
2206 | 0 | 8161306U, // M5_vdmacbsu |
2207 | 0 | 8177690U, // M5_vdmpybsu |
2208 | 0 | 8194074U, // M5_vmacbsu |
2209 | 0 | 8210458U, // M5_vmacbuu |
2210 | 0 | 8226842U, // M5_vmpybsu |
2211 | 0 | 8243226U, // M5_vmpybuu |
2212 | 0 | 8259610U, // M5_vrmacbsu |
2213 | 0 | 8275994U, // M5_vrmacbuu |
2214 | 0 | 8292378U, // M5_vrmpybsu |
2215 | 0 | 8308762U, // M5_vrmpybuu |
2216 | 0 | 8325146U, // M6_vabsdiffb |
2217 | 0 | 1329178U, // M6_vabsdiffub |
2218 | 0 | 25118746U, // M7_dcmpyiw |
2219 | 0 | 25135130U, // M7_dcmpyiw_acc |
2220 | 0 | 1669285914U, // M7_dcmpyiwc |
2221 | 0 | 1669302298U, // M7_dcmpyiwc_acc |
2222 | 0 | 25151514U, // M7_dcmpyrw |
2223 | 0 | 25167898U, // M7_dcmpyrw_acc |
2224 | 0 | 1669318682U, // M7_dcmpyrwc |
2225 | 0 | 1669335066U, // M7_dcmpyrwc_acc |
2226 | 0 | 209668122U, // M7_wcmpyiw |
2227 | 0 | 226445338U, // M7_wcmpyiw_rnd |
2228 | 0 | 1618954266U, // M7_wcmpyiwc |
2229 | 0 | 1652508698U, // M7_wcmpyiwc_rnd |
2230 | 0 | 209700890U, // M7_wcmpyrw |
2231 | 0 | 226478106U, // M7_wcmpyrw_rnd |
2232 | 0 | 1618987034U, // M7_wcmpyrwc |
2233 | 0 | 1652541466U, // M7_wcmpyrwc_rnd |
2234 | 0 | 759897U, // PS_call_stk |
2235 | 0 | 755813U, // PS_callr_nr |
2236 | 0 | 755820U, // PS_jmpret |
2237 | 0 | 6473843U, // PS_jmpretf |
2238 | 0 | 6490227U, // PS_jmpretfnew |
2239 | 0 | 6506611U, // PS_jmpretfnewpt |
2240 | 0 | 6474022U, // PS_jmprett |
2241 | 0 | 6490406U, // PS_jmprettnew |
2242 | 0 | 6506790U, // PS_jmprettnewpt |
2243 | 0 | 8407066U, // PS_loadrbabs |
2244 | 0 | 8423450U, // PS_loadrdabs |
2245 | 0 | 8439834U, // PS_loadrhabs |
2246 | 0 | 8456218U, // PS_loadriabs |
2247 | 0 | 8472602U, // PS_loadrubabs |
2248 | 0 | 8488986U, // PS_loadruhabs |
2249 | 0 | 51185838U, // PS_storerbabs |
2250 | 0 | 235735214U, // PS_storerbnewabs |
2251 | 0 | 51185845U, // PS_storerdabs |
2252 | 0 | 252512465U, // PS_storerfabs |
2253 | 0 | 51185873U, // PS_storerhabs |
2254 | 0 | 235735249U, // PS_storerhnewabs |
2255 | 0 | 51185889U, // PS_storeriabs |
2256 | 0 | 235735265U, // PS_storerinewabs |
2257 | 0 | 297114U, // PS_trap1 |
2258 | 0 | 8505899U, // R6_release_at_vi |
2259 | 0 | 8522283U, // R6_release_st_vi |
2260 | 0 | 759897U, // RESTORE_DEALLOC_BEFORE_TAILCALL_V4 |
2261 | 0 | 759897U, // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT |
2262 | 0 | 759897U, // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC |
2263 | 0 | 759897U, // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC |
2264 | 0 | 759903U, // RESTORE_DEALLOC_RET_JMP_V4 |
2265 | 0 | 759903U, // RESTORE_DEALLOC_RET_JMP_V4_EXT |
2266 | 0 | 759903U, // RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC |
2267 | 0 | 759903U, // RESTORE_DEALLOC_RET_JMP_V4_PIC |
2268 | 0 | 8538138U, // S2_addasl_rrri |
2269 | 0 | 71387669U, // S2_allocframe |
2270 | 0 | 193103898U, // S2_asl_i_p |
2271 | 0 | 193120282U, // S2_asl_i_p_acc |
2272 | 0 | 193136666U, // S2_asl_i_p_and |
2273 | 0 | 193153050U, // S2_asl_i_p_nac |
2274 | 0 | 193169434U, // S2_asl_i_p_or |
2275 | 0 | 193185818U, // S2_asl_i_p_xacc |
2276 | 0 | 193103898U, // S2_asl_i_r |
2277 | 0 | 193120282U, // S2_asl_i_r_acc |
2278 | 0 | 193136666U, // S2_asl_i_r_and |
2279 | 0 | 193153050U, // S2_asl_i_r_nac |
2280 | 0 | 193169434U, // S2_asl_i_r_or |
2281 | 0 | 193103898U, // S2_asl_i_r_sat |
2282 | 0 | 193185818U, // S2_asl_i_r_xacc |
2283 | 0 | 186271770U, // S2_asl_i_vh |
2284 | 0 | 186304538U, // S2_asl_i_vw |
2285 | 0 | 495093786U, // S2_asl_r_p |
2286 | 0 | 495110170U, // S2_asl_r_p_acc |
2287 | 0 | 495126554U, // S2_asl_r_p_and |
2288 | 0 | 495142938U, // S2_asl_r_p_nac |
2289 | 0 | 495159322U, // S2_asl_r_p_or |
2290 | 0 | 495175706U, // S2_asl_r_p_xor |
2291 | 0 | 495093786U, // S2_asl_r_r |
2292 | 0 | 495110170U, // S2_asl_r_r_acc |
2293 | 0 | 495126554U, // S2_asl_r_r_and |
2294 | 0 | 495142938U, // S2_asl_r_r_nac |
2295 | 0 | 495159322U, // S2_asl_r_r_or |
2296 | 0 | 495093786U, // S2_asl_r_r_sat |
2297 | 0 | 488261658U, // S2_asl_r_vh |
2298 | 0 | 488294426U, // S2_asl_r_vw |
2299 | 0 | 193202202U, // S2_asr_i_p |
2300 | 0 | 193218586U, // S2_asr_i_p_acc |
2301 | 0 | 193234970U, // S2_asr_i_p_and |
2302 | 0 | 193251354U, // S2_asr_i_p_nac |
2303 | 0 | 193267738U, // S2_asr_i_p_or |
2304 | 0 | 193202202U, // S2_asr_i_p_rnd |
2305 | 0 | 193202202U, // S2_asr_i_r |
2306 | 0 | 193218586U, // S2_asr_i_r_acc |
2307 | 0 | 193234970U, // S2_asr_i_r_and |
2308 | 0 | 193251354U, // S2_asr_i_r_nac |
2309 | 0 | 193267738U, // S2_asr_i_r_or |
2310 | 0 | 193202202U, // S2_asr_i_r_rnd |
2311 | 0 | 186370074U, // S2_asr_i_svw_trun |
2312 | 0 | 185583642U, // S2_asr_i_vh |
2313 | 0 | 186370074U, // S2_asr_i_vw |
2314 | 0 | 495192090U, // S2_asr_r_p |
2315 | 0 | 495208474U, // S2_asr_r_p_acc |
2316 | 0 | 495224858U, // S2_asr_r_p_and |
2317 | 0 | 495241242U, // S2_asr_r_p_nac |
2318 | 0 | 495257626U, // S2_asr_r_p_or |
2319 | 0 | 8734746U, // S2_asr_r_p_xor |
2320 | 0 | 495192090U, // S2_asr_r_r |
2321 | 0 | 495208474U, // S2_asr_r_r_acc |
2322 | 0 | 495224858U, // S2_asr_r_r_and |
2323 | 0 | 495241242U, // S2_asr_r_r_nac |
2324 | 0 | 495257626U, // S2_asr_r_r_or |
2325 | 0 | 495192090U, // S2_asr_r_r_sat |
2326 | 0 | 488359962U, // S2_asr_r_svw_trun |
2327 | 0 | 487573530U, // S2_asr_r_vh |
2328 | 0 | 488359962U, // S2_asr_r_vw |
2329 | 0 | 8751130U, // S2_brev |
2330 | 0 | 8751130U, // S2_brevp |
2331 | 0 | 8767514U, // S2_cabacdecbin |
2332 | 0 | 8783898U, // S2_cl0 |
2333 | 0 | 8783898U, // S2_cl0p |
2334 | 0 | 8800282U, // S2_cl1 |
2335 | 0 | 8800282U, // S2_cl1p |
2336 | 0 | 8816666U, // S2_clb |
2337 | 0 | 8833050U, // S2_clbnorm |
2338 | 0 | 8816666U, // S2_clbp |
2339 | 0 | 193398810U, // S2_clrbit_i |
2340 | 0 | 495388698U, // S2_clrbit_r |
2341 | 0 | 8865818U, // S2_ct0 |
2342 | 0 | 8865818U, // S2_ct0p |
2343 | 0 | 8882202U, // S2_ct1 |
2344 | 0 | 8882202U, // S2_ct1p |
2345 | 0 | 8898586U, // S2_deinterleave |
2346 | 0 | 193464346U, // S2_extractu |
2347 | 0 | 495454234U, // S2_extractu_rp |
2348 | 0 | 193464346U, // S2_extractup |
2349 | 0 | 495454234U, // S2_extractup_rp |
2350 | 0 | 193480730U, // S2_insert |
2351 | 0 | 495470618U, // S2_insert_rp |
2352 | 0 | 193480730U, // S2_insertp |
2353 | 0 | 495470618U, // S2_insertp_rp |
2354 | 0 | 8947738U, // S2_interleave |
2355 | 0 | 8964122U, // S2_lfsp |
2356 | 0 | 8980506U, // S2_lsl_r_p |
2357 | 0 | 8996890U, // S2_lsl_r_p_acc |
2358 | 0 | 9013274U, // S2_lsl_r_p_and |
2359 | 0 | 9029658U, // S2_lsl_r_p_nac |
2360 | 0 | 9046042U, // S2_lsl_r_p_or |
2361 | 0 | 9062426U, // S2_lsl_r_p_xor |
2362 | 0 | 8980506U, // S2_lsl_r_r |
2363 | 0 | 8996890U, // S2_lsl_r_r_acc |
2364 | 0 | 9013274U, // S2_lsl_r_r_and |
2365 | 0 | 9029658U, // S2_lsl_r_r_nac |
2366 | 0 | 9046042U, // S2_lsl_r_r_or |
2367 | 0 | 9078810U, // S2_lsl_r_vh |
2368 | 0 | 9095194U, // S2_lsl_r_vw |
2369 | 0 | 193660954U, // S2_lsr_i_p |
2370 | 0 | 193677338U, // S2_lsr_i_p_acc |
2371 | 0 | 193693722U, // S2_lsr_i_p_and |
2372 | 0 | 193710106U, // S2_lsr_i_p_nac |
2373 | 0 | 193726490U, // S2_lsr_i_p_or |
2374 | 0 | 193742874U, // S2_lsr_i_p_xacc |
2375 | 0 | 193660954U, // S2_lsr_i_r |
2376 | 0 | 193677338U, // S2_lsr_i_r_acc |
2377 | 0 | 193693722U, // S2_lsr_i_r_and |
2378 | 0 | 193710106U, // S2_lsr_i_r_nac |
2379 | 0 | 193726490U, // S2_lsr_i_r_or |
2380 | 0 | 193742874U, // S2_lsr_i_r_xacc |
2381 | 0 | 186746906U, // S2_lsr_i_vh |
2382 | 0 | 186763290U, // S2_lsr_i_vw |
2383 | 0 | 495650842U, // S2_lsr_r_p |
2384 | 0 | 495667226U, // S2_lsr_r_p_acc |
2385 | 0 | 495683610U, // S2_lsr_r_p_and |
2386 | 0 | 495699994U, // S2_lsr_r_p_nac |
2387 | 0 | 495716378U, // S2_lsr_r_p_or |
2388 | 0 | 495732762U, // S2_lsr_r_p_xor |
2389 | 0 | 495650842U, // S2_lsr_r_r |
2390 | 0 | 495667226U, // S2_lsr_r_r_acc |
2391 | 0 | 495683610U, // S2_lsr_r_r_and |
2392 | 0 | 495699994U, // S2_lsr_r_r_nac |
2393 | 0 | 495716378U, // S2_lsr_r_r_or |
2394 | 0 | 488736794U, // S2_lsr_r_vh |
2395 | 0 | 488753178U, // S2_lsr_r_vw |
2396 | 0 | 9209882U, // S2_mask |
2397 | 0 | 26003482U, // S2_packhl |
2398 | 0 | 9242650U, // S2_parityp |
2399 | 0 | 788595U, // S2_pstorerbf_io |
2400 | 0 | 1779175539U, // S2_pstorerbf_pi |
2401 | 0 | 1779322995U, // S2_pstorerbfnew_pi |
2402 | 0 | 788595U, // S2_pstorerbnewf_io |
2403 | 0 | 1779175539U, // S2_pstorerbnewf_pi |
2404 | 0 | 1779322995U, // S2_pstorerbnewfnew_pi |
2405 | 0 | 788774U, // S2_pstorerbnewt_io |
2406 | 0 | 1779175718U, // S2_pstorerbnewt_pi |
2407 | 0 | 1779323174U, // S2_pstorerbnewtnew_pi |
2408 | 0 | 788774U, // S2_pstorerbt_io |
2409 | 0 | 1779175718U, // S2_pstorerbt_pi |
2410 | 0 | 1779323174U, // S2_pstorerbtnew_pi |
2411 | 0 | 804979U, // S2_pstorerdf_io |
2412 | 0 | 1779191923U, // S2_pstorerdf_pi |
2413 | 0 | 1779339379U, // S2_pstorerdfnew_pi |
2414 | 0 | 805158U, // S2_pstorerdt_io |
2415 | 0 | 1779192102U, // S2_pstorerdt_pi |
2416 | 0 | 1779339558U, // S2_pstorerdtnew_pi |
2417 | 0 | 821363U, // S2_pstorerff_io |
2418 | 0 | 1779208307U, // S2_pstorerff_pi |
2419 | 0 | 1779355763U, // S2_pstorerffnew_pi |
2420 | 0 | 821542U, // S2_pstorerft_io |
2421 | 0 | 1779208486U, // S2_pstorerft_pi |
2422 | 0 | 1779355942U, // S2_pstorerftnew_pi |
2423 | 0 | 821363U, // S2_pstorerhf_io |
2424 | 0 | 1779208307U, // S2_pstorerhf_pi |
2425 | 0 | 1779355763U, // S2_pstorerhfnew_pi |
2426 | 0 | 821363U, // S2_pstorerhnewf_io |
2427 | 0 | 1779208307U, // S2_pstorerhnewf_pi |
2428 | 0 | 1779355763U, // S2_pstorerhnewfnew_pi |
2429 | 0 | 821542U, // S2_pstorerhnewt_io |
2430 | 0 | 1779208486U, // S2_pstorerhnewt_pi |
2431 | 0 | 1779355942U, // S2_pstorerhnewtnew_pi |
2432 | 0 | 821542U, // S2_pstorerht_io |
2433 | 0 | 1779208486U, // S2_pstorerht_pi |
2434 | 0 | 1779355942U, // S2_pstorerhtnew_pi |
2435 | 0 | 837747U, // S2_pstorerif_io |
2436 | 0 | 1779224691U, // S2_pstorerif_pi |
2437 | 0 | 1779372147U, // S2_pstorerifnew_pi |
2438 | 0 | 837747U, // S2_pstorerinewf_io |
2439 | 0 | 1779224691U, // S2_pstorerinewf_pi |
2440 | 0 | 1779372147U, // S2_pstorerinewfnew_pi |
2441 | 0 | 837926U, // S2_pstorerinewt_io |
2442 | 0 | 1779224870U, // S2_pstorerinewt_pi |
2443 | 0 | 1779372326U, // S2_pstorerinewtnew_pi |
2444 | 0 | 837926U, // S2_pstorerit_io |
2445 | 0 | 1779224870U, // S2_pstorerit_pi |
2446 | 0 | 1779372326U, // S2_pstoreritnew_pi |
2447 | 0 | 193808410U, // S2_setbit_i |
2448 | 0 | 495798298U, // S2_setbit_r |
2449 | 0 | 9275418U, // S2_shuffeb |
2450 | 0 | 9291802U, // S2_shuffeh |
2451 | 0 | 9308186U, // S2_shuffob |
2452 | 0 | 9324570U, // S2_shuffoh |
2453 | 0 | 725715408U, // S2_storerb_io |
2454 | 0 | 1804503504U, // S2_storerb_pbr |
2455 | 0 | 1821297104U, // S2_storerb_pci |
2456 | 0 | 59705808U, // S2_storerb_pcr |
2457 | 0 | 730778064U, // S2_storerb_pi |
2458 | 0 | 730761680U, // S2_storerb_pr |
2459 | 0 | 51185918U, // S2_storerbgp |
2460 | 0 | 725715408U, // S2_storerbnew_io |
2461 | 0 | 1804503504U, // S2_storerbnew_pbr |
2462 | 0 | 1821297104U, // S2_storerbnew_pci |
2463 | 0 | 244255184U, // S2_storerbnew_pcr |
2464 | 0 | 730778064U, // S2_storerbnew_pi |
2465 | 0 | 730761680U, // S2_storerbnew_pr |
2466 | 0 | 235735294U, // S2_storerbnewgp |
2467 | 0 | 725715464U, // S2_storerd_io |
2468 | 0 | 1804503560U, // S2_storerd_pbr |
2469 | 0 | 1821297160U, // S2_storerd_pci |
2470 | 0 | 59705864U, // S2_storerd_pcr |
2471 | 0 | 730778120U, // S2_storerd_pi |
2472 | 0 | 730761736U, // S2_storerd_pr |
2473 | 0 | 51185928U, // S2_storerdgp |
2474 | 0 | 725715540U, // S2_storerf_io |
2475 | 0 | 1804503636U, // S2_storerf_pbr |
2476 | 0 | 1821297236U, // S2_storerf_pci |
2477 | 0 | 261032532U, // S2_storerf_pcr |
2478 | 0 | 730778196U, // S2_storerf_pi |
2479 | 0 | 730761812U, // S2_storerf_pr |
2480 | 0 | 252512530U, // S2_storerfgp |
2481 | 0 | 725715540U, // S2_storerh_io |
2482 | 0 | 1804503636U, // S2_storerh_pbr |
2483 | 0 | 1821297236U, // S2_storerh_pci |
2484 | 0 | 59705940U, // S2_storerh_pcr |
2485 | 0 | 730778196U, // S2_storerh_pi |
2486 | 0 | 730761812U, // S2_storerh_pr |
2487 | 0 | 51185938U, // S2_storerhgp |
2488 | 0 | 725715540U, // S2_storerhnew_io |
2489 | 0 | 1804503636U, // S2_storerhnew_pbr |
2490 | 0 | 1821297236U, // S2_storerhnew_pci |
2491 | 0 | 244255316U, // S2_storerhnew_pcr |
2492 | 0 | 730778196U, // S2_storerhnew_pi |
2493 | 0 | 730761812U, // S2_storerhnew_pr |
2494 | 0 | 235735314U, // S2_storerhnewgp |
2495 | 0 | 725715986U, // S2_storeri_io |
2496 | 0 | 1804504082U, // S2_storeri_pbr |
2497 | 0 | 1821297682U, // S2_storeri_pci |
2498 | 0 | 59706386U, // S2_storeri_pcr |
2499 | 0 | 730778642U, // S2_storeri_pi |
2500 | 0 | 730762258U, // S2_storeri_pr |
2501 | 0 | 51185948U, // S2_storerigp |
2502 | 0 | 725715986U, // S2_storerinew_io |
2503 | 0 | 1804504082U, // S2_storerinew_pbr |
2504 | 0 | 1821297682U, // S2_storerinew_pci |
2505 | 0 | 244255762U, // S2_storerinew_pcr |
2506 | 0 | 730778642U, // S2_storerinew_pi |
2507 | 0 | 730762258U, // S2_storerinew_pr |
2508 | 0 | 235735324U, // S2_storerinewgp |
2509 | 0 | 1782010351U, // S2_storew_locked |
2510 | 0 | 9390727U, // S2_storew_rl_at_vi |
2511 | 0 | 9407111U, // S2_storew_rl_st_vi |
2512 | 0 | 9422874U, // S2_svsathb |
2513 | 0 | 20334618U, // S2_svsathub |
2514 | 0 | 1829586970U, // S2_tableidxb |
2515 | 0 | 1829603354U, // S2_tableidxd |
2516 | 0 | 1829619738U, // S2_tableidxh |
2517 | 0 | 1829636122U, // S2_tableidxw |
2518 | 0 | 193988634U, // S2_togglebit_i |
2519 | 0 | 495978522U, // S2_togglebit_r |
2520 | 0 | 194005018U, // S2_tstbit_i |
2521 | 0 | 495994906U, // S2_tstbit_r |
2522 | 0 | 194021402U, // S2_valignib |
2523 | 0 | 496011290U, // S2_valignrb |
2524 | 0 | 9488410U, // S2_vcnegh |
2525 | 0 | 9504794U, // S2_vcrotate |
2526 | 0 | 9521178U, // S2_vrcnegh |
2527 | 0 | 26314778U, // S2_vrndpackwh |
2528 | 0 | 428967962U, // S2_vrndpackwhs |
2529 | 0 | 9422874U, // S2_vsathb |
2530 | 0 | 9422874U, // S2_vsathb_nopack |
2531 | 0 | 20334618U, // S2_vsathub |
2532 | 0 | 20334618U, // S2_vsathub_nopack |
2533 | 0 | 20367386U, // S2_vsatwh |
2534 | 0 | 20367386U, // S2_vsatwh_nopack |
2535 | 0 | 9553946U, // S2_vsatwuh |
2536 | 0 | 9553946U, // S2_vsatwuh_nopack |
2537 | 0 | 9570330U, // S2_vsplatrb |
2538 | 0 | 9586714U, // S2_vsplatrh |
2539 | 0 | 194152474U, // S2_vspliceib |
2540 | 0 | 496142362U, // S2_vsplicerb |
2541 | 0 | 9619482U, // S2_vsxtbh |
2542 | 0 | 9635866U, // S2_vsxthw |
2543 | 0 | 26429466U, // S2_vtrunehb |
2544 | 0 | 9668634U, // S2_vtrunewh |
2545 | 0 | 26462234U, // S2_vtrunohb |
2546 | 0 | 9701402U, // S2_vtrunowh |
2547 | 0 | 9717786U, // S2_vzxtbh |
2548 | 0 | 9734170U, // S2_vzxthw |
2549 | 0 | 2074U, // S4_addaddi |
2550 | 0 | 1853425690U, // S4_addi_asl_ri |
2551 | 0 | 1870202906U, // S4_addi_lsr_ri |
2552 | 0 | 1855244314U, // S4_andi_asl_ri |
2553 | 0 | 1872021530U, // S4_andi_lsr_ri |
2554 | 0 | 9766938U, // S4_clbaddi |
2555 | 0 | 9766938U, // S4_clbpaddi |
2556 | 0 | 8833050U, // S4_clbpnorm |
2557 | 0 | 194332698U, // S4_extract |
2558 | 0 | 496322586U, // S4_extract_rp |
2559 | 0 | 194332698U, // S4_extractp |
2560 | 0 | 496322586U, // S4_extractp_rp |
2561 | 0 | 9799706U, // S4_lsli |
2562 | 0 | 194365466U, // S4_ntstbit_i |
2563 | 0 | 496355354U, // S4_ntstbit_r |
2564 | 0 | 192497690U, // S4_or_andi |
2565 | 0 | 1094944794U, // S4_or_andix |
2566 | 0 | 192514074U, // S4_or_ori |
2567 | 0 | 1855326234U, // S4_ori_asl_ri |
2568 | 0 | 1872103450U, // S4_ori_lsr_ri |
2569 | 0 | 9242650U, // S4_parity |
2570 | 0 | 60180595U, // S4_pstorerbf_abs |
2571 | 0 | 788595U, // S4_pstorerbf_rr |
2572 | 0 | 60196979U, // S4_pstorerbfnew_abs |
2573 | 0 | 936051U, // S4_pstorerbfnew_io |
2574 | 0 | 936051U, // S4_pstorerbfnew_rr |
2575 | 0 | 244729971U, // S4_pstorerbnewf_abs |
2576 | 0 | 788595U, // S4_pstorerbnewf_rr |
2577 | 0 | 244746355U, // S4_pstorerbnewfnew_abs |
2578 | 0 | 936051U, // S4_pstorerbnewfnew_io |
2579 | 0 | 936051U, // S4_pstorerbnewfnew_rr |
2580 | 0 | 244730150U, // S4_pstorerbnewt_abs |
2581 | 0 | 788774U, // S4_pstorerbnewt_rr |
2582 | 0 | 244746534U, // S4_pstorerbnewtnew_abs |
2583 | 0 | 936230U, // S4_pstorerbnewtnew_io |
2584 | 0 | 936230U, // S4_pstorerbnewtnew_rr |
2585 | 0 | 60180774U, // S4_pstorerbt_abs |
2586 | 0 | 788774U, // S4_pstorerbt_rr |
2587 | 0 | 60197158U, // S4_pstorerbtnew_abs |
2588 | 0 | 936230U, // S4_pstorerbtnew_io |
2589 | 0 | 936230U, // S4_pstorerbtnew_rr |
2590 | 0 | 9881715U, // S4_pstorerdf_abs |
2591 | 0 | 804979U, // S4_pstorerdf_rr |
2592 | 0 | 9898099U, // S4_pstorerdfnew_abs |
2593 | 0 | 952435U, // S4_pstorerdfnew_io |
2594 | 0 | 952435U, // S4_pstorerdfnew_rr |
2595 | 0 | 9881894U, // S4_pstorerdt_abs |
2596 | 0 | 805158U, // S4_pstorerdt_rr |
2597 | 0 | 9898278U, // S4_pstorerdtnew_abs |
2598 | 0 | 952614U, // S4_pstorerdtnew_io |
2599 | 0 | 952614U, // S4_pstorerdtnew_rr |
2600 | 0 | 261572723U, // S4_pstorerff_abs |
2601 | 0 | 821363U, // S4_pstorerff_rr |
2602 | 0 | 261589107U, // S4_pstorerffnew_abs |
2603 | 0 | 968819U, // S4_pstorerffnew_io |
2604 | 0 | 968819U, // S4_pstorerffnew_rr |
2605 | 0 | 261572902U, // S4_pstorerft_abs |
2606 | 0 | 821542U, // S4_pstorerft_rr |
2607 | 0 | 261589286U, // S4_pstorerftnew_abs |
2608 | 0 | 968998U, // S4_pstorerftnew_io |
2609 | 0 | 968998U, // S4_pstorerftnew_rr |
2610 | 0 | 60246131U, // S4_pstorerhf_abs |
2611 | 0 | 821363U, // S4_pstorerhf_rr |
2612 | 0 | 60262515U, // S4_pstorerhfnew_abs |
2613 | 0 | 968819U, // S4_pstorerhfnew_io |
2614 | 0 | 968819U, // S4_pstorerhfnew_rr |
2615 | 0 | 244795507U, // S4_pstorerhnewf_abs |
2616 | 0 | 821363U, // S4_pstorerhnewf_rr |
2617 | 0 | 244811891U, // S4_pstorerhnewfnew_abs |
2618 | 0 | 968819U, // S4_pstorerhnewfnew_io |
2619 | 0 | 968819U, // S4_pstorerhnewfnew_rr |
2620 | 0 | 244795686U, // S4_pstorerhnewt_abs |
2621 | 0 | 821542U, // S4_pstorerhnewt_rr |
2622 | 0 | 244812070U, // S4_pstorerhnewtnew_abs |
2623 | 0 | 968998U, // S4_pstorerhnewtnew_io |
2624 | 0 | 968998U, // S4_pstorerhnewtnew_rr |
2625 | 0 | 60246310U, // S4_pstorerht_abs |
2626 | 0 | 821542U, // S4_pstorerht_rr |
2627 | 0 | 60262694U, // S4_pstorerhtnew_abs |
2628 | 0 | 968998U, // S4_pstorerhtnew_io |
2629 | 0 | 968998U, // S4_pstorerhtnew_rr |
2630 | 0 | 60278899U, // S4_pstorerif_abs |
2631 | 0 | 837747U, // S4_pstorerif_rr |
2632 | 0 | 60295283U, // S4_pstorerifnew_abs |
2633 | 0 | 985203U, // S4_pstorerifnew_io |
2634 | 0 | 985203U, // S4_pstorerifnew_rr |
2635 | 0 | 244828275U, // S4_pstorerinewf_abs |
2636 | 0 | 837747U, // S4_pstorerinewf_rr |
2637 | 0 | 244844659U, // S4_pstorerinewfnew_abs |
2638 | 0 | 985203U, // S4_pstorerinewfnew_io |
2639 | 0 | 985203U, // S4_pstorerinewfnew_rr |
2640 | 0 | 244828454U, // S4_pstorerinewt_abs |
2641 | 0 | 837926U, // S4_pstorerinewt_rr |
2642 | 0 | 244844838U, // S4_pstorerinewtnew_abs |
2643 | 0 | 985382U, // S4_pstorerinewtnew_io |
2644 | 0 | 985382U, // S4_pstorerinewtnew_rr |
2645 | 0 | 60279078U, // S4_pstorerit_abs |
2646 | 0 | 837926U, // S4_pstorerit_rr |
2647 | 0 | 60295462U, // S4_pstoreritnew_abs |
2648 | 0 | 985382U, // S4_pstoreritnew_io |
2649 | 0 | 985382U, // S4_pstoreritnew_rr |
2650 | 0 | 1782010338U, // S4_stored_locked |
2651 | 0 | 9390718U, // S4_stored_rl_at_vi |
2652 | 0 | 9407102U, // S4_stored_rl_st_vi |
2653 | 0 | 742492624U, // S4_storeirb_io |
2654 | 0 | 788595U, // S4_storeirbf_io |
2655 | 0 | 936051U, // S4_storeirbfnew_io |
2656 | 0 | 788774U, // S4_storeirbt_io |
2657 | 0 | 936230U, // S4_storeirbtnew_io |
2658 | 0 | 742492756U, // S4_storeirh_io |
2659 | 0 | 821363U, // S4_storeirhf_io |
2660 | 0 | 968819U, // S4_storeirhfnew_io |
2661 | 0 | 821542U, // S4_storeirht_io |
2662 | 0 | 968998U, // S4_storeirhtnew_io |
2663 | 0 | 742493202U, // S4_storeiri_io |
2664 | 0 | 837747U, // S4_storeirif_io |
2665 | 0 | 985203U, // S4_storeirifnew_io |
2666 | 0 | 837926U, // S4_storeirit_io |
2667 | 0 | 985382U, // S4_storeiritnew_io |
2668 | 0 | 60312016U, // S4_storerb_ap |
2669 | 0 | 60328400U, // S4_storerb_rr |
2670 | 0 | 60344784U, // S4_storerb_ur |
2671 | 0 | 244861392U, // S4_storerbnew_ap |
2672 | 0 | 244877776U, // S4_storerbnew_rr |
2673 | 0 | 244894160U, // S4_storerbnew_ur |
2674 | 0 | 60312072U, // S4_storerd_ap |
2675 | 0 | 60328456U, // S4_storerd_rr |
2676 | 0 | 60344840U, // S4_storerd_ur |
2677 | 0 | 261638740U, // S4_storerf_ap |
2678 | 0 | 261655124U, // S4_storerf_rr |
2679 | 0 | 261671508U, // S4_storerf_ur |
2680 | 0 | 60312148U, // S4_storerh_ap |
2681 | 0 | 60328532U, // S4_storerh_rr |
2682 | 0 | 60344916U, // S4_storerh_ur |
2683 | 0 | 244861524U, // S4_storerhnew_ap |
2684 | 0 | 244877908U, // S4_storerhnew_rr |
2685 | 0 | 244894292U, // S4_storerhnew_ur |
2686 | 0 | 60312594U, // S4_storeri_ap |
2687 | 0 | 60328978U, // S4_storeri_rr |
2688 | 0 | 60345362U, // S4_storeri_ur |
2689 | 0 | 244861970U, // S4_storerinew_ap |
2690 | 0 | 244878354U, // S4_storerinew_rr |
2691 | 0 | 244894738U, // S4_storerinew_ur |
2692 | 0 | 2074U, // S4_subaddi |
2693 | 0 | 1850050586U, // S4_subi_asl_ri |
2694 | 0 | 1866827802U, // S4_subi_lsr_ri |
2695 | 0 | 10029082U, // S4_vrcrotate |
2696 | 0 | 10045466U, // S4_vrcrotate_acc |
2697 | 0 | 429492250U, // S4_vxaddsubh |
2698 | 0 | 1889110042U, // S4_vxaddsubhr |
2699 | 0 | 10078234U, // S4_vxaddsubw |
2700 | 0 | 429525018U, // S4_vxsubaddh |
2701 | 0 | 1889142810U, // S4_vxsubaddhr |
2702 | 0 | 10111002U, // S4_vxsubaddw |
2703 | 0 | 1829734426U, // S5_asrhub_rnd_sat |
2704 | 0 | 420448282U, // S5_asrhub_sat |
2705 | 0 | 10127386U, // S5_popcountp |
2706 | 0 | 185583642U, // S5_vasrhrnd |
2707 | 0 | 10143770U, // S6_rol_i_p |
2708 | 0 | 10160154U, // S6_rol_i_p_acc |
2709 | 0 | 10176538U, // S6_rol_i_p_and |
2710 | 0 | 10192922U, // S6_rol_i_p_nac |
2711 | 0 | 10209306U, // S6_rol_i_p_or |
2712 | 0 | 10225690U, // S6_rol_i_p_xacc |
2713 | 0 | 10143770U, // S6_rol_i_r |
2714 | 0 | 10160154U, // S6_rol_i_r_acc |
2715 | 0 | 10176538U, // S6_rol_i_r_and |
2716 | 0 | 10192922U, // S6_rol_i_r_nac |
2717 | 0 | 10209306U, // S6_rol_i_r_or |
2718 | 0 | 10225690U, // S6_rol_i_r_xacc |
2719 | 0 | 9570330U, // S6_vsplatrbp |
2720 | 0 | 496191514U, // S6_vtrunehb_ppp |
2721 | 0 | 496224282U, // S6_vtrunohb_ppp |
2722 | 0 | 2074U, // SA1_addi |
2723 | 0 | 2074U, // SA1_addrx |
2724 | 0 | 10242074U, // SA1_addsp |
2725 | 0 | 1899972634U, // SA1_and1 |
2726 | 0 | 1968155U, // SA1_clrf |
2727 | 0 | 1968174U, // SA1_clrfnew |
2728 | 0 | 1968165U, // SA1_clrt |
2729 | 0 | 1968188U, // SA1_clrtnew |
2730 | 0 | 4278971U, // SA1_cmpeqi |
2731 | 0 | 10258458U, // SA1_combine0i |
2732 | 0 | 10274842U, // SA1_combine1i |
2733 | 0 | 10291226U, // SA1_combine2i |
2734 | 0 | 10307610U, // SA1_combine3i |
2735 | 0 | 1916831770U, // SA1_combinerz |
2736 | 0 | 10323994U, // SA1_combinezr |
2737 | 0 | 2074U, // SA1_dec |
2738 | 0 | 2074U, // SA1_inc |
2739 | 0 | 50448410U, // SA1_seti |
2740 | 0 | 50448410U, // SA1_setin1 |
2741 | 0 | 4179994U, // SA1_sxtb |
2742 | 0 | 4196378U, // SA1_sxth |
2743 | 0 | 50432026U, // SA1_tfr |
2744 | 0 | 1933527066U, // SA1_zxtb |
2745 | 0 | 4212762U, // SA1_zxth |
2746 | 0 | 759897U, // SAVE_REGISTERS_CALL_V4 |
2747 | 0 | 759897U, // SAVE_REGISTERS_CALL_V4STK |
2748 | 0 | 759897U, // SAVE_REGISTERS_CALL_V4STK_EXT |
2749 | 0 | 759897U, // SAVE_REGISTERS_CALL_V4STK_EXT_PIC |
2750 | 0 | 759897U, // SAVE_REGISTERS_CALL_V4STK_PIC |
2751 | 0 | 759897U, // SAVE_REGISTERS_CALL_V4_EXT |
2752 | 0 | 759897U, // SAVE_REGISTERS_CALL_V4_EXT_PIC |
2753 | 0 | 759897U, // SAVE_REGISTERS_CALL_V4_PIC |
2754 | 0 | 705071130U, // SL1_loadri_io |
2755 | 0 | 705087514U, // SL1_loadrub_io |
2756 | 0 | 1565U, // SL2_deallocframe |
2757 | 0 | 1328U, // SL2_jumpr31 |
2758 | 0 | 1319U, // SL2_jumpr31_f |
2759 | 0 | 1356U, // SL2_jumpr31_fnew |
2760 | 0 | 1338U, // SL2_jumpr31_t |
2761 | 0 | 1382U, // SL2_jumpr31_tnew |
2762 | 0 | 705021978U, // SL2_loadrb_io |
2763 | 0 | 10340378U, // SL2_loadrd_sp |
2764 | 0 | 705054746U, // SL2_loadrh_io |
2765 | 0 | 10356762U, // SL2_loadri_sp |
2766 | 0 | 705103898U, // SL2_loadruh_io |
2767 | 0 | 1703U, // SL2_return |
2768 | 0 | 1694U, // SL2_return_f |
2769 | 0 | 1774U, // SL2_return_fnew |
2770 | 0 | 1718U, // SL2_return_t |
2771 | 0 | 1805U, // SL2_return_tnew |
2772 | 0 | 725715408U, // SS1_storeb_io |
2773 | 0 | 725715986U, // SS1_storew_io |
2774 | 0 | 297148U, // SS2_allocframe |
2775 | 0 | 1950452176U, // SS2_storebi0 |
2776 | 0 | 1967229392U, // SS2_storebi1 |
2777 | 0 | 51185896U, // SS2_stored_sp |
2778 | 0 | 725715540U, // SS2_storeh_io |
2779 | 0 | 51185907U, // SS2_storew_sp |
2780 | 0 | 1950452754U, // SS2_storewi0 |
2781 | 0 | 1967229970U, // SS2_storewi1 |
2782 | 0 | 188712986U, // TFRI64_V2_ext |
2783 | 0 | 50448410U, // TFRI64_V4 |
2784 | 0 | 10373146U, // V6_extractw |
2785 | 0 | 10389530U, // V6_lvsplatb |
2786 | 0 | 10405914U, // V6_lvsplath |
2787 | 0 | 10422298U, // V6_lvsplatw |
2788 | 0 | 490686490U, // V6_pred_and |
2789 | 0 | 1061111834U, // V6_pred_and_n |
2790 | 0 | 51226U, // V6_pred_not |
2791 | 0 | 490965018U, // V6_pred_or |
2792 | 0 | 1061390362U, // V6_pred_or_n |
2793 | 0 | 10438682U, // V6_pred_scalar2 |
2794 | 0 | 10455066U, // V6_pred_scalar2v2 |
2795 | 0 | 4851738U, // V6_pred_xor |
2796 | 0 | 765446170U, // V6_shuffeqh |
2797 | 0 | 1990199322U, // V6_shuffeqw |
2798 | 0 | 1997768730U, // V6_v6mpyhubs10 |
2799 | 0 | 2023770138U, // V6_v6mpyhubs10_vxx |
2800 | 0 | 1997768730U, // V6_v6mpyvubs10 |
2801 | 0 | 2040547354U, // V6_v6mpyvubs10_vxx |
2802 | 0 | 705808410U, // V6_vL32Ub_ai |
2803 | 0 | 1259456538U, // V6_vL32Ub_pi |
2804 | 0 | 1242679322U, // V6_vL32Ub_ppu |
2805 | 0 | 705759258U, // V6_vL32b_ai |
2806 | 0 | 715163674U, // V6_vL32b_cur_ai |
2807 | 0 | 335614067U, // V6_vL32b_cur_npred_ai |
2808 | 0 | 335618163U, // V6_vL32b_cur_npred_pi |
2809 | 0 | 335618163U, // V6_vL32b_cur_npred_ppu |
2810 | 0 | 1268811802U, // V6_vL32b_cur_pi |
2811 | 0 | 1252034586U, // V6_vL32b_cur_ppu |
2812 | 0 | 335614246U, // V6_vL32b_cur_pred_ai |
2813 | 0 | 335618342U, // V6_vL32b_cur_pred_pi |
2814 | 0 | 335618342U, // V6_vL32b_cur_pred_ppu |
2815 | 0 | 352391283U, // V6_vL32b_npred_ai |
2816 | 0 | 352395379U, // V6_vL32b_npred_pi |
2817 | 0 | 352395379U, // V6_vL32b_npred_ppu |
2818 | 0 | 705759258U, // V6_vL32b_nt_ai |
2819 | 0 | 715163674U, // V6_vL32b_nt_cur_ai |
2820 | 0 | 335614067U, // V6_vL32b_nt_cur_npred_ai |
2821 | 0 | 335618163U, // V6_vL32b_nt_cur_npred_pi |
2822 | 0 | 335618163U, // V6_vL32b_nt_cur_npred_ppu |
2823 | 0 | 1268811802U, // V6_vL32b_nt_cur_pi |
2824 | 0 | 1252034586U, // V6_vL32b_nt_cur_ppu |
2825 | 0 | 335614246U, // V6_vL32b_nt_cur_pred_ai |
2826 | 0 | 335618342U, // V6_vL32b_nt_cur_pred_pi |
2827 | 0 | 335618342U, // V6_vL32b_nt_cur_pred_ppu |
2828 | 0 | 352391283U, // V6_vL32b_nt_npred_ai |
2829 | 0 | 352395379U, // V6_vL32b_nt_npred_pi |
2830 | 0 | 352395379U, // V6_vL32b_nt_npred_ppu |
2831 | 0 | 1259407386U, // V6_vL32b_nt_pi |
2832 | 0 | 1242630170U, // V6_vL32b_nt_ppu |
2833 | 0 | 352391462U, // V6_vL32b_nt_pred_ai |
2834 | 0 | 352395558U, // V6_vL32b_nt_pred_pi |
2835 | 0 | 352395558U, // V6_vL32b_nt_pred_ppu |
2836 | 0 | 715180058U, // V6_vL32b_nt_tmp_ai |
2837 | 0 | 385945715U, // V6_vL32b_nt_tmp_npred_ai |
2838 | 0 | 385949811U, // V6_vL32b_nt_tmp_npred_pi |
2839 | 0 | 385949811U, // V6_vL32b_nt_tmp_npred_ppu |
2840 | 0 | 1268828186U, // V6_vL32b_nt_tmp_pi |
2841 | 0 | 1252050970U, // V6_vL32b_nt_tmp_ppu |
2842 | 0 | 385945894U, // V6_vL32b_nt_tmp_pred_ai |
2843 | 0 | 385949990U, // V6_vL32b_nt_tmp_pred_pi |
2844 | 0 | 385949990U, // V6_vL32b_nt_tmp_pred_ppu |
2845 | 0 | 1259407386U, // V6_vL32b_pi |
2846 | 0 | 1242630170U, // V6_vL32b_ppu |
2847 | 0 | 352391462U, // V6_vL32b_pred_ai |
2848 | 0 | 352395558U, // V6_vL32b_pred_pi |
2849 | 0 | 352395558U, // V6_vL32b_pred_ppu |
2850 | 0 | 715180058U, // V6_vL32b_tmp_ai |
2851 | 0 | 385945715U, // V6_vL32b_tmp_npred_ai |
2852 | 0 | 385949811U, // V6_vL32b_tmp_npred_pi |
2853 | 0 | 385949811U, // V6_vL32b_tmp_npred_ppu |
2854 | 0 | 1268828186U, // V6_vL32b_tmp_pi |
2855 | 0 | 1252050970U, // V6_vL32b_tmp_ppu |
2856 | 0 | 385945894U, // V6_vL32b_tmp_pred_ai |
2857 | 0 | 385949990U, // V6_vL32b_tmp_pred_pi |
2858 | 0 | 385949990U, // V6_vL32b_tmp_pred_ppu |
2859 | 0 | 725715872U, // V6_vS32Ub_ai |
2860 | 0 | 1230963U, // V6_vS32Ub_npred_ai |
2861 | 0 | 1779617907U, // V6_vS32Ub_npred_pi |
2862 | 0 | 1779617907U, // V6_vS32Ub_npred_ppu |
2863 | 0 | 730778528U, // V6_vS32Ub_pi |
2864 | 0 | 730762144U, // V6_vS32Ub_ppu |
2865 | 0 | 1231142U, // V6_vS32Ub_pred_ai |
2866 | 0 | 1779618086U, // V6_vS32Ub_pred_pi |
2867 | 0 | 1779618086U, // V6_vS32Ub_pred_ppu |
2868 | 0 | 725715604U, // V6_vS32b_ai |
2869 | 0 | 725715604U, // V6_vS32b_new_ai |
2870 | 0 | 1214579U, // V6_vS32b_new_npred_ai |
2871 | 0 | 1779601523U, // V6_vS32b_new_npred_pi |
2872 | 0 | 1779601523U, // V6_vS32b_new_npred_ppu |
2873 | 0 | 730778260U, // V6_vS32b_new_pi |
2874 | 0 | 730761876U, // V6_vS32b_new_ppu |
2875 | 0 | 1214758U, // V6_vS32b_new_pred_ai |
2876 | 0 | 1779601702U, // V6_vS32b_new_pred_pi |
2877 | 0 | 1779601702U, // V6_vS32b_new_pred_ppu |
2878 | 0 | 1214579U, // V6_vS32b_npred_ai |
2879 | 0 | 1779601523U, // V6_vS32b_npred_pi |
2880 | 0 | 1779601523U, // V6_vS32b_npred_ppu |
2881 | 0 | 1214579U, // V6_vS32b_nqpred_ai |
2882 | 0 | 1779601523U, // V6_vS32b_nqpred_pi |
2883 | 0 | 1779601523U, // V6_vS32b_nqpred_ppu |
2884 | 0 | 2051115668U, // V6_vS32b_nt_ai |
2885 | 0 | 2051115668U, // V6_vS32b_nt_new_ai |
2886 | 0 | 1214579U, // V6_vS32b_nt_new_npred_ai |
2887 | 0 | 1779601523U, // V6_vS32b_nt_new_npred_pi |
2888 | 0 | 1779601523U, // V6_vS32b_nt_new_npred_ppu |
2889 | 0 | 2056178324U, // V6_vS32b_nt_new_pi |
2890 | 0 | 2056161940U, // V6_vS32b_nt_new_ppu |
2891 | 0 | 1214758U, // V6_vS32b_nt_new_pred_ai |
2892 | 0 | 1779601702U, // V6_vS32b_nt_new_pred_pi |
2893 | 0 | 1779601702U, // V6_vS32b_nt_new_pred_ppu |
2894 | 0 | 1214579U, // V6_vS32b_nt_npred_ai |
2895 | 0 | 1779601523U, // V6_vS32b_nt_npred_pi |
2896 | 0 | 1779601523U, // V6_vS32b_nt_npred_ppu |
2897 | 0 | 1214579U, // V6_vS32b_nt_nqpred_ai |
2898 | 0 | 1779601523U, // V6_vS32b_nt_nqpred_pi |
2899 | 0 | 1779601523U, // V6_vS32b_nt_nqpred_ppu |
2900 | 0 | 2056178324U, // V6_vS32b_nt_pi |
2901 | 0 | 2056161940U, // V6_vS32b_nt_ppu |
2902 | 0 | 1214758U, // V6_vS32b_nt_pred_ai |
2903 | 0 | 1779601702U, // V6_vS32b_nt_pred_pi |
2904 | 0 | 1779601702U, // V6_vS32b_nt_pred_ppu |
2905 | 0 | 1214758U, // V6_vS32b_nt_qpred_ai |
2906 | 0 | 1779601702U, // V6_vS32b_nt_qpred_pi |
2907 | 0 | 1779601702U, // V6_vS32b_nt_qpred_ppu |
2908 | 0 | 730778260U, // V6_vS32b_pi |
2909 | 0 | 730761876U, // V6_vS32b_ppu |
2910 | 0 | 1214758U, // V6_vS32b_pred_ai |
2911 | 0 | 1779601702U, // V6_vS32b_pred_pi |
2912 | 0 | 1779601702U, // V6_vS32b_pred_ppu |
2913 | 0 | 1214758U, // V6_vS32b_qpred_ai |
2914 | 0 | 1779601702U, // V6_vS32b_qpred_pi |
2915 | 0 | 1779601702U, // V6_vS32b_qpred_ppu |
2916 | 0 | 2067892884U, // V6_vS32b_srls_ai |
2917 | 0 | 2072955540U, // V6_vS32b_srls_pi |
2918 | 0 | 2072939156U, // V6_vS32b_srls_ppu |
2919 | 0 | 10553370U, // V6_vabs_hf |
2920 | 0 | 10569754U, // V6_vabs_sf |
2921 | 0 | 2090960922U, // V6_vabsb |
2922 | 0 | 2107738138U, // V6_vabsb_sat |
2923 | 0 | 765577242U, // V6_vabsdiffh |
2924 | 0 | 10618906U, // V6_vabsdiffub |
2925 | 0 | 312592410U, // V6_vabsdiffuh |
2926 | 0 | 10635290U, // V6_vabsdiffw |
2927 | 0 | 2124580890U, // V6_vabsh |
2928 | 0 | 2141358106U, // V6_vabsh_sat |
2929 | 0 | 2158151706U, // V6_vabsw |
2930 | 0 | 2174928922U, // V6_vabsw_sat |
2931 | 0 | 2191722522U, // V6_vadd_hf |
2932 | 0 | 10700826U, // V6_vadd_hf_hf |
2933 | 0 | 2208499738U, // V6_vadd_qf16 |
2934 | 0 | 2208499738U, // V6_vadd_qf16_mix |
2935 | 0 | 2225309722U, // V6_vadd_qf32 |
2936 | 0 | 2225309722U, // V6_vadd_qf32_mix |
2937 | 0 | 2242086938U, // V6_vadd_sf |
2938 | 0 | 2258880538U, // V6_vadd_sf_bf |
2939 | 0 | 2191771674U, // V6_vadd_sf_hf |
2940 | 0 | 2242103322U, // V6_vadd_sf_sf |
2941 | 0 | 2091124762U, // V6_vaddb |
2942 | 0 | 2091124762U, // V6_vaddb_dv |
2943 | 0 | 436277363U, // V6_vaddbnq |
2944 | 0 | 436277542U, // V6_vaddbq |
2945 | 0 | 2107901978U, // V6_vaddbsat |
2946 | 0 | 2107901978U, // V6_vaddbsat_dv |
2947 | 0 | 77875226U, // V6_vaddcarry |
2948 | 0 | 2275706906U, // V6_vaddcarryo |
2949 | 0 | 10766362U, // V6_vaddcarrysat |
2950 | 0 | 10799130U, // V6_vaddclbh |
2951 | 0 | 10815514U, // V6_vaddclbw |
2952 | 0 | 765806618U, // V6_vaddh |
2953 | 0 | 765806618U, // V6_vaddh_dv |
2954 | 0 | 453054579U, // V6_vaddhnq |
2955 | 0 | 453054758U, // V6_vaddhq |
2956 | 0 | 765806618U, // V6_vaddhsat |
2957 | 0 | 765806618U, // V6_vaddhsat_dv |
2958 | 0 | 10766362U, // V6_vaddhw |
2959 | 0 | 765823002U, // V6_vaddhw_acc |
2960 | 0 | 296044570U, // V6_vaddubh |
2961 | 0 | 10864666U, // V6_vaddubh_acc |
2962 | 0 | 2292582426U, // V6_vaddubsat |
2963 | 0 | 2292582426U, // V6_vaddubsat_dv |
2964 | 0 | 2108033050U, // V6_vaddububb_sat |
2965 | 0 | 10897434U, // V6_vadduhsat |
2966 | 0 | 10897434U, // V6_vadduhsat_dv |
2967 | 0 | 10766362U, // V6_vadduhw |
2968 | 0 | 312838170U, // V6_vadduhw_acc |
2969 | 0 | 10913818U, // V6_vadduwsat |
2970 | 0 | 10913818U, // V6_vadduwsat_dv |
2971 | 0 | 10766362U, // V6_vaddw |
2972 | 0 | 10766362U, // V6_vaddw_dv |
2973 | 0 | 469831795U, // V6_vaddwnq |
2974 | 0 | 469831974U, // V6_vaddwq |
2975 | 0 | 10766362U, // V6_vaddwsat |
2976 | 0 | 10766362U, // V6_vaddwsat_dv |
2977 | 0 | 497469466U, // V6_valignb |
2978 | 0 | 195479578U, // V6_valignbi |
2979 | 0 | 10946586U, // V6_vand |
2980 | 0 | 10962970U, // V6_vandnqrt |
2981 | 0 | 10979354U, // V6_vandnqrt_acc |
2982 | 0 | 10946586U, // V6_vandqrt |
2983 | 0 | 10995738U, // V6_vandqrt_acc |
2984 | 0 | 10962970U, // V6_vandvnqv |
2985 | 0 | 10946586U, // V6_vandvqv |
2986 | 0 | 10946586U, // V6_vandvrt |
2987 | 0 | 10995738U, // V6_vandvrt_acc |
2988 | 0 | 27789338U, // V6_vaslh |
2989 | 0 | 11028506U, // V6_vaslh_acc |
2990 | 0 | 2124941338U, // V6_vaslhv |
2991 | 0 | 27822106U, // V6_vaslw |
2992 | 0 | 11061274U, // V6_vaslw_acc |
2993 | 0 | 2158528538U, // V6_vaslwv |
2994 | 0 | 11077658U, // V6_vasr_into |
2995 | 0 | 766068762U, // V6_vasrh |
2996 | 0 | 11110426U, // V6_vasrh_acc |
2997 | 0 | 279562266U, // V6_vasrhbrndsat |
2998 | 0 | 430557210U, // V6_vasrhbsat |
2999 | 0 | 766117914U, // V6_vasrhubrndsat |
3000 | 0 | 766117914U, // V6_vasrhubsat |
3001 | 0 | 766068762U, // V6_vasrhv |
3002 | 0 | 313133082U, // V6_vasruhubrndsat |
3003 | 0 | 313133082U, // V6_vasruhubsat |
3004 | 0 | 329926682U, // V6_vasruwuhrndsat |
3005 | 0 | 329926682U, // V6_vasruwuhsat |
3006 | 0 | 313133082U, // V6_vasrvuhubrndsat |
3007 | 0 | 313133082U, // V6_vasrvuhubsat |
3008 | 0 | 1990871066U, // V6_vasrvwuhrndsat |
3009 | 0 | 1990871066U, // V6_vasrvwuhsat |
3010 | 0 | 27953178U, // V6_vasrw |
3011 | 0 | 11192346U, // V6_vasrw_acc |
3012 | 0 | 1990805530U, // V6_vasrwh |
3013 | 0 | 1990805530U, // V6_vasrwhrndsat |
3014 | 0 | 1990805530U, // V6_vasrwhsat |
3015 | 0 | 1990871066U, // V6_vasrwuhrndsat |
3016 | 0 | 1990871066U, // V6_vasrwuhsat |
3017 | 0 | 2158659610U, // V6_vasrwv |
3018 | 0 | 50432026U, // V6_vassign |
3019 | 0 | 11208730U, // V6_vassign_fp |
3020 | 0 | 11225114U, // V6_vassign_tmp |
3021 | 0 | 2091616282U, // V6_vavgb |
3022 | 0 | 2309720090U, // V6_vavgbrnd |
3023 | 0 | 2125187098U, // V6_vavgh |
3024 | 0 | 2326513690U, // V6_vavghrnd |
3025 | 0 | 598476826U, // V6_vavgub |
3026 | 0 | 2343307290U, // V6_vavgubrnd |
3027 | 0 | 2360100890U, // V6_vavguh |
3028 | 0 | 2376878106U, // V6_vavguhrnd |
3029 | 0 | 2393671706U, // V6_vavguw |
3030 | 0 | 2410448922U, // V6_vavguwrnd |
3031 | 0 | 2158807066U, // V6_vavgw |
3032 | 0 | 2427242522U, // V6_vavgwrnd |
3033 | 0 | 2432766246U, // V6_vccombine |
3034 | 0 | 11339802U, // V6_vcl0h |
3035 | 0 | 11356186U, // V6_vcl0w |
3036 | 0 | 33624358U, // V6_vcmov |
3037 | 0 | 11372570U, // V6_vcombine |
3038 | 0 | 11388954U, // V6_vcombine_tmp |
3039 | 0 | 11405338U, // V6_vconv_h_hf |
3040 | 0 | 263079962U, // V6_vconv_hf_h |
3041 | 0 | 2460895258U, // V6_vconv_hf_qf16 |
3042 | 0 | 2477672474U, // V6_vconv_hf_qf32 |
3043 | 0 | 2477688858U, // V6_vconv_sf_qf32 |
3044 | 0 | 2494466074U, // V6_vconv_sf_w |
3045 | 0 | 11454490U, // V6_vconv_w_sf |
3046 | 0 | 11470874U, // V6_vcvt_b_hf |
3047 | 0 | 11487258U, // V6_vcvt_bf_sf |
3048 | 0 | 11503642U, // V6_vcvt_h_hf |
3049 | 0 | 2091894810U, // V6_vcvt_hf_b |
3050 | 0 | 2125449242U, // V6_vcvt_hf_h |
3051 | 0 | 2242889754U, // V6_vcvt_hf_sf |
3052 | 0 | 598722586U, // V6_vcvt_hf_ub |
3053 | 0 | 2360330266U, // V6_vcvt_hf_uh |
3054 | 0 | 11536410U, // V6_vcvt_sf_hf |
3055 | 0 | 11552794U, // V6_vcvt_ub_hf |
3056 | 0 | 11569178U, // V6_vcvt_uh_hf |
3057 | 0 | 3623543U, // V6_vdeal |
3058 | 0 | 11585562U, // V6_vdealb |
3059 | 0 | 11601946U, // V6_vdealb4w |
3060 | 0 | 11618330U, // V6_vdealh |
3061 | 0 | 11634714U, // V6_vdealvdd |
3062 | 0 | 11651098U, // V6_vdelta |
3063 | 0 | 11667482U, // V6_vdmpy_sf_hf |
3064 | 0 | 11683866U, // V6_vdmpy_sf_hf_acc |
3065 | 0 | 11700250U, // V6_vdmpybus |
3066 | 0 | 11716634U, // V6_vdmpybus_acc |
3067 | 0 | 11700250U, // V6_vdmpybus_dv |
3068 | 0 | 11716634U, // V6_vdmpybus_dv_acc |
3069 | 0 | 2092107802U, // V6_vdmpyhb |
3070 | 0 | 2092124186U, // V6_vdmpyhb_acc |
3071 | 0 | 2092107802U, // V6_vdmpyhb_dv |
3072 | 0 | 2092124186U, // V6_vdmpyhb_dv_acc |
3073 | 0 | 2142439450U, // V6_vdmpyhisat |
3074 | 0 | 2142455834U, // V6_vdmpyhisat_acc |
3075 | 0 | 2142439450U, // V6_vdmpyhsat |
3076 | 0 | 2142455834U, // V6_vdmpyhsat_acc |
3077 | 0 | 2511538202U, // V6_vdmpyhsuisat |
3078 | 0 | 2511554586U, // V6_vdmpyhsuisat_acc |
3079 | 0 | 2528315418U, // V6_vdmpyhsusat |
3080 | 0 | 2528331802U, // V6_vdmpyhsusat_acc |
3081 | 0 | 2142439450U, // V6_vdmpyhvsat |
3082 | 0 | 2142455834U, // V6_vdmpyhvsat_acc |
3083 | 0 | 11765786U, // V6_vdsaduh |
3084 | 0 | 11782170U, // V6_vdsaduh_acc |
3085 | 0 | 571475994U, // V6_veqb |
3086 | 0 | 571492378U, // V6_veqb_and |
3087 | 0 | 571508762U, // V6_veqb_or |
3088 | 0 | 571525146U, // V6_veqb_xor |
3089 | 0 | 756025370U, // V6_veqh |
3090 | 0 | 756041754U, // V6_veqh_and |
3091 | 0 | 756058138U, // V6_veqh_or |
3092 | 0 | 756074522U, // V6_veqh_xor |
3093 | 0 | 1980762138U, // V6_veqw |
3094 | 0 | 1980778522U, // V6_veqw_and |
3095 | 0 | 1980794906U, // V6_veqw_or |
3096 | 0 | 1980811290U, // V6_veqw_xor |
3097 | 0 | 11798554U, // V6_vfmax_hf |
3098 | 0 | 11814938U, // V6_vfmax_sf |
3099 | 0 | 11831322U, // V6_vfmin_hf |
3100 | 0 | 11847706U, // V6_vfmin_sf |
3101 | 0 | 11864090U, // V6_vfneg_hf |
3102 | 0 | 11880474U, // V6_vfneg_sf |
3103 | 0 | 3623662U, // V6_vgathermh |
3104 | 0 | 2545256742U, // V6_vgathermhq |
3105 | 0 | 3623662U, // V6_vgathermhw |
3106 | 0 | 2562033958U, // V6_vgathermhwq |
3107 | 0 | 3623680U, // V6_vgathermw |
3108 | 0 | 11913510U, // V6_vgathermwq |
3109 | 0 | 582354970U, // V6_vgtb |
3110 | 0 | 582371354U, // V6_vgtb_and |
3111 | 0 | 582387738U, // V6_vgtb_or |
3112 | 0 | 582404122U, // V6_vgtb_xor |
3113 | 0 | 2260076570U, // V6_vgtbf |
3114 | 0 | 2260092954U, // V6_vgtbf_and |
3115 | 0 | 2260109338U, // V6_vgtbf_or |
3116 | 0 | 2260125722U, // V6_vgtbf_xor |
3117 | 0 | 766904346U, // V6_vgth |
3118 | 0 | 766920730U, // V6_vgth_and |
3119 | 0 | 766937114U, // V6_vgth_or |
3120 | 0 | 766953498U, // V6_vgth_xor |
3121 | 0 | 2192967706U, // V6_vgthf |
3122 | 0 | 2192984090U, // V6_vgthf_and |
3123 | 0 | 2193000474U, // V6_vgthf_or |
3124 | 0 | 2193016858U, // V6_vgthf_xor |
3125 | 0 | 2243299354U, // V6_vgtsf |
3126 | 0 | 2243315738U, // V6_vgtsf_and |
3127 | 0 | 2243332122U, // V6_vgtsf_or |
3128 | 0 | 2243348506U, // V6_vgtsf_xor |
3129 | 0 | 297142298U, // V6_vgtub |
3130 | 0 | 297158682U, // V6_vgtub_and |
3131 | 0 | 297175066U, // V6_vgtub_or |
3132 | 0 | 297191450U, // V6_vgtub_xor |
3133 | 0 | 313919514U, // V6_vgtuh |
3134 | 0 | 313935898U, // V6_vgtuh_and |
3135 | 0 | 313952282U, // V6_vgtuh_or |
3136 | 0 | 313968666U, // V6_vgtuh_xor |
3137 | 0 | 330696730U, // V6_vgtuw |
3138 | 0 | 330713114U, // V6_vgtuw_and |
3139 | 0 | 330729498U, // V6_vgtuw_or |
3140 | 0 | 330745882U, // V6_vgtuw_xor |
3141 | 0 | 1991641114U, // V6_vgtw |
3142 | 0 | 1991657498U, // V6_vgtw_and |
3143 | 0 | 1991673882U, // V6_vgtw_or |
3144 | 0 | 1991690266U, // V6_vgtw_xor |
3145 | 0 | 1841U, // V6_vhist |
3146 | 0 | 297881U, // V6_vhistq |
3147 | 0 | 11995162U, // V6_vinsertwr |
3148 | 0 | 498550810U, // V6_vlalignb |
3149 | 0 | 196560922U, // V6_vlalignbi |
3150 | 0 | 12027930U, // V6_vlsrb |
3151 | 0 | 12044314U, // V6_vlsrh |
3152 | 0 | 12060698U, // V6_vlsrhv |
3153 | 0 | 12077082U, // V6_vlsrw |
3154 | 0 | 12093466U, // V6_vlsrwv |
3155 | 0 | 12109850U, // V6_vlut4 |
3156 | 0 | 582551578U, // V6_vlutvvb |
3157 | 0 | 582551578U, // V6_vlutvvb_nm |
3158 | 0 | 582567962U, // V6_vlutvvb_oracc |
3159 | 0 | 2008631322U, // V6_vlutvvb_oracci |
3160 | 0 | 2008614938U, // V6_vlutvvbi |
3161 | 0 | 767133722U, // V6_vlutvwh |
3162 | 0 | 767133722U, // V6_vlutvwh_nm |
3163 | 0 | 767150106U, // V6_vlutvwh_oracc |
3164 | 0 | 2579089434U, // V6_vlutvwh_oracci |
3165 | 0 | 2579073050U, // V6_vlutvwhi |
3166 | 0 | 12191770U, // V6_vmax_bf |
3167 | 0 | 12208154U, // V6_vmax_hf |
3168 | 0 | 12224538U, // V6_vmax_sf |
3169 | 0 | 12240922U, // V6_vmaxb |
3170 | 0 | 12257306U, // V6_vmaxh |
3171 | 0 | 12273690U, // V6_vmaxub |
3172 | 0 | 12290074U, // V6_vmaxuh |
3173 | 0 | 12306458U, // V6_vmaxw |
3174 | 0 | 12322842U, // V6_vmin_bf |
3175 | 0 | 12339226U, // V6_vmin_hf |
3176 | 0 | 12355610U, // V6_vmin_sf |
3177 | 0 | 12371994U, // V6_vminb |
3178 | 0 | 12388378U, // V6_vminh |
3179 | 0 | 12404762U, // V6_vminub |
3180 | 0 | 12421146U, // V6_vminuh |
3181 | 0 | 12437530U, // V6_vminw |
3182 | 0 | 297666586U, // V6_vmpabus |
3183 | 0 | 2092845082U, // V6_vmpabus_acc |
3184 | 0 | 297666586U, // V6_vmpabusv |
3185 | 0 | 297666586U, // V6_vmpabuu |
3186 | 0 | 599672858U, // V6_vmpabuu_acc |
3187 | 0 | 297666586U, // V6_vmpabuuv |
3188 | 0 | 767461402U, // V6_vmpahb |
3189 | 0 | 767477786U, // V6_vmpahb_acc |
3190 | 0 | 767428634U, // V6_vmpahhsat |
3191 | 0 | 314476570U, // V6_vmpauhb |
3192 | 0 | 314492954U, // V6_vmpauhb_acc |
3193 | 0 | 767428634U, // V6_vmpauhuhsat |
3194 | 0 | 12519450U, // V6_vmpsuhuhsat |
3195 | 0 | 12535834U, // V6_vmpy_hf_hf |
3196 | 0 | 12552218U, // V6_vmpy_hf_hf_acc |
3197 | 0 | 2210383898U, // V6_vmpy_qf16 |
3198 | 0 | 2193606682U, // V6_vmpy_qf16_hf |
3199 | 0 | 2210383898U, // V6_vmpy_qf16_mix_hf |
3200 | 0 | 2227177498U, // V6_vmpy_qf32 |
3201 | 0 | 2193623066U, // V6_vmpy_qf32_hf |
3202 | 0 | 2210400282U, // V6_vmpy_qf32_mix_hf |
3203 | 0 | 2210400282U, // V6_vmpy_qf32_qf16 |
3204 | 0 | 2243954714U, // V6_vmpy_qf32_sf |
3205 | 0 | 2260748314U, // V6_vmpy_sf_bf |
3206 | 0 | 2260764698U, // V6_vmpy_sf_bf_acc |
3207 | 0 | 2193639450U, // V6_vmpy_sf_hf |
3208 | 0 | 2193655834U, // V6_vmpy_sf_hf_acc |
3209 | 0 | 2243971098U, // V6_vmpy_sf_sf |
3210 | 0 | 297846810U, // V6_vmpybus |
3211 | 0 | 297863194U, // V6_vmpybus_acc |
3212 | 0 | 297846810U, // V6_vmpybusv |
3213 | 0 | 297863194U, // V6_vmpybusv_acc |
3214 | 0 | 583059482U, // V6_vmpybv |
3215 | 0 | 583075866U, // V6_vmpybv_acc |
3216 | 0 | 12666906U, // V6_vmpyewuh |
3217 | 0 | 12683290U, // V6_vmpyewuh_64 |
3218 | 0 | 2126628890U, // V6_vmpyh |
3219 | 0 | 2126645274U, // V6_vmpyh_acc |
3220 | 0 | 2143422490U, // V6_vmpyhsat_acc |
3221 | 0 | 767608858U, // V6_vmpyhsrs |
3222 | 0 | 767608858U, // V6_vmpyhss |
3223 | 0 | 2361509914U, // V6_vmpyhus |
3224 | 0 | 2361526298U, // V6_vmpyhus_acc |
3225 | 0 | 2126628890U, // V6_vmpyhv |
3226 | 0 | 2126645274U, // V6_vmpyhv_acc |
3227 | 0 | 767608858U, // V6_vmpyhvsrs |
3228 | 0 | 12732442U, // V6_vmpyieoh |
3229 | 0 | 2126678042U, // V6_vmpyiewh_acc |
3230 | 0 | 12765210U, // V6_vmpyiewuh |
3231 | 0 | 2361559066U, // V6_vmpyiewuh_acc |
3232 | 0 | 2126710810U, // V6_vmpyih |
3233 | 0 | 2126727194U, // V6_vmpyih_acc |
3234 | 0 | 2093156378U, // V6_vmpyihb |
3235 | 0 | 2093172762U, // V6_vmpyihb_acc |
3236 | 0 | 12814362U, // V6_vmpyiowh |
3237 | 0 | 2093205530U, // V6_vmpyiwb |
3238 | 0 | 2093221914U, // V6_vmpyiwb_acc |
3239 | 0 | 2126759962U, // V6_vmpyiwh |
3240 | 0 | 2126776346U, // V6_vmpyiwh_acc |
3241 | 0 | 600033306U, // V6_vmpyiwub |
3242 | 0 | 600049690U, // V6_vmpyiwub_acc |
3243 | 0 | 2596554778U, // V6_vmpyowh |
3244 | 0 | 12879898U, // V6_vmpyowh_64_acc |
3245 | 0 | 2613331994U, // V6_vmpyowh_rnd |
3246 | 0 | 2630141978U, // V6_vmpyowh_rnd_sacc |
3247 | 0 | 2646919194U, // V6_vmpyowh_sacc |
3248 | 0 | 298125338U, // V6_vmpyub |
3249 | 0 | 12929050U, // V6_vmpyub_acc |
3250 | 0 | 298125338U, // V6_vmpyubv |
3251 | 0 | 12929050U, // V6_vmpyubv_acc |
3252 | 0 | 12945434U, // V6_vmpyuh |
3253 | 0 | 12961818U, // V6_vmpyuh_acc |
3254 | 0 | 12978202U, // V6_vmpyuhe |
3255 | 0 | 12994586U, // V6_vmpyuhe_acc |
3256 | 0 | 12945434U, // V6_vmpyuhv |
3257 | 0 | 12961818U, // V6_vmpyuhv_acc |
3258 | 0 | 314902554U, // V6_vmpyuhvs |
3259 | 0 | 5425178U, // V6_vmux |
3260 | 0 | 583436314U, // V6_vnavgb |
3261 | 0 | 13027354U, // V6_vnavgh |
3262 | 0 | 298223642U, // V6_vnavgub |
3263 | 0 | 13043738U, // V6_vnavgw |
3264 | 0 | 2432766067U, // V6_vnccombine |
3265 | 0 | 33624179U, // V6_vncmov |
3266 | 0 | 13060122U, // V6_vnormamth |
3267 | 0 | 13076506U, // V6_vnormamtw |
3268 | 0 | 13092890U, // V6_vnot |
3269 | 0 | 13109274U, // V6_vor |
3270 | 0 | 13125658U, // V6_vpackeb |
3271 | 0 | 13142042U, // V6_vpackeh |
3272 | 0 | 13158426U, // V6_vpackhb_sat |
3273 | 0 | 13174810U, // V6_vpackhub_sat |
3274 | 0 | 13191194U, // V6_vpackob |
3275 | 0 | 13207578U, // V6_vpackoh |
3276 | 0 | 13223962U, // V6_vpackwh_sat |
3277 | 0 | 13240346U, // V6_vpackwuh_sat |
3278 | 0 | 13256730U, // V6_vpopcounth |
3279 | 0 | 13273114U, // V6_vprefixqb |
3280 | 0 | 13289498U, // V6_vprefixqh |
3281 | 0 | 13305882U, // V6_vprefixqw |
3282 | 0 | 13322266U, // V6_vrdelta |
3283 | 0 | 573687834U, // V6_vrmpybub_rtt |
3284 | 0 | 573671450U, // V6_vrmpybub_rtt_acc |
3285 | 0 | 288475162U, // V6_vrmpybus |
3286 | 0 | 288458778U, // V6_vrmpybus_acc |
3287 | 0 | 288475162U, // V6_vrmpybusi |
3288 | 0 | 288458778U, // V6_vrmpybusi_acc |
3289 | 0 | 288475162U, // V6_vrmpybusv |
3290 | 0 | 288458778U, // V6_vrmpybusv_acc |
3291 | 0 | 573687834U, // V6_vrmpybv |
3292 | 0 | 573671450U, // V6_vrmpybv_acc |
3293 | 0 | 590596122U, // V6_vrmpyub |
3294 | 0 | 590579738U, // V6_vrmpyub_acc |
3295 | 0 | 590596122U, // V6_vrmpyub_rtt |
3296 | 0 | 590579738U, // V6_vrmpyub_rtt_acc |
3297 | 0 | 2654193690U, // V6_vrmpyubi |
3298 | 0 | 2654177306U, // V6_vrmpyubi_acc |
3299 | 0 | 590596122U, // V6_vrmpyubv |
3300 | 0 | 590579738U, // V6_vrmpyubv_acc |
3301 | 0 | 13338650U, // V6_vrmpyzbb_rt |
3302 | 0 | 80463898U, // V6_vrmpyzbb_rt_acc |
3303 | 0 | 80447514U, // V6_vrmpyzbb_rx |
3304 | 0 | 2680932378U, // V6_vrmpyzbb_rx_acc |
3305 | 0 | 13338650U, // V6_vrmpyzbub_rt |
3306 | 0 | 80463898U, // V6_vrmpyzbub_rt_acc |
3307 | 0 | 80447514U, // V6_vrmpyzbub_rx |
3308 | 0 | 2680932378U, // V6_vrmpyzbub_rx_acc |
3309 | 0 | 13371418U, // V6_vrmpyzcb_rt |
3310 | 0 | 80496666U, // V6_vrmpyzcb_rt_acc |
3311 | 0 | 80480282U, // V6_vrmpyzcb_rx |
3312 | 0 | 2680965146U, // V6_vrmpyzcb_rx_acc |
3313 | 0 | 13404186U, // V6_vrmpyzcbs_rt |
3314 | 0 | 80529434U, // V6_vrmpyzcbs_rt_acc |
3315 | 0 | 80513050U, // V6_vrmpyzcbs_rx |
3316 | 0 | 2680997914U, // V6_vrmpyzcbs_rx_acc |
3317 | 0 | 13436954U, // V6_vrmpyznb_rt |
3318 | 0 | 80562202U, // V6_vrmpyznb_rt_acc |
3319 | 0 | 80545818U, // V6_vrmpyznb_rx |
3320 | 0 | 2681030682U, // V6_vrmpyznb_rx_acc |
3321 | 0 | 13469722U, // V6_vror |
3322 | 0 | 13486106U, // V6_vrotr |
3323 | 0 | 13502490U, // V6_vroundhb |
3324 | 0 | 768493594U, // V6_vroundhub |
3325 | 0 | 315508762U, // V6_vrounduhub |
3326 | 0 | 332302362U, // V6_vrounduwuh |
3327 | 0 | 13551642U, // V6_vroundwh |
3328 | 0 | 1993246746U, // V6_vroundwuh |
3329 | 0 | 13568026U, // V6_vrsadubi |
3330 | 0 | 13584410U, // V6_vrsadubi_acc |
3331 | 0 | 13600794U, // V6_vsatdw |
3332 | 0 | 13617178U, // V6_vsathub |
3333 | 0 | 13633562U, // V6_vsatuwuh |
3334 | 0 | 13649946U, // V6_vsatwh |
3335 | 0 | 13666330U, // V6_vsb |
3336 | 0 | 3623698U, // V6_vscattermh |
3337 | 0 | 3623698U, // V6_vscattermh_add |
3338 | 0 | 2687994150U, // V6_vscattermhq |
3339 | 0 | 3623698U, // V6_vscattermhw |
3340 | 0 | 3623698U, // V6_vscattermhw_add |
3341 | 0 | 2704771366U, // V6_vscattermhwq |
3342 | 0 | 3623698U, // V6_vscattermw |
3343 | 0 | 3623698U, // V6_vscattermw_add |
3344 | 0 | 2721548582U, // V6_vscattermwq |
3345 | 0 | 13682714U, // V6_vsh |
3346 | 0 | 765462554U, // V6_vshufeh |
3347 | 0 | 3623476U, // V6_vshuff |
3348 | 0 | 13699098U, // V6_vshuffb |
3349 | 0 | 580896794U, // V6_vshuffeb |
3350 | 0 | 13715482U, // V6_vshuffh |
3351 | 0 | 13731866U, // V6_vshuffob |
3352 | 0 | 13748250U, // V6_vshuffvdd |
3353 | 0 | 13764634U, // V6_vshufoeb |
3354 | 0 | 13781018U, // V6_vshufoeh |
3355 | 0 | 13797402U, // V6_vshufoh |
3356 | 0 | 2194851866U, // V6_vsub_hf |
3357 | 0 | 13830170U, // V6_vsub_hf_hf |
3358 | 0 | 2211629082U, // V6_vsub_qf16 |
3359 | 0 | 2211629082U, // V6_vsub_qf16_mix |
3360 | 0 | 2228439066U, // V6_vsub_qf32 |
3361 | 0 | 2228439066U, // V6_vsub_qf32_mix |
3362 | 0 | 2245216282U, // V6_vsub_sf |
3363 | 0 | 2262009882U, // V6_vsub_sf_bf |
3364 | 0 | 2194901018U, // V6_vsub_sf_hf |
3365 | 0 | 2245232666U, // V6_vsub_sf_sf |
3366 | 0 | 2094254106U, // V6_vsubb |
3367 | 0 | 2094254106U, // V6_vsubb_dv |
3368 | 0 | 637603955U, // V6_vsubbnq |
3369 | 0 | 637604134U, // V6_vsubbq |
3370 | 0 | 2111031322U, // V6_vsubbsat |
3371 | 0 | 2111031322U, // V6_vsubbsat_dv |
3372 | 0 | 81004570U, // V6_vsubcarry |
3373 | 0 | 2745468954U, // V6_vsubcarryo |
3374 | 0 | 768886810U, // V6_vsubh |
3375 | 0 | 768886810U, // V6_vsubh_dv |
3376 | 0 | 654381171U, // V6_vsubhnq |
3377 | 0 | 654381350U, // V6_vsubhq |
3378 | 0 | 768886810U, // V6_vsubhsat |
3379 | 0 | 768886810U, // V6_vsubhsat_dv |
3380 | 0 | 13895706U, // V6_vsubhw |
3381 | 0 | 299124762U, // V6_vsububh |
3382 | 0 | 2295629850U, // V6_vsububsat |
3383 | 0 | 2295629850U, // V6_vsububsat_dv |
3384 | 0 | 2111080474U, // V6_vsubububb_sat |
3385 | 0 | 13944858U, // V6_vsubuhsat |
3386 | 0 | 13944858U, // V6_vsubuhsat_dv |
3387 | 0 | 13895706U, // V6_vsubuhw |
3388 | 0 | 13961242U, // V6_vsubuwsat |
3389 | 0 | 13961242U, // V6_vsubuwsat_dv |
3390 | 0 | 13895706U, // V6_vsubw |
3391 | 0 | 13895706U, // V6_vsubw_dv |
3392 | 0 | 671158387U, // V6_vsubwnq |
3393 | 0 | 671158566U, // V6_vsubwq |
3394 | 0 | 13895706U, // V6_vsubwsat |
3395 | 0 | 13895706U, // V6_vsubwsat_dv |
3396 | 0 | 13977626U, // V6_vswap |
3397 | 0 | 584419354U, // V6_vtmpyb |
3398 | 0 | 584435738U, // V6_vtmpyb_acc |
3399 | 0 | 299206682U, // V6_vtmpybus |
3400 | 0 | 299223066U, // V6_vtmpybus_acc |
3401 | 0 | 14026778U, // V6_vtmpyhb |
3402 | 0 | 14043162U, // V6_vtmpyhb_acc |
3403 | 0 | 14059546U, // V6_vunpackb |
3404 | 0 | 14075930U, // V6_vunpackh |
3405 | 0 | 14092314U, // V6_vunpackob |
3406 | 0 | 14108698U, // V6_vunpackoh |
3407 | 0 | 14125082U, // V6_vunpackub |
3408 | 0 | 14141466U, // V6_vunpackuh |
3409 | 0 | 1427U, // V6_vwhist128 |
3410 | 0 | 297122U, // V6_vwhist128m |
3411 | 0 | 297354U, // V6_vwhist128q |
3412 | 0 | 4278666U, // V6_vwhist128qm |
3413 | 0 | 1417U, // V6_vwhist256 |
3414 | 0 | 1753U, // V6_vwhist256_sat |
3415 | 0 | 297343U, // V6_vwhist256q |
3416 | 0 | 14158207U, // V6_vwhist256q_sat |
3417 | 0 | 14174234U, // V6_vxor |
3418 | 0 | 14190618U, // V6_vzb |
3419 | 0 | 14207002U, // V6_vzh |
3420 | 0 | 21072528U, // V6_zLd_ai |
3421 | 0 | 26135184U, // V6_zLd_pi |
3422 | 0 | 26118800U, // V6_zLd_ppu |
3423 | 0 | 4114726U, // V6_zLd_pred_ai |
3424 | 0 | 1782501670U, // V6_zLd_pred_pi |
3425 | 0 | 1782501670U, // V6_zLd_pred_ppu |
3426 | 0 | 14223386U, // V6_zextract |
3427 | 0 | 1745U, // Y2_barrier |
3428 | 0 | 1835U, // Y2_break |
3429 | 0 | 297430U, // Y2_ciad |
3430 | 0 | 14240429U, // Y2_crswap0 |
3431 | 0 | 297567U, // Y2_cswi |
3432 | 0 | 297376U, // Y2_dccleana |
3433 | 0 | 298030U, // Y2_dccleanidx |
3434 | 0 | 297411U, // Y2_dccleaninva |
3435 | 0 | 298087U, // Y2_dccleaninvidx |
3436 | 0 | 21072459U, // Y2_dcfetchbo |
3437 | 0 | 297395U, // Y2_dcinva |
3438 | 0 | 298052U, // Y2_dcinvidx |
3439 | 0 | 1671U, // Y2_dckill |
3440 | 0 | 14256154U, // Y2_dctagr |
3441 | 0 | 3623938U, // Y2_dctagw |
3442 | 0 | 297386U, // Y2_dczeroa |
3443 | 0 | 14272538U, // Y2_getimask |
3444 | 0 | 14288922U, // Y2_iassignr |
3445 | 0 | 298008U, // Y2_iassignw |
3446 | 0 | 14305306U, // Y2_icdatar |
3447 | 0 | 3623915U, // Y2_icdataw |
3448 | 0 | 297403U, // Y2_icinva |
3449 | 0 | 298062U, // Y2_icinvidx |
3450 | 0 | 1678U, // Y2_ickill |
3451 | 0 | 14321690U, // Y2_ictagr |
3452 | 0 | 3623946U, // Y2_ictagw |
3453 | 0 | 1559U, // Y2_isync |
3454 | 0 | 1590U, // Y2_k0lock |
3455 | 0 | 1612U, // Y2_k0unlock |
3456 | 0 | 298072U, // Y2_l2cleaninvidx |
3457 | 0 | 1664U, // Y2_l2kill |
3458 | 0 | 297507U, // Y2_resume |
3459 | 0 | 3623533U, // Y2_setimask |
3460 | 0 | 3623588U, // Y2_setprio |
3461 | 0 | 297874U, // Y2_start |
3462 | 0 | 297653U, // Y2_stop |
3463 | 0 | 297568U, // Y2_swi |
3464 | 0 | 1767U, // Y2_syncht |
3465 | 0 | 50432026U, // Y2_tfrscrr |
3466 | 0 | 50432026U, // Y2_tfrsrcr |
3467 | 0 | 1604U, // Y2_tlblock |
3468 | 0 | 14338074U, // Y2_tlbp |
3469 | 0 | 14354458U, // Y2_tlbr |
3470 | 0 | 1630U, // Y2_tlbunlock |
3471 | 0 | 3623924U, // Y2_tlbw |
3472 | 0 | 297815U, // Y2_wait |
3473 | 0 | 14371501U, // Y4_crswap1 |
3474 | 0 | 70732461U, // Y4_crswap10 |
3475 | 0 | 3623490U, // Y4_l2fetch |
3476 | 0 | 14387226U, // Y4_l2tagr |
3477 | 0 | 3623930U, // Y4_l2tagw |
3478 | 0 | 297562U, // Y4_nmi |
3479 | 0 | 297436U, // Y4_siad |
3480 | 0 | 50432026U, // Y4_tfrscpp |
3481 | 0 | 50432026U, // Y4_tfrspcp |
3482 | 0 | 297486U, // Y4_trace |
3483 | 0 | 14403610U, // Y5_ctlbw |
3484 | 0 | 298018U, // Y5_l2cleanidx |
3485 | 0 | 3623490U, // Y5_l2fetch |
3486 | 0 | 1685U, // Y5_l2gclean |
3487 | 0 | 1847U, // Y5_l2gcleaninv |
3488 | 0 | 1640U, // Y5_l2gunlock |
3489 | 0 | 298042U, // Y5_l2invidx |
3490 | 0 | 14419994U, // Y5_l2locka |
3491 | 0 | 297365U, // Y5_l2unlocka |
3492 | 0 | 297468U, // Y5_tlbasidi |
3493 | 0 | 14436378U, // Y5_tlboc |
3494 | 0 | 297532U, // Y6_diag |
3495 | 0 | 3623211U, // Y6_diag0 |
3496 | 0 | 3623263U, // Y6_diag1 |
3497 | 0 | 3623525U, // Y6_dmlink |
3498 | 0 | 14452762U, // Y6_dmpause |
3499 | 0 | 14469146U, // Y6_dmpoll |
3500 | 0 | 297505U, // Y6_dmresume |
3501 | 0 | 297872U, // Y6_dmstart |
3502 | 0 | 14485530U, // Y6_dmwait |
3503 | 0 | 297950U, // Y6_l2gcleaninvpa |
3504 | 0 | 297626U, // Y6_l2gcleanpa |
3505 | 0 | 2074U, // dep_A2_addsat |
3506 | 0 | 4540442U, // dep_A2_subsat |
3507 | 0 | 2760689690U, // dep_S2_packhl |
3508 | 0 | 1437U, // invalid_decode |
3509 | 0 | }; |
3510 | |
|
3511 | 0 | static const uint16_t OpInfo1[] = { |
3512 | 0 | 0U, // PHI |
3513 | 0 | 0U, // INLINEASM |
3514 | 0 | 0U, // INLINEASM_BR |
3515 | 0 | 0U, // CFI_INSTRUCTION |
3516 | 0 | 0U, // EH_LABEL |
3517 | 0 | 0U, // GC_LABEL |
3518 | 0 | 0U, // ANNOTATION_LABEL |
3519 | 0 | 0U, // KILL |
3520 | 0 | 0U, // EXTRACT_SUBREG |
3521 | 0 | 0U, // INSERT_SUBREG |
3522 | 0 | 0U, // IMPLICIT_DEF |
3523 | 0 | 0U, // SUBREG_TO_REG |
3524 | 0 | 0U, // COPY_TO_REGCLASS |
3525 | 0 | 0U, // DBG_VALUE |
3526 | 0 | 0U, // DBG_VALUE_LIST |
3527 | 0 | 0U, // DBG_INSTR_REF |
3528 | 0 | 0U, // DBG_PHI |
3529 | 0 | 0U, // DBG_LABEL |
3530 | 0 | 0U, // REG_SEQUENCE |
3531 | 0 | 0U, // COPY |
3532 | 0 | 0U, // BUNDLE |
3533 | 0 | 0U, // LIFETIME_START |
3534 | 0 | 0U, // LIFETIME_END |
3535 | 0 | 0U, // PSEUDO_PROBE |
3536 | 0 | 0U, // ARITH_FENCE |
3537 | 0 | 0U, // STACKMAP |
3538 | 0 | 0U, // FENTRY_CALL |
3539 | 0 | 0U, // PATCHPOINT |
3540 | 0 | 0U, // LOAD_STACK_GUARD |
3541 | 0 | 0U, // PREALLOCATED_SETUP |
3542 | 0 | 0U, // PREALLOCATED_ARG |
3543 | 0 | 0U, // STATEPOINT |
3544 | 0 | 0U, // LOCAL_ESCAPE |
3545 | 0 | 0U, // FAULTING_OP |
3546 | 0 | 0U, // PATCHABLE_OP |
3547 | 0 | 0U, // PATCHABLE_FUNCTION_ENTER |
3548 | 0 | 0U, // PATCHABLE_RET |
3549 | 0 | 0U, // PATCHABLE_FUNCTION_EXIT |
3550 | 0 | 0U, // PATCHABLE_TAIL_CALL |
3551 | 0 | 0U, // PATCHABLE_EVENT_CALL |
3552 | 0 | 0U, // PATCHABLE_TYPED_EVENT_CALL |
3553 | 0 | 0U, // ICALL_BRANCH_FUNNEL |
3554 | 0 | 0U, // MEMBARRIER |
3555 | 0 | 0U, // JUMP_TABLE_DEBUG_INFO |
3556 | 0 | 0U, // G_ASSERT_SEXT |
3557 | 0 | 0U, // G_ASSERT_ZEXT |
3558 | 0 | 0U, // G_ASSERT_ALIGN |
3559 | 0 | 0U, // G_ADD |
3560 | 0 | 0U, // G_SUB |
3561 | 0 | 0U, // G_MUL |
3562 | 0 | 0U, // G_SDIV |
3563 | 0 | 0U, // G_UDIV |
3564 | 0 | 0U, // G_SREM |
3565 | 0 | 0U, // G_UREM |
3566 | 0 | 0U, // G_SDIVREM |
3567 | 0 | 0U, // G_UDIVREM |
3568 | 0 | 0U, // G_AND |
3569 | 0 | 0U, // G_OR |
3570 | 0 | 0U, // G_XOR |
3571 | 0 | 0U, // G_IMPLICIT_DEF |
3572 | 0 | 0U, // G_PHI |
3573 | 0 | 0U, // G_FRAME_INDEX |
3574 | 0 | 0U, // G_GLOBAL_VALUE |
3575 | 0 | 0U, // G_CONSTANT_POOL |
3576 | 0 | 0U, // G_EXTRACT |
3577 | 0 | 0U, // G_UNMERGE_VALUES |
3578 | 0 | 0U, // G_INSERT |
3579 | 0 | 0U, // G_MERGE_VALUES |
3580 | 0 | 0U, // G_BUILD_VECTOR |
3581 | 0 | 0U, // G_BUILD_VECTOR_TRUNC |
3582 | 0 | 0U, // G_CONCAT_VECTORS |
3583 | 0 | 0U, // G_PTRTOINT |
3584 | 0 | 0U, // G_INTTOPTR |
3585 | 0 | 0U, // G_BITCAST |
3586 | 0 | 0U, // G_FREEZE |
3587 | 0 | 0U, // G_CONSTANT_FOLD_BARRIER |
3588 | 0 | 0U, // G_INTRINSIC_FPTRUNC_ROUND |
3589 | 0 | 0U, // G_INTRINSIC_TRUNC |
3590 | 0 | 0U, // G_INTRINSIC_ROUND |
3591 | 0 | 0U, // G_INTRINSIC_LRINT |
3592 | 0 | 0U, // G_INTRINSIC_ROUNDEVEN |
3593 | 0 | 0U, // G_READCYCLECOUNTER |
3594 | 0 | 0U, // G_LOAD |
3595 | 0 | 0U, // G_SEXTLOAD |
3596 | 0 | 0U, // G_ZEXTLOAD |
3597 | 0 | 0U, // G_INDEXED_LOAD |
3598 | 0 | 0U, // G_INDEXED_SEXTLOAD |
3599 | 0 | 0U, // G_INDEXED_ZEXTLOAD |
3600 | 0 | 0U, // G_STORE |
3601 | 0 | 0U, // G_INDEXED_STORE |
3602 | 0 | 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
3603 | 0 | 0U, // G_ATOMIC_CMPXCHG |
3604 | 0 | 0U, // G_ATOMICRMW_XCHG |
3605 | 0 | 0U, // G_ATOMICRMW_ADD |
3606 | 0 | 0U, // G_ATOMICRMW_SUB |
3607 | 0 | 0U, // G_ATOMICRMW_AND |
3608 | 0 | 0U, // G_ATOMICRMW_NAND |
3609 | 0 | 0U, // G_ATOMICRMW_OR |
3610 | 0 | 0U, // G_ATOMICRMW_XOR |
3611 | 0 | 0U, // G_ATOMICRMW_MAX |
3612 | 0 | 0U, // G_ATOMICRMW_MIN |
3613 | 0 | 0U, // G_ATOMICRMW_UMAX |
3614 | 0 | 0U, // G_ATOMICRMW_UMIN |
3615 | 0 | 0U, // G_ATOMICRMW_FADD |
3616 | 0 | 0U, // G_ATOMICRMW_FSUB |
3617 | 0 | 0U, // G_ATOMICRMW_FMAX |
3618 | 0 | 0U, // G_ATOMICRMW_FMIN |
3619 | 0 | 0U, // G_ATOMICRMW_UINC_WRAP |
3620 | 0 | 0U, // G_ATOMICRMW_UDEC_WRAP |
3621 | 0 | 0U, // G_FENCE |
3622 | 0 | 0U, // G_PREFETCH |
3623 | 0 | 0U, // G_BRCOND |
3624 | 0 | 0U, // G_BRINDIRECT |
3625 | 0 | 0U, // G_INVOKE_REGION_START |
3626 | 0 | 0U, // G_INTRINSIC |
3627 | 0 | 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
3628 | 0 | 0U, // G_INTRINSIC_CONVERGENT |
3629 | 0 | 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
3630 | 0 | 0U, // G_ANYEXT |
3631 | 0 | 0U, // G_TRUNC |
3632 | 0 | 0U, // G_CONSTANT |
3633 | 0 | 0U, // G_FCONSTANT |
3634 | 0 | 0U, // G_VASTART |
3635 | 0 | 0U, // G_VAARG |
3636 | 0 | 0U, // G_SEXT |
3637 | 0 | 0U, // G_SEXT_INREG |
3638 | 0 | 0U, // G_ZEXT |
3639 | 0 | 0U, // G_SHL |
3640 | 0 | 0U, // G_LSHR |
3641 | 0 | 0U, // G_ASHR |
3642 | 0 | 0U, // G_FSHL |
3643 | 0 | 0U, // G_FSHR |
3644 | 0 | 0U, // G_ROTR |
3645 | 0 | 0U, // G_ROTL |
3646 | 0 | 0U, // G_ICMP |
3647 | 0 | 0U, // G_FCMP |
3648 | 0 | 0U, // G_SELECT |
3649 | 0 | 0U, // G_UADDO |
3650 | 0 | 0U, // G_UADDE |
3651 | 0 | 0U, // G_USUBO |
3652 | 0 | 0U, // G_USUBE |
3653 | 0 | 0U, // G_SADDO |
3654 | 0 | 0U, // G_SADDE |
3655 | 0 | 0U, // G_SSUBO |
3656 | 0 | 0U, // G_SSUBE |
3657 | 0 | 0U, // G_UMULO |
3658 | 0 | 0U, // G_SMULO |
3659 | 0 | 0U, // G_UMULH |
3660 | 0 | 0U, // G_SMULH |
3661 | 0 | 0U, // G_UADDSAT |
3662 | 0 | 0U, // G_SADDSAT |
3663 | 0 | 0U, // G_USUBSAT |
3664 | 0 | 0U, // G_SSUBSAT |
3665 | 0 | 0U, // G_USHLSAT |
3666 | 0 | 0U, // G_SSHLSAT |
3667 | 0 | 0U, // G_SMULFIX |
3668 | 0 | 0U, // G_UMULFIX |
3669 | 0 | 0U, // G_SMULFIXSAT |
3670 | 0 | 0U, // G_UMULFIXSAT |
3671 | 0 | 0U, // G_SDIVFIX |
3672 | 0 | 0U, // G_UDIVFIX |
3673 | 0 | 0U, // G_SDIVFIXSAT |
3674 | 0 | 0U, // G_UDIVFIXSAT |
3675 | 0 | 0U, // G_FADD |
3676 | 0 | 0U, // G_FSUB |
3677 | 0 | 0U, // G_FMUL |
3678 | 0 | 0U, // G_FMA |
3679 | 0 | 0U, // G_FMAD |
3680 | 0 | 0U, // G_FDIV |
3681 | 0 | 0U, // G_FREM |
3682 | 0 | 0U, // G_FPOW |
3683 | 0 | 0U, // G_FPOWI |
3684 | 0 | 0U, // G_FEXP |
3685 | 0 | 0U, // G_FEXP2 |
3686 | 0 | 0U, // G_FEXP10 |
3687 | 0 | 0U, // G_FLOG |
3688 | 0 | 0U, // G_FLOG2 |
3689 | 0 | 0U, // G_FLOG10 |
3690 | 0 | 0U, // G_FLDEXP |
3691 | 0 | 0U, // G_FFREXP |
3692 | 0 | 0U, // G_FNEG |
3693 | 0 | 0U, // G_FPEXT |
3694 | 0 | 0U, // G_FPTRUNC |
3695 | 0 | 0U, // G_FPTOSI |
3696 | 0 | 0U, // G_FPTOUI |
3697 | 0 | 0U, // G_SITOFP |
3698 | 0 | 0U, // G_UITOFP |
3699 | 0 | 0U, // G_FABS |
3700 | 0 | 0U, // G_FCOPYSIGN |
3701 | 0 | 0U, // G_IS_FPCLASS |
3702 | 0 | 0U, // G_FCANONICALIZE |
3703 | 0 | 0U, // G_FMINNUM |
3704 | 0 | 0U, // G_FMAXNUM |
3705 | 0 | 0U, // G_FMINNUM_IEEE |
3706 | 0 | 0U, // G_FMAXNUM_IEEE |
3707 | 0 | 0U, // G_FMINIMUM |
3708 | 0 | 0U, // G_FMAXIMUM |
3709 | 0 | 0U, // G_GET_FPENV |
3710 | 0 | 0U, // G_SET_FPENV |
3711 | 0 | 0U, // G_RESET_FPENV |
3712 | 0 | 0U, // G_GET_FPMODE |
3713 | 0 | 0U, // G_SET_FPMODE |
3714 | 0 | 0U, // G_RESET_FPMODE |
3715 | 0 | 0U, // G_PTR_ADD |
3716 | 0 | 0U, // G_PTRMASK |
3717 | 0 | 0U, // G_SMIN |
3718 | 0 | 0U, // G_SMAX |
3719 | 0 | 0U, // G_UMIN |
3720 | 0 | 0U, // G_UMAX |
3721 | 0 | 0U, // G_ABS |
3722 | 0 | 0U, // G_LROUND |
3723 | 0 | 0U, // G_LLROUND |
3724 | 0 | 0U, // G_BR |
3725 | 0 | 0U, // G_BRJT |
3726 | 0 | 0U, // G_INSERT_VECTOR_ELT |
3727 | 0 | 0U, // G_EXTRACT_VECTOR_ELT |
3728 | 0 | 0U, // G_SHUFFLE_VECTOR |
3729 | 0 | 0U, // G_CTTZ |
3730 | 0 | 0U, // G_CTTZ_ZERO_UNDEF |
3731 | 0 | 0U, // G_CTLZ |
3732 | 0 | 0U, // G_CTLZ_ZERO_UNDEF |
3733 | 0 | 0U, // G_CTPOP |
3734 | 0 | 0U, // G_BSWAP |
3735 | 0 | 0U, // G_BITREVERSE |
3736 | 0 | 0U, // G_FCEIL |
3737 | 0 | 0U, // G_FCOS |
3738 | 0 | 0U, // G_FSIN |
3739 | 0 | 0U, // G_FSQRT |
3740 | 0 | 0U, // G_FFLOOR |
3741 | 0 | 0U, // G_FRINT |
3742 | 0 | 0U, // G_FNEARBYINT |
3743 | 0 | 0U, // G_ADDRSPACE_CAST |
3744 | 0 | 0U, // G_BLOCK_ADDR |
3745 | 0 | 0U, // G_JUMP_TABLE |
3746 | 0 | 0U, // G_DYN_STACKALLOC |
3747 | 0 | 0U, // G_STACKSAVE |
3748 | 0 | 0U, // G_STACKRESTORE |
3749 | 0 | 0U, // G_STRICT_FADD |
3750 | 0 | 0U, // G_STRICT_FSUB |
3751 | 0 | 0U, // G_STRICT_FMUL |
3752 | 0 | 0U, // G_STRICT_FDIV |
3753 | 0 | 0U, // G_STRICT_FREM |
3754 | 0 | 0U, // G_STRICT_FMA |
3755 | 0 | 0U, // G_STRICT_FSQRT |
3756 | 0 | 0U, // G_STRICT_FLDEXP |
3757 | 0 | 0U, // G_READ_REGISTER |
3758 | 0 | 0U, // G_WRITE_REGISTER |
3759 | 0 | 0U, // G_MEMCPY |
3760 | 0 | 0U, // G_MEMCPY_INLINE |
3761 | 0 | 0U, // G_MEMMOVE |
3762 | 0 | 0U, // G_MEMSET |
3763 | 0 | 0U, // G_BZERO |
3764 | 0 | 0U, // G_VECREDUCE_SEQ_FADD |
3765 | 0 | 0U, // G_VECREDUCE_SEQ_FMUL |
3766 | 0 | 0U, // G_VECREDUCE_FADD |
3767 | 0 | 0U, // G_VECREDUCE_FMUL |
3768 | 0 | 0U, // G_VECREDUCE_FMAX |
3769 | 0 | 0U, // G_VECREDUCE_FMIN |
3770 | 0 | 0U, // G_VECREDUCE_FMAXIMUM |
3771 | 0 | 0U, // G_VECREDUCE_FMINIMUM |
3772 | 0 | 0U, // G_VECREDUCE_ADD |
3773 | 0 | 0U, // G_VECREDUCE_MUL |
3774 | 0 | 0U, // G_VECREDUCE_AND |
3775 | 0 | 0U, // G_VECREDUCE_OR |
3776 | 0 | 0U, // G_VECREDUCE_XOR |
3777 | 0 | 0U, // G_VECREDUCE_SMAX |
3778 | 0 | 0U, // G_VECREDUCE_SMIN |
3779 | 0 | 0U, // G_VECREDUCE_UMAX |
3780 | 0 | 0U, // G_VECREDUCE_UMIN |
3781 | 0 | 0U, // G_SBFX |
3782 | 0 | 0U, // G_UBFX |
3783 | 0 | 0U, // A2_addsp |
3784 | 0 | 0U, // A2_iconst |
3785 | 0 | 0U, // A2_neg |
3786 | 0 | 0U, // A2_not |
3787 | 0 | 0U, // A2_tfrf |
3788 | 0 | 0U, // A2_tfrfnew |
3789 | 0 | 0U, // A2_tfrp |
3790 | 0 | 0U, // A2_tfrpf |
3791 | 0 | 0U, // A2_tfrpfnew |
3792 | 0 | 0U, // A2_tfrpi |
3793 | 0 | 0U, // A2_tfrpt |
3794 | 0 | 0U, // A2_tfrptnew |
3795 | 0 | 0U, // A2_tfrt |
3796 | 0 | 0U, // A2_tfrtnew |
3797 | 0 | 0U, // A2_vaddb_map |
3798 | 0 | 0U, // A2_vsubb_map |
3799 | 0 | 0U, // A2_zxtb |
3800 | 0 | 0U, // A4_boundscheck |
3801 | 0 | 0U, // ADJCALLSTACKDOWN |
3802 | 0 | 0U, // ADJCALLSTACKUP |
3803 | 0 | 0U, // C2_cmpgei |
3804 | 0 | 0U, // C2_cmpgeui |
3805 | 0 | 0U, // C2_cmplt |
3806 | 0 | 0U, // C2_cmpltu |
3807 | 0 | 0U, // C2_pxfer_map |
3808 | 0 | 0U, // DUPLEX_Pseudo |
3809 | 0 | 0U, // ENDLOOP0 |
3810 | 0 | 0U, // ENDLOOP01 |
3811 | 0 | 0U, // ENDLOOP1 |
3812 | 0 | 0U, // J2_endloop0 |
3813 | 0 | 0U, // J2_endloop01 |
3814 | 0 | 0U, // J2_endloop1 |
3815 | 0 | 0U, // J2_jumpf_nopred_map |
3816 | 0 | 0U, // J2_jumprf_nopred_map |
3817 | 0 | 0U, // J2_jumprt_nopred_map |
3818 | 0 | 0U, // J2_jumpt_nopred_map |
3819 | 0 | 0U, // J2_trap1_noregmap |
3820 | 0 | 1U, // L2_loadalignb_zomap |
3821 | 0 | 1U, // L2_loadalignh_zomap |
3822 | 0 | 0U, // L2_loadbsw2_zomap |
3823 | 0 | 0U, // L2_loadbsw4_zomap |
3824 | 0 | 0U, // L2_loadbzw2_zomap |
3825 | 0 | 0U, // L2_loadbzw4_zomap |
3826 | 0 | 0U, // L2_loadrb_zomap |
3827 | 0 | 0U, // L2_loadrd_zomap |
3828 | 0 | 0U, // L2_loadrh_zomap |
3829 | 0 | 0U, // L2_loadri_zomap |
3830 | 0 | 0U, // L2_loadrub_zomap |
3831 | 0 | 0U, // L2_loadruh_zomap |
3832 | 0 | 66U, // L2_ploadrbf_zomap |
3833 | 0 | 66U, // L2_ploadrbfnew_zomap |
3834 | 0 | 66U, // L2_ploadrbt_zomap |
3835 | 0 | 66U, // L2_ploadrbtnew_zomap |
3836 | 0 | 66U, // L2_ploadrdf_zomap |
3837 | 0 | 66U, // L2_ploadrdfnew_zomap |
3838 | 0 | 66U, // L2_ploadrdt_zomap |
3839 | 0 | 66U, // L2_ploadrdtnew_zomap |
3840 | 0 | 66U, // L2_ploadrhf_zomap |
3841 | 0 | 66U, // L2_ploadrhfnew_zomap |
3842 | 0 | 66U, // L2_ploadrht_zomap |
3843 | 0 | 66U, // L2_ploadrhtnew_zomap |
3844 | 0 | 66U, // L2_ploadrif_zomap |
3845 | 0 | 66U, // L2_ploadrifnew_zomap |
3846 | 0 | 66U, // L2_ploadrit_zomap |
3847 | 0 | 66U, // L2_ploadritnew_zomap |
3848 | 0 | 66U, // L2_ploadrubf_zomap |
3849 | 0 | 66U, // L2_ploadrubfnew_zomap |
3850 | 0 | 66U, // L2_ploadrubt_zomap |
3851 | 0 | 66U, // L2_ploadrubtnew_zomap |
3852 | 0 | 66U, // L2_ploadruhf_zomap |
3853 | 0 | 66U, // L2_ploadruhfnew_zomap |
3854 | 0 | 66U, // L2_ploadruht_zomap |
3855 | 0 | 66U, // L2_ploadruhtnew_zomap |
3856 | 0 | 0U, // L4_add_memopb_zomap |
3857 | 0 | 0U, // L4_add_memoph_zomap |
3858 | 0 | 0U, // L4_add_memopw_zomap |
3859 | 0 | 0U, // L4_and_memopb_zomap |
3860 | 0 | 0U, // L4_and_memoph_zomap |
3861 | 0 | 0U, // L4_and_memopw_zomap |
3862 | 0 | 0U, // L4_iadd_memopb_zomap |
3863 | 0 | 0U, // L4_iadd_memoph_zomap |
3864 | 0 | 0U, // L4_iadd_memopw_zomap |
3865 | 0 | 0U, // L4_iand_memopb_zomap |
3866 | 0 | 0U, // L4_iand_memoph_zomap |
3867 | 0 | 0U, // L4_iand_memopw_zomap |
3868 | 0 | 0U, // L4_ior_memopb_zomap |
3869 | 0 | 0U, // L4_ior_memoph_zomap |
3870 | 0 | 0U, // L4_ior_memopw_zomap |
3871 | 0 | 0U, // L4_isub_memopb_zomap |
3872 | 0 | 0U, // L4_isub_memoph_zomap |
3873 | 0 | 0U, // L4_isub_memopw_zomap |
3874 | 0 | 0U, // L4_or_memopb_zomap |
3875 | 0 | 0U, // L4_or_memoph_zomap |
3876 | 0 | 0U, // L4_or_memopw_zomap |
3877 | 0 | 0U, // L4_return_map_to_raw_f |
3878 | 0 | 0U, // L4_return_map_to_raw_fnew_pnt |
3879 | 0 | 0U, // L4_return_map_to_raw_fnew_pt |
3880 | 0 | 0U, // L4_return_map_to_raw_t |
3881 | 0 | 0U, // L4_return_map_to_raw_tnew_pnt |
3882 | 0 | 0U, // L4_return_map_to_raw_tnew_pt |
3883 | 0 | 0U, // L4_sub_memopb_zomap |
3884 | 0 | 0U, // L4_sub_memoph_zomap |
3885 | 0 | 0U, // L4_sub_memopw_zomap |
3886 | 0 | 0U, // L6_deallocframe_map_to_raw |
3887 | 0 | 0U, // L6_return_map_to_raw |
3888 | 0 | 0U, // LDriw_ctr |
3889 | 0 | 0U, // LDriw_pred |
3890 | 0 | 66U, // M2_mpysmi |
3891 | 0 | 0U, // M2_mpyui |
3892 | 0 | 0U, // M2_vrcmpys_acc_s1 |
3893 | 0 | 0U, // M2_vrcmpys_s1 |
3894 | 0 | 0U, // M2_vrcmpys_s1rp |
3895 | 0 | 0U, // M7_vdmpy |
3896 | 0 | 0U, // M7_vdmpy_acc |
3897 | 0 | 0U, // PS_aligna |
3898 | 0 | 0U, // PS_alloca |
3899 | 0 | 0U, // PS_call_instrprof_custom |
3900 | 0 | 0U, // PS_call_nr |
3901 | 0 | 0U, // PS_crash |
3902 | 0 | 0U, // PS_false |
3903 | 0 | 0U, // PS_fi |
3904 | 0 | 0U, // PS_fia |
3905 | 0 | 0U, // PS_loadrb_pci |
3906 | 0 | 0U, // PS_loadrb_pcr |
3907 | 0 | 0U, // PS_loadrd_pci |
3908 | 0 | 0U, // PS_loadrd_pcr |
3909 | 0 | 0U, // PS_loadrh_pci |
3910 | 0 | 0U, // PS_loadrh_pcr |
3911 | 0 | 0U, // PS_loadri_pci |
3912 | 0 | 0U, // PS_loadri_pcr |
3913 | 0 | 0U, // PS_loadrub_pci |
3914 | 0 | 0U, // PS_loadrub_pcr |
3915 | 0 | 0U, // PS_loadruh_pci |
3916 | 0 | 0U, // PS_loadruh_pcr |
3917 | 0 | 0U, // PS_pselect |
3918 | 0 | 0U, // PS_qfalse |
3919 | 0 | 0U, // PS_qtrue |
3920 | 0 | 0U, // PS_storerb_pci |
3921 | 0 | 0U, // PS_storerb_pcr |
3922 | 0 | 0U, // PS_storerd_pci |
3923 | 0 | 0U, // PS_storerd_pcr |
3924 | 0 | 0U, // PS_storerf_pci |
3925 | 0 | 0U, // PS_storerf_pcr |
3926 | 0 | 0U, // PS_storerh_pci |
3927 | 0 | 0U, // PS_storerh_pcr |
3928 | 0 | 0U, // PS_storeri_pci |
3929 | 0 | 0U, // PS_storeri_pcr |
3930 | 0 | 0U, // PS_tailcall_i |
3931 | 0 | 0U, // PS_tailcall_r |
3932 | 0 | 0U, // PS_true |
3933 | 0 | 0U, // PS_vdd0 |
3934 | 0 | 0U, // PS_vloadrq_ai |
3935 | 0 | 0U, // PS_vloadrv_ai |
3936 | 0 | 0U, // PS_vloadrv_nt_ai |
3937 | 0 | 0U, // PS_vloadrw_ai |
3938 | 0 | 0U, // PS_vloadrw_nt_ai |
3939 | 0 | 0U, // PS_vmulw |
3940 | 0 | 0U, // PS_vmulw_acc |
3941 | 0 | 0U, // PS_vselect |
3942 | 0 | 0U, // PS_vsplatib |
3943 | 0 | 0U, // PS_vsplatih |
3944 | 0 | 0U, // PS_vsplatiw |
3945 | 0 | 0U, // PS_vsplatrb |
3946 | 0 | 0U, // PS_vsplatrh |
3947 | 0 | 0U, // PS_vsplatrw |
3948 | 0 | 0U, // PS_vstorerq_ai |
3949 | 0 | 0U, // PS_vstorerv_ai |
3950 | 0 | 0U, // PS_vstorerv_nt_ai |
3951 | 0 | 0U, // PS_vstorerw_ai |
3952 | 0 | 0U, // PS_vstorerw_nt_ai |
3953 | 0 | 0U, // PS_wselect |
3954 | 0 | 0U, // S2_asr_i_p_rnd_goodsyntax |
3955 | 0 | 0U, // S2_asr_i_r_rnd_goodsyntax |
3956 | 0 | 131U, // S2_pstorerbf_zomap |
3957 | 0 | 195U, // S2_pstorerbnewf_zomap |
3958 | 0 | 195U, // S2_pstorerbnewt_zomap |
3959 | 0 | 131U, // S2_pstorerbt_zomap |
3960 | 0 | 131U, // S2_pstorerdf_zomap |
3961 | 0 | 131U, // S2_pstorerdt_zomap |
3962 | 0 | 259U, // S2_pstorerff_zomap |
3963 | 0 | 259U, // S2_pstorerft_zomap |
3964 | 0 | 131U, // S2_pstorerhf_zomap |
3965 | 0 | 195U, // S2_pstorerhnewf_zomap |
3966 | 0 | 195U, // S2_pstorerhnewt_zomap |
3967 | 0 | 131U, // S2_pstorerht_zomap |
3968 | 0 | 131U, // S2_pstorerif_zomap |
3969 | 0 | 195U, // S2_pstorerinewf_zomap |
3970 | 0 | 195U, // S2_pstorerinewt_zomap |
3971 | 0 | 131U, // S2_pstorerit_zomap |
3972 | 0 | 0U, // S2_storerb_zomap |
3973 | 0 | 0U, // S2_storerbnew_zomap |
3974 | 0 | 0U, // S2_storerd_zomap |
3975 | 0 | 0U, // S2_storerf_zomap |
3976 | 0 | 0U, // S2_storerh_zomap |
3977 | 0 | 0U, // S2_storerhnew_zomap |
3978 | 0 | 0U, // S2_storeri_zomap |
3979 | 0 | 0U, // S2_storerinew_zomap |
3980 | 0 | 0U, // S2_tableidxb_goodsyntax |
3981 | 0 | 0U, // S2_tableidxd_goodsyntax |
3982 | 0 | 0U, // S2_tableidxh_goodsyntax |
3983 | 0 | 0U, // S2_tableidxw_goodsyntax |
3984 | 0 | 131U, // S4_pstorerbfnew_zomap |
3985 | 0 | 195U, // S4_pstorerbnewfnew_zomap |
3986 | 0 | 195U, // S4_pstorerbnewtnew_zomap |
3987 | 0 | 131U, // S4_pstorerbtnew_zomap |
3988 | 0 | 131U, // S4_pstorerdfnew_zomap |
3989 | 0 | 131U, // S4_pstorerdtnew_zomap |
3990 | 0 | 259U, // S4_pstorerffnew_zomap |
3991 | 0 | 259U, // S4_pstorerftnew_zomap |
3992 | 0 | 131U, // S4_pstorerhfnew_zomap |
3993 | 0 | 195U, // S4_pstorerhnewfnew_zomap |
3994 | 0 | 195U, // S4_pstorerhnewtnew_zomap |
3995 | 0 | 131U, // S4_pstorerhtnew_zomap |
3996 | 0 | 131U, // S4_pstorerifnew_zomap |
3997 | 0 | 195U, // S4_pstorerinewfnew_zomap |
3998 | 0 | 195U, // S4_pstorerinewtnew_zomap |
3999 | 0 | 131U, // S4_pstoreritnew_zomap |
4000 | 0 | 0U, // S4_storeirb_zomap |
4001 | 0 | 4U, // S4_storeirbf_zomap |
4002 | 0 | 4U, // S4_storeirbfnew_zomap |
4003 | 0 | 4U, // S4_storeirbt_zomap |
4004 | 0 | 4U, // S4_storeirbtnew_zomap |
4005 | 0 | 0U, // S4_storeirh_zomap |
4006 | 0 | 4U, // S4_storeirhf_zomap |
4007 | 0 | 4U, // S4_storeirhfnew_zomap |
4008 | 0 | 4U, // S4_storeirht_zomap |
4009 | 0 | 4U, // S4_storeirhtnew_zomap |
4010 | 0 | 0U, // S4_storeiri_zomap |
4011 | 0 | 4U, // S4_storeirif_zomap |
4012 | 0 | 4U, // S4_storeirifnew_zomap |
4013 | 0 | 4U, // S4_storeirit_zomap |
4014 | 0 | 4U, // S4_storeiritnew_zomap |
4015 | 0 | 0U, // S5_asrhub_rnd_sat_goodsyntax |
4016 | 0 | 322U, // S5_vasrhrnd_goodsyntax |
4017 | 0 | 0U, // S6_allocframe_to_raw |
4018 | 0 | 0U, // STriw_ctr |
4019 | 0 | 0U, // STriw_pred |
4020 | 0 | 386U, // V6_MAP_equb |
4021 | 0 | 389U, // V6_MAP_equb_and |
4022 | 0 | 389U, // V6_MAP_equb_ior |
4023 | 0 | 389U, // V6_MAP_equb_xor |
4024 | 0 | 450U, // V6_MAP_equh |
4025 | 0 | 453U, // V6_MAP_equh_and |
4026 | 0 | 453U, // V6_MAP_equh_ior |
4027 | 0 | 453U, // V6_MAP_equh_xor |
4028 | 0 | 514U, // V6_MAP_equw |
4029 | 0 | 517U, // V6_MAP_equw_and |
4030 | 0 | 517U, // V6_MAP_equw_ior |
4031 | 0 | 517U, // V6_MAP_equw_xor |
4032 | 0 | 0U, // V6_dbl_ld0 |
4033 | 0 | 0U, // V6_dbl_st0 |
4034 | 0 | 0U, // V6_extractw_alt |
4035 | 0 | 0U, // V6_hi |
4036 | 0 | 0U, // V6_ld0 |
4037 | 0 | 66U, // V6_ldcnp0 |
4038 | 0 | 578U, // V6_ldcnpnt0 |
4039 | 0 | 66U, // V6_ldcp0 |
4040 | 0 | 578U, // V6_ldcpnt0 |
4041 | 0 | 66U, // V6_ldnp0 |
4042 | 0 | 578U, // V6_ldnpnt0 |
4043 | 0 | 0U, // V6_ldnt0 |
4044 | 0 | 66U, // V6_ldp0 |
4045 | 0 | 578U, // V6_ldpnt0 |
4046 | 0 | 66U, // V6_ldtnp0 |
4047 | 0 | 578U, // V6_ldtnpnt0 |
4048 | 0 | 66U, // V6_ldtp0 |
4049 | 0 | 578U, // V6_ldtpnt0 |
4050 | 0 | 0U, // V6_ldu0 |
4051 | 0 | 0U, // V6_lo |
4052 | 0 | 0U, // V6_st0 |
4053 | 0 | 0U, // V6_stn0 |
4054 | 0 | 0U, // V6_stnnt0 |
4055 | 0 | 131U, // V6_stnp0 |
4056 | 0 | 6U, // V6_stnpnt0 |
4057 | 0 | 131U, // V6_stnq0 |
4058 | 0 | 6U, // V6_stnqnt0 |
4059 | 0 | 0U, // V6_stnt0 |
4060 | 0 | 131U, // V6_stp0 |
4061 | 0 | 6U, // V6_stpnt0 |
4062 | 0 | 131U, // V6_stq0 |
4063 | 0 | 6U, // V6_stqnt0 |
4064 | 0 | 0U, // V6_stu0 |
4065 | 0 | 131U, // V6_stunp0 |
4066 | 0 | 131U, // V6_stup0 |
4067 | 0 | 0U, // V6_v10mpyubs10 |
4068 | 0 | 0U, // V6_v10mpyubs10_vxx |
4069 | 0 | 7U, // V6_v6mpyhubs10_alt |
4070 | 0 | 8U, // V6_v6mpyvubs10_alt |
4071 | 0 | 0U, // V6_vabsb_alt |
4072 | 0 | 0U, // V6_vabsb_sat_alt |
4073 | 0 | 0U, // V6_vabsdiffh_alt |
4074 | 0 | 0U, // V6_vabsdiffub_alt |
4075 | 0 | 0U, // V6_vabsdiffuh_alt |
4076 | 0 | 0U, // V6_vabsdiffw_alt |
4077 | 0 | 0U, // V6_vabsh_alt |
4078 | 0 | 0U, // V6_vabsh_sat_alt |
4079 | 0 | 0U, // V6_vabsub_alt |
4080 | 0 | 0U, // V6_vabsuh_alt |
4081 | 0 | 0U, // V6_vabsuw_alt |
4082 | 0 | 0U, // V6_vabsw_alt |
4083 | 0 | 0U, // V6_vabsw_sat_alt |
4084 | 0 | 0U, // V6_vaddb_alt |
4085 | 0 | 0U, // V6_vaddb_dv_alt |
4086 | 0 | 0U, // V6_vaddbnq_alt |
4087 | 0 | 0U, // V6_vaddbq_alt |
4088 | 0 | 0U, // V6_vaddbsat_alt |
4089 | 0 | 0U, // V6_vaddbsat_dv_alt |
4090 | 0 | 0U, // V6_vaddh_alt |
4091 | 0 | 0U, // V6_vaddh_dv_alt |
4092 | 0 | 0U, // V6_vaddhnq_alt |
4093 | 0 | 0U, // V6_vaddhq_alt |
4094 | 0 | 0U, // V6_vaddhsat_alt |
4095 | 0 | 0U, // V6_vaddhsat_dv_alt |
4096 | 0 | 0U, // V6_vaddhw_acc_alt |
4097 | 0 | 0U, // V6_vaddhw_alt |
4098 | 0 | 0U, // V6_vaddubh_acc_alt |
4099 | 0 | 0U, // V6_vaddubh_alt |
4100 | 0 | 0U, // V6_vaddubsat_alt |
4101 | 0 | 0U, // V6_vaddubsat_dv_alt |
4102 | 0 | 0U, // V6_vadduhsat_alt |
4103 | 0 | 0U, // V6_vadduhsat_dv_alt |
4104 | 0 | 0U, // V6_vadduhw_acc_alt |
4105 | 0 | 0U, // V6_vadduhw_alt |
4106 | 0 | 0U, // V6_vadduwsat_alt |
4107 | 0 | 0U, // V6_vadduwsat_dv_alt |
4108 | 0 | 0U, // V6_vaddw_alt |
4109 | 0 | 0U, // V6_vaddw_dv_alt |
4110 | 0 | 0U, // V6_vaddwnq_alt |
4111 | 0 | 0U, // V6_vaddwq_alt |
4112 | 0 | 0U, // V6_vaddwsat_alt |
4113 | 0 | 0U, // V6_vaddwsat_dv_alt |
4114 | 0 | 0U, // V6_vandnqrt_acc_alt |
4115 | 0 | 0U, // V6_vandnqrt_alt |
4116 | 0 | 0U, // V6_vandqrt_acc_alt |
4117 | 0 | 0U, // V6_vandqrt_alt |
4118 | 0 | 0U, // V6_vandvrt_acc_alt |
4119 | 0 | 0U, // V6_vandvrt_alt |
4120 | 0 | 0U, // V6_vaslh_acc_alt |
4121 | 0 | 66U, // V6_vaslh_alt |
4122 | 0 | 66U, // V6_vaslhv_alt |
4123 | 0 | 0U, // V6_vaslw_acc_alt |
4124 | 0 | 66U, // V6_vaslw_alt |
4125 | 0 | 66U, // V6_vaslwv_alt |
4126 | 0 | 0U, // V6_vasr_into_alt |
4127 | 0 | 0U, // V6_vasrh_acc_alt |
4128 | 0 | 66U, // V6_vasrh_alt |
4129 | 0 | 66U, // V6_vasrhv_alt |
4130 | 0 | 0U, // V6_vasrw_acc_alt |
4131 | 0 | 66U, // V6_vasrw_alt |
4132 | 0 | 66U, // V6_vasrwv_alt |
4133 | 0 | 0U, // V6_vassignp |
4134 | 0 | 0U, // V6_vavgb_alt |
4135 | 0 | 0U, // V6_vavgbrnd_alt |
4136 | 0 | 0U, // V6_vavgh_alt |
4137 | 0 | 0U, // V6_vavghrnd_alt |
4138 | 0 | 0U, // V6_vavgub_alt |
4139 | 0 | 0U, // V6_vavgubrnd_alt |
4140 | 0 | 0U, // V6_vavguh_alt |
4141 | 0 | 0U, // V6_vavguhrnd_alt |
4142 | 0 | 0U, // V6_vavguw_alt |
4143 | 0 | 0U, // V6_vavguwrnd_alt |
4144 | 0 | 0U, // V6_vavgw_alt |
4145 | 0 | 0U, // V6_vavgwrnd_alt |
4146 | 0 | 0U, // V6_vcl0h_alt |
4147 | 0 | 0U, // V6_vcl0w_alt |
4148 | 0 | 0U, // V6_vd0 |
4149 | 0 | 0U, // V6_vdd0 |
4150 | 0 | 0U, // V6_vdealb4w_alt |
4151 | 0 | 0U, // V6_vdealb_alt |
4152 | 0 | 0U, // V6_vdealh_alt |
4153 | 0 | 0U, // V6_vdmpybus_acc_alt |
4154 | 0 | 0U, // V6_vdmpybus_alt |
4155 | 0 | 0U, // V6_vdmpybus_dv_acc_alt |
4156 | 0 | 0U, // V6_vdmpybus_dv_alt |
4157 | 0 | 0U, // V6_vdmpyhb_acc_alt |
4158 | 0 | 0U, // V6_vdmpyhb_alt |
4159 | 0 | 0U, // V6_vdmpyhb_dv_acc_alt |
4160 | 0 | 0U, // V6_vdmpyhb_dv_alt |
4161 | 0 | 0U, // V6_vdmpyhisat_acc_alt |
4162 | 0 | 0U, // V6_vdmpyhisat_alt |
4163 | 0 | 0U, // V6_vdmpyhsat_acc_alt |
4164 | 0 | 0U, // V6_vdmpyhsat_alt |
4165 | 0 | 0U, // V6_vdmpyhsuisat_acc_alt |
4166 | 0 | 0U, // V6_vdmpyhsuisat_alt |
4167 | 0 | 0U, // V6_vdmpyhsusat_acc_alt |
4168 | 0 | 0U, // V6_vdmpyhsusat_alt |
4169 | 0 | 0U, // V6_vdmpyhvsat_acc_alt |
4170 | 0 | 0U, // V6_vdmpyhvsat_alt |
4171 | 0 | 0U, // V6_vdsaduh_acc_alt |
4172 | 0 | 0U, // V6_vdsaduh_alt |
4173 | 0 | 0U, // V6_vgathermh_pseudo |
4174 | 0 | 0U, // V6_vgathermhq_pseudo |
4175 | 0 | 0U, // V6_vgathermhw_pseudo |
4176 | 0 | 0U, // V6_vgathermhwq_pseudo |
4177 | 0 | 0U, // V6_vgathermw_pseudo |
4178 | 0 | 0U, // V6_vgathermwq_pseudo |
4179 | 0 | 66U, // V6_vlsrh_alt |
4180 | 0 | 66U, // V6_vlsrhv_alt |
4181 | 0 | 66U, // V6_vlsrw_alt |
4182 | 0 | 66U, // V6_vlsrwv_alt |
4183 | 0 | 0U, // V6_vmaxb_alt |
4184 | 0 | 0U, // V6_vmaxh_alt |
4185 | 0 | 0U, // V6_vmaxub_alt |
4186 | 0 | 0U, // V6_vmaxuh_alt |
4187 | 0 | 0U, // V6_vmaxw_alt |
4188 | 0 | 0U, // V6_vminb_alt |
4189 | 0 | 0U, // V6_vminh_alt |
4190 | 0 | 0U, // V6_vminub_alt |
4191 | 0 | 0U, // V6_vminuh_alt |
4192 | 0 | 0U, // V6_vminw_alt |
4193 | 0 | 0U, // V6_vmpabus_acc_alt |
4194 | 0 | 0U, // V6_vmpabus_alt |
4195 | 0 | 0U, // V6_vmpabusv_alt |
4196 | 0 | 0U, // V6_vmpabuu_acc_alt |
4197 | 0 | 0U, // V6_vmpabuu_alt |
4198 | 0 | 0U, // V6_vmpabuuv_alt |
4199 | 0 | 0U, // V6_vmpahb_acc_alt |
4200 | 0 | 0U, // V6_vmpahb_alt |
4201 | 0 | 0U, // V6_vmpauhb_acc_alt |
4202 | 0 | 0U, // V6_vmpauhb_alt |
4203 | 0 | 0U, // V6_vmpybus_acc_alt |
4204 | 0 | 0U, // V6_vmpybus_alt |
4205 | 0 | 0U, // V6_vmpybusv_acc_alt |
4206 | 0 | 0U, // V6_vmpybusv_alt |
4207 | 0 | 0U, // V6_vmpybv_acc_alt |
4208 | 0 | 0U, // V6_vmpybv_alt |
4209 | 0 | 0U, // V6_vmpyewuh_alt |
4210 | 0 | 0U, // V6_vmpyh_acc_alt |
4211 | 0 | 0U, // V6_vmpyh_alt |
4212 | 0 | 0U, // V6_vmpyhsat_acc_alt |
4213 | 0 | 0U, // V6_vmpyhsrs_alt |
4214 | 0 | 0U, // V6_vmpyhss_alt |
4215 | 0 | 0U, // V6_vmpyhus_acc_alt |
4216 | 0 | 0U, // V6_vmpyhus_alt |
4217 | 0 | 0U, // V6_vmpyhv_acc_alt |
4218 | 0 | 0U, // V6_vmpyhv_alt |
4219 | 0 | 0U, // V6_vmpyhvsrs_alt |
4220 | 0 | 0U, // V6_vmpyiewh_acc_alt |
4221 | 0 | 0U, // V6_vmpyiewuh_acc_alt |
4222 | 0 | 0U, // V6_vmpyiewuh_alt |
4223 | 0 | 0U, // V6_vmpyih_acc_alt |
4224 | 0 | 0U, // V6_vmpyih_alt |
4225 | 0 | 0U, // V6_vmpyihb_acc_alt |
4226 | 0 | 0U, // V6_vmpyihb_alt |
4227 | 0 | 0U, // V6_vmpyiowh_alt |
4228 | 0 | 0U, // V6_vmpyiwb_acc_alt |
4229 | 0 | 0U, // V6_vmpyiwb_alt |
4230 | 0 | 0U, // V6_vmpyiwh_acc_alt |
4231 | 0 | 0U, // V6_vmpyiwh_alt |
4232 | 0 | 0U, // V6_vmpyiwub_acc_alt |
4233 | 0 | 0U, // V6_vmpyiwub_alt |
4234 | 0 | 0U, // V6_vmpyowh_alt |
4235 | 0 | 0U, // V6_vmpyowh_rnd_alt |
4236 | 0 | 0U, // V6_vmpyowh_rnd_sacc_alt |
4237 | 0 | 0U, // V6_vmpyowh_sacc_alt |
4238 | 0 | 0U, // V6_vmpyub_acc_alt |
4239 | 0 | 0U, // V6_vmpyub_alt |
4240 | 0 | 0U, // V6_vmpyubv_acc_alt |
4241 | 0 | 0U, // V6_vmpyubv_alt |
4242 | 0 | 0U, // V6_vmpyuh_acc_alt |
4243 | 0 | 0U, // V6_vmpyuh_alt |
4244 | 0 | 0U, // V6_vmpyuhv_acc_alt |
4245 | 0 | 0U, // V6_vmpyuhv_alt |
4246 | 0 | 0U, // V6_vnavgb_alt |
4247 | 0 | 0U, // V6_vnavgh_alt |
4248 | 0 | 0U, // V6_vnavgub_alt |
4249 | 0 | 0U, // V6_vnavgw_alt |
4250 | 0 | 0U, // V6_vnormamth_alt |
4251 | 0 | 0U, // V6_vnormamtw_alt |
4252 | 0 | 0U, // V6_vpackeb_alt |
4253 | 0 | 0U, // V6_vpackeh_alt |
4254 | 0 | 0U, // V6_vpackhb_sat_alt |
4255 | 0 | 0U, // V6_vpackhub_sat_alt |
4256 | 0 | 0U, // V6_vpackob_alt |
4257 | 0 | 0U, // V6_vpackoh_alt |
4258 | 0 | 0U, // V6_vpackwh_sat_alt |
4259 | 0 | 0U, // V6_vpackwuh_sat_alt |
4260 | 0 | 0U, // V6_vpopcounth_alt |
4261 | 0 | 389U, // V6_vrmpybub_rtt_acc_alt |
4262 | 0 | 386U, // V6_vrmpybub_rtt_alt |
4263 | 0 | 0U, // V6_vrmpybus_acc_alt |
4264 | 0 | 0U, // V6_vrmpybus_alt |
4265 | 0 | 73U, // V6_vrmpybusi_acc_alt |
4266 | 0 | 69U, // V6_vrmpybusi_alt |
4267 | 0 | 0U, // V6_vrmpybusv_acc_alt |
4268 | 0 | 0U, // V6_vrmpybusv_alt |
4269 | 0 | 0U, // V6_vrmpybv_acc_alt |
4270 | 0 | 0U, // V6_vrmpybv_alt |
4271 | 0 | 0U, // V6_vrmpyub_acc_alt |
4272 | 0 | 0U, // V6_vrmpyub_alt |
4273 | 0 | 0U, // V6_vrmpyub_rtt_acc_alt |
4274 | 0 | 0U, // V6_vrmpyub_rtt_alt |
4275 | 0 | 73U, // V6_vrmpyubi_acc_alt |
4276 | 0 | 69U, // V6_vrmpyubi_alt |
4277 | 0 | 0U, // V6_vrmpyubv_acc_alt |
4278 | 0 | 0U, // V6_vrmpyubv_alt |
4279 | 0 | 0U, // V6_vrotr_alt |
4280 | 0 | 0U, // V6_vroundhb_alt |
4281 | 0 | 0U, // V6_vroundhub_alt |
4282 | 0 | 0U, // V6_vrounduhub_alt |
4283 | 0 | 0U, // V6_vrounduwuh_alt |
4284 | 0 | 0U, // V6_vroundwh_alt |
4285 | 0 | 0U, // V6_vroundwuh_alt |
4286 | 0 | 73U, // V6_vrsadubi_acc_alt |
4287 | 0 | 69U, // V6_vrsadubi_alt |
4288 | 0 | 66U, // V6_vsathub_alt |
4289 | 0 | 0U, // V6_vsatuwuh_alt |
4290 | 0 | 66U, // V6_vsatwh_alt |
4291 | 0 | 0U, // V6_vsb_alt |
4292 | 0 | 4096U, // V6_vscattermh_add_alt |
4293 | 0 | 8192U, // V6_vscattermh_alt |
4294 | 0 | 0U, // V6_vscattermhq_alt |
4295 | 0 | 12288U, // V6_vscattermw_add_alt |
4296 | 0 | 16384U, // V6_vscattermw_alt |
4297 | 0 | 12288U, // V6_vscattermwh_add_alt |
4298 | 0 | 16384U, // V6_vscattermwh_alt |
4299 | 0 | 10U, // V6_vscattermwhq_alt |
4300 | 0 | 11U, // V6_vscattermwq_alt |
4301 | 0 | 0U, // V6_vsh_alt |
4302 | 0 | 0U, // V6_vshufeh_alt |
4303 | 0 | 0U, // V6_vshuffb_alt |
4304 | 0 | 0U, // V6_vshuffeb_alt |
4305 | 0 | 0U, // V6_vshuffh_alt |
4306 | 0 | 0U, // V6_vshuffob_alt |
4307 | 0 | 0U, // V6_vshufoeb_alt |
4308 | 0 | 0U, // V6_vshufoeh_alt |
4309 | 0 | 0U, // V6_vshufoh_alt |
4310 | 0 | 0U, // V6_vsubb_alt |
4311 | 0 | 0U, // V6_vsubb_dv_alt |
4312 | 0 | 0U, // V6_vsubbnq_alt |
4313 | 0 | 0U, // V6_vsubbq_alt |
4314 | 0 | 0U, // V6_vsubbsat_alt |
4315 | 0 | 0U, // V6_vsubbsat_dv_alt |
4316 | 0 | 0U, // V6_vsubh_alt |
4317 | 0 | 0U, // V6_vsubh_dv_alt |
4318 | 0 | 0U, // V6_vsubhnq_alt |
4319 | 0 | 0U, // V6_vsubhq_alt |
4320 | 0 | 0U, // V6_vsubhsat_alt |
4321 | 0 | 0U, // V6_vsubhsat_dv_alt |
4322 | 0 | 0U, // V6_vsubhw_alt |
4323 | 0 | 0U, // V6_vsububh_alt |
4324 | 0 | 0U, // V6_vsububsat_alt |
4325 | 0 | 0U, // V6_vsububsat_dv_alt |
4326 | 0 | 0U, // V6_vsubuhsat_alt |
4327 | 0 | 0U, // V6_vsubuhsat_dv_alt |
4328 | 0 | 0U, // V6_vsubuhw_alt |
4329 | 0 | 0U, // V6_vsubuwsat_alt |
4330 | 0 | 0U, // V6_vsubuwsat_dv_alt |
4331 | 0 | 0U, // V6_vsubw_alt |
4332 | 0 | 0U, // V6_vsubw_dv_alt |
4333 | 0 | 0U, // V6_vsubwnq_alt |
4334 | 0 | 0U, // V6_vsubwq_alt |
4335 | 0 | 0U, // V6_vsubwsat_alt |
4336 | 0 | 0U, // V6_vsubwsat_dv_alt |
4337 | 0 | 0U, // V6_vtmpyb_acc_alt |
4338 | 0 | 0U, // V6_vtmpyb_alt |
4339 | 0 | 0U, // V6_vtmpybus_acc_alt |
4340 | 0 | 0U, // V6_vtmpybus_alt |
4341 | 0 | 0U, // V6_vtmpyhb_acc_alt |
4342 | 0 | 0U, // V6_vtmpyhb_alt |
4343 | 0 | 640U, // V6_vtran2x2_map |
4344 | 0 | 0U, // V6_vunpackb_alt |
4345 | 0 | 0U, // V6_vunpackh_alt |
4346 | 0 | 0U, // V6_vunpackob_alt |
4347 | 0 | 0U, // V6_vunpackoh_alt |
4348 | 0 | 0U, // V6_vunpackub_alt |
4349 | 0 | 0U, // V6_vunpackuh_alt |
4350 | 0 | 0U, // V6_vzb_alt |
4351 | 0 | 0U, // V6_vzh_alt |
4352 | 0 | 0U, // V6_zld0 |
4353 | 0 | 1U, // V6_zldp0 |
4354 | 0 | 0U, // Y2_crswap_old |
4355 | 0 | 0U, // Y2_dcfetch |
4356 | 0 | 0U, // Y2_k1lock_map |
4357 | 0 | 0U, // Y2_k1unlock_map |
4358 | 0 | 0U, // dup_A2_add |
4359 | 0 | 12U, // dup_A2_addi |
4360 | 0 | 66U, // dup_A2_andir |
4361 | 0 | 66U, // dup_A2_combineii |
4362 | 0 | 0U, // dup_A2_sxtb |
4363 | 0 | 0U, // dup_A2_sxth |
4364 | 0 | 0U, // dup_A2_tfr |
4365 | 0 | 0U, // dup_A2_tfrsi |
4366 | 0 | 0U, // dup_A2_zxtb |
4367 | 0 | 0U, // dup_A2_zxth |
4368 | 0 | 66U, // dup_A4_combineii |
4369 | 0 | 66U, // dup_A4_combineir |
4370 | 0 | 66U, // dup_A4_combineri |
4371 | 0 | 0U, // dup_C2_cmoveif |
4372 | 0 | 0U, // dup_C2_cmoveit |
4373 | 0 | 0U, // dup_C2_cmovenewif |
4374 | 0 | 0U, // dup_C2_cmovenewit |
4375 | 0 | 66U, // dup_C2_cmpeqi |
4376 | 0 | 0U, // dup_L2_deallocframe |
4377 | 0 | 1U, // dup_L2_loadrb_io |
4378 | 0 | 1U, // dup_L2_loadrd_io |
4379 | 0 | 1U, // dup_L2_loadrh_io |
4380 | 0 | 1U, // dup_L2_loadri_io |
4381 | 0 | 1U, // dup_L2_loadrub_io |
4382 | 0 | 1U, // dup_L2_loadruh_io |
4383 | 0 | 13U, // dup_S2_allocframe |
4384 | 0 | 130U, // dup_S2_storerb_io |
4385 | 0 | 130U, // dup_S2_storerd_io |
4386 | 0 | 130U, // dup_S2_storerh_io |
4387 | 0 | 130U, // dup_S2_storeri_io |
4388 | 0 | 0U, // dup_S4_storeirb_io |
4389 | 0 | 0U, // dup_S4_storeiri_io |
4390 | 0 | 0U, // A2_abs |
4391 | 0 | 0U, // A2_absp |
4392 | 0 | 0U, // A2_abssat |
4393 | 0 | 0U, // A2_add |
4394 | 0 | 718U, // A2_addh_h16_hh |
4395 | 0 | 782U, // A2_addh_h16_hl |
4396 | 0 | 719U, // A2_addh_h16_lh |
4397 | 0 | 783U, // A2_addh_h16_ll |
4398 | 0 | 846U, // A2_addh_h16_sat_hh |
4399 | 0 | 910U, // A2_addh_h16_sat_hl |
4400 | 0 | 847U, // A2_addh_h16_sat_lh |
4401 | 0 | 911U, // A2_addh_h16_sat_ll |
4402 | 0 | 975U, // A2_addh_l16_hl |
4403 | 0 | 1039U, // A2_addh_l16_ll |
4404 | 0 | 1103U, // A2_addh_l16_sat_hl |
4405 | 0 | 1167U, // A2_addh_l16_sat_ll |
4406 | 0 | 12U, // A2_addi |
4407 | 0 | 0U, // A2_addp |
4408 | 0 | 20480U, // A2_addpsat |
4409 | 0 | 20480U, // A2_addsat |
4410 | 0 | 24576U, // A2_addsph |
4411 | 0 | 28672U, // A2_addspl |
4412 | 0 | 66U, // A2_and |
4413 | 0 | 66U, // A2_andir |
4414 | 0 | 66U, // A2_andp |
4415 | 0 | 0U, // A2_aslh |
4416 | 0 | 0U, // A2_asrh |
4417 | 0 | 962U, // A2_combine_hh |
4418 | 0 | 1026U, // A2_combine_hl |
4419 | 0 | 962U, // A2_combine_lh |
4420 | 0 | 1026U, // A2_combine_ll |
4421 | 0 | 66U, // A2_combineii |
4422 | 0 | 66U, // A2_combinew |
4423 | 0 | 0U, // A2_max |
4424 | 0 | 0U, // A2_maxp |
4425 | 0 | 0U, // A2_maxu |
4426 | 0 | 0U, // A2_maxup |
4427 | 0 | 0U, // A2_min |
4428 | 0 | 0U, // A2_minp |
4429 | 0 | 0U, // A2_minu |
4430 | 0 | 0U, // A2_minup |
4431 | 0 | 0U, // A2_negp |
4432 | 0 | 0U, // A2_negsat |
4433 | 0 | 0U, // A2_nop |
4434 | 0 | 0U, // A2_notp |
4435 | 0 | 66U, // A2_or |
4436 | 0 | 66U, // A2_orir |
4437 | 0 | 66U, // A2_orp |
4438 | 0 | 1216U, // A2_paddf |
4439 | 0 | 1216U, // A2_paddfnew |
4440 | 0 | 1228U, // A2_paddif |
4441 | 0 | 1228U, // A2_paddifnew |
4442 | 0 | 1228U, // A2_paddit |
4443 | 0 | 1228U, // A2_padditnew |
4444 | 0 | 1216U, // A2_paddt |
4445 | 0 | 1216U, // A2_paddtnew |
4446 | 0 | 0U, // A2_pandf |
4447 | 0 | 0U, // A2_pandfnew |
4448 | 0 | 0U, // A2_pandt |
4449 | 0 | 0U, // A2_pandtnew |
4450 | 0 | 0U, // A2_porf |
4451 | 0 | 0U, // A2_porfnew |
4452 | 0 | 0U, // A2_port |
4453 | 0 | 0U, // A2_portnew |
4454 | 0 | 0U, // A2_psubf |
4455 | 0 | 0U, // A2_psubfnew |
4456 | 0 | 0U, // A2_psubt |
4457 | 0 | 0U, // A2_psubtnew |
4458 | 0 | 0U, // A2_pxorf |
4459 | 0 | 0U, // A2_pxorfnew |
4460 | 0 | 0U, // A2_pxort |
4461 | 0 | 0U, // A2_pxortnew |
4462 | 0 | 0U, // A2_roundsat |
4463 | 0 | 0U, // A2_sat |
4464 | 0 | 0U, // A2_satb |
4465 | 0 | 0U, // A2_sath |
4466 | 0 | 0U, // A2_satub |
4467 | 0 | 0U, // A2_satuh |
4468 | 0 | 0U, // A2_sub |
4469 | 0 | 718U, // A2_subh_h16_hh |
4470 | 0 | 782U, // A2_subh_h16_hl |
4471 | 0 | 719U, // A2_subh_h16_lh |
4472 | 0 | 783U, // A2_subh_h16_ll |
4473 | 0 | 846U, // A2_subh_h16_sat_hh |
4474 | 0 | 910U, // A2_subh_h16_sat_hl |
4475 | 0 | 847U, // A2_subh_h16_sat_lh |
4476 | 0 | 911U, // A2_subh_h16_sat_ll |
4477 | 0 | 975U, // A2_subh_l16_hl |
4478 | 0 | 1039U, // A2_subh_l16_ll |
4479 | 0 | 1103U, // A2_subh_l16_sat_hl |
4480 | 0 | 1167U, // A2_subh_l16_sat_ll |
4481 | 0 | 0U, // A2_subp |
4482 | 0 | 66U, // A2_subri |
4483 | 0 | 20480U, // A2_subsat |
4484 | 0 | 0U, // A2_svaddh |
4485 | 0 | 0U, // A2_svaddhs |
4486 | 0 | 0U, // A2_svadduhs |
4487 | 0 | 0U, // A2_svavgh |
4488 | 0 | 0U, // A2_svavghs |
4489 | 0 | 0U, // A2_svnavgh |
4490 | 0 | 0U, // A2_svsubh |
4491 | 0 | 0U, // A2_svsubhs |
4492 | 0 | 0U, // A2_svsubuhs |
4493 | 0 | 0U, // A2_swiz |
4494 | 0 | 0U, // A2_sxtb |
4495 | 0 | 0U, // A2_sxth |
4496 | 0 | 0U, // A2_sxtw |
4497 | 0 | 0U, // A2_tfr |
4498 | 0 | 0U, // A2_tfrcrr |
4499 | 0 | 16U, // A2_tfrih |
4500 | 0 | 16U, // A2_tfril |
4501 | 0 | 0U, // A2_tfrrcr |
4502 | 0 | 0U, // A2_tfrsi |
4503 | 0 | 0U, // A2_vabsh |
4504 | 0 | 0U, // A2_vabshsat |
4505 | 0 | 0U, // A2_vabsw |
4506 | 0 | 0U, // A2_vabswsat |
4507 | 0 | 0U, // A2_vaddh |
4508 | 0 | 0U, // A2_vaddhs |
4509 | 0 | 0U, // A2_vaddub |
4510 | 0 | 0U, // A2_vaddubs |
4511 | 0 | 0U, // A2_vadduhs |
4512 | 0 | 0U, // A2_vaddw |
4513 | 0 | 0U, // A2_vaddws |
4514 | 0 | 0U, // A2_vavgh |
4515 | 0 | 0U, // A2_vavghcr |
4516 | 0 | 0U, // A2_vavghr |
4517 | 0 | 0U, // A2_vavgub |
4518 | 0 | 0U, // A2_vavgubr |
4519 | 0 | 0U, // A2_vavguh |
4520 | 0 | 0U, // A2_vavguhr |
4521 | 0 | 0U, // A2_vavguw |
4522 | 0 | 0U, // A2_vavguwr |
4523 | 0 | 0U, // A2_vavgw |
4524 | 0 | 0U, // A2_vavgwcr |
4525 | 0 | 0U, // A2_vavgwr |
4526 | 0 | 66U, // A2_vcmpbeq |
4527 | 0 | 66U, // A2_vcmpbgtu |
4528 | 0 | 66U, // A2_vcmpheq |
4529 | 0 | 66U, // A2_vcmphgt |
4530 | 0 | 66U, // A2_vcmphgtu |
4531 | 0 | 66U, // A2_vcmpweq |
4532 | 0 | 66U, // A2_vcmpwgt |
4533 | 0 | 66U, // A2_vcmpwgtu |
4534 | 0 | 0U, // A2_vconj |
4535 | 0 | 0U, // A2_vmaxb |
4536 | 0 | 0U, // A2_vmaxh |
4537 | 0 | 0U, // A2_vmaxub |
4538 | 0 | 0U, // A2_vmaxuh |
4539 | 0 | 0U, // A2_vmaxuw |
4540 | 0 | 0U, // A2_vmaxw |
4541 | 0 | 0U, // A2_vminb |
4542 | 0 | 0U, // A2_vminh |
4543 | 0 | 0U, // A2_vminub |
4544 | 0 | 0U, // A2_vminuh |
4545 | 0 | 0U, // A2_vminuw |
4546 | 0 | 0U, // A2_vminw |
4547 | 0 | 0U, // A2_vnavgh |
4548 | 0 | 0U, // A2_vnavghcr |
4549 | 0 | 0U, // A2_vnavghr |
4550 | 0 | 0U, // A2_vnavgw |
4551 | 0 | 0U, // A2_vnavgwcr |
4552 | 0 | 0U, // A2_vnavgwr |
4553 | 0 | 0U, // A2_vraddub |
4554 | 0 | 0U, // A2_vraddub_acc |
4555 | 0 | 0U, // A2_vrsadub |
4556 | 0 | 0U, // A2_vrsadub_acc |
4557 | 0 | 0U, // A2_vsubh |
4558 | 0 | 0U, // A2_vsubhs |
4559 | 0 | 0U, // A2_vsubub |
4560 | 0 | 0U, // A2_vsububs |
4561 | 0 | 0U, // A2_vsubuhs |
4562 | 0 | 0U, // A2_vsubw |
4563 | 0 | 0U, // A2_vsubws |
4564 | 0 | 0U, // A2_xor |
4565 | 0 | 0U, // A2_xorp |
4566 | 0 | 0U, // A2_zxth |
4567 | 0 | 33984U, // A4_addp_c |
4568 | 0 | 66U, // A4_andn |
4569 | 0 | 66U, // A4_andnp |
4570 | 0 | 66U, // A4_bitsplit |
4571 | 0 | 66U, // A4_bitspliti |
4572 | 0 | 0U, // A4_boundscheck_hi |
4573 | 0 | 0U, // A4_boundscheck_lo |
4574 | 0 | 66U, // A4_cmpbeq |
4575 | 0 | 66U, // A4_cmpbeqi |
4576 | 0 | 66U, // A4_cmpbgt |
4577 | 0 | 66U, // A4_cmpbgti |
4578 | 0 | 66U, // A4_cmpbgtu |
4579 | 0 | 66U, // A4_cmpbgtui |
4580 | 0 | 66U, // A4_cmpheq |
4581 | 0 | 66U, // A4_cmpheqi |
4582 | 0 | 66U, // A4_cmphgt |
4583 | 0 | 66U, // A4_cmphgti |
4584 | 0 | 66U, // A4_cmphgtu |
4585 | 0 | 66U, // A4_cmphgtui |
4586 | 0 | 66U, // A4_combineii |
4587 | 0 | 66U, // A4_combineir |
4588 | 0 | 66U, // A4_combineri |
4589 | 0 | 66U, // A4_cround_ri |
4590 | 0 | 66U, // A4_cround_rr |
4591 | 0 | 0U, // A4_ext |
4592 | 0 | 0U, // A4_modwrapu |
4593 | 0 | 66U, // A4_orn |
4594 | 0 | 66U, // A4_ornp |
4595 | 0 | 0U, // A4_paslhf |
4596 | 0 | 0U, // A4_paslhfnew |
4597 | 0 | 0U, // A4_paslht |
4598 | 0 | 0U, // A4_paslhtnew |
4599 | 0 | 0U, // A4_pasrhf |
4600 | 0 | 0U, // A4_pasrhfnew |
4601 | 0 | 0U, // A4_pasrht |
4602 | 0 | 0U, // A4_pasrhtnew |
4603 | 0 | 0U, // A4_psxtbf |
4604 | 0 | 0U, // A4_psxtbfnew |
4605 | 0 | 0U, // A4_psxtbt |
4606 | 0 | 0U, // A4_psxtbtnew |
4607 | 0 | 0U, // A4_psxthf |
4608 | 0 | 0U, // A4_psxthfnew |
4609 | 0 | 0U, // A4_psxtht |
4610 | 0 | 0U, // A4_psxthtnew |
4611 | 0 | 0U, // A4_pzxtbf |
4612 | 0 | 0U, // A4_pzxtbfnew |
4613 | 0 | 0U, // A4_pzxtbt |
4614 | 0 | 0U, // A4_pzxtbtnew |
4615 | 0 | 0U, // A4_pzxthf |
4616 | 0 | 0U, // A4_pzxthfnew |
4617 | 0 | 0U, // A4_pzxtht |
4618 | 0 | 0U, // A4_pzxthtnew |
4619 | 0 | 66U, // A4_rcmpeq |
4620 | 0 | 66U, // A4_rcmpeqi |
4621 | 0 | 66U, // A4_rcmpneq |
4622 | 0 | 66U, // A4_rcmpneqi |
4623 | 0 | 66U, // A4_round_ri |
4624 | 0 | 1282U, // A4_round_ri_sat |
4625 | 0 | 66U, // A4_round_rr |
4626 | 0 | 1282U, // A4_round_rr_sat |
4627 | 0 | 33984U, // A4_subp_c |
4628 | 0 | 0U, // A4_tfrcpp |
4629 | 0 | 0U, // A4_tfrpcp |
4630 | 0 | 0U, // A4_tlbmatch |
4631 | 0 | 0U, // A4_vcmpbeq_any |
4632 | 0 | 66U, // A4_vcmpbeqi |
4633 | 0 | 66U, // A4_vcmpbgt |
4634 | 0 | 66U, // A4_vcmpbgti |
4635 | 0 | 66U, // A4_vcmpbgtui |
4636 | 0 | 66U, // A4_vcmpheqi |
4637 | 0 | 66U, // A4_vcmphgti |
4638 | 0 | 66U, // A4_vcmphgtui |
4639 | 0 | 66U, // A4_vcmpweqi |
4640 | 0 | 66U, // A4_vcmpwgti |
4641 | 0 | 66U, // A4_vcmpwgtui |
4642 | 0 | 0U, // A4_vrmaxh |
4643 | 0 | 0U, // A4_vrmaxuh |
4644 | 0 | 0U, // A4_vrmaxuw |
4645 | 0 | 0U, // A4_vrmaxw |
4646 | 0 | 0U, // A4_vrminh |
4647 | 0 | 0U, // A4_vrminuh |
4648 | 0 | 0U, // A4_vrminuw |
4649 | 0 | 0U, // A4_vrminw |
4650 | 0 | 17U, // A5_ACS |
4651 | 0 | 0U, // A5_vaddhubs |
4652 | 0 | 0U, // A6_vcmpbeq_notany |
4653 | 0 | 18U, // A6_vminub_RdP |
4654 | 0 | 0U, // A7_clip |
4655 | 0 | 66U, // A7_croundd_ri |
4656 | 0 | 66U, // A7_croundd_rr |
4657 | 0 | 0U, // A7_vclip |
4658 | 0 | 0U, // C2_all8 |
4659 | 0 | 66U, // C2_and |
4660 | 0 | 0U, // C2_andn |
4661 | 0 | 0U, // C2_any8 |
4662 | 0 | 66U, // C2_bitsclr |
4663 | 0 | 66U, // C2_bitsclri |
4664 | 0 | 0U, // C2_bitsset |
4665 | 0 | 0U, // C2_ccombinewf |
4666 | 0 | 0U, // C2_ccombinewnewf |
4667 | 0 | 0U, // C2_ccombinewnewt |
4668 | 0 | 0U, // C2_ccombinewt |
4669 | 0 | 0U, // C2_cmoveif |
4670 | 0 | 0U, // C2_cmoveit |
4671 | 0 | 0U, // C2_cmovenewif |
4672 | 0 | 0U, // C2_cmovenewit |
4673 | 0 | 66U, // C2_cmpeq |
4674 | 0 | 66U, // C2_cmpeqi |
4675 | 0 | 66U, // C2_cmpeqp |
4676 | 0 | 66U, // C2_cmpgt |
4677 | 0 | 66U, // C2_cmpgti |
4678 | 0 | 66U, // C2_cmpgtp |
4679 | 0 | 66U, // C2_cmpgtu |
4680 | 0 | 66U, // C2_cmpgtui |
4681 | 0 | 66U, // C2_cmpgtup |
4682 | 0 | 0U, // C2_mask |
4683 | 0 | 1346U, // C2_mux |
4684 | 0 | 38274U, // C2_muxii |
4685 | 0 | 38274U, // C2_muxir |
4686 | 0 | 1346U, // C2_muxri |
4687 | 0 | 0U, // C2_not |
4688 | 0 | 66U, // C2_or |
4689 | 0 | 0U, // C2_orn |
4690 | 0 | 0U, // C2_tfrpr |
4691 | 0 | 0U, // C2_tfrrp |
4692 | 0 | 0U, // C2_vitpack |
4693 | 0 | 0U, // C2_vmux |
4694 | 0 | 0U, // C2_xor |
4695 | 0 | 0U, // C4_addipc |
4696 | 0 | 42176U, // C4_and_and |
4697 | 0 | 19U, // C4_and_andn |
4698 | 0 | 42176U, // C4_and_or |
4699 | 0 | 19U, // C4_and_orn |
4700 | 0 | 66U, // C4_cmplte |
4701 | 0 | 66U, // C4_cmpltei |
4702 | 0 | 66U, // C4_cmplteu |
4703 | 0 | 66U, // C4_cmplteui |
4704 | 0 | 66U, // C4_cmpneq |
4705 | 0 | 66U, // C4_cmpneqi |
4706 | 0 | 0U, // C4_fastcorner9 |
4707 | 0 | 0U, // C4_fastcorner9_not |
4708 | 0 | 66U, // C4_nbitsclr |
4709 | 0 | 66U, // C4_nbitsclri |
4710 | 0 | 0U, // C4_nbitsset |
4711 | 0 | 42176U, // C4_or_and |
4712 | 0 | 19U, // C4_or_andn |
4713 | 0 | 42176U, // C4_or_or |
4714 | 0 | 19U, // C4_or_orn |
4715 | 0 | 0U, // CALLProfile |
4716 | 0 | 0U, // CONST32 |
4717 | 0 | 0U, // CONST64 |
4718 | 0 | 0U, // DuplexIClass0 |
4719 | 0 | 0U, // DuplexIClass1 |
4720 | 0 | 0U, // DuplexIClass2 |
4721 | 0 | 0U, // DuplexIClass3 |
4722 | 0 | 0U, // DuplexIClass4 |
4723 | 0 | 0U, // DuplexIClass5 |
4724 | 0 | 0U, // DuplexIClass6 |
4725 | 0 | 0U, // DuplexIClass7 |
4726 | 0 | 0U, // DuplexIClass8 |
4727 | 0 | 0U, // DuplexIClass9 |
4728 | 0 | 0U, // DuplexIClassA |
4729 | 0 | 0U, // DuplexIClassB |
4730 | 0 | 0U, // DuplexIClassC |
4731 | 0 | 0U, // DuplexIClassD |
4732 | 0 | 0U, // DuplexIClassE |
4733 | 0 | 0U, // DuplexIClassF |
4734 | 0 | 0U, // EH_RETURN_JMPR |
4735 | 0 | 0U, // F2_conv_d2df |
4736 | 0 | 0U, // F2_conv_d2sf |
4737 | 0 | 0U, // F2_conv_df2d |
4738 | 0 | 0U, // F2_conv_df2d_chop |
4739 | 0 | 0U, // F2_conv_df2sf |
4740 | 0 | 0U, // F2_conv_df2ud |
4741 | 0 | 0U, // F2_conv_df2ud_chop |
4742 | 0 | 0U, // F2_conv_df2uw |
4743 | 0 | 0U, // F2_conv_df2uw_chop |
4744 | 0 | 0U, // F2_conv_df2w |
4745 | 0 | 0U, // F2_conv_df2w_chop |
4746 | 0 | 0U, // F2_conv_sf2d |
4747 | 0 | 0U, // F2_conv_sf2d_chop |
4748 | 0 | 0U, // F2_conv_sf2df |
4749 | 0 | 0U, // F2_conv_sf2ud |
4750 | 0 | 0U, // F2_conv_sf2ud_chop |
4751 | 0 | 0U, // F2_conv_sf2uw |
4752 | 0 | 0U, // F2_conv_sf2uw_chop |
4753 | 0 | 0U, // F2_conv_sf2w |
4754 | 0 | 0U, // F2_conv_sf2w_chop |
4755 | 0 | 0U, // F2_conv_ud2df |
4756 | 0 | 0U, // F2_conv_ud2sf |
4757 | 0 | 0U, // F2_conv_uw2df |
4758 | 0 | 0U, // F2_conv_uw2sf |
4759 | 0 | 0U, // F2_conv_w2df |
4760 | 0 | 0U, // F2_conv_w2sf |
4761 | 0 | 0U, // F2_dfadd |
4762 | 0 | 0U, // F2_dfclass |
4763 | 0 | 0U, // F2_dfcmpeq |
4764 | 0 | 0U, // F2_dfcmpge |
4765 | 0 | 0U, // F2_dfcmpgt |
4766 | 0 | 0U, // F2_dfcmpuo |
4767 | 0 | 0U, // F2_dfimm_n |
4768 | 0 | 0U, // F2_dfimm_p |
4769 | 0 | 0U, // F2_dfmax |
4770 | 0 | 0U, // F2_dfmin |
4771 | 0 | 0U, // F2_dfmpyfix |
4772 | 0 | 0U, // F2_dfmpyhh |
4773 | 0 | 0U, // F2_dfmpylh |
4774 | 0 | 0U, // F2_dfmpyll |
4775 | 0 | 0U, // F2_dfsub |
4776 | 0 | 0U, // F2_sfadd |
4777 | 0 | 0U, // F2_sfclass |
4778 | 0 | 0U, // F2_sfcmpeq |
4779 | 0 | 0U, // F2_sfcmpge |
4780 | 0 | 0U, // F2_sfcmpgt |
4781 | 0 | 0U, // F2_sfcmpuo |
4782 | 0 | 0U, // F2_sffixupd |
4783 | 0 | 0U, // F2_sffixupn |
4784 | 0 | 0U, // F2_sffixupr |
4785 | 0 | 0U, // F2_sffma |
4786 | 0 | 0U, // F2_sffma_lib |
4787 | 0 | 1481U, // F2_sffma_sc |
4788 | 0 | 0U, // F2_sffms |
4789 | 0 | 0U, // F2_sffms_lib |
4790 | 0 | 0U, // F2_sfimm_n |
4791 | 0 | 0U, // F2_sfimm_p |
4792 | 0 | 20U, // F2_sfinvsqrta |
4793 | 0 | 0U, // F2_sfmax |
4794 | 0 | 0U, // F2_sfmin |
4795 | 0 | 0U, // F2_sfmpy |
4796 | 0 | 21U, // F2_sfrecipa |
4797 | 0 | 0U, // F2_sfsub |
4798 | 0 | 0U, // G4_tfrgcpp |
4799 | 0 | 0U, // G4_tfrgcrr |
4800 | 0 | 0U, // G4_tfrgpcp |
4801 | 0 | 0U, // G4_tfrgrcr |
4802 | 0 | 16U, // HI |
4803 | 0 | 0U, // J2_call |
4804 | 0 | 0U, // J2_callf |
4805 | 0 | 0U, // J2_callr |
4806 | 0 | 0U, // J2_callrf |
4807 | 0 | 0U, // J2_callrh |
4808 | 0 | 0U, // J2_callrt |
4809 | 0 | 0U, // J2_callt |
4810 | 0 | 0U, // J2_jump |
4811 | 0 | 0U, // J2_jumpf |
4812 | 0 | 0U, // J2_jumpfnew |
4813 | 0 | 0U, // J2_jumpfnewpt |
4814 | 0 | 0U, // J2_jumpfpt |
4815 | 0 | 0U, // J2_jumpr |
4816 | 0 | 0U, // J2_jumprf |
4817 | 0 | 0U, // J2_jumprfnew |
4818 | 0 | 0U, // J2_jumprfnewpt |
4819 | 0 | 0U, // J2_jumprfpt |
4820 | 0 | 0U, // J2_jumprgtez |
4821 | 0 | 0U, // J2_jumprgtezpt |
4822 | 0 | 0U, // J2_jumprh |
4823 | 0 | 0U, // J2_jumprltez |
4824 | 0 | 0U, // J2_jumprltezpt |
4825 | 0 | 0U, // J2_jumprnz |
4826 | 0 | 0U, // J2_jumprnzpt |
4827 | 0 | 0U, // J2_jumprt |
4828 | 0 | 0U, // J2_jumprtnew |
4829 | 0 | 0U, // J2_jumprtnewpt |
4830 | 0 | 0U, // J2_jumprtpt |
4831 | 0 | 0U, // J2_jumprz |
4832 | 0 | 0U, // J2_jumprzpt |
4833 | 0 | 0U, // J2_jumpt |
4834 | 0 | 0U, // J2_jumptnew |
4835 | 0 | 0U, // J2_jumptnewpt |
4836 | 0 | 0U, // J2_jumptpt |
4837 | 0 | 1U, // J2_loop0i |
4838 | 0 | 1U, // J2_loop0iext |
4839 | 0 | 1U, // J2_loop0r |
4840 | 0 | 1U, // J2_loop0rext |
4841 | 0 | 1U, // J2_loop1i |
4842 | 0 | 1U, // J2_loop1iext |
4843 | 0 | 1U, // J2_loop1r |
4844 | 0 | 1U, // J2_loop1rext |
4845 | 0 | 0U, // J2_pause |
4846 | 0 | 1U, // J2_ploop1si |
4847 | 0 | 1U, // J2_ploop1sr |
4848 | 0 | 1U, // J2_ploop2si |
4849 | 0 | 1U, // J2_ploop2sr |
4850 | 0 | 1U, // J2_ploop3si |
4851 | 0 | 1U, // J2_ploop3sr |
4852 | 0 | 0U, // J2_rte |
4853 | 0 | 0U, // J2_trap0 |
4854 | 0 | 1U, // J2_trap1 |
4855 | 0 | 0U, // J2_unpause |
4856 | 0 | 0U, // J4_cmpeq_f_jumpnv_nt |
4857 | 0 | 0U, // J4_cmpeq_f_jumpnv_t |
4858 | 0 | 22U, // J4_cmpeq_fp0_jump_nt |
4859 | 0 | 23U, // J4_cmpeq_fp0_jump_t |
4860 | 0 | 24U, // J4_cmpeq_fp1_jump_nt |
4861 | 0 | 25U, // J4_cmpeq_fp1_jump_t |
4862 | 0 | 0U, // J4_cmpeq_t_jumpnv_nt |
4863 | 0 | 0U, // J4_cmpeq_t_jumpnv_t |
4864 | 0 | 26U, // J4_cmpeq_tp0_jump_nt |
4865 | 0 | 27U, // J4_cmpeq_tp0_jump_t |
4866 | 0 | 28U, // J4_cmpeq_tp1_jump_nt |
4867 | 0 | 29U, // J4_cmpeq_tp1_jump_t |
4868 | 0 | 0U, // J4_cmpeqi_f_jumpnv_nt |
4869 | 0 | 0U, // J4_cmpeqi_f_jumpnv_t |
4870 | 0 | 22U, // J4_cmpeqi_fp0_jump_nt |
4871 | 0 | 23U, // J4_cmpeqi_fp0_jump_t |
4872 | 0 | 24U, // J4_cmpeqi_fp1_jump_nt |
4873 | 0 | 25U, // J4_cmpeqi_fp1_jump_t |
4874 | 0 | 0U, // J4_cmpeqi_t_jumpnv_nt |
4875 | 0 | 0U, // J4_cmpeqi_t_jumpnv_t |
4876 | 0 | 26U, // J4_cmpeqi_tp0_jump_nt |
4877 | 0 | 27U, // J4_cmpeqi_tp0_jump_t |
4878 | 0 | 28U, // J4_cmpeqi_tp1_jump_nt |
4879 | 0 | 29U, // J4_cmpeqi_tp1_jump_t |
4880 | 0 | 0U, // J4_cmpeqn1_f_jumpnv_nt |
4881 | 0 | 0U, // J4_cmpeqn1_f_jumpnv_t |
4882 | 0 | 22U, // J4_cmpeqn1_fp0_jump_nt |
4883 | 0 | 23U, // J4_cmpeqn1_fp0_jump_t |
4884 | 0 | 24U, // J4_cmpeqn1_fp1_jump_nt |
4885 | 0 | 25U, // J4_cmpeqn1_fp1_jump_t |
4886 | 0 | 0U, // J4_cmpeqn1_t_jumpnv_nt |
4887 | 0 | 0U, // J4_cmpeqn1_t_jumpnv_t |
4888 | 0 | 26U, // J4_cmpeqn1_tp0_jump_nt |
4889 | 0 | 27U, // J4_cmpeqn1_tp0_jump_t |
4890 | 0 | 28U, // J4_cmpeqn1_tp1_jump_nt |
4891 | 0 | 29U, // J4_cmpeqn1_tp1_jump_t |
4892 | 0 | 0U, // J4_cmpgt_f_jumpnv_nt |
4893 | 0 | 0U, // J4_cmpgt_f_jumpnv_t |
4894 | 0 | 22U, // J4_cmpgt_fp0_jump_nt |
4895 | 0 | 23U, // J4_cmpgt_fp0_jump_t |
4896 | 0 | 24U, // J4_cmpgt_fp1_jump_nt |
4897 | 0 | 25U, // J4_cmpgt_fp1_jump_t |
4898 | 0 | 0U, // J4_cmpgt_t_jumpnv_nt |
4899 | 0 | 0U, // J4_cmpgt_t_jumpnv_t |
4900 | 0 | 26U, // J4_cmpgt_tp0_jump_nt |
4901 | 0 | 27U, // J4_cmpgt_tp0_jump_t |
4902 | 0 | 28U, // J4_cmpgt_tp1_jump_nt |
4903 | 0 | 29U, // J4_cmpgt_tp1_jump_t |
4904 | 0 | 0U, // J4_cmpgti_f_jumpnv_nt |
4905 | 0 | 0U, // J4_cmpgti_f_jumpnv_t |
4906 | 0 | 22U, // J4_cmpgti_fp0_jump_nt |
4907 | 0 | 23U, // J4_cmpgti_fp0_jump_t |
4908 | 0 | 24U, // J4_cmpgti_fp1_jump_nt |
4909 | 0 | 25U, // J4_cmpgti_fp1_jump_t |
4910 | 0 | 0U, // J4_cmpgti_t_jumpnv_nt |
4911 | 0 | 0U, // J4_cmpgti_t_jumpnv_t |
4912 | 0 | 26U, // J4_cmpgti_tp0_jump_nt |
4913 | 0 | 27U, // J4_cmpgti_tp0_jump_t |
4914 | 0 | 28U, // J4_cmpgti_tp1_jump_nt |
4915 | 0 | 29U, // J4_cmpgti_tp1_jump_t |
4916 | 0 | 0U, // J4_cmpgtn1_f_jumpnv_nt |
4917 | 0 | 0U, // J4_cmpgtn1_f_jumpnv_t |
4918 | 0 | 22U, // J4_cmpgtn1_fp0_jump_nt |
4919 | 0 | 23U, // J4_cmpgtn1_fp0_jump_t |
4920 | 0 | 24U, // J4_cmpgtn1_fp1_jump_nt |
4921 | 0 | 25U, // J4_cmpgtn1_fp1_jump_t |
4922 | 0 | 0U, // J4_cmpgtn1_t_jumpnv_nt |
4923 | 0 | 0U, // J4_cmpgtn1_t_jumpnv_t |
4924 | 0 | 26U, // J4_cmpgtn1_tp0_jump_nt |
4925 | 0 | 27U, // J4_cmpgtn1_tp0_jump_t |
4926 | 0 | 28U, // J4_cmpgtn1_tp1_jump_nt |
4927 | 0 | 29U, // J4_cmpgtn1_tp1_jump_t |
4928 | 0 | 0U, // J4_cmpgtu_f_jumpnv_nt |
4929 | 0 | 0U, // J4_cmpgtu_f_jumpnv_t |
4930 | 0 | 22U, // J4_cmpgtu_fp0_jump_nt |
4931 | 0 | 23U, // J4_cmpgtu_fp0_jump_t |
4932 | 0 | 24U, // J4_cmpgtu_fp1_jump_nt |
4933 | 0 | 25U, // J4_cmpgtu_fp1_jump_t |
4934 | 0 | 0U, // J4_cmpgtu_t_jumpnv_nt |
4935 | 0 | 0U, // J4_cmpgtu_t_jumpnv_t |
4936 | 0 | 26U, // J4_cmpgtu_tp0_jump_nt |
4937 | 0 | 27U, // J4_cmpgtu_tp0_jump_t |
4938 | 0 | 28U, // J4_cmpgtu_tp1_jump_nt |
4939 | 0 | 29U, // J4_cmpgtu_tp1_jump_t |
4940 | 0 | 0U, // J4_cmpgtui_f_jumpnv_nt |
4941 | 0 | 0U, // J4_cmpgtui_f_jumpnv_t |
4942 | 0 | 22U, // J4_cmpgtui_fp0_jump_nt |
4943 | 0 | 23U, // J4_cmpgtui_fp0_jump_t |
4944 | 0 | 24U, // J4_cmpgtui_fp1_jump_nt |
4945 | 0 | 25U, // J4_cmpgtui_fp1_jump_t |
4946 | 0 | 0U, // J4_cmpgtui_t_jumpnv_nt |
4947 | 0 | 0U, // J4_cmpgtui_t_jumpnv_t |
4948 | 0 | 26U, // J4_cmpgtui_tp0_jump_nt |
4949 | 0 | 27U, // J4_cmpgtui_tp0_jump_t |
4950 | 0 | 28U, // J4_cmpgtui_tp1_jump_nt |
4951 | 0 | 29U, // J4_cmpgtui_tp1_jump_t |
4952 | 0 | 30U, // J4_cmplt_f_jumpnv_nt |
4953 | 0 | 31U, // J4_cmplt_f_jumpnv_t |
4954 | 0 | 30U, // J4_cmplt_t_jumpnv_nt |
4955 | 0 | 31U, // J4_cmplt_t_jumpnv_t |
4956 | 0 | 30U, // J4_cmpltu_f_jumpnv_nt |
4957 | 0 | 31U, // J4_cmpltu_f_jumpnv_t |
4958 | 0 | 30U, // J4_cmpltu_t_jumpnv_nt |
4959 | 0 | 31U, // J4_cmpltu_t_jumpnv_t |
4960 | 0 | 0U, // J4_hintjumpr |
4961 | 0 | 0U, // J4_jumpseti |
4962 | 0 | 0U, // J4_jumpsetr |
4963 | 0 | 0U, // J4_tstbit0_f_jumpnv_nt |
4964 | 0 | 0U, // J4_tstbit0_f_jumpnv_t |
4965 | 0 | 0U, // J4_tstbit0_fp0_jump_nt |
4966 | 0 | 0U, // J4_tstbit0_fp0_jump_t |
4967 | 0 | 0U, // J4_tstbit0_fp1_jump_nt |
4968 | 0 | 0U, // J4_tstbit0_fp1_jump_t |
4969 | 0 | 0U, // J4_tstbit0_t_jumpnv_nt |
4970 | 0 | 0U, // J4_tstbit0_t_jumpnv_t |
4971 | 0 | 0U, // J4_tstbit0_tp0_jump_nt |
4972 | 0 | 0U, // J4_tstbit0_tp0_jump_t |
4973 | 0 | 0U, // J4_tstbit0_tp1_jump_nt |
4974 | 0 | 0U, // J4_tstbit0_tp1_jump_t |
4975 | 0 | 0U, // L2_deallocframe |
4976 | 0 | 1248U, // L2_loadalignb_io |
4977 | 0 | 45729U, // L2_loadalignb_pbr |
4978 | 0 | 49826U, // L2_loadalignb_pci |
4979 | 0 | 35U, // L2_loadalignb_pcr |
4980 | 0 | 674U, // L2_loadalignb_pi |
4981 | 0 | 673U, // L2_loadalignb_pr |
4982 | 0 | 1248U, // L2_loadalignh_io |
4983 | 0 | 45729U, // L2_loadalignh_pbr |
4984 | 0 | 49826U, // L2_loadalignh_pci |
4985 | 0 | 35U, // L2_loadalignh_pcr |
4986 | 0 | 674U, // L2_loadalignh_pi |
4987 | 0 | 673U, // L2_loadalignh_pr |
4988 | 0 | 1U, // L2_loadbsw2_io |
4989 | 0 | 36U, // L2_loadbsw2_pbr |
4990 | 0 | 37U, // L2_loadbsw2_pci |
4991 | 0 | 0U, // L2_loadbsw2_pcr |
4992 | 0 | 1U, // L2_loadbsw2_pi |
4993 | 0 | 1U, // L2_loadbsw2_pr |
4994 | 0 | 1U, // L2_loadbsw4_io |
4995 | 0 | 36U, // L2_loadbsw4_pbr |
4996 | 0 | 37U, // L2_loadbsw4_pci |
4997 | 0 | 0U, // L2_loadbsw4_pcr |
4998 | 0 | 1U, // L2_loadbsw4_pi |
4999 | 0 | 1U, // L2_loadbsw4_pr |
5000 | 0 | 1U, // L2_loadbzw2_io |
5001 | 0 | 36U, // L2_loadbzw2_pbr |
5002 | 0 | 37U, // L2_loadbzw2_pci |
5003 | 0 | 0U, // L2_loadbzw2_pcr |
5004 | 0 | 1U, // L2_loadbzw2_pi |
5005 | 0 | 1U, // L2_loadbzw2_pr |
5006 | 0 | 1U, // L2_loadbzw4_io |
5007 | 0 | 36U, // L2_loadbzw4_pbr |
5008 | 0 | 37U, // L2_loadbzw4_pci |
5009 | 0 | 0U, // L2_loadbzw4_pcr |
5010 | 0 | 1U, // L2_loadbzw4_pi |
5011 | 0 | 1U, // L2_loadbzw4_pr |
5012 | 0 | 1U, // L2_loadrb_io |
5013 | 0 | 36U, // L2_loadrb_pbr |
5014 | 0 | 37U, // L2_loadrb_pci |
5015 | 0 | 0U, // L2_loadrb_pcr |
5016 | 0 | 1U, // L2_loadrb_pi |
5017 | 0 | 1U, // L2_loadrb_pr |
5018 | 0 | 0U, // L2_loadrbgp |
5019 | 0 | 1U, // L2_loadrd_io |
5020 | 0 | 36U, // L2_loadrd_pbr |
5021 | 0 | 37U, // L2_loadrd_pci |
5022 | 0 | 0U, // L2_loadrd_pcr |
5023 | 0 | 1U, // L2_loadrd_pi |
5024 | 0 | 1U, // L2_loadrd_pr |
5025 | 0 | 0U, // L2_loadrdgp |
5026 | 0 | 1U, // L2_loadrh_io |
5027 | 0 | 36U, // L2_loadrh_pbr |
5028 | 0 | 37U, // L2_loadrh_pci |
5029 | 0 | 0U, // L2_loadrh_pcr |
5030 | 0 | 1U, // L2_loadrh_pi |
5031 | 0 | 1U, // L2_loadrh_pr |
5032 | 0 | 0U, // L2_loadrhgp |
5033 | 0 | 1U, // L2_loadri_io |
5034 | 0 | 36U, // L2_loadri_pbr |
5035 | 0 | 37U, // L2_loadri_pci |
5036 | 0 | 0U, // L2_loadri_pcr |
5037 | 0 | 1U, // L2_loadri_pi |
5038 | 0 | 1U, // L2_loadri_pr |
5039 | 0 | 0U, // L2_loadrigp |
5040 | 0 | 1U, // L2_loadrub_io |
5041 | 0 | 36U, // L2_loadrub_pbr |
5042 | 0 | 37U, // L2_loadrub_pci |
5043 | 0 | 0U, // L2_loadrub_pcr |
5044 | 0 | 1U, // L2_loadrub_pi |
5045 | 0 | 1U, // L2_loadrub_pr |
5046 | 0 | 0U, // L2_loadrubgp |
5047 | 0 | 1U, // L2_loadruh_io |
5048 | 0 | 36U, // L2_loadruh_pbr |
5049 | 0 | 37U, // L2_loadruh_pci |
5050 | 0 | 0U, // L2_loadruh_pcr |
5051 | 0 | 1U, // L2_loadruh_pi |
5052 | 0 | 1U, // L2_loadruh_pr |
5053 | 0 | 0U, // L2_loadruhgp |
5054 | 0 | 0U, // L2_loadw_aq |
5055 | 0 | 0U, // L2_loadw_locked |
5056 | 0 | 1538U, // L2_ploadrbf_io |
5057 | 0 | 1638U, // L2_ploadrbf_pi |
5058 | 0 | 1538U, // L2_ploadrbfnew_io |
5059 | 0 | 1638U, // L2_ploadrbfnew_pi |
5060 | 0 | 1538U, // L2_ploadrbt_io |
5061 | 0 | 1638U, // L2_ploadrbt_pi |
5062 | 0 | 1538U, // L2_ploadrbtnew_io |
5063 | 0 | 1638U, // L2_ploadrbtnew_pi |
5064 | 0 | 1538U, // L2_ploadrdf_io |
5065 | 0 | 1638U, // L2_ploadrdf_pi |
5066 | 0 | 1538U, // L2_ploadrdfnew_io |
5067 | 0 | 1638U, // L2_ploadrdfnew_pi |
5068 | 0 | 1538U, // L2_ploadrdt_io |
5069 | 0 | 1638U, // L2_ploadrdt_pi |
5070 | 0 | 1538U, // L2_ploadrdtnew_io |
5071 | 0 | 1638U, // L2_ploadrdtnew_pi |
5072 | 0 | 1538U, // L2_ploadrhf_io |
5073 | 0 | 1638U, // L2_ploadrhf_pi |
5074 | 0 | 1538U, // L2_ploadrhfnew_io |
5075 | 0 | 1638U, // L2_ploadrhfnew_pi |
5076 | 0 | 1538U, // L2_ploadrht_io |
5077 | 0 | 1638U, // L2_ploadrht_pi |
5078 | 0 | 1538U, // L2_ploadrhtnew_io |
5079 | 0 | 1638U, // L2_ploadrhtnew_pi |
5080 | 0 | 1538U, // L2_ploadrif_io |
5081 | 0 | 1638U, // L2_ploadrif_pi |
5082 | 0 | 1538U, // L2_ploadrifnew_io |
5083 | 0 | 1638U, // L2_ploadrifnew_pi |
5084 | 0 | 1538U, // L2_ploadrit_io |
5085 | 0 | 1638U, // L2_ploadrit_pi |
5086 | 0 | 1538U, // L2_ploadritnew_io |
5087 | 0 | 1638U, // L2_ploadritnew_pi |
5088 | 0 | 1538U, // L2_ploadrubf_io |
5089 | 0 | 1638U, // L2_ploadrubf_pi |
5090 | 0 | 1538U, // L2_ploadrubfnew_io |
5091 | 0 | 1638U, // L2_ploadrubfnew_pi |
5092 | 0 | 1538U, // L2_ploadrubt_io |
5093 | 0 | 1638U, // L2_ploadrubt_pi |
5094 | 0 | 1538U, // L2_ploadrubtnew_io |
5095 | 0 | 1638U, // L2_ploadrubtnew_pi |
5096 | 0 | 1538U, // L2_ploadruhf_io |
5097 | 0 | 1638U, // L2_ploadruhf_pi |
5098 | 0 | 1538U, // L2_ploadruhfnew_io |
5099 | 0 | 1638U, // L2_ploadruhfnew_pi |
5100 | 0 | 1538U, // L2_ploadruht_io |
5101 | 0 | 1638U, // L2_ploadruht_pi |
5102 | 0 | 1538U, // L2_ploadruhtnew_io |
5103 | 0 | 1638U, // L2_ploadruhtnew_pi |
5104 | 0 | 0U, // L4_add_memopb_io |
5105 | 0 | 0U, // L4_add_memoph_io |
5106 | 0 | 0U, // L4_add_memopw_io |
5107 | 0 | 0U, // L4_and_memopb_io |
5108 | 0 | 0U, // L4_and_memoph_io |
5109 | 0 | 0U, // L4_and_memopw_io |
5110 | 0 | 0U, // L4_iadd_memopb_io |
5111 | 0 | 0U, // L4_iadd_memoph_io |
5112 | 0 | 0U, // L4_iadd_memopw_io |
5113 | 0 | 0U, // L4_iand_memopb_io |
5114 | 0 | 0U, // L4_iand_memoph_io |
5115 | 0 | 0U, // L4_iand_memopw_io |
5116 | 0 | 0U, // L4_ior_memopb_io |
5117 | 0 | 0U, // L4_ior_memoph_io |
5118 | 0 | 0U, // L4_ior_memopw_io |
5119 | 0 | 0U, // L4_isub_memopb_io |
5120 | 0 | 0U, // L4_isub_memoph_io |
5121 | 0 | 0U, // L4_isub_memopw_io |
5122 | 0 | 39U, // L4_loadalignb_ap |
5123 | 0 | 40U, // L4_loadalignb_ur |
5124 | 0 | 39U, // L4_loadalignh_ap |
5125 | 0 | 40U, // L4_loadalignh_ur |
5126 | 0 | 0U, // L4_loadbsw2_ap |
5127 | 0 | 0U, // L4_loadbsw2_ur |
5128 | 0 | 0U, // L4_loadbsw4_ap |
5129 | 0 | 0U, // L4_loadbsw4_ur |
5130 | 0 | 0U, // L4_loadbzw2_ap |
5131 | 0 | 0U, // L4_loadbzw2_ur |
5132 | 0 | 0U, // L4_loadbzw4_ap |
5133 | 0 | 0U, // L4_loadbzw4_ur |
5134 | 0 | 0U, // L4_loadd_aq |
5135 | 0 | 0U, // L4_loadd_locked |
5136 | 0 | 0U, // L4_loadrb_ap |
5137 | 0 | 0U, // L4_loadrb_rr |
5138 | 0 | 0U, // L4_loadrb_ur |
5139 | 0 | 0U, // L4_loadrd_ap |
5140 | 0 | 0U, // L4_loadrd_rr |
5141 | 0 | 0U, // L4_loadrd_ur |
5142 | 0 | 0U, // L4_loadrh_ap |
5143 | 0 | 0U, // L4_loadrh_rr |
5144 | 0 | 0U, // L4_loadrh_ur |
5145 | 0 | 0U, // L4_loadri_ap |
5146 | 0 | 0U, // L4_loadri_rr |
5147 | 0 | 0U, // L4_loadri_ur |
5148 | 0 | 0U, // L4_loadrub_ap |
5149 | 0 | 0U, // L4_loadrub_rr |
5150 | 0 | 0U, // L4_loadrub_ur |
5151 | 0 | 0U, // L4_loadruh_ap |
5152 | 0 | 0U, // L4_loadruh_rr |
5153 | 0 | 0U, // L4_loadruh_ur |
5154 | 0 | 0U, // L4_loadw_phys |
5155 | 0 | 0U, // L4_or_memopb_io |
5156 | 0 | 0U, // L4_or_memoph_io |
5157 | 0 | 0U, // L4_or_memopw_io |
5158 | 0 | 0U, // L4_ploadrbf_abs |
5159 | 0 | 1666U, // L4_ploadrbf_rr |
5160 | 0 | 0U, // L4_ploadrbfnew_abs |
5161 | 0 | 1666U, // L4_ploadrbfnew_rr |
5162 | 0 | 0U, // L4_ploadrbt_abs |
5163 | 0 | 1666U, // L4_ploadrbt_rr |
5164 | 0 | 0U, // L4_ploadrbtnew_abs |
5165 | 0 | 1666U, // L4_ploadrbtnew_rr |
5166 | 0 | 0U, // L4_ploadrdf_abs |
5167 | 0 | 1666U, // L4_ploadrdf_rr |
5168 | 0 | 0U, // L4_ploadrdfnew_abs |
5169 | 0 | 1666U, // L4_ploadrdfnew_rr |
5170 | 0 | 0U, // L4_ploadrdt_abs |
5171 | 0 | 1666U, // L4_ploadrdt_rr |
5172 | 0 | 0U, // L4_ploadrdtnew_abs |
5173 | 0 | 1666U, // L4_ploadrdtnew_rr |
5174 | 0 | 0U, // L4_ploadrhf_abs |
5175 | 0 | 1666U, // L4_ploadrhf_rr |
5176 | 0 | 0U, // L4_ploadrhfnew_abs |
5177 | 0 | 1666U, // L4_ploadrhfnew_rr |
5178 | 0 | 0U, // L4_ploadrht_abs |
5179 | 0 | 1666U, // L4_ploadrht_rr |
5180 | 0 | 0U, // L4_ploadrhtnew_abs |
5181 | 0 | 1666U, // L4_ploadrhtnew_rr |
5182 | 0 | 0U, // L4_ploadrif_abs |
5183 | 0 | 1666U, // L4_ploadrif_rr |
5184 | 0 | 0U, // L4_ploadrifnew_abs |
5185 | 0 | 1666U, // L4_ploadrifnew_rr |
5186 | 0 | 0U, // L4_ploadrit_abs |
5187 | 0 | 1666U, // L4_ploadrit_rr |
5188 | 0 | 0U, // L4_ploadritnew_abs |
5189 | 0 | 1666U, // L4_ploadritnew_rr |
5190 | 0 | 0U, // L4_ploadrubf_abs |
5191 | 0 | 1666U, // L4_ploadrubf_rr |
5192 | 0 | 0U, // L4_ploadrubfnew_abs |
5193 | 0 | 1666U, // L4_ploadrubfnew_rr |
5194 | 0 | 0U, // L4_ploadrubt_abs |
5195 | 0 | 1666U, // L4_ploadrubt_rr |
5196 | 0 | 0U, // L4_ploadrubtnew_abs |
5197 | 0 | 1666U, // L4_ploadrubtnew_rr |
5198 | 0 | 0U, // L4_ploadruhf_abs |
5199 | 0 | 1666U, // L4_ploadruhf_rr |
5200 | 0 | 0U, // L4_ploadruhfnew_abs |
5201 | 0 | 1666U, // L4_ploadruhfnew_rr |
5202 | 0 | 0U, // L4_ploadruht_abs |
5203 | 0 | 1666U, // L4_ploadruht_rr |
5204 | 0 | 0U, // L4_ploadruhtnew_abs |
5205 | 0 | 1666U, // L4_ploadruhtnew_rr |
5206 | 0 | 0U, // L4_return |
5207 | 0 | 13U, // L4_return_f |
5208 | 0 | 41U, // L4_return_fnew_pnt |
5209 | 0 | 42U, // L4_return_fnew_pt |
5210 | 0 | 13U, // L4_return_t |
5211 | 0 | 41U, // L4_return_tnew_pnt |
5212 | 0 | 42U, // L4_return_tnew_pt |
5213 | 0 | 0U, // L4_sub_memopb_io |
5214 | 0 | 0U, // L4_sub_memoph_io |
5215 | 0 | 0U, // L4_sub_memopw_io |
5216 | 0 | 0U, // L6_memcpy |
5217 | 0 | 16U, // LO |
5218 | 0 | 69U, // M2_acci |
5219 | 0 | 69U, // M2_accii |
5220 | 0 | 0U, // M2_cmaci_s0 |
5221 | 0 | 0U, // M2_cmacr_s0 |
5222 | 0 | 0U, // M2_cmacs_s0 |
5223 | 0 | 0U, // M2_cmacs_s1 |
5224 | 0 | 0U, // M2_cmacsc_s0 |
5225 | 0 | 0U, // M2_cmacsc_s1 |
5226 | 0 | 0U, // M2_cmpyi_s0 |
5227 | 0 | 0U, // M2_cmpyr_s0 |
5228 | 0 | 0U, // M2_cmpyrs_s0 |
5229 | 0 | 0U, // M2_cmpyrs_s1 |
5230 | 0 | 0U, // M2_cmpyrsc_s0 |
5231 | 0 | 0U, // M2_cmpyrsc_s1 |
5232 | 0 | 0U, // M2_cmpys_s0 |
5233 | 0 | 0U, // M2_cmpys_s1 |
5234 | 0 | 0U, // M2_cmpysc_s0 |
5235 | 0 | 0U, // M2_cmpysc_s1 |
5236 | 0 | 0U, // M2_cnacs_s0 |
5237 | 0 | 0U, // M2_cnacs_s1 |
5238 | 0 | 0U, // M2_cnacsc_s0 |
5239 | 0 | 0U, // M2_cnacsc_s1 |
5240 | 0 | 69U, // M2_dpmpyss_acc_s0 |
5241 | 0 | 69U, // M2_dpmpyss_nac_s0 |
5242 | 0 | 322U, // M2_dpmpyss_rnd_s0 |
5243 | 0 | 66U, // M2_dpmpyss_s0 |
5244 | 0 | 69U, // M2_dpmpyuu_acc_s0 |
5245 | 0 | 69U, // M2_dpmpyuu_nac_s0 |
5246 | 0 | 66U, // M2_dpmpyuu_s0 |
5247 | 0 | 1730U, // M2_hmmpyh_rs1 |
5248 | 0 | 1794U, // M2_hmmpyh_s1 |
5249 | 0 | 1858U, // M2_hmmpyl_rs1 |
5250 | 0 | 1922U, // M2_hmmpyl_s1 |
5251 | 0 | 69U, // M2_maci |
5252 | 0 | 69U, // M2_macsin |
5253 | 0 | 69U, // M2_macsip |
5254 | 0 | 0U, // M2_mmachs_rs0 |
5255 | 0 | 0U, // M2_mmachs_rs1 |
5256 | 0 | 0U, // M2_mmachs_s0 |
5257 | 0 | 0U, // M2_mmachs_s1 |
5258 | 0 | 0U, // M2_mmacls_rs0 |
5259 | 0 | 0U, // M2_mmacls_rs1 |
5260 | 0 | 0U, // M2_mmacls_s0 |
5261 | 0 | 0U, // M2_mmacls_s1 |
5262 | 0 | 0U, // M2_mmacuhs_rs0 |
5263 | 0 | 0U, // M2_mmacuhs_rs1 |
5264 | 0 | 0U, // M2_mmacuhs_s0 |
5265 | 0 | 0U, // M2_mmacuhs_s1 |
5266 | 0 | 0U, // M2_mmaculs_rs0 |
5267 | 0 | 0U, // M2_mmaculs_rs1 |
5268 | 0 | 0U, // M2_mmaculs_s0 |
5269 | 0 | 0U, // M2_mmaculs_s1 |
5270 | 0 | 0U, // M2_mmpyh_rs0 |
5271 | 0 | 0U, // M2_mmpyh_rs1 |
5272 | 0 | 0U, // M2_mmpyh_s0 |
5273 | 0 | 0U, // M2_mmpyh_s1 |
5274 | 0 | 0U, // M2_mmpyl_rs0 |
5275 | 0 | 0U, // M2_mmpyl_rs1 |
5276 | 0 | 0U, // M2_mmpyl_s0 |
5277 | 0 | 0U, // M2_mmpyl_s1 |
5278 | 0 | 0U, // M2_mmpyuh_rs0 |
5279 | 0 | 0U, // M2_mmpyuh_rs1 |
5280 | 0 | 0U, // M2_mmpyuh_s0 |
5281 | 0 | 0U, // M2_mmpyuh_s1 |
5282 | 0 | 0U, // M2_mmpyul_rs0 |
5283 | 0 | 0U, // M2_mmpyul_rs1 |
5284 | 0 | 0U, // M2_mmpyul_s0 |
5285 | 0 | 0U, // M2_mmpyul_s1 |
5286 | 0 | 69U, // M2_mnaci |
5287 | 0 | 965U, // M2_mpy_acc_hh_s0 |
5288 | 0 | 1989U, // M2_mpy_acc_hh_s1 |
5289 | 0 | 1029U, // M2_mpy_acc_hl_s0 |
5290 | 0 | 2053U, // M2_mpy_acc_hl_s1 |
5291 | 0 | 965U, // M2_mpy_acc_lh_s0 |
5292 | 0 | 1989U, // M2_mpy_acc_lh_s1 |
5293 | 0 | 1029U, // M2_mpy_acc_ll_s0 |
5294 | 0 | 2053U, // M2_mpy_acc_ll_s1 |
5295 | 0 | 1093U, // M2_mpy_acc_sat_hh_s0 |
5296 | 0 | 1797U, // M2_mpy_acc_sat_hh_s1 |
5297 | 0 | 1157U, // M2_mpy_acc_sat_hl_s0 |
5298 | 0 | 1925U, // M2_mpy_acc_sat_hl_s1 |
5299 | 0 | 1093U, // M2_mpy_acc_sat_lh_s0 |
5300 | 0 | 1797U, // M2_mpy_acc_sat_lh_s1 |
5301 | 0 | 1157U, // M2_mpy_acc_sat_ll_s0 |
5302 | 0 | 1925U, // M2_mpy_acc_sat_ll_s1 |
5303 | 0 | 962U, // M2_mpy_hh_s0 |
5304 | 0 | 1986U, // M2_mpy_hh_s1 |
5305 | 0 | 1026U, // M2_mpy_hl_s0 |
5306 | 0 | 2050U, // M2_mpy_hl_s1 |
5307 | 0 | 962U, // M2_mpy_lh_s0 |
5308 | 0 | 1986U, // M2_mpy_lh_s1 |
5309 | 0 | 1026U, // M2_mpy_ll_s0 |
5310 | 0 | 2050U, // M2_mpy_ll_s1 |
5311 | 0 | 965U, // M2_mpy_nac_hh_s0 |
5312 | 0 | 1989U, // M2_mpy_nac_hh_s1 |
5313 | 0 | 1029U, // M2_mpy_nac_hl_s0 |
5314 | 0 | 2053U, // M2_mpy_nac_hl_s1 |
5315 | 0 | 965U, // M2_mpy_nac_lh_s0 |
5316 | 0 | 1989U, // M2_mpy_nac_lh_s1 |
5317 | 0 | 1029U, // M2_mpy_nac_ll_s0 |
5318 | 0 | 2053U, // M2_mpy_nac_ll_s1 |
5319 | 0 | 1093U, // M2_mpy_nac_sat_hh_s0 |
5320 | 0 | 1797U, // M2_mpy_nac_sat_hh_s1 |
5321 | 0 | 1157U, // M2_mpy_nac_sat_hl_s0 |
5322 | 0 | 1925U, // M2_mpy_nac_sat_hl_s1 |
5323 | 0 | 1093U, // M2_mpy_nac_sat_lh_s0 |
5324 | 0 | 1797U, // M2_mpy_nac_sat_lh_s1 |
5325 | 0 | 1157U, // M2_mpy_nac_sat_ll_s0 |
5326 | 0 | 1925U, // M2_mpy_nac_sat_ll_s1 |
5327 | 0 | 2114U, // M2_mpy_rnd_hh_s0 |
5328 | 0 | 2178U, // M2_mpy_rnd_hh_s1 |
5329 | 0 | 2242U, // M2_mpy_rnd_hl_s0 |
5330 | 0 | 2306U, // M2_mpy_rnd_hl_s1 |
5331 | 0 | 2114U, // M2_mpy_rnd_lh_s0 |
5332 | 0 | 2178U, // M2_mpy_rnd_lh_s1 |
5333 | 0 | 2242U, // M2_mpy_rnd_ll_s0 |
5334 | 0 | 2306U, // M2_mpy_rnd_ll_s1 |
5335 | 0 | 1090U, // M2_mpy_sat_hh_s0 |
5336 | 0 | 1794U, // M2_mpy_sat_hh_s1 |
5337 | 0 | 1154U, // M2_mpy_sat_hl_s0 |
5338 | 0 | 1922U, // M2_mpy_sat_hl_s1 |
5339 | 0 | 1090U, // M2_mpy_sat_lh_s0 |
5340 | 0 | 1794U, // M2_mpy_sat_lh_s1 |
5341 | 0 | 1154U, // M2_mpy_sat_ll_s0 |
5342 | 0 | 1922U, // M2_mpy_sat_ll_s1 |
5343 | 0 | 2370U, // M2_mpy_sat_rnd_hh_s0 |
5344 | 0 | 1730U, // M2_mpy_sat_rnd_hh_s1 |
5345 | 0 | 2434U, // M2_mpy_sat_rnd_hl_s0 |
5346 | 0 | 1858U, // M2_mpy_sat_rnd_hl_s1 |
5347 | 0 | 2370U, // M2_mpy_sat_rnd_lh_s0 |
5348 | 0 | 1730U, // M2_mpy_sat_rnd_lh_s1 |
5349 | 0 | 2434U, // M2_mpy_sat_rnd_ll_s0 |
5350 | 0 | 1858U, // M2_mpy_sat_rnd_ll_s1 |
5351 | 0 | 66U, // M2_mpy_up |
5352 | 0 | 2498U, // M2_mpy_up_s1 |
5353 | 0 | 2562U, // M2_mpy_up_s1_sat |
5354 | 0 | 965U, // M2_mpyd_acc_hh_s0 |
5355 | 0 | 1989U, // M2_mpyd_acc_hh_s1 |
5356 | 0 | 1029U, // M2_mpyd_acc_hl_s0 |
5357 | 0 | 2053U, // M2_mpyd_acc_hl_s1 |
5358 | 0 | 965U, // M2_mpyd_acc_lh_s0 |
5359 | 0 | 1989U, // M2_mpyd_acc_lh_s1 |
5360 | 0 | 1029U, // M2_mpyd_acc_ll_s0 |
5361 | 0 | 2053U, // M2_mpyd_acc_ll_s1 |
5362 | 0 | 962U, // M2_mpyd_hh_s0 |
5363 | 0 | 1986U, // M2_mpyd_hh_s1 |
5364 | 0 | 1026U, // M2_mpyd_hl_s0 |
5365 | 0 | 2050U, // M2_mpyd_hl_s1 |
5366 | 0 | 962U, // M2_mpyd_lh_s0 |
5367 | 0 | 1986U, // M2_mpyd_lh_s1 |
5368 | 0 | 1026U, // M2_mpyd_ll_s0 |
5369 | 0 | 2050U, // M2_mpyd_ll_s1 |
5370 | 0 | 965U, // M2_mpyd_nac_hh_s0 |
5371 | 0 | 1989U, // M2_mpyd_nac_hh_s1 |
5372 | 0 | 1029U, // M2_mpyd_nac_hl_s0 |
5373 | 0 | 2053U, // M2_mpyd_nac_hl_s1 |
5374 | 0 | 965U, // M2_mpyd_nac_lh_s0 |
5375 | 0 | 1989U, // M2_mpyd_nac_lh_s1 |
5376 | 0 | 1029U, // M2_mpyd_nac_ll_s0 |
5377 | 0 | 2053U, // M2_mpyd_nac_ll_s1 |
5378 | 0 | 2114U, // M2_mpyd_rnd_hh_s0 |
5379 | 0 | 2178U, // M2_mpyd_rnd_hh_s1 |
5380 | 0 | 2242U, // M2_mpyd_rnd_hl_s0 |
5381 | 0 | 2306U, // M2_mpyd_rnd_hl_s1 |
5382 | 0 | 2114U, // M2_mpyd_rnd_lh_s0 |
5383 | 0 | 2178U, // M2_mpyd_rnd_lh_s1 |
5384 | 0 | 2242U, // M2_mpyd_rnd_ll_s0 |
5385 | 0 | 2306U, // M2_mpyd_rnd_ll_s1 |
5386 | 0 | 66U, // M2_mpyi |
5387 | 0 | 0U, // M2_mpysin |
5388 | 0 | 0U, // M2_mpysip |
5389 | 0 | 0U, // M2_mpysu_up |
5390 | 0 | 965U, // M2_mpyu_acc_hh_s0 |
5391 | 0 | 1989U, // M2_mpyu_acc_hh_s1 |
5392 | 0 | 1029U, // M2_mpyu_acc_hl_s0 |
5393 | 0 | 2053U, // M2_mpyu_acc_hl_s1 |
5394 | 0 | 965U, // M2_mpyu_acc_lh_s0 |
5395 | 0 | 1989U, // M2_mpyu_acc_lh_s1 |
5396 | 0 | 1029U, // M2_mpyu_acc_ll_s0 |
5397 | 0 | 2053U, // M2_mpyu_acc_ll_s1 |
5398 | 0 | 962U, // M2_mpyu_hh_s0 |
5399 | 0 | 1986U, // M2_mpyu_hh_s1 |
5400 | 0 | 1026U, // M2_mpyu_hl_s0 |
5401 | 0 | 2050U, // M2_mpyu_hl_s1 |
5402 | 0 | 962U, // M2_mpyu_lh_s0 |
5403 | 0 | 1986U, // M2_mpyu_lh_s1 |
5404 | 0 | 1026U, // M2_mpyu_ll_s0 |
5405 | 0 | 2050U, // M2_mpyu_ll_s1 |
5406 | 0 | 965U, // M2_mpyu_nac_hh_s0 |
5407 | 0 | 1989U, // M2_mpyu_nac_hh_s1 |
5408 | 0 | 1029U, // M2_mpyu_nac_hl_s0 |
5409 | 0 | 2053U, // M2_mpyu_nac_hl_s1 |
5410 | 0 | 965U, // M2_mpyu_nac_lh_s0 |
5411 | 0 | 1989U, // M2_mpyu_nac_lh_s1 |
5412 | 0 | 1029U, // M2_mpyu_nac_ll_s0 |
5413 | 0 | 2053U, // M2_mpyu_nac_ll_s1 |
5414 | 0 | 66U, // M2_mpyu_up |
5415 | 0 | 965U, // M2_mpyud_acc_hh_s0 |
5416 | 0 | 1989U, // M2_mpyud_acc_hh_s1 |
5417 | 0 | 1029U, // M2_mpyud_acc_hl_s0 |
5418 | 0 | 2053U, // M2_mpyud_acc_hl_s1 |
5419 | 0 | 965U, // M2_mpyud_acc_lh_s0 |
5420 | 0 | 1989U, // M2_mpyud_acc_lh_s1 |
5421 | 0 | 1029U, // M2_mpyud_acc_ll_s0 |
5422 | 0 | 2053U, // M2_mpyud_acc_ll_s1 |
5423 | 0 | 962U, // M2_mpyud_hh_s0 |
5424 | 0 | 1986U, // M2_mpyud_hh_s1 |
5425 | 0 | 1026U, // M2_mpyud_hl_s0 |
5426 | 0 | 2050U, // M2_mpyud_hl_s1 |
5427 | 0 | 962U, // M2_mpyud_lh_s0 |
5428 | 0 | 1986U, // M2_mpyud_lh_s1 |
5429 | 0 | 1026U, // M2_mpyud_ll_s0 |
5430 | 0 | 2050U, // M2_mpyud_ll_s1 |
5431 | 0 | 965U, // M2_mpyud_nac_hh_s0 |
5432 | 0 | 1989U, // M2_mpyud_nac_hh_s1 |
5433 | 0 | 1029U, // M2_mpyud_nac_hl_s0 |
5434 | 0 | 2053U, // M2_mpyud_nac_hl_s1 |
5435 | 0 | 965U, // M2_mpyud_nac_lh_s0 |
5436 | 0 | 1989U, // M2_mpyud_nac_lh_s1 |
5437 | 0 | 1029U, // M2_mpyud_nac_ll_s0 |
5438 | 0 | 2053U, // M2_mpyud_nac_ll_s1 |
5439 | 0 | 69U, // M2_nacci |
5440 | 0 | 69U, // M2_naccii |
5441 | 0 | 0U, // M2_subacc |
5442 | 0 | 0U, // M2_vabsdiffh |
5443 | 0 | 0U, // M2_vabsdiffw |
5444 | 0 | 0U, // M2_vcmac_s0_sat_i |
5445 | 0 | 0U, // M2_vcmac_s0_sat_r |
5446 | 0 | 0U, // M2_vcmpy_s0_sat_i |
5447 | 0 | 0U, // M2_vcmpy_s0_sat_r |
5448 | 0 | 0U, // M2_vcmpy_s1_sat_i |
5449 | 0 | 0U, // M2_vcmpy_s1_sat_r |
5450 | 0 | 0U, // M2_vdmacs_s0 |
5451 | 0 | 0U, // M2_vdmacs_s1 |
5452 | 0 | 0U, // M2_vdmpyrs_s0 |
5453 | 0 | 0U, // M2_vdmpyrs_s1 |
5454 | 0 | 0U, // M2_vdmpys_s0 |
5455 | 0 | 0U, // M2_vdmpys_s1 |
5456 | 0 | 0U, // M2_vmac2 |
5457 | 0 | 0U, // M2_vmac2es |
5458 | 0 | 0U, // M2_vmac2es_s0 |
5459 | 0 | 0U, // M2_vmac2es_s1 |
5460 | 0 | 0U, // M2_vmac2s_s0 |
5461 | 0 | 0U, // M2_vmac2s_s1 |
5462 | 0 | 0U, // M2_vmac2su_s0 |
5463 | 0 | 0U, // M2_vmac2su_s1 |
5464 | 0 | 0U, // M2_vmpy2es_s0 |
5465 | 0 | 0U, // M2_vmpy2es_s1 |
5466 | 0 | 0U, // M2_vmpy2s_s0 |
5467 | 0 | 0U, // M2_vmpy2s_s0pack |
5468 | 0 | 0U, // M2_vmpy2s_s1 |
5469 | 0 | 0U, // M2_vmpy2s_s1pack |
5470 | 0 | 0U, // M2_vmpy2su_s0 |
5471 | 0 | 0U, // M2_vmpy2su_s1 |
5472 | 0 | 0U, // M2_vraddh |
5473 | 0 | 0U, // M2_vradduh |
5474 | 0 | 0U, // M2_vrcmaci_s0 |
5475 | 0 | 0U, // M2_vrcmaci_s0c |
5476 | 0 | 0U, // M2_vrcmacr_s0 |
5477 | 0 | 0U, // M2_vrcmacr_s0c |
5478 | 0 | 0U, // M2_vrcmpyi_s0 |
5479 | 0 | 0U, // M2_vrcmpyi_s0c |
5480 | 0 | 0U, // M2_vrcmpyr_s0 |
5481 | 0 | 0U, // M2_vrcmpyr_s0c |
5482 | 0 | 0U, // M2_vrcmpys_acc_s1_h |
5483 | 0 | 0U, // M2_vrcmpys_acc_s1_l |
5484 | 0 | 0U, // M2_vrcmpys_s1_h |
5485 | 0 | 0U, // M2_vrcmpys_s1_l |
5486 | 0 | 0U, // M2_vrcmpys_s1rp_h |
5487 | 0 | 0U, // M2_vrcmpys_s1rp_l |
5488 | 0 | 0U, // M2_vrmac_s0 |
5489 | 0 | 0U, // M2_vrmpy_s0 |
5490 | 0 | 0U, // M2_xor_xacc |
5491 | 0 | 69U, // M4_and_and |
5492 | 0 | 69U, // M4_and_andn |
5493 | 0 | 0U, // M4_and_or |
5494 | 0 | 0U, // M4_and_xor |
5495 | 0 | 0U, // M4_cmpyi_wh |
5496 | 0 | 0U, // M4_cmpyi_whc |
5497 | 0 | 0U, // M4_cmpyr_wh |
5498 | 0 | 0U, // M4_cmpyr_whc |
5499 | 0 | 2565U, // M4_mac_up_s1_sat |
5500 | 0 | 42188U, // M4_mpyri_addi |
5501 | 0 | 38315U, // M4_mpyri_addr |
5502 | 0 | 44U, // M4_mpyri_addr_u2 |
5503 | 0 | 42176U, // M4_mpyrr_addi |
5504 | 0 | 42347U, // M4_mpyrr_addr |
5505 | 0 | 2565U, // M4_nac_up_s1_sat |
5506 | 0 | 69U, // M4_or_and |
5507 | 0 | 69U, // M4_or_andn |
5508 | 0 | 69U, // M4_or_or |
5509 | 0 | 0U, // M4_or_xor |
5510 | 0 | 0U, // M4_pmpyw |
5511 | 0 | 0U, // M4_pmpyw_acc |
5512 | 0 | 0U, // M4_vpmpyh |
5513 | 0 | 0U, // M4_vpmpyh_acc |
5514 | 0 | 0U, // M4_vrmpyeh_acc_s0 |
5515 | 0 | 0U, // M4_vrmpyeh_acc_s1 |
5516 | 0 | 0U, // M4_vrmpyeh_s0 |
5517 | 0 | 0U, // M4_vrmpyeh_s1 |
5518 | 0 | 0U, // M4_vrmpyoh_acc_s0 |
5519 | 0 | 0U, // M4_vrmpyoh_acc_s1 |
5520 | 0 | 0U, // M4_vrmpyoh_s0 |
5521 | 0 | 0U, // M4_vrmpyoh_s1 |
5522 | 0 | 69U, // M4_xor_and |
5523 | 0 | 69U, // M4_xor_andn |
5524 | 0 | 0U, // M4_xor_or |
5525 | 0 | 0U, // M4_xor_xacc |
5526 | 0 | 0U, // M5_vdmacbsu |
5527 | 0 | 0U, // M5_vdmpybsu |
5528 | 0 | 0U, // M5_vmacbsu |
5529 | 0 | 0U, // M5_vmacbuu |
5530 | 0 | 0U, // M5_vmpybsu |
5531 | 0 | 0U, // M5_vmpybuu |
5532 | 0 | 0U, // M5_vrmacbsu |
5533 | 0 | 0U, // M5_vrmacbuu |
5534 | 0 | 0U, // M5_vrmpybsu |
5535 | 0 | 0U, // M5_vrmpybuu |
5536 | 0 | 0U, // M6_vabsdiffb |
5537 | 0 | 0U, // M6_vabsdiffub |
5538 | 0 | 0U, // M7_dcmpyiw |
5539 | 0 | 0U, // M7_dcmpyiw_acc |
5540 | 0 | 0U, // M7_dcmpyiwc |
5541 | 0 | 0U, // M7_dcmpyiwc_acc |
5542 | 0 | 0U, // M7_dcmpyrw |
5543 | 0 | 0U, // M7_dcmpyrw_acc |
5544 | 0 | 0U, // M7_dcmpyrwc |
5545 | 0 | 0U, // M7_dcmpyrwc_acc |
5546 | 0 | 0U, // M7_wcmpyiw |
5547 | 0 | 0U, // M7_wcmpyiw_rnd |
5548 | 0 | 0U, // M7_wcmpyiwc |
5549 | 0 | 0U, // M7_wcmpyiwc_rnd |
5550 | 0 | 0U, // M7_wcmpyrw |
5551 | 0 | 0U, // M7_wcmpyrw_rnd |
5552 | 0 | 0U, // M7_wcmpyrwc |
5553 | 0 | 0U, // M7_wcmpyrwc_rnd |
5554 | 0 | 0U, // PS_call_stk |
5555 | 0 | 0U, // PS_callr_nr |
5556 | 0 | 0U, // PS_jmpret |
5557 | 0 | 0U, // PS_jmpretf |
5558 | 0 | 0U, // PS_jmpretfnew |
5559 | 0 | 0U, // PS_jmpretfnewpt |
5560 | 0 | 0U, // PS_jmprett |
5561 | 0 | 0U, // PS_jmprettnew |
5562 | 0 | 0U, // PS_jmprettnewpt |
5563 | 0 | 0U, // PS_loadrbabs |
5564 | 0 | 0U, // PS_loadrdabs |
5565 | 0 | 0U, // PS_loadrhabs |
5566 | 0 | 0U, // PS_loadriabs |
5567 | 0 | 0U, // PS_loadrubabs |
5568 | 0 | 0U, // PS_loadruhabs |
5569 | 0 | 0U, // PS_storerbabs |
5570 | 0 | 0U, // PS_storerbnewabs |
5571 | 0 | 0U, // PS_storerdabs |
5572 | 0 | 0U, // PS_storerfabs |
5573 | 0 | 0U, // PS_storerhabs |
5574 | 0 | 0U, // PS_storerhnewabs |
5575 | 0 | 0U, // PS_storeriabs |
5576 | 0 | 0U, // PS_storerinewabs |
5577 | 0 | 0U, // PS_trap1 |
5578 | 0 | 0U, // R6_release_at_vi |
5579 | 0 | 0U, // R6_release_st_vi |
5580 | 0 | 0U, // RESTORE_DEALLOC_BEFORE_TAILCALL_V4 |
5581 | 0 | 0U, // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT |
5582 | 0 | 0U, // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC |
5583 | 0 | 0U, // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC |
5584 | 0 | 0U, // RESTORE_DEALLOC_RET_JMP_V4 |
5585 | 0 | 0U, // RESTORE_DEALLOC_RET_JMP_V4_EXT |
5586 | 0 | 0U, // RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC |
5587 | 0 | 0U, // RESTORE_DEALLOC_RET_JMP_V4_PIC |
5588 | 0 | 0U, // S2_addasl_rrri |
5589 | 0 | 13U, // S2_allocframe |
5590 | 0 | 66U, // S2_asl_i_p |
5591 | 0 | 69U, // S2_asl_i_p_acc |
5592 | 0 | 69U, // S2_asl_i_p_and |
5593 | 0 | 69U, // S2_asl_i_p_nac |
5594 | 0 | 69U, // S2_asl_i_p_or |
5595 | 0 | 69U, // S2_asl_i_p_xacc |
5596 | 0 | 66U, // S2_asl_i_r |
5597 | 0 | 69U, // S2_asl_i_r_acc |
5598 | 0 | 69U, // S2_asl_i_r_and |
5599 | 0 | 69U, // S2_asl_i_r_nac |
5600 | 0 | 69U, // S2_asl_i_r_or |
5601 | 0 | 1282U, // S2_asl_i_r_sat |
5602 | 0 | 69U, // S2_asl_i_r_xacc |
5603 | 0 | 66U, // S2_asl_i_vh |
5604 | 0 | 66U, // S2_asl_i_vw |
5605 | 0 | 66U, // S2_asl_r_p |
5606 | 0 | 69U, // S2_asl_r_p_acc |
5607 | 0 | 69U, // S2_asl_r_p_and |
5608 | 0 | 69U, // S2_asl_r_p_nac |
5609 | 0 | 69U, // S2_asl_r_p_or |
5610 | 0 | 69U, // S2_asl_r_p_xor |
5611 | 0 | 66U, // S2_asl_r_r |
5612 | 0 | 69U, // S2_asl_r_r_acc |
5613 | 0 | 69U, // S2_asl_r_r_and |
5614 | 0 | 69U, // S2_asl_r_r_nac |
5615 | 0 | 69U, // S2_asl_r_r_or |
5616 | 0 | 1282U, // S2_asl_r_r_sat |
5617 | 0 | 66U, // S2_asl_r_vh |
5618 | 0 | 66U, // S2_asl_r_vw |
5619 | 0 | 66U, // S2_asr_i_p |
5620 | 0 | 69U, // S2_asr_i_p_acc |
5621 | 0 | 69U, // S2_asr_i_p_and |
5622 | 0 | 69U, // S2_asr_i_p_nac |
5623 | 0 | 69U, // S2_asr_i_p_or |
5624 | 0 | 322U, // S2_asr_i_p_rnd |
5625 | 0 | 66U, // S2_asr_i_r |
5626 | 0 | 69U, // S2_asr_i_r_acc |
5627 | 0 | 69U, // S2_asr_i_r_and |
5628 | 0 | 69U, // S2_asr_i_r_nac |
5629 | 0 | 69U, // S2_asr_i_r_or |
5630 | 0 | 322U, // S2_asr_i_r_rnd |
5631 | 0 | 66U, // S2_asr_i_svw_trun |
5632 | 0 | 66U, // S2_asr_i_vh |
5633 | 0 | 66U, // S2_asr_i_vw |
5634 | 0 | 66U, // S2_asr_r_p |
5635 | 0 | 69U, // S2_asr_r_p_acc |
5636 | 0 | 69U, // S2_asr_r_p_and |
5637 | 0 | 69U, // S2_asr_r_p_nac |
5638 | 0 | 69U, // S2_asr_r_p_or |
5639 | 0 | 0U, // S2_asr_r_p_xor |
5640 | 0 | 66U, // S2_asr_r_r |
5641 | 0 | 69U, // S2_asr_r_r_acc |
5642 | 0 | 69U, // S2_asr_r_r_and |
5643 | 0 | 69U, // S2_asr_r_r_nac |
5644 | 0 | 69U, // S2_asr_r_r_or |
5645 | 0 | 1282U, // S2_asr_r_r_sat |
5646 | 0 | 66U, // S2_asr_r_svw_trun |
5647 | 0 | 66U, // S2_asr_r_vh |
5648 | 0 | 66U, // S2_asr_r_vw |
5649 | 0 | 0U, // S2_brev |
5650 | 0 | 0U, // S2_brevp |
5651 | 0 | 0U, // S2_cabacdecbin |
5652 | 0 | 0U, // S2_cl0 |
5653 | 0 | 0U, // S2_cl0p |
5654 | 0 | 0U, // S2_cl1 |
5655 | 0 | 0U, // S2_cl1p |
5656 | 0 | 0U, // S2_clb |
5657 | 0 | 0U, // S2_clbnorm |
5658 | 0 | 0U, // S2_clbp |
5659 | 0 | 66U, // S2_clrbit_i |
5660 | 0 | 66U, // S2_clrbit_r |
5661 | 0 | 0U, // S2_ct0 |
5662 | 0 | 0U, // S2_ct0p |
5663 | 0 | 0U, // S2_ct1 |
5664 | 0 | 0U, // S2_ct1p |
5665 | 0 | 0U, // S2_deinterleave |
5666 | 0 | 38274U, // S2_extractu |
5667 | 0 | 66U, // S2_extractu_rp |
5668 | 0 | 38274U, // S2_extractup |
5669 | 0 | 66U, // S2_extractup_rp |
5670 | 0 | 54661U, // S2_insert |
5671 | 0 | 69U, // S2_insert_rp |
5672 | 0 | 54661U, // S2_insertp |
5673 | 0 | 69U, // S2_insertp_rp |
5674 | 0 | 0U, // S2_interleave |
5675 | 0 | 0U, // S2_lfsp |
5676 | 0 | 0U, // S2_lsl_r_p |
5677 | 0 | 0U, // S2_lsl_r_p_acc |
5678 | 0 | 0U, // S2_lsl_r_p_and |
5679 | 0 | 0U, // S2_lsl_r_p_nac |
5680 | 0 | 0U, // S2_lsl_r_p_or |
5681 | 0 | 0U, // S2_lsl_r_p_xor |
5682 | 0 | 0U, // S2_lsl_r_r |
5683 | 0 | 0U, // S2_lsl_r_r_acc |
5684 | 0 | 0U, // S2_lsl_r_r_and |
5685 | 0 | 0U, // S2_lsl_r_r_nac |
5686 | 0 | 0U, // S2_lsl_r_r_or |
5687 | 0 | 0U, // S2_lsl_r_vh |
5688 | 0 | 0U, // S2_lsl_r_vw |
5689 | 0 | 66U, // S2_lsr_i_p |
5690 | 0 | 69U, // S2_lsr_i_p_acc |
5691 | 0 | 69U, // S2_lsr_i_p_and |
5692 | 0 | 69U, // S2_lsr_i_p_nac |
5693 | 0 | 69U, // S2_lsr_i_p_or |
5694 | 0 | 69U, // S2_lsr_i_p_xacc |
5695 | 0 | 66U, // S2_lsr_i_r |
5696 | 0 | 69U, // S2_lsr_i_r_acc |
5697 | 0 | 69U, // S2_lsr_i_r_and |
5698 | 0 | 69U, // S2_lsr_i_r_nac |
5699 | 0 | 69U, // S2_lsr_i_r_or |
5700 | 0 | 69U, // S2_lsr_i_r_xacc |
5701 | 0 | 66U, // S2_lsr_i_vh |
5702 | 0 | 66U, // S2_lsr_i_vw |
5703 | 0 | 66U, // S2_lsr_r_p |
5704 | 0 | 69U, // S2_lsr_r_p_acc |
5705 | 0 | 69U, // S2_lsr_r_p_and |
5706 | 0 | 69U, // S2_lsr_r_p_nac |
5707 | 0 | 69U, // S2_lsr_r_p_or |
5708 | 0 | 69U, // S2_lsr_r_p_xor |
5709 | 0 | 66U, // S2_lsr_r_r |
5710 | 0 | 69U, // S2_lsr_r_r_acc |
5711 | 0 | 69U, // S2_lsr_r_r_and |
5712 | 0 | 69U, // S2_lsr_r_r_nac |
5713 | 0 | 69U, // S2_lsr_r_r_or |
5714 | 0 | 66U, // S2_lsr_r_vh |
5715 | 0 | 66U, // S2_lsr_r_vw |
5716 | 0 | 0U, // S2_mask |
5717 | 0 | 0U, // S2_packhl |
5718 | 0 | 0U, // S2_parityp |
5719 | 0 | 57376U, // S2_pstorerbf_io |
5720 | 0 | 58594U, // S2_pstorerbf_pi |
5721 | 0 | 58594U, // S2_pstorerbfnew_pi |
5722 | 0 | 57376U, // S2_pstorerbnewf_io |
5723 | 0 | 58594U, // S2_pstorerbnewf_pi |
5724 | 0 | 58594U, // S2_pstorerbnewfnew_pi |
5725 | 0 | 57376U, // S2_pstorerbnewt_io |
5726 | 0 | 58594U, // S2_pstorerbnewt_pi |
5727 | 0 | 58594U, // S2_pstorerbnewtnew_pi |
5728 | 0 | 57376U, // S2_pstorerbt_io |
5729 | 0 | 58594U, // S2_pstorerbt_pi |
5730 | 0 | 58594U, // S2_pstorerbtnew_pi |
5731 | 0 | 57376U, // S2_pstorerdf_io |
5732 | 0 | 58594U, // S2_pstorerdf_pi |
5733 | 0 | 58594U, // S2_pstorerdfnew_pi |
5734 | 0 | 57376U, // S2_pstorerdt_io |
5735 | 0 | 58594U, // S2_pstorerdt_pi |
5736 | 0 | 58594U, // S2_pstorerdtnew_pi |
5737 | 0 | 57376U, // S2_pstorerff_io |
5738 | 0 | 58594U, // S2_pstorerff_pi |
5739 | 0 | 58594U, // S2_pstorerffnew_pi |
5740 | 0 | 57376U, // S2_pstorerft_io |
5741 | 0 | 58594U, // S2_pstorerft_pi |
5742 | 0 | 58594U, // S2_pstorerftnew_pi |
5743 | 0 | 57376U, // S2_pstorerhf_io |
5744 | 0 | 58594U, // S2_pstorerhf_pi |
5745 | 0 | 58594U, // S2_pstorerhfnew_pi |
5746 | 0 | 57376U, // S2_pstorerhnewf_io |
5747 | 0 | 58594U, // S2_pstorerhnewf_pi |
5748 | 0 | 58594U, // S2_pstorerhnewfnew_pi |
5749 | 0 | 57376U, // S2_pstorerhnewt_io |
5750 | 0 | 58594U, // S2_pstorerhnewt_pi |
5751 | 0 | 58594U, // S2_pstorerhnewtnew_pi |
5752 | 0 | 57376U, // S2_pstorerht_io |
5753 | 0 | 58594U, // S2_pstorerht_pi |
5754 | 0 | 58594U, // S2_pstorerhtnew_pi |
5755 | 0 | 57376U, // S2_pstorerif_io |
5756 | 0 | 58594U, // S2_pstorerif_pi |
5757 | 0 | 58594U, // S2_pstorerifnew_pi |
5758 | 0 | 57376U, // S2_pstorerinewf_io |
5759 | 0 | 58594U, // S2_pstorerinewf_pi |
5760 | 0 | 58594U, // S2_pstorerinewfnew_pi |
5761 | 0 | 57376U, // S2_pstorerinewt_io |
5762 | 0 | 58594U, // S2_pstorerinewt_pi |
5763 | 0 | 58594U, // S2_pstorerinewtnew_pi |
5764 | 0 | 57376U, // S2_pstorerit_io |
5765 | 0 | 58594U, // S2_pstorerit_pi |
5766 | 0 | 58594U, // S2_pstoreritnew_pi |
5767 | 0 | 66U, // S2_setbit_i |
5768 | 0 | 66U, // S2_setbit_r |
5769 | 0 | 0U, // S2_shuffeb |
5770 | 0 | 0U, // S2_shuffeh |
5771 | 0 | 0U, // S2_shuffob |
5772 | 0 | 0U, // S2_shuffoh |
5773 | 0 | 130U, // S2_storerb_io |
5774 | 0 | 16U, // S2_storerb_pbr |
5775 | 0 | 16U, // S2_storerb_pci |
5776 | 0 | 0U, // S2_storerb_pcr |
5777 | 0 | 133U, // S2_storerb_pi |
5778 | 0 | 133U, // S2_storerb_pr |
5779 | 0 | 0U, // S2_storerbgp |
5780 | 0 | 194U, // S2_storerbnew_io |
5781 | 0 | 45U, // S2_storerbnew_pbr |
5782 | 0 | 45U, // S2_storerbnew_pci |
5783 | 0 | 0U, // S2_storerbnew_pcr |
5784 | 0 | 197U, // S2_storerbnew_pi |
5785 | 0 | 197U, // S2_storerbnew_pr |
5786 | 0 | 0U, // S2_storerbnewgp |
5787 | 0 | 130U, // S2_storerd_io |
5788 | 0 | 16U, // S2_storerd_pbr |
5789 | 0 | 16U, // S2_storerd_pci |
5790 | 0 | 0U, // S2_storerd_pcr |
5791 | 0 | 133U, // S2_storerd_pi |
5792 | 0 | 133U, // S2_storerd_pr |
5793 | 0 | 0U, // S2_storerdgp |
5794 | 0 | 258U, // S2_storerf_io |
5795 | 0 | 10U, // S2_storerf_pbr |
5796 | 0 | 10U, // S2_storerf_pci |
5797 | 0 | 0U, // S2_storerf_pcr |
5798 | 0 | 261U, // S2_storerf_pi |
5799 | 0 | 261U, // S2_storerf_pr |
5800 | 0 | 0U, // S2_storerfgp |
5801 | 0 | 130U, // S2_storerh_io |
5802 | 0 | 16U, // S2_storerh_pbr |
5803 | 0 | 16U, // S2_storerh_pci |
5804 | 0 | 0U, // S2_storerh_pcr |
5805 | 0 | 133U, // S2_storerh_pi |
5806 | 0 | 133U, // S2_storerh_pr |
5807 | 0 | 0U, // S2_storerhgp |
5808 | 0 | 194U, // S2_storerhnew_io |
5809 | 0 | 45U, // S2_storerhnew_pbr |
5810 | 0 | 45U, // S2_storerhnew_pci |
5811 | 0 | 0U, // S2_storerhnew_pcr |
5812 | 0 | 197U, // S2_storerhnew_pi |
5813 | 0 | 197U, // S2_storerhnew_pr |
5814 | 0 | 0U, // S2_storerhnewgp |
5815 | 0 | 130U, // S2_storeri_io |
5816 | 0 | 16U, // S2_storeri_pbr |
5817 | 0 | 16U, // S2_storeri_pci |
5818 | 0 | 0U, // S2_storeri_pcr |
5819 | 0 | 133U, // S2_storeri_pi |
5820 | 0 | 133U, // S2_storeri_pr |
5821 | 0 | 0U, // S2_storerigp |
5822 | 0 | 194U, // S2_storerinew_io |
5823 | 0 | 45U, // S2_storerinew_pbr |
5824 | 0 | 45U, // S2_storerinew_pci |
5825 | 0 | 0U, // S2_storerinew_pcr |
5826 | 0 | 197U, // S2_storerinew_pi |
5827 | 0 | 197U, // S2_storerinew_pr |
5828 | 0 | 0U, // S2_storerinewgp |
5829 | 0 | 131U, // S2_storew_locked |
5830 | 0 | 0U, // S2_storew_rl_at_vi |
5831 | 0 | 0U, // S2_storew_rl_st_vi |
5832 | 0 | 0U, // S2_svsathb |
5833 | 0 | 0U, // S2_svsathub |
5834 | 0 | 0U, // S2_tableidxb |
5835 | 0 | 0U, // S2_tableidxd |
5836 | 0 | 0U, // S2_tableidxh |
5837 | 0 | 0U, // S2_tableidxw |
5838 | 0 | 66U, // S2_togglebit_i |
5839 | 0 | 66U, // S2_togglebit_r |
5840 | 0 | 66U, // S2_tstbit_i |
5841 | 0 | 66U, // S2_tstbit_r |
5842 | 0 | 69U, // S2_valignib |
5843 | 0 | 69U, // S2_valignrb |
5844 | 0 | 0U, // S2_vcnegh |
5845 | 0 | 0U, // S2_vcrotate |
5846 | 0 | 0U, // S2_vrcnegh |
5847 | 0 | 0U, // S2_vrndpackwh |
5848 | 0 | 0U, // S2_vrndpackwhs |
5849 | 0 | 0U, // S2_vsathb |
5850 | 0 | 0U, // S2_vsathb_nopack |
5851 | 0 | 0U, // S2_vsathub |
5852 | 0 | 0U, // S2_vsathub_nopack |
5853 | 0 | 0U, // S2_vsatwh |
5854 | 0 | 0U, // S2_vsatwh_nopack |
5855 | 0 | 0U, // S2_vsatwuh |
5856 | 0 | 0U, // S2_vsatwuh_nopack |
5857 | 0 | 0U, // S2_vsplatrb |
5858 | 0 | 0U, // S2_vsplatrh |
5859 | 0 | 69U, // S2_vspliceib |
5860 | 0 | 69U, // S2_vsplicerb |
5861 | 0 | 0U, // S2_vsxtbh |
5862 | 0 | 0U, // S2_vsxthw |
5863 | 0 | 0U, // S2_vtrunehb |
5864 | 0 | 0U, // S2_vtrunewh |
5865 | 0 | 0U, // S2_vtrunohb |
5866 | 0 | 0U, // S2_vtrunowh |
5867 | 0 | 0U, // S2_vzxtbh |
5868 | 0 | 0U, // S2_vzxthw |
5869 | 0 | 46U, // S4_addaddi |
5870 | 0 | 0U, // S4_addi_asl_ri |
5871 | 0 | 0U, // S4_addi_lsr_ri |
5872 | 0 | 0U, // S4_andi_asl_ri |
5873 | 0 | 0U, // S4_andi_lsr_ri |
5874 | 0 | 0U, // S4_clbaddi |
5875 | 0 | 0U, // S4_clbpaddi |
5876 | 0 | 0U, // S4_clbpnorm |
5877 | 0 | 38274U, // S4_extract |
5878 | 0 | 66U, // S4_extract_rp |
5879 | 0 | 38274U, // S4_extractp |
5880 | 0 | 66U, // S4_extractp_rp |
5881 | 0 | 0U, // S4_lsli |
5882 | 0 | 66U, // S4_ntstbit_i |
5883 | 0 | 66U, // S4_ntstbit_r |
5884 | 0 | 69U, // S4_or_andi |
5885 | 0 | 42188U, // S4_or_andix |
5886 | 0 | 69U, // S4_or_ori |
5887 | 0 | 0U, // S4_ori_asl_ri |
5888 | 0 | 0U, // S4_ori_lsr_ri |
5889 | 0 | 0U, // S4_parity |
5890 | 0 | 0U, // S4_pstorerbf_abs |
5891 | 0 | 175U, // S4_pstorerbf_rr |
5892 | 0 | 0U, // S4_pstorerbfnew_abs |
5893 | 0 | 57376U, // S4_pstorerbfnew_io |
5894 | 0 | 175U, // S4_pstorerbfnew_rr |
5895 | 0 | 0U, // S4_pstorerbnewf_abs |
5896 | 0 | 239U, // S4_pstorerbnewf_rr |
5897 | 0 | 0U, // S4_pstorerbnewfnew_abs |
5898 | 0 | 57376U, // S4_pstorerbnewfnew_io |
5899 | 0 | 239U, // S4_pstorerbnewfnew_rr |
5900 | 0 | 0U, // S4_pstorerbnewt_abs |
5901 | 0 | 239U, // S4_pstorerbnewt_rr |
5902 | 0 | 0U, // S4_pstorerbnewtnew_abs |
5903 | 0 | 57376U, // S4_pstorerbnewtnew_io |
5904 | 0 | 239U, // S4_pstorerbnewtnew_rr |
5905 | 0 | 0U, // S4_pstorerbt_abs |
5906 | 0 | 175U, // S4_pstorerbt_rr |
5907 | 0 | 0U, // S4_pstorerbtnew_abs |
5908 | 0 | 57376U, // S4_pstorerbtnew_io |
5909 | 0 | 175U, // S4_pstorerbtnew_rr |
5910 | 0 | 0U, // S4_pstorerdf_abs |
5911 | 0 | 175U, // S4_pstorerdf_rr |
5912 | 0 | 0U, // S4_pstorerdfnew_abs |
5913 | 0 | 57376U, // S4_pstorerdfnew_io |
5914 | 0 | 175U, // S4_pstorerdfnew_rr |
5915 | 0 | 0U, // S4_pstorerdt_abs |
5916 | 0 | 175U, // S4_pstorerdt_rr |
5917 | 0 | 0U, // S4_pstorerdtnew_abs |
5918 | 0 | 57376U, // S4_pstorerdtnew_io |
5919 | 0 | 175U, // S4_pstorerdtnew_rr |
5920 | 0 | 0U, // S4_pstorerff_abs |
5921 | 0 | 303U, // S4_pstorerff_rr |
5922 | 0 | 0U, // S4_pstorerffnew_abs |
5923 | 0 | 57376U, // S4_pstorerffnew_io |
5924 | 0 | 303U, // S4_pstorerffnew_rr |
5925 | 0 | 0U, // S4_pstorerft_abs |
5926 | 0 | 303U, // S4_pstorerft_rr |
5927 | 0 | 0U, // S4_pstorerftnew_abs |
5928 | 0 | 57376U, // S4_pstorerftnew_io |
5929 | 0 | 303U, // S4_pstorerftnew_rr |
5930 | 0 | 0U, // S4_pstorerhf_abs |
5931 | 0 | 175U, // S4_pstorerhf_rr |
5932 | 0 | 0U, // S4_pstorerhfnew_abs |
5933 | 0 | 57376U, // S4_pstorerhfnew_io |
5934 | 0 | 175U, // S4_pstorerhfnew_rr |
5935 | 0 | 0U, // S4_pstorerhnewf_abs |
5936 | 0 | 239U, // S4_pstorerhnewf_rr |
5937 | 0 | 0U, // S4_pstorerhnewfnew_abs |
5938 | 0 | 57376U, // S4_pstorerhnewfnew_io |
5939 | 0 | 239U, // S4_pstorerhnewfnew_rr |
5940 | 0 | 0U, // S4_pstorerhnewt_abs |
5941 | 0 | 239U, // S4_pstorerhnewt_rr |
5942 | 0 | 0U, // S4_pstorerhnewtnew_abs |
5943 | 0 | 57376U, // S4_pstorerhnewtnew_io |
5944 | 0 | 239U, // S4_pstorerhnewtnew_rr |
5945 | 0 | 0U, // S4_pstorerht_abs |
5946 | 0 | 175U, // S4_pstorerht_rr |
5947 | 0 | 0U, // S4_pstorerhtnew_abs |
5948 | 0 | 57376U, // S4_pstorerhtnew_io |
5949 | 0 | 175U, // S4_pstorerhtnew_rr |
5950 | 0 | 0U, // S4_pstorerif_abs |
5951 | 0 | 175U, // S4_pstorerif_rr |
5952 | 0 | 0U, // S4_pstorerifnew_abs |
5953 | 0 | 57376U, // S4_pstorerifnew_io |
5954 | 0 | 175U, // S4_pstorerifnew_rr |
5955 | 0 | 0U, // S4_pstorerinewf_abs |
5956 | 0 | 239U, // S4_pstorerinewf_rr |
5957 | 0 | 0U, // S4_pstorerinewfnew_abs |
5958 | 0 | 57376U, // S4_pstorerinewfnew_io |
5959 | 0 | 239U, // S4_pstorerinewfnew_rr |
5960 | 0 | 0U, // S4_pstorerinewt_abs |
5961 | 0 | 239U, // S4_pstorerinewt_rr |
5962 | 0 | 0U, // S4_pstorerinewtnew_abs |
5963 | 0 | 57376U, // S4_pstorerinewtnew_io |
5964 | 0 | 239U, // S4_pstorerinewtnew_rr |
5965 | 0 | 0U, // S4_pstorerit_abs |
5966 | 0 | 175U, // S4_pstorerit_rr |
5967 | 0 | 0U, // S4_pstoreritnew_abs |
5968 | 0 | 57376U, // S4_pstoreritnew_io |
5969 | 0 | 175U, // S4_pstoreritnew_rr |
5970 | 0 | 131U, // S4_stored_locked |
5971 | 0 | 0U, // S4_stored_rl_at_vi |
5972 | 0 | 0U, // S4_stored_rl_st_vi |
5973 | 0 | 0U, // S4_storeirb_io |
5974 | 0 | 61472U, // S4_storeirbf_io |
5975 | 0 | 61472U, // S4_storeirbfnew_io |
5976 | 0 | 61472U, // S4_storeirbt_io |
5977 | 0 | 61472U, // S4_storeirbtnew_io |
5978 | 0 | 0U, // S4_storeirh_io |
5979 | 0 | 61472U, // S4_storeirhf_io |
5980 | 0 | 61472U, // S4_storeirhfnew_io |
5981 | 0 | 61472U, // S4_storeirht_io |
5982 | 0 | 61472U, // S4_storeirhtnew_io |
5983 | 0 | 0U, // S4_storeiri_io |
5984 | 0 | 61472U, // S4_storeirif_io |
5985 | 0 | 61472U, // S4_storeirifnew_io |
5986 | 0 | 61472U, // S4_storeirit_io |
5987 | 0 | 61472U, // S4_storeiritnew_io |
5988 | 0 | 0U, // S4_storerb_ap |
5989 | 0 | 0U, // S4_storerb_rr |
5990 | 0 | 0U, // S4_storerb_ur |
5991 | 0 | 0U, // S4_storerbnew_ap |
5992 | 0 | 0U, // S4_storerbnew_rr |
5993 | 0 | 0U, // S4_storerbnew_ur |
5994 | 0 | 0U, // S4_storerd_ap |
5995 | 0 | 0U, // S4_storerd_rr |
5996 | 0 | 0U, // S4_storerd_ur |
5997 | 0 | 0U, // S4_storerf_ap |
5998 | 0 | 0U, // S4_storerf_rr |
5999 | 0 | 0U, // S4_storerf_ur |
6000 | 0 | 0U, // S4_storerh_ap |
6001 | 0 | 0U, // S4_storerh_rr |
6002 | 0 | 0U, // S4_storerh_ur |
6003 | 0 | 0U, // S4_storerhnew_ap |
6004 | 0 | 0U, // S4_storerhnew_rr |
6005 | 0 | 0U, // S4_storerhnew_ur |
6006 | 0 | 0U, // S4_storeri_ap |
6007 | 0 | 0U, // S4_storeri_rr |
6008 | 0 | 0U, // S4_storeri_ur |
6009 | 0 | 0U, // S4_storerinew_ap |
6010 | 0 | 0U, // S4_storerinew_rr |
6011 | 0 | 0U, // S4_storerinew_ur |
6012 | 0 | 48U, // S4_subaddi |
6013 | 0 | 0U, // S4_subi_asl_ri |
6014 | 0 | 0U, // S4_subi_lsr_ri |
6015 | 0 | 0U, // S4_vrcrotate |
6016 | 0 | 0U, // S4_vrcrotate_acc |
6017 | 0 | 0U, // S4_vxaddsubh |
6018 | 0 | 0U, // S4_vxaddsubhr |
6019 | 0 | 0U, // S4_vxaddsubw |
6020 | 0 | 0U, // S4_vxsubaddh |
6021 | 0 | 0U, // S4_vxsubaddhr |
6022 | 0 | 0U, // S4_vxsubaddw |
6023 | 0 | 0U, // S5_asrhub_rnd_sat |
6024 | 0 | 0U, // S5_asrhub_sat |
6025 | 0 | 0U, // S5_popcountp |
6026 | 0 | 2626U, // S5_vasrhrnd |
6027 | 0 | 0U, // S6_rol_i_p |
6028 | 0 | 0U, // S6_rol_i_p_acc |
6029 | 0 | 0U, // S6_rol_i_p_and |
6030 | 0 | 0U, // S6_rol_i_p_nac |
6031 | 0 | 0U, // S6_rol_i_p_or |
6032 | 0 | 0U, // S6_rol_i_p_xacc |
6033 | 0 | 0U, // S6_rol_i_r |
6034 | 0 | 0U, // S6_rol_i_r_acc |
6035 | 0 | 0U, // S6_rol_i_r_and |
6036 | 0 | 0U, // S6_rol_i_r_nac |
6037 | 0 | 0U, // S6_rol_i_r_or |
6038 | 0 | 0U, // S6_rol_i_r_xacc |
6039 | 0 | 0U, // S6_vsplatrbp |
6040 | 0 | 66U, // S6_vtrunehb_ppp |
6041 | 0 | 66U, // S6_vtrunohb_ppp |
6042 | 0 | 12U, // SA1_addi |
6043 | 0 | 0U, // SA1_addrx |
6044 | 0 | 0U, // SA1_addsp |
6045 | 0 | 0U, // SA1_and1 |
6046 | 0 | 0U, // SA1_clrf |
6047 | 0 | 0U, // SA1_clrfnew |
6048 | 0 | 0U, // SA1_clrt |
6049 | 0 | 0U, // SA1_clrtnew |
6050 | 0 | 1U, // SA1_cmpeqi |
6051 | 0 | 0U, // SA1_combine0i |
6052 | 0 | 0U, // SA1_combine1i |
6053 | 0 | 0U, // SA1_combine2i |
6054 | 0 | 0U, // SA1_combine3i |
6055 | 0 | 0U, // SA1_combinerz |
6056 | 0 | 0U, // SA1_combinezr |
6057 | 0 | 12U, // SA1_dec |
6058 | 0 | 49U, // SA1_inc |
6059 | 0 | 0U, // SA1_seti |
6060 | 0 | 0U, // SA1_setin1 |
6061 | 0 | 0U, // SA1_sxtb |
6062 | 0 | 0U, // SA1_sxth |
6063 | 0 | 0U, // SA1_tfr |
6064 | 0 | 0U, // SA1_zxtb |
6065 | 0 | 0U, // SA1_zxth |
6066 | 0 | 0U, // SAVE_REGISTERS_CALL_V4 |
6067 | 0 | 0U, // SAVE_REGISTERS_CALL_V4STK |
6068 | 0 | 0U, // SAVE_REGISTERS_CALL_V4STK_EXT |
6069 | 0 | 0U, // SAVE_REGISTERS_CALL_V4STK_EXT_PIC |
6070 | 0 | 0U, // SAVE_REGISTERS_CALL_V4STK_PIC |
6071 | 0 | 0U, // SAVE_REGISTERS_CALL_V4_EXT |
6072 | 0 | 0U, // SAVE_REGISTERS_CALL_V4_EXT_PIC |
6073 | 0 | 0U, // SAVE_REGISTERS_CALL_V4_PIC |
6074 | 0 | 1U, // SL1_loadri_io |
6075 | 0 | 1U, // SL1_loadrub_io |
6076 | 0 | 0U, // SL2_deallocframe |
6077 | 0 | 0U, // SL2_jumpr31 |
6078 | 0 | 0U, // SL2_jumpr31_f |
6079 | 0 | 0U, // SL2_jumpr31_fnew |
6080 | 0 | 0U, // SL2_jumpr31_t |
6081 | 0 | 0U, // SL2_jumpr31_tnew |
6082 | 0 | 1U, // SL2_loadrb_io |
6083 | 0 | 0U, // SL2_loadrd_sp |
6084 | 0 | 1U, // SL2_loadrh_io |
6085 | 0 | 0U, // SL2_loadri_sp |
6086 | 0 | 1U, // SL2_loadruh_io |
6087 | 0 | 0U, // SL2_return |
6088 | 0 | 0U, // SL2_return_f |
6089 | 0 | 0U, // SL2_return_fnew |
6090 | 0 | 0U, // SL2_return_t |
6091 | 0 | 0U, // SL2_return_tnew |
6092 | 0 | 130U, // SS1_storeb_io |
6093 | 0 | 130U, // SS1_storew_io |
6094 | 0 | 0U, // SS2_allocframe |
6095 | 0 | 0U, // SS2_storebi0 |
6096 | 0 | 0U, // SS2_storebi1 |
6097 | 0 | 0U, // SS2_stored_sp |
6098 | 0 | 130U, // SS2_storeh_io |
6099 | 0 | 0U, // SS2_storew_sp |
6100 | 0 | 0U, // SS2_storewi0 |
6101 | 0 | 0U, // SS2_storewi1 |
6102 | 0 | 66U, // TFRI64_V2_ext |
6103 | 0 | 0U, // TFRI64_V4 |
6104 | 0 | 0U, // V6_extractw |
6105 | 0 | 0U, // V6_lvsplatb |
6106 | 0 | 0U, // V6_lvsplath |
6107 | 0 | 0U, // V6_lvsplatw |
6108 | 0 | 66U, // V6_pred_and |
6109 | 0 | 0U, // V6_pred_and_n |
6110 | 0 | 0U, // V6_pred_not |
6111 | 0 | 66U, // V6_pred_or |
6112 | 0 | 0U, // V6_pred_or_n |
6113 | 0 | 0U, // V6_pred_scalar2 |
6114 | 0 | 0U, // V6_pred_scalar2v2 |
6115 | 0 | 0U, // V6_pred_xor |
6116 | 0 | 962U, // V6_shuffeqh |
6117 | 0 | 2690U, // V6_shuffeqw |
6118 | 0 | 2757U, // V6_v6mpyhubs10 |
6119 | 0 | 0U, // V6_v6mpyhubs10_vxx |
6120 | 0 | 2821U, // V6_v6mpyvubs10 |
6121 | 0 | 0U, // V6_v6mpyvubs10_vxx |
6122 | 0 | 1U, // V6_vL32Ub_ai |
6123 | 0 | 1U, // V6_vL32Ub_pi |
6124 | 0 | 1U, // V6_vL32Ub_ppu |
6125 | 0 | 1U, // V6_vL32b_ai |
6126 | 0 | 1U, // V6_vL32b_cur_ai |
6127 | 0 | 1538U, // V6_vL32b_cur_npred_ai |
6128 | 0 | 1638U, // V6_vL32b_cur_npred_pi |
6129 | 0 | 2918U, // V6_vL32b_cur_npred_ppu |
6130 | 0 | 1U, // V6_vL32b_cur_pi |
6131 | 0 | 1U, // V6_vL32b_cur_ppu |
6132 | 0 | 1538U, // V6_vL32b_cur_pred_ai |
6133 | 0 | 1638U, // V6_vL32b_cur_pred_pi |
6134 | 0 | 2918U, // V6_vL32b_cur_pred_ppu |
6135 | 0 | 1538U, // V6_vL32b_npred_ai |
6136 | 0 | 1638U, // V6_vL32b_npred_pi |
6137 | 0 | 2918U, // V6_vL32b_npred_ppu |
6138 | 0 | 50U, // V6_vL32b_nt_ai |
6139 | 0 | 50U, // V6_vL32b_nt_cur_ai |
6140 | 0 | 1538U, // V6_vL32b_nt_cur_npred_ai |
6141 | 0 | 1638U, // V6_vL32b_nt_cur_npred_pi |
6142 | 0 | 2918U, // V6_vL32b_nt_cur_npred_ppu |
6143 | 0 | 50U, // V6_vL32b_nt_cur_pi |
6144 | 0 | 50U, // V6_vL32b_nt_cur_ppu |
6145 | 0 | 1538U, // V6_vL32b_nt_cur_pred_ai |
6146 | 0 | 1638U, // V6_vL32b_nt_cur_pred_pi |
6147 | 0 | 2918U, // V6_vL32b_nt_cur_pred_ppu |
6148 | 0 | 1538U, // V6_vL32b_nt_npred_ai |
6149 | 0 | 1638U, // V6_vL32b_nt_npred_pi |
6150 | 0 | 2918U, // V6_vL32b_nt_npred_ppu |
6151 | 0 | 50U, // V6_vL32b_nt_pi |
6152 | 0 | 50U, // V6_vL32b_nt_ppu |
6153 | 0 | 1538U, // V6_vL32b_nt_pred_ai |
6154 | 0 | 1638U, // V6_vL32b_nt_pred_pi |
6155 | 0 | 2918U, // V6_vL32b_nt_pred_ppu |
6156 | 0 | 50U, // V6_vL32b_nt_tmp_ai |
6157 | 0 | 1538U, // V6_vL32b_nt_tmp_npred_ai |
6158 | 0 | 1638U, // V6_vL32b_nt_tmp_npred_pi |
6159 | 0 | 2918U, // V6_vL32b_nt_tmp_npred_ppu |
6160 | 0 | 50U, // V6_vL32b_nt_tmp_pi |
6161 | 0 | 50U, // V6_vL32b_nt_tmp_ppu |
6162 | 0 | 1538U, // V6_vL32b_nt_tmp_pred_ai |
6163 | 0 | 1638U, // V6_vL32b_nt_tmp_pred_pi |
6164 | 0 | 2918U, // V6_vL32b_nt_tmp_pred_ppu |
6165 | 0 | 1U, // V6_vL32b_pi |
6166 | 0 | 1U, // V6_vL32b_ppu |
6167 | 0 | 1538U, // V6_vL32b_pred_ai |
6168 | 0 | 1638U, // V6_vL32b_pred_pi |
6169 | 0 | 2918U, // V6_vL32b_pred_ppu |
6170 | 0 | 1U, // V6_vL32b_tmp_ai |
6171 | 0 | 1538U, // V6_vL32b_tmp_npred_ai |
6172 | 0 | 1638U, // V6_vL32b_tmp_npred_pi |
6173 | 0 | 2918U, // V6_vL32b_tmp_npred_ppu |
6174 | 0 | 1U, // V6_vL32b_tmp_pi |
6175 | 0 | 1U, // V6_vL32b_tmp_ppu |
6176 | 0 | 1538U, // V6_vL32b_tmp_pred_ai |
6177 | 0 | 1638U, // V6_vL32b_tmp_pred_pi |
6178 | 0 | 2918U, // V6_vL32b_tmp_pred_ppu |
6179 | 0 | 130U, // V6_vS32Ub_ai |
6180 | 0 | 57376U, // V6_vS32Ub_npred_ai |
6181 | 0 | 58594U, // V6_vS32Ub_npred_pi |
6182 | 0 | 58593U, // V6_vS32Ub_npred_ppu |
6183 | 0 | 133U, // V6_vS32Ub_pi |
6184 | 0 | 133U, // V6_vS32Ub_ppu |
6185 | 0 | 57376U, // V6_vS32Ub_pred_ai |
6186 | 0 | 58594U, // V6_vS32Ub_pred_pi |
6187 | 0 | 58593U, // V6_vS32Ub_pred_ppu |
6188 | 0 | 130U, // V6_vS32b_ai |
6189 | 0 | 194U, // V6_vS32b_new_ai |
6190 | 0 | 57376U, // V6_vS32b_new_npred_ai |
6191 | 0 | 58594U, // V6_vS32b_new_npred_pi |
6192 | 0 | 58593U, // V6_vS32b_new_npred_ppu |
6193 | 0 | 197U, // V6_vS32b_new_pi |
6194 | 0 | 197U, // V6_vS32b_new_ppu |
6195 | 0 | 57376U, // V6_vS32b_new_pred_ai |
6196 | 0 | 58594U, // V6_vS32b_new_pred_pi |
6197 | 0 | 58593U, // V6_vS32b_new_pred_ppu |
6198 | 0 | 57376U, // V6_vS32b_npred_ai |
6199 | 0 | 58594U, // V6_vS32b_npred_pi |
6200 | 0 | 58593U, // V6_vS32b_npred_ppu |
6201 | 0 | 57376U, // V6_vS32b_nqpred_ai |
6202 | 0 | 58594U, // V6_vS32b_nqpred_pi |
6203 | 0 | 58593U, // V6_vS32b_nqpred_ppu |
6204 | 0 | 130U, // V6_vS32b_nt_ai |
6205 | 0 | 194U, // V6_vS32b_nt_new_ai |
6206 | 0 | 4128U, // V6_vS32b_nt_new_npred_ai |
6207 | 0 | 5346U, // V6_vS32b_nt_new_npred_pi |
6208 | 0 | 5345U, // V6_vS32b_nt_new_npred_ppu |
6209 | 0 | 197U, // V6_vS32b_nt_new_pi |
6210 | 0 | 197U, // V6_vS32b_nt_new_ppu |
6211 | 0 | 4128U, // V6_vS32b_nt_new_pred_ai |
6212 | 0 | 5346U, // V6_vS32b_nt_new_pred_pi |
6213 | 0 | 5345U, // V6_vS32b_nt_new_pred_ppu |
6214 | 0 | 4128U, // V6_vS32b_nt_npred_ai |
6215 | 0 | 5346U, // V6_vS32b_nt_npred_pi |
6216 | 0 | 5345U, // V6_vS32b_nt_npred_ppu |
6217 | 0 | 4128U, // V6_vS32b_nt_nqpred_ai |
6218 | 0 | 5346U, // V6_vS32b_nt_nqpred_pi |
6219 | 0 | 5345U, // V6_vS32b_nt_nqpred_ppu |
6220 | 0 | 133U, // V6_vS32b_nt_pi |
6221 | 0 | 133U, // V6_vS32b_nt_ppu |
6222 | 0 | 4128U, // V6_vS32b_nt_pred_ai |
6223 | 0 | 5346U, // V6_vS32b_nt_pred_pi |
6224 | 0 | 5345U, // V6_vS32b_nt_pred_ppu |
6225 | 0 | 4128U, // V6_vS32b_nt_qpred_ai |
6226 | 0 | 5346U, // V6_vS32b_nt_qpred_pi |
6227 | 0 | 5345U, // V6_vS32b_nt_qpred_ppu |
6228 | 0 | 133U, // V6_vS32b_pi |
6229 | 0 | 133U, // V6_vS32b_ppu |
6230 | 0 | 57376U, // V6_vS32b_pred_ai |
6231 | 0 | 58594U, // V6_vS32b_pred_pi |
6232 | 0 | 58593U, // V6_vS32b_pred_ppu |
6233 | 0 | 57376U, // V6_vS32b_qpred_ai |
6234 | 0 | 58594U, // V6_vS32b_qpred_pi |
6235 | 0 | 58593U, // V6_vS32b_qpred_ppu |
6236 | 0 | 0U, // V6_vS32b_srls_ai |
6237 | 0 | 0U, // V6_vS32b_srls_pi |
6238 | 0 | 0U, // V6_vS32b_srls_ppu |
6239 | 0 | 0U, // V6_vabs_hf |
6240 | 0 | 0U, // V6_vabs_sf |
6241 | 0 | 0U, // V6_vabsb |
6242 | 0 | 0U, // V6_vabsb_sat |
6243 | 0 | 962U, // V6_vabsdiffh |
6244 | 0 | 0U, // V6_vabsdiffub |
6245 | 0 | 450U, // V6_vabsdiffuh |
6246 | 0 | 0U, // V6_vabsdiffw |
6247 | 0 | 0U, // V6_vabsh |
6248 | 0 | 0U, // V6_vabsh_sat |
6249 | 0 | 0U, // V6_vabsw |
6250 | 0 | 0U, // V6_vabsw_sat |
6251 | 0 | 2946U, // V6_vadd_hf |
6252 | 0 | 0U, // V6_vadd_hf_hf |
6253 | 0 | 51U, // V6_vadd_qf16 |
6254 | 0 | 52U, // V6_vadd_qf16_mix |
6255 | 0 | 53U, // V6_vadd_qf32 |
6256 | 0 | 54U, // V6_vadd_qf32_mix |
6257 | 0 | 3010U, // V6_vadd_sf |
6258 | 0 | 3074U, // V6_vadd_sf_bf |
6259 | 0 | 2946U, // V6_vadd_sf_hf |
6260 | 0 | 3010U, // V6_vadd_sf_sf |
6261 | 0 | 0U, // V6_vaddb |
6262 | 0 | 0U, // V6_vaddb_dv |
6263 | 0 | 0U, // V6_vaddbnq |
6264 | 0 | 0U, // V6_vaddbq |
6265 | 0 | 0U, // V6_vaddbsat |
6266 | 0 | 0U, // V6_vaddbsat_dv |
6267 | 0 | 9463U, // V6_vaddcarry |
6268 | 0 | 0U, // V6_vaddcarryo |
6269 | 0 | 8247U, // V6_vaddcarrysat |
6270 | 0 | 0U, // V6_vaddclbh |
6271 | 0 | 0U, // V6_vaddclbw |
6272 | 0 | 962U, // V6_vaddh |
6273 | 0 | 962U, // V6_vaddh_dv |
6274 | 0 | 0U, // V6_vaddhnq |
6275 | 0 | 0U, // V6_vaddhq |
6276 | 0 | 1090U, // V6_vaddhsat |
6277 | 0 | 1090U, // V6_vaddhsat_dv |
6278 | 0 | 974U, // V6_vaddhw |
6279 | 0 | 965U, // V6_vaddhw_acc |
6280 | 0 | 386U, // V6_vaddubh |
6281 | 0 | 0U, // V6_vaddubh_acc |
6282 | 0 | 0U, // V6_vaddubsat |
6283 | 0 | 0U, // V6_vaddubsat_dv |
6284 | 0 | 0U, // V6_vaddububb_sat |
6285 | 0 | 0U, // V6_vadduhsat |
6286 | 0 | 0U, // V6_vadduhsat_dv |
6287 | 0 | 56U, // V6_vadduhw |
6288 | 0 | 453U, // V6_vadduhw_acc |
6289 | 0 | 0U, // V6_vadduwsat |
6290 | 0 | 0U, // V6_vadduwsat_dv |
6291 | 0 | 12343U, // V6_vaddw |
6292 | 0 | 12343U, // V6_vaddw_dv |
6293 | 0 | 0U, // V6_vaddwnq |
6294 | 0 | 0U, // V6_vaddwq |
6295 | 0 | 16439U, // V6_vaddwsat |
6296 | 0 | 16439U, // V6_vaddwsat_dv |
6297 | 0 | 69U, // V6_valignb |
6298 | 0 | 69U, // V6_valignbi |
6299 | 0 | 0U, // V6_vand |
6300 | 0 | 0U, // V6_vandnqrt |
6301 | 0 | 0U, // V6_vandnqrt_acc |
6302 | 0 | 0U, // V6_vandqrt |
6303 | 0 | 0U, // V6_vandqrt_acc |
6304 | 0 | 0U, // V6_vandvnqv |
6305 | 0 | 0U, // V6_vandvqv |
6306 | 0 | 0U, // V6_vandvrt |
6307 | 0 | 0U, // V6_vandvrt_acc |
6308 | 0 | 0U, // V6_vaslh |
6309 | 0 | 0U, // V6_vaslh_acc |
6310 | 0 | 0U, // V6_vaslhv |
6311 | 0 | 0U, // V6_vaslw |
6312 | 0 | 0U, // V6_vaslw_acc |
6313 | 0 | 0U, // V6_vaslwv |
6314 | 0 | 0U, // V6_vasr_into |
6315 | 0 | 66U, // V6_vasrh |
6316 | 0 | 0U, // V6_vasrh_acc |
6317 | 0 | 0U, // V6_vasrhbrndsat |
6318 | 0 | 0U, // V6_vasrhbsat |
6319 | 0 | 23618U, // V6_vasrhubrndsat |
6320 | 0 | 23618U, // V6_vasrhubsat |
6321 | 0 | 962U, // V6_vasrhv |
6322 | 0 | 23682U, // V6_vasruhubrndsat |
6323 | 0 | 23682U, // V6_vasruhubsat |
6324 | 0 | 23746U, // V6_vasruwuhrndsat |
6325 | 0 | 23746U, // V6_vasruwuhsat |
6326 | 0 | 3330U, // V6_vasrvuhubrndsat |
6327 | 0 | 3394U, // V6_vasrvuhubsat |
6328 | 0 | 3458U, // V6_vasrvwuhrndsat |
6329 | 0 | 3522U, // V6_vasrvwuhsat |
6330 | 0 | 0U, // V6_vasrw |
6331 | 0 | 0U, // V6_vasrw_acc |
6332 | 0 | 3586U, // V6_vasrwh |
6333 | 0 | 24066U, // V6_vasrwhrndsat |
6334 | 0 | 24066U, // V6_vasrwhsat |
6335 | 0 | 24066U, // V6_vasrwuhrndsat |
6336 | 0 | 24066U, // V6_vasrwuhsat |
6337 | 0 | 0U, // V6_vasrwv |
6338 | 0 | 0U, // V6_vassign |
6339 | 0 | 0U, // V6_vassign_fp |
6340 | 0 | 0U, // V6_vassign_tmp |
6341 | 0 | 0U, // V6_vavgb |
6342 | 0 | 0U, // V6_vavgbrnd |
6343 | 0 | 0U, // V6_vavgh |
6344 | 0 | 0U, // V6_vavghrnd |
6345 | 0 | 0U, // V6_vavgub |
6346 | 0 | 0U, // V6_vavgubrnd |
6347 | 0 | 0U, // V6_vavguh |
6348 | 0 | 0U, // V6_vavguhrnd |
6349 | 0 | 0U, // V6_vavguw |
6350 | 0 | 0U, // V6_vavguwrnd |
6351 | 0 | 0U, // V6_vavgw |
6352 | 0 | 0U, // V6_vavgwrnd |
6353 | 0 | 0U, // V6_vccombine |
6354 | 0 | 0U, // V6_vcl0h |
6355 | 0 | 0U, // V6_vcl0w |
6356 | 0 | 0U, // V6_vcmov |
6357 | 0 | 0U, // V6_vcombine |
6358 | 0 | 0U, // V6_vcombine_tmp |
6359 | 0 | 0U, // V6_vconv_h_hf |
6360 | 0 | 0U, // V6_vconv_hf_h |
6361 | 0 | 0U, // V6_vconv_hf_qf16 |
6362 | 0 | 0U, // V6_vconv_hf_qf32 |
6363 | 0 | 0U, // V6_vconv_sf_qf32 |
6364 | 0 | 0U, // V6_vconv_sf_w |
6365 | 0 | 0U, // V6_vconv_w_sf |
6366 | 0 | 0U, // V6_vcvt_b_hf |
6367 | 0 | 0U, // V6_vcvt_bf_sf |
6368 | 0 | 0U, // V6_vcvt_h_hf |
6369 | 0 | 0U, // V6_vcvt_hf_b |
6370 | 0 | 0U, // V6_vcvt_hf_h |
6371 | 0 | 3010U, // V6_vcvt_hf_sf |
6372 | 0 | 0U, // V6_vcvt_hf_ub |
6373 | 0 | 0U, // V6_vcvt_hf_uh |
6374 | 0 | 0U, // V6_vcvt_sf_hf |
6375 | 0 | 0U, // V6_vcvt_ub_hf |
6376 | 0 | 0U, // V6_vcvt_uh_hf |
6377 | 0 | 640U, // V6_vdeal |
6378 | 0 | 0U, // V6_vdealb |
6379 | 0 | 0U, // V6_vdealb4w |
6380 | 0 | 0U, // V6_vdealh |
6381 | 0 | 0U, // V6_vdealvdd |
6382 | 0 | 0U, // V6_vdelta |
6383 | 0 | 0U, // V6_vdmpy_sf_hf |
6384 | 0 | 0U, // V6_vdmpy_sf_hf_acc |
6385 | 0 | 0U, // V6_vdmpybus |
6386 | 0 | 0U, // V6_vdmpybus_acc |
6387 | 0 | 0U, // V6_vdmpybus_dv |
6388 | 0 | 0U, // V6_vdmpybus_dv_acc |
6389 | 0 | 0U, // V6_vdmpyhb |
6390 | 0 | 0U, // V6_vdmpyhb_acc |
6391 | 0 | 0U, // V6_vdmpyhb_dv |
6392 | 0 | 0U, // V6_vdmpyhb_dv_acc |
6393 | 0 | 0U, // V6_vdmpyhisat |
6394 | 0 | 0U, // V6_vdmpyhisat_acc |
6395 | 0 | 0U, // V6_vdmpyhsat |
6396 | 0 | 0U, // V6_vdmpyhsat_acc |
6397 | 0 | 0U, // V6_vdmpyhsuisat |
6398 | 0 | 0U, // V6_vdmpyhsuisat_acc |
6399 | 0 | 0U, // V6_vdmpyhsusat |
6400 | 0 | 0U, // V6_vdmpyhsusat_acc |
6401 | 0 | 0U, // V6_vdmpyhvsat |
6402 | 0 | 0U, // V6_vdmpyhvsat_acc |
6403 | 0 | 0U, // V6_vdsaduh |
6404 | 0 | 0U, // V6_vdsaduh_acc |
6405 | 0 | 3650U, // V6_veqb |
6406 | 0 | 3653U, // V6_veqb_and |
6407 | 0 | 3653U, // V6_veqb_or |
6408 | 0 | 3653U, // V6_veqb_xor |
6409 | 0 | 962U, // V6_veqh |
6410 | 0 | 965U, // V6_veqh_and |
6411 | 0 | 965U, // V6_veqh_or |
6412 | 0 | 965U, // V6_veqh_xor |
6413 | 0 | 2690U, // V6_veqw |
6414 | 0 | 2693U, // V6_veqw_and |
6415 | 0 | 2693U, // V6_veqw_or |
6416 | 0 | 2693U, // V6_veqw_xor |
6417 | 0 | 0U, // V6_vfmax_hf |
6418 | 0 | 0U, // V6_vfmax_sf |
6419 | 0 | 0U, // V6_vfmin_hf |
6420 | 0 | 0U, // V6_vfmin_sf |
6421 | 0 | 0U, // V6_vfneg_hf |
6422 | 0 | 0U, // V6_vfneg_sf |
6423 | 0 | 24576U, // V6_vgathermh |
6424 | 0 | 0U, // V6_vgathermhq |
6425 | 0 | 28672U, // V6_vgathermhw |
6426 | 0 | 0U, // V6_vgathermhwq |
6427 | 0 | 32768U, // V6_vgathermw |
6428 | 0 | 0U, // V6_vgathermwq |
6429 | 0 | 3650U, // V6_vgtb |
6430 | 0 | 3653U, // V6_vgtb_and |
6431 | 0 | 3653U, // V6_vgtb_or |
6432 | 0 | 3653U, // V6_vgtb_xor |
6433 | 0 | 3074U, // V6_vgtbf |
6434 | 0 | 3077U, // V6_vgtbf_and |
6435 | 0 | 3077U, // V6_vgtbf_or |
6436 | 0 | 3077U, // V6_vgtbf_xor |
6437 | 0 | 962U, // V6_vgth |
6438 | 0 | 965U, // V6_vgth_and |
6439 | 0 | 965U, // V6_vgth_or |
6440 | 0 | 965U, // V6_vgth_xor |
6441 | 0 | 2946U, // V6_vgthf |
6442 | 0 | 2949U, // V6_vgthf_and |
6443 | 0 | 2949U, // V6_vgthf_or |
6444 | 0 | 2949U, // V6_vgthf_xor |
6445 | 0 | 3010U, // V6_vgtsf |
6446 | 0 | 3013U, // V6_vgtsf_and |
6447 | 0 | 3013U, // V6_vgtsf_or |
6448 | 0 | 3013U, // V6_vgtsf_xor |
6449 | 0 | 386U, // V6_vgtub |
6450 | 0 | 389U, // V6_vgtub_and |
6451 | 0 | 389U, // V6_vgtub_or |
6452 | 0 | 389U, // V6_vgtub_xor |
6453 | 0 | 450U, // V6_vgtuh |
6454 | 0 | 453U, // V6_vgtuh_and |
6455 | 0 | 453U, // V6_vgtuh_or |
6456 | 0 | 453U, // V6_vgtuh_xor |
6457 | 0 | 514U, // V6_vgtuw |
6458 | 0 | 517U, // V6_vgtuw_and |
6459 | 0 | 517U, // V6_vgtuw_or |
6460 | 0 | 517U, // V6_vgtuw_xor |
6461 | 0 | 2690U, // V6_vgtw |
6462 | 0 | 2693U, // V6_vgtw_and |
6463 | 0 | 2693U, // V6_vgtw_or |
6464 | 0 | 2693U, // V6_vgtw_xor |
6465 | 0 | 0U, // V6_vhist |
6466 | 0 | 0U, // V6_vhistq |
6467 | 0 | 0U, // V6_vinsertwr |
6468 | 0 | 69U, // V6_vlalignb |
6469 | 0 | 69U, // V6_vlalignbi |
6470 | 0 | 0U, // V6_vlsrb |
6471 | 0 | 0U, // V6_vlsrh |
6472 | 0 | 0U, // V6_vlsrhv |
6473 | 0 | 0U, // V6_vlsrw |
6474 | 0 | 0U, // V6_vlsrwv |
6475 | 0 | 0U, // V6_vlut4 |
6476 | 0 | 69U, // V6_vlutvvb |
6477 | 0 | 3717U, // V6_vlutvvb_nm |
6478 | 0 | 73U, // V6_vlutvvb_oracc |
6479 | 0 | 73U, // V6_vlutvvb_oracci |
6480 | 0 | 69U, // V6_vlutvvbi |
6481 | 0 | 69U, // V6_vlutvwh |
6482 | 0 | 3717U, // V6_vlutvwh_nm |
6483 | 0 | 73U, // V6_vlutvwh_oracc |
6484 | 0 | 73U, // V6_vlutvwh_oracci |
6485 | 0 | 69U, // V6_vlutvwhi |
6486 | 0 | 0U, // V6_vmax_bf |
6487 | 0 | 0U, // V6_vmax_hf |
6488 | 0 | 0U, // V6_vmax_sf |
6489 | 0 | 0U, // V6_vmaxb |
6490 | 0 | 0U, // V6_vmaxh |
6491 | 0 | 0U, // V6_vmaxub |
6492 | 0 | 0U, // V6_vmaxuh |
6493 | 0 | 0U, // V6_vmaxw |
6494 | 0 | 0U, // V6_vmin_bf |
6495 | 0 | 0U, // V6_vmin_hf |
6496 | 0 | 0U, // V6_vmin_sf |
6497 | 0 | 0U, // V6_vminb |
6498 | 0 | 0U, // V6_vminh |
6499 | 0 | 0U, // V6_vminub |
6500 | 0 | 0U, // V6_vminuh |
6501 | 0 | 0U, // V6_vminw |
6502 | 0 | 3650U, // V6_vmpabus |
6503 | 0 | 0U, // V6_vmpabus_acc |
6504 | 0 | 3650U, // V6_vmpabusv |
6505 | 0 | 386U, // V6_vmpabuu |
6506 | 0 | 0U, // V6_vmpabuu_acc |
6507 | 0 | 386U, // V6_vmpabuuv |
6508 | 0 | 3650U, // V6_vmpahb |
6509 | 0 | 3653U, // V6_vmpahb_acc |
6510 | 0 | 40002U, // V6_vmpahhsat |
6511 | 0 | 3650U, // V6_vmpauhb |
6512 | 0 | 3653U, // V6_vmpauhb_acc |
6513 | 0 | 44162U, // V6_vmpauhuhsat |
6514 | 0 | 0U, // V6_vmpsuhuhsat |
6515 | 0 | 0U, // V6_vmpy_hf_hf |
6516 | 0 | 0U, // V6_vmpy_hf_hf_acc |
6517 | 0 | 51U, // V6_vmpy_qf16 |
6518 | 0 | 2946U, // V6_vmpy_qf16_hf |
6519 | 0 | 52U, // V6_vmpy_qf16_mix_hf |
6520 | 0 | 53U, // V6_vmpy_qf32 |
6521 | 0 | 2946U, // V6_vmpy_qf32_hf |
6522 | 0 | 52U, // V6_vmpy_qf32_mix_hf |
6523 | 0 | 51U, // V6_vmpy_qf32_qf16 |
6524 | 0 | 3010U, // V6_vmpy_qf32_sf |
6525 | 0 | 3074U, // V6_vmpy_sf_bf |
6526 | 0 | 3077U, // V6_vmpy_sf_bf_acc |
6527 | 0 | 2946U, // V6_vmpy_sf_hf |
6528 | 0 | 2949U, // V6_vmpy_sf_hf_acc |
6529 | 0 | 3010U, // V6_vmpy_sf_sf |
6530 | 0 | 3650U, // V6_vmpybus |
6531 | 0 | 3653U, // V6_vmpybus_acc |
6532 | 0 | 3650U, // V6_vmpybusv |
6533 | 0 | 3653U, // V6_vmpybusv_acc |
6534 | 0 | 3650U, // V6_vmpybv |
6535 | 0 | 3653U, // V6_vmpybv_acc |
6536 | 0 | 0U, // V6_vmpyewuh |
6537 | 0 | 0U, // V6_vmpyewuh_64 |
6538 | 0 | 0U, // V6_vmpyh |
6539 | 0 | 0U, // V6_vmpyh_acc |
6540 | 0 | 0U, // V6_vmpyhsat_acc |
6541 | 0 | 1730U, // V6_vmpyhsrs |
6542 | 0 | 1794U, // V6_vmpyhss |
6543 | 0 | 0U, // V6_vmpyhus |
6544 | 0 | 0U, // V6_vmpyhus_acc |
6545 | 0 | 0U, // V6_vmpyhv |
6546 | 0 | 0U, // V6_vmpyhv_acc |
6547 | 0 | 1730U, // V6_vmpyhvsrs |
6548 | 0 | 0U, // V6_vmpyieoh |
6549 | 0 | 0U, // V6_vmpyiewh_acc |
6550 | 0 | 0U, // V6_vmpyiewuh |
6551 | 0 | 0U, // V6_vmpyiewuh_acc |
6552 | 0 | 0U, // V6_vmpyih |
6553 | 0 | 0U, // V6_vmpyih_acc |
6554 | 0 | 0U, // V6_vmpyihb |
6555 | 0 | 0U, // V6_vmpyihb_acc |
6556 | 0 | 0U, // V6_vmpyiowh |
6557 | 0 | 0U, // V6_vmpyiwb |
6558 | 0 | 0U, // V6_vmpyiwb_acc |
6559 | 0 | 0U, // V6_vmpyiwh |
6560 | 0 | 0U, // V6_vmpyiwh_acc |
6561 | 0 | 0U, // V6_vmpyiwub |
6562 | 0 | 0U, // V6_vmpyiwub_acc |
6563 | 0 | 0U, // V6_vmpyowh |
6564 | 0 | 0U, // V6_vmpyowh_64_acc |
6565 | 0 | 0U, // V6_vmpyowh_rnd |
6566 | 0 | 0U, // V6_vmpyowh_rnd_sacc |
6567 | 0 | 0U, // V6_vmpyowh_sacc |
6568 | 0 | 386U, // V6_vmpyub |
6569 | 0 | 0U, // V6_vmpyub_acc |
6570 | 0 | 386U, // V6_vmpyubv |
6571 | 0 | 0U, // V6_vmpyubv_acc |
6572 | 0 | 0U, // V6_vmpyuh |
6573 | 0 | 0U, // V6_vmpyuh_acc |
6574 | 0 | 0U, // V6_vmpyuhe |
6575 | 0 | 0U, // V6_vmpyuhe_acc |
6576 | 0 | 0U, // V6_vmpyuhv |
6577 | 0 | 0U, // V6_vmpyuhv_acc |
6578 | 0 | 3778U, // V6_vmpyuhvs |
6579 | 0 | 0U, // V6_vmux |
6580 | 0 | 3650U, // V6_vnavgb |
6581 | 0 | 0U, // V6_vnavgh |
6582 | 0 | 386U, // V6_vnavgub |
6583 | 0 | 0U, // V6_vnavgw |
6584 | 0 | 0U, // V6_vnccombine |
6585 | 0 | 0U, // V6_vncmov |
6586 | 0 | 0U, // V6_vnormamth |
6587 | 0 | 0U, // V6_vnormamtw |
6588 | 0 | 0U, // V6_vnot |
6589 | 0 | 0U, // V6_vor |
6590 | 0 | 0U, // V6_vpackeb |
6591 | 0 | 0U, // V6_vpackeh |
6592 | 0 | 0U, // V6_vpackhb_sat |
6593 | 0 | 0U, // V6_vpackhub_sat |
6594 | 0 | 0U, // V6_vpackob |
6595 | 0 | 0U, // V6_vpackoh |
6596 | 0 | 0U, // V6_vpackwh_sat |
6597 | 0 | 0U, // V6_vpackwuh_sat |
6598 | 0 | 0U, // V6_vpopcounth |
6599 | 0 | 0U, // V6_vprefixqb |
6600 | 0 | 0U, // V6_vprefixqh |
6601 | 0 | 0U, // V6_vprefixqw |
6602 | 0 | 0U, // V6_vrdelta |
6603 | 0 | 386U, // V6_vrmpybub_rtt |
6604 | 0 | 389U, // V6_vrmpybub_rtt_acc |
6605 | 0 | 3650U, // V6_vrmpybus |
6606 | 0 | 3653U, // V6_vrmpybus_acc |
6607 | 0 | 40706U, // V6_vrmpybusi |
6608 | 0 | 57093U, // V6_vrmpybusi_acc |
6609 | 0 | 3650U, // V6_vrmpybusv |
6610 | 0 | 3653U, // V6_vrmpybusv_acc |
6611 | 0 | 3650U, // V6_vrmpybv |
6612 | 0 | 3653U, // V6_vrmpybv_acc |
6613 | 0 | 0U, // V6_vrmpyub |
6614 | 0 | 0U, // V6_vrmpyub_acc |
6615 | 0 | 0U, // V6_vrmpyub_rtt |
6616 | 0 | 0U, // V6_vrmpyub_rtt_acc |
6617 | 0 | 69U, // V6_vrmpyubi |
6618 | 0 | 73U, // V6_vrmpyubi_acc |
6619 | 0 | 0U, // V6_vrmpyubv |
6620 | 0 | 0U, // V6_vrmpyubv_acc |
6621 | 0 | 45113U, // V6_vrmpyzbb_rt |
6622 | 0 | 46329U, // V6_vrmpyzbb_rt_acc |
6623 | 0 | 53113U, // V6_vrmpyzbb_rx |
6624 | 0 | 53113U, // V6_vrmpyzbb_rx_acc |
6625 | 0 | 53305U, // V6_vrmpyzbub_rt |
6626 | 0 | 54521U, // V6_vrmpyzbub_rt_acc |
6627 | 0 | 61305U, // V6_vrmpyzbub_rx |
6628 | 0 | 61305U, // V6_vrmpyzbub_rx_acc |
6629 | 0 | 45114U, // V6_vrmpyzcb_rt |
6630 | 0 | 46330U, // V6_vrmpyzcb_rt_acc |
6631 | 0 | 53114U, // V6_vrmpyzcb_rx |
6632 | 0 | 53114U, // V6_vrmpyzcb_rx_acc |
6633 | 0 | 45114U, // V6_vrmpyzcbs_rt |
6634 | 0 | 46330U, // V6_vrmpyzcbs_rt_acc |
6635 | 0 | 53114U, // V6_vrmpyzcbs_rx |
6636 | 0 | 53114U, // V6_vrmpyzcbs_rx_acc |
6637 | 0 | 45115U, // V6_vrmpyznb_rt |
6638 | 0 | 46331U, // V6_vrmpyznb_rt_acc |
6639 | 0 | 53115U, // V6_vrmpyznb_rx |
6640 | 0 | 53115U, // V6_vrmpyznb_rx_acc |
6641 | 0 | 0U, // V6_vror |
6642 | 0 | 0U, // V6_vrotr |
6643 | 0 | 0U, // V6_vroundhb |
6644 | 0 | 1090U, // V6_vroundhub |
6645 | 0 | 3522U, // V6_vrounduhub |
6646 | 0 | 3970U, // V6_vrounduwuh |
6647 | 0 | 0U, // V6_vroundwh |
6648 | 0 | 4034U, // V6_vroundwuh |
6649 | 0 | 0U, // V6_vrsadubi |
6650 | 0 | 0U, // V6_vrsadubi_acc |
6651 | 0 | 0U, // V6_vsatdw |
6652 | 0 | 0U, // V6_vsathub |
6653 | 0 | 0U, // V6_vsatuwuh |
6654 | 0 | 0U, // V6_vsatwh |
6655 | 0 | 0U, // V6_vsb |
6656 | 0 | 61440U, // V6_vscattermh |
6657 | 0 | 0U, // V6_vscattermh_add |
6658 | 0 | 0U, // V6_vscattermhq |
6659 | 0 | 4096U, // V6_vscattermhw |
6660 | 0 | 8192U, // V6_vscattermhw_add |
6661 | 0 | 0U, // V6_vscattermhwq |
6662 | 0 | 12288U, // V6_vscattermw |
6663 | 0 | 16384U, // V6_vscattermw_add |
6664 | 0 | 0U, // V6_vscattermwq |
6665 | 0 | 0U, // V6_vsh |
6666 | 0 | 962U, // V6_vshufeh |
6667 | 0 | 640U, // V6_vshuff |
6668 | 0 | 0U, // V6_vshuffb |
6669 | 0 | 3650U, // V6_vshuffeb |
6670 | 0 | 0U, // V6_vshuffh |
6671 | 0 | 0U, // V6_vshuffob |
6672 | 0 | 0U, // V6_vshuffvdd |
6673 | 0 | 0U, // V6_vshufoeb |
6674 | 0 | 0U, // V6_vshufoeh |
6675 | 0 | 0U, // V6_vshufoh |
6676 | 0 | 2946U, // V6_vsub_hf |
6677 | 0 | 0U, // V6_vsub_hf_hf |
6678 | 0 | 51U, // V6_vsub_qf16 |
6679 | 0 | 52U, // V6_vsub_qf16_mix |
6680 | 0 | 53U, // V6_vsub_qf32 |
6681 | 0 | 54U, // V6_vsub_qf32_mix |
6682 | 0 | 3010U, // V6_vsub_sf |
6683 | 0 | 3074U, // V6_vsub_sf_bf |
6684 | 0 | 2946U, // V6_vsub_sf_hf |
6685 | 0 | 3010U, // V6_vsub_sf_sf |
6686 | 0 | 0U, // V6_vsubb |
6687 | 0 | 0U, // V6_vsubb_dv |
6688 | 0 | 0U, // V6_vsubbnq |
6689 | 0 | 0U, // V6_vsubbq |
6690 | 0 | 0U, // V6_vsubbsat |
6691 | 0 | 0U, // V6_vsubbsat_dv |
6692 | 0 | 9463U, // V6_vsubcarry |
6693 | 0 | 0U, // V6_vsubcarryo |
6694 | 0 | 962U, // V6_vsubh |
6695 | 0 | 962U, // V6_vsubh_dv |
6696 | 0 | 0U, // V6_vsubhnq |
6697 | 0 | 0U, // V6_vsubhq |
6698 | 0 | 1090U, // V6_vsubhsat |
6699 | 0 | 1090U, // V6_vsubhsat_dv |
6700 | 0 | 974U, // V6_vsubhw |
6701 | 0 | 386U, // V6_vsububh |
6702 | 0 | 0U, // V6_vsububsat |
6703 | 0 | 0U, // V6_vsububsat_dv |
6704 | 0 | 0U, // V6_vsubububb_sat |
6705 | 0 | 0U, // V6_vsubuhsat |
6706 | 0 | 0U, // V6_vsubuhsat_dv |
6707 | 0 | 56U, // V6_vsubuhw |
6708 | 0 | 0U, // V6_vsubuwsat |
6709 | 0 | 0U, // V6_vsubuwsat_dv |
6710 | 0 | 12343U, // V6_vsubw |
6711 | 0 | 12343U, // V6_vsubw_dv |
6712 | 0 | 0U, // V6_vsubwnq |
6713 | 0 | 0U, // V6_vsubwq |
6714 | 0 | 16439U, // V6_vsubwsat |
6715 | 0 | 16439U, // V6_vsubwsat_dv |
6716 | 0 | 0U, // V6_vswap |
6717 | 0 | 3650U, // V6_vtmpyb |
6718 | 0 | 3653U, // V6_vtmpyb_acc |
6719 | 0 | 3650U, // V6_vtmpybus |
6720 | 0 | 3653U, // V6_vtmpybus_acc |
6721 | 0 | 0U, // V6_vtmpyhb |
6722 | 0 | 0U, // V6_vtmpyhb_acc |
6723 | 0 | 0U, // V6_vunpackb |
6724 | 0 | 0U, // V6_vunpackh |
6725 | 0 | 0U, // V6_vunpackob |
6726 | 0 | 0U, // V6_vunpackoh |
6727 | 0 | 0U, // V6_vunpackub |
6728 | 0 | 0U, // V6_vunpackuh |
6729 | 0 | 0U, // V6_vwhist128 |
6730 | 0 | 0U, // V6_vwhist128m |
6731 | 0 | 0U, // V6_vwhist128q |
6732 | 0 | 1U, // V6_vwhist128qm |
6733 | 0 | 0U, // V6_vwhist256 |
6734 | 0 | 0U, // V6_vwhist256_sat |
6735 | 0 | 0U, // V6_vwhist256q |
6736 | 0 | 0U, // V6_vwhist256q_sat |
6737 | 0 | 0U, // V6_vxor |
6738 | 0 | 0U, // V6_vzb |
6739 | 0 | 0U, // V6_vzh |
6740 | 0 | 0U, // V6_zLd_ai |
6741 | 0 | 0U, // V6_zLd_pi |
6742 | 0 | 0U, // V6_zLd_ppu |
6743 | 0 | 32U, // V6_zLd_pred_ai |
6744 | 0 | 1250U, // V6_zLd_pred_pi |
6745 | 0 | 1249U, // V6_zLd_pred_ppu |
6746 | 0 | 0U, // V6_zextract |
6747 | 0 | 0U, // Y2_barrier |
6748 | 0 | 0U, // Y2_break |
6749 | 0 | 0U, // Y2_ciad |
6750 | 0 | 0U, // Y2_crswap0 |
6751 | 0 | 0U, // Y2_cswi |
6752 | 0 | 0U, // Y2_dccleana |
6753 | 0 | 0U, // Y2_dccleanidx |
6754 | 0 | 0U, // Y2_dccleaninva |
6755 | 0 | 0U, // Y2_dccleaninvidx |
6756 | 0 | 0U, // Y2_dcfetchbo |
6757 | 0 | 0U, // Y2_dcinva |
6758 | 0 | 0U, // Y2_dcinvidx |
6759 | 0 | 0U, // Y2_dckill |
6760 | 0 | 0U, // Y2_dctagr |
6761 | 0 | 1U, // Y2_dctagw |
6762 | 0 | 0U, // Y2_dczeroa |
6763 | 0 | 0U, // Y2_getimask |
6764 | 0 | 0U, // Y2_iassignr |
6765 | 0 | 0U, // Y2_iassignw |
6766 | 0 | 0U, // Y2_icdatar |
6767 | 0 | 1U, // Y2_icdataw |
6768 | 0 | 0U, // Y2_icinva |
6769 | 0 | 0U, // Y2_icinvidx |
6770 | 0 | 0U, // Y2_ickill |
6771 | 0 | 0U, // Y2_ictagr |
6772 | 0 | 1U, // Y2_ictagw |
6773 | 0 | 0U, // Y2_isync |
6774 | 0 | 0U, // Y2_k0lock |
6775 | 0 | 0U, // Y2_k0unlock |
6776 | 0 | 0U, // Y2_l2cleaninvidx |
6777 | 0 | 0U, // Y2_l2kill |
6778 | 0 | 0U, // Y2_resume |
6779 | 0 | 1U, // Y2_setimask |
6780 | 0 | 1U, // Y2_setprio |
6781 | 0 | 0U, // Y2_start |
6782 | 0 | 0U, // Y2_stop |
6783 | 0 | 0U, // Y2_swi |
6784 | 0 | 0U, // Y2_syncht |
6785 | 0 | 0U, // Y2_tfrscrr |
6786 | 0 | 0U, // Y2_tfrsrcr |
6787 | 0 | 0U, // Y2_tlblock |
6788 | 0 | 0U, // Y2_tlbp |
6789 | 0 | 0U, // Y2_tlbr |
6790 | 0 | 0U, // Y2_tlbunlock |
6791 | 0 | 1U, // Y2_tlbw |
6792 | 0 | 0U, // Y2_wait |
6793 | 0 | 0U, // Y4_crswap1 |
6794 | 0 | 1U, // Y4_crswap10 |
6795 | 0 | 1U, // Y4_l2fetch |
6796 | 0 | 0U, // Y4_l2tagr |
6797 | 0 | 1U, // Y4_l2tagw |
6798 | 0 | 0U, // Y4_nmi |
6799 | 0 | 0U, // Y4_siad |
6800 | 0 | 0U, // Y4_tfrscpp |
6801 | 0 | 0U, // Y4_tfrspcp |
6802 | 0 | 0U, // Y4_trace |
6803 | 0 | 0U, // Y5_ctlbw |
6804 | 0 | 0U, // Y5_l2cleanidx |
6805 | 0 | 1U, // Y5_l2fetch |
6806 | 0 | 0U, // Y5_l2gclean |
6807 | 0 | 0U, // Y5_l2gcleaninv |
6808 | 0 | 0U, // Y5_l2gunlock |
6809 | 0 | 0U, // Y5_l2invidx |
6810 | 0 | 0U, // Y5_l2locka |
6811 | 0 | 0U, // Y5_l2unlocka |
6812 | 0 | 0U, // Y5_tlbasidi |
6813 | 0 | 0U, // Y5_tlboc |
6814 | 0 | 0U, // Y6_diag |
6815 | 0 | 1U, // Y6_diag0 |
6816 | 0 | 1U, // Y6_diag1 |
6817 | 0 | 1U, // Y6_dmlink |
6818 | 0 | 0U, // Y6_dmpause |
6819 | 0 | 0U, // Y6_dmpoll |
6820 | 0 | 0U, // Y6_dmresume |
6821 | 0 | 0U, // Y6_dmstart |
6822 | 0 | 0U, // Y6_dmwait |
6823 | 0 | 0U, // Y6_l2gcleaninvpa |
6824 | 0 | 0U, // Y6_l2gcleanpa |
6825 | 0 | 20480U, // dep_A2_addsat |
6826 | 0 | 20480U, // dep_A2_subsat |
6827 | 0 | 0U, // dep_S2_packhl |
6828 | 0 | 0U, // invalid_decode |
6829 | 0 | }; |
6830 | |
|
6831 | 0 | static const uint8_t OpInfo2[] = { |
6832 | 0 | 0U, // PHI |
6833 | 0 | 0U, // INLINEASM |
6834 | 0 | 0U, // INLINEASM_BR |
6835 | 0 | 0U, // CFI_INSTRUCTION |
6836 | 0 | 0U, // EH_LABEL |
6837 | 0 | 0U, // GC_LABEL |
6838 | 0 | 0U, // ANNOTATION_LABEL |
6839 | 0 | 0U, // KILL |
6840 | 0 | 0U, // EXTRACT_SUBREG |
6841 | 0 | 0U, // INSERT_SUBREG |
6842 | 0 | 0U, // IMPLICIT_DEF |
6843 | 0 | 0U, // SUBREG_TO_REG |
6844 | 0 | 0U, // COPY_TO_REGCLASS |
6845 | 0 | 0U, // DBG_VALUE |
6846 | 0 | 0U, // DBG_VALUE_LIST |
6847 | 0 | 0U, // DBG_INSTR_REF |
6848 | 0 | 0U, // DBG_PHI |
6849 | 0 | 0U, // DBG_LABEL |
6850 | 0 | 0U, // REG_SEQUENCE |
6851 | 0 | 0U, // COPY |
6852 | 0 | 0U, // BUNDLE |
6853 | 0 | 0U, // LIFETIME_START |
6854 | 0 | 0U, // LIFETIME_END |
6855 | 0 | 0U, // PSEUDO_PROBE |
6856 | 0 | 0U, // ARITH_FENCE |
6857 | 0 | 0U, // STACKMAP |
6858 | 0 | 0U, // FENTRY_CALL |
6859 | 0 | 0U, // PATCHPOINT |
6860 | 0 | 0U, // LOAD_STACK_GUARD |
6861 | 0 | 0U, // PREALLOCATED_SETUP |
6862 | 0 | 0U, // PREALLOCATED_ARG |
6863 | 0 | 0U, // STATEPOINT |
6864 | 0 | 0U, // LOCAL_ESCAPE |
6865 | 0 | 0U, // FAULTING_OP |
6866 | 0 | 0U, // PATCHABLE_OP |
6867 | 0 | 0U, // PATCHABLE_FUNCTION_ENTER |
6868 | 0 | 0U, // PATCHABLE_RET |
6869 | 0 | 0U, // PATCHABLE_FUNCTION_EXIT |
6870 | 0 | 0U, // PATCHABLE_TAIL_CALL |
6871 | 0 | 0U, // PATCHABLE_EVENT_CALL |
6872 | 0 | 0U, // PATCHABLE_TYPED_EVENT_CALL |
6873 | 0 | 0U, // ICALL_BRANCH_FUNNEL |
6874 | 0 | 0U, // MEMBARRIER |
6875 | 0 | 0U, // JUMP_TABLE_DEBUG_INFO |
6876 | 0 | 0U, // G_ASSERT_SEXT |
6877 | 0 | 0U, // G_ASSERT_ZEXT |
6878 | 0 | 0U, // G_ASSERT_ALIGN |
6879 | 0 | 0U, // G_ADD |
6880 | 0 | 0U, // G_SUB |
6881 | 0 | 0U, // G_MUL |
6882 | 0 | 0U, // G_SDIV |
6883 | 0 | 0U, // G_UDIV |
6884 | 0 | 0U, // G_SREM |
6885 | 0 | 0U, // G_UREM |
6886 | 0 | 0U, // G_SDIVREM |
6887 | 0 | 0U, // G_UDIVREM |
6888 | 0 | 0U, // G_AND |
6889 | 0 | 0U, // G_OR |
6890 | 0 | 0U, // G_XOR |
6891 | 0 | 0U, // G_IMPLICIT_DEF |
6892 | 0 | 0U, // G_PHI |
6893 | 0 | 0U, // G_FRAME_INDEX |
6894 | 0 | 0U, // G_GLOBAL_VALUE |
6895 | 0 | 0U, // G_CONSTANT_POOL |
6896 | 0 | 0U, // G_EXTRACT |
6897 | 0 | 0U, // G_UNMERGE_VALUES |
6898 | 0 | 0U, // G_INSERT |
6899 | 0 | 0U, // G_MERGE_VALUES |
6900 | 0 | 0U, // G_BUILD_VECTOR |
6901 | 0 | 0U, // G_BUILD_VECTOR_TRUNC |
6902 | 0 | 0U, // G_CONCAT_VECTORS |
6903 | 0 | 0U, // G_PTRTOINT |
6904 | 0 | 0U, // G_INTTOPTR |
6905 | 0 | 0U, // G_BITCAST |
6906 | 0 | 0U, // G_FREEZE |
6907 | 0 | 0U, // G_CONSTANT_FOLD_BARRIER |
6908 | 0 | 0U, // G_INTRINSIC_FPTRUNC_ROUND |
6909 | 0 | 0U, // G_INTRINSIC_TRUNC |
6910 | 0 | 0U, // G_INTRINSIC_ROUND |
6911 | 0 | 0U, // G_INTRINSIC_LRINT |
6912 | 0 | 0U, // G_INTRINSIC_ROUNDEVEN |
6913 | 0 | 0U, // G_READCYCLECOUNTER |
6914 | 0 | 0U, // G_LOAD |
6915 | 0 | 0U, // G_SEXTLOAD |
6916 | 0 | 0U, // G_ZEXTLOAD |
6917 | 0 | 0U, // G_INDEXED_LOAD |
6918 | 0 | 0U, // G_INDEXED_SEXTLOAD |
6919 | 0 | 0U, // G_INDEXED_ZEXTLOAD |
6920 | 0 | 0U, // G_STORE |
6921 | 0 | 0U, // G_INDEXED_STORE |
6922 | 0 | 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
6923 | 0 | 0U, // G_ATOMIC_CMPXCHG |
6924 | 0 | 0U, // G_ATOMICRMW_XCHG |
6925 | 0 | 0U, // G_ATOMICRMW_ADD |
6926 | 0 | 0U, // G_ATOMICRMW_SUB |
6927 | 0 | 0U, // G_ATOMICRMW_AND |
6928 | 0 | 0U, // G_ATOMICRMW_NAND |
6929 | 0 | 0U, // G_ATOMICRMW_OR |
6930 | 0 | 0U, // G_ATOMICRMW_XOR |
6931 | 0 | 0U, // G_ATOMICRMW_MAX |
6932 | 0 | 0U, // G_ATOMICRMW_MIN |
6933 | 0 | 0U, // G_ATOMICRMW_UMAX |
6934 | 0 | 0U, // G_ATOMICRMW_UMIN |
6935 | 0 | 0U, // G_ATOMICRMW_FADD |
6936 | 0 | 0U, // G_ATOMICRMW_FSUB |
6937 | 0 | 0U, // G_ATOMICRMW_FMAX |
6938 | 0 | 0U, // G_ATOMICRMW_FMIN |
6939 | 0 | 0U, // G_ATOMICRMW_UINC_WRAP |
6940 | 0 | 0U, // G_ATOMICRMW_UDEC_WRAP |
6941 | 0 | 0U, // G_FENCE |
6942 | 0 | 0U, // G_PREFETCH |
6943 | 0 | 0U, // G_BRCOND |
6944 | 0 | 0U, // G_BRINDIRECT |
6945 | 0 | 0U, // G_INVOKE_REGION_START |
6946 | 0 | 0U, // G_INTRINSIC |
6947 | 0 | 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
6948 | 0 | 0U, // G_INTRINSIC_CONVERGENT |
6949 | 0 | 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
6950 | 0 | 0U, // G_ANYEXT |
6951 | 0 | 0U, // G_TRUNC |
6952 | 0 | 0U, // G_CONSTANT |
6953 | 0 | 0U, // G_FCONSTANT |
6954 | 0 | 0U, // G_VASTART |
6955 | 0 | 0U, // G_VAARG |
6956 | 0 | 0U, // G_SEXT |
6957 | 0 | 0U, // G_SEXT_INREG |
6958 | 0 | 0U, // G_ZEXT |
6959 | 0 | 0U, // G_SHL |
6960 | 0 | 0U, // G_LSHR |
6961 | 0 | 0U, // G_ASHR |
6962 | 0 | 0U, // G_FSHL |
6963 | 0 | 0U, // G_FSHR |
6964 | 0 | 0U, // G_ROTR |
6965 | 0 | 0U, // G_ROTL |
6966 | 0 | 0U, // G_ICMP |
6967 | 0 | 0U, // G_FCMP |
6968 | 0 | 0U, // G_SELECT |
6969 | 0 | 0U, // G_UADDO |
6970 | 0 | 0U, // G_UADDE |
6971 | 0 | 0U, // G_USUBO |
6972 | 0 | 0U, // G_USUBE |
6973 | 0 | 0U, // G_SADDO |
6974 | 0 | 0U, // G_SADDE |
6975 | 0 | 0U, // G_SSUBO |
6976 | 0 | 0U, // G_SSUBE |
6977 | 0 | 0U, // G_UMULO |
6978 | 0 | 0U, // G_SMULO |
6979 | 0 | 0U, // G_UMULH |
6980 | 0 | 0U, // G_SMULH |
6981 | 0 | 0U, // G_UADDSAT |
6982 | 0 | 0U, // G_SADDSAT |
6983 | 0 | 0U, // G_USUBSAT |
6984 | 0 | 0U, // G_SSUBSAT |
6985 | 0 | 0U, // G_USHLSAT |
6986 | 0 | 0U, // G_SSHLSAT |
6987 | 0 | 0U, // G_SMULFIX |
6988 | 0 | 0U, // G_UMULFIX |
6989 | 0 | 0U, // G_SMULFIXSAT |
6990 | 0 | 0U, // G_UMULFIXSAT |
6991 | 0 | 0U, // G_SDIVFIX |
6992 | 0 | 0U, // G_UDIVFIX |
6993 | 0 | 0U, // G_SDIVFIXSAT |
6994 | 0 | 0U, // G_UDIVFIXSAT |
6995 | 0 | 0U, // G_FADD |
6996 | 0 | 0U, // G_FSUB |
6997 | 0 | 0U, // G_FMUL |
6998 | 0 | 0U, // G_FMA |
6999 | 0 | 0U, // G_FMAD |
7000 | 0 | 0U, // G_FDIV |
7001 | 0 | 0U, // G_FREM |
7002 | 0 | 0U, // G_FPOW |
7003 | 0 | 0U, // G_FPOWI |
7004 | 0 | 0U, // G_FEXP |
7005 | 0 | 0U, // G_FEXP2 |
7006 | 0 | 0U, // G_FEXP10 |
7007 | 0 | 0U, // G_FLOG |
7008 | 0 | 0U, // G_FLOG2 |
7009 | 0 | 0U, // G_FLOG10 |
7010 | 0 | 0U, // G_FLDEXP |
7011 | 0 | 0U, // G_FFREXP |
7012 | 0 | 0U, // G_FNEG |
7013 | 0 | 0U, // G_FPEXT |
7014 | 0 | 0U, // G_FPTRUNC |
7015 | 0 | 0U, // G_FPTOSI |
7016 | 0 | 0U, // G_FPTOUI |
7017 | 0 | 0U, // G_SITOFP |
7018 | 0 | 0U, // G_UITOFP |
7019 | 0 | 0U, // G_FABS |
7020 | 0 | 0U, // G_FCOPYSIGN |
7021 | 0 | 0U, // G_IS_FPCLASS |
7022 | 0 | 0U, // G_FCANONICALIZE |
7023 | 0 | 0U, // G_FMINNUM |
7024 | 0 | 0U, // G_FMAXNUM |
7025 | 0 | 0U, // G_FMINNUM_IEEE |
7026 | 0 | 0U, // G_FMAXNUM_IEEE |
7027 | 0 | 0U, // G_FMINIMUM |
7028 | 0 | 0U, // G_FMAXIMUM |
7029 | 0 | 0U, // G_GET_FPENV |
7030 | 0 | 0U, // G_SET_FPENV |
7031 | 0 | 0U, // G_RESET_FPENV |
7032 | 0 | 0U, // G_GET_FPMODE |
7033 | 0 | 0U, // G_SET_FPMODE |
7034 | 0 | 0U, // G_RESET_FPMODE |
7035 | 0 | 0U, // G_PTR_ADD |
7036 | 0 | 0U, // G_PTRMASK |
7037 | 0 | 0U, // G_SMIN |
7038 | 0 | 0U, // G_SMAX |
7039 | 0 | 0U, // G_UMIN |
7040 | 0 | 0U, // G_UMAX |
7041 | 0 | 0U, // G_ABS |
7042 | 0 | 0U, // G_LROUND |
7043 | 0 | 0U, // G_LLROUND |
7044 | 0 | 0U, // G_BR |
7045 | 0 | 0U, // G_BRJT |
7046 | 0 | 0U, // G_INSERT_VECTOR_ELT |
7047 | 0 | 0U, // G_EXTRACT_VECTOR_ELT |
7048 | 0 | 0U, // G_SHUFFLE_VECTOR |
7049 | 0 | 0U, // G_CTTZ |
7050 | 0 | 0U, // G_CTTZ_ZERO_UNDEF |
7051 | 0 | 0U, // G_CTLZ |
7052 | 0 | 0U, // G_CTLZ_ZERO_UNDEF |
7053 | 0 | 0U, // G_CTPOP |
7054 | 0 | 0U, // G_BSWAP |
7055 | 0 | 0U, // G_BITREVERSE |
7056 | 0 | 0U, // G_FCEIL |
7057 | 0 | 0U, // G_FCOS |
7058 | 0 | 0U, // G_FSIN |
7059 | 0 | 0U, // G_FSQRT |
7060 | 0 | 0U, // G_FFLOOR |
7061 | 0 | 0U, // G_FRINT |
7062 | 0 | 0U, // G_FNEARBYINT |
7063 | 0 | 0U, // G_ADDRSPACE_CAST |
7064 | 0 | 0U, // G_BLOCK_ADDR |
7065 | 0 | 0U, // G_JUMP_TABLE |
7066 | 0 | 0U, // G_DYN_STACKALLOC |
7067 | 0 | 0U, // G_STACKSAVE |
7068 | 0 | 0U, // G_STACKRESTORE |
7069 | 0 | 0U, // G_STRICT_FADD |
7070 | 0 | 0U, // G_STRICT_FSUB |
7071 | 0 | 0U, // G_STRICT_FMUL |
7072 | 0 | 0U, // G_STRICT_FDIV |
7073 | 0 | 0U, // G_STRICT_FREM |
7074 | 0 | 0U, // G_STRICT_FMA |
7075 | 0 | 0U, // G_STRICT_FSQRT |
7076 | 0 | 0U, // G_STRICT_FLDEXP |
7077 | 0 | 0U, // G_READ_REGISTER |
7078 | 0 | 0U, // G_WRITE_REGISTER |
7079 | 0 | 0U, // G_MEMCPY |
7080 | 0 | 0U, // G_MEMCPY_INLINE |
7081 | 0 | 0U, // G_MEMMOVE |
7082 | 0 | 0U, // G_MEMSET |
7083 | 0 | 0U, // G_BZERO |
7084 | 0 | 0U, // G_VECREDUCE_SEQ_FADD |
7085 | 0 | 0U, // G_VECREDUCE_SEQ_FMUL |
7086 | 0 | 0U, // G_VECREDUCE_FADD |
7087 | 0 | 0U, // G_VECREDUCE_FMUL |
7088 | 0 | 0U, // G_VECREDUCE_FMAX |
7089 | 0 | 0U, // G_VECREDUCE_FMIN |
7090 | 0 | 0U, // G_VECREDUCE_FMAXIMUM |
7091 | 0 | 0U, // G_VECREDUCE_FMINIMUM |
7092 | 0 | 0U, // G_VECREDUCE_ADD |
7093 | 0 | 0U, // G_VECREDUCE_MUL |
7094 | 0 | 0U, // G_VECREDUCE_AND |
7095 | 0 | 0U, // G_VECREDUCE_OR |
7096 | 0 | 0U, // G_VECREDUCE_XOR |
7097 | 0 | 0U, // G_VECREDUCE_SMAX |
7098 | 0 | 0U, // G_VECREDUCE_SMIN |
7099 | 0 | 0U, // G_VECREDUCE_UMAX |
7100 | 0 | 0U, // G_VECREDUCE_UMIN |
7101 | 0 | 0U, // G_SBFX |
7102 | 0 | 0U, // G_UBFX |
7103 | 0 | 0U, // A2_addsp |
7104 | 0 | 0U, // A2_iconst |
7105 | 0 | 0U, // A2_neg |
7106 | 0 | 0U, // A2_not |
7107 | 0 | 0U, // A2_tfrf |
7108 | 0 | 0U, // A2_tfrfnew |
7109 | 0 | 0U, // A2_tfrp |
7110 | 0 | 0U, // A2_tfrpf |
7111 | 0 | 0U, // A2_tfrpfnew |
7112 | 0 | 0U, // A2_tfrpi |
7113 | 0 | 0U, // A2_tfrpt |
7114 | 0 | 0U, // A2_tfrptnew |
7115 | 0 | 0U, // A2_tfrt |
7116 | 0 | 0U, // A2_tfrtnew |
7117 | 0 | 0U, // A2_vaddb_map |
7118 | 0 | 0U, // A2_vsubb_map |
7119 | 0 | 0U, // A2_zxtb |
7120 | 0 | 0U, // A4_boundscheck |
7121 | 0 | 0U, // ADJCALLSTACKDOWN |
7122 | 0 | 0U, // ADJCALLSTACKUP |
7123 | 0 | 0U, // C2_cmpgei |
7124 | 0 | 0U, // C2_cmpgeui |
7125 | 0 | 0U, // C2_cmplt |
7126 | 0 | 0U, // C2_cmpltu |
7127 | 0 | 0U, // C2_pxfer_map |
7128 | 0 | 0U, // DUPLEX_Pseudo |
7129 | 0 | 0U, // ENDLOOP0 |
7130 | 0 | 0U, // ENDLOOP01 |
7131 | 0 | 0U, // ENDLOOP1 |
7132 | 0 | 0U, // J2_endloop0 |
7133 | 0 | 0U, // J2_endloop01 |
7134 | 0 | 0U, // J2_endloop1 |
7135 | 0 | 0U, // J2_jumpf_nopred_map |
7136 | 0 | 0U, // J2_jumprf_nopred_map |
7137 | 0 | 0U, // J2_jumprt_nopred_map |
7138 | 0 | 0U, // J2_jumpt_nopred_map |
7139 | 0 | 0U, // J2_trap1_noregmap |
7140 | 0 | 0U, // L2_loadalignb_zomap |
7141 | 0 | 0U, // L2_loadalignh_zomap |
7142 | 0 | 0U, // L2_loadbsw2_zomap |
7143 | 0 | 0U, // L2_loadbsw4_zomap |
7144 | 0 | 0U, // L2_loadbzw2_zomap |
7145 | 0 | 0U, // L2_loadbzw4_zomap |
7146 | 0 | 0U, // L2_loadrb_zomap |
7147 | 0 | 0U, // L2_loadrd_zomap |
7148 | 0 | 0U, // L2_loadrh_zomap |
7149 | 0 | 0U, // L2_loadri_zomap |
7150 | 0 | 0U, // L2_loadrub_zomap |
7151 | 0 | 0U, // L2_loadruh_zomap |
7152 | 0 | 0U, // L2_ploadrbf_zomap |
7153 | 0 | 0U, // L2_ploadrbfnew_zomap |
7154 | 0 | 0U, // L2_ploadrbt_zomap |
7155 | 0 | 0U, // L2_ploadrbtnew_zomap |
7156 | 0 | 0U, // L2_ploadrdf_zomap |
7157 | 0 | 0U, // L2_ploadrdfnew_zomap |
7158 | 0 | 0U, // L2_ploadrdt_zomap |
7159 | 0 | 0U, // L2_ploadrdtnew_zomap |
7160 | 0 | 0U, // L2_ploadrhf_zomap |
7161 | 0 | 0U, // L2_ploadrhfnew_zomap |
7162 | 0 | 0U, // L2_ploadrht_zomap |
7163 | 0 | 0U, // L2_ploadrhtnew_zomap |
7164 | 0 | 0U, // L2_ploadrif_zomap |
7165 | 0 | 0U, // L2_ploadrifnew_zomap |
7166 | 0 | 0U, // L2_ploadrit_zomap |
7167 | 0 | 0U, // L2_ploadritnew_zomap |
7168 | 0 | 0U, // L2_ploadrubf_zomap |
7169 | 0 | 0U, // L2_ploadrubfnew_zomap |
7170 | 0 | 0U, // L2_ploadrubt_zomap |
7171 | 0 | 0U, // L2_ploadrubtnew_zomap |
7172 | 0 | 0U, // L2_ploadruhf_zomap |
7173 | 0 | 0U, // L2_ploadruhfnew_zomap |
7174 | 0 | 0U, // L2_ploadruht_zomap |
7175 | 0 | 0U, // L2_ploadruhtnew_zomap |
7176 | 0 | 0U, // L4_add_memopb_zomap |
7177 | 0 | 0U, // L4_add_memoph_zomap |
7178 | 0 | 0U, // L4_add_memopw_zomap |
7179 | 0 | 0U, // L4_and_memopb_zomap |
7180 | 0 | 0U, // L4_and_memoph_zomap |
7181 | 0 | 0U, // L4_and_memopw_zomap |
7182 | 0 | 0U, // L4_iadd_memopb_zomap |
7183 | 0 | 0U, // L4_iadd_memoph_zomap |
7184 | 0 | 0U, // L4_iadd_memopw_zomap |
7185 | 0 | 0U, // L4_iand_memopb_zomap |
7186 | 0 | 0U, // L4_iand_memoph_zomap |
7187 | 0 | 0U, // L4_iand_memopw_zomap |
7188 | 0 | 0U, // L4_ior_memopb_zomap |
7189 | 0 | 0U, // L4_ior_memoph_zomap |
7190 | 0 | 0U, // L4_ior_memopw_zomap |
7191 | 0 | 0U, // L4_isub_memopb_zomap |
7192 | 0 | 0U, // L4_isub_memoph_zomap |
7193 | 0 | 0U, // L4_isub_memopw_zomap |
7194 | 0 | 0U, // L4_or_memopb_zomap |
7195 | 0 | 0U, // L4_or_memoph_zomap |
7196 | 0 | 0U, // L4_or_memopw_zomap |
7197 | 0 | 0U, // L4_return_map_to_raw_f |
7198 | 0 | 0U, // L4_return_map_to_raw_fnew_pnt |
7199 | 0 | 0U, // L4_return_map_to_raw_fnew_pt |
7200 | 0 | 0U, // L4_return_map_to_raw_t |
7201 | 0 | 0U, // L4_return_map_to_raw_tnew_pnt |
7202 | 0 | 0U, // L4_return_map_to_raw_tnew_pt |
7203 | 0 | 0U, // L4_sub_memopb_zomap |
7204 | 0 | 0U, // L4_sub_memoph_zomap |
7205 | 0 | 0U, // L4_sub_memopw_zomap |
7206 | 0 | 0U, // L6_deallocframe_map_to_raw |
7207 | 0 | 0U, // L6_return_map_to_raw |
7208 | 0 | 0U, // LDriw_ctr |
7209 | 0 | 0U, // LDriw_pred |
7210 | 0 | 0U, // M2_mpysmi |
7211 | 0 | 0U, // M2_mpyui |
7212 | 0 | 0U, // M2_vrcmpys_acc_s1 |
7213 | 0 | 0U, // M2_vrcmpys_s1 |
7214 | 0 | 0U, // M2_vrcmpys_s1rp |
7215 | 0 | 0U, // M7_vdmpy |
7216 | 0 | 0U, // M7_vdmpy_acc |
7217 | 0 | 0U, // PS_aligna |
7218 | 0 | 0U, // PS_alloca |
7219 | 0 | 0U, // PS_call_instrprof_custom |
7220 | 0 | 0U, // PS_call_nr |
7221 | 0 | 0U, // PS_crash |
7222 | 0 | 0U, // PS_false |
7223 | 0 | 0U, // PS_fi |
7224 | 0 | 0U, // PS_fia |
7225 | 0 | 0U, // PS_loadrb_pci |
7226 | 0 | 0U, // PS_loadrb_pcr |
7227 | 0 | 0U, // PS_loadrd_pci |
7228 | 0 | 0U, // PS_loadrd_pcr |
7229 | 0 | 0U, // PS_loadrh_pci |
7230 | 0 | 0U, // PS_loadrh_pcr |
7231 | 0 | 0U, // PS_loadri_pci |
7232 | 0 | 0U, // PS_loadri_pcr |
7233 | 0 | 0U, // PS_loadrub_pci |
7234 | 0 | 0U, // PS_loadrub_pcr |
7235 | 0 | 0U, // PS_loadruh_pci |
7236 | 0 | 0U, // PS_loadruh_pcr |
7237 | 0 | 0U, // PS_pselect |
7238 | 0 | 0U, // PS_qfalse |
7239 | 0 | 0U, // PS_qtrue |
7240 | 0 | 0U, // PS_storerb_pci |
7241 | 0 | 0U, // PS_storerb_pcr |
7242 | 0 | 0U, // PS_storerd_pci |
7243 | 0 | 0U, // PS_storerd_pcr |
7244 | 0 | 0U, // PS_storerf_pci |
7245 | 0 | 0U, // PS_storerf_pcr |
7246 | 0 | 0U, // PS_storerh_pci |
7247 | 0 | 0U, // PS_storerh_pcr |
7248 | 0 | 0U, // PS_storeri_pci |
7249 | 0 | 0U, // PS_storeri_pcr |
7250 | 0 | 0U, // PS_tailcall_i |
7251 | 0 | 0U, // PS_tailcall_r |
7252 | 0 | 0U, // PS_true |
7253 | 0 | 0U, // PS_vdd0 |
7254 | 0 | 0U, // PS_vloadrq_ai |
7255 | 0 | 0U, // PS_vloadrv_ai |
7256 | 0 | 0U, // PS_vloadrv_nt_ai |
7257 | 0 | 0U, // PS_vloadrw_ai |
7258 | 0 | 0U, // PS_vloadrw_nt_ai |
7259 | 0 | 0U, // PS_vmulw |
7260 | 0 | 0U, // PS_vmulw_acc |
7261 | 0 | 0U, // PS_vselect |
7262 | 0 | 0U, // PS_vsplatib |
7263 | 0 | 0U, // PS_vsplatih |
7264 | 0 | 0U, // PS_vsplatiw |
7265 | 0 | 0U, // PS_vsplatrb |
7266 | 0 | 0U, // PS_vsplatrh |
7267 | 0 | 0U, // PS_vsplatrw |
7268 | 0 | 0U, // PS_vstorerq_ai |
7269 | 0 | 0U, // PS_vstorerv_ai |
7270 | 0 | 0U, // PS_vstorerv_nt_ai |
7271 | 0 | 0U, // PS_vstorerw_ai |
7272 | 0 | 0U, // PS_vstorerw_nt_ai |
7273 | 0 | 0U, // PS_wselect |
7274 | 0 | 0U, // S2_asr_i_p_rnd_goodsyntax |
7275 | 0 | 0U, // S2_asr_i_r_rnd_goodsyntax |
7276 | 0 | 0U, // S2_pstorerbf_zomap |
7277 | 0 | 0U, // S2_pstorerbnewf_zomap |
7278 | 0 | 0U, // S2_pstorerbnewt_zomap |
7279 | 0 | 0U, // S2_pstorerbt_zomap |
7280 | 0 | 0U, // S2_pstorerdf_zomap |
7281 | 0 | 0U, // S2_pstorerdt_zomap |
7282 | 0 | 0U, // S2_pstorerff_zomap |
7283 | 0 | 0U, // S2_pstorerft_zomap |
7284 | 0 | 0U, // S2_pstorerhf_zomap |
7285 | 0 | 0U, // S2_pstorerhnewf_zomap |
7286 | 0 | 0U, // S2_pstorerhnewt_zomap |
7287 | 0 | 0U, // S2_pstorerht_zomap |
7288 | 0 | 0U, // S2_pstorerif_zomap |
7289 | 0 | 0U, // S2_pstorerinewf_zomap |
7290 | 0 | 0U, // S2_pstorerinewt_zomap |
7291 | 0 | 0U, // S2_pstorerit_zomap |
7292 | 0 | 0U, // S2_storerb_zomap |
7293 | 0 | 0U, // S2_storerbnew_zomap |
7294 | 0 | 0U, // S2_storerd_zomap |
7295 | 0 | 0U, // S2_storerf_zomap |
7296 | 0 | 0U, // S2_storerh_zomap |
7297 | 0 | 0U, // S2_storerhnew_zomap |
7298 | 0 | 0U, // S2_storeri_zomap |
7299 | 0 | 0U, // S2_storerinew_zomap |
7300 | 0 | 0U, // S2_tableidxb_goodsyntax |
7301 | 0 | 0U, // S2_tableidxd_goodsyntax |
7302 | 0 | 0U, // S2_tableidxh_goodsyntax |
7303 | 0 | 0U, // S2_tableidxw_goodsyntax |
7304 | 0 | 0U, // S4_pstorerbfnew_zomap |
7305 | 0 | 0U, // S4_pstorerbnewfnew_zomap |
7306 | 0 | 0U, // S4_pstorerbnewtnew_zomap |
7307 | 0 | 0U, // S4_pstorerbtnew_zomap |
7308 | 0 | 0U, // S4_pstorerdfnew_zomap |
7309 | 0 | 0U, // S4_pstorerdtnew_zomap |
7310 | 0 | 0U, // S4_pstorerffnew_zomap |
7311 | 0 | 0U, // S4_pstorerftnew_zomap |
7312 | 0 | 0U, // S4_pstorerhfnew_zomap |
7313 | 0 | 0U, // S4_pstorerhnewfnew_zomap |
7314 | 0 | 0U, // S4_pstorerhnewtnew_zomap |
7315 | 0 | 0U, // S4_pstorerhtnew_zomap |
7316 | 0 | 0U, // S4_pstorerifnew_zomap |
7317 | 0 | 0U, // S4_pstorerinewfnew_zomap |
7318 | 0 | 0U, // S4_pstorerinewtnew_zomap |
7319 | 0 | 0U, // S4_pstoreritnew_zomap |
7320 | 0 | 0U, // S4_storeirb_zomap |
7321 | 0 | 0U, // S4_storeirbf_zomap |
7322 | 0 | 0U, // S4_storeirbfnew_zomap |
7323 | 0 | 0U, // S4_storeirbt_zomap |
7324 | 0 | 0U, // S4_storeirbtnew_zomap |
7325 | 0 | 0U, // S4_storeirh_zomap |
7326 | 0 | 0U, // S4_storeirhf_zomap |
7327 | 0 | 0U, // S4_storeirhfnew_zomap |
7328 | 0 | 0U, // S4_storeirht_zomap |
7329 | 0 | 0U, // S4_storeirhtnew_zomap |
7330 | 0 | 0U, // S4_storeiri_zomap |
7331 | 0 | 0U, // S4_storeirif_zomap |
7332 | 0 | 0U, // S4_storeirifnew_zomap |
7333 | 0 | 0U, // S4_storeirit_zomap |
7334 | 0 | 0U, // S4_storeiritnew_zomap |
7335 | 0 | 0U, // S5_asrhub_rnd_sat_goodsyntax |
7336 | 0 | 0U, // S5_vasrhrnd_goodsyntax |
7337 | 0 | 0U, // S6_allocframe_to_raw |
7338 | 0 | 0U, // STriw_ctr |
7339 | 0 | 0U, // STriw_pred |
7340 | 0 | 0U, // V6_MAP_equb |
7341 | 0 | 0U, // V6_MAP_equb_and |
7342 | 0 | 0U, // V6_MAP_equb_ior |
7343 | 0 | 0U, // V6_MAP_equb_xor |
7344 | 0 | 0U, // V6_MAP_equh |
7345 | 0 | 0U, // V6_MAP_equh_and |
7346 | 0 | 0U, // V6_MAP_equh_ior |
7347 | 0 | 0U, // V6_MAP_equh_xor |
7348 | 0 | 0U, // V6_MAP_equw |
7349 | 0 | 0U, // V6_MAP_equw_and |
7350 | 0 | 0U, // V6_MAP_equw_ior |
7351 | 0 | 0U, // V6_MAP_equw_xor |
7352 | 0 | 0U, // V6_dbl_ld0 |
7353 | 0 | 0U, // V6_dbl_st0 |
7354 | 0 | 0U, // V6_extractw_alt |
7355 | 0 | 0U, // V6_hi |
7356 | 0 | 0U, // V6_ld0 |
7357 | 0 | 0U, // V6_ldcnp0 |
7358 | 0 | 0U, // V6_ldcnpnt0 |
7359 | 0 | 0U, // V6_ldcp0 |
7360 | 0 | 0U, // V6_ldcpnt0 |
7361 | 0 | 0U, // V6_ldnp0 |
7362 | 0 | 0U, // V6_ldnpnt0 |
7363 | 0 | 0U, // V6_ldnt0 |
7364 | 0 | 0U, // V6_ldp0 |
7365 | 0 | 0U, // V6_ldpnt0 |
7366 | 0 | 0U, // V6_ldtnp0 |
7367 | 0 | 0U, // V6_ldtnpnt0 |
7368 | 0 | 0U, // V6_ldtp0 |
7369 | 0 | 0U, // V6_ldtpnt0 |
7370 | 0 | 0U, // V6_ldu0 |
7371 | 0 | 0U, // V6_lo |
7372 | 0 | 0U, // V6_st0 |
7373 | 0 | 0U, // V6_stn0 |
7374 | 0 | 0U, // V6_stnnt0 |
7375 | 0 | 0U, // V6_stnp0 |
7376 | 0 | 0U, // V6_stnpnt0 |
7377 | 0 | 0U, // V6_stnq0 |
7378 | 0 | 0U, // V6_stnqnt0 |
7379 | 0 | 0U, // V6_stnt0 |
7380 | 0 | 0U, // V6_stp0 |
7381 | 0 | 0U, // V6_stpnt0 |
7382 | 0 | 0U, // V6_stq0 |
7383 | 0 | 0U, // V6_stqnt0 |
7384 | 0 | 0U, // V6_stu0 |
7385 | 0 | 0U, // V6_stunp0 |
7386 | 0 | 0U, // V6_stup0 |
7387 | 0 | 0U, // V6_v10mpyubs10 |
7388 | 0 | 0U, // V6_v10mpyubs10_vxx |
7389 | 0 | 0U, // V6_v6mpyhubs10_alt |
7390 | 0 | 0U, // V6_v6mpyvubs10_alt |
7391 | 0 | 0U, // V6_vabsb_alt |
7392 | 0 | 0U, // V6_vabsb_sat_alt |
7393 | 0 | 0U, // V6_vabsdiffh_alt |
7394 | 0 | 0U, // V6_vabsdiffub_alt |
7395 | 0 | 0U, // V6_vabsdiffuh_alt |
7396 | 0 | 0U, // V6_vabsdiffw_alt |
7397 | 0 | 0U, // V6_vabsh_alt |
7398 | 0 | 0U, // V6_vabsh_sat_alt |
7399 | 0 | 0U, // V6_vabsub_alt |
7400 | 0 | 0U, // V6_vabsuh_alt |
7401 | 0 | 0U, // V6_vabsuw_alt |
7402 | 0 | 0U, // V6_vabsw_alt |
7403 | 0 | 0U, // V6_vabsw_sat_alt |
7404 | 0 | 0U, // V6_vaddb_alt |
7405 | 0 | 0U, // V6_vaddb_dv_alt |
7406 | 0 | 0U, // V6_vaddbnq_alt |
7407 | 0 | 0U, // V6_vaddbq_alt |
7408 | 0 | 0U, // V6_vaddbsat_alt |
7409 | 0 | 0U, // V6_vaddbsat_dv_alt |
7410 | 0 | 0U, // V6_vaddh_alt |
7411 | 0 | 0U, // V6_vaddh_dv_alt |
7412 | 0 | 0U, // V6_vaddhnq_alt |
7413 | 0 | 0U, // V6_vaddhq_alt |
7414 | 0 | 0U, // V6_vaddhsat_alt |
7415 | 0 | 0U, // V6_vaddhsat_dv_alt |
7416 | 0 | 0U, // V6_vaddhw_acc_alt |
7417 | 0 | 0U, // V6_vaddhw_alt |
7418 | 0 | 0U, // V6_vaddubh_acc_alt |
7419 | 0 | 0U, // V6_vaddubh_alt |
7420 | 0 | 0U, // V6_vaddubsat_alt |
7421 | 0 | 0U, // V6_vaddubsat_dv_alt |
7422 | 0 | 0U, // V6_vadduhsat_alt |
7423 | 0 | 0U, // V6_vadduhsat_dv_alt |
7424 | 0 | 0U, // V6_vadduhw_acc_alt |
7425 | 0 | 0U, // V6_vadduhw_alt |
7426 | 0 | 0U, // V6_vadduwsat_alt |
7427 | 0 | 0U, // V6_vadduwsat_dv_alt |
7428 | 0 | 0U, // V6_vaddw_alt |
7429 | 0 | 0U, // V6_vaddw_dv_alt |
7430 | 0 | 0U, // V6_vaddwnq_alt |
7431 | 0 | 0U, // V6_vaddwq_alt |
7432 | 0 | 0U, // V6_vaddwsat_alt |
7433 | 0 | 0U, // V6_vaddwsat_dv_alt |
7434 | 0 | 0U, // V6_vandnqrt_acc_alt |
7435 | 0 | 0U, // V6_vandnqrt_alt |
7436 | 0 | 0U, // V6_vandqrt_acc_alt |
7437 | 0 | 0U, // V6_vandqrt_alt |
7438 | 0 | 0U, // V6_vandvrt_acc_alt |
7439 | 0 | 0U, // V6_vandvrt_alt |
7440 | 0 | 0U, // V6_vaslh_acc_alt |
7441 | 0 | 0U, // V6_vaslh_alt |
7442 | 0 | 0U, // V6_vaslhv_alt |
7443 | 0 | 0U, // V6_vaslw_acc_alt |
7444 | 0 | 0U, // V6_vaslw_alt |
7445 | 0 | 0U, // V6_vaslwv_alt |
7446 | 0 | 0U, // V6_vasr_into_alt |
7447 | 0 | 0U, // V6_vasrh_acc_alt |
7448 | 0 | 0U, // V6_vasrh_alt |
7449 | 0 | 0U, // V6_vasrhv_alt |
7450 | 0 | 0U, // V6_vasrw_acc_alt |
7451 | 0 | 0U, // V6_vasrw_alt |
7452 | 0 | 0U, // V6_vasrwv_alt |
7453 | 0 | 0U, // V6_vassignp |
7454 | 0 | 0U, // V6_vavgb_alt |
7455 | 0 | 0U, // V6_vavgbrnd_alt |
7456 | 0 | 0U, // V6_vavgh_alt |
7457 | 0 | 0U, // V6_vavghrnd_alt |
7458 | 0 | 0U, // V6_vavgub_alt |
7459 | 0 | 0U, // V6_vavgubrnd_alt |
7460 | 0 | 0U, // V6_vavguh_alt |
7461 | 0 | 0U, // V6_vavguhrnd_alt |
7462 | 0 | 0U, // V6_vavguw_alt |
7463 | 0 | 0U, // V6_vavguwrnd_alt |
7464 | 0 | 0U, // V6_vavgw_alt |
7465 | 0 | 0U, // V6_vavgwrnd_alt |
7466 | 0 | 0U, // V6_vcl0h_alt |
7467 | 0 | 0U, // V6_vcl0w_alt |
7468 | 0 | 0U, // V6_vd0 |
7469 | 0 | 0U, // V6_vdd0 |
7470 | 0 | 0U, // V6_vdealb4w_alt |
7471 | 0 | 0U, // V6_vdealb_alt |
7472 | 0 | 0U, // V6_vdealh_alt |
7473 | 0 | 0U, // V6_vdmpybus_acc_alt |
7474 | 0 | 0U, // V6_vdmpybus_alt |
7475 | 0 | 0U, // V6_vdmpybus_dv_acc_alt |
7476 | 0 | 0U, // V6_vdmpybus_dv_alt |
7477 | 0 | 0U, // V6_vdmpyhb_acc_alt |
7478 | 0 | 0U, // V6_vdmpyhb_alt |
7479 | 0 | 0U, // V6_vdmpyhb_dv_acc_alt |
7480 | 0 | 0U, // V6_vdmpyhb_dv_alt |
7481 | 0 | 0U, // V6_vdmpyhisat_acc_alt |
7482 | 0 | 0U, // V6_vdmpyhisat_alt |
7483 | 0 | 0U, // V6_vdmpyhsat_acc_alt |
7484 | 0 | 0U, // V6_vdmpyhsat_alt |
7485 | 0 | 0U, // V6_vdmpyhsuisat_acc_alt |
7486 | 0 | 0U, // V6_vdmpyhsuisat_alt |
7487 | 0 | 0U, // V6_vdmpyhsusat_acc_alt |
7488 | 0 | 0U, // V6_vdmpyhsusat_alt |
7489 | 0 | 0U, // V6_vdmpyhvsat_acc_alt |
7490 | 0 | 0U, // V6_vdmpyhvsat_alt |
7491 | 0 | 0U, // V6_vdsaduh_acc_alt |
7492 | 0 | 0U, // V6_vdsaduh_alt |
7493 | 0 | 0U, // V6_vgathermh_pseudo |
7494 | 0 | 0U, // V6_vgathermhq_pseudo |
7495 | 0 | 0U, // V6_vgathermhw_pseudo |
7496 | 0 | 0U, // V6_vgathermhwq_pseudo |
7497 | 0 | 0U, // V6_vgathermw_pseudo |
7498 | 0 | 0U, // V6_vgathermwq_pseudo |
7499 | 0 | 0U, // V6_vlsrh_alt |
7500 | 0 | 0U, // V6_vlsrhv_alt |
7501 | 0 | 0U, // V6_vlsrw_alt |
7502 | 0 | 0U, // V6_vlsrwv_alt |
7503 | 0 | 0U, // V6_vmaxb_alt |
7504 | 0 | 0U, // V6_vmaxh_alt |
7505 | 0 | 0U, // V6_vmaxub_alt |
7506 | 0 | 0U, // V6_vmaxuh_alt |
7507 | 0 | 0U, // V6_vmaxw_alt |
7508 | 0 | 0U, // V6_vminb_alt |
7509 | 0 | 0U, // V6_vminh_alt |
7510 | 0 | 0U, // V6_vminub_alt |
7511 | 0 | 0U, // V6_vminuh_alt |
7512 | 0 | 0U, // V6_vminw_alt |
7513 | 0 | 0U, // V6_vmpabus_acc_alt |
7514 | 0 | 0U, // V6_vmpabus_alt |
7515 | 0 | 0U, // V6_vmpabusv_alt |
7516 | 0 | 0U, // V6_vmpabuu_acc_alt |
7517 | 0 | 0U, // V6_vmpabuu_alt |
7518 | 0 | 0U, // V6_vmpabuuv_alt |
7519 | 0 | 0U, // V6_vmpahb_acc_alt |
7520 | 0 | 0U, // V6_vmpahb_alt |
7521 | 0 | 0U, // V6_vmpauhb_acc_alt |
7522 | 0 | 0U, // V6_vmpauhb_alt |
7523 | 0 | 0U, // V6_vmpybus_acc_alt |
7524 | 0 | 0U, // V6_vmpybus_alt |
7525 | 0 | 0U, // V6_vmpybusv_acc_alt |
7526 | 0 | 0U, // V6_vmpybusv_alt |
7527 | 0 | 0U, // V6_vmpybv_acc_alt |
7528 | 0 | 0U, // V6_vmpybv_alt |
7529 | 0 | 0U, // V6_vmpyewuh_alt |
7530 | 0 | 0U, // V6_vmpyh_acc_alt |
7531 | 0 | 0U, // V6_vmpyh_alt |
7532 | 0 | 0U, // V6_vmpyhsat_acc_alt |
7533 | 0 | 0U, // V6_vmpyhsrs_alt |
7534 | 0 | 0U, // V6_vmpyhss_alt |
7535 | 0 | 0U, // V6_vmpyhus_acc_alt |
7536 | 0 | 0U, // V6_vmpyhus_alt |
7537 | 0 | 0U, // V6_vmpyhv_acc_alt |
7538 | 0 | 0U, // V6_vmpyhv_alt |
7539 | 0 | 0U, // V6_vmpyhvsrs_alt |
7540 | 0 | 0U, // V6_vmpyiewh_acc_alt |
7541 | 0 | 0U, // V6_vmpyiewuh_acc_alt |
7542 | 0 | 0U, // V6_vmpyiewuh_alt |
7543 | 0 | 0U, // V6_vmpyih_acc_alt |
7544 | 0 | 0U, // V6_vmpyih_alt |
7545 | 0 | 0U, // V6_vmpyihb_acc_alt |
7546 | 0 | 0U, // V6_vmpyihb_alt |
7547 | 0 | 0U, // V6_vmpyiowh_alt |
7548 | 0 | 0U, // V6_vmpyiwb_acc_alt |
7549 | 0 | 0U, // V6_vmpyiwb_alt |
7550 | 0 | 0U, // V6_vmpyiwh_acc_alt |
7551 | 0 | 0U, // V6_vmpyiwh_alt |
7552 | 0 | 0U, // V6_vmpyiwub_acc_alt |
7553 | 0 | 0U, // V6_vmpyiwub_alt |
7554 | 0 | 0U, // V6_vmpyowh_alt |
7555 | 0 | 0U, // V6_vmpyowh_rnd_alt |
7556 | 0 | 0U, // V6_vmpyowh_rnd_sacc_alt |
7557 | 0 | 0U, // V6_vmpyowh_sacc_alt |
7558 | 0 | 0U, // V6_vmpyub_acc_alt |
7559 | 0 | 0U, // V6_vmpyub_alt |
7560 | 0 | 0U, // V6_vmpyubv_acc_alt |
7561 | 0 | 0U, // V6_vmpyubv_alt |
7562 | 0 | 0U, // V6_vmpyuh_acc_alt |
7563 | 0 | 0U, // V6_vmpyuh_alt |
7564 | 0 | 0U, // V6_vmpyuhv_acc_alt |
7565 | 0 | 0U, // V6_vmpyuhv_alt |
7566 | 0 | 0U, // V6_vnavgb_alt |
7567 | 0 | 0U, // V6_vnavgh_alt |
7568 | 0 | 0U, // V6_vnavgub_alt |
7569 | 0 | 0U, // V6_vnavgw_alt |
7570 | 0 | 0U, // V6_vnormamth_alt |
7571 | 0 | 0U, // V6_vnormamtw_alt |
7572 | 0 | 0U, // V6_vpackeb_alt |
7573 | 0 | 0U, // V6_vpackeh_alt |
7574 | 0 | 0U, // V6_vpackhb_sat_alt |
7575 | 0 | 0U, // V6_vpackhub_sat_alt |
7576 | 0 | 0U, // V6_vpackob_alt |
7577 | 0 | 0U, // V6_vpackoh_alt |
7578 | 0 | 0U, // V6_vpackwh_sat_alt |
7579 | 0 | 0U, // V6_vpackwuh_sat_alt |
7580 | 0 | 0U, // V6_vpopcounth_alt |
7581 | 0 | 0U, // V6_vrmpybub_rtt_acc_alt |
7582 | 0 | 0U, // V6_vrmpybub_rtt_alt |
7583 | 0 | 0U, // V6_vrmpybus_acc_alt |
7584 | 0 | 0U, // V6_vrmpybus_alt |
7585 | 0 | 0U, // V6_vrmpybusi_acc_alt |
7586 | 0 | 0U, // V6_vrmpybusi_alt |
7587 | 0 | 0U, // V6_vrmpybusv_acc_alt |
7588 | 0 | 0U, // V6_vrmpybusv_alt |
7589 | 0 | 0U, // V6_vrmpybv_acc_alt |
7590 | 0 | 0U, // V6_vrmpybv_alt |
7591 | 0 | 0U, // V6_vrmpyub_acc_alt |
7592 | 0 | 0U, // V6_vrmpyub_alt |
7593 | 0 | 0U, // V6_vrmpyub_rtt_acc_alt |
7594 | 0 | 0U, // V6_vrmpyub_rtt_alt |
7595 | 0 | 0U, // V6_vrmpyubi_acc_alt |
7596 | 0 | 0U, // V6_vrmpyubi_alt |
7597 | 0 | 0U, // V6_vrmpyubv_acc_alt |
7598 | 0 | 0U, // V6_vrmpyubv_alt |
7599 | 0 | 0U, // V6_vrotr_alt |
7600 | 0 | 0U, // V6_vroundhb_alt |
7601 | 0 | 0U, // V6_vroundhub_alt |
7602 | 0 | 0U, // V6_vrounduhub_alt |
7603 | 0 | 0U, // V6_vrounduwuh_alt |
7604 | 0 | 0U, // V6_vroundwh_alt |
7605 | 0 | 0U, // V6_vroundwuh_alt |
7606 | 0 | 0U, // V6_vrsadubi_acc_alt |
7607 | 0 | 0U, // V6_vrsadubi_alt |
7608 | 0 | 0U, // V6_vsathub_alt |
7609 | 0 | 0U, // V6_vsatuwuh_alt |
7610 | 0 | 0U, // V6_vsatwh_alt |
7611 | 0 | 0U, // V6_vsb_alt |
7612 | 0 | 0U, // V6_vscattermh_add_alt |
7613 | 0 | 0U, // V6_vscattermh_alt |
7614 | 0 | 0U, // V6_vscattermhq_alt |
7615 | 0 | 0U, // V6_vscattermw_add_alt |
7616 | 0 | 0U, // V6_vscattermw_alt |
7617 | 0 | 4U, // V6_vscattermwh_add_alt |
7618 | 0 | 4U, // V6_vscattermwh_alt |
7619 | 0 | 0U, // V6_vscattermwhq_alt |
7620 | 0 | 0U, // V6_vscattermwq_alt |
7621 | 0 | 0U, // V6_vsh_alt |
7622 | 0 | 0U, // V6_vshufeh_alt |
7623 | 0 | 0U, // V6_vshuffb_alt |
7624 | 0 | 0U, // V6_vshuffeb_alt |
7625 | 0 | 0U, // V6_vshuffh_alt |
7626 | 0 | 0U, // V6_vshuffob_alt |
7627 | 0 | 0U, // V6_vshufoeb_alt |
7628 | 0 | 0U, // V6_vshufoeh_alt |
7629 | 0 | 0U, // V6_vshufoh_alt |
7630 | 0 | 0U, // V6_vsubb_alt |
7631 | 0 | 0U, // V6_vsubb_dv_alt |
7632 | 0 | 0U, // V6_vsubbnq_alt |
7633 | 0 | 0U, // V6_vsubbq_alt |
7634 | 0 | 0U, // V6_vsubbsat_alt |
7635 | 0 | 0U, // V6_vsubbsat_dv_alt |
7636 | 0 | 0U, // V6_vsubh_alt |
7637 | 0 | 0U, // V6_vsubh_dv_alt |
7638 | 0 | 0U, // V6_vsubhnq_alt |
7639 | 0 | 0U, // V6_vsubhq_alt |
7640 | 0 | 0U, // V6_vsubhsat_alt |
7641 | 0 | 0U, // V6_vsubhsat_dv_alt |
7642 | 0 | 0U, // V6_vsubhw_alt |
7643 | 0 | 0U, // V6_vsububh_alt |
7644 | 0 | 0U, // V6_vsububsat_alt |
7645 | 0 | 0U, // V6_vsububsat_dv_alt |
7646 | 0 | 0U, // V6_vsubuhsat_alt |
7647 | 0 | 0U, // V6_vsubuhsat_dv_alt |
7648 | 0 | 0U, // V6_vsubuhw_alt |
7649 | 0 | 0U, // V6_vsubuwsat_alt |
7650 | 0 | 0U, // V6_vsubuwsat_dv_alt |
7651 | 0 | 0U, // V6_vsubw_alt |
7652 | 0 | 0U, // V6_vsubw_dv_alt |
7653 | 0 | 0U, // V6_vsubwnq_alt |
7654 | 0 | 0U, // V6_vsubwq_alt |
7655 | 0 | 0U, // V6_vsubwsat_alt |
7656 | 0 | 0U, // V6_vsubwsat_dv_alt |
7657 | 0 | 0U, // V6_vtmpyb_acc_alt |
7658 | 0 | 0U, // V6_vtmpyb_alt |
7659 | 0 | 0U, // V6_vtmpybus_acc_alt |
7660 | 0 | 0U, // V6_vtmpybus_alt |
7661 | 0 | 0U, // V6_vtmpyhb_acc_alt |
7662 | 0 | 0U, // V6_vtmpyhb_alt |
7663 | 0 | 0U, // V6_vtran2x2_map |
7664 | 0 | 0U, // V6_vunpackb_alt |
7665 | 0 | 0U, // V6_vunpackh_alt |
7666 | 0 | 0U, // V6_vunpackob_alt |
7667 | 0 | 0U, // V6_vunpackoh_alt |
7668 | 0 | 0U, // V6_vunpackub_alt |
7669 | 0 | 0U, // V6_vunpackuh_alt |
7670 | 0 | 0U, // V6_vzb_alt |
7671 | 0 | 0U, // V6_vzh_alt |
7672 | 0 | 0U, // V6_zld0 |
7673 | 0 | 0U, // V6_zldp0 |
7674 | 0 | 0U, // Y2_crswap_old |
7675 | 0 | 0U, // Y2_dcfetch |
7676 | 0 | 0U, // Y2_k1lock_map |
7677 | 0 | 0U, // Y2_k1unlock_map |
7678 | 0 | 0U, // dup_A2_add |
7679 | 0 | 0U, // dup_A2_addi |
7680 | 0 | 0U, // dup_A2_andir |
7681 | 0 | 0U, // dup_A2_combineii |
7682 | 0 | 0U, // dup_A2_sxtb |
7683 | 0 | 0U, // dup_A2_sxth |
7684 | 0 | 0U, // dup_A2_tfr |
7685 | 0 | 0U, // dup_A2_tfrsi |
7686 | 0 | 0U, // dup_A2_zxtb |
7687 | 0 | 0U, // dup_A2_zxth |
7688 | 0 | 0U, // dup_A4_combineii |
7689 | 0 | 0U, // dup_A4_combineir |
7690 | 0 | 0U, // dup_A4_combineri |
7691 | 0 | 0U, // dup_C2_cmoveif |
7692 | 0 | 0U, // dup_C2_cmoveit |
7693 | 0 | 0U, // dup_C2_cmovenewif |
7694 | 0 | 0U, // dup_C2_cmovenewit |
7695 | 0 | 0U, // dup_C2_cmpeqi |
7696 | 0 | 0U, // dup_L2_deallocframe |
7697 | 0 | 0U, // dup_L2_loadrb_io |
7698 | 0 | 0U, // dup_L2_loadrd_io |
7699 | 0 | 0U, // dup_L2_loadrh_io |
7700 | 0 | 0U, // dup_L2_loadri_io |
7701 | 0 | 0U, // dup_L2_loadrub_io |
7702 | 0 | 0U, // dup_L2_loadruh_io |
7703 | 0 | 0U, // dup_S2_allocframe |
7704 | 0 | 0U, // dup_S2_storerb_io |
7705 | 0 | 0U, // dup_S2_storerd_io |
7706 | 0 | 0U, // dup_S2_storerh_io |
7707 | 0 | 0U, // dup_S2_storeri_io |
7708 | 0 | 0U, // dup_S4_storeirb_io |
7709 | 0 | 0U, // dup_S4_storeiri_io |
7710 | 0 | 0U, // A2_abs |
7711 | 0 | 0U, // A2_absp |
7712 | 0 | 0U, // A2_abssat |
7713 | 0 | 0U, // A2_add |
7714 | 0 | 0U, // A2_addh_h16_hh |
7715 | 0 | 0U, // A2_addh_h16_hl |
7716 | 0 | 0U, // A2_addh_h16_lh |
7717 | 0 | 0U, // A2_addh_h16_ll |
7718 | 0 | 0U, // A2_addh_h16_sat_hh |
7719 | 0 | 0U, // A2_addh_h16_sat_hl |
7720 | 0 | 0U, // A2_addh_h16_sat_lh |
7721 | 0 | 0U, // A2_addh_h16_sat_ll |
7722 | 0 | 0U, // A2_addh_l16_hl |
7723 | 0 | 0U, // A2_addh_l16_ll |
7724 | 0 | 0U, // A2_addh_l16_sat_hl |
7725 | 0 | 0U, // A2_addh_l16_sat_ll |
7726 | 0 | 0U, // A2_addi |
7727 | 0 | 0U, // A2_addp |
7728 | 0 | 0U, // A2_addpsat |
7729 | 0 | 0U, // A2_addsat |
7730 | 0 | 0U, // A2_addsph |
7731 | 0 | 0U, // A2_addspl |
7732 | 0 | 0U, // A2_and |
7733 | 0 | 0U, // A2_andir |
7734 | 0 | 0U, // A2_andp |
7735 | 0 | 0U, // A2_aslh |
7736 | 0 | 0U, // A2_asrh |
7737 | 0 | 0U, // A2_combine_hh |
7738 | 0 | 0U, // A2_combine_hl |
7739 | 0 | 0U, // A2_combine_lh |
7740 | 0 | 0U, // A2_combine_ll |
7741 | 0 | 0U, // A2_combineii |
7742 | 0 | 0U, // A2_combinew |
7743 | 0 | 0U, // A2_max |
7744 | 0 | 0U, // A2_maxp |
7745 | 0 | 0U, // A2_maxu |
7746 | 0 | 0U, // A2_maxup |
7747 | 0 | 0U, // A2_min |
7748 | 0 | 0U, // A2_minp |
7749 | 0 | 0U, // A2_minu |
7750 | 0 | 0U, // A2_minup |
7751 | 0 | 0U, // A2_negp |
7752 | 0 | 0U, // A2_negsat |
7753 | 0 | 0U, // A2_nop |
7754 | 0 | 0U, // A2_notp |
7755 | 0 | 0U, // A2_or |
7756 | 0 | 0U, // A2_orir |
7757 | 0 | 0U, // A2_orp |
7758 | 0 | 0U, // A2_paddf |
7759 | 0 | 0U, // A2_paddfnew |
7760 | 0 | 0U, // A2_paddif |
7761 | 0 | 0U, // A2_paddifnew |
7762 | 0 | 0U, // A2_paddit |
7763 | 0 | 0U, // A2_padditnew |
7764 | 0 | 0U, // A2_paddt |
7765 | 0 | 0U, // A2_paddtnew |
7766 | 0 | 0U, // A2_pandf |
7767 | 0 | 0U, // A2_pandfnew |
7768 | 0 | 0U, // A2_pandt |
7769 | 0 | 0U, // A2_pandtnew |
7770 | 0 | 0U, // A2_porf |
7771 | 0 | 0U, // A2_porfnew |
7772 | 0 | 0U, // A2_port |
7773 | 0 | 0U, // A2_portnew |
7774 | 0 | 0U, // A2_psubf |
7775 | 0 | 0U, // A2_psubfnew |
7776 | 0 | 0U, // A2_psubt |
7777 | 0 | 0U, // A2_psubtnew |
7778 | 0 | 0U, // A2_pxorf |
7779 | 0 | 0U, // A2_pxorfnew |
7780 | 0 | 0U, // A2_pxort |
7781 | 0 | 0U, // A2_pxortnew |
7782 | 0 | 0U, // A2_roundsat |
7783 | 0 | 0U, // A2_sat |
7784 | 0 | 0U, // A2_satb |
7785 | 0 | 0U, // A2_sath |
7786 | 0 | 0U, // A2_satub |
7787 | 0 | 0U, // A2_satuh |
7788 | 0 | 0U, // A2_sub |
7789 | 0 | 0U, // A2_subh_h16_hh |
7790 | 0 | 0U, // A2_subh_h16_hl |
7791 | 0 | 0U, // A2_subh_h16_lh |
7792 | 0 | 0U, // A2_subh_h16_ll |
7793 | 0 | 0U, // A2_subh_h16_sat_hh |
7794 | 0 | 0U, // A2_subh_h16_sat_hl |
7795 | 0 | 0U, // A2_subh_h16_sat_lh |
7796 | 0 | 0U, // A2_subh_h16_sat_ll |
7797 | 0 | 0U, // A2_subh_l16_hl |
7798 | 0 | 0U, // A2_subh_l16_ll |
7799 | 0 | 0U, // A2_subh_l16_sat_hl |
7800 | 0 | 0U, // A2_subh_l16_sat_ll |
7801 | 0 | 0U, // A2_subp |
7802 | 0 | 0U, // A2_subri |
7803 | 0 | 0U, // A2_subsat |
7804 | 0 | 0U, // A2_svaddh |
7805 | 0 | 0U, // A2_svaddhs |
7806 | 0 | 0U, // A2_svadduhs |
7807 | 0 | 0U, // A2_svavgh |
7808 | 0 | 0U, // A2_svavghs |
7809 | 0 | 0U, // A2_svnavgh |
7810 | 0 | 0U, // A2_svsubh |
7811 | 0 | 0U, // A2_svsubhs |
7812 | 0 | 0U, // A2_svsubuhs |
7813 | 0 | 0U, // A2_swiz |
7814 | 0 | 0U, // A2_sxtb |
7815 | 0 | 0U, // A2_sxth |
7816 | 0 | 0U, // A2_sxtw |
7817 | 0 | 0U, // A2_tfr |
7818 | 0 | 0U, // A2_tfrcrr |
7819 | 0 | 0U, // A2_tfrih |
7820 | 0 | 0U, // A2_tfril |
7821 | 0 | 0U, // A2_tfrrcr |
7822 | 0 | 0U, // A2_tfrsi |
7823 | 0 | 0U, // A2_vabsh |
7824 | 0 | 0U, // A2_vabshsat |
7825 | 0 | 0U, // A2_vabsw |
7826 | 0 | 0U, // A2_vabswsat |
7827 | 0 | 0U, // A2_vaddh |
7828 | 0 | 0U, // A2_vaddhs |
7829 | 0 | 0U, // A2_vaddub |
7830 | 0 | 0U, // A2_vaddubs |
7831 | 0 | 0U, // A2_vadduhs |
7832 | 0 | 0U, // A2_vaddw |
7833 | 0 | 0U, // A2_vaddws |
7834 | 0 | 0U, // A2_vavgh |
7835 | 0 | 0U, // A2_vavghcr |
7836 | 0 | 0U, // A2_vavghr |
7837 | 0 | 0U, // A2_vavgub |
7838 | 0 | 0U, // A2_vavgubr |
7839 | 0 | 0U, // A2_vavguh |
7840 | 0 | 0U, // A2_vavguhr |
7841 | 0 | 0U, // A2_vavguw |
7842 | 0 | 0U, // A2_vavguwr |
7843 | 0 | 0U, // A2_vavgw |
7844 | 0 | 0U, // A2_vavgwcr |
7845 | 0 | 0U, // A2_vavgwr |
7846 | 0 | 0U, // A2_vcmpbeq |
7847 | 0 | 0U, // A2_vcmpbgtu |
7848 | 0 | 0U, // A2_vcmpheq |
7849 | 0 | 0U, // A2_vcmphgt |
7850 | 0 | 0U, // A2_vcmphgtu |
7851 | 0 | 0U, // A2_vcmpweq |
7852 | 0 | 0U, // A2_vcmpwgt |
7853 | 0 | 0U, // A2_vcmpwgtu |
7854 | 0 | 0U, // A2_vconj |
7855 | 0 | 0U, // A2_vmaxb |
7856 | 0 | 0U, // A2_vmaxh |
7857 | 0 | 0U, // A2_vmaxub |
7858 | 0 | 0U, // A2_vmaxuh |
7859 | 0 | 0U, // A2_vmaxuw |
7860 | 0 | 0U, // A2_vmaxw |
7861 | 0 | 0U, // A2_vminb |
7862 | 0 | 0U, // A2_vminh |
7863 | 0 | 0U, // A2_vminub |
7864 | 0 | 0U, // A2_vminuh |
7865 | 0 | 0U, // A2_vminuw |
7866 | 0 | 0U, // A2_vminw |
7867 | 0 | 0U, // A2_vnavgh |
7868 | 0 | 0U, // A2_vnavghcr |
7869 | 0 | 0U, // A2_vnavghr |
7870 | 0 | 0U, // A2_vnavgw |
7871 | 0 | 0U, // A2_vnavgwcr |
7872 | 0 | 0U, // A2_vnavgwr |
7873 | 0 | 0U, // A2_vraddub |
7874 | 0 | 0U, // A2_vraddub_acc |
7875 | 0 | 0U, // A2_vrsadub |
7876 | 0 | 0U, // A2_vrsadub_acc |
7877 | 0 | 0U, // A2_vsubh |
7878 | 0 | 0U, // A2_vsubhs |
7879 | 0 | 0U, // A2_vsubub |
7880 | 0 | 0U, // A2_vsububs |
7881 | 0 | 0U, // A2_vsubuhs |
7882 | 0 | 0U, // A2_vsubw |
7883 | 0 | 0U, // A2_vsubws |
7884 | 0 | 0U, // A2_xor |
7885 | 0 | 0U, // A2_xorp |
7886 | 0 | 0U, // A2_zxth |
7887 | 0 | 0U, // A4_addp_c |
7888 | 0 | 0U, // A4_andn |
7889 | 0 | 0U, // A4_andnp |
7890 | 0 | 0U, // A4_bitsplit |
7891 | 0 | 0U, // A4_bitspliti |
7892 | 0 | 0U, // A4_boundscheck_hi |
7893 | 0 | 0U, // A4_boundscheck_lo |
7894 | 0 | 0U, // A4_cmpbeq |
7895 | 0 | 0U, // A4_cmpbeqi |
7896 | 0 | 0U, // A4_cmpbgt |
7897 | 0 | 0U, // A4_cmpbgti |
7898 | 0 | 0U, // A4_cmpbgtu |
7899 | 0 | 0U, // A4_cmpbgtui |
7900 | 0 | 0U, // A4_cmpheq |
7901 | 0 | 0U, // A4_cmpheqi |
7902 | 0 | 0U, // A4_cmphgt |
7903 | 0 | 0U, // A4_cmphgti |
7904 | 0 | 0U, // A4_cmphgtu |
7905 | 0 | 0U, // A4_cmphgtui |
7906 | 0 | 0U, // A4_combineii |
7907 | 0 | 0U, // A4_combineir |
7908 | 0 | 0U, // A4_combineri |
7909 | 0 | 0U, // A4_cround_ri |
7910 | 0 | 0U, // A4_cround_rr |
7911 | 0 | 0U, // A4_ext |
7912 | 0 | 0U, // A4_modwrapu |
7913 | 0 | 0U, // A4_orn |
7914 | 0 | 0U, // A4_ornp |
7915 | 0 | 0U, // A4_paslhf |
7916 | 0 | 0U, // A4_paslhfnew |
7917 | 0 | 0U, // A4_paslht |
7918 | 0 | 0U, // A4_paslhtnew |
7919 | 0 | 0U, // A4_pasrhf |
7920 | 0 | 0U, // A4_pasrhfnew |
7921 | 0 | 0U, // A4_pasrht |
7922 | 0 | 0U, // A4_pasrhtnew |
7923 | 0 | 0U, // A4_psxtbf |
7924 | 0 | 0U, // A4_psxtbfnew |
7925 | 0 | 0U, // A4_psxtbt |
7926 | 0 | 0U, // A4_psxtbtnew |
7927 | 0 | 0U, // A4_psxthf |
7928 | 0 | 0U, // A4_psxthfnew |
7929 | 0 | 0U, // A4_psxtht |
7930 | 0 | 0U, // A4_psxthtnew |
7931 | 0 | 0U, // A4_pzxtbf |
7932 | 0 | 0U, // A4_pzxtbfnew |
7933 | 0 | 0U, // A4_pzxtbt |
7934 | 0 | 0U, // A4_pzxtbtnew |
7935 | 0 | 0U, // A4_pzxthf |
7936 | 0 | 0U, // A4_pzxthfnew |
7937 | 0 | 0U, // A4_pzxtht |
7938 | 0 | 0U, // A4_pzxthtnew |
7939 | 0 | 0U, // A4_rcmpeq |
7940 | 0 | 0U, // A4_rcmpeqi |
7941 | 0 | 0U, // A4_rcmpneq |
7942 | 0 | 0U, // A4_rcmpneqi |
7943 | 0 | 0U, // A4_round_ri |
7944 | 0 | 0U, // A4_round_ri_sat |
7945 | 0 | 0U, // A4_round_rr |
7946 | 0 | 0U, // A4_round_rr_sat |
7947 | 0 | 0U, // A4_subp_c |
7948 | 0 | 0U, // A4_tfrcpp |
7949 | 0 | 0U, // A4_tfrpcp |
7950 | 0 | 0U, // A4_tlbmatch |
7951 | 0 | 0U, // A4_vcmpbeq_any |
7952 | 0 | 0U, // A4_vcmpbeqi |
7953 | 0 | 0U, // A4_vcmpbgt |
7954 | 0 | 0U, // A4_vcmpbgti |
7955 | 0 | 0U, // A4_vcmpbgtui |
7956 | 0 | 0U, // A4_vcmpheqi |
7957 | 0 | 0U, // A4_vcmphgti |
7958 | 0 | 0U, // A4_vcmphgtui |
7959 | 0 | 0U, // A4_vcmpweqi |
7960 | 0 | 0U, // A4_vcmpwgti |
7961 | 0 | 0U, // A4_vcmpwgtui |
7962 | 0 | 0U, // A4_vrmaxh |
7963 | 0 | 0U, // A4_vrmaxuh |
7964 | 0 | 0U, // A4_vrmaxuw |
7965 | 0 | 0U, // A4_vrmaxw |
7966 | 0 | 0U, // A4_vrminh |
7967 | 0 | 0U, // A4_vrminuh |
7968 | 0 | 0U, // A4_vrminuw |
7969 | 0 | 0U, // A4_vrminw |
7970 | 0 | 0U, // A5_ACS |
7971 | 0 | 0U, // A5_vaddhubs |
7972 | 0 | 0U, // A6_vcmpbeq_notany |
7973 | 0 | 0U, // A6_vminub_RdP |
7974 | 0 | 0U, // A7_clip |
7975 | 0 | 0U, // A7_croundd_ri |
7976 | 0 | 0U, // A7_croundd_rr |
7977 | 0 | 0U, // A7_vclip |
7978 | 0 | 0U, // C2_all8 |
7979 | 0 | 0U, // C2_and |
7980 | 0 | 0U, // C2_andn |
7981 | 0 | 0U, // C2_any8 |
7982 | 0 | 0U, // C2_bitsclr |
7983 | 0 | 0U, // C2_bitsclri |
7984 | 0 | 0U, // C2_bitsset |
7985 | 0 | 0U, // C2_ccombinewf |
7986 | 0 | 0U, // C2_ccombinewnewf |
7987 | 0 | 0U, // C2_ccombinewnewt |
7988 | 0 | 0U, // C2_ccombinewt |
7989 | 0 | 0U, // C2_cmoveif |
7990 | 0 | 0U, // C2_cmoveit |
7991 | 0 | 0U, // C2_cmovenewif |
7992 | 0 | 0U, // C2_cmovenewit |
7993 | 0 | 0U, // C2_cmpeq |
7994 | 0 | 0U, // C2_cmpeqi |
7995 | 0 | 0U, // C2_cmpeqp |
7996 | 0 | 0U, // C2_cmpgt |
7997 | 0 | 0U, // C2_cmpgti |
7998 | 0 | 0U, // C2_cmpgtp |
7999 | 0 | 0U, // C2_cmpgtu |
8000 | 0 | 0U, // C2_cmpgtui |
8001 | 0 | 0U, // C2_cmpgtup |
8002 | 0 | 0U, // C2_mask |
8003 | 0 | 0U, // C2_mux |
8004 | 0 | 8U, // C2_muxii |
8005 | 0 | 8U, // C2_muxir |
8006 | 0 | 0U, // C2_muxri |
8007 | 0 | 0U, // C2_not |
8008 | 0 | 0U, // C2_or |
8009 | 0 | 0U, // C2_orn |
8010 | 0 | 0U, // C2_tfrpr |
8011 | 0 | 0U, // C2_tfrrp |
8012 | 0 | 0U, // C2_vitpack |
8013 | 0 | 0U, // C2_vmux |
8014 | 0 | 0U, // C2_xor |
8015 | 0 | 0U, // C4_addipc |
8016 | 0 | 0U, // C4_and_and |
8017 | 0 | 0U, // C4_and_andn |
8018 | 0 | 0U, // C4_and_or |
8019 | 0 | 0U, // C4_and_orn |
8020 | 0 | 0U, // C4_cmplte |
8021 | 0 | 0U, // C4_cmpltei |
8022 | 0 | 0U, // C4_cmplteu |
8023 | 0 | 0U, // C4_cmplteui |
8024 | 0 | 0U, // C4_cmpneq |
8025 | 0 | 0U, // C4_cmpneqi |
8026 | 0 | 0U, // C4_fastcorner9 |
8027 | 0 | 0U, // C4_fastcorner9_not |
8028 | 0 | 0U, // C4_nbitsclr |
8029 | 0 | 0U, // C4_nbitsclri |
8030 | 0 | 0U, // C4_nbitsset |
8031 | 0 | 0U, // C4_or_and |
8032 | 0 | 0U, // C4_or_andn |
8033 | 0 | 0U, // C4_or_or |
8034 | 0 | 0U, // C4_or_orn |
8035 | 0 | 0U, // CALLProfile |
8036 | 0 | 0U, // CONST32 |
8037 | 0 | 0U, // CONST64 |
8038 | 0 | 0U, // DuplexIClass0 |
8039 | 0 | 0U, // DuplexIClass1 |
8040 | 0 | 0U, // DuplexIClass2 |
8041 | 0 | 0U, // DuplexIClass3 |
8042 | 0 | 0U, // DuplexIClass4 |
8043 | 0 | 0U, // DuplexIClass5 |
8044 | 0 | 0U, // DuplexIClass6 |
8045 | 0 | 0U, // DuplexIClass7 |
8046 | 0 | 0U, // DuplexIClass8 |
8047 | 0 | 0U, // DuplexIClass9 |
8048 | 0 | 0U, // DuplexIClassA |
8049 | 0 | 0U, // DuplexIClassB |
8050 | 0 | 0U, // DuplexIClassC |
8051 | 0 | 0U, // DuplexIClassD |
8052 | 0 | 0U, // DuplexIClassE |
8053 | 0 | 0U, // DuplexIClassF |
8054 | 0 | 0U, // EH_RETURN_JMPR |
8055 | 0 | 0U, // F2_conv_d2df |
8056 | 0 | 0U, // F2_conv_d2sf |
8057 | 0 | 0U, // F2_conv_df2d |
8058 | 0 | 0U, // F2_conv_df2d_chop |
8059 | 0 | 0U, // F2_conv_df2sf |
8060 | 0 | 0U, // F2_conv_df2ud |
8061 | 0 | 0U, // F2_conv_df2ud_chop |
8062 | 0 | 0U, // F2_conv_df2uw |
8063 | 0 | 0U, // F2_conv_df2uw_chop |
8064 | 0 | 0U, // F2_conv_df2w |
8065 | 0 | 0U, // F2_conv_df2w_chop |
8066 | 0 | 0U, // F2_conv_sf2d |
8067 | 0 | 0U, // F2_conv_sf2d_chop |
8068 | 0 | 0U, // F2_conv_sf2df |
8069 | 0 | 0U, // F2_conv_sf2ud |
8070 | 0 | 0U, // F2_conv_sf2ud_chop |
8071 | 0 | 0U, // F2_conv_sf2uw |
8072 | 0 | 0U, // F2_conv_sf2uw_chop |
8073 | 0 | 0U, // F2_conv_sf2w |
8074 | 0 | 0U, // F2_conv_sf2w_chop |
8075 | 0 | 0U, // F2_conv_ud2df |
8076 | 0 | 0U, // F2_conv_ud2sf |
8077 | 0 | 0U, // F2_conv_uw2df |
8078 | 0 | 0U, // F2_conv_uw2sf |
8079 | 0 | 0U, // F2_conv_w2df |
8080 | 0 | 0U, // F2_conv_w2sf |
8081 | 0 | 0U, // F2_dfadd |
8082 | 0 | 0U, // F2_dfclass |
8083 | 0 | 0U, // F2_dfcmpeq |
8084 | 0 | 0U, // F2_dfcmpge |
8085 | 0 | 0U, // F2_dfcmpgt |
8086 | 0 | 0U, // F2_dfcmpuo |
8087 | 0 | 0U, // F2_dfimm_n |
8088 | 0 | 0U, // F2_dfimm_p |
8089 | 0 | 0U, // F2_dfmax |
8090 | 0 | 0U, // F2_dfmin |
8091 | 0 | 0U, // F2_dfmpyfix |
8092 | 0 | 0U, // F2_dfmpyhh |
8093 | 0 | 0U, // F2_dfmpylh |
8094 | 0 | 0U, // F2_dfmpyll |
8095 | 0 | 0U, // F2_dfsub |
8096 | 0 | 0U, // F2_sfadd |
8097 | 0 | 0U, // F2_sfclass |
8098 | 0 | 0U, // F2_sfcmpeq |
8099 | 0 | 0U, // F2_sfcmpge |
8100 | 0 | 0U, // F2_sfcmpgt |
8101 | 0 | 0U, // F2_sfcmpuo |
8102 | 0 | 0U, // F2_sffixupd |
8103 | 0 | 0U, // F2_sffixupn |
8104 | 0 | 0U, // F2_sffixupr |
8105 | 0 | 0U, // F2_sffma |
8106 | 0 | 0U, // F2_sffma_lib |
8107 | 0 | 0U, // F2_sffma_sc |
8108 | 0 | 0U, // F2_sffms |
8109 | 0 | 0U, // F2_sffms_lib |
8110 | 0 | 0U, // F2_sfimm_n |
8111 | 0 | 0U, // F2_sfimm_p |
8112 | 0 | 0U, // F2_sfinvsqrta |
8113 | 0 | 0U, // F2_sfmax |
8114 | 0 | 0U, // F2_sfmin |
8115 | 0 | 0U, // F2_sfmpy |
8116 | 0 | 0U, // F2_sfrecipa |
8117 | 0 | 0U, // F2_sfsub |
8118 | 0 | 0U, // G4_tfrgcpp |
8119 | 0 | 0U, // G4_tfrgcrr |
8120 | 0 | 0U, // G4_tfrgpcp |
8121 | 0 | 0U, // G4_tfrgrcr |
8122 | 0 | 0U, // HI |
8123 | 0 | 0U, // J2_call |
8124 | 0 | 0U, // J2_callf |
8125 | 0 | 0U, // J2_callr |
8126 | 0 | 0U, // J2_callrf |
8127 | 0 | 0U, // J2_callrh |
8128 | 0 | 0U, // J2_callrt |
8129 | 0 | 0U, // J2_callt |
8130 | 0 | 0U, // J2_jump |
8131 | 0 | 0U, // J2_jumpf |
8132 | 0 | 0U, // J2_jumpfnew |
8133 | 0 | 0U, // J2_jumpfnewpt |
8134 | 0 | 0U, // J2_jumpfpt |
8135 | 0 | 0U, // J2_jumpr |
8136 | 0 | 0U, // J2_jumprf |
8137 | 0 | 0U, // J2_jumprfnew |
8138 | 0 | 0U, // J2_jumprfnewpt |
8139 | 0 | 0U, // J2_jumprfpt |
8140 | 0 | 0U, // J2_jumprgtez |
8141 | 0 | 0U, // J2_jumprgtezpt |
8142 | 0 | 0U, // J2_jumprh |
8143 | 0 | 0U, // J2_jumprltez |
8144 | 0 | 0U, // J2_jumprltezpt |
8145 | 0 | 0U, // J2_jumprnz |
8146 | 0 | 0U, // J2_jumprnzpt |
8147 | 0 | 0U, // J2_jumprt |
8148 | 0 | 0U, // J2_jumprtnew |
8149 | 0 | 0U, // J2_jumprtnewpt |
8150 | 0 | 0U, // J2_jumprtpt |
8151 | 0 | 0U, // J2_jumprz |
8152 | 0 | 0U, // J2_jumprzpt |
8153 | 0 | 0U, // J2_jumpt |
8154 | 0 | 0U, // J2_jumptnew |
8155 | 0 | 0U, // J2_jumptnewpt |
8156 | 0 | 0U, // J2_jumptpt |
8157 | 0 | 0U, // J2_loop0i |
8158 | 0 | 0U, // J2_loop0iext |
8159 | 0 | 0U, // J2_loop0r |
8160 | 0 | 0U, // J2_loop0rext |
8161 | 0 | 0U, // J2_loop1i |
8162 | 0 | 0U, // J2_loop1iext |
8163 | 0 | 0U, // J2_loop1r |
8164 | 0 | 0U, // J2_loop1rext |
8165 | 0 | 0U, // J2_pause |
8166 | 0 | 0U, // J2_ploop1si |
8167 | 0 | 0U, // J2_ploop1sr |
8168 | 0 | 0U, // J2_ploop2si |
8169 | 0 | 0U, // J2_ploop2sr |
8170 | 0 | 0U, // J2_ploop3si |
8171 | 0 | 0U, // J2_ploop3sr |
8172 | 0 | 0U, // J2_rte |
8173 | 0 | 0U, // J2_trap0 |
8174 | 0 | 0U, // J2_trap1 |
8175 | 0 | 0U, // J2_unpause |
8176 | 0 | 0U, // J4_cmpeq_f_jumpnv_nt |
8177 | 0 | 0U, // J4_cmpeq_f_jumpnv_t |
8178 | 0 | 0U, // J4_cmpeq_fp0_jump_nt |
8179 | 0 | 0U, // J4_cmpeq_fp0_jump_t |
8180 | 0 | 0U, // J4_cmpeq_fp1_jump_nt |
8181 | 0 | 0U, // J4_cmpeq_fp1_jump_t |
8182 | 0 | 0U, // J4_cmpeq_t_jumpnv_nt |
8183 | 0 | 0U, // J4_cmpeq_t_jumpnv_t |
8184 | 0 | 0U, // J4_cmpeq_tp0_jump_nt |
8185 | 0 | 0U, // J4_cmpeq_tp0_jump_t |
8186 | 0 | 0U, // J4_cmpeq_tp1_jump_nt |
8187 | 0 | 0U, // J4_cmpeq_tp1_jump_t |
8188 | 0 | 0U, // J4_cmpeqi_f_jumpnv_nt |
8189 | 0 | 0U, // J4_cmpeqi_f_jumpnv_t |
8190 | 0 | 0U, // J4_cmpeqi_fp0_jump_nt |
8191 | 0 | 0U, // J4_cmpeqi_fp0_jump_t |
8192 | 0 | 0U, // J4_cmpeqi_fp1_jump_nt |
8193 | 0 | 0U, // J4_cmpeqi_fp1_jump_t |
8194 | 0 | 0U, // J4_cmpeqi_t_jumpnv_nt |
8195 | 0 | 0U, // J4_cmpeqi_t_jumpnv_t |
8196 | 0 | 0U, // J4_cmpeqi_tp0_jump_nt |
8197 | 0 | 0U, // J4_cmpeqi_tp0_jump_t |
8198 | 0 | 0U, // J4_cmpeqi_tp1_jump_nt |
8199 | 0 | 0U, // J4_cmpeqi_tp1_jump_t |
8200 | 0 | 0U, // J4_cmpeqn1_f_jumpnv_nt |
8201 | 0 | 0U, // J4_cmpeqn1_f_jumpnv_t |
8202 | 0 | 0U, // J4_cmpeqn1_fp0_jump_nt |
8203 | 0 | 0U, // J4_cmpeqn1_fp0_jump_t |
8204 | 0 | 0U, // J4_cmpeqn1_fp1_jump_nt |
8205 | 0 | 0U, // J4_cmpeqn1_fp1_jump_t |
8206 | 0 | 0U, // J4_cmpeqn1_t_jumpnv_nt |
8207 | 0 | 0U, // J4_cmpeqn1_t_jumpnv_t |
8208 | 0 | 0U, // J4_cmpeqn1_tp0_jump_nt |
8209 | 0 | 0U, // J4_cmpeqn1_tp0_jump_t |
8210 | 0 | 0U, // J4_cmpeqn1_tp1_jump_nt |
8211 | 0 | 0U, // J4_cmpeqn1_tp1_jump_t |
8212 | 0 | 0U, // J4_cmpgt_f_jumpnv_nt |
8213 | 0 | 0U, // J4_cmpgt_f_jumpnv_t |
8214 | 0 | 0U, // J4_cmpgt_fp0_jump_nt |
8215 | 0 | 0U, // J4_cmpgt_fp0_jump_t |
8216 | 0 | 0U, // J4_cmpgt_fp1_jump_nt |
8217 | 0 | 0U, // J4_cmpgt_fp1_jump_t |
8218 | 0 | 0U, // J4_cmpgt_t_jumpnv_nt |
8219 | 0 | 0U, // J4_cmpgt_t_jumpnv_t |
8220 | 0 | 0U, // J4_cmpgt_tp0_jump_nt |
8221 | 0 | 0U, // J4_cmpgt_tp0_jump_t |
8222 | 0 | 0U, // J4_cmpgt_tp1_jump_nt |
8223 | 0 | 0U, // J4_cmpgt_tp1_jump_t |
8224 | 0 | 0U, // J4_cmpgti_f_jumpnv_nt |
8225 | 0 | 0U, // J4_cmpgti_f_jumpnv_t |
8226 | 0 | 0U, // J4_cmpgti_fp0_jump_nt |
8227 | 0 | 0U, // J4_cmpgti_fp0_jump_t |
8228 | 0 | 0U, // J4_cmpgti_fp1_jump_nt |
8229 | 0 | 0U, // J4_cmpgti_fp1_jump_t |
8230 | 0 | 0U, // J4_cmpgti_t_jumpnv_nt |
8231 | 0 | 0U, // J4_cmpgti_t_jumpnv_t |
8232 | 0 | 0U, // J4_cmpgti_tp0_jump_nt |
8233 | 0 | 0U, // J4_cmpgti_tp0_jump_t |
8234 | 0 | 0U, // J4_cmpgti_tp1_jump_nt |
8235 | 0 | 0U, // J4_cmpgti_tp1_jump_t |
8236 | 0 | 0U, // J4_cmpgtn1_f_jumpnv_nt |
8237 | 0 | 0U, // J4_cmpgtn1_f_jumpnv_t |
8238 | 0 | 0U, // J4_cmpgtn1_fp0_jump_nt |
8239 | 0 | 0U, // J4_cmpgtn1_fp0_jump_t |
8240 | 0 | 0U, // J4_cmpgtn1_fp1_jump_nt |
8241 | 0 | 0U, // J4_cmpgtn1_fp1_jump_t |
8242 | 0 | 0U, // J4_cmpgtn1_t_jumpnv_nt |
8243 | 0 | 0U, // J4_cmpgtn1_t_jumpnv_t |
8244 | 0 | 0U, // J4_cmpgtn1_tp0_jump_nt |
8245 | 0 | 0U, // J4_cmpgtn1_tp0_jump_t |
8246 | 0 | 0U, // J4_cmpgtn1_tp1_jump_nt |
8247 | 0 | 0U, // J4_cmpgtn1_tp1_jump_t |
8248 | 0 | 0U, // J4_cmpgtu_f_jumpnv_nt |
8249 | 0 | 0U, // J4_cmpgtu_f_jumpnv_t |
8250 | 0 | 0U, // J4_cmpgtu_fp0_jump_nt |
8251 | 0 | 0U, // J4_cmpgtu_fp0_jump_t |
8252 | 0 | 0U, // J4_cmpgtu_fp1_jump_nt |
8253 | 0 | 0U, // J4_cmpgtu_fp1_jump_t |
8254 | 0 | 0U, // J4_cmpgtu_t_jumpnv_nt |
8255 | 0 | 0U, // J4_cmpgtu_t_jumpnv_t |
8256 | 0 | 0U, // J4_cmpgtu_tp0_jump_nt |
8257 | 0 | 0U, // J4_cmpgtu_tp0_jump_t |
8258 | 0 | 0U, // J4_cmpgtu_tp1_jump_nt |
8259 | 0 | 0U, // J4_cmpgtu_tp1_jump_t |
8260 | 0 | 0U, // J4_cmpgtui_f_jumpnv_nt |
8261 | 0 | 0U, // J4_cmpgtui_f_jumpnv_t |
8262 | 0 | 0U, // J4_cmpgtui_fp0_jump_nt |
8263 | 0 | 0U, // J4_cmpgtui_fp0_jump_t |
8264 | 0 | 0U, // J4_cmpgtui_fp1_jump_nt |
8265 | 0 | 0U, // J4_cmpgtui_fp1_jump_t |
8266 | 0 | 0U, // J4_cmpgtui_t_jumpnv_nt |
8267 | 0 | 0U, // J4_cmpgtui_t_jumpnv_t |
8268 | 0 | 0U, // J4_cmpgtui_tp0_jump_nt |
8269 | 0 | 0U, // J4_cmpgtui_tp0_jump_t |
8270 | 0 | 0U, // J4_cmpgtui_tp1_jump_nt |
8271 | 0 | 0U, // J4_cmpgtui_tp1_jump_t |
8272 | 0 | 0U, // J4_cmplt_f_jumpnv_nt |
8273 | 0 | 0U, // J4_cmplt_f_jumpnv_t |
8274 | 0 | 0U, // J4_cmplt_t_jumpnv_nt |
8275 | 0 | 0U, // J4_cmplt_t_jumpnv_t |
8276 | 0 | 0U, // J4_cmpltu_f_jumpnv_nt |
8277 | 0 | 0U, // J4_cmpltu_f_jumpnv_t |
8278 | 0 | 0U, // J4_cmpltu_t_jumpnv_nt |
8279 | 0 | 0U, // J4_cmpltu_t_jumpnv_t |
8280 | 0 | 0U, // J4_hintjumpr |
8281 | 0 | 0U, // J4_jumpseti |
8282 | 0 | 0U, // J4_jumpsetr |
8283 | 0 | 0U, // J4_tstbit0_f_jumpnv_nt |
8284 | 0 | 0U, // J4_tstbit0_f_jumpnv_t |
8285 | 0 | 0U, // J4_tstbit0_fp0_jump_nt |
8286 | 0 | 0U, // J4_tstbit0_fp0_jump_t |
8287 | 0 | 0U, // J4_tstbit0_fp1_jump_nt |
8288 | 0 | 0U, // J4_tstbit0_fp1_jump_t |
8289 | 0 | 0U, // J4_tstbit0_t_jumpnv_nt |
8290 | 0 | 0U, // J4_tstbit0_t_jumpnv_t |
8291 | 0 | 0U, // J4_tstbit0_tp0_jump_nt |
8292 | 0 | 0U, // J4_tstbit0_tp0_jump_t |
8293 | 0 | 0U, // J4_tstbit0_tp1_jump_nt |
8294 | 0 | 0U, // J4_tstbit0_tp1_jump_t |
8295 | 0 | 0U, // L2_deallocframe |
8296 | 0 | 0U, // L2_loadalignb_io |
8297 | 0 | 0U, // L2_loadalignb_pbr |
8298 | 0 | 0U, // L2_loadalignb_pci |
8299 | 0 | 0U, // L2_loadalignb_pcr |
8300 | 0 | 0U, // L2_loadalignb_pi |
8301 | 0 | 0U, // L2_loadalignb_pr |
8302 | 0 | 0U, // L2_loadalignh_io |
8303 | 0 | 0U, // L2_loadalignh_pbr |
8304 | 0 | 0U, // L2_loadalignh_pci |
8305 | 0 | 0U, // L2_loadalignh_pcr |
8306 | 0 | 0U, // L2_loadalignh_pi |
8307 | 0 | 0U, // L2_loadalignh_pr |
8308 | 0 | 0U, // L2_loadbsw2_io |
8309 | 0 | 0U, // L2_loadbsw2_pbr |
8310 | 0 | 0U, // L2_loadbsw2_pci |
8311 | 0 | 0U, // L2_loadbsw2_pcr |
8312 | 0 | 0U, // L2_loadbsw2_pi |
8313 | 0 | 0U, // L2_loadbsw2_pr |
8314 | 0 | 0U, // L2_loadbsw4_io |
8315 | 0 | 0U, // L2_loadbsw4_pbr |
8316 | 0 | 0U, // L2_loadbsw4_pci |
8317 | 0 | 0U, // L2_loadbsw4_pcr |
8318 | 0 | 0U, // L2_loadbsw4_pi |
8319 | 0 | 0U, // L2_loadbsw4_pr |
8320 | 0 | 0U, // L2_loadbzw2_io |
8321 | 0 | 0U, // L2_loadbzw2_pbr |
8322 | 0 | 0U, // L2_loadbzw2_pci |
8323 | 0 | 0U, // L2_loadbzw2_pcr |
8324 | 0 | 0U, // L2_loadbzw2_pi |
8325 | 0 | 0U, // L2_loadbzw2_pr |
8326 | 0 | 0U, // L2_loadbzw4_io |
8327 | 0 | 0U, // L2_loadbzw4_pbr |
8328 | 0 | 0U, // L2_loadbzw4_pci |
8329 | 0 | 0U, // L2_loadbzw4_pcr |
8330 | 0 | 0U, // L2_loadbzw4_pi |
8331 | 0 | 0U, // L2_loadbzw4_pr |
8332 | 0 | 0U, // L2_loadrb_io |
8333 | 0 | 0U, // L2_loadrb_pbr |
8334 | 0 | 0U, // L2_loadrb_pci |
8335 | 0 | 0U, // L2_loadrb_pcr |
8336 | 0 | 0U, // L2_loadrb_pi |
8337 | 0 | 0U, // L2_loadrb_pr |
8338 | 0 | 0U, // L2_loadrbgp |
8339 | 0 | 0U, // L2_loadrd_io |
8340 | 0 | 0U, // L2_loadrd_pbr |
8341 | 0 | 0U, // L2_loadrd_pci |
8342 | 0 | 0U, // L2_loadrd_pcr |
8343 | 0 | 0U, // L2_loadrd_pi |
8344 | 0 | 0U, // L2_loadrd_pr |
8345 | 0 | 0U, // L2_loadrdgp |
8346 | 0 | 0U, // L2_loadrh_io |
8347 | 0 | 0U, // L2_loadrh_pbr |
8348 | 0 | 0U, // L2_loadrh_pci |
8349 | 0 | 0U, // L2_loadrh_pcr |
8350 | 0 | 0U, // L2_loadrh_pi |
8351 | 0 | 0U, // L2_loadrh_pr |
8352 | 0 | 0U, // L2_loadrhgp |
8353 | 0 | 0U, // L2_loadri_io |
8354 | 0 | 0U, // L2_loadri_pbr |
8355 | 0 | 0U, // L2_loadri_pci |
8356 | 0 | 0U, // L2_loadri_pcr |
8357 | 0 | 0U, // L2_loadri_pi |
8358 | 0 | 0U, // L2_loadri_pr |
8359 | 0 | 0U, // L2_loadrigp |
8360 | 0 | 0U, // L2_loadrub_io |
8361 | 0 | 0U, // L2_loadrub_pbr |
8362 | 0 | 0U, // L2_loadrub_pci |
8363 | 0 | 0U, // L2_loadrub_pcr |
8364 | 0 | 0U, // L2_loadrub_pi |
8365 | 0 | 0U, // L2_loadrub_pr |
8366 | 0 | 0U, // L2_loadrubgp |
8367 | 0 | 0U, // L2_loadruh_io |
8368 | 0 | 0U, // L2_loadruh_pbr |
8369 | 0 | 0U, // L2_loadruh_pci |
8370 | 0 | 0U, // L2_loadruh_pcr |
8371 | 0 | 0U, // L2_loadruh_pi |
8372 | 0 | 0U, // L2_loadruh_pr |
8373 | 0 | 0U, // L2_loadruhgp |
8374 | 0 | 0U, // L2_loadw_aq |
8375 | 0 | 0U, // L2_loadw_locked |
8376 | 0 | 0U, // L2_ploadrbf_io |
8377 | 0 | 0U, // L2_ploadrbf_pi |
8378 | 0 | 0U, // L2_ploadrbfnew_io |
8379 | 0 | 0U, // L2_ploadrbfnew_pi |
8380 | 0 | 0U, // L2_ploadrbt_io |
8381 | 0 | 0U, // L2_ploadrbt_pi |
8382 | 0 | 0U, // L2_ploadrbtnew_io |
8383 | 0 | 0U, // L2_ploadrbtnew_pi |
8384 | 0 | 0U, // L2_ploadrdf_io |
8385 | 0 | 0U, // L2_ploadrdf_pi |
8386 | 0 | 0U, // L2_ploadrdfnew_io |
8387 | 0 | 0U, // L2_ploadrdfnew_pi |
8388 | 0 | 0U, // L2_ploadrdt_io |
8389 | 0 | 0U, // L2_ploadrdt_pi |
8390 | 0 | 0U, // L2_ploadrdtnew_io |
8391 | 0 | 0U, // L2_ploadrdtnew_pi |
8392 | 0 | 0U, // L2_ploadrhf_io |
8393 | 0 | 0U, // L2_ploadrhf_pi |
8394 | 0 | 0U, // L2_ploadrhfnew_io |
8395 | 0 | 0U, // L2_ploadrhfnew_pi |
8396 | 0 | 0U, // L2_ploadrht_io |
8397 | 0 | 0U, // L2_ploadrht_pi |
8398 | 0 | 0U, // L2_ploadrhtnew_io |
8399 | 0 | 0U, // L2_ploadrhtnew_pi |
8400 | 0 | 0U, // L2_ploadrif_io |
8401 | 0 | 0U, // L2_ploadrif_pi |
8402 | 0 | 0U, // L2_ploadrifnew_io |
8403 | 0 | 0U, // L2_ploadrifnew_pi |
8404 | 0 | 0U, // L2_ploadrit_io |
8405 | 0 | 0U, // L2_ploadrit_pi |
8406 | 0 | 0U, // L2_ploadritnew_io |
8407 | 0 | 0U, // L2_ploadritnew_pi |
8408 | 0 | 0U, // L2_ploadrubf_io |
8409 | 0 | 0U, // L2_ploadrubf_pi |
8410 | 0 | 0U, // L2_ploadrubfnew_io |
8411 | 0 | 0U, // L2_ploadrubfnew_pi |
8412 | 0 | 0U, // L2_ploadrubt_io |
8413 | 0 | 0U, // L2_ploadrubt_pi |
8414 | 0 | 0U, // L2_ploadrubtnew_io |
8415 | 0 | 0U, // L2_ploadrubtnew_pi |
8416 | 0 | 0U, // L2_ploadruhf_io |
8417 | 0 | 0U, // L2_ploadruhf_pi |
8418 | 0 | 0U, // L2_ploadruhfnew_io |
8419 | 0 | 0U, // L2_ploadruhfnew_pi |
8420 | 0 | 0U, // L2_ploadruht_io |
8421 | 0 | 0U, // L2_ploadruht_pi |
8422 | 0 | 0U, // L2_ploadruhtnew_io |
8423 | 0 | 0U, // L2_ploadruhtnew_pi |
8424 | 0 | 0U, // L4_add_memopb_io |
8425 | 0 | 0U, // L4_add_memoph_io |
8426 | 0 | 0U, // L4_add_memopw_io |
8427 | 0 | 0U, // L4_and_memopb_io |
8428 | 0 | 0U, // L4_and_memoph_io |
8429 | 0 | 0U, // L4_and_memopw_io |
8430 | 0 | 0U, // L4_iadd_memopb_io |
8431 | 0 | 0U, // L4_iadd_memoph_io |
8432 | 0 | 0U, // L4_iadd_memopw_io |
8433 | 0 | 0U, // L4_iand_memopb_io |
8434 | 0 | 0U, // L4_iand_memoph_io |
8435 | 0 | 0U, // L4_iand_memopw_io |
8436 | 0 | 0U, // L4_ior_memopb_io |
8437 | 0 | 0U, // L4_ior_memoph_io |
8438 | 0 | 0U, // L4_ior_memopw_io |
8439 | 0 | 0U, // L4_isub_memopb_io |
8440 | 0 | 0U, // L4_isub_memoph_io |
8441 | 0 | 0U, // L4_isub_memopw_io |
8442 | 0 | 0U, // L4_loadalignb_ap |
8443 | 0 | 0U, // L4_loadalignb_ur |
8444 | 0 | 0U, // L4_loadalignh_ap |
8445 | 0 | 0U, // L4_loadalignh_ur |
8446 | 0 | 0U, // L4_loadbsw2_ap |
8447 | 0 | 0U, // L4_loadbsw2_ur |
8448 | 0 | 0U, // L4_loadbsw4_ap |
8449 | 0 | 0U, // L4_loadbsw4_ur |
8450 | 0 | 0U, // L4_loadbzw2_ap |
8451 | 0 | 0U, // L4_loadbzw2_ur |
8452 | 0 | 0U, // L4_loadbzw4_ap |
8453 | 0 | 0U, // L4_loadbzw4_ur |
8454 | 0 | 0U, // L4_loadd_aq |
8455 | 0 | 0U, // L4_loadd_locked |
8456 | 0 | 0U, // L4_loadrb_ap |
8457 | 0 | 0U, // L4_loadrb_rr |
8458 | 0 | 0U, // L4_loadrb_ur |
8459 | 0 | 0U, // L4_loadrd_ap |
8460 | 0 | 0U, // L4_loadrd_rr |
8461 | 0 | 0U, // L4_loadrd_ur |
8462 | 0 | 0U, // L4_loadrh_ap |
8463 | 0 | 0U, // L4_loadrh_rr |
8464 | 0 | 0U, // L4_loadrh_ur |
8465 | 0 | 0U, // L4_loadri_ap |
8466 | 0 | 0U, // L4_loadri_rr |
8467 | 0 | 0U, // L4_loadri_ur |
8468 | 0 | 0U, // L4_loadrub_ap |
8469 | 0 | 0U, // L4_loadrub_rr |
8470 | 0 | 0U, // L4_loadrub_ur |
8471 | 0 | 0U, // L4_loadruh_ap |
8472 | 0 | 0U, // L4_loadruh_rr |
8473 | 0 | 0U, // L4_loadruh_ur |
8474 | 0 | 0U, // L4_loadw_phys |
8475 | 0 | 0U, // L4_or_memopb_io |
8476 | 0 | 0U, // L4_or_memoph_io |
8477 | 0 | 0U, // L4_or_memopw_io |
8478 | 0 | 0U, // L4_ploadrbf_abs |
8479 | 0 | 0U, // L4_ploadrbf_rr |
8480 | 0 | 0U, // L4_ploadrbfnew_abs |
8481 | 0 | 0U, // L4_ploadrbfnew_rr |
8482 | 0 | 0U, // L4_ploadrbt_abs |
8483 | 0 | 0U, // L4_ploadrbt_rr |
8484 | 0 | 0U, // L4_ploadrbtnew_abs |
8485 | 0 | 0U, // L4_ploadrbtnew_rr |
8486 | 0 | 0U, // L4_ploadrdf_abs |
8487 | 0 | 0U, // L4_ploadrdf_rr |
8488 | 0 | 0U, // L4_ploadrdfnew_abs |
8489 | 0 | 0U, // L4_ploadrdfnew_rr |
8490 | 0 | 0U, // L4_ploadrdt_abs |
8491 | 0 | 0U, // L4_ploadrdt_rr |
8492 | 0 | 0U, // L4_ploadrdtnew_abs |
8493 | 0 | 0U, // L4_ploadrdtnew_rr |
8494 | 0 | 0U, // L4_ploadrhf_abs |
8495 | 0 | 0U, // L4_ploadrhf_rr |
8496 | 0 | 0U, // L4_ploadrhfnew_abs |
8497 | 0 | 0U, // L4_ploadrhfnew_rr |
8498 | 0 | 0U, // L4_ploadrht_abs |
8499 | 0 | 0U, // L4_ploadrht_rr |
8500 | 0 | 0U, // L4_ploadrhtnew_abs |
8501 | 0 | 0U, // L4_ploadrhtnew_rr |
8502 | 0 | 0U, // L4_ploadrif_abs |
8503 | 0 | 0U, // L4_ploadrif_rr |
8504 | 0 | 0U, // L4_ploadrifnew_abs |
8505 | 0 | 0U, // L4_ploadrifnew_rr |
8506 | 0 | 0U, // L4_ploadrit_abs |
8507 | 0 | 0U, // L4_ploadrit_rr |
8508 | 0 | 0U, // L4_ploadritnew_abs |
8509 | 0 | 0U, // L4_ploadritnew_rr |
8510 | 0 | 0U, // L4_ploadrubf_abs |
8511 | 0 | 0U, // L4_ploadrubf_rr |
8512 | 0 | 0U, // L4_ploadrubfnew_abs |
8513 | 0 | 0U, // L4_ploadrubfnew_rr |
8514 | 0 | 0U, // L4_ploadrubt_abs |
8515 | 0 | 0U, // L4_ploadrubt_rr |
8516 | 0 | 0U, // L4_ploadrubtnew_abs |
8517 | 0 | 0U, // L4_ploadrubtnew_rr |
8518 | 0 | 0U, // L4_ploadruhf_abs |
8519 | 0 | 0U, // L4_ploadruhf_rr |
8520 | 0 | 0U, // L4_ploadruhfnew_abs |
8521 | 0 | 0U, // L4_ploadruhfnew_rr |
8522 | 0 | 0U, // L4_ploadruht_abs |
8523 | 0 | 0U, // L4_ploadruht_rr |
8524 | 0 | 0U, // L4_ploadruhtnew_abs |
8525 | 0 | 0U, // L4_ploadruhtnew_rr |
8526 | 0 | 0U, // L4_return |
8527 | 0 | 0U, // L4_return_f |
8528 | 0 | 0U, // L4_return_fnew_pnt |
8529 | 0 | 0U, // L4_return_fnew_pt |
8530 | 0 | 0U, // L4_return_t |
8531 | 0 | 0U, // L4_return_tnew_pnt |
8532 | 0 | 0U, // L4_return_tnew_pt |
8533 | 0 | 0U, // L4_sub_memopb_io |
8534 | 0 | 0U, // L4_sub_memoph_io |
8535 | 0 | 0U, // L4_sub_memopw_io |
8536 | 0 | 0U, // L6_memcpy |
8537 | 0 | 0U, // LO |
8538 | 0 | 0U, // M2_acci |
8539 | 0 | 0U, // M2_accii |
8540 | 0 | 0U, // M2_cmaci_s0 |
8541 | 0 | 0U, // M2_cmacr_s0 |
8542 | 0 | 0U, // M2_cmacs_s0 |
8543 | 0 | 0U, // M2_cmacs_s1 |
8544 | 0 | 0U, // M2_cmacsc_s0 |
8545 | 0 | 0U, // M2_cmacsc_s1 |
8546 | 0 | 0U, // M2_cmpyi_s0 |
8547 | 0 | 0U, // M2_cmpyr_s0 |
8548 | 0 | 0U, // M2_cmpyrs_s0 |
8549 | 0 | 0U, // M2_cmpyrs_s1 |
8550 | 0 | 0U, // M2_cmpyrsc_s0 |
8551 | 0 | 0U, // M2_cmpyrsc_s1 |
8552 | 0 | 0U, // M2_cmpys_s0 |
8553 | 0 | 0U, // M2_cmpys_s1 |
8554 | 0 | 0U, // M2_cmpysc_s0 |
8555 | 0 | 0U, // M2_cmpysc_s1 |
8556 | 0 | 0U, // M2_cnacs_s0 |
8557 | 0 | 0U, // M2_cnacs_s1 |
8558 | 0 | 0U, // M2_cnacsc_s0 |
8559 | 0 | 0U, // M2_cnacsc_s1 |
8560 | 0 | 0U, // M2_dpmpyss_acc_s0 |
8561 | 0 | 0U, // M2_dpmpyss_nac_s0 |
8562 | 0 | 0U, // M2_dpmpyss_rnd_s0 |
8563 | 0 | 0U, // M2_dpmpyss_s0 |
8564 | 0 | 0U, // M2_dpmpyuu_acc_s0 |
8565 | 0 | 0U, // M2_dpmpyuu_nac_s0 |
8566 | 0 | 0U, // M2_dpmpyuu_s0 |
8567 | 0 | 0U, // M2_hmmpyh_rs1 |
8568 | 0 | 0U, // M2_hmmpyh_s1 |
8569 | 0 | 0U, // M2_hmmpyl_rs1 |
8570 | 0 | 0U, // M2_hmmpyl_s1 |
8571 | 0 | 0U, // M2_maci |
8572 | 0 | 0U, // M2_macsin |
8573 | 0 | 0U, // M2_macsip |
8574 | 0 | 0U, // M2_mmachs_rs0 |
8575 | 0 | 0U, // M2_mmachs_rs1 |
8576 | 0 | 0U, // M2_mmachs_s0 |
8577 | 0 | 0U, // M2_mmachs_s1 |
8578 | 0 | 0U, // M2_mmacls_rs0 |
8579 | 0 | 0U, // M2_mmacls_rs1 |
8580 | 0 | 0U, // M2_mmacls_s0 |
8581 | 0 | 0U, // M2_mmacls_s1 |
8582 | 0 | 0U, // M2_mmacuhs_rs0 |
8583 | 0 | 0U, // M2_mmacuhs_rs1 |
8584 | 0 | 0U, // M2_mmacuhs_s0 |
8585 | 0 | 0U, // M2_mmacuhs_s1 |
8586 | 0 | 0U, // M2_mmaculs_rs0 |
8587 | 0 | 0U, // M2_mmaculs_rs1 |
8588 | 0 | 0U, // M2_mmaculs_s0 |
8589 | 0 | 0U, // M2_mmaculs_s1 |
8590 | 0 | 0U, // M2_mmpyh_rs0 |
8591 | 0 | 0U, // M2_mmpyh_rs1 |
8592 | 0 | 0U, // M2_mmpyh_s0 |
8593 | 0 | 0U, // M2_mmpyh_s1 |
8594 | 0 | 0U, // M2_mmpyl_rs0 |
8595 | 0 | 0U, // M2_mmpyl_rs1 |
8596 | 0 | 0U, // M2_mmpyl_s0 |
8597 | 0 | 0U, // M2_mmpyl_s1 |
8598 | 0 | 0U, // M2_mmpyuh_rs0 |
8599 | 0 | 0U, // M2_mmpyuh_rs1 |
8600 | 0 | 0U, // M2_mmpyuh_s0 |
8601 | 0 | 0U, // M2_mmpyuh_s1 |
8602 | 0 | 0U, // M2_mmpyul_rs0 |
8603 | 0 | 0U, // M2_mmpyul_rs1 |
8604 | 0 | 0U, // M2_mmpyul_s0 |
8605 | 0 | 0U, // M2_mmpyul_s1 |
8606 | 0 | 0U, // M2_mnaci |
8607 | 0 | 0U, // M2_mpy_acc_hh_s0 |
8608 | 0 | 0U, // M2_mpy_acc_hh_s1 |
8609 | 0 | 0U, // M2_mpy_acc_hl_s0 |
8610 | 0 | 0U, // M2_mpy_acc_hl_s1 |
8611 | 0 | 0U, // M2_mpy_acc_lh_s0 |
8612 | 0 | 0U, // M2_mpy_acc_lh_s1 |
8613 | 0 | 0U, // M2_mpy_acc_ll_s0 |
8614 | 0 | 0U, // M2_mpy_acc_ll_s1 |
8615 | 0 | 0U, // M2_mpy_acc_sat_hh_s0 |
8616 | 0 | 0U, // M2_mpy_acc_sat_hh_s1 |
8617 | 0 | 0U, // M2_mpy_acc_sat_hl_s0 |
8618 | 0 | 0U, // M2_mpy_acc_sat_hl_s1 |
8619 | 0 | 0U, // M2_mpy_acc_sat_lh_s0 |
8620 | 0 | 0U, // M2_mpy_acc_sat_lh_s1 |
8621 | 0 | 0U, // M2_mpy_acc_sat_ll_s0 |
8622 | 0 | 0U, // M2_mpy_acc_sat_ll_s1 |
8623 | 0 | 0U, // M2_mpy_hh_s0 |
8624 | 0 | 0U, // M2_mpy_hh_s1 |
8625 | 0 | 0U, // M2_mpy_hl_s0 |
8626 | 0 | 0U, // M2_mpy_hl_s1 |
8627 | 0 | 0U, // M2_mpy_lh_s0 |
8628 | 0 | 0U, // M2_mpy_lh_s1 |
8629 | 0 | 0U, // M2_mpy_ll_s0 |
8630 | 0 | 0U, // M2_mpy_ll_s1 |
8631 | 0 | 0U, // M2_mpy_nac_hh_s0 |
8632 | 0 | 0U, // M2_mpy_nac_hh_s1 |
8633 | 0 | 0U, // M2_mpy_nac_hl_s0 |
8634 | 0 | 0U, // M2_mpy_nac_hl_s1 |
8635 | 0 | 0U, // M2_mpy_nac_lh_s0 |
8636 | 0 | 0U, // M2_mpy_nac_lh_s1 |
8637 | 0 | 0U, // M2_mpy_nac_ll_s0 |
8638 | 0 | 0U, // M2_mpy_nac_ll_s1 |
8639 | 0 | 0U, // M2_mpy_nac_sat_hh_s0 |
8640 | 0 | 0U, // M2_mpy_nac_sat_hh_s1 |
8641 | 0 | 0U, // M2_mpy_nac_sat_hl_s0 |
8642 | 0 | 0U, // M2_mpy_nac_sat_hl_s1 |
8643 | 0 | 0U, // M2_mpy_nac_sat_lh_s0 |
8644 | 0 | 0U, // M2_mpy_nac_sat_lh_s1 |
8645 | 0 | 0U, // M2_mpy_nac_sat_ll_s0 |
8646 | 0 | 0U, // M2_mpy_nac_sat_ll_s1 |
8647 | 0 | 0U, // M2_mpy_rnd_hh_s0 |
8648 | 0 | 0U, // M2_mpy_rnd_hh_s1 |
8649 | 0 | 0U, // M2_mpy_rnd_hl_s0 |
8650 | 0 | 0U, // M2_mpy_rnd_hl_s1 |
8651 | 0 | 0U, // M2_mpy_rnd_lh_s0 |
8652 | 0 | 0U, // M2_mpy_rnd_lh_s1 |
8653 | 0 | 0U, // M2_mpy_rnd_ll_s0 |
8654 | 0 | 0U, // M2_mpy_rnd_ll_s1 |
8655 | 0 | 0U, // M2_mpy_sat_hh_s0 |
8656 | 0 | 0U, // M2_mpy_sat_hh_s1 |
8657 | 0 | 0U, // M2_mpy_sat_hl_s0 |
8658 | 0 | 0U, // M2_mpy_sat_hl_s1 |
8659 | 0 | 0U, // M2_mpy_sat_lh_s0 |
8660 | 0 | 0U, // M2_mpy_sat_lh_s1 |
8661 | 0 | 0U, // M2_mpy_sat_ll_s0 |
8662 | 0 | 0U, // M2_mpy_sat_ll_s1 |
8663 | 0 | 0U, // M2_mpy_sat_rnd_hh_s0 |
8664 | 0 | 0U, // M2_mpy_sat_rnd_hh_s1 |
8665 | 0 | 0U, // M2_mpy_sat_rnd_hl_s0 |
8666 | 0 | 0U, // M2_mpy_sat_rnd_hl_s1 |
8667 | 0 | 0U, // M2_mpy_sat_rnd_lh_s0 |
8668 | 0 | 0U, // M2_mpy_sat_rnd_lh_s1 |
8669 | 0 | 0U, // M2_mpy_sat_rnd_ll_s0 |
8670 | 0 | 0U, // M2_mpy_sat_rnd_ll_s1 |
8671 | 0 | 0U, // M2_mpy_up |
8672 | 0 | 0U, // M2_mpy_up_s1 |
8673 | 0 | 0U, // M2_mpy_up_s1_sat |
8674 | 0 | 0U, // M2_mpyd_acc_hh_s0 |
8675 | 0 | 0U, // M2_mpyd_acc_hh_s1 |
8676 | 0 | 0U, // M2_mpyd_acc_hl_s0 |
8677 | 0 | 0U, // M2_mpyd_acc_hl_s1 |
8678 | 0 | 0U, // M2_mpyd_acc_lh_s0 |
8679 | 0 | 0U, // M2_mpyd_acc_lh_s1 |
8680 | 0 | 0U, // M2_mpyd_acc_ll_s0 |
8681 | 0 | 0U, // M2_mpyd_acc_ll_s1 |
8682 | 0 | 0U, // M2_mpyd_hh_s0 |
8683 | 0 | 0U, // M2_mpyd_hh_s1 |
8684 | 0 | 0U, // M2_mpyd_hl_s0 |
8685 | 0 | 0U, // M2_mpyd_hl_s1 |
8686 | 0 | 0U, // M2_mpyd_lh_s0 |
8687 | 0 | 0U, // M2_mpyd_lh_s1 |
8688 | 0 | 0U, // M2_mpyd_ll_s0 |
8689 | 0 | 0U, // M2_mpyd_ll_s1 |
8690 | 0 | 0U, // M2_mpyd_nac_hh_s0 |
8691 | 0 | 0U, // M2_mpyd_nac_hh_s1 |
8692 | 0 | 0U, // M2_mpyd_nac_hl_s0 |
8693 | 0 | 0U, // M2_mpyd_nac_hl_s1 |
8694 | 0 | 0U, // M2_mpyd_nac_lh_s0 |
8695 | 0 | 0U, // M2_mpyd_nac_lh_s1 |
8696 | 0 | 0U, // M2_mpyd_nac_ll_s0 |
8697 | 0 | 0U, // M2_mpyd_nac_ll_s1 |
8698 | 0 | 0U, // M2_mpyd_rnd_hh_s0 |
8699 | 0 | 0U, // M2_mpyd_rnd_hh_s1 |
8700 | 0 | 0U, // M2_mpyd_rnd_hl_s0 |
8701 | 0 | 0U, // M2_mpyd_rnd_hl_s1 |
8702 | 0 | 0U, // M2_mpyd_rnd_lh_s0 |
8703 | 0 | 0U, // M2_mpyd_rnd_lh_s1 |
8704 | 0 | 0U, // M2_mpyd_rnd_ll_s0 |
8705 | 0 | 0U, // M2_mpyd_rnd_ll_s1 |
8706 | 0 | 0U, // M2_mpyi |
8707 | 0 | 0U, // M2_mpysin |
8708 | 0 | 0U, // M2_mpysip |
8709 | 0 | 0U, // M2_mpysu_up |
8710 | 0 | 0U, // M2_mpyu_acc_hh_s0 |
8711 | 0 | 0U, // M2_mpyu_acc_hh_s1 |
8712 | 0 | 0U, // M2_mpyu_acc_hl_s0 |
8713 | 0 | 0U, // M2_mpyu_acc_hl_s1 |
8714 | 0 | 0U, // M2_mpyu_acc_lh_s0 |
8715 | 0 | 0U, // M2_mpyu_acc_lh_s1 |
8716 | 0 | 0U, // M2_mpyu_acc_ll_s0 |
8717 | 0 | 0U, // M2_mpyu_acc_ll_s1 |
8718 | 0 | 0U, // M2_mpyu_hh_s0 |
8719 | 0 | 0U, // M2_mpyu_hh_s1 |
8720 | 0 | 0U, // M2_mpyu_hl_s0 |
8721 | 0 | 0U, // M2_mpyu_hl_s1 |
8722 | 0 | 0U, // M2_mpyu_lh_s0 |
8723 | 0 | 0U, // M2_mpyu_lh_s1 |
8724 | 0 | 0U, // M2_mpyu_ll_s0 |
8725 | 0 | 0U, // M2_mpyu_ll_s1 |
8726 | 0 | 0U, // M2_mpyu_nac_hh_s0 |
8727 | 0 | 0U, // M2_mpyu_nac_hh_s1 |
8728 | 0 | 0U, // M2_mpyu_nac_hl_s0 |
8729 | 0 | 0U, // M2_mpyu_nac_hl_s1 |
8730 | 0 | 0U, // M2_mpyu_nac_lh_s0 |
8731 | 0 | 0U, // M2_mpyu_nac_lh_s1 |
8732 | 0 | 0U, // M2_mpyu_nac_ll_s0 |
8733 | 0 | 0U, // M2_mpyu_nac_ll_s1 |
8734 | 0 | 0U, // M2_mpyu_up |
8735 | 0 | 0U, // M2_mpyud_acc_hh_s0 |
8736 | 0 | 0U, // M2_mpyud_acc_hh_s1 |
8737 | 0 | 0U, // M2_mpyud_acc_hl_s0 |
8738 | 0 | 0U, // M2_mpyud_acc_hl_s1 |
8739 | 0 | 0U, // M2_mpyud_acc_lh_s0 |
8740 | 0 | 0U, // M2_mpyud_acc_lh_s1 |
8741 | 0 | 0U, // M2_mpyud_acc_ll_s0 |
8742 | 0 | 0U, // M2_mpyud_acc_ll_s1 |
8743 | 0 | 0U, // M2_mpyud_hh_s0 |
8744 | 0 | 0U, // M2_mpyud_hh_s1 |
8745 | 0 | 0U, // M2_mpyud_hl_s0 |
8746 | 0 | 0U, // M2_mpyud_hl_s1 |
8747 | 0 | 0U, // M2_mpyud_lh_s0 |
8748 | 0 | 0U, // M2_mpyud_lh_s1 |
8749 | 0 | 0U, // M2_mpyud_ll_s0 |
8750 | 0 | 0U, // M2_mpyud_ll_s1 |
8751 | 0 | 0U, // M2_mpyud_nac_hh_s0 |
8752 | 0 | 0U, // M2_mpyud_nac_hh_s1 |
8753 | 0 | 0U, // M2_mpyud_nac_hl_s0 |
8754 | 0 | 0U, // M2_mpyud_nac_hl_s1 |
8755 | 0 | 0U, // M2_mpyud_nac_lh_s0 |
8756 | 0 | 0U, // M2_mpyud_nac_lh_s1 |
8757 | 0 | 0U, // M2_mpyud_nac_ll_s0 |
8758 | 0 | 0U, // M2_mpyud_nac_ll_s1 |
8759 | 0 | 0U, // M2_nacci |
8760 | 0 | 0U, // M2_naccii |
8761 | 0 | 0U, // M2_subacc |
8762 | 0 | 0U, // M2_vabsdiffh |
8763 | 0 | 0U, // M2_vabsdiffw |
8764 | 0 | 0U, // M2_vcmac_s0_sat_i |
8765 | 0 | 0U, // M2_vcmac_s0_sat_r |
8766 | 0 | 0U, // M2_vcmpy_s0_sat_i |
8767 | 0 | 0U, // M2_vcmpy_s0_sat_r |
8768 | 0 | 0U, // M2_vcmpy_s1_sat_i |
8769 | 0 | 0U, // M2_vcmpy_s1_sat_r |
8770 | 0 | 0U, // M2_vdmacs_s0 |
8771 | 0 | 0U, // M2_vdmacs_s1 |
8772 | 0 | 0U, // M2_vdmpyrs_s0 |
8773 | 0 | 0U, // M2_vdmpyrs_s1 |
8774 | 0 | 0U, // M2_vdmpys_s0 |
8775 | 0 | 0U, // M2_vdmpys_s1 |
8776 | 0 | 0U, // M2_vmac2 |
8777 | 0 | 0U, // M2_vmac2es |
8778 | 0 | 0U, // M2_vmac2es_s0 |
8779 | 0 | 0U, // M2_vmac2es_s1 |
8780 | 0 | 0U, // M2_vmac2s_s0 |
8781 | 0 | 0U, // M2_vmac2s_s1 |
8782 | 0 | 0U, // M2_vmac2su_s0 |
8783 | 0 | 0U, // M2_vmac2su_s1 |
8784 | 0 | 0U, // M2_vmpy2es_s0 |
8785 | 0 | 0U, // M2_vmpy2es_s1 |
8786 | 0 | 0U, // M2_vmpy2s_s0 |
8787 | 0 | 0U, // M2_vmpy2s_s0pack |
8788 | 0 | 0U, // M2_vmpy2s_s1 |
8789 | 0 | 0U, // M2_vmpy2s_s1pack |
8790 | 0 | 0U, // M2_vmpy2su_s0 |
8791 | 0 | 0U, // M2_vmpy2su_s1 |
8792 | 0 | 0U, // M2_vraddh |
8793 | 0 | 0U, // M2_vradduh |
8794 | 0 | 0U, // M2_vrcmaci_s0 |
8795 | 0 | 0U, // M2_vrcmaci_s0c |
8796 | 0 | 0U, // M2_vrcmacr_s0 |
8797 | 0 | 0U, // M2_vrcmacr_s0c |
8798 | 0 | 0U, // M2_vrcmpyi_s0 |
8799 | 0 | 0U, // M2_vrcmpyi_s0c |
8800 | 0 | 0U, // M2_vrcmpyr_s0 |
8801 | 0 | 0U, // M2_vrcmpyr_s0c |
8802 | 0 | 0U, // M2_vrcmpys_acc_s1_h |
8803 | 0 | 0U, // M2_vrcmpys_acc_s1_l |
8804 | 0 | 0U, // M2_vrcmpys_s1_h |
8805 | 0 | 0U, // M2_vrcmpys_s1_l |
8806 | 0 | 0U, // M2_vrcmpys_s1rp_h |
8807 | 0 | 0U, // M2_vrcmpys_s1rp_l |
8808 | 0 | 0U, // M2_vrmac_s0 |
8809 | 0 | 0U, // M2_vrmpy_s0 |
8810 | 0 | 0U, // M2_xor_xacc |
8811 | 0 | 0U, // M4_and_and |
8812 | 0 | 0U, // M4_and_andn |
8813 | 0 | 0U, // M4_and_or |
8814 | 0 | 0U, // M4_and_xor |
8815 | 0 | 0U, // M4_cmpyi_wh |
8816 | 0 | 0U, // M4_cmpyi_whc |
8817 | 0 | 0U, // M4_cmpyr_wh |
8818 | 0 | 0U, // M4_cmpyr_whc |
8819 | 0 | 0U, // M4_mac_up_s1_sat |
8820 | 0 | 0U, // M4_mpyri_addi |
8821 | 0 | 12U, // M4_mpyri_addr |
8822 | 0 | 0U, // M4_mpyri_addr_u2 |
8823 | 0 | 0U, // M4_mpyrr_addi |
8824 | 0 | 0U, // M4_mpyrr_addr |
8825 | 0 | 0U, // M4_nac_up_s1_sat |
8826 | 0 | 0U, // M4_or_and |
8827 | 0 | 0U, // M4_or_andn |
8828 | 0 | 0U, // M4_or_or |
8829 | 0 | 0U, // M4_or_xor |
8830 | 0 | 0U, // M4_pmpyw |
8831 | 0 | 0U, // M4_pmpyw_acc |
8832 | 0 | 0U, // M4_vpmpyh |
8833 | 0 | 0U, // M4_vpmpyh_acc |
8834 | 0 | 0U, // M4_vrmpyeh_acc_s0 |
8835 | 0 | 0U, // M4_vrmpyeh_acc_s1 |
8836 | 0 | 0U, // M4_vrmpyeh_s0 |
8837 | 0 | 0U, // M4_vrmpyeh_s1 |
8838 | 0 | 0U, // M4_vrmpyoh_acc_s0 |
8839 | 0 | 0U, // M4_vrmpyoh_acc_s1 |
8840 | 0 | 0U, // M4_vrmpyoh_s0 |
8841 | 0 | 0U, // M4_vrmpyoh_s1 |
8842 | 0 | 0U, // M4_xor_and |
8843 | 0 | 0U, // M4_xor_andn |
8844 | 0 | 0U, // M4_xor_or |
8845 | 0 | 0U, // M4_xor_xacc |
8846 | 0 | 0U, // M5_vdmacbsu |
8847 | 0 | 0U, // M5_vdmpybsu |
8848 | 0 | 0U, // M5_vmacbsu |
8849 | 0 | 0U, // M5_vmacbuu |
8850 | 0 | 0U, // M5_vmpybsu |
8851 | 0 | 0U, // M5_vmpybuu |
8852 | 0 | 0U, // M5_vrmacbsu |
8853 | 0 | 0U, // M5_vrmacbuu |
8854 | 0 | 0U, // M5_vrmpybsu |
8855 | 0 | 0U, // M5_vrmpybuu |
8856 | 0 | 0U, // M6_vabsdiffb |
8857 | 0 | 0U, // M6_vabsdiffub |
8858 | 0 | 0U, // M7_dcmpyiw |
8859 | 0 | 0U, // M7_dcmpyiw_acc |
8860 | 0 | 0U, // M7_dcmpyiwc |
8861 | 0 | 0U, // M7_dcmpyiwc_acc |
8862 | 0 | 0U, // M7_dcmpyrw |
8863 | 0 | 0U, // M7_dcmpyrw_acc |
8864 | 0 | 0U, // M7_dcmpyrwc |
8865 | 0 | 0U, // M7_dcmpyrwc_acc |
8866 | 0 | 0U, // M7_wcmpyiw |
8867 | 0 | 0U, // M7_wcmpyiw_rnd |
8868 | 0 | 0U, // M7_wcmpyiwc |
8869 | 0 | 0U, // M7_wcmpyiwc_rnd |
8870 | 0 | 0U, // M7_wcmpyrw |
8871 | 0 | 0U, // M7_wcmpyrw_rnd |
8872 | 0 | 0U, // M7_wcmpyrwc |
8873 | 0 | 0U, // M7_wcmpyrwc_rnd |
8874 | 0 | 0U, // PS_call_stk |
8875 | 0 | 0U, // PS_callr_nr |
8876 | 0 | 0U, // PS_jmpret |
8877 | 0 | 0U, // PS_jmpretf |
8878 | 0 | 0U, // PS_jmpretfnew |
8879 | 0 | 0U, // PS_jmpretfnewpt |
8880 | 0 | 0U, // PS_jmprett |
8881 | 0 | 0U, // PS_jmprettnew |
8882 | 0 | 0U, // PS_jmprettnewpt |
8883 | 0 | 0U, // PS_loadrbabs |
8884 | 0 | 0U, // PS_loadrdabs |
8885 | 0 | 0U, // PS_loadrhabs |
8886 | 0 | 0U, // PS_loadriabs |
8887 | 0 | 0U, // PS_loadrubabs |
8888 | 0 | 0U, // PS_loadruhabs |
8889 | 0 | 0U, // PS_storerbabs |
8890 | 0 | 0U, // PS_storerbnewabs |
8891 | 0 | 0U, // PS_storerdabs |
8892 | 0 | 0U, // PS_storerfabs |
8893 | 0 | 0U, // PS_storerhabs |
8894 | 0 | 0U, // PS_storerhnewabs |
8895 | 0 | 0U, // PS_storeriabs |
8896 | 0 | 0U, // PS_storerinewabs |
8897 | 0 | 0U, // PS_trap1 |
8898 | 0 | 0U, // R6_release_at_vi |
8899 | 0 | 0U, // R6_release_st_vi |
8900 | 0 | 0U, // RESTORE_DEALLOC_BEFORE_TAILCALL_V4 |
8901 | 0 | 0U, // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT |
8902 | 0 | 0U, // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC |
8903 | 0 | 0U, // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC |
8904 | 0 | 0U, // RESTORE_DEALLOC_RET_JMP_V4 |
8905 | 0 | 0U, // RESTORE_DEALLOC_RET_JMP_V4_EXT |
8906 | 0 | 0U, // RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC |
8907 | 0 | 0U, // RESTORE_DEALLOC_RET_JMP_V4_PIC |
8908 | 0 | 0U, // S2_addasl_rrri |
8909 | 0 | 0U, // S2_allocframe |
8910 | 0 | 0U, // S2_asl_i_p |
8911 | 0 | 0U, // S2_asl_i_p_acc |
8912 | 0 | 0U, // S2_asl_i_p_and |
8913 | 0 | 0U, // S2_asl_i_p_nac |
8914 | 0 | 0U, // S2_asl_i_p_or |
8915 | 0 | 0U, // S2_asl_i_p_xacc |
8916 | 0 | 0U, // S2_asl_i_r |
8917 | 0 | 0U, // S2_asl_i_r_acc |
8918 | 0 | 0U, // S2_asl_i_r_and |
8919 | 0 | 0U, // S2_asl_i_r_nac |
8920 | 0 | 0U, // S2_asl_i_r_or |
8921 | 0 | 0U, // S2_asl_i_r_sat |
8922 | 0 | 0U, // S2_asl_i_r_xacc |
8923 | 0 | 0U, // S2_asl_i_vh |
8924 | 0 | 0U, // S2_asl_i_vw |
8925 | 0 | 0U, // S2_asl_r_p |
8926 | 0 | 0U, // S2_asl_r_p_acc |
8927 | 0 | 0U, // S2_asl_r_p_and |
8928 | 0 | 0U, // S2_asl_r_p_nac |
8929 | 0 | 0U, // S2_asl_r_p_or |
8930 | 0 | 0U, // S2_asl_r_p_xor |
8931 | 0 | 0U, // S2_asl_r_r |
8932 | 0 | 0U, // S2_asl_r_r_acc |
8933 | 0 | 0U, // S2_asl_r_r_and |
8934 | 0 | 0U, // S2_asl_r_r_nac |
8935 | 0 | 0U, // S2_asl_r_r_or |
8936 | 0 | 0U, // S2_asl_r_r_sat |
8937 | 0 | 0U, // S2_asl_r_vh |
8938 | 0 | 0U, // S2_asl_r_vw |
8939 | 0 | 0U, // S2_asr_i_p |
8940 | 0 | 0U, // S2_asr_i_p_acc |
8941 | 0 | 0U, // S2_asr_i_p_and |
8942 | 0 | 0U, // S2_asr_i_p_nac |
8943 | 0 | 0U, // S2_asr_i_p_or |
8944 | 0 | 0U, // S2_asr_i_p_rnd |
8945 | 0 | 0U, // S2_asr_i_r |
8946 | 0 | 0U, // S2_asr_i_r_acc |
8947 | 0 | 0U, // S2_asr_i_r_and |
8948 | 0 | 0U, // S2_asr_i_r_nac |
8949 | 0 | 0U, // S2_asr_i_r_or |
8950 | 0 | 0U, // S2_asr_i_r_rnd |
8951 | 0 | 0U, // S2_asr_i_svw_trun |
8952 | 0 | 0U, // S2_asr_i_vh |
8953 | 0 | 0U, // S2_asr_i_vw |
8954 | 0 | 0U, // S2_asr_r_p |
8955 | 0 | 0U, // S2_asr_r_p_acc |
8956 | 0 | 0U, // S2_asr_r_p_and |
8957 | 0 | 0U, // S2_asr_r_p_nac |
8958 | 0 | 0U, // S2_asr_r_p_or |
8959 | 0 | 0U, // S2_asr_r_p_xor |
8960 | 0 | 0U, // S2_asr_r_r |
8961 | 0 | 0U, // S2_asr_r_r_acc |
8962 | 0 | 0U, // S2_asr_r_r_and |
8963 | 0 | 0U, // S2_asr_r_r_nac |
8964 | 0 | 0U, // S2_asr_r_r_or |
8965 | 0 | 0U, // S2_asr_r_r_sat |
8966 | 0 | 0U, // S2_asr_r_svw_trun |
8967 | 0 | 0U, // S2_asr_r_vh |
8968 | 0 | 0U, // S2_asr_r_vw |
8969 | 0 | 0U, // S2_brev |
8970 | 0 | 0U, // S2_brevp |
8971 | 0 | 0U, // S2_cabacdecbin |
8972 | 0 | 0U, // S2_cl0 |
8973 | 0 | 0U, // S2_cl0p |
8974 | 0 | 0U, // S2_cl1 |
8975 | 0 | 0U, // S2_cl1p |
8976 | 0 | 0U, // S2_clb |
8977 | 0 | 0U, // S2_clbnorm |
8978 | 0 | 0U, // S2_clbp |
8979 | 0 | 0U, // S2_clrbit_i |
8980 | 0 | 0U, // S2_clrbit_r |
8981 | 0 | 0U, // S2_ct0 |
8982 | 0 | 0U, // S2_ct0p |
8983 | 0 | 0U, // S2_ct1 |
8984 | 0 | 0U, // S2_ct1p |
8985 | 0 | 0U, // S2_deinterleave |
8986 | 0 | 8U, // S2_extractu |
8987 | 0 | 0U, // S2_extractu_rp |
8988 | 0 | 8U, // S2_extractup |
8989 | 0 | 0U, // S2_extractup_rp |
8990 | 0 | 0U, // S2_insert |
8991 | 0 | 0U, // S2_insert_rp |
8992 | 0 | 0U, // S2_insertp |
8993 | 0 | 0U, // S2_insertp_rp |
8994 | 0 | 0U, // S2_interleave |
8995 | 0 | 0U, // S2_lfsp |
8996 | 0 | 0U, // S2_lsl_r_p |
8997 | 0 | 0U, // S2_lsl_r_p_acc |
8998 | 0 | 0U, // S2_lsl_r_p_and |
8999 | 0 | 0U, // S2_lsl_r_p_nac |
9000 | 0 | 0U, // S2_lsl_r_p_or |
9001 | 0 | 0U, // S2_lsl_r_p_xor |
9002 | 0 | 0U, // S2_lsl_r_r |
9003 | 0 | 0U, // S2_lsl_r_r_acc |
9004 | 0 | 0U, // S2_lsl_r_r_and |
9005 | 0 | 0U, // S2_lsl_r_r_nac |
9006 | 0 | 0U, // S2_lsl_r_r_or |
9007 | 0 | 0U, // S2_lsl_r_vh |
9008 | 0 | 0U, // S2_lsl_r_vw |
9009 | 0 | 0U, // S2_lsr_i_p |
9010 | 0 | 0U, // S2_lsr_i_p_acc |
9011 | 0 | 0U, // S2_lsr_i_p_and |
9012 | 0 | 0U, // S2_lsr_i_p_nac |
9013 | 0 | 0U, // S2_lsr_i_p_or |
9014 | 0 | 0U, // S2_lsr_i_p_xacc |
9015 | 0 | 0U, // S2_lsr_i_r |
9016 | 0 | 0U, // S2_lsr_i_r_acc |
9017 | 0 | 0U, // S2_lsr_i_r_and |
9018 | 0 | 0U, // S2_lsr_i_r_nac |
9019 | 0 | 0U, // S2_lsr_i_r_or |
9020 | 0 | 0U, // S2_lsr_i_r_xacc |
9021 | 0 | 0U, // S2_lsr_i_vh |
9022 | 0 | 0U, // S2_lsr_i_vw |
9023 | 0 | 0U, // S2_lsr_r_p |
9024 | 0 | 0U, // S2_lsr_r_p_acc |
9025 | 0 | 0U, // S2_lsr_r_p_and |
9026 | 0 | 0U, // S2_lsr_r_p_nac |
9027 | 0 | 0U, // S2_lsr_r_p_or |
9028 | 0 | 0U, // S2_lsr_r_p_xor |
9029 | 0 | 0U, // S2_lsr_r_r |
9030 | 0 | 0U, // S2_lsr_r_r_acc |
9031 | 0 | 0U, // S2_lsr_r_r_and |
9032 | 0 | 0U, // S2_lsr_r_r_nac |
9033 | 0 | 0U, // S2_lsr_r_r_or |
9034 | 0 | 0U, // S2_lsr_r_vh |
9035 | 0 | 0U, // S2_lsr_r_vw |
9036 | 0 | 0U, // S2_mask |
9037 | 0 | 0U, // S2_packhl |
9038 | 0 | 0U, // S2_parityp |
9039 | 0 | 16U, // S2_pstorerbf_io |
9040 | 0 | 20U, // S2_pstorerbf_pi |
9041 | 0 | 20U, // S2_pstorerbfnew_pi |
9042 | 0 | 48U, // S2_pstorerbnewf_io |
9043 | 0 | 52U, // S2_pstorerbnewf_pi |
9044 | 0 | 52U, // S2_pstorerbnewfnew_pi |
9045 | 0 | 48U, // S2_pstorerbnewt_io |
9046 | 0 | 52U, // S2_pstorerbnewt_pi |
9047 | 0 | 52U, // S2_pstorerbnewtnew_pi |
9048 | 0 | 16U, // S2_pstorerbt_io |
9049 | 0 | 20U, // S2_pstorerbt_pi |
9050 | 0 | 20U, // S2_pstorerbtnew_pi |
9051 | 0 | 16U, // S2_pstorerdf_io |
9052 | 0 | 20U, // S2_pstorerdf_pi |
9053 | 0 | 20U, // S2_pstorerdfnew_pi |
9054 | 0 | 16U, // S2_pstorerdt_io |
9055 | 0 | 20U, // S2_pstorerdt_pi |
9056 | 0 | 20U, // S2_pstorerdtnew_pi |
9057 | 0 | 80U, // S2_pstorerff_io |
9058 | 0 | 84U, // S2_pstorerff_pi |
9059 | 0 | 84U, // S2_pstorerffnew_pi |
9060 | 0 | 80U, // S2_pstorerft_io |
9061 | 0 | 84U, // S2_pstorerft_pi |
9062 | 0 | 84U, // S2_pstorerftnew_pi |
9063 | 0 | 16U, // S2_pstorerhf_io |
9064 | 0 | 20U, // S2_pstorerhf_pi |
9065 | 0 | 20U, // S2_pstorerhfnew_pi |
9066 | 0 | 48U, // S2_pstorerhnewf_io |
9067 | 0 | 52U, // S2_pstorerhnewf_pi |
9068 | 0 | 52U, // S2_pstorerhnewfnew_pi |
9069 | 0 | 48U, // S2_pstorerhnewt_io |
9070 | 0 | 52U, // S2_pstorerhnewt_pi |
9071 | 0 | 52U, // S2_pstorerhnewtnew_pi |
9072 | 0 | 16U, // S2_pstorerht_io |
9073 | 0 | 20U, // S2_pstorerht_pi |
9074 | 0 | 20U, // S2_pstorerhtnew_pi |
9075 | 0 | 16U, // S2_pstorerif_io |
9076 | 0 | 20U, // S2_pstorerif_pi |
9077 | 0 | 20U, // S2_pstorerifnew_pi |
9078 | 0 | 48U, // S2_pstorerinewf_io |
9079 | 0 | 52U, // S2_pstorerinewf_pi |
9080 | 0 | 52U, // S2_pstorerinewfnew_pi |
9081 | 0 | 48U, // S2_pstorerinewt_io |
9082 | 0 | 52U, // S2_pstorerinewt_pi |
9083 | 0 | 52U, // S2_pstorerinewtnew_pi |
9084 | 0 | 16U, // S2_pstorerit_io |
9085 | 0 | 20U, // S2_pstorerit_pi |
9086 | 0 | 20U, // S2_pstoreritnew_pi |
9087 | 0 | 0U, // S2_setbit_i |
9088 | 0 | 0U, // S2_setbit_r |
9089 | 0 | 0U, // S2_shuffeb |
9090 | 0 | 0U, // S2_shuffeh |
9091 | 0 | 0U, // S2_shuffob |
9092 | 0 | 0U, // S2_shuffoh |
9093 | 0 | 0U, // S2_storerb_io |
9094 | 0 | 0U, // S2_storerb_pbr |
9095 | 0 | 0U, // S2_storerb_pci |
9096 | 0 | 0U, // S2_storerb_pcr |
9097 | 0 | 0U, // S2_storerb_pi |
9098 | 0 | 0U, // S2_storerb_pr |
9099 | 0 | 0U, // S2_storerbgp |
9100 | 0 | 0U, // S2_storerbnew_io |
9101 | 0 | 0U, // S2_storerbnew_pbr |
9102 | 0 | 0U, // S2_storerbnew_pci |
9103 | 0 | 0U, // S2_storerbnew_pcr |
9104 | 0 | 0U, // S2_storerbnew_pi |
9105 | 0 | 0U, // S2_storerbnew_pr |
9106 | 0 | 0U, // S2_storerbnewgp |
9107 | 0 | 0U, // S2_storerd_io |
9108 | 0 | 0U, // S2_storerd_pbr |
9109 | 0 | 0U, // S2_storerd_pci |
9110 | 0 | 0U, // S2_storerd_pcr |
9111 | 0 | 0U, // S2_storerd_pi |
9112 | 0 | 0U, // S2_storerd_pr |
9113 | 0 | 0U, // S2_storerdgp |
9114 | 0 | 0U, // S2_storerf_io |
9115 | 0 | 0U, // S2_storerf_pbr |
9116 | 0 | 0U, // S2_storerf_pci |
9117 | 0 | 0U, // S2_storerf_pcr |
9118 | 0 | 0U, // S2_storerf_pi |
9119 | 0 | 0U, // S2_storerf_pr |
9120 | 0 | 0U, // S2_storerfgp |
9121 | 0 | 0U, // S2_storerh_io |
9122 | 0 | 0U, // S2_storerh_pbr |
9123 | 0 | 0U, // S2_storerh_pci |
9124 | 0 | 0U, // S2_storerh_pcr |
9125 | 0 | 0U, // S2_storerh_pi |
9126 | 0 | 0U, // S2_storerh_pr |
9127 | 0 | 0U, // S2_storerhgp |
9128 | 0 | 0U, // S2_storerhnew_io |
9129 | 0 | 0U, // S2_storerhnew_pbr |
9130 | 0 | 0U, // S2_storerhnew_pci |
9131 | 0 | 0U, // S2_storerhnew_pcr |
9132 | 0 | 0U, // S2_storerhnew_pi |
9133 | 0 | 0U, // S2_storerhnew_pr |
9134 | 0 | 0U, // S2_storerhnewgp |
9135 | 0 | 0U, // S2_storeri_io |
9136 | 0 | 0U, // S2_storeri_pbr |
9137 | 0 | 0U, // S2_storeri_pci |
9138 | 0 | 0U, // S2_storeri_pcr |
9139 | 0 | 0U, // S2_storeri_pi |
9140 | 0 | 0U, // S2_storeri_pr |
9141 | 0 | 0U, // S2_storerigp |
9142 | 0 | 0U, // S2_storerinew_io |
9143 | 0 | 0U, // S2_storerinew_pbr |
9144 | 0 | 0U, // S2_storerinew_pci |
9145 | 0 | 0U, // S2_storerinew_pcr |
9146 | 0 | 0U, // S2_storerinew_pi |
9147 | 0 | 0U, // S2_storerinew_pr |
9148 | 0 | 0U, // S2_storerinewgp |
9149 | 0 | 0U, // S2_storew_locked |
9150 | 0 | 0U, // S2_storew_rl_at_vi |
9151 | 0 | 0U, // S2_storew_rl_st_vi |
9152 | 0 | 0U, // S2_svsathb |
9153 | 0 | 0U, // S2_svsathub |
9154 | 0 | 0U, // S2_tableidxb |
9155 | 0 | 0U, // S2_tableidxd |
9156 | 0 | 0U, // S2_tableidxh |
9157 | 0 | 0U, // S2_tableidxw |
9158 | 0 | 0U, // S2_togglebit_i |
9159 | 0 | 0U, // S2_togglebit_r |
9160 | 0 | 0U, // S2_tstbit_i |
9161 | 0 | 0U, // S2_tstbit_r |
9162 | 0 | 0U, // S2_valignib |
9163 | 0 | 0U, // S2_valignrb |
9164 | 0 | 0U, // S2_vcnegh |
9165 | 0 | 0U, // S2_vcrotate |
9166 | 0 | 0U, // S2_vrcnegh |
9167 | 0 | 0U, // S2_vrndpackwh |
9168 | 0 | 0U, // S2_vrndpackwhs |
9169 | 0 | 0U, // S2_vsathb |
9170 | 0 | 0U, // S2_vsathb_nopack |
9171 | 0 | 0U, // S2_vsathub |
9172 | 0 | 0U, // S2_vsathub_nopack |
9173 | 0 | 0U, // S2_vsatwh |
9174 | 0 | 0U, // S2_vsatwh_nopack |
9175 | 0 | 0U, // S2_vsatwuh |
9176 | 0 | 0U, // S2_vsatwuh_nopack |
9177 | 0 | 0U, // S2_vsplatrb |
9178 | 0 | 0U, // S2_vsplatrh |
9179 | 0 | 0U, // S2_vspliceib |
9180 | 0 | 0U, // S2_vsplicerb |
9181 | 0 | 0U, // S2_vsxtbh |
9182 | 0 | 0U, // S2_vsxthw |
9183 | 0 | 0U, // S2_vtrunehb |
9184 | 0 | 0U, // S2_vtrunewh |
9185 | 0 | 0U, // S2_vtrunohb |
9186 | 0 | 0U, // S2_vtrunowh |
9187 | 0 | 0U, // S2_vzxtbh |
9188 | 0 | 0U, // S2_vzxthw |
9189 | 0 | 0U, // S4_addaddi |
9190 | 0 | 0U, // S4_addi_asl_ri |
9191 | 0 | 0U, // S4_addi_lsr_ri |
9192 | 0 | 0U, // S4_andi_asl_ri |
9193 | 0 | 0U, // S4_andi_lsr_ri |
9194 | 0 | 0U, // S4_clbaddi |
9195 | 0 | 0U, // S4_clbpaddi |
9196 | 0 | 0U, // S4_clbpnorm |
9197 | 0 | 8U, // S4_extract |
9198 | 0 | 0U, // S4_extract_rp |
9199 | 0 | 8U, // S4_extractp |
9200 | 0 | 0U, // S4_extractp_rp |
9201 | 0 | 0U, // S4_lsli |
9202 | 0 | 0U, // S4_ntstbit_i |
9203 | 0 | 0U, // S4_ntstbit_r |
9204 | 0 | 0U, // S4_or_andi |
9205 | 0 | 0U, // S4_or_andix |
9206 | 0 | 0U, // S4_or_ori |
9207 | 0 | 0U, // S4_ori_asl_ri |
9208 | 0 | 0U, // S4_ori_lsr_ri |
9209 | 0 | 0U, // S4_parity |
9210 | 0 | 0U, // S4_pstorerbf_abs |
9211 | 0 | 0U, // S4_pstorerbf_rr |
9212 | 0 | 0U, // S4_pstorerbfnew_abs |
9213 | 0 | 16U, // S4_pstorerbfnew_io |
9214 | 0 | 0U, // S4_pstorerbfnew_rr |
9215 | 0 | 0U, // S4_pstorerbnewf_abs |
9216 | 0 | 0U, // S4_pstorerbnewf_rr |
9217 | 0 | 0U, // S4_pstorerbnewfnew_abs |
9218 | 0 | 48U, // S4_pstorerbnewfnew_io |
9219 | 0 | 0U, // S4_pstorerbnewfnew_rr |
9220 | 0 | 0U, // S4_pstorerbnewt_abs |
9221 | 0 | 0U, // S4_pstorerbnewt_rr |
9222 | 0 | 0U, // S4_pstorerbnewtnew_abs |
9223 | 0 | 48U, // S4_pstorerbnewtnew_io |
9224 | 0 | 0U, // S4_pstorerbnewtnew_rr |
9225 | 0 | 0U, // S4_pstorerbt_abs |
9226 | 0 | 0U, // S4_pstorerbt_rr |
9227 | 0 | 0U, // S4_pstorerbtnew_abs |
9228 | 0 | 16U, // S4_pstorerbtnew_io |
9229 | 0 | 0U, // S4_pstorerbtnew_rr |
9230 | 0 | 0U, // S4_pstorerdf_abs |
9231 | 0 | 0U, // S4_pstorerdf_rr |
9232 | 0 | 0U, // S4_pstorerdfnew_abs |
9233 | 0 | 16U, // S4_pstorerdfnew_io |
9234 | 0 | 0U, // S4_pstorerdfnew_rr |
9235 | 0 | 0U, // S4_pstorerdt_abs |
9236 | 0 | 0U, // S4_pstorerdt_rr |
9237 | 0 | 0U, // S4_pstorerdtnew_abs |
9238 | 0 | 16U, // S4_pstorerdtnew_io |
9239 | 0 | 0U, // S4_pstorerdtnew_rr |
9240 | 0 | 0U, // S4_pstorerff_abs |
9241 | 0 | 0U, // S4_pstorerff_rr |
9242 | 0 | 0U, // S4_pstorerffnew_abs |
9243 | 0 | 80U, // S4_pstorerffnew_io |
9244 | 0 | 0U, // S4_pstorerffnew_rr |
9245 | 0 | 0U, // S4_pstorerft_abs |
9246 | 0 | 0U, // S4_pstorerft_rr |
9247 | 0 | 0U, // S4_pstorerftnew_abs |
9248 | 0 | 80U, // S4_pstorerftnew_io |
9249 | 0 | 0U, // S4_pstorerftnew_rr |
9250 | 0 | 0U, // S4_pstorerhf_abs |
9251 | 0 | 0U, // S4_pstorerhf_rr |
9252 | 0 | 0U, // S4_pstorerhfnew_abs |
9253 | 0 | 16U, // S4_pstorerhfnew_io |
9254 | 0 | 0U, // S4_pstorerhfnew_rr |
9255 | 0 | 0U, // S4_pstorerhnewf_abs |
9256 | 0 | 0U, // S4_pstorerhnewf_rr |
9257 | 0 | 0U, // S4_pstorerhnewfnew_abs |
9258 | 0 | 48U, // S4_pstorerhnewfnew_io |
9259 | 0 | 0U, // S4_pstorerhnewfnew_rr |
9260 | 0 | 0U, // S4_pstorerhnewt_abs |
9261 | 0 | 0U, // S4_pstorerhnewt_rr |
9262 | 0 | 0U, // S4_pstorerhnewtnew_abs |
9263 | 0 | 48U, // S4_pstorerhnewtnew_io |
9264 | 0 | 0U, // S4_pstorerhnewtnew_rr |
9265 | 0 | 0U, // S4_pstorerht_abs |
9266 | 0 | 0U, // S4_pstorerht_rr |
9267 | 0 | 0U, // S4_pstorerhtnew_abs |
9268 | 0 | 16U, // S4_pstorerhtnew_io |
9269 | 0 | 0U, // S4_pstorerhtnew_rr |
9270 | 0 | 0U, // S4_pstorerif_abs |
9271 | 0 | 0U, // S4_pstorerif_rr |
9272 | 0 | 0U, // S4_pstorerifnew_abs |
9273 | 0 | 16U, // S4_pstorerifnew_io |
9274 | 0 | 0U, // S4_pstorerifnew_rr |
9275 | 0 | 0U, // S4_pstorerinewf_abs |
9276 | 0 | 0U, // S4_pstorerinewf_rr |
9277 | 0 | 0U, // S4_pstorerinewfnew_abs |
9278 | 0 | 48U, // S4_pstorerinewfnew_io |
9279 | 0 | 0U, // S4_pstorerinewfnew_rr |
9280 | 0 | 0U, // S4_pstorerinewt_abs |
9281 | 0 | 0U, // S4_pstorerinewt_rr |
9282 | 0 | 0U, // S4_pstorerinewtnew_abs |
9283 | 0 | 48U, // S4_pstorerinewtnew_io |
9284 | 0 | 0U, // S4_pstorerinewtnew_rr |
9285 | 0 | 0U, // S4_pstorerit_abs |
9286 | 0 | 0U, // S4_pstorerit_rr |
9287 | 0 | 0U, // S4_pstoreritnew_abs |
9288 | 0 | 16U, // S4_pstoreritnew_io |
9289 | 0 | 0U, // S4_pstoreritnew_rr |
9290 | 0 | 0U, // S4_stored_locked |
9291 | 0 | 0U, // S4_stored_rl_at_vi |
9292 | 0 | 0U, // S4_stored_rl_st_vi |
9293 | 0 | 0U, // S4_storeirb_io |
9294 | 0 | 0U, // S4_storeirbf_io |
9295 | 0 | 0U, // S4_storeirbfnew_io |
9296 | 0 | 0U, // S4_storeirbt_io |
9297 | 0 | 0U, // S4_storeirbtnew_io |
9298 | 0 | 0U, // S4_storeirh_io |
9299 | 0 | 0U, // S4_storeirhf_io |
9300 | 0 | 0U, // S4_storeirhfnew_io |
9301 | 0 | 0U, // S4_storeirht_io |
9302 | 0 | 0U, // S4_storeirhtnew_io |
9303 | 0 | 0U, // S4_storeiri_io |
9304 | 0 | 0U, // S4_storeirif_io |
9305 | 0 | 0U, // S4_storeirifnew_io |
9306 | 0 | 0U, // S4_storeirit_io |
9307 | 0 | 0U, // S4_storeiritnew_io |
9308 | 0 | 0U, // S4_storerb_ap |
9309 | 0 | 0U, // S4_storerb_rr |
9310 | 0 | 0U, // S4_storerb_ur |
9311 | 0 | 0U, // S4_storerbnew_ap |
9312 | 0 | 0U, // S4_storerbnew_rr |
9313 | 0 | 0U, // S4_storerbnew_ur |
9314 | 0 | 0U, // S4_storerd_ap |
9315 | 0 | 0U, // S4_storerd_rr |
9316 | 0 | 0U, // S4_storerd_ur |
9317 | 0 | 0U, // S4_storerf_ap |
9318 | 0 | 0U, // S4_storerf_rr |
9319 | 0 | 0U, // S4_storerf_ur |
9320 | 0 | 0U, // S4_storerh_ap |
9321 | 0 | 0U, // S4_storerh_rr |
9322 | 0 | 0U, // S4_storerh_ur |
9323 | 0 | 0U, // S4_storerhnew_ap |
9324 | 0 | 0U, // S4_storerhnew_rr |
9325 | 0 | 0U, // S4_storerhnew_ur |
9326 | 0 | 0U, // S4_storeri_ap |
9327 | 0 | 0U, // S4_storeri_rr |
9328 | 0 | 0U, // S4_storeri_ur |
9329 | 0 | 0U, // S4_storerinew_ap |
9330 | 0 | 0U, // S4_storerinew_rr |
9331 | 0 | 0U, // S4_storerinew_ur |
9332 | 0 | 0U, // S4_subaddi |
9333 | 0 | 0U, // S4_subi_asl_ri |
9334 | 0 | 0U, // S4_subi_lsr_ri |
9335 | 0 | 0U, // S4_vrcrotate |
9336 | 0 | 0U, // S4_vrcrotate_acc |
9337 | 0 | 0U, // S4_vxaddsubh |
9338 | 0 | 0U, // S4_vxaddsubhr |
9339 | 0 | 0U, // S4_vxaddsubw |
9340 | 0 | 0U, // S4_vxsubaddh |
9341 | 0 | 0U, // S4_vxsubaddhr |
9342 | 0 | 0U, // S4_vxsubaddw |
9343 | 0 | 0U, // S5_asrhub_rnd_sat |
9344 | 0 | 0U, // S5_asrhub_sat |
9345 | 0 | 0U, // S5_popcountp |
9346 | 0 | 0U, // S5_vasrhrnd |
9347 | 0 | 0U, // S6_rol_i_p |
9348 | 0 | 0U, // S6_rol_i_p_acc |
9349 | 0 | 0U, // S6_rol_i_p_and |
9350 | 0 | 0U, // S6_rol_i_p_nac |
9351 | 0 | 0U, // S6_rol_i_p_or |
9352 | 0 | 0U, // S6_rol_i_p_xacc |
9353 | 0 | 0U, // S6_rol_i_r |
9354 | 0 | 0U, // S6_rol_i_r_acc |
9355 | 0 | 0U, // S6_rol_i_r_and |
9356 | 0 | 0U, // S6_rol_i_r_nac |
9357 | 0 | 0U, // S6_rol_i_r_or |
9358 | 0 | 0U, // S6_rol_i_r_xacc |
9359 | 0 | 0U, // S6_vsplatrbp |
9360 | 0 | 0U, // S6_vtrunehb_ppp |
9361 | 0 | 0U, // S6_vtrunohb_ppp |
9362 | 0 | 0U, // SA1_addi |
9363 | 0 | 0U, // SA1_addrx |
9364 | 0 | 0U, // SA1_addsp |
9365 | 0 | 0U, // SA1_and1 |
9366 | 0 | 0U, // SA1_clrf |
9367 | 0 | 0U, // SA1_clrfnew |
9368 | 0 | 0U, // SA1_clrt |
9369 | 0 | 0U, // SA1_clrtnew |
9370 | 0 | 0U, // SA1_cmpeqi |
9371 | 0 | 0U, // SA1_combine0i |
9372 | 0 | 0U, // SA1_combine1i |
9373 | 0 | 0U, // SA1_combine2i |
9374 | 0 | 0U, // SA1_combine3i |
9375 | 0 | 0U, // SA1_combinerz |
9376 | 0 | 0U, // SA1_combinezr |
9377 | 0 | 0U, // SA1_dec |
9378 | 0 | 0U, // SA1_inc |
9379 | 0 | 0U, // SA1_seti |
9380 | 0 | 0U, // SA1_setin1 |
9381 | 0 | 0U, // SA1_sxtb |
9382 | 0 | 0U, // SA1_sxth |
9383 | 0 | 0U, // SA1_tfr |
9384 | 0 | 0U, // SA1_zxtb |
9385 | 0 | 0U, // SA1_zxth |
9386 | 0 | 0U, // SAVE_REGISTERS_CALL_V4 |
9387 | 0 | 0U, // SAVE_REGISTERS_CALL_V4STK |
9388 | 0 | 0U, // SAVE_REGISTERS_CALL_V4STK_EXT |
9389 | 0 | 0U, // SAVE_REGISTERS_CALL_V4STK_EXT_PIC |
9390 | 0 | 0U, // SAVE_REGISTERS_CALL_V4STK_PIC |
9391 | 0 | 0U, // SAVE_REGISTERS_CALL_V4_EXT |
9392 | 0 | 0U, // SAVE_REGISTERS_CALL_V4_EXT_PIC |
9393 | 0 | 0U, // SAVE_REGISTERS_CALL_V4_PIC |
9394 | 0 | 0U, // SL1_loadri_io |
9395 | 0 | 0U, // SL1_loadrub_io |
9396 | 0 | 0U, // SL2_deallocframe |
9397 | 0 | 0U, // SL2_jumpr31 |
9398 | 0 | 0U, // SL2_jumpr31_f |
9399 | 0 | 0U, // SL2_jumpr31_fnew |
9400 | 0 | 0U, // SL2_jumpr31_t |
9401 | 0 | 0U, // SL2_jumpr31_tnew |
9402 | 0 | 0U, // SL2_loadrb_io |
9403 | 0 | 0U, // SL2_loadrd_sp |
9404 | 0 | 0U, // SL2_loadrh_io |
9405 | 0 | 0U, // SL2_loadri_sp |
9406 | 0 | 0U, // SL2_loadruh_io |
9407 | 0 | 0U, // SL2_return |
9408 | 0 | 0U, // SL2_return_f |
9409 | 0 | 0U, // SL2_return_fnew |
9410 | 0 | 0U, // SL2_return_t |
9411 | 0 | 0U, // SL2_return_tnew |
9412 | 0 | 0U, // SS1_storeb_io |
9413 | 0 | 0U, // SS1_storew_io |
9414 | 0 | 0U, // SS2_allocframe |
9415 | 0 | 0U, // SS2_storebi0 |
9416 | 0 | 0U, // SS2_storebi1 |
9417 | 0 | 0U, // SS2_stored_sp |
9418 | 0 | 0U, // SS2_storeh_io |
9419 | 0 | 0U, // SS2_storew_sp |
9420 | 0 | 0U, // SS2_storewi0 |
9421 | 0 | 0U, // SS2_storewi1 |
9422 | 0 | 0U, // TFRI64_V2_ext |
9423 | 0 | 0U, // TFRI64_V4 |
9424 | 0 | 0U, // V6_extractw |
9425 | 0 | 0U, // V6_lvsplatb |
9426 | 0 | 0U, // V6_lvsplath |
9427 | 0 | 0U, // V6_lvsplatw |
9428 | 0 | 0U, // V6_pred_and |
9429 | 0 | 0U, // V6_pred_and_n |
9430 | 0 | 0U, // V6_pred_not |
9431 | 0 | 0U, // V6_pred_or |
9432 | 0 | 0U, // V6_pred_or_n |
9433 | 0 | 0U, // V6_pred_scalar2 |
9434 | 0 | 0U, // V6_pred_scalar2v2 |
9435 | 0 | 0U, // V6_pred_xor |
9436 | 0 | 0U, // V6_shuffeqh |
9437 | 0 | 0U, // V6_shuffeqw |
9438 | 0 | 0U, // V6_v6mpyhubs10 |
9439 | 0 | 0U, // V6_v6mpyhubs10_vxx |
9440 | 0 | 0U, // V6_v6mpyvubs10 |
9441 | 0 | 0U, // V6_v6mpyvubs10_vxx |
9442 | 0 | 0U, // V6_vL32Ub_ai |
9443 | 0 | 0U, // V6_vL32Ub_pi |
9444 | 0 | 0U, // V6_vL32Ub_ppu |
9445 | 0 | 0U, // V6_vL32b_ai |
9446 | 0 | 0U, // V6_vL32b_cur_ai |
9447 | 0 | 0U, // V6_vL32b_cur_npred_ai |
9448 | 0 | 0U, // V6_vL32b_cur_npred_pi |
9449 | 0 | 0U, // V6_vL32b_cur_npred_ppu |
9450 | 0 | 0U, // V6_vL32b_cur_pi |
9451 | 0 | 0U, // V6_vL32b_cur_ppu |
9452 | 0 | 0U, // V6_vL32b_cur_pred_ai |
9453 | 0 | 0U, // V6_vL32b_cur_pred_pi |
9454 | 0 | 0U, // V6_vL32b_cur_pred_ppu |
9455 | 0 | 0U, // V6_vL32b_npred_ai |
9456 | 0 | 0U, // V6_vL32b_npred_pi |
9457 | 0 | 0U, // V6_vL32b_npred_ppu |
9458 | 0 | 0U, // V6_vL32b_nt_ai |
9459 | 0 | 0U, // V6_vL32b_nt_cur_ai |
9460 | 0 | 1U, // V6_vL32b_nt_cur_npred_ai |
9461 | 0 | 1U, // V6_vL32b_nt_cur_npred_pi |
9462 | 0 | 1U, // V6_vL32b_nt_cur_npred_ppu |
9463 | 0 | 0U, // V6_vL32b_nt_cur_pi |
9464 | 0 | 0U, // V6_vL32b_nt_cur_ppu |
9465 | 0 | 1U, // V6_vL32b_nt_cur_pred_ai |
9466 | 0 | 1U, // V6_vL32b_nt_cur_pred_pi |
9467 | 0 | 1U, // V6_vL32b_nt_cur_pred_ppu |
9468 | 0 | 1U, // V6_vL32b_nt_npred_ai |
9469 | 0 | 1U, // V6_vL32b_nt_npred_pi |
9470 | 0 | 1U, // V6_vL32b_nt_npred_ppu |
9471 | 0 | 0U, // V6_vL32b_nt_pi |
9472 | 0 | 0U, // V6_vL32b_nt_ppu |
9473 | 0 | 1U, // V6_vL32b_nt_pred_ai |
9474 | 0 | 1U, // V6_vL32b_nt_pred_pi |
9475 | 0 | 1U, // V6_vL32b_nt_pred_ppu |
9476 | 0 | 0U, // V6_vL32b_nt_tmp_ai |
9477 | 0 | 1U, // V6_vL32b_nt_tmp_npred_ai |
9478 | 0 | 1U, // V6_vL32b_nt_tmp_npred_pi |
9479 | 0 | 1U, // V6_vL32b_nt_tmp_npred_ppu |
9480 | 0 | 0U, // V6_vL32b_nt_tmp_pi |
9481 | 0 | 0U, // V6_vL32b_nt_tmp_ppu |
9482 | 0 | 1U, // V6_vL32b_nt_tmp_pred_ai |
9483 | 0 | 1U, // V6_vL32b_nt_tmp_pred_pi |
9484 | 0 | 1U, // V6_vL32b_nt_tmp_pred_ppu |
9485 | 0 | 0U, // V6_vL32b_pi |
9486 | 0 | 0U, // V6_vL32b_ppu |
9487 | 0 | 0U, // V6_vL32b_pred_ai |
9488 | 0 | 0U, // V6_vL32b_pred_pi |
9489 | 0 | 0U, // V6_vL32b_pred_ppu |
9490 | 0 | 0U, // V6_vL32b_tmp_ai |
9491 | 0 | 0U, // V6_vL32b_tmp_npred_ai |
9492 | 0 | 0U, // V6_vL32b_tmp_npred_pi |
9493 | 0 | 0U, // V6_vL32b_tmp_npred_ppu |
9494 | 0 | 0U, // V6_vL32b_tmp_pi |
9495 | 0 | 0U, // V6_vL32b_tmp_ppu |
9496 | 0 | 0U, // V6_vL32b_tmp_pred_ai |
9497 | 0 | 0U, // V6_vL32b_tmp_pred_pi |
9498 | 0 | 0U, // V6_vL32b_tmp_pred_ppu |
9499 | 0 | 0U, // V6_vS32Ub_ai |
9500 | 0 | 16U, // V6_vS32Ub_npred_ai |
9501 | 0 | 20U, // V6_vS32Ub_npred_pi |
9502 | 0 | 20U, // V6_vS32Ub_npred_ppu |
9503 | 0 | 0U, // V6_vS32Ub_pi |
9504 | 0 | 0U, // V6_vS32Ub_ppu |
9505 | 0 | 16U, // V6_vS32Ub_pred_ai |
9506 | 0 | 20U, // V6_vS32Ub_pred_pi |
9507 | 0 | 20U, // V6_vS32Ub_pred_ppu |
9508 | 0 | 0U, // V6_vS32b_ai |
9509 | 0 | 0U, // V6_vS32b_new_ai |
9510 | 0 | 48U, // V6_vS32b_new_npred_ai |
9511 | 0 | 52U, // V6_vS32b_new_npred_pi |
9512 | 0 | 52U, // V6_vS32b_new_npred_ppu |
9513 | 0 | 0U, // V6_vS32b_new_pi |
9514 | 0 | 0U, // V6_vS32b_new_ppu |
9515 | 0 | 48U, // V6_vS32b_new_pred_ai |
9516 | 0 | 52U, // V6_vS32b_new_pred_pi |
9517 | 0 | 52U, // V6_vS32b_new_pred_ppu |
9518 | 0 | 16U, // V6_vS32b_npred_ai |
9519 | 0 | 20U, // V6_vS32b_npred_pi |
9520 | 0 | 20U, // V6_vS32b_npred_ppu |
9521 | 0 | 16U, // V6_vS32b_nqpred_ai |
9522 | 0 | 20U, // V6_vS32b_nqpred_pi |
9523 | 0 | 20U, // V6_vS32b_nqpred_ppu |
9524 | 0 | 0U, // V6_vS32b_nt_ai |
9525 | 0 | 0U, // V6_vS32b_nt_new_ai |
9526 | 0 | 49U, // V6_vS32b_nt_new_npred_ai |
9527 | 0 | 53U, // V6_vS32b_nt_new_npred_pi |
9528 | 0 | 53U, // V6_vS32b_nt_new_npred_ppu |
9529 | 0 | 0U, // V6_vS32b_nt_new_pi |
9530 | 0 | 0U, // V6_vS32b_nt_new_ppu |
9531 | 0 | 49U, // V6_vS32b_nt_new_pred_ai |
9532 | 0 | 53U, // V6_vS32b_nt_new_pred_pi |
9533 | 0 | 53U, // V6_vS32b_nt_new_pred_ppu |
9534 | 0 | 17U, // V6_vS32b_nt_npred_ai |
9535 | 0 | 21U, // V6_vS32b_nt_npred_pi |
9536 | 0 | 21U, // V6_vS32b_nt_npred_ppu |
9537 | 0 | 17U, // V6_vS32b_nt_nqpred_ai |
9538 | 0 | 21U, // V6_vS32b_nt_nqpred_pi |
9539 | 0 | 21U, // V6_vS32b_nt_nqpred_ppu |
9540 | 0 | 0U, // V6_vS32b_nt_pi |
9541 | 0 | 0U, // V6_vS32b_nt_ppu |
9542 | 0 | 17U, // V6_vS32b_nt_pred_ai |
9543 | 0 | 21U, // V6_vS32b_nt_pred_pi |
9544 | 0 | 21U, // V6_vS32b_nt_pred_ppu |
9545 | 0 | 17U, // V6_vS32b_nt_qpred_ai |
9546 | 0 | 21U, // V6_vS32b_nt_qpred_pi |
9547 | 0 | 21U, // V6_vS32b_nt_qpred_ppu |
9548 | 0 | 0U, // V6_vS32b_pi |
9549 | 0 | 0U, // V6_vS32b_ppu |
9550 | 0 | 16U, // V6_vS32b_pred_ai |
9551 | 0 | 20U, // V6_vS32b_pred_pi |
9552 | 0 | 20U, // V6_vS32b_pred_ppu |
9553 | 0 | 16U, // V6_vS32b_qpred_ai |
9554 | 0 | 20U, // V6_vS32b_qpred_pi |
9555 | 0 | 20U, // V6_vS32b_qpred_ppu |
9556 | 0 | 0U, // V6_vS32b_srls_ai |
9557 | 0 | 0U, // V6_vS32b_srls_pi |
9558 | 0 | 0U, // V6_vS32b_srls_ppu |
9559 | 0 | 0U, // V6_vabs_hf |
9560 | 0 | 0U, // V6_vabs_sf |
9561 | 0 | 0U, // V6_vabsb |
9562 | 0 | 0U, // V6_vabsb_sat |
9563 | 0 | 0U, // V6_vabsdiffh |
9564 | 0 | 0U, // V6_vabsdiffub |
9565 | 0 | 0U, // V6_vabsdiffuh |
9566 | 0 | 0U, // V6_vabsdiffw |
9567 | 0 | 0U, // V6_vabsh |
9568 | 0 | 0U, // V6_vabsh_sat |
9569 | 0 | 0U, // V6_vabsw |
9570 | 0 | 0U, // V6_vabsw_sat |
9571 | 0 | 0U, // V6_vadd_hf |
9572 | 0 | 0U, // V6_vadd_hf_hf |
9573 | 0 | 0U, // V6_vadd_qf16 |
9574 | 0 | 0U, // V6_vadd_qf16_mix |
9575 | 0 | 0U, // V6_vadd_qf32 |
9576 | 0 | 0U, // V6_vadd_qf32_mix |
9577 | 0 | 0U, // V6_vadd_sf |
9578 | 0 | 0U, // V6_vadd_sf_bf |
9579 | 0 | 0U, // V6_vadd_sf_hf |
9580 | 0 | 0U, // V6_vadd_sf_sf |
9581 | 0 | 0U, // V6_vaddb |
9582 | 0 | 0U, // V6_vaddb_dv |
9583 | 0 | 0U, // V6_vaddbnq |
9584 | 0 | 0U, // V6_vaddbq |
9585 | 0 | 0U, // V6_vaddbsat |
9586 | 0 | 0U, // V6_vaddbsat_dv |
9587 | 0 | 25U, // V6_vaddcarry |
9588 | 0 | 0U, // V6_vaddcarryo |
9589 | 0 | 113U, // V6_vaddcarrysat |
9590 | 0 | 0U, // V6_vaddclbh |
9591 | 0 | 0U, // V6_vaddclbw |
9592 | 0 | 0U, // V6_vaddh |
9593 | 0 | 0U, // V6_vaddh_dv |
9594 | 0 | 0U, // V6_vaddhnq |
9595 | 0 | 0U, // V6_vaddhq |
9596 | 0 | 0U, // V6_vaddhsat |
9597 | 0 | 0U, // V6_vaddhsat_dv |
9598 | 0 | 0U, // V6_vaddhw |
9599 | 0 | 0U, // V6_vaddhw_acc |
9600 | 0 | 0U, // V6_vaddubh |
9601 | 0 | 0U, // V6_vaddubh_acc |
9602 | 0 | 0U, // V6_vaddubsat |
9603 | 0 | 0U, // V6_vaddubsat_dv |
9604 | 0 | 0U, // V6_vaddububb_sat |
9605 | 0 | 0U, // V6_vadduhsat |
9606 | 0 | 0U, // V6_vadduhsat_dv |
9607 | 0 | 0U, // V6_vadduhw |
9608 | 0 | 0U, // V6_vadduhw_acc |
9609 | 0 | 0U, // V6_vadduwsat |
9610 | 0 | 0U, // V6_vadduwsat_dv |
9611 | 0 | 1U, // V6_vaddw |
9612 | 0 | 1U, // V6_vaddw_dv |
9613 | 0 | 0U, // V6_vaddwnq |
9614 | 0 | 0U, // V6_vaddwq |
9615 | 0 | 1U, // V6_vaddwsat |
9616 | 0 | 1U, // V6_vaddwsat_dv |
9617 | 0 | 0U, // V6_valignb |
9618 | 0 | 0U, // V6_valignbi |
9619 | 0 | 0U, // V6_vand |
9620 | 0 | 0U, // V6_vandnqrt |
9621 | 0 | 0U, // V6_vandnqrt_acc |
9622 | 0 | 0U, // V6_vandqrt |
9623 | 0 | 0U, // V6_vandqrt_acc |
9624 | 0 | 0U, // V6_vandvnqv |
9625 | 0 | 0U, // V6_vandvqv |
9626 | 0 | 0U, // V6_vandvrt |
9627 | 0 | 0U, // V6_vandvrt_acc |
9628 | 0 | 0U, // V6_vaslh |
9629 | 0 | 0U, // V6_vaslh_acc |
9630 | 0 | 0U, // V6_vaslhv |
9631 | 0 | 0U, // V6_vaslw |
9632 | 0 | 0U, // V6_vaslw_acc |
9633 | 0 | 0U, // V6_vaslwv |
9634 | 0 | 0U, // V6_vasr_into |
9635 | 0 | 0U, // V6_vasrh |
9636 | 0 | 0U, // V6_vasrh_acc |
9637 | 0 | 0U, // V6_vasrhbrndsat |
9638 | 0 | 0U, // V6_vasrhbsat |
9639 | 0 | 1U, // V6_vasrhubrndsat |
9640 | 0 | 0U, // V6_vasrhubsat |
9641 | 0 | 0U, // V6_vasrhv |
9642 | 0 | 1U, // V6_vasruhubrndsat |
9643 | 0 | 0U, // V6_vasruhubsat |
9644 | 0 | 1U, // V6_vasruwuhrndsat |
9645 | 0 | 0U, // V6_vasruwuhsat |
9646 | 0 | 0U, // V6_vasrvuhubrndsat |
9647 | 0 | 0U, // V6_vasrvuhubsat |
9648 | 0 | 0U, // V6_vasrvwuhrndsat |
9649 | 0 | 0U, // V6_vasrvwuhsat |
9650 | 0 | 0U, // V6_vasrw |
9651 | 0 | 0U, // V6_vasrw_acc |
9652 | 0 | 0U, // V6_vasrwh |
9653 | 0 | 1U, // V6_vasrwhrndsat |
9654 | 0 | 0U, // V6_vasrwhsat |
9655 | 0 | 1U, // V6_vasrwuhrndsat |
9656 | 0 | 0U, // V6_vasrwuhsat |
9657 | 0 | 0U, // V6_vasrwv |
9658 | 0 | 0U, // V6_vassign |
9659 | 0 | 0U, // V6_vassign_fp |
9660 | 0 | 0U, // V6_vassign_tmp |
9661 | 0 | 0U, // V6_vavgb |
9662 | 0 | 0U, // V6_vavgbrnd |
9663 | 0 | 0U, // V6_vavgh |
9664 | 0 | 0U, // V6_vavghrnd |
9665 | 0 | 0U, // V6_vavgub |
9666 | 0 | 0U, // V6_vavgubrnd |
9667 | 0 | 0U, // V6_vavguh |
9668 | 0 | 0U, // V6_vavguhrnd |
9669 | 0 | 0U, // V6_vavguw |
9670 | 0 | 0U, // V6_vavguwrnd |
9671 | 0 | 0U, // V6_vavgw |
9672 | 0 | 0U, // V6_vavgwrnd |
9673 | 0 | 0U, // V6_vccombine |
9674 | 0 | 0U, // V6_vcl0h |
9675 | 0 | 0U, // V6_vcl0w |
9676 | 0 | 0U, // V6_vcmov |
9677 | 0 | 0U, // V6_vcombine |
9678 | 0 | 0U, // V6_vcombine_tmp |
9679 | 0 | 0U, // V6_vconv_h_hf |
9680 | 0 | 0U, // V6_vconv_hf_h |
9681 | 0 | 0U, // V6_vconv_hf_qf16 |
9682 | 0 | 0U, // V6_vconv_hf_qf32 |
9683 | 0 | 0U, // V6_vconv_sf_qf32 |
9684 | 0 | 0U, // V6_vconv_sf_w |
9685 | 0 | 0U, // V6_vconv_w_sf |
9686 | 0 | 0U, // V6_vcvt_b_hf |
9687 | 0 | 0U, // V6_vcvt_bf_sf |
9688 | 0 | 0U, // V6_vcvt_h_hf |
9689 | 0 | 0U, // V6_vcvt_hf_b |
9690 | 0 | 0U, // V6_vcvt_hf_h |
9691 | 0 | 0U, // V6_vcvt_hf_sf |
9692 | 0 | 0U, // V6_vcvt_hf_ub |
9693 | 0 | 0U, // V6_vcvt_hf_uh |
9694 | 0 | 0U, // V6_vcvt_sf_hf |
9695 | 0 | 0U, // V6_vcvt_ub_hf |
9696 | 0 | 0U, // V6_vcvt_uh_hf |
9697 | 0 | 0U, // V6_vdeal |
9698 | 0 | 0U, // V6_vdealb |
9699 | 0 | 0U, // V6_vdealb4w |
9700 | 0 | 0U, // V6_vdealh |
9701 | 0 | 0U, // V6_vdealvdd |
9702 | 0 | 0U, // V6_vdelta |
9703 | 0 | 0U, // V6_vdmpy_sf_hf |
9704 | 0 | 0U, // V6_vdmpy_sf_hf_acc |
9705 | 0 | 0U, // V6_vdmpybus |
9706 | 0 | 0U, // V6_vdmpybus_acc |
9707 | 0 | 0U, // V6_vdmpybus_dv |
9708 | 0 | 0U, // V6_vdmpybus_dv_acc |
9709 | 0 | 0U, // V6_vdmpyhb |
9710 | 0 | 0U, // V6_vdmpyhb_acc |
9711 | 0 | 0U, // V6_vdmpyhb_dv |
9712 | 0 | 0U, // V6_vdmpyhb_dv_acc |
9713 | 0 | 0U, // V6_vdmpyhisat |
9714 | 0 | 0U, // V6_vdmpyhisat_acc |
9715 | 0 | 0U, // V6_vdmpyhsat |
9716 | 0 | 0U, // V6_vdmpyhsat_acc |
9717 | 0 | 0U, // V6_vdmpyhsuisat |
9718 | 0 | 0U, // V6_vdmpyhsuisat_acc |
9719 | 0 | 0U, // V6_vdmpyhsusat |
9720 | 0 | 0U, // V6_vdmpyhsusat_acc |
9721 | 0 | 0U, // V6_vdmpyhvsat |
9722 | 0 | 0U, // V6_vdmpyhvsat_acc |
9723 | 0 | 0U, // V6_vdsaduh |
9724 | 0 | 0U, // V6_vdsaduh_acc |
9725 | 0 | 0U, // V6_veqb |
9726 | 0 | 0U, // V6_veqb_and |
9727 | 0 | 0U, // V6_veqb_or |
9728 | 0 | 0U, // V6_veqb_xor |
9729 | 0 | 0U, // V6_veqh |
9730 | 0 | 0U, // V6_veqh_and |
9731 | 0 | 0U, // V6_veqh_or |
9732 | 0 | 0U, // V6_veqh_xor |
9733 | 0 | 0U, // V6_veqw |
9734 | 0 | 0U, // V6_veqw_and |
9735 | 0 | 0U, // V6_veqw_or |
9736 | 0 | 0U, // V6_veqw_xor |
9737 | 0 | 0U, // V6_vfmax_hf |
9738 | 0 | 0U, // V6_vfmax_sf |
9739 | 0 | 0U, // V6_vfmin_hf |
9740 | 0 | 0U, // V6_vfmin_sf |
9741 | 0 | 0U, // V6_vfneg_hf |
9742 | 0 | 0U, // V6_vfneg_sf |
9743 | 0 | 1U, // V6_vgathermh |
9744 | 0 | 0U, // V6_vgathermhq |
9745 | 0 | 1U, // V6_vgathermhw |
9746 | 0 | 0U, // V6_vgathermhwq |
9747 | 0 | 1U, // V6_vgathermw |
9748 | 0 | 0U, // V6_vgathermwq |
9749 | 0 | 0U, // V6_vgtb |
9750 | 0 | 0U, // V6_vgtb_and |
9751 | 0 | 0U, // V6_vgtb_or |
9752 | 0 | 0U, // V6_vgtb_xor |
9753 | 0 | 0U, // V6_vgtbf |
9754 | 0 | 0U, // V6_vgtbf_and |
9755 | 0 | 0U, // V6_vgtbf_or |
9756 | 0 | 0U, // V6_vgtbf_xor |
9757 | 0 | 0U, // V6_vgth |
9758 | 0 | 0U, // V6_vgth_and |
9759 | 0 | 0U, // V6_vgth_or |
9760 | 0 | 0U, // V6_vgth_xor |
9761 | 0 | 0U, // V6_vgthf |
9762 | 0 | 0U, // V6_vgthf_and |
9763 | 0 | 0U, // V6_vgthf_or |
9764 | 0 | 0U, // V6_vgthf_xor |
9765 | 0 | 0U, // V6_vgtsf |
9766 | 0 | 0U, // V6_vgtsf_and |
9767 | 0 | 0U, // V6_vgtsf_or |
9768 | 0 | 0U, // V6_vgtsf_xor |
9769 | 0 | 0U, // V6_vgtub |
9770 | 0 | 0U, // V6_vgtub_and |
9771 | 0 | 0U, // V6_vgtub_or |
9772 | 0 | 0U, // V6_vgtub_xor |
9773 | 0 | 0U, // V6_vgtuh |
9774 | 0 | 0U, // V6_vgtuh_and |
9775 | 0 | 0U, // V6_vgtuh_or |
9776 | 0 | 0U, // V6_vgtuh_xor |
9777 | 0 | 0U, // V6_vgtuw |
9778 | 0 | 0U, // V6_vgtuw_and |
9779 | 0 | 0U, // V6_vgtuw_or |
9780 | 0 | 0U, // V6_vgtuw_xor |
9781 | 0 | 0U, // V6_vgtw |
9782 | 0 | 0U, // V6_vgtw_and |
9783 | 0 | 0U, // V6_vgtw_or |
9784 | 0 | 0U, // V6_vgtw_xor |
9785 | 0 | 0U, // V6_vhist |
9786 | 0 | 0U, // V6_vhistq |
9787 | 0 | 0U, // V6_vinsertwr |
9788 | 0 | 0U, // V6_vlalignb |
9789 | 0 | 0U, // V6_vlalignbi |
9790 | 0 | 0U, // V6_vlsrb |
9791 | 0 | 0U, // V6_vlsrh |
9792 | 0 | 0U, // V6_vlsrhv |
9793 | 0 | 0U, // V6_vlsrw |
9794 | 0 | 0U, // V6_vlsrwv |
9795 | 0 | 0U, // V6_vlut4 |
9796 | 0 | 0U, // V6_vlutvvb |
9797 | 0 | 0U, // V6_vlutvvb_nm |
9798 | 0 | 0U, // V6_vlutvvb_oracc |
9799 | 0 | 0U, // V6_vlutvvb_oracci |
9800 | 0 | 0U, // V6_vlutvvbi |
9801 | 0 | 0U, // V6_vlutvwh |
9802 | 0 | 0U, // V6_vlutvwh_nm |
9803 | 0 | 0U, // V6_vlutvwh_oracc |
9804 | 0 | 0U, // V6_vlutvwh_oracci |
9805 | 0 | 0U, // V6_vlutvwhi |
9806 | 0 | 0U, // V6_vmax_bf |
9807 | 0 | 0U, // V6_vmax_hf |
9808 | 0 | 0U, // V6_vmax_sf |
9809 | 0 | 0U, // V6_vmaxb |
9810 | 0 | 0U, // V6_vmaxh |
9811 | 0 | 0U, // V6_vmaxub |
9812 | 0 | 0U, // V6_vmaxuh |
9813 | 0 | 0U, // V6_vmaxw |
9814 | 0 | 0U, // V6_vmin_bf |
9815 | 0 | 0U, // V6_vmin_hf |
9816 | 0 | 0U, // V6_vmin_sf |
9817 | 0 | 0U, // V6_vminb |
9818 | 0 | 0U, // V6_vminh |
9819 | 0 | 0U, // V6_vminub |
9820 | 0 | 0U, // V6_vminuh |
9821 | 0 | 0U, // V6_vminw |
9822 | 0 | 0U, // V6_vmpabus |
9823 | 0 | 0U, // V6_vmpabus_acc |
9824 | 0 | 0U, // V6_vmpabusv |
9825 | 0 | 0U, // V6_vmpabuu |
9826 | 0 | 0U, // V6_vmpabuu_acc |
9827 | 0 | 0U, // V6_vmpabuuv |
9828 | 0 | 0U, // V6_vmpahb |
9829 | 0 | 0U, // V6_vmpahb_acc |
9830 | 0 | 1U, // V6_vmpahhsat |
9831 | 0 | 0U, // V6_vmpauhb |
9832 | 0 | 0U, // V6_vmpauhb_acc |
9833 | 0 | 1U, // V6_vmpauhuhsat |
9834 | 0 | 0U, // V6_vmpsuhuhsat |
9835 | 0 | 0U, // V6_vmpy_hf_hf |
9836 | 0 | 0U, // V6_vmpy_hf_hf_acc |
9837 | 0 | 0U, // V6_vmpy_qf16 |
9838 | 0 | 0U, // V6_vmpy_qf16_hf |
9839 | 0 | 0U, // V6_vmpy_qf16_mix_hf |
9840 | 0 | 0U, // V6_vmpy_qf32 |
9841 | 0 | 0U, // V6_vmpy_qf32_hf |
9842 | 0 | 0U, // V6_vmpy_qf32_mix_hf |
9843 | 0 | 0U, // V6_vmpy_qf32_qf16 |
9844 | 0 | 0U, // V6_vmpy_qf32_sf |
9845 | 0 | 0U, // V6_vmpy_sf_bf |
9846 | 0 | 0U, // V6_vmpy_sf_bf_acc |
9847 | 0 | 0U, // V6_vmpy_sf_hf |
9848 | 0 | 0U, // V6_vmpy_sf_hf_acc |
9849 | 0 | 0U, // V6_vmpy_sf_sf |
9850 | 0 | 0U, // V6_vmpybus |
9851 | 0 | 0U, // V6_vmpybus_acc |
9852 | 0 | 0U, // V6_vmpybusv |
9853 | 0 | 0U, // V6_vmpybusv_acc |
9854 | 0 | 0U, // V6_vmpybv |
9855 | 0 | 0U, // V6_vmpybv_acc |
9856 | 0 | 0U, // V6_vmpyewuh |
9857 | 0 | 0U, // V6_vmpyewuh_64 |
9858 | 0 | 0U, // V6_vmpyh |
9859 | 0 | 0U, // V6_vmpyh_acc |
9860 | 0 | 0U, // V6_vmpyhsat_acc |
9861 | 0 | 0U, // V6_vmpyhsrs |
9862 | 0 | 0U, // V6_vmpyhss |
9863 | 0 | 0U, // V6_vmpyhus |
9864 | 0 | 0U, // V6_vmpyhus_acc |
9865 | 0 | 0U, // V6_vmpyhv |
9866 | 0 | 0U, // V6_vmpyhv_acc |
9867 | 0 | 0U, // V6_vmpyhvsrs |
9868 | 0 | 0U, // V6_vmpyieoh |
9869 | 0 | 0U, // V6_vmpyiewh_acc |
9870 | 0 | 0U, // V6_vmpyiewuh |
9871 | 0 | 0U, // V6_vmpyiewuh_acc |
9872 | 0 | 0U, // V6_vmpyih |
9873 | 0 | 0U, // V6_vmpyih_acc |
9874 | 0 | 0U, // V6_vmpyihb |
9875 | 0 | 0U, // V6_vmpyihb_acc |
9876 | 0 | 0U, // V6_vmpyiowh |
9877 | 0 | 0U, // V6_vmpyiwb |
9878 | 0 | 0U, // V6_vmpyiwb_acc |
9879 | 0 | 0U, // V6_vmpyiwh |
9880 | 0 | 0U, // V6_vmpyiwh_acc |
9881 | 0 | 0U, // V6_vmpyiwub |
9882 | 0 | 0U, // V6_vmpyiwub_acc |
9883 | 0 | 0U, // V6_vmpyowh |
9884 | 0 | 0U, // V6_vmpyowh_64_acc |
9885 | 0 | 0U, // V6_vmpyowh_rnd |
9886 | 0 | 0U, // V6_vmpyowh_rnd_sacc |
9887 | 0 | 0U, // V6_vmpyowh_sacc |
9888 | 0 | 0U, // V6_vmpyub |
9889 | 0 | 0U, // V6_vmpyub_acc |
9890 | 0 | 0U, // V6_vmpyubv |
9891 | 0 | 0U, // V6_vmpyubv_acc |
9892 | 0 | 0U, // V6_vmpyuh |
9893 | 0 | 0U, // V6_vmpyuh_acc |
9894 | 0 | 0U, // V6_vmpyuhe |
9895 | 0 | 0U, // V6_vmpyuhe_acc |
9896 | 0 | 0U, // V6_vmpyuhv |
9897 | 0 | 0U, // V6_vmpyuhv_acc |
9898 | 0 | 0U, // V6_vmpyuhvs |
9899 | 0 | 0U, // V6_vmux |
9900 | 0 | 0U, // V6_vnavgb |
9901 | 0 | 0U, // V6_vnavgh |
9902 | 0 | 0U, // V6_vnavgub |
9903 | 0 | 0U, // V6_vnavgw |
9904 | 0 | 0U, // V6_vnccombine |
9905 | 0 | 0U, // V6_vncmov |
9906 | 0 | 0U, // V6_vnormamth |
9907 | 0 | 0U, // V6_vnormamtw |
9908 | 0 | 0U, // V6_vnot |
9909 | 0 | 0U, // V6_vor |
9910 | 0 | 0U, // V6_vpackeb |
9911 | 0 | 0U, // V6_vpackeh |
9912 | 0 | 0U, // V6_vpackhb_sat |
9913 | 0 | 0U, // V6_vpackhub_sat |
9914 | 0 | 0U, // V6_vpackob |
9915 | 0 | 0U, // V6_vpackoh |
9916 | 0 | 0U, // V6_vpackwh_sat |
9917 | 0 | 0U, // V6_vpackwuh_sat |
9918 | 0 | 0U, // V6_vpopcounth |
9919 | 0 | 0U, // V6_vprefixqb |
9920 | 0 | 0U, // V6_vprefixqh |
9921 | 0 | 0U, // V6_vprefixqw |
9922 | 0 | 0U, // V6_vrdelta |
9923 | 0 | 0U, // V6_vrmpybub_rtt |
9924 | 0 | 0U, // V6_vrmpybub_rtt_acc |
9925 | 0 | 0U, // V6_vrmpybus |
9926 | 0 | 0U, // V6_vrmpybus_acc |
9927 | 0 | 8U, // V6_vrmpybusi |
9928 | 0 | 0U, // V6_vrmpybusi_acc |
9929 | 0 | 0U, // V6_vrmpybusv |
9930 | 0 | 0U, // V6_vrmpybusv_acc |
9931 | 0 | 0U, // V6_vrmpybv |
9932 | 0 | 0U, // V6_vrmpybv_acc |
9933 | 0 | 0U, // V6_vrmpyub |
9934 | 0 | 0U, // V6_vrmpyub_acc |
9935 | 0 | 0U, // V6_vrmpyub_rtt |
9936 | 0 | 0U, // V6_vrmpyub_rtt_acc |
9937 | 0 | 0U, // V6_vrmpyubi |
9938 | 0 | 0U, // V6_vrmpyubi_acc |
9939 | 0 | 0U, // V6_vrmpyubv |
9940 | 0 | 0U, // V6_vrmpyubv_acc |
9941 | 0 | 1U, // V6_vrmpyzbb_rt |
9942 | 0 | 1U, // V6_vrmpyzbb_rt_acc |
9943 | 0 | 1U, // V6_vrmpyzbb_rx |
9944 | 0 | 1U, // V6_vrmpyzbb_rx_acc |
9945 | 0 | 1U, // V6_vrmpyzbub_rt |
9946 | 0 | 1U, // V6_vrmpyzbub_rt_acc |
9947 | 0 | 1U, // V6_vrmpyzbub_rx |
9948 | 0 | 1U, // V6_vrmpyzbub_rx_acc |
9949 | 0 | 1U, // V6_vrmpyzcb_rt |
9950 | 0 | 1U, // V6_vrmpyzcb_rt_acc |
9951 | 0 | 1U, // V6_vrmpyzcb_rx |
9952 | 0 | 1U, // V6_vrmpyzcb_rx_acc |
9953 | 0 | 1U, // V6_vrmpyzcbs_rt |
9954 | 0 | 1U, // V6_vrmpyzcbs_rt_acc |
9955 | 0 | 1U, // V6_vrmpyzcbs_rx |
9956 | 0 | 1U, // V6_vrmpyzcbs_rx_acc |
9957 | 0 | 1U, // V6_vrmpyznb_rt |
9958 | 0 | 1U, // V6_vrmpyznb_rt_acc |
9959 | 0 | 1U, // V6_vrmpyznb_rx |
9960 | 0 | 1U, // V6_vrmpyznb_rx_acc |
9961 | 0 | 0U, // V6_vror |
9962 | 0 | 0U, // V6_vrotr |
9963 | 0 | 0U, // V6_vroundhb |
9964 | 0 | 0U, // V6_vroundhub |
9965 | 0 | 0U, // V6_vrounduhub |
9966 | 0 | 0U, // V6_vrounduwuh |
9967 | 0 | 0U, // V6_vroundwh |
9968 | 0 | 0U, // V6_vroundwuh |
9969 | 0 | 0U, // V6_vrsadubi |
9970 | 0 | 0U, // V6_vrsadubi_acc |
9971 | 0 | 0U, // V6_vsatdw |
9972 | 0 | 0U, // V6_vsathub |
9973 | 0 | 0U, // V6_vsatuwuh |
9974 | 0 | 0U, // V6_vsatwh |
9975 | 0 | 0U, // V6_vsb |
9976 | 0 | 1U, // V6_vscattermh |
9977 | 0 | 2U, // V6_vscattermh_add |
9978 | 0 | 0U, // V6_vscattermhq |
9979 | 0 | 2U, // V6_vscattermhw |
9980 | 0 | 2U, // V6_vscattermhw_add |
9981 | 0 | 0U, // V6_vscattermhwq |
9982 | 0 | 2U, // V6_vscattermw |
9983 | 0 | 2U, // V6_vscattermw_add |
9984 | 0 | 0U, // V6_vscattermwq |
9985 | 0 | 0U, // V6_vsh |
9986 | 0 | 0U, // V6_vshufeh |
9987 | 0 | 0U, // V6_vshuff |
9988 | 0 | 0U, // V6_vshuffb |
9989 | 0 | 0U, // V6_vshuffeb |
9990 | 0 | 0U, // V6_vshuffh |
9991 | 0 | 0U, // V6_vshuffob |
9992 | 0 | 0U, // V6_vshuffvdd |
9993 | 0 | 0U, // V6_vshufoeb |
9994 | 0 | 0U, // V6_vshufoeh |
9995 | 0 | 0U, // V6_vshufoh |
9996 | 0 | 0U, // V6_vsub_hf |
9997 | 0 | 0U, // V6_vsub_hf_hf |
9998 | 0 | 0U, // V6_vsub_qf16 |
9999 | 0 | 0U, // V6_vsub_qf16_mix |
10000 | 0 | 0U, // V6_vsub_qf32 |
10001 | 0 | 0U, // V6_vsub_qf32_mix |
10002 | 0 | 0U, // V6_vsub_sf |
10003 | 0 | 0U, // V6_vsub_sf_bf |
10004 | 0 | 0U, // V6_vsub_sf_hf |
10005 | 0 | 0U, // V6_vsub_sf_sf |
10006 | 0 | 0U, // V6_vsubb |
10007 | 0 | 0U, // V6_vsubb_dv |
10008 | 0 | 0U, // V6_vsubbnq |
10009 | 0 | 0U, // V6_vsubbq |
10010 | 0 | 0U, // V6_vsubbsat |
10011 | 0 | 0U, // V6_vsubbsat_dv |
10012 | 0 | 25U, // V6_vsubcarry |
10013 | 0 | 0U, // V6_vsubcarryo |
10014 | 0 | 0U, // V6_vsubh |
10015 | 0 | 0U, // V6_vsubh_dv |
10016 | 0 | 0U, // V6_vsubhnq |
10017 | 0 | 0U, // V6_vsubhq |
10018 | 0 | 0U, // V6_vsubhsat |
10019 | 0 | 0U, // V6_vsubhsat_dv |
10020 | 0 | 0U, // V6_vsubhw |
10021 | 0 | 0U, // V6_vsububh |
10022 | 0 | 0U, // V6_vsububsat |
10023 | 0 | 0U, // V6_vsububsat_dv |
10024 | 0 | 0U, // V6_vsubububb_sat |
10025 | 0 | 0U, // V6_vsubuhsat |
10026 | 0 | 0U, // V6_vsubuhsat_dv |
10027 | 0 | 0U, // V6_vsubuhw |
10028 | 0 | 0U, // V6_vsubuwsat |
10029 | 0 | 0U, // V6_vsubuwsat_dv |
10030 | 0 | 1U, // V6_vsubw |
10031 | 0 | 1U, // V6_vsubw_dv |
10032 | 0 | 0U, // V6_vsubwnq |
10033 | 0 | 0U, // V6_vsubwq |
10034 | 0 | 1U, // V6_vsubwsat |
10035 | 0 | 1U, // V6_vsubwsat_dv |
10036 | 0 | 0U, // V6_vswap |
10037 | 0 | 0U, // V6_vtmpyb |
10038 | 0 | 0U, // V6_vtmpyb_acc |
10039 | 0 | 0U, // V6_vtmpybus |
10040 | 0 | 0U, // V6_vtmpybus_acc |
10041 | 0 | 0U, // V6_vtmpyhb |
10042 | 0 | 0U, // V6_vtmpyhb_acc |
10043 | 0 | 0U, // V6_vunpackb |
10044 | 0 | 0U, // V6_vunpackh |
10045 | 0 | 0U, // V6_vunpackob |
10046 | 0 | 0U, // V6_vunpackoh |
10047 | 0 | 0U, // V6_vunpackub |
10048 | 0 | 0U, // V6_vunpackuh |
10049 | 0 | 0U, // V6_vwhist128 |
10050 | 0 | 0U, // V6_vwhist128m |
10051 | 0 | 0U, // V6_vwhist128q |
10052 | 0 | 0U, // V6_vwhist128qm |
10053 | 0 | 0U, // V6_vwhist256 |
10054 | 0 | 0U, // V6_vwhist256_sat |
10055 | 0 | 0U, // V6_vwhist256q |
10056 | 0 | 0U, // V6_vwhist256q_sat |
10057 | 0 | 0U, // V6_vxor |
10058 | 0 | 0U, // V6_vzb |
10059 | 0 | 0U, // V6_vzh |
10060 | 0 | 0U, // V6_zLd_ai |
10061 | 0 | 0U, // V6_zLd_pi |
10062 | 0 | 0U, // V6_zLd_ppu |
10063 | 0 | 0U, // V6_zLd_pred_ai |
10064 | 0 | 0U, // V6_zLd_pred_pi |
10065 | 0 | 0U, // V6_zLd_pred_ppu |
10066 | 0 | 0U, // V6_zextract |
10067 | 0 | 0U, // Y2_barrier |
10068 | 0 | 0U, // Y2_break |
10069 | 0 | 0U, // Y2_ciad |
10070 | 0 | 0U, // Y2_crswap0 |
10071 | 0 | 0U, // Y2_cswi |
10072 | 0 | 0U, // Y2_dccleana |
10073 | 0 | 0U, // Y2_dccleanidx |
10074 | 0 | 0U, // Y2_dccleaninva |
10075 | 0 | 0U, // Y2_dccleaninvidx |
10076 | 0 | 0U, // Y2_dcfetchbo |
10077 | 0 | 0U, // Y2_dcinva |
10078 | 0 | 0U, // Y2_dcinvidx |
10079 | 0 | 0U, // Y2_dckill |
10080 | 0 | 0U, // Y2_dctagr |
10081 | 0 | 0U, // Y2_dctagw |
10082 | 0 | 0U, // Y2_dczeroa |
10083 | 0 | 0U, // Y2_getimask |
10084 | 0 | 0U, // Y2_iassignr |
10085 | 0 | 0U, // Y2_iassignw |
10086 | 0 | 0U, // Y2_icdatar |
10087 | 0 | 0U, // Y2_icdataw |
10088 | 0 | 0U, // Y2_icinva |
10089 | 0 | 0U, // Y2_icinvidx |
10090 | 0 | 0U, // Y2_ickill |
10091 | 0 | 0U, // Y2_ictagr |
10092 | 0 | 0U, // Y2_ictagw |
10093 | 0 | 0U, // Y2_isync |
10094 | 0 | 0U, // Y2_k0lock |
10095 | 0 | 0U, // Y2_k0unlock |
10096 | 0 | 0U, // Y2_l2cleaninvidx |
10097 | 0 | 0U, // Y2_l2kill |
10098 | 0 | 0U, // Y2_resume |
10099 | 0 | 0U, // Y2_setimask |
10100 | 0 | 0U, // Y2_setprio |
10101 | 0 | 0U, // Y2_start |
10102 | 0 | 0U, // Y2_stop |
10103 | 0 | 0U, // Y2_swi |
10104 | 0 | 0U, // Y2_syncht |
10105 | 0 | 0U, // Y2_tfrscrr |
10106 | 0 | 0U, // Y2_tfrsrcr |
10107 | 0 | 0U, // Y2_tlblock |
10108 | 0 | 0U, // Y2_tlbp |
10109 | 0 | 0U, // Y2_tlbr |
10110 | 0 | 0U, // Y2_tlbunlock |
10111 | 0 | 0U, // Y2_tlbw |
10112 | 0 | 0U, // Y2_wait |
10113 | 0 | 0U, // Y4_crswap1 |
10114 | 0 | 0U, // Y4_crswap10 |
10115 | 0 | 0U, // Y4_l2fetch |
10116 | 0 | 0U, // Y4_l2tagr |
10117 | 0 | 0U, // Y4_l2tagw |
10118 | 0 | 0U, // Y4_nmi |
10119 | 0 | 0U, // Y4_siad |
10120 | 0 | 0U, // Y4_tfrscpp |
10121 | 0 | 0U, // Y4_tfrspcp |
10122 | 0 | 0U, // Y4_trace |
10123 | 0 | 0U, // Y5_ctlbw |
10124 | 0 | 0U, // Y5_l2cleanidx |
10125 | 0 | 0U, // Y5_l2fetch |
10126 | 0 | 0U, // Y5_l2gclean |
10127 | 0 | 0U, // Y5_l2gcleaninv |
10128 | 0 | 0U, // Y5_l2gunlock |
10129 | 0 | 0U, // Y5_l2invidx |
10130 | 0 | 0U, // Y5_l2locka |
10131 | 0 | 0U, // Y5_l2unlocka |
10132 | 0 | 0U, // Y5_tlbasidi |
10133 | 0 | 0U, // Y5_tlboc |
10134 | 0 | 0U, // Y6_diag |
10135 | 0 | 0U, // Y6_diag0 |
10136 | 0 | 0U, // Y6_diag1 |
10137 | 0 | 0U, // Y6_dmlink |
10138 | 0 | 0U, // Y6_dmpause |
10139 | 0 | 0U, // Y6_dmpoll |
10140 | 0 | 0U, // Y6_dmresume |
10141 | 0 | 0U, // Y6_dmstart |
10142 | 0 | 0U, // Y6_dmwait |
10143 | 0 | 0U, // Y6_l2gcleaninvpa |
10144 | 0 | 0U, // Y6_l2gcleanpa |
10145 | 0 | 2U, // dep_A2_addsat |
10146 | 0 | 2U, // dep_A2_subsat |
10147 | 0 | 0U, // dep_S2_packhl |
10148 | 0 | 0U, // invalid_decode |
10149 | 0 | }; |
10150 | | |
10151 | | // Emit the opcode for the instruction. |
10152 | 0 | uint64_t Bits = 0; |
10153 | 0 | Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0; |
10154 | 0 | Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32; |
10155 | 0 | Bits |= (uint64_t)OpInfo2[MI->getOpcode()] << 48; |
10156 | 0 | if (Bits == 0) |
10157 | 0 | return {nullptr, Bits}; |
10158 | 0 | return {AsmStrs+(Bits & 2047)-1, Bits}; |
10159 | |
|
10160 | 0 | } |
10161 | | /// printInstruction - This method is automatically generated by tablegen |
10162 | | /// from the instruction set description. |
10163 | | LLVM_NO_PROFILE_INSTRUMENT_FUNCTION |
10164 | | void HexagonInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O) { |
10165 | | O << "\t"; |
10166 | | |
10167 | | auto MnemonicInfo = getMnemonic(MI); |
10168 | | |
10169 | | O << MnemonicInfo.first; |
10170 | | |
10171 | | uint64_t Bits = MnemonicInfo.second; |
10172 | | assert(Bits != 0 && "Cannot print this instruction."); |
10173 | | |
10174 | | // Fragment 0 encoded into 3 bits for 5 unique commands. |
10175 | | switch ((Bits >> 11) & 7) { |
10176 | | default: llvm_unreachable("Invalid command number."); |
10177 | | case 0: |
10178 | | // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... |
10179 | | return; |
10180 | | break; |
10181 | | case 1: |
10182 | | // A2_addsp, A2_iconst, A2_neg, A2_not, A2_tfrp, A2_tfrpi, A2_vaddb_map, ... |
10183 | | printOperand(MI, 0, O); |
10184 | | break; |
10185 | | case 2: |
10186 | | // A2_tfrf, A2_tfrfnew, A2_tfrpf, A2_tfrpfnew, A2_tfrpt, A2_tfrptnew, A2_... |
10187 | | printOperand(MI, 1, O); |
10188 | | break; |
10189 | | case 3: |
10190 | | // CALLProfile, J2_call, J2_jump, J2_loop0i, J2_loop0iext, J2_loop0r, J2_... |
10191 | | printBrtarget(MI, 0, O); |
10192 | | break; |
10193 | | case 4: |
10194 | | // L2_ploadrbf_pi, L2_ploadrbfnew_pi, L2_ploadrbt_pi, L2_ploadrbtnew_pi, ... |
10195 | | printOperand(MI, 2, O); |
10196 | | break; |
10197 | | } |
10198 | | |
10199 | | |
10200 | | // Fragment 1 encoded into 10 bits for 885 unique commands. |
10201 | | switch ((Bits >> 14) & 1023) { |
10202 | | default: llvm_unreachable("Invalid command number."); |
10203 | | case 0: |
10204 | | // A2_addsp, dup_A2_add, dup_A2_addi, A2_add, A2_addh_h16_hh, A2_addh_h16... |
10205 | | O << " = add("; |
10206 | | break; |
10207 | | case 1: |
10208 | | // A2_iconst |
10209 | | O << " = iconst(#"; |
10210 | | printOperand(MI, 1, O); |
10211 | | O << ')'; |
10212 | | return; |
10213 | | break; |
10214 | | case 2: |
10215 | | // A2_neg, A2_negp, A2_negsat |
10216 | | O << " = neg("; |
10217 | | printOperand(MI, 1, O); |
10218 | | break; |
10219 | | case 3: |
10220 | | // A2_not, A2_notp, C2_not, V6_pred_not |
10221 | | O << " = not("; |
10222 | | printOperand(MI, 1, O); |
10223 | | O << ')'; |
10224 | | return; |
10225 | | break; |
10226 | | case 4: |
10227 | | // A2_tfrf, A2_tfrpf, A2_tfrpt, A2_tfrt, L2_ploadrbf_zomap, L2_ploadrbt_z... |
10228 | | O << ") "; |
10229 | | printOperand(MI, 0, O); |
10230 | | break; |
10231 | | case 5: |
10232 | | // A2_tfrfnew, A2_tfrpfnew, A2_tfrptnew, A2_tfrtnew, L2_ploadrbfnew_zomap... |
10233 | | O << ".new) "; |
10234 | | printOperand(MI, 0, O); |
10235 | | break; |
10236 | | case 6: |
10237 | | // A2_tfrp, C2_pxfer_map, V6_vassignp, dup_A2_tfr, A2_tfr, A2_tfrcrr, A2_... |
10238 | | O << " = "; |
10239 | | printOperand(MI, 1, O); |
10240 | | break; |
10241 | | case 7: |
10242 | | // A2_tfrpi, dup_A2_tfrsi, A2_tfrsi, J4_jumpseti, SA1_seti, SA1_setin1, T... |
10243 | | O << " = #"; |
10244 | | printOperand(MI, 1, O); |
10245 | | break; |
10246 | | case 8: |
10247 | | // A2_vaddb_map, V6_vaddb_alt, V6_vaddb_dv_alt, V6_vaddbsat_alt, V6_vaddb... |
10248 | | O << " = vaddb("; |
10249 | | printOperand(MI, 1, O); |
10250 | | O << ','; |
10251 | | printOperand(MI, 2, O); |
10252 | | break; |
10253 | | case 9: |
10254 | | // A2_vsubb_map, V6_vsubb_alt, V6_vsubb_dv_alt, V6_vsubbsat_alt, V6_vsubb... |
10255 | | O << " = vsubb("; |
10256 | | printOperand(MI, 1, O); |
10257 | | O << ','; |
10258 | | printOperand(MI, 2, O); |
10259 | | break; |
10260 | | case 10: |
10261 | | // A2_zxtb, dup_A2_zxtb |
10262 | | O << " = zxtb("; |
10263 | | printOperand(MI, 1, O); |
10264 | | O << ')'; |
10265 | | return; |
10266 | | break; |
10267 | | case 11: |
10268 | | // A4_boundscheck, A4_boundscheck_hi, A4_boundscheck_lo |
10269 | | O << " = boundscheck("; |
10270 | | printOperand(MI, 1, O); |
10271 | | O << ','; |
10272 | | printOperand(MI, 2, O); |
10273 | | break; |
10274 | | case 12: |
10275 | | // C2_cmpgei |
10276 | | O << " = cmp.ge("; |
10277 | | printOperand(MI, 1, O); |
10278 | | O << ",#"; |
10279 | | printOperand(MI, 2, O); |
10280 | | O << ')'; |
10281 | | return; |
10282 | | break; |
10283 | | case 13: |
10284 | | // C2_cmpgeui |
10285 | | O << " = cmp.geu("; |
10286 | | printOperand(MI, 1, O); |
10287 | | O << ",#"; |
10288 | | printOperand(MI, 2, O); |
10289 | | O << ')'; |
10290 | | return; |
10291 | | break; |
10292 | | case 14: |
10293 | | // C2_cmplt |
10294 | | O << " = cmp.lt("; |
10295 | | printOperand(MI, 1, O); |
10296 | | O << ','; |
10297 | | printOperand(MI, 2, O); |
10298 | | O << ')'; |
10299 | | return; |
10300 | | break; |
10301 | | case 15: |
10302 | | // C2_cmpltu |
10303 | | O << " = cmp.ltu("; |
10304 | | printOperand(MI, 1, O); |
10305 | | O << ','; |
10306 | | printOperand(MI, 2, O); |
10307 | | O << ')'; |
10308 | | return; |
10309 | | break; |
10310 | | case 16: |
10311 | | // J2_jumpf_nopred_map, J2_jumpt_nopred_map |
10312 | | O << ") jump "; |
10313 | | printBrtarget(MI, 1, O); |
10314 | | return; |
10315 | | break; |
10316 | | case 17: |
10317 | | // J2_jumprf_nopred_map, J2_jumprt_nopred_map |
10318 | | O << ") jumpr "; |
10319 | | printOperand(MI, 1, O); |
10320 | | return; |
10321 | | break; |
10322 | | case 18: |
10323 | | // J2_trap1_noregmap, S6_allocframe_to_raw, V6_zld0, Y2_dcfetch, A4_ext, ... |
10324 | | O << ')'; |
10325 | | return; |
10326 | | break; |
10327 | | case 19: |
10328 | | // L2_loadalignb_zomap, L2_loadalignb_io, L2_loadalignb_pbr, L2_loadalign... |
10329 | | O << " = memb_fifo("; |
10330 | | break; |
10331 | | case 20: |
10332 | | // L2_loadalignh_zomap, L2_loadalignh_io, L2_loadalignh_pbr, L2_loadalign... |
10333 | | O << " = memh_fifo("; |
10334 | | break; |
10335 | | case 21: |
10336 | | // L2_loadbsw2_zomap, L2_loadbsw4_zomap, L2_loadbsw2_io, L2_loadbsw2_pbr,... |
10337 | | O << " = membh("; |
10338 | | printOperand(MI, 1, O); |
10339 | | break; |
10340 | | case 22: |
10341 | | // L2_loadbzw2_zomap, L2_loadbzw4_zomap, L2_loadbzw2_io, L2_loadbzw2_pbr,... |
10342 | | O << " = memubh("; |
10343 | | printOperand(MI, 1, O); |
10344 | | break; |
10345 | | case 23: |
10346 | | // L2_loadrb_zomap, dup_L2_loadrb_io, L2_loadrb_io, L2_loadrb_pbr, L2_loa... |
10347 | | O << " = memb("; |
10348 | | printOperand(MI, 1, O); |
10349 | | break; |
10350 | | case 24: |
10351 | | // L2_loadrd_zomap, dup_L2_loadrd_io, L2_loadrd_io, L2_loadrd_pbr, L2_loa... |
10352 | | O << " = memd("; |
10353 | | printOperand(MI, 1, O); |
10354 | | break; |
10355 | | case 25: |
10356 | | // L2_loadrh_zomap, dup_L2_loadrh_io, L2_loadrh_io, L2_loadrh_pbr, L2_loa... |
10357 | | O << " = memh("; |
10358 | | printOperand(MI, 1, O); |
10359 | | break; |
10360 | | case 26: |
10361 | | // L2_loadri_zomap, dup_L2_loadri_io, L2_loadri_io, L2_loadri_pbr, L2_loa... |
10362 | | O << " = memw("; |
10363 | | printOperand(MI, 1, O); |
10364 | | break; |
10365 | | case 27: |
10366 | | // L2_loadrub_zomap, dup_L2_loadrub_io, L2_loadrub_io, L2_loadrub_pbr, L2... |
10367 | | O << " = memub("; |
10368 | | printOperand(MI, 1, O); |
10369 | | break; |
10370 | | case 28: |
10371 | | // L2_loadruh_zomap, dup_L2_loadruh_io, L2_loadruh_io, L2_loadruh_pbr, L2... |
10372 | | O << " = memuh("; |
10373 | | printOperand(MI, 1, O); |
10374 | | break; |
10375 | | case 29: |
10376 | | // L4_add_memopb_zomap, L4_add_memoph_zomap, L4_add_memopw_zomap |
10377 | | O << ") += "; |
10378 | | printOperand(MI, 1, O); |
10379 | | return; |
10380 | | break; |
10381 | | case 30: |
10382 | | // L4_and_memopb_zomap, L4_and_memoph_zomap, L4_and_memopw_zomap |
10383 | | O << ") &= "; |
10384 | | printOperand(MI, 1, O); |
10385 | | return; |
10386 | | break; |
10387 | | case 31: |
10388 | | // L4_iadd_memopb_zomap, L4_iadd_memoph_zomap, L4_iadd_memopw_zomap |
10389 | | O << ") += #"; |
10390 | | printOperand(MI, 1, O); |
10391 | | return; |
10392 | | break; |
10393 | | case 32: |
10394 | | // L4_iand_memopb_zomap, L4_iand_memoph_zomap, L4_iand_memopw_zomap |
10395 | | O << ") = clrbit(#"; |
10396 | | printOperand(MI, 1, O); |
10397 | | O << ')'; |
10398 | | return; |
10399 | | break; |
10400 | | case 33: |
10401 | | // L4_ior_memopb_zomap, L4_ior_memoph_zomap, L4_ior_memopw_zomap |
10402 | | O << ") = setbit(#"; |
10403 | | printOperand(MI, 1, O); |
10404 | | O << ')'; |
10405 | | return; |
10406 | | break; |
10407 | | case 34: |
10408 | | // L4_isub_memopb_zomap, L4_isub_memoph_zomap, L4_isub_memopw_zomap |
10409 | | O << ") -= #"; |
10410 | | printOperand(MI, 1, O); |
10411 | | return; |
10412 | | break; |
10413 | | case 35: |
10414 | | // L4_or_memopb_zomap, L4_or_memoph_zomap, L4_or_memopw_zomap |
10415 | | O << ") |= "; |
10416 | | printOperand(MI, 1, O); |
10417 | | return; |
10418 | | break; |
10419 | | case 36: |
10420 | | // L4_return_map_to_raw_f, L4_return_map_to_raw_t |
10421 | | O << ") dealloc_return"; |
10422 | | return; |
10423 | | break; |
10424 | | case 37: |
10425 | | // L4_return_map_to_raw_fnew_pnt, L4_return_map_to_raw_tnew_pnt |
10426 | | O << ".new) dealloc_return:nt"; |
10427 | | return; |
10428 | | break; |
10429 | | case 38: |
10430 | | // L4_return_map_to_raw_fnew_pt, L4_return_map_to_raw_tnew_pt |
10431 | | O << ".new) dealloc_return:t"; |
10432 | | return; |
10433 | | break; |
10434 | | case 39: |
10435 | | // L4_sub_memopb_zomap, L4_sub_memoph_zomap, L4_sub_memopw_zomap |
10436 | | O << ") -= "; |
10437 | | printOperand(MI, 1, O); |
10438 | | return; |
10439 | | break; |
10440 | | case 40: |
10441 | | // M2_mpysmi, M2_mpyi |
10442 | | O << " = mpyi("; |
10443 | | printOperand(MI, 1, O); |
10444 | | break; |
10445 | | case 41: |
10446 | | // M2_mpyui |
10447 | | O << " = mpyui("; |
10448 | | printOperand(MI, 1, O); |
10449 | | O << ','; |
10450 | | printOperand(MI, 2, O); |
10451 | | O << ')'; |
10452 | | return; |
10453 | | break; |
10454 | | case 42: |
10455 | | // M2_vrcmpys_acc_s1, M2_vrcmpys_acc_s1_h, M2_vrcmpys_acc_s1_l |
10456 | | O << " += vrcmpys("; |
10457 | | printOperand(MI, 2, O); |
10458 | | O << ','; |
10459 | | printOperand(MI, 3, O); |
10460 | | break; |
10461 | | case 43: |
10462 | | // M2_vrcmpys_s1, M2_vrcmpys_s1rp, M2_vrcmpys_s1_h, M2_vrcmpys_s1_l, M2_v... |
10463 | | O << " = vrcmpys("; |
10464 | | printOperand(MI, 1, O); |
10465 | | O << ','; |
10466 | | printOperand(MI, 2, O); |
10467 | | break; |
10468 | | case 44: |
10469 | | // M7_vdmpy |
10470 | | O << " = vdmpyw("; |
10471 | | printOperand(MI, 1, O); |
10472 | | O << ','; |
10473 | | printOperand(MI, 2, O); |
10474 | | O << ')'; |
10475 | | return; |
10476 | | break; |
10477 | | case 45: |
10478 | | // M7_vdmpy_acc |
10479 | | O << " += vdmpyw("; |
10480 | | printOperand(MI, 2, O); |
10481 | | O << ','; |
10482 | | printOperand(MI, 3, O); |
10483 | | O << ')'; |
10484 | | return; |
10485 | | break; |
10486 | | case 46: |
10487 | | // PS_tailcall_r, CALLProfile, EH_RETURN_JMPR, J2_call, J2_callr, J2_call... |
10488 | | return; |
10489 | | break; |
10490 | | case 47: |
10491 | | // S2_asr_i_p_rnd_goodsyntax, S2_asr_i_r_rnd_goodsyntax |
10492 | | O << " = asrrnd("; |
10493 | | printOperand(MI, 1, O); |
10494 | | O << ",#"; |
10495 | | printOperand(MI, 2, O); |
10496 | | O << ')'; |
10497 | | return; |
10498 | | break; |
10499 | | case 48: |
10500 | | // S2_pstorerbf_zomap, S2_pstorerbnewf_zomap, S2_pstorerbnewt_zomap, S2_p... |
10501 | | O << ") memb("; |
10502 | | break; |
10503 | | case 49: |
10504 | | // S2_pstorerdf_zomap, S2_pstorerdt_zomap, S2_pstorerdf_io, S2_pstorerdf_... |
10505 | | O << ") memd("; |
10506 | | break; |
10507 | | case 50: |
10508 | | // S2_pstorerff_zomap, S2_pstorerft_zomap, S2_pstorerhf_zomap, S2_pstorer... |
10509 | | O << ") memh("; |
10510 | | break; |
10511 | | case 51: |
10512 | | // S2_pstorerif_zomap, S2_pstorerinewf_zomap, S2_pstorerinewt_zomap, S2_p... |
10513 | | O << ") memw("; |
10514 | | break; |
10515 | | case 52: |
10516 | | // S2_storerb_zomap, S2_storerbnew_zomap, S2_storerd_zomap, S2_storerf_zo... |
10517 | | O << ") = "; |
10518 | | printOperand(MI, 1, O); |
10519 | | break; |
10520 | | case 53: |
10521 | | // S2_tableidxb_goodsyntax, S2_tableidxb |
10522 | | O << " = tableidxb("; |
10523 | | printOperand(MI, 2, O); |
10524 | | O << ",#"; |
10525 | | printOperand(MI, 3, O); |
10526 | | O << ",#"; |
10527 | | printOperand(MI, 4, O); |
10528 | | break; |
10529 | | case 54: |
10530 | | // S2_tableidxd_goodsyntax, S2_tableidxd |
10531 | | O << " = tableidxd("; |
10532 | | printOperand(MI, 2, O); |
10533 | | O << ",#"; |
10534 | | printOperand(MI, 3, O); |
10535 | | O << ",#"; |
10536 | | printOperand(MI, 4, O); |
10537 | | break; |
10538 | | case 55: |
10539 | | // S2_tableidxh_goodsyntax, S2_tableidxh |
10540 | | O << " = tableidxh("; |
10541 | | printOperand(MI, 2, O); |
10542 | | O << ",#"; |
10543 | | printOperand(MI, 3, O); |
10544 | | O << ",#"; |
10545 | | printOperand(MI, 4, O); |
10546 | | break; |
10547 | | case 56: |
10548 | | // S2_tableidxw_goodsyntax, S2_tableidxw |
10549 | | O << " = tableidxw("; |
10550 | | printOperand(MI, 2, O); |
10551 | | O << ",#"; |
10552 | | printOperand(MI, 3, O); |
10553 | | O << ",#"; |
10554 | | printOperand(MI, 4, O); |
10555 | | break; |
10556 | | case 57: |
10557 | | // S4_pstorerbfnew_zomap, S4_pstorerbnewfnew_zomap, S4_pstorerbnewtnew_zo... |
10558 | | O << ".new) memb("; |
10559 | | break; |
10560 | | case 58: |
10561 | | // S4_pstorerdfnew_zomap, S4_pstorerdtnew_zomap, S2_pstorerdfnew_pi, S2_p... |
10562 | | O << ".new) memd("; |
10563 | | break; |
10564 | | case 59: |
10565 | | // S4_pstorerffnew_zomap, S4_pstorerftnew_zomap, S4_pstorerhfnew_zomap, S... |
10566 | | O << ".new) memh("; |
10567 | | break; |
10568 | | case 60: |
10569 | | // S4_pstorerifnew_zomap, S4_pstorerinewfnew_zomap, S4_pstorerinewtnew_zo... |
10570 | | O << ".new) memw("; |
10571 | | break; |
10572 | | case 61: |
10573 | | // S4_storeirb_zomap, S4_storeirh_zomap, S4_storeiri_zomap |
10574 | | O << ") = #"; |
10575 | | printOperand(MI, 1, O); |
10576 | | return; |
10577 | | break; |
10578 | | case 62: |
10579 | | // S5_asrhub_rnd_sat_goodsyntax, S5_asrhub_rnd_sat, S5_asrhub_sat |
10580 | | O << " = vasrhub("; |
10581 | | printOperand(MI, 1, O); |
10582 | | O << ",#"; |
10583 | | printOperand(MI, 2, O); |
10584 | | break; |
10585 | | case 63: |
10586 | | // S5_vasrhrnd_goodsyntax, V6_vasrh_alt, V6_vasrhv_alt, S2_asr_i_vh, S2_a... |
10587 | | O << " = vasrh("; |
10588 | | printOperand(MI, 1, O); |
10589 | | break; |
10590 | | case 64: |
10591 | | // V6_MAP_equb, V6_MAP_equh, V6_MAP_equw, V6_veqb, V6_veqh, V6_veqw |
10592 | | O << " = vcmp.eq("; |
10593 | | printOperand(MI, 1, O); |
10594 | | break; |
10595 | | case 65: |
10596 | | // V6_MAP_equb_and, V6_MAP_equh_and, V6_MAP_equw_and, V6_veqb_and, V6_veq... |
10597 | | O << " &= vcmp.eq("; |
10598 | | printOperand(MI, 2, O); |
10599 | | break; |
10600 | | case 66: |
10601 | | // V6_MAP_equb_ior, V6_MAP_equh_ior, V6_MAP_equw_ior, V6_veqb_or, V6_veqh... |
10602 | | O << " |= vcmp.eq("; |
10603 | | printOperand(MI, 2, O); |
10604 | | break; |
10605 | | case 67: |
10606 | | // V6_MAP_equb_xor, V6_MAP_equh_xor, V6_MAP_equw_xor, V6_veqb_xor, V6_veq... |
10607 | | O << " ^= vcmp.eq("; |
10608 | | printOperand(MI, 2, O); |
10609 | | break; |
10610 | | case 68: |
10611 | | // V6_dbl_ld0, V6_ld0, V6_ldnt0, V6_vL32b_ai, V6_vL32b_nt_ai, V6_vL32b_nt... |
10612 | | O << " = vmem("; |
10613 | | printOperand(MI, 1, O); |
10614 | | break; |
10615 | | case 69: |
10616 | | // V6_extractw_alt |
10617 | | O << ".w = vextract("; |
10618 | | printOperand(MI, 1, O); |
10619 | | O << ','; |
10620 | | printOperand(MI, 2, O); |
10621 | | O << ')'; |
10622 | | return; |
10623 | | break; |
10624 | | case 70: |
10625 | | // V6_hi |
10626 | | O << " = hi("; |
10627 | | printOperand(MI, 1, O); |
10628 | | O << ')'; |
10629 | | return; |
10630 | | break; |
10631 | | case 71: |
10632 | | // V6_ldu0, V6_vL32Ub_ai, V6_vL32Ub_pi, V6_vL32Ub_ppu |
10633 | | O << " = vmemu("; |
10634 | | printOperand(MI, 1, O); |
10635 | | break; |
10636 | | case 72: |
10637 | | // V6_lo |
10638 | | O << " = lo("; |
10639 | | printOperand(MI, 1, O); |
10640 | | O << ')'; |
10641 | | return; |
10642 | | break; |
10643 | | case 73: |
10644 | | // V6_stnnt0, V6_stnt0 |
10645 | | O << "):nt = "; |
10646 | | printOperand(MI, 1, O); |
10647 | | break; |
10648 | | case 74: |
10649 | | // V6_stnp0, V6_stnpnt0, V6_stnq0, V6_stnqnt0, V6_stp0, V6_stpnt0, V6_stq... |
10650 | | O << ") vmem("; |
10651 | | break; |
10652 | | case 75: |
10653 | | // V6_stunp0, V6_stup0, V6_vS32Ub_npred_ai, V6_vS32Ub_npred_pi, V6_vS32Ub... |
10654 | | O << ") vmemu("; |
10655 | | break; |
10656 | | case 76: |
10657 | | // V6_v10mpyubs10 |
10658 | | O << ".w = v10mpy("; |
10659 | | printOperand(MI, 1, O); |
10660 | | O << ".ub,"; |
10661 | | printOperand(MI, 2, O); |
10662 | | O << ".b,#"; |
10663 | | printOperand(MI, 3, O); |
10664 | | O << ')'; |
10665 | | return; |
10666 | | break; |
10667 | | case 77: |
10668 | | // V6_v10mpyubs10_vxx |
10669 | | O << ".w += v10mpy("; |
10670 | | printOperand(MI, 2, O); |
10671 | | O << ".ub,"; |
10672 | | printOperand(MI, 3, O); |
10673 | | O << ".b,#"; |
10674 | | printOperand(MI, 4, O); |
10675 | | O << ')'; |
10676 | | return; |
10677 | | break; |
10678 | | case 78: |
10679 | | // V6_v6mpyhubs10_alt, V6_v6mpyvubs10_alt, V6_v6mpyhubs10, V6_v6mpyvubs10 |
10680 | | O << ".w = v6mpy("; |
10681 | | printOperand(MI, 1, O); |
10682 | | O << ".ub,"; |
10683 | | printOperand(MI, 2, O); |
10684 | | break; |
10685 | | case 79: |
10686 | | // V6_vabsb_alt, V6_vabsb_sat_alt |
10687 | | O << " = vabsb("; |
10688 | | printOperand(MI, 1, O); |
10689 | | break; |
10690 | | case 80: |
10691 | | // V6_vabsdiffh_alt, M2_vabsdiffh |
10692 | | O << " = vabsdiffh("; |
10693 | | printOperand(MI, 1, O); |
10694 | | O << ','; |
10695 | | printOperand(MI, 2, O); |
10696 | | O << ')'; |
10697 | | return; |
10698 | | break; |
10699 | | case 81: |
10700 | | // V6_vabsdiffub_alt, M6_vabsdiffub |
10701 | | O << " = vabsdiffub("; |
10702 | | printOperand(MI, 1, O); |
10703 | | O << ','; |
10704 | | printOperand(MI, 2, O); |
10705 | | O << ')'; |
10706 | | return; |
10707 | | break; |
10708 | | case 82: |
10709 | | // V6_vabsdiffuh_alt |
10710 | | O << " = vabsdiffuh("; |
10711 | | printOperand(MI, 1, O); |
10712 | | O << ','; |
10713 | | printOperand(MI, 2, O); |
10714 | | O << ')'; |
10715 | | return; |
10716 | | break; |
10717 | | case 83: |
10718 | | // V6_vabsdiffw_alt, M2_vabsdiffw |
10719 | | O << " = vabsdiffw("; |
10720 | | printOperand(MI, 1, O); |
10721 | | O << ','; |
10722 | | printOperand(MI, 2, O); |
10723 | | O << ')'; |
10724 | | return; |
10725 | | break; |
10726 | | case 84: |
10727 | | // V6_vabsh_alt, V6_vabsh_sat_alt, A2_vabsh, A2_vabshsat |
10728 | | O << " = vabsh("; |
10729 | | printOperand(MI, 1, O); |
10730 | | break; |
10731 | | case 85: |
10732 | | // V6_vabsub_alt |
10733 | | O << ".ub = vabs("; |
10734 | | printOperand(MI, 1, O); |
10735 | | O << ".b)"; |
10736 | | return; |
10737 | | break; |
10738 | | case 86: |
10739 | | // V6_vabsuh_alt |
10740 | | O << ".uh = vabs("; |
10741 | | printOperand(MI, 1, O); |
10742 | | O << ".h)"; |
10743 | | return; |
10744 | | break; |
10745 | | case 87: |
10746 | | // V6_vabsuw_alt |
10747 | | O << ".uw = vabs("; |
10748 | | printOperand(MI, 1, O); |
10749 | | O << ".w)"; |
10750 | | return; |
10751 | | break; |
10752 | | case 88: |
10753 | | // V6_vabsw_alt, V6_vabsw_sat_alt, A2_vabsw, A2_vabswsat |
10754 | | O << " = vabsw("; |
10755 | | printOperand(MI, 1, O); |
10756 | | break; |
10757 | | case 89: |
10758 | | // V6_vaddbnq_alt, V6_vaddbq_alt, V6_vsubbnq_alt, V6_vsubbq_alt |
10759 | | O << ".b) "; |
10760 | | printOperand(MI, 0, O); |
10761 | | break; |
10762 | | case 90: |
10763 | | // V6_vaddh_alt, V6_vaddh_dv_alt, V6_vaddhsat_alt, V6_vaddhsat_dv_alt, V6... |
10764 | | O << " = vaddh("; |
10765 | | printOperand(MI, 1, O); |
10766 | | O << ','; |
10767 | | printOperand(MI, 2, O); |
10768 | | break; |
10769 | | case 91: |
10770 | | // V6_vaddhnq_alt, V6_vaddhq_alt, V6_vsubhnq_alt, V6_vsubhq_alt |
10771 | | O << ".h) "; |
10772 | | printOperand(MI, 0, O); |
10773 | | break; |
10774 | | case 92: |
10775 | | // V6_vaddhw_acc_alt |
10776 | | O << " += vaddh("; |
10777 | | printOperand(MI, 2, O); |
10778 | | O << ','; |
10779 | | printOperand(MI, 3, O); |
10780 | | O << ')'; |
10781 | | return; |
10782 | | break; |
10783 | | case 93: |
10784 | | // V6_vaddubh_acc_alt |
10785 | | O << " += vaddub("; |
10786 | | printOperand(MI, 2, O); |
10787 | | O << ','; |
10788 | | printOperand(MI, 3, O); |
10789 | | O << ')'; |
10790 | | return; |
10791 | | break; |
10792 | | case 94: |
10793 | | // V6_vaddubh_alt, V6_vaddubsat_alt, V6_vaddubsat_dv_alt, A2_vaddub, A2_v... |
10794 | | O << " = vaddub("; |
10795 | | printOperand(MI, 1, O); |
10796 | | O << ','; |
10797 | | printOperand(MI, 2, O); |
10798 | | break; |
10799 | | case 95: |
10800 | | // V6_vadduhsat_alt, V6_vadduhsat_dv_alt, V6_vadduhw_alt, A2_svadduhs, A2... |
10801 | | O << " = vadduh("; |
10802 | | printOperand(MI, 1, O); |
10803 | | O << ','; |
10804 | | printOperand(MI, 2, O); |
10805 | | break; |
10806 | | case 96: |
10807 | | // V6_vadduhw_acc_alt |
10808 | | O << " += vadduh("; |
10809 | | printOperand(MI, 2, O); |
10810 | | O << ','; |
10811 | | printOperand(MI, 3, O); |
10812 | | O << ')'; |
10813 | | return; |
10814 | | break; |
10815 | | case 97: |
10816 | | // V6_vadduwsat_alt, V6_vadduwsat_dv_alt |
10817 | | O << " = vadduw("; |
10818 | | printOperand(MI, 1, O); |
10819 | | O << ','; |
10820 | | printOperand(MI, 2, O); |
10821 | | O << "):sat"; |
10822 | | return; |
10823 | | break; |
10824 | | case 98: |
10825 | | // V6_vaddw_alt, V6_vaddw_dv_alt, V6_vaddwsat_alt, V6_vaddwsat_dv_alt, A2... |
10826 | | O << " = vaddw("; |
10827 | | printOperand(MI, 1, O); |
10828 | | O << ','; |
10829 | | printOperand(MI, 2, O); |
10830 | | break; |
10831 | | case 99: |
10832 | | // V6_vaddwnq_alt, V6_vaddwq_alt, V6_vsubwnq_alt, V6_vsubwq_alt |
10833 | | O << ".w) "; |
10834 | | printOperand(MI, 0, O); |
10835 | | break; |
10836 | | case 100: |
10837 | | // V6_vandnqrt_acc_alt |
10838 | | O << ".ub |= vand(!"; |
10839 | | printOperand(MI, 2, O); |
10840 | | O << ".ub,"; |
10841 | | printOperand(MI, 3, O); |
10842 | | O << ".ub)"; |
10843 | | return; |
10844 | | break; |
10845 | | case 101: |
10846 | | // V6_vandnqrt_alt |
10847 | | O << ".ub = vand(!"; |
10848 | | printOperand(MI, 1, O); |
10849 | | O << ".ub,"; |
10850 | | printOperand(MI, 2, O); |
10851 | | O << ".ub)"; |
10852 | | return; |
10853 | | break; |
10854 | | case 102: |
10855 | | // V6_vandqrt_acc_alt, V6_vandvrt_acc_alt |
10856 | | O << ".ub |= vand("; |
10857 | | printOperand(MI, 2, O); |
10858 | | O << ".ub,"; |
10859 | | printOperand(MI, 3, O); |
10860 | | O << ".ub)"; |
10861 | | return; |
10862 | | break; |
10863 | | case 103: |
10864 | | // V6_vandqrt_alt, V6_vandvrt_alt |
10865 | | O << ".ub = vand("; |
10866 | | printOperand(MI, 1, O); |
10867 | | O << ".ub,"; |
10868 | | printOperand(MI, 2, O); |
10869 | | O << ".ub)"; |
10870 | | return; |
10871 | | break; |
10872 | | case 104: |
10873 | | // V6_vaslh_acc_alt |
10874 | | O << " += vaslh("; |
10875 | | printOperand(MI, 2, O); |
10876 | | O << ','; |
10877 | | printOperand(MI, 3, O); |
10878 | | O << ')'; |
10879 | | return; |
10880 | | break; |
10881 | | case 105: |
10882 | | // V6_vaslh_alt, V6_vaslhv_alt, S2_asl_i_vh, S2_asl_r_vh |
10883 | | O << " = vaslh("; |
10884 | | printOperand(MI, 1, O); |
10885 | | break; |
10886 | | case 106: |
10887 | | // V6_vaslw_acc_alt |
10888 | | O << " += vaslw("; |
10889 | | printOperand(MI, 2, O); |
10890 | | O << ','; |
10891 | | printOperand(MI, 3, O); |
10892 | | O << ')'; |
10893 | | return; |
10894 | | break; |
10895 | | case 107: |
10896 | | // V6_vaslw_alt, V6_vaslwv_alt, S2_asl_i_vw, S2_asl_r_vw |
10897 | | O << " = vaslw("; |
10898 | | printOperand(MI, 1, O); |
10899 | | break; |
10900 | | case 108: |
10901 | | // V6_vasr_into_alt |
10902 | | O << " = vasrinto("; |
10903 | | printOperand(MI, 2, O); |
10904 | | O << ','; |
10905 | | printOperand(MI, 3, O); |
10906 | | O << ')'; |
10907 | | return; |
10908 | | break; |
10909 | | case 109: |
10910 | | // V6_vasrh_acc_alt |
10911 | | O << " += vasrh("; |
10912 | | printOperand(MI, 2, O); |
10913 | | O << ','; |
10914 | | printOperand(MI, 3, O); |
10915 | | O << ')'; |
10916 | | return; |
10917 | | break; |
10918 | | case 110: |
10919 | | // V6_vasrw_acc_alt |
10920 | | O << " += vasrw("; |
10921 | | printOperand(MI, 2, O); |
10922 | | O << ','; |
10923 | | printOperand(MI, 3, O); |
10924 | | O << ')'; |
10925 | | return; |
10926 | | break; |
10927 | | case 111: |
10928 | | // V6_vasrw_alt, V6_vasrwv_alt, S2_asr_i_svw_trun, S2_asr_i_vw, S2_asr_r_... |
10929 | | O << " = vasrw("; |
10930 | | printOperand(MI, 1, O); |
10931 | | break; |
10932 | | case 112: |
10933 | | // V6_vavgb_alt, V6_vavgbrnd_alt |
10934 | | O << " = vavgb("; |
10935 | | printOperand(MI, 1, O); |
10936 | | O << ','; |
10937 | | printOperand(MI, 2, O); |
10938 | | break; |
10939 | | case 113: |
10940 | | // V6_vavgh_alt, V6_vavghrnd_alt, A2_svavgh, A2_svavghs, A2_vavgh, A2_vav... |
10941 | | O << " = vavgh("; |
10942 | | printOperand(MI, 1, O); |
10943 | | O << ','; |
10944 | | printOperand(MI, 2, O); |
10945 | | break; |
10946 | | case 114: |
10947 | | // V6_vavgub_alt, V6_vavgubrnd_alt, A2_vavgub, A2_vavgubr |
10948 | | O << " = vavgub("; |
10949 | | printOperand(MI, 1, O); |
10950 | | O << ','; |
10951 | | printOperand(MI, 2, O); |
10952 | | break; |
10953 | | case 115: |
10954 | | // V6_vavguh_alt, V6_vavguhrnd_alt, A2_vavguh, A2_vavguhr |
10955 | | O << " = vavguh("; |
10956 | | printOperand(MI, 1, O); |
10957 | | O << ','; |
10958 | | printOperand(MI, 2, O); |
10959 | | break; |
10960 | | case 116: |
10961 | | // V6_vavguw_alt, V6_vavguwrnd_alt, A2_vavguw, A2_vavguwr |
10962 | | O << " = vavguw("; |
10963 | | printOperand(MI, 1, O); |
10964 | | O << ','; |
10965 | | printOperand(MI, 2, O); |
10966 | | break; |
10967 | | case 117: |
10968 | | // V6_vavgw_alt, V6_vavgwrnd_alt, A2_vavgw, A2_vavgwcr, A2_vavgwr |
10969 | | O << " = vavgw("; |
10970 | | printOperand(MI, 1, O); |
10971 | | O << ','; |
10972 | | printOperand(MI, 2, O); |
10973 | | break; |
10974 | | case 118: |
10975 | | // V6_vcl0h_alt |
10976 | | O << " = vcl0h("; |
10977 | | printOperand(MI, 1, O); |
10978 | | O << ')'; |
10979 | | return; |
10980 | | break; |
10981 | | case 119: |
10982 | | // V6_vcl0w_alt |
10983 | | O << " = vcl0w("; |
10984 | | printOperand(MI, 1, O); |
10985 | | O << ')'; |
10986 | | return; |
10987 | | break; |
10988 | | case 120: |
10989 | | // V6_vd0, V6_vdd0, SA1_clrf, SA1_clrfnew, SA1_clrt, SA1_clrtnew |
10990 | | O << " = #0"; |
10991 | | return; |
10992 | | break; |
10993 | | case 121: |
10994 | | // V6_vdealb4w_alt |
10995 | | O << " = vdealb4w("; |
10996 | | printOperand(MI, 1, O); |
10997 | | O << ','; |
10998 | | printOperand(MI, 2, O); |
10999 | | O << ')'; |
11000 | | return; |
11001 | | break; |
11002 | | case 122: |
11003 | | // V6_vdealb_alt |
11004 | | O << " = vdealb("; |
11005 | | printOperand(MI, 1, O); |
11006 | | O << ')'; |
11007 | | return; |
11008 | | break; |
11009 | | case 123: |
11010 | | // V6_vdealh_alt |
11011 | | O << " = vdealh("; |
11012 | | printOperand(MI, 1, O); |
11013 | | O << ')'; |
11014 | | return; |
11015 | | break; |
11016 | | case 124: |
11017 | | // V6_vdmpybus_acc_alt, V6_vdmpybus_dv_acc_alt |
11018 | | O << " += vdmpybus("; |
11019 | | printOperand(MI, 2, O); |
11020 | | O << ','; |
11021 | | printOperand(MI, 3, O); |
11022 | | O << ')'; |
11023 | | return; |
11024 | | break; |
11025 | | case 125: |
11026 | | // V6_vdmpybus_alt, V6_vdmpybus_dv_alt |
11027 | | O << " = vdmpybus("; |
11028 | | printOperand(MI, 1, O); |
11029 | | O << ','; |
11030 | | printOperand(MI, 2, O); |
11031 | | O << ')'; |
11032 | | return; |
11033 | | break; |
11034 | | case 126: |
11035 | | // V6_vdmpyhb_acc_alt, V6_vdmpyhb_dv_acc_alt |
11036 | | O << " += vdmpyhb("; |
11037 | | printOperand(MI, 2, O); |
11038 | | O << ','; |
11039 | | printOperand(MI, 3, O); |
11040 | | O << ')'; |
11041 | | return; |
11042 | | break; |
11043 | | case 127: |
11044 | | // V6_vdmpyhb_alt, V6_vdmpyhb_dv_alt |
11045 | | O << " = vdmpyhb("; |
11046 | | printOperand(MI, 1, O); |
11047 | | O << ','; |
11048 | | printOperand(MI, 2, O); |
11049 | | O << ')'; |
11050 | | return; |
11051 | | break; |
11052 | | case 128: |
11053 | | // V6_vdmpyhisat_acc_alt, V6_vdmpyhsat_acc_alt, V6_vdmpyhvsat_acc_alt |
11054 | | O << " += vdmpyh("; |
11055 | | printOperand(MI, 2, O); |
11056 | | O << ','; |
11057 | | printOperand(MI, 3, O); |
11058 | | O << "):sat"; |
11059 | | return; |
11060 | | break; |
11061 | | case 129: |
11062 | | // V6_vdmpyhisat_alt, V6_vdmpyhsat_alt, V6_vdmpyhvsat_alt |
11063 | | O << " = vdmpyh("; |
11064 | | printOperand(MI, 1, O); |
11065 | | O << ','; |
11066 | | printOperand(MI, 2, O); |
11067 | | O << "):sat"; |
11068 | | return; |
11069 | | break; |
11070 | | case 130: |
11071 | | // V6_vdmpyhsuisat_acc_alt, V6_vdmpyhsusat_acc_alt |
11072 | | O << " += vdmpyhsu("; |
11073 | | printOperand(MI, 2, O); |
11074 | | O << ','; |
11075 | | printOperand(MI, 3, O); |
11076 | | break; |
11077 | | case 131: |
11078 | | // V6_vdmpyhsuisat_alt, V6_vdmpyhsusat_alt |
11079 | | O << " = vdmpyhsu("; |
11080 | | printOperand(MI, 1, O); |
11081 | | O << ','; |
11082 | | printOperand(MI, 2, O); |
11083 | | break; |
11084 | | case 132: |
11085 | | // V6_vdsaduh_acc_alt |
11086 | | O << " += vdsaduh("; |
11087 | | printOperand(MI, 2, O); |
11088 | | O << ','; |
11089 | | printOperand(MI, 3, O); |
11090 | | O << ')'; |
11091 | | return; |
11092 | | break; |
11093 | | case 133: |
11094 | | // V6_vdsaduh_alt |
11095 | | O << " = vdsaduh("; |
11096 | | printOperand(MI, 1, O); |
11097 | | O << ','; |
11098 | | printOperand(MI, 2, O); |
11099 | | O << ')'; |
11100 | | return; |
11101 | | break; |
11102 | | case 134: |
11103 | | // V6_vlsrh_alt, V6_vlsrhv_alt, S2_lsr_i_vh, S2_lsr_r_vh |
11104 | | O << " = vlsrh("; |
11105 | | printOperand(MI, 1, O); |
11106 | | break; |
11107 | | case 135: |
11108 | | // V6_vlsrw_alt, V6_vlsrwv_alt, S2_lsr_i_vw, S2_lsr_r_vw |
11109 | | O << " = vlsrw("; |
11110 | | printOperand(MI, 1, O); |
11111 | | break; |
11112 | | case 136: |
11113 | | // V6_vmaxb_alt, A2_vmaxb |
11114 | | O << " = vmaxb("; |
11115 | | printOperand(MI, 1, O); |
11116 | | O << ','; |
11117 | | printOperand(MI, 2, O); |
11118 | | O << ')'; |
11119 | | return; |
11120 | | break; |
11121 | | case 137: |
11122 | | // V6_vmaxh_alt, A2_vmaxh |
11123 | | O << " = vmaxh("; |
11124 | | printOperand(MI, 1, O); |
11125 | | O << ','; |
11126 | | printOperand(MI, 2, O); |
11127 | | O << ')'; |
11128 | | return; |
11129 | | break; |
11130 | | case 138: |
11131 | | // V6_vmaxub_alt, A2_vmaxub |
11132 | | O << " = vmaxub("; |
11133 | | printOperand(MI, 1, O); |
11134 | | O << ','; |
11135 | | printOperand(MI, 2, O); |
11136 | | O << ')'; |
11137 | | return; |
11138 | | break; |
11139 | | case 139: |
11140 | | // V6_vmaxuh_alt, A2_vmaxuh |
11141 | | O << " = vmaxuh("; |
11142 | | printOperand(MI, 1, O); |
11143 | | O << ','; |
11144 | | printOperand(MI, 2, O); |
11145 | | O << ')'; |
11146 | | return; |
11147 | | break; |
11148 | | case 140: |
11149 | | // V6_vmaxw_alt, A2_vmaxw |
11150 | | O << " = vmaxw("; |
11151 | | printOperand(MI, 1, O); |
11152 | | O << ','; |
11153 | | printOperand(MI, 2, O); |
11154 | | O << ')'; |
11155 | | return; |
11156 | | break; |
11157 | | case 141: |
11158 | | // V6_vminb_alt, A2_vminb |
11159 | | O << " = vminb("; |
11160 | | printOperand(MI, 1, O); |
11161 | | O << ','; |
11162 | | printOperand(MI, 2, O); |
11163 | | O << ')'; |
11164 | | return; |
11165 | | break; |
11166 | | case 142: |
11167 | | // V6_vminh_alt, A2_vminh |
11168 | | O << " = vminh("; |
11169 | | printOperand(MI, 1, O); |
11170 | | O << ','; |
11171 | | printOperand(MI, 2, O); |
11172 | | O << ')'; |
11173 | | return; |
11174 | | break; |
11175 | | case 143: |
11176 | | // V6_vminub_alt, A2_vminub |
11177 | | O << " = vminub("; |
11178 | | printOperand(MI, 1, O); |
11179 | | O << ','; |
11180 | | printOperand(MI, 2, O); |
11181 | | O << ')'; |
11182 | | return; |
11183 | | break; |
11184 | | case 144: |
11185 | | // V6_vminuh_alt, A2_vminuh |
11186 | | O << " = vminuh("; |
11187 | | printOperand(MI, 1, O); |
11188 | | O << ','; |
11189 | | printOperand(MI, 2, O); |
11190 | | O << ')'; |
11191 | | return; |
11192 | | break; |
11193 | | case 145: |
11194 | | // V6_vminw_alt, A2_vminw |
11195 | | O << " = vminw("; |
11196 | | printOperand(MI, 1, O); |
11197 | | O << ','; |
11198 | | printOperand(MI, 2, O); |
11199 | | O << ')'; |
11200 | | return; |
11201 | | break; |
11202 | | case 146: |
11203 | | // V6_vmpabus_acc_alt |
11204 | | O << " += vmpabus("; |
11205 | | printOperand(MI, 2, O); |
11206 | | O << ','; |
11207 | | printOperand(MI, 3, O); |
11208 | | O << ')'; |
11209 | | return; |
11210 | | break; |
11211 | | case 147: |
11212 | | // V6_vmpabus_alt, V6_vmpabusv_alt |
11213 | | O << " = vmpabus("; |
11214 | | printOperand(MI, 1, O); |
11215 | | O << ','; |
11216 | | printOperand(MI, 2, O); |
11217 | | O << ')'; |
11218 | | return; |
11219 | | break; |
11220 | | case 148: |
11221 | | // V6_vmpabuu_acc_alt |
11222 | | O << " += vmpabuu("; |
11223 | | printOperand(MI, 2, O); |
11224 | | O << ','; |
11225 | | printOperand(MI, 3, O); |
11226 | | O << ')'; |
11227 | | return; |
11228 | | break; |
11229 | | case 149: |
11230 | | // V6_vmpabuu_alt, V6_vmpabuuv_alt |
11231 | | O << " = vmpabuu("; |
11232 | | printOperand(MI, 1, O); |
11233 | | O << ','; |
11234 | | printOperand(MI, 2, O); |
11235 | | O << ')'; |
11236 | | return; |
11237 | | break; |
11238 | | case 150: |
11239 | | // V6_vmpahb_acc_alt |
11240 | | O << " += vmpahb("; |
11241 | | printOperand(MI, 2, O); |
11242 | | O << ','; |
11243 | | printOperand(MI, 3, O); |
11244 | | O << ')'; |
11245 | | return; |
11246 | | break; |
11247 | | case 151: |
11248 | | // V6_vmpahb_alt |
11249 | | O << " = vmpahb("; |
11250 | | printOperand(MI, 1, O); |
11251 | | O << ','; |
11252 | | printOperand(MI, 2, O); |
11253 | | O << ')'; |
11254 | | return; |
11255 | | break; |
11256 | | case 152: |
11257 | | // V6_vmpauhb_acc_alt |
11258 | | O << " += vmpauhb("; |
11259 | | printOperand(MI, 2, O); |
11260 | | O << ','; |
11261 | | printOperand(MI, 3, O); |
11262 | | O << ')'; |
11263 | | return; |
11264 | | break; |
11265 | | case 153: |
11266 | | // V6_vmpauhb_alt |
11267 | | O << " = vmpauhb("; |
11268 | | printOperand(MI, 1, O); |
11269 | | O << ','; |
11270 | | printOperand(MI, 2, O); |
11271 | | O << ')'; |
11272 | | return; |
11273 | | break; |
11274 | | case 154: |
11275 | | // V6_vmpybus_acc_alt, V6_vmpybusv_acc_alt |
11276 | | O << " += vmpybus("; |
11277 | | printOperand(MI, 2, O); |
11278 | | O << ','; |
11279 | | printOperand(MI, 3, O); |
11280 | | O << ')'; |
11281 | | return; |
11282 | | break; |
11283 | | case 155: |
11284 | | // V6_vmpybus_alt, V6_vmpybusv_alt |
11285 | | O << " = vmpybus("; |
11286 | | printOperand(MI, 1, O); |
11287 | | O << ','; |
11288 | | printOperand(MI, 2, O); |
11289 | | O << ')'; |
11290 | | return; |
11291 | | break; |
11292 | | case 156: |
11293 | | // V6_vmpybv_acc_alt |
11294 | | O << " += vmpyb("; |
11295 | | printOperand(MI, 2, O); |
11296 | | O << ','; |
11297 | | printOperand(MI, 3, O); |
11298 | | O << ')'; |
11299 | | return; |
11300 | | break; |
11301 | | case 157: |
11302 | | // V6_vmpybv_alt |
11303 | | O << " = vmpyb("; |
11304 | | printOperand(MI, 1, O); |
11305 | | O << ','; |
11306 | | printOperand(MI, 2, O); |
11307 | | O << ')'; |
11308 | | return; |
11309 | | break; |
11310 | | case 158: |
11311 | | // V6_vmpyewuh_alt |
11312 | | O << " = vmpyewuh("; |
11313 | | printOperand(MI, 1, O); |
11314 | | O << ','; |
11315 | | printOperand(MI, 2, O); |
11316 | | O << ')'; |
11317 | | return; |
11318 | | break; |
11319 | | case 159: |
11320 | | // V6_vmpyh_acc_alt, V6_vmpyhsat_acc_alt, V6_vmpyhv_acc_alt, M2_vmac2, M2... |
11321 | | O << " += vmpyh("; |
11322 | | printOperand(MI, 2, O); |
11323 | | O << ','; |
11324 | | printOperand(MI, 3, O); |
11325 | | break; |
11326 | | case 160: |
11327 | | // V6_vmpyh_alt, V6_vmpyhsrs_alt, V6_vmpyhss_alt, V6_vmpyhv_alt, V6_vmpyh... |
11328 | | O << " = vmpyh("; |
11329 | | printOperand(MI, 1, O); |
11330 | | O << ','; |
11331 | | printOperand(MI, 2, O); |
11332 | | break; |
11333 | | case 161: |
11334 | | // V6_vmpyhus_acc_alt |
11335 | | O << " += vmpyhus("; |
11336 | | printOperand(MI, 2, O); |
11337 | | O << ','; |
11338 | | printOperand(MI, 3, O); |
11339 | | O << ')'; |
11340 | | return; |
11341 | | break; |
11342 | | case 162: |
11343 | | // V6_vmpyhus_alt |
11344 | | O << " = vmpyhus("; |
11345 | | printOperand(MI, 1, O); |
11346 | | O << ','; |
11347 | | printOperand(MI, 2, O); |
11348 | | O << ')'; |
11349 | | return; |
11350 | | break; |
11351 | | case 163: |
11352 | | // V6_vmpyiewh_acc_alt |
11353 | | O << " += vmpyiewh("; |
11354 | | printOperand(MI, 2, O); |
11355 | | O << ','; |
11356 | | printOperand(MI, 3, O); |
11357 | | O << ')'; |
11358 | | return; |
11359 | | break; |
11360 | | case 164: |
11361 | | // V6_vmpyiewuh_acc_alt |
11362 | | O << " += vmpyiewuh("; |
11363 | | printOperand(MI, 2, O); |
11364 | | O << ','; |
11365 | | printOperand(MI, 3, O); |
11366 | | O << ')'; |
11367 | | return; |
11368 | | break; |
11369 | | case 165: |
11370 | | // V6_vmpyiewuh_alt |
11371 | | O << " = vmpyiewuh("; |
11372 | | printOperand(MI, 1, O); |
11373 | | O << ','; |
11374 | | printOperand(MI, 2, O); |
11375 | | O << ')'; |
11376 | | return; |
11377 | | break; |
11378 | | case 166: |
11379 | | // V6_vmpyih_acc_alt |
11380 | | O << " += vmpyih("; |
11381 | | printOperand(MI, 2, O); |
11382 | | O << ','; |
11383 | | printOperand(MI, 3, O); |
11384 | | O << ')'; |
11385 | | return; |
11386 | | break; |
11387 | | case 167: |
11388 | | // V6_vmpyih_alt |
11389 | | O << " = vmpyih("; |
11390 | | printOperand(MI, 1, O); |
11391 | | O << ','; |
11392 | | printOperand(MI, 2, O); |
11393 | | O << ')'; |
11394 | | return; |
11395 | | break; |
11396 | | case 168: |
11397 | | // V6_vmpyihb_acc_alt |
11398 | | O << " += vmpyihb("; |
11399 | | printOperand(MI, 2, O); |
11400 | | O << ','; |
11401 | | printOperand(MI, 3, O); |
11402 | | O << ')'; |
11403 | | return; |
11404 | | break; |
11405 | | case 169: |
11406 | | // V6_vmpyihb_alt |
11407 | | O << " = vmpyihb("; |
11408 | | printOperand(MI, 1, O); |
11409 | | O << ','; |
11410 | | printOperand(MI, 2, O); |
11411 | | O << ')'; |
11412 | | return; |
11413 | | break; |
11414 | | case 170: |
11415 | | // V6_vmpyiowh_alt |
11416 | | O << " = vmpyiowh("; |
11417 | | printOperand(MI, 1, O); |
11418 | | O << ','; |
11419 | | printOperand(MI, 2, O); |
11420 | | O << ')'; |
11421 | | return; |
11422 | | break; |
11423 | | case 171: |
11424 | | // V6_vmpyiwb_acc_alt |
11425 | | O << " += vmpyiwb("; |
11426 | | printOperand(MI, 2, O); |
11427 | | O << ','; |
11428 | | printOperand(MI, 3, O); |
11429 | | O << ')'; |
11430 | | return; |
11431 | | break; |
11432 | | case 172: |
11433 | | // V6_vmpyiwb_alt |
11434 | | O << " = vmpyiwb("; |
11435 | | printOperand(MI, 1, O); |
11436 | | O << ','; |
11437 | | printOperand(MI, 2, O); |
11438 | | O << ')'; |
11439 | | return; |
11440 | | break; |
11441 | | case 173: |
11442 | | // V6_vmpyiwh_acc_alt |
11443 | | O << " += vmpyiwh("; |
11444 | | printOperand(MI, 2, O); |
11445 | | O << ','; |
11446 | | printOperand(MI, 3, O); |
11447 | | O << ')'; |
11448 | | return; |
11449 | | break; |
11450 | | case 174: |
11451 | | // V6_vmpyiwh_alt |
11452 | | O << " = vmpyiwh("; |
11453 | | printOperand(MI, 1, O); |
11454 | | O << ','; |
11455 | | printOperand(MI, 2, O); |
11456 | | O << ')'; |
11457 | | return; |
11458 | | break; |
11459 | | case 175: |
11460 | | // V6_vmpyiwub_acc_alt |
11461 | | O << " += vmpyiwub("; |
11462 | | printOperand(MI, 2, O); |
11463 | | O << ','; |
11464 | | printOperand(MI, 3, O); |
11465 | | O << ')'; |
11466 | | return; |
11467 | | break; |
11468 | | case 176: |
11469 | | // V6_vmpyiwub_alt |
11470 | | O << " = vmpyiwub("; |
11471 | | printOperand(MI, 1, O); |
11472 | | O << ','; |
11473 | | printOperand(MI, 2, O); |
11474 | | O << ')'; |
11475 | | return; |
11476 | | break; |
11477 | | case 177: |
11478 | | // V6_vmpyowh_alt, V6_vmpyowh_rnd_alt |
11479 | | O << " = vmpyowh("; |
11480 | | printOperand(MI, 1, O); |
11481 | | O << ','; |
11482 | | printOperand(MI, 2, O); |
11483 | | break; |
11484 | | case 178: |
11485 | | // V6_vmpyowh_rnd_sacc_alt, V6_vmpyowh_sacc_alt |
11486 | | O << " += vmpyowh("; |
11487 | | printOperand(MI, 2, O); |
11488 | | O << ','; |
11489 | | printOperand(MI, 3, O); |
11490 | | break; |
11491 | | case 179: |
11492 | | // V6_vmpyub_acc_alt, V6_vmpyubv_acc_alt |
11493 | | O << " += vmpyub("; |
11494 | | printOperand(MI, 2, O); |
11495 | | O << ','; |
11496 | | printOperand(MI, 3, O); |
11497 | | O << ')'; |
11498 | | return; |
11499 | | break; |
11500 | | case 180: |
11501 | | // V6_vmpyub_alt, V6_vmpyubv_alt |
11502 | | O << " = vmpyub("; |
11503 | | printOperand(MI, 1, O); |
11504 | | O << ','; |
11505 | | printOperand(MI, 2, O); |
11506 | | O << ')'; |
11507 | | return; |
11508 | | break; |
11509 | | case 181: |
11510 | | // V6_vmpyuh_acc_alt, V6_vmpyuhv_acc_alt |
11511 | | O << " += vmpyuh("; |
11512 | | printOperand(MI, 2, O); |
11513 | | O << ','; |
11514 | | printOperand(MI, 3, O); |
11515 | | O << ')'; |
11516 | | return; |
11517 | | break; |
11518 | | case 182: |
11519 | | // V6_vmpyuh_alt, V6_vmpyuhv_alt |
11520 | | O << " = vmpyuh("; |
11521 | | printOperand(MI, 1, O); |
11522 | | O << ','; |
11523 | | printOperand(MI, 2, O); |
11524 | | O << ')'; |
11525 | | return; |
11526 | | break; |
11527 | | case 183: |
11528 | | // V6_vnavgb_alt |
11529 | | O << " = vnavgb("; |
11530 | | printOperand(MI, 1, O); |
11531 | | O << ','; |
11532 | | printOperand(MI, 2, O); |
11533 | | O << ')'; |
11534 | | return; |
11535 | | break; |
11536 | | case 184: |
11537 | | // V6_vnavgh_alt, A2_svnavgh, A2_vnavgh, A2_vnavghcr, A2_vnavghr |
11538 | | O << " = vnavgh("; |
11539 | | printOperand(MI, 1, O); |
11540 | | O << ','; |
11541 | | printOperand(MI, 2, O); |
11542 | | break; |
11543 | | case 185: |
11544 | | // V6_vnavgub_alt |
11545 | | O << " = vnavgub("; |
11546 | | printOperand(MI, 1, O); |
11547 | | O << ','; |
11548 | | printOperand(MI, 2, O); |
11549 | | O << ')'; |
11550 | | return; |
11551 | | break; |
11552 | | case 186: |
11553 | | // V6_vnavgw_alt, A2_vnavgw, A2_vnavgwcr, A2_vnavgwr |
11554 | | O << " = vnavgw("; |
11555 | | printOperand(MI, 1, O); |
11556 | | O << ','; |
11557 | | printOperand(MI, 2, O); |
11558 | | break; |
11559 | | case 187: |
11560 | | // V6_vnormamth_alt |
11561 | | O << " = vnormamth("; |
11562 | | printOperand(MI, 1, O); |
11563 | | O << ')'; |
11564 | | return; |
11565 | | break; |
11566 | | case 188: |
11567 | | // V6_vnormamtw_alt |
11568 | | O << " = vnormamtw("; |
11569 | | printOperand(MI, 1, O); |
11570 | | O << ')'; |
11571 | | return; |
11572 | | break; |
11573 | | case 189: |
11574 | | // V6_vpackeb_alt |
11575 | | O << " = vpackeb("; |
11576 | | printOperand(MI, 1, O); |
11577 | | O << ','; |
11578 | | printOperand(MI, 2, O); |
11579 | | O << ')'; |
11580 | | return; |
11581 | | break; |
11582 | | case 190: |
11583 | | // V6_vpackeh_alt |
11584 | | O << " = vpackeh("; |
11585 | | printOperand(MI, 1, O); |
11586 | | O << ','; |
11587 | | printOperand(MI, 2, O); |
11588 | | O << ')'; |
11589 | | return; |
11590 | | break; |
11591 | | case 191: |
11592 | | // V6_vpackhb_sat_alt |
11593 | | O << " = vpackhb("; |
11594 | | printOperand(MI, 1, O); |
11595 | | O << ','; |
11596 | | printOperand(MI, 2, O); |
11597 | | O << "):sat"; |
11598 | | return; |
11599 | | break; |
11600 | | case 192: |
11601 | | // V6_vpackhub_sat_alt |
11602 | | O << " = vpackhub("; |
11603 | | printOperand(MI, 1, O); |
11604 | | O << ','; |
11605 | | printOperand(MI, 2, O); |
11606 | | O << "):sat"; |
11607 | | return; |
11608 | | break; |
11609 | | case 193: |
11610 | | // V6_vpackob_alt |
11611 | | O << " = vpackob("; |
11612 | | printOperand(MI, 1, O); |
11613 | | O << ','; |
11614 | | printOperand(MI, 2, O); |
11615 | | O << ')'; |
11616 | | return; |
11617 | | break; |
11618 | | case 194: |
11619 | | // V6_vpackoh_alt |
11620 | | O << " = vpackoh("; |
11621 | | printOperand(MI, 1, O); |
11622 | | O << ','; |
11623 | | printOperand(MI, 2, O); |
11624 | | O << ')'; |
11625 | | return; |
11626 | | break; |
11627 | | case 195: |
11628 | | // V6_vpackwh_sat_alt |
11629 | | O << " = vpackwh("; |
11630 | | printOperand(MI, 1, O); |
11631 | | O << ','; |
11632 | | printOperand(MI, 2, O); |
11633 | | O << "):sat"; |
11634 | | return; |
11635 | | break; |
11636 | | case 196: |
11637 | | // V6_vpackwuh_sat_alt |
11638 | | O << " = vpackwuh("; |
11639 | | printOperand(MI, 1, O); |
11640 | | O << ','; |
11641 | | printOperand(MI, 2, O); |
11642 | | O << "):sat"; |
11643 | | return; |
11644 | | break; |
11645 | | case 197: |
11646 | | // V6_vpopcounth_alt |
11647 | | O << " = vpopcounth("; |
11648 | | printOperand(MI, 1, O); |
11649 | | O << ')'; |
11650 | | return; |
11651 | | break; |
11652 | | case 198: |
11653 | | // V6_vrmpybub_rtt_acc_alt, V6_vrmpybub_rtt_acc, V6_vrmpybus_acc, V6_vrmp... |
11654 | | O << ".w += vrmpy("; |
11655 | | printOperand(MI, 2, O); |
11656 | | break; |
11657 | | case 199: |
11658 | | // V6_vrmpybub_rtt_alt, V6_vrmpybub_rtt, V6_vrmpybus, V6_vrmpybusi, V6_vr... |
11659 | | O << ".w = vrmpy("; |
11660 | | printOperand(MI, 1, O); |
11661 | | break; |
11662 | | case 200: |
11663 | | // V6_vrmpybus_acc_alt, V6_vrmpybusi_acc_alt, V6_vrmpybusv_acc_alt |
11664 | | O << " += vrmpybus("; |
11665 | | printOperand(MI, 2, O); |
11666 | | O << ','; |
11667 | | printOperand(MI, 3, O); |
11668 | | break; |
11669 | | case 201: |
11670 | | // V6_vrmpybus_alt, V6_vrmpybusi_alt, V6_vrmpybusv_alt |
11671 | | O << " = vrmpybus("; |
11672 | | printOperand(MI, 1, O); |
11673 | | O << ','; |
11674 | | printOperand(MI, 2, O); |
11675 | | break; |
11676 | | case 202: |
11677 | | // V6_vrmpybv_acc_alt |
11678 | | O << " += vrmpyb("; |
11679 | | printOperand(MI, 2, O); |
11680 | | O << ','; |
11681 | | printOperand(MI, 3, O); |
11682 | | O << ')'; |
11683 | | return; |
11684 | | break; |
11685 | | case 203: |
11686 | | // V6_vrmpybv_alt |
11687 | | O << " = vrmpyb("; |
11688 | | printOperand(MI, 1, O); |
11689 | | O << ','; |
11690 | | printOperand(MI, 2, O); |
11691 | | O << ')'; |
11692 | | return; |
11693 | | break; |
11694 | | case 204: |
11695 | | // V6_vrmpyub_acc_alt, V6_vrmpyubi_acc_alt, V6_vrmpyubv_acc_alt |
11696 | | O << " += vrmpyub("; |
11697 | | printOperand(MI, 2, O); |
11698 | | O << ','; |
11699 | | printOperand(MI, 3, O); |
11700 | | break; |
11701 | | case 205: |
11702 | | // V6_vrmpyub_alt, V6_vrmpyubi_alt, V6_vrmpyubv_alt |
11703 | | O << " = vrmpyub("; |
11704 | | printOperand(MI, 1, O); |
11705 | | O << ','; |
11706 | | printOperand(MI, 2, O); |
11707 | | break; |
11708 | | case 206: |
11709 | | // V6_vrmpyub_rtt_acc_alt, V6_vrmpyub_acc, V6_vrmpyub_rtt_acc, V6_vrmpyub... |
11710 | | O << ".uw += vrmpy("; |
11711 | | printOperand(MI, 2, O); |
11712 | | O << ".ub,"; |
11713 | | printOperand(MI, 3, O); |
11714 | | break; |
11715 | | case 207: |
11716 | | // V6_vrmpyub_rtt_alt, V6_vrmpyub, V6_vrmpyub_rtt, V6_vrmpyubi, V6_vrmpyu... |
11717 | | O << ".uw = vrmpy("; |
11718 | | printOperand(MI, 1, O); |
11719 | | O << ".ub,"; |
11720 | | printOperand(MI, 2, O); |
11721 | | break; |
11722 | | case 208: |
11723 | | // V6_vrotr_alt |
11724 | | O << " = vrotr("; |
11725 | | printOperand(MI, 1, O); |
11726 | | O << ','; |
11727 | | printOperand(MI, 2, O); |
11728 | | O << ')'; |
11729 | | return; |
11730 | | break; |
11731 | | case 209: |
11732 | | // V6_vroundhb_alt |
11733 | | O << " = vroundhb("; |
11734 | | printOperand(MI, 1, O); |
11735 | | O << ','; |
11736 | | printOperand(MI, 2, O); |
11737 | | O << "):sat"; |
11738 | | return; |
11739 | | break; |
11740 | | case 210: |
11741 | | // V6_vroundhub_alt |
11742 | | O << " = vroundhub("; |
11743 | | printOperand(MI, 1, O); |
11744 | | O << ','; |
11745 | | printOperand(MI, 2, O); |
11746 | | O << "):sat"; |
11747 | | return; |
11748 | | break; |
11749 | | case 211: |
11750 | | // V6_vrounduhub_alt |
11751 | | O << " = vrounduhub("; |
11752 | | printOperand(MI, 1, O); |
11753 | | O << ','; |
11754 | | printOperand(MI, 2, O); |
11755 | | O << "):sat"; |
11756 | | return; |
11757 | | break; |
11758 | | case 212: |
11759 | | // V6_vrounduwuh_alt |
11760 | | O << " = vrounduwuh("; |
11761 | | printOperand(MI, 1, O); |
11762 | | O << ','; |
11763 | | printOperand(MI, 2, O); |
11764 | | O << "):sat"; |
11765 | | return; |
11766 | | break; |
11767 | | case 213: |
11768 | | // V6_vroundwh_alt |
11769 | | O << " = vroundwh("; |
11770 | | printOperand(MI, 1, O); |
11771 | | O << ','; |
11772 | | printOperand(MI, 2, O); |
11773 | | O << "):sat"; |
11774 | | return; |
11775 | | break; |
11776 | | case 214: |
11777 | | // V6_vroundwuh_alt |
11778 | | O << " = vroundwuh("; |
11779 | | printOperand(MI, 1, O); |
11780 | | O << ','; |
11781 | | printOperand(MI, 2, O); |
11782 | | O << "):sat"; |
11783 | | return; |
11784 | | break; |
11785 | | case 215: |
11786 | | // V6_vrsadubi_acc_alt, A2_vrsadub_acc |
11787 | | O << " += vrsadub("; |
11788 | | printOperand(MI, 2, O); |
11789 | | O << ','; |
11790 | | printOperand(MI, 3, O); |
11791 | | break; |
11792 | | case 216: |
11793 | | // V6_vrsadubi_alt, A2_vrsadub |
11794 | | O << " = vrsadub("; |
11795 | | printOperand(MI, 1, O); |
11796 | | O << ','; |
11797 | | printOperand(MI, 2, O); |
11798 | | break; |
11799 | | case 217: |
11800 | | // V6_vsathub_alt, S2_svsathub, S2_vsathub, S2_vsathub_nopack |
11801 | | O << " = vsathub("; |
11802 | | printOperand(MI, 1, O); |
11803 | | break; |
11804 | | case 218: |
11805 | | // V6_vsatuwuh_alt |
11806 | | O << " = vsatuwuh("; |
11807 | | printOperand(MI, 1, O); |
11808 | | O << ','; |
11809 | | printOperand(MI, 2, O); |
11810 | | O << ')'; |
11811 | | return; |
11812 | | break; |
11813 | | case 219: |
11814 | | // V6_vsatwh_alt, S2_vsatwh, S2_vsatwh_nopack |
11815 | | O << " = vsatwh("; |
11816 | | printOperand(MI, 1, O); |
11817 | | break; |
11818 | | case 220: |
11819 | | // V6_vsb_alt |
11820 | | O << " = vsxtb("; |
11821 | | printOperand(MI, 1, O); |
11822 | | O << ')'; |
11823 | | return; |
11824 | | break; |
11825 | | case 221: |
11826 | | // V6_vscattermh_add_alt, V6_vscattermh_alt, V6_vscattermw_add_alt, V6_vs... |
11827 | | O << ','; |
11828 | | break; |
11829 | | case 222: |
11830 | | // V6_vscattermhq_alt, V6_vscattermwhq_alt, V6_vscattermwq_alt, V6_vscatt... |
11831 | | O << ") vscatter("; |
11832 | | printOperand(MI, 1, O); |
11833 | | O << ','; |
11834 | | printOperand(MI, 2, O); |
11835 | | O << ','; |
11836 | | printOperand(MI, 3, O); |
11837 | | break; |
11838 | | case 223: |
11839 | | // V6_vsh_alt |
11840 | | O << " = vsxth("; |
11841 | | printOperand(MI, 1, O); |
11842 | | O << ')'; |
11843 | | return; |
11844 | | break; |
11845 | | case 224: |
11846 | | // V6_vshufeh_alt |
11847 | | O << " = vshuffeh("; |
11848 | | printOperand(MI, 1, O); |
11849 | | O << ','; |
11850 | | printOperand(MI, 2, O); |
11851 | | O << ')'; |
11852 | | return; |
11853 | | break; |
11854 | | case 225: |
11855 | | // V6_vshuffb_alt |
11856 | | O << " = vshuffb("; |
11857 | | printOperand(MI, 1, O); |
11858 | | O << ')'; |
11859 | | return; |
11860 | | break; |
11861 | | case 226: |
11862 | | // V6_vshuffeb_alt |
11863 | | O << " = vshuffeb("; |
11864 | | printOperand(MI, 1, O); |
11865 | | O << ','; |
11866 | | printOperand(MI, 2, O); |
11867 | | O << ')'; |
11868 | | return; |
11869 | | break; |
11870 | | case 227: |
11871 | | // V6_vshuffh_alt |
11872 | | O << " = vshuffh("; |
11873 | | printOperand(MI, 1, O); |
11874 | | O << ')'; |
11875 | | return; |
11876 | | break; |
11877 | | case 228: |
11878 | | // V6_vshuffob_alt |
11879 | | O << " = vshuffob("; |
11880 | | printOperand(MI, 1, O); |
11881 | | O << ','; |
11882 | | printOperand(MI, 2, O); |
11883 | | O << ')'; |
11884 | | return; |
11885 | | break; |
11886 | | case 229: |
11887 | | // V6_vshufoeb_alt |
11888 | | O << " = vshuffoeb("; |
11889 | | printOperand(MI, 1, O); |
11890 | | O << ','; |
11891 | | printOperand(MI, 2, O); |
11892 | | O << ')'; |
11893 | | return; |
11894 | | break; |
11895 | | case 230: |
11896 | | // V6_vshufoeh_alt |
11897 | | O << " = vshuffoeh("; |
11898 | | printOperand(MI, 1, O); |
11899 | | O << ','; |
11900 | | printOperand(MI, 2, O); |
11901 | | O << ')'; |
11902 | | return; |
11903 | | break; |
11904 | | case 231: |
11905 | | // V6_vshufoh_alt |
11906 | | O << " = vshuffoh("; |
11907 | | printOperand(MI, 1, O); |
11908 | | O << ','; |
11909 | | printOperand(MI, 2, O); |
11910 | | O << ')'; |
11911 | | return; |
11912 | | break; |
11913 | | case 232: |
11914 | | // V6_vsubh_alt, V6_vsubh_dv_alt, V6_vsubhsat_alt, V6_vsubhsat_dv_alt, V6... |
11915 | | O << " = vsubh("; |
11916 | | printOperand(MI, 1, O); |
11917 | | O << ','; |
11918 | | printOperand(MI, 2, O); |
11919 | | break; |
11920 | | case 233: |
11921 | | // V6_vsububh_alt, V6_vsububsat_alt, V6_vsububsat_dv_alt, A2_vsubub, A2_v... |
11922 | | O << " = vsubub("; |
11923 | | printOperand(MI, 1, O); |
11924 | | O << ','; |
11925 | | printOperand(MI, 2, O); |
11926 | | break; |
11927 | | case 234: |
11928 | | // V6_vsubuhsat_alt, V6_vsubuhsat_dv_alt, V6_vsubuhw_alt, A2_svsubuhs, A2... |
11929 | | O << " = vsubuh("; |
11930 | | printOperand(MI, 1, O); |
11931 | | O << ','; |
11932 | | printOperand(MI, 2, O); |
11933 | | break; |
11934 | | case 235: |
11935 | | // V6_vsubuwsat_alt, V6_vsubuwsat_dv_alt |
11936 | | O << " = vsubuw("; |
11937 | | printOperand(MI, 1, O); |
11938 | | O << ','; |
11939 | | printOperand(MI, 2, O); |
11940 | | O << "):sat"; |
11941 | | return; |
11942 | | break; |
11943 | | case 236: |
11944 | | // V6_vsubw_alt, V6_vsubw_dv_alt, V6_vsubwsat_alt, V6_vsubwsat_dv_alt, A2... |
11945 | | O << " = vsubw("; |
11946 | | printOperand(MI, 1, O); |
11947 | | O << ','; |
11948 | | printOperand(MI, 2, O); |
11949 | | break; |
11950 | | case 237: |
11951 | | // V6_vtmpyb_acc_alt |
11952 | | O << " += vtmpyb("; |
11953 | | printOperand(MI, 2, O); |
11954 | | O << ','; |
11955 | | printOperand(MI, 3, O); |
11956 | | O << ')'; |
11957 | | return; |
11958 | | break; |
11959 | | case 238: |
11960 | | // V6_vtmpyb_alt |
11961 | | O << " = vtmpyb("; |
11962 | | printOperand(MI, 1, O); |
11963 | | O << ','; |
11964 | | printOperand(MI, 2, O); |
11965 | | O << ')'; |
11966 | | return; |
11967 | | break; |
11968 | | case 239: |
11969 | | // V6_vtmpybus_acc_alt |
11970 | | O << " += vtmpybus("; |
11971 | | printOperand(MI, 2, O); |
11972 | | O << ','; |
11973 | | printOperand(MI, 3, O); |
11974 | | O << ')'; |
11975 | | return; |
11976 | | break; |
11977 | | case 240: |
11978 | | // V6_vtmpybus_alt |
11979 | | O << " = vtmpybus("; |
11980 | | printOperand(MI, 1, O); |
11981 | | O << ','; |
11982 | | printOperand(MI, 2, O); |
11983 | | O << ')'; |
11984 | | return; |
11985 | | break; |
11986 | | case 241: |
11987 | | // V6_vtmpyhb_acc_alt |
11988 | | O << " += vtmpyhb("; |
11989 | | printOperand(MI, 2, O); |
11990 | | O << ','; |
11991 | | printOperand(MI, 3, O); |
11992 | | O << ')'; |
11993 | | return; |
11994 | | break; |
11995 | | case 242: |
11996 | | // V6_vtmpyhb_alt |
11997 | | O << " = vtmpyhb("; |
11998 | | printOperand(MI, 1, O); |
11999 | | O << ','; |
12000 | | printOperand(MI, 2, O); |
12001 | | O << ')'; |
12002 | | return; |
12003 | | break; |
12004 | | case 243: |
12005 | | // V6_vunpackb_alt |
12006 | | O << " = vunpackb("; |
12007 | | printOperand(MI, 1, O); |
12008 | | O << ')'; |
12009 | | return; |
12010 | | break; |
12011 | | case 244: |
12012 | | // V6_vunpackh_alt |
12013 | | O << " = vunpackh("; |
12014 | | printOperand(MI, 1, O); |
12015 | | O << ')'; |
12016 | | return; |
12017 | | break; |
12018 | | case 245: |
12019 | | // V6_vunpackob_alt |
12020 | | O << " |= vunpackob("; |
12021 | | printOperand(MI, 2, O); |
12022 | | O << ')'; |
12023 | | return; |
12024 | | break; |
12025 | | case 246: |
12026 | | // V6_vunpackoh_alt |
12027 | | O << " |= vunpackoh("; |
12028 | | printOperand(MI, 2, O); |
12029 | | O << ')'; |
12030 | | return; |
12031 | | break; |
12032 | | case 247: |
12033 | | // V6_vunpackub_alt |
12034 | | O << " = vunpackub("; |
12035 | | printOperand(MI, 1, O); |
12036 | | O << ')'; |
12037 | | return; |
12038 | | break; |
12039 | | case 248: |
12040 | | // V6_vunpackuh_alt |
12041 | | O << " = vunpackuh("; |
12042 | | printOperand(MI, 1, O); |
12043 | | O << ')'; |
12044 | | return; |
12045 | | break; |
12046 | | case 249: |
12047 | | // V6_vzb_alt |
12048 | | O << " = vzxtb("; |
12049 | | printOperand(MI, 1, O); |
12050 | | O << ')'; |
12051 | | return; |
12052 | | break; |
12053 | | case 250: |
12054 | | // V6_vzh_alt |
12055 | | O << " = vzxth("; |
12056 | | printOperand(MI, 1, O); |
12057 | | O << ')'; |
12058 | | return; |
12059 | | break; |
12060 | | case 251: |
12061 | | // V6_zldp0, V6_zLd_pred_ai, V6_zLd_pred_pi, V6_zLd_pred_ppu |
12062 | | O << ") z = vmem("; |
12063 | | break; |
12064 | | case 252: |
12065 | | // Y2_crswap_old |
12066 | | O << ",sgp)"; |
12067 | | return; |
12068 | | break; |
12069 | | case 253: |
12070 | | // dup_A2_andir, A2_and, A2_andir, A2_andp, A4_andn, A4_andnp, C2_and, C2... |
12071 | | O << " = and("; |
12072 | | printOperand(MI, 1, O); |
12073 | | break; |
12074 | | case 254: |
12075 | | // dup_A2_combineii, dup_A4_combineii, dup_A4_combineir, A2_combineii, A4... |
12076 | | O << " = combine(#"; |
12077 | | printOperand(MI, 1, O); |
12078 | | break; |
12079 | | case 255: |
12080 | | // dup_A2_sxtb, A2_sxtb, SA1_sxtb |
12081 | | O << " = sxtb("; |
12082 | | printOperand(MI, 1, O); |
12083 | | O << ')'; |
12084 | | return; |
12085 | | break; |
12086 | | case 256: |
12087 | | // dup_A2_sxth, A2_sxth, SA1_sxth |
12088 | | O << " = sxth("; |
12089 | | printOperand(MI, 1, O); |
12090 | | O << ')'; |
12091 | | return; |
12092 | | break; |
12093 | | case 257: |
12094 | | // dup_A2_zxth, A2_zxth, SA1_zxth |
12095 | | O << " = zxth("; |
12096 | | printOperand(MI, 1, O); |
12097 | | O << ')'; |
12098 | | return; |
12099 | | break; |
12100 | | case 258: |
12101 | | // dup_A4_combineri, A2_combine_hh, A2_combine_hl, A2_combine_lh, A2_comb... |
12102 | | O << " = combine("; |
12103 | | printOperand(MI, 1, O); |
12104 | | break; |
12105 | | case 259: |
12106 | | // dup_C2_cmpeqi, A4_rcmpeq, A4_rcmpeqi, C2_cmpeq, C2_cmpeqi, C2_cmpeqp |
12107 | | O << " = cmp.eq("; |
12108 | | printOperand(MI, 1, O); |
12109 | | break; |
12110 | | case 260: |
12111 | | // dup_L2_deallocframe, L2_deallocframe |
12112 | | O << " = deallocframe("; |
12113 | | printOperand(MI, 1, O); |
12114 | | O << "):raw"; |
12115 | | return; |
12116 | | break; |
12117 | | case 261: |
12118 | | // dup_S2_allocframe, J2_loop0i, J2_loop0iext, J2_loop1i, J2_loop1iext, J... |
12119 | | O << ",#"; |
12120 | | break; |
12121 | | case 262: |
12122 | | // dup_S2_storerb_io, dup_S2_storerd_io, dup_S2_storerh_io, dup_S2_storer... |
12123 | | O << "+#"; |
12124 | | printOperand(MI, 1, O); |
12125 | | break; |
12126 | | case 263: |
12127 | | // A2_abs, A2_absp, A2_abssat |
12128 | | O << " = abs("; |
12129 | | printOperand(MI, 1, O); |
12130 | | break; |
12131 | | case 264: |
12132 | | // A2_aslh |
12133 | | O << " = aslh("; |
12134 | | printOperand(MI, 1, O); |
12135 | | O << ')'; |
12136 | | return; |
12137 | | break; |
12138 | | case 265: |
12139 | | // A2_asrh |
12140 | | O << " = asrh("; |
12141 | | printOperand(MI, 1, O); |
12142 | | O << ')'; |
12143 | | return; |
12144 | | break; |
12145 | | case 266: |
12146 | | // A2_max, A2_maxp |
12147 | | O << " = max("; |
12148 | | printOperand(MI, 1, O); |
12149 | | O << ','; |
12150 | | printOperand(MI, 2, O); |
12151 | | O << ')'; |
12152 | | return; |
12153 | | break; |
12154 | | case 267: |
12155 | | // A2_maxu, A2_maxup |
12156 | | O << " = maxu("; |
12157 | | printOperand(MI, 1, O); |
12158 | | O << ','; |
12159 | | printOperand(MI, 2, O); |
12160 | | O << ')'; |
12161 | | return; |
12162 | | break; |
12163 | | case 268: |
12164 | | // A2_min, A2_minp |
12165 | | O << " = min("; |
12166 | | printOperand(MI, 1, O); |
12167 | | O << ','; |
12168 | | printOperand(MI, 2, O); |
12169 | | O << ')'; |
12170 | | return; |
12171 | | break; |
12172 | | case 269: |
12173 | | // A2_minu, A2_minup |
12174 | | O << " = minu("; |
12175 | | printOperand(MI, 1, O); |
12176 | | O << ','; |
12177 | | printOperand(MI, 2, O); |
12178 | | O << ')'; |
12179 | | return; |
12180 | | break; |
12181 | | case 270: |
12182 | | // A2_or, A2_orir, A2_orp, A4_orn, A4_ornp, C2_or, C2_orn, C4_or_and, C4_... |
12183 | | O << " = or("; |
12184 | | printOperand(MI, 1, O); |
12185 | | break; |
12186 | | case 271: |
12187 | | // A2_roundsat, A4_round_ri, A4_round_ri_sat, A4_round_rr, A4_round_rr_sa... |
12188 | | O << " = round("; |
12189 | | printOperand(MI, 1, O); |
12190 | | break; |
12191 | | case 272: |
12192 | | // A2_sat |
12193 | | O << " = sat("; |
12194 | | printOperand(MI, 1, O); |
12195 | | O << ')'; |
12196 | | return; |
12197 | | break; |
12198 | | case 273: |
12199 | | // A2_satb |
12200 | | O << " = satb("; |
12201 | | printOperand(MI, 1, O); |
12202 | | O << ')'; |
12203 | | return; |
12204 | | break; |
12205 | | case 274: |
12206 | | // A2_sath |
12207 | | O << " = sath("; |
12208 | | printOperand(MI, 1, O); |
12209 | | O << ')'; |
12210 | | return; |
12211 | | break; |
12212 | | case 275: |
12213 | | // A2_satub |
12214 | | O << " = satub("; |
12215 | | printOperand(MI, 1, O); |
12216 | | O << ')'; |
12217 | | return; |
12218 | | break; |
12219 | | case 276: |
12220 | | // A2_satuh |
12221 | | O << " = satuh("; |
12222 | | printOperand(MI, 1, O); |
12223 | | O << ')'; |
12224 | | return; |
12225 | | break; |
12226 | | case 277: |
12227 | | // A2_sub, A2_subh_h16_hh, A2_subh_h16_hl, A2_subh_h16_lh, A2_subh_h16_ll... |
12228 | | O << " = sub("; |
12229 | | break; |
12230 | | case 278: |
12231 | | // A2_subri, S4_subi_asl_ri, S4_subi_lsr_ri |
12232 | | O << " = sub(#"; |
12233 | | printOperand(MI, 1, O); |
12234 | | break; |
12235 | | case 279: |
12236 | | // A2_swiz |
12237 | | O << " = swiz("; |
12238 | | printOperand(MI, 1, O); |
12239 | | O << ')'; |
12240 | | return; |
12241 | | break; |
12242 | | case 280: |
12243 | | // A2_sxtw |
12244 | | O << " = sxtw("; |
12245 | | printOperand(MI, 1, O); |
12246 | | O << ')'; |
12247 | | return; |
12248 | | break; |
12249 | | case 281: |
12250 | | // A2_tfrih, HI |
12251 | | O << ".h = #"; |
12252 | | break; |
12253 | | case 282: |
12254 | | // A2_tfril, LO |
12255 | | O << ".l = #"; |
12256 | | break; |
12257 | | case 283: |
12258 | | // A2_vcmpbeq, A4_vcmpbeqi |
12259 | | O << " = vcmpb.eq("; |
12260 | | printOperand(MI, 1, O); |
12261 | | break; |
12262 | | case 284: |
12263 | | // A2_vcmpbgtu, A4_vcmpbgtui |
12264 | | O << " = vcmpb.gtu("; |
12265 | | printOperand(MI, 1, O); |
12266 | | break; |
12267 | | case 285: |
12268 | | // A2_vcmpheq, A4_vcmpheqi |
12269 | | O << " = vcmph.eq("; |
12270 | | printOperand(MI, 1, O); |
12271 | | break; |
12272 | | case 286: |
12273 | | // A2_vcmphgt, A4_vcmphgti |
12274 | | O << " = vcmph.gt("; |
12275 | | printOperand(MI, 1, O); |
12276 | | break; |
12277 | | case 287: |
12278 | | // A2_vcmphgtu, A4_vcmphgtui |
12279 | | O << " = vcmph.gtu("; |
12280 | | printOperand(MI, 1, O); |
12281 | | break; |
12282 | | case 288: |
12283 | | // A2_vcmpweq, A4_vcmpweqi |
12284 | | O << " = vcmpw.eq("; |
12285 | | printOperand(MI, 1, O); |
12286 | | break; |
12287 | | case 289: |
12288 | | // A2_vcmpwgt, A4_vcmpwgti |
12289 | | O << " = vcmpw.gt("; |
12290 | | printOperand(MI, 1, O); |
12291 | | break; |
12292 | | case 290: |
12293 | | // A2_vcmpwgtu, A4_vcmpwgtui |
12294 | | O << " = vcmpw.gtu("; |
12295 | | printOperand(MI, 1, O); |
12296 | | break; |
12297 | | case 291: |
12298 | | // A2_vconj |
12299 | | O << " = vconj("; |
12300 | | printOperand(MI, 1, O); |
12301 | | O << "):sat"; |
12302 | | return; |
12303 | | break; |
12304 | | case 292: |
12305 | | // A2_vmaxuw |
12306 | | O << " = vmaxuw("; |
12307 | | printOperand(MI, 1, O); |
12308 | | O << ','; |
12309 | | printOperand(MI, 2, O); |
12310 | | O << ')'; |
12311 | | return; |
12312 | | break; |
12313 | | case 293: |
12314 | | // A2_vminuw |
12315 | | O << " = vminuw("; |
12316 | | printOperand(MI, 1, O); |
12317 | | O << ','; |
12318 | | printOperand(MI, 2, O); |
12319 | | O << ')'; |
12320 | | return; |
12321 | | break; |
12322 | | case 294: |
12323 | | // A2_vraddub |
12324 | | O << " = vraddub("; |
12325 | | printOperand(MI, 1, O); |
12326 | | O << ','; |
12327 | | printOperand(MI, 2, O); |
12328 | | O << ')'; |
12329 | | return; |
12330 | | break; |
12331 | | case 295: |
12332 | | // A2_vraddub_acc |
12333 | | O << " += vraddub("; |
12334 | | printOperand(MI, 2, O); |
12335 | | O << ','; |
12336 | | printOperand(MI, 3, O); |
12337 | | O << ')'; |
12338 | | return; |
12339 | | break; |
12340 | | case 296: |
12341 | | // A2_xor, A2_xorp, C2_xor, V6_pred_xor |
12342 | | O << " = xor("; |
12343 | | printOperand(MI, 1, O); |
12344 | | O << ','; |
12345 | | printOperand(MI, 2, O); |
12346 | | O << ')'; |
12347 | | return; |
12348 | | break; |
12349 | | case 297: |
12350 | | // A4_bitsplit, A4_bitspliti |
12351 | | O << " = bitsplit("; |
12352 | | printOperand(MI, 1, O); |
12353 | | break; |
12354 | | case 298: |
12355 | | // A4_cmpbeq, A4_cmpbeqi |
12356 | | O << " = cmpb.eq("; |
12357 | | printOperand(MI, 1, O); |
12358 | | break; |
12359 | | case 299: |
12360 | | // A4_cmpbgt, A4_cmpbgti |
12361 | | O << " = cmpb.gt("; |
12362 | | printOperand(MI, 1, O); |
12363 | | break; |
12364 | | case 300: |
12365 | | // A4_cmpbgtu, A4_cmpbgtui |
12366 | | O << " = cmpb.gtu("; |
12367 | | printOperand(MI, 1, O); |
12368 | | break; |
12369 | | case 301: |
12370 | | // A4_cmpheq, A4_cmpheqi |
12371 | | O << " = cmph.eq("; |
12372 | | printOperand(MI, 1, O); |
12373 | | break; |
12374 | | case 302: |
12375 | | // A4_cmphgt, A4_cmphgti |
12376 | | O << " = cmph.gt("; |
12377 | | printOperand(MI, 1, O); |
12378 | | break; |
12379 | | case 303: |
12380 | | // A4_cmphgtu, A4_cmphgtui |
12381 | | O << " = cmph.gtu("; |
12382 | | printOperand(MI, 1, O); |
12383 | | break; |
12384 | | case 304: |
12385 | | // A4_cround_ri, A4_cround_rr, A7_croundd_ri, A7_croundd_rr |
12386 | | O << " = cround("; |
12387 | | printOperand(MI, 1, O); |
12388 | | break; |
12389 | | case 305: |
12390 | | // A4_modwrapu |
12391 | | O << " = modwrap("; |
12392 | | printOperand(MI, 1, O); |
12393 | | O << ','; |
12394 | | printOperand(MI, 2, O); |
12395 | | O << ')'; |
12396 | | return; |
12397 | | break; |
12398 | | case 306: |
12399 | | // A4_rcmpneq, A4_rcmpneqi, C4_cmpneq, C4_cmpneqi |
12400 | | O << " = !cmp.eq("; |
12401 | | printOperand(MI, 1, O); |
12402 | | break; |
12403 | | case 307: |
12404 | | // A4_tlbmatch |
12405 | | O << " = tlbmatch("; |
12406 | | printOperand(MI, 1, O); |
12407 | | O << ','; |
12408 | | printOperand(MI, 2, O); |
12409 | | O << ')'; |
12410 | | return; |
12411 | | break; |
12412 | | case 308: |
12413 | | // A4_vcmpbeq_any |
12414 | | O << " = any8(vcmpb.eq("; |
12415 | | printOperand(MI, 1, O); |
12416 | | O << ','; |
12417 | | printOperand(MI, 2, O); |
12418 | | O << "))"; |
12419 | | return; |
12420 | | break; |
12421 | | case 309: |
12422 | | // A4_vcmpbgt, A4_vcmpbgti |
12423 | | O << " = vcmpb.gt("; |
12424 | | printOperand(MI, 1, O); |
12425 | | break; |
12426 | | case 310: |
12427 | | // A4_vrmaxh |
12428 | | O << " = vrmaxh("; |
12429 | | printOperand(MI, 2, O); |
12430 | | O << ','; |
12431 | | printOperand(MI, 3, O); |
12432 | | O << ')'; |
12433 | | return; |
12434 | | break; |
12435 | | case 311: |
12436 | | // A4_vrmaxuh |
12437 | | O << " = vrmaxuh("; |
12438 | | printOperand(MI, 2, O); |
12439 | | O << ','; |
12440 | | printOperand(MI, 3, O); |
12441 | | O << ')'; |
12442 | | return; |
12443 | | break; |
12444 | | case 312: |
12445 | | // A4_vrmaxuw |
12446 | | O << " = vrmaxuw("; |
12447 | | printOperand(MI, 2, O); |
12448 | | O << ','; |
12449 | | printOperand(MI, 3, O); |
12450 | | O << ')'; |
12451 | | return; |
12452 | | break; |
12453 | | case 313: |
12454 | | // A4_vrmaxw |
12455 | | O << " = vrmaxw("; |
12456 | | printOperand(MI, 2, O); |
12457 | | O << ','; |
12458 | | printOperand(MI, 3, O); |
12459 | | O << ')'; |
12460 | | return; |
12461 | | break; |
12462 | | case 314: |
12463 | | // A4_vrminh |
12464 | | O << " = vrminh("; |
12465 | | printOperand(MI, 2, O); |
12466 | | O << ','; |
12467 | | printOperand(MI, 3, O); |
12468 | | O << ')'; |
12469 | | return; |
12470 | | break; |
12471 | | case 315: |
12472 | | // A4_vrminuh |
12473 | | O << " = vrminuh("; |
12474 | | printOperand(MI, 2, O); |
12475 | | O << ','; |
12476 | | printOperand(MI, 3, O); |
12477 | | O << ')'; |
12478 | | return; |
12479 | | break; |
12480 | | case 316: |
12481 | | // A4_vrminuw |
12482 | | O << " = vrminuw("; |
12483 | | printOperand(MI, 2, O); |
12484 | | O << ','; |
12485 | | printOperand(MI, 3, O); |
12486 | | O << ')'; |
12487 | | return; |
12488 | | break; |
12489 | | case 317: |
12490 | | // A4_vrminw |
12491 | | O << " = vrminw("; |
12492 | | printOperand(MI, 2, O); |
12493 | | O << ','; |
12494 | | printOperand(MI, 3, O); |
12495 | | O << ')'; |
12496 | | return; |
12497 | | break; |
12498 | | case 318: |
12499 | | // A5_vaddhubs |
12500 | | O << " = vaddhub("; |
12501 | | printOperand(MI, 1, O); |
12502 | | O << ','; |
12503 | | printOperand(MI, 2, O); |
12504 | | O << "):sat"; |
12505 | | return; |
12506 | | break; |
12507 | | case 319: |
12508 | | // A6_vcmpbeq_notany |
12509 | | O << " = !any8(vcmpb.eq("; |
12510 | | printOperand(MI, 1, O); |
12511 | | O << ','; |
12512 | | printOperand(MI, 2, O); |
12513 | | O << "))"; |
12514 | | return; |
12515 | | break; |
12516 | | case 320: |
12517 | | // A7_clip |
12518 | | O << " = clip("; |
12519 | | printOperand(MI, 1, O); |
12520 | | O << ",#"; |
12521 | | printOperand(MI, 2, O); |
12522 | | O << ')'; |
12523 | | return; |
12524 | | break; |
12525 | | case 321: |
12526 | | // A7_vclip |
12527 | | O << " = vclip("; |
12528 | | printOperand(MI, 1, O); |
12529 | | O << ",#"; |
12530 | | printOperand(MI, 2, O); |
12531 | | O << ')'; |
12532 | | return; |
12533 | | break; |
12534 | | case 322: |
12535 | | // C2_all8 |
12536 | | O << " = all8("; |
12537 | | printOperand(MI, 1, O); |
12538 | | O << ')'; |
12539 | | return; |
12540 | | break; |
12541 | | case 323: |
12542 | | // C2_any8 |
12543 | | O << " = any8("; |
12544 | | printOperand(MI, 1, O); |
12545 | | O << ')'; |
12546 | | return; |
12547 | | break; |
12548 | | case 324: |
12549 | | // C2_bitsclr, C2_bitsclri |
12550 | | O << " = bitsclr("; |
12551 | | printOperand(MI, 1, O); |
12552 | | break; |
12553 | | case 325: |
12554 | | // C2_bitsset |
12555 | | O << " = bitsset("; |
12556 | | printOperand(MI, 1, O); |
12557 | | O << ','; |
12558 | | printOperand(MI, 2, O); |
12559 | | O << ')'; |
12560 | | return; |
12561 | | break; |
12562 | | case 326: |
12563 | | // C2_cmpgt, C2_cmpgti, C2_cmpgtp |
12564 | | O << " = cmp.gt("; |
12565 | | printOperand(MI, 1, O); |
12566 | | break; |
12567 | | case 327: |
12568 | | // C2_cmpgtu, C2_cmpgtui, C2_cmpgtup |
12569 | | O << " = cmp.gtu("; |
12570 | | printOperand(MI, 1, O); |
12571 | | break; |
12572 | | case 328: |
12573 | | // C2_mask |
12574 | | O << " = mask("; |
12575 | | printOperand(MI, 1, O); |
12576 | | O << ')'; |
12577 | | return; |
12578 | | break; |
12579 | | case 329: |
12580 | | // C2_mux, C2_muxii, C2_muxir, C2_muxri |
12581 | | O << " = mux("; |
12582 | | printOperand(MI, 1, O); |
12583 | | break; |
12584 | | case 330: |
12585 | | // C2_vitpack |
12586 | | O << " = vitpack("; |
12587 | | printOperand(MI, 1, O); |
12588 | | O << ','; |
12589 | | printOperand(MI, 2, O); |
12590 | | O << ')'; |
12591 | | return; |
12592 | | break; |
12593 | | case 331: |
12594 | | // C2_vmux, V6_vmux |
12595 | | O << " = vmux("; |
12596 | | printOperand(MI, 1, O); |
12597 | | O << ','; |
12598 | | printOperand(MI, 2, O); |
12599 | | O << ','; |
12600 | | printOperand(MI, 3, O); |
12601 | | O << ')'; |
12602 | | return; |
12603 | | break; |
12604 | | case 332: |
12605 | | // C4_addipc |
12606 | | O << " = add(pc,#"; |
12607 | | printOperand(MI, 1, O); |
12608 | | O << ')'; |
12609 | | return; |
12610 | | break; |
12611 | | case 333: |
12612 | | // C4_cmplte, C4_cmpltei |
12613 | | O << " = !cmp.gt("; |
12614 | | printOperand(MI, 1, O); |
12615 | | break; |
12616 | | case 334: |
12617 | | // C4_cmplteu, C4_cmplteui |
12618 | | O << " = !cmp.gtu("; |
12619 | | printOperand(MI, 1, O); |
12620 | | break; |
12621 | | case 335: |
12622 | | // C4_fastcorner9 |
12623 | | O << " = fastcorner9("; |
12624 | | printOperand(MI, 1, O); |
12625 | | O << ','; |
12626 | | printOperand(MI, 2, O); |
12627 | | O << ')'; |
12628 | | return; |
12629 | | break; |
12630 | | case 336: |
12631 | | // C4_fastcorner9_not |
12632 | | O << " = !fastcorner9("; |
12633 | | printOperand(MI, 1, O); |
12634 | | O << ','; |
12635 | | printOperand(MI, 2, O); |
12636 | | O << ')'; |
12637 | | return; |
12638 | | break; |
12639 | | case 337: |
12640 | | // C4_nbitsclr, C4_nbitsclri |
12641 | | O << " = !bitsclr("; |
12642 | | printOperand(MI, 1, O); |
12643 | | break; |
12644 | | case 338: |
12645 | | // C4_nbitsset |
12646 | | O << " = !bitsset("; |
12647 | | printOperand(MI, 1, O); |
12648 | | O << ','; |
12649 | | printOperand(MI, 2, O); |
12650 | | O << ')'; |
12651 | | return; |
12652 | | break; |
12653 | | case 339: |
12654 | | // CONST32 |
12655 | | O << " = CONST32(#"; |
12656 | | printOperand(MI, 1, O); |
12657 | | O << ')'; |
12658 | | return; |
12659 | | break; |
12660 | | case 340: |
12661 | | // CONST64 |
12662 | | O << " = CONST64(#"; |
12663 | | printOperand(MI, 1, O); |
12664 | | O << ')'; |
12665 | | return; |
12666 | | break; |
12667 | | case 341: |
12668 | | // F2_conv_d2df |
12669 | | O << " = convert_d2df("; |
12670 | | printOperand(MI, 1, O); |
12671 | | O << ')'; |
12672 | | return; |
12673 | | break; |
12674 | | case 342: |
12675 | | // F2_conv_d2sf |
12676 | | O << " = convert_d2sf("; |
12677 | | printOperand(MI, 1, O); |
12678 | | O << ')'; |
12679 | | return; |
12680 | | break; |
12681 | | case 343: |
12682 | | // F2_conv_df2d, F2_conv_df2d_chop |
12683 | | O << " = convert_df2d("; |
12684 | | printOperand(MI, 1, O); |
12685 | | break; |
12686 | | case 344: |
12687 | | // F2_conv_df2sf |
12688 | | O << " = convert_df2sf("; |
12689 | | printOperand(MI, 1, O); |
12690 | | O << ')'; |
12691 | | return; |
12692 | | break; |
12693 | | case 345: |
12694 | | // F2_conv_df2ud, F2_conv_df2ud_chop |
12695 | | O << " = convert_df2ud("; |
12696 | | printOperand(MI, 1, O); |
12697 | | break; |
12698 | | case 346: |
12699 | | // F2_conv_df2uw, F2_conv_df2uw_chop |
12700 | | O << " = convert_df2uw("; |
12701 | | printOperand(MI, 1, O); |
12702 | | break; |
12703 | | case 347: |
12704 | | // F2_conv_df2w, F2_conv_df2w_chop |
12705 | | O << " = convert_df2w("; |
12706 | | printOperand(MI, 1, O); |
12707 | | break; |
12708 | | case 348: |
12709 | | // F2_conv_sf2d, F2_conv_sf2d_chop |
12710 | | O << " = convert_sf2d("; |
12711 | | printOperand(MI, 1, O); |
12712 | | break; |
12713 | | case 349: |
12714 | | // F2_conv_sf2df |
12715 | | O << " = convert_sf2df("; |
12716 | | printOperand(MI, 1, O); |
12717 | | O << ')'; |
12718 | | return; |
12719 | | break; |
12720 | | case 350: |
12721 | | // F2_conv_sf2ud, F2_conv_sf2ud_chop |
12722 | | O << " = convert_sf2ud("; |
12723 | | printOperand(MI, 1, O); |
12724 | | break; |
12725 | | case 351: |
12726 | | // F2_conv_sf2uw, F2_conv_sf2uw_chop |
12727 | | O << " = convert_sf2uw("; |
12728 | | printOperand(MI, 1, O); |
12729 | | break; |
12730 | | case 352: |
12731 | | // F2_conv_sf2w, F2_conv_sf2w_chop |
12732 | | O << " = convert_sf2w("; |
12733 | | printOperand(MI, 1, O); |
12734 | | break; |
12735 | | case 353: |
12736 | | // F2_conv_ud2df |
12737 | | O << " = convert_ud2df("; |
12738 | | printOperand(MI, 1, O); |
12739 | | O << ')'; |
12740 | | return; |
12741 | | break; |
12742 | | case 354: |
12743 | | // F2_conv_ud2sf |
12744 | | O << " = convert_ud2sf("; |
12745 | | printOperand(MI, 1, O); |
12746 | | O << ')'; |
12747 | | return; |
12748 | | break; |
12749 | | case 355: |
12750 | | // F2_conv_uw2df |
12751 | | O << " = convert_uw2df("; |
12752 | | printOperand(MI, 1, O); |
12753 | | O << ')'; |
12754 | | return; |
12755 | | break; |
12756 | | case 356: |
12757 | | // F2_conv_uw2sf |
12758 | | O << " = convert_uw2sf("; |
12759 | | printOperand(MI, 1, O); |
12760 | | O << ')'; |
12761 | | return; |
12762 | | break; |
12763 | | case 357: |
12764 | | // F2_conv_w2df |
12765 | | O << " = convert_w2df("; |
12766 | | printOperand(MI, 1, O); |
12767 | | O << ')'; |
12768 | | return; |
12769 | | break; |
12770 | | case 358: |
12771 | | // F2_conv_w2sf |
12772 | | O << " = convert_w2sf("; |
12773 | | printOperand(MI, 1, O); |
12774 | | O << ')'; |
12775 | | return; |
12776 | | break; |
12777 | | case 359: |
12778 | | // F2_dfadd |
12779 | | O << " = dfadd("; |
12780 | | printOperand(MI, 1, O); |
12781 | | O << ','; |
12782 | | printOperand(MI, 2, O); |
12783 | | O << ')'; |
12784 | | return; |
12785 | | break; |
12786 | | case 360: |
12787 | | // F2_dfclass |
12788 | | O << " = dfclass("; |
12789 | | printOperand(MI, 1, O); |
12790 | | O << ",#"; |
12791 | | printOperand(MI, 2, O); |
12792 | | O << ')'; |
12793 | | return; |
12794 | | break; |
12795 | | case 361: |
12796 | | // F2_dfcmpeq |
12797 | | O << " = dfcmp.eq("; |
12798 | | printOperand(MI, 1, O); |
12799 | | O << ','; |
12800 | | printOperand(MI, 2, O); |
12801 | | O << ')'; |
12802 | | return; |
12803 | | break; |
12804 | | case 362: |
12805 | | // F2_dfcmpge |
12806 | | O << " = dfcmp.ge("; |
12807 | | printOperand(MI, 1, O); |
12808 | | O << ','; |
12809 | | printOperand(MI, 2, O); |
12810 | | O << ')'; |
12811 | | return; |
12812 | | break; |
12813 | | case 363: |
12814 | | // F2_dfcmpgt |
12815 | | O << " = dfcmp.gt("; |
12816 | | printOperand(MI, 1, O); |
12817 | | O << ','; |
12818 | | printOperand(MI, 2, O); |
12819 | | O << ')'; |
12820 | | return; |
12821 | | break; |
12822 | | case 364: |
12823 | | // F2_dfcmpuo |
12824 | | O << " = dfcmp.uo("; |
12825 | | printOperand(MI, 1, O); |
12826 | | O << ','; |
12827 | | printOperand(MI, 2, O); |
12828 | | O << ')'; |
12829 | | return; |
12830 | | break; |
12831 | | case 365: |
12832 | | // F2_dfimm_n, F2_dfimm_p |
12833 | | O << " = dfmake(#"; |
12834 | | printOperand(MI, 1, O); |
12835 | | break; |
12836 | | case 366: |
12837 | | // F2_dfmax |
12838 | | O << " = dfmax("; |
12839 | | printOperand(MI, 1, O); |
12840 | | O << ','; |
12841 | | printOperand(MI, 2, O); |
12842 | | O << ')'; |
12843 | | return; |
12844 | | break; |
12845 | | case 367: |
12846 | | // F2_dfmin |
12847 | | O << " = dfmin("; |
12848 | | printOperand(MI, 1, O); |
12849 | | O << ','; |
12850 | | printOperand(MI, 2, O); |
12851 | | O << ')'; |
12852 | | return; |
12853 | | break; |
12854 | | case 368: |
12855 | | // F2_dfmpyfix |
12856 | | O << " = dfmpyfix("; |
12857 | | printOperand(MI, 1, O); |
12858 | | O << ','; |
12859 | | printOperand(MI, 2, O); |
12860 | | O << ')'; |
12861 | | return; |
12862 | | break; |
12863 | | case 369: |
12864 | | // F2_dfmpyhh |
12865 | | O << " += dfmpyhh("; |
12866 | | printOperand(MI, 2, O); |
12867 | | O << ','; |
12868 | | printOperand(MI, 3, O); |
12869 | | O << ')'; |
12870 | | return; |
12871 | | break; |
12872 | | case 370: |
12873 | | // F2_dfmpylh |
12874 | | O << " += dfmpylh("; |
12875 | | printOperand(MI, 2, O); |
12876 | | O << ','; |
12877 | | printOperand(MI, 3, O); |
12878 | | O << ')'; |
12879 | | return; |
12880 | | break; |
12881 | | case 371: |
12882 | | // F2_dfmpyll |
12883 | | O << " = dfmpyll("; |
12884 | | printOperand(MI, 1, O); |
12885 | | O << ','; |
12886 | | printOperand(MI, 2, O); |
12887 | | O << ')'; |
12888 | | return; |
12889 | | break; |
12890 | | case 372: |
12891 | | // F2_dfsub |
12892 | | O << " = dfsub("; |
12893 | | printOperand(MI, 1, O); |
12894 | | O << ','; |
12895 | | printOperand(MI, 2, O); |
12896 | | O << ')'; |
12897 | | return; |
12898 | | break; |
12899 | | case 373: |
12900 | | // F2_sfadd |
12901 | | O << " = sfadd("; |
12902 | | printOperand(MI, 1, O); |
12903 | | O << ','; |
12904 | | printOperand(MI, 2, O); |
12905 | | O << ')'; |
12906 | | return; |
12907 | | break; |
12908 | | case 374: |
12909 | | // F2_sfclass |
12910 | | O << " = sfclass("; |
12911 | | printOperand(MI, 1, O); |
12912 | | O << ",#"; |
12913 | | printOperand(MI, 2, O); |
12914 | | O << ')'; |
12915 | | return; |
12916 | | break; |
12917 | | case 375: |
12918 | | // F2_sfcmpeq |
12919 | | O << " = sfcmp.eq("; |
12920 | | printOperand(MI, 1, O); |
12921 | | O << ','; |
12922 | | printOperand(MI, 2, O); |
12923 | | O << ')'; |
12924 | | return; |
12925 | | break; |
12926 | | case 376: |
12927 | | // F2_sfcmpge |
12928 | | O << " = sfcmp.ge("; |
12929 | | printOperand(MI, 1, O); |
12930 | | O << ','; |
12931 | | printOperand(MI, 2, O); |
12932 | | O << ')'; |
12933 | | return; |
12934 | | break; |
12935 | | case 377: |
12936 | | // F2_sfcmpgt |
12937 | | O << " = sfcmp.gt("; |
12938 | | printOperand(MI, 1, O); |
12939 | | O << ','; |
12940 | | printOperand(MI, 2, O); |
12941 | | O << ')'; |
12942 | | return; |
12943 | | break; |
12944 | | case 378: |
12945 | | // F2_sfcmpuo |
12946 | | O << " = sfcmp.uo("; |
12947 | | printOperand(MI, 1, O); |
12948 | | O << ','; |
12949 | | printOperand(MI, 2, O); |
12950 | | O << ')'; |
12951 | | return; |
12952 | | break; |
12953 | | case 379: |
12954 | | // F2_sffixupd |
12955 | | O << " = sffixupd("; |
12956 | | printOperand(MI, 1, O); |
12957 | | O << ','; |
12958 | | printOperand(MI, 2, O); |
12959 | | O << ')'; |
12960 | | return; |
12961 | | break; |
12962 | | case 380: |
12963 | | // F2_sffixupn |
12964 | | O << " = sffixupn("; |
12965 | | printOperand(MI, 1, O); |
12966 | | O << ','; |
12967 | | printOperand(MI, 2, O); |
12968 | | O << ')'; |
12969 | | return; |
12970 | | break; |
12971 | | case 381: |
12972 | | // F2_sffixupr |
12973 | | O << " = sffixupr("; |
12974 | | printOperand(MI, 1, O); |
12975 | | O << ')'; |
12976 | | return; |
12977 | | break; |
12978 | | case 382: |
12979 | | // F2_sffma, F2_sffma_lib, F2_sffma_sc |
12980 | | O << " += sfmpy("; |
12981 | | printOperand(MI, 2, O); |
12982 | | O << ','; |
12983 | | printOperand(MI, 3, O); |
12984 | | break; |
12985 | | case 383: |
12986 | | // F2_sffms, F2_sffms_lib |
12987 | | O << " -= sfmpy("; |
12988 | | printOperand(MI, 2, O); |
12989 | | O << ','; |
12990 | | printOperand(MI, 3, O); |
12991 | | break; |
12992 | | case 384: |
12993 | | // F2_sfimm_n, F2_sfimm_p |
12994 | | O << " = sfmake(#"; |
12995 | | printOperand(MI, 1, O); |
12996 | | break; |
12997 | | case 385: |
12998 | | // F2_sfmax |
12999 | | O << " = sfmax("; |
13000 | | printOperand(MI, 1, O); |
13001 | | O << ','; |
13002 | | printOperand(MI, 2, O); |
13003 | | O << ')'; |
13004 | | return; |
13005 | | break; |
13006 | | case 386: |
13007 | | // F2_sfmin |
13008 | | O << " = sfmin("; |
13009 | | printOperand(MI, 1, O); |
13010 | | O << ','; |
13011 | | printOperand(MI, 2, O); |
13012 | | O << ')'; |
13013 | | return; |
13014 | | break; |
13015 | | case 387: |
13016 | | // F2_sfmpy |
13017 | | O << " = sfmpy("; |
13018 | | printOperand(MI, 1, O); |
13019 | | O << ','; |
13020 | | printOperand(MI, 2, O); |
13021 | | O << ')'; |
13022 | | return; |
13023 | | break; |
13024 | | case 388: |
13025 | | // F2_sfsub |
13026 | | O << " = sfsub("; |
13027 | | printOperand(MI, 1, O); |
13028 | | O << ','; |
13029 | | printOperand(MI, 2, O); |
13030 | | O << ')'; |
13031 | | return; |
13032 | | break; |
13033 | | case 389: |
13034 | | // J2_callf, J2_callt |
13035 | | O << ") call "; |
13036 | | printBrtarget(MI, 1, O); |
13037 | | return; |
13038 | | break; |
13039 | | case 390: |
13040 | | // J2_callrf, J2_callrt |
13041 | | O << ") callr "; |
13042 | | printOperand(MI, 1, O); |
13043 | | return; |
13044 | | break; |
13045 | | case 391: |
13046 | | // J2_jumpf, J2_jumpt |
13047 | | O << ") jump:nt "; |
13048 | | printBrtarget(MI, 1, O); |
13049 | | return; |
13050 | | break; |
13051 | | case 392: |
13052 | | // J2_jumpfnew, J2_jumptnew |
13053 | | O << ".new) jump:nt "; |
13054 | | printBrtarget(MI, 1, O); |
13055 | | return; |
13056 | | break; |
13057 | | case 393: |
13058 | | // J2_jumpfnewpt, J2_jumptnewpt |
13059 | | O << ".new) jump:t "; |
13060 | | printBrtarget(MI, 1, O); |
13061 | | return; |
13062 | | break; |
13063 | | case 394: |
13064 | | // J2_jumpfpt, J2_jumptpt |
13065 | | O << ") jump:t "; |
13066 | | printBrtarget(MI, 1, O); |
13067 | | return; |
13068 | | break; |
13069 | | case 395: |
13070 | | // J2_jumprf, J2_jumprt, PS_jmpretf, PS_jmprett |
13071 | | O << ") jumpr:nt "; |
13072 | | printOperand(MI, 1, O); |
13073 | | return; |
13074 | | break; |
13075 | | case 396: |
13076 | | // J2_jumprfnew, J2_jumprtnew, PS_jmpretfnew, PS_jmprettnew |
13077 | | O << ".new) jumpr:nt "; |
13078 | | printOperand(MI, 1, O); |
13079 | | return; |
13080 | | break; |
13081 | | case 397: |
13082 | | // J2_jumprfnewpt, J2_jumprtnewpt, PS_jmpretfnewpt, PS_jmprettnewpt |
13083 | | O << ".new) jumpr:t "; |
13084 | | printOperand(MI, 1, O); |
13085 | | return; |
13086 | | break; |
13087 | | case 398: |
13088 | | // J2_jumprfpt, J2_jumprtpt |
13089 | | O << ") jumpr:t "; |
13090 | | printOperand(MI, 1, O); |
13091 | | return; |
13092 | | break; |
13093 | | case 399: |
13094 | | // J2_jumprgtez |
13095 | | O << ">=#0) jump:nt "; |
13096 | | printBrtarget(MI, 1, O); |
13097 | | return; |
13098 | | break; |
13099 | | case 400: |
13100 | | // J2_jumprgtezpt |
13101 | | O << ">=#0) jump:t "; |
13102 | | printBrtarget(MI, 1, O); |
13103 | | return; |
13104 | | break; |
13105 | | case 401: |
13106 | | // J2_jumprltez |
13107 | | O << "<=#0) jump:nt "; |
13108 | | printBrtarget(MI, 1, O); |
13109 | | return; |
13110 | | break; |
13111 | | case 402: |
13112 | | // J2_jumprltezpt |
13113 | | O << "<=#0) jump:t "; |
13114 | | printBrtarget(MI, 1, O); |
13115 | | return; |
13116 | | break; |
13117 | | case 403: |
13118 | | // J2_jumprnz |
13119 | | O << "==#0) jump:nt "; |
13120 | | printBrtarget(MI, 1, O); |
13121 | | return; |
13122 | | break; |
13123 | | case 404: |
13124 | | // J2_jumprnzpt |
13125 | | O << "==#0) jump:t "; |
13126 | | printBrtarget(MI, 1, O); |
13127 | | return; |
13128 | | break; |
13129 | | case 405: |
13130 | | // J2_jumprz |
13131 | | O << "!=#0) jump:nt "; |
13132 | | printBrtarget(MI, 1, O); |
13133 | | return; |
13134 | | break; |
13135 | | case 406: |
13136 | | // J2_jumprzpt |
13137 | | O << "!=#0) jump:t "; |
13138 | | printBrtarget(MI, 1, O); |
13139 | | return; |
13140 | | break; |
13141 | | case 407: |
13142 | | // J4_cmpeq_f_jumpnv_nt, J4_cmpeq_f_jumpnv_t, J4_cmpeq_t_jumpnv_nt, J4_cm... |
13143 | | O << ".new,"; |
13144 | | printOperand(MI, 1, O); |
13145 | | break; |
13146 | | case 408: |
13147 | | // J4_cmpeqi_f_jumpnv_nt, J4_cmpeqi_f_jumpnv_t, J4_cmpeqi_t_jumpnv_nt, J4... |
13148 | | O << ".new,#"; |
13149 | | printOperand(MI, 1, O); |
13150 | | break; |
13151 | | case 409: |
13152 | | // J4_tstbit0_f_jumpnv_nt, J4_tstbit0_t_jumpnv_nt |
13153 | | O << ".new,#0)) jump:nt "; |
13154 | | printBrtarget(MI, 1, O); |
13155 | | return; |
13156 | | break; |
13157 | | case 410: |
13158 | | // J4_tstbit0_f_jumpnv_t, J4_tstbit0_t_jumpnv_t |
13159 | | O << ".new,#0)) jump:t "; |
13160 | | printBrtarget(MI, 1, O); |
13161 | | return; |
13162 | | break; |
13163 | | case 411: |
13164 | | // J4_tstbit0_fp0_jump_nt |
13165 | | O << ",#0); if (!p0.new) jump:nt "; |
13166 | | printBrtarget(MI, 1, O); |
13167 | | return; |
13168 | | break; |
13169 | | case 412: |
13170 | | // J4_tstbit0_fp0_jump_t |
13171 | | O << ",#0); if (!p0.new) jump:t "; |
13172 | | printBrtarget(MI, 1, O); |
13173 | | return; |
13174 | | break; |
13175 | | case 413: |
13176 | | // J4_tstbit0_fp1_jump_nt |
13177 | | O << ",#0); if (!p1.new) jump:nt "; |
13178 | | printBrtarget(MI, 1, O); |
13179 | | return; |
13180 | | break; |
13181 | | case 414: |
13182 | | // J4_tstbit0_fp1_jump_t |
13183 | | O << ",#0); if (!p1.new) jump:t "; |
13184 | | printBrtarget(MI, 1, O); |
13185 | | return; |
13186 | | break; |
13187 | | case 415: |
13188 | | // J4_tstbit0_tp0_jump_nt |
13189 | | O << ",#0); if (p0.new) jump:nt "; |
13190 | | printBrtarget(MI, 1, O); |
13191 | | return; |
13192 | | break; |
13193 | | case 416: |
13194 | | // J4_tstbit0_tp0_jump_t |
13195 | | O << ",#0); if (p0.new) jump:t "; |
13196 | | printBrtarget(MI, 1, O); |
13197 | | return; |
13198 | | break; |
13199 | | case 417: |
13200 | | // J4_tstbit0_tp1_jump_nt |
13201 | | O << ",#0); if (p1.new) jump:nt "; |
13202 | | printBrtarget(MI, 1, O); |
13203 | | return; |
13204 | | break; |
13205 | | case 418: |
13206 | | // J4_tstbit0_tp1_jump_t |
13207 | | O << ",#0); if (p1.new) jump:t "; |
13208 | | printBrtarget(MI, 1, O); |
13209 | | return; |
13210 | | break; |
13211 | | case 419: |
13212 | | // L2_loadrbgp |
13213 | | O << " = memb(gp+#"; |
13214 | | printOperand(MI, 1, O); |
13215 | | O << ')'; |
13216 | | return; |
13217 | | break; |
13218 | | case 420: |
13219 | | // L2_loadrdgp |
13220 | | O << " = memd(gp+#"; |
13221 | | printOperand(MI, 1, O); |
13222 | | O << ')'; |
13223 | | return; |
13224 | | break; |
13225 | | case 421: |
13226 | | // L2_loadrhgp |
13227 | | O << " = memh(gp+#"; |
13228 | | printOperand(MI, 1, O); |
13229 | | O << ')'; |
13230 | | return; |
13231 | | break; |
13232 | | case 422: |
13233 | | // L2_loadrigp |
13234 | | O << " = memw(gp+#"; |
13235 | | printOperand(MI, 1, O); |
13236 | | O << ')'; |
13237 | | return; |
13238 | | break; |
13239 | | case 423: |
13240 | | // L2_loadrubgp |
13241 | | O << " = memub(gp+#"; |
13242 | | printOperand(MI, 1, O); |
13243 | | O << ')'; |
13244 | | return; |
13245 | | break; |
13246 | | case 424: |
13247 | | // L2_loadruhgp |
13248 | | O << " = memuh(gp+#"; |
13249 | | printOperand(MI, 1, O); |
13250 | | O << ')'; |
13251 | | return; |
13252 | | break; |
13253 | | case 425: |
13254 | | // L2_loadw_aq |
13255 | | O << " = memw_aq("; |
13256 | | printOperand(MI, 1, O); |
13257 | | O << ')'; |
13258 | | return; |
13259 | | break; |
13260 | | case 426: |
13261 | | // L2_loadw_locked |
13262 | | O << " = memw_locked("; |
13263 | | printOperand(MI, 1, O); |
13264 | | O << ')'; |
13265 | | return; |
13266 | | break; |
13267 | | case 427: |
13268 | | // L4_loadd_aq |
13269 | | O << " = memd_aq("; |
13270 | | printOperand(MI, 1, O); |
13271 | | O << ')'; |
13272 | | return; |
13273 | | break; |
13274 | | case 428: |
13275 | | // L4_loadd_locked |
13276 | | O << " = memd_locked("; |
13277 | | printOperand(MI, 1, O); |
13278 | | O << ')'; |
13279 | | return; |
13280 | | break; |
13281 | | case 429: |
13282 | | // L4_loadw_phys |
13283 | | O << " = memw_phys("; |
13284 | | printOperand(MI, 1, O); |
13285 | | O << ','; |
13286 | | printOperand(MI, 2, O); |
13287 | | O << ')'; |
13288 | | return; |
13289 | | break; |
13290 | | case 430: |
13291 | | // L4_return |
13292 | | O << " = dealloc_return("; |
13293 | | printOperand(MI, 1, O); |
13294 | | O << "):raw"; |
13295 | | return; |
13296 | | break; |
13297 | | case 431: |
13298 | | // M2_acci, M2_accii |
13299 | | O << " += add("; |
13300 | | printOperand(MI, 2, O); |
13301 | | break; |
13302 | | case 432: |
13303 | | // M2_cmaci_s0 |
13304 | | O << " += cmpyi("; |
13305 | | printOperand(MI, 2, O); |
13306 | | O << ','; |
13307 | | printOperand(MI, 3, O); |
13308 | | O << ')'; |
13309 | | return; |
13310 | | break; |
13311 | | case 433: |
13312 | | // M2_cmacr_s0 |
13313 | | O << " += cmpyr("; |
13314 | | printOperand(MI, 2, O); |
13315 | | O << ','; |
13316 | | printOperand(MI, 3, O); |
13317 | | O << ')'; |
13318 | | return; |
13319 | | break; |
13320 | | case 434: |
13321 | | // M2_cmacs_s0, M2_cmacs_s1, M2_cmacsc_s0, M2_cmacsc_s1 |
13322 | | O << " += cmpy("; |
13323 | | printOperand(MI, 2, O); |
13324 | | O << ','; |
13325 | | printOperand(MI, 3, O); |
13326 | | break; |
13327 | | case 435: |
13328 | | // M2_cmpyi_s0 |
13329 | | O << " = cmpyi("; |
13330 | | printOperand(MI, 1, O); |
13331 | | O << ','; |
13332 | | printOperand(MI, 2, O); |
13333 | | O << ')'; |
13334 | | return; |
13335 | | break; |
13336 | | case 436: |
13337 | | // M2_cmpyr_s0 |
13338 | | O << " = cmpyr("; |
13339 | | printOperand(MI, 1, O); |
13340 | | O << ','; |
13341 | | printOperand(MI, 2, O); |
13342 | | O << ')'; |
13343 | | return; |
13344 | | break; |
13345 | | case 437: |
13346 | | // M2_cmpyrs_s0, M2_cmpyrs_s1, M2_cmpyrsc_s0, M2_cmpyrsc_s1, M2_cmpys_s0,... |
13347 | | O << " = cmpy("; |
13348 | | printOperand(MI, 1, O); |
13349 | | O << ','; |
13350 | | printOperand(MI, 2, O); |
13351 | | break; |
13352 | | case 438: |
13353 | | // M2_cnacs_s0, M2_cnacs_s1, M2_cnacsc_s0, M2_cnacsc_s1 |
13354 | | O << " -= cmpy("; |
13355 | | printOperand(MI, 2, O); |
13356 | | O << ','; |
13357 | | printOperand(MI, 3, O); |
13358 | | break; |
13359 | | case 439: |
13360 | | // M2_dpmpyss_acc_s0, M2_mpy_acc_hh_s0, M2_mpy_acc_hh_s1, M2_mpy_acc_hl_s... |
13361 | | O << " += mpy("; |
13362 | | printOperand(MI, 2, O); |
13363 | | break; |
13364 | | case 440: |
13365 | | // M2_dpmpyss_nac_s0, M2_mpy_nac_hh_s0, M2_mpy_nac_hh_s1, M2_mpy_nac_hl_s... |
13366 | | O << " -= mpy("; |
13367 | | printOperand(MI, 2, O); |
13368 | | break; |
13369 | | case 441: |
13370 | | // M2_dpmpyss_rnd_s0, M2_dpmpyss_s0, M2_hmmpyh_rs1, M2_hmmpyh_s1, M2_hmmp... |
13371 | | O << " = mpy("; |
13372 | | printOperand(MI, 1, O); |
13373 | | break; |
13374 | | case 442: |
13375 | | // M2_dpmpyuu_acc_s0, M2_mpyu_acc_hh_s0, M2_mpyu_acc_hh_s1, M2_mpyu_acc_h... |
13376 | | O << " += mpyu("; |
13377 | | printOperand(MI, 2, O); |
13378 | | break; |
13379 | | case 443: |
13380 | | // M2_dpmpyuu_nac_s0, M2_mpyu_nac_hh_s0, M2_mpyu_nac_hh_s1, M2_mpyu_nac_h... |
13381 | | O << " -= mpyu("; |
13382 | | printOperand(MI, 2, O); |
13383 | | break; |
13384 | | case 444: |
13385 | | // M2_dpmpyuu_s0, M2_mpyu_hh_s0, M2_mpyu_hh_s1, M2_mpyu_hl_s0, M2_mpyu_hl... |
13386 | | O << " = mpyu("; |
13387 | | printOperand(MI, 1, O); |
13388 | | break; |
13389 | | case 445: |
13390 | | // M2_maci, M2_macsip |
13391 | | O << " += mpyi("; |
13392 | | printOperand(MI, 2, O); |
13393 | | break; |
13394 | | case 446: |
13395 | | // M2_macsin, M2_mnaci |
13396 | | O << " -= mpyi("; |
13397 | | printOperand(MI, 2, O); |
13398 | | break; |
13399 | | case 447: |
13400 | | // M2_mmachs_rs0, M2_mmachs_rs1, M2_mmachs_s0, M2_mmachs_s1 |
13401 | | O << " += vmpywoh("; |
13402 | | printOperand(MI, 2, O); |
13403 | | O << ','; |
13404 | | printOperand(MI, 3, O); |
13405 | | break; |
13406 | | case 448: |
13407 | | // M2_mmacls_rs0, M2_mmacls_rs1, M2_mmacls_s0, M2_mmacls_s1 |
13408 | | O << " += vmpyweh("; |
13409 | | printOperand(MI, 2, O); |
13410 | | O << ','; |
13411 | | printOperand(MI, 3, O); |
13412 | | break; |
13413 | | case 449: |
13414 | | // M2_mmacuhs_rs0, M2_mmacuhs_rs1, M2_mmacuhs_s0, M2_mmacuhs_s1 |
13415 | | O << " += vmpywouh("; |
13416 | | printOperand(MI, 2, O); |
13417 | | O << ','; |
13418 | | printOperand(MI, 3, O); |
13419 | | break; |
13420 | | case 450: |
13421 | | // M2_mmaculs_rs0, M2_mmaculs_rs1, M2_mmaculs_s0, M2_mmaculs_s1 |
13422 | | O << " += vmpyweuh("; |
13423 | | printOperand(MI, 2, O); |
13424 | | O << ','; |
13425 | | printOperand(MI, 3, O); |
13426 | | break; |
13427 | | case 451: |
13428 | | // M2_mmpyh_rs0, M2_mmpyh_rs1, M2_mmpyh_s0, M2_mmpyh_s1 |
13429 | | O << " = vmpywoh("; |
13430 | | printOperand(MI, 1, O); |
13431 | | O << ','; |
13432 | | printOperand(MI, 2, O); |
13433 | | break; |
13434 | | case 452: |
13435 | | // M2_mmpyl_rs0, M2_mmpyl_rs1, M2_mmpyl_s0, M2_mmpyl_s1 |
13436 | | O << " = vmpyweh("; |
13437 | | printOperand(MI, 1, O); |
13438 | | O << ','; |
13439 | | printOperand(MI, 2, O); |
13440 | | break; |
13441 | | case 453: |
13442 | | // M2_mmpyuh_rs0, M2_mmpyuh_rs1, M2_mmpyuh_s0, M2_mmpyuh_s1 |
13443 | | O << " = vmpywouh("; |
13444 | | printOperand(MI, 1, O); |
13445 | | O << ','; |
13446 | | printOperand(MI, 2, O); |
13447 | | break; |
13448 | | case 454: |
13449 | | // M2_mmpyul_rs0, M2_mmpyul_rs1, M2_mmpyul_s0, M2_mmpyul_s1 |
13450 | | O << " = vmpyweuh("; |
13451 | | printOperand(MI, 1, O); |
13452 | | O << ','; |
13453 | | printOperand(MI, 2, O); |
13454 | | break; |
13455 | | case 455: |
13456 | | // M2_mpysin |
13457 | | O << " = -mpyi("; |
13458 | | printOperand(MI, 1, O); |
13459 | | O << ",#"; |
13460 | | printOperand(MI, 2, O); |
13461 | | O << ')'; |
13462 | | return; |
13463 | | break; |
13464 | | case 456: |
13465 | | // M2_mpysip |
13466 | | O << " = +mpyi("; |
13467 | | printOperand(MI, 1, O); |
13468 | | O << ",#"; |
13469 | | printOperand(MI, 2, O); |
13470 | | O << ')'; |
13471 | | return; |
13472 | | break; |
13473 | | case 457: |
13474 | | // M2_mpysu_up |
13475 | | O << " = mpysu("; |
13476 | | printOperand(MI, 1, O); |
13477 | | O << ','; |
13478 | | printOperand(MI, 2, O); |
13479 | | O << ')'; |
13480 | | return; |
13481 | | break; |
13482 | | case 458: |
13483 | | // M2_nacci, M2_naccii |
13484 | | O << " -= add("; |
13485 | | printOperand(MI, 2, O); |
13486 | | break; |
13487 | | case 459: |
13488 | | // M2_subacc |
13489 | | O << " += sub("; |
13490 | | printOperand(MI, 2, O); |
13491 | | O << ','; |
13492 | | printOperand(MI, 3, O); |
13493 | | O << ')'; |
13494 | | return; |
13495 | | break; |
13496 | | case 460: |
13497 | | // M2_vcmac_s0_sat_i |
13498 | | O << " += vcmpyi("; |
13499 | | printOperand(MI, 2, O); |
13500 | | O << ','; |
13501 | | printOperand(MI, 3, O); |
13502 | | O << "):sat"; |
13503 | | return; |
13504 | | break; |
13505 | | case 461: |
13506 | | // M2_vcmac_s0_sat_r |
13507 | | O << " += vcmpyr("; |
13508 | | printOperand(MI, 2, O); |
13509 | | O << ','; |
13510 | | printOperand(MI, 3, O); |
13511 | | O << "):sat"; |
13512 | | return; |
13513 | | break; |
13514 | | case 462: |
13515 | | // M2_vcmpy_s0_sat_i, M2_vcmpy_s1_sat_i |
13516 | | O << " = vcmpyi("; |
13517 | | printOperand(MI, 1, O); |
13518 | | O << ','; |
13519 | | printOperand(MI, 2, O); |
13520 | | break; |
13521 | | case 463: |
13522 | | // M2_vcmpy_s0_sat_r, M2_vcmpy_s1_sat_r |
13523 | | O << " = vcmpyr("; |
13524 | | printOperand(MI, 1, O); |
13525 | | O << ','; |
13526 | | printOperand(MI, 2, O); |
13527 | | break; |
13528 | | case 464: |
13529 | | // M2_vdmacs_s0, M2_vdmacs_s1 |
13530 | | O << " += vdmpy("; |
13531 | | printOperand(MI, 2, O); |
13532 | | O << ','; |
13533 | | printOperand(MI, 3, O); |
13534 | | break; |
13535 | | case 465: |
13536 | | // M2_vdmpyrs_s0, M2_vdmpyrs_s1, M2_vdmpys_s0, M2_vdmpys_s1 |
13537 | | O << " = vdmpy("; |
13538 | | printOperand(MI, 1, O); |
13539 | | O << ','; |
13540 | | printOperand(MI, 2, O); |
13541 | | break; |
13542 | | case 466: |
13543 | | // M2_vmac2es, M2_vmac2es_s0, M2_vmac2es_s1 |
13544 | | O << " += vmpyeh("; |
13545 | | printOperand(MI, 2, O); |
13546 | | O << ','; |
13547 | | printOperand(MI, 3, O); |
13548 | | break; |
13549 | | case 467: |
13550 | | // M2_vmac2su_s0, M2_vmac2su_s1 |
13551 | | O << " += vmpyhsu("; |
13552 | | printOperand(MI, 2, O); |
13553 | | O << ','; |
13554 | | printOperand(MI, 3, O); |
13555 | | break; |
13556 | | case 468: |
13557 | | // M2_vmpy2es_s0, M2_vmpy2es_s1 |
13558 | | O << " = vmpyeh("; |
13559 | | printOperand(MI, 1, O); |
13560 | | O << ','; |
13561 | | printOperand(MI, 2, O); |
13562 | | break; |
13563 | | case 469: |
13564 | | // M2_vmpy2su_s0, M2_vmpy2su_s1 |
13565 | | O << " = vmpyhsu("; |
13566 | | printOperand(MI, 1, O); |
13567 | | O << ','; |
13568 | | printOperand(MI, 2, O); |
13569 | | break; |
13570 | | case 470: |
13571 | | // M2_vraddh |
13572 | | O << " = vraddh("; |
13573 | | printOperand(MI, 1, O); |
13574 | | O << ','; |
13575 | | printOperand(MI, 2, O); |
13576 | | O << ')'; |
13577 | | return; |
13578 | | break; |
13579 | | case 471: |
13580 | | // M2_vradduh |
13581 | | O << " = vradduh("; |
13582 | | printOperand(MI, 1, O); |
13583 | | O << ','; |
13584 | | printOperand(MI, 2, O); |
13585 | | O << ')'; |
13586 | | return; |
13587 | | break; |
13588 | | case 472: |
13589 | | // M2_vrcmaci_s0, M2_vrcmaci_s0c |
13590 | | O << " += vrcmpyi("; |
13591 | | printOperand(MI, 2, O); |
13592 | | O << ','; |
13593 | | printOperand(MI, 3, O); |
13594 | | break; |
13595 | | case 473: |
13596 | | // M2_vrcmacr_s0, M2_vrcmacr_s0c |
13597 | | O << " += vrcmpyr("; |
13598 | | printOperand(MI, 2, O); |
13599 | | O << ','; |
13600 | | printOperand(MI, 3, O); |
13601 | | break; |
13602 | | case 474: |
13603 | | // M2_vrcmpyi_s0, M2_vrcmpyi_s0c |
13604 | | O << " = vrcmpyi("; |
13605 | | printOperand(MI, 1, O); |
13606 | | O << ','; |
13607 | | printOperand(MI, 2, O); |
13608 | | break; |
13609 | | case 475: |
13610 | | // M2_vrcmpyr_s0, M2_vrcmpyr_s0c |
13611 | | O << " = vrcmpyr("; |
13612 | | printOperand(MI, 1, O); |
13613 | | O << ','; |
13614 | | printOperand(MI, 2, O); |
13615 | | break; |
13616 | | case 476: |
13617 | | // M2_vrmac_s0 |
13618 | | O << " += vrmpyh("; |
13619 | | printOperand(MI, 2, O); |
13620 | | O << ','; |
13621 | | printOperand(MI, 3, O); |
13622 | | O << ')'; |
13623 | | return; |
13624 | | break; |
13625 | | case 477: |
13626 | | // M2_vrmpy_s0 |
13627 | | O << " = vrmpyh("; |
13628 | | printOperand(MI, 1, O); |
13629 | | O << ','; |
13630 | | printOperand(MI, 2, O); |
13631 | | O << ')'; |
13632 | | return; |
13633 | | break; |
13634 | | case 478: |
13635 | | // M2_xor_xacc, M4_xor_xacc |
13636 | | O << " ^= xor("; |
13637 | | printOperand(MI, 2, O); |
13638 | | O << ','; |
13639 | | printOperand(MI, 3, O); |
13640 | | O << ')'; |
13641 | | return; |
13642 | | break; |
13643 | | case 479: |
13644 | | // M4_and_and, M4_and_andn |
13645 | | O << " &= and("; |
13646 | | printOperand(MI, 2, O); |
13647 | | break; |
13648 | | case 480: |
13649 | | // M4_and_or |
13650 | | O << " &= or("; |
13651 | | printOperand(MI, 2, O); |
13652 | | O << ','; |
13653 | | printOperand(MI, 3, O); |
13654 | | O << ')'; |
13655 | | return; |
13656 | | break; |
13657 | | case 481: |
13658 | | // M4_and_xor |
13659 | | O << " &= xor("; |
13660 | | printOperand(MI, 2, O); |
13661 | | O << ','; |
13662 | | printOperand(MI, 3, O); |
13663 | | O << ')'; |
13664 | | return; |
13665 | | break; |
13666 | | case 482: |
13667 | | // M4_cmpyi_wh, M4_cmpyi_whc |
13668 | | O << " = cmpyiwh("; |
13669 | | printOperand(MI, 1, O); |
13670 | | O << ','; |
13671 | | printOperand(MI, 2, O); |
13672 | | break; |
13673 | | case 483: |
13674 | | // M4_cmpyr_wh, M4_cmpyr_whc |
13675 | | O << " = cmpyrwh("; |
13676 | | printOperand(MI, 1, O); |
13677 | | O << ','; |
13678 | | printOperand(MI, 2, O); |
13679 | | break; |
13680 | | case 484: |
13681 | | // M4_mpyri_addi, M4_mpyrr_addi, S4_addi_asl_ri, S4_addi_lsr_ri |
13682 | | O << " = add(#"; |
13683 | | printOperand(MI, 1, O); |
13684 | | break; |
13685 | | case 485: |
13686 | | // M4_or_and, M4_or_andn, S4_or_andi |
13687 | | O << " |= and("; |
13688 | | printOperand(MI, 2, O); |
13689 | | break; |
13690 | | case 486: |
13691 | | // M4_or_or, S4_or_ori |
13692 | | O << " |= or("; |
13693 | | printOperand(MI, 2, O); |
13694 | | break; |
13695 | | case 487: |
13696 | | // M4_or_xor |
13697 | | O << " |= xor("; |
13698 | | printOperand(MI, 2, O); |
13699 | | O << ','; |
13700 | | printOperand(MI, 3, O); |
13701 | | O << ')'; |
13702 | | return; |
13703 | | break; |
13704 | | case 488: |
13705 | | // M4_pmpyw |
13706 | | O << " = pmpyw("; |
13707 | | printOperand(MI, 1, O); |
13708 | | O << ','; |
13709 | | printOperand(MI, 2, O); |
13710 | | O << ')'; |
13711 | | return; |
13712 | | break; |
13713 | | case 489: |
13714 | | // M4_pmpyw_acc |
13715 | | O << " ^= pmpyw("; |
13716 | | printOperand(MI, 2, O); |
13717 | | O << ','; |
13718 | | printOperand(MI, 3, O); |
13719 | | O << ')'; |
13720 | | return; |
13721 | | break; |
13722 | | case 490: |
13723 | | // M4_vpmpyh |
13724 | | O << " = vpmpyh("; |
13725 | | printOperand(MI, 1, O); |
13726 | | O << ','; |
13727 | | printOperand(MI, 2, O); |
13728 | | O << ')'; |
13729 | | return; |
13730 | | break; |
13731 | | case 491: |
13732 | | // M4_vpmpyh_acc |
13733 | | O << " ^= vpmpyh("; |
13734 | | printOperand(MI, 2, O); |
13735 | | O << ','; |
13736 | | printOperand(MI, 3, O); |
13737 | | O << ')'; |
13738 | | return; |
13739 | | break; |
13740 | | case 492: |
13741 | | // M4_vrmpyeh_acc_s0, M4_vrmpyeh_acc_s1 |
13742 | | O << " += vrmpyweh("; |
13743 | | printOperand(MI, 2, O); |
13744 | | O << ','; |
13745 | | printOperand(MI, 3, O); |
13746 | | break; |
13747 | | case 493: |
13748 | | // M4_vrmpyeh_s0, M4_vrmpyeh_s1 |
13749 | | O << " = vrmpyweh("; |
13750 | | printOperand(MI, 1, O); |
13751 | | O << ','; |
13752 | | printOperand(MI, 2, O); |
13753 | | break; |
13754 | | case 494: |
13755 | | // M4_vrmpyoh_acc_s0, M4_vrmpyoh_acc_s1 |
13756 | | O << " += vrmpywoh("; |
13757 | | printOperand(MI, 2, O); |
13758 | | O << ','; |
13759 | | printOperand(MI, 3, O); |
13760 | | break; |
13761 | | case 495: |
13762 | | // M4_vrmpyoh_s0, M4_vrmpyoh_s1 |
13763 | | O << " = vrmpywoh("; |
13764 | | printOperand(MI, 1, O); |
13765 | | O << ','; |
13766 | | printOperand(MI, 2, O); |
13767 | | break; |
13768 | | case 496: |
13769 | | // M4_xor_and, M4_xor_andn |
13770 | | O << " ^= and("; |
13771 | | printOperand(MI, 2, O); |
13772 | | break; |
13773 | | case 497: |
13774 | | // M4_xor_or |
13775 | | O << " ^= or("; |
13776 | | printOperand(MI, 2, O); |
13777 | | O << ','; |
13778 | | printOperand(MI, 3, O); |
13779 | | O << ')'; |
13780 | | return; |
13781 | | break; |
13782 | | case 498: |
13783 | | // M5_vdmacbsu |
13784 | | O << " += vdmpybsu("; |
13785 | | printOperand(MI, 2, O); |
13786 | | O << ','; |
13787 | | printOperand(MI, 3, O); |
13788 | | O << "):sat"; |
13789 | | return; |
13790 | | break; |
13791 | | case 499: |
13792 | | // M5_vdmpybsu |
13793 | | O << " = vdmpybsu("; |
13794 | | printOperand(MI, 1, O); |
13795 | | O << ','; |
13796 | | printOperand(MI, 2, O); |
13797 | | O << "):sat"; |
13798 | | return; |
13799 | | break; |
13800 | | case 500: |
13801 | | // M5_vmacbsu |
13802 | | O << " += vmpybsu("; |
13803 | | printOperand(MI, 2, O); |
13804 | | O << ','; |
13805 | | printOperand(MI, 3, O); |
13806 | | O << ')'; |
13807 | | return; |
13808 | | break; |
13809 | | case 501: |
13810 | | // M5_vmacbuu |
13811 | | O << " += vmpybu("; |
13812 | | printOperand(MI, 2, O); |
13813 | | O << ','; |
13814 | | printOperand(MI, 3, O); |
13815 | | O << ')'; |
13816 | | return; |
13817 | | break; |
13818 | | case 502: |
13819 | | // M5_vmpybsu |
13820 | | O << " = vmpybsu("; |
13821 | | printOperand(MI, 1, O); |
13822 | | O << ','; |
13823 | | printOperand(MI, 2, O); |
13824 | | O << ')'; |
13825 | | return; |
13826 | | break; |
13827 | | case 503: |
13828 | | // M5_vmpybuu |
13829 | | O << " = vmpybu("; |
13830 | | printOperand(MI, 1, O); |
13831 | | O << ','; |
13832 | | printOperand(MI, 2, O); |
13833 | | O << ')'; |
13834 | | return; |
13835 | | break; |
13836 | | case 504: |
13837 | | // M5_vrmacbsu |
13838 | | O << " += vrmpybsu("; |
13839 | | printOperand(MI, 2, O); |
13840 | | O << ','; |
13841 | | printOperand(MI, 3, O); |
13842 | | O << ')'; |
13843 | | return; |
13844 | | break; |
13845 | | case 505: |
13846 | | // M5_vrmacbuu |
13847 | | O << " += vrmpybu("; |
13848 | | printOperand(MI, 2, O); |
13849 | | O << ','; |
13850 | | printOperand(MI, 3, O); |
13851 | | O << ')'; |
13852 | | return; |
13853 | | break; |
13854 | | case 506: |
13855 | | // M5_vrmpybsu |
13856 | | O << " = vrmpybsu("; |
13857 | | printOperand(MI, 1, O); |
13858 | | O << ','; |
13859 | | printOperand(MI, 2, O); |
13860 | | O << ')'; |
13861 | | return; |
13862 | | break; |
13863 | | case 507: |
13864 | | // M5_vrmpybuu |
13865 | | O << " = vrmpybu("; |
13866 | | printOperand(MI, 1, O); |
13867 | | O << ','; |
13868 | | printOperand(MI, 2, O); |
13869 | | O << ')'; |
13870 | | return; |
13871 | | break; |
13872 | | case 508: |
13873 | | // M6_vabsdiffb |
13874 | | O << " = vabsdiffb("; |
13875 | | printOperand(MI, 1, O); |
13876 | | O << ','; |
13877 | | printOperand(MI, 2, O); |
13878 | | O << ')'; |
13879 | | return; |
13880 | | break; |
13881 | | case 509: |
13882 | | // M7_dcmpyiw, M7_dcmpyiwc, M7_wcmpyiw, M7_wcmpyiw_rnd, M7_wcmpyiwc, M7_w... |
13883 | | O << " = cmpyiw("; |
13884 | | printOperand(MI, 1, O); |
13885 | | O << ','; |
13886 | | printOperand(MI, 2, O); |
13887 | | break; |
13888 | | case 510: |
13889 | | // M7_dcmpyiw_acc, M7_dcmpyiwc_acc |
13890 | | O << " += cmpyiw("; |
13891 | | printOperand(MI, 2, O); |
13892 | | O << ','; |
13893 | | printOperand(MI, 3, O); |
13894 | | break; |
13895 | | case 511: |
13896 | | // M7_dcmpyrw, M7_dcmpyrwc, M7_wcmpyrw, M7_wcmpyrw_rnd, M7_wcmpyrwc, M7_w... |
13897 | | O << " = cmpyrw("; |
13898 | | printOperand(MI, 1, O); |
13899 | | O << ','; |
13900 | | printOperand(MI, 2, O); |
13901 | | break; |
13902 | | case 512: |
13903 | | // M7_dcmpyrw_acc, M7_dcmpyrwc_acc |
13904 | | O << " += cmpyrw("; |
13905 | | printOperand(MI, 2, O); |
13906 | | O << ','; |
13907 | | printOperand(MI, 3, O); |
13908 | | break; |
13909 | | case 513: |
13910 | | // PS_loadrbabs |
13911 | | O << " = memb(#"; |
13912 | | printOperand(MI, 1, O); |
13913 | | O << ')'; |
13914 | | return; |
13915 | | break; |
13916 | | case 514: |
13917 | | // PS_loadrdabs |
13918 | | O << " = memd(#"; |
13919 | | printOperand(MI, 1, O); |
13920 | | O << ')'; |
13921 | | return; |
13922 | | break; |
13923 | | case 515: |
13924 | | // PS_loadrhabs |
13925 | | O << " = memh(#"; |
13926 | | printOperand(MI, 1, O); |
13927 | | O << ')'; |
13928 | | return; |
13929 | | break; |
13930 | | case 516: |
13931 | | // PS_loadriabs |
13932 | | O << " = memw(#"; |
13933 | | printOperand(MI, 1, O); |
13934 | | O << ')'; |
13935 | | return; |
13936 | | break; |
13937 | | case 517: |
13938 | | // PS_loadrubabs |
13939 | | O << " = memub(#"; |
13940 | | printOperand(MI, 1, O); |
13941 | | O << ')'; |
13942 | | return; |
13943 | | break; |
13944 | | case 518: |
13945 | | // PS_loadruhabs |
13946 | | O << " = memuh(#"; |
13947 | | printOperand(MI, 1, O); |
13948 | | O << ')'; |
13949 | | return; |
13950 | | break; |
13951 | | case 519: |
13952 | | // R6_release_at_vi |
13953 | | O << "):at"; |
13954 | | return; |
13955 | | break; |
13956 | | case 520: |
13957 | | // R6_release_st_vi |
13958 | | O << "):st"; |
13959 | | return; |
13960 | | break; |
13961 | | case 521: |
13962 | | // S2_addasl_rrri |
13963 | | O << " = addasl("; |
13964 | | printOperand(MI, 1, O); |
13965 | | O << ','; |
13966 | | printOperand(MI, 2, O); |
13967 | | O << ",#"; |
13968 | | printOperand(MI, 3, O); |
13969 | | O << ')'; |
13970 | | return; |
13971 | | break; |
13972 | | case 522: |
13973 | | // S2_asl_i_p, S2_asl_i_r, S2_asl_i_r_sat, S2_asl_r_p, S2_asl_r_r, S2_asl... |
13974 | | O << " = asl("; |
13975 | | printOperand(MI, 1, O); |
13976 | | break; |
13977 | | case 523: |
13978 | | // S2_asl_i_p_acc, S2_asl_i_r_acc, S2_asl_r_p_acc, S2_asl_r_r_acc |
13979 | | O << " += asl("; |
13980 | | printOperand(MI, 2, O); |
13981 | | break; |
13982 | | case 524: |
13983 | | // S2_asl_i_p_and, S2_asl_i_r_and, S2_asl_r_p_and, S2_asl_r_r_and |
13984 | | O << " &= asl("; |
13985 | | printOperand(MI, 2, O); |
13986 | | break; |
13987 | | case 525: |
13988 | | // S2_asl_i_p_nac, S2_asl_i_r_nac, S2_asl_r_p_nac, S2_asl_r_r_nac |
13989 | | O << " -= asl("; |
13990 | | printOperand(MI, 2, O); |
13991 | | break; |
13992 | | case 526: |
13993 | | // S2_asl_i_p_or, S2_asl_i_r_or, S2_asl_r_p_or, S2_asl_r_r_or |
13994 | | O << " |= asl("; |
13995 | | printOperand(MI, 2, O); |
13996 | | break; |
13997 | | case 527: |
13998 | | // S2_asl_i_p_xacc, S2_asl_i_r_xacc, S2_asl_r_p_xor |
13999 | | O << " ^= asl("; |
14000 | | printOperand(MI, 2, O); |
14001 | | break; |
14002 | | case 528: |
14003 | | // S2_asr_i_p, S2_asr_i_p_rnd, S2_asr_i_r, S2_asr_i_r_rnd, S2_asr_r_p, S2... |
14004 | | O << " = asr("; |
14005 | | printOperand(MI, 1, O); |
14006 | | break; |
14007 | | case 529: |
14008 | | // S2_asr_i_p_acc, S2_asr_i_r_acc, S2_asr_r_p_acc, S2_asr_r_r_acc |
14009 | | O << " += asr("; |
14010 | | printOperand(MI, 2, O); |
14011 | | break; |
14012 | | case 530: |
14013 | | // S2_asr_i_p_and, S2_asr_i_r_and, S2_asr_r_p_and, S2_asr_r_r_and |
14014 | | O << " &= asr("; |
14015 | | printOperand(MI, 2, O); |
14016 | | break; |
14017 | | case 531: |
14018 | | // S2_asr_i_p_nac, S2_asr_i_r_nac, S2_asr_r_p_nac, S2_asr_r_r_nac |
14019 | | O << " -= asr("; |
14020 | | printOperand(MI, 2, O); |
14021 | | break; |
14022 | | case 532: |
14023 | | // S2_asr_i_p_or, S2_asr_i_r_or, S2_asr_r_p_or, S2_asr_r_r_or |
14024 | | O << " |= asr("; |
14025 | | printOperand(MI, 2, O); |
14026 | | break; |
14027 | | case 533: |
14028 | | // S2_asr_r_p_xor |
14029 | | O << " ^= asr("; |
14030 | | printOperand(MI, 2, O); |
14031 | | O << ','; |
14032 | | printOperand(MI, 3, O); |
14033 | | O << ')'; |
14034 | | return; |
14035 | | break; |
14036 | | case 534: |
14037 | | // S2_brev, S2_brevp |
14038 | | O << " = brev("; |
14039 | | printOperand(MI, 1, O); |
14040 | | O << ')'; |
14041 | | return; |
14042 | | break; |
14043 | | case 535: |
14044 | | // S2_cabacdecbin |
14045 | | O << " = decbin("; |
14046 | | printOperand(MI, 1, O); |
14047 | | O << ','; |
14048 | | printOperand(MI, 2, O); |
14049 | | O << ')'; |
14050 | | return; |
14051 | | break; |
14052 | | case 536: |
14053 | | // S2_cl0, S2_cl0p |
14054 | | O << " = cl0("; |
14055 | | printOperand(MI, 1, O); |
14056 | | O << ')'; |
14057 | | return; |
14058 | | break; |
14059 | | case 537: |
14060 | | // S2_cl1, S2_cl1p |
14061 | | O << " = cl1("; |
14062 | | printOperand(MI, 1, O); |
14063 | | O << ')'; |
14064 | | return; |
14065 | | break; |
14066 | | case 538: |
14067 | | // S2_clb, S2_clbp |
14068 | | O << " = clb("; |
14069 | | printOperand(MI, 1, O); |
14070 | | O << ')'; |
14071 | | return; |
14072 | | break; |
14073 | | case 539: |
14074 | | // S2_clbnorm, S4_clbpnorm |
14075 | | O << " = normamt("; |
14076 | | printOperand(MI, 1, O); |
14077 | | O << ')'; |
14078 | | return; |
14079 | | break; |
14080 | | case 540: |
14081 | | // S2_clrbit_i, S2_clrbit_r |
14082 | | O << " = clrbit("; |
14083 | | printOperand(MI, 1, O); |
14084 | | break; |
14085 | | case 541: |
14086 | | // S2_ct0, S2_ct0p |
14087 | | O << " = ct0("; |
14088 | | printOperand(MI, 1, O); |
14089 | | O << ')'; |
14090 | | return; |
14091 | | break; |
14092 | | case 542: |
14093 | | // S2_ct1, S2_ct1p |
14094 | | O << " = ct1("; |
14095 | | printOperand(MI, 1, O); |
14096 | | O << ')'; |
14097 | | return; |
14098 | | break; |
14099 | | case 543: |
14100 | | // S2_deinterleave |
14101 | | O << " = deinterleave("; |
14102 | | printOperand(MI, 1, O); |
14103 | | O << ')'; |
14104 | | return; |
14105 | | break; |
14106 | | case 544: |
14107 | | // S2_extractu, S2_extractu_rp, S2_extractup, S2_extractup_rp |
14108 | | O << " = extractu("; |
14109 | | printOperand(MI, 1, O); |
14110 | | break; |
14111 | | case 545: |
14112 | | // S2_insert, S2_insert_rp, S2_insertp, S2_insertp_rp |
14113 | | O << " = insert("; |
14114 | | printOperand(MI, 2, O); |
14115 | | break; |
14116 | | case 546: |
14117 | | // S2_interleave |
14118 | | O << " = interleave("; |
14119 | | printOperand(MI, 1, O); |
14120 | | O << ')'; |
14121 | | return; |
14122 | | break; |
14123 | | case 547: |
14124 | | // S2_lfsp |
14125 | | O << " = lfs("; |
14126 | | printOperand(MI, 1, O); |
14127 | | O << ','; |
14128 | | printOperand(MI, 2, O); |
14129 | | O << ')'; |
14130 | | return; |
14131 | | break; |
14132 | | case 548: |
14133 | | // S2_lsl_r_p, S2_lsl_r_r |
14134 | | O << " = lsl("; |
14135 | | printOperand(MI, 1, O); |
14136 | | O << ','; |
14137 | | printOperand(MI, 2, O); |
14138 | | O << ')'; |
14139 | | return; |
14140 | | break; |
14141 | | case 549: |
14142 | | // S2_lsl_r_p_acc, S2_lsl_r_r_acc |
14143 | | O << " += lsl("; |
14144 | | printOperand(MI, 2, O); |
14145 | | O << ','; |
14146 | | printOperand(MI, 3, O); |
14147 | | O << ')'; |
14148 | | return; |
14149 | | break; |
14150 | | case 550: |
14151 | | // S2_lsl_r_p_and, S2_lsl_r_r_and |
14152 | | O << " &= lsl("; |
14153 | | printOperand(MI, 2, O); |
14154 | | O << ','; |
14155 | | printOperand(MI, 3, O); |
14156 | | O << ')'; |
14157 | | return; |
14158 | | break; |
14159 | | case 551: |
14160 | | // S2_lsl_r_p_nac, S2_lsl_r_r_nac |
14161 | | O << " -= lsl("; |
14162 | | printOperand(MI, 2, O); |
14163 | | O << ','; |
14164 | | printOperand(MI, 3, O); |
14165 | | O << ')'; |
14166 | | return; |
14167 | | break; |
14168 | | case 552: |
14169 | | // S2_lsl_r_p_or, S2_lsl_r_r_or |
14170 | | O << " |= lsl("; |
14171 | | printOperand(MI, 2, O); |
14172 | | O << ','; |
14173 | | printOperand(MI, 3, O); |
14174 | | O << ')'; |
14175 | | return; |
14176 | | break; |
14177 | | case 553: |
14178 | | // S2_lsl_r_p_xor |
14179 | | O << " ^= lsl("; |
14180 | | printOperand(MI, 2, O); |
14181 | | O << ','; |
14182 | | printOperand(MI, 3, O); |
14183 | | O << ')'; |
14184 | | return; |
14185 | | break; |
14186 | | case 554: |
14187 | | // S2_lsl_r_vh |
14188 | | O << " = vlslh("; |
14189 | | printOperand(MI, 1, O); |
14190 | | O << ','; |
14191 | | printOperand(MI, 2, O); |
14192 | | O << ')'; |
14193 | | return; |
14194 | | break; |
14195 | | case 555: |
14196 | | // S2_lsl_r_vw |
14197 | | O << " = vlslw("; |
14198 | | printOperand(MI, 1, O); |
14199 | | O << ','; |
14200 | | printOperand(MI, 2, O); |
14201 | | O << ')'; |
14202 | | return; |
14203 | | break; |
14204 | | case 556: |
14205 | | // S2_lsr_i_p, S2_lsr_i_r, S2_lsr_r_p, S2_lsr_r_r |
14206 | | O << " = lsr("; |
14207 | | printOperand(MI, 1, O); |
14208 | | break; |
14209 | | case 557: |
14210 | | // S2_lsr_i_p_acc, S2_lsr_i_r_acc, S2_lsr_r_p_acc, S2_lsr_r_r_acc |
14211 | | O << " += lsr("; |
14212 | | printOperand(MI, 2, O); |
14213 | | break; |
14214 | | case 558: |
14215 | | // S2_lsr_i_p_and, S2_lsr_i_r_and, S2_lsr_r_p_and, S2_lsr_r_r_and |
14216 | | O << " &= lsr("; |
14217 | | printOperand(MI, 2, O); |
14218 | | break; |
14219 | | case 559: |
14220 | | // S2_lsr_i_p_nac, S2_lsr_i_r_nac, S2_lsr_r_p_nac, S2_lsr_r_r_nac |
14221 | | O << " -= lsr("; |
14222 | | printOperand(MI, 2, O); |
14223 | | break; |
14224 | | case 560: |
14225 | | // S2_lsr_i_p_or, S2_lsr_i_r_or, S2_lsr_r_p_or, S2_lsr_r_r_or |
14226 | | O << " |= lsr("; |
14227 | | printOperand(MI, 2, O); |
14228 | | break; |
14229 | | case 561: |
14230 | | // S2_lsr_i_p_xacc, S2_lsr_i_r_xacc, S2_lsr_r_p_xor |
14231 | | O << " ^= lsr("; |
14232 | | printOperand(MI, 2, O); |
14233 | | break; |
14234 | | case 562: |
14235 | | // S2_mask |
14236 | | O << " = mask(#"; |
14237 | | printOperand(MI, 1, O); |
14238 | | O << ",#"; |
14239 | | printOperand(MI, 2, O); |
14240 | | O << ')'; |
14241 | | return; |
14242 | | break; |
14243 | | case 563: |
14244 | | // S2_packhl, dep_S2_packhl |
14245 | | O << " = packhl("; |
14246 | | printOperand(MI, 1, O); |
14247 | | O << ','; |
14248 | | printOperand(MI, 2, O); |
14249 | | break; |
14250 | | case 564: |
14251 | | // S2_parityp, S4_parity |
14252 | | O << " = parity("; |
14253 | | printOperand(MI, 1, O); |
14254 | | O << ','; |
14255 | | printOperand(MI, 2, O); |
14256 | | O << ')'; |
14257 | | return; |
14258 | | break; |
14259 | | case 565: |
14260 | | // S2_setbit_i, S2_setbit_r |
14261 | | O << " = setbit("; |
14262 | | printOperand(MI, 1, O); |
14263 | | break; |
14264 | | case 566: |
14265 | | // S2_shuffeb |
14266 | | O << " = shuffeb("; |
14267 | | printOperand(MI, 1, O); |
14268 | | O << ','; |
14269 | | printOperand(MI, 2, O); |
14270 | | O << ')'; |
14271 | | return; |
14272 | | break; |
14273 | | case 567: |
14274 | | // S2_shuffeh |
14275 | | O << " = shuffeh("; |
14276 | | printOperand(MI, 1, O); |
14277 | | O << ','; |
14278 | | printOperand(MI, 2, O); |
14279 | | O << ')'; |
14280 | | return; |
14281 | | break; |
14282 | | case 568: |
14283 | | // S2_shuffob |
14284 | | O << " = shuffob("; |
14285 | | printOperand(MI, 1, O); |
14286 | | O << ','; |
14287 | | printOperand(MI, 2, O); |
14288 | | O << ')'; |
14289 | | return; |
14290 | | break; |
14291 | | case 569: |
14292 | | // S2_shuffoh |
14293 | | O << " = shuffoh("; |
14294 | | printOperand(MI, 1, O); |
14295 | | O << ','; |
14296 | | printOperand(MI, 2, O); |
14297 | | O << ')'; |
14298 | | return; |
14299 | | break; |
14300 | | case 570: |
14301 | | // S2_storerb_pbr, S2_storerb_pr, S2_storerbnew_pbr, S2_storerbnew_pr, S2... |
14302 | | O << "++"; |
14303 | | printOperand(MI, 2, O); |
14304 | | break; |
14305 | | case 571: |
14306 | | // S2_storerb_pci, S2_storerb_pi, S2_storerbnew_pci, S2_storerbnew_pi, S2... |
14307 | | O << "++#"; |
14308 | | printOperand(MI, 2, O); |
14309 | | break; |
14310 | | case 572: |
14311 | | // S2_storerb_pcr, S2_storerbnew_pcr, S2_storerd_pcr, S2_storerf_pcr, S2_... |
14312 | | O << "++I:circ("; |
14313 | | printOperand(MI, 2, O); |
14314 | | O << ")) = "; |
14315 | | printOperand(MI, 3, O); |
14316 | | break; |
14317 | | case 573: |
14318 | | // S2_storew_rl_at_vi, S4_stored_rl_at_vi |
14319 | | O << "):at = "; |
14320 | | printOperand(MI, 1, O); |
14321 | | return; |
14322 | | break; |
14323 | | case 574: |
14324 | | // S2_storew_rl_st_vi, S4_stored_rl_st_vi |
14325 | | O << "):st = "; |
14326 | | printOperand(MI, 1, O); |
14327 | | return; |
14328 | | break; |
14329 | | case 575: |
14330 | | // S2_svsathb, S2_vsathb, S2_vsathb_nopack |
14331 | | O << " = vsathb("; |
14332 | | printOperand(MI, 1, O); |
14333 | | O << ')'; |
14334 | | return; |
14335 | | break; |
14336 | | case 576: |
14337 | | // S2_togglebit_i, S2_togglebit_r |
14338 | | O << " = togglebit("; |
14339 | | printOperand(MI, 1, O); |
14340 | | break; |
14341 | | case 577: |
14342 | | // S2_tstbit_i, S2_tstbit_r |
14343 | | O << " = tstbit("; |
14344 | | printOperand(MI, 1, O); |
14345 | | break; |
14346 | | case 578: |
14347 | | // S2_valignib, S2_valignrb |
14348 | | O << " = valignb("; |
14349 | | printOperand(MI, 1, O); |
14350 | | O << ','; |
14351 | | printOperand(MI, 2, O); |
14352 | | break; |
14353 | | case 579: |
14354 | | // S2_vcnegh |
14355 | | O << " = vcnegh("; |
14356 | | printOperand(MI, 1, O); |
14357 | | O << ','; |
14358 | | printOperand(MI, 2, O); |
14359 | | O << ')'; |
14360 | | return; |
14361 | | break; |
14362 | | case 580: |
14363 | | // S2_vcrotate |
14364 | | O << " = vcrotate("; |
14365 | | printOperand(MI, 1, O); |
14366 | | O << ','; |
14367 | | printOperand(MI, 2, O); |
14368 | | O << ')'; |
14369 | | return; |
14370 | | break; |
14371 | | case 581: |
14372 | | // S2_vrcnegh |
14373 | | O << " += vrcnegh("; |
14374 | | printOperand(MI, 2, O); |
14375 | | O << ','; |
14376 | | printOperand(MI, 3, O); |
14377 | | O << ')'; |
14378 | | return; |
14379 | | break; |
14380 | | case 582: |
14381 | | // S2_vrndpackwh, S2_vrndpackwhs |
14382 | | O << " = vrndwh("; |
14383 | | printOperand(MI, 1, O); |
14384 | | break; |
14385 | | case 583: |
14386 | | // S2_vsatwuh, S2_vsatwuh_nopack |
14387 | | O << " = vsatwuh("; |
14388 | | printOperand(MI, 1, O); |
14389 | | O << ')'; |
14390 | | return; |
14391 | | break; |
14392 | | case 584: |
14393 | | // S2_vsplatrb, S6_vsplatrbp |
14394 | | O << " = vsplatb("; |
14395 | | printOperand(MI, 1, O); |
14396 | | O << ')'; |
14397 | | return; |
14398 | | break; |
14399 | | case 585: |
14400 | | // S2_vsplatrh |
14401 | | O << " = vsplath("; |
14402 | | printOperand(MI, 1, O); |
14403 | | O << ')'; |
14404 | | return; |
14405 | | break; |
14406 | | case 586: |
14407 | | // S2_vspliceib, S2_vsplicerb |
14408 | | O << " = vspliceb("; |
14409 | | printOperand(MI, 1, O); |
14410 | | O << ','; |
14411 | | printOperand(MI, 2, O); |
14412 | | break; |
14413 | | case 587: |
14414 | | // S2_vsxtbh |
14415 | | O << " = vsxtbh("; |
14416 | | printOperand(MI, 1, O); |
14417 | | O << ')'; |
14418 | | return; |
14419 | | break; |
14420 | | case 588: |
14421 | | // S2_vsxthw |
14422 | | O << " = vsxthw("; |
14423 | | printOperand(MI, 1, O); |
14424 | | O << ')'; |
14425 | | return; |
14426 | | break; |
14427 | | case 589: |
14428 | | // S2_vtrunehb, S6_vtrunehb_ppp |
14429 | | O << " = vtrunehb("; |
14430 | | printOperand(MI, 1, O); |
14431 | | break; |
14432 | | case 590: |
14433 | | // S2_vtrunewh |
14434 | | O << " = vtrunewh("; |
14435 | | printOperand(MI, 1, O); |
14436 | | O << ','; |
14437 | | printOperand(MI, 2, O); |
14438 | | O << ')'; |
14439 | | return; |
14440 | | break; |
14441 | | case 591: |
14442 | | // S2_vtrunohb, S6_vtrunohb_ppp |
14443 | | O << " = vtrunohb("; |
14444 | | printOperand(MI, 1, O); |
14445 | | break; |
14446 | | case 592: |
14447 | | // S2_vtrunowh |
14448 | | O << " = vtrunowh("; |
14449 | | printOperand(MI, 1, O); |
14450 | | O << ','; |
14451 | | printOperand(MI, 2, O); |
14452 | | O << ')'; |
14453 | | return; |
14454 | | break; |
14455 | | case 593: |
14456 | | // S2_vzxtbh |
14457 | | O << " = vzxtbh("; |
14458 | | printOperand(MI, 1, O); |
14459 | | O << ')'; |
14460 | | return; |
14461 | | break; |
14462 | | case 594: |
14463 | | // S2_vzxthw |
14464 | | O << " = vzxthw("; |
14465 | | printOperand(MI, 1, O); |
14466 | | O << ')'; |
14467 | | return; |
14468 | | break; |
14469 | | case 595: |
14470 | | // S4_andi_asl_ri, S4_andi_lsr_ri |
14471 | | O << " = and(#"; |
14472 | | printOperand(MI, 1, O); |
14473 | | break; |
14474 | | case 596: |
14475 | | // S4_clbaddi, S4_clbpaddi |
14476 | | O << " = add(clb("; |
14477 | | printOperand(MI, 1, O); |
14478 | | O << "),#"; |
14479 | | printOperand(MI, 2, O); |
14480 | | O << ')'; |
14481 | | return; |
14482 | | break; |
14483 | | case 597: |
14484 | | // S4_extract, S4_extract_rp, S4_extractp, S4_extractp_rp |
14485 | | O << " = extract("; |
14486 | | printOperand(MI, 1, O); |
14487 | | break; |
14488 | | case 598: |
14489 | | // S4_lsli |
14490 | | O << " = lsl(#"; |
14491 | | printOperand(MI, 1, O); |
14492 | | O << ','; |
14493 | | printOperand(MI, 2, O); |
14494 | | O << ')'; |
14495 | | return; |
14496 | | break; |
14497 | | case 599: |
14498 | | // S4_ntstbit_i, S4_ntstbit_r |
14499 | | O << " = !tstbit("; |
14500 | | printOperand(MI, 1, O); |
14501 | | break; |
14502 | | case 600: |
14503 | | // S4_ori_asl_ri, S4_ori_lsr_ri |
14504 | | O << " = or(#"; |
14505 | | printOperand(MI, 1, O); |
14506 | | break; |
14507 | | case 601: |
14508 | | // S4_pstorerbf_abs, S4_pstorerbnewf_abs, S4_pstorerbnewt_abs, S4_pstorer... |
14509 | | O << ") memb(#"; |
14510 | | printOperand(MI, 1, O); |
14511 | | O << ") = "; |
14512 | | printOperand(MI, 2, O); |
14513 | | break; |
14514 | | case 602: |
14515 | | // S4_pstorerbfnew_abs, S4_pstorerbnewfnew_abs, S4_pstorerbnewtnew_abs, S... |
14516 | | O << ".new) memb(#"; |
14517 | | printOperand(MI, 1, O); |
14518 | | O << ") = "; |
14519 | | printOperand(MI, 2, O); |
14520 | | break; |
14521 | | case 603: |
14522 | | // S4_pstorerdf_abs, S4_pstorerdt_abs |
14523 | | O << ") memd(#"; |
14524 | | printOperand(MI, 1, O); |
14525 | | O << ") = "; |
14526 | | printOperand(MI, 2, O); |
14527 | | return; |
14528 | | break; |
14529 | | case 604: |
14530 | | // S4_pstorerdfnew_abs, S4_pstorerdtnew_abs |
14531 | | O << ".new) memd(#"; |
14532 | | printOperand(MI, 1, O); |
14533 | | O << ") = "; |
14534 | | printOperand(MI, 2, O); |
14535 | | return; |
14536 | | break; |
14537 | | case 605: |
14538 | | // S4_pstorerff_abs, S4_pstorerft_abs, S4_pstorerhf_abs, S4_pstorerhnewf_... |
14539 | | O << ") memh(#"; |
14540 | | printOperand(MI, 1, O); |
14541 | | O << ") = "; |
14542 | | printOperand(MI, 2, O); |
14543 | | break; |
14544 | | case 606: |
14545 | | // S4_pstorerffnew_abs, S4_pstorerftnew_abs, S4_pstorerhfnew_abs, S4_psto... |
14546 | | O << ".new) memh(#"; |
14547 | | printOperand(MI, 1, O); |
14548 | | O << ") = "; |
14549 | | printOperand(MI, 2, O); |
14550 | | break; |
14551 | | case 607: |
14552 | | // S4_pstorerif_abs, S4_pstorerinewf_abs, S4_pstorerinewt_abs, S4_pstorer... |
14553 | | O << ") memw(#"; |
14554 | | printOperand(MI, 1, O); |
14555 | | O << ") = "; |
14556 | | printOperand(MI, 2, O); |
14557 | | break; |
14558 | | case 608: |
14559 | | // S4_pstorerifnew_abs, S4_pstorerinewfnew_abs, S4_pstorerinewtnew_abs, S... |
14560 | | O << ".new) memw(#"; |
14561 | | printOperand(MI, 1, O); |
14562 | | O << ") = "; |
14563 | | printOperand(MI, 2, O); |
14564 | | break; |
14565 | | case 609: |
14566 | | // S4_storerb_ap, S4_storerbnew_ap, S4_storerd_ap, S4_storerf_ap, S4_stor... |
14567 | | O << "=#"; |
14568 | | printOperand(MI, 1, O); |
14569 | | O << ") = "; |
14570 | | printOperand(MI, 2, O); |
14571 | | break; |
14572 | | case 610: |
14573 | | // S4_storerb_rr, S4_storerbnew_rr, S4_storerd_rr, S4_storerf_rr, S4_stor... |
14574 | | O << '+'; |
14575 | | printOperand(MI, 1, O); |
14576 | | O << "<<#"; |
14577 | | printOperand(MI, 2, O); |
14578 | | O << ") = "; |
14579 | | printOperand(MI, 3, O); |
14580 | | break; |
14581 | | case 611: |
14582 | | // S4_storerb_ur, S4_storerbnew_ur, S4_storerd_ur, S4_storerf_ur, S4_stor... |
14583 | | O << "<<#"; |
14584 | | printOperand(MI, 1, O); |
14585 | | O << "+#"; |
14586 | | printOperand(MI, 2, O); |
14587 | | O << ") = "; |
14588 | | printOperand(MI, 3, O); |
14589 | | break; |
14590 | | case 612: |
14591 | | // S4_vrcrotate |
14592 | | O << " = vrcrotate("; |
14593 | | printOperand(MI, 1, O); |
14594 | | O << ','; |
14595 | | printOperand(MI, 2, O); |
14596 | | O << ",#"; |
14597 | | printOperand(MI, 3, O); |
14598 | | O << ')'; |
14599 | | return; |
14600 | | break; |
14601 | | case 613: |
14602 | | // S4_vrcrotate_acc |
14603 | | O << " += vrcrotate("; |
14604 | | printOperand(MI, 2, O); |
14605 | | O << ','; |
14606 | | printOperand(MI, 3, O); |
14607 | | O << ",#"; |
14608 | | printOperand(MI, 4, O); |
14609 | | O << ')'; |
14610 | | return; |
14611 | | break; |
14612 | | case 614: |
14613 | | // S4_vxaddsubh, S4_vxaddsubhr |
14614 | | O << " = vxaddsubh("; |
14615 | | printOperand(MI, 1, O); |
14616 | | O << ','; |
14617 | | printOperand(MI, 2, O); |
14618 | | break; |
14619 | | case 615: |
14620 | | // S4_vxaddsubw |
14621 | | O << " = vxaddsubw("; |
14622 | | printOperand(MI, 1, O); |
14623 | | O << ','; |
14624 | | printOperand(MI, 2, O); |
14625 | | O << "):sat"; |
14626 | | return; |
14627 | | break; |
14628 | | case 616: |
14629 | | // S4_vxsubaddh, S4_vxsubaddhr |
14630 | | O << " = vxsubaddh("; |
14631 | | printOperand(MI, 1, O); |
14632 | | O << ','; |
14633 | | printOperand(MI, 2, O); |
14634 | | break; |
14635 | | case 617: |
14636 | | // S4_vxsubaddw |
14637 | | O << " = vxsubaddw("; |
14638 | | printOperand(MI, 1, O); |
14639 | | O << ','; |
14640 | | printOperand(MI, 2, O); |
14641 | | O << "):sat"; |
14642 | | return; |
14643 | | break; |
14644 | | case 618: |
14645 | | // S5_popcountp |
14646 | | O << " = popcount("; |
14647 | | printOperand(MI, 1, O); |
14648 | | O << ')'; |
14649 | | return; |
14650 | | break; |
14651 | | case 619: |
14652 | | // S6_rol_i_p, S6_rol_i_r |
14653 | | O << " = rol("; |
14654 | | printOperand(MI, 1, O); |
14655 | | O << ",#"; |
14656 | | printOperand(MI, 2, O); |
14657 | | O << ')'; |
14658 | | return; |
14659 | | break; |
14660 | | case 620: |
14661 | | // S6_rol_i_p_acc, S6_rol_i_r_acc |
14662 | | O << " += rol("; |
14663 | | printOperand(MI, 2, O); |
14664 | | O << ",#"; |
14665 | | printOperand(MI, 3, O); |
14666 | | O << ')'; |
14667 | | return; |
14668 | | break; |
14669 | | case 621: |
14670 | | // S6_rol_i_p_and, S6_rol_i_r_and |
14671 | | O << " &= rol("; |
14672 | | printOperand(MI, 2, O); |
14673 | | O << ",#"; |
14674 | | printOperand(MI, 3, O); |
14675 | | O << ')'; |
14676 | | return; |
14677 | | break; |
14678 | | case 622: |
14679 | | // S6_rol_i_p_nac, S6_rol_i_r_nac |
14680 | | O << " -= rol("; |
14681 | | printOperand(MI, 2, O); |
14682 | | O << ",#"; |
14683 | | printOperand(MI, 3, O); |
14684 | | O << ')'; |
14685 | | return; |
14686 | | break; |
14687 | | case 623: |
14688 | | // S6_rol_i_p_or, S6_rol_i_r_or |
14689 | | O << " |= rol("; |
14690 | | printOperand(MI, 2, O); |
14691 | | O << ",#"; |
14692 | | printOperand(MI, 3, O); |
14693 | | O << ')'; |
14694 | | return; |
14695 | | break; |
14696 | | case 624: |
14697 | | // S6_rol_i_p_xacc, S6_rol_i_r_xacc |
14698 | | O << " ^= rol("; |
14699 | | printOperand(MI, 2, O); |
14700 | | O << ",#"; |
14701 | | printOperand(MI, 3, O); |
14702 | | O << ')'; |
14703 | | return; |
14704 | | break; |
14705 | | case 625: |
14706 | | // SA1_addsp |
14707 | | O << " = add(r29,#"; |
14708 | | printOperand(MI, 1, O); |
14709 | | O << ')'; |
14710 | | return; |
14711 | | break; |
14712 | | case 626: |
14713 | | // SA1_combine0i |
14714 | | O << " = combine(#0,#"; |
14715 | | printOperand(MI, 1, O); |
14716 | | O << ')'; |
14717 | | return; |
14718 | | break; |
14719 | | case 627: |
14720 | | // SA1_combine1i |
14721 | | O << " = combine(#1,#"; |
14722 | | printOperand(MI, 1, O); |
14723 | | O << ')'; |
14724 | | return; |
14725 | | break; |
14726 | | case 628: |
14727 | | // SA1_combine2i |
14728 | | O << " = combine(#2,#"; |
14729 | | printOperand(MI, 1, O); |
14730 | | O << ')'; |
14731 | | return; |
14732 | | break; |
14733 | | case 629: |
14734 | | // SA1_combine3i |
14735 | | O << " = combine(#3,#"; |
14736 | | printOperand(MI, 1, O); |
14737 | | O << ')'; |
14738 | | return; |
14739 | | break; |
14740 | | case 630: |
14741 | | // SA1_combinezr |
14742 | | O << " = combine(#0,"; |
14743 | | printOperand(MI, 1, O); |
14744 | | O << ')'; |
14745 | | return; |
14746 | | break; |
14747 | | case 631: |
14748 | | // SL2_loadrd_sp |
14749 | | O << " = memd(r29+#"; |
14750 | | printOperand(MI, 1, O); |
14751 | | O << ')'; |
14752 | | return; |
14753 | | break; |
14754 | | case 632: |
14755 | | // SL2_loadri_sp |
14756 | | O << " = memw(r29+#"; |
14757 | | printOperand(MI, 1, O); |
14758 | | O << ')'; |
14759 | | return; |
14760 | | break; |
14761 | | case 633: |
14762 | | // V6_extractw |
14763 | | O << " = vextract("; |
14764 | | printOperand(MI, 1, O); |
14765 | | O << ','; |
14766 | | printOperand(MI, 2, O); |
14767 | | O << ')'; |
14768 | | return; |
14769 | | break; |
14770 | | case 634: |
14771 | | // V6_lvsplatb |
14772 | | O << ".b = vsplat("; |
14773 | | printOperand(MI, 1, O); |
14774 | | O << ')'; |
14775 | | return; |
14776 | | break; |
14777 | | case 635: |
14778 | | // V6_lvsplath |
14779 | | O << ".h = vsplat("; |
14780 | | printOperand(MI, 1, O); |
14781 | | O << ')'; |
14782 | | return; |
14783 | | break; |
14784 | | case 636: |
14785 | | // V6_lvsplatw |
14786 | | O << " = vsplat("; |
14787 | | printOperand(MI, 1, O); |
14788 | | O << ')'; |
14789 | | return; |
14790 | | break; |
14791 | | case 637: |
14792 | | // V6_pred_scalar2 |
14793 | | O << " = vsetq("; |
14794 | | printOperand(MI, 1, O); |
14795 | | O << ')'; |
14796 | | return; |
14797 | | break; |
14798 | | case 638: |
14799 | | // V6_pred_scalar2v2 |
14800 | | O << " = vsetq2("; |
14801 | | printOperand(MI, 1, O); |
14802 | | O << ')'; |
14803 | | return; |
14804 | | break; |
14805 | | case 639: |
14806 | | // V6_shuffeqh, V6_vshuffeb |
14807 | | O << ".b = vshuffe("; |
14808 | | printOperand(MI, 1, O); |
14809 | | break; |
14810 | | case 640: |
14811 | | // V6_shuffeqw, V6_vshufeh |
14812 | | O << ".h = vshuffe("; |
14813 | | printOperand(MI, 1, O); |
14814 | | break; |
14815 | | case 641: |
14816 | | // V6_v6mpyhubs10_vxx, V6_v6mpyvubs10_vxx |
14817 | | O << ".w += v6mpy("; |
14818 | | printOperand(MI, 2, O); |
14819 | | O << ".ub,"; |
14820 | | printOperand(MI, 3, O); |
14821 | | O << ".b,#"; |
14822 | | printOperand(MI, 4, O); |
14823 | | break; |
14824 | | case 642: |
14825 | | // V6_vL32b_cur_ai, V6_vL32b_cur_pi, V6_vL32b_cur_ppu, V6_vL32b_nt_cur_ai... |
14826 | | O << ".cur = vmem("; |
14827 | | printOperand(MI, 1, O); |
14828 | | break; |
14829 | | case 643: |
14830 | | // V6_vL32b_nt_tmp_ai, V6_vL32b_nt_tmp_pi, V6_vL32b_nt_tmp_ppu, V6_vL32b_... |
14831 | | O << ".tmp = vmem("; |
14832 | | printOperand(MI, 1, O); |
14833 | | break; |
14834 | | case 644: |
14835 | | // V6_vabs_hf |
14836 | | O << ".hf = vabs("; |
14837 | | printOperand(MI, 1, O); |
14838 | | O << ".hf)"; |
14839 | | return; |
14840 | | break; |
14841 | | case 645: |
14842 | | // V6_vabs_sf |
14843 | | O << ".sf = vabs("; |
14844 | | printOperand(MI, 1, O); |
14845 | | O << ".sf)"; |
14846 | | return; |
14847 | | break; |
14848 | | case 646: |
14849 | | // V6_vabsb, V6_vabsb_sat |
14850 | | O << ".b = vabs("; |
14851 | | printOperand(MI, 1, O); |
14852 | | break; |
14853 | | case 647: |
14854 | | // V6_vabsdiffh, V6_vabsdiffuh |
14855 | | O << ".uh = vabsdiff("; |
14856 | | printOperand(MI, 1, O); |
14857 | | break; |
14858 | | case 648: |
14859 | | // V6_vabsdiffub |
14860 | | O << ".ub = vabsdiff("; |
14861 | | printOperand(MI, 1, O); |
14862 | | O << ".ub,"; |
14863 | | printOperand(MI, 2, O); |
14864 | | O << ".ub)"; |
14865 | | return; |
14866 | | break; |
14867 | | case 649: |
14868 | | // V6_vabsdiffw |
14869 | | O << ".uw = vabsdiff("; |
14870 | | printOperand(MI, 1, O); |
14871 | | O << ".w,"; |
14872 | | printOperand(MI, 2, O); |
14873 | | O << ".w)"; |
14874 | | return; |
14875 | | break; |
14876 | | case 650: |
14877 | | // V6_vabsh, V6_vabsh_sat |
14878 | | O << ".h = vabs("; |
14879 | | printOperand(MI, 1, O); |
14880 | | break; |
14881 | | case 651: |
14882 | | // V6_vabsw, V6_vabsw_sat |
14883 | | O << ".w = vabs("; |
14884 | | printOperand(MI, 1, O); |
14885 | | break; |
14886 | | case 652: |
14887 | | // V6_vadd_hf, V6_vadd_qf16, V6_vadd_qf16_mix |
14888 | | O << ".qf16 = vadd("; |
14889 | | printOperand(MI, 1, O); |
14890 | | break; |
14891 | | case 653: |
14892 | | // V6_vadd_hf_hf |
14893 | | O << ".hf = vadd("; |
14894 | | printOperand(MI, 1, O); |
14895 | | O << ".hf,"; |
14896 | | printOperand(MI, 2, O); |
14897 | | O << ".hf)"; |
14898 | | return; |
14899 | | break; |
14900 | | case 654: |
14901 | | // V6_vadd_qf32, V6_vadd_qf32_mix, V6_vadd_sf |
14902 | | O << ".qf32 = vadd("; |
14903 | | printOperand(MI, 1, O); |
14904 | | break; |
14905 | | case 655: |
14906 | | // V6_vadd_sf_bf, V6_vadd_sf_hf, V6_vadd_sf_sf |
14907 | | O << ".sf = vadd("; |
14908 | | printOperand(MI, 1, O); |
14909 | | break; |
14910 | | case 656: |
14911 | | // V6_vaddb, V6_vaddb_dv, V6_vaddbsat, V6_vaddbsat_dv |
14912 | | O << ".b = vadd("; |
14913 | | printOperand(MI, 1, O); |
14914 | | O << ".b,"; |
14915 | | printOperand(MI, 2, O); |
14916 | | break; |
14917 | | case 657: |
14918 | | // V6_vaddcarry, V6_vaddcarrysat, V6_vaddhw, V6_vadduhw, V6_vaddw, V6_vad... |
14919 | | O << ".w = vadd("; |
14920 | | break; |
14921 | | case 658: |
14922 | | // V6_vaddcarryo, V6_vsubcarryo |
14923 | | O << ".w,"; |
14924 | | printOperand(MI, 1, O); |
14925 | | break; |
14926 | | case 659: |
14927 | | // V6_vaddclbh |
14928 | | O << ".h = vadd(vclb("; |
14929 | | printOperand(MI, 1, O); |
14930 | | O << ".h),"; |
14931 | | printOperand(MI, 2, O); |
14932 | | O << ".h)"; |
14933 | | return; |
14934 | | break; |
14935 | | case 660: |
14936 | | // V6_vaddclbw |
14937 | | O << ".w = vadd(vclb("; |
14938 | | printOperand(MI, 1, O); |
14939 | | O << ".w),"; |
14940 | | printOperand(MI, 2, O); |
14941 | | O << ".w)"; |
14942 | | return; |
14943 | | break; |
14944 | | case 661: |
14945 | | // V6_vaddh, V6_vaddh_dv, V6_vaddhsat, V6_vaddhsat_dv, V6_vaddubh |
14946 | | O << ".h = vadd("; |
14947 | | printOperand(MI, 1, O); |
14948 | | break; |
14949 | | case 662: |
14950 | | // V6_vaddhw_acc, V6_vadduhw_acc |
14951 | | O << ".w += vadd("; |
14952 | | printOperand(MI, 2, O); |
14953 | | break; |
14954 | | case 663: |
14955 | | // V6_vaddubh_acc |
14956 | | O << ".h += vadd("; |
14957 | | printOperand(MI, 2, O); |
14958 | | O << ".ub,"; |
14959 | | printOperand(MI, 3, O); |
14960 | | O << ".ub)"; |
14961 | | return; |
14962 | | break; |
14963 | | case 664: |
14964 | | // V6_vaddubsat, V6_vaddubsat_dv, V6_vaddububb_sat |
14965 | | O << ".ub = vadd("; |
14966 | | printOperand(MI, 1, O); |
14967 | | O << ".ub,"; |
14968 | | printOperand(MI, 2, O); |
14969 | | break; |
14970 | | case 665: |
14971 | | // V6_vadduhsat, V6_vadduhsat_dv |
14972 | | O << ".uh = vadd("; |
14973 | | printOperand(MI, 1, O); |
14974 | | O << ".uh,"; |
14975 | | printOperand(MI, 2, O); |
14976 | | O << ".uh):sat"; |
14977 | | return; |
14978 | | break; |
14979 | | case 666: |
14980 | | // V6_vadduwsat, V6_vadduwsat_dv |
14981 | | O << ".uw = vadd("; |
14982 | | printOperand(MI, 1, O); |
14983 | | O << ".uw,"; |
14984 | | printOperand(MI, 2, O); |
14985 | | O << ".uw):sat"; |
14986 | | return; |
14987 | | break; |
14988 | | case 667: |
14989 | | // V6_valignb, V6_valignbi |
14990 | | O << " = valign("; |
14991 | | printOperand(MI, 1, O); |
14992 | | O << ','; |
14993 | | printOperand(MI, 2, O); |
14994 | | break; |
14995 | | case 668: |
14996 | | // V6_vand, V6_vandqrt, V6_vandvqv, V6_vandvrt |
14997 | | O << " = vand("; |
14998 | | printOperand(MI, 1, O); |
14999 | | O << ','; |
15000 | | printOperand(MI, 2, O); |
15001 | | O << ')'; |
15002 | | return; |
15003 | | break; |
15004 | | case 669: |
15005 | | // V6_vandnqrt, V6_vandvnqv |
15006 | | O << " = vand(!"; |
15007 | | printOperand(MI, 1, O); |
15008 | | O << ','; |
15009 | | printOperand(MI, 2, O); |
15010 | | O << ')'; |
15011 | | return; |
15012 | | break; |
15013 | | case 670: |
15014 | | // V6_vandnqrt_acc |
15015 | | O << " |= vand(!"; |
15016 | | printOperand(MI, 2, O); |
15017 | | O << ','; |
15018 | | printOperand(MI, 3, O); |
15019 | | O << ')'; |
15020 | | return; |
15021 | | break; |
15022 | | case 671: |
15023 | | // V6_vandqrt_acc, V6_vandvrt_acc |
15024 | | O << " |= vand("; |
15025 | | printOperand(MI, 2, O); |
15026 | | O << ','; |
15027 | | printOperand(MI, 3, O); |
15028 | | O << ')'; |
15029 | | return; |
15030 | | break; |
15031 | | case 672: |
15032 | | // V6_vaslh, V6_vaslhv |
15033 | | O << ".h = vasl("; |
15034 | | printOperand(MI, 1, O); |
15035 | | O << ".h,"; |
15036 | | printOperand(MI, 2, O); |
15037 | | break; |
15038 | | case 673: |
15039 | | // V6_vaslh_acc |
15040 | | O << ".h += vasl("; |
15041 | | printOperand(MI, 2, O); |
15042 | | O << ".h,"; |
15043 | | printOperand(MI, 3, O); |
15044 | | O << ')'; |
15045 | | return; |
15046 | | break; |
15047 | | case 674: |
15048 | | // V6_vaslw, V6_vaslwv |
15049 | | O << ".w = vasl("; |
15050 | | printOperand(MI, 1, O); |
15051 | | O << ".w,"; |
15052 | | printOperand(MI, 2, O); |
15053 | | break; |
15054 | | case 675: |
15055 | | // V6_vaslw_acc |
15056 | | O << ".w += vasl("; |
15057 | | printOperand(MI, 2, O); |
15058 | | O << ".w,"; |
15059 | | printOperand(MI, 3, O); |
15060 | | O << ')'; |
15061 | | return; |
15062 | | break; |
15063 | | case 676: |
15064 | | // V6_vasr_into |
15065 | | O << ".w = vasrinto("; |
15066 | | printOperand(MI, 2, O); |
15067 | | O << ".w,"; |
15068 | | printOperand(MI, 3, O); |
15069 | | O << ".w)"; |
15070 | | return; |
15071 | | break; |
15072 | | case 677: |
15073 | | // V6_vasrh, V6_vasrhv, V6_vasrwh, V6_vasrwhrndsat, V6_vasrwhsat |
15074 | | O << ".h = vasr("; |
15075 | | printOperand(MI, 1, O); |
15076 | | break; |
15077 | | case 678: |
15078 | | // V6_vasrh_acc |
15079 | | O << ".h += vasr("; |
15080 | | printOperand(MI, 2, O); |
15081 | | O << ".h,"; |
15082 | | printOperand(MI, 3, O); |
15083 | | O << ')'; |
15084 | | return; |
15085 | | break; |
15086 | | case 679: |
15087 | | // V6_vasrhbrndsat, V6_vasrhbsat |
15088 | | O << ".b = vasr("; |
15089 | | printOperand(MI, 1, O); |
15090 | | O << ".h,"; |
15091 | | printOperand(MI, 2, O); |
15092 | | O << ".h,"; |
15093 | | printOperand(MI, 3, O); |
15094 | | break; |
15095 | | case 680: |
15096 | | // V6_vasrhubrndsat, V6_vasrhubsat, V6_vasruhubrndsat, V6_vasruhubsat, V6... |
15097 | | O << ".ub = vasr("; |
15098 | | printOperand(MI, 1, O); |
15099 | | break; |
15100 | | case 681: |
15101 | | // V6_vasruwuhrndsat, V6_vasruwuhsat, V6_vasrvwuhrndsat, V6_vasrvwuhsat, ... |
15102 | | O << ".uh = vasr("; |
15103 | | printOperand(MI, 1, O); |
15104 | | break; |
15105 | | case 682: |
15106 | | // V6_vasrw, V6_vasrwv |
15107 | | O << ".w = vasr("; |
15108 | | printOperand(MI, 1, O); |
15109 | | O << ".w,"; |
15110 | | printOperand(MI, 2, O); |
15111 | | break; |
15112 | | case 683: |
15113 | | // V6_vasrw_acc |
15114 | | O << ".w += vasr("; |
15115 | | printOperand(MI, 2, O); |
15116 | | O << ".w,"; |
15117 | | printOperand(MI, 3, O); |
15118 | | O << ')'; |
15119 | | return; |
15120 | | break; |
15121 | | case 684: |
15122 | | // V6_vassign_fp |
15123 | | O << ".w = vfmv("; |
15124 | | printOperand(MI, 1, O); |
15125 | | O << ".w)"; |
15126 | | return; |
15127 | | break; |
15128 | | case 685: |
15129 | | // V6_vassign_tmp |
15130 | | O << ".tmp = "; |
15131 | | printOperand(MI, 1, O); |
15132 | | return; |
15133 | | break; |
15134 | | case 686: |
15135 | | // V6_vavgb, V6_vavgbrnd |
15136 | | O << ".b = vavg("; |
15137 | | printOperand(MI, 1, O); |
15138 | | O << ".b,"; |
15139 | | printOperand(MI, 2, O); |
15140 | | break; |
15141 | | case 687: |
15142 | | // V6_vavgh, V6_vavghrnd |
15143 | | O << ".h = vavg("; |
15144 | | printOperand(MI, 1, O); |
15145 | | O << ".h,"; |
15146 | | printOperand(MI, 2, O); |
15147 | | break; |
15148 | | case 688: |
15149 | | // V6_vavgub, V6_vavgubrnd |
15150 | | O << ".ub = vavg("; |
15151 | | printOperand(MI, 1, O); |
15152 | | O << ".ub,"; |
15153 | | printOperand(MI, 2, O); |
15154 | | break; |
15155 | | case 689: |
15156 | | // V6_vavguh, V6_vavguhrnd |
15157 | | O << ".uh = vavg("; |
15158 | | printOperand(MI, 1, O); |
15159 | | O << ".uh,"; |
15160 | | printOperand(MI, 2, O); |
15161 | | break; |
15162 | | case 690: |
15163 | | // V6_vavguw, V6_vavguwrnd |
15164 | | O << ".uw = vavg("; |
15165 | | printOperand(MI, 1, O); |
15166 | | O << ".uw,"; |
15167 | | printOperand(MI, 2, O); |
15168 | | break; |
15169 | | case 691: |
15170 | | // V6_vavgw, V6_vavgwrnd |
15171 | | O << ".w = vavg("; |
15172 | | printOperand(MI, 1, O); |
15173 | | O << ".w,"; |
15174 | | printOperand(MI, 2, O); |
15175 | | break; |
15176 | | case 692: |
15177 | | // V6_vcl0h |
15178 | | O << ".uh = vcl0("; |
15179 | | printOperand(MI, 1, O); |
15180 | | O << ".uh)"; |
15181 | | return; |
15182 | | break; |
15183 | | case 693: |
15184 | | // V6_vcl0w |
15185 | | O << ".uw = vcl0("; |
15186 | | printOperand(MI, 1, O); |
15187 | | O << ".uw)"; |
15188 | | return; |
15189 | | break; |
15190 | | case 694: |
15191 | | // V6_vcombine |
15192 | | O << " = vcombine("; |
15193 | | printOperand(MI, 1, O); |
15194 | | O << ','; |
15195 | | printOperand(MI, 2, O); |
15196 | | O << ')'; |
15197 | | return; |
15198 | | break; |
15199 | | case 695: |
15200 | | // V6_vcombine_tmp |
15201 | | O << ".tmp = vcombine("; |
15202 | | printOperand(MI, 1, O); |
15203 | | O << ','; |
15204 | | printOperand(MI, 2, O); |
15205 | | O << ')'; |
15206 | | return; |
15207 | | break; |
15208 | | case 696: |
15209 | | // V6_vconv_h_hf |
15210 | | O << ".h = "; |
15211 | | printOperand(MI, 1, O); |
15212 | | O << ".hf"; |
15213 | | return; |
15214 | | break; |
15215 | | case 697: |
15216 | | // V6_vconv_hf_h, V6_vconv_hf_qf16, V6_vconv_hf_qf32 |
15217 | | O << ".hf = "; |
15218 | | printOperand(MI, 1, O); |
15219 | | break; |
15220 | | case 698: |
15221 | | // V6_vconv_sf_qf32, V6_vconv_sf_w |
15222 | | O << ".sf = "; |
15223 | | printOperand(MI, 1, O); |
15224 | | break; |
15225 | | case 699: |
15226 | | // V6_vconv_w_sf |
15227 | | O << ".w = "; |
15228 | | printOperand(MI, 1, O); |
15229 | | O << ".sf"; |
15230 | | return; |
15231 | | break; |
15232 | | case 700: |
15233 | | // V6_vcvt_b_hf |
15234 | | O << ".b = vcvt("; |
15235 | | printOperand(MI, 1, O); |
15236 | | O << ".hf,"; |
15237 | | printOperand(MI, 2, O); |
15238 | | O << ".hf)"; |
15239 | | return; |
15240 | | break; |
15241 | | case 701: |
15242 | | // V6_vcvt_bf_sf |
15243 | | O << ".bf = vcvt("; |
15244 | | printOperand(MI, 1, O); |
15245 | | O << ".sf,"; |
15246 | | printOperand(MI, 2, O); |
15247 | | O << ".sf)"; |
15248 | | return; |
15249 | | break; |
15250 | | case 702: |
15251 | | // V6_vcvt_h_hf |
15252 | | O << ".h = vcvt("; |
15253 | | printOperand(MI, 1, O); |
15254 | | O << ".hf)"; |
15255 | | return; |
15256 | | break; |
15257 | | case 703: |
15258 | | // V6_vcvt_hf_b, V6_vcvt_hf_h, V6_vcvt_hf_sf, V6_vcvt_hf_ub, V6_vcvt_hf_u... |
15259 | | O << ".hf = vcvt("; |
15260 | | printOperand(MI, 1, O); |
15261 | | break; |
15262 | | case 704: |
15263 | | // V6_vcvt_sf_hf |
15264 | | O << ".sf = vcvt("; |
15265 | | printOperand(MI, 1, O); |
15266 | | O << ".hf)"; |
15267 | | return; |
15268 | | break; |
15269 | | case 705: |
15270 | | // V6_vcvt_ub_hf |
15271 | | O << ".ub = vcvt("; |
15272 | | printOperand(MI, 1, O); |
15273 | | O << ".hf,"; |
15274 | | printOperand(MI, 2, O); |
15275 | | O << ".hf)"; |
15276 | | return; |
15277 | | break; |
15278 | | case 706: |
15279 | | // V6_vcvt_uh_hf |
15280 | | O << ".uh = vcvt("; |
15281 | | printOperand(MI, 1, O); |
15282 | | O << ".hf)"; |
15283 | | return; |
15284 | | break; |
15285 | | case 707: |
15286 | | // V6_vdealb |
15287 | | O << ".b = vdeal("; |
15288 | | printOperand(MI, 1, O); |
15289 | | O << ".b)"; |
15290 | | return; |
15291 | | break; |
15292 | | case 708: |
15293 | | // V6_vdealb4w |
15294 | | O << ".b = vdeale("; |
15295 | | printOperand(MI, 1, O); |
15296 | | O << ".b,"; |
15297 | | printOperand(MI, 2, O); |
15298 | | O << ".b)"; |
15299 | | return; |
15300 | | break; |
15301 | | case 709: |
15302 | | // V6_vdealh |
15303 | | O << ".h = vdeal("; |
15304 | | printOperand(MI, 1, O); |
15305 | | O << ".h)"; |
15306 | | return; |
15307 | | break; |
15308 | | case 710: |
15309 | | // V6_vdealvdd |
15310 | | O << " = vdeal("; |
15311 | | printOperand(MI, 1, O); |
15312 | | O << ','; |
15313 | | printOperand(MI, 2, O); |
15314 | | O << ','; |
15315 | | printOperand(MI, 3, O); |
15316 | | O << ')'; |
15317 | | return; |
15318 | | break; |
15319 | | case 711: |
15320 | | // V6_vdelta |
15321 | | O << " = vdelta("; |
15322 | | printOperand(MI, 1, O); |
15323 | | O << ','; |
15324 | | printOperand(MI, 2, O); |
15325 | | O << ')'; |
15326 | | return; |
15327 | | break; |
15328 | | case 712: |
15329 | | // V6_vdmpy_sf_hf |
15330 | | O << ".sf = vdmpy("; |
15331 | | printOperand(MI, 1, O); |
15332 | | O << ".hf,"; |
15333 | | printOperand(MI, 2, O); |
15334 | | O << ".hf)"; |
15335 | | return; |
15336 | | break; |
15337 | | case 713: |
15338 | | // V6_vdmpy_sf_hf_acc |
15339 | | O << ".sf += vdmpy("; |
15340 | | printOperand(MI, 2, O); |
15341 | | O << ".hf,"; |
15342 | | printOperand(MI, 3, O); |
15343 | | O << ".hf)"; |
15344 | | return; |
15345 | | break; |
15346 | | case 714: |
15347 | | // V6_vdmpybus, V6_vdmpybus_dv |
15348 | | O << ".h = vdmpy("; |
15349 | | printOperand(MI, 1, O); |
15350 | | O << ".ub,"; |
15351 | | printOperand(MI, 2, O); |
15352 | | O << ".b)"; |
15353 | | return; |
15354 | | break; |
15355 | | case 715: |
15356 | | // V6_vdmpybus_acc, V6_vdmpybus_dv_acc |
15357 | | O << ".h += vdmpy("; |
15358 | | printOperand(MI, 2, O); |
15359 | | O << ".ub,"; |
15360 | | printOperand(MI, 3, O); |
15361 | | O << ".b)"; |
15362 | | return; |
15363 | | break; |
15364 | | case 716: |
15365 | | // V6_vdmpyhb, V6_vdmpyhb_dv, V6_vdmpyhisat, V6_vdmpyhsat, V6_vdmpyhsuisa... |
15366 | | O << ".w = vdmpy("; |
15367 | | printOperand(MI, 1, O); |
15368 | | O << ".h,"; |
15369 | | printOperand(MI, 2, O); |
15370 | | break; |
15371 | | case 717: |
15372 | | // V6_vdmpyhb_acc, V6_vdmpyhb_dv_acc, V6_vdmpyhisat_acc, V6_vdmpyhsat_acc... |
15373 | | O << ".w += vdmpy("; |
15374 | | printOperand(MI, 2, O); |
15375 | | O << ".h,"; |
15376 | | printOperand(MI, 3, O); |
15377 | | break; |
15378 | | case 718: |
15379 | | // V6_vdsaduh |
15380 | | O << ".uw = vdsad("; |
15381 | | printOperand(MI, 1, O); |
15382 | | O << ".uh,"; |
15383 | | printOperand(MI, 2, O); |
15384 | | O << ".uh)"; |
15385 | | return; |
15386 | | break; |
15387 | | case 719: |
15388 | | // V6_vdsaduh_acc |
15389 | | O << ".uw += vdsad("; |
15390 | | printOperand(MI, 2, O); |
15391 | | O << ".uh,"; |
15392 | | printOperand(MI, 3, O); |
15393 | | O << ".uh)"; |
15394 | | return; |
15395 | | break; |
15396 | | case 720: |
15397 | | // V6_vfmax_hf |
15398 | | O << ".hf = vfmax("; |
15399 | | printOperand(MI, 1, O); |
15400 | | O << ".hf,"; |
15401 | | printOperand(MI, 2, O); |
15402 | | O << ".hf)"; |
15403 | | return; |
15404 | | break; |
15405 | | case 721: |
15406 | | // V6_vfmax_sf |
15407 | | O << ".sf = vfmax("; |
15408 | | printOperand(MI, 1, O); |
15409 | | O << ".sf,"; |
15410 | | printOperand(MI, 2, O); |
15411 | | O << ".sf)"; |
15412 | | return; |
15413 | | break; |
15414 | | case 722: |
15415 | | // V6_vfmin_hf |
15416 | | O << ".hf = vfmin("; |
15417 | | printOperand(MI, 1, O); |
15418 | | O << ".hf,"; |
15419 | | printOperand(MI, 2, O); |
15420 | | O << ".hf)"; |
15421 | | return; |
15422 | | break; |
15423 | | case 723: |
15424 | | // V6_vfmin_sf |
15425 | | O << ".sf = vfmin("; |
15426 | | printOperand(MI, 1, O); |
15427 | | O << ".sf,"; |
15428 | | printOperand(MI, 2, O); |
15429 | | O << ".sf)"; |
15430 | | return; |
15431 | | break; |
15432 | | case 724: |
15433 | | // V6_vfneg_hf |
15434 | | O << ".hf = vfneg("; |
15435 | | printOperand(MI, 1, O); |
15436 | | O << ".hf)"; |
15437 | | return; |
15438 | | break; |
15439 | | case 725: |
15440 | | // V6_vfneg_sf |
15441 | | O << ".sf = vfneg("; |
15442 | | printOperand(MI, 1, O); |
15443 | | O << ".sf)"; |
15444 | | return; |
15445 | | break; |
15446 | | case 726: |
15447 | | // V6_vgathermhq, V6_vgathermhwq |
15448 | | O << ") vtmp.h = vgather("; |
15449 | | printOperand(MI, 1, O); |
15450 | | O << ','; |
15451 | | printOperand(MI, 2, O); |
15452 | | O << ','; |
15453 | | printOperand(MI, 3, O); |
15454 | | break; |
15455 | | case 727: |
15456 | | // V6_vgathermwq |
15457 | | O << ") vtmp.w = vgather("; |
15458 | | printOperand(MI, 1, O); |
15459 | | O << ','; |
15460 | | printOperand(MI, 2, O); |
15461 | | O << ','; |
15462 | | printOperand(MI, 3, O); |
15463 | | O << ".w).w"; |
15464 | | return; |
15465 | | break; |
15466 | | case 728: |
15467 | | // V6_vgtb, V6_vgtbf, V6_vgth, V6_vgthf, V6_vgtsf, V6_vgtub, V6_vgtuh, V6... |
15468 | | O << " = vcmp.gt("; |
15469 | | printOperand(MI, 1, O); |
15470 | | break; |
15471 | | case 729: |
15472 | | // V6_vgtb_and, V6_vgtbf_and, V6_vgth_and, V6_vgthf_and, V6_vgtsf_and, V6... |
15473 | | O << " &= vcmp.gt("; |
15474 | | printOperand(MI, 2, O); |
15475 | | break; |
15476 | | case 730: |
15477 | | // V6_vgtb_or, V6_vgtbf_or, V6_vgth_or, V6_vgthf_or, V6_vgtsf_or, V6_vgtu... |
15478 | | O << " |= vcmp.gt("; |
15479 | | printOperand(MI, 2, O); |
15480 | | break; |
15481 | | case 731: |
15482 | | // V6_vgtb_xor, V6_vgtbf_xor, V6_vgth_xor, V6_vgthf_xor, V6_vgtsf_xor, V6... |
15483 | | O << " ^= vcmp.gt("; |
15484 | | printOperand(MI, 2, O); |
15485 | | break; |
15486 | | case 732: |
15487 | | // V6_vinsertwr |
15488 | | O << ".w = vinsert("; |
15489 | | printOperand(MI, 2, O); |
15490 | | O << ')'; |
15491 | | return; |
15492 | | break; |
15493 | | case 733: |
15494 | | // V6_vlalignb, V6_vlalignbi |
15495 | | O << " = vlalign("; |
15496 | | printOperand(MI, 1, O); |
15497 | | O << ','; |
15498 | | printOperand(MI, 2, O); |
15499 | | break; |
15500 | | case 734: |
15501 | | // V6_vlsrb |
15502 | | O << ".ub = vlsr("; |
15503 | | printOperand(MI, 1, O); |
15504 | | O << ".ub,"; |
15505 | | printOperand(MI, 2, O); |
15506 | | O << ')'; |
15507 | | return; |
15508 | | break; |
15509 | | case 735: |
15510 | | // V6_vlsrh |
15511 | | O << ".uh = vlsr("; |
15512 | | printOperand(MI, 1, O); |
15513 | | O << ".uh,"; |
15514 | | printOperand(MI, 2, O); |
15515 | | O << ')'; |
15516 | | return; |
15517 | | break; |
15518 | | case 736: |
15519 | | // V6_vlsrhv |
15520 | | O << ".h = vlsr("; |
15521 | | printOperand(MI, 1, O); |
15522 | | O << ".h,"; |
15523 | | printOperand(MI, 2, O); |
15524 | | O << ".h)"; |
15525 | | return; |
15526 | | break; |
15527 | | case 737: |
15528 | | // V6_vlsrw |
15529 | | O << ".uw = vlsr("; |
15530 | | printOperand(MI, 1, O); |
15531 | | O << ".uw,"; |
15532 | | printOperand(MI, 2, O); |
15533 | | O << ')'; |
15534 | | return; |
15535 | | break; |
15536 | | case 738: |
15537 | | // V6_vlsrwv |
15538 | | O << ".w = vlsr("; |
15539 | | printOperand(MI, 1, O); |
15540 | | O << ".w,"; |
15541 | | printOperand(MI, 2, O); |
15542 | | O << ".w)"; |
15543 | | return; |
15544 | | break; |
15545 | | case 739: |
15546 | | // V6_vlut4 |
15547 | | O << ".h = vlut4("; |
15548 | | printOperand(MI, 1, O); |
15549 | | O << ".uh,"; |
15550 | | printOperand(MI, 2, O); |
15551 | | O << ".h)"; |
15552 | | return; |
15553 | | break; |
15554 | | case 740: |
15555 | | // V6_vlutvvb, V6_vlutvvb_nm, V6_vlutvvbi |
15556 | | O << ".b = vlut32("; |
15557 | | printOperand(MI, 1, O); |
15558 | | O << ".b,"; |
15559 | | printOperand(MI, 2, O); |
15560 | | break; |
15561 | | case 741: |
15562 | | // V6_vlutvvb_oracc, V6_vlutvvb_oracci |
15563 | | O << ".b |= vlut32("; |
15564 | | printOperand(MI, 2, O); |
15565 | | O << ".b,"; |
15566 | | printOperand(MI, 3, O); |
15567 | | break; |
15568 | | case 742: |
15569 | | // V6_vlutvwh, V6_vlutvwh_nm, V6_vlutvwhi |
15570 | | O << ".h = vlut16("; |
15571 | | printOperand(MI, 1, O); |
15572 | | O << ".b,"; |
15573 | | printOperand(MI, 2, O); |
15574 | | break; |
15575 | | case 743: |
15576 | | // V6_vlutvwh_oracc, V6_vlutvwh_oracci |
15577 | | O << ".h |= vlut16("; |
15578 | | printOperand(MI, 2, O); |
15579 | | O << ".b,"; |
15580 | | printOperand(MI, 3, O); |
15581 | | break; |
15582 | | case 744: |
15583 | | // V6_vmax_bf |
15584 | | O << ".bf = vmax("; |
15585 | | printOperand(MI, 1, O); |
15586 | | O << ".bf,"; |
15587 | | printOperand(MI, 2, O); |
15588 | | O << ".bf)"; |
15589 | | return; |
15590 | | break; |
15591 | | case 745: |
15592 | | // V6_vmax_hf |
15593 | | O << ".hf = vmax("; |
15594 | | printOperand(MI, 1, O); |
15595 | | O << ".hf,"; |
15596 | | printOperand(MI, 2, O); |
15597 | | O << ".hf)"; |
15598 | | return; |
15599 | | break; |
15600 | | case 746: |
15601 | | // V6_vmax_sf |
15602 | | O << ".sf = vmax("; |
15603 | | printOperand(MI, 1, O); |
15604 | | O << ".sf,"; |
15605 | | printOperand(MI, 2, O); |
15606 | | O << ".sf)"; |
15607 | | return; |
15608 | | break; |
15609 | | case 747: |
15610 | | // V6_vmaxb |
15611 | | O << ".b = vmax("; |
15612 | | printOperand(MI, 1, O); |
15613 | | O << ".b,"; |
15614 | | printOperand(MI, 2, O); |
15615 | | O << ".b)"; |
15616 | | return; |
15617 | | break; |
15618 | | case 748: |
15619 | | // V6_vmaxh |
15620 | | O << ".h = vmax("; |
15621 | | printOperand(MI, 1, O); |
15622 | | O << ".h,"; |
15623 | | printOperand(MI, 2, O); |
15624 | | O << ".h)"; |
15625 | | return; |
15626 | | break; |
15627 | | case 749: |
15628 | | // V6_vmaxub |
15629 | | O << ".ub = vmax("; |
15630 | | printOperand(MI, 1, O); |
15631 | | O << ".ub,"; |
15632 | | printOperand(MI, 2, O); |
15633 | | O << ".ub)"; |
15634 | | return; |
15635 | | break; |
15636 | | case 750: |
15637 | | // V6_vmaxuh |
15638 | | O << ".uh = vmax("; |
15639 | | printOperand(MI, 1, O); |
15640 | | O << ".uh,"; |
15641 | | printOperand(MI, 2, O); |
15642 | | O << ".uh)"; |
15643 | | return; |
15644 | | break; |
15645 | | case 751: |
15646 | | // V6_vmaxw |
15647 | | O << ".w = vmax("; |
15648 | | printOperand(MI, 1, O); |
15649 | | O << ".w,"; |
15650 | | printOperand(MI, 2, O); |
15651 | | O << ".w)"; |
15652 | | return; |
15653 | | break; |
15654 | | case 752: |
15655 | | // V6_vmin_bf |
15656 | | O << ".bf = vmin("; |
15657 | | printOperand(MI, 1, O); |
15658 | | O << ".bf,"; |
15659 | | printOperand(MI, 2, O); |
15660 | | O << ".bf)"; |
15661 | | return; |
15662 | | break; |
15663 | | case 753: |
15664 | | // V6_vmin_hf |
15665 | | O << ".hf = vmin("; |
15666 | | printOperand(MI, 1, O); |
15667 | | O << ".hf,"; |
15668 | | printOperand(MI, 2, O); |
15669 | | O << ".hf)"; |
15670 | | return; |
15671 | | break; |
15672 | | case 754: |
15673 | | // V6_vmin_sf |
15674 | | O << ".sf = vmin("; |
15675 | | printOperand(MI, 1, O); |
15676 | | O << ".sf,"; |
15677 | | printOperand(MI, 2, O); |
15678 | | O << ".sf)"; |
15679 | | return; |
15680 | | break; |
15681 | | case 755: |
15682 | | // V6_vminb |
15683 | | O << ".b = vmin("; |
15684 | | printOperand(MI, 1, O); |
15685 | | O << ".b,"; |
15686 | | printOperand(MI, 2, O); |
15687 | | O << ".b)"; |
15688 | | return; |
15689 | | break; |
15690 | | case 756: |
15691 | | // V6_vminh |
15692 | | O << ".h = vmin("; |
15693 | | printOperand(MI, 1, O); |
15694 | | O << ".h,"; |
15695 | | printOperand(MI, 2, O); |
15696 | | O << ".h)"; |
15697 | | return; |
15698 | | break; |
15699 | | case 757: |
15700 | | // V6_vminub |
15701 | | O << ".ub = vmin("; |
15702 | | printOperand(MI, 1, O); |
15703 | | O << ".ub,"; |
15704 | | printOperand(MI, 2, O); |
15705 | | O << ".ub)"; |
15706 | | return; |
15707 | | break; |
15708 | | case 758: |
15709 | | // V6_vminuh |
15710 | | O << ".uh = vmin("; |
15711 | | printOperand(MI, 1, O); |
15712 | | O << ".uh,"; |
15713 | | printOperand(MI, 2, O); |
15714 | | O << ".uh)"; |
15715 | | return; |
15716 | | break; |
15717 | | case 759: |
15718 | | // V6_vminw |
15719 | | O << ".w = vmin("; |
15720 | | printOperand(MI, 1, O); |
15721 | | O << ".w,"; |
15722 | | printOperand(MI, 2, O); |
15723 | | O << ".w)"; |
15724 | | return; |
15725 | | break; |
15726 | | case 760: |
15727 | | // V6_vmpabus, V6_vmpabusv, V6_vmpabuu, V6_vmpabuuv, V6_vmpahhsat, V6_vmp... |
15728 | | O << ".h = vmpa("; |
15729 | | printOperand(MI, 1, O); |
15730 | | break; |
15731 | | case 761: |
15732 | | // V6_vmpabus_acc, V6_vmpabuu_acc |
15733 | | O << ".h += vmpa("; |
15734 | | printOperand(MI, 2, O); |
15735 | | O << ".ub,"; |
15736 | | printOperand(MI, 3, O); |
15737 | | break; |
15738 | | case 762: |
15739 | | // V6_vmpahb, V6_vmpauhb |
15740 | | O << ".w = vmpa("; |
15741 | | printOperand(MI, 1, O); |
15742 | | break; |
15743 | | case 763: |
15744 | | // V6_vmpahb_acc, V6_vmpauhb_acc |
15745 | | O << ".w += vmpa("; |
15746 | | printOperand(MI, 2, O); |
15747 | | break; |
15748 | | case 764: |
15749 | | // V6_vmpsuhuhsat |
15750 | | O << ".h = vmps("; |
15751 | | printOperand(MI, 1, O); |
15752 | | O << ".h,"; |
15753 | | printOperand(MI, 2, O); |
15754 | | O << ".uh,"; |
15755 | | printOperand(MI, 3, O); |
15756 | | O << ".uh):sat"; |
15757 | | return; |
15758 | | break; |
15759 | | case 765: |
15760 | | // V6_vmpy_hf_hf |
15761 | | O << ".hf = vmpy("; |
15762 | | printOperand(MI, 1, O); |
15763 | | O << ".hf,"; |
15764 | | printOperand(MI, 2, O); |
15765 | | O << ".hf)"; |
15766 | | return; |
15767 | | break; |
15768 | | case 766: |
15769 | | // V6_vmpy_hf_hf_acc |
15770 | | O << ".hf += vmpy("; |
15771 | | printOperand(MI, 2, O); |
15772 | | O << ".hf,"; |
15773 | | printOperand(MI, 3, O); |
15774 | | O << ".hf)"; |
15775 | | return; |
15776 | | break; |
15777 | | case 767: |
15778 | | // V6_vmpy_qf16, V6_vmpy_qf16_hf, V6_vmpy_qf16_mix_hf |
15779 | | O << ".qf16 = vmpy("; |
15780 | | printOperand(MI, 1, O); |
15781 | | break; |
15782 | | case 768: |
15783 | | // V6_vmpy_qf32, V6_vmpy_qf32_hf, V6_vmpy_qf32_mix_hf, V6_vmpy_qf32_qf16,... |
15784 | | O << ".qf32 = vmpy("; |
15785 | | printOperand(MI, 1, O); |
15786 | | break; |
15787 | | case 769: |
15788 | | // V6_vmpy_sf_bf, V6_vmpy_sf_hf, V6_vmpy_sf_sf |
15789 | | O << ".sf = vmpy("; |
15790 | | printOperand(MI, 1, O); |
15791 | | break; |
15792 | | case 770: |
15793 | | // V6_vmpy_sf_bf_acc, V6_vmpy_sf_hf_acc |
15794 | | O << ".sf += vmpy("; |
15795 | | printOperand(MI, 2, O); |
15796 | | break; |
15797 | | case 771: |
15798 | | // V6_vmpybus, V6_vmpybusv, V6_vmpybv, V6_vmpyhsrs, V6_vmpyhss, V6_vmpyhv... |
15799 | | O << ".h = vmpy("; |
15800 | | printOperand(MI, 1, O); |
15801 | | break; |
15802 | | case 772: |
15803 | | // V6_vmpybus_acc, V6_vmpybusv_acc, V6_vmpybv_acc |
15804 | | O << ".h += vmpy("; |
15805 | | printOperand(MI, 2, O); |
15806 | | break; |
15807 | | case 773: |
15808 | | // V6_vmpyewuh |
15809 | | O << ".w = vmpye("; |
15810 | | printOperand(MI, 1, O); |
15811 | | O << ".w,"; |
15812 | | printOperand(MI, 2, O); |
15813 | | O << ".uh)"; |
15814 | | return; |
15815 | | break; |
15816 | | case 774: |
15817 | | // V6_vmpyewuh_64 |
15818 | | O << " = vmpye("; |
15819 | | printOperand(MI, 1, O); |
15820 | | O << ".w,"; |
15821 | | printOperand(MI, 2, O); |
15822 | | O << ".uh)"; |
15823 | | return; |
15824 | | break; |
15825 | | case 775: |
15826 | | // V6_vmpyh, V6_vmpyhus, V6_vmpyhv |
15827 | | O << ".w = vmpy("; |
15828 | | printOperand(MI, 1, O); |
15829 | | O << ".h,"; |
15830 | | printOperand(MI, 2, O); |
15831 | | break; |
15832 | | case 776: |
15833 | | // V6_vmpyh_acc, V6_vmpyhsat_acc, V6_vmpyhus_acc, V6_vmpyhv_acc |
15834 | | O << ".w += vmpy("; |
15835 | | printOperand(MI, 2, O); |
15836 | | O << ".h,"; |
15837 | | printOperand(MI, 3, O); |
15838 | | break; |
15839 | | case 777: |
15840 | | // V6_vmpyieoh |
15841 | | O << ".w = vmpyieo("; |
15842 | | printOperand(MI, 1, O); |
15843 | | O << ".h,"; |
15844 | | printOperand(MI, 2, O); |
15845 | | O << ".h)"; |
15846 | | return; |
15847 | | break; |
15848 | | case 778: |
15849 | | // V6_vmpyiewh_acc, V6_vmpyiewuh_acc |
15850 | | O << ".w += vmpyie("; |
15851 | | printOperand(MI, 2, O); |
15852 | | O << ".w,"; |
15853 | | printOperand(MI, 3, O); |
15854 | | break; |
15855 | | case 779: |
15856 | | // V6_vmpyiewuh |
15857 | | O << ".w = vmpyie("; |
15858 | | printOperand(MI, 1, O); |
15859 | | O << ".w,"; |
15860 | | printOperand(MI, 2, O); |
15861 | | O << ".uh)"; |
15862 | | return; |
15863 | | break; |
15864 | | case 780: |
15865 | | // V6_vmpyih, V6_vmpyihb |
15866 | | O << ".h = vmpyi("; |
15867 | | printOperand(MI, 1, O); |
15868 | | O << ".h,"; |
15869 | | printOperand(MI, 2, O); |
15870 | | break; |
15871 | | case 781: |
15872 | | // V6_vmpyih_acc, V6_vmpyihb_acc |
15873 | | O << ".h += vmpyi("; |
15874 | | printOperand(MI, 2, O); |
15875 | | O << ".h,"; |
15876 | | printOperand(MI, 3, O); |
15877 | | break; |
15878 | | case 782: |
15879 | | // V6_vmpyiowh |
15880 | | O << ".w = vmpyio("; |
15881 | | printOperand(MI, 1, O); |
15882 | | O << ".w,"; |
15883 | | printOperand(MI, 2, O); |
15884 | | O << ".h)"; |
15885 | | return; |
15886 | | break; |
15887 | | case 783: |
15888 | | // V6_vmpyiwb, V6_vmpyiwh, V6_vmpyiwub |
15889 | | O << ".w = vmpyi("; |
15890 | | printOperand(MI, 1, O); |
15891 | | O << ".w,"; |
15892 | | printOperand(MI, 2, O); |
15893 | | break; |
15894 | | case 784: |
15895 | | // V6_vmpyiwb_acc, V6_vmpyiwh_acc, V6_vmpyiwub_acc |
15896 | | O << ".w += vmpyi("; |
15897 | | printOperand(MI, 2, O); |
15898 | | O << ".w,"; |
15899 | | printOperand(MI, 3, O); |
15900 | | break; |
15901 | | case 785: |
15902 | | // V6_vmpyowh, V6_vmpyowh_rnd |
15903 | | O << ".w = vmpyo("; |
15904 | | printOperand(MI, 1, O); |
15905 | | O << ".w,"; |
15906 | | printOperand(MI, 2, O); |
15907 | | break; |
15908 | | case 786: |
15909 | | // V6_vmpyowh_64_acc |
15910 | | O << " += vmpyo("; |
15911 | | printOperand(MI, 2, O); |
15912 | | O << ".w,"; |
15913 | | printOperand(MI, 3, O); |
15914 | | O << ".h)"; |
15915 | | return; |
15916 | | break; |
15917 | | case 787: |
15918 | | // V6_vmpyowh_rnd_sacc, V6_vmpyowh_sacc |
15919 | | O << ".w += vmpyo("; |
15920 | | printOperand(MI, 2, O); |
15921 | | O << ".w,"; |
15922 | | printOperand(MI, 3, O); |
15923 | | break; |
15924 | | case 788: |
15925 | | // V6_vmpyub, V6_vmpyubv, V6_vmpyuhvs |
15926 | | O << ".uh = vmpy("; |
15927 | | printOperand(MI, 1, O); |
15928 | | break; |
15929 | | case 789: |
15930 | | // V6_vmpyub_acc, V6_vmpyubv_acc |
15931 | | O << ".uh += vmpy("; |
15932 | | printOperand(MI, 2, O); |
15933 | | O << ".ub,"; |
15934 | | printOperand(MI, 3, O); |
15935 | | O << ".ub)"; |
15936 | | return; |
15937 | | break; |
15938 | | case 790: |
15939 | | // V6_vmpyuh, V6_vmpyuhv |
15940 | | O << ".uw = vmpy("; |
15941 | | printOperand(MI, 1, O); |
15942 | | O << ".uh,"; |
15943 | | printOperand(MI, 2, O); |
15944 | | O << ".uh)"; |
15945 | | return; |
15946 | | break; |
15947 | | case 791: |
15948 | | // V6_vmpyuh_acc, V6_vmpyuhv_acc |
15949 | | O << ".uw += vmpy("; |
15950 | | printOperand(MI, 2, O); |
15951 | | O << ".uh,"; |
15952 | | printOperand(MI, 3, O); |
15953 | | O << ".uh)"; |
15954 | | return; |
15955 | | break; |
15956 | | case 792: |
15957 | | // V6_vmpyuhe |
15958 | | O << ".uw = vmpye("; |
15959 | | printOperand(MI, 1, O); |
15960 | | O << ".uh,"; |
15961 | | printOperand(MI, 2, O); |
15962 | | O << ".uh)"; |
15963 | | return; |
15964 | | break; |
15965 | | case 793: |
15966 | | // V6_vmpyuhe_acc |
15967 | | O << ".uw += vmpye("; |
15968 | | printOperand(MI, 2, O); |
15969 | | O << ".uh,"; |
15970 | | printOperand(MI, 3, O); |
15971 | | O << ".uh)"; |
15972 | | return; |
15973 | | break; |
15974 | | case 794: |
15975 | | // V6_vnavgb, V6_vnavgub |
15976 | | O << ".b = vnavg("; |
15977 | | printOperand(MI, 1, O); |
15978 | | break; |
15979 | | case 795: |
15980 | | // V6_vnavgh |
15981 | | O << ".h = vnavg("; |
15982 | | printOperand(MI, 1, O); |
15983 | | O << ".h,"; |
15984 | | printOperand(MI, 2, O); |
15985 | | O << ".h)"; |
15986 | | return; |
15987 | | break; |
15988 | | case 796: |
15989 | | // V6_vnavgw |
15990 | | O << ".w = vnavg("; |
15991 | | printOperand(MI, 1, O); |
15992 | | O << ".w,"; |
15993 | | printOperand(MI, 2, O); |
15994 | | O << ".w)"; |
15995 | | return; |
15996 | | break; |
15997 | | case 797: |
15998 | | // V6_vnormamth |
15999 | | O << ".h = vnormamt("; |
16000 | | printOperand(MI, 1, O); |
16001 | | O << ".h)"; |
16002 | | return; |
16003 | | break; |
16004 | | case 798: |
16005 | | // V6_vnormamtw |
16006 | | O << ".w = vnormamt("; |
16007 | | printOperand(MI, 1, O); |
16008 | | O << ".w)"; |
16009 | | return; |
16010 | | break; |
16011 | | case 799: |
16012 | | // V6_vnot |
16013 | | O << " = vnot("; |
16014 | | printOperand(MI, 1, O); |
16015 | | O << ')'; |
16016 | | return; |
16017 | | break; |
16018 | | case 800: |
16019 | | // V6_vor |
16020 | | O << " = vor("; |
16021 | | printOperand(MI, 1, O); |
16022 | | O << ','; |
16023 | | printOperand(MI, 2, O); |
16024 | | O << ')'; |
16025 | | return; |
16026 | | break; |
16027 | | case 801: |
16028 | | // V6_vpackeb |
16029 | | O << ".b = vpacke("; |
16030 | | printOperand(MI, 1, O); |
16031 | | O << ".h,"; |
16032 | | printOperand(MI, 2, O); |
16033 | | O << ".h)"; |
16034 | | return; |
16035 | | break; |
16036 | | case 802: |
16037 | | // V6_vpackeh |
16038 | | O << ".h = vpacke("; |
16039 | | printOperand(MI, 1, O); |
16040 | | O << ".w,"; |
16041 | | printOperand(MI, 2, O); |
16042 | | O << ".w)"; |
16043 | | return; |
16044 | | break; |
16045 | | case 803: |
16046 | | // V6_vpackhb_sat |
16047 | | O << ".b = vpack("; |
16048 | | printOperand(MI, 1, O); |
16049 | | O << ".h,"; |
16050 | | printOperand(MI, 2, O); |
16051 | | O << ".h):sat"; |
16052 | | return; |
16053 | | break; |
16054 | | case 804: |
16055 | | // V6_vpackhub_sat |
16056 | | O << ".ub = vpack("; |
16057 | | printOperand(MI, 1, O); |
16058 | | O << ".h,"; |
16059 | | printOperand(MI, 2, O); |
16060 | | O << ".h):sat"; |
16061 | | return; |
16062 | | break; |
16063 | | case 805: |
16064 | | // V6_vpackob |
16065 | | O << ".b = vpacko("; |
16066 | | printOperand(MI, 1, O); |
16067 | | O << ".h,"; |
16068 | | printOperand(MI, 2, O); |
16069 | | O << ".h)"; |
16070 | | return; |
16071 | | break; |
16072 | | case 806: |
16073 | | // V6_vpackoh |
16074 | | O << ".h = vpacko("; |
16075 | | printOperand(MI, 1, O); |
16076 | | O << ".w,"; |
16077 | | printOperand(MI, 2, O); |
16078 | | O << ".w)"; |
16079 | | return; |
16080 | | break; |
16081 | | case 807: |
16082 | | // V6_vpackwh_sat |
16083 | | O << ".h = vpack("; |
16084 | | printOperand(MI, 1, O); |
16085 | | O << ".w,"; |
16086 | | printOperand(MI, 2, O); |
16087 | | O << ".w):sat"; |
16088 | | return; |
16089 | | break; |
16090 | | case 808: |
16091 | | // V6_vpackwuh_sat |
16092 | | O << ".uh = vpack("; |
16093 | | printOperand(MI, 1, O); |
16094 | | O << ".w,"; |
16095 | | printOperand(MI, 2, O); |
16096 | | O << ".w):sat"; |
16097 | | return; |
16098 | | break; |
16099 | | case 809: |
16100 | | // V6_vpopcounth |
16101 | | O << ".h = vpopcount("; |
16102 | | printOperand(MI, 1, O); |
16103 | | O << ".h)"; |
16104 | | return; |
16105 | | break; |
16106 | | case 810: |
16107 | | // V6_vprefixqb |
16108 | | O << ".b = prefixsum("; |
16109 | | printOperand(MI, 1, O); |
16110 | | O << ')'; |
16111 | | return; |
16112 | | break; |
16113 | | case 811: |
16114 | | // V6_vprefixqh |
16115 | | O << ".h = prefixsum("; |
16116 | | printOperand(MI, 1, O); |
16117 | | O << ')'; |
16118 | | return; |
16119 | | break; |
16120 | | case 812: |
16121 | | // V6_vprefixqw |
16122 | | O << ".w = prefixsum("; |
16123 | | printOperand(MI, 1, O); |
16124 | | O << ')'; |
16125 | | return; |
16126 | | break; |
16127 | | case 813: |
16128 | | // V6_vrdelta |
16129 | | O << " = vrdelta("; |
16130 | | printOperand(MI, 1, O); |
16131 | | O << ','; |
16132 | | printOperand(MI, 2, O); |
16133 | | O << ')'; |
16134 | | return; |
16135 | | break; |
16136 | | case 814: |
16137 | | // V6_vrmpyzbb_rt, V6_vrmpyzbb_rx, V6_vrmpyzbub_rt, V6_vrmpyzbub_rx |
16138 | | O << ".w = vrmpyz("; |
16139 | | break; |
16140 | | case 815: |
16141 | | // V6_vrmpyzbb_rt_acc, V6_vrmpyzbb_rx_acc, V6_vrmpyzbub_rt_acc, V6_vrmpyz... |
16142 | | O << ".w += vrmpyz("; |
16143 | | break; |
16144 | | case 816: |
16145 | | // V6_vrmpyzcb_rt, V6_vrmpyzcb_rx |
16146 | | O << ".w = vr16mpyz("; |
16147 | | break; |
16148 | | case 817: |
16149 | | // V6_vrmpyzcb_rt_acc, V6_vrmpyzcb_rx_acc |
16150 | | O << ".w += vr16mpyz("; |
16151 | | break; |
16152 | | case 818: |
16153 | | // V6_vrmpyzcbs_rt, V6_vrmpyzcbs_rx |
16154 | | O << ".w = vr16mpyzs("; |
16155 | | break; |
16156 | | case 819: |
16157 | | // V6_vrmpyzcbs_rt_acc, V6_vrmpyzcbs_rx_acc |
16158 | | O << ".w += vr16mpyzs("; |
16159 | | break; |
16160 | | case 820: |
16161 | | // V6_vrmpyznb_rt, V6_vrmpyznb_rx |
16162 | | O << ".w = vr8mpyz("; |
16163 | | break; |
16164 | | case 821: |
16165 | | // V6_vrmpyznb_rt_acc, V6_vrmpyznb_rx_acc |
16166 | | O << ".w += vr8mpyz("; |
16167 | | break; |
16168 | | case 822: |
16169 | | // V6_vror |
16170 | | O << " = vror("; |
16171 | | printOperand(MI, 1, O); |
16172 | | O << ','; |
16173 | | printOperand(MI, 2, O); |
16174 | | O << ')'; |
16175 | | return; |
16176 | | break; |
16177 | | case 823: |
16178 | | // V6_vrotr |
16179 | | O << ".uw = vrotr("; |
16180 | | printOperand(MI, 1, O); |
16181 | | O << ".uw,"; |
16182 | | printOperand(MI, 2, O); |
16183 | | O << ".uw)"; |
16184 | | return; |
16185 | | break; |
16186 | | case 824: |
16187 | | // V6_vroundhb |
16188 | | O << ".b = vround("; |
16189 | | printOperand(MI, 1, O); |
16190 | | O << ".h,"; |
16191 | | printOperand(MI, 2, O); |
16192 | | O << ".h):sat"; |
16193 | | return; |
16194 | | break; |
16195 | | case 825: |
16196 | | // V6_vroundhub, V6_vrounduhub |
16197 | | O << ".ub = vround("; |
16198 | | printOperand(MI, 1, O); |
16199 | | break; |
16200 | | case 826: |
16201 | | // V6_vrounduwuh, V6_vroundwuh |
16202 | | O << ".uh = vround("; |
16203 | | printOperand(MI, 1, O); |
16204 | | break; |
16205 | | case 827: |
16206 | | // V6_vroundwh |
16207 | | O << ".h = vround("; |
16208 | | printOperand(MI, 1, O); |
16209 | | O << ".w,"; |
16210 | | printOperand(MI, 2, O); |
16211 | | O << ".w):sat"; |
16212 | | return; |
16213 | | break; |
16214 | | case 828: |
16215 | | // V6_vrsadubi |
16216 | | O << ".uw = vrsad("; |
16217 | | printOperand(MI, 1, O); |
16218 | | O << ".ub,"; |
16219 | | printOperand(MI, 2, O); |
16220 | | O << ".ub,#"; |
16221 | | printOperand(MI, 3, O); |
16222 | | O << ')'; |
16223 | | return; |
16224 | | break; |
16225 | | case 829: |
16226 | | // V6_vrsadubi_acc |
16227 | | O << ".uw += vrsad("; |
16228 | | printOperand(MI, 2, O); |
16229 | | O << ".ub,"; |
16230 | | printOperand(MI, 3, O); |
16231 | | O << ".ub,#"; |
16232 | | printOperand(MI, 4, O); |
16233 | | O << ')'; |
16234 | | return; |
16235 | | break; |
16236 | | case 830: |
16237 | | // V6_vsatdw |
16238 | | O << ".w = vsatdw("; |
16239 | | printOperand(MI, 1, O); |
16240 | | O << ".w,"; |
16241 | | printOperand(MI, 2, O); |
16242 | | O << ".w)"; |
16243 | | return; |
16244 | | break; |
16245 | | case 831: |
16246 | | // V6_vsathub |
16247 | | O << ".ub = vsat("; |
16248 | | printOperand(MI, 1, O); |
16249 | | O << ".h,"; |
16250 | | printOperand(MI, 2, O); |
16251 | | O << ".h)"; |
16252 | | return; |
16253 | | break; |
16254 | | case 832: |
16255 | | // V6_vsatuwuh |
16256 | | O << ".uh = vsat("; |
16257 | | printOperand(MI, 1, O); |
16258 | | O << ".uw,"; |
16259 | | printOperand(MI, 2, O); |
16260 | | O << ".uw)"; |
16261 | | return; |
16262 | | break; |
16263 | | case 833: |
16264 | | // V6_vsatwh |
16265 | | O << ".h = vsat("; |
16266 | | printOperand(MI, 1, O); |
16267 | | O << ".w,"; |
16268 | | printOperand(MI, 2, O); |
16269 | | O << ".w)"; |
16270 | | return; |
16271 | | break; |
16272 | | case 834: |
16273 | | // V6_vsb |
16274 | | O << ".h = vsxt("; |
16275 | | printOperand(MI, 1, O); |
16276 | | O << ".b)"; |
16277 | | return; |
16278 | | break; |
16279 | | case 835: |
16280 | | // V6_vsh |
16281 | | O << ".w = vsxt("; |
16282 | | printOperand(MI, 1, O); |
16283 | | O << ".h)"; |
16284 | | return; |
16285 | | break; |
16286 | | case 836: |
16287 | | // V6_vshuffb |
16288 | | O << ".b = vshuff("; |
16289 | | printOperand(MI, 1, O); |
16290 | | O << ".b)"; |
16291 | | return; |
16292 | | break; |
16293 | | case 837: |
16294 | | // V6_vshuffh |
16295 | | O << ".h = vshuff("; |
16296 | | printOperand(MI, 1, O); |
16297 | | O << ".h)"; |
16298 | | return; |
16299 | | break; |
16300 | | case 838: |
16301 | | // V6_vshuffob |
16302 | | O << ".b = vshuffo("; |
16303 | | printOperand(MI, 1, O); |
16304 | | O << ".b,"; |
16305 | | printOperand(MI, 2, O); |
16306 | | O << ".b)"; |
16307 | | return; |
16308 | | break; |
16309 | | case 839: |
16310 | | // V6_vshuffvdd |
16311 | | O << " = vshuff("; |
16312 | | printOperand(MI, 1, O); |
16313 | | O << ','; |
16314 | | printOperand(MI, 2, O); |
16315 | | O << ','; |
16316 | | printOperand(MI, 3, O); |
16317 | | O << ')'; |
16318 | | return; |
16319 | | break; |
16320 | | case 840: |
16321 | | // V6_vshufoeb |
16322 | | O << ".b = vshuffoe("; |
16323 | | printOperand(MI, 1, O); |
16324 | | O << ".b,"; |
16325 | | printOperand(MI, 2, O); |
16326 | | O << ".b)"; |
16327 | | return; |
16328 | | break; |
16329 | | case 841: |
16330 | | // V6_vshufoeh |
16331 | | O << ".h = vshuffoe("; |
16332 | | printOperand(MI, 1, O); |
16333 | | O << ".h,"; |
16334 | | printOperand(MI, 2, O); |
16335 | | O << ".h)"; |
16336 | | return; |
16337 | | break; |
16338 | | case 842: |
16339 | | // V6_vshufoh |
16340 | | O << ".h = vshuffo("; |
16341 | | printOperand(MI, 1, O); |
16342 | | O << ".h,"; |
16343 | | printOperand(MI, 2, O); |
16344 | | O << ".h)"; |
16345 | | return; |
16346 | | break; |
16347 | | case 843: |
16348 | | // V6_vsub_hf, V6_vsub_qf16, V6_vsub_qf16_mix |
16349 | | O << ".qf16 = vsub("; |
16350 | | printOperand(MI, 1, O); |
16351 | | break; |
16352 | | case 844: |
16353 | | // V6_vsub_hf_hf |
16354 | | O << ".hf = vsub("; |
16355 | | printOperand(MI, 1, O); |
16356 | | O << ".hf,"; |
16357 | | printOperand(MI, 2, O); |
16358 | | O << ".hf)"; |
16359 | | return; |
16360 | | break; |
16361 | | case 845: |
16362 | | // V6_vsub_qf32, V6_vsub_qf32_mix, V6_vsub_sf |
16363 | | O << ".qf32 = vsub("; |
16364 | | printOperand(MI, 1, O); |
16365 | | break; |
16366 | | case 846: |
16367 | | // V6_vsub_sf_bf, V6_vsub_sf_hf, V6_vsub_sf_sf |
16368 | | O << ".sf = vsub("; |
16369 | | printOperand(MI, 1, O); |
16370 | | break; |
16371 | | case 847: |
16372 | | // V6_vsubb, V6_vsubb_dv, V6_vsubbsat, V6_vsubbsat_dv |
16373 | | O << ".b = vsub("; |
16374 | | printOperand(MI, 1, O); |
16375 | | O << ".b,"; |
16376 | | printOperand(MI, 2, O); |
16377 | | break; |
16378 | | case 848: |
16379 | | // V6_vsubcarry, V6_vsubhw, V6_vsubuhw, V6_vsubw, V6_vsubw_dv, V6_vsubwsa... |
16380 | | O << ".w = vsub("; |
16381 | | break; |
16382 | | case 849: |
16383 | | // V6_vsubh, V6_vsubh_dv, V6_vsubhsat, V6_vsubhsat_dv, V6_vsububh |
16384 | | O << ".h = vsub("; |
16385 | | printOperand(MI, 1, O); |
16386 | | break; |
16387 | | case 850: |
16388 | | // V6_vsububsat, V6_vsububsat_dv, V6_vsubububb_sat |
16389 | | O << ".ub = vsub("; |
16390 | | printOperand(MI, 1, O); |
16391 | | O << ".ub,"; |
16392 | | printOperand(MI, 2, O); |
16393 | | break; |
16394 | | case 851: |
16395 | | // V6_vsubuhsat, V6_vsubuhsat_dv |
16396 | | O << ".uh = vsub("; |
16397 | | printOperand(MI, 1, O); |
16398 | | O << ".uh,"; |
16399 | | printOperand(MI, 2, O); |
16400 | | O << ".uh):sat"; |
16401 | | return; |
16402 | | break; |
16403 | | case 852: |
16404 | | // V6_vsubuwsat, V6_vsubuwsat_dv |
16405 | | O << ".uw = vsub("; |
16406 | | printOperand(MI, 1, O); |
16407 | | O << ".uw,"; |
16408 | | printOperand(MI, 2, O); |
16409 | | O << ".uw):sat"; |
16410 | | return; |
16411 | | break; |
16412 | | case 853: |
16413 | | // V6_vswap |
16414 | | O << " = vswap("; |
16415 | | printOperand(MI, 1, O); |
16416 | | O << ','; |
16417 | | printOperand(MI, 2, O); |
16418 | | O << ','; |
16419 | | printOperand(MI, 3, O); |
16420 | | O << ')'; |
16421 | | return; |
16422 | | break; |
16423 | | case 854: |
16424 | | // V6_vtmpyb, V6_vtmpybus |
16425 | | O << ".h = vtmpy("; |
16426 | | printOperand(MI, 1, O); |
16427 | | break; |
16428 | | case 855: |
16429 | | // V6_vtmpyb_acc, V6_vtmpybus_acc |
16430 | | O << ".h += vtmpy("; |
16431 | | printOperand(MI, 2, O); |
16432 | | break; |
16433 | | case 856: |
16434 | | // V6_vtmpyhb |
16435 | | O << ".w = vtmpy("; |
16436 | | printOperand(MI, 1, O); |
16437 | | O << ".h,"; |
16438 | | printOperand(MI, 2, O); |
16439 | | O << ".b)"; |
16440 | | return; |
16441 | | break; |
16442 | | case 857: |
16443 | | // V6_vtmpyhb_acc |
16444 | | O << ".w += vtmpy("; |
16445 | | printOperand(MI, 2, O); |
16446 | | O << ".h,"; |
16447 | | printOperand(MI, 3, O); |
16448 | | O << ".b)"; |
16449 | | return; |
16450 | | break; |
16451 | | case 858: |
16452 | | // V6_vunpackb |
16453 | | O << ".h = vunpack("; |
16454 | | printOperand(MI, 1, O); |
16455 | | O << ".b)"; |
16456 | | return; |
16457 | | break; |
16458 | | case 859: |
16459 | | // V6_vunpackh |
16460 | | O << ".w = vunpack("; |
16461 | | printOperand(MI, 1, O); |
16462 | | O << ".h)"; |
16463 | | return; |
16464 | | break; |
16465 | | case 860: |
16466 | | // V6_vunpackob |
16467 | | O << ".h |= vunpacko("; |
16468 | | printOperand(MI, 2, O); |
16469 | | O << ".b)"; |
16470 | | return; |
16471 | | break; |
16472 | | case 861: |
16473 | | // V6_vunpackoh |
16474 | | O << ".w |= vunpacko("; |
16475 | | printOperand(MI, 2, O); |
16476 | | O << ".h)"; |
16477 | | return; |
16478 | | break; |
16479 | | case 862: |
16480 | | // V6_vunpackub |
16481 | | O << ".uh = vunpack("; |
16482 | | printOperand(MI, 1, O); |
16483 | | O << ".ub)"; |
16484 | | return; |
16485 | | break; |
16486 | | case 863: |
16487 | | // V6_vunpackuh |
16488 | | O << ".uw = vunpack("; |
16489 | | printOperand(MI, 1, O); |
16490 | | O << ".uh)"; |
16491 | | return; |
16492 | | break; |
16493 | | case 864: |
16494 | | // V6_vwhist256q_sat |
16495 | | O << "):sat"; |
16496 | | return; |
16497 | | break; |
16498 | | case 865: |
16499 | | // V6_vxor |
16500 | | O << " = vxor("; |
16501 | | printOperand(MI, 1, O); |
16502 | | O << ','; |
16503 | | printOperand(MI, 2, O); |
16504 | | O << ')'; |
16505 | | return; |
16506 | | break; |
16507 | | case 866: |
16508 | | // V6_vzb |
16509 | | O << ".uh = vzxt("; |
16510 | | printOperand(MI, 1, O); |
16511 | | O << ".ub)"; |
16512 | | return; |
16513 | | break; |
16514 | | case 867: |
16515 | | // V6_vzh |
16516 | | O << ".uw = vzxt("; |
16517 | | printOperand(MI, 1, O); |
16518 | | O << ".uh)"; |
16519 | | return; |
16520 | | break; |
16521 | | case 868: |
16522 | | // V6_zextract |
16523 | | O << " = zextract("; |
16524 | | printOperand(MI, 1, O); |
16525 | | O << ')'; |
16526 | | return; |
16527 | | break; |
16528 | | case 869: |
16529 | | // Y2_crswap0 |
16530 | | O << ",sgp0)"; |
16531 | | return; |
16532 | | break; |
16533 | | case 870: |
16534 | | // Y2_dctagr |
16535 | | O << " = dctagr("; |
16536 | | printOperand(MI, 1, O); |
16537 | | O << ')'; |
16538 | | return; |
16539 | | break; |
16540 | | case 871: |
16541 | | // Y2_getimask |
16542 | | O << " = getimask("; |
16543 | | printOperand(MI, 1, O); |
16544 | | O << ')'; |
16545 | | return; |
16546 | | break; |
16547 | | case 872: |
16548 | | // Y2_iassignr |
16549 | | O << " = iassignr("; |
16550 | | printOperand(MI, 1, O); |
16551 | | O << ')'; |
16552 | | return; |
16553 | | break; |
16554 | | case 873: |
16555 | | // Y2_icdatar |
16556 | | O << " = icdatar("; |
16557 | | printOperand(MI, 1, O); |
16558 | | O << ')'; |
16559 | | return; |
16560 | | break; |
16561 | | case 874: |
16562 | | // Y2_ictagr |
16563 | | O << " = ictagr("; |
16564 | | printOperand(MI, 1, O); |
16565 | | O << ')'; |
16566 | | return; |
16567 | | break; |
16568 | | case 875: |
16569 | | // Y2_tlbp |
16570 | | O << " = tlbp("; |
16571 | | printOperand(MI, 1, O); |
16572 | | O << ')'; |
16573 | | return; |
16574 | | break; |
16575 | | case 876: |
16576 | | // Y2_tlbr |
16577 | | O << " = tlbr("; |
16578 | | printOperand(MI, 1, O); |
16579 | | O << ')'; |
16580 | | return; |
16581 | | break; |
16582 | | case 877: |
16583 | | // Y4_crswap1 |
16584 | | O << ",sgp1)"; |
16585 | | return; |
16586 | | break; |
16587 | | case 878: |
16588 | | // Y4_l2tagr |
16589 | | O << " = l2tagr("; |
16590 | | printOperand(MI, 1, O); |
16591 | | O << ')'; |
16592 | | return; |
16593 | | break; |
16594 | | case 879: |
16595 | | // Y5_ctlbw |
16596 | | O << " = ctlbw("; |
16597 | | printOperand(MI, 1, O); |
16598 | | O << ','; |
16599 | | printOperand(MI, 2, O); |
16600 | | O << ')'; |
16601 | | return; |
16602 | | break; |
16603 | | case 880: |
16604 | | // Y5_l2locka |
16605 | | O << " = l2locka("; |
16606 | | printOperand(MI, 1, O); |
16607 | | O << ')'; |
16608 | | return; |
16609 | | break; |
16610 | | case 881: |
16611 | | // Y5_tlboc |
16612 | | O << " = tlboc("; |
16613 | | printOperand(MI, 1, O); |
16614 | | O << ')'; |
16615 | | return; |
16616 | | break; |
16617 | | case 882: |
16618 | | // Y6_dmpause |
16619 | | O << " = dmpause"; |
16620 | | return; |
16621 | | break; |
16622 | | case 883: |
16623 | | // Y6_dmpoll |
16624 | | O << " = dmpoll"; |
16625 | | return; |
16626 | | break; |
16627 | | case 884: |
16628 | | // Y6_dmwait |
16629 | | O << " = dmwait"; |
16630 | | return; |
16631 | | break; |
16632 | | } |
16633 | | |
16634 | | |
16635 | | // Fragment 2 encoded into 8 bits for 165 unique commands. |
16636 | | switch ((Bits >> 24) & 255) { |
16637 | | default: llvm_unreachable("Invalid command number."); |
16638 | | case 0: |
16639 | | // A2_addsp, S2_pstorerbf_zomap, S2_pstorerbnewf_zomap, S2_pstorerbnewt_z... |
16640 | | printOperand(MI, 1, O); |
16641 | | break; |
16642 | | case 1: |
16643 | | // A2_neg, A2_vaddb_map, A2_vsubb_map, A4_boundscheck, L2_loadbsw2_zomap,... |
16644 | | O << ')'; |
16645 | | return; |
16646 | | break; |
16647 | | case 2: |
16648 | | // A2_tfrf, A2_tfrfnew, A2_tfrpf, A2_tfrpfnew, A2_tfrpt, A2_tfrptnew, A2_... |
16649 | | O << " = "; |
16650 | | printOperand(MI, 2, O); |
16651 | | return; |
16652 | | break; |
16653 | | case 3: |
16654 | | // A2_tfrp, A2_tfrpi, C2_pxfer_map, S2_storerb_zomap, S2_storerd_zomap, S... |
16655 | | return; |
16656 | | break; |
16657 | | case 4: |
16658 | | // L2_loadalignb_zomap, L2_loadalignh_zomap, dup_S2_allocframe, A2_tfrih,... |
16659 | | printOperand(MI, 2, O); |
16660 | | break; |
16661 | | case 5: |
16662 | | // L2_ploadrbf_zomap, L2_ploadrbfnew_zomap, L2_ploadrbt_zomap, L2_ploadrb... |
16663 | | O << " = memb("; |
16664 | | break; |
16665 | | case 6: |
16666 | | // L2_ploadrdf_zomap, L2_ploadrdfnew_zomap, L2_ploadrdt_zomap, L2_ploadrd... |
16667 | | O << " = memd("; |
16668 | | break; |
16669 | | case 7: |
16670 | | // L2_ploadrhf_zomap, L2_ploadrhfnew_zomap, L2_ploadrht_zomap, L2_ploadrh... |
16671 | | O << " = memh("; |
16672 | | break; |
16673 | | case 8: |
16674 | | // L2_ploadrif_zomap, L2_ploadrifnew_zomap, L2_ploadrit_zomap, L2_ploadri... |
16675 | | O << " = memw("; |
16676 | | break; |
16677 | | case 9: |
16678 | | // L2_ploadrubf_zomap, L2_ploadrubfnew_zomap, L2_ploadrubt_zomap, L2_ploa... |
16679 | | O << " = memub("; |
16680 | | break; |
16681 | | case 10: |
16682 | | // L2_ploadruhf_zomap, L2_ploadruhfnew_zomap, L2_ploadruht_zomap, L2_ploa... |
16683 | | O << " = memuh("; |
16684 | | break; |
16685 | | case 11: |
16686 | | // M2_mpysmi, S5_vasrhrnd_goodsyntax, V6_vrmpybusi_acc_alt, V6_vrmpybusi_... |
16687 | | O << ",#"; |
16688 | | break; |
16689 | | case 12: |
16690 | | // M2_vrcmpys_acc_s1, M2_vrcmpys_s1, V6_vmpyhss_alt, V6_vmpyowh_alt, M2_c... |
16691 | | O << "):<<1:sat"; |
16692 | | return; |
16693 | | break; |
16694 | | case 13: |
16695 | | // M2_vrcmpys_s1rp, V6_vmpyhsrs_alt, V6_vmpyhvsrs_alt, V6_vmpyowh_rnd_alt... |
16696 | | O << "):<<1:rnd:sat"; |
16697 | | return; |
16698 | | break; |
16699 | | case 14: |
16700 | | // S2_storerbnew_zomap, S2_storerhnew_zomap, S2_storerinew_zomap, V6_stn0... |
16701 | | O << ".new"; |
16702 | | return; |
16703 | | break; |
16704 | | case 15: |
16705 | | // S2_storerf_zomap, PS_storerfabs, S2_storerf_pcr, S2_storerfgp, S4_psto... |
16706 | | O << ".h"; |
16707 | | return; |
16708 | | break; |
16709 | | case 16: |
16710 | | // S5_asrhub_rnd_sat_goodsyntax, A2_vnavghr, A2_vnavgwr, M2_cmpyrs_s0, M2... |
16711 | | O << "):rnd:sat"; |
16712 | | return; |
16713 | | break; |
16714 | | case 17: |
16715 | | // V6_MAP_equb, V6_MAP_equb_and, V6_MAP_equb_ior, V6_MAP_equb_xor, V6_vad... |
16716 | | O << ".ub,"; |
16717 | | break; |
16718 | | case 18: |
16719 | | // V6_MAP_equh, V6_MAP_equh_and, V6_MAP_equh_ior, V6_MAP_equh_xor, V6_vab... |
16720 | | O << ".uh,"; |
16721 | | break; |
16722 | | case 19: |
16723 | | // V6_MAP_equw, V6_MAP_equw_and, V6_MAP_equw_ior, V6_MAP_equw_xor, V6_vas... |
16724 | | O << ".uw,"; |
16725 | | break; |
16726 | | case 20: |
16727 | | // V6_ldcnp0, V6_ldcnpnt0, V6_ldcp0, V6_ldcpnt0, V6_vL32b_cur_npred_ai, V... |
16728 | | O << ".cur = vmem("; |
16729 | | break; |
16730 | | case 21: |
16731 | | // V6_ldnp0, V6_ldnpnt0, V6_ldp0, V6_ldpnt0, V6_vL32b_npred_ai, V6_vL32b_... |
16732 | | O << " = vmem("; |
16733 | | break; |
16734 | | case 22: |
16735 | | // V6_ldnt0 |
16736 | | O << "):nt"; |
16737 | | return; |
16738 | | break; |
16739 | | case 23: |
16740 | | // V6_ldtnp0, V6_ldtnpnt0, V6_ldtp0, V6_ldtpnt0, V6_vL32b_nt_tmp_npred_ai... |
16741 | | O << ".tmp = vmem("; |
16742 | | break; |
16743 | | case 24: |
16744 | | // V6_v6mpyhubs10_alt, V6_v6mpyvubs10_alt |
16745 | | O << ".b10,#"; |
16746 | | printOperand(MI, 3, O); |
16747 | | break; |
16748 | | case 25: |
16749 | | // V6_vabsb_sat_alt, V6_vabsh_sat_alt, V6_vabsw_sat_alt, V6_vaddbsat_alt,... |
16750 | | O << "):sat"; |
16751 | | return; |
16752 | | break; |
16753 | | case 26: |
16754 | | // V6_vaddbnq_alt, V6_vaddbq_alt, V6_vaddbnq, V6_vaddbq |
16755 | | O << ".b += "; |
16756 | | printOperand(MI, 3, O); |
16757 | | O << ".b"; |
16758 | | return; |
16759 | | break; |
16760 | | case 27: |
16761 | | // V6_vaddhnq_alt, V6_vaddhq_alt, V6_vaddhnq, V6_vaddhq |
16762 | | O << ".h += "; |
16763 | | printOperand(MI, 3, O); |
16764 | | O << ".h"; |
16765 | | return; |
16766 | | break; |
16767 | | case 28: |
16768 | | // V6_vaddwnq_alt, V6_vaddwq_alt, V6_vaddwnq, V6_vaddwq |
16769 | | O << ".w += "; |
16770 | | printOperand(MI, 3, O); |
16771 | | O << ".w"; |
16772 | | return; |
16773 | | break; |
16774 | | case 29: |
16775 | | // V6_vaslh_alt, V6_vaslhv_alt, V6_vaslw_alt, V6_vaslwv_alt, V6_vasrh_alt... |
16776 | | O << ','; |
16777 | | break; |
16778 | | case 30: |
16779 | | // V6_vavgbrnd_alt, V6_vavghrnd_alt, V6_vavgubrnd_alt, V6_vavguhrnd_alt, ... |
16780 | | O << "):rnd"; |
16781 | | return; |
16782 | | break; |
16783 | | case 31: |
16784 | | // V6_vdmpyhsuisat_acc_alt, V6_vdmpyhsuisat_alt |
16785 | | O << ",#1):sat"; |
16786 | | return; |
16787 | | break; |
16788 | | case 32: |
16789 | | // V6_vmpyowh_rnd_sacc_alt |
16790 | | O << "):<<1:rnd:sat:shift"; |
16791 | | return; |
16792 | | break; |
16793 | | case 33: |
16794 | | // V6_vmpyowh_sacc_alt |
16795 | | O << "):<<1:sat:shift"; |
16796 | | return; |
16797 | | break; |
16798 | | case 34: |
16799 | | // V6_vrmpybub_rtt_acc_alt, V6_vrmpybub_rtt_alt, V6_veqb, V6_veqb_and, V6... |
16800 | | O << ".b,"; |
16801 | | break; |
16802 | | case 35: |
16803 | | // V6_vrmpyub_rtt_acc_alt, V6_vrmpyub_rtt_alt, V6_vavgub, V6_vcvt_hf_ub, ... |
16804 | | O << ".ub)"; |
16805 | | return; |
16806 | | break; |
16807 | | case 36: |
16808 | | // V6_vscattermhq_alt |
16809 | | O << ".h) = "; |
16810 | | printOperand(MI, 4, O); |
16811 | | O << ".h"; |
16812 | | return; |
16813 | | break; |
16814 | | case 37: |
16815 | | // V6_vscattermwhq_alt, V6_vscattermwq_alt |
16816 | | O << ".w) = "; |
16817 | | printOperand(MI, 4, O); |
16818 | | break; |
16819 | | case 38: |
16820 | | // V6_vsubbnq_alt, V6_vsubbq_alt, V6_vsubbnq, V6_vsubbq |
16821 | | O << ".b -= "; |
16822 | | printOperand(MI, 3, O); |
16823 | | O << ".b"; |
16824 | | return; |
16825 | | break; |
16826 | | case 39: |
16827 | | // V6_vsubhnq_alt, V6_vsubhq_alt, V6_vsubhnq, V6_vsubhq |
16828 | | O << ".h -= "; |
16829 | | printOperand(MI, 3, O); |
16830 | | O << ".h"; |
16831 | | return; |
16832 | | break; |
16833 | | case 40: |
16834 | | // V6_vsubwnq_alt, V6_vsubwq_alt, V6_vsubwnq, V6_vsubwq |
16835 | | O << ".w -= "; |
16836 | | printOperand(MI, 3, O); |
16837 | | O << ".w"; |
16838 | | return; |
16839 | | break; |
16840 | | case 41: |
16841 | | // dup_C2_cmoveif, dup_C2_cmoveit, dup_C2_cmovenewif, dup_C2_cmovenewit, ... |
16842 | | O << " = #"; |
16843 | | printOperand(MI, 2, O); |
16844 | | return; |
16845 | | break; |
16846 | | case 42: |
16847 | | // dup_L2_loadrb_io, dup_L2_loadrd_io, dup_L2_loadrh_io, dup_L2_loadri_io... |
16848 | | O << "+#"; |
16849 | | printOperand(MI, 2, O); |
16850 | | break; |
16851 | | case 43: |
16852 | | // dup_S2_storerb_io, dup_S2_storerd_io, dup_S2_storerh_io, dup_S2_storer... |
16853 | | O << ") = "; |
16854 | | break; |
16855 | | case 44: |
16856 | | // dup_S4_storeirb_io, dup_S4_storeiri_io, S4_storeirb_io, S4_storeirh_io... |
16857 | | O << ") = #"; |
16858 | | printOperand(MI, 2, O); |
16859 | | return; |
16860 | | break; |
16861 | | case 45: |
16862 | | // A2_combine_hh, A2_combine_hl, M2_mpy_acc_hh_s0, M2_mpy_acc_hh_s1, M2_m... |
16863 | | O << ".h,"; |
16864 | | break; |
16865 | | case 46: |
16866 | | // A2_combine_lh, A2_combine_ll, M2_mpy_acc_lh_s0, M2_mpy_acc_lh_s1, M2_m... |
16867 | | O << ".l,"; |
16868 | | break; |
16869 | | case 47: |
16870 | | // A2_paddf, A2_paddfnew, A2_paddif, A2_paddifnew, A2_paddit, A2_padditne... |
16871 | | O << " = add("; |
16872 | | printOperand(MI, 2, O); |
16873 | | break; |
16874 | | case 48: |
16875 | | // A2_pandf, A2_pandfnew, A2_pandt, A2_pandtnew |
16876 | | O << " = and("; |
16877 | | printOperand(MI, 2, O); |
16878 | | O << ','; |
16879 | | printOperand(MI, 3, O); |
16880 | | O << ')'; |
16881 | | return; |
16882 | | break; |
16883 | | case 49: |
16884 | | // A2_porf, A2_porfnew, A2_port, A2_portnew |
16885 | | O << " = or("; |
16886 | | printOperand(MI, 2, O); |
16887 | | O << ','; |
16888 | | printOperand(MI, 3, O); |
16889 | | O << ')'; |
16890 | | return; |
16891 | | break; |
16892 | | case 50: |
16893 | | // A2_psubf, A2_psubfnew, A2_psubt, A2_psubtnew |
16894 | | O << " = sub("; |
16895 | | printOperand(MI, 2, O); |
16896 | | O << ','; |
16897 | | printOperand(MI, 3, O); |
16898 | | O << ')'; |
16899 | | return; |
16900 | | break; |
16901 | | case 51: |
16902 | | // A2_pxorf, A2_pxorfnew, A2_pxort, A2_pxortnew |
16903 | | O << " = xor("; |
16904 | | printOperand(MI, 2, O); |
16905 | | O << ','; |
16906 | | printOperand(MI, 3, O); |
16907 | | O << ')'; |
16908 | | return; |
16909 | | break; |
16910 | | case 52: |
16911 | | // A2_vavghcr, A2_vavgwcr |
16912 | | O << "):crnd"; |
16913 | | return; |
16914 | | break; |
16915 | | case 53: |
16916 | | // A2_vnavghcr, A2_vnavgwcr |
16917 | | O << "):crnd:sat"; |
16918 | | return; |
16919 | | break; |
16920 | | case 54: |
16921 | | // A4_andn, A4_andnp, A4_orn, A4_ornp, M4_and_andn, M4_or_andn, M4_xor_an... |
16922 | | O << ",~"; |
16923 | | break; |
16924 | | case 55: |
16925 | | // A4_boundscheck_hi |
16926 | | O << "):raw:hi"; |
16927 | | return; |
16928 | | break; |
16929 | | case 56: |
16930 | | // A4_boundscheck_lo |
16931 | | O << "):raw:lo"; |
16932 | | return; |
16933 | | break; |
16934 | | case 57: |
16935 | | // A4_paslhf, A4_paslhfnew, A4_paslht, A4_paslhtnew |
16936 | | O << " = aslh("; |
16937 | | printOperand(MI, 2, O); |
16938 | | O << ')'; |
16939 | | return; |
16940 | | break; |
16941 | | case 58: |
16942 | | // A4_pasrhf, A4_pasrhfnew, A4_pasrht, A4_pasrhtnew |
16943 | | O << " = asrh("; |
16944 | | printOperand(MI, 2, O); |
16945 | | O << ')'; |
16946 | | return; |
16947 | | break; |
16948 | | case 59: |
16949 | | // A4_psxtbf, A4_psxtbfnew, A4_psxtbt, A4_psxtbtnew |
16950 | | O << " = sxtb("; |
16951 | | printOperand(MI, 2, O); |
16952 | | O << ')'; |
16953 | | return; |
16954 | | break; |
16955 | | case 60: |
16956 | | // A4_psxthf, A4_psxthfnew, A4_psxtht, A4_psxthtnew |
16957 | | O << " = sxth("; |
16958 | | printOperand(MI, 2, O); |
16959 | | O << ')'; |
16960 | | return; |
16961 | | break; |
16962 | | case 61: |
16963 | | // A4_pzxtbf, A4_pzxtbfnew, A4_pzxtbt, A4_pzxtbtnew |
16964 | | O << " = zxtb("; |
16965 | | printOperand(MI, 2, O); |
16966 | | O << ')'; |
16967 | | return; |
16968 | | break; |
16969 | | case 62: |
16970 | | // A4_pzxthf, A4_pzxthfnew, A4_pzxtht, A4_pzxthtnew |
16971 | | O << " = zxth("; |
16972 | | printOperand(MI, 2, O); |
16973 | | O << ')'; |
16974 | | return; |
16975 | | break; |
16976 | | case 63: |
16977 | | // C2_andn, C2_orn, V6_pred_and_n, V6_pred_or_n |
16978 | | O << ",!"; |
16979 | | printOperand(MI, 2, O); |
16980 | | O << ')'; |
16981 | | return; |
16982 | | break; |
16983 | | case 64: |
16984 | | // C2_ccombinewf, C2_ccombinewnewf, C2_ccombinewnewt, C2_ccombinewt |
16985 | | O << " = combine("; |
16986 | | printOperand(MI, 2, O); |
16987 | | O << ','; |
16988 | | printOperand(MI, 3, O); |
16989 | | O << ')'; |
16990 | | return; |
16991 | | break; |
16992 | | case 65: |
16993 | | // C4_and_and, C4_and_andn, C4_or_and, C4_or_andn, S4_or_andix |
16994 | | O << ",and("; |
16995 | | printOperand(MI, 2, O); |
16996 | | break; |
16997 | | case 66: |
16998 | | // C4_and_or, C4_and_orn, C4_or_or, C4_or_orn |
16999 | | O << ",or("; |
17000 | | printOperand(MI, 2, O); |
17001 | | break; |
17002 | | case 67: |
17003 | | // F2_conv_df2d_chop, F2_conv_df2ud_chop, F2_conv_df2uw_chop, F2_conv_df2... |
17004 | | O << "):chop"; |
17005 | | return; |
17006 | | break; |
17007 | | case 68: |
17008 | | // F2_dfimm_n, F2_sfimm_n |
17009 | | O << "):neg"; |
17010 | | return; |
17011 | | break; |
17012 | | case 69: |
17013 | | // F2_dfimm_p, F2_sfimm_p |
17014 | | O << "):pos"; |
17015 | | return; |
17016 | | break; |
17017 | | case 70: |
17018 | | // F2_sffma_lib, F2_sffms_lib |
17019 | | O << "):lib"; |
17020 | | return; |
17021 | | break; |
17022 | | case 71: |
17023 | | // J4_cmpeq_f_jumpnv_nt, J4_cmpeq_t_jumpnv_nt, J4_cmpeqi_f_jumpnv_nt, J4_... |
17024 | | O << ")) jump:nt "; |
17025 | | printBrtarget(MI, 2, O); |
17026 | | return; |
17027 | | break; |
17028 | | case 72: |
17029 | | // J4_cmpeq_f_jumpnv_t, J4_cmpeq_t_jumpnv_t, J4_cmpeqi_f_jumpnv_t, J4_cmp... |
17030 | | O << ")) jump:t "; |
17031 | | printBrtarget(MI, 2, O); |
17032 | | return; |
17033 | | break; |
17034 | | case 73: |
17035 | | // J4_jumpseti, J4_jumpsetr |
17036 | | O << " ; jump "; |
17037 | | printBrtarget(MI, 2, O); |
17038 | | return; |
17039 | | break; |
17040 | | case 74: |
17041 | | // L2_loadbsw2_pbr, L2_loadbsw2_pr, L2_loadbsw4_pbr, L2_loadbsw4_pr, L2_l... |
17042 | | O << "++"; |
17043 | | printOperand(MI, 3, O); |
17044 | | break; |
17045 | | case 75: |
17046 | | // L2_loadbsw2_pci, L2_loadbsw2_pi, L2_loadbsw4_pci, L2_loadbsw4_pi, L2_l... |
17047 | | O << "++#"; |
17048 | | printOperand(MI, 3, O); |
17049 | | break; |
17050 | | case 76: |
17051 | | // L2_loadbsw2_pcr, L2_loadbsw4_pcr, L2_loadbzw2_pcr, L2_loadbzw4_pcr, L2... |
17052 | | O << "++I:circ("; |
17053 | | printOperand(MI, 3, O); |
17054 | | O << "))"; |
17055 | | return; |
17056 | | break; |
17057 | | case 77: |
17058 | | // L4_add_memopb_io, L4_add_memoph_io, L4_add_memopw_io |
17059 | | O << ") += "; |
17060 | | printOperand(MI, 2, O); |
17061 | | return; |
17062 | | break; |
17063 | | case 78: |
17064 | | // L4_and_memopb_io, L4_and_memoph_io, L4_and_memopw_io |
17065 | | O << ") &= "; |
17066 | | printOperand(MI, 2, O); |
17067 | | return; |
17068 | | break; |
17069 | | case 79: |
17070 | | // L4_iadd_memopb_io, L4_iadd_memoph_io, L4_iadd_memopw_io |
17071 | | O << ") += #"; |
17072 | | printOperand(MI, 2, O); |
17073 | | return; |
17074 | | break; |
17075 | | case 80: |
17076 | | // L4_iand_memopb_io, L4_iand_memoph_io, L4_iand_memopw_io |
17077 | | O << ") = clrbit(#"; |
17078 | | printOperand(MI, 2, O); |
17079 | | O << ')'; |
17080 | | return; |
17081 | | break; |
17082 | | case 81: |
17083 | | // L4_ior_memopb_io, L4_ior_memoph_io, L4_ior_memopw_io |
17084 | | O << ") = setbit(#"; |
17085 | | printOperand(MI, 2, O); |
17086 | | O << ')'; |
17087 | | return; |
17088 | | break; |
17089 | | case 82: |
17090 | | // L4_isub_memopb_io, L4_isub_memoph_io, L4_isub_memopw_io |
17091 | | O << ") -= #"; |
17092 | | printOperand(MI, 2, O); |
17093 | | return; |
17094 | | break; |
17095 | | case 83: |
17096 | | // L4_loadbsw2_ap, L4_loadbsw4_ap, L4_loadbzw2_ap, L4_loadbzw4_ap, L4_loa... |
17097 | | O << "=#"; |
17098 | | printOperand(MI, 2, O); |
17099 | | O << ')'; |
17100 | | return; |
17101 | | break; |
17102 | | case 84: |
17103 | | // L4_loadbsw2_ur, L4_loadbsw4_ur, L4_loadbzw2_ur, L4_loadbzw4_ur, L4_loa... |
17104 | | O << "<<#"; |
17105 | | printOperand(MI, 2, O); |
17106 | | O << "+#"; |
17107 | | printOperand(MI, 3, O); |
17108 | | O << ')'; |
17109 | | return; |
17110 | | break; |
17111 | | case 85: |
17112 | | // L4_loadrb_rr, L4_loadrd_rr, L4_loadrh_rr, L4_loadri_rr, L4_loadrub_rr,... |
17113 | | O << '+'; |
17114 | | printOperand(MI, 2, O); |
17115 | | O << "<<#"; |
17116 | | printOperand(MI, 3, O); |
17117 | | O << ')'; |
17118 | | return; |
17119 | | break; |
17120 | | case 86: |
17121 | | // L4_or_memopb_io, L4_or_memoph_io, L4_or_memopw_io |
17122 | | O << ") |= "; |
17123 | | printOperand(MI, 2, O); |
17124 | | return; |
17125 | | break; |
17126 | | case 87: |
17127 | | // L4_ploadrbf_abs, L4_ploadrbfnew_abs, L4_ploadrbt_abs, L4_ploadrbtnew_a... |
17128 | | O << " = memb(#"; |
17129 | | printOperand(MI, 2, O); |
17130 | | O << ')'; |
17131 | | return; |
17132 | | break; |
17133 | | case 88: |
17134 | | // L4_ploadrdf_abs, L4_ploadrdfnew_abs, L4_ploadrdt_abs, L4_ploadrdtnew_a... |
17135 | | O << " = memd(#"; |
17136 | | printOperand(MI, 2, O); |
17137 | | O << ')'; |
17138 | | return; |
17139 | | break; |
17140 | | case 89: |
17141 | | // L4_ploadrhf_abs, L4_ploadrhfnew_abs, L4_ploadrht_abs, L4_ploadrhtnew_a... |
17142 | | O << " = memh(#"; |
17143 | | printOperand(MI, 2, O); |
17144 | | O << ')'; |
17145 | | return; |
17146 | | break; |
17147 | | case 90: |
17148 | | // L4_ploadrif_abs, L4_ploadrifnew_abs, L4_ploadrit_abs, L4_ploadritnew_a... |
17149 | | O << " = memw(#"; |
17150 | | printOperand(MI, 2, O); |
17151 | | O << ')'; |
17152 | | return; |
17153 | | break; |
17154 | | case 91: |
17155 | | // L4_ploadrubf_abs, L4_ploadrubfnew_abs, L4_ploadrubt_abs, L4_ploadrubtn... |
17156 | | O << " = memub(#"; |
17157 | | printOperand(MI, 2, O); |
17158 | | O << ')'; |
17159 | | return; |
17160 | | break; |
17161 | | case 92: |
17162 | | // L4_ploadruhf_abs, L4_ploadruhfnew_abs, L4_ploadruht_abs, L4_ploadruhtn... |
17163 | | O << " = memuh(#"; |
17164 | | printOperand(MI, 2, O); |
17165 | | O << ')'; |
17166 | | return; |
17167 | | break; |
17168 | | case 93: |
17169 | | // L4_return_f, L4_return_fnew_pnt, L4_return_fnew_pt, L4_return_t, L4_re... |
17170 | | O << " = dealloc_return("; |
17171 | | printOperand(MI, 2, O); |
17172 | | break; |
17173 | | case 94: |
17174 | | // L4_sub_memopb_io, L4_sub_memoph_io, L4_sub_memopw_io |
17175 | | O << ") -= "; |
17176 | | printOperand(MI, 2, O); |
17177 | | return; |
17178 | | break; |
17179 | | case 95: |
17180 | | // M2_cmacsc_s0, M2_cmpysc_s0, M2_cnacsc_s0 |
17181 | | O << "*):sat"; |
17182 | | return; |
17183 | | break; |
17184 | | case 96: |
17185 | | // M2_cmacsc_s1, M2_cmpysc_s1, M2_cnacsc_s1, M7_wcmpyiwc, M7_wcmpyrwc |
17186 | | O << "*):<<1:sat"; |
17187 | | return; |
17188 | | break; |
17189 | | case 97: |
17190 | | // M2_cmpyrsc_s0 |
17191 | | O << "*):rnd:sat"; |
17192 | | return; |
17193 | | break; |
17194 | | case 98: |
17195 | | // M2_cmpyrsc_s1, M4_cmpyi_whc, M4_cmpyr_whc, M7_wcmpyiwc_rnd, M7_wcmpyrw... |
17196 | | O << "*):<<1:rnd:sat"; |
17197 | | return; |
17198 | | break; |
17199 | | case 99: |
17200 | | // M2_vrcmaci_s0c, M2_vrcmacr_s0c, M2_vrcmpyi_s0c, M2_vrcmpyr_s0c, M7_dcm... |
17201 | | O << "*)"; |
17202 | | return; |
17203 | | break; |
17204 | | case 100: |
17205 | | // M2_vrcmpys_acc_s1_h, M2_vrcmpys_s1_h |
17206 | | O << "):<<1:sat:raw:hi"; |
17207 | | return; |
17208 | | break; |
17209 | | case 101: |
17210 | | // M2_vrcmpys_acc_s1_l, M2_vrcmpys_s1_l |
17211 | | O << "):<<1:sat:raw:lo"; |
17212 | | return; |
17213 | | break; |
17214 | | case 102: |
17215 | | // M2_vrcmpys_s1rp_h |
17216 | | O << "):<<1:rnd:sat:raw:hi"; |
17217 | | return; |
17218 | | break; |
17219 | | case 103: |
17220 | | // M2_vrcmpys_s1rp_l |
17221 | | O << "):<<1:rnd:sat:raw:lo"; |
17222 | | return; |
17223 | | break; |
17224 | | case 104: |
17225 | | // M4_mpyri_addi, M4_mpyrr_addi |
17226 | | O << ",mpyi("; |
17227 | | printOperand(MI, 2, O); |
17228 | | break; |
17229 | | case 105: |
17230 | | // M4_vrmpyeh_acc_s1, M4_vrmpyeh_s1, M4_vrmpyoh_acc_s1, M4_vrmpyoh_s1 |
17231 | | O << "):<<1"; |
17232 | | return; |
17233 | | break; |
17234 | | case 106: |
17235 | | // S2_pstorerbf_pi, S2_pstorerbfnew_pi, S2_pstorerbnewf_pi, S2_pstorerbne... |
17236 | | printOperand(MI, 0, O); |
17237 | | break; |
17238 | | case 107: |
17239 | | // S2_storerb_pbr, S2_storerbnew_pbr, S2_storerd_pbr, S2_storerf_pbr, S2_... |
17240 | | O << ":brev) = "; |
17241 | | printOperand(MI, 3, O); |
17242 | | break; |
17243 | | case 108: |
17244 | | // S2_storerb_pci, S2_storerbnew_pci, S2_storerd_pci, S2_storerf_pci, S2_... |
17245 | | O << ":circ("; |
17246 | | printOperand(MI, 3, O); |
17247 | | O << ")) = "; |
17248 | | printOperand(MI, 4, O); |
17249 | | break; |
17250 | | case 109: |
17251 | | // S2_tableidxb, S2_tableidxd, S2_tableidxh, S2_tableidxw, S5_asrhub_rnd_... |
17252 | | O << "):raw"; |
17253 | | return; |
17254 | | break; |
17255 | | case 110: |
17256 | | // S4_addi_asl_ri, S4_andi_asl_ri, S4_ori_asl_ri, S4_subi_asl_ri |
17257 | | O << ",asl("; |
17258 | | printOperand(MI, 2, O); |
17259 | | O << ",#"; |
17260 | | printOperand(MI, 3, O); |
17261 | | O << "))"; |
17262 | | return; |
17263 | | break; |
17264 | | case 111: |
17265 | | // S4_addi_lsr_ri, S4_andi_lsr_ri, S4_ori_lsr_ri, S4_subi_lsr_ri |
17266 | | O << ",lsr("; |
17267 | | printOperand(MI, 2, O); |
17268 | | O << ",#"; |
17269 | | printOperand(MI, 3, O); |
17270 | | O << "))"; |
17271 | | return; |
17272 | | break; |
17273 | | case 112: |
17274 | | // S4_vxaddsubhr, S4_vxsubaddhr |
17275 | | O << "):rnd:>>1:sat"; |
17276 | | return; |
17277 | | break; |
17278 | | case 113: |
17279 | | // SA1_and1 |
17280 | | O << ",#1)"; |
17281 | | return; |
17282 | | break; |
17283 | | case 114: |
17284 | | // SA1_combinerz |
17285 | | O << ",#0)"; |
17286 | | return; |
17287 | | break; |
17288 | | case 115: |
17289 | | // SA1_zxtb |
17290 | | O << ",#255)"; |
17291 | | return; |
17292 | | break; |
17293 | | case 116: |
17294 | | // SS2_storebi0, SS2_storewi0 |
17295 | | O << ") = #0"; |
17296 | | return; |
17297 | | break; |
17298 | | case 117: |
17299 | | // SS2_storebi1, SS2_storewi1 |
17300 | | O << ") = #1"; |
17301 | | return; |
17302 | | break; |
17303 | | case 118: |
17304 | | // V6_shuffeqw, V6_vasrvwuhrndsat, V6_vasrvwuhsat, V6_vasrwh, V6_vasrwhrn... |
17305 | | O << ".w,"; |
17306 | | break; |
17307 | | case 119: |
17308 | | // V6_v6mpyhubs10, V6_v6mpyvubs10, V6_vlutvvb_oracci, V6_vlutvvbi |
17309 | | O << ".b,#"; |
17310 | | break; |
17311 | | case 120: |
17312 | | // V6_v6mpyhubs10_vxx |
17313 | | O << "):h"; |
17314 | | return; |
17315 | | break; |
17316 | | case 121: |
17317 | | // V6_v6mpyvubs10_vxx |
17318 | | O << "):v"; |
17319 | | return; |
17320 | | break; |
17321 | | case 122: |
17322 | | // V6_vS32b_nt_ai, V6_vS32b_nt_new_ai, V6_vS32b_nt_new_pi, V6_vS32b_nt_ne... |
17323 | | O << "):nt = "; |
17324 | | break; |
17325 | | case 123: |
17326 | | // V6_vS32b_srls_ai, V6_vS32b_srls_pi, V6_vS32b_srls_ppu |
17327 | | O << "):scatter_release"; |
17328 | | return; |
17329 | | break; |
17330 | | case 124: |
17331 | | // V6_vabsb, V6_vaddb, V6_vaddb_dv, V6_vavgb, V6_vcvt_hf_b, V6_vdmpyhb, V... |
17332 | | O << ".b)"; |
17333 | | return; |
17334 | | break; |
17335 | | case 125: |
17336 | | // V6_vabsb_sat, V6_vaddbsat, V6_vaddbsat_dv, V6_vaddububb_sat, V6_vsubbs... |
17337 | | O << ".b):sat"; |
17338 | | return; |
17339 | | break; |
17340 | | case 126: |
17341 | | // V6_vabsh, V6_vaslhv, V6_vavgh, V6_vcvt_hf_h, V6_vmpyh, V6_vmpyh_acc, V... |
17342 | | O << ".h)"; |
17343 | | return; |
17344 | | break; |
17345 | | case 127: |
17346 | | // V6_vabsh_sat, V6_vdmpyhisat, V6_vdmpyhisat_acc, V6_vdmpyhsat, V6_vdmpy... |
17347 | | O << ".h):sat"; |
17348 | | return; |
17349 | | break; |
17350 | | case 128: |
17351 | | // V6_vabsw, V6_vaslwv, V6_vasrwv, V6_vavgw |
17352 | | O << ".w)"; |
17353 | | return; |
17354 | | break; |
17355 | | case 129: |
17356 | | // V6_vabsw_sat |
17357 | | O << ".w):sat"; |
17358 | | return; |
17359 | | break; |
17360 | | case 130: |
17361 | | // V6_vadd_hf, V6_vadd_sf_hf, V6_vgthf, V6_vgthf_and, V6_vgthf_or, V6_vgt... |
17362 | | O << ".hf,"; |
17363 | | break; |
17364 | | case 131: |
17365 | | // V6_vadd_qf16, V6_vadd_qf16_mix, V6_vmpy_qf16, V6_vmpy_qf16_mix_hf, V6_... |
17366 | | O << ".qf16,"; |
17367 | | printOperand(MI, 2, O); |
17368 | | break; |
17369 | | case 132: |
17370 | | // V6_vadd_qf32, V6_vadd_qf32_mix, V6_vmpy_qf32, V6_vsub_qf32, V6_vsub_qf... |
17371 | | O << ".qf32,"; |
17372 | | printOperand(MI, 2, O); |
17373 | | break; |
17374 | | case 133: |
17375 | | // V6_vadd_sf, V6_vadd_sf_sf, V6_vcvt_hf_sf, V6_vgtsf, V6_vgtsf_and, V6_v... |
17376 | | O << ".sf,"; |
17377 | | break; |
17378 | | case 134: |
17379 | | // V6_vadd_sf_bf, V6_vgtbf, V6_vgtbf_and, V6_vgtbf_or, V6_vgtbf_xor, V6_v... |
17380 | | O << ".bf,"; |
17381 | | break; |
17382 | | case 135: |
17383 | | // V6_vaddcarryo |
17384 | | O << " = vadd("; |
17385 | | printOperand(MI, 2, O); |
17386 | | O << ".w,"; |
17387 | | printOperand(MI, 3, O); |
17388 | | O << ".w):carry"; |
17389 | | return; |
17390 | | break; |
17391 | | case 136: |
17392 | | // V6_vaddubsat, V6_vaddubsat_dv, V6_vsububsat, V6_vsububsat_dv |
17393 | | O << ".ub):sat"; |
17394 | | return; |
17395 | | break; |
17396 | | case 137: |
17397 | | // V6_vavgbrnd |
17398 | | O << ".b):rnd"; |
17399 | | return; |
17400 | | break; |
17401 | | case 138: |
17402 | | // V6_vavghrnd |
17403 | | O << ".h):rnd"; |
17404 | | return; |
17405 | | break; |
17406 | | case 139: |
17407 | | // V6_vavgubrnd |
17408 | | O << ".ub):rnd"; |
17409 | | return; |
17410 | | break; |
17411 | | case 140: |
17412 | | // V6_vavguh, V6_vcvt_hf_uh, V6_vmpyhus, V6_vmpyhus_acc, V6_vmpyiewuh_acc |
17413 | | O << ".uh)"; |
17414 | | return; |
17415 | | break; |
17416 | | case 141: |
17417 | | // V6_vavguhrnd |
17418 | | O << ".uh):rnd"; |
17419 | | return; |
17420 | | break; |
17421 | | case 142: |
17422 | | // V6_vavguw |
17423 | | O << ".uw)"; |
17424 | | return; |
17425 | | break; |
17426 | | case 143: |
17427 | | // V6_vavguwrnd |
17428 | | O << ".uw):rnd"; |
17429 | | return; |
17430 | | break; |
17431 | | case 144: |
17432 | | // V6_vavgwrnd |
17433 | | O << ".w):rnd"; |
17434 | | return; |
17435 | | break; |
17436 | | case 145: |
17437 | | // V6_vccombine, V6_vnccombine |
17438 | | O << " = vcombine("; |
17439 | | printOperand(MI, 2, O); |
17440 | | O << ','; |
17441 | | printOperand(MI, 3, O); |
17442 | | O << ')'; |
17443 | | return; |
17444 | | break; |
17445 | | case 146: |
17446 | | // V6_vconv_hf_qf16 |
17447 | | O << ".qf16"; |
17448 | | return; |
17449 | | break; |
17450 | | case 147: |
17451 | | // V6_vconv_hf_qf32, V6_vconv_sf_qf32 |
17452 | | O << ".qf32"; |
17453 | | return; |
17454 | | break; |
17455 | | case 148: |
17456 | | // V6_vconv_sf_w |
17457 | | O << ".w"; |
17458 | | return; |
17459 | | break; |
17460 | | case 149: |
17461 | | // V6_vdmpyhsuisat, V6_vdmpyhsuisat_acc |
17462 | | O << ".uh,#1):sat"; |
17463 | | return; |
17464 | | break; |
17465 | | case 150: |
17466 | | // V6_vdmpyhsusat, V6_vdmpyhsusat_acc |
17467 | | O << ".uh):sat"; |
17468 | | return; |
17469 | | break; |
17470 | | case 151: |
17471 | | // V6_vgathermhq |
17472 | | O << ".h).h"; |
17473 | | return; |
17474 | | break; |
17475 | | case 152: |
17476 | | // V6_vgathermhwq |
17477 | | O << ".w).h"; |
17478 | | return; |
17479 | | break; |
17480 | | case 153: |
17481 | | // V6_vlutvwh_oracci, V6_vlutvwhi |
17482 | | O << ".h,#"; |
17483 | | break; |
17484 | | case 154: |
17485 | | // V6_vmpyowh |
17486 | | O << ".h):<<1:sat"; |
17487 | | return; |
17488 | | break; |
17489 | | case 155: |
17490 | | // V6_vmpyowh_rnd |
17491 | | O << ".h):<<1:rnd:sat"; |
17492 | | return; |
17493 | | break; |
17494 | | case 156: |
17495 | | // V6_vmpyowh_rnd_sacc |
17496 | | O << ".h):<<1:rnd:sat:shift"; |
17497 | | return; |
17498 | | break; |
17499 | | case 157: |
17500 | | // V6_vmpyowh_sacc |
17501 | | O << ".h):<<1:sat:shift"; |
17502 | | return; |
17503 | | break; |
17504 | | case 158: |
17505 | | // V6_vrmpyubi, V6_vrmpyubi_acc |
17506 | | O << ".ub,#"; |
17507 | | break; |
17508 | | case 159: |
17509 | | // V6_vrmpyzbb_rx_acc, V6_vrmpyzbub_rx_acc, V6_vrmpyzcb_rx_acc, V6_vrmpyz... |
17510 | | printOperand(MI, 3, O); |
17511 | | break; |
17512 | | case 160: |
17513 | | // V6_vscattermhq |
17514 | | O << ".h).h = "; |
17515 | | printOperand(MI, 4, O); |
17516 | | return; |
17517 | | break; |
17518 | | case 161: |
17519 | | // V6_vscattermhwq |
17520 | | O << ".w).h = "; |
17521 | | printOperand(MI, 4, O); |
17522 | | return; |
17523 | | break; |
17524 | | case 162: |
17525 | | // V6_vscattermwq |
17526 | | O << ".w).w = "; |
17527 | | printOperand(MI, 4, O); |
17528 | | return; |
17529 | | break; |
17530 | | case 163: |
17531 | | // V6_vsubcarryo |
17532 | | O << " = vsub("; |
17533 | | printOperand(MI, 2, O); |
17534 | | O << ".w,"; |
17535 | | printOperand(MI, 3, O); |
17536 | | O << ".w):carry"; |
17537 | | return; |
17538 | | break; |
17539 | | case 164: |
17540 | | // dep_S2_packhl |
17541 | | O << "):deprecated"; |
17542 | | return; |
17543 | | break; |
17544 | | } |
17545 | | |
17546 | | |
17547 | | // Fragment 3 encoded into 6 bits for 60 unique commands. |
17548 | | switch ((Bits >> 32) & 63) { |
17549 | | default: llvm_unreachable("Invalid command number."); |
17550 | | case 0: |
17551 | | // A2_addsp, V6_vscattermh_add_alt, V6_vscattermh_alt, V6_vscattermw_add_... |
17552 | | O << ','; |
17553 | | break; |
17554 | | case 1: |
17555 | | // L2_loadalignb_zomap, L2_loadalignh_zomap, V6_zldp0, dup_L2_loadrb_io, ... |
17556 | | O << ')'; |
17557 | | return; |
17558 | | break; |
17559 | | case 2: |
17560 | | // L2_ploadrbf_zomap, L2_ploadrbfnew_zomap, L2_ploadrbt_zomap, L2_ploadrb... |
17561 | | printOperand(MI, 2, O); |
17562 | | break; |
17563 | | case 3: |
17564 | | // S2_pstorerbf_zomap, S2_pstorerbnewf_zomap, S2_pstorerbnewt_zomap, S2_p... |
17565 | | O << ") = "; |
17566 | | printOperand(MI, 2, O); |
17567 | | break; |
17568 | | case 4: |
17569 | | // S4_storeirbf_zomap, S4_storeirbfnew_zomap, S4_storeirbt_zomap, S4_stor... |
17570 | | O << ") = #"; |
17571 | | printOperand(MI, 2, O); |
17572 | | return; |
17573 | | break; |
17574 | | case 5: |
17575 | | // V6_MAP_equb_and, V6_MAP_equb_ior, V6_MAP_equb_xor, V6_MAP_equh_and, V6... |
17576 | | printOperand(MI, 3, O); |
17577 | | break; |
17578 | | case 6: |
17579 | | // V6_stnpnt0, V6_stnqnt0, V6_stpnt0, V6_stqnt0 |
17580 | | O << "):nt = "; |
17581 | | printOperand(MI, 2, O); |
17582 | | return; |
17583 | | break; |
17584 | | case 7: |
17585 | | // V6_v6mpyhubs10_alt |
17586 | | O << "):h"; |
17587 | | return; |
17588 | | break; |
17589 | | case 8: |
17590 | | // V6_v6mpyvubs10_alt |
17591 | | O << "):v"; |
17592 | | return; |
17593 | | break; |
17594 | | case 9: |
17595 | | // V6_vrmpybusi_acc_alt, V6_vrmpyubi_acc_alt, V6_vrsadubi_acc_alt, F2_sff... |
17596 | | printOperand(MI, 4, O); |
17597 | | break; |
17598 | | case 10: |
17599 | | // V6_vscattermwhq_alt, S2_storerf_pbr, S2_storerf_pci |
17600 | | O << ".h"; |
17601 | | return; |
17602 | | break; |
17603 | | case 11: |
17604 | | // V6_vscattermwq_alt |
17605 | | O << ".w"; |
17606 | | return; |
17607 | | break; |
17608 | | case 12: |
17609 | | // dup_A2_addi, A2_addi, A2_paddif, A2_paddifnew, A2_paddit, A2_padditnew... |
17610 | | O << ",#"; |
17611 | | break; |
17612 | | case 13: |
17613 | | // dup_S2_allocframe, L4_return_f, L4_return_t, S2_allocframe |
17614 | | O << "):raw"; |
17615 | | return; |
17616 | | break; |
17617 | | case 14: |
17618 | | // A2_addh_h16_hh, A2_addh_h16_hl, A2_addh_h16_sat_hh, A2_addh_h16_sat_hl... |
17619 | | O << ".h,"; |
17620 | | printOperand(MI, 2, O); |
17621 | | break; |
17622 | | case 15: |
17623 | | // A2_addh_h16_lh, A2_addh_h16_ll, A2_addh_h16_sat_lh, A2_addh_h16_sat_ll... |
17624 | | O << ".l,"; |
17625 | | printOperand(MI, 2, O); |
17626 | | break; |
17627 | | case 16: |
17628 | | // A2_tfrih, A2_tfril, HI, LO, S2_storerb_pbr, S2_storerb_pci, S2_storerd... |
17629 | | return; |
17630 | | break; |
17631 | | case 17: |
17632 | | // A5_ACS |
17633 | | O << " = vacsh("; |
17634 | | printOperand(MI, 3, O); |
17635 | | O << ','; |
17636 | | printOperand(MI, 4, O); |
17637 | | O << ')'; |
17638 | | return; |
17639 | | break; |
17640 | | case 18: |
17641 | | // A6_vminub_RdP |
17642 | | O << " = vminub("; |
17643 | | printOperand(MI, 2, O); |
17644 | | O << ','; |
17645 | | printOperand(MI, 3, O); |
17646 | | O << ')'; |
17647 | | return; |
17648 | | break; |
17649 | | case 19: |
17650 | | // C4_and_andn, C4_and_orn, C4_or_andn, C4_or_orn |
17651 | | O << ",!"; |
17652 | | printOperand(MI, 3, O); |
17653 | | O << "))"; |
17654 | | return; |
17655 | | break; |
17656 | | case 20: |
17657 | | // F2_sfinvsqrta |
17658 | | O << " = sfinvsqrta("; |
17659 | | printOperand(MI, 2, O); |
17660 | | O << ')'; |
17661 | | return; |
17662 | | break; |
17663 | | case 21: |
17664 | | // F2_sfrecipa |
17665 | | O << " = sfrecipa("; |
17666 | | printOperand(MI, 2, O); |
17667 | | O << ','; |
17668 | | printOperand(MI, 3, O); |
17669 | | O << ')'; |
17670 | | return; |
17671 | | break; |
17672 | | case 22: |
17673 | | // J4_cmpeq_fp0_jump_nt, J4_cmpeqi_fp0_jump_nt, J4_cmpeqn1_fp0_jump_nt, J... |
17674 | | O << "); if (!p0.new) jump:nt "; |
17675 | | printBrtarget(MI, 2, O); |
17676 | | return; |
17677 | | break; |
17678 | | case 23: |
17679 | | // J4_cmpeq_fp0_jump_t, J4_cmpeqi_fp0_jump_t, J4_cmpeqn1_fp0_jump_t, J4_c... |
17680 | | O << "); if (!p0.new) jump:t "; |
17681 | | printBrtarget(MI, 2, O); |
17682 | | return; |
17683 | | break; |
17684 | | case 24: |
17685 | | // J4_cmpeq_fp1_jump_nt, J4_cmpeqi_fp1_jump_nt, J4_cmpeqn1_fp1_jump_nt, J... |
17686 | | O << "); if (!p1.new) jump:nt "; |
17687 | | printBrtarget(MI, 2, O); |
17688 | | return; |
17689 | | break; |
17690 | | case 25: |
17691 | | // J4_cmpeq_fp1_jump_t, J4_cmpeqi_fp1_jump_t, J4_cmpeqn1_fp1_jump_t, J4_c... |
17692 | | O << "); if (!p1.new) jump:t "; |
17693 | | printBrtarget(MI, 2, O); |
17694 | | return; |
17695 | | break; |
17696 | | case 26: |
17697 | | // J4_cmpeq_tp0_jump_nt, J4_cmpeqi_tp0_jump_nt, J4_cmpeqn1_tp0_jump_nt, J... |
17698 | | O << "); if (p0.new) jump:nt "; |
17699 | | printBrtarget(MI, 2, O); |
17700 | | return; |
17701 | | break; |
17702 | | case 27: |
17703 | | // J4_cmpeq_tp0_jump_t, J4_cmpeqi_tp0_jump_t, J4_cmpeqn1_tp0_jump_t, J4_c... |
17704 | | O << "); if (p0.new) jump:t "; |
17705 | | printBrtarget(MI, 2, O); |
17706 | | return; |
17707 | | break; |
17708 | | case 28: |
17709 | | // J4_cmpeq_tp1_jump_nt, J4_cmpeqi_tp1_jump_nt, J4_cmpeqn1_tp1_jump_nt, J... |
17710 | | O << "); if (p1.new) jump:nt "; |
17711 | | printBrtarget(MI, 2, O); |
17712 | | return; |
17713 | | break; |
17714 | | case 29: |
17715 | | // J4_cmpeq_tp1_jump_t, J4_cmpeqi_tp1_jump_t, J4_cmpeqn1_tp1_jump_t, J4_c... |
17716 | | O << "); if (p1.new) jump:t "; |
17717 | | printBrtarget(MI, 2, O); |
17718 | | return; |
17719 | | break; |
17720 | | case 30: |
17721 | | // J4_cmplt_f_jumpnv_nt, J4_cmplt_t_jumpnv_nt, J4_cmpltu_f_jumpnv_nt, J4_... |
17722 | | O << ".new)) jump:nt "; |
17723 | | printBrtarget(MI, 2, O); |
17724 | | return; |
17725 | | break; |
17726 | | case 31: |
17727 | | // J4_cmplt_f_jumpnv_t, J4_cmplt_t_jumpnv_t, J4_cmpltu_f_jumpnv_t, J4_cmp... |
17728 | | O << ".new)) jump:t "; |
17729 | | printBrtarget(MI, 2, O); |
17730 | | return; |
17731 | | break; |
17732 | | case 32: |
17733 | | // L2_loadalignb_io, L2_loadalignh_io, S2_pstorerbf_io, S2_pstorerbnewf_i... |
17734 | | O << "+#"; |
17735 | | break; |
17736 | | case 33: |
17737 | | // L2_loadalignb_pbr, L2_loadalignb_pr, L2_loadalignh_pbr, L2_loadalignh_... |
17738 | | O << "++"; |
17739 | | break; |
17740 | | case 34: |
17741 | | // L2_loadalignb_pci, L2_loadalignb_pi, L2_loadalignh_pci, L2_loadalignh_... |
17742 | | O << "++#"; |
17743 | | break; |
17744 | | case 35: |
17745 | | // L2_loadalignb_pcr, L2_loadalignh_pcr |
17746 | | O << "++I:circ("; |
17747 | | printOperand(MI, 4, O); |
17748 | | O << "))"; |
17749 | | return; |
17750 | | break; |
17751 | | case 36: |
17752 | | // L2_loadbsw2_pbr, L2_loadbsw4_pbr, L2_loadbzw2_pbr, L2_loadbzw4_pbr, L2... |
17753 | | O << ":brev)"; |
17754 | | return; |
17755 | | break; |
17756 | | case 37: |
17757 | | // L2_loadbsw2_pci, L2_loadbsw4_pci, L2_loadbzw2_pci, L2_loadbzw4_pci, L2... |
17758 | | O << ":circ("; |
17759 | | printOperand(MI, 4, O); |
17760 | | O << "))"; |
17761 | | return; |
17762 | | break; |
17763 | | case 38: |
17764 | | // L2_ploadrbf_pi, L2_ploadrbfnew_pi, L2_ploadrbt_pi, L2_ploadrbtnew_pi, ... |
17765 | | printOperand(MI, 1, O); |
17766 | | break; |
17767 | | case 39: |
17768 | | // L4_loadalignb_ap, L4_loadalignh_ap |
17769 | | O << "=#"; |
17770 | | printOperand(MI, 3, O); |
17771 | | O << ')'; |
17772 | | return; |
17773 | | break; |
17774 | | case 40: |
17775 | | // L4_loadalignb_ur, L4_loadalignh_ur |
17776 | | O << "<<#"; |
17777 | | printOperand(MI, 3, O); |
17778 | | O << "+#"; |
17779 | | printOperand(MI, 4, O); |
17780 | | O << ')'; |
17781 | | return; |
17782 | | break; |
17783 | | case 41: |
17784 | | // L4_return_fnew_pnt, L4_return_tnew_pnt |
17785 | | O << "):nt:raw"; |
17786 | | return; |
17787 | | break; |
17788 | | case 42: |
17789 | | // L4_return_fnew_pt, L4_return_tnew_pt |
17790 | | O << "):t:raw"; |
17791 | | return; |
17792 | | break; |
17793 | | case 43: |
17794 | | // M4_mpyri_addr, M4_mpyrr_addr |
17795 | | O << ",mpyi("; |
17796 | | printOperand(MI, 2, O); |
17797 | | break; |
17798 | | case 44: |
17799 | | // M4_mpyri_addr_u2 |
17800 | | O << ",mpyi(#"; |
17801 | | printOperand(MI, 2, O); |
17802 | | O << ','; |
17803 | | printOperand(MI, 3, O); |
17804 | | O << "))"; |
17805 | | return; |
17806 | | break; |
17807 | | case 45: |
17808 | | // S2_storerbnew_pbr, S2_storerbnew_pci, S2_storerhnew_pbr, S2_storerhnew... |
17809 | | O << ".new"; |
17810 | | return; |
17811 | | break; |
17812 | | case 46: |
17813 | | // S4_addaddi |
17814 | | O << ",add("; |
17815 | | printOperand(MI, 2, O); |
17816 | | O << ",#"; |
17817 | | printOperand(MI, 3, O); |
17818 | | O << "))"; |
17819 | | return; |
17820 | | break; |
17821 | | case 47: |
17822 | | // S4_pstorerbf_rr, S4_pstorerbfnew_rr, S4_pstorerbnewf_rr, S4_pstorerbne... |
17823 | | O << '+'; |
17824 | | printOperand(MI, 2, O); |
17825 | | O << "<<#"; |
17826 | | printOperand(MI, 3, O); |
17827 | | O << ") = "; |
17828 | | printOperand(MI, 4, O); |
17829 | | break; |
17830 | | case 48: |
17831 | | // S4_subaddi |
17832 | | O << ",sub(#"; |
17833 | | printOperand(MI, 2, O); |
17834 | | O << ','; |
17835 | | printOperand(MI, 3, O); |
17836 | | O << "))"; |
17837 | | return; |
17838 | | break; |
17839 | | case 49: |
17840 | | // SA1_inc |
17841 | | O << ",#1)"; |
17842 | | return; |
17843 | | break; |
17844 | | case 50: |
17845 | | // V6_vL32b_nt_ai, V6_vL32b_nt_cur_ai, V6_vL32b_nt_cur_pi, V6_vL32b_nt_cu... |
17846 | | O << "):nt"; |
17847 | | return; |
17848 | | break; |
17849 | | case 51: |
17850 | | // V6_vadd_qf16, V6_vmpy_qf16, V6_vmpy_qf32_qf16, V6_vsub_qf16 |
17851 | | O << ".qf16)"; |
17852 | | return; |
17853 | | break; |
17854 | | case 52: |
17855 | | // V6_vadd_qf16_mix, V6_vmpy_qf16_mix_hf, V6_vmpy_qf32_mix_hf, V6_vsub_qf... |
17856 | | O << ".hf)"; |
17857 | | return; |
17858 | | break; |
17859 | | case 53: |
17860 | | // V6_vadd_qf32, V6_vmpy_qf32, V6_vsub_qf32 |
17861 | | O << ".qf32)"; |
17862 | | return; |
17863 | | break; |
17864 | | case 54: |
17865 | | // V6_vadd_qf32_mix, V6_vsub_qf32_mix |
17866 | | O << ".sf)"; |
17867 | | return; |
17868 | | break; |
17869 | | case 55: |
17870 | | // V6_vaddcarry, V6_vaddcarrysat, V6_vaddw, V6_vaddw_dv, V6_vaddwsat, V6_... |
17871 | | O << ".w,"; |
17872 | | break; |
17873 | | case 56: |
17874 | | // V6_vadduhw, V6_vsubuhw |
17875 | | O << ".uh,"; |
17876 | | printOperand(MI, 2, O); |
17877 | | O << ".uh)"; |
17878 | | return; |
17879 | | break; |
17880 | | case 57: |
17881 | | // V6_vrmpyzbb_rt, V6_vrmpyzbb_rt_acc, V6_vrmpyzbb_rx, V6_vrmpyzbb_rx_acc... |
17882 | | O << ".b,"; |
17883 | | break; |
17884 | | case 58: |
17885 | | // V6_vrmpyzcb_rt, V6_vrmpyzcb_rt_acc, V6_vrmpyzcb_rx, V6_vrmpyzcb_rx_acc... |
17886 | | O << ".c,"; |
17887 | | break; |
17888 | | case 59: |
17889 | | // V6_vrmpyznb_rt, V6_vrmpyznb_rt_acc, V6_vrmpyznb_rx, V6_vrmpyznb_rx_acc |
17890 | | O << ".n,"; |
17891 | | break; |
17892 | | } |
17893 | | |
17894 | | |
17895 | | // Fragment 4 encoded into 6 bits for 64 unique commands. |
17896 | | switch ((Bits >> 38) & 63) { |
17897 | | default: llvm_unreachable("Invalid command number."); |
17898 | | case 0: |
17899 | | // A2_addsp, V6_vscattermh_add_alt, V6_vscattermh_alt, V6_vscattermw_add_... |
17900 | | printOperand(MI, 2, O); |
17901 | | break; |
17902 | | case 1: |
17903 | | // L2_ploadrbf_zomap, L2_ploadrbfnew_zomap, L2_ploadrbt_zomap, L2_ploadrb... |
17904 | | O << ')'; |
17905 | | return; |
17906 | | break; |
17907 | | case 2: |
17908 | | // S2_pstorerbf_zomap, S2_pstorerbt_zomap, S2_pstorerdf_zomap, S2_pstorer... |
17909 | | return; |
17910 | | break; |
17911 | | case 3: |
17912 | | // S2_pstorerbnewf_zomap, S2_pstorerbnewt_zomap, S2_pstorerhnewf_zomap, S... |
17913 | | O << ".new"; |
17914 | | return; |
17915 | | break; |
17916 | | case 4: |
17917 | | // S2_pstorerff_zomap, S2_pstorerft_zomap, S4_pstorerffnew_zomap, S4_psto... |
17918 | | O << ".h"; |
17919 | | return; |
17920 | | break; |
17921 | | case 5: |
17922 | | // S5_vasrhrnd_goodsyntax, M2_dpmpyss_rnd_s0, S2_asr_i_p_rnd, S2_asr_i_r_... |
17923 | | O << "):rnd"; |
17924 | | return; |
17925 | | break; |
17926 | | case 6: |
17927 | | // V6_MAP_equb, V6_MAP_equb_and, V6_MAP_equb_ior, V6_MAP_equb_xor, V6_vrm... |
17928 | | O << ".ub)"; |
17929 | | return; |
17930 | | break; |
17931 | | case 7: |
17932 | | // V6_MAP_equh, V6_MAP_equh_and, V6_MAP_equh_ior, V6_MAP_equh_xor, V6_vab... |
17933 | | O << ".uh)"; |
17934 | | return; |
17935 | | break; |
17936 | | case 8: |
17937 | | // V6_MAP_equw, V6_MAP_equw_and, V6_MAP_equw_ior, V6_MAP_equw_xor, V6_vgt... |
17938 | | O << ".uw)"; |
17939 | | return; |
17940 | | break; |
17941 | | case 9: |
17942 | | // V6_ldcnpnt0, V6_ldcpnt0, V6_ldnpnt0, V6_ldpnt0, V6_ldtnpnt0, V6_ldtpnt... |
17943 | | O << "):nt"; |
17944 | | return; |
17945 | | break; |
17946 | | case 10: |
17947 | | // V6_vtran2x2_map, L2_loadalignb_pbr, L2_loadalignb_pci, L2_loadalignb_p... |
17948 | | printOperand(MI, 4, O); |
17949 | | break; |
17950 | | case 11: |
17951 | | // A2_addh_h16_hh, A2_addh_h16_lh, A2_subh_h16_hh, A2_subh_h16_lh |
17952 | | O << ".h):<<16"; |
17953 | | return; |
17954 | | break; |
17955 | | case 12: |
17956 | | // A2_addh_h16_hl, A2_addh_h16_ll, A2_subh_h16_hl, A2_subh_h16_ll |
17957 | | O << ".l):<<16"; |
17958 | | return; |
17959 | | break; |
17960 | | case 13: |
17961 | | // A2_addh_h16_sat_hh, A2_addh_h16_sat_lh, A2_subh_h16_sat_hh, A2_subh_h1... |
17962 | | O << ".h):sat:<<16"; |
17963 | | return; |
17964 | | break; |
17965 | | case 14: |
17966 | | // A2_addh_h16_sat_hl, A2_addh_h16_sat_ll, A2_subh_h16_sat_hl, A2_subh_h1... |
17967 | | O << ".l):sat:<<16"; |
17968 | | return; |
17969 | | break; |
17970 | | case 15: |
17971 | | // A2_addh_l16_hl, A2_combine_hh, A2_combine_lh, A2_subh_l16_hl, M2_mpy_a... |
17972 | | O << ".h)"; |
17973 | | return; |
17974 | | break; |
17975 | | case 16: |
17976 | | // A2_addh_l16_ll, A2_combine_hl, A2_combine_ll, A2_subh_l16_ll, M2_mpy_a... |
17977 | | O << ".l)"; |
17978 | | return; |
17979 | | break; |
17980 | | case 17: |
17981 | | // A2_addh_l16_sat_hl, A2_subh_l16_sat_hl, M2_mpy_acc_sat_hh_s0, M2_mpy_a... |
17982 | | O << ".h):sat"; |
17983 | | return; |
17984 | | break; |
17985 | | case 18: |
17986 | | // A2_addh_l16_sat_ll, A2_subh_l16_sat_ll, M2_mpy_acc_sat_hl_s0, M2_mpy_a... |
17987 | | O << ".l):sat"; |
17988 | | return; |
17989 | | break; |
17990 | | case 19: |
17991 | | // A2_paddf, A2_paddfnew, A2_paddif, A2_paddifnew, A2_paddit, A2_padditne... |
17992 | | printOperand(MI, 3, O); |
17993 | | break; |
17994 | | case 20: |
17995 | | // A4_round_ri_sat, A4_round_rr_sat, S2_asl_i_r_sat, S2_asl_r_r_sat, S2_a... |
17996 | | O << "):sat"; |
17997 | | return; |
17998 | | break; |
17999 | | case 21: |
18000 | | // C2_mux, C2_muxri, M4_mpyrr_addr |
18001 | | O << ','; |
18002 | | printOperand(MI, 3, O); |
18003 | | break; |
18004 | | case 22: |
18005 | | // C2_muxii, C2_muxir, M4_mpyri_addr, S2_extractu, S2_extractup, S2_inser... |
18006 | | O << ",#"; |
18007 | | break; |
18008 | | case 23: |
18009 | | // F2_sffma_sc |
18010 | | O << "):scale"; |
18011 | | return; |
18012 | | break; |
18013 | | case 24: |
18014 | | // L2_ploadrbf_io, L2_ploadrbfnew_io, L2_ploadrbt_io, L2_ploadrbtnew_io, ... |
18015 | | O << "+#"; |
18016 | | printOperand(MI, 3, O); |
18017 | | break; |
18018 | | case 25: |
18019 | | // L2_ploadrbf_pi, L2_ploadrbfnew_pi, L2_ploadrbt_pi, L2_ploadrbtnew_pi, ... |
18020 | | O << "++#"; |
18021 | | printOperand(MI, 4, O); |
18022 | | break; |
18023 | | case 26: |
18024 | | // L4_ploadrbf_rr, L4_ploadrbfnew_rr, L4_ploadrbt_rr, L4_ploadrbtnew_rr, ... |
18025 | | O << '+'; |
18026 | | printOperand(MI, 3, O); |
18027 | | O << "<<#"; |
18028 | | printOperand(MI, 4, O); |
18029 | | O << ')'; |
18030 | | return; |
18031 | | break; |
18032 | | case 27: |
18033 | | // M2_hmmpyh_rs1, M2_mpy_sat_rnd_hh_s1, M2_mpy_sat_rnd_lh_s1, V6_vmpyhsrs... |
18034 | | O << ".h):<<1:rnd:sat"; |
18035 | | return; |
18036 | | break; |
18037 | | case 28: |
18038 | | // M2_hmmpyh_s1, M2_mpy_acc_sat_hh_s1, M2_mpy_acc_sat_lh_s1, M2_mpy_nac_s... |
18039 | | O << ".h):<<1:sat"; |
18040 | | return; |
18041 | | break; |
18042 | | case 29: |
18043 | | // M2_hmmpyl_rs1, M2_mpy_sat_rnd_hl_s1, M2_mpy_sat_rnd_ll_s1 |
18044 | | O << ".l):<<1:rnd:sat"; |
18045 | | return; |
18046 | | break; |
18047 | | case 30: |
18048 | | // M2_hmmpyl_s1, M2_mpy_acc_sat_hl_s1, M2_mpy_acc_sat_ll_s1, M2_mpy_nac_s... |
18049 | | O << ".l):<<1:sat"; |
18050 | | return; |
18051 | | break; |
18052 | | case 31: |
18053 | | // M2_mpy_acc_hh_s1, M2_mpy_acc_lh_s1, M2_mpy_hh_s1, M2_mpy_lh_s1, M2_mpy... |
18054 | | O << ".h):<<1"; |
18055 | | return; |
18056 | | break; |
18057 | | case 32: |
18058 | | // M2_mpy_acc_hl_s1, M2_mpy_acc_ll_s1, M2_mpy_hl_s1, M2_mpy_ll_s1, M2_mpy... |
18059 | | O << ".l):<<1"; |
18060 | | return; |
18061 | | break; |
18062 | | case 33: |
18063 | | // M2_mpy_rnd_hh_s0, M2_mpy_rnd_lh_s0, M2_mpyd_rnd_hh_s0, M2_mpyd_rnd_lh_... |
18064 | | O << ".h):rnd"; |
18065 | | return; |
18066 | | break; |
18067 | | case 34: |
18068 | | // M2_mpy_rnd_hh_s1, M2_mpy_rnd_lh_s1, M2_mpyd_rnd_hh_s1, M2_mpyd_rnd_lh_... |
18069 | | O << ".h):<<1:rnd"; |
18070 | | return; |
18071 | | break; |
18072 | | case 35: |
18073 | | // M2_mpy_rnd_hl_s0, M2_mpy_rnd_ll_s0, M2_mpyd_rnd_hl_s0, M2_mpyd_rnd_ll_... |
18074 | | O << ".l):rnd"; |
18075 | | return; |
18076 | | break; |
18077 | | case 36: |
18078 | | // M2_mpy_rnd_hl_s1, M2_mpy_rnd_ll_s1, M2_mpyd_rnd_hl_s1, M2_mpyd_rnd_ll_... |
18079 | | O << ".l):<<1:rnd"; |
18080 | | return; |
18081 | | break; |
18082 | | case 37: |
18083 | | // M2_mpy_sat_rnd_hh_s0, M2_mpy_sat_rnd_lh_s0 |
18084 | | O << ".h):rnd:sat"; |
18085 | | return; |
18086 | | break; |
18087 | | case 38: |
18088 | | // M2_mpy_sat_rnd_hl_s0, M2_mpy_sat_rnd_ll_s0 |
18089 | | O << ".l):rnd:sat"; |
18090 | | return; |
18091 | | break; |
18092 | | case 39: |
18093 | | // M2_mpy_up_s1 |
18094 | | O << "):<<1"; |
18095 | | return; |
18096 | | break; |
18097 | | case 40: |
18098 | | // M2_mpy_up_s1_sat, M4_mac_up_s1_sat, M4_nac_up_s1_sat |
18099 | | O << "):<<1:sat"; |
18100 | | return; |
18101 | | break; |
18102 | | case 41: |
18103 | | // S5_vasrhrnd |
18104 | | O << "):raw"; |
18105 | | return; |
18106 | | break; |
18107 | | case 42: |
18108 | | // V6_shuffeqw, V6_veqw, V6_veqw_and, V6_veqw_or, V6_veqw_xor, V6_vgtw, V... |
18109 | | O << ".w)"; |
18110 | | return; |
18111 | | break; |
18112 | | case 43: |
18113 | | // V6_v6mpyhubs10 |
18114 | | O << "):h"; |
18115 | | return; |
18116 | | break; |
18117 | | case 44: |
18118 | | // V6_v6mpyvubs10 |
18119 | | O << "):v"; |
18120 | | return; |
18121 | | break; |
18122 | | case 45: |
18123 | | // V6_vL32b_cur_npred_ppu, V6_vL32b_cur_pred_ppu, V6_vL32b_npred_ppu, V6_... |
18124 | | O << "++"; |
18125 | | printOperand(MI, 4, O); |
18126 | | break; |
18127 | | case 46: |
18128 | | // V6_vadd_hf, V6_vadd_sf_hf, V6_vgthf, V6_vgthf_and, V6_vgthf_or, V6_vgt... |
18129 | | O << ".hf)"; |
18130 | | return; |
18131 | | break; |
18132 | | case 47: |
18133 | | // V6_vadd_sf, V6_vadd_sf_sf, V6_vcvt_hf_sf, V6_vgtsf, V6_vgtsf_and, V6_v... |
18134 | | O << ".sf)"; |
18135 | | return; |
18136 | | break; |
18137 | | case 48: |
18138 | | // V6_vadd_sf_bf, V6_vgtbf, V6_vgtbf_and, V6_vgtbf_or, V6_vgtbf_xor, V6_v... |
18139 | | O << ".bf)"; |
18140 | | return; |
18141 | | break; |
18142 | | case 49: |
18143 | | // V6_vasrhubrndsat, V6_vasrhubsat, V6_vmpahhsat |
18144 | | O << ".h,"; |
18145 | | printOperand(MI, 3, O); |
18146 | | break; |
18147 | | case 50: |
18148 | | // V6_vasruhubrndsat, V6_vasruhubsat, V6_vmpauhuhsat |
18149 | | O << ".uh,"; |
18150 | | printOperand(MI, 3, O); |
18151 | | break; |
18152 | | case 51: |
18153 | | // V6_vasruwuhrndsat, V6_vasruwuhsat |
18154 | | O << ".uw,"; |
18155 | | printOperand(MI, 3, O); |
18156 | | break; |
18157 | | case 52: |
18158 | | // V6_vasrvuhubrndsat |
18159 | | O << ".ub):rnd:sat"; |
18160 | | return; |
18161 | | break; |
18162 | | case 53: |
18163 | | // V6_vasrvuhubsat |
18164 | | O << ".ub):sat"; |
18165 | | return; |
18166 | | break; |
18167 | | case 54: |
18168 | | // V6_vasrvwuhrndsat |
18169 | | O << ".uh):rnd:sat"; |
18170 | | return; |
18171 | | break; |
18172 | | case 55: |
18173 | | // V6_vasrvwuhsat, V6_vrounduhub |
18174 | | O << ".uh):sat"; |
18175 | | return; |
18176 | | break; |
18177 | | case 56: |
18178 | | // V6_vasrwh, V6_vasrwhrndsat, V6_vasrwhsat, V6_vasrwuhrndsat, V6_vasrwuh... |
18179 | | O << ".w,"; |
18180 | | printOperand(MI, 3, O); |
18181 | | break; |
18182 | | case 57: |
18183 | | // V6_veqb, V6_veqb_and, V6_veqb_or, V6_veqb_xor, V6_vgtb, V6_vgtb_and, V... |
18184 | | O << ".b)"; |
18185 | | return; |
18186 | | break; |
18187 | | case 58: |
18188 | | // V6_vlutvvb_nm, V6_vlutvwh_nm |
18189 | | O << "):nomatch"; |
18190 | | return; |
18191 | | break; |
18192 | | case 59: |
18193 | | // V6_vmpyuhvs |
18194 | | O << ".uh):>>16"; |
18195 | | return; |
18196 | | break; |
18197 | | case 60: |
18198 | | // V6_vrmpybusi, V6_vrmpybusi_acc |
18199 | | O << ".b,#"; |
18200 | | break; |
18201 | | case 61: |
18202 | | // V6_vrmpyzbb_rx, V6_vrmpyzbb_rx_acc, V6_vrmpyzbub_rx, V6_vrmpyzbub_rx_a... |
18203 | | printOperand(MI, 1, O); |
18204 | | break; |
18205 | | case 62: |
18206 | | // V6_vrounduwuh |
18207 | | O << ".uw):sat"; |
18208 | | return; |
18209 | | break; |
18210 | | case 63: |
18211 | | // V6_vroundwuh |
18212 | | O << ".w):sat"; |
18213 | | return; |
18214 | | break; |
18215 | | } |
18216 | | |
18217 | | |
18218 | | // Fragment 5 encoded into 6 bits for 38 unique commands. |
18219 | | switch ((Bits >> 44) & 63) { |
18220 | | default: llvm_unreachable("Invalid command number."); |
18221 | | case 0: |
18222 | | // A2_addsp, V6_vtran2x2_map, dup_A2_add, dup_A2_addi, A2_add, A2_addi, A... |
18223 | | O << ')'; |
18224 | | return; |
18225 | | break; |
18226 | | case 1: |
18227 | | // V6_vscattermh_add_alt |
18228 | | O << ".h) += "; |
18229 | | printOperand(MI, 3, O); |
18230 | | O << ".h"; |
18231 | | return; |
18232 | | break; |
18233 | | case 2: |
18234 | | // V6_vscattermh_alt |
18235 | | O << ".h) = "; |
18236 | | printOperand(MI, 3, O); |
18237 | | O << ".h"; |
18238 | | return; |
18239 | | break; |
18240 | | case 3: |
18241 | | // V6_vscattermw_add_alt, V6_vscattermwh_add_alt |
18242 | | O << ".w) += "; |
18243 | | printOperand(MI, 3, O); |
18244 | | break; |
18245 | | case 4: |
18246 | | // V6_vscattermw_alt, V6_vscattermwh_alt |
18247 | | O << ".w) = "; |
18248 | | printOperand(MI, 3, O); |
18249 | | break; |
18250 | | case 5: |
18251 | | // A2_addpsat, A2_addsat, A2_subsat, V6_vasrhubsat, V6_vasruhubsat, V6_va... |
18252 | | O << "):sat"; |
18253 | | return; |
18254 | | break; |
18255 | | case 6: |
18256 | | // A2_addsph |
18257 | | O << "):raw:hi"; |
18258 | | return; |
18259 | | break; |
18260 | | case 7: |
18261 | | // A2_addspl |
18262 | | O << "):raw:lo"; |
18263 | | return; |
18264 | | break; |
18265 | | case 8: |
18266 | | // A4_addp_c, A4_subp_c |
18267 | | O << ','; |
18268 | | printOperand(MI, 1, O); |
18269 | | O << "):carry"; |
18270 | | return; |
18271 | | break; |
18272 | | case 9: |
18273 | | // C2_muxii, C2_muxir, M4_mpyri_addr, S2_extractu, S2_extractup, S4_extra... |
18274 | | printOperand(MI, 3, O); |
18275 | | break; |
18276 | | case 10: |
18277 | | // C4_and_and, C4_and_or, C4_or_and, C4_or_or, M4_mpyri_addi, M4_mpyrr_ad... |
18278 | | O << "))"; |
18279 | | return; |
18280 | | break; |
18281 | | case 11: |
18282 | | // L2_loadalignb_pbr, L2_loadalignh_pbr |
18283 | | O << ":brev)"; |
18284 | | return; |
18285 | | break; |
18286 | | case 12: |
18287 | | // L2_loadalignb_pci, L2_loadalignh_pci |
18288 | | O << ":circ("; |
18289 | | printOperand(MI, 5, O); |
18290 | | O << "))"; |
18291 | | return; |
18292 | | break; |
18293 | | case 13: |
18294 | | // S2_insert, S2_insertp, V6_vrmpybusi_acc |
18295 | | printOperand(MI, 4, O); |
18296 | | O << ')'; |
18297 | | return; |
18298 | | break; |
18299 | | case 14: |
18300 | | // S2_pstorerbf_io, S2_pstorerbf_pi, S2_pstorerbfnew_pi, S2_pstorerbnewf_... |
18301 | | O << ") = "; |
18302 | | break; |
18303 | | case 15: |
18304 | | // S4_storeirbf_io, S4_storeirbfnew_io, S4_storeirbt_io, S4_storeirbtnew_... |
18305 | | O << ") = #"; |
18306 | | printOperand(MI, 3, O); |
18307 | | return; |
18308 | | break; |
18309 | | case 16: |
18310 | | // V6_vL32b_nt_cur_npred_ai, V6_vL32b_nt_cur_npred_pi, V6_vL32b_nt_cur_np... |
18311 | | O << "):nt"; |
18312 | | return; |
18313 | | break; |
18314 | | case 17: |
18315 | | // V6_vS32b_nt_new_npred_ai, V6_vS32b_nt_new_npred_pi, V6_vS32b_nt_new_np... |
18316 | | O << "):nt = "; |
18317 | | break; |
18318 | | case 18: |
18319 | | // V6_vaddcarry, V6_vaddcarrysat, V6_vsubcarry |
18320 | | O << ".w,"; |
18321 | | break; |
18322 | | case 19: |
18323 | | // V6_vaddw, V6_vaddw_dv, V6_vsubw, V6_vsubw_dv |
18324 | | O << ".w)"; |
18325 | | return; |
18326 | | break; |
18327 | | case 20: |
18328 | | // V6_vaddwsat, V6_vaddwsat_dv, V6_vsubwsat, V6_vsubwsat_dv |
18329 | | O << ".w):sat"; |
18330 | | return; |
18331 | | break; |
18332 | | case 21: |
18333 | | // V6_vasrhubrndsat, V6_vasruhubrndsat, V6_vasruwuhrndsat, V6_vasrwhrndsa... |
18334 | | O << "):rnd:sat"; |
18335 | | return; |
18336 | | break; |
18337 | | case 22: |
18338 | | // V6_vgathermh |
18339 | | O << ".h).h"; |
18340 | | return; |
18341 | | break; |
18342 | | case 23: |
18343 | | // V6_vgathermhw |
18344 | | O << ".w).h"; |
18345 | | return; |
18346 | | break; |
18347 | | case 24: |
18348 | | // V6_vgathermw |
18349 | | O << ".w).w"; |
18350 | | return; |
18351 | | break; |
18352 | | case 25: |
18353 | | // V6_vmpahhsat |
18354 | | O << ".h):sat"; |
18355 | | return; |
18356 | | break; |
18357 | | case 26: |
18358 | | // V6_vmpauhuhsat |
18359 | | O << ".uh):sat"; |
18360 | | return; |
18361 | | break; |
18362 | | case 27: |
18363 | | // V6_vrmpyzbb_rt, V6_vrmpyzbb_rt_acc, V6_vrmpyzcb_rt, V6_vrmpyzcb_rt_acc... |
18364 | | O << ".b)"; |
18365 | | return; |
18366 | | break; |
18367 | | case 28: |
18368 | | // V6_vrmpyzbb_rx, V6_vrmpyzbb_rx_acc, V6_vrmpyzcb_rx, V6_vrmpyzcb_rx_acc... |
18369 | | O << ".b++)"; |
18370 | | return; |
18371 | | break; |
18372 | | case 29: |
18373 | | // V6_vrmpyzbub_rt, V6_vrmpyzbub_rt_acc |
18374 | | O << ".ub)"; |
18375 | | return; |
18376 | | break; |
18377 | | case 30: |
18378 | | // V6_vrmpyzbub_rx, V6_vrmpyzbub_rx_acc |
18379 | | O << ".ub++)"; |
18380 | | return; |
18381 | | break; |
18382 | | case 31: |
18383 | | // V6_vscattermh |
18384 | | O << ".h).h = "; |
18385 | | printOperand(MI, 3, O); |
18386 | | return; |
18387 | | break; |
18388 | | case 32: |
18389 | | // V6_vscattermh_add |
18390 | | O << ".h).h += "; |
18391 | | printOperand(MI, 3, O); |
18392 | | return; |
18393 | | break; |
18394 | | case 33: |
18395 | | // V6_vscattermhw |
18396 | | O << ".w).h = "; |
18397 | | printOperand(MI, 3, O); |
18398 | | return; |
18399 | | break; |
18400 | | case 34: |
18401 | | // V6_vscattermhw_add |
18402 | | O << ".w).h += "; |
18403 | | printOperand(MI, 3, O); |
18404 | | return; |
18405 | | break; |
18406 | | case 35: |
18407 | | // V6_vscattermw |
18408 | | O << ".w).w = "; |
18409 | | printOperand(MI, 3, O); |
18410 | | return; |
18411 | | break; |
18412 | | case 36: |
18413 | | // V6_vscattermw_add |
18414 | | O << ".w).w += "; |
18415 | | printOperand(MI, 3, O); |
18416 | | return; |
18417 | | break; |
18418 | | case 37: |
18419 | | // dep_A2_addsat, dep_A2_subsat |
18420 | | O << "):sat:deprecated"; |
18421 | | return; |
18422 | | break; |
18423 | | } |
18424 | | |
18425 | | |
18426 | | // Fragment 6 encoded into 3 bits for 7 unique commands. |
18427 | | switch ((Bits >> 50) & 7) { |
18428 | | default: llvm_unreachable("Invalid command number."); |
18429 | | case 0: |
18430 | | // V6_vscattermw_add_alt, V6_vscattermw_alt |
18431 | | O << ".w"; |
18432 | | return; |
18433 | | break; |
18434 | | case 1: |
18435 | | // V6_vscattermwh_add_alt, V6_vscattermwh_alt |
18436 | | O << ".h"; |
18437 | | return; |
18438 | | break; |
18439 | | case 2: |
18440 | | // C2_muxii, C2_muxir, S2_extractu, S2_extractup, S4_extract, S4_extractp... |
18441 | | O << ')'; |
18442 | | return; |
18443 | | break; |
18444 | | case 3: |
18445 | | // M4_mpyri_addr |
18446 | | O << "))"; |
18447 | | return; |
18448 | | break; |
18449 | | case 4: |
18450 | | // S2_pstorerbf_io, S2_pstorerbnewf_io, S2_pstorerbnewt_io, S2_pstorerbt_... |
18451 | | printOperand(MI, 3, O); |
18452 | | break; |
18453 | | case 5: |
18454 | | // S2_pstorerbf_pi, S2_pstorerbfnew_pi, S2_pstorerbnewf_pi, S2_pstorerbne... |
18455 | | printOperand(MI, 4, O); |
18456 | | break; |
18457 | | case 6: |
18458 | | // V6_vaddcarry, V6_vsubcarry |
18459 | | printOperand(MI, 1, O); |
18460 | | O << "):carry"; |
18461 | | return; |
18462 | | break; |
18463 | | } |
18464 | | |
18465 | | |
18466 | | // Fragment 7 encoded into 2 bits for 4 unique commands. |
18467 | | switch ((Bits >> 53) & 3) { |
18468 | | default: llvm_unreachable("Invalid command number."); |
18469 | | case 0: |
18470 | | // S2_pstorerbf_io, S2_pstorerbf_pi, S2_pstorerbfnew_pi, S2_pstorerbt_io,... |
18471 | | return; |
18472 | | break; |
18473 | | case 1: |
18474 | | // S2_pstorerbnewf_io, S2_pstorerbnewf_pi, S2_pstorerbnewfnew_pi, S2_psto... |
18475 | | O << ".new"; |
18476 | | return; |
18477 | | break; |
18478 | | case 2: |
18479 | | // S2_pstorerff_io, S2_pstorerff_pi, S2_pstorerffnew_pi, S2_pstorerft_io,... |
18480 | | O << ".h"; |
18481 | | return; |
18482 | | break; |
18483 | | case 3: |
18484 | | // V6_vaddcarrysat |
18485 | | O << "):carry:sat"; |
18486 | | return; |
18487 | | break; |
18488 | | } |
18489 | | |
18490 | | } |
18491 | | |
18492 | | |
18493 | | /// getRegisterName - This method is automatically generated by tblgen |
18494 | | /// from the register set description. This returns the assembler name |
18495 | | /// for the specified register. |
18496 | 0 | const char *HexagonInstPrinter::getRegisterName(MCRegister Reg) { |
18497 | 0 | unsigned RegNo = Reg.id(); |
18498 | 0 | assert(RegNo && RegNo < 398 && "Invalid register number!"); |
18499 | | |
18500 | | |
18501 | 0 | #ifdef __GNUC__ |
18502 | 0 | #pragma GCC diagnostic push |
18503 | 0 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
18504 | 0 | #endif |
18505 | 0 | static const char AsmStrs[] = { |
18506 | 0 | /* 0 */ "__10000000\0" |
18507 | 0 | /* 11 */ "__1000000\0" |
18508 | 0 | /* 21 */ "__10000010\0" |
18509 | 0 | /* 32 */ "__1000010\0" |
18510 | 0 | /* 42 */ "c11:10\0" |
18511 | 0 | /* 49 */ "g11:10\0" |
18512 | 0 | /* 56 */ "r11:10\0" |
18513 | 0 | /* 63 */ "s11:10\0" |
18514 | 0 | /* 70 */ "v11:10\0" |
18515 | 0 | /* 77 */ "g10\0" |
18516 | 0 | /* 81 */ "r10\0" |
18517 | 0 | /* 85 */ "v10\0" |
18518 | 0 | /* 89 */ "__10000020\0" |
18519 | 0 | /* 100 */ "__1000020\0" |
18520 | 0 | /* 110 */ "g21:20\0" |
18521 | 0 | /* 117 */ "r21:20\0" |
18522 | 0 | /* 124 */ "s21:20\0" |
18523 | 0 | /* 131 */ "v21:20\0" |
18524 | 0 | /* 138 */ "v23:20\0" |
18525 | 0 | /* 145 */ "g20\0" |
18526 | 0 | /* 149 */ "r20\0" |
18527 | 0 | /* 153 */ "s20\0" |
18528 | 0 | /* 157 */ "v20\0" |
18529 | 0 | /* 161 */ "__10000030\0" |
18530 | 0 | /* 172 */ "__1000030\0" |
18531 | 0 | /* 182 */ "c31:30\0" |
18532 | 0 | /* 189 */ "g31:30\0" |
18533 | 0 | /* 196 */ "r31:30\0" |
18534 | 0 | /* 203 */ "s31:30\0" |
18535 | 0 | /* 210 */ "v31:30\0" |
18536 | 0 | /* 217 */ "g30\0" |
18537 | 0 | /* 221 */ "r30\0" |
18538 | 0 | /* 225 */ "v30\0" |
18539 | 0 | /* 229 */ "s41:40\0" |
18540 | 0 | /* 236 */ "s51:50\0" |
18541 | 0 | /* 243 */ "s61:60\0" |
18542 | 0 | /* 250 */ "s60\0" |
18543 | 0 | /* 254 */ "s71:70\0" |
18544 | 0 | /* 261 */ "s70\0" |
18545 | 0 | /* 265 */ "s80\0" |
18546 | 0 | /* 269 */ "c1:0\0" |
18547 | 0 | /* 274 */ "g1:0\0" |
18548 | 0 | /* 279 */ "r1:0\0" |
18549 | 0 | /* 284 */ "s1:0\0" |
18550 | 0 | /* 289 */ "v1:0\0" |
18551 | 0 | /* 294 */ "p3:0\0" |
18552 | 0 | /* 299 */ "v3:0\0" |
18553 | 0 | /* 304 */ "sa0\0" |
18554 | 0 | /* 308 */ "badva0\0" |
18555 | 0 | /* 315 */ "lc0\0" |
18556 | 0 | /* 319 */ "brkptpc0\0" |
18557 | 0 | /* 328 */ "isdbcfg0\0" |
18558 | 0 | /* 337 */ "brkptcfg0\0" |
18559 | 0 | /* 347 */ "m0\0" |
18560 | 0 | /* 350 */ "sgp0\0" |
18561 | 0 | /* 355 */ "q0\0" |
18562 | 0 | /* 358 */ "r0\0" |
18563 | 0 | /* 361 */ "cs0\0" |
18564 | 0 | /* 365 */ "gpmucnt0\0" |
18565 | 0 | /* 374 */ "v0\0" |
18566 | 0 | /* 377 */ "__10000001\0" |
18567 | 0 | /* 388 */ "__1000001\0" |
18568 | 0 | /* 398 */ "__10000011\0" |
18569 | 0 | /* 409 */ "__1000011\0" |
18570 | 0 | /* 419 */ "v10:11\0" |
18571 | 0 | /* 426 */ "g11\0" |
18572 | 0 | /* 430 */ "r11\0" |
18573 | 0 | /* 434 */ "s11\0" |
18574 | 0 | /* 438 */ "v11\0" |
18575 | 0 | /* 442 */ "__10000021\0" |
18576 | 0 | /* 453 */ "__1000021\0" |
18577 | 0 | /* 463 */ "v20:21\0" |
18578 | 0 | /* 470 */ "g21\0" |
18579 | 0 | /* 474 */ "r21\0" |
18580 | 0 | /* 478 */ "v21\0" |
18581 | 0 | /* 482 */ "v30:31\0" |
18582 | 0 | /* 489 */ "g31\0" |
18583 | 0 | /* 493 */ "r31\0" |
18584 | 0 | /* 497 */ "v31\0" |
18585 | 0 | /* 501 */ "s61\0" |
18586 | 0 | /* 505 */ "s71\0" |
18587 | 0 | /* 509 */ "v0:1\0" |
18588 | 0 | /* 514 */ "sa1\0" |
18589 | 0 | /* 518 */ "badva1\0" |
18590 | 0 | /* 525 */ "lc1\0" |
18591 | 0 | /* 529 */ "brkptpc1\0" |
18592 | 0 | /* 538 */ "isdbcfg1\0" |
18593 | 0 | /* 547 */ "brkptcfg1\0" |
18594 | 0 | /* 557 */ "m1\0" |
18595 | 0 | /* 560 */ "sgp1\0" |
18596 | 0 | /* 565 */ "q1\0" |
18597 | 0 | /* 568 */ "r1\0" |
18598 | 0 | /* 571 */ "cs1\0" |
18599 | 0 | /* 575 */ "gpmucnt1\0" |
18600 | 0 | /* 584 */ "v1\0" |
18601 | 0 | /* 587 */ "__10000002\0" |
18602 | 0 | /* 598 */ "__1000002\0" |
18603 | 0 | /* 608 */ "__10000012\0" |
18604 | 0 | /* 619 */ "__1000012\0" |
18605 | 0 | /* 629 */ "c13:12\0" |
18606 | 0 | /* 636 */ "g13:12\0" |
18607 | 0 | /* 643 */ "r13:12\0" |
18608 | 0 | /* 650 */ "s13:12\0" |
18609 | 0 | /* 657 */ "v13:12\0" |
18610 | 0 | /* 664 */ "v15:12\0" |
18611 | 0 | /* 671 */ "g12\0" |
18612 | 0 | /* 675 */ "r12\0" |
18613 | 0 | /* 679 */ "s12\0" |
18614 | 0 | /* 683 */ "v12\0" |
18615 | 0 | /* 687 */ "__10000022\0" |
18616 | 0 | /* 698 */ "__1000022\0" |
18617 | 0 | /* 708 */ "g23:22\0" |
18618 | 0 | /* 715 */ "r23:22\0" |
18619 | 0 | /* 722 */ "s23:22\0" |
18620 | 0 | /* 729 */ "v23:22\0" |
18621 | 0 | /* 736 */ "g22\0" |
18622 | 0 | /* 740 */ "r22\0" |
18623 | 0 | /* 744 */ "s22\0" |
18624 | 0 | /* 748 */ "v22\0" |
18625 | 0 | /* 752 */ "s33:32\0" |
18626 | 0 | /* 759 */ "s43:42\0" |
18627 | 0 | /* 766 */ "s53:52\0" |
18628 | 0 | /* 773 */ "s63:62\0" |
18629 | 0 | /* 780 */ "s62\0" |
18630 | 0 | /* 784 */ "s73:72\0" |
18631 | 0 | /* 791 */ "s72\0" |
18632 | 0 | /* 795 */ "c3:2\0" |
18633 | 0 | /* 800 */ "g3:2\0" |
18634 | 0 | /* 805 */ "r3:2\0" |
18635 | 0 | /* 810 */ "s3:2\0" |
18636 | 0 | /* 815 */ "v3:2\0" |
18637 | 0 | /* 820 */ "p2\0" |
18638 | 0 | /* 823 */ "q2\0" |
18639 | 0 | /* 826 */ "r2\0" |
18640 | 0 | /* 829 */ "gpmucnt2\0" |
18641 | 0 | /* 838 */ "v2\0" |
18642 | 0 | /* 841 */ "__10000003\0" |
18643 | 0 | /* 852 */ "__1000003\0" |
18644 | 0 | /* 862 */ "__10000013\0" |
18645 | 0 | /* 873 */ "__1000013\0" |
18646 | 0 | /* 883 */ "v12:13\0" |
18647 | 0 | /* 890 */ "g13\0" |
18648 | 0 | /* 894 */ "r13\0" |
18649 | 0 | /* 898 */ "s13\0" |
18650 | 0 | /* 902 */ "v13\0" |
18651 | 0 | /* 906 */ "__10000023\0" |
18652 | 0 | /* 917 */ "__1000023\0" |
18653 | 0 | /* 927 */ "v22:23\0" |
18654 | 0 | /* 934 */ "g23\0" |
18655 | 0 | /* 938 */ "r23\0" |
18656 | 0 | /* 942 */ "s23\0" |
18657 | 0 | /* 946 */ "v23\0" |
18658 | 0 | /* 950 */ "s63\0" |
18659 | 0 | /* 954 */ "s73\0" |
18660 | 0 | /* 958 */ "v2:3\0" |
18661 | 0 | /* 963 */ "p3\0" |
18662 | 0 | /* 966 */ "q3\0" |
18663 | 0 | /* 969 */ "r3\0" |
18664 | 0 | /* 972 */ "gpmucnt3\0" |
18665 | 0 | /* 981 */ "v3\0" |
18666 | 0 | /* 984 */ "__10000004\0" |
18667 | 0 | /* 995 */ "__1000004\0" |
18668 | 0 | /* 1005 */ "__10000014\0" |
18669 | 0 | /* 1016 */ "__1000014\0" |
18670 | 0 | /* 1026 */ "c15:14\0" |
18671 | 0 | /* 1033 */ "g15:14\0" |
18672 | 0 | /* 1040 */ "r15:14\0" |
18673 | 0 | /* 1047 */ "s15:14\0" |
18674 | 0 | /* 1054 */ "v15:14\0" |
18675 | 0 | /* 1061 */ "g14\0" |
18676 | 0 | /* 1065 */ "r14\0" |
18677 | 0 | /* 1069 */ "s14\0" |
18678 | 0 | /* 1073 */ "v14\0" |
18679 | 0 | /* 1077 */ "__10000024\0" |
18680 | 0 | /* 1088 */ "__1000024\0" |
18681 | 0 | /* 1098 */ "g25:24\0" |
18682 | 0 | /* 1105 */ "r25:24\0" |
18683 | 0 | /* 1112 */ "s25:24\0" |
18684 | 0 | /* 1119 */ "v25:24\0" |
18685 | 0 | /* 1126 */ "v27:24\0" |
18686 | 0 | /* 1133 */ "r24\0" |
18687 | 0 | /* 1137 */ "s24\0" |
18688 | 0 | /* 1141 */ "v24\0" |
18689 | 0 | /* 1145 */ "s35:34\0" |
18690 | 0 | /* 1152 */ "s45:44\0" |
18691 | 0 | /* 1159 */ "s44\0" |
18692 | 0 | /* 1163 */ "s55:54\0" |
18693 | 0 | /* 1170 */ "s54\0" |
18694 | 0 | /* 1174 */ "s65:64\0" |
18695 | 0 | /* 1181 */ "s64\0" |
18696 | 0 | /* 1185 */ "s75:74\0" |
18697 | 0 | /* 1192 */ "s74\0" |
18698 | 0 | /* 1196 */ "c5:4\0" |
18699 | 0 | /* 1201 */ "g5:4\0" |
18700 | 0 | /* 1206 */ "r5:4\0" |
18701 | 0 | /* 1211 */ "s5:4\0" |
18702 | 0 | /* 1216 */ "v5:4\0" |
18703 | 0 | /* 1221 */ "v7:4\0" |
18704 | 0 | /* 1226 */ "g4\0" |
18705 | 0 | /* 1229 */ "r4\0" |
18706 | 0 | /* 1232 */ "gpmucnt4\0" |
18707 | 0 | /* 1241 */ "v4\0" |
18708 | 0 | /* 1244 */ "__10000005\0" |
18709 | 0 | /* 1255 */ "__1000005\0" |
18710 | 0 | /* 1265 */ "__10000015\0" |
18711 | 0 | /* 1276 */ "__1000015\0" |
18712 | 0 | /* 1286 */ "v14:15\0" |
18713 | 0 | /* 1293 */ "g15\0" |
18714 | 0 | /* 1297 */ "r15\0" |
18715 | 0 | /* 1301 */ "s15\0" |
18716 | 0 | /* 1305 */ "v15\0" |
18717 | 0 | /* 1309 */ "__10000025\0" |
18718 | 0 | /* 1320 */ "__1000025\0" |
18719 | 0 | /* 1330 */ "v24:25\0" |
18720 | 0 | /* 1337 */ "r25\0" |
18721 | 0 | /* 1341 */ "s25\0" |
18722 | 0 | /* 1345 */ "v25\0" |
18723 | 0 | /* 1349 */ "s35\0" |
18724 | 0 | /* 1353 */ "s45\0" |
18725 | 0 | /* 1357 */ "s55\0" |
18726 | 0 | /* 1361 */ "s65\0" |
18727 | 0 | /* 1365 */ "s75\0" |
18728 | 0 | /* 1369 */ "v4:5\0" |
18729 | 0 | /* 1374 */ "c5\0" |
18730 | 0 | /* 1377 */ "g5\0" |
18731 | 0 | /* 1380 */ "r5\0" |
18732 | 0 | /* 1383 */ "gpmucnt5\0" |
18733 | 0 | /* 1392 */ "v5\0" |
18734 | 0 | /* 1395 */ "__10000006\0" |
18735 | 0 | /* 1406 */ "__1000006\0" |
18736 | 0 | /* 1416 */ "__10000016\0" |
18737 | 0 | /* 1427 */ "__1000016\0" |
18738 | 0 | /* 1437 */ "c17:16\0" |
18739 | 0 | /* 1444 */ "g17:16\0" |
18740 | 0 | /* 1451 */ "r17:16\0" |
18741 | 0 | /* 1458 */ "s17:16\0" |
18742 | 0 | /* 1465 */ "v17:16\0" |
18743 | 0 | /* 1472 */ "v19:16\0" |
18744 | 0 | /* 1479 */ "r16\0" |
18745 | 0 | /* 1483 */ "v16\0" |
18746 | 0 | /* 1487 */ "__10000026\0" |
18747 | 0 | /* 1498 */ "__1000026\0" |
18748 | 0 | /* 1508 */ "g27:26\0" |
18749 | 0 | /* 1515 */ "r27:26\0" |
18750 | 0 | /* 1522 */ "s27:26\0" |
18751 | 0 | /* 1529 */ "v27:26\0" |
18752 | 0 | /* 1536 */ "r26\0" |
18753 | 0 | /* 1540 */ "s26\0" |
18754 | 0 | /* 1544 */ "v26\0" |
18755 | 0 | /* 1548 */ "s37:36\0" |
18756 | 0 | /* 1555 */ "s47:46\0" |
18757 | 0 | /* 1562 */ "s46\0" |
18758 | 0 | /* 1566 */ "s57:56\0" |
18759 | 0 | /* 1573 */ "s56\0" |
18760 | 0 | /* 1577 */ "s67:66\0" |
18761 | 0 | /* 1584 */ "s66\0" |
18762 | 0 | /* 1588 */ "s77:76\0" |
18763 | 0 | /* 1595 */ "s76\0" |
18764 | 0 | /* 1599 */ "c7:6\0" |
18765 | 0 | /* 1604 */ "g7:6\0" |
18766 | 0 | /* 1609 */ "r7:6\0" |
18767 | 0 | /* 1614 */ "s7:6\0" |
18768 | 0 | /* 1619 */ "v7:6\0" |
18769 | 0 | /* 1624 */ "g6\0" |
18770 | 0 | /* 1627 */ "r6\0" |
18771 | 0 | /* 1630 */ "gpmucnt6\0" |
18772 | 0 | /* 1639 */ "v6\0" |
18773 | 0 | /* 1642 */ "__10000007\0" |
18774 | 0 | /* 1653 */ "__1000007\0" |
18775 | 0 | /* 1663 */ "__10000017\0" |
18776 | 0 | /* 1674 */ "__1000017\0" |
18777 | 0 | /* 1684 */ "v16:17\0" |
18778 | 0 | /* 1691 */ "r17\0" |
18779 | 0 | /* 1695 */ "v17\0" |
18780 | 0 | /* 1699 */ "__10000027\0" |
18781 | 0 | /* 1710 */ "__1000027\0" |
18782 | 0 | /* 1720 */ "v26:27\0" |
18783 | 0 | /* 1727 */ "r27\0" |
18784 | 0 | /* 1731 */ "v27\0" |
18785 | 0 | /* 1735 */ "s47\0" |
18786 | 0 | /* 1739 */ "s57\0" |
18787 | 0 | /* 1743 */ "s67\0" |
18788 | 0 | /* 1747 */ "s77\0" |
18789 | 0 | /* 1751 */ "v6:7\0" |
18790 | 0 | /* 1756 */ "g7\0" |
18791 | 0 | /* 1759 */ "r7\0" |
18792 | 0 | /* 1762 */ "gpmucnt7\0" |
18793 | 0 | /* 1771 */ "v7\0" |
18794 | 0 | /* 1774 */ "__10000008\0" |
18795 | 0 | /* 1785 */ "__1000008\0" |
18796 | 0 | /* 1795 */ "__10000018\0" |
18797 | 0 | /* 1806 */ "__1000018\0" |
18798 | 0 | /* 1816 */ "c19:18\0" |
18799 | 0 | /* 1823 */ "g19:18\0" |
18800 | 0 | /* 1830 */ "r19:18\0" |
18801 | 0 | /* 1837 */ "s19:18\0" |
18802 | 0 | /* 1844 */ "v19:18\0" |
18803 | 0 | /* 1851 */ "r18\0" |
18804 | 0 | /* 1855 */ "v18\0" |
18805 | 0 | /* 1859 */ "__10000028\0" |
18806 | 0 | /* 1870 */ "__1000028\0" |
18807 | 0 | /* 1880 */ "v31:28\0" |
18808 | 0 | /* 1887 */ "g29:28\0" |
18809 | 0 | /* 1894 */ "r29:28\0" |
18810 | 0 | /* 1901 */ "s29:28\0" |
18811 | 0 | /* 1908 */ "v29:28\0" |
18812 | 0 | /* 1915 */ "r28\0" |
18813 | 0 | /* 1919 */ "v28\0" |
18814 | 0 | /* 1923 */ "s39:38\0" |
18815 | 0 | /* 1930 */ "s49:48\0" |
18816 | 0 | /* 1937 */ "s59:58\0" |
18817 | 0 | /* 1944 */ "s58\0" |
18818 | 0 | /* 1948 */ "s69:68\0" |
18819 | 0 | /* 1955 */ "s68\0" |
18820 | 0 | /* 1959 */ "s79:78\0" |
18821 | 0 | /* 1966 */ "s78\0" |
18822 | 0 | /* 1970 */ "v11:8\0" |
18823 | 0 | /* 1976 */ "c9:8\0" |
18824 | 0 | /* 1981 */ "g9:8\0" |
18825 | 0 | /* 1986 */ "r9:8\0" |
18826 | 0 | /* 1991 */ "s9:8\0" |
18827 | 0 | /* 1996 */ "v9:8\0" |
18828 | 0 | /* 2001 */ "c8\0" |
18829 | 0 | /* 2004 */ "g8\0" |
18830 | 0 | /* 2007 */ "r8\0" |
18831 | 0 | /* 2010 */ "v8\0" |
18832 | 0 | /* 2013 */ "__10000009\0" |
18833 | 0 | /* 2024 */ "__1000009\0" |
18834 | 0 | /* 2034 */ "__10000019\0" |
18835 | 0 | /* 2045 */ "__1000019\0" |
18836 | 0 | /* 2055 */ "v18:19\0" |
18837 | 0 | /* 2062 */ "r19\0" |
18838 | 0 | /* 2066 */ "s19\0" |
18839 | 0 | /* 2070 */ "v19\0" |
18840 | 0 | /* 2074 */ "__10000029\0" |
18841 | 0 | /* 2085 */ "__1000029\0" |
18842 | 0 | /* 2095 */ "v28:29\0" |
18843 | 0 | /* 2102 */ "r29\0" |
18844 | 0 | /* 2106 */ "v29\0" |
18845 | 0 | /* 2110 */ "s59\0" |
18846 | 0 | /* 2114 */ "s69\0" |
18847 | 0 | /* 2118 */ "s79\0" |
18848 | 0 | /* 2122 */ "__9999999\0" |
18849 | 0 | /* 2132 */ "__999999\0" |
18850 | 0 | /* 2141 */ "v8:9\0" |
18851 | 0 | /* 2146 */ "g9\0" |
18852 | 0 | /* 2149 */ "r9\0" |
18853 | 0 | /* 2152 */ "v9\0" |
18854 | 0 | /* 2155 */ "gbadva\0" |
18855 | 0 | /* 2162 */ "evb\0" |
18856 | 0 | /* 2166 */ "pc\0" |
18857 | 0 | /* 2169 */ "htid\0" |
18858 | 0 | /* 2174 */ "stid\0" |
18859 | 0 | /* 2179 */ "vid\0" |
18860 | 0 | /* 2183 */ "cfgbase\0" |
18861 | 0 | /* 2191 */ "usr.ovf\0" |
18862 | 0 | /* 2199 */ "diag\0" |
18863 | 0 | /* 2204 */ "syscfg\0" |
18864 | 0 | /* 2211 */ "pmuevtcfg\0" |
18865 | 0 | /* 2221 */ "pmucfg\0" |
18866 | 0 | /* 2228 */ "gpcyclehi\0" |
18867 | 0 | /* 2238 */ "upcyclehi\0" |
18868 | 0 | /* 2248 */ "utimerhi\0" |
18869 | 0 | /* 2257 */ "pktcounthi\0" |
18870 | 0 | /* 2268 */ "imask\0" |
18871 | 0 | /* 2274 */ "modectl\0" |
18872 | 0 | /* 2282 */ "isdben\0" |
18873 | 0 | /* 2289 */ "isdbmbxin\0" |
18874 | 0 | /* 2299 */ "gpcyclelo\0" |
18875 | 0 | /* 2309 */ "upcyclelo\0" |
18876 | 0 | /* 2319 */ "utimerlo\0" |
18877 | 0 | /* 2328 */ "pktcountlo\0" |
18878 | 0 | /* 2339 */ "ugp\0" |
18879 | 0 | /* 2343 */ "vtmp\0" |
18880 | 0 | /* 2348 */ "gosp\0" |
18881 | 0 | /* 2353 */ "ccr\0" |
18882 | 0 | /* 2357 */ "gelr\0" |
18883 | 0 | /* 2362 */ "isdbgpr\0" |
18884 | 0 | /* 2370 */ "gsr\0" |
18885 | 0 | /* 2374 */ "ssr\0" |
18886 | 0 | /* 2378 */ "usr\0" |
18887 | 0 | /* 2382 */ "framelimit\0" |
18888 | 0 | /* 2393 */ "isdbst\0" |
18889 | 0 | /* 2400 */ "isdbmbxout\0" |
18890 | 0 | /* 2411 */ "rev\0" |
18891 | 0 | /* 2415 */ "framekey\0" |
18892 | 0 | }; |
18893 | 0 | #ifdef __GNUC__ |
18894 | 0 | #pragma GCC diagnostic pop |
18895 | 0 | #endif |
18896 | |
|
18897 | 0 | static const uint16_t RegAsmOffset[] = { |
18898 | 0 | 2156, 2353, 2183, 629, 2199, 2358, 2162, 2415, 2382, 2357, 2348, 2340, 2228, 2299, |
18899 | 0 | 2370, 2169, 2268, 2282, 2362, 2289, 2400, 2393, 2274, 2166, 2229, 2300, 1816, 2257, |
18900 | 0 | 2328, 2221, 2211, 2411, 2374, 2174, 2204, 2339, 1026, 2238, 2309, 2378, 2191, 182, |
18901 | 0 | 2248, 2319, 2179, 2343, 308, 518, 337, 547, 319, 529, 1374, 2001, 361, 571, |
18902 | 0 | 279, 805, 1206, 1609, 1986, 56, 643, 1040, 1451, 1830, 117, 715, 1105, 1515, |
18903 | 0 | 1894, 196, 2155, 1226, 1377, 1624, 1756, 2004, 2146, 77, 426, 671, 890, 1061, |
18904 | 0 | 1293, 145, 470, 736, 934, 217, 489, 365, 575, 829, 972, 1232, 1383, 1630, |
18905 | 0 | 1762, 328, 538, 315, 525, 347, 557, 352, 562, 820, 963, 366, 576, 830, |
18906 | 0 | 973, 355, 565, 823, 966, 358, 568, 826, 969, 1229, 1380, 1627, 1759, 2007, |
18907 | 0 | 2149, 81, 430, 675, 894, 1065, 1297, 1479, 1691, 1851, 2062, 149, 474, 740, |
18908 | 0 | 938, 1133, 1337, 1536, 1727, 1915, 2102, 221, 493, 434, 679, 898, 1069, 1301, |
18909 | 0 | 2066, 153, 744, 942, 1137, 1341, 1540, 1349, 1159, 1353, 1562, 1735, 1170, 1357, |
18910 | 0 | 1573, 1739, 1944, 2110, 250, 501, 780, 950, 1181, 1361, 1584, 1743, 1955, 2114, |
18911 | 0 | 261, 505, 791, 954, 1192, 1365, 1595, 1747, 1966, 2118, 265, 304, 514, 350, |
18912 | 0 | 560, 374, 584, 838, 981, 1241, 1392, 1639, 1771, 2010, 2152, 85, 438, 683, |
18913 | 0 | 902, 1073, 1305, 1483, 1695, 1855, 2070, 157, 478, 748, 946, 1141, 1345, 1544, |
18914 | 0 | 1731, 1919, 2106, 225, 497, 2132, 11, 388, 598, 852, 995, 1255, 1406, 1653, |
18915 | 0 | 1785, 2024, 32, 409, 619, 873, 1016, 1276, 1427, 1674, 1806, 2045, 100, 453, |
18916 | 0 | 698, 917, 1088, 1320, 1498, 1710, 1870, 2085, 172, 2122, 0, 377, 587, 841, |
18917 | 0 | 984, 1244, 1395, 1642, 1774, 2013, 21, 398, 608, 862, 1005, 1265, 1416, 1663, |
18918 | 0 | 1795, 2034, 89, 442, 687, 906, 1077, 1309, 1487, 1699, 1859, 2074, 161, 299, |
18919 | 0 | 1221, 1970, 664, 1472, 138, 1126, 1880, 289, 815, 1216, 1619, 1996, 70, 657, |
18920 | 0 | 1054, 1465, 1844, 131, 729, 1119, 1529, 1908, 210, 509, 958, 1369, 1751, 2141, |
18921 | 0 | 419, 883, 1286, 1684, 2055, 463, 927, 1330, 1720, 2095, 482, 269, 795, 1196, |
18922 | 0 | 1599, 1976, 42, 1437, 274, 800, 1201, 1604, 1981, 49, 636, 1033, 1444, 1823, |
18923 | 0 | 110, 708, 1098, 1508, 1887, 189, 294, 810, 1211, 1614, 1991, 63, 650, 1047, |
18924 | 0 | 1458, 1837, 124, 722, 1112, 1522, 1901, 203, 752, 1145, 1548, 1923, 229, 759, |
18925 | 0 | 1152, 1555, 1930, 236, 766, 1163, 1566, 1937, 243, 773, 1174, 1577, 1948, 254, |
18926 | 0 | 784, 1185, 1588, 1959, 284, |
18927 | 0 | }; |
18928 | |
|
18929 | 0 | assert (*(AsmStrs+RegAsmOffset[RegNo-1]) && |
18930 | 0 | "Invalid alt name index for register!"); |
18931 | 0 | return AsmStrs+RegAsmOffset[RegNo-1]; |
18932 | 0 | } |
18933 | | |
18934 | | #ifdef PRINT_ALIAS_INSTR |
18935 | | #undef PRINT_ALIAS_INSTR |
18936 | | |
18937 | | bool HexagonInstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS) { |
18938 | | static const PatternsForOpcode OpToPatterns[] = { |
18939 | | {Hexagon::A2_andir, 0, 1 }, |
18940 | | {Hexagon::A2_paddif, 1, 1 }, |
18941 | | {Hexagon::A2_paddifnew, 2, 1 }, |
18942 | | {Hexagon::A2_paddit, 3, 1 }, |
18943 | | {Hexagon::A2_padditnew, 4, 1 }, |
18944 | | {Hexagon::A2_subri, 5, 2 }, |
18945 | | {Hexagon::A2_vaddub, 7, 1 }, |
18946 | | {Hexagon::A2_vsubub, 8, 1 }, |
18947 | | {Hexagon::C2_cmpgt, 9, 1 }, |
18948 | | {Hexagon::C2_cmpgtu, 10, 1 }, |
18949 | | {Hexagon::C2_or, 11, 1 }, |
18950 | | {Hexagon::J2_jumpf, 12, 1 }, |
18951 | | {Hexagon::J2_jumprf, 13, 1 }, |
18952 | | {Hexagon::J2_jumprt, 14, 1 }, |
18953 | | {Hexagon::J2_jumpt, 15, 1 }, |
18954 | | {Hexagon::J2_trap1, 16, 1 }, |
18955 | | {Hexagon::L2_deallocframe, 17, 1 }, |
18956 | | {Hexagon::L2_loadalignb_io, 18, 1 }, |
18957 | | {Hexagon::L2_loadalignh_io, 19, 1 }, |
18958 | | {Hexagon::L2_loadbsw2_io, 20, 1 }, |
18959 | | {Hexagon::L2_loadbsw4_io, 21, 1 }, |
18960 | | {Hexagon::L2_loadbzw2_io, 22, 1 }, |
18961 | | {Hexagon::L2_loadbzw4_io, 23, 1 }, |
18962 | | {Hexagon::L2_loadrb_io, 24, 1 }, |
18963 | | {Hexagon::L2_loadrd_io, 25, 1 }, |
18964 | | {Hexagon::L2_loadrh_io, 26, 1 }, |
18965 | | {Hexagon::L2_loadri_io, 27, 1 }, |
18966 | | {Hexagon::L2_loadrub_io, 28, 1 }, |
18967 | | {Hexagon::L2_loadruh_io, 29, 1 }, |
18968 | | {Hexagon::L2_ploadrbf_io, 30, 1 }, |
18969 | | {Hexagon::L2_ploadrbfnew_io, 31, 1 }, |
18970 | | {Hexagon::L2_ploadrbt_io, 32, 1 }, |
18971 | | {Hexagon::L2_ploadrbtnew_io, 33, 1 }, |
18972 | | {Hexagon::L2_ploadrdf_io, 34, 1 }, |
18973 | | {Hexagon::L2_ploadrdfnew_io, 35, 1 }, |
18974 | | {Hexagon::L2_ploadrdt_io, 36, 1 }, |
18975 | | {Hexagon::L2_ploadrdtnew_io, 37, 1 }, |
18976 | | {Hexagon::L2_ploadrhf_io, 38, 1 }, |
18977 | | {Hexagon::L2_ploadrhfnew_io, 39, 1 }, |
18978 | | {Hexagon::L2_ploadrht_io, 40, 1 }, |
18979 | | {Hexagon::L2_ploadrhtnew_io, 41, 1 }, |
18980 | | {Hexagon::L2_ploadrif_io, 42, 1 }, |
18981 | | {Hexagon::L2_ploadrifnew_io, 43, 1 }, |
18982 | | {Hexagon::L2_ploadrit_io, 44, 1 }, |
18983 | | {Hexagon::L2_ploadritnew_io, 45, 1 }, |
18984 | | {Hexagon::L2_ploadrubf_io, 46, 1 }, |
18985 | | {Hexagon::L2_ploadrubfnew_io, 47, 1 }, |
18986 | | {Hexagon::L2_ploadrubt_io, 48, 1 }, |
18987 | | {Hexagon::L2_ploadrubtnew_io, 49, 1 }, |
18988 | | {Hexagon::L2_ploadruhf_io, 50, 1 }, |
18989 | | {Hexagon::L2_ploadruhfnew_io, 51, 1 }, |
18990 | | {Hexagon::L2_ploadruht_io, 52, 1 }, |
18991 | | {Hexagon::L2_ploadruhtnew_io, 53, 1 }, |
18992 | | {Hexagon::L4_add_memopb_io, 54, 1 }, |
18993 | | {Hexagon::L4_add_memoph_io, 55, 1 }, |
18994 | | {Hexagon::L4_add_memopw_io, 56, 1 }, |
18995 | | {Hexagon::L4_and_memopb_io, 57, 1 }, |
18996 | | {Hexagon::L4_and_memoph_io, 58, 1 }, |
18997 | | {Hexagon::L4_and_memopw_io, 59, 1 }, |
18998 | | {Hexagon::L4_iadd_memopb_io, 60, 1 }, |
18999 | | {Hexagon::L4_iadd_memoph_io, 61, 1 }, |
19000 | | {Hexagon::L4_iadd_memopw_io, 62, 1 }, |
19001 | | {Hexagon::L4_iand_memopb_io, 63, 1 }, |
19002 | | {Hexagon::L4_iand_memoph_io, 64, 1 }, |
19003 | | {Hexagon::L4_iand_memopw_io, 65, 1 }, |
19004 | | {Hexagon::L4_ior_memopb_io, 66, 1 }, |
19005 | | {Hexagon::L4_ior_memoph_io, 67, 1 }, |
19006 | | {Hexagon::L4_ior_memopw_io, 68, 1 }, |
19007 | | {Hexagon::L4_isub_memopb_io, 69, 1 }, |
19008 | | {Hexagon::L4_isub_memoph_io, 70, 1 }, |
19009 | | {Hexagon::L4_isub_memopw_io, 71, 1 }, |
19010 | | {Hexagon::L4_or_memopb_io, 72, 1 }, |
19011 | | {Hexagon::L4_or_memoph_io, 73, 1 }, |
19012 | | {Hexagon::L4_or_memopw_io, 74, 1 }, |
19013 | | {Hexagon::L4_return, 75, 1 }, |
19014 | | {Hexagon::L4_return_f, 76, 1 }, |
19015 | | {Hexagon::L4_return_fnew_pnt, 77, 1 }, |
19016 | | {Hexagon::L4_return_fnew_pt, 78, 1 }, |
19017 | | {Hexagon::L4_return_t, 79, 1 }, |
19018 | | {Hexagon::L4_return_tnew_pnt, 80, 1 }, |
19019 | | {Hexagon::L4_return_tnew_pt, 81, 1 }, |
19020 | | {Hexagon::L4_sub_memopb_io, 82, 1 }, |
19021 | | {Hexagon::L4_sub_memoph_io, 83, 1 }, |
19022 | | {Hexagon::L4_sub_memopw_io, 84, 1 }, |
19023 | | {Hexagon::M2_mpyi, 85, 1 }, |
19024 | | {Hexagon::M7_dcmpyrwc, 86, 1 }, |
19025 | | {Hexagon::M7_dcmpyrwc_acc, 87, 1 }, |
19026 | | {Hexagon::S2_allocframe, 88, 1 }, |
19027 | | {Hexagon::S2_pstorerbf_io, 89, 1 }, |
19028 | | {Hexagon::S2_pstorerbnewf_io, 90, 1 }, |
19029 | | {Hexagon::S2_pstorerbnewt_io, 91, 1 }, |
19030 | | {Hexagon::S2_pstorerbt_io, 92, 1 }, |
19031 | | {Hexagon::S2_pstorerdf_io, 93, 1 }, |
19032 | | {Hexagon::S2_pstorerdt_io, 94, 1 }, |
19033 | | {Hexagon::S2_pstorerff_io, 95, 1 }, |
19034 | | {Hexagon::S2_pstorerft_io, 96, 1 }, |
19035 | | {Hexagon::S2_pstorerhf_io, 97, 1 }, |
19036 | | {Hexagon::S2_pstorerhnewf_io, 98, 1 }, |
19037 | | {Hexagon::S2_pstorerhnewt_io, 99, 1 }, |
19038 | | {Hexagon::S2_pstorerht_io, 100, 1 }, |
19039 | | {Hexagon::S2_pstorerif_io, 101, 1 }, |
19040 | | {Hexagon::S2_pstorerinewf_io, 102, 1 }, |
19041 | | {Hexagon::S2_pstorerinewt_io, 103, 1 }, |
19042 | | {Hexagon::S2_pstorerit_io, 104, 1 }, |
19043 | | {Hexagon::S2_storerb_io, 105, 1 }, |
19044 | | {Hexagon::S2_storerbnew_io, 106, 1 }, |
19045 | | {Hexagon::S2_storerd_io, 107, 1 }, |
19046 | | {Hexagon::S2_storerf_io, 108, 1 }, |
19047 | | {Hexagon::S2_storerh_io, 109, 1 }, |
19048 | | {Hexagon::S2_storerhnew_io, 110, 1 }, |
19049 | | {Hexagon::S2_storeri_io, 111, 1 }, |
19050 | | {Hexagon::S2_storerinew_io, 112, 1 }, |
19051 | | {Hexagon::S2_tableidxb, 113, 1 }, |
19052 | | {Hexagon::S4_pstorerbfnew_io, 114, 1 }, |
19053 | | {Hexagon::S4_pstorerbnewfnew_io, 115, 1 }, |
19054 | | {Hexagon::S4_pstorerbnewtnew_io, 116, 1 }, |
19055 | | {Hexagon::S4_pstorerbtnew_io, 117, 1 }, |
19056 | | {Hexagon::S4_pstorerdfnew_io, 118, 1 }, |
19057 | | {Hexagon::S4_pstorerdtnew_io, 119, 1 }, |
19058 | | {Hexagon::S4_pstorerffnew_io, 120, 1 }, |
19059 | | {Hexagon::S4_pstorerftnew_io, 121, 1 }, |
19060 | | {Hexagon::S4_pstorerhfnew_io, 122, 1 }, |
19061 | | {Hexagon::S4_pstorerhnewfnew_io, 123, 1 }, |
19062 | | {Hexagon::S4_pstorerhnewtnew_io, 124, 1 }, |
19063 | | {Hexagon::S4_pstorerhtnew_io, 125, 1 }, |
19064 | | {Hexagon::S4_pstorerifnew_io, 126, 1 }, |
19065 | | {Hexagon::S4_pstorerinewfnew_io, 127, 1 }, |
19066 | | {Hexagon::S4_pstorerinewtnew_io, 128, 1 }, |
19067 | | {Hexagon::S4_pstoreritnew_io, 129, 1 }, |
19068 | | {Hexagon::S4_storeirb_io, 130, 1 }, |
19069 | | {Hexagon::S4_storeirbf_io, 131, 1 }, |
19070 | | {Hexagon::S4_storeirbfnew_io, 132, 1 }, |
19071 | | {Hexagon::S4_storeirbt_io, 133, 1 }, |
19072 | | {Hexagon::S4_storeirbtnew_io, 134, 1 }, |
19073 | | {Hexagon::S4_storeirh_io, 135, 1 }, |
19074 | | {Hexagon::S4_storeirhf_io, 136, 1 }, |
19075 | | {Hexagon::S4_storeirhfnew_io, 137, 1 }, |
19076 | | {Hexagon::S4_storeirht_io, 138, 1 }, |
19077 | | {Hexagon::S4_storeirhtnew_io, 139, 1 }, |
19078 | | {Hexagon::S4_storeiri_io, 140, 1 }, |
19079 | | {Hexagon::S4_storeirif_io, 141, 1 }, |
19080 | | {Hexagon::S4_storeirifnew_io, 142, 1 }, |
19081 | | {Hexagon::S4_storeirit_io, 143, 1 }, |
19082 | | {Hexagon::S4_storeiritnew_io, 144, 1 }, |
19083 | | {Hexagon::V6_extractw, 145, 1 }, |
19084 | | {Hexagon::V6_v6mpyhubs10, 146, 1 }, |
19085 | | {Hexagon::V6_v6mpyvubs10, 147, 1 }, |
19086 | | {Hexagon::V6_vL32Ub_ai, 148, 1 }, |
19087 | | {Hexagon::V6_vL32b_ai, 149, 1 }, |
19088 | | {Hexagon::V6_vL32b_cur_npred_pi, 150, 1 }, |
19089 | | {Hexagon::V6_vL32b_cur_pred_pi, 151, 1 }, |
19090 | | {Hexagon::V6_vL32b_npred_ai, 152, 1 }, |
19091 | | {Hexagon::V6_vL32b_npred_pi, 153, 1 }, |
19092 | | {Hexagon::V6_vL32b_nt_ai, 154, 1 }, |
19093 | | {Hexagon::V6_vL32b_nt_cur_npred_pi, 155, 1 }, |
19094 | | {Hexagon::V6_vL32b_nt_cur_pred_pi, 156, 1 }, |
19095 | | {Hexagon::V6_vL32b_nt_npred_ai, 157, 1 }, |
19096 | | {Hexagon::V6_vL32b_nt_npred_pi, 158, 1 }, |
19097 | | {Hexagon::V6_vL32b_nt_pred_ai, 159, 1 }, |
19098 | | {Hexagon::V6_vL32b_nt_tmp_pred_ai, 160, 1 }, |
19099 | | {Hexagon::V6_vL32b_pred_ai, 161, 1 }, |
19100 | | {Hexagon::V6_vL32b_tmp_pred_ai, 162, 1 }, |
19101 | | {Hexagon::V6_vS32Ub_ai, 163, 1 }, |
19102 | | {Hexagon::V6_vS32Ub_npred_ai, 164, 1 }, |
19103 | | {Hexagon::V6_vS32Ub_pred_ai, 165, 1 }, |
19104 | | {Hexagon::V6_vS32b_ai, 166, 1 }, |
19105 | | {Hexagon::V6_vS32b_new_ai, 167, 1 }, |
19106 | | {Hexagon::V6_vS32b_npred_ai, 168, 1 }, |
19107 | | {Hexagon::V6_vS32b_nqpred_ai, 169, 1 }, |
19108 | | {Hexagon::V6_vS32b_nt_ai, 170, 1 }, |
19109 | | {Hexagon::V6_vS32b_nt_new_ai, 171, 1 }, |
19110 | | {Hexagon::V6_vS32b_nt_npred_ai, 172, 1 }, |
19111 | | {Hexagon::V6_vS32b_nt_nqpred_ai, 173, 1 }, |
19112 | | {Hexagon::V6_vS32b_nt_pred_ai, 174, 1 }, |
19113 | | {Hexagon::V6_vS32b_nt_qpred_ai, 175, 1 }, |
19114 | | {Hexagon::V6_vS32b_pred_ai, 176, 1 }, |
19115 | | {Hexagon::V6_vS32b_qpred_ai, 177, 1 }, |
19116 | | {Hexagon::V6_vabsb_sat, 178, 1 }, |
19117 | | {Hexagon::V6_vabsdiffh, 179, 1 }, |
19118 | | {Hexagon::V6_vabsdiffub, 180, 1 }, |
19119 | | {Hexagon::V6_vabsdiffuh, 181, 1 }, |
19120 | | {Hexagon::V6_vabsdiffw, 182, 1 }, |
19121 | | {Hexagon::V6_vabsh_sat, 183, 1 }, |
19122 | | {Hexagon::V6_vabsw_sat, 184, 1 }, |
19123 | | {Hexagon::V6_vaddb, 185, 1 }, |
19124 | | {Hexagon::V6_vaddb_dv, 186, 1 }, |
19125 | | {Hexagon::V6_vaddbnq, 187, 1 }, |
19126 | | {Hexagon::V6_vaddbq, 188, 1 }, |
19127 | | {Hexagon::V6_vaddbsat, 189, 1 }, |
19128 | | {Hexagon::V6_vaddbsat_dv, 190, 1 }, |
19129 | | {Hexagon::V6_vaddh, 191, 1 }, |
19130 | | {Hexagon::V6_vaddh_dv, 192, 1 }, |
19131 | | {Hexagon::V6_vaddhnq, 193, 1 }, |
19132 | | {Hexagon::V6_vaddhq, 194, 1 }, |
19133 | | {Hexagon::V6_vaddhsat, 195, 1 }, |
19134 | | {Hexagon::V6_vaddhsat_dv, 196, 1 }, |
19135 | | {Hexagon::V6_vaddhw, 197, 1 }, |
19136 | | {Hexagon::V6_vaddhw_acc, 198, 1 }, |
19137 | | {Hexagon::V6_vaddubh, 199, 1 }, |
19138 | | {Hexagon::V6_vaddubh_acc, 200, 1 }, |
19139 | | {Hexagon::V6_vaddubsat, 201, 1 }, |
19140 | | {Hexagon::V6_vaddubsat_dv, 202, 1 }, |
19141 | | {Hexagon::V6_vadduhsat, 203, 1 }, |
19142 | | {Hexagon::V6_vadduhsat_dv, 204, 1 }, |
19143 | | {Hexagon::V6_vadduhw, 205, 1 }, |
19144 | | {Hexagon::V6_vadduhw_acc, 206, 1 }, |
19145 | | {Hexagon::V6_vadduwsat, 207, 1 }, |
19146 | | {Hexagon::V6_vadduwsat_dv, 208, 1 }, |
19147 | | {Hexagon::V6_vaddw, 209, 1 }, |
19148 | | {Hexagon::V6_vaddw_dv, 210, 1 }, |
19149 | | {Hexagon::V6_vaddwnq, 211, 1 }, |
19150 | | {Hexagon::V6_vaddwq, 212, 1 }, |
19151 | | {Hexagon::V6_vaddwsat, 213, 1 }, |
19152 | | {Hexagon::V6_vaddwsat_dv, 214, 1 }, |
19153 | | {Hexagon::V6_vandnqrt, 215, 1 }, |
19154 | | {Hexagon::V6_vandnqrt_acc, 216, 1 }, |
19155 | | {Hexagon::V6_vandqrt, 217, 1 }, |
19156 | | {Hexagon::V6_vandqrt_acc, 218, 1 }, |
19157 | | {Hexagon::V6_vandvrt, 219, 1 }, |
19158 | | {Hexagon::V6_vandvrt_acc, 220, 1 }, |
19159 | | {Hexagon::V6_vaslh, 221, 1 }, |
19160 | | {Hexagon::V6_vaslh_acc, 222, 1 }, |
19161 | | {Hexagon::V6_vaslhv, 223, 1 }, |
19162 | | {Hexagon::V6_vaslw, 224, 1 }, |
19163 | | {Hexagon::V6_vaslw_acc, 225, 1 }, |
19164 | | {Hexagon::V6_vaslwv, 226, 1 }, |
19165 | | {Hexagon::V6_vasr_into, 227, 1 }, |
19166 | | {Hexagon::V6_vasrh, 228, 1 }, |
19167 | | {Hexagon::V6_vasrh_acc, 229, 1 }, |
19168 | | {Hexagon::V6_vasrhv, 230, 1 }, |
19169 | | {Hexagon::V6_vasrw, 231, 1 }, |
19170 | | {Hexagon::V6_vasrw_acc, 232, 1 }, |
19171 | | {Hexagon::V6_vasrwv, 233, 1 }, |
19172 | | {Hexagon::V6_vavgb, 234, 1 }, |
19173 | | {Hexagon::V6_vavgbrnd, 235, 1 }, |
19174 | | {Hexagon::V6_vavgh, 236, 1 }, |
19175 | | {Hexagon::V6_vavghrnd, 237, 1 }, |
19176 | | {Hexagon::V6_vavgub, 238, 1 }, |
19177 | | {Hexagon::V6_vavgubrnd, 239, 1 }, |
19178 | | {Hexagon::V6_vavguh, 240, 1 }, |
19179 | | {Hexagon::V6_vavguhrnd, 241, 1 }, |
19180 | | {Hexagon::V6_vavguw, 242, 1 }, |
19181 | | {Hexagon::V6_vavguwrnd, 243, 1 }, |
19182 | | {Hexagon::V6_vavgw, 244, 1 }, |
19183 | | {Hexagon::V6_vavgwrnd, 245, 1 }, |
19184 | | {Hexagon::V6_vcl0h, 246, 1 }, |
19185 | | {Hexagon::V6_vcl0w, 247, 1 }, |
19186 | | {Hexagon::V6_vdealb, 248, 1 }, |
19187 | | {Hexagon::V6_vdealb4w, 249, 1 }, |
19188 | | {Hexagon::V6_vdealh, 250, 1 }, |
19189 | | {Hexagon::V6_vdmpybus, 251, 1 }, |
19190 | | {Hexagon::V6_vdmpybus_acc, 252, 1 }, |
19191 | | {Hexagon::V6_vdmpybus_dv, 253, 1 }, |
19192 | | {Hexagon::V6_vdmpybus_dv_acc, 254, 1 }, |
19193 | | {Hexagon::V6_vdmpyhb, 255, 1 }, |
19194 | | {Hexagon::V6_vdmpyhb_acc, 256, 1 }, |
19195 | | {Hexagon::V6_vdmpyhb_dv, 257, 1 }, |
19196 | | {Hexagon::V6_vdmpyhb_dv_acc, 258, 1 }, |
19197 | | {Hexagon::V6_vdmpyhisat, 259, 1 }, |
19198 | | {Hexagon::V6_vdmpyhisat_acc, 260, 1 }, |
19199 | | {Hexagon::V6_vdmpyhsat, 261, 1 }, |
19200 | | {Hexagon::V6_vdmpyhsat_acc, 262, 1 }, |
19201 | | {Hexagon::V6_vdmpyhsuisat, 263, 1 }, |
19202 | | {Hexagon::V6_vdmpyhsuisat_acc, 264, 1 }, |
19203 | | {Hexagon::V6_vdmpyhsusat, 265, 1 }, |
19204 | | {Hexagon::V6_vdmpyhsusat_acc, 266, 1 }, |
19205 | | {Hexagon::V6_vdmpyhvsat, 267, 1 }, |
19206 | | {Hexagon::V6_vdmpyhvsat_acc, 268, 1 }, |
19207 | | {Hexagon::V6_vdsaduh, 269, 1 }, |
19208 | | {Hexagon::V6_vdsaduh_acc, 270, 1 }, |
19209 | | {Hexagon::V6_veqb, 271, 1 }, |
19210 | | {Hexagon::V6_veqb_and, 272, 1 }, |
19211 | | {Hexagon::V6_veqb_or, 273, 1 }, |
19212 | | {Hexagon::V6_veqb_xor, 274, 1 }, |
19213 | | {Hexagon::V6_veqh, 275, 1 }, |
19214 | | {Hexagon::V6_veqh_and, 276, 1 }, |
19215 | | {Hexagon::V6_veqh_or, 277, 1 }, |
19216 | | {Hexagon::V6_veqh_xor, 278, 1 }, |
19217 | | {Hexagon::V6_veqw, 279, 1 }, |
19218 | | {Hexagon::V6_veqw_and, 280, 1 }, |
19219 | | {Hexagon::V6_veqw_or, 281, 1 }, |
19220 | | {Hexagon::V6_veqw_xor, 282, 1 }, |
19221 | | {Hexagon::V6_vlsrh, 283, 1 }, |
19222 | | {Hexagon::V6_vlsrhv, 284, 1 }, |
19223 | | {Hexagon::V6_vlsrw, 285, 1 }, |
19224 | | {Hexagon::V6_vlsrwv, 286, 1 }, |
19225 | | {Hexagon::V6_vmaxb, 287, 1 }, |
19226 | | {Hexagon::V6_vmaxh, 288, 1 }, |
19227 | | {Hexagon::V6_vmaxub, 289, 1 }, |
19228 | | {Hexagon::V6_vmaxuh, 290, 1 }, |
19229 | | {Hexagon::V6_vmaxw, 291, 1 }, |
19230 | | {Hexagon::V6_vminb, 292, 1 }, |
19231 | | {Hexagon::V6_vminh, 293, 1 }, |
19232 | | {Hexagon::V6_vminub, 294, 1 }, |
19233 | | {Hexagon::V6_vminuh, 295, 1 }, |
19234 | | {Hexagon::V6_vminw, 296, 1 }, |
19235 | | {Hexagon::V6_vmpabus, 297, 1 }, |
19236 | | {Hexagon::V6_vmpabus_acc, 298, 1 }, |
19237 | | {Hexagon::V6_vmpabusv, 299, 1 }, |
19238 | | {Hexagon::V6_vmpabuu, 300, 1 }, |
19239 | | {Hexagon::V6_vmpabuu_acc, 301, 1 }, |
19240 | | {Hexagon::V6_vmpabuuv, 302, 1 }, |
19241 | | {Hexagon::V6_vmpahb, 303, 1 }, |
19242 | | {Hexagon::V6_vmpahb_acc, 304, 1 }, |
19243 | | {Hexagon::V6_vmpauhb, 305, 1 }, |
19244 | | {Hexagon::V6_vmpauhb_acc, 306, 1 }, |
19245 | | {Hexagon::V6_vmpybus, 307, 1 }, |
19246 | | {Hexagon::V6_vmpybus_acc, 308, 1 }, |
19247 | | {Hexagon::V6_vmpybusv, 309, 1 }, |
19248 | | {Hexagon::V6_vmpybusv_acc, 310, 1 }, |
19249 | | {Hexagon::V6_vmpybv, 311, 1 }, |
19250 | | {Hexagon::V6_vmpybv_acc, 312, 1 }, |
19251 | | {Hexagon::V6_vmpyewuh, 313, 1 }, |
19252 | | {Hexagon::V6_vmpyh, 314, 1 }, |
19253 | | {Hexagon::V6_vmpyh_acc, 315, 1 }, |
19254 | | {Hexagon::V6_vmpyhsat_acc, 316, 1 }, |
19255 | | {Hexagon::V6_vmpyhsrs, 317, 1 }, |
19256 | | {Hexagon::V6_vmpyhss, 318, 1 }, |
19257 | | {Hexagon::V6_vmpyhus, 319, 1 }, |
19258 | | {Hexagon::V6_vmpyhus_acc, 320, 1 }, |
19259 | | {Hexagon::V6_vmpyhv, 321, 1 }, |
19260 | | {Hexagon::V6_vmpyhv_acc, 322, 1 }, |
19261 | | {Hexagon::V6_vmpyhvsrs, 323, 1 }, |
19262 | | {Hexagon::V6_vmpyiewh_acc, 324, 1 }, |
19263 | | {Hexagon::V6_vmpyiewuh, 325, 1 }, |
19264 | | {Hexagon::V6_vmpyiewuh_acc, 326, 1 }, |
19265 | | {Hexagon::V6_vmpyih, 327, 1 }, |
19266 | | {Hexagon::V6_vmpyih_acc, 328, 1 }, |
19267 | | {Hexagon::V6_vmpyihb, 329, 1 }, |
19268 | | {Hexagon::V6_vmpyihb_acc, 330, 1 }, |
19269 | | {Hexagon::V6_vmpyiowh, 331, 1 }, |
19270 | | {Hexagon::V6_vmpyiwb, 332, 1 }, |
19271 | | {Hexagon::V6_vmpyiwb_acc, 333, 1 }, |
19272 | | {Hexagon::V6_vmpyiwh, 334, 1 }, |
19273 | | {Hexagon::V6_vmpyiwh_acc, 335, 1 }, |
19274 | | {Hexagon::V6_vmpyiwub, 336, 1 }, |
19275 | | {Hexagon::V6_vmpyiwub_acc, 337, 1 }, |
19276 | | {Hexagon::V6_vmpyowh, 338, 1 }, |
19277 | | {Hexagon::V6_vmpyowh_rnd, 339, 1 }, |
19278 | | {Hexagon::V6_vmpyub, 340, 1 }, |
19279 | | {Hexagon::V6_vmpyub_acc, 341, 1 }, |
19280 | | {Hexagon::V6_vmpyubv, 342, 1 }, |
19281 | | {Hexagon::V6_vmpyubv_acc, 343, 1 }, |
19282 | | {Hexagon::V6_vmpyuh, 344, 1 }, |
19283 | | {Hexagon::V6_vmpyuh_acc, 345, 1 }, |
19284 | | {Hexagon::V6_vmpyuhv, 346, 1 }, |
19285 | | {Hexagon::V6_vmpyuhv_acc, 347, 1 }, |
19286 | | {Hexagon::V6_vnavgb, 348, 1 }, |
19287 | | {Hexagon::V6_vnavgh, 349, 1 }, |
19288 | | {Hexagon::V6_vnavgub, 350, 1 }, |
19289 | | {Hexagon::V6_vnavgw, 351, 1 }, |
19290 | | {Hexagon::V6_vnormamth, 352, 1 }, |
19291 | | {Hexagon::V6_vnormamtw, 353, 1 }, |
19292 | | {Hexagon::V6_vpackeb, 354, 1 }, |
19293 | | {Hexagon::V6_vpackeh, 355, 1 }, |
19294 | | {Hexagon::V6_vpackhb_sat, 356, 1 }, |
19295 | | {Hexagon::V6_vpackhub_sat, 357, 1 }, |
19296 | | {Hexagon::V6_vpackob, 358, 1 }, |
19297 | | {Hexagon::V6_vpackoh, 359, 1 }, |
19298 | | {Hexagon::V6_vpackwh_sat, 360, 1 }, |
19299 | | {Hexagon::V6_vpackwuh_sat, 361, 1 }, |
19300 | | {Hexagon::V6_vpopcounth, 362, 1 }, |
19301 | | {Hexagon::V6_vrmpybub_rtt, 363, 1 }, |
19302 | | {Hexagon::V6_vrmpybub_rtt_acc, 364, 1 }, |
19303 | | {Hexagon::V6_vrmpybus, 365, 1 }, |
19304 | | {Hexagon::V6_vrmpybus_acc, 366, 1 }, |
19305 | | {Hexagon::V6_vrmpybusi, 367, 1 }, |
19306 | | {Hexagon::V6_vrmpybusi_acc, 368, 1 }, |
19307 | | {Hexagon::V6_vrmpybusv, 369, 1 }, |
19308 | | {Hexagon::V6_vrmpybusv_acc, 370, 1 }, |
19309 | | {Hexagon::V6_vrmpybv, 371, 1 }, |
19310 | | {Hexagon::V6_vrmpybv_acc, 372, 1 }, |
19311 | | {Hexagon::V6_vrmpyub, 373, 1 }, |
19312 | | {Hexagon::V6_vrmpyub_acc, 374, 1 }, |
19313 | | {Hexagon::V6_vrmpyub_rtt, 375, 1 }, |
19314 | | {Hexagon::V6_vrmpyub_rtt_acc, 376, 1 }, |
19315 | | {Hexagon::V6_vrmpyubi, 377, 1 }, |
19316 | | {Hexagon::V6_vrmpyubi_acc, 378, 1 }, |
19317 | | {Hexagon::V6_vrmpyubv, 379, 1 }, |
19318 | | {Hexagon::V6_vrmpyubv_acc, 380, 1 }, |
19319 | | {Hexagon::V6_vrotr, 381, 1 }, |
19320 | | {Hexagon::V6_vroundhb, 382, 1 }, |
19321 | | {Hexagon::V6_vroundhub, 383, 1 }, |
19322 | | {Hexagon::V6_vrounduhub, 384, 1 }, |
19323 | | {Hexagon::V6_vrounduwuh, 385, 1 }, |
19324 | | {Hexagon::V6_vroundwh, 386, 1 }, |
19325 | | {Hexagon::V6_vroundwuh, 387, 1 }, |
19326 | | {Hexagon::V6_vrsadubi, 388, 1 }, |
19327 | | {Hexagon::V6_vrsadubi_acc, 389, 1 }, |
19328 | | {Hexagon::V6_vsathub, 390, 1 }, |
19329 | | {Hexagon::V6_vsatuwuh, 391, 1 }, |
19330 | | {Hexagon::V6_vsatwh, 392, 1 }, |
19331 | | {Hexagon::V6_vsb, 393, 1 }, |
19332 | | {Hexagon::V6_vscattermh, 394, 1 }, |
19333 | | {Hexagon::V6_vscattermh_add, 395, 1 }, |
19334 | | {Hexagon::V6_vscattermhq, 396, 1 }, |
19335 | | {Hexagon::V6_vscattermhw, 397, 1 }, |
19336 | | {Hexagon::V6_vscattermhw_add, 398, 1 }, |
19337 | | {Hexagon::V6_vscattermhwq, 399, 1 }, |
19338 | | {Hexagon::V6_vscattermw, 400, 1 }, |
19339 | | {Hexagon::V6_vscattermw_add, 401, 1 }, |
19340 | | {Hexagon::V6_vscattermwq, 402, 1 }, |
19341 | | {Hexagon::V6_vsh, 403, 1 }, |
19342 | | {Hexagon::V6_vshufeh, 404, 1 }, |
19343 | | {Hexagon::V6_vshuff, 405, 1 }, |
19344 | | {Hexagon::V6_vshuffb, 406, 1 }, |
19345 | | {Hexagon::V6_vshuffeb, 407, 1 }, |
19346 | | {Hexagon::V6_vshuffh, 408, 1 }, |
19347 | | {Hexagon::V6_vshuffob, 409, 1 }, |
19348 | | {Hexagon::V6_vshufoeb, 410, 1 }, |
19349 | | {Hexagon::V6_vshufoeh, 411, 1 }, |
19350 | | {Hexagon::V6_vshufoh, 412, 1 }, |
19351 | | {Hexagon::V6_vsubb, 413, 1 }, |
19352 | | {Hexagon::V6_vsubb_dv, 414, 1 }, |
19353 | | {Hexagon::V6_vsubbnq, 415, 1 }, |
19354 | | {Hexagon::V6_vsubbq, 416, 1 }, |
19355 | | {Hexagon::V6_vsubbsat, 417, 1 }, |
19356 | | {Hexagon::V6_vsubbsat_dv, 418, 1 }, |
19357 | | {Hexagon::V6_vsubh, 419, 1 }, |
19358 | | {Hexagon::V6_vsubh_dv, 420, 1 }, |
19359 | | {Hexagon::V6_vsubhnq, 421, 1 }, |
19360 | | {Hexagon::V6_vsubhq, 422, 1 }, |
19361 | | {Hexagon::V6_vsubhsat, 423, 1 }, |
19362 | | {Hexagon::V6_vsubhsat_dv, 424, 1 }, |
19363 | | {Hexagon::V6_vsubhw, 425, 1 }, |
19364 | | {Hexagon::V6_vsububh, 426, 1 }, |
19365 | | {Hexagon::V6_vsububsat, 427, 1 }, |
19366 | | {Hexagon::V6_vsububsat_dv, 428, 1 }, |
19367 | | {Hexagon::V6_vsubuhsat, 429, 1 }, |
19368 | | {Hexagon::V6_vsubuhsat_dv, 430, 1 }, |
19369 | | {Hexagon::V6_vsubuhw, 431, 1 }, |
19370 | | {Hexagon::V6_vsubuwsat, 432, 1 }, |
19371 | | {Hexagon::V6_vsubuwsat_dv, 433, 1 }, |
19372 | | {Hexagon::V6_vsubw, 434, 1 }, |
19373 | | {Hexagon::V6_vsubw_dv, 435, 2 }, |
19374 | | {Hexagon::V6_vsubwnq, 437, 1 }, |
19375 | | {Hexagon::V6_vsubwq, 438, 1 }, |
19376 | | {Hexagon::V6_vsubwsat, 439, 1 }, |
19377 | | {Hexagon::V6_vsubwsat_dv, 440, 1 }, |
19378 | | {Hexagon::V6_vtmpyb, 441, 1 }, |
19379 | | {Hexagon::V6_vtmpyb_acc, 442, 1 }, |
19380 | | {Hexagon::V6_vtmpybus, 443, 1 }, |
19381 | | {Hexagon::V6_vtmpybus_acc, 444, 1 }, |
19382 | | {Hexagon::V6_vtmpyhb, 445, 1 }, |
19383 | | {Hexagon::V6_vtmpyhb_acc, 446, 1 }, |
19384 | | {Hexagon::V6_vunpackb, 447, 1 }, |
19385 | | {Hexagon::V6_vunpackh, 448, 1 }, |
19386 | | {Hexagon::V6_vunpackoh, 449, 1 }, |
19387 | | {Hexagon::V6_vunpackub, 450, 1 }, |
19388 | | {Hexagon::V6_vunpackuh, 451, 1 }, |
19389 | | {Hexagon::V6_vxor, 452, 1 }, |
19390 | | {Hexagon::V6_vzb, 453, 1 }, |
19391 | | {Hexagon::V6_vzh, 454, 1 }, |
19392 | | {Hexagon::V6_zLd_ai, 455, 1 }, |
19393 | | {Hexagon::V6_zLd_pred_ai, 456, 1 }, |
19394 | | {Hexagon::Y2_crswap0, 457, 1 }, |
19395 | | {Hexagon::Y2_dcfetchbo, 458, 1 }, |
19396 | | }; |
19397 | | |
19398 | | static const AliasPattern Patterns[] = { |
19399 | | // Hexagon::A2_andir - 0 |
19400 | | {0, 0, 3, 3 }, |
19401 | | // Hexagon::A2_paddif - 1 |
19402 | | {14, 3, 4, 4 }, |
19403 | | // Hexagon::A2_paddifnew - 2 |
19404 | | {31, 7, 4, 4 }, |
19405 | | // Hexagon::A2_paddit - 3 |
19406 | | {52, 11, 4, 4 }, |
19407 | | // Hexagon::A2_padditnew - 4 |
19408 | | {68, 15, 4, 4 }, |
19409 | | // Hexagon::A2_subri - 5 |
19410 | | {88, 19, 3, 3 }, |
19411 | | {101, 22, 3, 3 }, |
19412 | | // Hexagon::A2_vaddub - 7 |
19413 | | {114, 25, 3, 3 }, |
19414 | | // Hexagon::A2_vsubub - 8 |
19415 | | {132, 28, 3, 3 }, |
19416 | | // Hexagon::C2_cmpgt - 9 |
19417 | | {150, 31, 3, 3 }, |
19418 | | // Hexagon::C2_cmpgtu - 10 |
19419 | | {169, 34, 3, 3 }, |
19420 | | // Hexagon::C2_or - 11 |
19421 | | {189, 37, 3, 3 }, |
19422 | | // Hexagon::J2_jumpf - 12 |
19423 | | {197, 40, 2, 1 }, |
19424 | | // Hexagon::J2_jumprf - 13 |
19425 | | {216, 41, 2, 2 }, |
19426 | | // Hexagon::J2_jumprt - 14 |
19427 | | {234, 43, 2, 2 }, |
19428 | | // Hexagon::J2_jumpt - 15 |
19429 | | {251, 45, 2, 1 }, |
19430 | | // Hexagon::J2_trap1 - 16 |
19431 | | {269, 46, 3, 2 }, |
19432 | | // Hexagon::L2_deallocframe - 17 |
19433 | | {280, 48, 2, 2 }, |
19434 | | // Hexagon::L2_loadalignb_io - 18 |
19435 | | {293, 50, 4, 4 }, |
19436 | | // Hexagon::L2_loadalignh_io - 19 |
19437 | | {312, 54, 4, 4 }, |
19438 | | // Hexagon::L2_loadbsw2_io - 20 |
19439 | | {331, 58, 3, 3 }, |
19440 | | // Hexagon::L2_loadbsw4_io - 21 |
19441 | | {331, 61, 3, 3 }, |
19442 | | // Hexagon::L2_loadbzw2_io - 22 |
19443 | | {346, 64, 3, 3 }, |
19444 | | // Hexagon::L2_loadbzw4_io - 23 |
19445 | | {346, 67, 3, 3 }, |
19446 | | // Hexagon::L2_loadrb_io - 24 |
19447 | | {362, 70, 3, 3 }, |
19448 | | // Hexagon::L2_loadrd_io - 25 |
19449 | | {376, 73, 3, 3 }, |
19450 | | // Hexagon::L2_loadrh_io - 26 |
19451 | | {390, 76, 3, 3 }, |
19452 | | // Hexagon::L2_loadri_io - 27 |
19453 | | {404, 79, 3, 3 }, |
19454 | | // Hexagon::L2_loadrub_io - 28 |
19455 | | {418, 82, 3, 3 }, |
19456 | | // Hexagon::L2_loadruh_io - 29 |
19457 | | {433, 85, 3, 3 }, |
19458 | | // Hexagon::L2_ploadrbf_io - 30 |
19459 | | {448, 88, 4, 4 }, |
19460 | | // Hexagon::L2_ploadrbfnew_io - 31 |
19461 | | {471, 92, 4, 4 }, |
19462 | | // Hexagon::L2_ploadrbt_io - 32 |
19463 | | {498, 96, 4, 4 }, |
19464 | | // Hexagon::L2_ploadrbtnew_io - 33 |
19465 | | {520, 100, 4, 4 }, |
19466 | | // Hexagon::L2_ploadrdf_io - 34 |
19467 | | {546, 104, 4, 4 }, |
19468 | | // Hexagon::L2_ploadrdfnew_io - 35 |
19469 | | {569, 108, 4, 4 }, |
19470 | | // Hexagon::L2_ploadrdt_io - 36 |
19471 | | {596, 112, 4, 4 }, |
19472 | | // Hexagon::L2_ploadrdtnew_io - 37 |
19473 | | {618, 116, 4, 4 }, |
19474 | | // Hexagon::L2_ploadrhf_io - 38 |
19475 | | {644, 120, 4, 4 }, |
19476 | | // Hexagon::L2_ploadrhfnew_io - 39 |
19477 | | {667, 124, 4, 4 }, |
19478 | | // Hexagon::L2_ploadrht_io - 40 |
19479 | | {694, 128, 4, 4 }, |
19480 | | // Hexagon::L2_ploadrhtnew_io - 41 |
19481 | | {716, 132, 4, 4 }, |
19482 | | // Hexagon::L2_ploadrif_io - 42 |
19483 | | {742, 136, 4, 4 }, |
19484 | | // Hexagon::L2_ploadrifnew_io - 43 |
19485 | | {765, 140, 4, 4 }, |
19486 | | // Hexagon::L2_ploadrit_io - 44 |
19487 | | {792, 144, 4, 4 }, |
19488 | | // Hexagon::L2_ploadritnew_io - 45 |
19489 | | {814, 148, 4, 4 }, |
19490 | | // Hexagon::L2_ploadrubf_io - 46 |
19491 | | {840, 152, 4, 4 }, |
19492 | | // Hexagon::L2_ploadrubfnew_io - 47 |
19493 | | {864, 156, 4, 4 }, |
19494 | | // Hexagon::L2_ploadrubt_io - 48 |
19495 | | {892, 160, 4, 4 }, |
19496 | | // Hexagon::L2_ploadrubtnew_io - 49 |
19497 | | {915, 164, 4, 4 }, |
19498 | | // Hexagon::L2_ploadruhf_io - 50 |
19499 | | {942, 168, 4, 4 }, |
19500 | | // Hexagon::L2_ploadruhfnew_io - 51 |
19501 | | {966, 172, 4, 4 }, |
19502 | | // Hexagon::L2_ploadruht_io - 52 |
19503 | | {994, 176, 4, 4 }, |
19504 | | // Hexagon::L2_ploadruhtnew_io - 53 |
19505 | | {1017, 180, 4, 4 }, |
19506 | | // Hexagon::L4_add_memopb_io - 54 |
19507 | | {1044, 184, 3, 3 }, |
19508 | | // Hexagon::L4_add_memoph_io - 55 |
19509 | | {1059, 187, 3, 3 }, |
19510 | | // Hexagon::L4_add_memopw_io - 56 |
19511 | | {1074, 190, 3, 3 }, |
19512 | | // Hexagon::L4_and_memopb_io - 57 |
19513 | | {1089, 193, 3, 3 }, |
19514 | | // Hexagon::L4_and_memoph_io - 58 |
19515 | | {1104, 196, 3, 3 }, |
19516 | | // Hexagon::L4_and_memopw_io - 59 |
19517 | | {1119, 199, 3, 3 }, |
19518 | | // Hexagon::L4_iadd_memopb_io - 60 |
19519 | | {1134, 202, 3, 2 }, |
19520 | | // Hexagon::L4_iadd_memoph_io - 61 |
19521 | | {1150, 204, 3, 2 }, |
19522 | | // Hexagon::L4_iadd_memopw_io - 62 |
19523 | | {1166, 206, 3, 2 }, |
19524 | | // Hexagon::L4_iand_memopb_io - 63 |
19525 | | {1182, 208, 3, 2 }, |
19526 | | // Hexagon::L4_iand_memoph_io - 64 |
19527 | | {1205, 210, 3, 2 }, |
19528 | | // Hexagon::L4_iand_memopw_io - 65 |
19529 | | {1228, 212, 3, 2 }, |
19530 | | // Hexagon::L4_ior_memopb_io - 66 |
19531 | | {1251, 214, 3, 2 }, |
19532 | | // Hexagon::L4_ior_memoph_io - 67 |
19533 | | {1274, 216, 3, 2 }, |
19534 | | // Hexagon::L4_ior_memopw_io - 68 |
19535 | | {1297, 218, 3, 2 }, |
19536 | | // Hexagon::L4_isub_memopb_io - 69 |
19537 | | {1320, 220, 3, 2 }, |
19538 | | // Hexagon::L4_isub_memoph_io - 70 |
19539 | | {1336, 222, 3, 2 }, |
19540 | | // Hexagon::L4_isub_memopw_io - 71 |
19541 | | {1352, 224, 3, 2 }, |
19542 | | // Hexagon::L4_or_memopb_io - 72 |
19543 | | {1368, 226, 3, 3 }, |
19544 | | // Hexagon::L4_or_memoph_io - 73 |
19545 | | {1383, 229, 3, 3 }, |
19546 | | // Hexagon::L4_or_memopw_io - 74 |
19547 | | {1398, 232, 3, 3 }, |
19548 | | // Hexagon::L4_return - 75 |
19549 | | {1413, 235, 2, 2 }, |
19550 | | // Hexagon::L4_return_f - 76 |
19551 | | {1428, 237, 3, 3 }, |
19552 | | // Hexagon::L4_return_fnew_pnt - 77 |
19553 | | {1452, 240, 3, 3 }, |
19554 | | // Hexagon::L4_return_fnew_pt - 78 |
19555 | | {1483, 243, 3, 3 }, |
19556 | | // Hexagon::L4_return_t - 79 |
19557 | | {1513, 246, 3, 3 }, |
19558 | | // Hexagon::L4_return_tnew_pnt - 80 |
19559 | | {1536, 249, 3, 3 }, |
19560 | | // Hexagon::L4_return_tnew_pt - 81 |
19561 | | {1566, 252, 3, 3 }, |
19562 | | // Hexagon::L4_sub_memopb_io - 82 |
19563 | | {1595, 255, 3, 3 }, |
19564 | | // Hexagon::L4_sub_memoph_io - 83 |
19565 | | {1610, 258, 3, 3 }, |
19566 | | // Hexagon::L4_sub_memopw_io - 84 |
19567 | | {1625, 261, 3, 3 }, |
19568 | | // Hexagon::M2_mpyi - 85 |
19569 | | {1640, 264, 3, 3 }, |
19570 | | // Hexagon::M7_dcmpyrwc - 86 |
19571 | | {1658, 267, 3, 3 }, |
19572 | | // Hexagon::M7_dcmpyrwc_acc - 87 |
19573 | | {1677, 270, 4, 4 }, |
19574 | | // Hexagon::S2_allocframe - 88 |
19575 | | {1697, 274, 3, 2 }, |
19576 | | // Hexagon::S2_pstorerbf_io - 89 |
19577 | | {1713, 276, 4, 4 }, |
19578 | | // Hexagon::S2_pstorerbnewf_io - 90 |
19579 | | {1736, 280, 4, 4 }, |
19580 | | // Hexagon::S2_pstorerbnewt_io - 91 |
19581 | | {1763, 284, 4, 4 }, |
19582 | | // Hexagon::S2_pstorerbt_io - 92 |
19583 | | {1789, 288, 4, 4 }, |
19584 | | // Hexagon::S2_pstorerdf_io - 93 |
19585 | | {1811, 292, 4, 4 }, |
19586 | | // Hexagon::S2_pstorerdt_io - 94 |
19587 | | {1834, 296, 4, 4 }, |
19588 | | // Hexagon::S2_pstorerff_io - 95 |
19589 | | {1856, 300, 4, 4 }, |
19590 | | // Hexagon::S2_pstorerft_io - 96 |
19591 | | {1881, 304, 4, 4 }, |
19592 | | // Hexagon::S2_pstorerhf_io - 97 |
19593 | | {1905, 308, 4, 4 }, |
19594 | | // Hexagon::S2_pstorerhnewf_io - 98 |
19595 | | {1928, 312, 4, 4 }, |
19596 | | // Hexagon::S2_pstorerhnewt_io - 99 |
19597 | | {1955, 316, 4, 4 }, |
19598 | | // Hexagon::S2_pstorerht_io - 100 |
19599 | | {1981, 320, 4, 4 }, |
19600 | | // Hexagon::S2_pstorerif_io - 101 |
19601 | | {2003, 324, 4, 4 }, |
19602 | | // Hexagon::S2_pstorerinewf_io - 102 |
19603 | | {2026, 328, 4, 4 }, |
19604 | | // Hexagon::S2_pstorerinewt_io - 103 |
19605 | | {2053, 332, 4, 4 }, |
19606 | | // Hexagon::S2_pstorerit_io - 104 |
19607 | | {2079, 336, 4, 4 }, |
19608 | | // Hexagon::S2_storerb_io - 105 |
19609 | | {2101, 340, 3, 3 }, |
19610 | | // Hexagon::S2_storerbnew_io - 106 |
19611 | | {2115, 343, 3, 3 }, |
19612 | | // Hexagon::S2_storerd_io - 107 |
19613 | | {2133, 346, 3, 3 }, |
19614 | | // Hexagon::S2_storerf_io - 108 |
19615 | | {2147, 349, 3, 3 }, |
19616 | | // Hexagon::S2_storerh_io - 109 |
19617 | | {2163, 352, 3, 3 }, |
19618 | | // Hexagon::S2_storerhnew_io - 110 |
19619 | | {2177, 355, 3, 3 }, |
19620 | | // Hexagon::S2_storeri_io - 111 |
19621 | | {2195, 358, 3, 3 }, |
19622 | | // Hexagon::S2_storerinew_io - 112 |
19623 | | {2209, 361, 3, 3 }, |
19624 | | // Hexagon::S2_tableidxb - 113 |
19625 | | {2227, 364, 5, 4 }, |
19626 | | // Hexagon::S4_pstorerbfnew_io - 114 |
19627 | | {2254, 368, 4, 4 }, |
19628 | | // Hexagon::S4_pstorerbnewfnew_io - 115 |
19629 | | {2281, 372, 4, 4 }, |
19630 | | // Hexagon::S4_pstorerbnewtnew_io - 116 |
19631 | | {2312, 376, 4, 4 }, |
19632 | | // Hexagon::S4_pstorerbtnew_io - 117 |
19633 | | {2342, 380, 4, 4 }, |
19634 | | // Hexagon::S4_pstorerdfnew_io - 118 |
19635 | | {2368, 384, 4, 4 }, |
19636 | | // Hexagon::S4_pstorerdtnew_io - 119 |
19637 | | {2395, 388, 4, 4 }, |
19638 | | // Hexagon::S4_pstorerffnew_io - 120 |
19639 | | {2421, 392, 4, 4 }, |
19640 | | // Hexagon::S4_pstorerftnew_io - 121 |
19641 | | {2450, 396, 4, 4 }, |
19642 | | // Hexagon::S4_pstorerhfnew_io - 122 |
19643 | | {2478, 400, 4, 4 }, |
19644 | | // Hexagon::S4_pstorerhnewfnew_io - 123 |
19645 | | {2505, 404, 4, 4 }, |
19646 | | // Hexagon::S4_pstorerhnewtnew_io - 124 |
19647 | | {2536, 408, 4, 4 }, |
19648 | | // Hexagon::S4_pstorerhtnew_io - 125 |
19649 | | {2566, 412, 4, 4 }, |
19650 | | // Hexagon::S4_pstorerifnew_io - 126 |
19651 | | {2592, 416, 4, 4 }, |
19652 | | // Hexagon::S4_pstorerinewfnew_io - 127 |
19653 | | {2619, 420, 4, 4 }, |
19654 | | // Hexagon::S4_pstorerinewtnew_io - 128 |
19655 | | {2650, 424, 4, 4 }, |
19656 | | // Hexagon::S4_pstoreritnew_io - 129 |
19657 | | {2680, 428, 4, 4 }, |
19658 | | // Hexagon::S4_storeirb_io - 130 |
19659 | | {2706, 432, 3, 2 }, |
19660 | | // Hexagon::S4_storeirbf_io - 131 |
19661 | | {2721, 434, 4, 3 }, |
19662 | | // Hexagon::S4_storeirbfnew_io - 132 |
19663 | | {2745, 437, 4, 3 }, |
19664 | | // Hexagon::S4_storeirbt_io - 133 |
19665 | | {2773, 440, 4, 3 }, |
19666 | | // Hexagon::S4_storeirbtnew_io - 134 |
19667 | | {2796, 443, 4, 3 }, |
19668 | | // Hexagon::S4_storeirh_io - 135 |
19669 | | {2823, 446, 3, 2 }, |
19670 | | // Hexagon::S4_storeirhf_io - 136 |
19671 | | {2838, 448, 4, 3 }, |
19672 | | // Hexagon::S4_storeirhfnew_io - 137 |
19673 | | {2862, 451, 4, 3 }, |
19674 | | // Hexagon::S4_storeirht_io - 138 |
19675 | | {2890, 454, 4, 3 }, |
19676 | | // Hexagon::S4_storeirhtnew_io - 139 |
19677 | | {2913, 457, 4, 3 }, |
19678 | | // Hexagon::S4_storeiri_io - 140 |
19679 | | {2940, 460, 3, 2 }, |
19680 | | // Hexagon::S4_storeirif_io - 141 |
19681 | | {2955, 462, 4, 3 }, |
19682 | | // Hexagon::S4_storeirifnew_io - 142 |
19683 | | {2979, 465, 4, 3 }, |
19684 | | // Hexagon::S4_storeirit_io - 143 |
19685 | | {3007, 468, 4, 3 }, |
19686 | | // Hexagon::S4_storeiritnew_io - 144 |
19687 | | {3030, 471, 4, 3 }, |
19688 | | // Hexagon::V6_extractw - 145 |
19689 | | {3057, 474, 3, 3 }, |
19690 | | // Hexagon::V6_v6mpyhubs10 - 146 |
19691 | | {3080, 477, 4, 3 }, |
19692 | | // Hexagon::V6_v6mpyvubs10 - 147 |
19693 | | {3113, 480, 4, 3 }, |
19694 | | // Hexagon::V6_vL32Ub_ai - 148 |
19695 | | {3146, 483, 3, 3 }, |
19696 | | // Hexagon::V6_vL32b_ai - 149 |
19697 | | {3161, 486, 3, 3 }, |
19698 | | // Hexagon::V6_vL32b_cur_npred_pi - 150 |
19699 | | {3175, 489, 5, 5 }, |
19700 | | // Hexagon::V6_vL32b_cur_pred_pi - 151 |
19701 | | {3202, 494, 5, 5 }, |
19702 | | // Hexagon::V6_vL32b_npred_ai - 152 |
19703 | | {3228, 499, 4, 4 }, |
19704 | | // Hexagon::V6_vL32b_npred_pi - 153 |
19705 | | {3255, 503, 5, 5 }, |
19706 | | // Hexagon::V6_vL32b_nt_ai - 154 |
19707 | | {3278, 508, 3, 3 }, |
19708 | | // Hexagon::V6_vL32b_nt_cur_npred_pi - 155 |
19709 | | {3295, 511, 5, 5 }, |
19710 | | // Hexagon::V6_vL32b_nt_cur_pred_pi - 156 |
19711 | | {3325, 516, 5, 5 }, |
19712 | | // Hexagon::V6_vL32b_nt_npred_ai - 157 |
19713 | | {3354, 521, 4, 4 }, |
19714 | | // Hexagon::V6_vL32b_nt_npred_pi - 158 |
19715 | | {3384, 525, 5, 5 }, |
19716 | | // Hexagon::V6_vL32b_nt_pred_ai - 159 |
19717 | | {3410, 530, 4, 4 }, |
19718 | | // Hexagon::V6_vL32b_nt_tmp_pred_ai - 160 |
19719 | | {3435, 534, 4, 4 }, |
19720 | | // Hexagon::V6_vL32b_pred_ai - 161 |
19721 | | {3464, 538, 4, 4 }, |
19722 | | // Hexagon::V6_vL32b_tmp_pred_ai - 162 |
19723 | | {3486, 542, 4, 4 }, |
19724 | | // Hexagon::V6_vS32Ub_ai - 163 |
19725 | | {3512, 546, 3, 3 }, |
19726 | | // Hexagon::V6_vS32Ub_npred_ai - 164 |
19727 | | {3527, 549, 4, 4 }, |
19728 | | // Hexagon::V6_vS32Ub_pred_ai - 165 |
19729 | | {3551, 553, 4, 4 }, |
19730 | | // Hexagon::V6_vS32b_ai - 166 |
19731 | | {3574, 557, 3, 3 }, |
19732 | | // Hexagon::V6_vS32b_new_ai - 167 |
19733 | | {3588, 560, 3, 3 }, |
19734 | | // Hexagon::V6_vS32b_npred_ai - 168 |
19735 | | {3606, 563, 4, 4 }, |
19736 | | // Hexagon::V6_vS32b_nqpred_ai - 169 |
19737 | | {3606, 567, 4, 4 }, |
19738 | | // Hexagon::V6_vS32b_nt_ai - 170 |
19739 | | {3629, 571, 3, 3 }, |
19740 | | // Hexagon::V6_vS32b_nt_new_ai - 171 |
19741 | | {3646, 574, 3, 3 }, |
19742 | | // Hexagon::V6_vS32b_nt_npred_ai - 172 |
19743 | | {3667, 577, 4, 4 }, |
19744 | | // Hexagon::V6_vS32b_nt_nqpred_ai - 173 |
19745 | | {3667, 581, 4, 4 }, |
19746 | | // Hexagon::V6_vS32b_nt_pred_ai - 174 |
19747 | | {3693, 585, 4, 4 }, |
19748 | | // Hexagon::V6_vS32b_nt_qpred_ai - 175 |
19749 | | {3693, 589, 4, 4 }, |
19750 | | // Hexagon::V6_vS32b_pred_ai - 176 |
19751 | | {3718, 593, 4, 4 }, |
19752 | | // Hexagon::V6_vS32b_qpred_ai - 177 |
19753 | | {3718, 597, 4, 4 }, |
19754 | | // Hexagon::V6_vabsb_sat - 178 |
19755 | | {3740, 601, 2, 2 }, |
19756 | | // Hexagon::V6_vabsdiffh - 179 |
19757 | | {3759, 603, 3, 3 }, |
19758 | | // Hexagon::V6_vabsdiffub - 180 |
19759 | | {3781, 606, 3, 3 }, |
19760 | | // Hexagon::V6_vabsdiffuh - 181 |
19761 | | {3804, 609, 3, 3 }, |
19762 | | // Hexagon::V6_vabsdiffw - 182 |
19763 | | {3827, 612, 3, 3 }, |
19764 | | // Hexagon::V6_vabsh_sat - 183 |
19765 | | {3849, 615, 2, 2 }, |
19766 | | // Hexagon::V6_vabsw_sat - 184 |
19767 | | {3868, 617, 2, 2 }, |
19768 | | // Hexagon::V6_vaddb - 185 |
19769 | | {114, 619, 3, 3 }, |
19770 | | // Hexagon::V6_vaddb_dv - 186 |
19771 | | {114, 622, 3, 3 }, |
19772 | | // Hexagon::V6_vaddbnq - 187 |
19773 | | {3887, 625, 4, 4 }, |
19774 | | // Hexagon::V6_vaddbq - 188 |
19775 | | {3911, 629, 4, 4 }, |
19776 | | // Hexagon::V6_vaddbsat - 189 |
19777 | | {3934, 633, 3, 3 }, |
19778 | | // Hexagon::V6_vaddbsat_dv - 190 |
19779 | | {3934, 636, 3, 3 }, |
19780 | | // Hexagon::V6_vaddh - 191 |
19781 | | {3956, 639, 3, 3 }, |
19782 | | // Hexagon::V6_vaddh_dv - 192 |
19783 | | {3956, 642, 3, 3 }, |
19784 | | // Hexagon::V6_vaddhnq - 193 |
19785 | | {3974, 645, 4, 4 }, |
19786 | | // Hexagon::V6_vaddhq - 194 |
19787 | | {3998, 649, 4, 4 }, |
19788 | | // Hexagon::V6_vaddhsat - 195 |
19789 | | {4021, 653, 3, 3 }, |
19790 | | // Hexagon::V6_vaddhsat_dv - 196 |
19791 | | {4021, 656, 3, 3 }, |
19792 | | // Hexagon::V6_vaddhw - 197 |
19793 | | {3956, 659, 3, 3 }, |
19794 | | // Hexagon::V6_vaddhw_acc - 198 |
19795 | | {4043, 662, 4, 4 }, |
19796 | | // Hexagon::V6_vaddubh - 199 |
19797 | | {4062, 666, 3, 3 }, |
19798 | | // Hexagon::V6_vaddubh_acc - 200 |
19799 | | {4081, 669, 4, 4 }, |
19800 | | // Hexagon::V6_vaddubsat - 201 |
19801 | | {4101, 673, 3, 3 }, |
19802 | | // Hexagon::V6_vaddubsat_dv - 202 |
19803 | | {4101, 676, 3, 3 }, |
19804 | | // Hexagon::V6_vadduhsat - 203 |
19805 | | {4124, 679, 3, 3 }, |
19806 | | // Hexagon::V6_vadduhsat_dv - 204 |
19807 | | {4124, 682, 3, 3 }, |
19808 | | // Hexagon::V6_vadduhw - 205 |
19809 | | {4147, 685, 3, 3 }, |
19810 | | // Hexagon::V6_vadduhw_acc - 206 |
19811 | | {4166, 688, 4, 4 }, |
19812 | | // Hexagon::V6_vadduwsat - 207 |
19813 | | {4186, 692, 3, 3 }, |
19814 | | // Hexagon::V6_vadduwsat_dv - 208 |
19815 | | {4186, 695, 3, 3 }, |
19816 | | // Hexagon::V6_vaddw - 209 |
19817 | | {4209, 698, 3, 3 }, |
19818 | | // Hexagon::V6_vaddw_dv - 210 |
19819 | | {4209, 701, 3, 3 }, |
19820 | | // Hexagon::V6_vaddwnq - 211 |
19821 | | {4227, 704, 4, 4 }, |
19822 | | // Hexagon::V6_vaddwq - 212 |
19823 | | {4251, 708, 4, 4 }, |
19824 | | // Hexagon::V6_vaddwsat - 213 |
19825 | | {4274, 712, 3, 3 }, |
19826 | | // Hexagon::V6_vaddwsat_dv - 214 |
19827 | | {4274, 715, 3, 3 }, |
19828 | | // Hexagon::V6_vandnqrt - 215 |
19829 | | {4296, 718, 3, 3 }, |
19830 | | // Hexagon::V6_vandnqrt_acc - 216 |
19831 | | {4323, 721, 4, 4 }, |
19832 | | // Hexagon::V6_vandqrt - 217 |
19833 | | {4351, 725, 3, 3 }, |
19834 | | // Hexagon::V6_vandqrt_acc - 218 |
19835 | | {4377, 728, 4, 4 }, |
19836 | | // Hexagon::V6_vandvrt - 219 |
19837 | | {4351, 732, 3, 3 }, |
19838 | | // Hexagon::V6_vandvrt_acc - 220 |
19839 | | {4377, 735, 4, 4 }, |
19840 | | // Hexagon::V6_vaslh - 221 |
19841 | | {4404, 739, 3, 3 }, |
19842 | | // Hexagon::V6_vaslh_acc - 222 |
19843 | | {4422, 742, 4, 4 }, |
19844 | | // Hexagon::V6_vaslhv - 223 |
19845 | | {4404, 746, 3, 3 }, |
19846 | | // Hexagon::V6_vaslw - 224 |
19847 | | {4441, 749, 3, 3 }, |
19848 | | // Hexagon::V6_vaslw_acc - 225 |
19849 | | {4459, 752, 4, 4 }, |
19850 | | // Hexagon::V6_vaslwv - 226 |
19851 | | {4441, 756, 3, 3 }, |
19852 | | // Hexagon::V6_vasr_into - 227 |
19853 | | {4478, 759, 4, 4 }, |
19854 | | // Hexagon::V6_vasrh - 228 |
19855 | | {4499, 763, 3, 3 }, |
19856 | | // Hexagon::V6_vasrh_acc - 229 |
19857 | | {4517, 766, 4, 4 }, |
19858 | | // Hexagon::V6_vasrhv - 230 |
19859 | | {4499, 770, 3, 3 }, |
19860 | | // Hexagon::V6_vasrw - 231 |
19861 | | {4536, 773, 3, 3 }, |
19862 | | // Hexagon::V6_vasrw_acc - 232 |
19863 | | {4554, 776, 4, 4 }, |
19864 | | // Hexagon::V6_vasrwv - 233 |
19865 | | {4536, 780, 3, 3 }, |
19866 | | // Hexagon::V6_vavgb - 234 |
19867 | | {4573, 783, 3, 3 }, |
19868 | | // Hexagon::V6_vavgbrnd - 235 |
19869 | | {4591, 786, 3, 3 }, |
19870 | | // Hexagon::V6_vavgh - 236 |
19871 | | {4613, 789, 3, 3 }, |
19872 | | // Hexagon::V6_vavghrnd - 237 |
19873 | | {4631, 792, 3, 3 }, |
19874 | | // Hexagon::V6_vavgub - 238 |
19875 | | {4653, 795, 3, 3 }, |
19876 | | // Hexagon::V6_vavgubrnd - 239 |
19877 | | {4672, 798, 3, 3 }, |
19878 | | // Hexagon::V6_vavguh - 240 |
19879 | | {4695, 801, 3, 3 }, |
19880 | | // Hexagon::V6_vavguhrnd - 241 |
19881 | | {4714, 804, 3, 3 }, |
19882 | | // Hexagon::V6_vavguw - 242 |
19883 | | {4737, 807, 3, 3 }, |
19884 | | // Hexagon::V6_vavguwrnd - 243 |
19885 | | {4756, 810, 3, 3 }, |
19886 | | // Hexagon::V6_vavgw - 244 |
19887 | | {4779, 813, 3, 3 }, |
19888 | | // Hexagon::V6_vavgwrnd - 245 |
19889 | | {4797, 816, 3, 3 }, |
19890 | | // Hexagon::V6_vcl0h - 246 |
19891 | | {4819, 819, 2, 2 }, |
19892 | | // Hexagon::V6_vcl0w - 247 |
19893 | | {4834, 821, 2, 2 }, |
19894 | | // Hexagon::V6_vdealb - 248 |
19895 | | {4849, 823, 2, 2 }, |
19896 | | // Hexagon::V6_vdealb4w - 249 |
19897 | | {4865, 825, 3, 3 }, |
19898 | | // Hexagon::V6_vdealh - 250 |
19899 | | {4886, 828, 2, 2 }, |
19900 | | // Hexagon::V6_vdmpybus - 251 |
19901 | | {4902, 830, 3, 3 }, |
19902 | | // Hexagon::V6_vdmpybus_acc - 252 |
19903 | | {4923, 833, 4, 4 }, |
19904 | | // Hexagon::V6_vdmpybus_dv - 253 |
19905 | | {4902, 837, 3, 3 }, |
19906 | | // Hexagon::V6_vdmpybus_dv_acc - 254 |
19907 | | {4923, 840, 4, 4 }, |
19908 | | // Hexagon::V6_vdmpyhb - 255 |
19909 | | {4945, 844, 3, 3 }, |
19910 | | // Hexagon::V6_vdmpyhb_acc - 256 |
19911 | | {4965, 847, 4, 4 }, |
19912 | | // Hexagon::V6_vdmpyhb_dv - 257 |
19913 | | {4945, 851, 3, 3 }, |
19914 | | // Hexagon::V6_vdmpyhb_dv_acc - 258 |
19915 | | {4965, 854, 4, 4 }, |
19916 | | // Hexagon::V6_vdmpyhisat - 259 |
19917 | | {4986, 858, 3, 3 }, |
19918 | | // Hexagon::V6_vdmpyhisat_acc - 260 |
19919 | | {5009, 861, 4, 4 }, |
19920 | | // Hexagon::V6_vdmpyhsat - 261 |
19921 | | {4986, 865, 3, 3 }, |
19922 | | // Hexagon::V6_vdmpyhsat_acc - 262 |
19923 | | {5009, 868, 4, 4 }, |
19924 | | // Hexagon::V6_vdmpyhsuisat - 263 |
19925 | | {5033, 872, 3, 3 }, |
19926 | | // Hexagon::V6_vdmpyhsuisat_acc - 264 |
19927 | | {5061, 875, 4, 4 }, |
19928 | | // Hexagon::V6_vdmpyhsusat - 265 |
19929 | | {5090, 879, 3, 3 }, |
19930 | | // Hexagon::V6_vdmpyhsusat_acc - 266 |
19931 | | {5115, 882, 4, 4 }, |
19932 | | // Hexagon::V6_vdmpyhvsat - 267 |
19933 | | {4986, 886, 3, 3 }, |
19934 | | // Hexagon::V6_vdmpyhvsat_acc - 268 |
19935 | | {5009, 889, 4, 4 }, |
19936 | | // Hexagon::V6_vdsaduh - 269 |
19937 | | {5141, 893, 3, 3 }, |
19938 | | // Hexagon::V6_vdsaduh_acc - 270 |
19939 | | {5161, 896, 4, 4 }, |
19940 | | // Hexagon::V6_veqb - 271 |
19941 | | {5182, 900, 3, 3 }, |
19942 | | // Hexagon::V6_veqb_and - 272 |
19943 | | {5208, 903, 4, 4 }, |
19944 | | // Hexagon::V6_veqb_or - 273 |
19945 | | {5235, 907, 4, 4 }, |
19946 | | // Hexagon::V6_veqb_xor - 274 |
19947 | | {5262, 911, 4, 4 }, |
19948 | | // Hexagon::V6_veqh - 275 |
19949 | | {5289, 915, 3, 3 }, |
19950 | | // Hexagon::V6_veqh_and - 276 |
19951 | | {5315, 918, 4, 4 }, |
19952 | | // Hexagon::V6_veqh_or - 277 |
19953 | | {5342, 922, 4, 4 }, |
19954 | | // Hexagon::V6_veqh_xor - 278 |
19955 | | {5369, 926, 4, 4 }, |
19956 | | // Hexagon::V6_veqw - 279 |
19957 | | {5396, 930, 3, 3 }, |
19958 | | // Hexagon::V6_veqw_and - 280 |
19959 | | {5422, 933, 4, 4 }, |
19960 | | // Hexagon::V6_veqw_or - 281 |
19961 | | {5449, 937, 4, 4 }, |
19962 | | // Hexagon::V6_veqw_xor - 282 |
19963 | | {5476, 941, 4, 4 }, |
19964 | | // Hexagon::V6_vlsrh - 283 |
19965 | | {5503, 945, 3, 3 }, |
19966 | | // Hexagon::V6_vlsrhv - 284 |
19967 | | {5503, 948, 3, 3 }, |
19968 | | // Hexagon::V6_vlsrw - 285 |
19969 | | {5521, 951, 3, 3 }, |
19970 | | // Hexagon::V6_vlsrwv - 286 |
19971 | | {5521, 954, 3, 3 }, |
19972 | | // Hexagon::V6_vmaxb - 287 |
19973 | | {5539, 957, 3, 3 }, |
19974 | | // Hexagon::V6_vmaxh - 288 |
19975 | | {5557, 960, 3, 3 }, |
19976 | | // Hexagon::V6_vmaxub - 289 |
19977 | | {5575, 963, 3, 3 }, |
19978 | | // Hexagon::V6_vmaxuh - 290 |
19979 | | {5594, 966, 3, 3 }, |
19980 | | // Hexagon::V6_vmaxw - 291 |
19981 | | {5613, 969, 3, 3 }, |
19982 | | // Hexagon::V6_vminb - 292 |
19983 | | {5631, 972, 3, 3 }, |
19984 | | // Hexagon::V6_vminh - 293 |
19985 | | {5649, 975, 3, 3 }, |
19986 | | // Hexagon::V6_vminub - 294 |
19987 | | {5667, 978, 3, 3 }, |
19988 | | // Hexagon::V6_vminuh - 295 |
19989 | | {5686, 981, 3, 3 }, |
19990 | | // Hexagon::V6_vminw - 296 |
19991 | | {5705, 984, 3, 3 }, |
19992 | | // Hexagon::V6_vmpabus - 297 |
19993 | | {5723, 987, 3, 3 }, |
19994 | | // Hexagon::V6_vmpabus_acc - 298 |
19995 | | {5743, 990, 4, 4 }, |
19996 | | // Hexagon::V6_vmpabusv - 299 |
19997 | | {5723, 994, 3, 3 }, |
19998 | | // Hexagon::V6_vmpabuu - 300 |
19999 | | {5764, 997, 3, 3 }, |
20000 | | // Hexagon::V6_vmpabuu_acc - 301 |
20001 | | {5784, 1000, 4, 4 }, |
20002 | | // Hexagon::V6_vmpabuuv - 302 |
20003 | | {5764, 1004, 3, 3 }, |
20004 | | // Hexagon::V6_vmpahb - 303 |
20005 | | {5805, 1007, 3, 3 }, |
20006 | | // Hexagon::V6_vmpahb_acc - 304 |
20007 | | {5824, 1010, 4, 4 }, |
20008 | | // Hexagon::V6_vmpauhb - 305 |
20009 | | {5844, 1014, 3, 3 }, |
20010 | | // Hexagon::V6_vmpauhb_acc - 306 |
20011 | | {5864, 1017, 4, 4 }, |
20012 | | // Hexagon::V6_vmpybus - 307 |
20013 | | {5885, 1021, 3, 3 }, |
20014 | | // Hexagon::V6_vmpybus_acc - 308 |
20015 | | {5905, 1024, 4, 4 }, |
20016 | | // Hexagon::V6_vmpybusv - 309 |
20017 | | {5885, 1028, 3, 3 }, |
20018 | | // Hexagon::V6_vmpybusv_acc - 310 |
20019 | | {5905, 1031, 4, 4 }, |
20020 | | // Hexagon::V6_vmpybv - 311 |
20021 | | {5926, 1035, 3, 3 }, |
20022 | | // Hexagon::V6_vmpybv_acc - 312 |
20023 | | {5944, 1038, 4, 4 }, |
20024 | | // Hexagon::V6_vmpyewuh - 313 |
20025 | | {5963, 1042, 3, 3 }, |
20026 | | // Hexagon::V6_vmpyh - 314 |
20027 | | {5984, 1045, 3, 3 }, |
20028 | | // Hexagon::V6_vmpyh_acc - 315 |
20029 | | {6002, 1048, 4, 4 }, |
20030 | | // Hexagon::V6_vmpyhsat_acc - 316 |
20031 | | {6021, 1052, 4, 4 }, |
20032 | | // Hexagon::V6_vmpyhsrs - 317 |
20033 | | {6044, 1056, 3, 3 }, |
20034 | | // Hexagon::V6_vmpyhss - 318 |
20035 | | {6074, 1059, 3, 3 }, |
20036 | | // Hexagon::V6_vmpyhus - 319 |
20037 | | {6100, 1062, 3, 3 }, |
20038 | | // Hexagon::V6_vmpyhus_acc - 320 |
20039 | | {6120, 1065, 4, 4 }, |
20040 | | // Hexagon::V6_vmpyhv - 321 |
20041 | | {5984, 1069, 3, 3 }, |
20042 | | // Hexagon::V6_vmpyhv_acc - 322 |
20043 | | {6002, 1072, 4, 4 }, |
20044 | | // Hexagon::V6_vmpyhvsrs - 323 |
20045 | | {6044, 1076, 3, 3 }, |
20046 | | // Hexagon::V6_vmpyiewh_acc - 324 |
20047 | | {6141, 1079, 4, 4 }, |
20048 | | // Hexagon::V6_vmpyiewuh - 325 |
20049 | | {6163, 1083, 3, 3 }, |
20050 | | // Hexagon::V6_vmpyiewuh_acc - 326 |
20051 | | {6185, 1086, 4, 4 }, |
20052 | | // Hexagon::V6_vmpyih - 327 |
20053 | | {6208, 1090, 3, 3 }, |
20054 | | // Hexagon::V6_vmpyih_acc - 328 |
20055 | | {6227, 1093, 4, 4 }, |
20056 | | // Hexagon::V6_vmpyihb - 329 |
20057 | | {6247, 1097, 3, 3 }, |
20058 | | // Hexagon::V6_vmpyihb_acc - 330 |
20059 | | {6267, 1100, 4, 4 }, |
20060 | | // Hexagon::V6_vmpyiowh - 331 |
20061 | | {6288, 1104, 3, 3 }, |
20062 | | // Hexagon::V6_vmpyiwb - 332 |
20063 | | {6309, 1107, 3, 3 }, |
20064 | | // Hexagon::V6_vmpyiwb_acc - 333 |
20065 | | {6329, 1110, 4, 4 }, |
20066 | | // Hexagon::V6_vmpyiwh - 334 |
20067 | | {6350, 1114, 3, 3 }, |
20068 | | // Hexagon::V6_vmpyiwh_acc - 335 |
20069 | | {6370, 1117, 4, 4 }, |
20070 | | // Hexagon::V6_vmpyiwub - 336 |
20071 | | {6391, 1121, 3, 3 }, |
20072 | | // Hexagon::V6_vmpyiwub_acc - 337 |
20073 | | {6412, 1124, 4, 4 }, |
20074 | | // Hexagon::V6_vmpyowh - 338 |
20075 | | {6434, 1128, 3, 3 }, |
20076 | | // Hexagon::V6_vmpyowh_rnd - 339 |
20077 | | {6462, 1131, 3, 3 }, |
20078 | | // Hexagon::V6_vmpyub - 340 |
20079 | | {6494, 1134, 3, 3 }, |
20080 | | // Hexagon::V6_vmpyub_acc - 341 |
20081 | | {6513, 1137, 4, 4 }, |
20082 | | // Hexagon::V6_vmpyubv - 342 |
20083 | | {6494, 1141, 3, 3 }, |
20084 | | // Hexagon::V6_vmpyubv_acc - 343 |
20085 | | {6513, 1144, 4, 4 }, |
20086 | | // Hexagon::V6_vmpyuh - 344 |
20087 | | {6533, 1148, 3, 3 }, |
20088 | | // Hexagon::V6_vmpyuh_acc - 345 |
20089 | | {6552, 1151, 4, 4 }, |
20090 | | // Hexagon::V6_vmpyuhv - 346 |
20091 | | {6533, 1155, 3, 3 }, |
20092 | | // Hexagon::V6_vmpyuhv_acc - 347 |
20093 | | {6552, 1158, 4, 4 }, |
20094 | | // Hexagon::V6_vnavgb - 348 |
20095 | | {6572, 1162, 3, 3 }, |
20096 | | // Hexagon::V6_vnavgh - 349 |
20097 | | {6591, 1165, 3, 3 }, |
20098 | | // Hexagon::V6_vnavgub - 350 |
20099 | | {6610, 1168, 3, 3 }, |
20100 | | // Hexagon::V6_vnavgw - 351 |
20101 | | {6630, 1171, 3, 3 }, |
20102 | | // Hexagon::V6_vnormamth - 352 |
20103 | | {6649, 1174, 2, 2 }, |
20104 | | // Hexagon::V6_vnormamtw - 353 |
20105 | | {6668, 1176, 2, 2 }, |
20106 | | // Hexagon::V6_vpackeb - 354 |
20107 | | {6687, 1178, 3, 3 }, |
20108 | | // Hexagon::V6_vpackeh - 355 |
20109 | | {6707, 1181, 3, 3 }, |
20110 | | // Hexagon::V6_vpackhb_sat - 356 |
20111 | | {6727, 1184, 3, 3 }, |
20112 | | // Hexagon::V6_vpackhub_sat - 357 |
20113 | | {6751, 1187, 3, 3 }, |
20114 | | // Hexagon::V6_vpackob - 358 |
20115 | | {6776, 1190, 3, 3 }, |
20116 | | // Hexagon::V6_vpackoh - 359 |
20117 | | {6796, 1193, 3, 3 }, |
20118 | | // Hexagon::V6_vpackwh_sat - 360 |
20119 | | {6816, 1196, 3, 3 }, |
20120 | | // Hexagon::V6_vpackwuh_sat - 361 |
20121 | | {6840, 1199, 3, 3 }, |
20122 | | // Hexagon::V6_vpopcounth - 362 |
20123 | | {6865, 1202, 2, 2 }, |
20124 | | // Hexagon::V6_vrmpybub_rtt - 363 |
20125 | | {6885, 1204, 3, 3 }, |
20126 | | // Hexagon::V6_vrmpybub_rtt_acc - 364 |
20127 | | {6910, 1207, 4, 4 }, |
20128 | | // Hexagon::V6_vrmpybus - 365 |
20129 | | {6936, 1211, 3, 3 }, |
20130 | | // Hexagon::V6_vrmpybus_acc - 366 |
20131 | | {6957, 1214, 4, 4 }, |
20132 | | // Hexagon::V6_vrmpybusi - 367 |
20133 | | {6979, 1218, 4, 3 }, |
20134 | | // Hexagon::V6_vrmpybusi_acc - 368 |
20135 | | {7004, 1221, 5, 4 }, |
20136 | | // Hexagon::V6_vrmpybusv - 369 |
20137 | | {6936, 1225, 3, 3 }, |
20138 | | // Hexagon::V6_vrmpybusv_acc - 370 |
20139 | | {6957, 1228, 4, 4 }, |
20140 | | // Hexagon::V6_vrmpybv - 371 |
20141 | | {7030, 1232, 3, 3 }, |
20142 | | // Hexagon::V6_vrmpybv_acc - 372 |
20143 | | {7049, 1235, 4, 4 }, |
20144 | | // Hexagon::V6_vrmpyub - 373 |
20145 | | {7069, 1239, 3, 3 }, |
20146 | | // Hexagon::V6_vrmpyub_acc - 374 |
20147 | | {7089, 1242, 4, 4 }, |
20148 | | // Hexagon::V6_vrmpyub_rtt - 375 |
20149 | | {7110, 1246, 3, 3 }, |
20150 | | // Hexagon::V6_vrmpyub_rtt_acc - 376 |
20151 | | {7137, 1249, 4, 4 }, |
20152 | | // Hexagon::V6_vrmpyubi - 377 |
20153 | | {7165, 1253, 4, 3 }, |
20154 | | // Hexagon::V6_vrmpyubi_acc - 378 |
20155 | | {7189, 1256, 5, 4 }, |
20156 | | // Hexagon::V6_vrmpyubv - 379 |
20157 | | {7069, 1260, 3, 3 }, |
20158 | | // Hexagon::V6_vrmpyubv_acc - 380 |
20159 | | {7089, 1263, 4, 4 }, |
20160 | | // Hexagon::V6_vrotr - 381 |
20161 | | {7214, 1267, 3, 3 }, |
20162 | | // Hexagon::V6_vroundhb - 382 |
20163 | | {7232, 1270, 3, 3 }, |
20164 | | // Hexagon::V6_vroundhub - 383 |
20165 | | {7257, 1273, 3, 3 }, |
20166 | | // Hexagon::V6_vrounduhub - 384 |
20167 | | {7283, 1276, 3, 3 }, |
20168 | | // Hexagon::V6_vrounduwuh - 385 |
20169 | | {7310, 1279, 3, 3 }, |
20170 | | // Hexagon::V6_vroundwh - 386 |
20171 | | {7337, 1282, 3, 3 }, |
20172 | | // Hexagon::V6_vroundwuh - 387 |
20173 | | {7362, 1285, 3, 3 }, |
20174 | | // Hexagon::V6_vrsadubi - 388 |
20175 | | {7388, 1288, 4, 3 }, |
20176 | | // Hexagon::V6_vrsadubi_acc - 389 |
20177 | | {7412, 1291, 5, 4 }, |
20178 | | // Hexagon::V6_vsathub - 390 |
20179 | | {7437, 1295, 3, 3 }, |
20180 | | // Hexagon::V6_vsatuwuh - 391 |
20181 | | {7457, 1298, 3, 3 }, |
20182 | | // Hexagon::V6_vsatwh - 392 |
20183 | | {7478, 1301, 3, 3 }, |
20184 | | // Hexagon::V6_vsb - 393 |
20185 | | {7497, 1304, 2, 2 }, |
20186 | | // Hexagon::V6_vscattermh - 394 |
20187 | | {7512, 1306, 4, 4 }, |
20188 | | // Hexagon::V6_vscattermh_add - 395 |
20189 | | {7540, 1310, 4, 4 }, |
20190 | | // Hexagon::V6_vscattermhq - 396 |
20191 | | {7569, 1314, 5, 5 }, |
20192 | | // Hexagon::V6_vscattermhw - 397 |
20193 | | {7605, 1319, 4, 4 }, |
20194 | | // Hexagon::V6_vscattermhw_add - 398 |
20195 | | {7633, 1323, 4, 4 }, |
20196 | | // Hexagon::V6_vscattermhwq - 399 |
20197 | | {7662, 1327, 5, 5 }, |
20198 | | // Hexagon::V6_vscattermw - 400 |
20199 | | {7698, 1332, 4, 4 }, |
20200 | | // Hexagon::V6_vscattermw_add - 401 |
20201 | | {7726, 1336, 4, 4 }, |
20202 | | // Hexagon::V6_vscattermwq - 402 |
20203 | | {7755, 1340, 5, 5 }, |
20204 | | // Hexagon::V6_vsh - 403 |
20205 | | {7791, 1345, 2, 2 }, |
20206 | | // Hexagon::V6_vshufeh - 404 |
20207 | | {7806, 1347, 3, 3 }, |
20208 | | // Hexagon::V6_vshuff - 405 |
20209 | | {7827, 1350, 5, 5 }, |
20210 | | // Hexagon::V6_vshuffb - 406 |
20211 | | {7847, 1355, 2, 2 }, |
20212 | | // Hexagon::V6_vshuffeb - 407 |
20213 | | {7864, 1357, 3, 3 }, |
20214 | | // Hexagon::V6_vshuffh - 408 |
20215 | | {7885, 1360, 2, 2 }, |
20216 | | // Hexagon::V6_vshuffob - 409 |
20217 | | {7902, 1362, 3, 3 }, |
20218 | | // Hexagon::V6_vshufoeb - 410 |
20219 | | {7923, 1365, 3, 3 }, |
20220 | | // Hexagon::V6_vshufoeh - 411 |
20221 | | {7945, 1368, 3, 3 }, |
20222 | | // Hexagon::V6_vshufoh - 412 |
20223 | | {7967, 1371, 3, 3 }, |
20224 | | // Hexagon::V6_vsubb - 413 |
20225 | | {132, 1374, 3, 3 }, |
20226 | | // Hexagon::V6_vsubb_dv - 414 |
20227 | | {132, 1377, 3, 3 }, |
20228 | | // Hexagon::V6_vsubbnq - 415 |
20229 | | {7988, 1380, 4, 4 }, |
20230 | | // Hexagon::V6_vsubbq - 416 |
20231 | | {8012, 1384, 4, 4 }, |
20232 | | // Hexagon::V6_vsubbsat - 417 |
20233 | | {8035, 1388, 3, 3 }, |
20234 | | // Hexagon::V6_vsubbsat_dv - 418 |
20235 | | {8035, 1391, 3, 3 }, |
20236 | | // Hexagon::V6_vsubh - 419 |
20237 | | {8057, 1394, 3, 3 }, |
20238 | | // Hexagon::V6_vsubh_dv - 420 |
20239 | | {8057, 1397, 3, 3 }, |
20240 | | // Hexagon::V6_vsubhnq - 421 |
20241 | | {8075, 1400, 4, 4 }, |
20242 | | // Hexagon::V6_vsubhq - 422 |
20243 | | {8099, 1404, 4, 4 }, |
20244 | | // Hexagon::V6_vsubhsat - 423 |
20245 | | {8122, 1408, 3, 3 }, |
20246 | | // Hexagon::V6_vsubhsat_dv - 424 |
20247 | | {8122, 1411, 3, 3 }, |
20248 | | // Hexagon::V6_vsubhw - 425 |
20249 | | {8057, 1414, 3, 3 }, |
20250 | | // Hexagon::V6_vsububh - 426 |
20251 | | {8144, 1417, 3, 3 }, |
20252 | | // Hexagon::V6_vsububsat - 427 |
20253 | | {8163, 1420, 3, 3 }, |
20254 | | // Hexagon::V6_vsububsat_dv - 428 |
20255 | | {8163, 1423, 3, 3 }, |
20256 | | // Hexagon::V6_vsubuhsat - 429 |
20257 | | {8186, 1426, 3, 3 }, |
20258 | | // Hexagon::V6_vsubuhsat_dv - 430 |
20259 | | {8186, 1429, 3, 3 }, |
20260 | | // Hexagon::V6_vsubuhw - 431 |
20261 | | {8209, 1432, 3, 3 }, |
20262 | | // Hexagon::V6_vsubuwsat - 432 |
20263 | | {8228, 1435, 3, 3 }, |
20264 | | // Hexagon::V6_vsubuwsat_dv - 433 |
20265 | | {8228, 1438, 3, 3 }, |
20266 | | // Hexagon::V6_vsubw - 434 |
20267 | | {8251, 1441, 3, 3 }, |
20268 | | // Hexagon::V6_vsubw_dv - 435 |
20269 | | {8269, 1444, 3, 3 }, |
20270 | | {8251, 1447, 3, 3 }, |
20271 | | // Hexagon::V6_vsubwnq - 437 |
20272 | | {8277, 1450, 4, 4 }, |
20273 | | // Hexagon::V6_vsubwq - 438 |
20274 | | {8301, 1454, 4, 4 }, |
20275 | | // Hexagon::V6_vsubwsat - 439 |
20276 | | {8324, 1458, 3, 3 }, |
20277 | | // Hexagon::V6_vsubwsat_dv - 440 |
20278 | | {8324, 1461, 3, 3 }, |
20279 | | // Hexagon::V6_vtmpyb - 441 |
20280 | | {8346, 1464, 3, 3 }, |
20281 | | // Hexagon::V6_vtmpyb_acc - 442 |
20282 | | {8365, 1467, 4, 4 }, |
20283 | | // Hexagon::V6_vtmpybus - 443 |
20284 | | {8385, 1471, 3, 3 }, |
20285 | | // Hexagon::V6_vtmpybus_acc - 444 |
20286 | | {8406, 1474, 4, 4 }, |
20287 | | // Hexagon::V6_vtmpyhb - 445 |
20288 | | {8428, 1478, 3, 3 }, |
20289 | | // Hexagon::V6_vtmpyhb_acc - 446 |
20290 | | {8448, 1481, 4, 4 }, |
20291 | | // Hexagon::V6_vunpackb - 447 |
20292 | | {8469, 1485, 2, 2 }, |
20293 | | // Hexagon::V6_vunpackh - 448 |
20294 | | {8487, 1487, 2, 2 }, |
20295 | | // Hexagon::V6_vunpackoh - 449 |
20296 | | {8505, 1489, 3, 3 }, |
20297 | | // Hexagon::V6_vunpackub - 450 |
20298 | | {8525, 1492, 2, 2 }, |
20299 | | // Hexagon::V6_vunpackuh - 451 |
20300 | | {8544, 1494, 2, 2 }, |
20301 | | // Hexagon::V6_vxor - 452 |
20302 | | {8269, 1496, 3, 3 }, |
20303 | | // Hexagon::V6_vzb - 453 |
20304 | | {8563, 1499, 2, 2 }, |
20305 | | // Hexagon::V6_vzh - 454 |
20306 | | {8578, 1501, 2, 2 }, |
20307 | | // Hexagon::V6_zLd_ai - 455 |
20308 | | {8593, 1503, 2, 2 }, |
20309 | | // Hexagon::V6_zLd_pred_ai - 456 |
20310 | | {8606, 1505, 3, 3 }, |
20311 | | // Hexagon::Y2_crswap0 - 457 |
20312 | | {8627, 1508, 2, 1 }, |
20313 | | // Hexagon::Y2_dcfetchbo - 458 |
20314 | | {8642, 1509, 2, 2 }, |
20315 | | }; |
20316 | | |
20317 | | static const AliasPatternCond Conds[] = { |
20318 | | // (A2_andir IntRegs:$Rd32, IntRegs:$Rs32, 255) - 0 |
20319 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20320 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20321 | | {AliasPatternCond::K_Imm, uint32_t(255)}, |
20322 | | // (A2_paddif IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0) - 3 |
20323 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20324 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20325 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20326 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20327 | | // (A2_paddifnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0) - 7 |
20328 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20329 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20330 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20331 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20332 | | // (A2_paddit IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0) - 11 |
20333 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20334 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20335 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20336 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20337 | | // (A2_padditnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0) - 15 |
20338 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20339 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20340 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20341 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20342 | | // (A2_subri IntRegs:$Rd32, 0, IntRegs:$Rs32) - 19 |
20343 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20344 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20345 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20346 | | // (A2_subri IntRegs:$Rd32, -1, IntRegs:$Rs32) - 22 |
20347 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20348 | | {AliasPatternCond::K_Imm, uint32_t(-1)}, |
20349 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20350 | | // (A2_vaddub DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32) - 25 |
20351 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20352 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20353 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20354 | | // (A2_vsubub DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32) - 28 |
20355 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20356 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20357 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20358 | | // (C2_cmpgt PredRegs:$Pd4, IntRegs:$Rt32, IntRegs:$Rs32) - 31 |
20359 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20360 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20361 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20362 | | // (C2_cmpgtu PredRegs:$Pd4, IntRegs:$Rt32, IntRegs:$Rs32) - 34 |
20363 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20364 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20365 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20366 | | // (C2_or PredRegs:$Pd4, PredRegs:$Ps4, PredRegs:$Ps4) - 37 |
20367 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20368 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20369 | | {AliasPatternCond::K_TiedReg, 1}, |
20370 | | // (J2_jumpf PredRegs:$Pu4, b30_2Imm:$Ii) - 40 |
20371 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20372 | | // (J2_jumprf PredRegs:$Pu4, IntRegs:$Rs32) - 41 |
20373 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20374 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20375 | | // (J2_jumprt PredRegs:$Pu4, IntRegs:$Rs32) - 43 |
20376 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20377 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20378 | | // (J2_jumpt PredRegs:$Pu4, b30_2Imm:$Ii) - 45 |
20379 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20380 | | // (J2_trap1 R0, u8_0Imm:$Ii) - 46 |
20381 | | {AliasPatternCond::K_Reg, Hexagon::R0}, |
20382 | | {AliasPatternCond::K_Ignore, 0}, |
20383 | | // (L2_deallocframe D15, R30) - 48 |
20384 | | {AliasPatternCond::K_Reg, Hexagon::D15}, |
20385 | | {AliasPatternCond::K_Reg, Hexagon::R30}, |
20386 | | // (L2_loadalignb_io DoubleRegs:$Ryy32, IntRegs:$Rs32, 0) - 50 |
20387 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20388 | | {AliasPatternCond::K_Ignore, 0}, |
20389 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20390 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20391 | | // (L2_loadalignh_io DoubleRegs:$Ryy32, IntRegs:$Rs32, 0) - 54 |
20392 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20393 | | {AliasPatternCond::K_Ignore, 0}, |
20394 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20395 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20396 | | // (L2_loadbsw2_io IntRegs:$Rd32, IntRegs:$Rs32, 0) - 58 |
20397 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20398 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20399 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20400 | | // (L2_loadbsw4_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0) - 61 |
20401 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20402 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20403 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20404 | | // (L2_loadbzw2_io IntRegs:$Rd32, IntRegs:$Rs32, 0) - 64 |
20405 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20406 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20407 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20408 | | // (L2_loadbzw4_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0) - 67 |
20409 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20410 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20411 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20412 | | // (L2_loadrb_io IntRegs:$Rd32, IntRegs:$Rs32, 0) - 70 |
20413 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20414 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20415 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20416 | | // (L2_loadrd_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0) - 73 |
20417 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20418 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20419 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20420 | | // (L2_loadrh_io IntRegs:$Rd32, IntRegs:$Rs32, 0) - 76 |
20421 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20422 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20423 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20424 | | // (L2_loadri_io IntRegs:$Rd32, IntRegs:$Rs32, 0) - 79 |
20425 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20426 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20427 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20428 | | // (L2_loadrub_io IntRegs:$Rd32, IntRegs:$Rs32, 0) - 82 |
20429 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20430 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20431 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20432 | | // (L2_loadruh_io IntRegs:$Rd32, IntRegs:$Rs32, 0) - 85 |
20433 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20434 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20435 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20436 | | // (L2_ploadrbf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 88 |
20437 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20438 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20439 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20440 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20441 | | // (L2_ploadrbfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 92 |
20442 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20443 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20444 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20445 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20446 | | // (L2_ploadrbt_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 96 |
20447 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20448 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20449 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20450 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20451 | | // (L2_ploadrbtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 100 |
20452 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20453 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20454 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20455 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20456 | | // (L2_ploadrdf_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 104 |
20457 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20458 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20459 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20460 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20461 | | // (L2_ploadrdfnew_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 108 |
20462 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20463 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20464 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20465 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20466 | | // (L2_ploadrdt_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 112 |
20467 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20468 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20469 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20470 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20471 | | // (L2_ploadrdtnew_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 116 |
20472 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20473 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20474 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20475 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20476 | | // (L2_ploadrhf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 120 |
20477 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20478 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20479 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20480 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20481 | | // (L2_ploadrhfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 124 |
20482 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20483 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20484 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20485 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20486 | | // (L2_ploadrht_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 128 |
20487 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20488 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20489 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20490 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20491 | | // (L2_ploadrhtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 132 |
20492 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20493 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20494 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20495 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20496 | | // (L2_ploadrif_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 136 |
20497 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20498 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20499 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20500 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20501 | | // (L2_ploadrifnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 140 |
20502 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20503 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20504 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20505 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20506 | | // (L2_ploadrit_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 144 |
20507 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20508 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20509 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20510 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20511 | | // (L2_ploadritnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 148 |
20512 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20513 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20514 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20515 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20516 | | // (L2_ploadrubf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 152 |
20517 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20518 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20519 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20520 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20521 | | // (L2_ploadrubfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 156 |
20522 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20523 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20524 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20525 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20526 | | // (L2_ploadrubt_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 160 |
20527 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20528 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20529 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20530 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20531 | | // (L2_ploadrubtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 164 |
20532 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20533 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20534 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20535 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20536 | | // (L2_ploadruhf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 168 |
20537 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20538 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20539 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20540 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20541 | | // (L2_ploadruhfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 172 |
20542 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20543 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20544 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20545 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20546 | | // (L2_ploadruht_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 176 |
20547 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20548 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20549 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20550 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20551 | | // (L2_ploadruhtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 180 |
20552 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20553 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20554 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20555 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20556 | | // (L4_add_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 184 |
20557 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20558 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20559 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20560 | | // (L4_add_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 187 |
20561 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20562 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20563 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20564 | | // (L4_add_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 190 |
20565 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20566 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20567 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20568 | | // (L4_and_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 193 |
20569 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20570 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20571 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20572 | | // (L4_and_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 196 |
20573 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20574 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20575 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20576 | | // (L4_and_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 199 |
20577 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20578 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20579 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20580 | | // (L4_iadd_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 202 |
20581 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20582 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20583 | | // (L4_iadd_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 204 |
20584 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20585 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20586 | | // (L4_iadd_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 206 |
20587 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20588 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20589 | | // (L4_iand_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 208 |
20590 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20591 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20592 | | // (L4_iand_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 210 |
20593 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20594 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20595 | | // (L4_iand_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 212 |
20596 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20597 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20598 | | // (L4_ior_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 214 |
20599 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20600 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20601 | | // (L4_ior_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 216 |
20602 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20603 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20604 | | // (L4_ior_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 218 |
20605 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20606 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20607 | | // (L4_isub_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 220 |
20608 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20609 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20610 | | // (L4_isub_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 222 |
20611 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20612 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20613 | | // (L4_isub_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 224 |
20614 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20615 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20616 | | // (L4_or_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 226 |
20617 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20618 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20619 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20620 | | // (L4_or_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 229 |
20621 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20622 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20623 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20624 | | // (L4_or_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 232 |
20625 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20626 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20627 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20628 | | // (L4_return D15, R30) - 235 |
20629 | | {AliasPatternCond::K_Reg, Hexagon::D15}, |
20630 | | {AliasPatternCond::K_Reg, Hexagon::R30}, |
20631 | | // (L4_return_f D15, PredRegs:$Pv4, R30) - 237 |
20632 | | {AliasPatternCond::K_Reg, Hexagon::D15}, |
20633 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20634 | | {AliasPatternCond::K_Reg, Hexagon::R30}, |
20635 | | // (L4_return_fnew_pnt D15, PredRegs:$Pv4, R30) - 240 |
20636 | | {AliasPatternCond::K_Reg, Hexagon::D15}, |
20637 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20638 | | {AliasPatternCond::K_Reg, Hexagon::R30}, |
20639 | | // (L4_return_fnew_pt D15, PredRegs:$Pv4, R30) - 243 |
20640 | | {AliasPatternCond::K_Reg, Hexagon::D15}, |
20641 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20642 | | {AliasPatternCond::K_Reg, Hexagon::R30}, |
20643 | | // (L4_return_t D15, PredRegs:$Pv4, R30) - 246 |
20644 | | {AliasPatternCond::K_Reg, Hexagon::D15}, |
20645 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20646 | | {AliasPatternCond::K_Reg, Hexagon::R30}, |
20647 | | // (L4_return_tnew_pnt D15, PredRegs:$Pv4, R30) - 249 |
20648 | | {AliasPatternCond::K_Reg, Hexagon::D15}, |
20649 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20650 | | {AliasPatternCond::K_Reg, Hexagon::R30}, |
20651 | | // (L4_return_tnew_pt D15, PredRegs:$Pv4, R30) - 252 |
20652 | | {AliasPatternCond::K_Reg, Hexagon::D15}, |
20653 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20654 | | {AliasPatternCond::K_Reg, Hexagon::R30}, |
20655 | | // (L4_sub_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 255 |
20656 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20657 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20658 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20659 | | // (L4_sub_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 258 |
20660 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20661 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20662 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20663 | | // (L4_sub_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 261 |
20664 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20665 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20666 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20667 | | // (M2_mpyi IntRegs:$Rd32, IntRegs:$Rs32, IntRegs:$Rt32) - 264 |
20668 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20669 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20670 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20671 | | // (M7_dcmpyrwc DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32) - 267 |
20672 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20673 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20674 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20675 | | // (M7_dcmpyrwc_acc DoubleRegs:$Rxx32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32) - 270 |
20676 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20677 | | {AliasPatternCond::K_Ignore, 0}, |
20678 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20679 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20680 | | // (S2_allocframe R29, u11_3Imm:$Ii) - 274 |
20681 | | {AliasPatternCond::K_Reg, Hexagon::R29}, |
20682 | | {AliasPatternCond::K_Ignore, 0}, |
20683 | | // (S2_pstorerbf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 276 |
20684 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20685 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20686 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20687 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20688 | | // (S2_pstorerbnewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 280 |
20689 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20690 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20691 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20692 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20693 | | // (S2_pstorerbnewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 284 |
20694 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20695 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20696 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20697 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20698 | | // (S2_pstorerbt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 288 |
20699 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20700 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20701 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20702 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20703 | | // (S2_pstorerdf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32) - 292 |
20704 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20705 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20706 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20707 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20708 | | // (S2_pstorerdt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32) - 296 |
20709 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20710 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20711 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20712 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20713 | | // (S2_pstorerff_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 300 |
20714 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20715 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20716 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20717 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20718 | | // (S2_pstorerft_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 304 |
20719 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20720 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20721 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20722 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20723 | | // (S2_pstorerhf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 308 |
20724 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20725 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20726 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20727 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20728 | | // (S2_pstorerhnewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 312 |
20729 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20730 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20731 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20732 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20733 | | // (S2_pstorerhnewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 316 |
20734 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20735 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20736 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20737 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20738 | | // (S2_pstorerht_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 320 |
20739 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20740 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20741 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20742 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20743 | | // (S2_pstorerif_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 324 |
20744 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20745 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20746 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20747 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20748 | | // (S2_pstorerinewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 328 |
20749 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20750 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20751 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20752 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20753 | | // (S2_pstorerinewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 332 |
20754 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20755 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20756 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20757 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20758 | | // (S2_pstorerit_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 336 |
20759 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20760 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20761 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20762 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20763 | | // (S2_storerb_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 340 |
20764 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20765 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20766 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20767 | | // (S2_storerbnew_io IntRegs:$Rs32, 0, IntRegs:$Nt8) - 343 |
20768 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20769 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20770 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20771 | | // (S2_storerd_io IntRegs:$Rs32, 0, DoubleRegs:$Rtt32) - 346 |
20772 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20773 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20774 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20775 | | // (S2_storerf_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 349 |
20776 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20777 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20778 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20779 | | // (S2_storerh_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 352 |
20780 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20781 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20782 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20783 | | // (S2_storerhnew_io IntRegs:$Rs32, 0, IntRegs:$Nt8) - 355 |
20784 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20785 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20786 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20787 | | // (S2_storeri_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 358 |
20788 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20789 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20790 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20791 | | // (S2_storerinew_io IntRegs:$Rs32, 0, IntRegs:$Nt8) - 361 |
20792 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20793 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20794 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20795 | | // (S2_tableidxb IntRegs:$Rx32, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II) - 364 |
20796 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20797 | | {AliasPatternCond::K_Ignore, 0}, |
20798 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20799 | | {AliasPatternCond::K_Ignore, 0}, |
20800 | | // (S4_pstorerbfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 368 |
20801 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20802 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20803 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20804 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20805 | | // (S4_pstorerbnewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 372 |
20806 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20807 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20808 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20809 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20810 | | // (S4_pstorerbnewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 376 |
20811 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20812 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20813 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20814 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20815 | | // (S4_pstorerbtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 380 |
20816 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20817 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20818 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20819 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20820 | | // (S4_pstorerdfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32) - 384 |
20821 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20822 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20823 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20824 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20825 | | // (S4_pstorerdtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32) - 388 |
20826 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20827 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20828 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20829 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
20830 | | // (S4_pstorerffnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 392 |
20831 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20832 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20833 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20834 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20835 | | // (S4_pstorerftnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 396 |
20836 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20837 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20838 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20839 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20840 | | // (S4_pstorerhfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 400 |
20841 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20842 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20843 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20844 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20845 | | // (S4_pstorerhnewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 404 |
20846 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20847 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20848 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20849 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20850 | | // (S4_pstorerhnewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 408 |
20851 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20852 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20853 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20854 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20855 | | // (S4_pstorerhtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 412 |
20856 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20857 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20858 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20859 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20860 | | // (S4_pstorerifnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 416 |
20861 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20862 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20863 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20864 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20865 | | // (S4_pstorerinewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 420 |
20866 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20867 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20868 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20869 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20870 | | // (S4_pstorerinewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 424 |
20871 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20872 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20873 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20874 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20875 | | // (S4_pstoreritnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 428 |
20876 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20877 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20878 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20879 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20880 | | // (S4_storeirb_io IntRegs:$Rs32, 0, s32_0Imm:$II) - 432 |
20881 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20882 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20883 | | // (S4_storeirbf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 434 |
20884 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20885 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20886 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20887 | | // (S4_storeirbfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 437 |
20888 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20889 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20890 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20891 | | // (S4_storeirbt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 440 |
20892 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20893 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20894 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20895 | | // (S4_storeirbtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 443 |
20896 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20897 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20898 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20899 | | // (S4_storeirh_io IntRegs:$Rs32, 0, s32_0Imm:$II) - 446 |
20900 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20901 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20902 | | // (S4_storeirhf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 448 |
20903 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20904 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20905 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20906 | | // (S4_storeirhfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 451 |
20907 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20908 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20909 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20910 | | // (S4_storeirht_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 454 |
20911 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20912 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20913 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20914 | | // (S4_storeirhtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 457 |
20915 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20916 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20917 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20918 | | // (S4_storeiri_io IntRegs:$Rs32, 0, s32_0Imm:$II) - 460 |
20919 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20920 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20921 | | // (S4_storeirif_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 462 |
20922 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20923 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20924 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20925 | | // (S4_storeirifnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 465 |
20926 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20927 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20928 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20929 | | // (S4_storeirit_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 468 |
20930 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20931 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20932 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20933 | | // (S4_storeiritnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 471 |
20934 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20935 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20936 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20937 | | // (V6_extractw IntRegs:$Rd32, HvxVR:$Vu32, IntRegs:$Rs32) - 474 |
20938 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20939 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
20940 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20941 | | // (V6_v6mpyhubs10 HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii) - 477 |
20942 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
20943 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
20944 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
20945 | | // (V6_v6mpyvubs10 HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii) - 480 |
20946 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
20947 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
20948 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
20949 | | // (V6_vL32Ub_ai HvxVR:$Vd32, IntRegs:$Rt32, 0) - 483 |
20950 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
20951 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20952 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20953 | | // (V6_vL32b_ai HvxVR:$Vd32, IntRegs:$Rt32, 0) - 486 |
20954 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
20955 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20956 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20957 | | // (V6_vL32b_cur_npred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0) - 489 |
20958 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
20959 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20960 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20961 | | {AliasPatternCond::K_Ignore, 0}, |
20962 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20963 | | // (V6_vL32b_cur_pred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0) - 494 |
20964 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
20965 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20966 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20967 | | {AliasPatternCond::K_Ignore, 0}, |
20968 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20969 | | // (V6_vL32b_npred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0) - 499 |
20970 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
20971 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20972 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20973 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20974 | | // (V6_vL32b_npred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0) - 503 |
20975 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
20976 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20977 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20978 | | {AliasPatternCond::K_Ignore, 0}, |
20979 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20980 | | // (V6_vL32b_nt_ai HvxVR:$Vd32, IntRegs:$Rt32, 0) - 508 |
20981 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
20982 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20983 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20984 | | // (V6_vL32b_nt_cur_npred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0) - 511 |
20985 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
20986 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20987 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20988 | | {AliasPatternCond::K_Ignore, 0}, |
20989 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20990 | | // (V6_vL32b_nt_cur_pred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0) - 516 |
20991 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
20992 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
20993 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20994 | | {AliasPatternCond::K_Ignore, 0}, |
20995 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
20996 | | // (V6_vL32b_nt_npred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0) - 521 |
20997 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
20998 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
20999 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21000 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
21001 | | // (V6_vL32b_nt_npred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0) - 525 |
21002 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21003 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21004 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
21005 | | {AliasPatternCond::K_Ignore, 0}, |
21006 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
21007 | | // (V6_vL32b_nt_pred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0) - 530 |
21008 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21009 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
21010 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21011 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
21012 | | // (V6_vL32b_nt_tmp_pred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0) - 534 |
21013 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21014 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
21015 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21016 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
21017 | | // (V6_vL32b_pred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0) - 538 |
21018 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21019 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
21020 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21021 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
21022 | | // (V6_vL32b_tmp_pred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0) - 542 |
21023 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21024 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
21025 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21026 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
21027 | | // (V6_vS32Ub_ai IntRegs:$Rt32, 0, HvxVR:$Vs32) - 546 |
21028 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21029 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
21030 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21031 | | // (V6_vS32Ub_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32) - 549 |
21032 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
21033 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21034 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
21035 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21036 | | // (V6_vS32Ub_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32) - 553 |
21037 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
21038 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21039 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
21040 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21041 | | // (V6_vS32b_ai IntRegs:$Rt32, 0, HvxVR:$Vs32) - 557 |
21042 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21043 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
21044 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21045 | | // (V6_vS32b_new_ai IntRegs:$Rt32, 0, HvxVR:$Os8) - 560 |
21046 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21047 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
21048 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21049 | | // (V6_vS32b_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32) - 563 |
21050 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
21051 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21052 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
21053 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21054 | | // (V6_vS32b_nqpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32) - 567 |
21055 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21056 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21057 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
21058 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21059 | | // (V6_vS32b_nt_ai IntRegs:$Rt32, 0, HvxVR:$Vs32) - 571 |
21060 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21061 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
21062 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21063 | | // (V6_vS32b_nt_new_ai IntRegs:$Rt32, 0, HvxVR:$Os8) - 574 |
21064 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21065 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
21066 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21067 | | // (V6_vS32b_nt_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32) - 577 |
21068 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
21069 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21070 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
21071 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21072 | | // (V6_vS32b_nt_nqpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32) - 581 |
21073 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21074 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21075 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
21076 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21077 | | // (V6_vS32b_nt_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32) - 585 |
21078 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
21079 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21080 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
21081 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21082 | | // (V6_vS32b_nt_qpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32) - 589 |
21083 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21084 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21085 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
21086 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21087 | | // (V6_vS32b_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32) - 593 |
21088 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
21089 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21090 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
21091 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21092 | | // (V6_vS32b_qpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32) - 597 |
21093 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21094 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21095 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
21096 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21097 | | // (V6_vabsb_sat HvxVR:$Vd32, HvxVR:$Vu32) - 601 |
21098 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21099 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21100 | | // (V6_vabsdiffh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 603 |
21101 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21102 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21103 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21104 | | // (V6_vabsdiffub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 606 |
21105 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21106 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21107 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21108 | | // (V6_vabsdiffuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 609 |
21109 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21110 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21111 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21112 | | // (V6_vabsdiffw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 612 |
21113 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21114 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21115 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21116 | | // (V6_vabsh_sat HvxVR:$Vd32, HvxVR:$Vu32) - 615 |
21117 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21118 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21119 | | // (V6_vabsw_sat HvxVR:$Vd32, HvxVR:$Vu32) - 617 |
21120 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21121 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21122 | | // (V6_vaddb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 619 |
21123 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21124 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21125 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21126 | | // (V6_vaddb_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 622 |
21127 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21128 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21129 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21130 | | // (V6_vaddbnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 625 |
21131 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21132 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21133 | | {AliasPatternCond::K_Ignore, 0}, |
21134 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21135 | | // (V6_vaddbq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 629 |
21136 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21137 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21138 | | {AliasPatternCond::K_Ignore, 0}, |
21139 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21140 | | // (V6_vaddbsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 633 |
21141 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21142 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21143 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21144 | | // (V6_vaddbsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 636 |
21145 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21146 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21147 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21148 | | // (V6_vaddh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 639 |
21149 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21150 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21151 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21152 | | // (V6_vaddh_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 642 |
21153 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21154 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21155 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21156 | | // (V6_vaddhnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 645 |
21157 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21158 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21159 | | {AliasPatternCond::K_Ignore, 0}, |
21160 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21161 | | // (V6_vaddhq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 649 |
21162 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21163 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21164 | | {AliasPatternCond::K_Ignore, 0}, |
21165 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21166 | | // (V6_vaddhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 653 |
21167 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21168 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21169 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21170 | | // (V6_vaddhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 656 |
21171 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21172 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21173 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21174 | | // (V6_vaddhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 659 |
21175 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21176 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21177 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21178 | | // (V6_vaddhw_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32) - 662 |
21179 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21180 | | {AliasPatternCond::K_Ignore, 0}, |
21181 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21182 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21183 | | // (V6_vaddubh HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 666 |
21184 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21185 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21186 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21187 | | // (V6_vaddubh_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32) - 669 |
21188 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21189 | | {AliasPatternCond::K_Ignore, 0}, |
21190 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21191 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21192 | | // (V6_vaddubsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 673 |
21193 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21194 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21195 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21196 | | // (V6_vaddubsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 676 |
21197 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21198 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21199 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21200 | | // (V6_vadduhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 679 |
21201 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21202 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21203 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21204 | | // (V6_vadduhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 682 |
21205 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21206 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21207 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21208 | | // (V6_vadduhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 685 |
21209 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21210 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21211 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21212 | | // (V6_vadduhw_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32) - 688 |
21213 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21214 | | {AliasPatternCond::K_Ignore, 0}, |
21215 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21216 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21217 | | // (V6_vadduwsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 692 |
21218 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21219 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21220 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21221 | | // (V6_vadduwsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 695 |
21222 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21223 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21224 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21225 | | // (V6_vaddw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 698 |
21226 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21227 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21228 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21229 | | // (V6_vaddw_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 701 |
21230 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21231 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21232 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21233 | | // (V6_vaddwnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 704 |
21234 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21235 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21236 | | {AliasPatternCond::K_Ignore, 0}, |
21237 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21238 | | // (V6_vaddwq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 708 |
21239 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21240 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21241 | | {AliasPatternCond::K_Ignore, 0}, |
21242 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21243 | | // (V6_vaddwsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 712 |
21244 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21245 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21246 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21247 | | // (V6_vaddwsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 715 |
21248 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21249 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21250 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21251 | | // (V6_vandnqrt HvxVR:$Vd32, HvxQR:$Qu4, IntRegs:$Rt32) - 718 |
21252 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21253 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21254 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21255 | | // (V6_vandnqrt_acc HvxVR:$Vx32, HvxQR:$Qu4, IntRegs:$Rt32) - 721 |
21256 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21257 | | {AliasPatternCond::K_Ignore, 0}, |
21258 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21259 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21260 | | // (V6_vandqrt HvxVR:$Vd32, HvxQR:$Qu4, IntRegs:$Rt32) - 725 |
21261 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21262 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21263 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21264 | | // (V6_vandqrt_acc HvxVR:$Vx32, HvxQR:$Qu4, IntRegs:$Rt32) - 728 |
21265 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21266 | | {AliasPatternCond::K_Ignore, 0}, |
21267 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21268 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21269 | | // (V6_vandvrt HvxQR:$Qd4, HvxVR:$Vu32, IntRegs:$Rt32) - 732 |
21270 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21271 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21272 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21273 | | // (V6_vandvrt_acc HvxQR:$Qx4, HvxVR:$Vu32, IntRegs:$Rt32) - 735 |
21274 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21275 | | {AliasPatternCond::K_Ignore, 0}, |
21276 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21277 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21278 | | // (V6_vaslh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 739 |
21279 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21280 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21281 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21282 | | // (V6_vaslh_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 742 |
21283 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21284 | | {AliasPatternCond::K_Ignore, 0}, |
21285 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21286 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21287 | | // (V6_vaslhv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 746 |
21288 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21289 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21290 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21291 | | // (V6_vaslw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 749 |
21292 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21293 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21294 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21295 | | // (V6_vaslw_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 752 |
21296 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21297 | | {AliasPatternCond::K_Ignore, 0}, |
21298 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21299 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21300 | | // (V6_vaslwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 756 |
21301 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21302 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21303 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21304 | | // (V6_vasr_into HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32) - 759 |
21305 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21306 | | {AliasPatternCond::K_Ignore, 0}, |
21307 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21308 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21309 | | // (V6_vasrh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 763 |
21310 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21311 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21312 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21313 | | // (V6_vasrh_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 766 |
21314 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21315 | | {AliasPatternCond::K_Ignore, 0}, |
21316 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21317 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21318 | | // (V6_vasrhv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 770 |
21319 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21320 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21321 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21322 | | // (V6_vasrw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 773 |
21323 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21324 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21325 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21326 | | // (V6_vasrw_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 776 |
21327 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21328 | | {AliasPatternCond::K_Ignore, 0}, |
21329 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21330 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21331 | | // (V6_vasrwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 780 |
21332 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21333 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21334 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21335 | | // (V6_vavgb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 783 |
21336 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21337 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21338 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21339 | | // (V6_vavgbrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 786 |
21340 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21341 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21342 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21343 | | // (V6_vavgh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 789 |
21344 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21345 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21346 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21347 | | // (V6_vavghrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 792 |
21348 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21349 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21350 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21351 | | // (V6_vavgub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 795 |
21352 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21353 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21354 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21355 | | // (V6_vavgubrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 798 |
21356 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21357 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21358 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21359 | | // (V6_vavguh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 801 |
21360 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21361 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21362 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21363 | | // (V6_vavguhrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 804 |
21364 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21365 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21366 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21367 | | // (V6_vavguw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 807 |
21368 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21369 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21370 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21371 | | // (V6_vavguwrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 810 |
21372 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21373 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21374 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21375 | | // (V6_vavgw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 813 |
21376 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21377 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21378 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21379 | | // (V6_vavgwrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 816 |
21380 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21381 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21382 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21383 | | // (V6_vcl0h HvxVR:$Vd32, HvxVR:$Vu32) - 819 |
21384 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21385 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21386 | | // (V6_vcl0w HvxVR:$Vd32, HvxVR:$Vu32) - 821 |
21387 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21388 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21389 | | // (V6_vdealb HvxVR:$Vd32, HvxVR:$Vu32) - 823 |
21390 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21391 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21392 | | // (V6_vdealb4w HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 825 |
21393 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21394 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21395 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21396 | | // (V6_vdealh HvxVR:$Vd32, HvxVR:$Vu32) - 828 |
21397 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21398 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21399 | | // (V6_vdmpybus HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 830 |
21400 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21401 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21402 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21403 | | // (V6_vdmpybus_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 833 |
21404 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21405 | | {AliasPatternCond::K_Ignore, 0}, |
21406 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21407 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21408 | | // (V6_vdmpybus_dv HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 837 |
21409 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21410 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21411 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21412 | | // (V6_vdmpybus_dv_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 840 |
21413 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21414 | | {AliasPatternCond::K_Ignore, 0}, |
21415 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21416 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21417 | | // (V6_vdmpyhb HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 844 |
21418 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21419 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21420 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21421 | | // (V6_vdmpyhb_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 847 |
21422 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21423 | | {AliasPatternCond::K_Ignore, 0}, |
21424 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21425 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21426 | | // (V6_vdmpyhb_dv HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 851 |
21427 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21428 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21429 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21430 | | // (V6_vdmpyhb_dv_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 854 |
21431 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21432 | | {AliasPatternCond::K_Ignore, 0}, |
21433 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21434 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21435 | | // (V6_vdmpyhisat HvxVR:$Vd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 858 |
21436 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21437 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21438 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21439 | | // (V6_vdmpyhisat_acc HvxVR:$Vx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 861 |
21440 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21441 | | {AliasPatternCond::K_Ignore, 0}, |
21442 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21443 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21444 | | // (V6_vdmpyhsat HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 865 |
21445 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21446 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21447 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21448 | | // (V6_vdmpyhsat_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 868 |
21449 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21450 | | {AliasPatternCond::K_Ignore, 0}, |
21451 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21452 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21453 | | // (V6_vdmpyhsuisat HvxVR:$Vd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 872 |
21454 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21455 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21456 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21457 | | // (V6_vdmpyhsuisat_acc HvxVR:$Vx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 875 |
21458 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21459 | | {AliasPatternCond::K_Ignore, 0}, |
21460 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21461 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21462 | | // (V6_vdmpyhsusat HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 879 |
21463 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21464 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21465 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21466 | | // (V6_vdmpyhsusat_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 882 |
21467 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21468 | | {AliasPatternCond::K_Ignore, 0}, |
21469 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21470 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21471 | | // (V6_vdmpyhvsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 886 |
21472 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21473 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21474 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21475 | | // (V6_vdmpyhvsat_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32) - 889 |
21476 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21477 | | {AliasPatternCond::K_Ignore, 0}, |
21478 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21479 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21480 | | // (V6_vdsaduh HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 893 |
21481 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21482 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21483 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21484 | | // (V6_vdsaduh_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 896 |
21485 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21486 | | {AliasPatternCond::K_Ignore, 0}, |
21487 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21488 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21489 | | // (V6_veqb HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32) - 900 |
21490 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21491 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21492 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21493 | | // (V6_veqb_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32) - 903 |
21494 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21495 | | {AliasPatternCond::K_Ignore, 0}, |
21496 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21497 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21498 | | // (V6_veqb_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32) - 907 |
21499 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21500 | | {AliasPatternCond::K_Ignore, 0}, |
21501 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21502 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21503 | | // (V6_veqb_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32) - 911 |
21504 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21505 | | {AliasPatternCond::K_Ignore, 0}, |
21506 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21507 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21508 | | // (V6_veqh HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32) - 915 |
21509 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21510 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21511 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21512 | | // (V6_veqh_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32) - 918 |
21513 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21514 | | {AliasPatternCond::K_Ignore, 0}, |
21515 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21516 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21517 | | // (V6_veqh_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32) - 922 |
21518 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21519 | | {AliasPatternCond::K_Ignore, 0}, |
21520 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21521 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21522 | | // (V6_veqh_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32) - 926 |
21523 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21524 | | {AliasPatternCond::K_Ignore, 0}, |
21525 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21526 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21527 | | // (V6_veqw HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32) - 930 |
21528 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21529 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21530 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21531 | | // (V6_veqw_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32) - 933 |
21532 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21533 | | {AliasPatternCond::K_Ignore, 0}, |
21534 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21535 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21536 | | // (V6_veqw_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32) - 937 |
21537 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21538 | | {AliasPatternCond::K_Ignore, 0}, |
21539 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21540 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21541 | | // (V6_veqw_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32) - 941 |
21542 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
21543 | | {AliasPatternCond::K_Ignore, 0}, |
21544 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21545 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21546 | | // (V6_vlsrh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 945 |
21547 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21548 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21549 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21550 | | // (V6_vlsrhv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 948 |
21551 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21552 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21553 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21554 | | // (V6_vlsrw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 951 |
21555 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21556 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21557 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21558 | | // (V6_vlsrwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 954 |
21559 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21560 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21561 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21562 | | // (V6_vmaxb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 957 |
21563 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21564 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21565 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21566 | | // (V6_vmaxh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 960 |
21567 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21568 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21569 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21570 | | // (V6_vmaxub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 963 |
21571 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21572 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21573 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21574 | | // (V6_vmaxuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 966 |
21575 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21576 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21577 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21578 | | // (V6_vmaxw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 969 |
21579 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21580 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21581 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21582 | | // (V6_vminb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 972 |
21583 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21584 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21585 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21586 | | // (V6_vminh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 975 |
21587 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21588 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21589 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21590 | | // (V6_vminub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 978 |
21591 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21592 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21593 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21594 | | // (V6_vminuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 981 |
21595 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21596 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21597 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21598 | | // (V6_vminw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 984 |
21599 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21600 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21601 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21602 | | // (V6_vmpabus HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 987 |
21603 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21604 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21605 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21606 | | // (V6_vmpabus_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 990 |
21607 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21608 | | {AliasPatternCond::K_Ignore, 0}, |
21609 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21610 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21611 | | // (V6_vmpabusv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 994 |
21612 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21613 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21614 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21615 | | // (V6_vmpabuu HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 997 |
21616 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21617 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21618 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21619 | | // (V6_vmpabuu_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 1000 |
21620 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21621 | | {AliasPatternCond::K_Ignore, 0}, |
21622 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21623 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21624 | | // (V6_vmpabuuv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 1004 |
21625 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21626 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21627 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21628 | | // (V6_vmpahb HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 1007 |
21629 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21630 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21631 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21632 | | // (V6_vmpahb_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 1010 |
21633 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21634 | | {AliasPatternCond::K_Ignore, 0}, |
21635 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21636 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21637 | | // (V6_vmpauhb HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 1014 |
21638 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21639 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21640 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21641 | | // (V6_vmpauhb_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 1017 |
21642 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21643 | | {AliasPatternCond::K_Ignore, 0}, |
21644 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21645 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21646 | | // (V6_vmpybus HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1021 |
21647 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21648 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21649 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21650 | | // (V6_vmpybus_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32) - 1024 |
21651 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21652 | | {AliasPatternCond::K_Ignore, 0}, |
21653 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21654 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21655 | | // (V6_vmpybusv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1028 |
21656 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21657 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21658 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21659 | | // (V6_vmpybusv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1031 |
21660 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21661 | | {AliasPatternCond::K_Ignore, 0}, |
21662 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21663 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21664 | | // (V6_vmpybv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1035 |
21665 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21666 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21667 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21668 | | // (V6_vmpybv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1038 |
21669 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21670 | | {AliasPatternCond::K_Ignore, 0}, |
21671 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21672 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21673 | | // (V6_vmpyewuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1042 |
21674 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21675 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21676 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21677 | | // (V6_vmpyh HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1045 |
21678 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21679 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21680 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21681 | | // (V6_vmpyh_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32) - 1048 |
21682 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21683 | | {AliasPatternCond::K_Ignore, 0}, |
21684 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21685 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21686 | | // (V6_vmpyhsat_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32) - 1052 |
21687 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21688 | | {AliasPatternCond::K_Ignore, 0}, |
21689 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21690 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21691 | | // (V6_vmpyhsrs HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1056 |
21692 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21693 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21694 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21695 | | // (V6_vmpyhss HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1059 |
21696 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21697 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21698 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21699 | | // (V6_vmpyhus HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1062 |
21700 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21701 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21702 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21703 | | // (V6_vmpyhus_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1065 |
21704 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21705 | | {AliasPatternCond::K_Ignore, 0}, |
21706 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21707 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21708 | | // (V6_vmpyhv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1069 |
21709 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21710 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21711 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21712 | | // (V6_vmpyhv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1072 |
21713 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21714 | | {AliasPatternCond::K_Ignore, 0}, |
21715 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21716 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21717 | | // (V6_vmpyhvsrs HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1076 |
21718 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21719 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21720 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21721 | | // (V6_vmpyiewh_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1079 |
21722 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21723 | | {AliasPatternCond::K_Ignore, 0}, |
21724 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21725 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21726 | | // (V6_vmpyiewuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1083 |
21727 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21728 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21729 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21730 | | // (V6_vmpyiewuh_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1086 |
21731 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21732 | | {AliasPatternCond::K_Ignore, 0}, |
21733 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21734 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21735 | | // (V6_vmpyih HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1090 |
21736 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21737 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21738 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21739 | | // (V6_vmpyih_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1093 |
21740 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21741 | | {AliasPatternCond::K_Ignore, 0}, |
21742 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21743 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21744 | | // (V6_vmpyihb HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1097 |
21745 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21746 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21747 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21748 | | // (V6_vmpyihb_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 1100 |
21749 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21750 | | {AliasPatternCond::K_Ignore, 0}, |
21751 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21752 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21753 | | // (V6_vmpyiowh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1104 |
21754 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21755 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21756 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21757 | | // (V6_vmpyiwb HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1107 |
21758 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21759 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21760 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21761 | | // (V6_vmpyiwb_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 1110 |
21762 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21763 | | {AliasPatternCond::K_Ignore, 0}, |
21764 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21765 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21766 | | // (V6_vmpyiwh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1114 |
21767 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21768 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21769 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21770 | | // (V6_vmpyiwh_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 1117 |
21771 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21772 | | {AliasPatternCond::K_Ignore, 0}, |
21773 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21774 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21775 | | // (V6_vmpyiwub HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1121 |
21776 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21777 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21778 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21779 | | // (V6_vmpyiwub_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 1124 |
21780 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21781 | | {AliasPatternCond::K_Ignore, 0}, |
21782 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21783 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21784 | | // (V6_vmpyowh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1128 |
21785 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21786 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21787 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21788 | | // (V6_vmpyowh_rnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1131 |
21789 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21790 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21791 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21792 | | // (V6_vmpyub HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1134 |
21793 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21794 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21795 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21796 | | // (V6_vmpyub_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32) - 1137 |
21797 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21798 | | {AliasPatternCond::K_Ignore, 0}, |
21799 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21800 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21801 | | // (V6_vmpyubv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1141 |
21802 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21803 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21804 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21805 | | // (V6_vmpyubv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1144 |
21806 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21807 | | {AliasPatternCond::K_Ignore, 0}, |
21808 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21809 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21810 | | // (V6_vmpyuh HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1148 |
21811 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21812 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21813 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21814 | | // (V6_vmpyuh_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32) - 1151 |
21815 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21816 | | {AliasPatternCond::K_Ignore, 0}, |
21817 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21818 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21819 | | // (V6_vmpyuhv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1155 |
21820 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21821 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21822 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21823 | | // (V6_vmpyuhv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1158 |
21824 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21825 | | {AliasPatternCond::K_Ignore, 0}, |
21826 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21827 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21828 | | // (V6_vnavgb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1162 |
21829 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21830 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21831 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21832 | | // (V6_vnavgh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1165 |
21833 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21834 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21835 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21836 | | // (V6_vnavgub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1168 |
21837 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21838 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21839 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21840 | | // (V6_vnavgw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1171 |
21841 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21842 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21843 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21844 | | // (V6_vnormamth HvxVR:$Vd32, HvxVR:$Vu32) - 1174 |
21845 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21846 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21847 | | // (V6_vnormamtw HvxVR:$Vd32, HvxVR:$Vu32) - 1176 |
21848 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21849 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21850 | | // (V6_vpackeb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1178 |
21851 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21852 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21853 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21854 | | // (V6_vpackeh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1181 |
21855 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21856 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21857 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21858 | | // (V6_vpackhb_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1184 |
21859 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21860 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21861 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21862 | | // (V6_vpackhub_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1187 |
21863 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21864 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21865 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21866 | | // (V6_vpackob HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1190 |
21867 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21868 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21869 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21870 | | // (V6_vpackoh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1193 |
21871 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21872 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21873 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21874 | | // (V6_vpackwh_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1196 |
21875 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21876 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21877 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21878 | | // (V6_vpackwuh_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1199 |
21879 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21880 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21881 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21882 | | // (V6_vpopcounth HvxVR:$Vd32, HvxVR:$Vu32) - 1202 |
21883 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21884 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21885 | | // (V6_vrmpybub_rtt HvxWR:$Vdd32, HvxVR:$Vu32, DoubleRegs:$Rtt32) - 1204 |
21886 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21887 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21888 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
21889 | | // (V6_vrmpybub_rtt_acc HvxWR:$Vxx32, HvxVR:$Vu32, DoubleRegs:$Rtt32) - 1207 |
21890 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21891 | | {AliasPatternCond::K_Ignore, 0}, |
21892 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21893 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
21894 | | // (V6_vrmpybus HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1211 |
21895 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21896 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21897 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21898 | | // (V6_vrmpybus_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 1214 |
21899 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21900 | | {AliasPatternCond::K_Ignore, 0}, |
21901 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21902 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21903 | | // (V6_vrmpybusi HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii) - 1218 |
21904 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21905 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21906 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21907 | | // (V6_vrmpybusi_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii) - 1221 |
21908 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21909 | | {AliasPatternCond::K_Ignore, 0}, |
21910 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21911 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21912 | | // (V6_vrmpybusv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1225 |
21913 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21914 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21915 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21916 | | // (V6_vrmpybusv_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1228 |
21917 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21918 | | {AliasPatternCond::K_Ignore, 0}, |
21919 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21920 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21921 | | // (V6_vrmpybv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1232 |
21922 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21923 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21924 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21925 | | // (V6_vrmpybv_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1235 |
21926 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21927 | | {AliasPatternCond::K_Ignore, 0}, |
21928 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21929 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21930 | | // (V6_vrmpyub HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1239 |
21931 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21932 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21933 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21934 | | // (V6_vrmpyub_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 1242 |
21935 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21936 | | {AliasPatternCond::K_Ignore, 0}, |
21937 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21938 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21939 | | // (V6_vrmpyub_rtt HvxWR:$Vdd32, HvxVR:$Vu32, DoubleRegs:$Rtt32) - 1246 |
21940 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21941 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21942 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
21943 | | // (V6_vrmpyub_rtt_acc HvxWR:$Vxx32, HvxVR:$Vu32, DoubleRegs:$Rtt32) - 1249 |
21944 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21945 | | {AliasPatternCond::K_Ignore, 0}, |
21946 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21947 | | {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID}, |
21948 | | // (V6_vrmpyubi HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii) - 1253 |
21949 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21950 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21951 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21952 | | // (V6_vrmpyubi_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii) - 1256 |
21953 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21954 | | {AliasPatternCond::K_Ignore, 0}, |
21955 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21956 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21957 | | // (V6_vrmpyubv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1260 |
21958 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21959 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21960 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21961 | | // (V6_vrmpyubv_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1263 |
21962 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21963 | | {AliasPatternCond::K_Ignore, 0}, |
21964 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21965 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21966 | | // (V6_vrotr HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1267 |
21967 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21968 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21969 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21970 | | // (V6_vroundhb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1270 |
21971 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21972 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21973 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21974 | | // (V6_vroundhub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1273 |
21975 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21976 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21977 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21978 | | // (V6_vrounduhub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1276 |
21979 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21980 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21981 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21982 | | // (V6_vrounduwuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1279 |
21983 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21984 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21985 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21986 | | // (V6_vroundwh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1282 |
21987 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21988 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21989 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21990 | | // (V6_vroundwuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1285 |
21991 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21992 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21993 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
21994 | | // (V6_vrsadubi HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii) - 1288 |
21995 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21996 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
21997 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
21998 | | // (V6_vrsadubi_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii) - 1291 |
21999 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22000 | | {AliasPatternCond::K_Ignore, 0}, |
22001 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22002 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
22003 | | // (V6_vsathub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1295 |
22004 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22005 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22006 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22007 | | // (V6_vsatuwuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1298 |
22008 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22009 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22010 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22011 | | // (V6_vsatwh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1301 |
22012 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22013 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22014 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22015 | | // (V6_vsb HvxWR:$Vdd32, HvxVR:$Vu32) - 1304 |
22016 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22017 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22018 | | // (V6_vscattermh IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32) - 1306 |
22019 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
22020 | | {AliasPatternCond::K_RegClass, Hexagon::ModRegsRegClassID}, |
22021 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22022 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22023 | | // (V6_vscattermh_add IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32) - 1310 |
22024 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
22025 | | {AliasPatternCond::K_RegClass, Hexagon::ModRegsRegClassID}, |
22026 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22027 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22028 | | // (V6_vscattermhq HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32) - 1314 |
22029 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
22030 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
22031 | | {AliasPatternCond::K_RegClass, Hexagon::ModRegsRegClassID}, |
22032 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22033 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22034 | | // (V6_vscattermhw IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32) - 1319 |
22035 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
22036 | | {AliasPatternCond::K_RegClass, Hexagon::ModRegsRegClassID}, |
22037 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22038 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22039 | | // (V6_vscattermhw_add IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32) - 1323 |
22040 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
22041 | | {AliasPatternCond::K_RegClass, Hexagon::ModRegsRegClassID}, |
22042 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22043 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22044 | | // (V6_vscattermhwq HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32) - 1327 |
22045 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
22046 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
22047 | | {AliasPatternCond::K_RegClass, Hexagon::ModRegsRegClassID}, |
22048 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22049 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22050 | | // (V6_vscattermw IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32) - 1332 |
22051 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
22052 | | {AliasPatternCond::K_RegClass, Hexagon::ModRegsRegClassID}, |
22053 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22054 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22055 | | // (V6_vscattermw_add IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32) - 1336 |
22056 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
22057 | | {AliasPatternCond::K_RegClass, Hexagon::ModRegsRegClassID}, |
22058 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22059 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22060 | | // (V6_vscattermwq HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32) - 1340 |
22061 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
22062 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
22063 | | {AliasPatternCond::K_RegClass, Hexagon::ModRegsRegClassID}, |
22064 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22065 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22066 | | // (V6_vsh HvxWR:$Vdd32, HvxVR:$Vu32) - 1345 |
22067 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22068 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22069 | | // (V6_vshufeh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1347 |
22070 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22071 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22072 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22073 | | // (V6_vshuff HvxVR:$Vy32, HvxVR:$Vx32, IntRegs:$Rt32) - 1350 |
22074 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22075 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22076 | | {AliasPatternCond::K_Ignore, 0}, |
22077 | | {AliasPatternCond::K_Ignore, 0}, |
22078 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
22079 | | // (V6_vshuffb HvxVR:$Vd32, HvxVR:$Vu32) - 1355 |
22080 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22081 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22082 | | // (V6_vshuffeb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1357 |
22083 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22084 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22085 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22086 | | // (V6_vshuffh HvxVR:$Vd32, HvxVR:$Vu32) - 1360 |
22087 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22088 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22089 | | // (V6_vshuffob HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1362 |
22090 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22091 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22092 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22093 | | // (V6_vshufoeb HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1365 |
22094 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22095 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22096 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22097 | | // (V6_vshufoeh HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1368 |
22098 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22099 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22100 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22101 | | // (V6_vshufoh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1371 |
22102 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22103 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22104 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22105 | | // (V6_vsubb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1374 |
22106 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22107 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22108 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22109 | | // (V6_vsubb_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 1377 |
22110 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22111 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22112 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22113 | | // (V6_vsubbnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 1380 |
22114 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22115 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
22116 | | {AliasPatternCond::K_Ignore, 0}, |
22117 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22118 | | // (V6_vsubbq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 1384 |
22119 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22120 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
22121 | | {AliasPatternCond::K_Ignore, 0}, |
22122 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22123 | | // (V6_vsubbsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1388 |
22124 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22125 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22126 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22127 | | // (V6_vsubbsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 1391 |
22128 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22129 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22130 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22131 | | // (V6_vsubh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1394 |
22132 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22133 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22134 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22135 | | // (V6_vsubh_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 1397 |
22136 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22137 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22138 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22139 | | // (V6_vsubhnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 1400 |
22140 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22141 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
22142 | | {AliasPatternCond::K_Ignore, 0}, |
22143 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22144 | | // (V6_vsubhq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 1404 |
22145 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22146 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
22147 | | {AliasPatternCond::K_Ignore, 0}, |
22148 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22149 | | // (V6_vsubhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1408 |
22150 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22151 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22152 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22153 | | // (V6_vsubhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 1411 |
22154 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22155 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22156 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22157 | | // (V6_vsubhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1414 |
22158 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22159 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22160 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22161 | | // (V6_vsububh HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1417 |
22162 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22163 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22164 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22165 | | // (V6_vsububsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1420 |
22166 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22167 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22168 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22169 | | // (V6_vsububsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 1423 |
22170 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22171 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22172 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22173 | | // (V6_vsubuhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1426 |
22174 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22175 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22176 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22177 | | // (V6_vsubuhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 1429 |
22178 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22179 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22180 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22181 | | // (V6_vsubuhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1432 |
22182 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22183 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22184 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22185 | | // (V6_vsubuwsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1435 |
22186 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22187 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22188 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22189 | | // (V6_vsubuwsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 1438 |
22190 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22191 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22192 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22193 | | // (V6_vsubw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1441 |
22194 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22195 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22196 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22197 | | // (V6_vsubw_dv HvxWR:$Vdd32, W15, W15) - 1444 |
22198 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22199 | | {AliasPatternCond::K_Reg, Hexagon::W15}, |
22200 | | {AliasPatternCond::K_Reg, Hexagon::W15}, |
22201 | | // (V6_vsubw_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 1447 |
22202 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22203 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22204 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22205 | | // (V6_vsubwnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 1450 |
22206 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22207 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
22208 | | {AliasPatternCond::K_Ignore, 0}, |
22209 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22210 | | // (V6_vsubwq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 1454 |
22211 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22212 | | {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID}, |
22213 | | {AliasPatternCond::K_Ignore, 0}, |
22214 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22215 | | // (V6_vsubwsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1458 |
22216 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22217 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22218 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22219 | | // (V6_vsubwsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 1461 |
22220 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22221 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22222 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22223 | | // (V6_vtmpyb HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 1464 |
22224 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22225 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22226 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
22227 | | // (V6_vtmpyb_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 1467 |
22228 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22229 | | {AliasPatternCond::K_Ignore, 0}, |
22230 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22231 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
22232 | | // (V6_vtmpybus HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 1471 |
22233 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22234 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22235 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
22236 | | // (V6_vtmpybus_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 1474 |
22237 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22238 | | {AliasPatternCond::K_Ignore, 0}, |
22239 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22240 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
22241 | | // (V6_vtmpyhb HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 1478 |
22242 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22243 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22244 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
22245 | | // (V6_vtmpyhb_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 1481 |
22246 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22247 | | {AliasPatternCond::K_Ignore, 0}, |
22248 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22249 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
22250 | | // (V6_vunpackb HvxWR:$Vdd32, HvxVR:$Vu32) - 1485 |
22251 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22252 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22253 | | // (V6_vunpackh HvxWR:$Vdd32, HvxVR:$Vu32) - 1487 |
22254 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22255 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22256 | | // (V6_vunpackoh HvxWR:$Vxx32, HvxVR:$Vu32) - 1489 |
22257 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22258 | | {AliasPatternCond::K_Ignore, 0}, |
22259 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22260 | | // (V6_vunpackub HvxWR:$Vdd32, HvxVR:$Vu32) - 1492 |
22261 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22262 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22263 | | // (V6_vunpackuh HvxWR:$Vdd32, HvxVR:$Vu32) - 1494 |
22264 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22265 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22266 | | // (V6_vxor HvxVR:$Vd32, HvxVR:$Vd32, HvxVR:$Vd32) - 1496 |
22267 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22268 | | {AliasPatternCond::K_TiedReg, 0}, |
22269 | | {AliasPatternCond::K_TiedReg, 0}, |
22270 | | // (V6_vzb HvxWR:$Vdd32, HvxVR:$Vu32) - 1499 |
22271 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22272 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22273 | | // (V6_vzh HvxWR:$Vdd32, HvxVR:$Vu32) - 1501 |
22274 | | {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID}, |
22275 | | {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID}, |
22276 | | // (V6_zLd_ai IntRegs:$Rt32, 0) - 1503 |
22277 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
22278 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
22279 | | // (V6_zLd_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0) - 1505 |
22280 | | {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID}, |
22281 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
22282 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
22283 | | // (Y2_crswap0 IntRegs:$Rx32) - 1508 |
22284 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
22285 | | // (Y2_dcfetchbo IntRegs:$Rs32, 0) - 1509 |
22286 | | {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID}, |
22287 | | {AliasPatternCond::K_Imm, uint32_t(0)}, |
22288 | | }; |
22289 | | |
22290 | | static const char AsmStrings[] = |
22291 | | /* 0 */ "$\x01 = zxtb($\x02)\0" |
22292 | | /* 14 */ "if (!$\x02) $\x01 = $\x03\0" |
22293 | | /* 31 */ "if (!$\x02.new) $\x01 = $\x03\0" |
22294 | | /* 52 */ "if ($\x02) $\x01 = $\x03\0" |
22295 | | /* 68 */ "if ($\x02.new) $\x01 = $\x03\0" |
22296 | | /* 88 */ "$\x01 = neg($\x03)\0" |
22297 | | /* 101 */ "$\x01 = not($\x03)\0" |
22298 | | /* 114 */ "$\x01 = vaddb($\x02,$\x03)\0" |
22299 | | /* 132 */ "$\x01 = vsubb($\x02,$\x03)\0" |
22300 | | /* 150 */ "$\x01 = cmp.lt($\x03,$\x02)\0" |
22301 | | /* 169 */ "$\x01 = cmp.ltu($\x03,$\x02)\0" |
22302 | | /* 189 */ "$\x01 = $\x02\0" |
22303 | | /* 197 */ "if (!$\x01) jump $\xFF\x02\x01\0" |
22304 | | /* 216 */ "if (!$\x01) jumpr $\x02\0" |
22305 | | /* 234 */ "if ($\x01) jumpr $\x02\0" |
22306 | | /* 251 */ "if ($\x01) jump $\xFF\x02\x01\0" |
22307 | | /* 269 */ "trap1(#$\x03)\0" |
22308 | | /* 280 */ "deallocframe\0" |
22309 | | /* 293 */ "$\x01 = memb_fifo($\x03)\0" |
22310 | | /* 312 */ "$\x01 = memh_fifo($\x03)\0" |
22311 | | /* 331 */ "$\x01 = membh($\x02)\0" |
22312 | | /* 346 */ "$\x01 = memubh($\x02)\0" |
22313 | | /* 362 */ "$\x01 = memb($\x02)\0" |
22314 | | /* 376 */ "$\x01 = memd($\x02)\0" |
22315 | | /* 390 */ "$\x01 = memh($\x02)\0" |
22316 | | /* 404 */ "$\x01 = memw($\x02)\0" |
22317 | | /* 418 */ "$\x01 = memub($\x02)\0" |
22318 | | /* 433 */ "$\x01 = memuh($\x02)\0" |
22319 | | /* 448 */ "if (!$\x02) $\x01 = memb($\x03)\0" |
22320 | | /* 471 */ "if (!$\x02.new) $\x01 = memb($\x03)\0" |
22321 | | /* 498 */ "if ($\x02) $\x01 = memb($\x03)\0" |
22322 | | /* 520 */ "if ($\x02.new) $\x01 = memb($\x03)\0" |
22323 | | /* 546 */ "if (!$\x02) $\x01 = memd($\x03)\0" |
22324 | | /* 569 */ "if (!$\x02.new) $\x01 = memd($\x03)\0" |
22325 | | /* 596 */ "if ($\x02) $\x01 = memd($\x03)\0" |
22326 | | /* 618 */ "if ($\x02.new) $\x01 = memd($\x03)\0" |
22327 | | /* 644 */ "if (!$\x02) $\x01 = memh($\x03)\0" |
22328 | | /* 667 */ "if (!$\x02.new) $\x01 = memh($\x03)\0" |
22329 | | /* 694 */ "if ($\x02) $\x01 = memh($\x03)\0" |
22330 | | /* 716 */ "if ($\x02.new) $\x01 = memh($\x03)\0" |
22331 | | /* 742 */ "if (!$\x02) $\x01 = memw($\x03)\0" |
22332 | | /* 765 */ "if (!$\x02.new) $\x01 = memw($\x03)\0" |
22333 | | /* 792 */ "if ($\x02) $\x01 = memw($\x03)\0" |
22334 | | /* 814 */ "if ($\x02.new) $\x01 = memw($\x03)\0" |
22335 | | /* 840 */ "if (!$\x02) $\x01 = memub($\x03)\0" |
22336 | | /* 864 */ "if (!$\x02.new) $\x01 = memub($\x03)\0" |
22337 | | /* 892 */ "if ($\x02) $\x01 = memub($\x03)\0" |
22338 | | /* 915 */ "if ($\x02.new) $\x01 = memub($\x03)\0" |
22339 | | /* 942 */ "if (!$\x02) $\x01 = memuh($\x03)\0" |
22340 | | /* 966 */ "if (!$\x02.new) $\x01 = memuh($\x03)\0" |
22341 | | /* 994 */ "if ($\x02) $\x01 = memuh($\x03)\0" |
22342 | | /* 1017 */ "if ($\x02.new) $\x01 = memuh($\x03)\0" |
22343 | | /* 1044 */ "memb($\x01) += $\x03\0" |
22344 | | /* 1059 */ "memh($\x01) += $\x03\0" |
22345 | | /* 1074 */ "memw($\x01) += $\x03\0" |
22346 | | /* 1089 */ "memb($\x01) &= $\x03\0" |
22347 | | /* 1104 */ "memh($\x01) &= $\x03\0" |
22348 | | /* 1119 */ "memw($\x01) &= $\x03\0" |
22349 | | /* 1134 */ "memb($\x01) += #$\x03\0" |
22350 | | /* 1150 */ "memh($\x01) += #$\x03\0" |
22351 | | /* 1166 */ "memw($\x01) += #$\x03\0" |
22352 | | /* 1182 */ "memb($\x01) = clrbit(#$\x03)\0" |
22353 | | /* 1205 */ "memh($\x01) = clrbit(#$\x03)\0" |
22354 | | /* 1228 */ "memw($\x01) = clrbit(#$\x03)\0" |
22355 | | /* 1251 */ "memb($\x01) = setbit(#$\x03)\0" |
22356 | | /* 1274 */ "memh($\x01) = setbit(#$\x03)\0" |
22357 | | /* 1297 */ "memw($\x01) = setbit(#$\x03)\0" |
22358 | | /* 1320 */ "memb($\x01) -= #$\x03\0" |
22359 | | /* 1336 */ "memh($\x01) -= #$\x03\0" |
22360 | | /* 1352 */ "memw($\x01) -= #$\x03\0" |
22361 | | /* 1368 */ "memb($\x01) |= $\x03\0" |
22362 | | /* 1383 */ "memh($\x01) |= $\x03\0" |
22363 | | /* 1398 */ "memw($\x01) |= $\x03\0" |
22364 | | /* 1413 */ "dealloc_return\0" |
22365 | | /* 1428 */ "if (!$\x02) dealloc_return\0" |
22366 | | /* 1452 */ "if (!$\x02.new) dealloc_return:nt\0" |
22367 | | /* 1483 */ "if (!$\x02.new) dealloc_return:t\0" |
22368 | | /* 1513 */ "if ($\x02) dealloc_return\0" |
22369 | | /* 1536 */ "if ($\x02.new) dealloc_return:nt\0" |
22370 | | /* 1566 */ "if ($\x02.new) dealloc_return:t\0" |
22371 | | /* 1595 */ "memb($\x01) -= $\x03\0" |
22372 | | /* 1610 */ "memh($\x01) -= $\x03\0" |
22373 | | /* 1625 */ "memw($\x01) -= $\x03\0" |
22374 | | /* 1640 */ "$\x01 = mpyui($\x02,$\x03)\0" |
22375 | | /* 1658 */ "$\x01 = vdmpyw($\x02,$\x03)\0" |
22376 | | /* 1677 */ "$\x01 += vdmpyw($\x03,$\x04)\0" |
22377 | | /* 1697 */ "allocframe(#$\x03)\0" |
22378 | | /* 1713 */ "if (!$\x01) memb($\x02) = $\x04\0" |
22379 | | /* 1736 */ "if (!$\x01) memb($\x02) = $\x04.new\0" |
22380 | | /* 1763 */ "if ($\x01) memb($\x02) = $\x04.new\0" |
22381 | | /* 1789 */ "if ($\x01) memb($\x02) = $\x04\0" |
22382 | | /* 1811 */ "if (!$\x01) memd($\x02) = $\x04\0" |
22383 | | /* 1834 */ "if ($\x01) memd($\x02) = $\x04\0" |
22384 | | /* 1856 */ "if (!$\x01) memh($\x02) = $\x04.h\0" |
22385 | | /* 1881 */ "if ($\x01) memh($\x02) = $\x04.h\0" |
22386 | | /* 1905 */ "if (!$\x01) memh($\x02) = $\x04\0" |
22387 | | /* 1928 */ "if (!$\x01) memh($\x02) = $\x04.new\0" |
22388 | | /* 1955 */ "if ($\x01) memh($\x02) = $\x04.new\0" |
22389 | | /* 1981 */ "if ($\x01) memh($\x02) = $\x04\0" |
22390 | | /* 2003 */ "if (!$\x01) memw($\x02) = $\x04\0" |
22391 | | /* 2026 */ "if (!$\x01) memw($\x02) = $\x04.new\0" |
22392 | | /* 2053 */ "if ($\x01) memw($\x02) = $\x04.new\0" |
22393 | | /* 2079 */ "if ($\x01) memw($\x02) = $\x04\0" |
22394 | | /* 2101 */ "memb($\x01) = $\x03\0" |
22395 | | /* 2115 */ "memb($\x01) = $\x03.new\0" |
22396 | | /* 2133 */ "memd($\x01) = $\x03\0" |
22397 | | /* 2147 */ "memh($\x01) = $\x03.h\0" |
22398 | | /* 2163 */ "memh($\x01) = $\x03\0" |
22399 | | /* 2177 */ "memh($\x01) = $\x03.new\0" |
22400 | | /* 2195 */ "memw($\x01) = $\x03\0" |
22401 | | /* 2209 */ "memw($\x01) = $\x03.new\0" |
22402 | | /* 2227 */ "$\x01 = tableidxb($\x03,#$\x04,#$\x05)\0" |
22403 | | /* 2254 */ "if (!$\x01.new) memb($\x02) = $\x04\0" |
22404 | | /* 2281 */ "if (!$\x01.new) memb($\x02) = $\x04.new\0" |
22405 | | /* 2312 */ "if ($\x01.new) memb($\x02) = $\x04.new\0" |
22406 | | /* 2342 */ "if ($\x01.new) memb($\x02) = $\x04\0" |
22407 | | /* 2368 */ "if (!$\x01.new) memd($\x02) = $\x04\0" |
22408 | | /* 2395 */ "if ($\x01.new) memd($\x02) = $\x04\0" |
22409 | | /* 2421 */ "if (!$\x01.new) memh($\x02) = $\x04.h\0" |
22410 | | /* 2450 */ "if ($\x01.new) memh($\x02) = $\x04.h\0" |
22411 | | /* 2478 */ "if (!$\x01.new) memh($\x02) = $\x04\0" |
22412 | | /* 2505 */ "if (!$\x01.new) memh($\x02) = $\x04.new\0" |
22413 | | /* 2536 */ "if ($\x01.new) memh($\x02) = $\x04.new\0" |
22414 | | /* 2566 */ "if ($\x01.new) memh($\x02) = $\x04\0" |
22415 | | /* 2592 */ "if (!$\x01.new) memw($\x02) = $\x04\0" |
22416 | | /* 2619 */ "if (!$\x01.new) memw($\x02) = $\x04.new\0" |
22417 | | /* 2650 */ "if ($\x01.new) memw($\x02) = $\x04.new\0" |
22418 | | /* 2680 */ "if ($\x01.new) memw($\x02) = $\x04\0" |
22419 | | /* 2706 */ "memb($\x01) = #$\x03\0" |
22420 | | /* 2721 */ "if (!$\x01) memb($\x02) = #$\x04\0" |
22421 | | /* 2745 */ "if (!$\x01.new) memb($\x02) = #$\x04\0" |
22422 | | /* 2773 */ "if ($\x01) memb($\x02) = #$\x04\0" |
22423 | | /* 2796 */ "if ($\x01.new) memb($\x02) = #$\x04\0" |
22424 | | /* 2823 */ "memh($\x01) = #$\x03\0" |
22425 | | /* 2838 */ "if (!$\x01) memh($\x02) = #$\x04\0" |
22426 | | /* 2862 */ "if (!$\x01.new) memh($\x02) = #$\x04\0" |
22427 | | /* 2890 */ "if ($\x01) memh($\x02) = #$\x04\0" |
22428 | | /* 2913 */ "if ($\x01.new) memh($\x02) = #$\x04\0" |
22429 | | /* 2940 */ "memw($\x01) = #$\x03\0" |
22430 | | /* 2955 */ "if (!$\x01) memw($\x02) = #$\x04\0" |
22431 | | /* 2979 */ "if (!$\x01.new) memw($\x02) = #$\x04\0" |
22432 | | /* 3007 */ "if ($\x01) memw($\x02) = #$\x04\0" |
22433 | | /* 3030 */ "if ($\x01.new) memw($\x02) = #$\x04\0" |
22434 | | /* 3057 */ "$\x01.w = vextract($\x02,$\x03)\0" |
22435 | | /* 3080 */ "$\x01.w = v6mpy($\x02.ub,$\x03.b10,#$\x04):h\0" |
22436 | | /* 3113 */ "$\x01.w = v6mpy($\x02.ub,$\x03.b10,#$\x04):v\0" |
22437 | | /* 3146 */ "$\x01 = vmemu($\x02)\0" |
22438 | | /* 3161 */ "$\x01 = vmem($\x02)\0" |
22439 | | /* 3175 */ "if (!$\x03) $\x01.cur = vmem($\x02)\0" |
22440 | | /* 3202 */ "if ($\x03) $\x01.cur = vmem($\x02)\0" |
22441 | | /* 3228 */ "if (!$\x02) $\x01.tmp = vmem($\x03)\0" |
22442 | | /* 3255 */ "if (!$\x03) $\x01 = vmem($\x02)\0" |
22443 | | /* 3278 */ "$\x01 = vmem($\x02):nt\0" |
22444 | | /* 3295 */ "if (!$\x03) $\x01.cur = vmem($\x02):nt\0" |
22445 | | /* 3325 */ "if ($\x03) $\x01.cur = vmem($\x02):nt\0" |
22446 | | /* 3354 */ "if (!$\x02) $\x01.tmp = vmem($\x03):nt\0" |
22447 | | /* 3384 */ "if (!$\x03) $\x01 = vmem($\x02):nt\0" |
22448 | | /* 3410 */ "if ($\x02) $\x01 = vmem($\x03):nt\0" |
22449 | | /* 3435 */ "if ($\x02) $\x01.tmp = vmem($\x03):nt\0" |
22450 | | /* 3464 */ "if ($\x02) $\x01 = vmem($\x03)\0" |
22451 | | /* 3486 */ "if ($\x02) $\x01.tmp = vmem($\x03)\0" |
22452 | | /* 3512 */ "vmemu($\x01) = $\x03\0" |
22453 | | /* 3527 */ "if (!$\x01) vmemu($\x02) = $\x04\0" |
22454 | | /* 3551 */ "if ($\x01) vmemu($\x02) = $\x04\0" |
22455 | | /* 3574 */ "vmem($\x01) = $\x03\0" |
22456 | | /* 3588 */ "vmem($\x01) = $\x03.new\0" |
22457 | | /* 3606 */ "if (!$\x01) vmem($\x02) = $\x04\0" |
22458 | | /* 3629 */ "vmem($\x01):nt = $\x03\0" |
22459 | | /* 3646 */ "vmem($\x01):nt = $\x03.new\0" |
22460 | | /* 3667 */ "if (!$\x01) vmem($\x02):nt = $\x04\0" |
22461 | | /* 3693 */ "if ($\x01) vmem($\x02):nt = $\x04\0" |
22462 | | /* 3718 */ "if ($\x01) vmem($\x02) = $\x04\0" |
22463 | | /* 3740 */ "$\x01 = vabsb($\x02):sat\0" |
22464 | | /* 3759 */ "$\x01 = vabsdiffh($\x02,$\x03)\0" |
22465 | | /* 3781 */ "$\x01 = vabsdiffub($\x02,$\x03)\0" |
22466 | | /* 3804 */ "$\x01 = vabsdiffuh($\x02,$\x03)\0" |
22467 | | /* 3827 */ "$\x01 = vabsdiffw($\x02,$\x03)\0" |
22468 | | /* 3849 */ "$\x01 = vabsh($\x02):sat\0" |
22469 | | /* 3868 */ "$\x01 = vabsw($\x02):sat\0" |
22470 | | /* 3887 */ "if (!$\x02.b) $\x01.b += $\x04.b\0" |
22471 | | /* 3911 */ "if ($\x02.b) $\x01.b += $\x04.b\0" |
22472 | | /* 3934 */ "$\x01 = vaddb($\x02,$\x03):sat\0" |
22473 | | /* 3956 */ "$\x01 = vaddh($\x02,$\x03)\0" |
22474 | | /* 3974 */ "if (!$\x02.h) $\x01.h += $\x04.h\0" |
22475 | | /* 3998 */ "if ($\x02.h) $\x01.h += $\x04.h\0" |
22476 | | /* 4021 */ "$\x01 = vaddh($\x02,$\x03):sat\0" |
22477 | | /* 4043 */ "$\x01 += vaddh($\x03,$\x04)\0" |
22478 | | /* 4062 */ "$\x01 = vaddub($\x02,$\x03)\0" |
22479 | | /* 4081 */ "$\x01 += vaddub($\x03,$\x04)\0" |
22480 | | /* 4101 */ "$\x01 = vaddub($\x02,$\x03):sat\0" |
22481 | | /* 4124 */ "$\x01 = vadduh($\x02,$\x03):sat\0" |
22482 | | /* 4147 */ "$\x01 = vadduh($\x02,$\x03)\0" |
22483 | | /* 4166 */ "$\x01 += vadduh($\x03,$\x04)\0" |
22484 | | /* 4186 */ "$\x01 = vadduw($\x02,$\x03):sat\0" |
22485 | | /* 4209 */ "$\x01 = vaddw($\x02,$\x03)\0" |
22486 | | /* 4227 */ "if (!$\x02.w) $\x01.w += $\x04.w\0" |
22487 | | /* 4251 */ "if ($\x02.w) $\x01.w += $\x04.w\0" |
22488 | | /* 4274 */ "$\x01 = vaddw($\x02,$\x03):sat\0" |
22489 | | /* 4296 */ "$\x01.ub = vand(!$\x02.ub,$\x03.ub)\0" |
22490 | | /* 4323 */ "$\x01.ub |= vand(!$\x03.ub,$\x04.ub)\0" |
22491 | | /* 4351 */ "$\x01.ub = vand($\x02.ub,$\x03.ub)\0" |
22492 | | /* 4377 */ "$\x01.ub |= vand($\x03.ub,$\x04.ub)\0" |
22493 | | /* 4404 */ "$\x01 = vaslh($\x02,$\x03)\0" |
22494 | | /* 4422 */ "$\x01 += vaslh($\x03,$\x04)\0" |
22495 | | /* 4441 */ "$\x01 = vaslw($\x02,$\x03)\0" |
22496 | | /* 4459 */ "$\x01 += vaslw($\x03,$\x04)\0" |
22497 | | /* 4478 */ "$\x01 = vasrinto($\x03,$\x04)\0" |
22498 | | /* 4499 */ "$\x01 = vasrh($\x02,$\x03)\0" |
22499 | | /* 4517 */ "$\x01 += vasrh($\x03,$\x04)\0" |
22500 | | /* 4536 */ "$\x01 = vasrw($\x02,$\x03)\0" |
22501 | | /* 4554 */ "$\x01 += vasrw($\x03,$\x04)\0" |
22502 | | /* 4573 */ "$\x01 = vavgb($\x02,$\x03)\0" |
22503 | | /* 4591 */ "$\x01 = vavgb($\x02,$\x03):rnd\0" |
22504 | | /* 4613 */ "$\x01 = vavgh($\x02,$\x03)\0" |
22505 | | /* 4631 */ "$\x01 = vavgh($\x02,$\x03):rnd\0" |
22506 | | /* 4653 */ "$\x01 = vavgub($\x02,$\x03)\0" |
22507 | | /* 4672 */ "$\x01 = vavgub($\x02,$\x03):rnd\0" |
22508 | | /* 4695 */ "$\x01 = vavguh($\x02,$\x03)\0" |
22509 | | /* 4714 */ "$\x01 = vavguh($\x02,$\x03):rnd\0" |
22510 | | /* 4737 */ "$\x01 = vavguw($\x02,$\x03)\0" |
22511 | | /* 4756 */ "$\x01 = vavguw($\x02,$\x03):rnd\0" |
22512 | | /* 4779 */ "$\x01 = vavgw($\x02,$\x03)\0" |
22513 | | /* 4797 */ "$\x01 = vavgw($\x02,$\x03):rnd\0" |
22514 | | /* 4819 */ "$\x01 = vcl0h($\x02)\0" |
22515 | | /* 4834 */ "$\x01 = vcl0w($\x02)\0" |
22516 | | /* 4849 */ "$\x01 = vdealb($\x02)\0" |
22517 | | /* 4865 */ "$\x01 = vdealb4w($\x02,$\x03)\0" |
22518 | | /* 4886 */ "$\x01 = vdealh($\x02)\0" |
22519 | | /* 4902 */ "$\x01 = vdmpybus($\x02,$\x03)\0" |
22520 | | /* 4923 */ "$\x01 += vdmpybus($\x03,$\x04)\0" |
22521 | | /* 4945 */ "$\x01 = vdmpyhb($\x02,$\x03)\0" |
22522 | | /* 4965 */ "$\x01 += vdmpyhb($\x03,$\x04)\0" |
22523 | | /* 4986 */ "$\x01 = vdmpyh($\x02,$\x03):sat\0" |
22524 | | /* 5009 */ "$\x01 += vdmpyh($\x03,$\x04):sat\0" |
22525 | | /* 5033 */ "$\x01 = vdmpyhsu($\x02,$\x03,#1):sat\0" |
22526 | | /* 5061 */ "$\x01 += vdmpyhsu($\x03,$\x04,#1):sat\0" |
22527 | | /* 5090 */ "$\x01 = vdmpyhsu($\x02,$\x03):sat\0" |
22528 | | /* 5115 */ "$\x01 += vdmpyhsu($\x03,$\x04):sat\0" |
22529 | | /* 5141 */ "$\x01 = vdsaduh($\x02,$\x03)\0" |
22530 | | /* 5161 */ "$\x01 += vdsaduh($\x03,$\x04)\0" |
22531 | | /* 5182 */ "$\x01 = vcmp.eq($\x02.ub,$\x03.ub)\0" |
22532 | | /* 5208 */ "$\x01 &= vcmp.eq($\x03.ub,$\x04.ub)\0" |
22533 | | /* 5235 */ "$\x01 |= vcmp.eq($\x03.ub,$\x04.ub)\0" |
22534 | | /* 5262 */ "$\x01 ^= vcmp.eq($\x03.ub,$\x04.ub)\0" |
22535 | | /* 5289 */ "$\x01 = vcmp.eq($\x02.uh,$\x03.uh)\0" |
22536 | | /* 5315 */ "$\x01 &= vcmp.eq($\x03.uh,$\x04.uh)\0" |
22537 | | /* 5342 */ "$\x01 |= vcmp.eq($\x03.uh,$\x04.uh)\0" |
22538 | | /* 5369 */ "$\x01 ^= vcmp.eq($\x03.uh,$\x04.uh)\0" |
22539 | | /* 5396 */ "$\x01 = vcmp.eq($\x02.uw,$\x03.uw)\0" |
22540 | | /* 5422 */ "$\x01 &= vcmp.eq($\x03.uw,$\x04.uw)\0" |
22541 | | /* 5449 */ "$\x01 |= vcmp.eq($\x03.uw,$\x04.uw)\0" |
22542 | | /* 5476 */ "$\x01 ^= vcmp.eq($\x03.uw,$\x04.uw)\0" |
22543 | | /* 5503 */ "$\x01 = vlsrh($\x02,$\x03)\0" |
22544 | | /* 5521 */ "$\x01 = vlsrw($\x02,$\x03)\0" |
22545 | | /* 5539 */ "$\x01 = vmaxb($\x02,$\x03)\0" |
22546 | | /* 5557 */ "$\x01 = vmaxh($\x02,$\x03)\0" |
22547 | | /* 5575 */ "$\x01 = vmaxub($\x02,$\x03)\0" |
22548 | | /* 5594 */ "$\x01 = vmaxuh($\x02,$\x03)\0" |
22549 | | /* 5613 */ "$\x01 = vmaxw($\x02,$\x03)\0" |
22550 | | /* 5631 */ "$\x01 = vminb($\x02,$\x03)\0" |
22551 | | /* 5649 */ "$\x01 = vminh($\x02,$\x03)\0" |
22552 | | /* 5667 */ "$\x01 = vminub($\x02,$\x03)\0" |
22553 | | /* 5686 */ "$\x01 = vminuh($\x02,$\x03)\0" |
22554 | | /* 5705 */ "$\x01 = vminw($\x02,$\x03)\0" |
22555 | | /* 5723 */ "$\x01 = vmpabus($\x02,$\x03)\0" |
22556 | | /* 5743 */ "$\x01 += vmpabus($\x03,$\x04)\0" |
22557 | | /* 5764 */ "$\x01 = vmpabuu($\x02,$\x03)\0" |
22558 | | /* 5784 */ "$\x01 += vmpabuu($\x03,$\x04)\0" |
22559 | | /* 5805 */ "$\x01 = vmpahb($\x02,$\x03)\0" |
22560 | | /* 5824 */ "$\x01 += vmpahb($\x03,$\x04)\0" |
22561 | | /* 5844 */ "$\x01 = vmpauhb($\x02,$\x03)\0" |
22562 | | /* 5864 */ "$\x01 += vmpauhb($\x03,$\x04)\0" |
22563 | | /* 5885 */ "$\x01 = vmpybus($\x02,$\x03)\0" |
22564 | | /* 5905 */ "$\x01 += vmpybus($\x03,$\x04)\0" |
22565 | | /* 5926 */ "$\x01 = vmpyb($\x02,$\x03)\0" |
22566 | | /* 5944 */ "$\x01 += vmpyb($\x03,$\x04)\0" |
22567 | | /* 5963 */ "$\x01 = vmpyewuh($\x02,$\x03)\0" |
22568 | | /* 5984 */ "$\x01 = vmpyh($\x02,$\x03)\0" |
22569 | | /* 6002 */ "$\x01 += vmpyh($\x03,$\x04)\0" |
22570 | | /* 6021 */ "$\x01 += vmpyh($\x03,$\x04):sat\0" |
22571 | | /* 6044 */ "$\x01 = vmpyh($\x02,$\x03):<<1:rnd:sat\0" |
22572 | | /* 6074 */ "$\x01 = vmpyh($\x02,$\x03):<<1:sat\0" |
22573 | | /* 6100 */ "$\x01 = vmpyhus($\x02,$\x03)\0" |
22574 | | /* 6120 */ "$\x01 += vmpyhus($\x03,$\x04)\0" |
22575 | | /* 6141 */ "$\x01 += vmpyiewh($\x03,$\x04)\0" |
22576 | | /* 6163 */ "$\x01 = vmpyiewuh($\x02,$\x03)\0" |
22577 | | /* 6185 */ "$\x01 += vmpyiewuh($\x03,$\x04)\0" |
22578 | | /* 6208 */ "$\x01 = vmpyih($\x02,$\x03)\0" |
22579 | | /* 6227 */ "$\x01 += vmpyih($\x03,$\x04)\0" |
22580 | | /* 6247 */ "$\x01 = vmpyihb($\x02,$\x03)\0" |
22581 | | /* 6267 */ "$\x01 += vmpyihb($\x03,$\x04)\0" |
22582 | | /* 6288 */ "$\x01 = vmpyiowh($\x02,$\x03)\0" |
22583 | | /* 6309 */ "$\x01 = vmpyiwb($\x02,$\x03)\0" |
22584 | | /* 6329 */ "$\x01 += vmpyiwb($\x03,$\x04)\0" |
22585 | | /* 6350 */ "$\x01 = vmpyiwh($\x02,$\x03)\0" |
22586 | | /* 6370 */ "$\x01 += vmpyiwh($\x03,$\x04)\0" |
22587 | | /* 6391 */ "$\x01 = vmpyiwub($\x02,$\x03)\0" |
22588 | | /* 6412 */ "$\x01 += vmpyiwub($\x03,$\x04)\0" |
22589 | | /* 6434 */ "$\x01 = vmpyowh($\x02,$\x03):<<1:sat\0" |
22590 | | /* 6462 */ "$\x01 = vmpyowh($\x02,$\x03):<<1:rnd:sat\0" |
22591 | | /* 6494 */ "$\x01 = vmpyub($\x02,$\x03)\0" |
22592 | | /* 6513 */ "$\x01 += vmpyub($\x03,$\x04)\0" |
22593 | | /* 6533 */ "$\x01 = vmpyuh($\x02,$\x03)\0" |
22594 | | /* 6552 */ "$\x01 += vmpyuh($\x03,$\x04)\0" |
22595 | | /* 6572 */ "$\x01 = vnavgb($\x02,$\x03)\0" |
22596 | | /* 6591 */ "$\x01 = vnavgh($\x02,$\x03)\0" |
22597 | | /* 6610 */ "$\x01 = vnavgub($\x02,$\x03)\0" |
22598 | | /* 6630 */ "$\x01 = vnavgw($\x02,$\x03)\0" |
22599 | | /* 6649 */ "$\x01 = vnormamth($\x02)\0" |
22600 | | /* 6668 */ "$\x01 = vnormamtw($\x02)\0" |
22601 | | /* 6687 */ "$\x01 = vpackeb($\x02,$\x03)\0" |
22602 | | /* 6707 */ "$\x01 = vpackeh($\x02,$\x03)\0" |
22603 | | /* 6727 */ "$\x01 = vpackhb($\x02,$\x03):sat\0" |
22604 | | /* 6751 */ "$\x01 = vpackhub($\x02,$\x03):sat\0" |
22605 | | /* 6776 */ "$\x01 = vpackob($\x02,$\x03)\0" |
22606 | | /* 6796 */ "$\x01 = vpackoh($\x02,$\x03)\0" |
22607 | | /* 6816 */ "$\x01 = vpackwh($\x02,$\x03):sat\0" |
22608 | | /* 6840 */ "$\x01 = vpackwuh($\x02,$\x03):sat\0" |
22609 | | /* 6865 */ "$\x01 = vpopcounth($\x02)\0" |
22610 | | /* 6885 */ "$\x01.w = vrmpy($\x02.b,$\x03.ub)\0" |
22611 | | /* 6910 */ "$\x01.w += vrmpy($\x03.b,$\x04.ub)\0" |
22612 | | /* 6936 */ "$\x01 = vrmpybus($\x02,$\x03)\0" |
22613 | | /* 6957 */ "$\x01 += vrmpybus($\x03,$\x04)\0" |
22614 | | /* 6979 */ "$\x01 = vrmpybus($\x02,$\x03,#$\x04)\0" |
22615 | | /* 7004 */ "$\x01 += vrmpybus($\x03,$\x04,#$\x05)\0" |
22616 | | /* 7030 */ "$\x01 = vrmpyb($\x02,$\x03)\0" |
22617 | | /* 7049 */ "$\x01 += vrmpyb($\x03,$\x04)\0" |
22618 | | /* 7069 */ "$\x01 = vrmpyub($\x02,$\x03)\0" |
22619 | | /* 7089 */ "$\x01 += vrmpyub($\x03,$\x04)\0" |
22620 | | /* 7110 */ "$\x01.uw = vrmpy($\x02.ub,$\x03.ub)\0" |
22621 | | /* 7137 */ "$\x01.uw += vrmpy($\x03.ub,$\x04.ub)\0" |
22622 | | /* 7165 */ "$\x01 = vrmpyub($\x02,$\x03,#$\x04)\0" |
22623 | | /* 7189 */ "$\x01 += vrmpyub($\x03,$\x04,#$\x05)\0" |
22624 | | /* 7214 */ "$\x01 = vrotr($\x02,$\x03)\0" |
22625 | | /* 7232 */ "$\x01 = vroundhb($\x02,$\x03):sat\0" |
22626 | | /* 7257 */ "$\x01 = vroundhub($\x02,$\x03):sat\0" |
22627 | | /* 7283 */ "$\x01 = vrounduhub($\x02,$\x03):sat\0" |
22628 | | /* 7310 */ "$\x01 = vrounduwuh($\x02,$\x03):sat\0" |
22629 | | /* 7337 */ "$\x01 = vroundwh($\x02,$\x03):sat\0" |
22630 | | /* 7362 */ "$\x01 = vroundwuh($\x02,$\x03):sat\0" |
22631 | | /* 7388 */ "$\x01 = vrsadub($\x02,$\x03,#$\x04)\0" |
22632 | | /* 7412 */ "$\x01 += vrsadub($\x03,$\x04,#$\x05)\0" |
22633 | | /* 7437 */ "$\x01 = vsathub($\x02,$\x03)\0" |
22634 | | /* 7457 */ "$\x01 = vsatuwuh($\x02,$\x03)\0" |
22635 | | /* 7478 */ "$\x01 = vsatwh($\x02,$\x03)\0" |
22636 | | /* 7497 */ "$\x01 = vsxtb($\x02)\0" |
22637 | | /* 7512 */ "vscatter($\x01,$\x02,$\x03.h) = $\x04.h\0" |
22638 | | /* 7540 */ "vscatter($\x01,$\x02,$\x03.h) += $\x04.h\0" |
22639 | | /* 7569 */ "if ($\x01) vscatter($\x02,$\x03,$\x04.h) = $\x05.h\0" |
22640 | | /* 7605 */ "vscatter($\x01,$\x02,$\x03.w) = $\x04.h\0" |
22641 | | /* 7633 */ "vscatter($\x01,$\x02,$\x03.w) += $\x04.h\0" |
22642 | | /* 7662 */ "if ($\x01) vscatter($\x02,$\x03,$\x04.w) = $\x05.h\0" |
22643 | | /* 7698 */ "vscatter($\x01,$\x02,$\x03.w) = $\x04.w\0" |
22644 | | /* 7726 */ "vscatter($\x01,$\x02,$\x03.w) += $\x04.w\0" |
22645 | | /* 7755 */ "if ($\x01) vscatter($\x02,$\x03,$\x04.w) = $\x05.w\0" |
22646 | | /* 7791 */ "$\x01 = vsxth($\x02)\0" |
22647 | | /* 7806 */ "$\x01 = vshuffeh($\x02,$\x03)\0" |
22648 | | /* 7827 */ "vtrans2x2($\x01,$\x02,$\x05)\0" |
22649 | | /* 7847 */ "$\x01 = vshuffb($\x02)\0" |
22650 | | /* 7864 */ "$\x01 = vshuffeb($\x02,$\x03)\0" |
22651 | | /* 7885 */ "$\x01 = vshuffh($\x02)\0" |
22652 | | /* 7902 */ "$\x01 = vshuffob($\x02,$\x03)\0" |
22653 | | /* 7923 */ "$\x01 = vshuffoeb($\x02,$\x03)\0" |
22654 | | /* 7945 */ "$\x01 = vshuffoeh($\x02,$\x03)\0" |
22655 | | /* 7967 */ "$\x01 = vshuffoh($\x02,$\x03)\0" |
22656 | | /* 7988 */ "if (!$\x02.b) $\x01.b -= $\x04.b\0" |
22657 | | /* 8012 */ "if ($\x02.b) $\x01.b -= $\x04.b\0" |
22658 | | /* 8035 */ "$\x01 = vsubb($\x02,$\x03):sat\0" |
22659 | | /* 8057 */ "$\x01 = vsubh($\x02,$\x03)\0" |
22660 | | /* 8075 */ "if (!$\x02.h) $\x01.h -= $\x04.h\0" |
22661 | | /* 8099 */ "if ($\x02.h) $\x01.h -= $\x04.h\0" |
22662 | | /* 8122 */ "$\x01 = vsubh($\x02,$\x03):sat\0" |
22663 | | /* 8144 */ "$\x01 = vsubub($\x02,$\x03)\0" |
22664 | | /* 8163 */ "$\x01 = vsubub($\x02,$\x03):sat\0" |
22665 | | /* 8186 */ "$\x01 = vsubuh($\x02,$\x03):sat\0" |
22666 | | /* 8209 */ "$\x01 = vsubuh($\x02,$\x03)\0" |
22667 | | /* 8228 */ "$\x01 = vsubuw($\x02,$\x03):sat\0" |
22668 | | /* 8251 */ "$\x01 = vsubw($\x02,$\x03)\0" |
22669 | | /* 8269 */ "$\x01 = #0\0" |
22670 | | /* 8277 */ "if (!$\x02.w) $\x01.w -= $\x04.w\0" |
22671 | | /* 8301 */ "if ($\x02.w) $\x01.w -= $\x04.w\0" |
22672 | | /* 8324 */ "$\x01 = vsubw($\x02,$\x03):sat\0" |
22673 | | /* 8346 */ "$\x01 = vtmpyb($\x02,$\x03)\0" |
22674 | | /* 8365 */ "$\x01 += vtmpyb($\x03,$\x04)\0" |
22675 | | /* 8385 */ "$\x01 = vtmpybus($\x02,$\x03)\0" |
22676 | | /* 8406 */ "$\x01 += vtmpybus($\x03,$\x04)\0" |
22677 | | /* 8428 */ "$\x01 = vtmpyhb($\x02,$\x03)\0" |
22678 | | /* 8448 */ "$\x01 += vtmpyhb($\x03,$\x04)\0" |
22679 | | /* 8469 */ "$\x01 = vunpackb($\x02)\0" |
22680 | | /* 8487 */ "$\x01 = vunpackh($\x02)\0" |
22681 | | /* 8505 */ "$\x01 |= vunpackoh($\x03)\0" |
22682 | | /* 8525 */ "$\x01 = vunpackub($\x02)\0" |
22683 | | /* 8544 */ "$\x01 = vunpackuh($\x02)\0" |
22684 | | /* 8563 */ "$\x01 = vzxtb($\x02)\0" |
22685 | | /* 8578 */ "$\x01 = vzxth($\x02)\0" |
22686 | | /* 8593 */ "z = vmem($\x01)\0" |
22687 | | /* 8606 */ "if ($\x01) z = vmem($\x02)\0" |
22688 | | /* 8627 */ "crswap($\x01,sgp)\0" |
22689 | | /* 8642 */ "dcfetch($\x01)\0" |
22690 | | ; |
22691 | | |
22692 | | #ifndef NDEBUG |
22693 | | static struct SortCheck { |
22694 | | SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) { |
22695 | | assert(std::is_sorted( |
22696 | | OpToPatterns.begin(), OpToPatterns.end(), |
22697 | | [](const PatternsForOpcode &L, const PatternsForOpcode &R) { |
22698 | | return L.Opcode < R.Opcode; |
22699 | | }) && |
22700 | | "tablegen failed to sort opcode patterns"); |
22701 | | } |
22702 | | } sortCheckVar(OpToPatterns); |
22703 | | #endif |
22704 | | |
22705 | | AliasMatchingData M { |
22706 | | ArrayRef(OpToPatterns), |
22707 | | ArrayRef(Patterns), |
22708 | | ArrayRef(Conds), |
22709 | | StringRef(AsmStrings, std::size(AsmStrings)), |
22710 | | nullptr, |
22711 | | }; |
22712 | | const char *AsmString = matchAliasPatterns(MI, nullptr, M); |
22713 | | if (!AsmString) return false; |
22714 | | |
22715 | | unsigned I = 0; |
22716 | | while (AsmString[I] != ' ' && AsmString[I] != '\t' && |
22717 | | AsmString[I] != '$' && AsmString[I] != '\0') |
22718 | | ++I; |
22719 | | OS << '\t' << StringRef(AsmString, I); |
22720 | | if (AsmString[I] != '\0') { |
22721 | | if (AsmString[I] == ' ' || AsmString[I] == '\t') { |
22722 | | OS << '\t'; |
22723 | | ++I; |
22724 | | } |
22725 | | do { |
22726 | | if (AsmString[I] == '$') { |
22727 | | ++I; |
22728 | | if (AsmString[I] == (char)0xff) { |
22729 | | ++I; |
22730 | | int OpIdx = AsmString[I++] - 1; |
22731 | | int PrintMethodIdx = AsmString[I++] - 1; |
22732 | | printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, OS); |
22733 | | } else |
22734 | | printOperand(MI, unsigned(AsmString[I++]) - 1, OS); |
22735 | | } else { |
22736 | | OS << AsmString[I++]; |
22737 | | } |
22738 | | } while (AsmString[I] != '\0'); |
22739 | | } |
22740 | | |
22741 | | return true; |
22742 | | } |
22743 | | |
22744 | | void HexagonInstPrinter::printCustomAliasOperand( |
22745 | | const MCInst *MI, uint64_t Address, unsigned OpIdx, |
22746 | | unsigned PrintMethodIdx, |
22747 | | raw_ostream &OS) { |
22748 | | switch (PrintMethodIdx) { |
22749 | | default: |
22750 | | llvm_unreachable("Unknown PrintMethod kind"); |
22751 | | break; |
22752 | | case 0: |
22753 | | printBrtarget(MI, OpIdx, OS); |
22754 | | break; |
22755 | | } |
22756 | | } |
22757 | | |
22758 | | #endif // PRINT_ALIAS_INSTR |