Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/Hexagon/HexagonGenMCCodeEmitter.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Machine Code Emitter                                                       *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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uint64_t HexagonMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
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    SmallVectorImpl<MCFixup> &Fixups,
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0
    const MCSubtargetInfo &STI) const {
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0
  static const uint64_t InstBits[] = {
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508
0
    UINT64_C(0),
509
0
    UINT64_C(0),
510
0
    UINT64_C(0),
511
0
    UINT64_C(0),
512
0
    UINT64_C(0),
513
0
    UINT64_C(0),
514
0
    UINT64_C(0),
515
0
    UINT64_C(0),
516
0
    UINT64_C(0),
517
0
    UINT64_C(0),
518
0
    UINT64_C(0),
519
0
    UINT64_C(0),
520
0
    UINT64_C(0),
521
0
    UINT64_C(0),
522
0
    UINT64_C(0),
523
0
    UINT64_C(0),
524
0
    UINT64_C(0),
525
0
    UINT64_C(0),
526
0
    UINT64_C(0),
527
0
    UINT64_C(0),
528
0
    UINT64_C(0),
529
0
    UINT64_C(0),
530
0
    UINT64_C(0),
531
0
    UINT64_C(0),
532
0
    UINT64_C(0),
533
0
    UINT64_C(0),
534
0
    UINT64_C(0),
535
0
    UINT64_C(0),
536
0
    UINT64_C(0),
537
0
    UINT64_C(0),
538
0
    UINT64_C(0),
539
0
    UINT64_C(0),
540
0
    UINT64_C(0),
541
0
    UINT64_C(0),
542
0
    UINT64_C(0),
543
0
    UINT64_C(0),
544
0
    UINT64_C(0),
545
0
    UINT64_C(0),
546
0
    UINT64_C(0),
547
0
    UINT64_C(0),
548
0
    UINT64_C(0),
549
0
    UINT64_C(0),
550
0
    UINT64_C(0),
551
0
    UINT64_C(0),
552
0
    UINT64_C(0),
553
0
    UINT64_C(0),
554
0
    UINT64_C(0),
555
0
    UINT64_C(0),
556
0
    UINT64_C(0),
557
0
    UINT64_C(0),
558
0
    UINT64_C(0),
559
0
    UINT64_C(0),
560
0
    UINT64_C(0),
561
0
    UINT64_C(0),
562
0
    UINT64_C(0),
563
0
    UINT64_C(0),
564
0
    UINT64_C(0),
565
0
    UINT64_C(0),
566
0
    UINT64_C(0),
567
0
    UINT64_C(0),
568
0
    UINT64_C(0),
569
0
    UINT64_C(0),
570
0
    UINT64_C(0),
571
0
    UINT64_C(0),
572
0
    UINT64_C(0),
573
0
    UINT64_C(0),
574
0
    UINT64_C(0),
575
0
    UINT64_C(0),
576
0
    UINT64_C(0),
577
0
    UINT64_C(0),
578
0
    UINT64_C(0),
579
0
    UINT64_C(0),
580
0
    UINT64_C(0),
581
0
    UINT64_C(0),
582
0
    UINT64_C(0),
583
0
    UINT64_C(0),
584
0
    UINT64_C(0),
585
0
    UINT64_C(0),
586
0
    UINT64_C(0),
587
0
    UINT64_C(0),
588
0
    UINT64_C(0),
589
0
    UINT64_C(0),
590
0
    UINT64_C(0),
591
0
    UINT64_C(0),
592
0
    UINT64_C(0),
593
0
    UINT64_C(0),
594
0
    UINT64_C(0),
595
0
    UINT64_C(0),
596
0
    UINT64_C(0),
597
0
    UINT64_C(0),
598
0
    UINT64_C(0),
599
0
    UINT64_C(0),
600
0
    UINT64_C(0),
601
0
    UINT64_C(0),
602
0
    UINT64_C(0),
603
0
    UINT64_C(0),
604
0
    UINT64_C(0),
605
0
    UINT64_C(0),
606
0
    UINT64_C(0),
607
0
    UINT64_C(0),
608
0
    UINT64_C(0),
609
0
    UINT64_C(0),
610
0
    UINT64_C(0),
611
0
    UINT64_C(0),
612
0
    UINT64_C(0),
613
0
    UINT64_C(0),
614
0
    UINT64_C(0),
615
0
    UINT64_C(0),
616
0
    UINT64_C(0),
617
0
    UINT64_C(0),
618
0
    UINT64_C(0),
619
0
    UINT64_C(0),
620
0
    UINT64_C(0),
621
0
    UINT64_C(0),
622
0
    UINT64_C(0),
623
0
    UINT64_C(0),
624
0
    UINT64_C(0),
625
0
    UINT64_C(0),
626
0
    UINT64_C(0),
627
0
    UINT64_C(0),
628
0
    UINT64_C(0),
629
0
    UINT64_C(0),
630
0
    UINT64_C(0),
631
0
    UINT64_C(0),
632
0
    UINT64_C(0),
633
0
    UINT64_C(0),
634
0
    UINT64_C(0),
635
0
    UINT64_C(0),
636
0
    UINT64_C(0),
637
0
    UINT64_C(0),
638
0
    UINT64_C(0),
639
0
    UINT64_C(0),
640
0
    UINT64_C(0),
641
0
    UINT64_C(0),
642
0
    UINT64_C(0),
643
0
    UINT64_C(0),
644
0
    UINT64_C(0),
645
0
    UINT64_C(0),
646
0
    UINT64_C(0),
647
0
    UINT64_C(0),
648
0
    UINT64_C(0),
649
0
    UINT64_C(0),
650
0
    UINT64_C(0),
651
0
    UINT64_C(0),
652
0
    UINT64_C(0),
653
0
    UINT64_C(0),
654
0
    UINT64_C(0),
655
0
    UINT64_C(0),
656
0
    UINT64_C(0),
657
0
    UINT64_C(0),
658
0
    UINT64_C(0),
659
0
    UINT64_C(0),
660
0
    UINT64_C(0),
661
0
    UINT64_C(0),
662
0
    UINT64_C(0),
663
0
    UINT64_C(0),
664
0
    UINT64_C(0),
665
0
    UINT64_C(0),
666
0
    UINT64_C(0),
667
0
    UINT64_C(0),
668
0
    UINT64_C(0),
669
0
    UINT64_C(0),
670
0
    UINT64_C(0),
671
0
    UINT64_C(0),
672
0
    UINT64_C(0),
673
0
    UINT64_C(0),
674
0
    UINT64_C(0),
675
0
    UINT64_C(0),
676
0
    UINT64_C(0),
677
0
    UINT64_C(0),
678
0
    UINT64_C(0),
679
0
    UINT64_C(0),
680
0
    UINT64_C(0),
681
0
    UINT64_C(0),
682
0
    UINT64_C(0),
683
0
    UINT64_C(0),
684
0
    UINT64_C(0),
685
0
    UINT64_C(0),
686
0
    UINT64_C(0),
687
0
    UINT64_C(0),
688
0
    UINT64_C(0),
689
0
    UINT64_C(0),
690
0
    UINT64_C(0),
691
0
    UINT64_C(0),
692
0
    UINT64_C(0),
693
0
    UINT64_C(0),
694
0
    UINT64_C(0),
695
0
    UINT64_C(0),
696
0
    UINT64_C(0),
697
0
    UINT64_C(0),
698
0
    UINT64_C(0),
699
0
    UINT64_C(0),
700
0
    UINT64_C(0),
701
0
    UINT64_C(0),
702
0
    UINT64_C(0),
703
0
    UINT64_C(0),
704
0
    UINT64_C(0),
705
0
    UINT64_C(0),
706
0
    UINT64_C(0),
707
0
    UINT64_C(0),
708
0
    UINT64_C(0),
709
0
    UINT64_C(0),
710
0
    UINT64_C(0),
711
0
    UINT64_C(0),
712
0
    UINT64_C(0),
713
0
    UINT64_C(0),
714
0
    UINT64_C(0),
715
0
    UINT64_C(0),
716
0
    UINT64_C(0),
717
0
    UINT64_C(0),
718
0
    UINT64_C(0),
719
0
    UINT64_C(0),
720
0
    UINT64_C(0),
721
0
    UINT64_C(0),
722
0
    UINT64_C(0),
723
0
    UINT64_C(0),
724
0
    UINT64_C(0),
725
0
    UINT64_C(0),
726
0
    UINT64_C(0),
727
0
    UINT64_C(0),
728
0
    UINT64_C(0),
729
0
    UINT64_C(0),
730
0
    UINT64_C(0),
731
0
    UINT64_C(0),
732
0
    UINT64_C(0),
733
0
    UINT64_C(0),
734
0
    UINT64_C(0),
735
0
    UINT64_C(0),
736
0
    UINT64_C(0),
737
0
    UINT64_C(0),
738
0
    UINT64_C(0),
739
0
    UINT64_C(0),
740
0
    UINT64_C(0),
741
0
    UINT64_C(0),
742
0
    UINT64_C(0),
743
0
    UINT64_C(0),
744
0
    UINT64_C(0),
745
0
    UINT64_C(0),
746
0
    UINT64_C(0),
747
0
    UINT64_C(0),
748
0
    UINT64_C(0),
749
0
    UINT64_C(0),
750
0
    UINT64_C(0),
751
0
    UINT64_C(0),
752
0
    UINT64_C(0),
753
0
    UINT64_C(0),
754
0
    UINT64_C(0),
755
0
    UINT64_C(0),
756
0
    UINT64_C(0),
757
0
    UINT64_C(0),
758
0
    UINT64_C(0),
759
0
    UINT64_C(0),
760
0
    UINT64_C(0),
761
0
    UINT64_C(0),
762
0
    UINT64_C(0),
763
0
    UINT64_C(0),
764
0
    UINT64_C(0),
765
0
    UINT64_C(0),
766
0
    UINT64_C(0),
767
0
    UINT64_C(0),
768
0
    UINT64_C(0),
769
0
    UINT64_C(0),
770
0
    UINT64_C(0),
771
0
    UINT64_C(0),
772
0
    UINT64_C(0),
773
0
    UINT64_C(0),
774
0
    UINT64_C(0),
775
0
    UINT64_C(0),
776
0
    UINT64_C(0),
777
0
    UINT64_C(0),
778
0
    UINT64_C(0),
779
0
    UINT64_C(0),
780
0
    UINT64_C(0),
781
0
    UINT64_C(0),
782
0
    UINT64_C(0),
783
0
    UINT64_C(0),
784
0
    UINT64_C(0),
785
0
    UINT64_C(0),
786
0
    UINT64_C(0),
787
0
    UINT64_C(0),
788
0
    UINT64_C(0),
789
0
    UINT64_C(0),
790
0
    UINT64_C(0),
791
0
    UINT64_C(0),
792
0
    UINT64_C(0),
793
0
    UINT64_C(0),
794
0
    UINT64_C(0),
795
0
    UINT64_C(0),
796
0
    UINT64_C(0),
797
0
    UINT64_C(0),
798
0
    UINT64_C(0),
799
0
    UINT64_C(0),
800
0
    UINT64_C(0),
801
0
    UINT64_C(0),
802
0
    UINT64_C(0),
803
0
    UINT64_C(0),
804
0
    UINT64_C(0),
805
0
    UINT64_C(0),
806
0
    UINT64_C(0),
807
0
    UINT64_C(0),
808
0
    UINT64_C(0),
809
0
    UINT64_C(0),
810
0
    UINT64_C(0),
811
0
    UINT64_C(0),
812
0
    UINT64_C(0),
813
0
    UINT64_C(0),
814
0
    UINT64_C(0),
815
0
    UINT64_C(0),
816
0
    UINT64_C(0),
817
0
    UINT64_C(0),
818
0
    UINT64_C(0),
819
0
    UINT64_C(0),
820
0
    UINT64_C(0),
821
0
    UINT64_C(0),
822
0
    UINT64_C(0),
823
0
    UINT64_C(0),
824
0
    UINT64_C(0),
825
0
    UINT64_C(0),
826
0
    UINT64_C(0),
827
0
    UINT64_C(0),
828
0
    UINT64_C(0),
829
0
    UINT64_C(0),
830
0
    UINT64_C(0),
831
0
    UINT64_C(0),
832
0
    UINT64_C(0),
833
0
    UINT64_C(0),
834
0
    UINT64_C(0),
835
0
    UINT64_C(0),
836
0
    UINT64_C(0),
837
0
    UINT64_C(0),
838
0
    UINT64_C(0),
839
0
    UINT64_C(0),
840
0
    UINT64_C(0),
841
0
    UINT64_C(0),
842
0
    UINT64_C(0),
843
0
    UINT64_C(0),
844
0
    UINT64_C(0),
845
0
    UINT64_C(0),
846
0
    UINT64_C(0),
847
0
    UINT64_C(0),
848
0
    UINT64_C(0),
849
0
    UINT64_C(0),
850
0
    UINT64_C(0),
851
0
    UINT64_C(0),
852
0
    UINT64_C(0),
853
0
    UINT64_C(0),
854
0
    UINT64_C(0),
855
0
    UINT64_C(0),
856
0
    UINT64_C(0),
857
0
    UINT64_C(0),
858
0
    UINT64_C(0),
859
0
    UINT64_C(0),
860
0
    UINT64_C(0),
861
0
    UINT64_C(0),
862
0
    UINT64_C(0),
863
0
    UINT64_C(0),
864
0
    UINT64_C(0),
865
0
    UINT64_C(0),
866
0
    UINT64_C(0),
867
0
    UINT64_C(0),
868
0
    UINT64_C(0),
869
0
    UINT64_C(0),
870
0
    UINT64_C(0),
871
0
    UINT64_C(0),
872
0
    UINT64_C(0),
873
0
    UINT64_C(0),
874
0
    UINT64_C(0),
875
0
    UINT64_C(0),
876
0
    UINT64_C(0),
877
0
    UINT64_C(0),
878
0
    UINT64_C(0),
879
0
    UINT64_C(0),
880
0
    UINT64_C(0),
881
0
    UINT64_C(0),
882
0
    UINT64_C(0),
883
0
    UINT64_C(0),
884
0
    UINT64_C(0),
885
0
    UINT64_C(0),
886
0
    UINT64_C(0),
887
0
    UINT64_C(0),
888
0
    UINT64_C(0),
889
0
    UINT64_C(0),
890
0
    UINT64_C(0),
891
0
    UINT64_C(2357198976), // A2_abs
892
0
    UINT64_C(2155872448), // A2_absp
893
0
    UINT64_C(2357199008), // A2_abssat
894
0
    UINT64_C(4076863488), // A2_add
895
0
    UINT64_C(3577741408), // A2_addh_h16_hh
896
0
    UINT64_C(3577741376), // A2_addh_h16_hl
897
0
    UINT64_C(3577741344), // A2_addh_h16_lh
898
0
    UINT64_C(3577741312), // A2_addh_h16_ll
899
0
    UINT64_C(3577741536), // A2_addh_h16_sat_hh
900
0
    UINT64_C(3577741504), // A2_addh_h16_sat_hl
901
0
    UINT64_C(3577741472), // A2_addh_h16_sat_lh
902
0
    UINT64_C(3577741440), // A2_addh_h16_sat_ll
903
0
    UINT64_C(3573547072), // A2_addh_l16_hl
904
0
    UINT64_C(3573547008), // A2_addh_l16_ll
905
0
    UINT64_C(3573547200), // A2_addh_l16_sat_hl
906
0
    UINT64_C(3573547136), // A2_addh_l16_sat_ll
907
0
    UINT64_C(2952790016), // A2_addi
908
0
    UINT64_C(3539992800), // A2_addp
909
0
    UINT64_C(3546284192), // A2_addpsat
910
0
    UINT64_C(4131389440), // A2_addsat
911
0
    UINT64_C(3546284256), // A2_addsph
912
0
    UINT64_C(3546284224), // A2_addspl
913
0
    UINT64_C(4043309056), // A2_and
914
0
    UINT64_C(1979711488), // A2_andir
915
0
    UINT64_C(3554672640), // A2_andp
916
0
    UINT64_C(1879048192), // A2_aslh
917
0
    UINT64_C(1881145344), // A2_asrh
918
0
    UINT64_C(4085252096), // A2_combine_hh
919
0
    UINT64_C(4087349248), // A2_combine_hl
920
0
    UINT64_C(4089446400), // A2_combine_lh
921
0
    UINT64_C(4091543552), // A2_combine_ll
922
0
    UINT64_C(2080374784), // A2_combineii
923
0
    UINT64_C(4110417920), // A2_combinew
924
0
    UINT64_C(3586129920), // A2_max
925
0
    UINT64_C(3552575616), // A2_maxp
926
0
    UINT64_C(3586130048), // A2_maxu
927
0
    UINT64_C(3552575648), // A2_maxup
928
0
    UINT64_C(3584032768), // A2_min
929
0
    UINT64_C(3550478528), // A2_minp
930
0
    UINT64_C(3584032896), // A2_minu
931
0
    UINT64_C(3550478560), // A2_minup
932
0
    UINT64_C(2155872416), // A2_negp
933
0
    UINT64_C(2357199040), // A2_negsat
934
0
    UINT64_C(2130706432), // A2_nop
935
0
    UINT64_C(2155872384), // A2_notp
936
0
    UINT64_C(4045406208), // A2_or
937
0
    UINT64_C(1988100096), // A2_orir
938
0
    UINT64_C(3554672704), // A2_orp
939
0
    UINT64_C(4211081344), // A2_paddf
940
0
    UINT64_C(4211089536), // A2_paddfnew
941
0
    UINT64_C(1954545664), // A2_paddif
942
0
    UINT64_C(1954553856), // A2_paddifnew
943
0
    UINT64_C(1946157056), // A2_paddit
944
0
    UINT64_C(1946165248), // A2_padditnew
945
0
    UINT64_C(4211081216), // A2_paddt
946
0
    UINT64_C(4211089408), // A2_paddtnew
947
0
    UINT64_C(4177526912), // A2_pandf
948
0
    UINT64_C(4177535104), // A2_pandfnew
949
0
    UINT64_C(4177526784), // A2_pandt
950
0
    UINT64_C(4177534976), // A2_pandtnew
951
0
    UINT64_C(4179624064), // A2_porf
952
0
    UINT64_C(4179632256), // A2_porfnew
953
0
    UINT64_C(4179623936), // A2_port
954
0
    UINT64_C(4179632128), // A2_portnew
955
0
    UINT64_C(4213178496), // A2_psubf
956
0
    UINT64_C(4213186688), // A2_psubfnew
957
0
    UINT64_C(4213178368), // A2_psubt
958
0
    UINT64_C(4213186560), // A2_psubtnew
959
0
    UINT64_C(4183818368), // A2_pxorf
960
0
    UINT64_C(4183826560), // A2_pxorfnew
961
0
    UINT64_C(4183818240), // A2_pxort
962
0
    UINT64_C(4183826432), // A2_pxortnew
963
0
    UINT64_C(2294284320), // A2_roundsat
964
0
    UINT64_C(2294284288), // A2_sat
965
0
    UINT64_C(2361393376), // A2_satb
966
0
    UINT64_C(2361393280), // A2_sath
967
0
    UINT64_C(2361393344), // A2_satub
968
0
    UINT64_C(2361393312), // A2_satuh
969
0
    UINT64_C(4078960640), // A2_sub
970
0
    UINT64_C(3579838560), // A2_subh_h16_hh
971
0
    UINT64_C(3579838528), // A2_subh_h16_hl
972
0
    UINT64_C(3579838496), // A2_subh_h16_lh
973
0
    UINT64_C(3579838464), // A2_subh_h16_ll
974
0
    UINT64_C(3579838688), // A2_subh_h16_sat_hh
975
0
    UINT64_C(3579838656), // A2_subh_h16_sat_hl
976
0
    UINT64_C(3579838624), // A2_subh_h16_sat_lh
977
0
    UINT64_C(3579838592), // A2_subh_h16_sat_ll
978
0
    UINT64_C(3575644224), // A2_subh_l16_hl
979
0
    UINT64_C(3575644160), // A2_subh_l16_ll
980
0
    UINT64_C(3575644352), // A2_subh_l16_sat_hl
981
0
    UINT64_C(3575644288), // A2_subh_l16_sat_ll
982
0
    UINT64_C(3542089952), // A2_subp
983
0
    UINT64_C(1983905792), // A2_subri
984
0
    UINT64_C(4139778048), // A2_subsat
985
0
    UINT64_C(4127195136), // A2_svaddh
986
0
    UINT64_C(4129292288), // A2_svaddhs
987
0
    UINT64_C(4133486592), // A2_svadduhs
988
0
    UINT64_C(4143972352), // A2_svavgh
989
0
    UINT64_C(4146069504), // A2_svavghs
990
0
    UINT64_C(4150263808), // A2_svnavgh
991
0
    UINT64_C(4135583744), // A2_svsubh
992
0
    UINT64_C(4137680896), // A2_svsubhs
993
0
    UINT64_C(4141875200), // A2_svsubuhs
994
0
    UINT64_C(2357199072), // A2_swiz
995
0
    UINT64_C(1889533952), // A2_sxtb
996
0
    UINT64_C(1893728256), // A2_sxth
997
0
    UINT64_C(2218786816), // A2_sxtw
998
0
    UINT64_C(1885339648), // A2_tfr
999
0
    UINT64_C(1778384896), // A2_tfrcrr
1000
0
    UINT64_C(1914699776), // A2_tfrih
1001
0
    UINT64_C(1897922560), // A2_tfril
1002
0
    UINT64_C(1646264320), // A2_tfrrcr
1003
0
    UINT64_C(2013265920), // A2_tfrsi
1004
0
    UINT64_C(2151678080), // A2_vabsh
1005
0
    UINT64_C(2151678112), // A2_vabshsat
1006
0
    UINT64_C(2151678144), // A2_vabsw
1007
0
    UINT64_C(2151678176), // A2_vabswsat
1008
0
    UINT64_C(3539992640), // A2_vaddh
1009
0
    UINT64_C(3539992672), // A2_vaddhs
1010
0
    UINT64_C(3539992576), // A2_vaddub
1011
0
    UINT64_C(3539992608), // A2_vaddubs
1012
0
    UINT64_C(3539992704), // A2_vadduhs
1013
0
    UINT64_C(3539992736), // A2_vaddw
1014
0
    UINT64_C(3539992768), // A2_vaddws
1015
0
    UINT64_C(3544186944), // A2_vavgh
1016
0
    UINT64_C(3544187008), // A2_vavghcr
1017
0
    UINT64_C(3544186976), // A2_vavghr
1018
0
    UINT64_C(3544186880), // A2_vavgub
1019
0
    UINT64_C(3544186912), // A2_vavgubr
1020
0
    UINT64_C(3544187040), // A2_vavguh
1021
0
    UINT64_C(3544187072), // A2_vavguhr
1022
0
    UINT64_C(3546284128), // A2_vavguw
1023
0
    UINT64_C(3546284160), // A2_vavguwr
1024
0
    UINT64_C(3546284032), // A2_vavgw
1025
0
    UINT64_C(3546284096), // A2_vavgwcr
1026
0
    UINT64_C(3546284064), // A2_vavgwr
1027
0
    UINT64_C(3523215552), // A2_vcmpbeq
1028
0
    UINT64_C(3523215584), // A2_vcmpbgtu
1029
0
    UINT64_C(3523215456), // A2_vcmpheq
1030
0
    UINT64_C(3523215488), // A2_vcmphgt
1031
0
    UINT64_C(3523215520), // A2_vcmphgtu
1032
0
    UINT64_C(3523215360), // A2_vcmpweq
1033
0
    UINT64_C(3523215392), // A2_vcmpwgt
1034
0
    UINT64_C(3523215424), // A2_vcmpwgtu
1035
0
    UINT64_C(2155872480), // A2_vconj
1036
0
    UINT64_C(3552575680), // A2_vmaxb
1037
0
    UINT64_C(3552575520), // A2_vmaxh
1038
0
    UINT64_C(3552575488), // A2_vmaxub
1039
0
    UINT64_C(3552575552), // A2_vmaxuh
1040
0
    UINT64_C(3550478496), // A2_vmaxuw
1041
0
    UINT64_C(3552575584), // A2_vmaxw
1042
0
    UINT64_C(3552575712), // A2_vminb
1043
0
    UINT64_C(3550478368), // A2_vminh
1044
0
    UINT64_C(3550478336), // A2_vminub
1045
0
    UINT64_C(3550478400), // A2_vminuh
1046
0
    UINT64_C(3550478464), // A2_vminuw
1047
0
    UINT64_C(3550478432), // A2_vminw
1048
0
    UINT64_C(3548381184), // A2_vnavgh
1049
0
    UINT64_C(3548381248), // A2_vnavghcr
1050
0
    UINT64_C(3548381216), // A2_vnavghr
1051
0
    UINT64_C(3548381280), // A2_vnavgw
1052
0
    UINT64_C(3548381376), // A2_vnavgwcr
1053
0
    UINT64_C(3548381312), // A2_vnavgwr
1054
0
    UINT64_C(3896508448), // A2_vraddub
1055
0
    UINT64_C(3930062880), // A2_vraddub_acc
1056
0
    UINT64_C(3896508480), // A2_vrsadub
1057
0
    UINT64_C(3930062912), // A2_vrsadub_acc
1058
0
    UINT64_C(3542089792), // A2_vsubh
1059
0
    UINT64_C(3542089824), // A2_vsubhs
1060
0
    UINT64_C(3542089728), // A2_vsubub
1061
0
    UINT64_C(3542089760), // A2_vsububs
1062
0
    UINT64_C(3542089856), // A2_vsubuhs
1063
0
    UINT64_C(3542089888), // A2_vsubw
1064
0
    UINT64_C(3542089920), // A2_vsubws
1065
0
    UINT64_C(4049600512), // A2_xor
1066
0
    UINT64_C(3554672768), // A2_xorp
1067
0
    UINT64_C(1891631104), // A2_zxth
1068
0
    UINT64_C(3267362816), // A4_addp_c
1069
0
    UINT64_C(4051697664), // A4_andn
1070
0
    UINT64_C(3554672672), // A4_andnp
1071
0
    UINT64_C(3558866944), // A4_bitsplit
1072
0
    UINT64_C(2294284416), // A4_bitspliti
1073
0
    UINT64_C(3523223712), // A4_boundscheck_hi
1074
0
    UINT64_C(3523223680), // A4_boundscheck_lo
1075
0
    UINT64_C(3351249088), // A4_cmpbeq
1076
0
    UINT64_C(3707764736), // A4_cmpbeqi
1077
0
    UINT64_C(3351248960), // A4_cmpbgt
1078
0
    UINT64_C(3709861888), // A4_cmpbgti
1079
0
    UINT64_C(3351249120), // A4_cmpbgtu
1080
0
    UINT64_C(3711959040), // A4_cmpbgtui
1081
0
    UINT64_C(3351248992), // A4_cmpheq
1082
0
    UINT64_C(3707764744), // A4_cmpheqi
1083
0
    UINT64_C(3351249024), // A4_cmphgt
1084
0
    UINT64_C(3709861896), // A4_cmphgti
1085
0
    UINT64_C(3351249056), // A4_cmphgtu
1086
0
    UINT64_C(3711959048), // A4_cmphgtui
1087
0
    UINT64_C(2088763392), // A4_combineii
1088
0
    UINT64_C(1931485184), // A4_combineir
1089
0
    UINT64_C(1929388032), // A4_combineri
1090
0
    UINT64_C(2363490304), // A4_cround_ri
1091
0
    UINT64_C(3334471680), // A4_cround_rr
1092
0
    UINT64_C(0),  // A4_ext
1093
0
    UINT64_C(3554672864), // A4_modwrapu
1094
0
    UINT64_C(4053794816), // A4_orn
1095
0
    UINT64_C(3554672736), // A4_ornp
1096
0
    UINT64_C(1879058432), // A4_paslhf
1097
0
    UINT64_C(1879059456), // A4_paslhfnew
1098
0
    UINT64_C(1879056384), // A4_paslht
1099
0
    UINT64_C(1879057408), // A4_paslhtnew
1100
0
    UINT64_C(1881155584), // A4_pasrhf
1101
0
    UINT64_C(1881156608), // A4_pasrhfnew
1102
0
    UINT64_C(1881153536), // A4_pasrht
1103
0
    UINT64_C(1881154560), // A4_pasrhtnew
1104
0
    UINT64_C(1889544192), // A4_psxtbf
1105
0
    UINT64_C(1889545216), // A4_psxtbfnew
1106
0
    UINT64_C(1889542144), // A4_psxtbt
1107
0
    UINT64_C(1889543168), // A4_psxtbtnew
1108
0
    UINT64_C(1893738496), // A4_psxthf
1109
0
    UINT64_C(1893739520), // A4_psxthfnew
1110
0
    UINT64_C(1893736448), // A4_psxtht
1111
0
    UINT64_C(1893737472), // A4_psxthtnew
1112
0
    UINT64_C(1887447040), // A4_pzxtbf
1113
0
    UINT64_C(1887448064), // A4_pzxtbfnew
1114
0
    UINT64_C(1887444992), // A4_pzxtbt
1115
0
    UINT64_C(1887446016), // A4_pzxtbtnew
1116
0
    UINT64_C(1891641344), // A4_pzxthf
1117
0
    UINT64_C(1891642368), // A4_pzxthfnew
1118
0
    UINT64_C(1891639296), // A4_pzxtht
1119
0
    UINT64_C(1891640320), // A4_pzxthtnew
1120
0
    UINT64_C(4081057792), // A4_rcmpeq
1121
0
    UINT64_C(1933582336), // A4_rcmpeqi
1122
0
    UINT64_C(4083154944), // A4_rcmpneq
1123
0
    UINT64_C(1935679488), // A4_rcmpneqi
1124
0
    UINT64_C(2363490432), // A4_round_ri
1125
0
    UINT64_C(2363490496), // A4_round_ri_sat
1126
0
    UINT64_C(3334471808), // A4_round_rr
1127
0
    UINT64_C(3334471872), // A4_round_rr_sat
1128
0
    UINT64_C(3269459968), // A4_subp_c
1129
0
    UINT64_C(1744830464), // A4_tfrcpp
1130
0
    UINT64_C(1663041536), // A4_tfrpcp
1131
0
    UINT64_C(3523223648), // A4_tlbmatch
1132
0
    UINT64_C(3523223552), // A4_vcmpbeq_any
1133
0
    UINT64_C(3690987520), // A4_vcmpbeqi
1134
0
    UINT64_C(3523223616), // A4_vcmpbgt
1135
0
    UINT64_C(3693084672), // A4_vcmpbgti
1136
0
    UINT64_C(3695181824), // A4_vcmpbgtui
1137
0
    UINT64_C(3690987528), // A4_vcmpheqi
1138
0
    UINT64_C(3693084680), // A4_vcmphgti
1139
0
    UINT64_C(3695181832), // A4_vcmphgtui
1140
0
    UINT64_C(3690987536), // A4_vcmpweqi
1141
0
    UINT64_C(3693084688), // A4_vcmpwgti
1142
0
    UINT64_C(3695181840), // A4_vcmpwgtui
1143
0
    UINT64_C(3407872032), // A4_vrmaxh
1144
0
    UINT64_C(3407880224), // A4_vrmaxuh
1145
0
    UINT64_C(3407880256), // A4_vrmaxuw
1146
0
    UINT64_C(3407872064), // A4_vrmaxw
1147
0
    UINT64_C(3407872160), // A4_vrminh
1148
0
    UINT64_C(3407880352), // A4_vrminuh
1149
0
    UINT64_C(3407880384), // A4_vrminuw
1150
0
    UINT64_C(3407872192), // A4_vrminw
1151
0
    UINT64_C(3936354304), // A5_ACS
1152
0
    UINT64_C(3242197024), // A5_vaddhubs
1153
0
    UINT64_C(3523223584), // A6_vcmpbeq_notany
1154
0
    UINT64_C(3940548608), // A6_vminub_RdP
1155
0
    UINT64_C(2294284448), // A7_clip
1156
0
    UINT64_C(2363490368), // A7_croundd_ri
1157
0
    UINT64_C(3334471744), // A7_croundd_rr
1158
0
    UINT64_C(2294284480), // A7_vclip
1159
0
    UINT64_C(1805647872), // C2_all8
1160
0
    UINT64_C(1795162112), // C2_and
1161
0
    UINT64_C(1801453568), // C2_andn
1162
0
    UINT64_C(1803550720), // C2_any8
1163
0
    UINT64_C(3347054592), // C2_bitsclr
1164
0
    UINT64_C(2239758336), // C2_bitsclri
1165
0
    UINT64_C(3342860288), // C2_bitsset
1166
0
    UINT64_C(4244635776), // C2_ccombinewf
1167
0
    UINT64_C(4244643968), // C2_ccombinewnewf
1168
0
    UINT64_C(4244643840), // C2_ccombinewnewt
1169
0
    UINT64_C(4244635648), // C2_ccombinewt
1170
0
    UINT64_C(2122317824), // C2_cmoveif
1171
0
    UINT64_C(2113929216), // C2_cmoveit
1172
0
    UINT64_C(2122326016), // C2_cmovenewif
1173
0
    UINT64_C(2113937408), // C2_cmovenewit
1174
0
    UINT64_C(4060086272), // C2_cmpeq
1175
0
    UINT64_C(1962934272), // C2_cmpeqi
1176
0
    UINT64_C(3531603968), // C2_cmpeqp
1177
0
    UINT64_C(4064280576), // C2_cmpgt
1178
0
    UINT64_C(1967128576), // C2_cmpgti
1179
0
    UINT64_C(3531604032), // C2_cmpgtp
1180
0
    UINT64_C(4066377728), // C2_cmpgtu
1181
0
    UINT64_C(1971322880), // C2_cmpgtui
1182
0
    UINT64_C(3531604096), // C2_cmpgtup
1183
0
    UINT64_C(2248146944), // C2_mask
1184
0
    UINT64_C(4093640704), // C2_mux
1185
0
    UINT64_C(2046820352), // C2_muxii
1186
0
    UINT64_C(1929379840), // C2_muxir
1187
0
    UINT64_C(1937768448), // C2_muxri
1188
0
    UINT64_C(1807745024), // C2_not
1189
0
    UINT64_C(1797259264), // C2_or
1190
0
    UINT64_C(1809842176), // C2_orn
1191
0
    UINT64_C(2302672896), // C2_tfrpr
1192
0
    UINT64_C(2235564032), // C2_tfrrp
1193
0
    UINT64_C(2298478592), // C2_vitpack
1194
0
    UINT64_C(3506438144), // C2_vmux
1195
0
    UINT64_C(1799356416), // C2_xor
1196
0
    UINT64_C(1783169024), // C4_addipc
1197
0
    UINT64_C(1796210688), // C4_and_and
1198
0
    UINT64_C(1804599296), // C4_and_andn
1199
0
    UINT64_C(1798307840), // C4_and_or
1200
0
    UINT64_C(1806696448), // C4_and_orn
1201
0
    UINT64_C(4064280592), // C4_cmplte
1202
0
    UINT64_C(1967128592), // C4_cmpltei
1203
0
    UINT64_C(4066377744), // C4_cmplteu
1204
0
    UINT64_C(1971322896), // C4_cmplteui
1205
0
    UINT64_C(4060086288), // C4_cmpneq
1206
0
    UINT64_C(1962934288), // C4_cmpneqi
1207
0
    UINT64_C(1795170448), // C4_fastcorner9
1208
0
    UINT64_C(1796219024), // C4_fastcorner9_not
1209
0
    UINT64_C(3349151744), // C4_nbitsclr
1210
0
    UINT64_C(2241855488), // C4_nbitsclri
1211
0
    UINT64_C(3344957440), // C4_nbitsset
1212
0
    UINT64_C(1800404992), // C4_or_and
1213
0
    UINT64_C(1808793600), // C4_or_andn
1214
0
    UINT64_C(1802502144), // C4_or_or
1215
0
    UINT64_C(1810890752), // C4_or_orn
1216
0
    UINT64_C(1509949440), // CALLProfile
1217
0
    UINT64_C(0),  // CONST32
1218
0
    UINT64_C(0),  // CONST64
1219
0
    UINT64_C(0),  // DuplexIClass0
1220
0
    UINT64_C(8192), // DuplexIClass1
1221
0
    UINT64_C(536870912),  // DuplexIClass2
1222
0
    UINT64_C(536879104),  // DuplexIClass3
1223
0
    UINT64_C(1073741824), // DuplexIClass4
1224
0
    UINT64_C(1073750016), // DuplexIClass5
1225
0
    UINT64_C(1610612736), // DuplexIClass6
1226
0
    UINT64_C(1610620928), // DuplexIClass7
1227
0
    UINT64_C(2147483648), // DuplexIClass8
1228
0
    UINT64_C(2147491840), // DuplexIClass9
1229
0
    UINT64_C(2684354560), // DuplexIClassA
1230
0
    UINT64_C(2684362752), // DuplexIClassB
1231
0
    UINT64_C(3221225472), // DuplexIClassC
1232
0
    UINT64_C(3221233664), // DuplexIClassD
1233
0
    UINT64_C(3758096384), // DuplexIClassE
1234
0
    UINT64_C(3758104576), // DuplexIClassF
1235
0
    UINT64_C(1384120320), // EH_RETURN_JMPR
1236
0
    UINT64_C(2162163808), // F2_conv_d2df
1237
0
    UINT64_C(2285895712), // F2_conv_d2sf
1238
0
    UINT64_C(2162163712), // F2_conv_df2d
1239
0
    UINT64_C(2162163904), // F2_conv_df2d_chop
1240
0
    UINT64_C(2281701408), // F2_conv_df2sf
1241
0
    UINT64_C(2162163744), // F2_conv_df2ud
1242
0
    UINT64_C(2162163936), // F2_conv_df2ud_chop
1243
0
    UINT64_C(2287992864), // F2_conv_df2uw
1244
0
    UINT64_C(2292187168), // F2_conv_df2uw_chop
1245
0
    UINT64_C(2290090016), // F2_conv_df2w
1246
0
    UINT64_C(2296381472), // F2_conv_df2w_chop
1247
0
    UINT64_C(2222981248), // F2_conv_sf2d
1248
0
    UINT64_C(2222981312), // F2_conv_sf2d_chop
1249
0
    UINT64_C(2222981120), // F2_conv_sf2df
1250
0
    UINT64_C(2222981216), // F2_conv_sf2ud
1251
0
    UINT64_C(2222981280), // F2_conv_sf2ud_chop
1252
0
    UINT64_C(2338324480), // F2_conv_sf2uw
1253
0
    UINT64_C(2338324512), // F2_conv_sf2uw_chop
1254
0
    UINT64_C(2340421632), // F2_conv_sf2w
1255
0
    UINT64_C(2340421664), // F2_conv_sf2w_chop
1256
0
    UINT64_C(2162163776), // F2_conv_ud2df
1257
0
    UINT64_C(2283798560), // F2_conv_ud2sf
1258
0
    UINT64_C(2222981152), // F2_conv_uw2df
1259
0
    UINT64_C(2334130176), // F2_conv_uw2sf
1260
0
    UINT64_C(2222981184), // F2_conv_w2df
1261
0
    UINT64_C(2336227328), // F2_conv_w2sf
1262
0
    UINT64_C(3892314208), // F2_dfadd
1263
0
    UINT64_C(3699376144), // F2_dfclass
1264
0
    UINT64_C(3537895424), // F2_dfcmpeq
1265
0
    UINT64_C(3537895488), // F2_dfcmpge
1266
0
    UINT64_C(3537895456), // F2_dfcmpgt
1267
0
    UINT64_C(3537895520), // F2_dfcmpuo
1268
0
    UINT64_C(3644850176), // F2_dfimm_n
1269
0
    UINT64_C(3640655872), // F2_dfimm_p
1270
0
    UINT64_C(3894411360), // F2_dfmax
1271
0
    UINT64_C(3904897120), // F2_dfmin
1272
0
    UINT64_C(3896508512), // F2_dfmpyfix
1273
0
    UINT64_C(3934257248), // F2_dfmpyhh
1274
0
    UINT64_C(3925868640), // F2_dfmpylh
1275
0
    UINT64_C(3902799968), // F2_dfmpyll
1276
0
    UINT64_C(3900702816), // F2_dfsub
1277
0
    UINT64_C(3942645760), // F2_sfadd
1278
0
    UINT64_C(2246049792), // F2_sfclass
1279
0
    UINT64_C(3353346144), // F2_sfcmpeq
1280
0
    UINT64_C(3353346048), // F2_sfcmpge
1281
0
    UINT64_C(3353346176), // F2_sfcmpgt
1282
0
    UINT64_C(3353346080), // F2_sfcmpuo
1283
0
    UINT64_C(3955228704), // F2_sffixupd
1284
0
    UINT64_C(3955228672), // F2_sffixupn
1285
0
    UINT64_C(2342518784), // F2_sffixupr
1286
0
    UINT64_C(4009754752), // F2_sffma
1287
0
    UINT64_C(4009754816), // F2_sffma_lib
1288
0
    UINT64_C(4016046208), // F2_sffma_sc
1289
0
    UINT64_C(4009754784), // F2_sffms
1290
0
    UINT64_C(4009754848), // F2_sffms_lib
1291
0
    UINT64_C(3594518528), // F2_sfimm_n
1292
0
    UINT64_C(3590324224), // F2_sfimm_p
1293
0
    UINT64_C(2346713088), // F2_sfinvsqrta
1294
0
    UINT64_C(3951034368), // F2_sfmax
1295
0
    UINT64_C(3951034400), // F2_sfmin
1296
0
    UINT64_C(3946840064), // F2_sfmpy
1297
0
    UINT64_C(3957325952), // F2_sfrecipa
1298
0
    UINT64_C(3942645792), // F2_sfsub
1299
0
    UINT64_C(1746927616), // G4_tfrgcpp
1300
0
    UINT64_C(1780482048), // G4_tfrgcrr
1301
0
    UINT64_C(1660944384), // G4_tfrgpcp
1302
0
    UINT64_C(1644167168), // G4_tfrgrcr
1303
0
    UINT64_C(35651584), // HI
1304
0
    UINT64_C(1509949440), // J2_call
1305
0
    UINT64_C(1562378240), // J2_callf
1306
0
    UINT64_C(1352663040), // J2_callr
1307
0
    UINT64_C(1361051648), // J2_callrf
1308
0
    UINT64_C(1354760192), // J2_callrh
1309
0
    UINT64_C(1358954496), // J2_callrt
1310
0
    UINT64_C(1560281088), // J2_callt
1311
0
    UINT64_C(1476395008), // J2_jump
1312
0
    UINT64_C(1545601024), // J2_jumpf
1313
0
    UINT64_C(1545603072), // J2_jumpfnew
1314
0
    UINT64_C(1545607168), // J2_jumpfnewpt
1315
0
    UINT64_C(1545605120), // J2_jumpfpt
1316
0
    UINT64_C(1384120320), // J2_jumpr
1317
0
    UINT64_C(1398800384), // J2_jumprf
1318
0
    UINT64_C(1398802432), // J2_jumprfnew
1319
0
    UINT64_C(1398806528), // J2_jumprfnewpt
1320
0
    UINT64_C(1398804480), // J2_jumprfpt
1321
0
    UINT64_C(1631584256), // J2_jumprgtez
1322
0
    UINT64_C(1631588352), // J2_jumprgtezpt
1323
0
    UINT64_C(1388314624), // J2_jumprh
1324
0
    UINT64_C(1639972864), // J2_jumprltez
1325
0
    UINT64_C(1639976960), // J2_jumprltezpt
1326
0
    UINT64_C(1635778560), // J2_jumprnz
1327
0
    UINT64_C(1635782656), // J2_jumprnzpt
1328
0
    UINT64_C(1396703232), // J2_jumprt
1329
0
    UINT64_C(1396705280), // J2_jumprtnew
1330
0
    UINT64_C(1396709376), // J2_jumprtnewpt
1331
0
    UINT64_C(1396707328), // J2_jumprtpt
1332
0
    UINT64_C(1627389952), // J2_jumprz
1333
0
    UINT64_C(1627394048), // J2_jumprzpt
1334
0
    UINT64_C(1543503872), // J2_jumpt
1335
0
    UINT64_C(1543505920), // J2_jumptnew
1336
0
    UINT64_C(1543510016), // J2_jumptnewpt
1337
0
    UINT64_C(1543507968), // J2_jumptpt
1338
0
    UINT64_C(1761607680), // J2_loop0i
1339
0
    UINT64_C(1761607680), // J2_loop0iext
1340
0
    UINT64_C(1610612736), // J2_loop0r
1341
0
    UINT64_C(1610612736), // J2_loop0rext
1342
0
    UINT64_C(1763704832), // J2_loop1i
1343
0
    UINT64_C(1763704832), // J2_loop1iext
1344
0
    UINT64_C(1612709888), // J2_loop1r
1345
0
    UINT64_C(1612709888), // J2_loop1rext
1346
0
    UINT64_C(1413480448), // J2_pause
1347
0
    UINT64_C(1772093440), // J2_ploop1si
1348
0
    UINT64_C(1621098496), // J2_ploop1sr
1349
0
    UINT64_C(1774190592), // J2_ploop2si
1350
0
    UINT64_C(1623195648), // J2_ploop2sr
1351
0
    UINT64_C(1776287744), // J2_ploop3si
1352
0
    UINT64_C(1625292800), // J2_ploop3sr
1353
0
    UINT64_C(1474297856), // J2_rte
1354
0
    UINT64_C(1409286144), // J2_trap0
1355
0
    UINT64_C(1417674752), // J2_trap1
1356
0
    UINT64_C(1474301952), // J2_unpause
1357
0
    UINT64_C(541065216),  // J4_cmpeq_f_jumpnv_nt
1358
0
    UINT64_C(541073408),  // J4_cmpeq_f_jumpnv_t
1359
0
    UINT64_C(339738624),  // J4_cmpeq_fp0_jump_nt
1360
0
    UINT64_C(339746816),  // J4_cmpeq_fp0_jump_t
1361
0
    UINT64_C(339742720),  // J4_cmpeq_fp1_jump_nt
1362
0
    UINT64_C(339750912),  // J4_cmpeq_fp1_jump_t
1363
0
    UINT64_C(536870912),  // J4_cmpeq_t_jumpnv_nt
1364
0
    UINT64_C(536879104),  // J4_cmpeq_t_jumpnv_t
1365
0
    UINT64_C(335544320),  // J4_cmpeq_tp0_jump_nt
1366
0
    UINT64_C(335552512),  // J4_cmpeq_tp0_jump_t
1367
0
    UINT64_C(335548416),  // J4_cmpeq_tp1_jump_nt
1368
0
    UINT64_C(335556608),  // J4_cmpeq_tp1_jump_t
1369
0
    UINT64_C(608174080),  // J4_cmpeqi_f_jumpnv_nt
1370
0
    UINT64_C(608182272),  // J4_cmpeqi_f_jumpnv_t
1371
0
    UINT64_C(272629760),  // J4_cmpeqi_fp0_jump_nt
1372
0
    UINT64_C(272637952),  // J4_cmpeqi_fp0_jump_t
1373
0
    UINT64_C(306184192),  // J4_cmpeqi_fp1_jump_nt
1374
0
    UINT64_C(306192384),  // J4_cmpeqi_fp1_jump_t
1375
0
    UINT64_C(603979776),  // J4_cmpeqi_t_jumpnv_nt
1376
0
    UINT64_C(603987968),  // J4_cmpeqi_t_jumpnv_t
1377
0
    UINT64_C(268435456),  // J4_cmpeqi_tp0_jump_nt
1378
0
    UINT64_C(268443648),  // J4_cmpeqi_tp0_jump_t
1379
0
    UINT64_C(301989888),  // J4_cmpeqi_tp1_jump_nt
1380
0
    UINT64_C(301998080),  // J4_cmpeqi_tp1_jump_t
1381
0
    UINT64_C(641728512),  // J4_cmpeqn1_f_jumpnv_nt
1382
0
    UINT64_C(641736704),  // J4_cmpeqn1_f_jumpnv_t
1383
0
    UINT64_C(297795584),  // J4_cmpeqn1_fp0_jump_nt
1384
0
    UINT64_C(297803776),  // J4_cmpeqn1_fp0_jump_t
1385
0
    UINT64_C(331350016),  // J4_cmpeqn1_fp1_jump_nt
1386
0
    UINT64_C(331358208),  // J4_cmpeqn1_fp1_jump_t
1387
0
    UINT64_C(637534208),  // J4_cmpeqn1_t_jumpnv_nt
1388
0
    UINT64_C(637542400),  // J4_cmpeqn1_t_jumpnv_t
1389
0
    UINT64_C(293601280),  // J4_cmpeqn1_tp0_jump_nt
1390
0
    UINT64_C(293609472),  // J4_cmpeqn1_tp0_jump_t
1391
0
    UINT64_C(327155712),  // J4_cmpeqn1_tp1_jump_nt
1392
0
    UINT64_C(327163904),  // J4_cmpeqn1_tp1_jump_t
1393
0
    UINT64_C(549453824),  // J4_cmpgt_f_jumpnv_nt
1394
0
    UINT64_C(549462016),  // J4_cmpgt_f_jumpnv_t
1395
0
    UINT64_C(348127232),  // J4_cmpgt_fp0_jump_nt
1396
0
    UINT64_C(348135424),  // J4_cmpgt_fp0_jump_t
1397
0
    UINT64_C(348131328),  // J4_cmpgt_fp1_jump_nt
1398
0
    UINT64_C(348139520),  // J4_cmpgt_fp1_jump_t
1399
0
    UINT64_C(545259520),  // J4_cmpgt_t_jumpnv_nt
1400
0
    UINT64_C(545267712),  // J4_cmpgt_t_jumpnv_t
1401
0
    UINT64_C(343932928),  // J4_cmpgt_tp0_jump_nt
1402
0
    UINT64_C(343941120),  // J4_cmpgt_tp0_jump_t
1403
0
    UINT64_C(343937024),  // J4_cmpgt_tp1_jump_nt
1404
0
    UINT64_C(343945216),  // J4_cmpgt_tp1_jump_t
1405
0
    UINT64_C(616562688),  // J4_cmpgti_f_jumpnv_nt
1406
0
    UINT64_C(616570880),  // J4_cmpgti_f_jumpnv_t
1407
0
    UINT64_C(281018368),  // J4_cmpgti_fp0_jump_nt
1408
0
    UINT64_C(281026560),  // J4_cmpgti_fp0_jump_t
1409
0
    UINT64_C(314572800),  // J4_cmpgti_fp1_jump_nt
1410
0
    UINT64_C(314580992),  // J4_cmpgti_fp1_jump_t
1411
0
    UINT64_C(612368384),  // J4_cmpgti_t_jumpnv_nt
1412
0
    UINT64_C(612376576),  // J4_cmpgti_t_jumpnv_t
1413
0
    UINT64_C(276824064),  // J4_cmpgti_tp0_jump_nt
1414
0
    UINT64_C(276832256),  // J4_cmpgti_tp0_jump_t
1415
0
    UINT64_C(310378496),  // J4_cmpgti_tp1_jump_nt
1416
0
    UINT64_C(310386688),  // J4_cmpgti_tp1_jump_t
1417
0
    UINT64_C(650117120),  // J4_cmpgtn1_f_jumpnv_nt
1418
0
    UINT64_C(650125312),  // J4_cmpgtn1_f_jumpnv_t
1419
0
    UINT64_C(297795840),  // J4_cmpgtn1_fp0_jump_nt
1420
0
    UINT64_C(297804032),  // J4_cmpgtn1_fp0_jump_t
1421
0
    UINT64_C(331350272),  // J4_cmpgtn1_fp1_jump_nt
1422
0
    UINT64_C(331358464),  // J4_cmpgtn1_fp1_jump_t
1423
0
    UINT64_C(645922816),  // J4_cmpgtn1_t_jumpnv_nt
1424
0
    UINT64_C(645931008),  // J4_cmpgtn1_t_jumpnv_t
1425
0
    UINT64_C(293601536),  // J4_cmpgtn1_tp0_jump_nt
1426
0
    UINT64_C(293609728),  // J4_cmpgtn1_tp0_jump_t
1427
0
    UINT64_C(327155968),  // J4_cmpgtn1_tp1_jump_nt
1428
0
    UINT64_C(327164160),  // J4_cmpgtn1_tp1_jump_t
1429
0
    UINT64_C(557842432),  // J4_cmpgtu_f_jumpnv_nt
1430
0
    UINT64_C(557850624),  // J4_cmpgtu_f_jumpnv_t
1431
0
    UINT64_C(356515840),  // J4_cmpgtu_fp0_jump_nt
1432
0
    UINT64_C(356524032),  // J4_cmpgtu_fp0_jump_t
1433
0
    UINT64_C(356519936),  // J4_cmpgtu_fp1_jump_nt
1434
0
    UINT64_C(356528128),  // J4_cmpgtu_fp1_jump_t
1435
0
    UINT64_C(553648128),  // J4_cmpgtu_t_jumpnv_nt
1436
0
    UINT64_C(553656320),  // J4_cmpgtu_t_jumpnv_t
1437
0
    UINT64_C(352321536),  // J4_cmpgtu_tp0_jump_nt
1438
0
    UINT64_C(352329728),  // J4_cmpgtu_tp0_jump_t
1439
0
    UINT64_C(352325632),  // J4_cmpgtu_tp1_jump_nt
1440
0
    UINT64_C(352333824),  // J4_cmpgtu_tp1_jump_t
1441
0
    UINT64_C(624951296),  // J4_cmpgtui_f_jumpnv_nt
1442
0
    UINT64_C(624959488),  // J4_cmpgtui_f_jumpnv_t
1443
0
    UINT64_C(289406976),  // J4_cmpgtui_fp0_jump_nt
1444
0
    UINT64_C(289415168),  // J4_cmpgtui_fp0_jump_t
1445
0
    UINT64_C(322961408),  // J4_cmpgtui_fp1_jump_nt
1446
0
    UINT64_C(322969600),  // J4_cmpgtui_fp1_jump_t
1447
0
    UINT64_C(620756992),  // J4_cmpgtui_t_jumpnv_nt
1448
0
    UINT64_C(620765184),  // J4_cmpgtui_t_jumpnv_t
1449
0
    UINT64_C(285212672),  // J4_cmpgtui_tp0_jump_nt
1450
0
    UINT64_C(285220864),  // J4_cmpgtui_tp0_jump_t
1451
0
    UINT64_C(318767104),  // J4_cmpgtui_tp1_jump_nt
1452
0
    UINT64_C(318775296),  // J4_cmpgtui_tp1_jump_t
1453
0
    UINT64_C(566231040),  // J4_cmplt_f_jumpnv_nt
1454
0
    UINT64_C(566239232),  // J4_cmplt_f_jumpnv_t
1455
0
    UINT64_C(562036736),  // J4_cmplt_t_jumpnv_nt
1456
0
    UINT64_C(562044928),  // J4_cmplt_t_jumpnv_t
1457
0
    UINT64_C(574619648),  // J4_cmpltu_f_jumpnv_nt
1458
0
    UINT64_C(574627840),  // J4_cmpltu_f_jumpnv_t
1459
0
    UINT64_C(570425344),  // J4_cmpltu_t_jumpnv_nt
1460
0
    UINT64_C(570433536),  // J4_cmpltu_t_jumpnv_t
1461
0
    UINT64_C(1386217472), // J4_hintjumpr
1462
0
    UINT64_C(369098752),  // J4_jumpseti
1463
0
    UINT64_C(385875968),  // J4_jumpsetr
1464
0
    UINT64_C(633339904),  // J4_tstbit0_f_jumpnv_nt
1465
0
    UINT64_C(633348096),  // J4_tstbit0_f_jumpnv_t
1466
0
    UINT64_C(297796352),  // J4_tstbit0_fp0_jump_nt
1467
0
    UINT64_C(297804544),  // J4_tstbit0_fp0_jump_t
1468
0
    UINT64_C(331350784),  // J4_tstbit0_fp1_jump_nt
1469
0
    UINT64_C(331358976),  // J4_tstbit0_fp1_jump_t
1470
0
    UINT64_C(629145600),  // J4_tstbit0_t_jumpnv_nt
1471
0
    UINT64_C(629153792),  // J4_tstbit0_t_jumpnv_t
1472
0
    UINT64_C(293602048),  // J4_tstbit0_tp0_jump_nt
1473
0
    UINT64_C(293610240),  // J4_tstbit0_tp0_jump_t
1474
0
    UINT64_C(327156480),  // J4_tstbit0_tp1_jump_nt
1475
0
    UINT64_C(327164672),  // J4_tstbit0_tp1_jump_t
1476
0
    UINT64_C(2415919104), // L2_deallocframe
1477
0
    UINT64_C(2424307712), // L2_loadalignb_io
1478
0
    UINT64_C(2659188736), // L2_loadalignb_pbr
1479
0
    UINT64_C(2558525440), // L2_loadalignb_pci
1480
0
    UINT64_C(2558525952), // L2_loadalignb_pcr
1481
0
    UINT64_C(2592079872), // L2_loadalignb_pi
1482
0
    UINT64_C(2625634304), // L2_loadalignb_pr
1483
0
    UINT64_C(2420113408), // L2_loadalignh_io
1484
0
    UINT64_C(2654994432), // L2_loadalignh_pbr
1485
0
    UINT64_C(2554331136), // L2_loadalignh_pci
1486
0
    UINT64_C(2554331648), // L2_loadalignh_pcr
1487
0
    UINT64_C(2587885568), // L2_loadalignh_pi
1488
0
    UINT64_C(2621440000), // L2_loadalignh_pr
1489
0
    UINT64_C(2418016256), // L2_loadbsw2_io
1490
0
    UINT64_C(2652897280), // L2_loadbsw2_pbr
1491
0
    UINT64_C(2552233984), // L2_loadbsw2_pci
1492
0
    UINT64_C(2552234496), // L2_loadbsw2_pcr
1493
0
    UINT64_C(2585788416), // L2_loadbsw2_pi
1494
0
    UINT64_C(2619342848), // L2_loadbsw2_pr
1495
0
    UINT64_C(2430599168), // L2_loadbsw4_io
1496
0
    UINT64_C(2665480192), // L2_loadbsw4_pbr
1497
0
    UINT64_C(2564816896), // L2_loadbsw4_pci
1498
0
    UINT64_C(2564817408), // L2_loadbsw4_pcr
1499
0
    UINT64_C(2598371328), // L2_loadbsw4_pi
1500
0
    UINT64_C(2631925760), // L2_loadbsw4_pr
1501
0
    UINT64_C(2422210560), // L2_loadbzw2_io
1502
0
    UINT64_C(2657091584), // L2_loadbzw2_pbr
1503
0
    UINT64_C(2556428288), // L2_loadbzw2_pci
1504
0
    UINT64_C(2556428800), // L2_loadbzw2_pcr
1505
0
    UINT64_C(2589982720), // L2_loadbzw2_pi
1506
0
    UINT64_C(2623537152), // L2_loadbzw2_pr
1507
0
    UINT64_C(2426404864), // L2_loadbzw4_io
1508
0
    UINT64_C(2661285888), // L2_loadbzw4_pbr
1509
0
    UINT64_C(2560622592), // L2_loadbzw4_pci
1510
0
    UINT64_C(2560623104), // L2_loadbzw4_pcr
1511
0
    UINT64_C(2594177024), // L2_loadbzw4_pi
1512
0
    UINT64_C(2627731456), // L2_loadbzw4_pr
1513
0
    UINT64_C(2432696320), // L2_loadrb_io
1514
0
    UINT64_C(2667577344), // L2_loadrb_pbr
1515
0
    UINT64_C(2566914048), // L2_loadrb_pci
1516
0
    UINT64_C(2566914560), // L2_loadrb_pcr
1517
0
    UINT64_C(2600468480), // L2_loadrb_pi
1518
0
    UINT64_C(2634022912), // L2_loadrb_pr
1519
0
    UINT64_C(1224736768), // L2_loadrbgp
1520
0
    UINT64_C(2445279232), // L2_loadrd_io
1521
0
    UINT64_C(2680160256), // L2_loadrd_pbr
1522
0
    UINT64_C(2579496960), // L2_loadrd_pci
1523
0
    UINT64_C(2579497472), // L2_loadrd_pcr
1524
0
    UINT64_C(2613051392), // L2_loadrd_pi
1525
0
    UINT64_C(2646605824), // L2_loadrd_pr
1526
0
    UINT64_C(1237319680), // L2_loadrdgp
1527
0
    UINT64_C(2436890624), // L2_loadrh_io
1528
0
    UINT64_C(2671771648), // L2_loadrh_pbr
1529
0
    UINT64_C(2571108352), // L2_loadrh_pci
1530
0
    UINT64_C(2571108864), // L2_loadrh_pcr
1531
0
    UINT64_C(2604662784), // L2_loadrh_pi
1532
0
    UINT64_C(2638217216), // L2_loadrh_pr
1533
0
    UINT64_C(1228931072), // L2_loadrhgp
1534
0
    UINT64_C(2441084928), // L2_loadri_io
1535
0
    UINT64_C(2675965952), // L2_loadri_pbr
1536
0
    UINT64_C(2575302656), // L2_loadri_pci
1537
0
    UINT64_C(2575303168), // L2_loadri_pcr
1538
0
    UINT64_C(2608857088), // L2_loadri_pi
1539
0
    UINT64_C(2642411520), // L2_loadri_pr
1540
0
    UINT64_C(1233125376), // L2_loadrigp
1541
0
    UINT64_C(2434793472), // L2_loadrub_io
1542
0
    UINT64_C(2669674496), // L2_loadrub_pbr
1543
0
    UINT64_C(2569011200), // L2_loadrub_pci
1544
0
    UINT64_C(2569011712), // L2_loadrub_pcr
1545
0
    UINT64_C(2602565632), // L2_loadrub_pi
1546
0
    UINT64_C(2636120064), // L2_loadrub_pr
1547
0
    UINT64_C(1226833920), // L2_loadrubgp
1548
0
    UINT64_C(2438987776), // L2_loadruh_io
1549
0
    UINT64_C(2673868800), // L2_loadruh_pbr
1550
0
    UINT64_C(2573205504), // L2_loadruh_pci
1551
0
    UINT64_C(2573206016), // L2_loadruh_pcr
1552
0
    UINT64_C(2606759936), // L2_loadruh_pi
1553
0
    UINT64_C(2640314368), // L2_loadruh_pr
1554
0
    UINT64_C(1231028224), // L2_loadruhgp
1555
0
    UINT64_C(2449475584), // L2_loadw_aq
1556
0
    UINT64_C(2449473536), // L2_loadw_locked
1557
0
    UINT64_C(1157627904), // L2_ploadrbf_io
1558
0
    UINT64_C(2600478720), // L2_ploadrbf_pi
1559
0
    UINT64_C(1191182336), // L2_ploadrbfnew_io
1560
0
    UINT64_C(2600482816), // L2_ploadrbfnew_pi
1561
0
    UINT64_C(1090519040), // L2_ploadrbt_io
1562
0
    UINT64_C(2600476672), // L2_ploadrbt_pi
1563
0
    UINT64_C(1124073472), // L2_ploadrbtnew_io
1564
0
    UINT64_C(2600480768), // L2_ploadrbtnew_pi
1565
0
    UINT64_C(1170210816), // L2_ploadrdf_io
1566
0
    UINT64_C(2613061632), // L2_ploadrdf_pi
1567
0
    UINT64_C(1203765248), // L2_ploadrdfnew_io
1568
0
    UINT64_C(2613065728), // L2_ploadrdfnew_pi
1569
0
    UINT64_C(1103101952), // L2_ploadrdt_io
1570
0
    UINT64_C(2613059584), // L2_ploadrdt_pi
1571
0
    UINT64_C(1136656384), // L2_ploadrdtnew_io
1572
0
    UINT64_C(2613063680), // L2_ploadrdtnew_pi
1573
0
    UINT64_C(1161822208), // L2_ploadrhf_io
1574
0
    UINT64_C(2604673024), // L2_ploadrhf_pi
1575
0
    UINT64_C(1195376640), // L2_ploadrhfnew_io
1576
0
    UINT64_C(2604677120), // L2_ploadrhfnew_pi
1577
0
    UINT64_C(1094713344), // L2_ploadrht_io
1578
0
    UINT64_C(2604670976), // L2_ploadrht_pi
1579
0
    UINT64_C(1128267776), // L2_ploadrhtnew_io
1580
0
    UINT64_C(2604675072), // L2_ploadrhtnew_pi
1581
0
    UINT64_C(1166016512), // L2_ploadrif_io
1582
0
    UINT64_C(2608867328), // L2_ploadrif_pi
1583
0
    UINT64_C(1199570944), // L2_ploadrifnew_io
1584
0
    UINT64_C(2608871424), // L2_ploadrifnew_pi
1585
0
    UINT64_C(1098907648), // L2_ploadrit_io
1586
0
    UINT64_C(2608865280), // L2_ploadrit_pi
1587
0
    UINT64_C(1132462080), // L2_ploadritnew_io
1588
0
    UINT64_C(2608869376), // L2_ploadritnew_pi
1589
0
    UINT64_C(1159725056), // L2_ploadrubf_io
1590
0
    UINT64_C(2602575872), // L2_ploadrubf_pi
1591
0
    UINT64_C(1193279488), // L2_ploadrubfnew_io
1592
0
    UINT64_C(2602579968), // L2_ploadrubfnew_pi
1593
0
    UINT64_C(1092616192), // L2_ploadrubt_io
1594
0
    UINT64_C(2602573824), // L2_ploadrubt_pi
1595
0
    UINT64_C(1126170624), // L2_ploadrubtnew_io
1596
0
    UINT64_C(2602577920), // L2_ploadrubtnew_pi
1597
0
    UINT64_C(1163919360), // L2_ploadruhf_io
1598
0
    UINT64_C(2606770176), // L2_ploadruhf_pi
1599
0
    UINT64_C(1197473792), // L2_ploadruhfnew_io
1600
0
    UINT64_C(2606774272), // L2_ploadruhfnew_pi
1601
0
    UINT64_C(1096810496), // L2_ploadruht_io
1602
0
    UINT64_C(2606768128), // L2_ploadruht_pi
1603
0
    UINT64_C(1130364928), // L2_ploadruhtnew_io
1604
0
    UINT64_C(2606772224), // L2_ploadruhtnew_pi
1605
0
    UINT64_C(1040187392), // L4_add_memopb_io
1606
0
    UINT64_C(1042284544), // L4_add_memoph_io
1607
0
    UINT64_C(1044381696), // L4_add_memopw_io
1608
0
    UINT64_C(1040187456), // L4_and_memopb_io
1609
0
    UINT64_C(1042284608), // L4_and_memoph_io
1610
0
    UINT64_C(1044381760), // L4_and_memopw_io
1611
0
    UINT64_C(1056964608), // L4_iadd_memopb_io
1612
0
    UINT64_C(1059061760), // L4_iadd_memoph_io
1613
0
    UINT64_C(1061158912), // L4_iadd_memopw_io
1614
0
    UINT64_C(1056964672), // L4_iand_memopb_io
1615
0
    UINT64_C(1059061824), // L4_iand_memoph_io
1616
0
    UINT64_C(1061158976), // L4_iand_memopw_io
1617
0
    UINT64_C(1056964704), // L4_ior_memopb_io
1618
0
    UINT64_C(1059061856), // L4_ior_memoph_io
1619
0
    UINT64_C(1061159008), // L4_ior_memopw_io
1620
0
    UINT64_C(1056964640), // L4_isub_memopb_io
1621
0
    UINT64_C(1059061792), // L4_isub_memoph_io
1622
0
    UINT64_C(1061158944), // L4_isub_memopw_io
1623
0
    UINT64_C(2592083968), // L4_loadalignb_ap
1624
0
    UINT64_C(2625638400), // L4_loadalignb_ur
1625
0
    UINT64_C(2587889664), // L4_loadalignh_ap
1626
0
    UINT64_C(2621444096), // L4_loadalignh_ur
1627
0
    UINT64_C(2585792512), // L4_loadbsw2_ap
1628
0
    UINT64_C(2619346944), // L4_loadbsw2_ur
1629
0
    UINT64_C(2598375424), // L4_loadbsw4_ap
1630
0
    UINT64_C(2631929856), // L4_loadbsw4_ur
1631
0
    UINT64_C(2589986816), // L4_loadbzw2_ap
1632
0
    UINT64_C(2623541248), // L4_loadbzw2_ur
1633
0
    UINT64_C(2594181120), // L4_loadbzw4_ap
1634
0
    UINT64_C(2627735552), // L4_loadbzw4_ur
1635
0
    UINT64_C(2449479680), // L4_loadd_aq
1636
0
    UINT64_C(2449477632), // L4_loadd_locked
1637
0
    UINT64_C(2600472576), // L4_loadrb_ap
1638
0
    UINT64_C(973078528),  // L4_loadrb_rr
1639
0
    UINT64_C(2634027008), // L4_loadrb_ur
1640
0
    UINT64_C(2613055488), // L4_loadrd_ap
1641
0
    UINT64_C(985661440),  // L4_loadrd_rr
1642
0
    UINT64_C(2646609920), // L4_loadrd_ur
1643
0
    UINT64_C(2604666880), // L4_loadrh_ap
1644
0
    UINT64_C(977272832),  // L4_loadrh_rr
1645
0
    UINT64_C(2638221312), // L4_loadrh_ur
1646
0
    UINT64_C(2608861184), // L4_loadri_ap
1647
0
    UINT64_C(981467136),  // L4_loadri_rr
1648
0
    UINT64_C(2642415616), // L4_loadri_ur
1649
0
    UINT64_C(2602569728), // L4_loadrub_ap
1650
0
    UINT64_C(975175680),  // L4_loadrub_rr
1651
0
    UINT64_C(2636124160), // L4_loadrub_ur
1652
0
    UINT64_C(2606764032), // L4_loadruh_ap
1653
0
    UINT64_C(979369984),  // L4_loadruh_rr
1654
0
    UINT64_C(2640318464), // L4_loadruh_ur
1655
0
    UINT64_C(2449481728), // L4_loadw_phys
1656
0
    UINT64_C(1040187488), // L4_or_memopb_io
1657
0
    UINT64_C(1042284640), // L4_or_memoph_io
1658
0
    UINT64_C(1044381792), // L4_or_memopw_io
1659
0
    UINT64_C(2667587712), // L4_ploadrbf_abs
1660
0
    UINT64_C(822083584),  // L4_ploadrbf_rr
1661
0
    UINT64_C(2667591808), // L4_ploadrbfnew_abs
1662
0
    UINT64_C(855638016),  // L4_ploadrbfnew_rr
1663
0
    UINT64_C(2667585664), // L4_ploadrbt_abs
1664
0
    UINT64_C(805306368),  // L4_ploadrbt_rr
1665
0
    UINT64_C(2667589760), // L4_ploadrbtnew_abs
1666
0
    UINT64_C(838860800),  // L4_ploadrbtnew_rr
1667
0
    UINT64_C(2680170624), // L4_ploadrdf_abs
1668
0
    UINT64_C(834666496),  // L4_ploadrdf_rr
1669
0
    UINT64_C(2680174720), // L4_ploadrdfnew_abs
1670
0
    UINT64_C(868220928),  // L4_ploadrdfnew_rr
1671
0
    UINT64_C(2680168576), // L4_ploadrdt_abs
1672
0
    UINT64_C(817889280),  // L4_ploadrdt_rr
1673
0
    UINT64_C(2680172672), // L4_ploadrdtnew_abs
1674
0
    UINT64_C(851443712),  // L4_ploadrdtnew_rr
1675
0
    UINT64_C(2671782016), // L4_ploadrhf_abs
1676
0
    UINT64_C(826277888),  // L4_ploadrhf_rr
1677
0
    UINT64_C(2671786112), // L4_ploadrhfnew_abs
1678
0
    UINT64_C(859832320),  // L4_ploadrhfnew_rr
1679
0
    UINT64_C(2671779968), // L4_ploadrht_abs
1680
0
    UINT64_C(809500672),  // L4_ploadrht_rr
1681
0
    UINT64_C(2671784064), // L4_ploadrhtnew_abs
1682
0
    UINT64_C(843055104),  // L4_ploadrhtnew_rr
1683
0
    UINT64_C(2675976320), // L4_ploadrif_abs
1684
0
    UINT64_C(830472192),  // L4_ploadrif_rr
1685
0
    UINT64_C(2675980416), // L4_ploadrifnew_abs
1686
0
    UINT64_C(864026624),  // L4_ploadrifnew_rr
1687
0
    UINT64_C(2675974272), // L4_ploadrit_abs
1688
0
    UINT64_C(813694976),  // L4_ploadrit_rr
1689
0
    UINT64_C(2675978368), // L4_ploadritnew_abs
1690
0
    UINT64_C(847249408),  // L4_ploadritnew_rr
1691
0
    UINT64_C(2669684864), // L4_ploadrubf_abs
1692
0
    UINT64_C(824180736),  // L4_ploadrubf_rr
1693
0
    UINT64_C(2669688960), // L4_ploadrubfnew_abs
1694
0
    UINT64_C(857735168),  // L4_ploadrubfnew_rr
1695
0
    UINT64_C(2669682816), // L4_ploadrubt_abs
1696
0
    UINT64_C(807403520),  // L4_ploadrubt_rr
1697
0
    UINT64_C(2669686912), // L4_ploadrubtnew_abs
1698
0
    UINT64_C(840957952),  // L4_ploadrubtnew_rr
1699
0
    UINT64_C(2673879168), // L4_ploadruhf_abs
1700
0
    UINT64_C(828375040),  // L4_ploadruhf_rr
1701
0
    UINT64_C(2673883264), // L4_ploadruhfnew_abs
1702
0
    UINT64_C(861929472),  // L4_ploadruhfnew_rr
1703
0
    UINT64_C(2673877120), // L4_ploadruht_abs
1704
0
    UINT64_C(811597824),  // L4_ploadruht_rr
1705
0
    UINT64_C(2673881216), // L4_ploadruhtnew_abs
1706
0
    UINT64_C(845152256),  // L4_ploadruhtnew_rr
1707
0
    UINT64_C(2516582400), // L4_return
1708
0
    UINT64_C(2516594688), // L4_return_f
1709
0
    UINT64_C(2516592640), // L4_return_fnew_pnt
1710
0
    UINT64_C(2516596736), // L4_return_fnew_pt
1711
0
    UINT64_C(2516586496), // L4_return_t
1712
0
    UINT64_C(2516584448), // L4_return_tnew_pnt
1713
0
    UINT64_C(2516588544), // L4_return_tnew_pt
1714
0
    UINT64_C(1040187424), // L4_sub_memopb_io
1715
0
    UINT64_C(1042284576), // L4_sub_memoph_io
1716
0
    UINT64_C(1044381728), // L4_sub_memopw_io
1717
0
    UINT64_C(2449473600), // L6_memcpy
1718
0
    UINT64_C(18874368), // LO
1719
0
    UINT64_C(4009754656), // M2_acci
1720
0
    UINT64_C(3791650816), // M2_accii
1721
0
    UINT64_C(3875536928), // M2_cmaci_s0
1722
0
    UINT64_C(3875536960), // M2_cmacr_s0
1723
0
    UINT64_C(3875537088), // M2_cmacs_s0
1724
0
    UINT64_C(3883925696), // M2_cmacs_s1
1725
0
    UINT64_C(3879731392), // M2_cmacsc_s0
1726
0
    UINT64_C(3888120000), // M2_cmacsc_s1
1727
0
    UINT64_C(3841982496), // M2_cmpyi_s0
1728
0
    UINT64_C(3841982528), // M2_cmpyr_s0
1729
0
    UINT64_C(3978297536), // M2_cmpyrs_s0
1730
0
    UINT64_C(3986686144), // M2_cmpyrs_s1
1731
0
    UINT64_C(3982491840), // M2_cmpyrsc_s0
1732
0
    UINT64_C(3990880448), // M2_cmpyrsc_s1
1733
0
    UINT64_C(3841982656), // M2_cmpys_s0
1734
0
    UINT64_C(3850371264), // M2_cmpys_s1
1735
0
    UINT64_C(3846176960), // M2_cmpysc_s0
1736
0
    UINT64_C(3854565568), // M2_cmpysc_s1
1737
0
    UINT64_C(3875537120), // M2_cnacs_s0
1738
0
    UINT64_C(3883925728), // M2_cnacs_s1
1739
0
    UINT64_C(3879731424), // M2_cnacsc_s0
1740
0
    UINT64_C(3888120032), // M2_cnacsc_s1
1741
0
    UINT64_C(3875536896), // M2_dpmpyss_acc_s0
1742
0
    UINT64_C(3877634048), // M2_dpmpyss_nac_s0
1743
0
    UINT64_C(3978297376), // M2_dpmpyss_rnd_s0
1744
0
    UINT64_C(3841982464), // M2_dpmpyss_s0
1745
0
    UINT64_C(3879731200), // M2_dpmpyuu_acc_s0
1746
0
    UINT64_C(3881828352), // M2_dpmpyuu_nac_s0
1747
0
    UINT64_C(3846176768), // M2_dpmpyuu_s0
1748
0
    UINT64_C(3986686080), // M2_hmmpyh_rs1
1749
0
    UINT64_C(3986685952), // M2_hmmpyh_s1
1750
0
    UINT64_C(3990880384), // M2_hmmpyl_rs1
1751
0
    UINT64_C(3986685984), // M2_hmmpyl_s1
1752
0
    UINT64_C(4009754624), // M2_maci
1753
0
    UINT64_C(3783262208), // M2_macsin
1754
0
    UINT64_C(3774873600), // M2_macsip
1755
0
    UINT64_C(3927965920), // M2_mmachs_rs0
1756
0
    UINT64_C(3936354528), // M2_mmachs_rs1
1757
0
    UINT64_C(3925868768), // M2_mmachs_s0
1758
0
    UINT64_C(3934257376), // M2_mmachs_s1
1759
0
    UINT64_C(3927965856), // M2_mmacls_rs0
1760
0
    UINT64_C(3936354464), // M2_mmacls_rs1
1761
0
    UINT64_C(3925868704), // M2_mmacls_s0
1762
0
    UINT64_C(3934257312), // M2_mmacls_s1
1763
0
    UINT64_C(3932160224), // M2_mmacuhs_rs0
1764
0
    UINT64_C(3940548832), // M2_mmacuhs_rs1
1765
0
    UINT64_C(3930063072), // M2_mmacuhs_s0
1766
0
    UINT64_C(3938451680), // M2_mmacuhs_s1
1767
0
    UINT64_C(3932160160), // M2_mmaculs_rs0
1768
0
    UINT64_C(3940548768), // M2_mmaculs_rs1
1769
0
    UINT64_C(3930063008), // M2_mmaculs_s0
1770
0
    UINT64_C(3938451616), // M2_mmaculs_s1
1771
0
    UINT64_C(3894411488), // M2_mmpyh_rs0
1772
0
    UINT64_C(3902800096), // M2_mmpyh_rs1
1773
0
    UINT64_C(3892314336), // M2_mmpyh_s0
1774
0
    UINT64_C(3900702944), // M2_mmpyh_s1
1775
0
    UINT64_C(3894411424), // M2_mmpyl_rs0
1776
0
    UINT64_C(3902800032), // M2_mmpyl_rs1
1777
0
    UINT64_C(3892314272), // M2_mmpyl_s0
1778
0
    UINT64_C(3900702880), // M2_mmpyl_s1
1779
0
    UINT64_C(3898605792), // M2_mmpyuh_rs0
1780
0
    UINT64_C(3906994400), // M2_mmpyuh_rs1
1781
0
    UINT64_C(3896508640), // M2_mmpyuh_s0
1782
0
    UINT64_C(3904897248), // M2_mmpyuh_s1
1783
0
    UINT64_C(3898605728), // M2_mmpyul_rs0
1784
0
    UINT64_C(3906994336), // M2_mmpyul_rs1
1785
0
    UINT64_C(3896508576), // M2_mmpyul_s0
1786
0
    UINT64_C(3904897184), // M2_mmpyul_s1
1787
0
    UINT64_C(4018143232), // M2_mnaci
1788
0
    UINT64_C(3992977504), // M2_mpy_acc_hh_s0
1789
0
    UINT64_C(4001366112), // M2_mpy_acc_hh_s1
1790
0
    UINT64_C(3992977472), // M2_mpy_acc_hl_s0
1791
0
    UINT64_C(4001366080), // M2_mpy_acc_hl_s1
1792
0
    UINT64_C(3992977440), // M2_mpy_acc_lh_s0
1793
0
    UINT64_C(4001366048), // M2_mpy_acc_lh_s1
1794
0
    UINT64_C(3992977408), // M2_mpy_acc_ll_s0
1795
0
    UINT64_C(4001366016), // M2_mpy_acc_ll_s1
1796
0
    UINT64_C(3992977632), // M2_mpy_acc_sat_hh_s0
1797
0
    UINT64_C(4001366240), // M2_mpy_acc_sat_hh_s1
1798
0
    UINT64_C(3992977600), // M2_mpy_acc_sat_hl_s0
1799
0
    UINT64_C(4001366208), // M2_mpy_acc_sat_hl_s1
1800
0
    UINT64_C(3992977568), // M2_mpy_acc_sat_lh_s0
1801
0
    UINT64_C(4001366176), // M2_mpy_acc_sat_lh_s1
1802
0
    UINT64_C(3992977536), // M2_mpy_acc_sat_ll_s0
1803
0
    UINT64_C(4001366144), // M2_mpy_acc_sat_ll_s1
1804
0
    UINT64_C(3959423072), // M2_mpy_hh_s0
1805
0
    UINT64_C(3967811680), // M2_mpy_hh_s1
1806
0
    UINT64_C(3959423040), // M2_mpy_hl_s0
1807
0
    UINT64_C(3967811648), // M2_mpy_hl_s1
1808
0
    UINT64_C(3959423008), // M2_mpy_lh_s0
1809
0
    UINT64_C(3967811616), // M2_mpy_lh_s1
1810
0
    UINT64_C(3959422976), // M2_mpy_ll_s0
1811
0
    UINT64_C(3967811584), // M2_mpy_ll_s1
1812
0
    UINT64_C(3995074656), // M2_mpy_nac_hh_s0
1813
0
    UINT64_C(4003463264), // M2_mpy_nac_hh_s1
1814
0
    UINT64_C(3995074624), // M2_mpy_nac_hl_s0
1815
0
    UINT64_C(4003463232), // M2_mpy_nac_hl_s1
1816
0
    UINT64_C(3995074592), // M2_mpy_nac_lh_s0
1817
0
    UINT64_C(4003463200), // M2_mpy_nac_lh_s1
1818
0
    UINT64_C(3995074560), // M2_mpy_nac_ll_s0
1819
0
    UINT64_C(4003463168), // M2_mpy_nac_ll_s1
1820
0
    UINT64_C(3995074784), // M2_mpy_nac_sat_hh_s0
1821
0
    UINT64_C(4003463392), // M2_mpy_nac_sat_hh_s1
1822
0
    UINT64_C(3995074752), // M2_mpy_nac_sat_hl_s0
1823
0
    UINT64_C(4003463360), // M2_mpy_nac_sat_hl_s1
1824
0
    UINT64_C(3995074720), // M2_mpy_nac_sat_lh_s0
1825
0
    UINT64_C(4003463328), // M2_mpy_nac_sat_lh_s1
1826
0
    UINT64_C(3995074688), // M2_mpy_nac_sat_ll_s0
1827
0
    UINT64_C(4003463296), // M2_mpy_nac_sat_ll_s1
1828
0
    UINT64_C(3961520224), // M2_mpy_rnd_hh_s0
1829
0
    UINT64_C(3969908832), // M2_mpy_rnd_hh_s1
1830
0
    UINT64_C(3961520192), // M2_mpy_rnd_hl_s0
1831
0
    UINT64_C(3969908800), // M2_mpy_rnd_hl_s1
1832
0
    UINT64_C(3961520160), // M2_mpy_rnd_lh_s0
1833
0
    UINT64_C(3969908768), // M2_mpy_rnd_lh_s1
1834
0
    UINT64_C(3961520128), // M2_mpy_rnd_ll_s0
1835
0
    UINT64_C(3969908736), // M2_mpy_rnd_ll_s1
1836
0
    UINT64_C(3959423200), // M2_mpy_sat_hh_s0
1837
0
    UINT64_C(3967811808), // M2_mpy_sat_hh_s1
1838
0
    UINT64_C(3959423168), // M2_mpy_sat_hl_s0
1839
0
    UINT64_C(3967811776), // M2_mpy_sat_hl_s1
1840
0
    UINT64_C(3959423136), // M2_mpy_sat_lh_s0
1841
0
    UINT64_C(3967811744), // M2_mpy_sat_lh_s1
1842
0
    UINT64_C(3959423104), // M2_mpy_sat_ll_s0
1843
0
    UINT64_C(3967811712), // M2_mpy_sat_ll_s1
1844
0
    UINT64_C(3961520352), // M2_mpy_sat_rnd_hh_s0
1845
0
    UINT64_C(3969908960), // M2_mpy_sat_rnd_hh_s1
1846
0
    UINT64_C(3961520320), // M2_mpy_sat_rnd_hl_s0
1847
0
    UINT64_C(3969908928), // M2_mpy_sat_rnd_hl_s1
1848
0
    UINT64_C(3961520288), // M2_mpy_sat_rnd_lh_s0
1849
0
    UINT64_C(3969908896), // M2_mpy_sat_rnd_lh_s1
1850
0
    UINT64_C(3961520256), // M2_mpy_sat_rnd_ll_s0
1851
0
    UINT64_C(3969908864), // M2_mpy_sat_rnd_ll_s1
1852
0
    UINT64_C(3976200224), // M2_mpy_up
1853
0
    UINT64_C(3986686016), // M2_mpy_up_s1
1854
0
    UINT64_C(3990880256), // M2_mpy_up_s1_sat
1855
0
    UINT64_C(3858759776), // M2_mpyd_acc_hh_s0
1856
0
    UINT64_C(3867148384), // M2_mpyd_acc_hh_s1
1857
0
    UINT64_C(3858759744), // M2_mpyd_acc_hl_s0
1858
0
    UINT64_C(3867148352), // M2_mpyd_acc_hl_s1
1859
0
    UINT64_C(3858759712), // M2_mpyd_acc_lh_s0
1860
0
    UINT64_C(3867148320), // M2_mpyd_acc_lh_s1
1861
0
    UINT64_C(3858759680), // M2_mpyd_acc_ll_s0
1862
0
    UINT64_C(3867148288), // M2_mpyd_acc_ll_s1
1863
0
    UINT64_C(3825205344), // M2_mpyd_hh_s0
1864
0
    UINT64_C(3833593952), // M2_mpyd_hh_s1
1865
0
    UINT64_C(3825205312), // M2_mpyd_hl_s0
1866
0
    UINT64_C(3833593920), // M2_mpyd_hl_s1
1867
0
    UINT64_C(3825205280), // M2_mpyd_lh_s0
1868
0
    UINT64_C(3833593888), // M2_mpyd_lh_s1
1869
0
    UINT64_C(3825205248), // M2_mpyd_ll_s0
1870
0
    UINT64_C(3833593856), // M2_mpyd_ll_s1
1871
0
    UINT64_C(3860856928), // M2_mpyd_nac_hh_s0
1872
0
    UINT64_C(3869245536), // M2_mpyd_nac_hh_s1
1873
0
    UINT64_C(3860856896), // M2_mpyd_nac_hl_s0
1874
0
    UINT64_C(3869245504), // M2_mpyd_nac_hl_s1
1875
0
    UINT64_C(3860856864), // M2_mpyd_nac_lh_s0
1876
0
    UINT64_C(3869245472), // M2_mpyd_nac_lh_s1
1877
0
    UINT64_C(3860856832), // M2_mpyd_nac_ll_s0
1878
0
    UINT64_C(3869245440), // M2_mpyd_nac_ll_s1
1879
0
    UINT64_C(3827302496), // M2_mpyd_rnd_hh_s0
1880
0
    UINT64_C(3835691104), // M2_mpyd_rnd_hh_s1
1881
0
    UINT64_C(3827302464), // M2_mpyd_rnd_hl_s0
1882
0
    UINT64_C(3835691072), // M2_mpyd_rnd_hl_s1
1883
0
    UINT64_C(3827302432), // M2_mpyd_rnd_lh_s0
1884
0
    UINT64_C(3835691040), // M2_mpyd_rnd_lh_s1
1885
0
    UINT64_C(3827302400), // M2_mpyd_rnd_ll_s0
1886
0
    UINT64_C(3835691008), // M2_mpyd_rnd_ll_s1
1887
0
    UINT64_C(3976200192), // M2_mpyi
1888
0
    UINT64_C(3766484992), // M2_mpysin
1889
0
    UINT64_C(3758096384), // M2_mpysip
1890
0
    UINT64_C(3982491680), // M2_mpysu_up
1891
0
    UINT64_C(3997171808), // M2_mpyu_acc_hh_s0
1892
0
    UINT64_C(4005560416), // M2_mpyu_acc_hh_s1
1893
0
    UINT64_C(3997171776), // M2_mpyu_acc_hl_s0
1894
0
    UINT64_C(4005560384), // M2_mpyu_acc_hl_s1
1895
0
    UINT64_C(3997171744), // M2_mpyu_acc_lh_s0
1896
0
    UINT64_C(4005560352), // M2_mpyu_acc_lh_s1
1897
0
    UINT64_C(3997171712), // M2_mpyu_acc_ll_s0
1898
0
    UINT64_C(4005560320), // M2_mpyu_acc_ll_s1
1899
0
    UINT64_C(3963617376), // M2_mpyu_hh_s0
1900
0
    UINT64_C(3972005984), // M2_mpyu_hh_s1
1901
0
    UINT64_C(3963617344), // M2_mpyu_hl_s0
1902
0
    UINT64_C(3972005952), // M2_mpyu_hl_s1
1903
0
    UINT64_C(3963617312), // M2_mpyu_lh_s0
1904
0
    UINT64_C(3972005920), // M2_mpyu_lh_s1
1905
0
    UINT64_C(3963617280), // M2_mpyu_ll_s0
1906
0
    UINT64_C(3972005888), // M2_mpyu_ll_s1
1907
0
    UINT64_C(3999268960), // M2_mpyu_nac_hh_s0
1908
0
    UINT64_C(4007657568), // M2_mpyu_nac_hh_s1
1909
0
    UINT64_C(3999268928), // M2_mpyu_nac_hl_s0
1910
0
    UINT64_C(4007657536), // M2_mpyu_nac_hl_s1
1911
0
    UINT64_C(3999268896), // M2_mpyu_nac_lh_s0
1912
0
    UINT64_C(4007657504), // M2_mpyu_nac_lh_s1
1913
0
    UINT64_C(3999268864), // M2_mpyu_nac_ll_s0
1914
0
    UINT64_C(4007657472), // M2_mpyu_nac_ll_s1
1915
0
    UINT64_C(3980394528), // M2_mpyu_up
1916
0
    UINT64_C(3862954080), // M2_mpyud_acc_hh_s0
1917
0
    UINT64_C(3871342688), // M2_mpyud_acc_hh_s1
1918
0
    UINT64_C(3862954048), // M2_mpyud_acc_hl_s0
1919
0
    UINT64_C(3871342656), // M2_mpyud_acc_hl_s1
1920
0
    UINT64_C(3862954016), // M2_mpyud_acc_lh_s0
1921
0
    UINT64_C(3871342624), // M2_mpyud_acc_lh_s1
1922
0
    UINT64_C(3862953984), // M2_mpyud_acc_ll_s0
1923
0
    UINT64_C(3871342592), // M2_mpyud_acc_ll_s1
1924
0
    UINT64_C(3829399648), // M2_mpyud_hh_s0
1925
0
    UINT64_C(3837788256), // M2_mpyud_hh_s1
1926
0
    UINT64_C(3829399616), // M2_mpyud_hl_s0
1927
0
    UINT64_C(3837788224), // M2_mpyud_hl_s1
1928
0
    UINT64_C(3829399584), // M2_mpyud_lh_s0
1929
0
    UINT64_C(3837788192), // M2_mpyud_lh_s1
1930
0
    UINT64_C(3829399552), // M2_mpyud_ll_s0
1931
0
    UINT64_C(3837788160), // M2_mpyud_ll_s1
1932
0
    UINT64_C(3865051232), // M2_mpyud_nac_hh_s0
1933
0
    UINT64_C(3873439840), // M2_mpyud_nac_hh_s1
1934
0
    UINT64_C(3865051200), // M2_mpyud_nac_hl_s0
1935
0
    UINT64_C(3873439808), // M2_mpyud_nac_hl_s1
1936
0
    UINT64_C(3865051168), // M2_mpyud_nac_lh_s0
1937
0
    UINT64_C(3873439776), // M2_mpyud_nac_lh_s1
1938
0
    UINT64_C(3865051136), // M2_mpyud_nac_ll_s0
1939
0
    UINT64_C(3873439744), // M2_mpyud_nac_ll_s1
1940
0
    UINT64_C(4018143264), // M2_nacci
1941
0
    UINT64_C(3800039424), // M2_naccii
1942
0
    UINT64_C(4009754720), // M2_subacc
1943
0
    UINT64_C(3898605568), // M2_vabsdiffh
1944
0
    UINT64_C(3894411264), // M2_vabsdiffw
1945
0
    UINT64_C(3930062976), // M2_vcmac_s0_sat_i
1946
0
    UINT64_C(3927965824), // M2_vcmac_s0_sat_r
1947
0
    UINT64_C(3896508608), // M2_vcmpy_s0_sat_i
1948
0
    UINT64_C(3894411456), // M2_vcmpy_s0_sat_r
1949
0
    UINT64_C(3904897216), // M2_vcmpy_s1_sat_i
1950
0
    UINT64_C(3902800064), // M2_vcmpy_s1_sat_r
1951
0
    UINT64_C(3925868672), // M2_vdmacs_s0
1952
0
    UINT64_C(3934257280), // M2_vdmacs_s1
1953
0
    UINT64_C(3909091328), // M2_vdmpyrs_s0
1954
0
    UINT64_C(3917479936), // M2_vdmpyrs_s1
1955
0
    UINT64_C(3892314240), // M2_vdmpys_s0
1956
0
    UINT64_C(3900702848), // M2_vdmpys_s1
1957
0
    UINT64_C(3877634080), // M2_vmac2
1958
0
    UINT64_C(3927965760), // M2_vmac2es
1959
0
    UINT64_C(3925868736), // M2_vmac2es_s0
1960
0
    UINT64_C(3934257344), // M2_vmac2es_s1
1961
0
    UINT64_C(3875537056), // M2_vmac2s_s0
1962
0
    UINT64_C(3883925664), // M2_vmac2s_s1
1963
0
    UINT64_C(3881828512), // M2_vmac2su_s0
1964
0
    UINT64_C(3890217120), // M2_vmac2su_s1
1965
0
    UINT64_C(3892314304), // M2_vmpy2es_s0
1966
0
    UINT64_C(3900702912), // M2_vmpy2es_s1
1967
0
    UINT64_C(3841982624), // M2_vmpy2s_s0
1968
0
    UINT64_C(3978297568), // M2_vmpy2s_s0pack
1969
0
    UINT64_C(3850371232), // M2_vmpy2s_s1
1970
0
    UINT64_C(3986686176), // M2_vmpy2s_s1pack
1971
0
    UINT64_C(3841982688), // M2_vmpy2su_s0
1972
0
    UINT64_C(3850371296), // M2_vmpy2su_s1
1973
0
    UINT64_C(3911188704), // M2_vraddh
1974
0
    UINT64_C(3909091360), // M2_vradduh
1975
0
    UINT64_C(3925868544), // M2_vrcmaci_s0
1976
0
    UINT64_C(3930062848), // M2_vrcmaci_s0c
1977
0
    UINT64_C(3925868576), // M2_vrcmacr_s0
1978
0
    UINT64_C(3932160032), // M2_vrcmacr_s0c
1979
0
    UINT64_C(3892314112), // M2_vrcmpyi_s0
1980
0
    UINT64_C(3896508416), // M2_vrcmpyi_s0c
1981
0
    UINT64_C(3892314144), // M2_vrcmpyr_s0
1982
0
    UINT64_C(3898605600), // M2_vrcmpyr_s0c
1983
0
    UINT64_C(3936354432), // M2_vrcmpys_acc_s1_h
1984
0
    UINT64_C(3940548736), // M2_vrcmpys_acc_s1_l
1985
0
    UINT64_C(3902800000), // M2_vrcmpys_s1_h
1986
0
    UINT64_C(3906994304), // M2_vrcmpys_s1_l
1987
0
    UINT64_C(3919577280), // M2_vrcmpys_s1rp_h
1988
0
    UINT64_C(3919577312), // M2_vrcmpys_s1rp_l
1989
0
    UINT64_C(3925868608), // M2_vrmac_s0
1990
0
    UINT64_C(3892314176), // M2_vrmpy_s0
1991
0
    UINT64_C(4018143328), // M2_xor_xacc
1992
0
    UINT64_C(4013948928), // M4_and_and
1993
0
    UINT64_C(4011851808), // M4_and_andn
1994
0
    UINT64_C(4013948960), // M4_and_or
1995
0
    UINT64_C(4013948992), // M4_and_xor
1996
0
    UINT64_C(3305111680), // M4_cmpyi_wh
1997
0
    UINT64_C(3305111712), // M4_cmpyi_whc
1998
0
    UINT64_C(3305111744), // M4_cmpyr_wh
1999
0
    UINT64_C(3305111776), // M4_cmpyr_whc
2000
0
    UINT64_C(4016046080), // M4_mac_up_s1_sat
2001
0
    UINT64_C(3623878656), // M4_mpyri_addi
2002
0
    UINT64_C(3749707776), // M4_mpyri_addr
2003
0
    UINT64_C(3741319168), // M4_mpyri_addr_u2
2004
0
    UINT64_C(3607101440), // M4_mpyrr_addi
2005
0
    UINT64_C(3808428032), // M4_mpyrr_addr
2006
0
    UINT64_C(4016046112), // M4_nac_up_s1_sat
2007
0
    UINT64_C(4013949024), // M4_or_and
2008
0
    UINT64_C(4011851776), // M4_or_andn
2009
0
    UINT64_C(4022337536), // M4_or_or
2010
0
    UINT64_C(4022337568), // M4_or_xor
2011
0
    UINT64_C(3846176992), // M4_pmpyw
2012
0
    UINT64_C(3877634272), // M4_pmpyw_acc
2013
0
    UINT64_C(3854565600), // M4_vpmpyh
2014
0
    UINT64_C(3886022880), // M4_vpmpyh_acc
2015
0
    UINT64_C(3927965888), // M4_vrmpyeh_acc_s0
2016
0
    UINT64_C(3936354496), // M4_vrmpyeh_acc_s1
2017
0
    UINT64_C(3896508544), // M4_vrmpyeh_s0
2018
0
    UINT64_C(3904897152), // M4_vrmpyeh_s1
2019
0
    UINT64_C(3932160192), // M4_vrmpyoh_acc_s0
2020
0
    UINT64_C(3940548800), // M4_vrmpyoh_acc_s1
2021
0
    UINT64_C(3894411328), // M4_vrmpyoh_s0
2022
0
    UINT64_C(3902799936), // M4_vrmpyoh_s1
2023
0
    UINT64_C(4022337600), // M4_xor_and
2024
0
    UINT64_C(4011851840), // M4_xor_andn
2025
0
    UINT64_C(4022337632), // M4_xor_or
2026
0
    UINT64_C(3397386240), // M4_xor_xacc
2027
0
    UINT64_C(3927965728), // M5_vdmacbsu
2028
0
    UINT64_C(3902799904), // M5_vdmpybsu
2029
0
    UINT64_C(3888119840), // M5_vmacbsu
2030
0
    UINT64_C(3883925536), // M5_vmacbuu
2031
0
    UINT64_C(3846176800), // M5_vmpybsu
2032
0
    UINT64_C(3850371104), // M5_vmpybuu
2033
0
    UINT64_C(3938451488), // M5_vrmacbsu
2034
0
    UINT64_C(3934257184), // M5_vrmacbuu
2035
0
    UINT64_C(3904897056), // M5_vrmpybsu
2036
0
    UINT64_C(3900702752), // M5_vrmpybuu
2037
0
    UINT64_C(3906994176), // M6_vabsdiffb
2038
0
    UINT64_C(3902799872), // M6_vabsdiffub
2039
0
    UINT64_C(3898605632), // M7_dcmpyiw
2040
0
    UINT64_C(3932160064), // M7_dcmpyiw_acc
2041
0
    UINT64_C(3906994240), // M7_dcmpyiwc
2042
0
    UINT64_C(3930063040), // M7_dcmpyiwc_acc
2043
0
    UINT64_C(3900702784), // M7_dcmpyrw
2044
0
    UINT64_C(3934257216), // M7_dcmpyrw_acc
2045
0
    UINT64_C(3904897088), // M7_dcmpyrwc
2046
0
    UINT64_C(3938451520), // M7_dcmpyrwc_acc
2047
0
    UINT64_C(3911188480), // M7_wcmpyiw
2048
0
    UINT64_C(3919577088), // M7_wcmpyiw_rnd
2049
0
    UINT64_C(3909091456), // M7_wcmpyiwc
2050
0
    UINT64_C(3917480064), // M7_wcmpyiwc_rnd
2051
0
    UINT64_C(3913285632), // M7_wcmpyrw
2052
0
    UINT64_C(3921674240), // M7_wcmpyrw_rnd
2053
0
    UINT64_C(3915382784), // M7_wcmpyrwc
2054
0
    UINT64_C(3923771392), // M7_wcmpyrwc_rnd
2055
0
    UINT64_C(1509949440), // PS_call_stk
2056
0
    UINT64_C(1352663040), // PS_callr_nr
2057
0
    UINT64_C(1384120320), // PS_jmpret
2058
0
    UINT64_C(1398800384), // PS_jmpretf
2059
0
    UINT64_C(1398802432), // PS_jmpretfnew
2060
0
    UINT64_C(1398806528), // PS_jmpretfnewpt
2061
0
    UINT64_C(1396703232), // PS_jmprett
2062
0
    UINT64_C(1396705280), // PS_jmprettnew
2063
0
    UINT64_C(1396709376), // PS_jmprettnewpt
2064
0
    UINT64_C(1224736768), // PS_loadrbabs
2065
0
    UINT64_C(1237319680), // PS_loadrdabs
2066
0
    UINT64_C(1228931072), // PS_loadrhabs
2067
0
    UINT64_C(1233125376), // PS_loadriabs
2068
0
    UINT64_C(1226833920), // PS_loadrubabs
2069
0
    UINT64_C(1231028224), // PS_loadruhabs
2070
0
    UINT64_C(1207959552), // PS_storerbabs
2071
0
    UINT64_C(1218445312), // PS_storerbnewabs
2072
0
    UINT64_C(1220542464), // PS_storerdabs
2073
0
    UINT64_C(1214251008), // PS_storerfabs
2074
0
    UINT64_C(1212153856), // PS_storerhabs
2075
0
    UINT64_C(1218447360), // PS_storerhnewabs
2076
0
    UINT64_C(1216348160), // PS_storeriabs
2077
0
    UINT64_C(1218449408), // PS_storerinewabs
2078
0
    UINT64_C(1417674752), // PS_trap1
2079
0
    UINT64_C(2699034636), // R6_release_at_vi
2080
0
    UINT64_C(2699034668), // R6_release_st_vi
2081
0
    UINT64_C(1509949440), // RESTORE_DEALLOC_BEFORE_TAILCALL_V4
2082
0
    UINT64_C(1509949440), // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT
2083
0
    UINT64_C(1509949440), // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC
2084
0
    UINT64_C(1509949440), // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC
2085
0
    UINT64_C(1476395008), // RESTORE_DEALLOC_RET_JMP_V4
2086
0
    UINT64_C(1476395008), // RESTORE_DEALLOC_RET_JMP_V4_EXT
2087
0
    UINT64_C(1476395008), // RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC
2088
0
    UINT64_C(1476395008), // RESTORE_DEALLOC_RET_JMP_V4_PIC
2089
0
    UINT64_C(3288334336), // S2_addasl_rrri
2090
0
    UINT64_C(2692743168), // S2_allocframe
2091
0
    UINT64_C(2147483712), // S2_asl_i_p
2092
0
    UINT64_C(2181038272), // S2_asl_i_p_acc
2093
0
    UINT64_C(2185232448), // S2_asl_i_p_and
2094
0
    UINT64_C(2181038144), // S2_asl_i_p_nac
2095
0
    UINT64_C(2185232576), // S2_asl_i_p_or
2096
0
    UINT64_C(2189426752), // S2_asl_i_p_xacc
2097
0
    UINT64_C(2348810304), // S2_asl_i_r
2098
0
    UINT64_C(2382364864), // S2_asl_i_r_acc
2099
0
    UINT64_C(2386559040), // S2_asl_i_r_and
2100
0
    UINT64_C(2382364736), // S2_asl_i_r_nac
2101
0
    UINT64_C(2386559168), // S2_asl_i_r_or
2102
0
    UINT64_C(2353004608), // S2_asl_i_r_sat
2103
0
    UINT64_C(2390753344), // S2_asl_i_r_xacc
2104
0
    UINT64_C(2155872320), // S2_asl_i_vh
2105
0
    UINT64_C(2151678016), // S2_asl_i_vw
2106
0
    UINT64_C(3279945856), // S2_asl_r_p
2107
0
    UINT64_C(3418357888), // S2_asl_r_p_acc
2108
0
    UINT64_C(3409969280), // S2_asl_r_p_and
2109
0
    UINT64_C(3414163584), // S2_asl_r_p_nac
2110
0
    UINT64_C(3405774976), // S2_asl_r_p_or
2111
0
    UINT64_C(3412066432), // S2_asl_r_p_xor
2112
0
    UINT64_C(3326083200), // S2_asl_r_r
2113
0
    UINT64_C(3435135104), // S2_asl_r_r_acc
2114
0
    UINT64_C(3426746496), // S2_asl_r_r_and
2115
0
    UINT64_C(3430940800), // S2_asl_r_r_nac
2116
0
    UINT64_C(3422552192), // S2_asl_r_r_or
2117
0
    UINT64_C(3321888896), // S2_asl_r_r_sat
2118
0
    UINT64_C(3275751552), // S2_asl_r_vh
2119
0
    UINT64_C(3271557248), // S2_asl_r_vw
2120
0
    UINT64_C(2147483648), // S2_asr_i_p
2121
0
    UINT64_C(2181038208), // S2_asr_i_p_acc
2122
0
    UINT64_C(2185232384), // S2_asr_i_p_and
2123
0
    UINT64_C(2181038080), // S2_asr_i_p_nac
2124
0
    UINT64_C(2185232512), // S2_asr_i_p_or
2125
0
    UINT64_C(2160066784), // S2_asr_i_p_rnd
2126
0
    UINT64_C(2348810240), // S2_asr_i_r
2127
0
    UINT64_C(2382364800), // S2_asr_i_r_acc
2128
0
    UINT64_C(2386558976), // S2_asr_i_r_and
2129
0
    UINT64_C(2382364672), // S2_asr_i_r_nac
2130
0
    UINT64_C(2386559104), // S2_asr_i_r_or
2131
0
    UINT64_C(2353004544), // S2_asr_i_r_rnd
2132
0
    UINT64_C(2294284352), // S2_asr_i_svw_trun
2133
0
    UINT64_C(2155872256), // S2_asr_i_vh
2134
0
    UINT64_C(2151677952), // S2_asr_i_vw
2135
0
    UINT64_C(3279945728), // S2_asr_r_p
2136
0
    UINT64_C(3418357760), // S2_asr_r_p_acc
2137
0
    UINT64_C(3409969152), // S2_asr_r_p_and
2138
0
    UINT64_C(3414163456), // S2_asr_r_p_nac
2139
0
    UINT64_C(3405774848), // S2_asr_r_p_or
2140
0
    UINT64_C(3412066304), // S2_asr_r_p_xor
2141
0
    UINT64_C(3326083072), // S2_asr_r_r
2142
0
    UINT64_C(3435134976), // S2_asr_r_r_acc
2143
0
    UINT64_C(3426746368), // S2_asr_r_r_and
2144
0
    UINT64_C(3430940672), // S2_asr_r_r_nac
2145
0
    UINT64_C(3422552064), // S2_asr_r_r_or
2146
0
    UINT64_C(3321888768), // S2_asr_r_r_sat
2147
0
    UINT64_C(3305111616), // S2_asr_r_svw_trun
2148
0
    UINT64_C(3275751424), // S2_asr_r_vh
2149
0
    UINT64_C(3271557120), // S2_asr_r_vw
2150
0
    UINT64_C(2353004736), // S2_brev
2151
0
    UINT64_C(2160066752), // S2_brevp
2152
0
    UINT64_C(3250585792), // S2_cabacdecbin
2153
0
    UINT64_C(2348810400), // S2_cl0
2154
0
    UINT64_C(2285895744), // S2_cl0p
2155
0
    UINT64_C(2348810432), // S2_cl1
2156
0
    UINT64_C(2285895808), // S2_cl1p
2157
0
    UINT64_C(2348810368), // S2_clb
2158
0
    UINT64_C(2348810464), // S2_clbnorm
2159
0
    UINT64_C(2285895680), // S2_clbp
2160
0
    UINT64_C(2361393184), // S2_clrbit_i
2161
0
    UINT64_C(3330277440), // S2_clrbit_r
2162
0
    UINT64_C(2353004672), // S2_ct0
2163
0
    UINT64_C(2296381504), // S2_ct0p
2164
0
    UINT64_C(2353004704), // S2_ct1
2165
0
    UINT64_C(2296381568), // S2_ct1p
2166
0
    UINT64_C(2160066688), // S2_deinterleave
2167
0
    UINT64_C(2365587456), // S2_extractu
2168
0
    UINT64_C(3372220416), // S2_extractu_rp
2169
0
    UINT64_C(2164260864), // S2_extractup
2170
0
    UINT64_C(3238002688), // S2_extractup_rp
2171
0
    UINT64_C(2399141888), // S2_insert
2172
0
    UINT64_C(3355443200), // S2_insert_rp
2173
0
    UINT64_C(2197815296), // S2_insertp
2174
0
    UINT64_C(3388997632), // S2_insertp_rp
2175
0
    UINT64_C(2160066720), // S2_interleave
2176
0
    UINT64_C(3246391488), // S2_lfsp
2177
0
    UINT64_C(3279945920), // S2_lsl_r_p
2178
0
    UINT64_C(3418357952), // S2_lsl_r_p_acc
2179
0
    UINT64_C(3409969344), // S2_lsl_r_p_and
2180
0
    UINT64_C(3414163648), // S2_lsl_r_p_nac
2181
0
    UINT64_C(3405775040), // S2_lsl_r_p_or
2182
0
    UINT64_C(3412066496), // S2_lsl_r_p_xor
2183
0
    UINT64_C(3326083264), // S2_lsl_r_r
2184
0
    UINT64_C(3435135168), // S2_lsl_r_r_acc
2185
0
    UINT64_C(3426746560), // S2_lsl_r_r_and
2186
0
    UINT64_C(3430940864), // S2_lsl_r_r_nac
2187
0
    UINT64_C(3422552256), // S2_lsl_r_r_or
2188
0
    UINT64_C(3275751616), // S2_lsl_r_vh
2189
0
    UINT64_C(3271557312), // S2_lsl_r_vw
2190
0
    UINT64_C(2147483680), // S2_lsr_i_p
2191
0
    UINT64_C(2181038240), // S2_lsr_i_p_acc
2192
0
    UINT64_C(2185232416), // S2_lsr_i_p_and
2193
0
    UINT64_C(2181038112), // S2_lsr_i_p_nac
2194
0
    UINT64_C(2185232544), // S2_lsr_i_p_or
2195
0
    UINT64_C(2189426720), // S2_lsr_i_p_xacc
2196
0
    UINT64_C(2348810272), // S2_lsr_i_r
2197
0
    UINT64_C(2382364832), // S2_lsr_i_r_acc
2198
0
    UINT64_C(2386559008), // S2_lsr_i_r_and
2199
0
    UINT64_C(2382364704), // S2_lsr_i_r_nac
2200
0
    UINT64_C(2386559136), // S2_lsr_i_r_or
2201
0
    UINT64_C(2390753312), // S2_lsr_i_r_xacc
2202
0
    UINT64_C(2155872288), // S2_lsr_i_vh
2203
0
    UINT64_C(2151677984), // S2_lsr_i_vw
2204
0
    UINT64_C(3279945792), // S2_lsr_r_p
2205
0
    UINT64_C(3418357824), // S2_lsr_r_p_acc
2206
0
    UINT64_C(3409969216), // S2_lsr_r_p_and
2207
0
    UINT64_C(3414163520), // S2_lsr_r_p_nac
2208
0
    UINT64_C(3405774912), // S2_lsr_r_p_or
2209
0
    UINT64_C(3412066368), // S2_lsr_r_p_xor
2210
0
    UINT64_C(3326083136), // S2_lsr_r_r
2211
0
    UINT64_C(3435135040), // S2_lsr_r_r_acc
2212
0
    UINT64_C(3426746432), // S2_lsr_r_r_and
2213
0
    UINT64_C(3430940736), // S2_lsr_r_r_nac
2214
0
    UINT64_C(3422552128), // S2_lsr_r_r_or
2215
0
    UINT64_C(3275751488), // S2_lsr_r_vh
2216
0
    UINT64_C(3271557184), // S2_lsr_r_vw
2217
0
    UINT64_C(2365595648), // S2_mask
2218
0
    UINT64_C(4118806528), // S2_packhl
2219
0
    UINT64_C(3489660928), // S2_parityp
2220
0
    UINT64_C(1140850688), // S2_pstorerbf_io
2221
0
    UINT64_C(2868912132), // S2_pstorerbf_pi
2222
0
    UINT64_C(2868912260), // S2_pstorerbfnew_pi
2223
0
    UINT64_C(1151336448), // S2_pstorerbnewf_io
2224
0
    UINT64_C(2879397892), // S2_pstorerbnewf_pi
2225
0
    UINT64_C(2879398020), // S2_pstorerbnewfnew_pi
2226
0
    UINT64_C(1084227584), // S2_pstorerbnewt_io
2227
0
    UINT64_C(2879397888), // S2_pstorerbnewt_pi
2228
0
    UINT64_C(2879398016), // S2_pstorerbnewtnew_pi
2229
0
    UINT64_C(1073741824), // S2_pstorerbt_io
2230
0
    UINT64_C(2868912128), // S2_pstorerbt_pi
2231
0
    UINT64_C(2868912256), // S2_pstorerbtnew_pi
2232
0
    UINT64_C(1153433600), // S2_pstorerdf_io
2233
0
    UINT64_C(2881495044), // S2_pstorerdf_pi
2234
0
    UINT64_C(2881495172), // S2_pstorerdfnew_pi
2235
0
    UINT64_C(1086324736), // S2_pstorerdt_io
2236
0
    UINT64_C(2881495040), // S2_pstorerdt_pi
2237
0
    UINT64_C(2881495168), // S2_pstorerdtnew_pi
2238
0
    UINT64_C(1147142144), // S2_pstorerff_io
2239
0
    UINT64_C(2875203588), // S2_pstorerff_pi
2240
0
    UINT64_C(2875203716), // S2_pstorerffnew_pi
2241
0
    UINT64_C(1080033280), // S2_pstorerft_io
2242
0
    UINT64_C(2875203584), // S2_pstorerft_pi
2243
0
    UINT64_C(2875203712), // S2_pstorerftnew_pi
2244
0
    UINT64_C(1145044992), // S2_pstorerhf_io
2245
0
    UINT64_C(2873106436), // S2_pstorerhf_pi
2246
0
    UINT64_C(2873106564), // S2_pstorerhfnew_pi
2247
0
    UINT64_C(1151338496), // S2_pstorerhnewf_io
2248
0
    UINT64_C(2879399940), // S2_pstorerhnewf_pi
2249
0
    UINT64_C(2879400068), // S2_pstorerhnewfnew_pi
2250
0
    UINT64_C(1084229632), // S2_pstorerhnewt_io
2251
0
    UINT64_C(2879399936), // S2_pstorerhnewt_pi
2252
0
    UINT64_C(2879400064), // S2_pstorerhnewtnew_pi
2253
0
    UINT64_C(1077936128), // S2_pstorerht_io
2254
0
    UINT64_C(2873106432), // S2_pstorerht_pi
2255
0
    UINT64_C(2873106560), // S2_pstorerhtnew_pi
2256
0
    UINT64_C(1149239296), // S2_pstorerif_io
2257
0
    UINT64_C(2877300740), // S2_pstorerif_pi
2258
0
    UINT64_C(2877300868), // S2_pstorerifnew_pi
2259
0
    UINT64_C(1151340544), // S2_pstorerinewf_io
2260
0
    UINT64_C(2879401988), // S2_pstorerinewf_pi
2261
0
    UINT64_C(2879402116), // S2_pstorerinewfnew_pi
2262
0
    UINT64_C(1084231680), // S2_pstorerinewt_io
2263
0
    UINT64_C(2879401984), // S2_pstorerinewt_pi
2264
0
    UINT64_C(2879402112), // S2_pstorerinewtnew_pi
2265
0
    UINT64_C(1082130432), // S2_pstorerit_io
2266
0
    UINT64_C(2877300736), // S2_pstorerit_pi
2267
0
    UINT64_C(2877300864), // S2_pstoreritnew_pi
2268
0
    UINT64_C(2361393152), // S2_setbit_i
2269
0
    UINT64_C(3330277376), // S2_setbit_r
2270
0
    UINT64_C(3238002752), // S2_shuffeb
2271
0
    UINT64_C(3238002880), // S2_shuffeh
2272
0
    UINT64_C(3238002816), // S2_shuffob
2273
0
    UINT64_C(3246391296), // S2_shuffoh
2274
0
    UINT64_C(2701131776), // S2_storerb_io
2275
0
    UINT64_C(2936012800), // S2_storerb_pbr
2276
0
    UINT64_C(2835349504), // S2_storerb_pci
2277
0
    UINT64_C(2835349506), // S2_storerb_pcr
2278
0
    UINT64_C(2868903936), // S2_storerb_pi
2279
0
    UINT64_C(2902458368), // S2_storerb_pr
2280
0
    UINT64_C(1207959552), // S2_storerbgp
2281
0
    UINT64_C(2711617536), // S2_storerbnew_io
2282
0
    UINT64_C(2946498560), // S2_storerbnew_pbr
2283
0
    UINT64_C(2845835264), // S2_storerbnew_pci
2284
0
    UINT64_C(2845835266), // S2_storerbnew_pcr
2285
0
    UINT64_C(2879389696), // S2_storerbnew_pi
2286
0
    UINT64_C(2912944128), // S2_storerbnew_pr
2287
0
    UINT64_C(1218445312), // S2_storerbnewgp
2288
0
    UINT64_C(2713714688), // S2_storerd_io
2289
0
    UINT64_C(2948595712), // S2_storerd_pbr
2290
0
    UINT64_C(2847932416), // S2_storerd_pci
2291
0
    UINT64_C(2847932418), // S2_storerd_pcr
2292
0
    UINT64_C(2881486848), // S2_storerd_pi
2293
0
    UINT64_C(2915041280), // S2_storerd_pr
2294
0
    UINT64_C(1220542464), // S2_storerdgp
2295
0
    UINT64_C(2707423232), // S2_storerf_io
2296
0
    UINT64_C(2942304256), // S2_storerf_pbr
2297
0
    UINT64_C(2841640960), // S2_storerf_pci
2298
0
    UINT64_C(2841640962), // S2_storerf_pcr
2299
0
    UINT64_C(2875195392), // S2_storerf_pi
2300
0
    UINT64_C(2908749824), // S2_storerf_pr
2301
0
    UINT64_C(1214251008), // S2_storerfgp
2302
0
    UINT64_C(2705326080), // S2_storerh_io
2303
0
    UINT64_C(2940207104), // S2_storerh_pbr
2304
0
    UINT64_C(2839543808), // S2_storerh_pci
2305
0
    UINT64_C(2839543810), // S2_storerh_pcr
2306
0
    UINT64_C(2873098240), // S2_storerh_pi
2307
0
    UINT64_C(2906652672), // S2_storerh_pr
2308
0
    UINT64_C(1212153856), // S2_storerhgp
2309
0
    UINT64_C(2711619584), // S2_storerhnew_io
2310
0
    UINT64_C(2946500608), // S2_storerhnew_pbr
2311
0
    UINT64_C(2845837312), // S2_storerhnew_pci
2312
0
    UINT64_C(2845837314), // S2_storerhnew_pcr
2313
0
    UINT64_C(2879391744), // S2_storerhnew_pi
2314
0
    UINT64_C(2912946176), // S2_storerhnew_pr
2315
0
    UINT64_C(1218447360), // S2_storerhnewgp
2316
0
    UINT64_C(2709520384), // S2_storeri_io
2317
0
    UINT64_C(2944401408), // S2_storeri_pbr
2318
0
    UINT64_C(2843738112), // S2_storeri_pci
2319
0
    UINT64_C(2843738114), // S2_storeri_pcr
2320
0
    UINT64_C(2877292544), // S2_storeri_pi
2321
0
    UINT64_C(2910846976), // S2_storeri_pr
2322
0
    UINT64_C(1216348160), // S2_storerigp
2323
0
    UINT64_C(2711621632), // S2_storerinew_io
2324
0
    UINT64_C(2946502656), // S2_storerinew_pbr
2325
0
    UINT64_C(2845839360), // S2_storerinew_pci
2326
0
    UINT64_C(2845839362), // S2_storerinew_pcr
2327
0
    UINT64_C(2879393792), // S2_storerinew_pi
2328
0
    UINT64_C(2912948224), // S2_storerinew_pr
2329
0
    UINT64_C(1218449408), // S2_storerinewgp
2330
0
    UINT64_C(2694840320), // S2_storew_locked
2331
0
    UINT64_C(2694840328), // S2_storew_rl_at_vi
2332
0
    UINT64_C(2694840360), // S2_storew_rl_st_vi
2333
0
    UINT64_C(2357198848), // S2_svsathb
2334
0
    UINT64_C(2357198912), // S2_svsathub
2335
0
    UINT64_C(2264924160), // S2_tableidxb
2336
0
    UINT64_C(2277507072), // S2_tableidxd
2337
0
    UINT64_C(2269118464), // S2_tableidxh
2338
0
    UINT64_C(2273312768), // S2_tableidxw
2339
0
    UINT64_C(2361393216), // S2_togglebit_i
2340
0
    UINT64_C(3330277504), // S2_togglebit_r
2341
0
    UINT64_C(2231369728), // S2_tstbit_i
2342
0
    UINT64_C(3338665984), // S2_tstbit_r
2343
0
    UINT64_C(3221225472), // S2_valignib
2344
0
    UINT64_C(3254779904), // S2_valignrb
2345
0
    UINT64_C(3284140096), // S2_vcnegh
2346
0
    UINT64_C(3284140032), // S2_vcrotate
2347
0
    UINT64_C(3407880416), // S2_vrcnegh
2348
0
    UINT64_C(2290090112), // S2_vrndpackwh
2349
0
    UINT64_C(2290090176), // S2_vrndpackwhs
2350
0
    UINT64_C(2281701568), // S2_vsathb
2351
0
    UINT64_C(2147483872), // S2_vsathb_nopack
2352
0
    UINT64_C(2281701376), // S2_vsathub
2353
0
    UINT64_C(2147483776), // S2_vsathub_nopack
2354
0
    UINT64_C(2281701440), // S2_vsatwh
2355
0
    UINT64_C(2147483840), // S2_vsatwh_nopack
2356
0
    UINT64_C(2281701504), // S2_vsatwuh
2357
0
    UINT64_C(2147483808), // S2_vsatwuh_nopack
2358
0
    UINT64_C(2353004768), // S2_vsplatrb
2359
0
    UINT64_C(2218786880), // S2_vsplatrh
2360
0
    UINT64_C(3229614080), // S2_vspliceib
2361
0
    UINT64_C(3263168512), // S2_vsplicerb
2362
0
    UINT64_C(2214592512), // S2_vsxtbh
2363
0
    UINT64_C(2214592640), // S2_vsxthw
2364
0
    UINT64_C(2290090048), // S2_vtrunehb
2365
0
    UINT64_C(3246391360), // S2_vtrunewh
2366
0
    UINT64_C(2290089984), // S2_vtrunohb
2367
0
    UINT64_C(3246391424), // S2_vtrunowh
2368
0
    UINT64_C(2214592576), // S2_vzxtbh
2369
0
    UINT64_C(2214592704), // S2_vzxthw
2370
0
    UINT64_C(3674210304), // S4_addaddi
2371
0
    UINT64_C(3724541956), // S4_addi_asl_ri
2372
0
    UINT64_C(3724541972), // S4_addi_lsr_ri
2373
0
    UINT64_C(3724541952), // S4_andi_asl_ri
2374
0
    UINT64_C(3724541968), // S4_andi_lsr_ri
2375
0
    UINT64_C(2350907392), // S4_clbaddi
2376
0
    UINT64_C(2287992896), // S4_clbpaddi
2377
0
    UINT64_C(2287992832), // S4_clbpnorm
2378
0
    UINT64_C(2373976064), // S4_extract
2379
0
    UINT64_C(3372220480), // S4_extract_rp
2380
0
    UINT64_C(2315255808), // S4_extractp
2381
0
    UINT64_C(3250585728), // S4_extractp_rp
2382
0
    UINT64_C(3330277568), // S4_lsli
2383
0
    UINT64_C(2233466880), // S4_ntstbit_i
2384
0
    UINT64_C(3340763136), // S4_ntstbit_r
2385
0
    UINT64_C(3657433088), // S4_or_andi
2386
0
    UINT64_C(3661627392), // S4_or_andix
2387
0
    UINT64_C(3665821696), // S4_or_ori
2388
0
    UINT64_C(3724541954), // S4_ori_asl_ri
2389
0
    UINT64_C(3724541970), // S4_ori_lsr_ri
2390
0
    UINT64_C(3588227072), // S4_parity
2391
0
    UINT64_C(2936012932), // S4_pstorerbf_abs
2392
0
    UINT64_C(889192448),  // S4_pstorerbf_rr
2393
0
    UINT64_C(2936021124), // S4_pstorerbfnew_abs
2394
0
    UINT64_C(1174405120), // S4_pstorerbfnew_io
2395
0
    UINT64_C(922746880),  // S4_pstorerbfnew_rr
2396
0
    UINT64_C(2946498692), // S4_pstorerbnewf_abs
2397
0
    UINT64_C(899678208),  // S4_pstorerbnewf_rr
2398
0
    UINT64_C(2946506884), // S4_pstorerbnewfnew_abs
2399
0
    UINT64_C(1184890880), // S4_pstorerbnewfnew_io
2400
0
    UINT64_C(933232640),  // S4_pstorerbnewfnew_rr
2401
0
    UINT64_C(2946498688), // S4_pstorerbnewt_abs
2402
0
    UINT64_C(882900992),  // S4_pstorerbnewt_rr
2403
0
    UINT64_C(2946506880), // S4_pstorerbnewtnew_abs
2404
0
    UINT64_C(1117782016), // S4_pstorerbnewtnew_io
2405
0
    UINT64_C(916455424),  // S4_pstorerbnewtnew_rr
2406
0
    UINT64_C(2936012928), // S4_pstorerbt_abs
2407
0
    UINT64_C(872415232),  // S4_pstorerbt_rr
2408
0
    UINT64_C(2936021120), // S4_pstorerbtnew_abs
2409
0
    UINT64_C(1107296256), // S4_pstorerbtnew_io
2410
0
    UINT64_C(905969664),  // S4_pstorerbtnew_rr
2411
0
    UINT64_C(2948595844), // S4_pstorerdf_abs
2412
0
    UINT64_C(901775360),  // S4_pstorerdf_rr
2413
0
    UINT64_C(2948604036), // S4_pstorerdfnew_abs
2414
0
    UINT64_C(1186988032), // S4_pstorerdfnew_io
2415
0
    UINT64_C(935329792),  // S4_pstorerdfnew_rr
2416
0
    UINT64_C(2948595840), // S4_pstorerdt_abs
2417
0
    UINT64_C(884998144),  // S4_pstorerdt_rr
2418
0
    UINT64_C(2948604032), // S4_pstorerdtnew_abs
2419
0
    UINT64_C(1119879168), // S4_pstorerdtnew_io
2420
0
    UINT64_C(918552576),  // S4_pstorerdtnew_rr
2421
0
    UINT64_C(2942304388), // S4_pstorerff_abs
2422
0
    UINT64_C(895483904),  // S4_pstorerff_rr
2423
0
    UINT64_C(2942312580), // S4_pstorerffnew_abs
2424
0
    UINT64_C(1180696576), // S4_pstorerffnew_io
2425
0
    UINT64_C(929038336),  // S4_pstorerffnew_rr
2426
0
    UINT64_C(2942304384), // S4_pstorerft_abs
2427
0
    UINT64_C(878706688),  // S4_pstorerft_rr
2428
0
    UINT64_C(2942312576), // S4_pstorerftnew_abs
2429
0
    UINT64_C(1113587712), // S4_pstorerftnew_io
2430
0
    UINT64_C(912261120),  // S4_pstorerftnew_rr
2431
0
    UINT64_C(2940207236), // S4_pstorerhf_abs
2432
0
    UINT64_C(893386752),  // S4_pstorerhf_rr
2433
0
    UINT64_C(2940215428), // S4_pstorerhfnew_abs
2434
0
    UINT64_C(1178599424), // S4_pstorerhfnew_io
2435
0
    UINT64_C(926941184),  // S4_pstorerhfnew_rr
2436
0
    UINT64_C(2946500740), // S4_pstorerhnewf_abs
2437
0
    UINT64_C(899678216),  // S4_pstorerhnewf_rr
2438
0
    UINT64_C(2946508932), // S4_pstorerhnewfnew_abs
2439
0
    UINT64_C(1184892928), // S4_pstorerhnewfnew_io
2440
0
    UINT64_C(933232648),  // S4_pstorerhnewfnew_rr
2441
0
    UINT64_C(2946500736), // S4_pstorerhnewt_abs
2442
0
    UINT64_C(882901000),  // S4_pstorerhnewt_rr
2443
0
    UINT64_C(2946508928), // S4_pstorerhnewtnew_abs
2444
0
    UINT64_C(1117784064), // S4_pstorerhnewtnew_io
2445
0
    UINT64_C(916455432),  // S4_pstorerhnewtnew_rr
2446
0
    UINT64_C(2940207232), // S4_pstorerht_abs
2447
0
    UINT64_C(876609536),  // S4_pstorerht_rr
2448
0
    UINT64_C(2940215424), // S4_pstorerhtnew_abs
2449
0
    UINT64_C(1111490560), // S4_pstorerhtnew_io
2450
0
    UINT64_C(910163968),  // S4_pstorerhtnew_rr
2451
0
    UINT64_C(2944401540), // S4_pstorerif_abs
2452
0
    UINT64_C(897581056),  // S4_pstorerif_rr
2453
0
    UINT64_C(2944409732), // S4_pstorerifnew_abs
2454
0
    UINT64_C(1182793728), // S4_pstorerifnew_io
2455
0
    UINT64_C(931135488),  // S4_pstorerifnew_rr
2456
0
    UINT64_C(2946502788), // S4_pstorerinewf_abs
2457
0
    UINT64_C(899678224),  // S4_pstorerinewf_rr
2458
0
    UINT64_C(2946510980), // S4_pstorerinewfnew_abs
2459
0
    UINT64_C(1184894976), // S4_pstorerinewfnew_io
2460
0
    UINT64_C(933232656),  // S4_pstorerinewfnew_rr
2461
0
    UINT64_C(2946502784), // S4_pstorerinewt_abs
2462
0
    UINT64_C(882901008),  // S4_pstorerinewt_rr
2463
0
    UINT64_C(2946510976), // S4_pstorerinewtnew_abs
2464
0
    UINT64_C(1117786112), // S4_pstorerinewtnew_io
2465
0
    UINT64_C(916455440),  // S4_pstorerinewtnew_rr
2466
0
    UINT64_C(2944401536), // S4_pstorerit_abs
2467
0
    UINT64_C(880803840),  // S4_pstorerit_rr
2468
0
    UINT64_C(2944409728), // S4_pstoreritnew_abs
2469
0
    UINT64_C(1115684864), // S4_pstoreritnew_io
2470
0
    UINT64_C(914358272),  // S4_pstoreritnew_rr
2471
0
    UINT64_C(2699034624), // S4_stored_locked
2472
0
    UINT64_C(2699034632), // S4_stored_rl_at_vi
2473
0
    UINT64_C(2699034664), // S4_stored_rl_st_vi
2474
0
    UINT64_C(1006632960), // S4_storeirb_io
2475
0
    UINT64_C(947912704),  // S4_storeirbf_io
2476
0
    UINT64_C(964689920),  // S4_storeirbfnew_io
2477
0
    UINT64_C(939524096),  // S4_storeirbt_io
2478
0
    UINT64_C(956301312),  // S4_storeirbtnew_io
2479
0
    UINT64_C(1008730112), // S4_storeirh_io
2480
0
    UINT64_C(950009856),  // S4_storeirhf_io
2481
0
    UINT64_C(966787072),  // S4_storeirhfnew_io
2482
0
    UINT64_C(941621248),  // S4_storeirht_io
2483
0
    UINT64_C(958398464),  // S4_storeirhtnew_io
2484
0
    UINT64_C(1010827264), // S4_storeiri_io
2485
0
    UINT64_C(952107008),  // S4_storeirif_io
2486
0
    UINT64_C(968884224),  // S4_storeirifnew_io
2487
0
    UINT64_C(943718400),  // S4_storeirit_io
2488
0
    UINT64_C(960495616),  // S4_storeiritnew_io
2489
0
    UINT64_C(2868904064), // S4_storerb_ap
2490
0
    UINT64_C(989855744),  // S4_storerb_rr
2491
0
    UINT64_C(2902458496), // S4_storerb_ur
2492
0
    UINT64_C(2879389824), // S4_storerbnew_ap
2493
0
    UINT64_C(1000341504), // S4_storerbnew_rr
2494
0
    UINT64_C(2912944256), // S4_storerbnew_ur
2495
0
    UINT64_C(2881486976), // S4_storerd_ap
2496
0
    UINT64_C(1002438656), // S4_storerd_rr
2497
0
    UINT64_C(2915041408), // S4_storerd_ur
2498
0
    UINT64_C(2875195520), // S4_storerf_ap
2499
0
    UINT64_C(996147200),  // S4_storerf_rr
2500
0
    UINT64_C(2908749952), // S4_storerf_ur
2501
0
    UINT64_C(2873098368), // S4_storerh_ap
2502
0
    UINT64_C(994050048),  // S4_storerh_rr
2503
0
    UINT64_C(2906652800), // S4_storerh_ur
2504
0
    UINT64_C(2879391872), // S4_storerhnew_ap
2505
0
    UINT64_C(1000341512), // S4_storerhnew_rr
2506
0
    UINT64_C(2912946304), // S4_storerhnew_ur
2507
0
    UINT64_C(2877292672), // S4_storeri_ap
2508
0
    UINT64_C(998244352),  // S4_storeri_rr
2509
0
    UINT64_C(2910847104), // S4_storeri_ur
2510
0
    UINT64_C(2879393920), // S4_storerinew_ap
2511
0
    UINT64_C(1000341520), // S4_storerinew_rr
2512
0
    UINT64_C(2912948352), // S4_storerinew_ur
2513
0
    UINT64_C(3682598912), // S4_subaddi
2514
0
    UINT64_C(3724541958), // S4_subi_asl_ri
2515
0
    UINT64_C(3724541974), // S4_subi_lsr_ri
2516
0
    UINT64_C(3284140224), // S4_vrcrotate
2517
0
    UINT64_C(3416260608), // S4_vrcrotate_acc
2518
0
    UINT64_C(3242197120), // S4_vxaddsubh
2519
0
    UINT64_C(3250585600), // S4_vxaddsubhr
2520
0
    UINT64_C(3242196992), // S4_vxaddsubw
2521
0
    UINT64_C(3242197184), // S4_vxsubaddh
2522
0
    UINT64_C(3250585664), // S4_vxsubaddhr
2523
0
    UINT64_C(3242197056), // S4_vxsubaddw
2524
0
    UINT64_C(2287992960), // S5_asrhub_rnd_sat
2525
0
    UINT64_C(2287992992), // S5_asrhub_sat
2526
0
    UINT64_C(2287992928), // S5_popcountp
2527
0
    UINT64_C(2149580800), // S5_vasrhrnd
2528
0
    UINT64_C(2147483744), // S6_rol_i_p
2529
0
    UINT64_C(2181038304), // S6_rol_i_p_acc
2530
0
    UINT64_C(2185232480), // S6_rol_i_p_and
2531
0
    UINT64_C(2181038176), // S6_rol_i_p_nac
2532
0
    UINT64_C(2185232608), // S6_rol_i_p_or
2533
0
    UINT64_C(2189426784), // S6_rol_i_p_xacc
2534
0
    UINT64_C(2348810336), // S6_rol_i_r
2535
0
    UINT64_C(2382364896), // S6_rol_i_r_acc
2536
0
    UINT64_C(2386559072), // S6_rol_i_r_and
2537
0
    UINT64_C(2382364768), // S6_rol_i_r_nac
2538
0
    UINT64_C(2386559200), // S6_rol_i_r_or
2539
0
    UINT64_C(2390753376), // S6_rol_i_r_xacc
2540
0
    UINT64_C(2218786944), // S6_vsplatrbp
2541
0
    UINT64_C(3246391392), // S6_vtrunehb_ppp
2542
0
    UINT64_C(3246391456), // S6_vtrunohb_ppp
2543
0
    UINT64_C(0),  // SA1_addi
2544
0
    UINT64_C(6144), // SA1_addrx
2545
0
    UINT64_C(3072), // SA1_addsp
2546
0
    UINT64_C(4608), // SA1_and1
2547
0
    UINT64_C(6768), // SA1_clrf
2548
0
    UINT64_C(6736), // SA1_clrfnew
2549
0
    UINT64_C(6752), // SA1_clrt
2550
0
    UINT64_C(6720), // SA1_clrtnew
2551
0
    UINT64_C(6400), // SA1_cmpeqi
2552
0
    UINT64_C(7168), // SA1_combine0i
2553
0
    UINT64_C(7176), // SA1_combine1i
2554
0
    UINT64_C(7184), // SA1_combine2i
2555
0
    UINT64_C(7192), // SA1_combine3i
2556
0
    UINT64_C(7432), // SA1_combinerz
2557
0
    UINT64_C(7424), // SA1_combinezr
2558
0
    UINT64_C(4864), // SA1_dec
2559
0
    UINT64_C(4352), // SA1_inc
2560
0
    UINT64_C(2048), // SA1_seti
2561
0
    UINT64_C(6656), // SA1_setin1
2562
0
    UINT64_C(5376), // SA1_sxtb
2563
0
    UINT64_C(5120), // SA1_sxth
2564
0
    UINT64_C(4096), // SA1_tfr
2565
0
    UINT64_C(5888), // SA1_zxtb
2566
0
    UINT64_C(5632), // SA1_zxth
2567
0
    UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4
2568
0
    UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4STK
2569
0
    UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4STK_EXT
2570
0
    UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4STK_EXT_PIC
2571
0
    UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4STK_PIC
2572
0
    UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4_EXT
2573
0
    UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4_EXT_PIC
2574
0
    UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4_PIC
2575
0
    UINT64_C(0),  // SL1_loadri_io
2576
0
    UINT64_C(4096), // SL1_loadrub_io
2577
0
    UINT64_C(7936), // SL2_deallocframe
2578
0
    UINT64_C(8128), // SL2_jumpr31
2579
0
    UINT64_C(8133), // SL2_jumpr31_f
2580
0
    UINT64_C(8135), // SL2_jumpr31_fnew
2581
0
    UINT64_C(8132), // SL2_jumpr31_t
2582
0
    UINT64_C(8134), // SL2_jumpr31_tnew
2583
0
    UINT64_C(4096), // SL2_loadrb_io
2584
0
    UINT64_C(7680), // SL2_loadrd_sp
2585
0
    UINT64_C(0),  // SL2_loadrh_io
2586
0
    UINT64_C(7168), // SL2_loadri_sp
2587
0
    UINT64_C(2048), // SL2_loadruh_io
2588
0
    UINT64_C(8000), // SL2_return
2589
0
    UINT64_C(8005), // SL2_return_f
2590
0
    UINT64_C(8007), // SL2_return_fnew
2591
0
    UINT64_C(8004), // SL2_return_t
2592
0
    UINT64_C(8006), // SL2_return_tnew
2593
0
    UINT64_C(4096), // SS1_storeb_io
2594
0
    UINT64_C(0),  // SS1_storew_io
2595
0
    UINT64_C(7168), // SS2_allocframe
2596
0
    UINT64_C(4608), // SS2_storebi0
2597
0
    UINT64_C(4864), // SS2_storebi1
2598
0
    UINT64_C(2560), // SS2_stored_sp
2599
0
    UINT64_C(0),  // SS2_storeh_io
2600
0
    UINT64_C(2048), // SS2_storew_sp
2601
0
    UINT64_C(4096), // SS2_storewi0
2602
0
    UINT64_C(4352), // SS2_storewi1
2603
0
    UINT64_C(0),  // TFRI64_V2_ext
2604
0
    UINT64_C(0),  // TFRI64_V4
2605
0
    UINT64_C(2449473568), // V6_extractw
2606
0
    UINT64_C(432013376),  // V6_lvsplatb
2607
0
    UINT64_C(432013344),  // V6_lvsplath
2608
0
    UINT64_C(429916192),  // V6_lvsplatw
2609
0
    UINT64_C(503513088),  // V6_pred_and
2610
0
    UINT64_C(503513108),  // V6_pred_and_n
2611
0
    UINT64_C(503513096),  // V6_pred_not
2612
0
    UINT64_C(503513092),  // V6_pred_or
2613
0
    UINT64_C(503513104),  // V6_pred_or_n
2614
0
    UINT64_C(429916228),  // V6_pred_scalar2
2615
0
    UINT64_C(429916236),  // V6_pred_scalar2v2
2616
0
    UINT64_C(503513100),  // V6_pred_xor
2617
0
    UINT64_C(503513112),  // V6_shuffeqh
2618
0
    UINT64_C(503513116),  // V6_shuffeqw
2619
0
    UINT64_C(524296320),  // V6_v6mpyhubs10
2620
0
    UINT64_C(522199168),  // V6_v6mpyhubs10_vxx
2621
0
    UINT64_C(524296192),  // V6_v6mpyvubs10
2622
0
    UINT64_C(522199040),  // V6_v6mpyvubs10_vxx
2623
0
    UINT64_C(671088864),  // V6_vL32Ub_ai
2624
0
    UINT64_C(687866080),  // V6_vL32Ub_pi
2625
0
    UINT64_C(721420512),  // V6_vL32Ub_ppu
2626
0
    UINT64_C(671088640),  // V6_vL32b_ai
2627
0
    UINT64_C(671088672),  // V6_vL32b_cur_ai
2628
0
    UINT64_C(679477408),  // V6_vL32b_cur_npred_ai
2629
0
    UINT64_C(696254624),  // V6_vL32b_cur_npred_pi
2630
0
    UINT64_C(729809056),  // V6_vL32b_cur_npred_ppu
2631
0
    UINT64_C(687865888),  // V6_vL32b_cur_pi
2632
0
    UINT64_C(721420320),  // V6_vL32b_cur_ppu
2633
0
    UINT64_C(679477376),  // V6_vL32b_cur_pred_ai
2634
0
    UINT64_C(696254592),  // V6_vL32b_cur_pred_pi
2635
0
    UINT64_C(729809024),  // V6_vL32b_cur_pred_ppu
2636
0
    UINT64_C(679477344),  // V6_vL32b_npred_ai
2637
0
    UINT64_C(696254560),  // V6_vL32b_npred_pi
2638
0
    UINT64_C(729808992),  // V6_vL32b_npred_ppu
2639
0
    UINT64_C(675282944),  // V6_vL32b_nt_ai
2640
0
    UINT64_C(675282976),  // V6_vL32b_nt_cur_ai
2641
0
    UINT64_C(683671712),  // V6_vL32b_nt_cur_npred_ai
2642
0
    UINT64_C(700448928),  // V6_vL32b_nt_cur_npred_pi
2643
0
    UINT64_C(734003360),  // V6_vL32b_nt_cur_npred_ppu
2644
0
    UINT64_C(692060192),  // V6_vL32b_nt_cur_pi
2645
0
    UINT64_C(725614624),  // V6_vL32b_nt_cur_ppu
2646
0
    UINT64_C(683671680),  // V6_vL32b_nt_cur_pred_ai
2647
0
    UINT64_C(700448896),  // V6_vL32b_nt_cur_pred_pi
2648
0
    UINT64_C(734003328),  // V6_vL32b_nt_cur_pred_ppu
2649
0
    UINT64_C(683671648),  // V6_vL32b_nt_npred_ai
2650
0
    UINT64_C(700448864),  // V6_vL32b_nt_npred_pi
2651
0
    UINT64_C(734003296),  // V6_vL32b_nt_npred_ppu
2652
0
    UINT64_C(692060160),  // V6_vL32b_nt_pi
2653
0
    UINT64_C(725614592),  // V6_vL32b_nt_ppu
2654
0
    UINT64_C(683671616),  // V6_vL32b_nt_pred_ai
2655
0
    UINT64_C(700448832),  // V6_vL32b_nt_pred_pi
2656
0
    UINT64_C(734003264),  // V6_vL32b_nt_pred_ppu
2657
0
    UINT64_C(675283008),  // V6_vL32b_nt_tmp_ai
2658
0
    UINT64_C(683671776),  // V6_vL32b_nt_tmp_npred_ai
2659
0
    UINT64_C(700448992),  // V6_vL32b_nt_tmp_npred_pi
2660
0
    UINT64_C(734003424),  // V6_vL32b_nt_tmp_npred_ppu
2661
0
    UINT64_C(692060224),  // V6_vL32b_nt_tmp_pi
2662
0
    UINT64_C(725614656),  // V6_vL32b_nt_tmp_ppu
2663
0
    UINT64_C(683671744),  // V6_vL32b_nt_tmp_pred_ai
2664
0
    UINT64_C(700448960),  // V6_vL32b_nt_tmp_pred_pi
2665
0
    UINT64_C(734003392),  // V6_vL32b_nt_tmp_pred_ppu
2666
0
    UINT64_C(687865856),  // V6_vL32b_pi
2667
0
    UINT64_C(721420288),  // V6_vL32b_ppu
2668
0
    UINT64_C(679477312),  // V6_vL32b_pred_ai
2669
0
    UINT64_C(696254528),  // V6_vL32b_pred_pi
2670
0
    UINT64_C(729808960),  // V6_vL32b_pred_ppu
2671
0
    UINT64_C(671088704),  // V6_vL32b_tmp_ai
2672
0
    UINT64_C(679477472),  // V6_vL32b_tmp_npred_ai
2673
0
    UINT64_C(696254688),  // V6_vL32b_tmp_npred_pi
2674
0
    UINT64_C(729809120),  // V6_vL32b_tmp_npred_ppu
2675
0
    UINT64_C(687865920),  // V6_vL32b_tmp_pi
2676
0
    UINT64_C(721420352),  // V6_vL32b_tmp_ppu
2677
0
    UINT64_C(679477440),  // V6_vL32b_tmp_pred_ai
2678
0
    UINT64_C(696254656),  // V6_vL32b_tmp_pred_pi
2679
0
    UINT64_C(729809088),  // V6_vL32b_tmp_pred_ppu
2680
0
    UINT64_C(673186016),  // V6_vS32Ub_ai
2681
0
    UINT64_C(681574624),  // V6_vS32Ub_npred_ai
2682
0
    UINT64_C(698351840),  // V6_vS32Ub_npred_pi
2683
0
    UINT64_C(731906272),  // V6_vS32Ub_npred_ppu
2684
0
    UINT64_C(689963232),  // V6_vS32Ub_pi
2685
0
    UINT64_C(723517664),  // V6_vS32Ub_ppu
2686
0
    UINT64_C(681574592),  // V6_vS32Ub_pred_ai
2687
0
    UINT64_C(698351808),  // V6_vS32Ub_pred_pi
2688
0
    UINT64_C(731906240),  // V6_vS32Ub_pred_ppu
2689
0
    UINT64_C(673185792),  // V6_vS32b_ai
2690
0
    UINT64_C(673185824),  // V6_vS32b_new_ai
2691
0
    UINT64_C(681574504),  // V6_vS32b_new_npred_ai
2692
0
    UINT64_C(698351720),  // V6_vS32b_new_npred_pi
2693
0
    UINT64_C(731906152),  // V6_vS32b_new_npred_ppu
2694
0
    UINT64_C(689963040),  // V6_vS32b_new_pi
2695
0
    UINT64_C(723517472),  // V6_vS32b_new_ppu
2696
0
    UINT64_C(681574464),  // V6_vS32b_new_pred_ai
2697
0
    UINT64_C(698351680),  // V6_vS32b_new_pred_pi
2698
0
    UINT64_C(731906112),  // V6_vS32b_new_pred_ppu
2699
0
    UINT64_C(681574432),  // V6_vS32b_npred_ai
2700
0
    UINT64_C(698351648),  // V6_vS32b_npred_pi
2701
0
    UINT64_C(731906080),  // V6_vS32b_npred_ppu
2702
0
    UINT64_C(679477280),  // V6_vS32b_nqpred_ai
2703
0
    UINT64_C(696254496),  // V6_vS32b_nqpred_pi
2704
0
    UINT64_C(729808928),  // V6_vS32b_nqpred_ppu
2705
0
    UINT64_C(677380096),  // V6_vS32b_nt_ai
2706
0
    UINT64_C(677380128),  // V6_vS32b_nt_new_ai
2707
0
    UINT64_C(685768824),  // V6_vS32b_nt_new_npred_ai
2708
0
    UINT64_C(702546040),  // V6_vS32b_nt_new_npred_pi
2709
0
    UINT64_C(736100472),  // V6_vS32b_nt_new_npred_ppu
2710
0
    UINT64_C(694157344),  // V6_vS32b_nt_new_pi
2711
0
    UINT64_C(727711776),  // V6_vS32b_nt_new_ppu
2712
0
    UINT64_C(685768784),  // V6_vS32b_nt_new_pred_ai
2713
0
    UINT64_C(702546000),  // V6_vS32b_nt_new_pred_pi
2714
0
    UINT64_C(736100432),  // V6_vS32b_nt_new_pred_ppu
2715
0
    UINT64_C(685768736),  // V6_vS32b_nt_npred_ai
2716
0
    UINT64_C(702545952),  // V6_vS32b_nt_npred_pi
2717
0
    UINT64_C(736100384),  // V6_vS32b_nt_npred_ppu
2718
0
    UINT64_C(683671584),  // V6_vS32b_nt_nqpred_ai
2719
0
    UINT64_C(700448800),  // V6_vS32b_nt_nqpred_pi
2720
0
    UINT64_C(734003232),  // V6_vS32b_nt_nqpred_ppu
2721
0
    UINT64_C(694157312),  // V6_vS32b_nt_pi
2722
0
    UINT64_C(727711744),  // V6_vS32b_nt_ppu
2723
0
    UINT64_C(685768704),  // V6_vS32b_nt_pred_ai
2724
0
    UINT64_C(702545920),  // V6_vS32b_nt_pred_pi
2725
0
    UINT64_C(736100352),  // V6_vS32b_nt_pred_ppu
2726
0
    UINT64_C(683671552),  // V6_vS32b_nt_qpred_ai
2727
0
    UINT64_C(700448768),  // V6_vS32b_nt_qpred_pi
2728
0
    UINT64_C(734003200),  // V6_vS32b_nt_qpred_ppu
2729
0
    UINT64_C(689963008),  // V6_vS32b_pi
2730
0
    UINT64_C(723517440),  // V6_vS32b_ppu
2731
0
    UINT64_C(681574400),  // V6_vS32b_pred_ai
2732
0
    UINT64_C(698351616),  // V6_vS32b_pred_pi
2733
0
    UINT64_C(731906048),  // V6_vS32b_pred_ppu
2734
0
    UINT64_C(679477248),  // V6_vS32b_qpred_ai
2735
0
    UINT64_C(696254464),  // V6_vS32b_qpred_pi
2736
0
    UINT64_C(729808896),  // V6_vS32b_qpred_ppu
2737
0
    UINT64_C(673185832),  // V6_vS32b_srls_ai
2738
0
    UINT64_C(689963048),  // V6_vS32b_srls_pi
2739
0
    UINT64_C(723517480),  // V6_vS32b_srls_ppu
2740
0
    UINT64_C(503718016),  // V6_vabs_hf
2741
0
    UINT64_C(503718048),  // V6_vabs_sf
2742
0
    UINT64_C(503382144),  // V6_vabsb
2743
0
    UINT64_C(503382176),  // V6_vabsb_sat
2744
0
    UINT64_C(482344992),  // V6_vabsdiffh
2745
0
    UINT64_C(482344960),  // V6_vabsdiffub
2746
0
    UINT64_C(482345024),  // V6_vabsdiffuh
2747
0
    UINT64_C(482345056),  // V6_vabsdiffw
2748
0
    UINT64_C(503316480),  // V6_vabsh
2749
0
    UINT64_C(503316512),  // V6_vabsh_sat
2750
0
    UINT64_C(503316544),  // V6_vabsw
2751
0
    UINT64_C(503316576),  // V6_vabsw_sat
2752
0
    UINT64_C(526393440),  // V6_vadd_hf
2753
0
    UINT64_C(530587872),  // V6_vadd_hf_hf
2754
0
    UINT64_C(526393408),  // V6_vadd_qf16
2755
0
    UINT64_C(526393472),  // V6_vadd_qf16_mix
2756
0
    UINT64_C(530587648),  // V6_vadd_qf32
2757
0
    UINT64_C(530587712),  // V6_vadd_qf32_mix
2758
0
    UINT64_C(530587680),  // V6_vadd_sf
2759
0
    UINT64_C(490741952),  // V6_vadd_sf_bf
2760
0
    UINT64_C(528490624),  // V6_vadd_sf_hf
2761
0
    UINT64_C(528490688),  // V6_vadd_sf_sf
2762
0
    UINT64_C(530579648),  // V6_vaddb
2763
0
    UINT64_C(476053632),  // V6_vaddb_dv
2764
0
    UINT64_C(503390304),  // V6_vaddbnq
2765
0
    UINT64_C(503390208),  // V6_vaddbq
2766
0
    UINT64_C(520093696),  // V6_vaddbsat
2767
0
    UINT64_C(513802240),  // V6_vaddbsat_dv
2768
0
    UINT64_C(480256000),  // V6_vaddcarry
2769
0
    UINT64_C(497033216),  // V6_vaddcarryo
2770
0
    UINT64_C(494936064),  // V6_vaddcarrysat
2771
0
    UINT64_C(520101888),  // V6_vaddclbh
2772
0
    UINT64_C(520101920),  // V6_vaddclbw
2773
0
    UINT64_C(530579680),  // V6_vaddh
2774
0
    UINT64_C(476053664),  // V6_vaddh_dv
2775
0
    UINT64_C(503390336),  // V6_vaddhnq
2776
0
    UINT64_C(503390240),  // V6_vaddhq
2777
0
    UINT64_C(473956448),  // V6_vaddhsat
2778
0
    UINT64_C(478150688),  // V6_vaddhsat_dv
2779
0
    UINT64_C(480247936),  // V6_vaddhw
2780
0
    UINT64_C(471867456),  // V6_vaddhw_acc
2781
0
    UINT64_C(480247872),  // V6_vaddubh
2782
0
    UINT64_C(473964704),  // V6_vaddubh_acc
2783
0
    UINT64_C(473956384),  // V6_vaddubsat
2784
0
    UINT64_C(476053728),  // V6_vaddubsat_dv
2785
0
    UINT64_C(513802368),  // V6_vaddububb_sat
2786
0
    UINT64_C(473956416),  // V6_vadduhsat
2787
0
    UINT64_C(478150656),  // V6_vadduhsat_dv
2788
0
    UINT64_C(480247904),  // V6_vadduhw
2789
0
    UINT64_C(473964672),  // V6_vadduhw_acc
2790
0
    UINT64_C(526385184),  // V6_vadduwsat
2791
0
    UINT64_C(513802304),  // V6_vadduwsat_dv
2792
0
    UINT64_C(473956352),  // V6_vaddw
2793
0
    UINT64_C(476053696),  // V6_vaddw_dv
2794
0
    UINT64_C(503390368),  // V6_vaddwnq
2795
0
    UINT64_C(503390272),  // V6_vaddwq
2796
0
    UINT64_C(473956480),  // V6_vaddwsat
2797
0
    UINT64_C(478150720),  // V6_vaddwsat_dv
2798
0
    UINT64_C(452984832),  // V6_valignb
2799
0
    UINT64_C(505421824),  // V6_valignbi
2800
0
    UINT64_C(471859360),  // V6_vand
2801
0
    UINT64_C(429917344),  // V6_vandnqrt
2802
0
    UINT64_C(425731168),  // V6_vandnqrt_acc
2803
0
    UINT64_C(429916320),  // V6_vandqrt
2804
0
    UINT64_C(425730144),  // V6_vandqrt_acc
2805
0
    UINT64_C(503521312),  // V6_vandvnqv
2806
0
    UINT64_C(503521280),  // V6_vandvqv
2807
0
    UINT64_C(429916232),  // V6_vandvrt
2808
0
    UINT64_C(425730176),  // V6_vandvrt_acc
2809
0
    UINT64_C(427819008),  // V6_vaslh
2810
0
    UINT64_C(429924512),  // V6_vaslh_acc
2811
0
    UINT64_C(530579616),  // V6_vaslhv
2812
0
    UINT64_C(425722080),  // V6_vaslw
2813
0
    UINT64_C(425730112),  // V6_vaslw_acc
2814
0
    UINT64_C(530579584),  // V6_vaslwv
2815
0
    UINT64_C(446701792),  // V6_vasr_into
2816
0
    UINT64_C(425722048),  // V6_vasrh
2817
0
    UINT64_C(427827424),  // V6_vasrh_acc
2818
0
    UINT64_C(452993024),  // V6_vasrhbrndsat
2819
0
    UINT64_C(402653184),  // V6_vasrhbsat
2820
0
    UINT64_C(452985056),  // V6_vasrhubrndsat
2821
0
    UINT64_C(452985024),  // V6_vasrhubsat
2822
0
    UINT64_C(530579552),  // V6_vasrhv
2823
0
    UINT64_C(402653408),  // V6_vasruhubrndsat
2824
0
    UINT64_C(402661536),  // V6_vasruhubsat
2825
0
    UINT64_C(402653216),  // V6_vasruwuhrndsat
2826
0
    UINT64_C(402661504),  // V6_vasruwuhsat
2827
0
    UINT64_C(486539360),  // V6_vasrvuhubrndsat
2828
0
    UINT64_C(486539328),  // V6_vasrvuhubsat
2829
0
    UINT64_C(486539296),  // V6_vasrvwuhrndsat
2830
0
    UINT64_C(486539264),  // V6_vasrvwuhsat
2831
0
    UINT64_C(425722016),  // V6_vasrw
2832
0
    UINT64_C(425730208),  // V6_vasrw_acc
2833
0
    UINT64_C(452984896),  // V6_vasrwh
2834
0
    UINT64_C(452984960),  // V6_vasrwhrndsat
2835
0
    UINT64_C(452984928),  // V6_vasrwhsat
2836
0
    UINT64_C(402653248),  // V6_vasrwuhrndsat
2837
0
    UINT64_C(452984992),  // V6_vasrwuhsat
2838
0
    UINT64_C(530579456),  // V6_vasrwv
2839
0
    UINT64_C(503521504),  // V6_vassign
2840
0
    UINT64_C(503717920),  // V6_vassign_fp
2841
0
    UINT64_C(503382208),  // V6_vassign_tmp
2842
0
    UINT64_C(520102016),  // V6_vavgb
2843
0
    UINT64_C(520102048),  // V6_vavgbrnd
2844
0
    UINT64_C(482345152),  // V6_vavgh
2845
0
    UINT64_C(484442272),  // V6_vavghrnd
2846
0
    UINT64_C(482345088),  // V6_vavgub
2847
0
    UINT64_C(484442208),  // V6_vavgubrnd
2848
0
    UINT64_C(482345120),  // V6_vavguh
2849
0
    UINT64_C(484442240),  // V6_vavguhrnd
2850
0
    UINT64_C(520101952),  // V6_vavguw
2851
0
    UINT64_C(520101984),  // V6_vavguwrnd
2852
0
    UINT64_C(482345184),  // V6_vavgw
2853
0
    UINT64_C(484442304),  // V6_vavgwrnd
2854
0
    UINT64_C(442499072),  // V6_vccombine
2855
0
    UINT64_C(503447776),  // V6_vcl0h
2856
0
    UINT64_C(503447712),  // V6_vcl0w
2857
0
    UINT64_C(436207616),  // V6_vcmov
2858
0
    UINT64_C(524288224),  // V6_vcombine
2859
0
    UINT64_C(513802464),  // V6_vcombine_tmp
2860
0
    UINT64_C(503652416),  // V6_vconv_h_hf
2861
0
    UINT64_C(503652480),  // V6_vconv_hf_h
2862
0
    UINT64_C(503586912),  // V6_vconv_hf_qf16
2863
0
    UINT64_C(503587008),  // V6_vconv_hf_qf32
2864
0
    UINT64_C(503586816),  // V6_vconv_sf_qf32
2865
0
    UINT64_C(503652448),  // V6_vconv_sf_w
2866
0
    UINT64_C(503652384),  // V6_vconv_w_sf
2867
0
    UINT64_C(532684992),  // V6_vcvt_b_hf
2868
0
    UINT64_C(490741856),  // V6_vcvt_bf_sf
2869
0
    UINT64_C(503717888),  // V6_vcvt_h_hf
2870
0
    UINT64_C(503586880),  // V6_vcvt_hf_b
2871
0
    UINT64_C(503587040),  // V6_vcvt_hf_h
2872
0
    UINT64_C(526393376),  // V6_vcvt_hf_sf
2873
0
    UINT64_C(503586848),  // V6_vcvt_hf_ub
2874
0
    UINT64_C(503586976),  // V6_vcvt_hf_uh
2875
0
    UINT64_C(503586944),  // V6_vcvt_sf_hf
2876
0
    UINT64_C(532684960),  // V6_vcvt_ub_hf
2877
0
    UINT64_C(503652352),  // V6_vcvt_uh_hf
2878
0
    UINT64_C(434118720),  // V6_vdeal
2879
0
    UINT64_C(503316704),  // V6_vdealb
2880
0
    UINT64_C(522191072),  // V6_vdealb4w
2881
0
    UINT64_C(503316672),  // V6_vdealh
2882
0
    UINT64_C(452993152),  // V6_vdealvdd
2883
0
    UINT64_C(522190880),  // V6_vdelta
2884
0
    UINT64_C(530587840),  // V6_vdmpy_sf_hf
2885
0
    UINT64_C(473964640),  // V6_vdmpy_sf_hf_acc
2886
0
    UINT64_C(419430592),  // V6_vdmpybus
2887
0
    UINT64_C(419438784),  // V6_vdmpybus_acc
2888
0
    UINT64_C(419430624),  // V6_vdmpybus_dv
2889
0
    UINT64_C(419438816),  // V6_vdmpybus_dv_acc
2890
0
    UINT64_C(419430464),  // V6_vdmpyhb
2891
0
    UINT64_C(419438688),  // V6_vdmpyhb_acc
2892
0
    UINT64_C(421527680),  // V6_vdmpyhb_dv
2893
0
    UINT64_C(421535872),  // V6_vdmpyhb_dv_acc
2894
0
    UINT64_C(421527648),  // V6_vdmpyhisat
2895
0
    UINT64_C(421535808),  // V6_vdmpyhisat_acc
2896
0
    UINT64_C(421527616),  // V6_vdmpyhsat
2897
0
    UINT64_C(421535840),  // V6_vdmpyhsat_acc
2898
0
    UINT64_C(421527584),  // V6_vdmpyhsuisat
2899
0
    UINT64_C(421535776),  // V6_vdmpyhsuisat_acc
2900
0
    UINT64_C(421527552),  // V6_vdmpyhsusat
2901
0
    UINT64_C(421535744),  // V6_vdmpyhsusat_acc
2902
0
    UINT64_C(469762144),  // V6_vdmpyhvsat
2903
0
    UINT64_C(469770336),  // V6_vdmpyhvsat_acc
2904
0
    UINT64_C(419430560),  // V6_vdsaduh
2905
0
    UINT64_C(425730048),  // V6_vdsaduh_acc
2906
0
    UINT64_C(528482304),  // V6_veqb
2907
0
    UINT64_C(478158848),  // V6_veqb_and
2908
0
    UINT64_C(478158912),  // V6_veqb_or
2909
0
    UINT64_C(478158976),  // V6_veqb_xor
2910
0
    UINT64_C(528482308),  // V6_veqh
2911
0
    UINT64_C(478158852),  // V6_veqh_and
2912
0
    UINT64_C(478158916),  // V6_veqh_or
2913
0
    UINT64_C(478158980),  // V6_veqh_xor
2914
0
    UINT64_C(528482312),  // V6_veqw
2915
0
    UINT64_C(478158856),  // V6_veqw_and
2916
0
    UINT64_C(478158920),  // V6_veqw_or
2917
0
    UINT64_C(478158984),  // V6_veqw_xor
2918
0
    UINT64_C(476061760),  // V6_vfmax_hf
2919
0
    UINT64_C(476061792),  // V6_vfmax_sf
2920
0
    UINT64_C(476061696),  // V6_vfmin_hf
2921
0
    UINT64_C(476061728),  // V6_vfmin_sf
2922
0
    UINT64_C(503717952),  // V6_vfneg_hf
2923
0
    UINT64_C(503717984),  // V6_vfneg_sf
2924
0
    UINT64_C(788529408),  // V6_vgathermh
2925
0
    UINT64_C(788530432),  // V6_vgathermhq
2926
0
    UINT64_C(788529664),  // V6_vgathermhw
2927
0
    UINT64_C(788530688),  // V6_vgathermhwq
2928
0
    UINT64_C(788529152),  // V6_vgathermw
2929
0
    UINT64_C(788530176),  // V6_vgathermwq
2930
0
    UINT64_C(528482320),  // V6_vgtb
2931
0
    UINT64_C(478158864),  // V6_vgtb_and
2932
0
    UINT64_C(478158928),  // V6_vgtb_or
2933
0
    UINT64_C(478158992),  // V6_vgtb_xor
2934
0
    UINT64_C(478158968),  // V6_vgtbf
2935
0
    UINT64_C(478159056),  // V6_vgtbf_and
2936
0
    UINT64_C(478158904),  // V6_vgtbf_or
2937
0
    UINT64_C(478159088),  // V6_vgtbf_xor
2938
0
    UINT64_C(528482324),  // V6_vgth
2939
0
    UINT64_C(478158868),  // V6_vgth_and
2940
0
    UINT64_C(478158932),  // V6_vgth_or
2941
0
    UINT64_C(478158996),  // V6_vgth_xor
2942
0
    UINT64_C(478158964),  // V6_vgthf
2943
0
    UINT64_C(478159052),  // V6_vgthf_and
2944
0
    UINT64_C(478158900),  // V6_vgthf_or
2945
0
    UINT64_C(478159084),  // V6_vgthf_xor
2946
0
    UINT64_C(478158960),  // V6_vgtsf
2947
0
    UINT64_C(478159048),  // V6_vgtsf_and
2948
0
    UINT64_C(478158896),  // V6_vgtsf_or
2949
0
    UINT64_C(478159080),  // V6_vgtsf_xor
2950
0
    UINT64_C(528482336),  // V6_vgtub
2951
0
    UINT64_C(478158880),  // V6_vgtub_and
2952
0
    UINT64_C(478158944),  // V6_vgtub_or
2953
0
    UINT64_C(478159008),  // V6_vgtub_xor
2954
0
    UINT64_C(528482340),  // V6_vgtuh
2955
0
    UINT64_C(478158884),  // V6_vgtuh_and
2956
0
    UINT64_C(478158948),  // V6_vgtuh_or
2957
0
    UINT64_C(478159012),  // V6_vgtuh_xor
2958
0
    UINT64_C(528482344),  // V6_vgtuw
2959
0
    UINT64_C(478158888),  // V6_vgtuw_and
2960
0
    UINT64_C(478158952),  // V6_vgtuw_or
2961
0
    UINT64_C(478159016),  // V6_vgtuw_xor
2962
0
    UINT64_C(528482328),  // V6_vgtw
2963
0
    UINT64_C(478158872),  // V6_vgtw_and
2964
0
    UINT64_C(478158936),  // V6_vgtw_or
2965
0
    UINT64_C(478159000),  // V6_vgtw_xor
2966
0
    UINT64_C(503324800),  // V6_vhist
2967
0
    UINT64_C(503455872),  // V6_vhistq
2968
0
    UINT64_C(429924384),  // V6_vinsertwr
2969
0
    UINT64_C(452984864),  // V6_vlalignb
2970
0
    UINT64_C(509616128),  // V6_vlalignbi
2971
0
    UINT64_C(427819104),  // V6_vlsrb
2972
0
    UINT64_C(427819072),  // V6_vlsrh
2973
0
    UINT64_C(530579520),  // V6_vlsrhv
2974
0
    UINT64_C(427819040),  // V6_vlsrw
2975
0
    UINT64_C(530579488),  // V6_vlsrwv
2976
0
    UINT64_C(425721984),  // V6_vlut4
2977
0
    UINT64_C(452993056),  // V6_vlutvvb
2978
0
    UINT64_C(402653280),  // V6_vlutvvb_nm
2979
0
    UINT64_C(452993184),  // V6_vlutvvb_oracc
2980
0
    UINT64_C(482353152),  // V6_vlutvvb_oracci
2981
0
    UINT64_C(505413632),  // V6_vlutvvbi
2982
0
    UINT64_C(452993216),  // V6_vlutvwh
2983
0
    UINT64_C(402653312),  // V6_vlutvwh_nm
2984
0
    UINT64_C(452993248),  // V6_vlutvwh_oracc
2985
0
    UINT64_C(484450304),  // V6_vlutvwh_oracci
2986
0
    UINT64_C(509607936),  // V6_vlutvwhi
2987
0
    UINT64_C(490741984),  // V6_vmax_bf
2988
0
    UINT64_C(532684896),  // V6_vmax_hf
2989
0
    UINT64_C(532684832),  // V6_vmax_sf
2990
0
    UINT64_C(522191008),  // V6_vmaxb
2991
0
    UINT64_C(520093920),  // V6_vmaxh
2992
0
    UINT64_C(520093856),  // V6_vmaxub
2993
0
    UINT64_C(520093888),  // V6_vmaxuh
2994
0
    UINT64_C(522190848),  // V6_vmaxw
2995
0
    UINT64_C(490741760),  // V6_vmin_bf
2996
0
    UINT64_C(532684928),  // V6_vmin_hf
2997
0
    UINT64_C(532684864),  // V6_vmin_sf
2998
0
    UINT64_C(522190976),  // V6_vminb
2999
0
    UINT64_C(520093792),  // V6_vminh
3000
0
    UINT64_C(520093728),  // V6_vminub
3001
0
    UINT64_C(520093760),  // V6_vminuh
3002
0
    UINT64_C(520093824),  // V6_vminw
3003
0
    UINT64_C(421527744),  // V6_vmpabus
3004
0
    UINT64_C(421535936),  // V6_vmpabus_acc
3005
0
    UINT64_C(471859296),  // V6_vmpabusv
3006
0
    UINT64_C(425721952),  // V6_vmpabuu
3007
0
    UINT64_C(429924480),  // V6_vmpabuu_acc
3008
0
    UINT64_C(484442336),  // V6_vmpabuuv
3009
0
    UINT64_C(421527776),  // V6_vmpahb
3010
0
    UINT64_C(421535968),  // V6_vmpahb_acc
3011
0
    UINT64_C(427827328),  // V6_vmpahhsat
3012
0
    UINT64_C(427819168),  // V6_vmpauhb
3013
0
    UINT64_C(427827264),  // V6_vmpauhb_acc
3014
0
    UINT64_C(427827360),  // V6_vmpauhuhsat
3015
0
    UINT64_C(427827392),  // V6_vmpsuhuhsat
3016
0
    UINT64_C(528490592),  // V6_vmpy_hf_hf
3017
0
    UINT64_C(473964608),  // V6_vmpy_hf_hf_acc
3018
0
    UINT64_C(534782048),  // V6_vmpy_qf16
3019
0
    UINT64_C(534782080),  // V6_vmpy_qf16_hf
3020
0
    UINT64_C(534782112),  // V6_vmpy_qf16_mix_hf
3021
0
    UINT64_C(534781952),  // V6_vmpy_qf32
3022
0
    UINT64_C(534782176),  // V6_vmpy_qf32_hf
3023
0
    UINT64_C(528490496),  // V6_vmpy_qf32_mix_hf
3024
0
    UINT64_C(534782144),  // V6_vmpy_qf32_qf16
3025
0
    UINT64_C(534781984),  // V6_vmpy_qf32_sf
3026
0
    UINT64_C(490741888),  // V6_vmpy_sf_bf
3027
0
    UINT64_C(486547456),  // V6_vmpy_sf_bf_acc
3028
0
    UINT64_C(528490560),  // V6_vmpy_sf_hf
3029
0
    UINT64_C(473964576),  // V6_vmpy_sf_hf_acc
3030
0
    UINT64_C(528490528),  // V6_vmpy_sf_sf
3031
0
    UINT64_C(421527712),  // V6_vmpybus
3032
0
    UINT64_C(421535904),  // V6_vmpybus_acc
3033
0
    UINT64_C(469762240),  // V6_vmpybusv
3034
0
    UINT64_C(469770432),  // V6_vmpybusv_acc
3035
0
    UINT64_C(469762176),  // V6_vmpybv
3036
0
    UINT64_C(469770368),  // V6_vmpybv_acc
3037
0
    UINT64_C(534773920),  // V6_vmpyewuh
3038
0
    UINT64_C(513802432),  // V6_vmpyewuh_64
3039
0
    UINT64_C(423624704),  // V6_vmpyh
3040
0
    UINT64_C(429924544),  // V6_vmpyh_acc
3041
0
    UINT64_C(423632896),  // V6_vmpyhsat_acc
3042
0
    UINT64_C(423624768),  // V6_vmpyhsrs
3043
0
    UINT64_C(423624736),  // V6_vmpyhss
3044
0
    UINT64_C(471859264),  // V6_vmpyhus
3045
0
    UINT64_C(471867424),  // V6_vmpyhus_acc
3046
0
    UINT64_C(469762272),  // V6_vmpyhv
3047
0
    UINT64_C(469770464),  // V6_vmpyhv_acc
3048
0
    UINT64_C(471859232),  // V6_vmpyhvsrs
3049
0
    UINT64_C(526385152),  // V6_vmpyieoh
3050
0
    UINT64_C(473964544),  // V6_vmpyiewh_acc
3051
0
    UINT64_C(532676608),  // V6_vmpyiewuh
3052
0
    UINT64_C(471867552),  // V6_vmpyiewuh_acc
3053
0
    UINT64_C(471859328),  // V6_vmpyih
3054
0
    UINT64_C(471867520),  // V6_vmpyih_acc
3055
0
    UINT64_C(425721856),  // V6_vmpyihb
3056
0
    UINT64_C(425730080),  // V6_vmpyihb_acc
3057
0
    UINT64_C(532676640),  // V6_vmpyiowh
3058
0
    UINT64_C(429916160),  // V6_vmpyiwb
3059
0
    UINT64_C(423632960),  // V6_vmpyiwb_acc
3060
0
    UINT64_C(427819232),  // V6_vmpyiwh
3061
0
    UINT64_C(423632992),  // V6_vmpyiwh_acc
3062
0
    UINT64_C(427819200),  // V6_vmpyiwub
3063
0
    UINT64_C(427827232),  // V6_vmpyiwub_acc
3064
0
    UINT64_C(534773984),  // V6_vmpyowh
3065
0
    UINT64_C(471867488),  // V6_vmpyowh_64_acc
3066
0
    UINT64_C(524288000),  // V6_vmpyowh_rnd
3067
0
    UINT64_C(471867616),  // V6_vmpyowh_rnd_sacc
3068
0
    UINT64_C(471867584),  // V6_vmpyowh_sacc
3069
0
    UINT64_C(432013312),  // V6_vmpyub
3070
0
    UINT64_C(427827200),  // V6_vmpyub_acc
3071
0
    UINT64_C(469762208),  // V6_vmpyubv
3072
0
    UINT64_C(469770400),  // V6_vmpyubv_acc
3073
0
    UINT64_C(423624800),  // V6_vmpyuh
3074
0
    UINT64_C(423632928),  // V6_vmpyuh_acc
3075
0
    UINT64_C(425721920),  // V6_vmpyuhe
3076
0
    UINT64_C(427827296),  // V6_vmpyuhe_acc
3077
0
    UINT64_C(471859200),  // V6_vmpyuhv
3078
0
    UINT64_C(471867392),  // V6_vmpyuhv_acc
3079
0
    UINT64_C(532685024),  // V6_vmpyuhvs
3080
0
    UINT64_C(518004736),  // V6_vmux
3081
0
    UINT64_C(520102080),  // V6_vnavgb
3082
0
    UINT64_C(484442144),  // V6_vnavgh
3083
0
    UINT64_C(484442112),  // V6_vnavgub
3084
0
    UINT64_C(484442176),  // V6_vnavgw
3085
0
    UINT64_C(440401920),  // V6_vnccombine
3086
0
    UINT64_C(438304768),  // V6_vncmov
3087
0
    UINT64_C(503513248),  // V6_vnormamth
3088
0
    UINT64_C(503513216),  // V6_vnormamtw
3089
0
    UINT64_C(503316608),  // V6_vnot
3090
0
    UINT64_C(471859392),  // V6_vor
3091
0
    UINT64_C(532676672),  // V6_vpackeb
3092
0
    UINT64_C(532676704),  // V6_vpackeh
3093
0
    UINT64_C(532676800),  // V6_vpackhb_sat
3094
0
    UINT64_C(532676768),  // V6_vpackhub_sat
3095
0
    UINT64_C(534773792),  // V6_vpackob
3096
0
    UINT64_C(534773824),  // V6_vpackoh
3097
0
    UINT64_C(534773760),  // V6_vpackwh_sat
3098
0
    UINT64_C(532676832),  // V6_vpackwuh_sat
3099
0
    UINT64_C(503447744),  // V6_vpopcounth
3100
0
    UINT64_C(503521344),  // V6_vprefixqb
3101
0
    UINT64_C(503521600),  // V6_vprefixqh
3102
0
    UINT64_C(503521856),  // V6_vprefixqw
3103
0
    UINT64_C(522190944),  // V6_vrdelta
3104
0
    UINT64_C(432013472),  // V6_vrmpybub_rtt
3105
0
    UINT64_C(429924352),  // V6_vrmpybub_rtt_acc
3106
0
    UINT64_C(419430528),  // V6_vrmpybus
3107
0
    UINT64_C(419438752),  // V6_vrmpybus_acc
3108
0
    UINT64_C(423624832),  // V6_vrmpybusi
3109
0
    UINT64_C(423633024),  // V6_vrmpybusi_acc
3110
0
    UINT64_C(469762112),  // V6_vrmpybusv
3111
0
    UINT64_C(469770304),  // V6_vrmpybusv_acc
3112
0
    UINT64_C(469762080),  // V6_vrmpybv
3113
0
    UINT64_C(469770272),  // V6_vrmpybv_acc
3114
0
    UINT64_C(419430496),  // V6_vrmpyub
3115
0
    UINT64_C(419438720),  // V6_vrmpyub_acc
3116
0
    UINT64_C(432013440),  // V6_vrmpyub_rtt
3117
0
    UINT64_C(429924576),  // V6_vrmpyub_rtt_acc
3118
0
    UINT64_C(429916352),  // V6_vrmpyubi
3119
0
    UINT64_C(425730240),  // V6_vrmpyubi_acc
3120
0
    UINT64_C(469762048),  // V6_vrmpyubv
3121
0
    UINT64_C(469770240),  // V6_vrmpyubv_acc
3122
0
    UINT64_C(434634752),  // V6_vrmpyzbb_rt
3123
0
    UINT64_C(432021568),  // V6_vrmpyzbb_rt_acc
3124
0
    UINT64_C(434110464),  // V6_vrmpyzbb_rx
3125
0
    UINT64_C(432545856),  // V6_vrmpyzbb_rx_acc
3126
0
    UINT64_C(435683392),  // V6_vrmpyzbub_rt
3127
0
    UINT64_C(433070112),  // V6_vrmpyzbub_rt_acc
3128
0
    UINT64_C(435159104),  // V6_vrmpyzbub_rx
3129
0
    UINT64_C(433594400),  // V6_vrmpyzbub_rx_acc
3130
0
    UINT64_C(434634784),  // V6_vrmpyzcb_rt
3131
0
    UINT64_C(432021600),  // V6_vrmpyzcb_rt_acc
3132
0
    UINT64_C(434110496),  // V6_vrmpyzcb_rx
3133
0
    UINT64_C(432545888),  // V6_vrmpyzcb_rx_acc
3134
0
    UINT64_C(434634816),  // V6_vrmpyzcbs_rt
3135
0
    UINT64_C(432021536),  // V6_vrmpyzcbs_rt_acc
3136
0
    UINT64_C(434110528),  // V6_vrmpyzcbs_rx
3137
0
    UINT64_C(432545824),  // V6_vrmpyzcbs_rx_acc
3138
0
    UINT64_C(435683328),  // V6_vrmpyznb_rt
3139
0
    UINT64_C(433070144),  // V6_vrmpyznb_rt_acc
3140
0
    UINT64_C(435159040),  // V6_vrmpyznb_rx
3141
0
    UINT64_C(433594432),  // V6_vrmpyznb_rx_acc
3142
0
    UINT64_C(425721888),  // V6_vror
3143
0
    UINT64_C(444604640),  // V6_vrotr
3144
0
    UINT64_C(526385344),  // V6_vroundhb
3145
0
    UINT64_C(526385376),  // V6_vroundhub
3146
0
    UINT64_C(534773856),  // V6_vrounduhub
3147
0
    UINT64_C(534773888),  // V6_vrounduwuh
3148
0
    UINT64_C(526385280),  // V6_vroundwh
3149
0
    UINT64_C(526385312),  // V6_vroundwuh
3150
0
    UINT64_C(423624896),  // V6_vrsadubi
3151
0
    UINT64_C(423633088),  // V6_vrsadubi_acc
3152
0
    UINT64_C(494936288),  // V6_vsatdw
3153
0
    UINT64_C(526385216),  // V6_vsathub
3154
0
    UINT64_C(522191040),  // V6_vsatuwuh
3155
0
    UINT64_C(526385248),  // V6_vsatwh
3156
0
    UINT64_C(503447648),  // V6_vsb
3157
0
    UINT64_C(790626336),  // V6_vscattermh
3158
0
    UINT64_C(790626464),  // V6_vscattermh_add
3159
0
    UINT64_C(796917888),  // V6_vscattermhq
3160
0
    UINT64_C(790626368),  // V6_vscattermhw
3161
0
    UINT64_C(790626496),  // V6_vscattermhw_add
3162
0
    UINT64_C(799014912),  // V6_vscattermhwq
3163
0
    UINT64_C(790626304),  // V6_vscattermw
3164
0
    UINT64_C(790626432),  // V6_vscattermw_add
3165
0
    UINT64_C(796917760),  // V6_vscattermwq
3166
0
    UINT64_C(503447680),  // V6_vsh
3167
0
    UINT64_C(524288096),  // V6_vshufeh
3168
0
    UINT64_C(434118688),  // V6_vshuff
3169
0
    UINT64_C(503447552),  // V6_vshuffb
3170
0
    UINT64_C(524288032),  // V6_vshuffeb
3171
0
    UINT64_C(503382240),  // V6_vshuffh
3172
0
    UINT64_C(524288064),  // V6_vshuffob
3173
0
    UINT64_C(452993120),  // V6_vshuffvdd
3174
0
    UINT64_C(524288192),  // V6_vshufoeb
3175
0
    UINT64_C(524288160),  // V6_vshufoeh
3176
0
    UINT64_C(524288128),  // V6_vshufoh
3177
0
    UINT64_C(526393536),  // V6_vsub_hf
3178
0
    UINT64_C(526393344),  // V6_vsub_hf_hf
3179
0
    UINT64_C(526393504),  // V6_vsub_qf16
3180
0
    UINT64_C(526393568),  // V6_vsub_qf16_mix
3181
0
    UINT64_C(530587744),  // V6_vsub_qf32
3182
0
    UINT64_C(530587808),  // V6_vsub_qf32_mix
3183
0
    UINT64_C(530587776),  // V6_vsub_sf
3184
0
    UINT64_C(490741920),  // V6_vsub_sf_bf
3185
0
    UINT64_C(528490656),  // V6_vsub_sf_hf
3186
0
    UINT64_C(528490720),  // V6_vsub_sf_sf
3187
0
    UINT64_C(473956512),  // V6_vsubb
3188
0
    UINT64_C(478150752),  // V6_vsubb_dv
3189
0
    UINT64_C(503455776),  // V6_vsubbnq
3190
0
    UINT64_C(503390400),  // V6_vsubbq
3191
0
    UINT64_C(522190912),  // V6_vsubbsat
3192
0
    UINT64_C(513802272),  // V6_vsubbsat_dv
3193
0
    UINT64_C(480256128),  // V6_vsubcarry
3194
0
    UINT64_C(497033344),  // V6_vsubcarryo
3195
0
    UINT64_C(473956544),  // V6_vsubh
3196
0
    UINT64_C(478150784),  // V6_vsubh_dv
3197
0
    UINT64_C(503455808),  // V6_vsubhnq
3198
0
    UINT64_C(503390432),  // V6_vsubhq
3199
0
    UINT64_C(476053568),  // V6_vsubhsat
3200
0
    UINT64_C(480247808),  // V6_vsubhsat_dv
3201
0
    UINT64_C(480248032),  // V6_vsubhw
3202
0
    UINT64_C(480247968),  // V6_vsububh
3203
0
    UINT64_C(476053504),  // V6_vsububsat
3204
0
    UINT64_C(478150848),  // V6_vsububsat_dv
3205
0
    UINT64_C(513802400),  // V6_vsubububb_sat
3206
0
    UINT64_C(476053536),  // V6_vsubuhsat
3207
0
    UINT64_C(478150880),  // V6_vsubuhsat_dv
3208
0
    UINT64_C(480248000),  // V6_vsubuhw
3209
0
    UINT64_C(532676736),  // V6_vsubuwsat
3210
0
    UINT64_C(513802336),  // V6_vsubuwsat_dv
3211
0
    UINT64_C(473956576),  // V6_vsubw
3212
0
    UINT64_C(478150816),  // V6_vsubw_dv
3213
0
    UINT64_C(503455840),  // V6_vsubwnq
3214
0
    UINT64_C(503455744),  // V6_vsubwq
3215
0
    UINT64_C(476053600),  // V6_vsubwsat
3216
0
    UINT64_C(480247840),  // V6_vsubwsat_dv
3217
0
    UINT64_C(513810432),  // V6_vswap
3218
0
    UINT64_C(419430400),  // V6_vtmpyb
3219
0
    UINT64_C(419438592),  // V6_vtmpyb_acc
3220
0
    UINT64_C(419430432),  // V6_vtmpybus
3221
0
    UINT64_C(419438624),  // V6_vtmpybus_acc
3222
0
    UINT64_C(429916288),  // V6_vtmpyhb
3223
0
    UINT64_C(419438656),  // V6_vtmpyhb_acc
3224
0
    UINT64_C(503382080),  // V6_vunpackb
3225
0
    UINT64_C(503382112),  // V6_vunpackh
3226
0
    UINT64_C(503324672),  // V6_vunpackob
3227
0
    UINT64_C(503324704),  // V6_vunpackoh
3228
0
    UINT64_C(503382016),  // V6_vunpackub
3229
0
    UINT64_C(503382048),  // V6_vunpackuh
3230
0
    UINT64_C(503325824),  // V6_vwhist128
3231
0
    UINT64_C(503326336),  // V6_vwhist128m
3232
0
    UINT64_C(503456896),  // V6_vwhist128q
3233
0
    UINT64_C(503457408),  // V6_vwhist128qm
3234
0
    UINT64_C(503325312),  // V6_vwhist256
3235
0
    UINT64_C(503325568),  // V6_vwhist256_sat
3236
0
    UINT64_C(503456384),  // V6_vwhist256q
3237
0
    UINT64_C(503456640),  // V6_vwhist256q_sat
3238
0
    UINT64_C(471859424),  // V6_vxor
3239
0
    UINT64_C(503447584),  // V6_vzb
3240
0
    UINT64_C(503447616),  // V6_vzh
3241
0
    UINT64_C(738197504),  // V6_zLd_ai
3242
0
    UINT64_C(754974720),  // V6_zLd_pi
3243
0
    UINT64_C(754974721),  // V6_zLd_ppu
3244
0
    UINT64_C(746586112),  // V6_zLd_pred_ai
3245
0
    UINT64_C(763363328),  // V6_zLd_pred_pi
3246
0
    UINT64_C(763363329),  // V6_zLd_pred_ppu
3247
0
    UINT64_C(429916448),  // V6_zextract
3248
0
    UINT64_C(2818572288), // Y2_barrier
3249
0
    UINT64_C(1814036480), // Y2_break
3250
0
    UINT64_C(1677721696), // Y2_ciad
3251
0
    UINT64_C(1694498816), // Y2_crswap0
3252
0
    UINT64_C(1677721632), // Y2_cswi
3253
0
    UINT64_C(2684354560), // Y2_dccleana
3254
0
    UINT64_C(2720006144), // Y2_dccleanidx
3255
0
    UINT64_C(2688548864), // Y2_dccleaninva
3256
0
    UINT64_C(2724200448), // Y2_dccleaninvidx
3257
0
    UINT64_C(2483027968), // Y2_dcfetchbo
3258
0
    UINT64_C(2686451712), // Y2_dcinva
3259
0
    UINT64_C(2722103296), // Y2_dcinvidx
3260
0
    UINT64_C(2717908992), // Y2_dckill
3261
0
    UINT64_C(2753560576), // Y2_dctagr
3262
0
    UINT64_C(2751463424), // Y2_dctagw
3263
0
    UINT64_C(2696937472), // Y2_dczeroa
3264
0
    UINT64_C(1711276032), // Y2_getimask
3265
0
    UINT64_C(1717567488), // Y2_iassignr
3266
0
    UINT64_C(1677721664), // Y2_iassignw
3267
0
    UINT64_C(1436549120), // Y2_icdatar
3268
0
    UINT64_C(1438654464), // Y2_icdataw
3269
0
    UINT64_C(1455423488), // Y2_icinva
3270
0
    UINT64_C(1455425536), // Y2_icinvidx
3271
0
    UINT64_C(1455427584), // Y2_ickill
3272
0
    UINT64_C(1440743424), // Y2_ictagr
3273
0
    UINT64_C(1438646272), // Y2_ictagw
3274
0
    UINT64_C(1472200706), // Y2_isync
3275
0
    UINT64_C(1814036576), // Y2_k0lock
3276
0
    UINT64_C(1814036608), // Y2_k0unlock
3277
0
    UINT64_C(2824863744), // Y2_l2cleaninvidx
3278
0
    UINT64_C(2820669440), // Y2_l2kill
3279
0
    UINT64_C(1681915936), // Y2_resume
3280
0
    UINT64_C(1686110208), // Y2_setimask
3281
0
    UINT64_C(1686110240), // Y2_setprio
3282
0
    UINT64_C(1684013088), // Y2_start
3283
0
    UINT64_C(1684013056), // Y2_stop
3284
0
    UINT64_C(1677721600), // Y2_swi
3285
0
    UINT64_C(2822766592), // Y2_syncht
3286
0
    UINT64_C(1853882368), // Y2_tfrscrr
3287
0
    UINT64_C(1728053248), // Y2_tfrsrcr
3288
0
    UINT64_C(1814036512), // Y2_tlblock
3289
0
    UINT64_C(1820327936), // Y2_tlbp
3290
0
    UINT64_C(1816133632), // Y2_tlbr
3291
0
    UINT64_C(1814036544), // Y2_tlbunlock
3292
0
    UINT64_C(1811939328), // Y2_tlbw
3293
0
    UINT64_C(1681915904), // Y2_wait
3294
0
    UINT64_C(1696595968), // Y4_crswap1
3295
0
    UINT64_C(1837105152), // Y4_crswap10
3296
0
    UINT64_C(2785017856), // Y4_l2fetch
3297
0
    UINT64_C(2757754880), // Y4_l2tagr
3298
0
    UINT64_C(2755657728), // Y4_l2tagw
3299
0
    UINT64_C(1684013120), // Y4_nmi
3300
0
    UINT64_C(1686110304), // Y4_siad
3301
0
    UINT64_C(1862270976), // Y4_tfrscpp
3302
0
    UINT64_C(1828716544), // Y4_tfrspcp
3303
0
    UINT64_C(1648361472), // Y4_trace
3304
0
    UINT64_C(1824522240), // Y5_ctlbw
3305
0
    UINT64_C(2787115008), // Y5_l2cleanidx
3306
0
    UINT64_C(2793406464), // Y5_l2fetch
3307
0
    UINT64_C(2820673536), // Y5_l2gclean
3308
0
    UINT64_C(2820675584), // Y5_l2gcleaninv
3309
0
    UINT64_C(2820671488), // Y5_l2gunlock
3310
0
    UINT64_C(2789212160), // Y5_l2invidx
3311
0
    UINT64_C(2699042816), // Y5_l2locka
3312
0
    UINT64_C(2791309312), // Y5_l2unlocka
3313
0
    UINT64_C(1822425088), // Y5_tlbasidi
3314
0
    UINT64_C(1826619392), // Y5_tlboc
3315
0
    UINT64_C(1648361504), // Y6_diag
3316
0
    UINT64_C(1648361536), // Y6_diag0
3317
0
    UINT64_C(1648361568), // Y6_diag1
3318
0
    UINT64_C(2785017920), // Y6_dmlink
3319
0
    UINT64_C(2818572384), // Y6_dmpause
3320
0
    UINT64_C(2818572352), // Y6_dmpoll
3321
0
    UINT64_C(2785017984), // Y6_dmresume
3322
0
    UINT64_C(2785017888), // Y6_dmstart
3323
0
    UINT64_C(2818572320), // Y6_dmwait
3324
0
    UINT64_C(2797600768), // Y6_l2gcleaninvpa
3325
0
    UINT64_C(2795503616), // Y6_l2gcleanpa
3326
0
    UINT64_C(3581935616), // dep_A2_addsat
3327
0
    UINT64_C(3581935744), // dep_A2_subsat
3328
0
    UINT64_C(3556769792), // dep_S2_packhl
3329
0
    UINT64_C(0),  // invalid_decode
3330
0
    UINT64_C(0)
3331
0
  };
3332
0
  const unsigned opcode = MI.getOpcode();
3333
0
  uint64_t Value = InstBits[opcode];
3334
0
  uint64_t op = 0;
3335
0
  (void)op;  // suppress warning
3336
0
  switch (opcode) {
3337
0
    case Hexagon::A2_nop:
3338
0
    case Hexagon::CONST32:
3339
0
    case Hexagon::CONST64:
3340
0
    case Hexagon::DuplexIClass0:
3341
0
    case Hexagon::DuplexIClass1:
3342
0
    case Hexagon::DuplexIClass2:
3343
0
    case Hexagon::DuplexIClass3:
3344
0
    case Hexagon::DuplexIClass4:
3345
0
    case Hexagon::DuplexIClass5:
3346
0
    case Hexagon::DuplexIClass6:
3347
0
    case Hexagon::DuplexIClass7:
3348
0
    case Hexagon::DuplexIClass8:
3349
0
    case Hexagon::DuplexIClass9:
3350
0
    case Hexagon::DuplexIClassA:
3351
0
    case Hexagon::DuplexIClassB:
3352
0
    case Hexagon::DuplexIClassC:
3353
0
    case Hexagon::DuplexIClassD:
3354
0
    case Hexagon::DuplexIClassE:
3355
0
    case Hexagon::DuplexIClassF:
3356
0
    case Hexagon::J2_rte:
3357
0
    case Hexagon::J2_unpause:
3358
0
    case Hexagon::SL2_deallocframe:
3359
0
    case Hexagon::SL2_jumpr31:
3360
0
    case Hexagon::SL2_jumpr31_f:
3361
0
    case Hexagon::SL2_jumpr31_fnew:
3362
0
    case Hexagon::SL2_jumpr31_t:
3363
0
    case Hexagon::SL2_jumpr31_tnew:
3364
0
    case Hexagon::SL2_return:
3365
0
    case Hexagon::SL2_return_f:
3366
0
    case Hexagon::SL2_return_fnew:
3367
0
    case Hexagon::SL2_return_t:
3368
0
    case Hexagon::SL2_return_tnew:
3369
0
    case Hexagon::TFRI64_V2_ext:
3370
0
    case Hexagon::TFRI64_V4:
3371
0
    case Hexagon::V6_vhist:
3372
0
    case Hexagon::V6_vwhist128:
3373
0
    case Hexagon::V6_vwhist256:
3374
0
    case Hexagon::V6_vwhist256_sat:
3375
0
    case Hexagon::Y2_barrier:
3376
0
    case Hexagon::Y2_break:
3377
0
    case Hexagon::Y2_dckill:
3378
0
    case Hexagon::Y2_ickill:
3379
0
    case Hexagon::Y2_isync:
3380
0
    case Hexagon::Y2_k0lock:
3381
0
    case Hexagon::Y2_k0unlock:
3382
0
    case Hexagon::Y2_l2kill:
3383
0
    case Hexagon::Y2_syncht:
3384
0
    case Hexagon::Y2_tlblock:
3385
0
    case Hexagon::Y2_tlbunlock:
3386
0
    case Hexagon::Y5_l2gclean:
3387
0
    case Hexagon::Y5_l2gcleaninv:
3388
0
    case Hexagon::Y5_l2gunlock:
3389
0
    case Hexagon::invalid_decode: {
3390
0
      break;
3391
0
    }
3392
0
    case Hexagon::A2_tfrcrr: {
3393
      // op: Cs32
3394
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3395
0
      op &= UINT64_C(31);
3396
0
      op <<= 16;
3397
0
      Value |= op;
3398
      // op: Rd32
3399
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3400
0
      op &= UINT64_C(31);
3401
0
      Value |= op;
3402
0
      break;
3403
0
    }
3404
0
    case Hexagon::A4_tfrcpp: {
3405
      // op: Css32
3406
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3407
0
      op &= UINT64_C(31);
3408
0
      op <<= 16;
3409
0
      Value |= op;
3410
      // op: Rdd32
3411
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3412
0
      op &= UINT64_C(31);
3413
0
      Value |= op;
3414
0
      break;
3415
0
    }
3416
0
    case Hexagon::G4_tfrgcrr: {
3417
      // op: Gs32
3418
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3419
0
      op &= UINT64_C(31);
3420
0
      op <<= 16;
3421
0
      Value |= op;
3422
      // op: Rd32
3423
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3424
0
      op &= UINT64_C(31);
3425
0
      Value |= op;
3426
0
      break;
3427
0
    }
3428
0
    case Hexagon::G4_tfrgcpp: {
3429
      // op: Gss32
3430
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3431
0
      op &= UINT64_C(31);
3432
0
      op <<= 16;
3433
0
      Value |= op;
3434
      // op: Rdd32
3435
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3436
0
      op &= UINT64_C(31);
3437
0
      Value |= op;
3438
0
      break;
3439
0
    }
3440
0
    case Hexagon::J4_cmpeqi_f_jumpnv_nt:
3441
0
    case Hexagon::J4_cmpeqi_f_jumpnv_t:
3442
0
    case Hexagon::J4_cmpeqi_t_jumpnv_nt:
3443
0
    case Hexagon::J4_cmpeqi_t_jumpnv_t:
3444
0
    case Hexagon::J4_cmpgti_f_jumpnv_nt:
3445
0
    case Hexagon::J4_cmpgti_f_jumpnv_t:
3446
0
    case Hexagon::J4_cmpgti_t_jumpnv_nt:
3447
0
    case Hexagon::J4_cmpgti_t_jumpnv_t:
3448
0
    case Hexagon::J4_cmpgtui_f_jumpnv_nt:
3449
0
    case Hexagon::J4_cmpgtui_f_jumpnv_t:
3450
0
    case Hexagon::J4_cmpgtui_t_jumpnv_nt:
3451
0
    case Hexagon::J4_cmpgtui_t_jumpnv_t: {
3452
      // op: II
3453
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3454
0
      op &= UINT64_C(31);
3455
0
      op <<= 8;
3456
0
      Value |= op;
3457
      // op: Ii
3458
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3459
0
      Value |= (op & UINT64_C(1536)) << 11;
3460
0
      Value |= (op & UINT64_C(508)) >> 1;
3461
      // op: Ns8
3462
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3463
0
      op &= UINT64_C(7);
3464
0
      op <<= 16;
3465
0
      Value |= op;
3466
0
      break;
3467
0
    }
3468
0
    case Hexagon::J4_cmpeqi_fp0_jump_nt:
3469
0
    case Hexagon::J4_cmpeqi_fp0_jump_t:
3470
0
    case Hexagon::J4_cmpeqi_fp1_jump_nt:
3471
0
    case Hexagon::J4_cmpeqi_fp1_jump_t:
3472
0
    case Hexagon::J4_cmpeqi_tp0_jump_nt:
3473
0
    case Hexagon::J4_cmpeqi_tp0_jump_t:
3474
0
    case Hexagon::J4_cmpeqi_tp1_jump_nt:
3475
0
    case Hexagon::J4_cmpeqi_tp1_jump_t:
3476
0
    case Hexagon::J4_cmpgti_fp0_jump_nt:
3477
0
    case Hexagon::J4_cmpgti_fp0_jump_t:
3478
0
    case Hexagon::J4_cmpgti_fp1_jump_nt:
3479
0
    case Hexagon::J4_cmpgti_fp1_jump_t:
3480
0
    case Hexagon::J4_cmpgti_tp0_jump_nt:
3481
0
    case Hexagon::J4_cmpgti_tp0_jump_t:
3482
0
    case Hexagon::J4_cmpgti_tp1_jump_nt:
3483
0
    case Hexagon::J4_cmpgti_tp1_jump_t:
3484
0
    case Hexagon::J4_cmpgtui_fp0_jump_nt:
3485
0
    case Hexagon::J4_cmpgtui_fp0_jump_t:
3486
0
    case Hexagon::J4_cmpgtui_fp1_jump_nt:
3487
0
    case Hexagon::J4_cmpgtui_fp1_jump_t:
3488
0
    case Hexagon::J4_cmpgtui_tp0_jump_nt:
3489
0
    case Hexagon::J4_cmpgtui_tp0_jump_t:
3490
0
    case Hexagon::J4_cmpgtui_tp1_jump_nt:
3491
0
    case Hexagon::J4_cmpgtui_tp1_jump_t: {
3492
      // op: II
3493
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3494
0
      op &= UINT64_C(31);
3495
0
      op <<= 8;
3496
0
      Value |= op;
3497
      // op: Ii
3498
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3499
0
      Value |= (op & UINT64_C(1536)) << 11;
3500
0
      Value |= (op & UINT64_C(508)) >> 1;
3501
      // op: Rs16
3502
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3503
0
      op &= UINT64_C(15);
3504
0
      op <<= 16;
3505
0
      Value |= op;
3506
0
      break;
3507
0
    }
3508
0
    case Hexagon::S4_storerbnew_ap:
3509
0
    case Hexagon::S4_storerhnew_ap:
3510
0
    case Hexagon::S4_storerinew_ap: {
3511
      // op: II
3512
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3513
0
      op &= UINT64_C(63);
3514
0
      Value |= op;
3515
      // op: Nt8
3516
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3517
0
      op &= UINT64_C(7);
3518
0
      op <<= 8;
3519
0
      Value |= op;
3520
      // op: Re32
3521
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3522
0
      op &= UINT64_C(31);
3523
0
      op <<= 16;
3524
0
      Value |= op;
3525
0
      break;
3526
0
    }
3527
0
    case Hexagon::S4_storerb_ap:
3528
0
    case Hexagon::S4_storerf_ap:
3529
0
    case Hexagon::S4_storerh_ap:
3530
0
    case Hexagon::S4_storeri_ap: {
3531
      // op: II
3532
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3533
0
      op &= UINT64_C(63);
3534
0
      Value |= op;
3535
      // op: Rt32
3536
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3537
0
      op &= UINT64_C(31);
3538
0
      op <<= 8;
3539
0
      Value |= op;
3540
      // op: Re32
3541
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3542
0
      op &= UINT64_C(31);
3543
0
      op <<= 16;
3544
0
      Value |= op;
3545
0
      break;
3546
0
    }
3547
0
    case Hexagon::S4_storerd_ap: {
3548
      // op: II
3549
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3550
0
      op &= UINT64_C(63);
3551
0
      Value |= op;
3552
      // op: Rtt32
3553
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3554
0
      op &= UINT64_C(31);
3555
0
      op <<= 8;
3556
0
      Value |= op;
3557
      // op: Re32
3558
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3559
0
      op &= UINT64_C(31);
3560
0
      op <<= 16;
3561
0
      Value |= op;
3562
0
      break;
3563
0
    }
3564
0
    case Hexagon::J4_jumpseti: {
3565
      // op: II
3566
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3567
0
      op &= UINT64_C(63);
3568
0
      op <<= 8;
3569
0
      Value |= op;
3570
      // op: Ii
3571
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3572
0
      Value |= (op & UINT64_C(1536)) << 11;
3573
0
      Value |= (op & UINT64_C(508)) >> 1;
3574
      // op: Rd16
3575
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3576
0
      op &= UINT64_C(15);
3577
0
      op <<= 16;
3578
0
      Value |= op;
3579
0
      break;
3580
0
    }
3581
0
    case Hexagon::L4_loadbsw2_ap:
3582
0
    case Hexagon::L4_loadbzw2_ap:
3583
0
    case Hexagon::L4_loadrb_ap:
3584
0
    case Hexagon::L4_loadrh_ap:
3585
0
    case Hexagon::L4_loadri_ap:
3586
0
    case Hexagon::L4_loadrub_ap:
3587
0
    case Hexagon::L4_loadruh_ap: {
3588
      // op: II
3589
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3590
0
      Value |= (op & UINT64_C(60)) << 6;
3591
0
      Value |= (op & UINT64_C(3)) << 5;
3592
      // op: Rd32
3593
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3594
0
      op &= UINT64_C(31);
3595
0
      Value |= op;
3596
      // op: Re32
3597
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3598
0
      op &= UINT64_C(31);
3599
0
      op <<= 16;
3600
0
      Value |= op;
3601
0
      break;
3602
0
    }
3603
0
    case Hexagon::L4_loadbsw4_ap:
3604
0
    case Hexagon::L4_loadbzw4_ap:
3605
0
    case Hexagon::L4_loadrd_ap: {
3606
      // op: II
3607
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3608
0
      Value |= (op & UINT64_C(60)) << 6;
3609
0
      Value |= (op & UINT64_C(3)) << 5;
3610
      // op: Rdd32
3611
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3612
0
      op &= UINT64_C(31);
3613
0
      Value |= op;
3614
      // op: Re32
3615
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3616
0
      op &= UINT64_C(31);
3617
0
      op <<= 16;
3618
0
      Value |= op;
3619
0
      break;
3620
0
    }
3621
0
    case Hexagon::L4_loadalignb_ap:
3622
0
    case Hexagon::L4_loadalignh_ap: {
3623
      // op: II
3624
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
3625
0
      Value |= (op & UINT64_C(60)) << 6;
3626
0
      Value |= (op & UINT64_C(3)) << 5;
3627
      // op: Ryy32
3628
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3629
0
      op &= UINT64_C(31);
3630
0
      Value |= op;
3631
      // op: Re32
3632
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3633
0
      op &= UINT64_C(31);
3634
0
      op <<= 16;
3635
0
      Value |= op;
3636
0
      break;
3637
0
    }
3638
0
    case Hexagon::J2_call:
3639
0
    case Hexagon::J2_jump: {
3640
      // op: Ii
3641
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3642
0
      Value |= (op & UINT64_C(16744448)) << 1;
3643
0
      Value |= (op & UINT64_C(32764)) >> 1;
3644
0
      break;
3645
0
    }
3646
0
    case Hexagon::PS_storerinewabs:
3647
0
    case Hexagon::S2_storerinewgp: {
3648
      // op: Ii
3649
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3650
0
      Value |= (op & UINT64_C(196608)) << 9;
3651
0
      Value |= (op & UINT64_C(63488)) << 5;
3652
0
      Value |= (op & UINT64_C(1024)) << 3;
3653
0
      Value |= (op & UINT64_C(1020)) >> 2;
3654
      // op: Nt8
3655
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3656
0
      op &= UINT64_C(7);
3657
0
      op <<= 8;
3658
0
      Value |= op;
3659
0
      break;
3660
0
    }
3661
0
    case Hexagon::PS_storeriabs:
3662
0
    case Hexagon::S2_storerigp: {
3663
      // op: Ii
3664
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3665
0
      Value |= (op & UINT64_C(196608)) << 9;
3666
0
      Value |= (op & UINT64_C(63488)) << 5;
3667
0
      Value |= (op & UINT64_C(1024)) << 3;
3668
0
      Value |= (op & UINT64_C(1020)) >> 2;
3669
      // op: Rt32
3670
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3671
0
      op &= UINT64_C(31);
3672
0
      op <<= 8;
3673
0
      Value |= op;
3674
0
      break;
3675
0
    }
3676
0
    case Hexagon::J2_trap0:
3677
0
    case Hexagon::PS_trap1: {
3678
      // op: Ii
3679
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3680
0
      Value |= (op & UINT64_C(248)) << 5;
3681
0
      Value |= (op & UINT64_C(7)) << 2;
3682
0
      break;
3683
0
    }
3684
0
    case Hexagon::PS_storerdabs:
3685
0
    case Hexagon::S2_storerdgp: {
3686
      // op: Ii
3687
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3688
0
      Value |= (op & UINT64_C(393216)) << 8;
3689
0
      Value |= (op & UINT64_C(126976)) << 4;
3690
0
      Value |= (op & UINT64_C(2048)) << 2;
3691
0
      Value |= (op & UINT64_C(2040)) >> 3;
3692
      // op: Rtt32
3693
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3694
0
      op &= UINT64_C(31);
3695
0
      op <<= 8;
3696
0
      Value |= op;
3697
0
      break;
3698
0
    }
3699
0
    case Hexagon::A4_ext: {
3700
      // op: Ii
3701
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3702
0
      Value |= (op & UINT64_C(4293918720)) >> 4;
3703
0
      Value |= (op & UINT64_C(1048512)) >> 6;
3704
0
      break;
3705
0
    }
3706
0
    case Hexagon::PS_storerbnewabs:
3707
0
    case Hexagon::S2_storerbnewgp: {
3708
      // op: Ii
3709
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3710
0
      Value |= (op & UINT64_C(49152)) << 11;
3711
0
      Value |= (op & UINT64_C(15872)) << 7;
3712
0
      Value |= (op & UINT64_C(256)) << 5;
3713
0
      Value |= (op & UINT64_C(255));
3714
      // op: Nt8
3715
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3716
0
      op &= UINT64_C(7);
3717
0
      op <<= 8;
3718
0
      Value |= op;
3719
0
      break;
3720
0
    }
3721
0
    case Hexagon::PS_storerbabs:
3722
0
    case Hexagon::S2_storerbgp: {
3723
      // op: Ii
3724
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3725
0
      Value |= (op & UINT64_C(49152)) << 11;
3726
0
      Value |= (op & UINT64_C(15872)) << 7;
3727
0
      Value |= (op & UINT64_C(256)) << 5;
3728
0
      Value |= (op & UINT64_C(255));
3729
      // op: Rt32
3730
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3731
0
      op &= UINT64_C(31);
3732
0
      op <<= 8;
3733
0
      Value |= op;
3734
0
      break;
3735
0
    }
3736
0
    case Hexagon::J2_loop0i:
3737
0
    case Hexagon::J2_loop1i:
3738
0
    case Hexagon::J2_ploop1si:
3739
0
    case Hexagon::J2_ploop2si:
3740
0
    case Hexagon::J2_ploop3si: {
3741
      // op: Ii
3742
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3743
0
      Value |= (op & UINT64_C(496)) << 4;
3744
0
      Value |= (op & UINT64_C(12)) << 1;
3745
      // op: II
3746
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3747
0
      Value |= (op & UINT64_C(992)) << 11;
3748
0
      Value |= (op & UINT64_C(28)) << 3;
3749
0
      Value |= (op & UINT64_C(3));
3750
0
      break;
3751
0
    }
3752
0
    case Hexagon::J2_loop0r:
3753
0
    case Hexagon::J2_loop1r:
3754
0
    case Hexagon::J2_ploop1sr:
3755
0
    case Hexagon::J2_ploop2sr:
3756
0
    case Hexagon::J2_ploop3sr: {
3757
      // op: Ii
3758
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3759
0
      Value |= (op & UINT64_C(496)) << 4;
3760
0
      Value |= (op & UINT64_C(12)) << 1;
3761
      // op: Rs32
3762
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3763
0
      op &= UINT64_C(31);
3764
0
      op <<= 16;
3765
0
      Value |= op;
3766
0
      break;
3767
0
    }
3768
0
    case Hexagon::J2_pause: {
3769
      // op: Ii
3770
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3771
0
      Value |= (op & UINT64_C(768)) << 8;
3772
0
      Value |= (op & UINT64_C(248)) << 5;
3773
0
      Value |= (op & UINT64_C(7)) << 2;
3774
0
      break;
3775
0
    }
3776
0
    case Hexagon::PS_storerhnewabs:
3777
0
    case Hexagon::S2_storerhnewgp: {
3778
      // op: Ii
3779
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3780
0
      Value |= (op & UINT64_C(98304)) << 10;
3781
0
      Value |= (op & UINT64_C(31744)) << 6;
3782
0
      Value |= (op & UINT64_C(512)) << 4;
3783
0
      Value |= (op & UINT64_C(510)) >> 1;
3784
      // op: Nt8
3785
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3786
0
      op &= UINT64_C(7);
3787
0
      op <<= 8;
3788
0
      Value |= op;
3789
0
      break;
3790
0
    }
3791
0
    case Hexagon::PS_storerfabs:
3792
0
    case Hexagon::PS_storerhabs:
3793
0
    case Hexagon::S2_storerfgp:
3794
0
    case Hexagon::S2_storerhgp: {
3795
      // op: Ii
3796
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3797
0
      Value |= (op & UINT64_C(98304)) << 10;
3798
0
      Value |= (op & UINT64_C(31744)) << 6;
3799
0
      Value |= (op & UINT64_C(512)) << 4;
3800
0
      Value |= (op & UINT64_C(510)) >> 1;
3801
      // op: Rt32
3802
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3803
0
      op &= UINT64_C(31);
3804
0
      op <<= 8;
3805
0
      Value |= op;
3806
0
      break;
3807
0
    }
3808
0
    case Hexagon::V6_vwhist128m: {
3809
      // op: Ii
3810
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3811
0
      op &= UINT64_C(1);
3812
0
      op <<= 8;
3813
0
      Value |= op;
3814
0
      break;
3815
0
    }
3816
0
    case Hexagon::SS2_storew_sp: {
3817
      // op: Ii
3818
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3819
0
      op &= UINT64_C(124);
3820
0
      op <<= 2;
3821
0
      Value |= op;
3822
      // op: Rt16
3823
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3824
0
      op &= UINT64_C(15);
3825
0
      Value |= op;
3826
0
      break;
3827
0
    }
3828
0
    case Hexagon::SS2_allocframe: {
3829
      // op: Ii
3830
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3831
0
      op &= UINT64_C(248);
3832
0
      op <<= 1;
3833
0
      Value |= op;
3834
0
      break;
3835
0
    }
3836
0
    case Hexagon::SS2_stored_sp: {
3837
      // op: Ii
3838
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3839
0
      op &= UINT64_C(504);
3840
0
      Value |= op;
3841
      // op: Rtt8
3842
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3843
0
      op &= UINT64_C(7);
3844
0
      Value |= op;
3845
0
      break;
3846
0
    }
3847
0
    case Hexagon::S2_storerd_io: {
3848
      // op: Ii
3849
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3850
0
      Value |= (op & UINT64_C(12288)) << 13;
3851
0
      Value |= (op & UINT64_C(2048)) << 2;
3852
0
      Value |= (op & UINT64_C(2040)) >> 3;
3853
      // op: Rs32
3854
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3855
0
      op &= UINT64_C(31);
3856
0
      op <<= 16;
3857
0
      Value |= op;
3858
      // op: Rtt32
3859
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3860
0
      op &= UINT64_C(31);
3861
0
      op <<= 8;
3862
0
      Value |= op;
3863
0
      break;
3864
0
    }
3865
0
    case Hexagon::J4_tstbit0_f_jumpnv_nt:
3866
0
    case Hexagon::J4_tstbit0_f_jumpnv_t:
3867
0
    case Hexagon::J4_tstbit0_t_jumpnv_nt:
3868
0
    case Hexagon::J4_tstbit0_t_jumpnv_t: {
3869
      // op: Ii
3870
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3871
0
      Value |= (op & UINT64_C(1536)) << 11;
3872
0
      Value |= (op & UINT64_C(508)) >> 1;
3873
      // op: Ns8
3874
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3875
0
      op &= UINT64_C(7);
3876
0
      op <<= 16;
3877
0
      Value |= op;
3878
0
      break;
3879
0
    }
3880
0
    case Hexagon::J4_tstbit0_fp0_jump_nt:
3881
0
    case Hexagon::J4_tstbit0_fp0_jump_t:
3882
0
    case Hexagon::J4_tstbit0_fp1_jump_nt:
3883
0
    case Hexagon::J4_tstbit0_fp1_jump_t:
3884
0
    case Hexagon::J4_tstbit0_tp0_jump_nt:
3885
0
    case Hexagon::J4_tstbit0_tp0_jump_t:
3886
0
    case Hexagon::J4_tstbit0_tp1_jump_nt:
3887
0
    case Hexagon::J4_tstbit0_tp1_jump_t: {
3888
      // op: Ii
3889
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3890
0
      Value |= (op & UINT64_C(1536)) << 11;
3891
0
      Value |= (op & UINT64_C(508)) >> 1;
3892
      // op: Rs16
3893
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3894
0
      op &= UINT64_C(15);
3895
0
      op <<= 16;
3896
0
      Value |= op;
3897
0
      break;
3898
0
    }
3899
0
    case Hexagon::S2_storerbnew_io: {
3900
      // op: Ii
3901
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3902
0
      Value |= (op & UINT64_C(1536)) << 16;
3903
0
      Value |= (op & UINT64_C(256)) << 5;
3904
0
      Value |= (op & UINT64_C(255));
3905
      // op: Rs32
3906
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3907
0
      op &= UINT64_C(31);
3908
0
      op <<= 16;
3909
0
      Value |= op;
3910
      // op: Nt8
3911
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3912
0
      op &= UINT64_C(7);
3913
0
      op <<= 8;
3914
0
      Value |= op;
3915
0
      break;
3916
0
    }
3917
0
    case Hexagon::S2_storerb_io: {
3918
      // op: Ii
3919
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3920
0
      Value |= (op & UINT64_C(1536)) << 16;
3921
0
      Value |= (op & UINT64_C(256)) << 5;
3922
0
      Value |= (op & UINT64_C(255));
3923
      // op: Rs32
3924
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3925
0
      op &= UINT64_C(31);
3926
0
      op <<= 16;
3927
0
      Value |= op;
3928
      // op: Rt32
3929
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3930
0
      op &= UINT64_C(31);
3931
0
      op <<= 8;
3932
0
      Value |= op;
3933
0
      break;
3934
0
    }
3935
0
    case Hexagon::J2_jumprgtez:
3936
0
    case Hexagon::J2_jumprgtezpt:
3937
0
    case Hexagon::J2_jumprltez:
3938
0
    case Hexagon::J2_jumprltezpt:
3939
0
    case Hexagon::J2_jumprnz:
3940
0
    case Hexagon::J2_jumprnzpt:
3941
0
    case Hexagon::J2_jumprz:
3942
0
    case Hexagon::J2_jumprzpt: {
3943
      // op: Ii
3944
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3945
0
      Value |= (op & UINT64_C(16384)) << 7;
3946
0
      Value |= (op & UINT64_C(8192));
3947
0
      Value |= (op & UINT64_C(8188)) >> 1;
3948
      // op: Rs32
3949
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3950
0
      op &= UINT64_C(31);
3951
0
      op <<= 16;
3952
0
      Value |= op;
3953
0
      break;
3954
0
    }
3955
0
    case Hexagon::L2_loadrigp:
3956
0
    case Hexagon::PS_loadriabs: {
3957
      // op: Ii
3958
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3959
0
      Value |= (op & UINT64_C(196608)) << 9;
3960
0
      Value |= (op & UINT64_C(63488)) << 5;
3961
0
      Value |= (op & UINT64_C(2044)) << 3;
3962
      // op: Rd32
3963
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3964
0
      op &= UINT64_C(31);
3965
0
      Value |= op;
3966
0
      break;
3967
0
    }
3968
0
    case Hexagon::S4_storerbnew_ur:
3969
0
    case Hexagon::S4_storerhnew_ur:
3970
0
    case Hexagon::S4_storerinew_ur: {
3971
      // op: Ii
3972
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3973
0
      Value |= (op & UINT64_C(2)) << 12;
3974
0
      Value |= (op & UINT64_C(1)) << 6;
3975
      // op: II
3976
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3977
0
      op &= UINT64_C(63);
3978
0
      Value |= op;
3979
      // op: Ru32
3980
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3981
0
      op &= UINT64_C(31);
3982
0
      op <<= 16;
3983
0
      Value |= op;
3984
      // op: Nt8
3985
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
3986
0
      op &= UINT64_C(7);
3987
0
      op <<= 8;
3988
0
      Value |= op;
3989
0
      break;
3990
0
    }
3991
0
    case Hexagon::S4_storerb_ur:
3992
0
    case Hexagon::S4_storerf_ur:
3993
0
    case Hexagon::S4_storerh_ur:
3994
0
    case Hexagon::S4_storeri_ur: {
3995
      // op: Ii
3996
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3997
0
      Value |= (op & UINT64_C(2)) << 12;
3998
0
      Value |= (op & UINT64_C(1)) << 6;
3999
      // op: II
4000
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4001
0
      op &= UINT64_C(63);
4002
0
      Value |= op;
4003
      // op: Ru32
4004
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4005
0
      op &= UINT64_C(31);
4006
0
      op <<= 16;
4007
0
      Value |= op;
4008
      // op: Rt32
4009
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4010
0
      op &= UINT64_C(31);
4011
0
      op <<= 8;
4012
0
      Value |= op;
4013
0
      break;
4014
0
    }
4015
0
    case Hexagon::S4_storerd_ur: {
4016
      // op: Ii
4017
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4018
0
      Value |= (op & UINT64_C(2)) << 12;
4019
0
      Value |= (op & UINT64_C(1)) << 6;
4020
      // op: II
4021
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4022
0
      op &= UINT64_C(63);
4023
0
      Value |= op;
4024
      // op: Ru32
4025
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4026
0
      op &= UINT64_C(31);
4027
0
      op <<= 16;
4028
0
      Value |= op;
4029
      // op: Rtt32
4030
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4031
0
      op &= UINT64_C(31);
4032
0
      op <<= 8;
4033
0
      Value |= op;
4034
0
      break;
4035
0
    }
4036
0
    case Hexagon::S4_addi_asl_ri:
4037
0
    case Hexagon::S4_addi_lsr_ri:
4038
0
    case Hexagon::S4_andi_asl_ri:
4039
0
    case Hexagon::S4_andi_lsr_ri:
4040
0
    case Hexagon::S4_ori_asl_ri:
4041
0
    case Hexagon::S4_ori_lsr_ri:
4042
0
    case Hexagon::S4_subi_asl_ri:
4043
0
    case Hexagon::S4_subi_lsr_ri: {
4044
      // op: Ii
4045
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4046
0
      Value |= (op & UINT64_C(224)) << 16;
4047
0
      Value |= (op & UINT64_C(16)) << 9;
4048
0
      Value |= (op & UINT64_C(14)) << 4;
4049
0
      Value |= (op & UINT64_C(1)) << 3;
4050
      // op: II
4051
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4052
0
      op &= UINT64_C(31);
4053
0
      op <<= 8;
4054
0
      Value |= op;
4055
      // op: Rx32
4056
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4057
0
      op &= UINT64_C(31);
4058
0
      op <<= 16;
4059
0
      Value |= op;
4060
0
      break;
4061
0
    }
4062
0
    case Hexagon::S2_storerhnew_io: {
4063
      // op: Ii
4064
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4065
0
      Value |= (op & UINT64_C(3072)) << 15;
4066
0
      Value |= (op & UINT64_C(512)) << 4;
4067
0
      Value |= (op & UINT64_C(510)) >> 1;
4068
      // op: Rs32
4069
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4070
0
      op &= UINT64_C(31);
4071
0
      op <<= 16;
4072
0
      Value |= op;
4073
      // op: Nt8
4074
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4075
0
      op &= UINT64_C(7);
4076
0
      op <<= 8;
4077
0
      Value |= op;
4078
0
      break;
4079
0
    }
4080
0
    case Hexagon::S2_storerf_io:
4081
0
    case Hexagon::S2_storerh_io: {
4082
      // op: Ii
4083
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4084
0
      Value |= (op & UINT64_C(3072)) << 15;
4085
0
      Value |= (op & UINT64_C(512)) << 4;
4086
0
      Value |= (op & UINT64_C(510)) >> 1;
4087
      // op: Rs32
4088
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4089
0
      op &= UINT64_C(31);
4090
0
      op <<= 16;
4091
0
      Value |= op;
4092
      // op: Rt32
4093
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4094
0
      op &= UINT64_C(31);
4095
0
      op <<= 8;
4096
0
      Value |= op;
4097
0
      break;
4098
0
    }
4099
0
    case Hexagon::L2_loadrdgp:
4100
0
    case Hexagon::PS_loadrdabs: {
4101
      // op: Ii
4102
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4103
0
      Value |= (op & UINT64_C(393216)) << 8;
4104
0
      Value |= (op & UINT64_C(126976)) << 4;
4105
0
      Value |= (op & UINT64_C(4088)) << 2;
4106
      // op: Rdd32
4107
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4108
0
      op &= UINT64_C(31);
4109
0
      Value |= op;
4110
0
      break;
4111
0
    }
4112
0
    case Hexagon::S4_pstorerbnewf_abs:
4113
0
    case Hexagon::S4_pstorerbnewfnew_abs:
4114
0
    case Hexagon::S4_pstorerbnewt_abs:
4115
0
    case Hexagon::S4_pstorerbnewtnew_abs:
4116
0
    case Hexagon::S4_pstorerhnewf_abs:
4117
0
    case Hexagon::S4_pstorerhnewfnew_abs:
4118
0
    case Hexagon::S4_pstorerhnewt_abs:
4119
0
    case Hexagon::S4_pstorerhnewtnew_abs:
4120
0
    case Hexagon::S4_pstorerinewf_abs:
4121
0
    case Hexagon::S4_pstorerinewfnew_abs:
4122
0
    case Hexagon::S4_pstorerinewt_abs:
4123
0
    case Hexagon::S4_pstorerinewtnew_abs: {
4124
      // op: Ii
4125
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4126
0
      Value |= (op & UINT64_C(48)) << 12;
4127
0
      Value |= (op & UINT64_C(15)) << 3;
4128
      // op: Pv4
4129
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4130
0
      op &= UINT64_C(3);
4131
0
      Value |= op;
4132
      // op: Nt8
4133
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4134
0
      op &= UINT64_C(7);
4135
0
      op <<= 8;
4136
0
      Value |= op;
4137
0
      break;
4138
0
    }
4139
0
    case Hexagon::S4_pstorerbf_abs:
4140
0
    case Hexagon::S4_pstorerbfnew_abs:
4141
0
    case Hexagon::S4_pstorerbt_abs:
4142
0
    case Hexagon::S4_pstorerbtnew_abs:
4143
0
    case Hexagon::S4_pstorerff_abs:
4144
0
    case Hexagon::S4_pstorerffnew_abs:
4145
0
    case Hexagon::S4_pstorerft_abs:
4146
0
    case Hexagon::S4_pstorerftnew_abs:
4147
0
    case Hexagon::S4_pstorerhf_abs:
4148
0
    case Hexagon::S4_pstorerhfnew_abs:
4149
0
    case Hexagon::S4_pstorerht_abs:
4150
0
    case Hexagon::S4_pstorerhtnew_abs:
4151
0
    case Hexagon::S4_pstorerif_abs:
4152
0
    case Hexagon::S4_pstorerifnew_abs:
4153
0
    case Hexagon::S4_pstorerit_abs:
4154
0
    case Hexagon::S4_pstoreritnew_abs: {
4155
      // op: Ii
4156
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4157
0
      Value |= (op & UINT64_C(48)) << 12;
4158
0
      Value |= (op & UINT64_C(15)) << 3;
4159
      // op: Pv4
4160
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4161
0
      op &= UINT64_C(3);
4162
0
      Value |= op;
4163
      // op: Rt32
4164
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4165
0
      op &= UINT64_C(31);
4166
0
      op <<= 8;
4167
0
      Value |= op;
4168
0
      break;
4169
0
    }
4170
0
    case Hexagon::S4_pstorerdf_abs:
4171
0
    case Hexagon::S4_pstorerdfnew_abs:
4172
0
    case Hexagon::S4_pstorerdt_abs:
4173
0
    case Hexagon::S4_pstorerdtnew_abs: {
4174
      // op: Ii
4175
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4176
0
      Value |= (op & UINT64_C(48)) << 12;
4177
0
      Value |= (op & UINT64_C(15)) << 3;
4178
      // op: Pv4
4179
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4180
0
      op &= UINT64_C(3);
4181
0
      Value |= op;
4182
      // op: Rtt32
4183
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4184
0
      op &= UINT64_C(31);
4185
0
      op <<= 8;
4186
0
      Value |= op;
4187
0
      break;
4188
0
    }
4189
0
    case Hexagon::M4_mpyri_addi: {
4190
      // op: Ii
4191
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4192
0
      Value |= (op & UINT64_C(48)) << 17;
4193
0
      Value |= (op & UINT64_C(8)) << 10;
4194
0
      Value |= (op & UINT64_C(7)) << 5;
4195
      // op: II
4196
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4197
0
      Value |= (op & UINT64_C(32)) << 18;
4198
0
      Value |= (op & UINT64_C(31));
4199
      // op: Rs32
4200
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4201
0
      op &= UINT64_C(31);
4202
0
      op <<= 16;
4203
0
      Value |= op;
4204
      // op: Rd32
4205
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4206
0
      op &= UINT64_C(31);
4207
0
      op <<= 8;
4208
0
      Value |= op;
4209
0
      break;
4210
0
    }
4211
0
    case Hexagon::M4_mpyrr_addi: {
4212
      // op: Ii
4213
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4214
0
      Value |= (op & UINT64_C(48)) << 17;
4215
0
      Value |= (op & UINT64_C(8)) << 10;
4216
0
      Value |= (op & UINT64_C(7)) << 5;
4217
      // op: Rs32
4218
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4219
0
      op &= UINT64_C(31);
4220
0
      op <<= 16;
4221
0
      Value |= op;
4222
      // op: Rt32
4223
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4224
0
      op &= UINT64_C(31);
4225
0
      op <<= 8;
4226
0
      Value |= op;
4227
      // op: Rd32
4228
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4229
0
      op &= UINT64_C(31);
4230
0
      Value |= op;
4231
0
      break;
4232
0
    }
4233
0
    case Hexagon::L2_loadrbgp:
4234
0
    case Hexagon::L2_loadrubgp:
4235
0
    case Hexagon::PS_loadrbabs:
4236
0
    case Hexagon::PS_loadrubabs: {
4237
      // op: Ii
4238
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4239
0
      Value |= (op & UINT64_C(49152)) << 11;
4240
0
      Value |= (op & UINT64_C(15872)) << 7;
4241
0
      Value |= (op & UINT64_C(511)) << 5;
4242
      // op: Rd32
4243
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4244
0
      op &= UINT64_C(31);
4245
0
      Value |= op;
4246
0
      break;
4247
0
    }
4248
0
    case Hexagon::A2_tfrsi: {
4249
      // op: Ii
4250
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4251
0
      Value |= (op & UINT64_C(49152)) << 8;
4252
0
      Value |= (op & UINT64_C(15872)) << 7;
4253
0
      Value |= (op & UINT64_C(511)) << 5;
4254
      // op: Rd32
4255
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4256
0
      op &= UINT64_C(31);
4257
0
      Value |= op;
4258
0
      break;
4259
0
    }
4260
0
    case Hexagon::F2_sfimm_n:
4261
0
    case Hexagon::F2_sfimm_p: {
4262
      // op: Ii
4263
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4264
0
      Value |= (op & UINT64_C(512)) << 12;
4265
0
      Value |= (op & UINT64_C(511)) << 5;
4266
      // op: Rd32
4267
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4268
0
      op &= UINT64_C(31);
4269
0
      Value |= op;
4270
0
      break;
4271
0
    }
4272
0
    case Hexagon::F2_dfimm_n:
4273
0
    case Hexagon::F2_dfimm_p: {
4274
      // op: Ii
4275
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4276
0
      Value |= (op & UINT64_C(512)) << 12;
4277
0
      Value |= (op & UINT64_C(511)) << 5;
4278
      // op: Rdd32
4279
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4280
0
      op &= UINT64_C(31);
4281
0
      Value |= op;
4282
0
      break;
4283
0
    }
4284
0
    case Hexagon::A2_subri: {
4285
      // op: Ii
4286
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4287
0
      Value |= (op & UINT64_C(512)) << 12;
4288
0
      Value |= (op & UINT64_C(511)) << 5;
4289
      // op: Rs32
4290
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4291
0
      op &= UINT64_C(31);
4292
0
      op <<= 16;
4293
0
      Value |= op;
4294
      // op: Rd32
4295
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4296
0
      op &= UINT64_C(31);
4297
0
      Value |= op;
4298
0
      break;
4299
0
    }
4300
0
    case Hexagon::S2_storerinew_io: {
4301
      // op: Ii
4302
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4303
0
      Value |= (op & UINT64_C(6144)) << 14;
4304
0
      Value |= (op & UINT64_C(1024)) << 3;
4305
0
      Value |= (op & UINT64_C(1020)) >> 2;
4306
      // op: Rs32
4307
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4308
0
      op &= UINT64_C(31);
4309
0
      op <<= 16;
4310
0
      Value |= op;
4311
      // op: Nt8
4312
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4313
0
      op &= UINT64_C(7);
4314
0
      op <<= 8;
4315
0
      Value |= op;
4316
0
      break;
4317
0
    }
4318
0
    case Hexagon::S2_storeri_io: {
4319
      // op: Ii
4320
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4321
0
      Value |= (op & UINT64_C(6144)) << 14;
4322
0
      Value |= (op & UINT64_C(1024)) << 3;
4323
0
      Value |= (op & UINT64_C(1020)) >> 2;
4324
      // op: Rs32
4325
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4326
0
      op &= UINT64_C(31);
4327
0
      op <<= 16;
4328
0
      Value |= op;
4329
      // op: Rt32
4330
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4331
0
      op &= UINT64_C(31);
4332
0
      op <<= 8;
4333
0
      Value |= op;
4334
0
      break;
4335
0
    }
4336
0
    case Hexagon::S4_lsli: {
4337
      // op: Ii
4338
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4339
0
      Value |= (op & UINT64_C(62)) << 15;
4340
0
      Value |= (op & UINT64_C(1)) << 5;
4341
      // op: Rt32
4342
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4343
0
      op &= UINT64_C(31);
4344
0
      op <<= 8;
4345
0
      Value |= op;
4346
      // op: Rd32
4347
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4348
0
      op &= UINT64_C(31);
4349
0
      Value |= op;
4350
0
      break;
4351
0
    }
4352
0
    case Hexagon::V6_vS32b_srls_ai:
4353
0
    case Hexagon::V6_zLd_ai: {
4354
      // op: Ii
4355
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4356
0
      Value |= (op & UINT64_C(8)) << 10;
4357
0
      Value |= (op & UINT64_C(7)) << 8;
4358
      // op: Rt32
4359
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4360
0
      op &= UINT64_C(31);
4361
0
      op <<= 16;
4362
0
      Value |= op;
4363
0
      break;
4364
0
    }
4365
0
    case Hexagon::V6_vS32b_new_ai:
4366
0
    case Hexagon::V6_vS32b_nt_new_ai: {
4367
      // op: Ii
4368
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4369
0
      Value |= (op & UINT64_C(8)) << 10;
4370
0
      Value |= (op & UINT64_C(7)) << 8;
4371
      // op: Rt32
4372
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4373
0
      op &= UINT64_C(31);
4374
0
      op <<= 16;
4375
0
      Value |= op;
4376
      // op: Os8
4377
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4378
0
      op &= UINT64_C(7);
4379
0
      Value |= op;
4380
0
      break;
4381
0
    }
4382
0
    case Hexagon::V6_vS32Ub_ai:
4383
0
    case Hexagon::V6_vS32b_ai:
4384
0
    case Hexagon::V6_vS32b_nt_ai: {
4385
      // op: Ii
4386
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4387
0
      Value |= (op & UINT64_C(8)) << 10;
4388
0
      Value |= (op & UINT64_C(7)) << 8;
4389
      // op: Rt32
4390
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4391
0
      op &= UINT64_C(31);
4392
0
      op <<= 16;
4393
0
      Value |= op;
4394
      // op: Vs32
4395
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4396
0
      op &= UINT64_C(31);
4397
0
      Value |= op;
4398
0
      break;
4399
0
    }
4400
0
    case Hexagon::L2_loadrhgp:
4401
0
    case Hexagon::L2_loadruhgp:
4402
0
    case Hexagon::PS_loadrhabs:
4403
0
    case Hexagon::PS_loadruhabs: {
4404
      // op: Ii
4405
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4406
0
      Value |= (op & UINT64_C(98304)) << 10;
4407
0
      Value |= (op & UINT64_C(31744)) << 6;
4408
0
      Value |= (op & UINT64_C(1022)) << 4;
4409
      // op: Rd32
4410
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4411
0
      op &= UINT64_C(31);
4412
0
      Value |= op;
4413
0
      break;
4414
0
    }
4415
0
    case Hexagon::J2_callf:
4416
0
    case Hexagon::J2_callt:
4417
0
    case Hexagon::J2_jumpf:
4418
0
    case Hexagon::J2_jumpfnew:
4419
0
    case Hexagon::J2_jumpfnewpt:
4420
0
    case Hexagon::J2_jumpfpt:
4421
0
    case Hexagon::J2_jumpt:
4422
0
    case Hexagon::J2_jumptnew:
4423
0
    case Hexagon::J2_jumptnewpt:
4424
0
    case Hexagon::J2_jumptpt: {
4425
      // op: Ii
4426
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4427
0
      Value |= (op & UINT64_C(98304)) << 7;
4428
0
      Value |= (op & UINT64_C(31744)) << 6;
4429
0
      Value |= (op & UINT64_C(512)) << 4;
4430
0
      Value |= (op & UINT64_C(508)) >> 1;
4431
      // op: Pu4
4432
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4433
0
      op &= UINT64_C(3);
4434
0
      op <<= 8;
4435
0
      Value |= op;
4436
0
      break;
4437
0
    }
4438
0
    case Hexagon::V6_vwhist128qm: {
4439
      // op: Ii
4440
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4441
0
      op &= UINT64_C(1);
4442
0
      op <<= 8;
4443
0
      Value |= op;
4444
      // op: Qv4
4445
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4446
0
      op &= UINT64_C(3);
4447
0
      op <<= 22;
4448
0
      Value |= op;
4449
0
      break;
4450
0
    }
4451
0
    case Hexagon::SL2_loadri_sp: {
4452
      // op: Ii
4453
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4454
0
      op &= UINT64_C(124);
4455
0
      op <<= 2;
4456
0
      Value |= op;
4457
      // op: Rd16
4458
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4459
0
      op &= UINT64_C(15);
4460
0
      Value |= op;
4461
0
      break;
4462
0
    }
4463
0
    case Hexagon::S4_storeirh_io: {
4464
      // op: Ii
4465
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4466
0
      op &= UINT64_C(126);
4467
0
      op <<= 6;
4468
0
      Value |= op;
4469
      // op: II
4470
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4471
0
      Value |= (op & UINT64_C(128)) << 6;
4472
0
      Value |= (op & UINT64_C(127));
4473
      // op: Rs32
4474
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4475
0
      op &= UINT64_C(31);
4476
0
      op <<= 16;
4477
0
      Value |= op;
4478
0
      break;
4479
0
    }
4480
0
    case Hexagon::L4_iadd_memoph_io:
4481
0
    case Hexagon::L4_iand_memoph_io:
4482
0
    case Hexagon::L4_ior_memoph_io:
4483
0
    case Hexagon::L4_isub_memoph_io: {
4484
      // op: Ii
4485
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4486
0
      op &= UINT64_C(126);
4487
0
      op <<= 6;
4488
0
      Value |= op;
4489
      // op: II
4490
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4491
0
      op &= UINT64_C(31);
4492
0
      Value |= op;
4493
      // op: Rs32
4494
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4495
0
      op &= UINT64_C(31);
4496
0
      op <<= 16;
4497
0
      Value |= op;
4498
0
      break;
4499
0
    }
4500
0
    case Hexagon::L4_add_memoph_io:
4501
0
    case Hexagon::L4_and_memoph_io:
4502
0
    case Hexagon::L4_or_memoph_io:
4503
0
    case Hexagon::L4_sub_memoph_io: {
4504
      // op: Ii
4505
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4506
0
      op &= UINT64_C(126);
4507
0
      op <<= 6;
4508
0
      Value |= op;
4509
      // op: Rs32
4510
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4511
0
      op &= UINT64_C(31);
4512
0
      op <<= 16;
4513
0
      Value |= op;
4514
      // op: Rt32
4515
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4516
0
      op &= UINT64_C(31);
4517
0
      Value |= op;
4518
0
      break;
4519
0
    }
4520
0
    case Hexagon::SS2_storeh_io: {
4521
      // op: Ii
4522
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4523
0
      op &= UINT64_C(14);
4524
0
      op <<= 7;
4525
0
      Value |= op;
4526
      // op: Rs16
4527
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4528
0
      op &= UINT64_C(15);
4529
0
      op <<= 4;
4530
0
      Value |= op;
4531
      // op: Rt16
4532
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4533
0
      op &= UINT64_C(15);
4534
0
      Value |= op;
4535
0
      break;
4536
0
    }
4537
0
    case Hexagon::SS2_storebi0:
4538
0
    case Hexagon::SS2_storebi1: {
4539
      // op: Ii
4540
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4541
0
      op &= UINT64_C(15);
4542
0
      Value |= op;
4543
      // op: Rs16
4544
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4545
0
      op &= UINT64_C(15);
4546
0
      op <<= 4;
4547
0
      Value |= op;
4548
0
      break;
4549
0
    }
4550
0
    case Hexagon::SS1_storeb_io: {
4551
      // op: Ii
4552
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4553
0
      op &= UINT64_C(15);
4554
0
      op <<= 8;
4555
0
      Value |= op;
4556
      // op: Rs16
4557
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4558
0
      op &= UINT64_C(15);
4559
0
      op <<= 4;
4560
0
      Value |= op;
4561
      // op: Rt16
4562
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4563
0
      op &= UINT64_C(15);
4564
0
      Value |= op;
4565
0
      break;
4566
0
    }
4567
0
    case Hexagon::Y2_dcfetchbo: {
4568
      // op: Ii
4569
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4570
0
      op &= UINT64_C(16376);
4571
0
      op >>= 3;
4572
0
      Value |= op;
4573
      // op: Rs32
4574
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4575
0
      op &= UINT64_C(31);
4576
0
      op <<= 16;
4577
0
      Value |= op;
4578
0
      break;
4579
0
    }
4580
0
    case Hexagon::SL2_loadrd_sp: {
4581
      // op: Ii
4582
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4583
0
      op &= UINT64_C(248);
4584
0
      Value |= op;
4585
      // op: Rdd8
4586
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4587
0
      op &= UINT64_C(7);
4588
0
      Value |= op;
4589
0
      break;
4590
0
    }
4591
0
    case Hexagon::SA1_addsp: {
4592
      // op: Ii
4593
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4594
0
      op &= UINT64_C(252);
4595
0
      op <<= 2;
4596
0
      Value |= op;
4597
      // op: Rd16
4598
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4599
0
      op &= UINT64_C(15);
4600
0
      Value |= op;
4601
0
      break;
4602
0
    }
4603
0
    case Hexagon::S4_storeiri_io: {
4604
      // op: Ii
4605
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4606
0
      op &= UINT64_C(252);
4607
0
      op <<= 5;
4608
0
      Value |= op;
4609
      // op: II
4610
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4611
0
      Value |= (op & UINT64_C(128)) << 6;
4612
0
      Value |= (op & UINT64_C(127));
4613
      // op: Rs32
4614
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4615
0
      op &= UINT64_C(31);
4616
0
      op <<= 16;
4617
0
      Value |= op;
4618
0
      break;
4619
0
    }
4620
0
    case Hexagon::L4_iadd_memopw_io:
4621
0
    case Hexagon::L4_iand_memopw_io:
4622
0
    case Hexagon::L4_ior_memopw_io:
4623
0
    case Hexagon::L4_isub_memopw_io: {
4624
      // op: Ii
4625
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4626
0
      op &= UINT64_C(252);
4627
0
      op <<= 5;
4628
0
      Value |= op;
4629
      // op: II
4630
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4631
0
      op &= UINT64_C(31);
4632
0
      Value |= op;
4633
      // op: Rs32
4634
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4635
0
      op &= UINT64_C(31);
4636
0
      op <<= 16;
4637
0
      Value |= op;
4638
0
      break;
4639
0
    }
4640
0
    case Hexagon::L4_add_memopw_io:
4641
0
    case Hexagon::L4_and_memopw_io:
4642
0
    case Hexagon::L4_or_memopw_io:
4643
0
    case Hexagon::L4_sub_memopw_io: {
4644
      // op: Ii
4645
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4646
0
      op &= UINT64_C(252);
4647
0
      op <<= 5;
4648
0
      Value |= op;
4649
      // op: Rs32
4650
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4651
0
      op &= UINT64_C(31);
4652
0
      op <<= 16;
4653
0
      Value |= op;
4654
      // op: Rt32
4655
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4656
0
      op &= UINT64_C(31);
4657
0
      Value |= op;
4658
0
      break;
4659
0
    }
4660
0
    case Hexagon::A2_combineii: {
4661
      // op: Ii
4662
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4663
0
      op &= UINT64_C(255);
4664
0
      op <<= 5;
4665
0
      Value |= op;
4666
      // op: II
4667
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4668
0
      Value |= (op & UINT64_C(254)) << 15;
4669
0
      Value |= (op & UINT64_C(1)) << 13;
4670
      // op: Rdd32
4671
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4672
0
      op &= UINT64_C(31);
4673
0
      Value |= op;
4674
0
      break;
4675
0
    }
4676
0
    case Hexagon::A4_combineii: {
4677
      // op: Ii
4678
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4679
0
      op &= UINT64_C(255);
4680
0
      op <<= 5;
4681
0
      Value |= op;
4682
      // op: II
4683
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4684
0
      Value |= (op & UINT64_C(62)) << 15;
4685
0
      Value |= (op & UINT64_C(1)) << 13;
4686
      // op: Rdd32
4687
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4688
0
      op &= UINT64_C(31);
4689
0
      Value |= op;
4690
0
      break;
4691
0
    }
4692
0
    case Hexagon::A4_combineir: {
4693
      // op: Ii
4694
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4695
0
      op &= UINT64_C(255);
4696
0
      op <<= 5;
4697
0
      Value |= op;
4698
      // op: Rs32
4699
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4700
0
      op &= UINT64_C(31);
4701
0
      op <<= 16;
4702
0
      Value |= op;
4703
      // op: Rdd32
4704
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4705
0
      op &= UINT64_C(31);
4706
0
      Value |= op;
4707
0
      break;
4708
0
    }
4709
0
    case Hexagon::SA1_cmpeqi: {
4710
      // op: Ii
4711
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4712
0
      op &= UINT64_C(3);
4713
0
      Value |= op;
4714
      // op: Rs16
4715
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4716
0
      op &= UINT64_C(15);
4717
0
      op <<= 4;
4718
0
      Value |= op;
4719
0
      break;
4720
0
    }
4721
0
    case Hexagon::SA1_combine0i:
4722
0
    case Hexagon::SA1_combine1i:
4723
0
    case Hexagon::SA1_combine2i:
4724
0
    case Hexagon::SA1_combine3i: {
4725
      // op: Ii
4726
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4727
0
      op &= UINT64_C(3);
4728
0
      op <<= 5;
4729
0
      Value |= op;
4730
      // op: Rdd8
4731
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4732
0
      op &= UINT64_C(7);
4733
0
      Value |= op;
4734
0
      break;
4735
0
    }
4736
0
    case Hexagon::S2_mask: {
4737
      // op: Ii
4738
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4739
0
      op &= UINT64_C(31);
4740
0
      op <<= 8;
4741
0
      Value |= op;
4742
      // op: II
4743
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4744
0
      Value |= (op & UINT64_C(24)) << 18;
4745
0
      Value |= (op & UINT64_C(7)) << 5;
4746
      // op: Rd32
4747
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4748
0
      op &= UINT64_C(31);
4749
0
      Value |= op;
4750
0
      break;
4751
0
    }
4752
0
    case Hexagon::SS1_storew_io: {
4753
      // op: Ii
4754
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4755
0
      op &= UINT64_C(60);
4756
0
      op <<= 6;
4757
0
      Value |= op;
4758
      // op: Rs16
4759
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4760
0
      op &= UINT64_C(15);
4761
0
      op <<= 4;
4762
0
      Value |= op;
4763
      // op: Rt16
4764
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4765
0
      op &= UINT64_C(15);
4766
0
      Value |= op;
4767
0
      break;
4768
0
    }
4769
0
    case Hexagon::SS2_storewi0:
4770
0
    case Hexagon::SS2_storewi1: {
4771
      // op: Ii
4772
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4773
0
      op &= UINT64_C(60);
4774
0
      op >>= 2;
4775
0
      Value |= op;
4776
      // op: Rs16
4777
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4778
0
      op &= UINT64_C(15);
4779
0
      op <<= 4;
4780
0
      Value |= op;
4781
0
      break;
4782
0
    }
4783
0
    case Hexagon::SA1_seti: {
4784
      // op: Ii
4785
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4786
0
      op &= UINT64_C(63);
4787
0
      op <<= 4;
4788
0
      Value |= op;
4789
      // op: Rd16
4790
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4791
0
      op &= UINT64_C(15);
4792
0
      Value |= op;
4793
0
      break;
4794
0
    }
4795
0
    case Hexagon::S4_storeirb_io: {
4796
      // op: Ii
4797
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4798
0
      op &= UINT64_C(63);
4799
0
      op <<= 7;
4800
0
      Value |= op;
4801
      // op: II
4802
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4803
0
      Value |= (op & UINT64_C(128)) << 6;
4804
0
      Value |= (op & UINT64_C(127));
4805
      // op: Rs32
4806
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4807
0
      op &= UINT64_C(31);
4808
0
      op <<= 16;
4809
0
      Value |= op;
4810
0
      break;
4811
0
    }
4812
0
    case Hexagon::L4_iadd_memopb_io:
4813
0
    case Hexagon::L4_iand_memopb_io:
4814
0
    case Hexagon::L4_ior_memopb_io:
4815
0
    case Hexagon::L4_isub_memopb_io: {
4816
      // op: Ii
4817
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4818
0
      op &= UINT64_C(63);
4819
0
      op <<= 7;
4820
0
      Value |= op;
4821
      // op: II
4822
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4823
0
      op &= UINT64_C(31);
4824
0
      Value |= op;
4825
      // op: Rs32
4826
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4827
0
      op &= UINT64_C(31);
4828
0
      op <<= 16;
4829
0
      Value |= op;
4830
0
      break;
4831
0
    }
4832
0
    case Hexagon::C4_addipc: {
4833
      // op: Ii
4834
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4835
0
      op &= UINT64_C(63);
4836
0
      op <<= 7;
4837
0
      Value |= op;
4838
      // op: Rd32
4839
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4840
0
      op &= UINT64_C(31);
4841
0
      Value |= op;
4842
0
      break;
4843
0
    }
4844
0
    case Hexagon::L4_add_memopb_io:
4845
0
    case Hexagon::L4_and_memopb_io:
4846
0
    case Hexagon::L4_or_memopb_io:
4847
0
    case Hexagon::L4_sub_memopb_io: {
4848
      // op: Ii
4849
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4850
0
      op &= UINT64_C(63);
4851
0
      op <<= 7;
4852
0
      Value |= op;
4853
      // op: Rs32
4854
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4855
0
      op &= UINT64_C(31);
4856
0
      op <<= 16;
4857
0
      Value |= op;
4858
      // op: Rt32
4859
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4860
0
      op &= UINT64_C(31);
4861
0
      Value |= op;
4862
0
      break;
4863
0
    }
4864
0
    case Hexagon::L2_loadrd_io: {
4865
      // op: Ii
4866
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4867
0
      Value |= (op & UINT64_C(12288)) << 13;
4868
0
      Value |= (op & UINT64_C(4088)) << 2;
4869
      // op: Rs32
4870
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4871
0
      op &= UINT64_C(31);
4872
0
      op <<= 16;
4873
0
      Value |= op;
4874
      // op: Rdd32
4875
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4876
0
      op &= UINT64_C(31);
4877
0
      Value |= op;
4878
0
      break;
4879
0
    }
4880
0
    case Hexagon::S2_pstorerinewf_io:
4881
0
    case Hexagon::S2_pstorerinewt_io:
4882
0
    case Hexagon::S4_pstorerinewfnew_io:
4883
0
    case Hexagon::S4_pstorerinewtnew_io: {
4884
      // op: Ii
4885
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4886
0
      Value |= (op & UINT64_C(128)) << 6;
4887
0
      Value |= (op & UINT64_C(124)) << 1;
4888
      // op: Pv4
4889
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4890
0
      op &= UINT64_C(3);
4891
0
      Value |= op;
4892
      // op: Rs32
4893
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4894
0
      op &= UINT64_C(31);
4895
0
      op <<= 16;
4896
0
      Value |= op;
4897
      // op: Nt8
4898
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4899
0
      op &= UINT64_C(7);
4900
0
      op <<= 8;
4901
0
      Value |= op;
4902
0
      break;
4903
0
    }
4904
0
    case Hexagon::S2_pstorerif_io:
4905
0
    case Hexagon::S2_pstorerit_io:
4906
0
    case Hexagon::S4_pstorerifnew_io:
4907
0
    case Hexagon::S4_pstoreritnew_io: {
4908
      // op: Ii
4909
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4910
0
      Value |= (op & UINT64_C(128)) << 6;
4911
0
      Value |= (op & UINT64_C(124)) << 1;
4912
      // op: Pv4
4913
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4914
0
      op &= UINT64_C(3);
4915
0
      Value |= op;
4916
      // op: Rs32
4917
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4918
0
      op &= UINT64_C(31);
4919
0
      op <<= 16;
4920
0
      Value |= op;
4921
      // op: Rt32
4922
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4923
0
      op &= UINT64_C(31);
4924
0
      op <<= 8;
4925
0
      Value |= op;
4926
0
      break;
4927
0
    }
4928
0
    case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
4929
0
    case Hexagon::J4_cmpeqn1_f_jumpnv_t:
4930
0
    case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
4931
0
    case Hexagon::J4_cmpeqn1_t_jumpnv_t:
4932
0
    case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
4933
0
    case Hexagon::J4_cmpgtn1_f_jumpnv_t:
4934
0
    case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
4935
0
    case Hexagon::J4_cmpgtn1_t_jumpnv_t: {
4936
      // op: Ii
4937
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4938
0
      Value |= (op & UINT64_C(1536)) << 11;
4939
0
      Value |= (op & UINT64_C(508)) >> 1;
4940
      // op: Ns8
4941
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4942
0
      op &= UINT64_C(7);
4943
0
      op <<= 16;
4944
0
      Value |= op;
4945
0
      break;
4946
0
    }
4947
0
    case Hexagon::J4_cmpeq_f_jumpnv_nt:
4948
0
    case Hexagon::J4_cmpeq_f_jumpnv_t:
4949
0
    case Hexagon::J4_cmpeq_t_jumpnv_nt:
4950
0
    case Hexagon::J4_cmpeq_t_jumpnv_t:
4951
0
    case Hexagon::J4_cmpgt_f_jumpnv_nt:
4952
0
    case Hexagon::J4_cmpgt_f_jumpnv_t:
4953
0
    case Hexagon::J4_cmpgt_t_jumpnv_nt:
4954
0
    case Hexagon::J4_cmpgt_t_jumpnv_t:
4955
0
    case Hexagon::J4_cmpgtu_f_jumpnv_nt:
4956
0
    case Hexagon::J4_cmpgtu_f_jumpnv_t:
4957
0
    case Hexagon::J4_cmpgtu_t_jumpnv_nt:
4958
0
    case Hexagon::J4_cmpgtu_t_jumpnv_t: {
4959
      // op: Ii
4960
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4961
0
      Value |= (op & UINT64_C(1536)) << 11;
4962
0
      Value |= (op & UINT64_C(508)) >> 1;
4963
      // op: Ns8
4964
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4965
0
      op &= UINT64_C(7);
4966
0
      op <<= 16;
4967
0
      Value |= op;
4968
      // op: Rt32
4969
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4970
0
      op &= UINT64_C(31);
4971
0
      op <<= 8;
4972
0
      Value |= op;
4973
0
      break;
4974
0
    }
4975
0
    case Hexagon::J4_cmpeqn1_fp0_jump_nt:
4976
0
    case Hexagon::J4_cmpeqn1_fp0_jump_t:
4977
0
    case Hexagon::J4_cmpeqn1_fp1_jump_nt:
4978
0
    case Hexagon::J4_cmpeqn1_fp1_jump_t:
4979
0
    case Hexagon::J4_cmpeqn1_tp0_jump_nt:
4980
0
    case Hexagon::J4_cmpeqn1_tp0_jump_t:
4981
0
    case Hexagon::J4_cmpeqn1_tp1_jump_nt:
4982
0
    case Hexagon::J4_cmpeqn1_tp1_jump_t:
4983
0
    case Hexagon::J4_cmpgtn1_fp0_jump_nt:
4984
0
    case Hexagon::J4_cmpgtn1_fp0_jump_t:
4985
0
    case Hexagon::J4_cmpgtn1_fp1_jump_nt:
4986
0
    case Hexagon::J4_cmpgtn1_fp1_jump_t:
4987
0
    case Hexagon::J4_cmpgtn1_tp0_jump_nt:
4988
0
    case Hexagon::J4_cmpgtn1_tp0_jump_t:
4989
0
    case Hexagon::J4_cmpgtn1_tp1_jump_nt:
4990
0
    case Hexagon::J4_cmpgtn1_tp1_jump_t: {
4991
      // op: Ii
4992
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4993
0
      Value |= (op & UINT64_C(1536)) << 11;
4994
0
      Value |= (op & UINT64_C(508)) >> 1;
4995
      // op: Rs16
4996
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4997
0
      op &= UINT64_C(15);
4998
0
      op <<= 16;
4999
0
      Value |= op;
5000
0
      break;
5001
0
    }
5002
0
    case Hexagon::J4_cmpeq_fp0_jump_nt:
5003
0
    case Hexagon::J4_cmpeq_fp0_jump_t:
5004
0
    case Hexagon::J4_cmpeq_fp1_jump_nt:
5005
0
    case Hexagon::J4_cmpeq_fp1_jump_t:
5006
0
    case Hexagon::J4_cmpeq_tp0_jump_nt:
5007
0
    case Hexagon::J4_cmpeq_tp0_jump_t:
5008
0
    case Hexagon::J4_cmpeq_tp1_jump_nt:
5009
0
    case Hexagon::J4_cmpeq_tp1_jump_t:
5010
0
    case Hexagon::J4_cmpgt_fp0_jump_nt:
5011
0
    case Hexagon::J4_cmpgt_fp0_jump_t:
5012
0
    case Hexagon::J4_cmpgt_fp1_jump_nt:
5013
0
    case Hexagon::J4_cmpgt_fp1_jump_t:
5014
0
    case Hexagon::J4_cmpgt_tp0_jump_nt:
5015
0
    case Hexagon::J4_cmpgt_tp0_jump_t:
5016
0
    case Hexagon::J4_cmpgt_tp1_jump_nt:
5017
0
    case Hexagon::J4_cmpgt_tp1_jump_t:
5018
0
    case Hexagon::J4_cmpgtu_fp0_jump_nt:
5019
0
    case Hexagon::J4_cmpgtu_fp0_jump_t:
5020
0
    case Hexagon::J4_cmpgtu_fp1_jump_nt:
5021
0
    case Hexagon::J4_cmpgtu_fp1_jump_t:
5022
0
    case Hexagon::J4_cmpgtu_tp0_jump_nt:
5023
0
    case Hexagon::J4_cmpgtu_tp0_jump_t:
5024
0
    case Hexagon::J4_cmpgtu_tp1_jump_nt:
5025
0
    case Hexagon::J4_cmpgtu_tp1_jump_t: {
5026
      // op: Ii
5027
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5028
0
      Value |= (op & UINT64_C(1536)) << 11;
5029
0
      Value |= (op & UINT64_C(508)) >> 1;
5030
      // op: Rs16
5031
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5032
0
      op &= UINT64_C(15);
5033
0
      op <<= 16;
5034
0
      Value |= op;
5035
      // op: Rt16
5036
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5037
0
      op &= UINT64_C(15);
5038
0
      op <<= 8;
5039
0
      Value |= op;
5040
0
      break;
5041
0
    }
5042
0
    case Hexagon::J4_jumpsetr: {
5043
      // op: Ii
5044
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5045
0
      Value |= (op & UINT64_C(1536)) << 11;
5046
0
      Value |= (op & UINT64_C(508)) >> 1;
5047
      // op: Rs16
5048
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5049
0
      op &= UINT64_C(15);
5050
0
      op <<= 16;
5051
0
      Value |= op;
5052
      // op: Rd16
5053
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5054
0
      op &= UINT64_C(15);
5055
0
      op <<= 8;
5056
0
      Value |= op;
5057
0
      break;
5058
0
    }
5059
0
    case Hexagon::J4_cmplt_f_jumpnv_nt:
5060
0
    case Hexagon::J4_cmplt_f_jumpnv_t:
5061
0
    case Hexagon::J4_cmplt_t_jumpnv_nt:
5062
0
    case Hexagon::J4_cmplt_t_jumpnv_t:
5063
0
    case Hexagon::J4_cmpltu_f_jumpnv_nt:
5064
0
    case Hexagon::J4_cmpltu_f_jumpnv_t:
5065
0
    case Hexagon::J4_cmpltu_t_jumpnv_nt:
5066
0
    case Hexagon::J4_cmpltu_t_jumpnv_t: {
5067
      // op: Ii
5068
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5069
0
      Value |= (op & UINT64_C(1536)) << 11;
5070
0
      Value |= (op & UINT64_C(508)) >> 1;
5071
      // op: Rt32
5072
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5073
0
      op &= UINT64_C(31);
5074
0
      op <<= 8;
5075
0
      Value |= op;
5076
      // op: Ns8
5077
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5078
0
      op &= UINT64_C(7);
5079
0
      op <<= 16;
5080
0
      Value |= op;
5081
0
      break;
5082
0
    }
5083
0
    case Hexagon::L2_loadrb_io:
5084
0
    case Hexagon::L2_loadrub_io: {
5085
      // op: Ii
5086
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5087
0
      Value |= (op & UINT64_C(1536)) << 16;
5088
0
      Value |= (op & UINT64_C(511)) << 5;
5089
      // op: Rs32
5090
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5091
0
      op &= UINT64_C(31);
5092
0
      op <<= 16;
5093
0
      Value |= op;
5094
      // op: Rd32
5095
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5096
0
      op &= UINT64_C(31);
5097
0
      Value |= op;
5098
0
      break;
5099
0
    }
5100
0
    case Hexagon::M4_mpyri_addr_u2: {
5101
      // op: Ii
5102
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5103
0
      Value |= (op & UINT64_C(192)) << 15;
5104
0
      Value |= (op & UINT64_C(32)) << 8;
5105
0
      Value |= (op & UINT64_C(28)) << 3;
5106
      // op: Ru32
5107
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5108
0
      op &= UINT64_C(31);
5109
0
      Value |= op;
5110
      // op: Rs32
5111
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5112
0
      op &= UINT64_C(31);
5113
0
      op <<= 16;
5114
0
      Value |= op;
5115
      // op: Rd32
5116
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5117
0
      op &= UINT64_C(31);
5118
0
      op <<= 8;
5119
0
      Value |= op;
5120
0
      break;
5121
0
    }
5122
0
    case Hexagon::L4_loadbsw2_ur:
5123
0
    case Hexagon::L4_loadbzw2_ur:
5124
0
    case Hexagon::L4_loadrb_ur:
5125
0
    case Hexagon::L4_loadrh_ur:
5126
0
    case Hexagon::L4_loadri_ur:
5127
0
    case Hexagon::L4_loadrub_ur:
5128
0
    case Hexagon::L4_loadruh_ur: {
5129
      // op: Ii
5130
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5131
0
      Value |= (op & UINT64_C(2)) << 12;
5132
0
      Value |= (op & UINT64_C(1)) << 7;
5133
      // op: II
5134
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5135
0
      Value |= (op & UINT64_C(60)) << 6;
5136
0
      Value |= (op & UINT64_C(3)) << 5;
5137
      // op: Rt32
5138
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5139
0
      op &= UINT64_C(31);
5140
0
      op <<= 16;
5141
0
      Value |= op;
5142
      // op: Rd32
5143
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5144
0
      op &= UINT64_C(31);
5145
0
      Value |= op;
5146
0
      break;
5147
0
    }
5148
0
    case Hexagon::L4_loadbsw4_ur:
5149
0
    case Hexagon::L4_loadbzw4_ur:
5150
0
    case Hexagon::L4_loadrd_ur: {
5151
      // op: Ii
5152
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5153
0
      Value |= (op & UINT64_C(2)) << 12;
5154
0
      Value |= (op & UINT64_C(1)) << 7;
5155
      // op: II
5156
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5157
0
      Value |= (op & UINT64_C(60)) << 6;
5158
0
      Value |= (op & UINT64_C(3)) << 5;
5159
      // op: Rt32
5160
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5161
0
      op &= UINT64_C(31);
5162
0
      op <<= 16;
5163
0
      Value |= op;
5164
      // op: Rdd32
5165
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5166
0
      op &= UINT64_C(31);
5167
0
      Value |= op;
5168
0
      break;
5169
0
    }
5170
0
    case Hexagon::S4_storerbnew_rr:
5171
0
    case Hexagon::S4_storerhnew_rr:
5172
0
    case Hexagon::S4_storerinew_rr: {
5173
      // op: Ii
5174
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5175
0
      Value |= (op & UINT64_C(2)) << 12;
5176
0
      Value |= (op & UINT64_C(1)) << 7;
5177
      // op: Rs32
5178
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5179
0
      op &= UINT64_C(31);
5180
0
      op <<= 16;
5181
0
      Value |= op;
5182
      // op: Ru32
5183
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5184
0
      op &= UINT64_C(31);
5185
0
      op <<= 8;
5186
0
      Value |= op;
5187
      // op: Nt8
5188
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5189
0
      op &= UINT64_C(7);
5190
0
      Value |= op;
5191
0
      break;
5192
0
    }
5193
0
    case Hexagon::S4_storerb_rr:
5194
0
    case Hexagon::S4_storerf_rr:
5195
0
    case Hexagon::S4_storerh_rr:
5196
0
    case Hexagon::S4_storeri_rr: {
5197
      // op: Ii
5198
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5199
0
      Value |= (op & UINT64_C(2)) << 12;
5200
0
      Value |= (op & UINT64_C(1)) << 7;
5201
      // op: Rs32
5202
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5203
0
      op &= UINT64_C(31);
5204
0
      op <<= 16;
5205
0
      Value |= op;
5206
      // op: Ru32
5207
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5208
0
      op &= UINT64_C(31);
5209
0
      op <<= 8;
5210
0
      Value |= op;
5211
      // op: Rt32
5212
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5213
0
      op &= UINT64_C(31);
5214
0
      Value |= op;
5215
0
      break;
5216
0
    }
5217
0
    case Hexagon::S4_storerd_rr: {
5218
      // op: Ii
5219
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5220
0
      Value |= (op & UINT64_C(2)) << 12;
5221
0
      Value |= (op & UINT64_C(1)) << 7;
5222
      // op: Rs32
5223
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5224
0
      op &= UINT64_C(31);
5225
0
      op <<= 16;
5226
0
      Value |= op;
5227
      // op: Ru32
5228
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5229
0
      op &= UINT64_C(31);
5230
0
      op <<= 8;
5231
0
      Value |= op;
5232
      // op: Rtt32
5233
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5234
0
      op &= UINT64_C(31);
5235
0
      Value |= op;
5236
0
      break;
5237
0
    }
5238
0
    case Hexagon::J2_trap1: {
5239
      // op: Ii
5240
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5241
0
      Value |= (op & UINT64_C(248)) << 5;
5242
0
      Value |= (op & UINT64_C(7)) << 2;
5243
      // op: Rx32
5244
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5245
0
      op &= UINT64_C(31);
5246
0
      op <<= 16;
5247
0
      Value |= op;
5248
0
      break;
5249
0
    }
5250
0
    case Hexagon::S2_pstorerdf_io:
5251
0
    case Hexagon::S2_pstorerdt_io:
5252
0
    case Hexagon::S4_pstorerdfnew_io:
5253
0
    case Hexagon::S4_pstorerdtnew_io: {
5254
      // op: Ii
5255
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5256
0
      Value |= (op & UINT64_C(256)) << 5;
5257
0
      Value |= (op & UINT64_C(248));
5258
      // op: Pv4
5259
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5260
0
      op &= UINT64_C(3);
5261
0
      Value |= op;
5262
      // op: Rs32
5263
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5264
0
      op &= UINT64_C(31);
5265
0
      op <<= 16;
5266
0
      Value |= op;
5267
      // op: Rtt32
5268
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5269
0
      op &= UINT64_C(31);
5270
0
      op <<= 8;
5271
0
      Value |= op;
5272
0
      break;
5273
0
    }
5274
0
    case Hexagon::L2_loadbsw2_io:
5275
0
    case Hexagon::L2_loadbzw2_io:
5276
0
    case Hexagon::L2_loadrh_io:
5277
0
    case Hexagon::L2_loadruh_io: {
5278
      // op: Ii
5279
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5280
0
      Value |= (op & UINT64_C(3072)) << 15;
5281
0
      Value |= (op & UINT64_C(1022)) << 4;
5282
      // op: Rs32
5283
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5284
0
      op &= UINT64_C(31);
5285
0
      op <<= 16;
5286
0
      Value |= op;
5287
      // op: Rd32
5288
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5289
0
      op &= UINT64_C(31);
5290
0
      Value |= op;
5291
0
      break;
5292
0
    }
5293
0
    case Hexagon::S2_pstorerbnewf_io:
5294
0
    case Hexagon::S2_pstorerbnewt_io:
5295
0
    case Hexagon::S4_pstorerbnewfnew_io:
5296
0
    case Hexagon::S4_pstorerbnewtnew_io: {
5297
      // op: Ii
5298
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5299
0
      Value |= (op & UINT64_C(32)) << 8;
5300
0
      Value |= (op & UINT64_C(31)) << 3;
5301
      // op: Pv4
5302
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5303
0
      op &= UINT64_C(3);
5304
0
      Value |= op;
5305
      // op: Rs32
5306
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5307
0
      op &= UINT64_C(31);
5308
0
      op <<= 16;
5309
0
      Value |= op;
5310
      // op: Nt8
5311
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5312
0
      op &= UINT64_C(7);
5313
0
      op <<= 8;
5314
0
      Value |= op;
5315
0
      break;
5316
0
    }
5317
0
    case Hexagon::S2_pstorerbf_io:
5318
0
    case Hexagon::S2_pstorerbt_io:
5319
0
    case Hexagon::S4_pstorerbfnew_io:
5320
0
    case Hexagon::S4_pstorerbtnew_io: {
5321
      // op: Ii
5322
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5323
0
      Value |= (op & UINT64_C(32)) << 8;
5324
0
      Value |= (op & UINT64_C(31)) << 3;
5325
      // op: Pv4
5326
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5327
0
      op &= UINT64_C(3);
5328
0
      Value |= op;
5329
      // op: Rs32
5330
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5331
0
      op &= UINT64_C(31);
5332
0
      op <<= 16;
5333
0
      Value |= op;
5334
      // op: Rt32
5335
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5336
0
      op &= UINT64_C(31);
5337
0
      op <<= 8;
5338
0
      Value |= op;
5339
0
      break;
5340
0
    }
5341
0
    case Hexagon::C2_cmoveif:
5342
0
    case Hexagon::C2_cmoveit:
5343
0
    case Hexagon::C2_cmovenewif:
5344
0
    case Hexagon::C2_cmovenewit: {
5345
      // op: Ii
5346
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5347
0
      Value |= (op & UINT64_C(3840)) << 8;
5348
0
      Value |= (op & UINT64_C(255)) << 5;
5349
      // op: Pu4
5350
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5351
0
      op &= UINT64_C(3);
5352
0
      op <<= 21;
5353
0
      Value |= op;
5354
      // op: Rd32
5355
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5356
0
      op &= UINT64_C(31);
5357
0
      Value |= op;
5358
0
      break;
5359
0
    }
5360
0
    case Hexagon::S4_subaddi: {
5361
      // op: Ii
5362
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5363
0
      Value |= (op & UINT64_C(48)) << 17;
5364
0
      Value |= (op & UINT64_C(8)) << 10;
5365
0
      Value |= (op & UINT64_C(7)) << 5;
5366
      // op: Rs32
5367
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5368
0
      op &= UINT64_C(31);
5369
0
      op <<= 16;
5370
0
      Value |= op;
5371
      // op: Ru32
5372
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5373
0
      op &= UINT64_C(31);
5374
0
      Value |= op;
5375
      // op: Rd32
5376
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5377
0
      op &= UINT64_C(31);
5378
0
      op <<= 8;
5379
0
      Value |= op;
5380
0
      break;
5381
0
    }
5382
0
    case Hexagon::A2_tfrih:
5383
0
    case Hexagon::A2_tfril: {
5384
      // op: Ii
5385
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5386
0
      Value |= (op & UINT64_C(49152)) << 8;
5387
0
      Value |= (op & UINT64_C(16383));
5388
      // op: Rx32
5389
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5390
0
      op &= UINT64_C(31);
5391
0
      op <<= 16;
5392
0
      Value |= op;
5393
0
      break;
5394
0
    }
5395
0
    case Hexagon::C2_cmpeqi:
5396
0
    case Hexagon::C2_cmpgti:
5397
0
    case Hexagon::C4_cmpltei:
5398
0
    case Hexagon::C4_cmpneqi: {
5399
      // op: Ii
5400
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5401
0
      Value |= (op & UINT64_C(512)) << 12;
5402
0
      Value |= (op & UINT64_C(511)) << 5;
5403
      // op: Rs32
5404
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5405
0
      op &= UINT64_C(31);
5406
0
      op <<= 16;
5407
0
      Value |= op;
5408
      // op: Pd4
5409
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5410
0
      op &= UINT64_C(3);
5411
0
      Value |= op;
5412
0
      break;
5413
0
    }
5414
0
    case Hexagon::A2_andir:
5415
0
    case Hexagon::A2_orir: {
5416
      // op: Ii
5417
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5418
0
      Value |= (op & UINT64_C(512)) << 12;
5419
0
      Value |= (op & UINT64_C(511)) << 5;
5420
      // op: Rs32
5421
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5422
0
      op &= UINT64_C(31);
5423
0
      op <<= 16;
5424
0
      Value |= op;
5425
      // op: Rd32
5426
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5427
0
      op &= UINT64_C(31);
5428
0
      Value |= op;
5429
0
      break;
5430
0
    }
5431
0
    case Hexagon::L2_loadri_io: {
5432
      // op: Ii
5433
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5434
0
      Value |= (op & UINT64_C(6144)) << 14;
5435
0
      Value |= (op & UINT64_C(2044)) << 3;
5436
      // op: Rs32
5437
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5438
0
      op &= UINT64_C(31);
5439
0
      op <<= 16;
5440
0
      Value |= op;
5441
      // op: Rd32
5442
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5443
0
      op &= UINT64_C(31);
5444
0
      Value |= op;
5445
0
      break;
5446
0
    }
5447
0
    case Hexagon::L2_loadbsw4_io:
5448
0
    case Hexagon::L2_loadbzw4_io: {
5449
      // op: Ii
5450
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5451
0
      Value |= (op & UINT64_C(6144)) << 14;
5452
0
      Value |= (op & UINT64_C(2044)) << 3;
5453
      // op: Rs32
5454
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5455
0
      op &= UINT64_C(31);
5456
0
      op <<= 16;
5457
0
      Value |= op;
5458
      // op: Rdd32
5459
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5460
0
      op &= UINT64_C(31);
5461
0
      Value |= op;
5462
0
      break;
5463
0
    }
5464
0
    case Hexagon::L4_ploadrbf_abs:
5465
0
    case Hexagon::L4_ploadrbfnew_abs:
5466
0
    case Hexagon::L4_ploadrbt_abs:
5467
0
    case Hexagon::L4_ploadrbtnew_abs:
5468
0
    case Hexagon::L4_ploadrhf_abs:
5469
0
    case Hexagon::L4_ploadrhfnew_abs:
5470
0
    case Hexagon::L4_ploadrht_abs:
5471
0
    case Hexagon::L4_ploadrhtnew_abs:
5472
0
    case Hexagon::L4_ploadrif_abs:
5473
0
    case Hexagon::L4_ploadrifnew_abs:
5474
0
    case Hexagon::L4_ploadrit_abs:
5475
0
    case Hexagon::L4_ploadritnew_abs:
5476
0
    case Hexagon::L4_ploadrubf_abs:
5477
0
    case Hexagon::L4_ploadrubfnew_abs:
5478
0
    case Hexagon::L4_ploadrubt_abs:
5479
0
    case Hexagon::L4_ploadrubtnew_abs:
5480
0
    case Hexagon::L4_ploadruhf_abs:
5481
0
    case Hexagon::L4_ploadruhfnew_abs:
5482
0
    case Hexagon::L4_ploadruht_abs:
5483
0
    case Hexagon::L4_ploadruhtnew_abs: {
5484
      // op: Ii
5485
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5486
0
      Value |= (op & UINT64_C(62)) << 15;
5487
0
      Value |= (op & UINT64_C(1)) << 8;
5488
      // op: Pt4
5489
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5490
0
      op &= UINT64_C(3);
5491
0
      op <<= 9;
5492
0
      Value |= op;
5493
      // op: Rd32
5494
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5495
0
      op &= UINT64_C(31);
5496
0
      Value |= op;
5497
0
      break;
5498
0
    }
5499
0
    case Hexagon::L4_ploadrdf_abs:
5500
0
    case Hexagon::L4_ploadrdfnew_abs:
5501
0
    case Hexagon::L4_ploadrdt_abs:
5502
0
    case Hexagon::L4_ploadrdtnew_abs: {
5503
      // op: Ii
5504
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5505
0
      Value |= (op & UINT64_C(62)) << 15;
5506
0
      Value |= (op & UINT64_C(1)) << 8;
5507
      // op: Pt4
5508
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5509
0
      op &= UINT64_C(3);
5510
0
      op <<= 9;
5511
0
      Value |= op;
5512
      // op: Rdd32
5513
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5514
0
      op &= UINT64_C(31);
5515
0
      Value |= op;
5516
0
      break;
5517
0
    }
5518
0
    case Hexagon::S2_pstorerhnewf_io:
5519
0
    case Hexagon::S2_pstorerhnewt_io:
5520
0
    case Hexagon::S4_pstorerhnewfnew_io:
5521
0
    case Hexagon::S4_pstorerhnewtnew_io: {
5522
      // op: Ii
5523
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5524
0
      Value |= (op & UINT64_C(64)) << 7;
5525
0
      Value |= (op & UINT64_C(62)) << 2;
5526
      // op: Pv4
5527
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5528
0
      op &= UINT64_C(3);
5529
0
      Value |= op;
5530
      // op: Rs32
5531
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5532
0
      op &= UINT64_C(31);
5533
0
      op <<= 16;
5534
0
      Value |= op;
5535
      // op: Nt8
5536
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5537
0
      op &= UINT64_C(7);
5538
0
      op <<= 8;
5539
0
      Value |= op;
5540
0
      break;
5541
0
    }
5542
0
    case Hexagon::S2_pstorerff_io:
5543
0
    case Hexagon::S2_pstorerft_io:
5544
0
    case Hexagon::S2_pstorerhf_io:
5545
0
    case Hexagon::S2_pstorerht_io:
5546
0
    case Hexagon::S4_pstorerffnew_io:
5547
0
    case Hexagon::S4_pstorerftnew_io:
5548
0
    case Hexagon::S4_pstorerhfnew_io:
5549
0
    case Hexagon::S4_pstorerhtnew_io: {
5550
      // op: Ii
5551
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5552
0
      Value |= (op & UINT64_C(64)) << 7;
5553
0
      Value |= (op & UINT64_C(62)) << 2;
5554
      // op: Pv4
5555
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5556
0
      op &= UINT64_C(3);
5557
0
      Value |= op;
5558
      // op: Rs32
5559
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5560
0
      op &= UINT64_C(31);
5561
0
      op <<= 16;
5562
0
      Value |= op;
5563
      // op: Rt32
5564
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5565
0
      op &= UINT64_C(31);
5566
0
      op <<= 8;
5567
0
      Value |= op;
5568
0
      break;
5569
0
    }
5570
0
    case Hexagon::A2_addi: {
5571
      // op: Ii
5572
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5573
0
      Value |= (op & UINT64_C(65024)) << 12;
5574
0
      Value |= (op & UINT64_C(511)) << 5;
5575
      // op: Rs32
5576
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5577
0
      op &= UINT64_C(31);
5578
0
      op <<= 16;
5579
0
      Value |= op;
5580
      // op: Rd32
5581
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5582
0
      op &= UINT64_C(31);
5583
0
      Value |= op;
5584
0
      break;
5585
0
    }
5586
0
    case Hexagon::V6_zLd_pred_ai: {
5587
      // op: Ii
5588
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5589
0
      Value |= (op & UINT64_C(8)) << 10;
5590
0
      Value |= (op & UINT64_C(7)) << 8;
5591
      // op: Pv4
5592
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5593
0
      op &= UINT64_C(3);
5594
0
      op <<= 11;
5595
0
      Value |= op;
5596
      // op: Rt32
5597
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5598
0
      op &= UINT64_C(31);
5599
0
      op <<= 16;
5600
0
      Value |= op;
5601
0
      break;
5602
0
    }
5603
0
    case Hexagon::V6_vS32b_new_npred_ai:
5604
0
    case Hexagon::V6_vS32b_new_pred_ai:
5605
0
    case Hexagon::V6_vS32b_nt_new_npred_ai:
5606
0
    case Hexagon::V6_vS32b_nt_new_pred_ai: {
5607
      // op: Ii
5608
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5609
0
      Value |= (op & UINT64_C(8)) << 10;
5610
0
      Value |= (op & UINT64_C(7)) << 8;
5611
      // op: Pv4
5612
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5613
0
      op &= UINT64_C(3);
5614
0
      op <<= 11;
5615
0
      Value |= op;
5616
      // op: Rt32
5617
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5618
0
      op &= UINT64_C(31);
5619
0
      op <<= 16;
5620
0
      Value |= op;
5621
      // op: Os8
5622
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5623
0
      op &= UINT64_C(7);
5624
0
      Value |= op;
5625
0
      break;
5626
0
    }
5627
0
    case Hexagon::V6_vS32Ub_npred_ai:
5628
0
    case Hexagon::V6_vS32Ub_pred_ai:
5629
0
    case Hexagon::V6_vS32b_npred_ai:
5630
0
    case Hexagon::V6_vS32b_nt_npred_ai:
5631
0
    case Hexagon::V6_vS32b_nt_pred_ai:
5632
0
    case Hexagon::V6_vS32b_pred_ai: {
5633
      // op: Ii
5634
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5635
0
      Value |= (op & UINT64_C(8)) << 10;
5636
0
      Value |= (op & UINT64_C(7)) << 8;
5637
      // op: Pv4
5638
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5639
0
      op &= UINT64_C(3);
5640
0
      op <<= 11;
5641
0
      Value |= op;
5642
      // op: Rt32
5643
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5644
0
      op &= UINT64_C(31);
5645
0
      op <<= 16;
5646
0
      Value |= op;
5647
      // op: Vs32
5648
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5649
0
      op &= UINT64_C(31);
5650
0
      Value |= op;
5651
0
      break;
5652
0
    }
5653
0
    case Hexagon::V6_vS32b_nqpred_ai:
5654
0
    case Hexagon::V6_vS32b_nt_nqpred_ai:
5655
0
    case Hexagon::V6_vS32b_nt_qpred_ai:
5656
0
    case Hexagon::V6_vS32b_qpred_ai: {
5657
      // op: Ii
5658
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5659
0
      Value |= (op & UINT64_C(8)) << 10;
5660
0
      Value |= (op & UINT64_C(7)) << 8;
5661
      // op: Qv4
5662
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5663
0
      op &= UINT64_C(3);
5664
0
      op <<= 11;
5665
0
      Value |= op;
5666
      // op: Rt32
5667
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5668
0
      op &= UINT64_C(31);
5669
0
      op <<= 16;
5670
0
      Value |= op;
5671
      // op: Vs32
5672
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5673
0
      op &= UINT64_C(31);
5674
0
      Value |= op;
5675
0
      break;
5676
0
    }
5677
0
    case Hexagon::V6_vL32Ub_ai:
5678
0
    case Hexagon::V6_vL32b_ai:
5679
0
    case Hexagon::V6_vL32b_cur_ai:
5680
0
    case Hexagon::V6_vL32b_nt_ai:
5681
0
    case Hexagon::V6_vL32b_nt_cur_ai:
5682
0
    case Hexagon::V6_vL32b_nt_tmp_ai:
5683
0
    case Hexagon::V6_vL32b_tmp_ai: {
5684
      // op: Ii
5685
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5686
0
      Value |= (op & UINT64_C(8)) << 10;
5687
0
      Value |= (op & UINT64_C(7)) << 8;
5688
      // op: Rt32
5689
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5690
0
      op &= UINT64_C(31);
5691
0
      op <<= 16;
5692
0
      Value |= op;
5693
      // op: Vd32
5694
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5695
0
      op &= UINT64_C(31);
5696
0
      Value |= op;
5697
0
      break;
5698
0
    }
5699
0
    case Hexagon::S2_storerd_pci: {
5700
      // op: Ii
5701
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5702
0
      op &= UINT64_C(120);
5703
0
      Value |= op;
5704
      // op: Mu2
5705
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5706
0
      op &= UINT64_C(1);
5707
0
      op <<= 13;
5708
0
      Value |= op;
5709
      // op: Rtt32
5710
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
5711
0
      op &= UINT64_C(31);
5712
0
      op <<= 8;
5713
0
      Value |= op;
5714
      // op: Rx32
5715
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5716
0
      op &= UINT64_C(31);
5717
0
      op <<= 16;
5718
0
      Value |= op;
5719
0
      break;
5720
0
    }
5721
0
    case Hexagon::S2_storerd_pi: {
5722
      // op: Ii
5723
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5724
0
      op &= UINT64_C(120);
5725
0
      Value |= op;
5726
      // op: Rtt32
5727
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5728
0
      op &= UINT64_C(31);
5729
0
      op <<= 8;
5730
0
      Value |= op;
5731
      // op: Rx32
5732
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5733
0
      op &= UINT64_C(31);
5734
0
      op <<= 16;
5735
0
      Value |= op;
5736
0
      break;
5737
0
    }
5738
0
    case Hexagon::S4_storeirhf_io:
5739
0
    case Hexagon::S4_storeirhfnew_io:
5740
0
    case Hexagon::S4_storeirht_io:
5741
0
    case Hexagon::S4_storeirhtnew_io: {
5742
      // op: Ii
5743
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5744
0
      op &= UINT64_C(126);
5745
0
      op <<= 6;
5746
0
      Value |= op;
5747
      // op: II
5748
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5749
0
      Value |= (op & UINT64_C(32)) << 8;
5750
0
      Value |= (op & UINT64_C(31));
5751
      // op: Pv4
5752
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5753
0
      op &= UINT64_C(3);
5754
0
      op <<= 5;
5755
0
      Value |= op;
5756
      // op: Rs32
5757
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5758
0
      op &= UINT64_C(31);
5759
0
      op <<= 16;
5760
0
      Value |= op;
5761
0
      break;
5762
0
    }
5763
0
    case Hexagon::SA1_addi: {
5764
      // op: Ii
5765
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5766
0
      op &= UINT64_C(127);
5767
0
      op <<= 4;
5768
0
      Value |= op;
5769
      // op: Rx16
5770
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5771
0
      op &= UINT64_C(15);
5772
0
      Value |= op;
5773
0
      break;
5774
0
    }
5775
0
    case Hexagon::A4_cmpbgtui:
5776
0
    case Hexagon::A4_cmphgtui: {
5777
      // op: Ii
5778
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5779
0
      op &= UINT64_C(127);
5780
0
      op <<= 5;
5781
0
      Value |= op;
5782
      // op: Rs32
5783
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5784
0
      op &= UINT64_C(31);
5785
0
      op <<= 16;
5786
0
      Value |= op;
5787
      // op: Pd4
5788
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5789
0
      op &= UINT64_C(3);
5790
0
      Value |= op;
5791
0
      break;
5792
0
    }
5793
0
    case Hexagon::A4_vcmpbgtui:
5794
0
    case Hexagon::A4_vcmphgtui:
5795
0
    case Hexagon::A4_vcmpwgtui: {
5796
      // op: Ii
5797
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5798
0
      op &= UINT64_C(127);
5799
0
      op <<= 5;
5800
0
      Value |= op;
5801
      // op: Rss32
5802
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5803
0
      op &= UINT64_C(31);
5804
0
      op <<= 16;
5805
0
      Value |= op;
5806
      // op: Pd4
5807
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5808
0
      op &= UINT64_C(3);
5809
0
      Value |= op;
5810
0
      break;
5811
0
    }
5812
0
    case Hexagon::SL2_loadrh_io:
5813
0
    case Hexagon::SL2_loadruh_io: {
5814
      // op: Ii
5815
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5816
0
      op &= UINT64_C(14);
5817
0
      op <<= 7;
5818
0
      Value |= op;
5819
      // op: Rs16
5820
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5821
0
      op &= UINT64_C(15);
5822
0
      op <<= 4;
5823
0
      Value |= op;
5824
      // op: Rd16
5825
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5826
0
      op &= UINT64_C(15);
5827
0
      Value |= op;
5828
0
      break;
5829
0
    }
5830
0
    case Hexagon::S2_storerbnew_pci: {
5831
      // op: Ii
5832
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5833
0
      op &= UINT64_C(15);
5834
0
      op <<= 3;
5835
0
      Value |= op;
5836
      // op: Mu2
5837
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5838
0
      op &= UINT64_C(1);
5839
0
      op <<= 13;
5840
0
      Value |= op;
5841
      // op: Nt8
5842
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
5843
0
      op &= UINT64_C(7);
5844
0
      op <<= 8;
5845
0
      Value |= op;
5846
      // op: Rx32
5847
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5848
0
      op &= UINT64_C(31);
5849
0
      op <<= 16;
5850
0
      Value |= op;
5851
0
      break;
5852
0
    }
5853
0
    case Hexagon::S2_storerb_pci: {
5854
      // op: Ii
5855
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5856
0
      op &= UINT64_C(15);
5857
0
      op <<= 3;
5858
0
      Value |= op;
5859
      // op: Mu2
5860
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5861
0
      op &= UINT64_C(1);
5862
0
      op <<= 13;
5863
0
      Value |= op;
5864
      // op: Rt32
5865
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
5866
0
      op &= UINT64_C(31);
5867
0
      op <<= 8;
5868
0
      Value |= op;
5869
      // op: Rx32
5870
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5871
0
      op &= UINT64_C(31);
5872
0
      op <<= 16;
5873
0
      Value |= op;
5874
0
      break;
5875
0
    }
5876
0
    case Hexagon::S2_storerbnew_pi: {
5877
      // op: Ii
5878
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5879
0
      op &= UINT64_C(15);
5880
0
      op <<= 3;
5881
0
      Value |= op;
5882
      // op: Nt8
5883
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5884
0
      op &= UINT64_C(7);
5885
0
      op <<= 8;
5886
0
      Value |= op;
5887
      // op: Rx32
5888
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5889
0
      op &= UINT64_C(31);
5890
0
      op <<= 16;
5891
0
      Value |= op;
5892
0
      break;
5893
0
    }
5894
0
    case Hexagon::S2_storerb_pi: {
5895
      // op: Ii
5896
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5897
0
      op &= UINT64_C(15);
5898
0
      op <<= 3;
5899
0
      Value |= op;
5900
      // op: Rt32
5901
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5902
0
      op &= UINT64_C(31);
5903
0
      op <<= 8;
5904
0
      Value |= op;
5905
      // op: Rx32
5906
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5907
0
      op &= UINT64_C(31);
5908
0
      op <<= 16;
5909
0
      Value |= op;
5910
0
      break;
5911
0
    }
5912
0
    case Hexagon::SL1_loadrub_io: {
5913
      // op: Ii
5914
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5915
0
      op &= UINT64_C(15);
5916
0
      op <<= 8;
5917
0
      Value |= op;
5918
      // op: Rs16
5919
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5920
0
      op &= UINT64_C(15);
5921
0
      op <<= 4;
5922
0
      Value |= op;
5923
      // op: Rd16
5924
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5925
0
      op &= UINT64_C(15);
5926
0
      Value |= op;
5927
0
      break;
5928
0
    }
5929
0
    case Hexagon::S5_asrhub_rnd_sat:
5930
0
    case Hexagon::S5_asrhub_sat: {
5931
      // op: Ii
5932
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5933
0
      op &= UINT64_C(15);
5934
0
      op <<= 8;
5935
0
      Value |= op;
5936
      // op: Rss32
5937
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5938
0
      op &= UINT64_C(31);
5939
0
      op <<= 16;
5940
0
      Value |= op;
5941
      // op: Rd32
5942
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5943
0
      op &= UINT64_C(31);
5944
0
      Value |= op;
5945
0
      break;
5946
0
    }
5947
0
    case Hexagon::S2_asl_i_vh:
5948
0
    case Hexagon::S2_asr_i_vh:
5949
0
    case Hexagon::S2_lsr_i_vh:
5950
0
    case Hexagon::S5_vasrhrnd: {
5951
      // op: Ii
5952
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5953
0
      op &= UINT64_C(15);
5954
0
      op <<= 8;
5955
0
      Value |= op;
5956
      // op: Rss32
5957
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5958
0
      op &= UINT64_C(31);
5959
0
      op <<= 16;
5960
0
      Value |= op;
5961
      // op: Rdd32
5962
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5963
0
      op &= UINT64_C(31);
5964
0
      Value |= op;
5965
0
      break;
5966
0
    }
5967
0
    case Hexagon::S2_allocframe: {
5968
      // op: Ii
5969
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5970
0
      op &= UINT64_C(16376);
5971
0
      op >>= 3;
5972
0
      Value |= op;
5973
      // op: Rx32
5974
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5975
0
      op &= UINT64_C(31);
5976
0
      op <<= 16;
5977
0
      Value |= op;
5978
0
      break;
5979
0
    }
5980
0
    case Hexagon::S4_storeirif_io:
5981
0
    case Hexagon::S4_storeirifnew_io:
5982
0
    case Hexagon::S4_storeirit_io:
5983
0
    case Hexagon::S4_storeiritnew_io: {
5984
      // op: Ii
5985
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5986
0
      op &= UINT64_C(252);
5987
0
      op <<= 5;
5988
0
      Value |= op;
5989
      // op: II
5990
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5991
0
      Value |= (op & UINT64_C(32)) << 8;
5992
0
      Value |= (op & UINT64_C(31));
5993
      // op: Pv4
5994
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5995
0
      op &= UINT64_C(3);
5996
0
      op <<= 5;
5997
0
      Value |= op;
5998
      // op: Rs32
5999
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6000
0
      op &= UINT64_C(31);
6001
0
      op <<= 16;
6002
0
      Value |= op;
6003
0
      break;
6004
0
    }
6005
0
    case Hexagon::C2_muxii: {
6006
      // op: Ii
6007
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6008
0
      op &= UINT64_C(255);
6009
0
      op <<= 5;
6010
0
      Value |= op;
6011
      // op: II
6012
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6013
0
      Value |= (op & UINT64_C(254)) << 15;
6014
0
      Value |= (op & UINT64_C(1)) << 13;
6015
      // op: Pu4
6016
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6017
0
      op &= UINT64_C(3);
6018
0
      op <<= 23;
6019
0
      Value |= op;
6020
      // op: Rd32
6021
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6022
0
      op &= UINT64_C(31);
6023
0
      Value |= op;
6024
0
      break;
6025
0
    }
6026
0
    case Hexagon::C2_muxri: {
6027
      // op: Ii
6028
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6029
0
      op &= UINT64_C(255);
6030
0
      op <<= 5;
6031
0
      Value |= op;
6032
      // op: Pu4
6033
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6034
0
      op &= UINT64_C(3);
6035
0
      op <<= 21;
6036
0
      Value |= op;
6037
      // op: Rs32
6038
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6039
0
      op &= UINT64_C(31);
6040
0
      op <<= 16;
6041
0
      Value |= op;
6042
      // op: Rd32
6043
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6044
0
      op &= UINT64_C(31);
6045
0
      Value |= op;
6046
0
      break;
6047
0
    }
6048
0
    case Hexagon::A4_cmpbeqi:
6049
0
    case Hexagon::A4_cmpbgti:
6050
0
    case Hexagon::A4_cmpheqi:
6051
0
    case Hexagon::A4_cmphgti: {
6052
      // op: Ii
6053
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6054
0
      op &= UINT64_C(255);
6055
0
      op <<= 5;
6056
0
      Value |= op;
6057
      // op: Rs32
6058
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6059
0
      op &= UINT64_C(31);
6060
0
      op <<= 16;
6061
0
      Value |= op;
6062
      // op: Pd4
6063
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6064
0
      op &= UINT64_C(3);
6065
0
      Value |= op;
6066
0
      break;
6067
0
    }
6068
0
    case Hexagon::A4_rcmpeqi:
6069
0
    case Hexagon::A4_rcmpneqi:
6070
0
    case Hexagon::M2_mpysin:
6071
0
    case Hexagon::M2_mpysip: {
6072
      // op: Ii
6073
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6074
0
      op &= UINT64_C(255);
6075
0
      op <<= 5;
6076
0
      Value |= op;
6077
      // op: Rs32
6078
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6079
0
      op &= UINT64_C(31);
6080
0
      op <<= 16;
6081
0
      Value |= op;
6082
      // op: Rd32
6083
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6084
0
      op &= UINT64_C(31);
6085
0
      Value |= op;
6086
0
      break;
6087
0
    }
6088
0
    case Hexagon::A4_combineri: {
6089
      // op: Ii
6090
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6091
0
      op &= UINT64_C(255);
6092
0
      op <<= 5;
6093
0
      Value |= op;
6094
      // op: Rs32
6095
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6096
0
      op &= UINT64_C(31);
6097
0
      op <<= 16;
6098
0
      Value |= op;
6099
      // op: Rdd32
6100
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6101
0
      op &= UINT64_C(31);
6102
0
      Value |= op;
6103
0
      break;
6104
0
    }
6105
0
    case Hexagon::A4_vcmpbeqi:
6106
0
    case Hexagon::A4_vcmpbgti:
6107
0
    case Hexagon::A4_vcmpheqi:
6108
0
    case Hexagon::A4_vcmphgti:
6109
0
    case Hexagon::A4_vcmpweqi:
6110
0
    case Hexagon::A4_vcmpwgti: {
6111
      // op: Ii
6112
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6113
0
      op &= UINT64_C(255);
6114
0
      op <<= 5;
6115
0
      Value |= op;
6116
      // op: Rss32
6117
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6118
0
      op &= UINT64_C(31);
6119
0
      op <<= 16;
6120
0
      Value |= op;
6121
      // op: Pd4
6122
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6123
0
      op &= UINT64_C(3);
6124
0
      Value |= op;
6125
0
      break;
6126
0
    }
6127
0
    case Hexagon::S2_storerhnew_pci: {
6128
      // op: Ii
6129
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6130
0
      op &= UINT64_C(30);
6131
0
      op <<= 2;
6132
0
      Value |= op;
6133
      // op: Mu2
6134
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6135
0
      op &= UINT64_C(1);
6136
0
      op <<= 13;
6137
0
      Value |= op;
6138
      // op: Nt8
6139
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
6140
0
      op &= UINT64_C(7);
6141
0
      op <<= 8;
6142
0
      Value |= op;
6143
      // op: Rx32
6144
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6145
0
      op &= UINT64_C(31);
6146
0
      op <<= 16;
6147
0
      Value |= op;
6148
0
      break;
6149
0
    }
6150
0
    case Hexagon::S2_storerf_pci:
6151
0
    case Hexagon::S2_storerh_pci: {
6152
      // op: Ii
6153
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6154
0
      op &= UINT64_C(30);
6155
0
      op <<= 2;
6156
0
      Value |= op;
6157
      // op: Mu2
6158
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6159
0
      op &= UINT64_C(1);
6160
0
      op <<= 13;
6161
0
      Value |= op;
6162
      // op: Rt32
6163
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
6164
0
      op &= UINT64_C(31);
6165
0
      op <<= 8;
6166
0
      Value |= op;
6167
      // op: Rx32
6168
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6169
0
      op &= UINT64_C(31);
6170
0
      op <<= 16;
6171
0
      Value |= op;
6172
0
      break;
6173
0
    }
6174
0
    case Hexagon::S2_storerhnew_pi: {
6175
      // op: Ii
6176
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6177
0
      op &= UINT64_C(30);
6178
0
      op <<= 2;
6179
0
      Value |= op;
6180
      // op: Nt8
6181
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6182
0
      op &= UINT64_C(7);
6183
0
      op <<= 8;
6184
0
      Value |= op;
6185
      // op: Rx32
6186
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6187
0
      op &= UINT64_C(31);
6188
0
      op <<= 16;
6189
0
      Value |= op;
6190
0
      break;
6191
0
    }
6192
0
    case Hexagon::S2_storerf_pi:
6193
0
    case Hexagon::S2_storerh_pi: {
6194
      // op: Ii
6195
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6196
0
      op &= UINT64_C(30);
6197
0
      op <<= 2;
6198
0
      Value |= op;
6199
      // op: Rt32
6200
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6201
0
      op &= UINT64_C(31);
6202
0
      op <<= 8;
6203
0
      Value |= op;
6204
      // op: Rx32
6205
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6206
0
      op &= UINT64_C(31);
6207
0
      op <<= 16;
6208
0
      Value |= op;
6209
0
      break;
6210
0
    }
6211
0
    case Hexagon::F2_dfclass: {
6212
      // op: Ii
6213
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6214
0
      op &= UINT64_C(31);
6215
0
      op <<= 5;
6216
0
      Value |= op;
6217
      // op: Rss32
6218
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6219
0
      op &= UINT64_C(31);
6220
0
      op <<= 16;
6221
0
      Value |= op;
6222
      // op: Pd4
6223
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6224
0
      op &= UINT64_C(3);
6225
0
      Value |= op;
6226
0
      break;
6227
0
    }
6228
0
    case Hexagon::S2_extractu:
6229
0
    case Hexagon::S4_extract: {
6230
      // op: Ii
6231
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6232
0
      op &= UINT64_C(31);
6233
0
      op <<= 8;
6234
0
      Value |= op;
6235
      // op: II
6236
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6237
0
      Value |= (op & UINT64_C(24)) << 18;
6238
0
      Value |= (op & UINT64_C(7)) << 5;
6239
      // op: Rs32
6240
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6241
0
      op &= UINT64_C(31);
6242
0
      op <<= 16;
6243
0
      Value |= op;
6244
      // op: Rd32
6245
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6246
0
      op &= UINT64_C(31);
6247
0
      Value |= op;
6248
0
      break;
6249
0
    }
6250
0
    case Hexagon::F2_sfclass:
6251
0
    case Hexagon::S2_tstbit_i:
6252
0
    case Hexagon::S4_ntstbit_i: {
6253
      // op: Ii
6254
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6255
0
      op &= UINT64_C(31);
6256
0
      op <<= 8;
6257
0
      Value |= op;
6258
      // op: Rs32
6259
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6260
0
      op &= UINT64_C(31);
6261
0
      op <<= 16;
6262
0
      Value |= op;
6263
      // op: Pd4
6264
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6265
0
      op &= UINT64_C(3);
6266
0
      Value |= op;
6267
0
      break;
6268
0
    }
6269
0
    case Hexagon::A4_cround_ri:
6270
0
    case Hexagon::A4_round_ri:
6271
0
    case Hexagon::A4_round_ri_sat:
6272
0
    case Hexagon::A7_clip:
6273
0
    case Hexagon::S2_asl_i_r:
6274
0
    case Hexagon::S2_asl_i_r_sat:
6275
0
    case Hexagon::S2_asr_i_r:
6276
0
    case Hexagon::S2_asr_i_r_rnd:
6277
0
    case Hexagon::S2_clrbit_i:
6278
0
    case Hexagon::S2_lsr_i_r:
6279
0
    case Hexagon::S2_setbit_i:
6280
0
    case Hexagon::S2_togglebit_i:
6281
0
    case Hexagon::S6_rol_i_r: {
6282
      // op: Ii
6283
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6284
0
      op &= UINT64_C(31);
6285
0
      op <<= 8;
6286
0
      Value |= op;
6287
      // op: Rs32
6288
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6289
0
      op &= UINT64_C(31);
6290
0
      op <<= 16;
6291
0
      Value |= op;
6292
      // op: Rd32
6293
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6294
0
      op &= UINT64_C(31);
6295
0
      Value |= op;
6296
0
      break;
6297
0
    }
6298
0
    case Hexagon::A4_bitspliti: {
6299
      // op: Ii
6300
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6301
0
      op &= UINT64_C(31);
6302
0
      op <<= 8;
6303
0
      Value |= op;
6304
      // op: Rs32
6305
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6306
0
      op &= UINT64_C(31);
6307
0
      op <<= 16;
6308
0
      Value |= op;
6309
      // op: Rdd32
6310
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6311
0
      op &= UINT64_C(31);
6312
0
      Value |= op;
6313
0
      break;
6314
0
    }
6315
0
    case Hexagon::S2_asr_i_svw_trun: {
6316
      // op: Ii
6317
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6318
0
      op &= UINT64_C(31);
6319
0
      op <<= 8;
6320
0
      Value |= op;
6321
      // op: Rss32
6322
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6323
0
      op &= UINT64_C(31);
6324
0
      op <<= 16;
6325
0
      Value |= op;
6326
      // op: Rd32
6327
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6328
0
      op &= UINT64_C(31);
6329
0
      Value |= op;
6330
0
      break;
6331
0
    }
6332
0
    case Hexagon::A7_vclip:
6333
0
    case Hexagon::S2_asl_i_vw:
6334
0
    case Hexagon::S2_asr_i_vw:
6335
0
    case Hexagon::S2_lsr_i_vw: {
6336
      // op: Ii
6337
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6338
0
      op &= UINT64_C(31);
6339
0
      op <<= 8;
6340
0
      Value |= op;
6341
      // op: Rss32
6342
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6343
0
      op &= UINT64_C(31);
6344
0
      op <<= 16;
6345
0
      Value |= op;
6346
      // op: Rdd32
6347
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6348
0
      op &= UINT64_C(31);
6349
0
      Value |= op;
6350
0
      break;
6351
0
    }
6352
0
    case Hexagon::C2_cmpgtui:
6353
0
    case Hexagon::C4_cmplteui: {
6354
      // op: Ii
6355
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6356
0
      op &= UINT64_C(511);
6357
0
      op <<= 5;
6358
0
      Value |= op;
6359
      // op: Rs32
6360
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6361
0
      op &= UINT64_C(31);
6362
0
      op <<= 16;
6363
0
      Value |= op;
6364
      // op: Pd4
6365
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6366
0
      op &= UINT64_C(3);
6367
0
      Value |= op;
6368
0
      break;
6369
0
    }
6370
0
    case Hexagon::S2_storerinew_pci: {
6371
      // op: Ii
6372
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6373
0
      op &= UINT64_C(60);
6374
0
      op <<= 1;
6375
0
      Value |= op;
6376
      // op: Mu2
6377
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6378
0
      op &= UINT64_C(1);
6379
0
      op <<= 13;
6380
0
      Value |= op;
6381
      // op: Nt8
6382
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
6383
0
      op &= UINT64_C(7);
6384
0
      op <<= 8;
6385
0
      Value |= op;
6386
      // op: Rx32
6387
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6388
0
      op &= UINT64_C(31);
6389
0
      op <<= 16;
6390
0
      Value |= op;
6391
0
      break;
6392
0
    }
6393
0
    case Hexagon::S2_storeri_pci: {
6394
      // op: Ii
6395
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6396
0
      op &= UINT64_C(60);
6397
0
      op <<= 1;
6398
0
      Value |= op;
6399
      // op: Mu2
6400
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6401
0
      op &= UINT64_C(1);
6402
0
      op <<= 13;
6403
0
      Value |= op;
6404
      // op: Rt32
6405
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
6406
0
      op &= UINT64_C(31);
6407
0
      op <<= 8;
6408
0
      Value |= op;
6409
      // op: Rx32
6410
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6411
0
      op &= UINT64_C(31);
6412
0
      op <<= 16;
6413
0
      Value |= op;
6414
0
      break;
6415
0
    }
6416
0
    case Hexagon::S2_storerinew_pi: {
6417
      // op: Ii
6418
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6419
0
      op &= UINT64_C(60);
6420
0
      op <<= 1;
6421
0
      Value |= op;
6422
      // op: Nt8
6423
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6424
0
      op &= UINT64_C(7);
6425
0
      op <<= 8;
6426
0
      Value |= op;
6427
      // op: Rx32
6428
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6429
0
      op &= UINT64_C(31);
6430
0
      op <<= 16;
6431
0
      Value |= op;
6432
0
      break;
6433
0
    }
6434
0
    case Hexagon::S2_storeri_pi: {
6435
      // op: Ii
6436
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6437
0
      op &= UINT64_C(60);
6438
0
      op <<= 1;
6439
0
      Value |= op;
6440
      // op: Rt32
6441
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6442
0
      op &= UINT64_C(31);
6443
0
      op <<= 8;
6444
0
      Value |= op;
6445
      // op: Rx32
6446
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6447
0
      op &= UINT64_C(31);
6448
0
      op <<= 16;
6449
0
      Value |= op;
6450
0
      break;
6451
0
    }
6452
0
    case Hexagon::SL1_loadri_io: {
6453
      // op: Ii
6454
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6455
0
      op &= UINT64_C(60);
6456
0
      op <<= 6;
6457
0
      Value |= op;
6458
      // op: Rs16
6459
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6460
0
      op &= UINT64_C(15);
6461
0
      op <<= 4;
6462
0
      Value |= op;
6463
      // op: Rd16
6464
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6465
0
      op &= UINT64_C(15);
6466
0
      Value |= op;
6467
0
      break;
6468
0
    }
6469
0
    case Hexagon::S4_storeirbf_io:
6470
0
    case Hexagon::S4_storeirbfnew_io:
6471
0
    case Hexagon::S4_storeirbt_io:
6472
0
    case Hexagon::S4_storeirbtnew_io: {
6473
      // op: Ii
6474
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6475
0
      op &= UINT64_C(63);
6476
0
      op <<= 7;
6477
0
      Value |= op;
6478
      // op: II
6479
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6480
0
      Value |= (op & UINT64_C(32)) << 8;
6481
0
      Value |= (op & UINT64_C(31));
6482
      // op: Pv4
6483
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6484
0
      op &= UINT64_C(3);
6485
0
      op <<= 5;
6486
0
      Value |= op;
6487
      // op: Rs32
6488
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6489
0
      op &= UINT64_C(31);
6490
0
      op <<= 16;
6491
0
      Value |= op;
6492
0
      break;
6493
0
    }
6494
0
    case Hexagon::S2_extractup:
6495
0
    case Hexagon::S4_extractp: {
6496
      // op: Ii
6497
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6498
0
      op &= UINT64_C(63);
6499
0
      op <<= 8;
6500
0
      Value |= op;
6501
      // op: II
6502
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6503
0
      Value |= (op & UINT64_C(56)) << 18;
6504
0
      Value |= (op & UINT64_C(7)) << 5;
6505
      // op: Rss32
6506
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6507
0
      op &= UINT64_C(31);
6508
0
      op <<= 16;
6509
0
      Value |= op;
6510
      // op: Rdd32
6511
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6512
0
      op &= UINT64_C(31);
6513
0
      Value |= op;
6514
0
      break;
6515
0
    }
6516
0
    case Hexagon::C2_bitsclri:
6517
0
    case Hexagon::C4_nbitsclri: {
6518
      // op: Ii
6519
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6520
0
      op &= UINT64_C(63);
6521
0
      op <<= 8;
6522
0
      Value |= op;
6523
      // op: Rs32
6524
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6525
0
      op &= UINT64_C(31);
6526
0
      op <<= 16;
6527
0
      Value |= op;
6528
      // op: Pd4
6529
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6530
0
      op &= UINT64_C(3);
6531
0
      Value |= op;
6532
0
      break;
6533
0
    }
6534
0
    case Hexagon::S4_clbaddi: {
6535
      // op: Ii
6536
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6537
0
      op &= UINT64_C(63);
6538
0
      op <<= 8;
6539
0
      Value |= op;
6540
      // op: Rs32
6541
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6542
0
      op &= UINT64_C(31);
6543
0
      op <<= 16;
6544
0
      Value |= op;
6545
      // op: Rd32
6546
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6547
0
      op &= UINT64_C(31);
6548
0
      Value |= op;
6549
0
      break;
6550
0
    }
6551
0
    case Hexagon::S4_clbpaddi: {
6552
      // op: Ii
6553
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6554
0
      op &= UINT64_C(63);
6555
0
      op <<= 8;
6556
0
      Value |= op;
6557
      // op: Rss32
6558
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6559
0
      op &= UINT64_C(31);
6560
0
      op <<= 16;
6561
0
      Value |= op;
6562
      // op: Rd32
6563
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6564
0
      op &= UINT64_C(31);
6565
0
      Value |= op;
6566
0
      break;
6567
0
    }
6568
0
    case Hexagon::A7_croundd_ri:
6569
0
    case Hexagon::S2_asl_i_p:
6570
0
    case Hexagon::S2_asr_i_p:
6571
0
    case Hexagon::S2_asr_i_p_rnd:
6572
0
    case Hexagon::S2_lsr_i_p:
6573
0
    case Hexagon::S6_rol_i_p: {
6574
      // op: Ii
6575
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6576
0
      op &= UINT64_C(63);
6577
0
      op <<= 8;
6578
0
      Value |= op;
6579
      // op: Rss32
6580
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6581
0
      op &= UINT64_C(31);
6582
0
      op <<= 16;
6583
0
      Value |= op;
6584
      // op: Rdd32
6585
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6586
0
      op &= UINT64_C(31);
6587
0
      Value |= op;
6588
0
      break;
6589
0
    }
6590
0
    case Hexagon::V6_vS32b_new_pi:
6591
0
    case Hexagon::V6_vS32b_nt_new_pi: {
6592
      // op: Ii
6593
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6594
0
      op &= UINT64_C(7);
6595
0
      op <<= 8;
6596
0
      Value |= op;
6597
      // op: Os8
6598
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6599
0
      op &= UINT64_C(7);
6600
0
      Value |= op;
6601
      // op: Rx32
6602
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6603
0
      op &= UINT64_C(31);
6604
0
      op <<= 16;
6605
0
      Value |= op;
6606
0
      break;
6607
0
    }
6608
0
    case Hexagon::SL2_loadrb_io: {
6609
      // op: Ii
6610
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6611
0
      op &= UINT64_C(7);
6612
0
      op <<= 8;
6613
0
      Value |= op;
6614
      // op: Rs16
6615
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6616
0
      op &= UINT64_C(15);
6617
0
      op <<= 4;
6618
0
      Value |= op;
6619
      // op: Rd16
6620
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6621
0
      op &= UINT64_C(15);
6622
0
      Value |= op;
6623
0
      break;
6624
0
    }
6625
0
    case Hexagon::V6_vS32b_srls_pi:
6626
0
    case Hexagon::V6_zLd_pi: {
6627
      // op: Ii
6628
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6629
0
      op &= UINT64_C(7);
6630
0
      op <<= 8;
6631
0
      Value |= op;
6632
      // op: Rx32
6633
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6634
0
      op &= UINT64_C(31);
6635
0
      op <<= 16;
6636
0
      Value |= op;
6637
0
      break;
6638
0
    }
6639
0
    case Hexagon::V6_vS32Ub_pi:
6640
0
    case Hexagon::V6_vS32b_nt_pi:
6641
0
    case Hexagon::V6_vS32b_pi: {
6642
      // op: Ii
6643
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6644
0
      op &= UINT64_C(7);
6645
0
      op <<= 8;
6646
0
      Value |= op;
6647
      // op: Vs32
6648
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6649
0
      op &= UINT64_C(31);
6650
0
      Value |= op;
6651
      // op: Rx32
6652
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6653
0
      op &= UINT64_C(31);
6654
0
      op <<= 16;
6655
0
      Value |= op;
6656
0
      break;
6657
0
    }
6658
0
    case Hexagon::L2_loadalignb_io: {
6659
      // op: Ii
6660
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6661
0
      Value |= (op & UINT64_C(1536)) << 16;
6662
0
      Value |= (op & UINT64_C(511)) << 5;
6663
      // op: Rs32
6664
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6665
0
      op &= UINT64_C(31);
6666
0
      op <<= 16;
6667
0
      Value |= op;
6668
      // op: Ryy32
6669
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6670
0
      op &= UINT64_C(31);
6671
0
      Value |= op;
6672
0
      break;
6673
0
    }
6674
0
    case Hexagon::S4_vrcrotate: {
6675
      // op: Ii
6676
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6677
0
      Value |= (op & UINT64_C(2)) << 12;
6678
0
      Value |= (op & UINT64_C(1)) << 5;
6679
      // op: Rss32
6680
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6681
0
      op &= UINT64_C(31);
6682
0
      op <<= 16;
6683
0
      Value |= op;
6684
      // op: Rt32
6685
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6686
0
      op &= UINT64_C(31);
6687
0
      op <<= 8;
6688
0
      Value |= op;
6689
      // op: Rdd32
6690
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6691
0
      op &= UINT64_C(31);
6692
0
      Value |= op;
6693
0
      break;
6694
0
    }
6695
0
    case Hexagon::L4_loadalignb_ur:
6696
0
    case Hexagon::L4_loadalignh_ur: {
6697
      // op: Ii
6698
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6699
0
      Value |= (op & UINT64_C(2)) << 12;
6700
0
      Value |= (op & UINT64_C(1)) << 7;
6701
      // op: II
6702
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
6703
0
      Value |= (op & UINT64_C(60)) << 6;
6704
0
      Value |= (op & UINT64_C(3)) << 5;
6705
      // op: Rt32
6706
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6707
0
      op &= UINT64_C(31);
6708
0
      op <<= 16;
6709
0
      Value |= op;
6710
      // op: Ryy32
6711
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6712
0
      op &= UINT64_C(31);
6713
0
      Value |= op;
6714
0
      break;
6715
0
    }
6716
0
    case Hexagon::S4_pstorerbnewf_rr:
6717
0
    case Hexagon::S4_pstorerbnewfnew_rr:
6718
0
    case Hexagon::S4_pstorerbnewt_rr:
6719
0
    case Hexagon::S4_pstorerbnewtnew_rr:
6720
0
    case Hexagon::S4_pstorerhnewf_rr:
6721
0
    case Hexagon::S4_pstorerhnewfnew_rr:
6722
0
    case Hexagon::S4_pstorerhnewt_rr:
6723
0
    case Hexagon::S4_pstorerhnewtnew_rr:
6724
0
    case Hexagon::S4_pstorerinewf_rr:
6725
0
    case Hexagon::S4_pstorerinewfnew_rr:
6726
0
    case Hexagon::S4_pstorerinewt_rr:
6727
0
    case Hexagon::S4_pstorerinewtnew_rr: {
6728
      // op: Ii
6729
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6730
0
      Value |= (op & UINT64_C(2)) << 12;
6731
0
      Value |= (op & UINT64_C(1)) << 7;
6732
      // op: Pv4
6733
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6734
0
      op &= UINT64_C(3);
6735
0
      op <<= 5;
6736
0
      Value |= op;
6737
      // op: Rs32
6738
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6739
0
      op &= UINT64_C(31);
6740
0
      op <<= 16;
6741
0
      Value |= op;
6742
      // op: Ru32
6743
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6744
0
      op &= UINT64_C(31);
6745
0
      op <<= 8;
6746
0
      Value |= op;
6747
      // op: Nt8
6748
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
6749
0
      op &= UINT64_C(7);
6750
0
      Value |= op;
6751
0
      break;
6752
0
    }
6753
0
    case Hexagon::S4_pstorerbf_rr:
6754
0
    case Hexagon::S4_pstorerbfnew_rr:
6755
0
    case Hexagon::S4_pstorerbt_rr:
6756
0
    case Hexagon::S4_pstorerbtnew_rr:
6757
0
    case Hexagon::S4_pstorerff_rr:
6758
0
    case Hexagon::S4_pstorerffnew_rr:
6759
0
    case Hexagon::S4_pstorerft_rr:
6760
0
    case Hexagon::S4_pstorerftnew_rr:
6761
0
    case Hexagon::S4_pstorerhf_rr:
6762
0
    case Hexagon::S4_pstorerhfnew_rr:
6763
0
    case Hexagon::S4_pstorerht_rr:
6764
0
    case Hexagon::S4_pstorerhtnew_rr:
6765
0
    case Hexagon::S4_pstorerif_rr:
6766
0
    case Hexagon::S4_pstorerifnew_rr:
6767
0
    case Hexagon::S4_pstorerit_rr:
6768
0
    case Hexagon::S4_pstoreritnew_rr: {
6769
      // op: Ii
6770
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6771
0
      Value |= (op & UINT64_C(2)) << 12;
6772
0
      Value |= (op & UINT64_C(1)) << 7;
6773
      // op: Pv4
6774
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6775
0
      op &= UINT64_C(3);
6776
0
      op <<= 5;
6777
0
      Value |= op;
6778
      // op: Rs32
6779
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6780
0
      op &= UINT64_C(31);
6781
0
      op <<= 16;
6782
0
      Value |= op;
6783
      // op: Ru32
6784
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6785
0
      op &= UINT64_C(31);
6786
0
      op <<= 8;
6787
0
      Value |= op;
6788
      // op: Rt32
6789
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
6790
0
      op &= UINT64_C(31);
6791
0
      Value |= op;
6792
0
      break;
6793
0
    }
6794
0
    case Hexagon::S4_pstorerdf_rr:
6795
0
    case Hexagon::S4_pstorerdfnew_rr:
6796
0
    case Hexagon::S4_pstorerdt_rr:
6797
0
    case Hexagon::S4_pstorerdtnew_rr: {
6798
      // op: Ii
6799
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6800
0
      Value |= (op & UINT64_C(2)) << 12;
6801
0
      Value |= (op & UINT64_C(1)) << 7;
6802
      // op: Pv4
6803
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6804
0
      op &= UINT64_C(3);
6805
0
      op <<= 5;
6806
0
      Value |= op;
6807
      // op: Rs32
6808
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6809
0
      op &= UINT64_C(31);
6810
0
      op <<= 16;
6811
0
      Value |= op;
6812
      // op: Ru32
6813
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6814
0
      op &= UINT64_C(31);
6815
0
      op <<= 8;
6816
0
      Value |= op;
6817
      // op: Rtt32
6818
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
6819
0
      op &= UINT64_C(31);
6820
0
      Value |= op;
6821
0
      break;
6822
0
    }
6823
0
    case Hexagon::L4_loadrb_rr:
6824
0
    case Hexagon::L4_loadrh_rr:
6825
0
    case Hexagon::L4_loadri_rr:
6826
0
    case Hexagon::L4_loadrub_rr:
6827
0
    case Hexagon::L4_loadruh_rr: {
6828
      // op: Ii
6829
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6830
0
      Value |= (op & UINT64_C(2)) << 12;
6831
0
      Value |= (op & UINT64_C(1)) << 7;
6832
      // op: Rs32
6833
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6834
0
      op &= UINT64_C(31);
6835
0
      op <<= 16;
6836
0
      Value |= op;
6837
      // op: Rt32
6838
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6839
0
      op &= UINT64_C(31);
6840
0
      op <<= 8;
6841
0
      Value |= op;
6842
      // op: Rd32
6843
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6844
0
      op &= UINT64_C(31);
6845
0
      Value |= op;
6846
0
      break;
6847
0
    }
6848
0
    case Hexagon::L4_loadrd_rr: {
6849
      // op: Ii
6850
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6851
0
      Value |= (op & UINT64_C(2)) << 12;
6852
0
      Value |= (op & UINT64_C(1)) << 7;
6853
      // op: Rs32
6854
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6855
0
      op &= UINT64_C(31);
6856
0
      op <<= 16;
6857
0
      Value |= op;
6858
      // op: Rt32
6859
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6860
0
      op &= UINT64_C(31);
6861
0
      op <<= 8;
6862
0
      Value |= op;
6863
      // op: Rdd32
6864
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6865
0
      op &= UINT64_C(31);
6866
0
      Value |= op;
6867
0
      break;
6868
0
    }
6869
0
    case Hexagon::L2_loadalignh_io: {
6870
      // op: Ii
6871
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6872
0
      Value |= (op & UINT64_C(3072)) << 15;
6873
0
      Value |= (op & UINT64_C(1022)) << 4;
6874
      // op: Rs32
6875
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6876
0
      op &= UINT64_C(31);
6877
0
      op <<= 16;
6878
0
      Value |= op;
6879
      // op: Ryy32
6880
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6881
0
      op &= UINT64_C(31);
6882
0
      Value |= op;
6883
0
      break;
6884
0
    }
6885
0
    case Hexagon::S4_addaddi: {
6886
      // op: Ii
6887
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6888
0
      Value |= (op & UINT64_C(48)) << 17;
6889
0
      Value |= (op & UINT64_C(8)) << 10;
6890
0
      Value |= (op & UINT64_C(7)) << 5;
6891
      // op: Rs32
6892
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6893
0
      op &= UINT64_C(31);
6894
0
      op <<= 16;
6895
0
      Value |= op;
6896
      // op: Ru32
6897
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6898
0
      op &= UINT64_C(31);
6899
0
      Value |= op;
6900
      // op: Rd32
6901
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6902
0
      op &= UINT64_C(31);
6903
0
      op <<= 8;
6904
0
      Value |= op;
6905
0
      break;
6906
0
    }
6907
0
    case Hexagon::M4_mpyri_addr: {
6908
      // op: Ii
6909
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6910
0
      Value |= (op & UINT64_C(48)) << 17;
6911
0
      Value |= (op & UINT64_C(8)) << 10;
6912
0
      Value |= (op & UINT64_C(7)) << 5;
6913
      // op: Ru32
6914
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6915
0
      op &= UINT64_C(31);
6916
0
      Value |= op;
6917
      // op: Rs32
6918
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6919
0
      op &= UINT64_C(31);
6920
0
      op <<= 16;
6921
0
      Value |= op;
6922
      // op: Rd32
6923
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6924
0
      op &= UINT64_C(31);
6925
0
      op <<= 8;
6926
0
      Value |= op;
6927
0
      break;
6928
0
    }
6929
0
    case Hexagon::S4_or_andi:
6930
0
    case Hexagon::S4_or_ori: {
6931
      // op: Ii
6932
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6933
0
      Value |= (op & UINT64_C(512)) << 12;
6934
0
      Value |= (op & UINT64_C(511)) << 5;
6935
      // op: Rs32
6936
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6937
0
      op &= UINT64_C(31);
6938
0
      op <<= 16;
6939
0
      Value |= op;
6940
      // op: Rx32
6941
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6942
0
      op &= UINT64_C(31);
6943
0
      Value |= op;
6944
0
      break;
6945
0
    }
6946
0
    case Hexagon::S4_or_andix: {
6947
      // op: Ii
6948
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6949
0
      Value |= (op & UINT64_C(512)) << 12;
6950
0
      Value |= (op & UINT64_C(511)) << 5;
6951
      // op: Ru32
6952
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6953
0
      op &= UINT64_C(31);
6954
0
      Value |= op;
6955
      // op: Rx32
6956
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6957
0
      op &= UINT64_C(31);
6958
0
      op <<= 16;
6959
0
      Value |= op;
6960
0
      break;
6961
0
    }
6962
0
    case Hexagon::V6_vL32b_cur_npred_ai:
6963
0
    case Hexagon::V6_vL32b_cur_pred_ai:
6964
0
    case Hexagon::V6_vL32b_npred_ai:
6965
0
    case Hexagon::V6_vL32b_nt_cur_npred_ai:
6966
0
    case Hexagon::V6_vL32b_nt_cur_pred_ai:
6967
0
    case Hexagon::V6_vL32b_nt_npred_ai:
6968
0
    case Hexagon::V6_vL32b_nt_pred_ai:
6969
0
    case Hexagon::V6_vL32b_nt_tmp_npred_ai:
6970
0
    case Hexagon::V6_vL32b_nt_tmp_pred_ai:
6971
0
    case Hexagon::V6_vL32b_pred_ai:
6972
0
    case Hexagon::V6_vL32b_tmp_npred_ai:
6973
0
    case Hexagon::V6_vL32b_tmp_pred_ai: {
6974
      // op: Ii
6975
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6976
0
      Value |= (op & UINT64_C(8)) << 10;
6977
0
      Value |= (op & UINT64_C(7)) << 8;
6978
      // op: Pv4
6979
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6980
0
      op &= UINT64_C(3);
6981
0
      op <<= 11;
6982
0
      Value |= op;
6983
      // op: Rt32
6984
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6985
0
      op &= UINT64_C(31);
6986
0
      op <<= 16;
6987
0
      Value |= op;
6988
      // op: Vd32
6989
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6990
0
      op &= UINT64_C(31);
6991
0
      Value |= op;
6992
0
      break;
6993
0
    }
6994
0
    case Hexagon::S2_tableidxb:
6995
0
    case Hexagon::S2_tableidxd:
6996
0
    case Hexagon::S2_tableidxh:
6997
0
    case Hexagon::S2_tableidxw: {
6998
      // op: Ii
6999
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7000
0
      Value |= (op & UINT64_C(8)) << 18;
7001
0
      Value |= (op & UINT64_C(7)) << 5;
7002
      // op: II
7003
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7004
0
      op &= UINT64_C(63);
7005
0
      op <<= 8;
7006
0
      Value |= op;
7007
      // op: Rs32
7008
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7009
0
      op &= UINT64_C(31);
7010
0
      op <<= 16;
7011
0
      Value |= op;
7012
      // op: Rx32
7013
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7014
0
      op &= UINT64_C(31);
7015
0
      Value |= op;
7016
0
      break;
7017
0
    }
7018
0
    case Hexagon::V6_vrmpybusi:
7019
0
    case Hexagon::V6_vrmpyubi:
7020
0
    case Hexagon::V6_vrsadubi: {
7021
      // op: Ii
7022
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7023
0
      op &= UINT64_C(1);
7024
0
      op <<= 5;
7025
0
      Value |= op;
7026
      // op: Vuu32
7027
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7028
0
      op &= UINT64_C(31);
7029
0
      op <<= 8;
7030
0
      Value |= op;
7031
      // op: Rt32
7032
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7033
0
      op &= UINT64_C(31);
7034
0
      op <<= 16;
7035
0
      Value |= op;
7036
      // op: Vdd32
7037
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7038
0
      op &= UINT64_C(31);
7039
0
      Value |= op;
7040
0
      break;
7041
0
    }
7042
0
    case Hexagon::S2_pstorerdf_pi:
7043
0
    case Hexagon::S2_pstorerdfnew_pi:
7044
0
    case Hexagon::S2_pstorerdt_pi:
7045
0
    case Hexagon::S2_pstorerdtnew_pi: {
7046
      // op: Ii
7047
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7048
0
      op &= UINT64_C(120);
7049
0
      Value |= op;
7050
      // op: Pv4
7051
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7052
0
      op &= UINT64_C(3);
7053
0
      Value |= op;
7054
      // op: Rtt32
7055
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7056
0
      op &= UINT64_C(31);
7057
0
      op <<= 8;
7058
0
      Value |= op;
7059
      // op: Rx32
7060
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7061
0
      op &= UINT64_C(31);
7062
0
      op <<= 16;
7063
0
      Value |= op;
7064
0
      break;
7065
0
    }
7066
0
    case Hexagon::L2_loadrd_pci: {
7067
      // op: Ii
7068
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7069
0
      op &= UINT64_C(120);
7070
0
      op <<= 2;
7071
0
      Value |= op;
7072
      // op: Mu2
7073
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7074
0
      op &= UINT64_C(1);
7075
0
      op <<= 13;
7076
0
      Value |= op;
7077
      // op: Rdd32
7078
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7079
0
      op &= UINT64_C(31);
7080
0
      Value |= op;
7081
      // op: Rx32
7082
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7083
0
      op &= UINT64_C(31);
7084
0
      op <<= 16;
7085
0
      Value |= op;
7086
0
      break;
7087
0
    }
7088
0
    case Hexagon::L2_loadrd_pi: {
7089
      // op: Ii
7090
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7091
0
      op &= UINT64_C(120);
7092
0
      op <<= 2;
7093
0
      Value |= op;
7094
      // op: Rdd32
7095
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7096
0
      op &= UINT64_C(31);
7097
0
      Value |= op;
7098
      // op: Rx32
7099
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7100
0
      op &= UINT64_C(31);
7101
0
      op <<= 16;
7102
0
      Value |= op;
7103
0
      break;
7104
0
    }
7105
0
    case Hexagon::L2_ploadrhf_io:
7106
0
    case Hexagon::L2_ploadrhfnew_io:
7107
0
    case Hexagon::L2_ploadrht_io:
7108
0
    case Hexagon::L2_ploadrhtnew_io:
7109
0
    case Hexagon::L2_ploadruhf_io:
7110
0
    case Hexagon::L2_ploadruhfnew_io:
7111
0
    case Hexagon::L2_ploadruht_io:
7112
0
    case Hexagon::L2_ploadruhtnew_io: {
7113
      // op: Ii
7114
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7115
0
      op &= UINT64_C(126);
7116
0
      op <<= 4;
7117
0
      Value |= op;
7118
      // op: Pt4
7119
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7120
0
      op &= UINT64_C(3);
7121
0
      op <<= 11;
7122
0
      Value |= op;
7123
      // op: Rs32
7124
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7125
0
      op &= UINT64_C(31);
7126
0
      op <<= 16;
7127
0
      Value |= op;
7128
      // op: Rd32
7129
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7130
0
      op &= UINT64_C(31);
7131
0
      Value |= op;
7132
0
      break;
7133
0
    }
7134
0
    case Hexagon::S2_pstorerbnewf_pi:
7135
0
    case Hexagon::S2_pstorerbnewfnew_pi:
7136
0
    case Hexagon::S2_pstorerbnewt_pi:
7137
0
    case Hexagon::S2_pstorerbnewtnew_pi: {
7138
      // op: Ii
7139
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7140
0
      op &= UINT64_C(15);
7141
0
      op <<= 3;
7142
0
      Value |= op;
7143
      // op: Pv4
7144
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7145
0
      op &= UINT64_C(3);
7146
0
      Value |= op;
7147
      // op: Nt8
7148
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7149
0
      op &= UINT64_C(7);
7150
0
      op <<= 8;
7151
0
      Value |= op;
7152
      // op: Rx32
7153
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7154
0
      op &= UINT64_C(31);
7155
0
      op <<= 16;
7156
0
      Value |= op;
7157
0
      break;
7158
0
    }
7159
0
    case Hexagon::S2_pstorerbf_pi:
7160
0
    case Hexagon::S2_pstorerbfnew_pi:
7161
0
    case Hexagon::S2_pstorerbt_pi:
7162
0
    case Hexagon::S2_pstorerbtnew_pi: {
7163
      // op: Ii
7164
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7165
0
      op &= UINT64_C(15);
7166
0
      op <<= 3;
7167
0
      Value |= op;
7168
      // op: Pv4
7169
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7170
0
      op &= UINT64_C(3);
7171
0
      Value |= op;
7172
      // op: Rt32
7173
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7174
0
      op &= UINT64_C(31);
7175
0
      op <<= 8;
7176
0
      Value |= op;
7177
      // op: Rx32
7178
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7179
0
      op &= UINT64_C(31);
7180
0
      op <<= 16;
7181
0
      Value |= op;
7182
0
      break;
7183
0
    }
7184
0
    case Hexagon::L2_loadrb_pci:
7185
0
    case Hexagon::L2_loadrub_pci: {
7186
      // op: Ii
7187
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7188
0
      op &= UINT64_C(15);
7189
0
      op <<= 5;
7190
0
      Value |= op;
7191
      // op: Mu2
7192
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7193
0
      op &= UINT64_C(1);
7194
0
      op <<= 13;
7195
0
      Value |= op;
7196
      // op: Rd32
7197
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7198
0
      op &= UINT64_C(31);
7199
0
      Value |= op;
7200
      // op: Rx32
7201
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7202
0
      op &= UINT64_C(31);
7203
0
      op <<= 16;
7204
0
      Value |= op;
7205
0
      break;
7206
0
    }
7207
0
    case Hexagon::L2_loadrb_pi:
7208
0
    case Hexagon::L2_loadrub_pi: {
7209
      // op: Ii
7210
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7211
0
      op &= UINT64_C(15);
7212
0
      op <<= 5;
7213
0
      Value |= op;
7214
      // op: Rd32
7215
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7216
0
      op &= UINT64_C(31);
7217
0
      Value |= op;
7218
      // op: Rx32
7219
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7220
0
      op &= UINT64_C(31);
7221
0
      op <<= 16;
7222
0
      Value |= op;
7223
0
      break;
7224
0
    }
7225
0
    case Hexagon::L2_ploadrif_io:
7226
0
    case Hexagon::L2_ploadrifnew_io:
7227
0
    case Hexagon::L2_ploadrit_io:
7228
0
    case Hexagon::L2_ploadritnew_io: {
7229
      // op: Ii
7230
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7231
0
      op &= UINT64_C(252);
7232
0
      op <<= 3;
7233
0
      Value |= op;
7234
      // op: Pt4
7235
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7236
0
      op &= UINT64_C(3);
7237
0
      op <<= 11;
7238
0
      Value |= op;
7239
      // op: Rs32
7240
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7241
0
      op &= UINT64_C(31);
7242
0
      op <<= 16;
7243
0
      Value |= op;
7244
      // op: Rd32
7245
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7246
0
      op &= UINT64_C(31);
7247
0
      Value |= op;
7248
0
      break;
7249
0
    }
7250
0
    case Hexagon::A2_paddif:
7251
0
    case Hexagon::A2_paddifnew:
7252
0
    case Hexagon::A2_paddit:
7253
0
    case Hexagon::A2_padditnew:
7254
0
    case Hexagon::C2_muxir: {
7255
      // op: Ii
7256
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7257
0
      op &= UINT64_C(255);
7258
0
      op <<= 5;
7259
0
      Value |= op;
7260
      // op: Pu4
7261
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7262
0
      op &= UINT64_C(3);
7263
0
      op <<= 21;
7264
0
      Value |= op;
7265
      // op: Rs32
7266
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7267
0
      op &= UINT64_C(31);
7268
0
      op <<= 16;
7269
0
      Value |= op;
7270
      // op: Rd32
7271
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7272
0
      op &= UINT64_C(31);
7273
0
      Value |= op;
7274
0
      break;
7275
0
    }
7276
0
    case Hexagon::M2_accii:
7277
0
    case Hexagon::M2_macsin:
7278
0
    case Hexagon::M2_macsip:
7279
0
    case Hexagon::M2_naccii: {
7280
      // op: Ii
7281
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7282
0
      op &= UINT64_C(255);
7283
0
      op <<= 5;
7284
0
      Value |= op;
7285
      // op: Rs32
7286
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7287
0
      op &= UINT64_C(31);
7288
0
      op <<= 16;
7289
0
      Value |= op;
7290
      // op: Rx32
7291
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7292
0
      op &= UINT64_C(31);
7293
0
      Value |= op;
7294
0
      break;
7295
0
    }
7296
0
    case Hexagon::V6_v6mpyhubs10:
7297
0
    case Hexagon::V6_v6mpyvubs10: {
7298
      // op: Ii
7299
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7300
0
      op &= UINT64_C(3);
7301
0
      op <<= 5;
7302
0
      Value |= op;
7303
      // op: Vuu32
7304
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7305
0
      op &= UINT64_C(31);
7306
0
      op <<= 8;
7307
0
      Value |= op;
7308
      // op: Vvv32
7309
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7310
0
      op &= UINT64_C(31);
7311
0
      op <<= 16;
7312
0
      Value |= op;
7313
      // op: Vdd32
7314
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7315
0
      op &= UINT64_C(31);
7316
0
      Value |= op;
7317
0
      break;
7318
0
    }
7319
0
    case Hexagon::S2_pstorerhnewf_pi:
7320
0
    case Hexagon::S2_pstorerhnewfnew_pi:
7321
0
    case Hexagon::S2_pstorerhnewt_pi:
7322
0
    case Hexagon::S2_pstorerhnewtnew_pi: {
7323
      // op: Ii
7324
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7325
0
      op &= UINT64_C(30);
7326
0
      op <<= 2;
7327
0
      Value |= op;
7328
      // op: Pv4
7329
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7330
0
      op &= UINT64_C(3);
7331
0
      Value |= op;
7332
      // op: Nt8
7333
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7334
0
      op &= UINT64_C(7);
7335
0
      op <<= 8;
7336
0
      Value |= op;
7337
      // op: Rx32
7338
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7339
0
      op &= UINT64_C(31);
7340
0
      op <<= 16;
7341
0
      Value |= op;
7342
0
      break;
7343
0
    }
7344
0
    case Hexagon::S2_pstorerff_pi:
7345
0
    case Hexagon::S2_pstorerffnew_pi:
7346
0
    case Hexagon::S2_pstorerft_pi:
7347
0
    case Hexagon::S2_pstorerftnew_pi:
7348
0
    case Hexagon::S2_pstorerhf_pi:
7349
0
    case Hexagon::S2_pstorerhfnew_pi:
7350
0
    case Hexagon::S2_pstorerht_pi:
7351
0
    case Hexagon::S2_pstorerhtnew_pi: {
7352
      // op: Ii
7353
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7354
0
      op &= UINT64_C(30);
7355
0
      op <<= 2;
7356
0
      Value |= op;
7357
      // op: Pv4
7358
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7359
0
      op &= UINT64_C(3);
7360
0
      Value |= op;
7361
      // op: Rt32
7362
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7363
0
      op &= UINT64_C(31);
7364
0
      op <<= 8;
7365
0
      Value |= op;
7366
      // op: Rx32
7367
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7368
0
      op &= UINT64_C(31);
7369
0
      op <<= 16;
7370
0
      Value |= op;
7371
0
      break;
7372
0
    }
7373
0
    case Hexagon::L2_loadbsw2_pci:
7374
0
    case Hexagon::L2_loadbzw2_pci:
7375
0
    case Hexagon::L2_loadrh_pci:
7376
0
    case Hexagon::L2_loadruh_pci: {
7377
      // op: Ii
7378
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7379
0
      op &= UINT64_C(30);
7380
0
      op <<= 4;
7381
0
      Value |= op;
7382
      // op: Mu2
7383
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7384
0
      op &= UINT64_C(1);
7385
0
      op <<= 13;
7386
0
      Value |= op;
7387
      // op: Rd32
7388
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7389
0
      op &= UINT64_C(31);
7390
0
      Value |= op;
7391
      // op: Rx32
7392
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7393
0
      op &= UINT64_C(31);
7394
0
      op <<= 16;
7395
0
      Value |= op;
7396
0
      break;
7397
0
    }
7398
0
    case Hexagon::L2_loadbsw2_pi:
7399
0
    case Hexagon::L2_loadbzw2_pi:
7400
0
    case Hexagon::L2_loadrh_pi:
7401
0
    case Hexagon::L2_loadruh_pi: {
7402
      // op: Ii
7403
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7404
0
      op &= UINT64_C(30);
7405
0
      op <<= 4;
7406
0
      Value |= op;
7407
      // op: Rd32
7408
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7409
0
      op &= UINT64_C(31);
7410
0
      Value |= op;
7411
      // op: Rx32
7412
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7413
0
      op &= UINT64_C(31);
7414
0
      op <<= 16;
7415
0
      Value |= op;
7416
0
      break;
7417
0
    }
7418
0
    case Hexagon::S2_insert: {
7419
      // op: Ii
7420
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7421
0
      op &= UINT64_C(31);
7422
0
      op <<= 8;
7423
0
      Value |= op;
7424
      // op: II
7425
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7426
0
      Value |= (op & UINT64_C(24)) << 18;
7427
0
      Value |= (op & UINT64_C(7)) << 5;
7428
      // op: Rs32
7429
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7430
0
      op &= UINT64_C(31);
7431
0
      op <<= 16;
7432
0
      Value |= op;
7433
      // op: Rx32
7434
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7435
0
      op &= UINT64_C(31);
7436
0
      Value |= op;
7437
0
      break;
7438
0
    }
7439
0
    case Hexagon::S2_asl_i_r_acc:
7440
0
    case Hexagon::S2_asl_i_r_and:
7441
0
    case Hexagon::S2_asl_i_r_nac:
7442
0
    case Hexagon::S2_asl_i_r_or:
7443
0
    case Hexagon::S2_asl_i_r_xacc:
7444
0
    case Hexagon::S2_asr_i_r_acc:
7445
0
    case Hexagon::S2_asr_i_r_and:
7446
0
    case Hexagon::S2_asr_i_r_nac:
7447
0
    case Hexagon::S2_asr_i_r_or:
7448
0
    case Hexagon::S2_lsr_i_r_acc:
7449
0
    case Hexagon::S2_lsr_i_r_and:
7450
0
    case Hexagon::S2_lsr_i_r_nac:
7451
0
    case Hexagon::S2_lsr_i_r_or:
7452
0
    case Hexagon::S2_lsr_i_r_xacc:
7453
0
    case Hexagon::S6_rol_i_r_acc:
7454
0
    case Hexagon::S6_rol_i_r_and:
7455
0
    case Hexagon::S6_rol_i_r_nac:
7456
0
    case Hexagon::S6_rol_i_r_or:
7457
0
    case Hexagon::S6_rol_i_r_xacc: {
7458
      // op: Ii
7459
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7460
0
      op &= UINT64_C(31);
7461
0
      op <<= 8;
7462
0
      Value |= op;
7463
      // op: Rs32
7464
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7465
0
      op &= UINT64_C(31);
7466
0
      op <<= 16;
7467
0
      Value |= op;
7468
      // op: Rx32
7469
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7470
0
      op &= UINT64_C(31);
7471
0
      Value |= op;
7472
0
      break;
7473
0
    }
7474
0
    case Hexagon::L2_ploadrdf_io:
7475
0
    case Hexagon::L2_ploadrdfnew_io:
7476
0
    case Hexagon::L2_ploadrdt_io:
7477
0
    case Hexagon::L2_ploadrdtnew_io: {
7478
      // op: Ii
7479
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7480
0
      op &= UINT64_C(504);
7481
0
      op <<= 2;
7482
0
      Value |= op;
7483
      // op: Pt4
7484
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7485
0
      op &= UINT64_C(3);
7486
0
      op <<= 11;
7487
0
      Value |= op;
7488
      // op: Rs32
7489
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7490
0
      op &= UINT64_C(31);
7491
0
      op <<= 16;
7492
0
      Value |= op;
7493
      // op: Rdd32
7494
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7495
0
      op &= UINT64_C(31);
7496
0
      Value |= op;
7497
0
      break;
7498
0
    }
7499
0
    case Hexagon::S2_pstorerinewf_pi:
7500
0
    case Hexagon::S2_pstorerinewfnew_pi:
7501
0
    case Hexagon::S2_pstorerinewt_pi:
7502
0
    case Hexagon::S2_pstorerinewtnew_pi: {
7503
      // op: Ii
7504
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7505
0
      op &= UINT64_C(60);
7506
0
      op <<= 1;
7507
0
      Value |= op;
7508
      // op: Pv4
7509
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7510
0
      op &= UINT64_C(3);
7511
0
      Value |= op;
7512
      // op: Nt8
7513
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7514
0
      op &= UINT64_C(7);
7515
0
      op <<= 8;
7516
0
      Value |= op;
7517
      // op: Rx32
7518
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7519
0
      op &= UINT64_C(31);
7520
0
      op <<= 16;
7521
0
      Value |= op;
7522
0
      break;
7523
0
    }
7524
0
    case Hexagon::S2_pstorerif_pi:
7525
0
    case Hexagon::S2_pstorerifnew_pi:
7526
0
    case Hexagon::S2_pstorerit_pi:
7527
0
    case Hexagon::S2_pstoreritnew_pi: {
7528
      // op: Ii
7529
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7530
0
      op &= UINT64_C(60);
7531
0
      op <<= 1;
7532
0
      Value |= op;
7533
      // op: Pv4
7534
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7535
0
      op &= UINT64_C(3);
7536
0
      Value |= op;
7537
      // op: Rt32
7538
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7539
0
      op &= UINT64_C(31);
7540
0
      op <<= 8;
7541
0
      Value |= op;
7542
      // op: Rx32
7543
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7544
0
      op &= UINT64_C(31);
7545
0
      op <<= 16;
7546
0
      Value |= op;
7547
0
      break;
7548
0
    }
7549
0
    case Hexagon::L2_loadri_pci: {
7550
      // op: Ii
7551
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7552
0
      op &= UINT64_C(60);
7553
0
      op <<= 3;
7554
0
      Value |= op;
7555
      // op: Mu2
7556
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7557
0
      op &= UINT64_C(1);
7558
0
      op <<= 13;
7559
0
      Value |= op;
7560
      // op: Rd32
7561
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7562
0
      op &= UINT64_C(31);
7563
0
      Value |= op;
7564
      // op: Rx32
7565
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7566
0
      op &= UINT64_C(31);
7567
0
      op <<= 16;
7568
0
      Value |= op;
7569
0
      break;
7570
0
    }
7571
0
    case Hexagon::L2_loadbsw4_pci:
7572
0
    case Hexagon::L2_loadbzw4_pci: {
7573
      // op: Ii
7574
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7575
0
      op &= UINT64_C(60);
7576
0
      op <<= 3;
7577
0
      Value |= op;
7578
      // op: Mu2
7579
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7580
0
      op &= UINT64_C(1);
7581
0
      op <<= 13;
7582
0
      Value |= op;
7583
      // op: Rdd32
7584
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7585
0
      op &= UINT64_C(31);
7586
0
      Value |= op;
7587
      // op: Rx32
7588
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7589
0
      op &= UINT64_C(31);
7590
0
      op <<= 16;
7591
0
      Value |= op;
7592
0
      break;
7593
0
    }
7594
0
    case Hexagon::L2_loadri_pi: {
7595
      // op: Ii
7596
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7597
0
      op &= UINT64_C(60);
7598
0
      op <<= 3;
7599
0
      Value |= op;
7600
      // op: Rd32
7601
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7602
0
      op &= UINT64_C(31);
7603
0
      Value |= op;
7604
      // op: Rx32
7605
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7606
0
      op &= UINT64_C(31);
7607
0
      op <<= 16;
7608
0
      Value |= op;
7609
0
      break;
7610
0
    }
7611
0
    case Hexagon::L2_loadbsw4_pi:
7612
0
    case Hexagon::L2_loadbzw4_pi: {
7613
      // op: Ii
7614
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7615
0
      op &= UINT64_C(60);
7616
0
      op <<= 3;
7617
0
      Value |= op;
7618
      // op: Rdd32
7619
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7620
0
      op &= UINT64_C(31);
7621
0
      Value |= op;
7622
      // op: Rx32
7623
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7624
0
      op &= UINT64_C(31);
7625
0
      op <<= 16;
7626
0
      Value |= op;
7627
0
      break;
7628
0
    }
7629
0
    case Hexagon::L2_ploadrbf_io:
7630
0
    case Hexagon::L2_ploadrbfnew_io:
7631
0
    case Hexagon::L2_ploadrbt_io:
7632
0
    case Hexagon::L2_ploadrbtnew_io:
7633
0
    case Hexagon::L2_ploadrubf_io:
7634
0
    case Hexagon::L2_ploadrubfnew_io:
7635
0
    case Hexagon::L2_ploadrubt_io:
7636
0
    case Hexagon::L2_ploadrubtnew_io: {
7637
      // op: Ii
7638
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7639
0
      op &= UINT64_C(63);
7640
0
      op <<= 5;
7641
0
      Value |= op;
7642
      // op: Pt4
7643
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7644
0
      op &= UINT64_C(3);
7645
0
      op <<= 11;
7646
0
      Value |= op;
7647
      // op: Rs32
7648
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7649
0
      op &= UINT64_C(31);
7650
0
      op <<= 16;
7651
0
      Value |= op;
7652
      // op: Rd32
7653
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7654
0
      op &= UINT64_C(31);
7655
0
      Value |= op;
7656
0
      break;
7657
0
    }
7658
0
    case Hexagon::S2_insertp: {
7659
      // op: Ii
7660
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7661
0
      op &= UINT64_C(63);
7662
0
      op <<= 8;
7663
0
      Value |= op;
7664
      // op: II
7665
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7666
0
      Value |= (op & UINT64_C(56)) << 18;
7667
0
      Value |= (op & UINT64_C(7)) << 5;
7668
      // op: Rss32
7669
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7670
0
      op &= UINT64_C(31);
7671
0
      op <<= 16;
7672
0
      Value |= op;
7673
      // op: Rxx32
7674
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7675
0
      op &= UINT64_C(31);
7676
0
      Value |= op;
7677
0
      break;
7678
0
    }
7679
0
    case Hexagon::S2_asl_i_p_acc:
7680
0
    case Hexagon::S2_asl_i_p_and:
7681
0
    case Hexagon::S2_asl_i_p_nac:
7682
0
    case Hexagon::S2_asl_i_p_or:
7683
0
    case Hexagon::S2_asl_i_p_xacc:
7684
0
    case Hexagon::S2_asr_i_p_acc:
7685
0
    case Hexagon::S2_asr_i_p_and:
7686
0
    case Hexagon::S2_asr_i_p_nac:
7687
0
    case Hexagon::S2_asr_i_p_or:
7688
0
    case Hexagon::S2_lsr_i_p_acc:
7689
0
    case Hexagon::S2_lsr_i_p_and:
7690
0
    case Hexagon::S2_lsr_i_p_nac:
7691
0
    case Hexagon::S2_lsr_i_p_or:
7692
0
    case Hexagon::S2_lsr_i_p_xacc:
7693
0
    case Hexagon::S6_rol_i_p_acc:
7694
0
    case Hexagon::S6_rol_i_p_and:
7695
0
    case Hexagon::S6_rol_i_p_nac:
7696
0
    case Hexagon::S6_rol_i_p_or:
7697
0
    case Hexagon::S6_rol_i_p_xacc: {
7698
      // op: Ii
7699
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7700
0
      op &= UINT64_C(63);
7701
0
      op <<= 8;
7702
0
      Value |= op;
7703
      // op: Rss32
7704
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7705
0
      op &= UINT64_C(31);
7706
0
      op <<= 16;
7707
0
      Value |= op;
7708
      // op: Rxx32
7709
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7710
0
      op &= UINT64_C(31);
7711
0
      Value |= op;
7712
0
      break;
7713
0
    }
7714
0
    case Hexagon::S2_vspliceib: {
7715
      // op: Ii
7716
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7717
0
      op &= UINT64_C(7);
7718
0
      op <<= 5;
7719
0
      Value |= op;
7720
      // op: Rss32
7721
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7722
0
      op &= UINT64_C(31);
7723
0
      op <<= 16;
7724
0
      Value |= op;
7725
      // op: Rtt32
7726
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7727
0
      op &= UINT64_C(31);
7728
0
      op <<= 8;
7729
0
      Value |= op;
7730
      // op: Rdd32
7731
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7732
0
      op &= UINT64_C(31);
7733
0
      Value |= op;
7734
0
      break;
7735
0
    }
7736
0
    case Hexagon::S2_addasl_rrri: {
7737
      // op: Ii
7738
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7739
0
      op &= UINT64_C(7);
7740
0
      op <<= 5;
7741
0
      Value |= op;
7742
      // op: Rt32
7743
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7744
0
      op &= UINT64_C(31);
7745
0
      op <<= 8;
7746
0
      Value |= op;
7747
      // op: Rs32
7748
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7749
0
      op &= UINT64_C(31);
7750
0
      op <<= 16;
7751
0
      Value |= op;
7752
      // op: Rd32
7753
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7754
0
      op &= UINT64_C(31);
7755
0
      Value |= op;
7756
0
      break;
7757
0
    }
7758
0
    case Hexagon::S2_valignib: {
7759
      // op: Ii
7760
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7761
0
      op &= UINT64_C(7);
7762
0
      op <<= 5;
7763
0
      Value |= op;
7764
      // op: Rtt32
7765
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7766
0
      op &= UINT64_C(31);
7767
0
      op <<= 8;
7768
0
      Value |= op;
7769
      // op: Rss32
7770
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7771
0
      op &= UINT64_C(31);
7772
0
      op <<= 16;
7773
0
      Value |= op;
7774
      // op: Rdd32
7775
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7776
0
      op &= UINT64_C(31);
7777
0
      Value |= op;
7778
0
      break;
7779
0
    }
7780
0
    case Hexagon::V6_valignbi:
7781
0
    case Hexagon::V6_vlalignbi:
7782
0
    case Hexagon::V6_vlutvvbi: {
7783
      // op: Ii
7784
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7785
0
      op &= UINT64_C(7);
7786
0
      op <<= 5;
7787
0
      Value |= op;
7788
      // op: Vu32
7789
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7790
0
      op &= UINT64_C(31);
7791
0
      op <<= 8;
7792
0
      Value |= op;
7793
      // op: Vv32
7794
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7795
0
      op &= UINT64_C(31);
7796
0
      op <<= 16;
7797
0
      Value |= op;
7798
      // op: Vd32
7799
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7800
0
      op &= UINT64_C(31);
7801
0
      Value |= op;
7802
0
      break;
7803
0
    }
7804
0
    case Hexagon::V6_vlutvwhi: {
7805
      // op: Ii
7806
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7807
0
      op &= UINT64_C(7);
7808
0
      op <<= 5;
7809
0
      Value |= op;
7810
      // op: Vu32
7811
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7812
0
      op &= UINT64_C(31);
7813
0
      op <<= 8;
7814
0
      Value |= op;
7815
      // op: Vv32
7816
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7817
0
      op &= UINT64_C(31);
7818
0
      op <<= 16;
7819
0
      Value |= op;
7820
      // op: Vdd32
7821
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7822
0
      op &= UINT64_C(31);
7823
0
      Value |= op;
7824
0
      break;
7825
0
    }
7826
0
    case Hexagon::V6_vS32b_new_npred_pi:
7827
0
    case Hexagon::V6_vS32b_new_pred_pi:
7828
0
    case Hexagon::V6_vS32b_nt_new_npred_pi:
7829
0
    case Hexagon::V6_vS32b_nt_new_pred_pi: {
7830
      // op: Ii
7831
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7832
0
      op &= UINT64_C(7);
7833
0
      op <<= 8;
7834
0
      Value |= op;
7835
      // op: Pv4
7836
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7837
0
      op &= UINT64_C(3);
7838
0
      op <<= 11;
7839
0
      Value |= op;
7840
      // op: Os8
7841
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7842
0
      op &= UINT64_C(7);
7843
0
      Value |= op;
7844
      // op: Rx32
7845
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7846
0
      op &= UINT64_C(31);
7847
0
      op <<= 16;
7848
0
      Value |= op;
7849
0
      break;
7850
0
    }
7851
0
    case Hexagon::V6_zLd_pred_pi: {
7852
      // op: Ii
7853
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7854
0
      op &= UINT64_C(7);
7855
0
      op <<= 8;
7856
0
      Value |= op;
7857
      // op: Pv4
7858
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7859
0
      op &= UINT64_C(3);
7860
0
      op <<= 11;
7861
0
      Value |= op;
7862
      // op: Rx32
7863
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7864
0
      op &= UINT64_C(31);
7865
0
      op <<= 16;
7866
0
      Value |= op;
7867
0
      break;
7868
0
    }
7869
0
    case Hexagon::V6_vS32Ub_npred_pi:
7870
0
    case Hexagon::V6_vS32Ub_pred_pi:
7871
0
    case Hexagon::V6_vS32b_npred_pi:
7872
0
    case Hexagon::V6_vS32b_nt_npred_pi:
7873
0
    case Hexagon::V6_vS32b_nt_pred_pi:
7874
0
    case Hexagon::V6_vS32b_pred_pi: {
7875
      // op: Ii
7876
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7877
0
      op &= UINT64_C(7);
7878
0
      op <<= 8;
7879
0
      Value |= op;
7880
      // op: Pv4
7881
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7882
0
      op &= UINT64_C(3);
7883
0
      op <<= 11;
7884
0
      Value |= op;
7885
      // op: Vs32
7886
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7887
0
      op &= UINT64_C(31);
7888
0
      Value |= op;
7889
      // op: Rx32
7890
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7891
0
      op &= UINT64_C(31);
7892
0
      op <<= 16;
7893
0
      Value |= op;
7894
0
      break;
7895
0
    }
7896
0
    case Hexagon::V6_vS32b_nqpred_pi:
7897
0
    case Hexagon::V6_vS32b_nt_nqpred_pi:
7898
0
    case Hexagon::V6_vS32b_nt_qpred_pi:
7899
0
    case Hexagon::V6_vS32b_qpred_pi: {
7900
      // op: Ii
7901
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7902
0
      op &= UINT64_C(7);
7903
0
      op <<= 8;
7904
0
      Value |= op;
7905
      // op: Qv4
7906
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7907
0
      op &= UINT64_C(3);
7908
0
      op <<= 11;
7909
0
      Value |= op;
7910
      // op: Vs32
7911
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7912
0
      op &= UINT64_C(31);
7913
0
      Value |= op;
7914
      // op: Rx32
7915
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7916
0
      op &= UINT64_C(31);
7917
0
      op <<= 16;
7918
0
      Value |= op;
7919
0
      break;
7920
0
    }
7921
0
    case Hexagon::V6_vL32Ub_pi:
7922
0
    case Hexagon::V6_vL32b_cur_pi:
7923
0
    case Hexagon::V6_vL32b_nt_cur_pi:
7924
0
    case Hexagon::V6_vL32b_nt_pi:
7925
0
    case Hexagon::V6_vL32b_nt_tmp_pi:
7926
0
    case Hexagon::V6_vL32b_pi:
7927
0
    case Hexagon::V6_vL32b_tmp_pi: {
7928
      // op: Ii
7929
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7930
0
      op &= UINT64_C(7);
7931
0
      op <<= 8;
7932
0
      Value |= op;
7933
      // op: Vd32
7934
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7935
0
      op &= UINT64_C(31);
7936
0
      Value |= op;
7937
      // op: Rx32
7938
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7939
0
      op &= UINT64_C(31);
7940
0
      op <<= 16;
7941
0
      Value |= op;
7942
0
      break;
7943
0
    }
7944
0
    case Hexagon::S4_vrcrotate_acc: {
7945
      // op: Ii
7946
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7947
0
      Value |= (op & UINT64_C(2)) << 12;
7948
0
      Value |= (op & UINT64_C(1)) << 5;
7949
      // op: Rss32
7950
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7951
0
      op &= UINT64_C(31);
7952
0
      op <<= 16;
7953
0
      Value |= op;
7954
      // op: Rt32
7955
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7956
0
      op &= UINT64_C(31);
7957
0
      op <<= 8;
7958
0
      Value |= op;
7959
      // op: Rxx32
7960
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7961
0
      op &= UINT64_C(31);
7962
0
      Value |= op;
7963
0
      break;
7964
0
    }
7965
0
    case Hexagon::L4_ploadrbf_rr:
7966
0
    case Hexagon::L4_ploadrbfnew_rr:
7967
0
    case Hexagon::L4_ploadrbt_rr:
7968
0
    case Hexagon::L4_ploadrbtnew_rr:
7969
0
    case Hexagon::L4_ploadrhf_rr:
7970
0
    case Hexagon::L4_ploadrhfnew_rr:
7971
0
    case Hexagon::L4_ploadrht_rr:
7972
0
    case Hexagon::L4_ploadrhtnew_rr:
7973
0
    case Hexagon::L4_ploadrif_rr:
7974
0
    case Hexagon::L4_ploadrifnew_rr:
7975
0
    case Hexagon::L4_ploadrit_rr:
7976
0
    case Hexagon::L4_ploadritnew_rr:
7977
0
    case Hexagon::L4_ploadrubf_rr:
7978
0
    case Hexagon::L4_ploadrubfnew_rr:
7979
0
    case Hexagon::L4_ploadrubt_rr:
7980
0
    case Hexagon::L4_ploadrubtnew_rr:
7981
0
    case Hexagon::L4_ploadruhf_rr:
7982
0
    case Hexagon::L4_ploadruhfnew_rr:
7983
0
    case Hexagon::L4_ploadruht_rr:
7984
0
    case Hexagon::L4_ploadruhtnew_rr: {
7985
      // op: Ii
7986
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7987
0
      Value |= (op & UINT64_C(2)) << 12;
7988
0
      Value |= (op & UINT64_C(1)) << 7;
7989
      // op: Pv4
7990
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7991
0
      op &= UINT64_C(3);
7992
0
      op <<= 5;
7993
0
      Value |= op;
7994
      // op: Rs32
7995
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7996
0
      op &= UINT64_C(31);
7997
0
      op <<= 16;
7998
0
      Value |= op;
7999
      // op: Rt32
8000
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8001
0
      op &= UINT64_C(31);
8002
0
      op <<= 8;
8003
0
      Value |= op;
8004
      // op: Rd32
8005
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8006
0
      op &= UINT64_C(31);
8007
0
      Value |= op;
8008
0
      break;
8009
0
    }
8010
0
    case Hexagon::L4_ploadrdf_rr:
8011
0
    case Hexagon::L4_ploadrdfnew_rr:
8012
0
    case Hexagon::L4_ploadrdt_rr:
8013
0
    case Hexagon::L4_ploadrdtnew_rr: {
8014
      // op: Ii
8015
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8016
0
      Value |= (op & UINT64_C(2)) << 12;
8017
0
      Value |= (op & UINT64_C(1)) << 7;
8018
      // op: Pv4
8019
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8020
0
      op &= UINT64_C(3);
8021
0
      op <<= 5;
8022
0
      Value |= op;
8023
      // op: Rs32
8024
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8025
0
      op &= UINT64_C(31);
8026
0
      op <<= 16;
8027
0
      Value |= op;
8028
      // op: Rt32
8029
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8030
0
      op &= UINT64_C(31);
8031
0
      op <<= 8;
8032
0
      Value |= op;
8033
      // op: Rdd32
8034
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8035
0
      op &= UINT64_C(31);
8036
0
      Value |= op;
8037
0
      break;
8038
0
    }
8039
0
    case Hexagon::V6_vrmpybusi_acc:
8040
0
    case Hexagon::V6_vrmpyubi_acc:
8041
0
    case Hexagon::V6_vrsadubi_acc: {
8042
      // op: Ii
8043
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8044
0
      op &= UINT64_C(1);
8045
0
      op <<= 5;
8046
0
      Value |= op;
8047
      // op: Vuu32
8048
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8049
0
      op &= UINT64_C(31);
8050
0
      op <<= 8;
8051
0
      Value |= op;
8052
      // op: Rt32
8053
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8054
0
      op &= UINT64_C(31);
8055
0
      op <<= 16;
8056
0
      Value |= op;
8057
      // op: Vxx32
8058
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8059
0
      op &= UINT64_C(31);
8060
0
      Value |= op;
8061
0
      break;
8062
0
    }
8063
0
    case Hexagon::L2_ploadrdf_pi:
8064
0
    case Hexagon::L2_ploadrdfnew_pi:
8065
0
    case Hexagon::L2_ploadrdt_pi:
8066
0
    case Hexagon::L2_ploadrdtnew_pi: {
8067
      // op: Ii
8068
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8069
0
      op &= UINT64_C(120);
8070
0
      op <<= 2;
8071
0
      Value |= op;
8072
      // op: Pt4
8073
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8074
0
      op &= UINT64_C(3);
8075
0
      op <<= 9;
8076
0
      Value |= op;
8077
      // op: Rdd32
8078
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8079
0
      op &= UINT64_C(31);
8080
0
      Value |= op;
8081
      // op: Rx32
8082
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8083
0
      op &= UINT64_C(31);
8084
0
      op <<= 16;
8085
0
      Value |= op;
8086
0
      break;
8087
0
    }
8088
0
    case Hexagon::L2_loadalignb_pci: {
8089
      // op: Ii
8090
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8091
0
      op &= UINT64_C(15);
8092
0
      op <<= 5;
8093
0
      Value |= op;
8094
      // op: Mu2
8095
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
8096
0
      op &= UINT64_C(1);
8097
0
      op <<= 13;
8098
0
      Value |= op;
8099
      // op: Ryy32
8100
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8101
0
      op &= UINT64_C(31);
8102
0
      Value |= op;
8103
      // op: Rx32
8104
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8105
0
      op &= UINT64_C(31);
8106
0
      op <<= 16;
8107
0
      Value |= op;
8108
0
      break;
8109
0
    }
8110
0
    case Hexagon::L2_ploadrbf_pi:
8111
0
    case Hexagon::L2_ploadrbfnew_pi:
8112
0
    case Hexagon::L2_ploadrbt_pi:
8113
0
    case Hexagon::L2_ploadrbtnew_pi:
8114
0
    case Hexagon::L2_ploadrubf_pi:
8115
0
    case Hexagon::L2_ploadrubfnew_pi:
8116
0
    case Hexagon::L2_ploadrubt_pi:
8117
0
    case Hexagon::L2_ploadrubtnew_pi: {
8118
      // op: Ii
8119
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8120
0
      op &= UINT64_C(15);
8121
0
      op <<= 5;
8122
0
      Value |= op;
8123
      // op: Pt4
8124
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8125
0
      op &= UINT64_C(3);
8126
0
      op <<= 9;
8127
0
      Value |= op;
8128
      // op: Rd32
8129
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8130
0
      op &= UINT64_C(31);
8131
0
      Value |= op;
8132
      // op: Rx32
8133
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8134
0
      op &= UINT64_C(31);
8135
0
      op <<= 16;
8136
0
      Value |= op;
8137
0
      break;
8138
0
    }
8139
0
    case Hexagon::L2_loadalignb_pi: {
8140
      // op: Ii
8141
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8142
0
      op &= UINT64_C(15);
8143
0
      op <<= 5;
8144
0
      Value |= op;
8145
      // op: Ryy32
8146
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8147
0
      op &= UINT64_C(31);
8148
0
      Value |= op;
8149
      // op: Rx32
8150
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8151
0
      op &= UINT64_C(31);
8152
0
      op <<= 16;
8153
0
      Value |= op;
8154
0
      break;
8155
0
    }
8156
0
    case Hexagon::V6_v6mpyhubs10_vxx:
8157
0
    case Hexagon::V6_v6mpyvubs10_vxx: {
8158
      // op: Ii
8159
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8160
0
      op &= UINT64_C(3);
8161
0
      op <<= 5;
8162
0
      Value |= op;
8163
      // op: Vuu32
8164
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8165
0
      op &= UINT64_C(31);
8166
0
      op <<= 8;
8167
0
      Value |= op;
8168
      // op: Vvv32
8169
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8170
0
      op &= UINT64_C(31);
8171
0
      op <<= 16;
8172
0
      Value |= op;
8173
      // op: Vxx32
8174
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8175
0
      op &= UINT64_C(31);
8176
0
      Value |= op;
8177
0
      break;
8178
0
    }
8179
0
    case Hexagon::L2_loadalignh_pci: {
8180
      // op: Ii
8181
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8182
0
      op &= UINT64_C(30);
8183
0
      op <<= 4;
8184
0
      Value |= op;
8185
      // op: Mu2
8186
0
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
8187
0
      op &= UINT64_C(1);
8188
0
      op <<= 13;
8189
0
      Value |= op;
8190
      // op: Ryy32
8191
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8192
0
      op &= UINT64_C(31);
8193
0
      Value |= op;
8194
      // op: Rx32
8195
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8196
0
      op &= UINT64_C(31);
8197
0
      op <<= 16;
8198
0
      Value |= op;
8199
0
      break;
8200
0
    }
8201
0
    case Hexagon::L2_ploadrhf_pi:
8202
0
    case Hexagon::L2_ploadrhfnew_pi:
8203
0
    case Hexagon::L2_ploadrht_pi:
8204
0
    case Hexagon::L2_ploadrhtnew_pi:
8205
0
    case Hexagon::L2_ploadruhf_pi:
8206
0
    case Hexagon::L2_ploadruhfnew_pi:
8207
0
    case Hexagon::L2_ploadruht_pi:
8208
0
    case Hexagon::L2_ploadruhtnew_pi: {
8209
      // op: Ii
8210
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8211
0
      op &= UINT64_C(30);
8212
0
      op <<= 4;
8213
0
      Value |= op;
8214
      // op: Pt4
8215
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8216
0
      op &= UINT64_C(3);
8217
0
      op <<= 9;
8218
0
      Value |= op;
8219
      // op: Rd32
8220
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8221
0
      op &= UINT64_C(31);
8222
0
      Value |= op;
8223
      // op: Rx32
8224
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8225
0
      op &= UINT64_C(31);
8226
0
      op <<= 16;
8227
0
      Value |= op;
8228
0
      break;
8229
0
    }
8230
0
    case Hexagon::L2_loadalignh_pi: {
8231
      // op: Ii
8232
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8233
0
      op &= UINT64_C(30);
8234
0
      op <<= 4;
8235
0
      Value |= op;
8236
      // op: Ryy32
8237
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8238
0
      op &= UINT64_C(31);
8239
0
      Value |= op;
8240
      // op: Rx32
8241
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8242
0
      op &= UINT64_C(31);
8243
0
      op <<= 16;
8244
0
      Value |= op;
8245
0
      break;
8246
0
    }
8247
0
    case Hexagon::L2_ploadrif_pi:
8248
0
    case Hexagon::L2_ploadrifnew_pi:
8249
0
    case Hexagon::L2_ploadrit_pi:
8250
0
    case Hexagon::L2_ploadritnew_pi: {
8251
      // op: Ii
8252
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8253
0
      op &= UINT64_C(60);
8254
0
      op <<= 3;
8255
0
      Value |= op;
8256
      // op: Pt4
8257
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8258
0
      op &= UINT64_C(3);
8259
0
      op <<= 9;
8260
0
      Value |= op;
8261
      // op: Rd32
8262
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8263
0
      op &= UINT64_C(31);
8264
0
      Value |= op;
8265
      // op: Rx32
8266
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8267
0
      op &= UINT64_C(31);
8268
0
      op <<= 16;
8269
0
      Value |= op;
8270
0
      break;
8271
0
    }
8272
0
    case Hexagon::V6_vlutvvb_oracci: {
8273
      // op: Ii
8274
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8275
0
      op &= UINT64_C(7);
8276
0
      op <<= 5;
8277
0
      Value |= op;
8278
      // op: Vu32
8279
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8280
0
      op &= UINT64_C(31);
8281
0
      op <<= 8;
8282
0
      Value |= op;
8283
      // op: Vv32
8284
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8285
0
      op &= UINT64_C(31);
8286
0
      op <<= 16;
8287
0
      Value |= op;
8288
      // op: Vx32
8289
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8290
0
      op &= UINT64_C(31);
8291
0
      Value |= op;
8292
0
      break;
8293
0
    }
8294
0
    case Hexagon::V6_vlutvwh_oracci: {
8295
      // op: Ii
8296
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8297
0
      op &= UINT64_C(7);
8298
0
      op <<= 5;
8299
0
      Value |= op;
8300
      // op: Vu32
8301
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8302
0
      op &= UINT64_C(31);
8303
0
      op <<= 8;
8304
0
      Value |= op;
8305
      // op: Vv32
8306
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8307
0
      op &= UINT64_C(31);
8308
0
      op <<= 16;
8309
0
      Value |= op;
8310
      // op: Vxx32
8311
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8312
0
      op &= UINT64_C(31);
8313
0
      Value |= op;
8314
0
      break;
8315
0
    }
8316
0
    case Hexagon::V6_vL32b_cur_npred_pi:
8317
0
    case Hexagon::V6_vL32b_cur_pred_pi:
8318
0
    case Hexagon::V6_vL32b_npred_pi:
8319
0
    case Hexagon::V6_vL32b_nt_cur_npred_pi:
8320
0
    case Hexagon::V6_vL32b_nt_cur_pred_pi:
8321
0
    case Hexagon::V6_vL32b_nt_npred_pi:
8322
0
    case Hexagon::V6_vL32b_nt_pred_pi:
8323
0
    case Hexagon::V6_vL32b_nt_tmp_npred_pi:
8324
0
    case Hexagon::V6_vL32b_nt_tmp_pred_pi:
8325
0
    case Hexagon::V6_vL32b_pred_pi:
8326
0
    case Hexagon::V6_vL32b_tmp_npred_pi:
8327
0
    case Hexagon::V6_vL32b_tmp_pred_pi: {
8328
      // op: Ii
8329
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8330
0
      op &= UINT64_C(7);
8331
0
      op <<= 8;
8332
0
      Value |= op;
8333
      // op: Pv4
8334
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8335
0
      op &= UINT64_C(3);
8336
0
      op <<= 11;
8337
0
      Value |= op;
8338
      // op: Vd32
8339
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8340
0
      op &= UINT64_C(31);
8341
0
      Value |= op;
8342
      // op: Rx32
8343
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8344
0
      op &= UINT64_C(31);
8345
0
      op <<= 16;
8346
0
      Value |= op;
8347
0
      break;
8348
0
    }
8349
0
    case Hexagon::S2_storerbnew_pbr:
8350
0
    case Hexagon::S2_storerbnew_pcr:
8351
0
    case Hexagon::S2_storerbnew_pr:
8352
0
    case Hexagon::S2_storerhnew_pbr:
8353
0
    case Hexagon::S2_storerhnew_pcr:
8354
0
    case Hexagon::S2_storerhnew_pr:
8355
0
    case Hexagon::S2_storerinew_pbr:
8356
0
    case Hexagon::S2_storerinew_pcr:
8357
0
    case Hexagon::S2_storerinew_pr: {
8358
      // op: Mu2
8359
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8360
0
      op &= UINT64_C(1);
8361
0
      op <<= 13;
8362
0
      Value |= op;
8363
      // op: Nt8
8364
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8365
0
      op &= UINT64_C(7);
8366
0
      op <<= 8;
8367
0
      Value |= op;
8368
      // op: Rx32
8369
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8370
0
      op &= UINT64_C(31);
8371
0
      op <<= 16;
8372
0
      Value |= op;
8373
0
      break;
8374
0
    }
8375
0
    case Hexagon::V6_vS32b_new_ppu:
8376
0
    case Hexagon::V6_vS32b_nt_new_ppu: {
8377
      // op: Mu2
8378
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8379
0
      op &= UINT64_C(1);
8380
0
      op <<= 13;
8381
0
      Value |= op;
8382
      // op: Os8
8383
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8384
0
      op &= UINT64_C(7);
8385
0
      Value |= op;
8386
      // op: Rx32
8387
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8388
0
      op &= UINT64_C(31);
8389
0
      op <<= 16;
8390
0
      Value |= op;
8391
0
      break;
8392
0
    }
8393
0
    case Hexagon::S2_storerb_pbr:
8394
0
    case Hexagon::S2_storerb_pcr:
8395
0
    case Hexagon::S2_storerb_pr:
8396
0
    case Hexagon::S2_storerf_pbr:
8397
0
    case Hexagon::S2_storerf_pcr:
8398
0
    case Hexagon::S2_storerf_pr:
8399
0
    case Hexagon::S2_storerh_pbr:
8400
0
    case Hexagon::S2_storerh_pcr:
8401
0
    case Hexagon::S2_storerh_pr:
8402
0
    case Hexagon::S2_storeri_pbr:
8403
0
    case Hexagon::S2_storeri_pcr:
8404
0
    case Hexagon::S2_storeri_pr: {
8405
      // op: Mu2
8406
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8407
0
      op &= UINT64_C(1);
8408
0
      op <<= 13;
8409
0
      Value |= op;
8410
      // op: Rt32
8411
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8412
0
      op &= UINT64_C(31);
8413
0
      op <<= 8;
8414
0
      Value |= op;
8415
      // op: Rx32
8416
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8417
0
      op &= UINT64_C(31);
8418
0
      op <<= 16;
8419
0
      Value |= op;
8420
0
      break;
8421
0
    }
8422
0
    case Hexagon::S2_storerd_pbr:
8423
0
    case Hexagon::S2_storerd_pcr:
8424
0
    case Hexagon::S2_storerd_pr: {
8425
      // op: Mu2
8426
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8427
0
      op &= UINT64_C(1);
8428
0
      op <<= 13;
8429
0
      Value |= op;
8430
      // op: Rtt32
8431
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8432
0
      op &= UINT64_C(31);
8433
0
      op <<= 8;
8434
0
      Value |= op;
8435
      // op: Rx32
8436
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8437
0
      op &= UINT64_C(31);
8438
0
      op <<= 16;
8439
0
      Value |= op;
8440
0
      break;
8441
0
    }
8442
0
    case Hexagon::V6_vS32b_srls_ppu:
8443
0
    case Hexagon::V6_zLd_ppu: {
8444
      // op: Mu2
8445
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8446
0
      op &= UINT64_C(1);
8447
0
      op <<= 13;
8448
0
      Value |= op;
8449
      // op: Rx32
8450
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8451
0
      op &= UINT64_C(31);
8452
0
      op <<= 16;
8453
0
      Value |= op;
8454
0
      break;
8455
0
    }
8456
0
    case Hexagon::V6_vS32Ub_ppu:
8457
0
    case Hexagon::V6_vS32b_nt_ppu:
8458
0
    case Hexagon::V6_vS32b_ppu: {
8459
      // op: Mu2
8460
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8461
0
      op &= UINT64_C(1);
8462
0
      op <<= 13;
8463
0
      Value |= op;
8464
      // op: Vs32
8465
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8466
0
      op &= UINT64_C(31);
8467
0
      Value |= op;
8468
      // op: Rx32
8469
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8470
0
      op &= UINT64_C(31);
8471
0
      op <<= 16;
8472
0
      Value |= op;
8473
0
      break;
8474
0
    }
8475
0
    case Hexagon::L2_loadbsw2_pbr:
8476
0
    case Hexagon::L2_loadbsw2_pcr:
8477
0
    case Hexagon::L2_loadbsw2_pr:
8478
0
    case Hexagon::L2_loadbzw2_pbr:
8479
0
    case Hexagon::L2_loadbzw2_pcr:
8480
0
    case Hexagon::L2_loadbzw2_pr:
8481
0
    case Hexagon::L2_loadrb_pbr:
8482
0
    case Hexagon::L2_loadrb_pcr:
8483
0
    case Hexagon::L2_loadrb_pr:
8484
0
    case Hexagon::L2_loadrh_pbr:
8485
0
    case Hexagon::L2_loadrh_pcr:
8486
0
    case Hexagon::L2_loadrh_pr:
8487
0
    case Hexagon::L2_loadri_pbr:
8488
0
    case Hexagon::L2_loadri_pcr:
8489
0
    case Hexagon::L2_loadri_pr:
8490
0
    case Hexagon::L2_loadrub_pbr:
8491
0
    case Hexagon::L2_loadrub_pcr:
8492
0
    case Hexagon::L2_loadrub_pr:
8493
0
    case Hexagon::L2_loadruh_pbr:
8494
0
    case Hexagon::L2_loadruh_pcr:
8495
0
    case Hexagon::L2_loadruh_pr: {
8496
      // op: Mu2
8497
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8498
0
      op &= UINT64_C(1);
8499
0
      op <<= 13;
8500
0
      Value |= op;
8501
      // op: Rd32
8502
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8503
0
      op &= UINT64_C(31);
8504
0
      Value |= op;
8505
      // op: Rx32
8506
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8507
0
      op &= UINT64_C(31);
8508
0
      op <<= 16;
8509
0
      Value |= op;
8510
0
      break;
8511
0
    }
8512
0
    case Hexagon::L2_loadbsw4_pbr:
8513
0
    case Hexagon::L2_loadbsw4_pcr:
8514
0
    case Hexagon::L2_loadbsw4_pr:
8515
0
    case Hexagon::L2_loadbzw4_pbr:
8516
0
    case Hexagon::L2_loadbzw4_pcr:
8517
0
    case Hexagon::L2_loadbzw4_pr:
8518
0
    case Hexagon::L2_loadrd_pbr:
8519
0
    case Hexagon::L2_loadrd_pcr:
8520
0
    case Hexagon::L2_loadrd_pr: {
8521
      // op: Mu2
8522
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8523
0
      op &= UINT64_C(1);
8524
0
      op <<= 13;
8525
0
      Value |= op;
8526
      // op: Rdd32
8527
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8528
0
      op &= UINT64_C(31);
8529
0
      Value |= op;
8530
      // op: Rx32
8531
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8532
0
      op &= UINT64_C(31);
8533
0
      op <<= 16;
8534
0
      Value |= op;
8535
0
      break;
8536
0
    }
8537
0
    case Hexagon::V6_vL32Ub_ppu:
8538
0
    case Hexagon::V6_vL32b_cur_ppu:
8539
0
    case Hexagon::V6_vL32b_nt_cur_ppu:
8540
0
    case Hexagon::V6_vL32b_nt_ppu:
8541
0
    case Hexagon::V6_vL32b_nt_tmp_ppu:
8542
0
    case Hexagon::V6_vL32b_ppu:
8543
0
    case Hexagon::V6_vL32b_tmp_ppu: {
8544
      // op: Mu2
8545
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8546
0
      op &= UINT64_C(1);
8547
0
      op <<= 13;
8548
0
      Value |= op;
8549
      // op: Vd32
8550
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8551
0
      op &= UINT64_C(31);
8552
0
      Value |= op;
8553
      // op: Rx32
8554
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8555
0
      op &= UINT64_C(31);
8556
0
      op <<= 16;
8557
0
      Value |= op;
8558
0
      break;
8559
0
    }
8560
0
    case Hexagon::L2_loadalignb_pbr:
8561
0
    case Hexagon::L2_loadalignb_pcr:
8562
0
    case Hexagon::L2_loadalignb_pr:
8563
0
    case Hexagon::L2_loadalignh_pbr:
8564
0
    case Hexagon::L2_loadalignh_pcr:
8565
0
    case Hexagon::L2_loadalignh_pr: {
8566
      // op: Mu2
8567
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8568
0
      op &= UINT64_C(1);
8569
0
      op <<= 13;
8570
0
      Value |= op;
8571
      // op: Ryy32
8572
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8573
0
      op &= UINT64_C(31);
8574
0
      Value |= op;
8575
      // op: Rx32
8576
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8577
0
      op &= UINT64_C(31);
8578
0
      op <<= 16;
8579
0
      Value |= op;
8580
0
      break;
8581
0
    }
8582
0
    case Hexagon::C2_all8:
8583
0
    case Hexagon::C2_any8:
8584
0
    case Hexagon::C2_not: {
8585
      // op: Ps4
8586
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8587
0
      op &= UINT64_C(3);
8588
0
      op <<= 16;
8589
0
      Value |= op;
8590
      // op: Pd4
8591
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8592
0
      op &= UINT64_C(3);
8593
0
      Value |= op;
8594
0
      break;
8595
0
    }
8596
0
    case Hexagon::C2_xor:
8597
0
    case Hexagon::C4_fastcorner9:
8598
0
    case Hexagon::C4_fastcorner9_not: {
8599
      // op: Ps4
8600
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8601
0
      op &= UINT64_C(3);
8602
0
      op <<= 16;
8603
0
      Value |= op;
8604
      // op: Pt4
8605
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8606
0
      op &= UINT64_C(3);
8607
0
      op <<= 8;
8608
0
      Value |= op;
8609
      // op: Pd4
8610
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8611
0
      op &= UINT64_C(3);
8612
0
      Value |= op;
8613
0
      break;
8614
0
    }
8615
0
    case Hexagon::C4_and_and:
8616
0
    case Hexagon::C4_and_andn:
8617
0
    case Hexagon::C4_and_or:
8618
0
    case Hexagon::C4_and_orn:
8619
0
    case Hexagon::C4_or_and:
8620
0
    case Hexagon::C4_or_andn:
8621
0
    case Hexagon::C4_or_or:
8622
0
    case Hexagon::C4_or_orn: {
8623
      // op: Ps4
8624
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8625
0
      op &= UINT64_C(3);
8626
0
      op <<= 16;
8627
0
      Value |= op;
8628
      // op: Pt4
8629
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8630
0
      op &= UINT64_C(3);
8631
0
      op <<= 8;
8632
0
      Value |= op;
8633
      // op: Pu4
8634
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8635
0
      op &= UINT64_C(3);
8636
0
      op <<= 6;
8637
0
      Value |= op;
8638
      // op: Pd4
8639
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8640
0
      op &= UINT64_C(3);
8641
0
      Value |= op;
8642
0
      break;
8643
0
    }
8644
0
    case Hexagon::C2_vitpack: {
8645
      // op: Ps4
8646
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8647
0
      op &= UINT64_C(3);
8648
0
      op <<= 16;
8649
0
      Value |= op;
8650
      // op: Pt4
8651
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8652
0
      op &= UINT64_C(3);
8653
0
      op <<= 8;
8654
0
      Value |= op;
8655
      // op: Rd32
8656
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8657
0
      op &= UINT64_C(31);
8658
0
      Value |= op;
8659
0
      break;
8660
0
    }
8661
0
    case Hexagon::C2_tfrpr: {
8662
      // op: Ps4
8663
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8664
0
      op &= UINT64_C(3);
8665
0
      op <<= 16;
8666
0
      Value |= op;
8667
      // op: Rd32
8668
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8669
0
      op &= UINT64_C(31);
8670
0
      Value |= op;
8671
0
      break;
8672
0
    }
8673
0
    case Hexagon::V6_vcmov:
8674
0
    case Hexagon::V6_vncmov: {
8675
      // op: Ps4
8676
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8677
0
      op &= UINT64_C(3);
8678
0
      op <<= 5;
8679
0
      Value |= op;
8680
      // op: Vu32
8681
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8682
0
      op &= UINT64_C(31);
8683
0
      op <<= 8;
8684
0
      Value |= op;
8685
      // op: Vd32
8686
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8687
0
      op &= UINT64_C(31);
8688
0
      Value |= op;
8689
0
      break;
8690
0
    }
8691
0
    case Hexagon::V6_vccombine:
8692
0
    case Hexagon::V6_vnccombine: {
8693
      // op: Ps4
8694
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8695
0
      op &= UINT64_C(3);
8696
0
      op <<= 5;
8697
0
      Value |= op;
8698
      // op: Vu32
8699
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8700
0
      op &= UINT64_C(31);
8701
0
      op <<= 8;
8702
0
      Value |= op;
8703
      // op: Vv32
8704
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8705
0
      op &= UINT64_C(31);
8706
0
      op <<= 16;
8707
0
      Value |= op;
8708
      // op: Vdd32
8709
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8710
0
      op &= UINT64_C(31);
8711
0
      Value |= op;
8712
0
      break;
8713
0
    }
8714
0
    case Hexagon::Y2_setimask:
8715
0
    case Hexagon::Y2_setprio: {
8716
      // op: Pt4
8717
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8718
0
      op &= UINT64_C(3);
8719
0
      op <<= 8;
8720
0
      Value |= op;
8721
      // op: Rs32
8722
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8723
0
      op &= UINT64_C(31);
8724
0
      op <<= 16;
8725
0
      Value |= op;
8726
0
      break;
8727
0
    }
8728
0
    case Hexagon::C2_and:
8729
0
    case Hexagon::C2_andn:
8730
0
    case Hexagon::C2_or:
8731
0
    case Hexagon::C2_orn: {
8732
      // op: Pt4
8733
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8734
0
      op &= UINT64_C(3);
8735
0
      op <<= 8;
8736
0
      Value |= op;
8737
      // op: Ps4
8738
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8739
0
      op &= UINT64_C(3);
8740
0
      op <<= 16;
8741
0
      Value |= op;
8742
      // op: Pd4
8743
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8744
0
      op &= UINT64_C(3);
8745
0
      Value |= op;
8746
0
      break;
8747
0
    }
8748
0
    case Hexagon::C2_mask: {
8749
      // op: Pt4
8750
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8751
0
      op &= UINT64_C(3);
8752
0
      op <<= 8;
8753
0
      Value |= op;
8754
      // op: Rdd32
8755
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8756
0
      op &= UINT64_C(31);
8757
0
      Value |= op;
8758
0
      break;
8759
0
    }
8760
0
    case Hexagon::J2_callrf:
8761
0
    case Hexagon::J2_callrt:
8762
0
    case Hexagon::J2_jumprf:
8763
0
    case Hexagon::J2_jumprfnew:
8764
0
    case Hexagon::J2_jumprfnewpt:
8765
0
    case Hexagon::J2_jumprfpt:
8766
0
    case Hexagon::J2_jumprt:
8767
0
    case Hexagon::J2_jumprtnew:
8768
0
    case Hexagon::J2_jumprtnewpt:
8769
0
    case Hexagon::J2_jumprtpt: {
8770
      // op: Pu4
8771
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8772
0
      op &= UINT64_C(3);
8773
0
      op <<= 8;
8774
0
      Value |= op;
8775
      // op: Rs32
8776
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8777
0
      op &= UINT64_C(31);
8778
0
      op <<= 16;
8779
0
      Value |= op;
8780
0
      break;
8781
0
    }
8782
0
    case Hexagon::A2_paddf:
8783
0
    case Hexagon::A2_paddfnew:
8784
0
    case Hexagon::A2_paddt:
8785
0
    case Hexagon::A2_paddtnew:
8786
0
    case Hexagon::A2_pandf:
8787
0
    case Hexagon::A2_pandfnew:
8788
0
    case Hexagon::A2_pandt:
8789
0
    case Hexagon::A2_pandtnew:
8790
0
    case Hexagon::A2_porf:
8791
0
    case Hexagon::A2_porfnew:
8792
0
    case Hexagon::A2_port:
8793
0
    case Hexagon::A2_portnew:
8794
0
    case Hexagon::A2_pxorf:
8795
0
    case Hexagon::A2_pxorfnew:
8796
0
    case Hexagon::A2_pxort:
8797
0
    case Hexagon::A2_pxortnew:
8798
0
    case Hexagon::C2_mux: {
8799
      // op: Pu4
8800
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8801
0
      op &= UINT64_C(3);
8802
0
      op <<= 5;
8803
0
      Value |= op;
8804
      // op: Rs32
8805
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8806
0
      op &= UINT64_C(31);
8807
0
      op <<= 16;
8808
0
      Value |= op;
8809
      // op: Rt32
8810
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8811
0
      op &= UINT64_C(31);
8812
0
      op <<= 8;
8813
0
      Value |= op;
8814
      // op: Rd32
8815
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8816
0
      op &= UINT64_C(31);
8817
0
      Value |= op;
8818
0
      break;
8819
0
    }
8820
0
    case Hexagon::C2_ccombinewf:
8821
0
    case Hexagon::C2_ccombinewnewf:
8822
0
    case Hexagon::C2_ccombinewnewt:
8823
0
    case Hexagon::C2_ccombinewt: {
8824
      // op: Pu4
8825
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8826
0
      op &= UINT64_C(3);
8827
0
      op <<= 5;
8828
0
      Value |= op;
8829
      // op: Rs32
8830
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8831
0
      op &= UINT64_C(31);
8832
0
      op <<= 16;
8833
0
      Value |= op;
8834
      // op: Rt32
8835
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8836
0
      op &= UINT64_C(31);
8837
0
      op <<= 8;
8838
0
      Value |= op;
8839
      // op: Rdd32
8840
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8841
0
      op &= UINT64_C(31);
8842
0
      Value |= op;
8843
0
      break;
8844
0
    }
8845
0
    case Hexagon::C2_vmux: {
8846
      // op: Pu4
8847
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8848
0
      op &= UINT64_C(3);
8849
0
      op <<= 5;
8850
0
      Value |= op;
8851
      // op: Rss32
8852
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8853
0
      op &= UINT64_C(31);
8854
0
      op <<= 16;
8855
0
      Value |= op;
8856
      // op: Rtt32
8857
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8858
0
      op &= UINT64_C(31);
8859
0
      op <<= 8;
8860
0
      Value |= op;
8861
      // op: Rdd32
8862
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8863
0
      op &= UINT64_C(31);
8864
0
      Value |= op;
8865
0
      break;
8866
0
    }
8867
0
    case Hexagon::A2_psubf:
8868
0
    case Hexagon::A2_psubfnew:
8869
0
    case Hexagon::A2_psubt:
8870
0
    case Hexagon::A2_psubtnew: {
8871
      // op: Pu4
8872
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8873
0
      op &= UINT64_C(3);
8874
0
      op <<= 5;
8875
0
      Value |= op;
8876
      // op: Rt32
8877
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8878
0
      op &= UINT64_C(31);
8879
0
      op <<= 8;
8880
0
      Value |= op;
8881
      // op: Rs32
8882
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8883
0
      op &= UINT64_C(31);
8884
0
      op <<= 16;
8885
0
      Value |= op;
8886
      // op: Rd32
8887
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8888
0
      op &= UINT64_C(31);
8889
0
      Value |= op;
8890
0
      break;
8891
0
    }
8892
0
    case Hexagon::A4_paslhf:
8893
0
    case Hexagon::A4_paslhfnew:
8894
0
    case Hexagon::A4_paslht:
8895
0
    case Hexagon::A4_paslhtnew:
8896
0
    case Hexagon::A4_pasrhf:
8897
0
    case Hexagon::A4_pasrhfnew:
8898
0
    case Hexagon::A4_pasrht:
8899
0
    case Hexagon::A4_pasrhtnew:
8900
0
    case Hexagon::A4_psxtbf:
8901
0
    case Hexagon::A4_psxtbfnew:
8902
0
    case Hexagon::A4_psxtbt:
8903
0
    case Hexagon::A4_psxtbtnew:
8904
0
    case Hexagon::A4_psxthf:
8905
0
    case Hexagon::A4_psxthfnew:
8906
0
    case Hexagon::A4_psxtht:
8907
0
    case Hexagon::A4_psxthtnew:
8908
0
    case Hexagon::A4_pzxtbf:
8909
0
    case Hexagon::A4_pzxtbfnew:
8910
0
    case Hexagon::A4_pzxtbt:
8911
0
    case Hexagon::A4_pzxtbtnew:
8912
0
    case Hexagon::A4_pzxthf:
8913
0
    case Hexagon::A4_pzxthfnew:
8914
0
    case Hexagon::A4_pzxtht:
8915
0
    case Hexagon::A4_pzxthtnew: {
8916
      // op: Pu4
8917
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8918
0
      op &= UINT64_C(3);
8919
0
      op <<= 8;
8920
0
      Value |= op;
8921
      // op: Rs32
8922
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8923
0
      op &= UINT64_C(31);
8924
0
      op <<= 16;
8925
0
      Value |= op;
8926
      // op: Rd32
8927
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8928
0
      op &= UINT64_C(31);
8929
0
      Value |= op;
8930
0
      break;
8931
0
    }
8932
0
    case Hexagon::V6_vS32b_new_npred_ppu:
8933
0
    case Hexagon::V6_vS32b_new_pred_ppu:
8934
0
    case Hexagon::V6_vS32b_nt_new_npred_ppu:
8935
0
    case Hexagon::V6_vS32b_nt_new_pred_ppu: {
8936
      // op: Pv4
8937
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8938
0
      op &= UINT64_C(3);
8939
0
      op <<= 11;
8940
0
      Value |= op;
8941
      // op: Mu2
8942
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8943
0
      op &= UINT64_C(1);
8944
0
      op <<= 13;
8945
0
      Value |= op;
8946
      // op: Os8
8947
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8948
0
      op &= UINT64_C(7);
8949
0
      Value |= op;
8950
      // op: Rx32
8951
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8952
0
      op &= UINT64_C(31);
8953
0
      op <<= 16;
8954
0
      Value |= op;
8955
0
      break;
8956
0
    }
8957
0
    case Hexagon::V6_zLd_pred_ppu: {
8958
      // op: Pv4
8959
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8960
0
      op &= UINT64_C(3);
8961
0
      op <<= 11;
8962
0
      Value |= op;
8963
      // op: Mu2
8964
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8965
0
      op &= UINT64_C(1);
8966
0
      op <<= 13;
8967
0
      Value |= op;
8968
      // op: Rx32
8969
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8970
0
      op &= UINT64_C(31);
8971
0
      op <<= 16;
8972
0
      Value |= op;
8973
0
      break;
8974
0
    }
8975
0
    case Hexagon::V6_vS32Ub_npred_ppu:
8976
0
    case Hexagon::V6_vS32Ub_pred_ppu:
8977
0
    case Hexagon::V6_vS32b_npred_ppu:
8978
0
    case Hexagon::V6_vS32b_nt_npred_ppu:
8979
0
    case Hexagon::V6_vS32b_nt_pred_ppu:
8980
0
    case Hexagon::V6_vS32b_pred_ppu: {
8981
      // op: Pv4
8982
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8983
0
      op &= UINT64_C(3);
8984
0
      op <<= 11;
8985
0
      Value |= op;
8986
      // op: Mu2
8987
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8988
0
      op &= UINT64_C(1);
8989
0
      op <<= 13;
8990
0
      Value |= op;
8991
      // op: Vs32
8992
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
8993
0
      op &= UINT64_C(31);
8994
0
      Value |= op;
8995
      // op: Rx32
8996
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8997
0
      op &= UINT64_C(31);
8998
0
      op <<= 16;
8999
0
      Value |= op;
9000
0
      break;
9001
0
    }
9002
0
    case Hexagon::L4_return_f:
9003
0
    case Hexagon::L4_return_fnew_pnt:
9004
0
    case Hexagon::L4_return_fnew_pt:
9005
0
    case Hexagon::L4_return_t:
9006
0
    case Hexagon::L4_return_tnew_pnt:
9007
0
    case Hexagon::L4_return_tnew_pt: {
9008
      // op: Pv4
9009
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9010
0
      op &= UINT64_C(3);
9011
0
      op <<= 8;
9012
0
      Value |= op;
9013
      // op: Rs32
9014
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9015
0
      op &= UINT64_C(31);
9016
0
      op <<= 16;
9017
0
      Value |= op;
9018
      // op: Rdd32
9019
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9020
0
      op &= UINT64_C(31);
9021
0
      Value |= op;
9022
0
      break;
9023
0
    }
9024
0
    case Hexagon::V6_vL32b_cur_npred_ppu:
9025
0
    case Hexagon::V6_vL32b_cur_pred_ppu:
9026
0
    case Hexagon::V6_vL32b_npred_ppu:
9027
0
    case Hexagon::V6_vL32b_nt_cur_npred_ppu:
9028
0
    case Hexagon::V6_vL32b_nt_cur_pred_ppu:
9029
0
    case Hexagon::V6_vL32b_nt_npred_ppu:
9030
0
    case Hexagon::V6_vL32b_nt_pred_ppu:
9031
0
    case Hexagon::V6_vL32b_nt_tmp_npred_ppu:
9032
0
    case Hexagon::V6_vL32b_nt_tmp_pred_ppu:
9033
0
    case Hexagon::V6_vL32b_pred_ppu:
9034
0
    case Hexagon::V6_vL32b_tmp_npred_ppu:
9035
0
    case Hexagon::V6_vL32b_tmp_pred_ppu: {
9036
      // op: Pv4
9037
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9038
0
      op &= UINT64_C(3);
9039
0
      op <<= 11;
9040
0
      Value |= op;
9041
      // op: Mu2
9042
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
9043
0
      op &= UINT64_C(1);
9044
0
      op <<= 13;
9045
0
      Value |= op;
9046
      // op: Vd32
9047
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9048
0
      op &= UINT64_C(31);
9049
0
      Value |= op;
9050
      // op: Rx32
9051
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9052
0
      op &= UINT64_C(31);
9053
0
      op <<= 16;
9054
0
      Value |= op;
9055
0
      break;
9056
0
    }
9057
0
    case Hexagon::V6_vgathermhq:
9058
0
    case Hexagon::V6_vgathermwq: {
9059
      // op: Qs4
9060
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9061
0
      op &= UINT64_C(3);
9062
0
      op <<= 5;
9063
0
      Value |= op;
9064
      // op: Rt32
9065
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9066
0
      op &= UINT64_C(31);
9067
0
      op <<= 16;
9068
0
      Value |= op;
9069
      // op: Mu2
9070
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9071
0
      op &= UINT64_C(1);
9072
0
      op <<= 13;
9073
0
      Value |= op;
9074
      // op: Vv32
9075
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9076
0
      op &= UINT64_C(31);
9077
0
      Value |= op;
9078
0
      break;
9079
0
    }
9080
0
    case Hexagon::V6_vscattermhq:
9081
0
    case Hexagon::V6_vscattermwq: {
9082
      // op: Qs4
9083
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9084
0
      op &= UINT64_C(3);
9085
0
      op <<= 5;
9086
0
      Value |= op;
9087
      // op: Rt32
9088
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9089
0
      op &= UINT64_C(31);
9090
0
      op <<= 16;
9091
0
      Value |= op;
9092
      // op: Mu2
9093
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9094
0
      op &= UINT64_C(1);
9095
0
      op <<= 13;
9096
0
      Value |= op;
9097
      // op: Vv32
9098
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9099
0
      op &= UINT64_C(31);
9100
0
      op <<= 8;
9101
0
      Value |= op;
9102
      // op: Vw32
9103
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
9104
0
      op &= UINT64_C(31);
9105
0
      Value |= op;
9106
0
      break;
9107
0
    }
9108
0
    case Hexagon::V6_vgathermhwq: {
9109
      // op: Qs4
9110
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9111
0
      op &= UINT64_C(3);
9112
0
      op <<= 5;
9113
0
      Value |= op;
9114
      // op: Rt32
9115
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9116
0
      op &= UINT64_C(31);
9117
0
      op <<= 16;
9118
0
      Value |= op;
9119
      // op: Mu2
9120
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9121
0
      op &= UINT64_C(1);
9122
0
      op <<= 13;
9123
0
      Value |= op;
9124
      // op: Vvv32
9125
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9126
0
      op &= UINT64_C(31);
9127
0
      Value |= op;
9128
0
      break;
9129
0
    }
9130
0
    case Hexagon::V6_vscattermhwq: {
9131
      // op: Qs4
9132
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9133
0
      op &= UINT64_C(3);
9134
0
      op <<= 5;
9135
0
      Value |= op;
9136
      // op: Rt32
9137
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9138
0
      op &= UINT64_C(31);
9139
0
      op <<= 16;
9140
0
      Value |= op;
9141
      // op: Mu2
9142
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9143
0
      op &= UINT64_C(1);
9144
0
      op <<= 13;
9145
0
      Value |= op;
9146
      // op: Vvv32
9147
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9148
0
      op &= UINT64_C(31);
9149
0
      op <<= 8;
9150
0
      Value |= op;
9151
      // op: Vw32
9152
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
9153
0
      op &= UINT64_C(31);
9154
0
      Value |= op;
9155
0
      break;
9156
0
    }
9157
0
    case Hexagon::V6_pred_not: {
9158
      // op: Qs4
9159
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9160
0
      op &= UINT64_C(3);
9161
0
      op <<= 8;
9162
0
      Value |= op;
9163
      // op: Qd4
9164
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9165
0
      op &= UINT64_C(3);
9166
0
      Value |= op;
9167
0
      break;
9168
0
    }
9169
0
    case Hexagon::V6_pred_and:
9170
0
    case Hexagon::V6_pred_and_n:
9171
0
    case Hexagon::V6_pred_or:
9172
0
    case Hexagon::V6_pred_or_n:
9173
0
    case Hexagon::V6_pred_xor:
9174
0
    case Hexagon::V6_shuffeqh:
9175
0
    case Hexagon::V6_shuffeqw: {
9176
      // op: Qs4
9177
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9178
0
      op &= UINT64_C(3);
9179
0
      op <<= 8;
9180
0
      Value |= op;
9181
      // op: Qt4
9182
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9183
0
      op &= UINT64_C(3);
9184
0
      op <<= 22;
9185
0
      Value |= op;
9186
      // op: Qd4
9187
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9188
0
      op &= UINT64_C(3);
9189
0
      Value |= op;
9190
0
      break;
9191
0
    }
9192
0
    case Hexagon::V6_vmux: {
9193
      // op: Qt4
9194
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9195
0
      op &= UINT64_C(3);
9196
0
      op <<= 5;
9197
0
      Value |= op;
9198
      // op: Vu32
9199
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9200
0
      op &= UINT64_C(31);
9201
0
      op <<= 8;
9202
0
      Value |= op;
9203
      // op: Vv32
9204
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9205
0
      op &= UINT64_C(31);
9206
0
      op <<= 16;
9207
0
      Value |= op;
9208
      // op: Vd32
9209
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9210
0
      op &= UINT64_C(31);
9211
0
      Value |= op;
9212
0
      break;
9213
0
    }
9214
0
    case Hexagon::V6_vswap: {
9215
      // op: Qt4
9216
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9217
0
      op &= UINT64_C(3);
9218
0
      op <<= 5;
9219
0
      Value |= op;
9220
      // op: Vu32
9221
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9222
0
      op &= UINT64_C(31);
9223
0
      op <<= 8;
9224
0
      Value |= op;
9225
      // op: Vv32
9226
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9227
0
      op &= UINT64_C(31);
9228
0
      op <<= 16;
9229
0
      Value |= op;
9230
      // op: Vdd32
9231
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9232
0
      op &= UINT64_C(31);
9233
0
      Value |= op;
9234
0
      break;
9235
0
    }
9236
0
    case Hexagon::V6_vandnqrt:
9237
0
    case Hexagon::V6_vandqrt: {
9238
      // op: Qu4
9239
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9240
0
      op &= UINT64_C(3);
9241
0
      op <<= 8;
9242
0
      Value |= op;
9243
      // op: Rt32
9244
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9245
0
      op &= UINT64_C(31);
9246
0
      op <<= 16;
9247
0
      Value |= op;
9248
      // op: Vd32
9249
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9250
0
      op &= UINT64_C(31);
9251
0
      Value |= op;
9252
0
      break;
9253
0
    }
9254
0
    case Hexagon::V6_vandnqrt_acc:
9255
0
    case Hexagon::V6_vandqrt_acc: {
9256
      // op: Qu4
9257
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9258
0
      op &= UINT64_C(3);
9259
0
      op <<= 8;
9260
0
      Value |= op;
9261
      // op: Rt32
9262
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9263
0
      op &= UINT64_C(31);
9264
0
      op <<= 16;
9265
0
      Value |= op;
9266
      // op: Vx32
9267
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9268
0
      op &= UINT64_C(31);
9269
0
      Value |= op;
9270
0
      break;
9271
0
    }
9272
0
    case Hexagon::V6_vhistq:
9273
0
    case Hexagon::V6_vwhist128q:
9274
0
    case Hexagon::V6_vwhist256q:
9275
0
    case Hexagon::V6_vwhist256q_sat: {
9276
      // op: Qv4
9277
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9278
0
      op &= UINT64_C(3);
9279
0
      op <<= 22;
9280
0
      Value |= op;
9281
0
      break;
9282
0
    }
9283
0
    case Hexagon::V6_vS32b_nqpred_ppu:
9284
0
    case Hexagon::V6_vS32b_nt_nqpred_ppu:
9285
0
    case Hexagon::V6_vS32b_nt_qpred_ppu:
9286
0
    case Hexagon::V6_vS32b_qpred_ppu: {
9287
      // op: Qv4
9288
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9289
0
      op &= UINT64_C(3);
9290
0
      op <<= 11;
9291
0
      Value |= op;
9292
      // op: Mu2
9293
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9294
0
      op &= UINT64_C(1);
9295
0
      op <<= 13;
9296
0
      Value |= op;
9297
      // op: Vs32
9298
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
9299
0
      op &= UINT64_C(31);
9300
0
      Value |= op;
9301
      // op: Rx32
9302
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9303
0
      op &= UINT64_C(31);
9304
0
      op <<= 16;
9305
0
      Value |= op;
9306
0
      break;
9307
0
    }
9308
0
    case Hexagon::V6_vprefixqb:
9309
0
    case Hexagon::V6_vprefixqh:
9310
0
    case Hexagon::V6_vprefixqw: {
9311
      // op: Qv4
9312
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9313
0
      op &= UINT64_C(3);
9314
0
      op <<= 22;
9315
0
      Value |= op;
9316
      // op: Vd32
9317
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9318
0
      op &= UINT64_C(31);
9319
0
      Value |= op;
9320
0
      break;
9321
0
    }
9322
0
    case Hexagon::V6_vandvnqv:
9323
0
    case Hexagon::V6_vandvqv: {
9324
      // op: Qv4
9325
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9326
0
      op &= UINT64_C(3);
9327
0
      op <<= 22;
9328
0
      Value |= op;
9329
      // op: Vu32
9330
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9331
0
      op &= UINT64_C(31);
9332
0
      op <<= 8;
9333
0
      Value |= op;
9334
      // op: Vd32
9335
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9336
0
      op &= UINT64_C(31);
9337
0
      Value |= op;
9338
0
      break;
9339
0
    }
9340
0
    case Hexagon::V6_vaddbnq:
9341
0
    case Hexagon::V6_vaddbq:
9342
0
    case Hexagon::V6_vaddhnq:
9343
0
    case Hexagon::V6_vaddhq:
9344
0
    case Hexagon::V6_vaddwnq:
9345
0
    case Hexagon::V6_vaddwq:
9346
0
    case Hexagon::V6_vsubbnq:
9347
0
    case Hexagon::V6_vsubbq:
9348
0
    case Hexagon::V6_vsubhnq:
9349
0
    case Hexagon::V6_vsubhq:
9350
0
    case Hexagon::V6_vsubwnq:
9351
0
    case Hexagon::V6_vsubwq: {
9352
      // op: Qv4
9353
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9354
0
      op &= UINT64_C(3);
9355
0
      op <<= 22;
9356
0
      Value |= op;
9357
      // op: Vu32
9358
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9359
0
      op &= UINT64_C(31);
9360
0
      op <<= 8;
9361
0
      Value |= op;
9362
      // op: Vx32
9363
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9364
0
      op &= UINT64_C(31);
9365
0
      Value |= op;
9366
0
      break;
9367
0
    }
9368
0
    case Hexagon::SA1_clrf:
9369
0
    case Hexagon::SA1_clrfnew:
9370
0
    case Hexagon::SA1_clrt:
9371
0
    case Hexagon::SA1_clrtnew:
9372
0
    case Hexagon::SA1_setin1: {
9373
      // op: Rd16
9374
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9375
0
      op &= UINT64_C(15);
9376
0
      Value |= op;
9377
0
      break;
9378
0
    }
9379
0
    case Hexagon::Y6_dmpause:
9380
0
    case Hexagon::Y6_dmpoll:
9381
0
    case Hexagon::Y6_dmwait: {
9382
      // op: Rd32
9383
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9384
0
      op &= UINT64_C(31);
9385
0
      Value |= op;
9386
0
      break;
9387
0
    }
9388
0
    case Hexagon::PS_callr_nr: {
9389
      // op: Rs
9390
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9391
0
      op &= UINT64_C(31);
9392
0
      op <<= 16;
9393
0
      Value |= op;
9394
0
      break;
9395
0
    }
9396
0
    case Hexagon::SA1_and1:
9397
0
    case Hexagon::SA1_dec:
9398
0
    case Hexagon::SA1_inc:
9399
0
    case Hexagon::SA1_sxtb:
9400
0
    case Hexagon::SA1_sxth:
9401
0
    case Hexagon::SA1_tfr:
9402
0
    case Hexagon::SA1_zxtb:
9403
0
    case Hexagon::SA1_zxth: {
9404
      // op: Rs16
9405
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9406
0
      op &= UINT64_C(15);
9407
0
      op <<= 4;
9408
0
      Value |= op;
9409
      // op: Rd16
9410
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9411
0
      op &= UINT64_C(15);
9412
0
      Value |= op;
9413
0
      break;
9414
0
    }
9415
0
    case Hexagon::SA1_combinerz:
9416
0
    case Hexagon::SA1_combinezr: {
9417
      // op: Rs16
9418
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9419
0
      op &= UINT64_C(15);
9420
0
      op <<= 4;
9421
0
      Value |= op;
9422
      // op: Rdd8
9423
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9424
0
      op &= UINT64_C(7);
9425
0
      Value |= op;
9426
0
      break;
9427
0
    }
9428
0
    case Hexagon::SA1_addrx: {
9429
      // op: Rs16
9430
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9431
0
      op &= UINT64_C(15);
9432
0
      op <<= 4;
9433
0
      Value |= op;
9434
      // op: Rx16
9435
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9436
0
      op &= UINT64_C(15);
9437
0
      Value |= op;
9438
0
      break;
9439
0
    }
9440
0
    case Hexagon::J2_callr:
9441
0
    case Hexagon::J2_callrh:
9442
0
    case Hexagon::J2_jumpr:
9443
0
    case Hexagon::J2_jumprh:
9444
0
    case Hexagon::J4_hintjumpr:
9445
0
    case Hexagon::R6_release_at_vi:
9446
0
    case Hexagon::R6_release_st_vi:
9447
0
    case Hexagon::Y2_ciad:
9448
0
    case Hexagon::Y2_cswi:
9449
0
    case Hexagon::Y2_dccleana:
9450
0
    case Hexagon::Y2_dccleanidx:
9451
0
    case Hexagon::Y2_dccleaninva:
9452
0
    case Hexagon::Y2_dccleaninvidx:
9453
0
    case Hexagon::Y2_dcinva:
9454
0
    case Hexagon::Y2_dcinvidx:
9455
0
    case Hexagon::Y2_dczeroa:
9456
0
    case Hexagon::Y2_iassignw:
9457
0
    case Hexagon::Y2_icinva:
9458
0
    case Hexagon::Y2_icinvidx:
9459
0
    case Hexagon::Y2_l2cleaninvidx:
9460
0
    case Hexagon::Y2_resume:
9461
0
    case Hexagon::Y2_start:
9462
0
    case Hexagon::Y2_stop:
9463
0
    case Hexagon::Y2_swi:
9464
0
    case Hexagon::Y2_wait:
9465
0
    case Hexagon::Y4_nmi:
9466
0
    case Hexagon::Y4_siad:
9467
0
    case Hexagon::Y4_trace:
9468
0
    case Hexagon::Y5_l2cleanidx:
9469
0
    case Hexagon::Y5_l2invidx:
9470
0
    case Hexagon::Y5_l2unlocka:
9471
0
    case Hexagon::Y5_tlbasidi:
9472
0
    case Hexagon::Y6_diag:
9473
0
    case Hexagon::Y6_dmresume:
9474
0
    case Hexagon::Y6_dmstart: {
9475
      // op: Rs32
9476
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9477
0
      op &= UINT64_C(31);
9478
0
      op <<= 16;
9479
0
      Value |= op;
9480
0
      break;
9481
0
    }
9482
0
    case Hexagon::S2_storew_rl_at_vi:
9483
0
    case Hexagon::S2_storew_rl_st_vi:
9484
0
    case Hexagon::Y2_dctagw:
9485
0
    case Hexagon::Y2_icdataw:
9486
0
    case Hexagon::Y2_ictagw:
9487
0
    case Hexagon::Y4_l2fetch:
9488
0
    case Hexagon::Y4_l2tagw:
9489
0
    case Hexagon::Y6_dmlink: {
9490
      // op: Rs32
9491
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9492
0
      op &= UINT64_C(31);
9493
0
      op <<= 16;
9494
0
      Value |= op;
9495
      // op: Rt32
9496
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9497
0
      op &= UINT64_C(31);
9498
0
      op <<= 8;
9499
0
      Value |= op;
9500
0
      break;
9501
0
    }
9502
0
    case Hexagon::L6_memcpy: {
9503
      // op: Rs32
9504
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9505
0
      op &= UINT64_C(31);
9506
0
      op <<= 16;
9507
0
      Value |= op;
9508
      // op: Rt32
9509
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9510
0
      op &= UINT64_C(31);
9511
0
      op <<= 8;
9512
0
      Value |= op;
9513
      // op: Mu2
9514
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9515
0
      op &= UINT64_C(1);
9516
0
      op <<= 13;
9517
0
      Value |= op;
9518
0
      break;
9519
0
    }
9520
0
    case Hexagon::S4_stored_rl_at_vi:
9521
0
    case Hexagon::S4_stored_rl_st_vi:
9522
0
    case Hexagon::Y5_l2fetch: {
9523
      // op: Rs32
9524
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9525
0
      op &= UINT64_C(31);
9526
0
      op <<= 16;
9527
0
      Value |= op;
9528
      // op: Rtt32
9529
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9530
0
      op &= UINT64_C(31);
9531
0
      op <<= 8;
9532
0
      Value |= op;
9533
0
      break;
9534
0
    }
9535
0
    case Hexagon::A2_tfrrcr: {
9536
      // op: Rs32
9537
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9538
0
      op &= UINT64_C(31);
9539
0
      op <<= 16;
9540
0
      Value |= op;
9541
      // op: Cd32
9542
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9543
0
      op &= UINT64_C(31);
9544
0
      Value |= op;
9545
0
      break;
9546
0
    }
9547
0
    case Hexagon::G4_tfrgrcr: {
9548
      // op: Rs32
9549
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9550
0
      op &= UINT64_C(31);
9551
0
      op <<= 16;
9552
0
      Value |= op;
9553
      // op: Gd32
9554
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9555
0
      op &= UINT64_C(31);
9556
0
      Value |= op;
9557
0
      break;
9558
0
    }
9559
0
    case Hexagon::C2_tfrrp:
9560
0
    case Hexagon::Y5_l2locka: {
9561
      // op: Rs32
9562
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9563
0
      op &= UINT64_C(31);
9564
0
      op <<= 16;
9565
0
      Value |= op;
9566
      // op: Pd4
9567
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9568
0
      op &= UINT64_C(3);
9569
0
      Value |= op;
9570
0
      break;
9571
0
    }
9572
0
    case Hexagon::A2_abs:
9573
0
    case Hexagon::A2_abssat:
9574
0
    case Hexagon::A2_aslh:
9575
0
    case Hexagon::A2_asrh:
9576
0
    case Hexagon::A2_negsat:
9577
0
    case Hexagon::A2_satb:
9578
0
    case Hexagon::A2_sath:
9579
0
    case Hexagon::A2_satub:
9580
0
    case Hexagon::A2_satuh:
9581
0
    case Hexagon::A2_swiz:
9582
0
    case Hexagon::A2_sxtb:
9583
0
    case Hexagon::A2_sxth:
9584
0
    case Hexagon::A2_tfr:
9585
0
    case Hexagon::A2_zxth:
9586
0
    case Hexagon::F2_conv_sf2uw:
9587
0
    case Hexagon::F2_conv_sf2uw_chop:
9588
0
    case Hexagon::F2_conv_sf2w:
9589
0
    case Hexagon::F2_conv_sf2w_chop:
9590
0
    case Hexagon::F2_conv_uw2sf:
9591
0
    case Hexagon::F2_conv_w2sf:
9592
0
    case Hexagon::F2_sffixupr:
9593
0
    case Hexagon::L2_loadw_aq:
9594
0
    case Hexagon::L2_loadw_locked:
9595
0
    case Hexagon::S2_brev:
9596
0
    case Hexagon::S2_cl0:
9597
0
    case Hexagon::S2_cl1:
9598
0
    case Hexagon::S2_clb:
9599
0
    case Hexagon::S2_clbnorm:
9600
0
    case Hexagon::S2_ct0:
9601
0
    case Hexagon::S2_ct1:
9602
0
    case Hexagon::S2_svsathb:
9603
0
    case Hexagon::S2_svsathub:
9604
0
    case Hexagon::S2_vsplatrb:
9605
0
    case Hexagon::Y2_dctagr:
9606
0
    case Hexagon::Y2_getimask:
9607
0
    case Hexagon::Y2_iassignr:
9608
0
    case Hexagon::Y2_icdatar:
9609
0
    case Hexagon::Y2_ictagr:
9610
0
    case Hexagon::Y2_tlbp:
9611
0
    case Hexagon::Y4_l2tagr: {
9612
      // op: Rs32
9613
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9614
0
      op &= UINT64_C(31);
9615
0
      op <<= 16;
9616
0
      Value |= op;
9617
      // op: Rd32
9618
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9619
0
      op &= UINT64_C(31);
9620
0
      Value |= op;
9621
0
      break;
9622
0
    }
9623
0
    case Hexagon::A2_sxtw:
9624
0
    case Hexagon::F2_conv_sf2d:
9625
0
    case Hexagon::F2_conv_sf2d_chop:
9626
0
    case Hexagon::F2_conv_sf2df:
9627
0
    case Hexagon::F2_conv_sf2ud:
9628
0
    case Hexagon::F2_conv_sf2ud_chop:
9629
0
    case Hexagon::F2_conv_uw2df:
9630
0
    case Hexagon::F2_conv_w2df:
9631
0
    case Hexagon::L2_deallocframe:
9632
0
    case Hexagon::L4_loadd_aq:
9633
0
    case Hexagon::L4_loadd_locked:
9634
0
    case Hexagon::L4_return:
9635
0
    case Hexagon::S2_vsplatrh:
9636
0
    case Hexagon::S2_vsxtbh:
9637
0
    case Hexagon::S2_vsxthw:
9638
0
    case Hexagon::S2_vzxtbh:
9639
0
    case Hexagon::S2_vzxthw:
9640
0
    case Hexagon::S6_vsplatrbp:
9641
0
    case Hexagon::Y2_tlbr: {
9642
      // op: Rs32
9643
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9644
0
      op &= UINT64_C(31);
9645
0
      op <<= 16;
9646
0
      Value |= op;
9647
      // op: Rdd32
9648
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9649
0
      op &= UINT64_C(31);
9650
0
      Value |= op;
9651
0
      break;
9652
0
    }
9653
0
    case Hexagon::A4_cmpbeq:
9654
0
    case Hexagon::A4_cmpbgt:
9655
0
    case Hexagon::A4_cmpbgtu:
9656
0
    case Hexagon::A4_cmpheq:
9657
0
    case Hexagon::A4_cmphgt:
9658
0
    case Hexagon::A4_cmphgtu:
9659
0
    case Hexagon::C2_bitsclr:
9660
0
    case Hexagon::C2_bitsset:
9661
0
    case Hexagon::C2_cmpeq:
9662
0
    case Hexagon::C2_cmpgt:
9663
0
    case Hexagon::C2_cmpgtu:
9664
0
    case Hexagon::C4_cmplte:
9665
0
    case Hexagon::C4_cmplteu:
9666
0
    case Hexagon::C4_cmpneq:
9667
0
    case Hexagon::C4_nbitsclr:
9668
0
    case Hexagon::C4_nbitsset:
9669
0
    case Hexagon::F2_sfcmpeq:
9670
0
    case Hexagon::F2_sfcmpge:
9671
0
    case Hexagon::F2_sfcmpgt:
9672
0
    case Hexagon::F2_sfcmpuo:
9673
0
    case Hexagon::S2_storew_locked:
9674
0
    case Hexagon::S2_tstbit_r:
9675
0
    case Hexagon::S4_ntstbit_r: {
9676
      // op: Rs32
9677
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9678
0
      op &= UINT64_C(31);
9679
0
      op <<= 16;
9680
0
      Value |= op;
9681
      // op: Rt32
9682
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9683
0
      op &= UINT64_C(31);
9684
0
      op <<= 8;
9685
0
      Value |= op;
9686
      // op: Pd4
9687
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9688
0
      op &= UINT64_C(3);
9689
0
      Value |= op;
9690
0
      break;
9691
0
    }
9692
0
    case Hexagon::A2_add:
9693
0
    case Hexagon::A2_addsat:
9694
0
    case Hexagon::A2_and:
9695
0
    case Hexagon::A2_max:
9696
0
    case Hexagon::A2_maxu:
9697
0
    case Hexagon::A2_or:
9698
0
    case Hexagon::A2_svaddh:
9699
0
    case Hexagon::A2_svaddhs:
9700
0
    case Hexagon::A2_svadduhs:
9701
0
    case Hexagon::A2_svavgh:
9702
0
    case Hexagon::A2_svavghs:
9703
0
    case Hexagon::A2_xor:
9704
0
    case Hexagon::A4_cround_rr:
9705
0
    case Hexagon::A4_modwrapu:
9706
0
    case Hexagon::A4_rcmpeq:
9707
0
    case Hexagon::A4_rcmpneq:
9708
0
    case Hexagon::A4_round_rr:
9709
0
    case Hexagon::A4_round_rr_sat:
9710
0
    case Hexagon::F2_sfadd:
9711
0
    case Hexagon::F2_sffixupd:
9712
0
    case Hexagon::F2_sffixupn:
9713
0
    case Hexagon::F2_sfmax:
9714
0
    case Hexagon::F2_sfmin:
9715
0
    case Hexagon::F2_sfmpy:
9716
0
    case Hexagon::F2_sfsub:
9717
0
    case Hexagon::L4_loadw_phys:
9718
0
    case Hexagon::M2_cmpyrs_s0:
9719
0
    case Hexagon::M2_cmpyrs_s1:
9720
0
    case Hexagon::M2_cmpyrsc_s0:
9721
0
    case Hexagon::M2_cmpyrsc_s1:
9722
0
    case Hexagon::M2_dpmpyss_rnd_s0:
9723
0
    case Hexagon::M2_hmmpyh_rs1:
9724
0
    case Hexagon::M2_hmmpyh_s1:
9725
0
    case Hexagon::M2_hmmpyl_rs1:
9726
0
    case Hexagon::M2_hmmpyl_s1:
9727
0
    case Hexagon::M2_mpy_hh_s0:
9728
0
    case Hexagon::M2_mpy_hh_s1:
9729
0
    case Hexagon::M2_mpy_hl_s0:
9730
0
    case Hexagon::M2_mpy_hl_s1:
9731
0
    case Hexagon::M2_mpy_lh_s0:
9732
0
    case Hexagon::M2_mpy_lh_s1:
9733
0
    case Hexagon::M2_mpy_ll_s0:
9734
0
    case Hexagon::M2_mpy_ll_s1:
9735
0
    case Hexagon::M2_mpy_rnd_hh_s0:
9736
0
    case Hexagon::M2_mpy_rnd_hh_s1:
9737
0
    case Hexagon::M2_mpy_rnd_hl_s0:
9738
0
    case Hexagon::M2_mpy_rnd_hl_s1:
9739
0
    case Hexagon::M2_mpy_rnd_lh_s0:
9740
0
    case Hexagon::M2_mpy_rnd_lh_s1:
9741
0
    case Hexagon::M2_mpy_rnd_ll_s0:
9742
0
    case Hexagon::M2_mpy_rnd_ll_s1:
9743
0
    case Hexagon::M2_mpy_sat_hh_s0:
9744
0
    case Hexagon::M2_mpy_sat_hh_s1:
9745
0
    case Hexagon::M2_mpy_sat_hl_s0:
9746
0
    case Hexagon::M2_mpy_sat_hl_s1:
9747
0
    case Hexagon::M2_mpy_sat_lh_s0:
9748
0
    case Hexagon::M2_mpy_sat_lh_s1:
9749
0
    case Hexagon::M2_mpy_sat_ll_s0:
9750
0
    case Hexagon::M2_mpy_sat_ll_s1:
9751
0
    case Hexagon::M2_mpy_sat_rnd_hh_s0:
9752
0
    case Hexagon::M2_mpy_sat_rnd_hh_s1:
9753
0
    case Hexagon::M2_mpy_sat_rnd_hl_s0:
9754
0
    case Hexagon::M2_mpy_sat_rnd_hl_s1:
9755
0
    case Hexagon::M2_mpy_sat_rnd_lh_s0:
9756
0
    case Hexagon::M2_mpy_sat_rnd_lh_s1:
9757
0
    case Hexagon::M2_mpy_sat_rnd_ll_s0:
9758
0
    case Hexagon::M2_mpy_sat_rnd_ll_s1:
9759
0
    case Hexagon::M2_mpy_up:
9760
0
    case Hexagon::M2_mpy_up_s1:
9761
0
    case Hexagon::M2_mpy_up_s1_sat:
9762
0
    case Hexagon::M2_mpyi:
9763
0
    case Hexagon::M2_mpysu_up:
9764
0
    case Hexagon::M2_mpyu_hh_s0:
9765
0
    case Hexagon::M2_mpyu_hh_s1:
9766
0
    case Hexagon::M2_mpyu_hl_s0:
9767
0
    case Hexagon::M2_mpyu_hl_s1:
9768
0
    case Hexagon::M2_mpyu_lh_s0:
9769
0
    case Hexagon::M2_mpyu_lh_s1:
9770
0
    case Hexagon::M2_mpyu_ll_s0:
9771
0
    case Hexagon::M2_mpyu_ll_s1:
9772
0
    case Hexagon::M2_mpyu_up:
9773
0
    case Hexagon::M2_vmpy2s_s0pack:
9774
0
    case Hexagon::M2_vmpy2s_s1pack:
9775
0
    case Hexagon::S2_asl_r_r:
9776
0
    case Hexagon::S2_asl_r_r_sat:
9777
0
    case Hexagon::S2_asr_r_r:
9778
0
    case Hexagon::S2_asr_r_r_sat:
9779
0
    case Hexagon::S2_clrbit_r:
9780
0
    case Hexagon::S2_lsl_r_r:
9781
0
    case Hexagon::S2_lsr_r_r:
9782
0
    case Hexagon::S2_setbit_r:
9783
0
    case Hexagon::S2_togglebit_r:
9784
0
    case Hexagon::S4_parity:
9785
0
    case Hexagon::dep_A2_addsat: {
9786
      // op: Rs32
9787
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9788
0
      op &= UINT64_C(31);
9789
0
      op <<= 16;
9790
0
      Value |= op;
9791
      // op: Rt32
9792
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9793
0
      op &= UINT64_C(31);
9794
0
      op <<= 8;
9795
0
      Value |= op;
9796
      // op: Rd32
9797
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9798
0
      op &= UINT64_C(31);
9799
0
      Value |= op;
9800
0
      break;
9801
0
    }
9802
0
    case Hexagon::A2_combinew:
9803
0
    case Hexagon::A4_bitsplit:
9804
0
    case Hexagon::M2_cmpyi_s0:
9805
0
    case Hexagon::M2_cmpyr_s0:
9806
0
    case Hexagon::M2_cmpys_s0:
9807
0
    case Hexagon::M2_cmpys_s1:
9808
0
    case Hexagon::M2_cmpysc_s0:
9809
0
    case Hexagon::M2_cmpysc_s1:
9810
0
    case Hexagon::M2_dpmpyss_s0:
9811
0
    case Hexagon::M2_dpmpyuu_s0:
9812
0
    case Hexagon::M2_mpyd_hh_s0:
9813
0
    case Hexagon::M2_mpyd_hh_s1:
9814
0
    case Hexagon::M2_mpyd_hl_s0:
9815
0
    case Hexagon::M2_mpyd_hl_s1:
9816
0
    case Hexagon::M2_mpyd_lh_s0:
9817
0
    case Hexagon::M2_mpyd_lh_s1:
9818
0
    case Hexagon::M2_mpyd_ll_s0:
9819
0
    case Hexagon::M2_mpyd_ll_s1:
9820
0
    case Hexagon::M2_mpyd_rnd_hh_s0:
9821
0
    case Hexagon::M2_mpyd_rnd_hh_s1:
9822
0
    case Hexagon::M2_mpyd_rnd_hl_s0:
9823
0
    case Hexagon::M2_mpyd_rnd_hl_s1:
9824
0
    case Hexagon::M2_mpyd_rnd_lh_s0:
9825
0
    case Hexagon::M2_mpyd_rnd_lh_s1:
9826
0
    case Hexagon::M2_mpyd_rnd_ll_s0:
9827
0
    case Hexagon::M2_mpyd_rnd_ll_s1:
9828
0
    case Hexagon::M2_mpyud_hh_s0:
9829
0
    case Hexagon::M2_mpyud_hh_s1:
9830
0
    case Hexagon::M2_mpyud_hl_s0:
9831
0
    case Hexagon::M2_mpyud_hl_s1:
9832
0
    case Hexagon::M2_mpyud_lh_s0:
9833
0
    case Hexagon::M2_mpyud_lh_s1:
9834
0
    case Hexagon::M2_mpyud_ll_s0:
9835
0
    case Hexagon::M2_mpyud_ll_s1:
9836
0
    case Hexagon::M2_vmpy2s_s0:
9837
0
    case Hexagon::M2_vmpy2s_s1:
9838
0
    case Hexagon::M2_vmpy2su_s0:
9839
0
    case Hexagon::M2_vmpy2su_s1:
9840
0
    case Hexagon::M4_pmpyw:
9841
0
    case Hexagon::M4_vpmpyh:
9842
0
    case Hexagon::M5_vmpybsu:
9843
0
    case Hexagon::M5_vmpybuu:
9844
0
    case Hexagon::S2_packhl:
9845
0
    case Hexagon::dep_S2_packhl: {
9846
      // op: Rs32
9847
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9848
0
      op &= UINT64_C(31);
9849
0
      op <<= 16;
9850
0
      Value |= op;
9851
      // op: Rt32
9852
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9853
0
      op &= UINT64_C(31);
9854
0
      op <<= 8;
9855
0
      Value |= op;
9856
      // op: Rdd32
9857
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9858
0
      op &= UINT64_C(31);
9859
0
      Value |= op;
9860
0
      break;
9861
0
    }
9862
0
    case Hexagon::S4_stored_locked: {
9863
      // op: Rs32
9864
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9865
0
      op &= UINT64_C(31);
9866
0
      op <<= 16;
9867
0
      Value |= op;
9868
      // op: Rtt32
9869
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9870
0
      op &= UINT64_C(31);
9871
0
      op <<= 8;
9872
0
      Value |= op;
9873
      // op: Pd4
9874
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9875
0
      op &= UINT64_C(3);
9876
0
      Value |= op;
9877
0
      break;
9878
0
    }
9879
0
    case Hexagon::S2_extractu_rp:
9880
0
    case Hexagon::S4_extract_rp: {
9881
      // op: Rs32
9882
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9883
0
      op &= UINT64_C(31);
9884
0
      op <<= 16;
9885
0
      Value |= op;
9886
      // op: Rtt32
9887
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9888
0
      op &= UINT64_C(31);
9889
0
      op <<= 8;
9890
0
      Value |= op;
9891
      // op: Rd32
9892
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9893
0
      op &= UINT64_C(31);
9894
0
      Value |= op;
9895
0
      break;
9896
0
    }
9897
0
    case Hexagon::Y2_tfrsrcr: {
9898
      // op: Rs32
9899
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9900
0
      op &= UINT64_C(31);
9901
0
      op <<= 16;
9902
0
      Value |= op;
9903
      // op: Sd128
9904
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9905
0
      op &= UINT64_C(127);
9906
0
      Value |= op;
9907
0
      break;
9908
0
    }
9909
0
    case Hexagon::F2_sfinvsqrta: {
9910
      // op: Rs32
9911
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9912
0
      op &= UINT64_C(31);
9913
0
      op <<= 16;
9914
0
      Value |= op;
9915
      // op: Rd32
9916
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9917
0
      op &= UINT64_C(31);
9918
0
      Value |= op;
9919
      // op: Pe4
9920
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9921
0
      op &= UINT64_C(3);
9922
0
      op <<= 5;
9923
0
      Value |= op;
9924
0
      break;
9925
0
    }
9926
0
    case Hexagon::F2_sffma_sc: {
9927
      // op: Rs32
9928
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9929
0
      op &= UINT64_C(31);
9930
0
      op <<= 16;
9931
0
      Value |= op;
9932
      // op: Rt32
9933
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9934
0
      op &= UINT64_C(31);
9935
0
      op <<= 8;
9936
0
      Value |= op;
9937
      // op: Pu4
9938
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
9939
0
      op &= UINT64_C(3);
9940
0
      op <<= 5;
9941
0
      Value |= op;
9942
      // op: Rx32
9943
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9944
0
      op &= UINT64_C(31);
9945
0
      Value |= op;
9946
0
      break;
9947
0
    }
9948
0
    case Hexagon::F2_sfrecipa: {
9949
      // op: Rs32
9950
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9951
0
      op &= UINT64_C(31);
9952
0
      op <<= 16;
9953
0
      Value |= op;
9954
      // op: Rt32
9955
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9956
0
      op &= UINT64_C(31);
9957
0
      op <<= 8;
9958
0
      Value |= op;
9959
      // op: Rd32
9960
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9961
0
      op &= UINT64_C(31);
9962
0
      Value |= op;
9963
      // op: Pe4
9964
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
9965
0
      op &= UINT64_C(3);
9966
0
      op <<= 5;
9967
0
      Value |= op;
9968
0
      break;
9969
0
    }
9970
0
    case Hexagon::F2_sffma:
9971
0
    case Hexagon::F2_sffma_lib:
9972
0
    case Hexagon::F2_sffms:
9973
0
    case Hexagon::F2_sffms_lib:
9974
0
    case Hexagon::M2_acci:
9975
0
    case Hexagon::M2_maci:
9976
0
    case Hexagon::M2_mnaci:
9977
0
    case Hexagon::M2_mpy_acc_hh_s0:
9978
0
    case Hexagon::M2_mpy_acc_hh_s1:
9979
0
    case Hexagon::M2_mpy_acc_hl_s0:
9980
0
    case Hexagon::M2_mpy_acc_hl_s1:
9981
0
    case Hexagon::M2_mpy_acc_lh_s0:
9982
0
    case Hexagon::M2_mpy_acc_lh_s1:
9983
0
    case Hexagon::M2_mpy_acc_ll_s0:
9984
0
    case Hexagon::M2_mpy_acc_ll_s1:
9985
0
    case Hexagon::M2_mpy_acc_sat_hh_s0:
9986
0
    case Hexagon::M2_mpy_acc_sat_hh_s1:
9987
0
    case Hexagon::M2_mpy_acc_sat_hl_s0:
9988
0
    case Hexagon::M2_mpy_acc_sat_hl_s1:
9989
0
    case Hexagon::M2_mpy_acc_sat_lh_s0:
9990
0
    case Hexagon::M2_mpy_acc_sat_lh_s1:
9991
0
    case Hexagon::M2_mpy_acc_sat_ll_s0:
9992
0
    case Hexagon::M2_mpy_acc_sat_ll_s1:
9993
0
    case Hexagon::M2_mpy_nac_hh_s0:
9994
0
    case Hexagon::M2_mpy_nac_hh_s1:
9995
0
    case Hexagon::M2_mpy_nac_hl_s0:
9996
0
    case Hexagon::M2_mpy_nac_hl_s1:
9997
0
    case Hexagon::M2_mpy_nac_lh_s0:
9998
0
    case Hexagon::M2_mpy_nac_lh_s1:
9999
0
    case Hexagon::M2_mpy_nac_ll_s0:
10000
0
    case Hexagon::M2_mpy_nac_ll_s1:
10001
0
    case Hexagon::M2_mpy_nac_sat_hh_s0:
10002
0
    case Hexagon::M2_mpy_nac_sat_hh_s1:
10003
0
    case Hexagon::M2_mpy_nac_sat_hl_s0:
10004
0
    case Hexagon::M2_mpy_nac_sat_hl_s1:
10005
0
    case Hexagon::M2_mpy_nac_sat_lh_s0:
10006
0
    case Hexagon::M2_mpy_nac_sat_lh_s1:
10007
0
    case Hexagon::M2_mpy_nac_sat_ll_s0:
10008
0
    case Hexagon::M2_mpy_nac_sat_ll_s1:
10009
0
    case Hexagon::M2_mpyu_acc_hh_s0:
10010
0
    case Hexagon::M2_mpyu_acc_hh_s1:
10011
0
    case Hexagon::M2_mpyu_acc_hl_s0:
10012
0
    case Hexagon::M2_mpyu_acc_hl_s1:
10013
0
    case Hexagon::M2_mpyu_acc_lh_s0:
10014
0
    case Hexagon::M2_mpyu_acc_lh_s1:
10015
0
    case Hexagon::M2_mpyu_acc_ll_s0:
10016
0
    case Hexagon::M2_mpyu_acc_ll_s1:
10017
0
    case Hexagon::M2_mpyu_nac_hh_s0:
10018
0
    case Hexagon::M2_mpyu_nac_hh_s1:
10019
0
    case Hexagon::M2_mpyu_nac_hl_s0:
10020
0
    case Hexagon::M2_mpyu_nac_hl_s1:
10021
0
    case Hexagon::M2_mpyu_nac_lh_s0:
10022
0
    case Hexagon::M2_mpyu_nac_lh_s1:
10023
0
    case Hexagon::M2_mpyu_nac_ll_s0:
10024
0
    case Hexagon::M2_mpyu_nac_ll_s1:
10025
0
    case Hexagon::M2_nacci:
10026
0
    case Hexagon::M2_xor_xacc:
10027
0
    case Hexagon::M4_and_and:
10028
0
    case Hexagon::M4_and_andn:
10029
0
    case Hexagon::M4_and_or:
10030
0
    case Hexagon::M4_and_xor:
10031
0
    case Hexagon::M4_mac_up_s1_sat:
10032
0
    case Hexagon::M4_nac_up_s1_sat:
10033
0
    case Hexagon::M4_or_and:
10034
0
    case Hexagon::M4_or_andn:
10035
0
    case Hexagon::M4_or_or:
10036
0
    case Hexagon::M4_or_xor:
10037
0
    case Hexagon::M4_xor_and:
10038
0
    case Hexagon::M4_xor_andn:
10039
0
    case Hexagon::M4_xor_or:
10040
0
    case Hexagon::S2_asl_r_r_acc:
10041
0
    case Hexagon::S2_asl_r_r_and:
10042
0
    case Hexagon::S2_asl_r_r_nac:
10043
0
    case Hexagon::S2_asl_r_r_or:
10044
0
    case Hexagon::S2_asr_r_r_acc:
10045
0
    case Hexagon::S2_asr_r_r_and:
10046
0
    case Hexagon::S2_asr_r_r_nac:
10047
0
    case Hexagon::S2_asr_r_r_or:
10048
0
    case Hexagon::S2_lsl_r_r_acc:
10049
0
    case Hexagon::S2_lsl_r_r_and:
10050
0
    case Hexagon::S2_lsl_r_r_nac:
10051
0
    case Hexagon::S2_lsl_r_r_or:
10052
0
    case Hexagon::S2_lsr_r_r_acc:
10053
0
    case Hexagon::S2_lsr_r_r_and:
10054
0
    case Hexagon::S2_lsr_r_r_nac:
10055
0
    case Hexagon::S2_lsr_r_r_or: {
10056
      // op: Rs32
10057
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10058
0
      op &= UINT64_C(31);
10059
0
      op <<= 16;
10060
0
      Value |= op;
10061
      // op: Rt32
10062
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10063
0
      op &= UINT64_C(31);
10064
0
      op <<= 8;
10065
0
      Value |= op;
10066
      // op: Rx32
10067
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10068
0
      op &= UINT64_C(31);
10069
0
      Value |= op;
10070
0
      break;
10071
0
    }
10072
0
    case Hexagon::M2_cmaci_s0:
10073
0
    case Hexagon::M2_cmacr_s0:
10074
0
    case Hexagon::M2_cmacs_s0:
10075
0
    case Hexagon::M2_cmacs_s1:
10076
0
    case Hexagon::M2_cmacsc_s0:
10077
0
    case Hexagon::M2_cmacsc_s1:
10078
0
    case Hexagon::M2_cnacs_s0:
10079
0
    case Hexagon::M2_cnacs_s1:
10080
0
    case Hexagon::M2_cnacsc_s0:
10081
0
    case Hexagon::M2_cnacsc_s1:
10082
0
    case Hexagon::M2_dpmpyss_acc_s0:
10083
0
    case Hexagon::M2_dpmpyss_nac_s0:
10084
0
    case Hexagon::M2_dpmpyuu_acc_s0:
10085
0
    case Hexagon::M2_dpmpyuu_nac_s0:
10086
0
    case Hexagon::M2_mpyd_acc_hh_s0:
10087
0
    case Hexagon::M2_mpyd_acc_hh_s1:
10088
0
    case Hexagon::M2_mpyd_acc_hl_s0:
10089
0
    case Hexagon::M2_mpyd_acc_hl_s1:
10090
0
    case Hexagon::M2_mpyd_acc_lh_s0:
10091
0
    case Hexagon::M2_mpyd_acc_lh_s1:
10092
0
    case Hexagon::M2_mpyd_acc_ll_s0:
10093
0
    case Hexagon::M2_mpyd_acc_ll_s1:
10094
0
    case Hexagon::M2_mpyd_nac_hh_s0:
10095
0
    case Hexagon::M2_mpyd_nac_hh_s1:
10096
0
    case Hexagon::M2_mpyd_nac_hl_s0:
10097
0
    case Hexagon::M2_mpyd_nac_hl_s1:
10098
0
    case Hexagon::M2_mpyd_nac_lh_s0:
10099
0
    case Hexagon::M2_mpyd_nac_lh_s1:
10100
0
    case Hexagon::M2_mpyd_nac_ll_s0:
10101
0
    case Hexagon::M2_mpyd_nac_ll_s1:
10102
0
    case Hexagon::M2_mpyud_acc_hh_s0:
10103
0
    case Hexagon::M2_mpyud_acc_hh_s1:
10104
0
    case Hexagon::M2_mpyud_acc_hl_s0:
10105
0
    case Hexagon::M2_mpyud_acc_hl_s1:
10106
0
    case Hexagon::M2_mpyud_acc_lh_s0:
10107
0
    case Hexagon::M2_mpyud_acc_lh_s1:
10108
0
    case Hexagon::M2_mpyud_acc_ll_s0:
10109
0
    case Hexagon::M2_mpyud_acc_ll_s1:
10110
0
    case Hexagon::M2_mpyud_nac_hh_s0:
10111
0
    case Hexagon::M2_mpyud_nac_hh_s1:
10112
0
    case Hexagon::M2_mpyud_nac_hl_s0:
10113
0
    case Hexagon::M2_mpyud_nac_hl_s1:
10114
0
    case Hexagon::M2_mpyud_nac_lh_s0:
10115
0
    case Hexagon::M2_mpyud_nac_lh_s1:
10116
0
    case Hexagon::M2_mpyud_nac_ll_s0:
10117
0
    case Hexagon::M2_mpyud_nac_ll_s1:
10118
0
    case Hexagon::M2_vmac2:
10119
0
    case Hexagon::M2_vmac2s_s0:
10120
0
    case Hexagon::M2_vmac2s_s1:
10121
0
    case Hexagon::M2_vmac2su_s0:
10122
0
    case Hexagon::M2_vmac2su_s1:
10123
0
    case Hexagon::M4_pmpyw_acc:
10124
0
    case Hexagon::M4_vpmpyh_acc:
10125
0
    case Hexagon::M5_vmacbsu:
10126
0
    case Hexagon::M5_vmacbuu: {
10127
      // op: Rs32
10128
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10129
0
      op &= UINT64_C(31);
10130
0
      op <<= 16;
10131
0
      Value |= op;
10132
      // op: Rt32
10133
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10134
0
      op &= UINT64_C(31);
10135
0
      op <<= 8;
10136
0
      Value |= op;
10137
      // op: Rxx32
10138
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10139
0
      op &= UINT64_C(31);
10140
0
      Value |= op;
10141
0
      break;
10142
0
    }
10143
0
    case Hexagon::S2_insert_rp: {
10144
      // op: Rs32
10145
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10146
0
      op &= UINT64_C(31);
10147
0
      op <<= 16;
10148
0
      Value |= op;
10149
      // op: Rtt32
10150
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10151
0
      op &= UINT64_C(31);
10152
0
      op <<= 8;
10153
0
      Value |= op;
10154
      // op: Rx32
10155
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10156
0
      op &= UINT64_C(31);
10157
0
      Value |= op;
10158
0
      break;
10159
0
    }
10160
0
    case Hexagon::Y2_tlbw: {
10161
      // op: Rss32
10162
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10163
0
      op &= UINT64_C(31);
10164
0
      op <<= 16;
10165
0
      Value |= op;
10166
      // op: Rt32
10167
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10168
0
      op &= UINT64_C(31);
10169
0
      op <<= 8;
10170
0
      Value |= op;
10171
0
      break;
10172
0
    }
10173
0
    case Hexagon::Y6_diag0:
10174
0
    case Hexagon::Y6_diag1: {
10175
      // op: Rss32
10176
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10177
0
      op &= UINT64_C(31);
10178
0
      op <<= 16;
10179
0
      Value |= op;
10180
      // op: Rtt32
10181
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10182
0
      op &= UINT64_C(31);
10183
0
      op <<= 8;
10184
0
      Value |= op;
10185
0
      break;
10186
0
    }
10187
0
    case Hexagon::A4_tfrpcp: {
10188
      // op: Rss32
10189
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10190
0
      op &= UINT64_C(31);
10191
0
      op <<= 16;
10192
0
      Value |= op;
10193
      // op: Cdd32
10194
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10195
0
      op &= UINT64_C(31);
10196
0
      Value |= op;
10197
0
      break;
10198
0
    }
10199
0
    case Hexagon::G4_tfrgpcp: {
10200
      // op: Rss32
10201
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10202
0
      op &= UINT64_C(31);
10203
0
      op <<= 16;
10204
0
      Value |= op;
10205
      // op: Gdd32
10206
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10207
0
      op &= UINT64_C(31);
10208
0
      Value |= op;
10209
0
      break;
10210
0
    }
10211
0
    case Hexagon::A2_roundsat:
10212
0
    case Hexagon::A2_sat:
10213
0
    case Hexagon::F2_conv_d2sf:
10214
0
    case Hexagon::F2_conv_df2sf:
10215
0
    case Hexagon::F2_conv_df2uw:
10216
0
    case Hexagon::F2_conv_df2uw_chop:
10217
0
    case Hexagon::F2_conv_df2w:
10218
0
    case Hexagon::F2_conv_df2w_chop:
10219
0
    case Hexagon::F2_conv_ud2sf:
10220
0
    case Hexagon::S2_cl0p:
10221
0
    case Hexagon::S2_cl1p:
10222
0
    case Hexagon::S2_clbp:
10223
0
    case Hexagon::S2_ct0p:
10224
0
    case Hexagon::S2_ct1p:
10225
0
    case Hexagon::S2_vrndpackwh:
10226
0
    case Hexagon::S2_vrndpackwhs:
10227
0
    case Hexagon::S2_vsathb:
10228
0
    case Hexagon::S2_vsathub:
10229
0
    case Hexagon::S2_vsatwh:
10230
0
    case Hexagon::S2_vsatwuh:
10231
0
    case Hexagon::S2_vtrunehb:
10232
0
    case Hexagon::S2_vtrunohb:
10233
0
    case Hexagon::S4_clbpnorm:
10234
0
    case Hexagon::S5_popcountp:
10235
0
    case Hexagon::Y5_tlboc: {
10236
      // op: Rss32
10237
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10238
0
      op &= UINT64_C(31);
10239
0
      op <<= 16;
10240
0
      Value |= op;
10241
      // op: Rd32
10242
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10243
0
      op &= UINT64_C(31);
10244
0
      Value |= op;
10245
0
      break;
10246
0
    }
10247
0
    case Hexagon::A2_absp:
10248
0
    case Hexagon::A2_negp:
10249
0
    case Hexagon::A2_notp:
10250
0
    case Hexagon::A2_vabsh:
10251
0
    case Hexagon::A2_vabshsat:
10252
0
    case Hexagon::A2_vabsw:
10253
0
    case Hexagon::A2_vabswsat:
10254
0
    case Hexagon::A2_vconj:
10255
0
    case Hexagon::F2_conv_d2df:
10256
0
    case Hexagon::F2_conv_df2d:
10257
0
    case Hexagon::F2_conv_df2d_chop:
10258
0
    case Hexagon::F2_conv_df2ud:
10259
0
    case Hexagon::F2_conv_df2ud_chop:
10260
0
    case Hexagon::F2_conv_ud2df:
10261
0
    case Hexagon::S2_brevp:
10262
0
    case Hexagon::S2_deinterleave:
10263
0
    case Hexagon::S2_interleave:
10264
0
    case Hexagon::S2_vsathb_nopack:
10265
0
    case Hexagon::S2_vsathub_nopack:
10266
0
    case Hexagon::S2_vsatwh_nopack:
10267
0
    case Hexagon::S2_vsatwuh_nopack: {
10268
      // op: Rss32
10269
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10270
0
      op &= UINT64_C(31);
10271
0
      op <<= 16;
10272
0
      Value |= op;
10273
      // op: Rdd32
10274
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10275
0
      op &= UINT64_C(31);
10276
0
      Value |= op;
10277
0
      break;
10278
0
    }
10279
0
    case Hexagon::A4_tlbmatch: {
10280
      // op: Rss32
10281
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10282
0
      op &= UINT64_C(31);
10283
0
      op <<= 16;
10284
0
      Value |= op;
10285
      // op: Rt32
10286
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10287
0
      op &= UINT64_C(31);
10288
0
      op <<= 8;
10289
0
      Value |= op;
10290
      // op: Pd4
10291
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10292
0
      op &= UINT64_C(3);
10293
0
      Value |= op;
10294
0
      break;
10295
0
    }
10296
0
    case Hexagon::M4_cmpyi_wh:
10297
0
    case Hexagon::M4_cmpyi_whc:
10298
0
    case Hexagon::M4_cmpyr_wh:
10299
0
    case Hexagon::M4_cmpyr_whc:
10300
0
    case Hexagon::S2_asr_r_svw_trun:
10301
0
    case Hexagon::Y5_ctlbw: {
10302
      // op: Rss32
10303
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10304
0
      op &= UINT64_C(31);
10305
0
      op <<= 16;
10306
0
      Value |= op;
10307
      // op: Rt32
10308
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10309
0
      op &= UINT64_C(31);
10310
0
      op <<= 8;
10311
0
      Value |= op;
10312
      // op: Rd32
10313
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10314
0
      op &= UINT64_C(31);
10315
0
      Value |= op;
10316
0
      break;
10317
0
    }
10318
0
    case Hexagon::A7_croundd_rr:
10319
0
    case Hexagon::S2_asl_r_p:
10320
0
    case Hexagon::S2_asl_r_vh:
10321
0
    case Hexagon::S2_asl_r_vw:
10322
0
    case Hexagon::S2_asr_r_p:
10323
0
    case Hexagon::S2_asr_r_vh:
10324
0
    case Hexagon::S2_asr_r_vw:
10325
0
    case Hexagon::S2_lsl_r_p:
10326
0
    case Hexagon::S2_lsl_r_vh:
10327
0
    case Hexagon::S2_lsl_r_vw:
10328
0
    case Hexagon::S2_lsr_r_p:
10329
0
    case Hexagon::S2_lsr_r_vh:
10330
0
    case Hexagon::S2_lsr_r_vw:
10331
0
    case Hexagon::S2_vcnegh:
10332
0
    case Hexagon::S2_vcrotate: {
10333
      // op: Rss32
10334
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10335
0
      op &= UINT64_C(31);
10336
0
      op <<= 16;
10337
0
      Value |= op;
10338
      // op: Rt32
10339
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10340
0
      op &= UINT64_C(31);
10341
0
      op <<= 8;
10342
0
      Value |= op;
10343
      // op: Rdd32
10344
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10345
0
      op &= UINT64_C(31);
10346
0
      Value |= op;
10347
0
      break;
10348
0
    }
10349
0
    case Hexagon::A2_vcmpbeq:
10350
0
    case Hexagon::A2_vcmpbgtu:
10351
0
    case Hexagon::A2_vcmpheq:
10352
0
    case Hexagon::A2_vcmphgt:
10353
0
    case Hexagon::A2_vcmphgtu:
10354
0
    case Hexagon::A2_vcmpweq:
10355
0
    case Hexagon::A2_vcmpwgt:
10356
0
    case Hexagon::A2_vcmpwgtu:
10357
0
    case Hexagon::A4_boundscheck_hi:
10358
0
    case Hexagon::A4_boundscheck_lo:
10359
0
    case Hexagon::A4_vcmpbeq_any:
10360
0
    case Hexagon::A4_vcmpbgt:
10361
0
    case Hexagon::A6_vcmpbeq_notany:
10362
0
    case Hexagon::C2_cmpeqp:
10363
0
    case Hexagon::C2_cmpgtp:
10364
0
    case Hexagon::C2_cmpgtup:
10365
0
    case Hexagon::F2_dfcmpeq:
10366
0
    case Hexagon::F2_dfcmpge:
10367
0
    case Hexagon::F2_dfcmpgt:
10368
0
    case Hexagon::F2_dfcmpuo: {
10369
      // op: Rss32
10370
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10371
0
      op &= UINT64_C(31);
10372
0
      op <<= 16;
10373
0
      Value |= op;
10374
      // op: Rtt32
10375
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10376
0
      op &= UINT64_C(31);
10377
0
      op <<= 8;
10378
0
      Value |= op;
10379
      // op: Pd4
10380
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10381
0
      op &= UINT64_C(3);
10382
0
      Value |= op;
10383
0
      break;
10384
0
    }
10385
0
    case Hexagon::S2_vsplicerb: {
10386
      // op: Rss32
10387
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10388
0
      op &= UINT64_C(31);
10389
0
      op <<= 16;
10390
0
      Value |= op;
10391
      // op: Rtt32
10392
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10393
0
      op &= UINT64_C(31);
10394
0
      op <<= 8;
10395
0
      Value |= op;
10396
      // op: Pu4
10397
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10398
0
      op &= UINT64_C(3);
10399
0
      op <<= 5;
10400
0
      Value |= op;
10401
      // op: Rdd32
10402
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10403
0
      op &= UINT64_C(31);
10404
0
      Value |= op;
10405
0
      break;
10406
0
    }
10407
0
    case Hexagon::A5_vaddhubs:
10408
0
    case Hexagon::M2_vdmpyrs_s0:
10409
0
    case Hexagon::M2_vdmpyrs_s1:
10410
0
    case Hexagon::M2_vraddh:
10411
0
    case Hexagon::M2_vradduh:
10412
0
    case Hexagon::M2_vrcmpys_s1rp_h:
10413
0
    case Hexagon::M2_vrcmpys_s1rp_l:
10414
0
    case Hexagon::M7_wcmpyiw:
10415
0
    case Hexagon::M7_wcmpyiw_rnd:
10416
0
    case Hexagon::M7_wcmpyiwc:
10417
0
    case Hexagon::M7_wcmpyiwc_rnd:
10418
0
    case Hexagon::M7_wcmpyrw:
10419
0
    case Hexagon::M7_wcmpyrw_rnd:
10420
0
    case Hexagon::M7_wcmpyrwc:
10421
0
    case Hexagon::M7_wcmpyrwc_rnd:
10422
0
    case Hexagon::S2_parityp: {
10423
      // op: Rss32
10424
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10425
0
      op &= UINT64_C(31);
10426
0
      op <<= 16;
10427
0
      Value |= op;
10428
      // op: Rtt32
10429
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10430
0
      op &= UINT64_C(31);
10431
0
      op <<= 8;
10432
0
      Value |= op;
10433
      // op: Rd32
10434
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10435
0
      op &= UINT64_C(31);
10436
0
      Value |= op;
10437
0
      break;
10438
0
    }
10439
0
    case Hexagon::A2_addp:
10440
0
    case Hexagon::A2_addpsat:
10441
0
    case Hexagon::A2_addsph:
10442
0
    case Hexagon::A2_addspl:
10443
0
    case Hexagon::A2_andp:
10444
0
    case Hexagon::A2_maxp:
10445
0
    case Hexagon::A2_maxup:
10446
0
    case Hexagon::A2_orp:
10447
0
    case Hexagon::A2_vaddh:
10448
0
    case Hexagon::A2_vaddhs:
10449
0
    case Hexagon::A2_vaddub:
10450
0
    case Hexagon::A2_vaddubs:
10451
0
    case Hexagon::A2_vadduhs:
10452
0
    case Hexagon::A2_vaddw:
10453
0
    case Hexagon::A2_vaddws:
10454
0
    case Hexagon::A2_vavgh:
10455
0
    case Hexagon::A2_vavghcr:
10456
0
    case Hexagon::A2_vavghr:
10457
0
    case Hexagon::A2_vavgub:
10458
0
    case Hexagon::A2_vavgubr:
10459
0
    case Hexagon::A2_vavguh:
10460
0
    case Hexagon::A2_vavguhr:
10461
0
    case Hexagon::A2_vavguw:
10462
0
    case Hexagon::A2_vavguwr:
10463
0
    case Hexagon::A2_vavgw:
10464
0
    case Hexagon::A2_vavgwcr:
10465
0
    case Hexagon::A2_vavgwr:
10466
0
    case Hexagon::A2_vraddub:
10467
0
    case Hexagon::A2_vrsadub:
10468
0
    case Hexagon::A2_xorp:
10469
0
    case Hexagon::F2_dfadd:
10470
0
    case Hexagon::F2_dfmax:
10471
0
    case Hexagon::F2_dfmin:
10472
0
    case Hexagon::F2_dfmpyfix:
10473
0
    case Hexagon::F2_dfmpyll:
10474
0
    case Hexagon::F2_dfsub:
10475
0
    case Hexagon::M2_mmpyh_rs0:
10476
0
    case Hexagon::M2_mmpyh_rs1:
10477
0
    case Hexagon::M2_mmpyh_s0:
10478
0
    case Hexagon::M2_mmpyh_s1:
10479
0
    case Hexagon::M2_mmpyl_rs0:
10480
0
    case Hexagon::M2_mmpyl_rs1:
10481
0
    case Hexagon::M2_mmpyl_s0:
10482
0
    case Hexagon::M2_mmpyl_s1:
10483
0
    case Hexagon::M2_mmpyuh_rs0:
10484
0
    case Hexagon::M2_mmpyuh_rs1:
10485
0
    case Hexagon::M2_mmpyuh_s0:
10486
0
    case Hexagon::M2_mmpyuh_s1:
10487
0
    case Hexagon::M2_mmpyul_rs0:
10488
0
    case Hexagon::M2_mmpyul_rs1:
10489
0
    case Hexagon::M2_mmpyul_s0:
10490
0
    case Hexagon::M2_mmpyul_s1:
10491
0
    case Hexagon::M2_vcmpy_s0_sat_i:
10492
0
    case Hexagon::M2_vcmpy_s0_sat_r:
10493
0
    case Hexagon::M2_vcmpy_s1_sat_i:
10494
0
    case Hexagon::M2_vcmpy_s1_sat_r:
10495
0
    case Hexagon::M2_vdmpys_s0:
10496
0
    case Hexagon::M2_vdmpys_s1:
10497
0
    case Hexagon::M2_vmpy2es_s0:
10498
0
    case Hexagon::M2_vmpy2es_s1:
10499
0
    case Hexagon::M2_vrcmpyi_s0:
10500
0
    case Hexagon::M2_vrcmpyi_s0c:
10501
0
    case Hexagon::M2_vrcmpyr_s0:
10502
0
    case Hexagon::M2_vrcmpyr_s0c:
10503
0
    case Hexagon::M2_vrcmpys_s1_h:
10504
0
    case Hexagon::M2_vrcmpys_s1_l:
10505
0
    case Hexagon::M2_vrmpy_s0:
10506
0
    case Hexagon::M4_vrmpyeh_s0:
10507
0
    case Hexagon::M4_vrmpyeh_s1:
10508
0
    case Hexagon::M4_vrmpyoh_s0:
10509
0
    case Hexagon::M4_vrmpyoh_s1:
10510
0
    case Hexagon::M5_vdmpybsu:
10511
0
    case Hexagon::M5_vrmpybsu:
10512
0
    case Hexagon::M5_vrmpybuu:
10513
0
    case Hexagon::M7_dcmpyiw:
10514
0
    case Hexagon::M7_dcmpyiwc:
10515
0
    case Hexagon::M7_dcmpyrw:
10516
0
    case Hexagon::M7_dcmpyrwc:
10517
0
    case Hexagon::S2_cabacdecbin:
10518
0
    case Hexagon::S2_extractup_rp:
10519
0
    case Hexagon::S2_lfsp:
10520
0
    case Hexagon::S2_shuffeb:
10521
0
    case Hexagon::S2_shuffeh:
10522
0
    case Hexagon::S2_vtrunewh:
10523
0
    case Hexagon::S2_vtrunowh:
10524
0
    case Hexagon::S4_extractp_rp:
10525
0
    case Hexagon::S4_vxaddsubh:
10526
0
    case Hexagon::S4_vxaddsubhr:
10527
0
    case Hexagon::S4_vxaddsubw:
10528
0
    case Hexagon::S4_vxsubaddh:
10529
0
    case Hexagon::S4_vxsubaddhr:
10530
0
    case Hexagon::S4_vxsubaddw:
10531
0
    case Hexagon::S6_vtrunehb_ppp:
10532
0
    case Hexagon::S6_vtrunohb_ppp: {
10533
      // op: Rss32
10534
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10535
0
      op &= UINT64_C(31);
10536
0
      op <<= 16;
10537
0
      Value |= op;
10538
      // op: Rtt32
10539
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10540
0
      op &= UINT64_C(31);
10541
0
      op <<= 8;
10542
0
      Value |= op;
10543
      // op: Rdd32
10544
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10545
0
      op &= UINT64_C(31);
10546
0
      Value |= op;
10547
0
      break;
10548
0
    }
10549
0
    case Hexagon::Y4_tfrspcp: {
10550
      // op: Rss32
10551
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10552
0
      op &= UINT64_C(31);
10553
0
      op <<= 16;
10554
0
      Value |= op;
10555
      // op: Sdd128
10556
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10557
0
      op &= UINT64_C(127);
10558
0
      Value |= op;
10559
0
      break;
10560
0
    }
10561
0
    case Hexagon::S2_asl_r_p_acc:
10562
0
    case Hexagon::S2_asl_r_p_and:
10563
0
    case Hexagon::S2_asl_r_p_nac:
10564
0
    case Hexagon::S2_asl_r_p_or:
10565
0
    case Hexagon::S2_asl_r_p_xor:
10566
0
    case Hexagon::S2_asr_r_p_acc:
10567
0
    case Hexagon::S2_asr_r_p_and:
10568
0
    case Hexagon::S2_asr_r_p_nac:
10569
0
    case Hexagon::S2_asr_r_p_or:
10570
0
    case Hexagon::S2_asr_r_p_xor:
10571
0
    case Hexagon::S2_lsl_r_p_acc:
10572
0
    case Hexagon::S2_lsl_r_p_and:
10573
0
    case Hexagon::S2_lsl_r_p_nac:
10574
0
    case Hexagon::S2_lsl_r_p_or:
10575
0
    case Hexagon::S2_lsl_r_p_xor:
10576
0
    case Hexagon::S2_lsr_r_p_acc:
10577
0
    case Hexagon::S2_lsr_r_p_and:
10578
0
    case Hexagon::S2_lsr_r_p_nac:
10579
0
    case Hexagon::S2_lsr_r_p_or:
10580
0
    case Hexagon::S2_lsr_r_p_xor:
10581
0
    case Hexagon::S2_vrcnegh: {
10582
      // op: Rss32
10583
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10584
0
      op &= UINT64_C(31);
10585
0
      op <<= 16;
10586
0
      Value |= op;
10587
      // op: Rt32
10588
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10589
0
      op &= UINT64_C(31);
10590
0
      op <<= 8;
10591
0
      Value |= op;
10592
      // op: Rxx32
10593
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10594
0
      op &= UINT64_C(31);
10595
0
      Value |= op;
10596
0
      break;
10597
0
    }
10598
0
    case Hexagon::A4_addp_c:
10599
0
    case Hexagon::A4_subp_c: {
10600
      // op: Rss32
10601
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10602
0
      op &= UINT64_C(31);
10603
0
      op <<= 16;
10604
0
      Value |= op;
10605
      // op: Rtt32
10606
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10607
0
      op &= UINT64_C(31);
10608
0
      op <<= 8;
10609
0
      Value |= op;
10610
      // op: Rdd32
10611
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10612
0
      op &= UINT64_C(31);
10613
0
      Value |= op;
10614
      // op: Px4
10615
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10616
0
      op &= UINT64_C(3);
10617
0
      op <<= 5;
10618
0
      Value |= op;
10619
0
      break;
10620
0
    }
10621
0
    case Hexagon::A2_vraddub_acc:
10622
0
    case Hexagon::A2_vrsadub_acc:
10623
0
    case Hexagon::F2_dfmpyhh:
10624
0
    case Hexagon::F2_dfmpylh:
10625
0
    case Hexagon::M2_mmachs_rs0:
10626
0
    case Hexagon::M2_mmachs_rs1:
10627
0
    case Hexagon::M2_mmachs_s0:
10628
0
    case Hexagon::M2_mmachs_s1:
10629
0
    case Hexagon::M2_mmacls_rs0:
10630
0
    case Hexagon::M2_mmacls_rs1:
10631
0
    case Hexagon::M2_mmacls_s0:
10632
0
    case Hexagon::M2_mmacls_s1:
10633
0
    case Hexagon::M2_mmacuhs_rs0:
10634
0
    case Hexagon::M2_mmacuhs_rs1:
10635
0
    case Hexagon::M2_mmacuhs_s0:
10636
0
    case Hexagon::M2_mmacuhs_s1:
10637
0
    case Hexagon::M2_mmaculs_rs0:
10638
0
    case Hexagon::M2_mmaculs_rs1:
10639
0
    case Hexagon::M2_mmaculs_s0:
10640
0
    case Hexagon::M2_mmaculs_s1:
10641
0
    case Hexagon::M2_vcmac_s0_sat_i:
10642
0
    case Hexagon::M2_vcmac_s0_sat_r:
10643
0
    case Hexagon::M2_vdmacs_s0:
10644
0
    case Hexagon::M2_vdmacs_s1:
10645
0
    case Hexagon::M2_vmac2es:
10646
0
    case Hexagon::M2_vmac2es_s0:
10647
0
    case Hexagon::M2_vmac2es_s1:
10648
0
    case Hexagon::M2_vrcmaci_s0:
10649
0
    case Hexagon::M2_vrcmaci_s0c:
10650
0
    case Hexagon::M2_vrcmacr_s0:
10651
0
    case Hexagon::M2_vrcmacr_s0c:
10652
0
    case Hexagon::M2_vrcmpys_acc_s1_h:
10653
0
    case Hexagon::M2_vrcmpys_acc_s1_l:
10654
0
    case Hexagon::M2_vrmac_s0:
10655
0
    case Hexagon::M4_vrmpyeh_acc_s0:
10656
0
    case Hexagon::M4_vrmpyeh_acc_s1:
10657
0
    case Hexagon::M4_vrmpyoh_acc_s0:
10658
0
    case Hexagon::M4_vrmpyoh_acc_s1:
10659
0
    case Hexagon::M4_xor_xacc:
10660
0
    case Hexagon::M5_vdmacbsu:
10661
0
    case Hexagon::M5_vrmacbsu:
10662
0
    case Hexagon::M5_vrmacbuu:
10663
0
    case Hexagon::M7_dcmpyiw_acc:
10664
0
    case Hexagon::M7_dcmpyiwc_acc:
10665
0
    case Hexagon::M7_dcmpyrw_acc:
10666
0
    case Hexagon::M7_dcmpyrwc_acc:
10667
0
    case Hexagon::S2_insertp_rp: {
10668
      // op: Rss32
10669
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10670
0
      op &= UINT64_C(31);
10671
0
      op <<= 16;
10672
0
      Value |= op;
10673
      // op: Rtt32
10674
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10675
0
      op &= UINT64_C(31);
10676
0
      op <<= 8;
10677
0
      Value |= op;
10678
      // op: Rxx32
10679
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10680
0
      op &= UINT64_C(31);
10681
0
      Value |= op;
10682
0
      break;
10683
0
    }
10684
0
    case Hexagon::A4_vrmaxh:
10685
0
    case Hexagon::A4_vrmaxuh:
10686
0
    case Hexagon::A4_vrmaxuw:
10687
0
    case Hexagon::A4_vrmaxw:
10688
0
    case Hexagon::A4_vrminh:
10689
0
    case Hexagon::A4_vrminuh:
10690
0
    case Hexagon::A4_vrminuw:
10691
0
    case Hexagon::A4_vrminw: {
10692
      // op: Rss32
10693
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10694
0
      op &= UINT64_C(31);
10695
0
      op <<= 16;
10696
0
      Value |= op;
10697
      // op: Ru32
10698
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10699
0
      op &= UINT64_C(31);
10700
0
      Value |= op;
10701
      // op: Rxx32
10702
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10703
0
      op &= UINT64_C(31);
10704
0
      op <<= 8;
10705
0
      Value |= op;
10706
0
      break;
10707
0
    }
10708
0
    case Hexagon::A5_ACS: {
10709
      // op: Rss32
10710
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10711
0
      op &= UINT64_C(31);
10712
0
      op <<= 16;
10713
0
      Value |= op;
10714
      // op: Rtt32
10715
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
10716
0
      op &= UINT64_C(31);
10717
0
      op <<= 8;
10718
0
      Value |= op;
10719
      // op: Rxx32
10720
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10721
0
      op &= UINT64_C(31);
10722
0
      Value |= op;
10723
      // op: Pe4
10724
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10725
0
      op &= UINT64_C(3);
10726
0
      op <<= 5;
10727
0
      Value |= op;
10728
0
      break;
10729
0
    }
10730
0
    case Hexagon::V6_vgathermh:
10731
0
    case Hexagon::V6_vgathermw: {
10732
      // op: Rt32
10733
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10734
0
      op &= UINT64_C(31);
10735
0
      op <<= 16;
10736
0
      Value |= op;
10737
      // op: Mu2
10738
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10739
0
      op &= UINT64_C(1);
10740
0
      op <<= 13;
10741
0
      Value |= op;
10742
      // op: Vv32
10743
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10744
0
      op &= UINT64_C(31);
10745
0
      Value |= op;
10746
0
      break;
10747
0
    }
10748
0
    case Hexagon::V6_vscattermh:
10749
0
    case Hexagon::V6_vscattermh_add:
10750
0
    case Hexagon::V6_vscattermw:
10751
0
    case Hexagon::V6_vscattermw_add: {
10752
      // op: Rt32
10753
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10754
0
      op &= UINT64_C(31);
10755
0
      op <<= 16;
10756
0
      Value |= op;
10757
      // op: Mu2
10758
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10759
0
      op &= UINT64_C(1);
10760
0
      op <<= 13;
10761
0
      Value |= op;
10762
      // op: Vv32
10763
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10764
0
      op &= UINT64_C(31);
10765
0
      op <<= 8;
10766
0
      Value |= op;
10767
      // op: Vw32
10768
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10769
0
      op &= UINT64_C(31);
10770
0
      Value |= op;
10771
0
      break;
10772
0
    }
10773
0
    case Hexagon::V6_vgathermhw: {
10774
      // op: Rt32
10775
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10776
0
      op &= UINT64_C(31);
10777
0
      op <<= 16;
10778
0
      Value |= op;
10779
      // op: Mu2
10780
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10781
0
      op &= UINT64_C(1);
10782
0
      op <<= 13;
10783
0
      Value |= op;
10784
      // op: Vvv32
10785
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10786
0
      op &= UINT64_C(31);
10787
0
      Value |= op;
10788
0
      break;
10789
0
    }
10790
0
    case Hexagon::V6_vscattermhw:
10791
0
    case Hexagon::V6_vscattermhw_add: {
10792
      // op: Rt32
10793
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10794
0
      op &= UINT64_C(31);
10795
0
      op <<= 16;
10796
0
      Value |= op;
10797
      // op: Mu2
10798
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10799
0
      op &= UINT64_C(1);
10800
0
      op <<= 13;
10801
0
      Value |= op;
10802
      // op: Vvv32
10803
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10804
0
      op &= UINT64_C(31);
10805
0
      op <<= 8;
10806
0
      Value |= op;
10807
      // op: Vw32
10808
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10809
0
      op &= UINT64_C(31);
10810
0
      Value |= op;
10811
0
      break;
10812
0
    }
10813
0
    case Hexagon::V6_pred_scalar2:
10814
0
    case Hexagon::V6_pred_scalar2v2: {
10815
      // op: Rt32
10816
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10817
0
      op &= UINT64_C(31);
10818
0
      op <<= 16;
10819
0
      Value |= op;
10820
      // op: Qd4
10821
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10822
0
      op &= UINT64_C(3);
10823
0
      Value |= op;
10824
0
      break;
10825
0
    }
10826
0
    case Hexagon::V6_lvsplatb:
10827
0
    case Hexagon::V6_lvsplath:
10828
0
    case Hexagon::V6_lvsplatw:
10829
0
    case Hexagon::V6_zextract: {
10830
      // op: Rt32
10831
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10832
0
      op &= UINT64_C(31);
10833
0
      op <<= 16;
10834
0
      Value |= op;
10835
      // op: Vd32
10836
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10837
0
      op &= UINT64_C(31);
10838
0
      Value |= op;
10839
0
      break;
10840
0
    }
10841
0
    case Hexagon::A2_addh_h16_hh:
10842
0
    case Hexagon::A2_addh_h16_hl:
10843
0
    case Hexagon::A2_addh_h16_lh:
10844
0
    case Hexagon::A2_addh_h16_ll:
10845
0
    case Hexagon::A2_addh_h16_sat_hh:
10846
0
    case Hexagon::A2_addh_h16_sat_hl:
10847
0
    case Hexagon::A2_addh_h16_sat_lh:
10848
0
    case Hexagon::A2_addh_h16_sat_ll:
10849
0
    case Hexagon::A2_addh_l16_hl:
10850
0
    case Hexagon::A2_addh_l16_ll:
10851
0
    case Hexagon::A2_addh_l16_sat_hl:
10852
0
    case Hexagon::A2_addh_l16_sat_ll:
10853
0
    case Hexagon::A2_combine_hh:
10854
0
    case Hexagon::A2_combine_hl:
10855
0
    case Hexagon::A2_combine_lh:
10856
0
    case Hexagon::A2_combine_ll:
10857
0
    case Hexagon::A2_min:
10858
0
    case Hexagon::A2_minu:
10859
0
    case Hexagon::A2_sub:
10860
0
    case Hexagon::A2_subh_h16_hh:
10861
0
    case Hexagon::A2_subh_h16_hl:
10862
0
    case Hexagon::A2_subh_h16_lh:
10863
0
    case Hexagon::A2_subh_h16_ll:
10864
0
    case Hexagon::A2_subh_h16_sat_hh:
10865
0
    case Hexagon::A2_subh_h16_sat_hl:
10866
0
    case Hexagon::A2_subh_h16_sat_lh:
10867
0
    case Hexagon::A2_subh_h16_sat_ll:
10868
0
    case Hexagon::A2_subh_l16_hl:
10869
0
    case Hexagon::A2_subh_l16_ll:
10870
0
    case Hexagon::A2_subh_l16_sat_hl:
10871
0
    case Hexagon::A2_subh_l16_sat_ll:
10872
0
    case Hexagon::A2_subsat:
10873
0
    case Hexagon::A2_svnavgh:
10874
0
    case Hexagon::A2_svsubh:
10875
0
    case Hexagon::A2_svsubhs:
10876
0
    case Hexagon::A2_svsubuhs:
10877
0
    case Hexagon::A4_andn:
10878
0
    case Hexagon::A4_orn:
10879
0
    case Hexagon::dep_A2_subsat: {
10880
      // op: Rt32
10881
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10882
0
      op &= UINT64_C(31);
10883
0
      op <<= 8;
10884
0
      Value |= op;
10885
      // op: Rs32
10886
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10887
0
      op &= UINT64_C(31);
10888
0
      op <<= 16;
10889
0
      Value |= op;
10890
      // op: Rd32
10891
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10892
0
      op &= UINT64_C(31);
10893
0
      Value |= op;
10894
0
      break;
10895
0
    }
10896
0
    case Hexagon::V6_vinsertwr: {
10897
      // op: Rt32
10898
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10899
0
      op &= UINT64_C(31);
10900
0
      op <<= 16;
10901
0
      Value |= op;
10902
      // op: Vx32
10903
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10904
0
      op &= UINT64_C(31);
10905
0
      Value |= op;
10906
0
      break;
10907
0
    }
10908
0
    case Hexagon::M2_subacc: {
10909
      // op: Rt32
10910
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10911
0
      op &= UINT64_C(31);
10912
0
      op <<= 8;
10913
0
      Value |= op;
10914
      // op: Rs32
10915
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10916
0
      op &= UINT64_C(31);
10917
0
      op <<= 16;
10918
0
      Value |= op;
10919
      // op: Rx32
10920
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10921
0
      op &= UINT64_C(31);
10922
0
      Value |= op;
10923
0
      break;
10924
0
    }
10925
0
    case Hexagon::V6_vdeal:
10926
0
    case Hexagon::V6_vshuff: {
10927
      // op: Rt32
10928
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
10929
0
      op &= UINT64_C(31);
10930
0
      op <<= 16;
10931
0
      Value |= op;
10932
      // op: Vy32
10933
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10934
0
      op &= UINT64_C(31);
10935
0
      op <<= 8;
10936
0
      Value |= op;
10937
      // op: Vx32
10938
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10939
0
      op &= UINT64_C(31);
10940
0
      Value |= op;
10941
0
      break;
10942
0
    }
10943
0
    case Hexagon::Y6_l2gcleaninvpa:
10944
0
    case Hexagon::Y6_l2gcleanpa: {
10945
      // op: Rtt32
10946
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10947
0
      op &= UINT64_C(31);
10948
0
      op <<= 8;
10949
0
      Value |= op;
10950
0
      break;
10951
0
    }
10952
0
    case Hexagon::S2_valignrb: {
10953
      // op: Rtt32
10954
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
10955
0
      op &= UINT64_C(31);
10956
0
      op <<= 8;
10957
0
      Value |= op;
10958
      // op: Rss32
10959
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
10960
0
      op &= UINT64_C(31);
10961
0
      op <<= 16;
10962
0
      Value |= op;
10963
      // op: Pu4
10964
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
10965
0
      op &= UINT64_C(3);
10966
0
      op <<= 5;
10967
0
      Value |= op;
10968
      // op: Rdd32
10969
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
10970
0
      op &= UINT64_C(31);
10971
0
      Value |= op;
10972
0
      break;
10973
0
    }
10974
0
    case Hexagon::A2_minp:
10975
0
    case Hexagon::A2_minup:
10976
0
    case Hexagon::A2_subp:
10977
0
    case Hexagon::A2_vmaxb:
10978
0
    case Hexagon::A2_vmaxh:
10979
0
    case Hexagon::A2_vmaxub:
10980
0
    case Hexagon::A2_vmaxuh:
10981
0
    case Hexagon::A2_vmaxuw:
10982
0
    case Hexagon::A2_vmaxw:
10983
0
    case Hexagon::A2_vminb:
10984
0
    case Hexagon::A2_vminh:
10985
0
    case Hexagon::A2_vminub:
10986
0
    case Hexagon::A2_vminuh:
10987
0
    case Hexagon::A2_vminuw:
10988
0
    case Hexagon::A2_vminw:
10989
0
    case Hexagon::A2_vnavgh:
10990
0
    case Hexagon::A2_vnavghcr:
10991
0
    case Hexagon::A2_vnavghr:
10992
0
    case Hexagon::A2_vnavgw:
10993
0
    case Hexagon::A2_vnavgwcr:
10994
0
    case Hexagon::A2_vnavgwr:
10995
0
    case Hexagon::A2_vsubh:
10996
0
    case Hexagon::A2_vsubhs:
10997
0
    case Hexagon::A2_vsubub:
10998
0
    case Hexagon::A2_vsububs:
10999
0
    case Hexagon::A2_vsubuhs:
11000
0
    case Hexagon::A2_vsubw:
11001
0
    case Hexagon::A2_vsubws:
11002
0
    case Hexagon::A4_andnp:
11003
0
    case Hexagon::A4_ornp:
11004
0
    case Hexagon::M2_vabsdiffh:
11005
0
    case Hexagon::M2_vabsdiffw:
11006
0
    case Hexagon::M6_vabsdiffb:
11007
0
    case Hexagon::M6_vabsdiffub:
11008
0
    case Hexagon::S2_shuffob:
11009
0
    case Hexagon::S2_shuffoh: {
11010
      // op: Rtt32
11011
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11012
0
      op &= UINT64_C(31);
11013
0
      op <<= 8;
11014
0
      Value |= op;
11015
      // op: Rss32
11016
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11017
0
      op &= UINT64_C(31);
11018
0
      op <<= 16;
11019
0
      Value |= op;
11020
      // op: Rdd32
11021
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11022
0
      op &= UINT64_C(31);
11023
0
      Value |= op;
11024
0
      break;
11025
0
    }
11026
0
    case Hexagon::A6_vminub_RdP: {
11027
      // op: Rtt32
11028
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11029
0
      op &= UINT64_C(31);
11030
0
      op <<= 8;
11031
0
      Value |= op;
11032
      // op: Rss32
11033
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11034
0
      op &= UINT64_C(31);
11035
0
      op <<= 16;
11036
0
      Value |= op;
11037
      // op: Rdd32
11038
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11039
0
      op &= UINT64_C(31);
11040
0
      Value |= op;
11041
      // op: Pe4
11042
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11043
0
      op &= UINT64_C(3);
11044
0
      op <<= 5;
11045
0
      Value |= op;
11046
0
      break;
11047
0
    }
11048
0
    case Hexagon::M4_mpyrr_addr: {
11049
      // op: Ru32
11050
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11051
0
      op &= UINT64_C(31);
11052
0
      Value |= op;
11053
      // op: Rs32
11054
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11055
0
      op &= UINT64_C(31);
11056
0
      op <<= 16;
11057
0
      Value |= op;
11058
      // op: Ry32
11059
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11060
0
      op &= UINT64_C(31);
11061
0
      op <<= 8;
11062
0
      Value |= op;
11063
0
      break;
11064
0
    }
11065
0
    case Hexagon::Y2_crswap0:
11066
0
    case Hexagon::Y4_crswap1: {
11067
      // op: Rx32
11068
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11069
0
      op &= UINT64_C(31);
11070
0
      op <<= 16;
11071
0
      Value |= op;
11072
0
      break;
11073
0
    }
11074
0
    case Hexagon::Y4_crswap10: {
11075
      // op: Rxx32
11076
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11077
0
      op &= UINT64_C(31);
11078
0
      op <<= 16;
11079
0
      Value |= op;
11080
0
      break;
11081
0
    }
11082
0
    case Hexagon::Y2_tfrscrr: {
11083
      // op: Ss128
11084
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11085
0
      op &= UINT64_C(127);
11086
0
      op <<= 16;
11087
0
      Value |= op;
11088
      // op: Rd32
11089
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11090
0
      op &= UINT64_C(31);
11091
0
      Value |= op;
11092
0
      break;
11093
0
    }
11094
0
    case Hexagon::Y4_tfrscpp: {
11095
      // op: Sss128
11096
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11097
0
      op &= UINT64_C(127);
11098
0
      op <<= 16;
11099
0
      Value |= op;
11100
      // op: Rdd32
11101
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11102
0
      op &= UINT64_C(31);
11103
0
      Value |= op;
11104
0
      break;
11105
0
    }
11106
0
    case Hexagon::V6_extractw: {
11107
      // op: Vu32
11108
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11109
0
      op &= UINT64_C(31);
11110
0
      op <<= 8;
11111
0
      Value |= op;
11112
      // op: Rs32
11113
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11114
0
      op &= UINT64_C(31);
11115
0
      op <<= 16;
11116
0
      Value |= op;
11117
      // op: Rd32
11118
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11119
0
      op &= UINT64_C(31);
11120
0
      Value |= op;
11121
0
      break;
11122
0
    }
11123
0
    case Hexagon::V6_vandvrt: {
11124
      // op: Vu32
11125
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11126
0
      op &= UINT64_C(31);
11127
0
      op <<= 8;
11128
0
      Value |= op;
11129
      // op: Rt32
11130
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11131
0
      op &= UINT64_C(31);
11132
0
      op <<= 16;
11133
0
      Value |= op;
11134
      // op: Qd4
11135
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11136
0
      op &= UINT64_C(3);
11137
0
      Value |= op;
11138
0
      break;
11139
0
    }
11140
0
    case Hexagon::V6_vaslh:
11141
0
    case Hexagon::V6_vaslw:
11142
0
    case Hexagon::V6_vasrh:
11143
0
    case Hexagon::V6_vasrw:
11144
0
    case Hexagon::V6_vdmpybus:
11145
0
    case Hexagon::V6_vdmpyhb:
11146
0
    case Hexagon::V6_vdmpyhsat:
11147
0
    case Hexagon::V6_vdmpyhsusat:
11148
0
    case Hexagon::V6_vlsrb:
11149
0
    case Hexagon::V6_vlsrh:
11150
0
    case Hexagon::V6_vlsrw:
11151
0
    case Hexagon::V6_vmpyhsrs:
11152
0
    case Hexagon::V6_vmpyhss:
11153
0
    case Hexagon::V6_vmpyihb:
11154
0
    case Hexagon::V6_vmpyiwb:
11155
0
    case Hexagon::V6_vmpyiwh:
11156
0
    case Hexagon::V6_vmpyiwub:
11157
0
    case Hexagon::V6_vmpyuhe:
11158
0
    case Hexagon::V6_vrmpybus:
11159
0
    case Hexagon::V6_vrmpyub:
11160
0
    case Hexagon::V6_vror: {
11161
      // op: Vu32
11162
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11163
0
      op &= UINT64_C(31);
11164
0
      op <<= 8;
11165
0
      Value |= op;
11166
      // op: Rt32
11167
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11168
0
      op &= UINT64_C(31);
11169
0
      op <<= 16;
11170
0
      Value |= op;
11171
      // op: Vd32
11172
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11173
0
      op &= UINT64_C(31);
11174
0
      Value |= op;
11175
0
      break;
11176
0
    }
11177
0
    case Hexagon::V6_vmpybus:
11178
0
    case Hexagon::V6_vmpyh:
11179
0
    case Hexagon::V6_vmpyub:
11180
0
    case Hexagon::V6_vmpyuh: {
11181
      // op: Vu32
11182
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11183
0
      op &= UINT64_C(31);
11184
0
      op <<= 8;
11185
0
      Value |= op;
11186
      // op: Rt32
11187
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11188
0
      op &= UINT64_C(31);
11189
0
      op <<= 16;
11190
0
      Value |= op;
11191
      // op: Vdd32
11192
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11193
0
      op &= UINT64_C(31);
11194
0
      Value |= op;
11195
0
      break;
11196
0
    }
11197
0
    case Hexagon::V6_vrmpyzbb_rt:
11198
0
    case Hexagon::V6_vrmpyzbub_rt:
11199
0
    case Hexagon::V6_vrmpyzcb_rt:
11200
0
    case Hexagon::V6_vrmpyzcbs_rt:
11201
0
    case Hexagon::V6_vrmpyznb_rt: {
11202
      // op: Vu32
11203
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11204
0
      op &= UINT64_C(31);
11205
0
      op <<= 8;
11206
0
      Value |= op;
11207
      // op: Rt8
11208
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11209
0
      op &= UINT64_C(7);
11210
0
      op <<= 16;
11211
0
      Value |= op;
11212
      // op: Vdddd32
11213
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11214
0
      op &= UINT64_C(31);
11215
0
      Value |= op;
11216
0
      break;
11217
0
    }
11218
0
    case Hexagon::V6_vlut4: {
11219
      // op: Vu32
11220
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11221
0
      op &= UINT64_C(31);
11222
0
      op <<= 8;
11223
0
      Value |= op;
11224
      // op: Rtt32
11225
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11226
0
      op &= UINT64_C(31);
11227
0
      op <<= 16;
11228
0
      Value |= op;
11229
      // op: Vd32
11230
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11231
0
      op &= UINT64_C(31);
11232
0
      Value |= op;
11233
0
      break;
11234
0
    }
11235
0
    case Hexagon::V6_vrmpybub_rtt:
11236
0
    case Hexagon::V6_vrmpyub_rtt: {
11237
      // op: Vu32
11238
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11239
0
      op &= UINT64_C(31);
11240
0
      op <<= 8;
11241
0
      Value |= op;
11242
      // op: Rtt32
11243
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11244
0
      op &= UINT64_C(31);
11245
0
      op <<= 16;
11246
0
      Value |= op;
11247
      // op: Vdd32
11248
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11249
0
      op &= UINT64_C(31);
11250
0
      Value |= op;
11251
0
      break;
11252
0
    }
11253
0
    case Hexagon::V6_vabs_hf:
11254
0
    case Hexagon::V6_vabs_sf:
11255
0
    case Hexagon::V6_vabsb:
11256
0
    case Hexagon::V6_vabsb_sat:
11257
0
    case Hexagon::V6_vabsh:
11258
0
    case Hexagon::V6_vabsh_sat:
11259
0
    case Hexagon::V6_vabsw:
11260
0
    case Hexagon::V6_vabsw_sat:
11261
0
    case Hexagon::V6_vassign:
11262
0
    case Hexagon::V6_vassign_fp:
11263
0
    case Hexagon::V6_vassign_tmp:
11264
0
    case Hexagon::V6_vcl0h:
11265
0
    case Hexagon::V6_vcl0w:
11266
0
    case Hexagon::V6_vconv_h_hf:
11267
0
    case Hexagon::V6_vconv_hf_h:
11268
0
    case Hexagon::V6_vconv_hf_qf16:
11269
0
    case Hexagon::V6_vconv_sf_qf32:
11270
0
    case Hexagon::V6_vconv_sf_w:
11271
0
    case Hexagon::V6_vconv_w_sf:
11272
0
    case Hexagon::V6_vcvt_h_hf:
11273
0
    case Hexagon::V6_vcvt_hf_h:
11274
0
    case Hexagon::V6_vcvt_hf_uh:
11275
0
    case Hexagon::V6_vcvt_uh_hf:
11276
0
    case Hexagon::V6_vdealb:
11277
0
    case Hexagon::V6_vdealh:
11278
0
    case Hexagon::V6_vfneg_hf:
11279
0
    case Hexagon::V6_vfneg_sf:
11280
0
    case Hexagon::V6_vnormamth:
11281
0
    case Hexagon::V6_vnormamtw:
11282
0
    case Hexagon::V6_vnot:
11283
0
    case Hexagon::V6_vpopcounth:
11284
0
    case Hexagon::V6_vshuffb:
11285
0
    case Hexagon::V6_vshuffh: {
11286
      // op: Vu32
11287
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11288
0
      op &= UINT64_C(31);
11289
0
      op <<= 8;
11290
0
      Value |= op;
11291
      // op: Vd32
11292
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11293
0
      op &= UINT64_C(31);
11294
0
      Value |= op;
11295
0
      break;
11296
0
    }
11297
0
    case Hexagon::V6_vcvt_hf_b:
11298
0
    case Hexagon::V6_vcvt_hf_ub:
11299
0
    case Hexagon::V6_vcvt_sf_hf:
11300
0
    case Hexagon::V6_vsb:
11301
0
    case Hexagon::V6_vsh:
11302
0
    case Hexagon::V6_vunpackb:
11303
0
    case Hexagon::V6_vunpackh:
11304
0
    case Hexagon::V6_vunpackub:
11305
0
    case Hexagon::V6_vunpackuh:
11306
0
    case Hexagon::V6_vzb:
11307
0
    case Hexagon::V6_vzh: {
11308
      // op: Vu32
11309
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11310
0
      op &= UINT64_C(31);
11311
0
      op <<= 8;
11312
0
      Value |= op;
11313
      // op: Vdd32
11314
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11315
0
      op &= UINT64_C(31);
11316
0
      Value |= op;
11317
0
      break;
11318
0
    }
11319
0
    case Hexagon::V6_veqb:
11320
0
    case Hexagon::V6_veqh:
11321
0
    case Hexagon::V6_veqw:
11322
0
    case Hexagon::V6_vgtb:
11323
0
    case Hexagon::V6_vgtbf:
11324
0
    case Hexagon::V6_vgth:
11325
0
    case Hexagon::V6_vgthf:
11326
0
    case Hexagon::V6_vgtsf:
11327
0
    case Hexagon::V6_vgtub:
11328
0
    case Hexagon::V6_vgtuh:
11329
0
    case Hexagon::V6_vgtuw:
11330
0
    case Hexagon::V6_vgtw: {
11331
      // op: Vu32
11332
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11333
0
      op &= UINT64_C(31);
11334
0
      op <<= 8;
11335
0
      Value |= op;
11336
      // op: Vv32
11337
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11338
0
      op &= UINT64_C(31);
11339
0
      op <<= 16;
11340
0
      Value |= op;
11341
      // op: Qd4
11342
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11343
0
      op &= UINT64_C(3);
11344
0
      Value |= op;
11345
0
      break;
11346
0
    }
11347
0
    case Hexagon::V6_vaddcarrysat: {
11348
      // op: Vu32
11349
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11350
0
      op &= UINT64_C(31);
11351
0
      op <<= 8;
11352
0
      Value |= op;
11353
      // op: Vv32
11354
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11355
0
      op &= UINT64_C(31);
11356
0
      op <<= 16;
11357
0
      Value |= op;
11358
      // op: Qs4
11359
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11360
0
      op &= UINT64_C(3);
11361
0
      op <<= 5;
11362
0
      Value |= op;
11363
      // op: Vd32
11364
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11365
0
      op &= UINT64_C(31);
11366
0
      Value |= op;
11367
0
      break;
11368
0
    }
11369
0
    case Hexagon::V6_vabsdiffh:
11370
0
    case Hexagon::V6_vabsdiffub:
11371
0
    case Hexagon::V6_vabsdiffuh:
11372
0
    case Hexagon::V6_vabsdiffw:
11373
0
    case Hexagon::V6_vadd_hf:
11374
0
    case Hexagon::V6_vadd_hf_hf:
11375
0
    case Hexagon::V6_vadd_qf16:
11376
0
    case Hexagon::V6_vadd_qf16_mix:
11377
0
    case Hexagon::V6_vadd_qf32:
11378
0
    case Hexagon::V6_vadd_qf32_mix:
11379
0
    case Hexagon::V6_vadd_sf:
11380
0
    case Hexagon::V6_vadd_sf_sf:
11381
0
    case Hexagon::V6_vaddb:
11382
0
    case Hexagon::V6_vaddbsat:
11383
0
    case Hexagon::V6_vaddclbh:
11384
0
    case Hexagon::V6_vaddclbw:
11385
0
    case Hexagon::V6_vaddh:
11386
0
    case Hexagon::V6_vaddhsat:
11387
0
    case Hexagon::V6_vaddubsat:
11388
0
    case Hexagon::V6_vaddububb_sat:
11389
0
    case Hexagon::V6_vadduhsat:
11390
0
    case Hexagon::V6_vadduwsat:
11391
0
    case Hexagon::V6_vaddw:
11392
0
    case Hexagon::V6_vaddwsat:
11393
0
    case Hexagon::V6_vand:
11394
0
    case Hexagon::V6_vaslhv:
11395
0
    case Hexagon::V6_vaslwv:
11396
0
    case Hexagon::V6_vasrhv:
11397
0
    case Hexagon::V6_vasrwv:
11398
0
    case Hexagon::V6_vavgb:
11399
0
    case Hexagon::V6_vavgbrnd:
11400
0
    case Hexagon::V6_vavgh:
11401
0
    case Hexagon::V6_vavghrnd:
11402
0
    case Hexagon::V6_vavgub:
11403
0
    case Hexagon::V6_vavgubrnd:
11404
0
    case Hexagon::V6_vavguh:
11405
0
    case Hexagon::V6_vavguhrnd:
11406
0
    case Hexagon::V6_vavguw:
11407
0
    case Hexagon::V6_vavguwrnd:
11408
0
    case Hexagon::V6_vavgw:
11409
0
    case Hexagon::V6_vavgwrnd:
11410
0
    case Hexagon::V6_vcvt_b_hf:
11411
0
    case Hexagon::V6_vcvt_bf_sf:
11412
0
    case Hexagon::V6_vcvt_hf_sf:
11413
0
    case Hexagon::V6_vcvt_ub_hf:
11414
0
    case Hexagon::V6_vdealb4w:
11415
0
    case Hexagon::V6_vdelta:
11416
0
    case Hexagon::V6_vdmpy_sf_hf:
11417
0
    case Hexagon::V6_vdmpyhvsat:
11418
0
    case Hexagon::V6_vfmax_hf:
11419
0
    case Hexagon::V6_vfmax_sf:
11420
0
    case Hexagon::V6_vfmin_hf:
11421
0
    case Hexagon::V6_vfmin_sf:
11422
0
    case Hexagon::V6_vlsrhv:
11423
0
    case Hexagon::V6_vlsrwv:
11424
0
    case Hexagon::V6_vmax_bf:
11425
0
    case Hexagon::V6_vmax_hf:
11426
0
    case Hexagon::V6_vmax_sf:
11427
0
    case Hexagon::V6_vmaxb:
11428
0
    case Hexagon::V6_vmaxh:
11429
0
    case Hexagon::V6_vmaxub:
11430
0
    case Hexagon::V6_vmaxuh:
11431
0
    case Hexagon::V6_vmaxw:
11432
0
    case Hexagon::V6_vmin_bf:
11433
0
    case Hexagon::V6_vmin_hf:
11434
0
    case Hexagon::V6_vmin_sf:
11435
0
    case Hexagon::V6_vminb:
11436
0
    case Hexagon::V6_vminh:
11437
0
    case Hexagon::V6_vminub:
11438
0
    case Hexagon::V6_vminuh:
11439
0
    case Hexagon::V6_vminw:
11440
0
    case Hexagon::V6_vmpy_hf_hf:
11441
0
    case Hexagon::V6_vmpy_qf16:
11442
0
    case Hexagon::V6_vmpy_qf16_hf:
11443
0
    case Hexagon::V6_vmpy_qf16_mix_hf:
11444
0
    case Hexagon::V6_vmpy_qf32:
11445
0
    case Hexagon::V6_vmpy_qf32_sf:
11446
0
    case Hexagon::V6_vmpy_sf_sf:
11447
0
    case Hexagon::V6_vmpyewuh:
11448
0
    case Hexagon::V6_vmpyhvsrs:
11449
0
    case Hexagon::V6_vmpyieoh:
11450
0
    case Hexagon::V6_vmpyiewuh:
11451
0
    case Hexagon::V6_vmpyih:
11452
0
    case Hexagon::V6_vmpyiowh:
11453
0
    case Hexagon::V6_vmpyowh:
11454
0
    case Hexagon::V6_vmpyowh_rnd:
11455
0
    case Hexagon::V6_vmpyuhvs:
11456
0
    case Hexagon::V6_vnavgb:
11457
0
    case Hexagon::V6_vnavgh:
11458
0
    case Hexagon::V6_vnavgub:
11459
0
    case Hexagon::V6_vnavgw:
11460
0
    case Hexagon::V6_vor:
11461
0
    case Hexagon::V6_vpackeb:
11462
0
    case Hexagon::V6_vpackeh:
11463
0
    case Hexagon::V6_vpackhb_sat:
11464
0
    case Hexagon::V6_vpackhub_sat:
11465
0
    case Hexagon::V6_vpackob:
11466
0
    case Hexagon::V6_vpackoh:
11467
0
    case Hexagon::V6_vpackwh_sat:
11468
0
    case Hexagon::V6_vpackwuh_sat:
11469
0
    case Hexagon::V6_vrdelta:
11470
0
    case Hexagon::V6_vrmpybusv:
11471
0
    case Hexagon::V6_vrmpybv:
11472
0
    case Hexagon::V6_vrmpyubv:
11473
0
    case Hexagon::V6_vrotr:
11474
0
    case Hexagon::V6_vroundhb:
11475
0
    case Hexagon::V6_vroundhub:
11476
0
    case Hexagon::V6_vrounduhub:
11477
0
    case Hexagon::V6_vrounduwuh:
11478
0
    case Hexagon::V6_vroundwh:
11479
0
    case Hexagon::V6_vroundwuh:
11480
0
    case Hexagon::V6_vsatdw:
11481
0
    case Hexagon::V6_vsathub:
11482
0
    case Hexagon::V6_vsatuwuh:
11483
0
    case Hexagon::V6_vsatwh:
11484
0
    case Hexagon::V6_vshufeh:
11485
0
    case Hexagon::V6_vshuffeb:
11486
0
    case Hexagon::V6_vshuffob:
11487
0
    case Hexagon::V6_vshufoh:
11488
0
    case Hexagon::V6_vsub_hf:
11489
0
    case Hexagon::V6_vsub_hf_hf:
11490
0
    case Hexagon::V6_vsub_qf16:
11491
0
    case Hexagon::V6_vsub_qf16_mix:
11492
0
    case Hexagon::V6_vsub_qf32:
11493
0
    case Hexagon::V6_vsub_qf32_mix:
11494
0
    case Hexagon::V6_vsub_sf:
11495
0
    case Hexagon::V6_vsub_sf_sf:
11496
0
    case Hexagon::V6_vsubb:
11497
0
    case Hexagon::V6_vsubbsat:
11498
0
    case Hexagon::V6_vsubh:
11499
0
    case Hexagon::V6_vsubhsat:
11500
0
    case Hexagon::V6_vsububsat:
11501
0
    case Hexagon::V6_vsubububb_sat:
11502
0
    case Hexagon::V6_vsubuhsat:
11503
0
    case Hexagon::V6_vsubuwsat:
11504
0
    case Hexagon::V6_vsubw:
11505
0
    case Hexagon::V6_vsubwsat:
11506
0
    case Hexagon::V6_vxor: {
11507
      // op: Vu32
11508
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11509
0
      op &= UINT64_C(31);
11510
0
      op <<= 8;
11511
0
      Value |= op;
11512
      // op: Vv32
11513
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11514
0
      op &= UINT64_C(31);
11515
0
      op <<= 16;
11516
0
      Value |= op;
11517
      // op: Vd32
11518
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11519
0
      op &= UINT64_C(31);
11520
0
      Value |= op;
11521
0
      break;
11522
0
    }
11523
0
    case Hexagon::V6_vadd_sf_bf:
11524
0
    case Hexagon::V6_vadd_sf_hf:
11525
0
    case Hexagon::V6_vaddhw:
11526
0
    case Hexagon::V6_vaddubh:
11527
0
    case Hexagon::V6_vadduhw:
11528
0
    case Hexagon::V6_vcombine:
11529
0
    case Hexagon::V6_vcombine_tmp:
11530
0
    case Hexagon::V6_vmpy_qf32_hf:
11531
0
    case Hexagon::V6_vmpy_qf32_mix_hf:
11532
0
    case Hexagon::V6_vmpy_qf32_qf16:
11533
0
    case Hexagon::V6_vmpy_sf_bf:
11534
0
    case Hexagon::V6_vmpy_sf_hf:
11535
0
    case Hexagon::V6_vmpybusv:
11536
0
    case Hexagon::V6_vmpybv:
11537
0
    case Hexagon::V6_vmpyewuh_64:
11538
0
    case Hexagon::V6_vmpyhus:
11539
0
    case Hexagon::V6_vmpyhv:
11540
0
    case Hexagon::V6_vmpyubv:
11541
0
    case Hexagon::V6_vmpyuhv:
11542
0
    case Hexagon::V6_vshufoeb:
11543
0
    case Hexagon::V6_vshufoeh:
11544
0
    case Hexagon::V6_vsub_sf_bf:
11545
0
    case Hexagon::V6_vsub_sf_hf:
11546
0
    case Hexagon::V6_vsubhw:
11547
0
    case Hexagon::V6_vsububh:
11548
0
    case Hexagon::V6_vsubuhw: {
11549
      // op: Vu32
11550
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11551
0
      op &= UINT64_C(31);
11552
0
      op <<= 8;
11553
0
      Value |= op;
11554
      // op: Vv32
11555
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11556
0
      op &= UINT64_C(31);
11557
0
      op <<= 16;
11558
0
      Value |= op;
11559
      // op: Vdd32
11560
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11561
0
      op &= UINT64_C(31);
11562
0
      Value |= op;
11563
0
      break;
11564
0
    }
11565
0
    case Hexagon::V6_valignb:
11566
0
    case Hexagon::V6_vasrhbrndsat:
11567
0
    case Hexagon::V6_vasrhbsat:
11568
0
    case Hexagon::V6_vasrhubrndsat:
11569
0
    case Hexagon::V6_vasrhubsat:
11570
0
    case Hexagon::V6_vasruhubrndsat:
11571
0
    case Hexagon::V6_vasruhubsat:
11572
0
    case Hexagon::V6_vasruwuhrndsat:
11573
0
    case Hexagon::V6_vasruwuhsat:
11574
0
    case Hexagon::V6_vasrwh:
11575
0
    case Hexagon::V6_vasrwhrndsat:
11576
0
    case Hexagon::V6_vasrwhsat:
11577
0
    case Hexagon::V6_vasrwuhrndsat:
11578
0
    case Hexagon::V6_vasrwuhsat:
11579
0
    case Hexagon::V6_vlalignb:
11580
0
    case Hexagon::V6_vlutvvb:
11581
0
    case Hexagon::V6_vlutvvb_nm: {
11582
      // op: Vu32
11583
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11584
0
      op &= UINT64_C(31);
11585
0
      op <<= 8;
11586
0
      Value |= op;
11587
      // op: Vv32
11588
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11589
0
      op &= UINT64_C(31);
11590
0
      op <<= 19;
11591
0
      Value |= op;
11592
      // op: Rt8
11593
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11594
0
      op &= UINT64_C(7);
11595
0
      op <<= 16;
11596
0
      Value |= op;
11597
      // op: Vd32
11598
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11599
0
      op &= UINT64_C(31);
11600
0
      Value |= op;
11601
0
      break;
11602
0
    }
11603
0
    case Hexagon::V6_vdealvdd:
11604
0
    case Hexagon::V6_vlutvwh:
11605
0
    case Hexagon::V6_vlutvwh_nm:
11606
0
    case Hexagon::V6_vshuffvdd: {
11607
      // op: Vu32
11608
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11609
0
      op &= UINT64_C(31);
11610
0
      op <<= 8;
11611
0
      Value |= op;
11612
      // op: Vv32
11613
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11614
0
      op &= UINT64_C(31);
11615
0
      op <<= 19;
11616
0
      Value |= op;
11617
      // op: Rt8
11618
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11619
0
      op &= UINT64_C(7);
11620
0
      op <<= 16;
11621
0
      Value |= op;
11622
      // op: Vdd32
11623
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11624
0
      op &= UINT64_C(31);
11625
0
      Value |= op;
11626
0
      break;
11627
0
    }
11628
0
    case Hexagon::V6_vandvrt_acc: {
11629
      // op: Vu32
11630
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11631
0
      op &= UINT64_C(31);
11632
0
      op <<= 8;
11633
0
      Value |= op;
11634
      // op: Rt32
11635
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11636
0
      op &= UINT64_C(31);
11637
0
      op <<= 16;
11638
0
      Value |= op;
11639
      // op: Qx4
11640
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11641
0
      op &= UINT64_C(3);
11642
0
      Value |= op;
11643
0
      break;
11644
0
    }
11645
0
    case Hexagon::V6_vaslh_acc:
11646
0
    case Hexagon::V6_vaslw_acc:
11647
0
    case Hexagon::V6_vasrh_acc:
11648
0
    case Hexagon::V6_vasrw_acc:
11649
0
    case Hexagon::V6_vdmpybus_acc:
11650
0
    case Hexagon::V6_vdmpyhb_acc:
11651
0
    case Hexagon::V6_vdmpyhsat_acc:
11652
0
    case Hexagon::V6_vdmpyhsusat_acc:
11653
0
    case Hexagon::V6_vmpyihb_acc:
11654
0
    case Hexagon::V6_vmpyiwb_acc:
11655
0
    case Hexagon::V6_vmpyiwh_acc:
11656
0
    case Hexagon::V6_vmpyiwub_acc:
11657
0
    case Hexagon::V6_vmpyuhe_acc:
11658
0
    case Hexagon::V6_vrmpybus_acc:
11659
0
    case Hexagon::V6_vrmpyub_acc: {
11660
      // op: Vu32
11661
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11662
0
      op &= UINT64_C(31);
11663
0
      op <<= 8;
11664
0
      Value |= op;
11665
      // op: Rt32
11666
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11667
0
      op &= UINT64_C(31);
11668
0
      op <<= 16;
11669
0
      Value |= op;
11670
      // op: Vx32
11671
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11672
0
      op &= UINT64_C(31);
11673
0
      Value |= op;
11674
0
      break;
11675
0
    }
11676
0
    case Hexagon::V6_vmpybus_acc:
11677
0
    case Hexagon::V6_vmpyh_acc:
11678
0
    case Hexagon::V6_vmpyhsat_acc:
11679
0
    case Hexagon::V6_vmpyub_acc:
11680
0
    case Hexagon::V6_vmpyuh_acc: {
11681
      // op: Vu32
11682
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11683
0
      op &= UINT64_C(31);
11684
0
      op <<= 8;
11685
0
      Value |= op;
11686
      // op: Rt32
11687
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11688
0
      op &= UINT64_C(31);
11689
0
      op <<= 16;
11690
0
      Value |= op;
11691
      // op: Vxx32
11692
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11693
0
      op &= UINT64_C(31);
11694
0
      Value |= op;
11695
0
      break;
11696
0
    }
11697
0
    case Hexagon::V6_vrmpyzbb_rt_acc:
11698
0
    case Hexagon::V6_vrmpyzbub_rt_acc:
11699
0
    case Hexagon::V6_vrmpyzcb_rt_acc:
11700
0
    case Hexagon::V6_vrmpyzcbs_rt_acc:
11701
0
    case Hexagon::V6_vrmpyznb_rt_acc: {
11702
      // op: Vu32
11703
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11704
0
      op &= UINT64_C(31);
11705
0
      op <<= 8;
11706
0
      Value |= op;
11707
      // op: Rt8
11708
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11709
0
      op &= UINT64_C(7);
11710
0
      op <<= 16;
11711
0
      Value |= op;
11712
      // op: Vyyyy32
11713
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11714
0
      op &= UINT64_C(31);
11715
0
      Value |= op;
11716
0
      break;
11717
0
    }
11718
0
    case Hexagon::V6_vmpahhsat:
11719
0
    case Hexagon::V6_vmpauhuhsat:
11720
0
    case Hexagon::V6_vmpsuhuhsat: {
11721
      // op: Vu32
11722
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11723
0
      op &= UINT64_C(31);
11724
0
      op <<= 8;
11725
0
      Value |= op;
11726
      // op: Rtt32
11727
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11728
0
      op &= UINT64_C(31);
11729
0
      op <<= 16;
11730
0
      Value |= op;
11731
      // op: Vx32
11732
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11733
0
      op &= UINT64_C(31);
11734
0
      Value |= op;
11735
0
      break;
11736
0
    }
11737
0
    case Hexagon::V6_vrmpybub_rtt_acc:
11738
0
    case Hexagon::V6_vrmpyub_rtt_acc: {
11739
      // op: Vu32
11740
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11741
0
      op &= UINT64_C(31);
11742
0
      op <<= 8;
11743
0
      Value |= op;
11744
      // op: Rtt32
11745
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11746
0
      op &= UINT64_C(31);
11747
0
      op <<= 16;
11748
0
      Value |= op;
11749
      // op: Vxx32
11750
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11751
0
      op &= UINT64_C(31);
11752
0
      Value |= op;
11753
0
      break;
11754
0
    }
11755
0
    case Hexagon::V6_vrmpyzbb_rx:
11756
0
    case Hexagon::V6_vrmpyzbub_rx:
11757
0
    case Hexagon::V6_vrmpyzcb_rx:
11758
0
    case Hexagon::V6_vrmpyzcbs_rx:
11759
0
    case Hexagon::V6_vrmpyznb_rx: {
11760
      // op: Vu32
11761
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11762
0
      op &= UINT64_C(31);
11763
0
      op <<= 8;
11764
0
      Value |= op;
11765
      // op: Vdddd32
11766
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11767
0
      op &= UINT64_C(31);
11768
0
      Value |= op;
11769
      // op: Rx8
11770
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11771
0
      op &= UINT64_C(7);
11772
0
      op <<= 16;
11773
0
      Value |= op;
11774
0
      break;
11775
0
    }
11776
0
    case Hexagon::V6_veqb_and:
11777
0
    case Hexagon::V6_veqb_or:
11778
0
    case Hexagon::V6_veqb_xor:
11779
0
    case Hexagon::V6_veqh_and:
11780
0
    case Hexagon::V6_veqh_or:
11781
0
    case Hexagon::V6_veqh_xor:
11782
0
    case Hexagon::V6_veqw_and:
11783
0
    case Hexagon::V6_veqw_or:
11784
0
    case Hexagon::V6_veqw_xor:
11785
0
    case Hexagon::V6_vgtb_and:
11786
0
    case Hexagon::V6_vgtb_or:
11787
0
    case Hexagon::V6_vgtb_xor:
11788
0
    case Hexagon::V6_vgtbf_and:
11789
0
    case Hexagon::V6_vgtbf_or:
11790
0
    case Hexagon::V6_vgtbf_xor:
11791
0
    case Hexagon::V6_vgth_and:
11792
0
    case Hexagon::V6_vgth_or:
11793
0
    case Hexagon::V6_vgth_xor:
11794
0
    case Hexagon::V6_vgthf_and:
11795
0
    case Hexagon::V6_vgthf_or:
11796
0
    case Hexagon::V6_vgthf_xor:
11797
0
    case Hexagon::V6_vgtsf_and:
11798
0
    case Hexagon::V6_vgtsf_or:
11799
0
    case Hexagon::V6_vgtsf_xor:
11800
0
    case Hexagon::V6_vgtub_and:
11801
0
    case Hexagon::V6_vgtub_or:
11802
0
    case Hexagon::V6_vgtub_xor:
11803
0
    case Hexagon::V6_vgtuh_and:
11804
0
    case Hexagon::V6_vgtuh_or:
11805
0
    case Hexagon::V6_vgtuh_xor:
11806
0
    case Hexagon::V6_vgtuw_and:
11807
0
    case Hexagon::V6_vgtuw_or:
11808
0
    case Hexagon::V6_vgtuw_xor:
11809
0
    case Hexagon::V6_vgtw_and:
11810
0
    case Hexagon::V6_vgtw_or:
11811
0
    case Hexagon::V6_vgtw_xor: {
11812
      // op: Vu32
11813
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11814
0
      op &= UINT64_C(31);
11815
0
      op <<= 8;
11816
0
      Value |= op;
11817
      // op: Vv32
11818
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11819
0
      op &= UINT64_C(31);
11820
0
      op <<= 16;
11821
0
      Value |= op;
11822
      // op: Qx4
11823
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11824
0
      op &= UINT64_C(3);
11825
0
      Value |= op;
11826
0
      break;
11827
0
    }
11828
0
    case Hexagon::V6_vaddcarryo:
11829
0
    case Hexagon::V6_vsubcarryo: {
11830
      // op: Vu32
11831
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11832
0
      op &= UINT64_C(31);
11833
0
      op <<= 8;
11834
0
      Value |= op;
11835
      // op: Vv32
11836
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11837
0
      op &= UINT64_C(31);
11838
0
      op <<= 16;
11839
0
      Value |= op;
11840
      // op: Vd32
11841
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11842
0
      op &= UINT64_C(31);
11843
0
      Value |= op;
11844
      // op: Qe4
11845
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11846
0
      op &= UINT64_C(3);
11847
0
      op <<= 5;
11848
0
      Value |= op;
11849
0
      break;
11850
0
    }
11851
0
    case Hexagon::V6_vaddcarry:
11852
0
    case Hexagon::V6_vsubcarry: {
11853
      // op: Vu32
11854
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11855
0
      op &= UINT64_C(31);
11856
0
      op <<= 8;
11857
0
      Value |= op;
11858
      // op: Vv32
11859
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11860
0
      op &= UINT64_C(31);
11861
0
      op <<= 16;
11862
0
      Value |= op;
11863
      // op: Vd32
11864
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11865
0
      op &= UINT64_C(31);
11866
0
      Value |= op;
11867
      // op: Qx4
11868
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
11869
0
      op &= UINT64_C(3);
11870
0
      op <<= 5;
11871
0
      Value |= op;
11872
0
      break;
11873
0
    }
11874
0
    case Hexagon::V6_vdmpy_sf_hf_acc:
11875
0
    case Hexagon::V6_vdmpyhvsat_acc:
11876
0
    case Hexagon::V6_vmpy_hf_hf_acc:
11877
0
    case Hexagon::V6_vmpyiewh_acc:
11878
0
    case Hexagon::V6_vmpyiewuh_acc:
11879
0
    case Hexagon::V6_vmpyih_acc:
11880
0
    case Hexagon::V6_vmpyowh_rnd_sacc:
11881
0
    case Hexagon::V6_vmpyowh_sacc:
11882
0
    case Hexagon::V6_vrmpybusv_acc:
11883
0
    case Hexagon::V6_vrmpybv_acc:
11884
0
    case Hexagon::V6_vrmpyubv_acc: {
11885
      // op: Vu32
11886
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11887
0
      op &= UINT64_C(31);
11888
0
      op <<= 8;
11889
0
      Value |= op;
11890
      // op: Vv32
11891
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11892
0
      op &= UINT64_C(31);
11893
0
      op <<= 16;
11894
0
      Value |= op;
11895
      // op: Vx32
11896
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11897
0
      op &= UINT64_C(31);
11898
0
      Value |= op;
11899
0
      break;
11900
0
    }
11901
0
    case Hexagon::V6_vaddhw_acc:
11902
0
    case Hexagon::V6_vaddubh_acc:
11903
0
    case Hexagon::V6_vadduhw_acc:
11904
0
    case Hexagon::V6_vasr_into:
11905
0
    case Hexagon::V6_vmpy_sf_bf_acc:
11906
0
    case Hexagon::V6_vmpy_sf_hf_acc:
11907
0
    case Hexagon::V6_vmpybusv_acc:
11908
0
    case Hexagon::V6_vmpybv_acc:
11909
0
    case Hexagon::V6_vmpyhus_acc:
11910
0
    case Hexagon::V6_vmpyhv_acc:
11911
0
    case Hexagon::V6_vmpyowh_64_acc:
11912
0
    case Hexagon::V6_vmpyubv_acc:
11913
0
    case Hexagon::V6_vmpyuhv_acc: {
11914
      // op: Vu32
11915
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11916
0
      op &= UINT64_C(31);
11917
0
      op <<= 8;
11918
0
      Value |= op;
11919
      // op: Vv32
11920
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11921
0
      op &= UINT64_C(31);
11922
0
      op <<= 16;
11923
0
      Value |= op;
11924
      // op: Vxx32
11925
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11926
0
      op &= UINT64_C(31);
11927
0
      Value |= op;
11928
0
      break;
11929
0
    }
11930
0
    case Hexagon::V6_vlutvvb_oracc: {
11931
      // op: Vu32
11932
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11933
0
      op &= UINT64_C(31);
11934
0
      op <<= 8;
11935
0
      Value |= op;
11936
      // op: Vv32
11937
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11938
0
      op &= UINT64_C(31);
11939
0
      op <<= 19;
11940
0
      Value |= op;
11941
      // op: Rt8
11942
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
11943
0
      op &= UINT64_C(7);
11944
0
      op <<= 16;
11945
0
      Value |= op;
11946
      // op: Vx32
11947
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11948
0
      op &= UINT64_C(31);
11949
0
      Value |= op;
11950
0
      break;
11951
0
    }
11952
0
    case Hexagon::V6_vlutvwh_oracc: {
11953
      // op: Vu32
11954
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11955
0
      op &= UINT64_C(31);
11956
0
      op <<= 8;
11957
0
      Value |= op;
11958
      // op: Vv32
11959
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11960
0
      op &= UINT64_C(31);
11961
0
      op <<= 19;
11962
0
      Value |= op;
11963
      // op: Rt8
11964
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
11965
0
      op &= UINT64_C(7);
11966
0
      op <<= 16;
11967
0
      Value |= op;
11968
      // op: Vxx32
11969
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11970
0
      op &= UINT64_C(31);
11971
0
      Value |= op;
11972
0
      break;
11973
0
    }
11974
0
    case Hexagon::V6_vunpackob:
11975
0
    case Hexagon::V6_vunpackoh: {
11976
      // op: Vu32
11977
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
11978
0
      op &= UINT64_C(31);
11979
0
      op <<= 8;
11980
0
      Value |= op;
11981
      // op: Vxx32
11982
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11983
0
      op &= UINT64_C(31);
11984
0
      Value |= op;
11985
0
      break;
11986
0
    }
11987
0
    case Hexagon::V6_vrmpyzbb_rx_acc:
11988
0
    case Hexagon::V6_vrmpyzbub_rx_acc:
11989
0
    case Hexagon::V6_vrmpyzcb_rx_acc:
11990
0
    case Hexagon::V6_vrmpyzcbs_rx_acc:
11991
0
    case Hexagon::V6_vrmpyznb_rx_acc: {
11992
      // op: Vu32
11993
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
11994
0
      op &= UINT64_C(31);
11995
0
      op <<= 8;
11996
0
      Value |= op;
11997
      // op: Vyyyy32
11998
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
11999
0
      op &= UINT64_C(31);
12000
0
      Value |= op;
12001
      // op: Rx8
12002
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12003
0
      op &= UINT64_C(7);
12004
0
      op <<= 16;
12005
0
      Value |= op;
12006
0
      break;
12007
0
    }
12008
0
    case Hexagon::V6_vdmpyhisat:
12009
0
    case Hexagon::V6_vdmpyhsuisat: {
12010
      // op: Vuu32
12011
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12012
0
      op &= UINT64_C(31);
12013
0
      op <<= 8;
12014
0
      Value |= op;
12015
      // op: Rt32
12016
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12017
0
      op &= UINT64_C(31);
12018
0
      op <<= 16;
12019
0
      Value |= op;
12020
      // op: Vd32
12021
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12022
0
      op &= UINT64_C(31);
12023
0
      Value |= op;
12024
0
      break;
12025
0
    }
12026
0
    case Hexagon::V6_vdmpybus_dv:
12027
0
    case Hexagon::V6_vdmpyhb_dv:
12028
0
    case Hexagon::V6_vdsaduh:
12029
0
    case Hexagon::V6_vmpabus:
12030
0
    case Hexagon::V6_vmpabuu:
12031
0
    case Hexagon::V6_vmpahb:
12032
0
    case Hexagon::V6_vmpauhb:
12033
0
    case Hexagon::V6_vtmpyb:
12034
0
    case Hexagon::V6_vtmpybus:
12035
0
    case Hexagon::V6_vtmpyhb: {
12036
      // op: Vuu32
12037
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12038
0
      op &= UINT64_C(31);
12039
0
      op <<= 8;
12040
0
      Value |= op;
12041
      // op: Rt32
12042
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12043
0
      op &= UINT64_C(31);
12044
0
      op <<= 16;
12045
0
      Value |= op;
12046
      // op: Vdd32
12047
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12048
0
      op &= UINT64_C(31);
12049
0
      Value |= op;
12050
0
      break;
12051
0
    }
12052
0
    case Hexagon::V6_vconv_hf_qf32: {
12053
      // op: Vuu32
12054
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12055
0
      op &= UINT64_C(31);
12056
0
      op <<= 8;
12057
0
      Value |= op;
12058
      // op: Vd32
12059
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12060
0
      op &= UINT64_C(31);
12061
0
      Value |= op;
12062
0
      break;
12063
0
    }
12064
0
    case Hexagon::V6_vasrvuhubrndsat:
12065
0
    case Hexagon::V6_vasrvuhubsat:
12066
0
    case Hexagon::V6_vasrvwuhrndsat:
12067
0
    case Hexagon::V6_vasrvwuhsat: {
12068
      // op: Vuu32
12069
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12070
0
      op &= UINT64_C(31);
12071
0
      op <<= 8;
12072
0
      Value |= op;
12073
      // op: Vv32
12074
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12075
0
      op &= UINT64_C(31);
12076
0
      op <<= 16;
12077
0
      Value |= op;
12078
      // op: Vd32
12079
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12080
0
      op &= UINT64_C(31);
12081
0
      Value |= op;
12082
0
      break;
12083
0
    }
12084
0
    case Hexagon::V6_vaddb_dv:
12085
0
    case Hexagon::V6_vaddbsat_dv:
12086
0
    case Hexagon::V6_vaddh_dv:
12087
0
    case Hexagon::V6_vaddhsat_dv:
12088
0
    case Hexagon::V6_vaddubsat_dv:
12089
0
    case Hexagon::V6_vadduhsat_dv:
12090
0
    case Hexagon::V6_vadduwsat_dv:
12091
0
    case Hexagon::V6_vaddw_dv:
12092
0
    case Hexagon::V6_vaddwsat_dv:
12093
0
    case Hexagon::V6_vmpabusv:
12094
0
    case Hexagon::V6_vmpabuuv:
12095
0
    case Hexagon::V6_vsubb_dv:
12096
0
    case Hexagon::V6_vsubbsat_dv:
12097
0
    case Hexagon::V6_vsubh_dv:
12098
0
    case Hexagon::V6_vsubhsat_dv:
12099
0
    case Hexagon::V6_vsububsat_dv:
12100
0
    case Hexagon::V6_vsubuhsat_dv:
12101
0
    case Hexagon::V6_vsubuwsat_dv:
12102
0
    case Hexagon::V6_vsubw_dv:
12103
0
    case Hexagon::V6_vsubwsat_dv: {
12104
      // op: Vuu32
12105
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12106
0
      op &= UINT64_C(31);
12107
0
      op <<= 8;
12108
0
      Value |= op;
12109
      // op: Vvv32
12110
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12111
0
      op &= UINT64_C(31);
12112
0
      op <<= 16;
12113
0
      Value |= op;
12114
      // op: Vdd32
12115
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12116
0
      op &= UINT64_C(31);
12117
0
      Value |= op;
12118
0
      break;
12119
0
    }
12120
0
    case Hexagon::V6_vdmpyhisat_acc:
12121
0
    case Hexagon::V6_vdmpyhsuisat_acc: {
12122
      // op: Vuu32
12123
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12124
0
      op &= UINT64_C(31);
12125
0
      op <<= 8;
12126
0
      Value |= op;
12127
      // op: Rt32
12128
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12129
0
      op &= UINT64_C(31);
12130
0
      op <<= 16;
12131
0
      Value |= op;
12132
      // op: Vx32
12133
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12134
0
      op &= UINT64_C(31);
12135
0
      Value |= op;
12136
0
      break;
12137
0
    }
12138
0
    case Hexagon::V6_vdmpybus_dv_acc:
12139
0
    case Hexagon::V6_vdmpyhb_dv_acc:
12140
0
    case Hexagon::V6_vdsaduh_acc:
12141
0
    case Hexagon::V6_vmpabus_acc:
12142
0
    case Hexagon::V6_vmpabuu_acc:
12143
0
    case Hexagon::V6_vmpahb_acc:
12144
0
    case Hexagon::V6_vmpauhb_acc:
12145
0
    case Hexagon::V6_vtmpyb_acc:
12146
0
    case Hexagon::V6_vtmpybus_acc:
12147
0
    case Hexagon::V6_vtmpyhb_acc: {
12148
      // op: Vuu32
12149
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
12150
0
      op &= UINT64_C(31);
12151
0
      op <<= 8;
12152
0
      Value |= op;
12153
      // op: Rt32
12154
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
12155
0
      op &= UINT64_C(31);
12156
0
      op <<= 16;
12157
0
      Value |= op;
12158
      // op: Vxx32
12159
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12160
0
      op &= UINT64_C(31);
12161
0
      Value |= op;
12162
0
      break;
12163
0
    }
12164
0
    case Hexagon::CALLProfile:
12165
0
    case Hexagon::PS_call_stk:
12166
0
    case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4:
12167
0
    case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT:
12168
0
    case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC:
12169
0
    case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC:
12170
0
    case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
12171
0
    case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT:
12172
0
    case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC:
12173
0
    case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
12174
0
    case Hexagon::SAVE_REGISTERS_CALL_V4:
12175
0
    case Hexagon::SAVE_REGISTERS_CALL_V4STK:
12176
0
    case Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT:
12177
0
    case Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT_PIC:
12178
0
    case Hexagon::SAVE_REGISTERS_CALL_V4STK_PIC:
12179
0
    case Hexagon::SAVE_REGISTERS_CALL_V4_EXT:
12180
0
    case Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC:
12181
0
    case Hexagon::SAVE_REGISTERS_CALL_V4_PIC: {
12182
      // op: dst
12183
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12184
0
      Value |= (op & UINT64_C(16744448)) << 1;
12185
0
      Value |= (op & UINT64_C(32764)) >> 1;
12186
0
      break;
12187
0
    }
12188
0
    case Hexagon::EH_RETURN_JMPR:
12189
0
    case Hexagon::PS_jmpret: {
12190
      // op: dst
12191
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12192
0
      op &= UINT64_C(31);
12193
0
      op <<= 16;
12194
0
      Value |= op;
12195
0
      break;
12196
0
    }
12197
0
    case Hexagon::HI:
12198
0
    case Hexagon::LO: {
12199
      // op: dst
12200
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12201
0
      op &= UINT64_C(31);
12202
0
      op <<= 16;
12203
0
      Value |= op;
12204
      // op: imm_value
12205
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12206
0
      Value |= (op & UINT64_C(49152)) << 8;
12207
0
      Value |= (op & UINT64_C(16383));
12208
0
      break;
12209
0
    }
12210
0
    case Hexagon::J2_loop0iext:
12211
0
    case Hexagon::J2_loop1iext: {
12212
      // op: offset
12213
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12214
0
      Value |= (op & UINT64_C(496)) << 4;
12215
0
      Value |= (op & UINT64_C(12)) << 1;
12216
      // op: src2
12217
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12218
0
      Value |= (op & UINT64_C(992)) << 11;
12219
0
      Value |= (op & UINT64_C(28)) << 3;
12220
0
      Value |= (op & UINT64_C(3));
12221
0
      break;
12222
0
    }
12223
0
    case Hexagon::J2_loop0rext:
12224
0
    case Hexagon::J2_loop1rext: {
12225
      // op: offset
12226
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12227
0
      Value |= (op & UINT64_C(496)) << 4;
12228
0
      Value |= (op & UINT64_C(12)) << 1;
12229
      // op: src2
12230
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12231
0
      op &= UINT64_C(31);
12232
0
      op <<= 16;
12233
0
      Value |= op;
12234
0
      break;
12235
0
    }
12236
0
    case Hexagon::PS_jmpretf:
12237
0
    case Hexagon::PS_jmpretfnew:
12238
0
    case Hexagon::PS_jmpretfnewpt:
12239
0
    case Hexagon::PS_jmprett:
12240
0
    case Hexagon::PS_jmprettnew:
12241
0
    case Hexagon::PS_jmprettnewpt: {
12242
      // op: src
12243
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
12244
0
      op &= UINT64_C(3);
12245
0
      op <<= 8;
12246
0
      Value |= op;
12247
      // op: dst
12248
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
12249
0
      op &= UINT64_C(31);
12250
0
      op <<= 16;
12251
0
      Value |= op;
12252
0
      break;
12253
0
    }
12254
0
  default:
12255
0
    std::string msg;
12256
0
    raw_string_ostream Msg(msg);
12257
0
    Msg << "Not supported instr: " << MI;
12258
0
    report_fatal_error(Msg.str().c_str());
12259
0
  }
12260
0
  return Value;
12261
0
}
12262
12263
#ifdef GET_OPERAND_BIT_OFFSET
12264
#undef GET_OPERAND_BIT_OFFSET
12265
12266
uint32_t HexagonMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
12267
    unsigned OpNum,
12268
    const MCSubtargetInfo &STI) const {
12269
  switch (MI.getOpcode()) {
12270
    case Hexagon::A2_nop:
12271
    case Hexagon::CONST32:
12272
    case Hexagon::CONST64:
12273
    case Hexagon::DuplexIClass0:
12274
    case Hexagon::DuplexIClass1:
12275
    case Hexagon::DuplexIClass2:
12276
    case Hexagon::DuplexIClass3:
12277
    case Hexagon::DuplexIClass4:
12278
    case Hexagon::DuplexIClass5:
12279
    case Hexagon::DuplexIClass6:
12280
    case Hexagon::DuplexIClass7:
12281
    case Hexagon::DuplexIClass8:
12282
    case Hexagon::DuplexIClass9:
12283
    case Hexagon::DuplexIClassA:
12284
    case Hexagon::DuplexIClassB:
12285
    case Hexagon::DuplexIClassC:
12286
    case Hexagon::DuplexIClassD:
12287
    case Hexagon::DuplexIClassE:
12288
    case Hexagon::DuplexIClassF:
12289
    case Hexagon::J2_rte:
12290
    case Hexagon::J2_unpause:
12291
    case Hexagon::SL2_deallocframe:
12292
    case Hexagon::SL2_jumpr31:
12293
    case Hexagon::SL2_jumpr31_f:
12294
    case Hexagon::SL2_jumpr31_fnew:
12295
    case Hexagon::SL2_jumpr31_t:
12296
    case Hexagon::SL2_jumpr31_tnew:
12297
    case Hexagon::SL2_return:
12298
    case Hexagon::SL2_return_f:
12299
    case Hexagon::SL2_return_fnew:
12300
    case Hexagon::SL2_return_t:
12301
    case Hexagon::SL2_return_tnew:
12302
    case Hexagon::TFRI64_V2_ext:
12303
    case Hexagon::TFRI64_V4:
12304
    case Hexagon::V6_vhist:
12305
    case Hexagon::V6_vwhist128:
12306
    case Hexagon::V6_vwhist256:
12307
    case Hexagon::V6_vwhist256_sat:
12308
    case Hexagon::Y2_barrier:
12309
    case Hexagon::Y2_break:
12310
    case Hexagon::Y2_dckill:
12311
    case Hexagon::Y2_ickill:
12312
    case Hexagon::Y2_isync:
12313
    case Hexagon::Y2_k0lock:
12314
    case Hexagon::Y2_k0unlock:
12315
    case Hexagon::Y2_l2kill:
12316
    case Hexagon::Y2_syncht:
12317
    case Hexagon::Y2_tlblock:
12318
    case Hexagon::Y2_tlbunlock:
12319
    case Hexagon::Y5_l2gclean:
12320
    case Hexagon::Y5_l2gcleaninv:
12321
    case Hexagon::Y5_l2gunlock:
12322
    case Hexagon::invalid_decode: {
12323
      break;
12324
    }
12325
    case Hexagon::PS_storerbnewabs:
12326
    case Hexagon::PS_storerhnewabs:
12327
    case Hexagon::PS_storerinewabs:
12328
    case Hexagon::S2_storerbnewgp:
12329
    case Hexagon::S2_storerhnewgp:
12330
    case Hexagon::S2_storerinewgp: {
12331
      switch (OpNum) {
12332
      case 0:
12333
        // op: Ii
12334
        return 0;
12335
      case 1:
12336
        // op: Nt8
12337
        return 8;
12338
      }
12339
      break;
12340
    }
12341
    case Hexagon::PS_storerbabs:
12342
    case Hexagon::PS_storerfabs:
12343
    case Hexagon::PS_storerhabs:
12344
    case Hexagon::PS_storeriabs:
12345
    case Hexagon::S2_storerbgp:
12346
    case Hexagon::S2_storerfgp:
12347
    case Hexagon::S2_storerhgp:
12348
    case Hexagon::S2_storerigp: {
12349
      switch (OpNum) {
12350
      case 0:
12351
        // op: Ii
12352
        return 0;
12353
      case 1:
12354
        // op: Rt32
12355
        return 8;
12356
      }
12357
      break;
12358
    }
12359
    case Hexagon::PS_storerdabs:
12360
    case Hexagon::S2_storerdgp: {
12361
      switch (OpNum) {
12362
      case 0:
12363
        // op: Ii
12364
        return 0;
12365
      case 1:
12366
        // op: Rtt32
12367
        return 8;
12368
      }
12369
      break;
12370
    }
12371
    case Hexagon::A4_ext: {
12372
      switch (OpNum) {
12373
      case 0:
12374
        // op: Ii
12375
        return 0;
12376
      }
12377
      break;
12378
    }
12379
    case Hexagon::J2_call:
12380
    case Hexagon::J2_jump: {
12381
      switch (OpNum) {
12382
      case 0:
12383
        // op: Ii
12384
        return 1;
12385
      }
12386
      break;
12387
    }
12388
    case Hexagon::J2_pause:
12389
    case Hexagon::J2_trap0:
12390
    case Hexagon::PS_trap1: {
12391
      switch (OpNum) {
12392
      case 0:
12393
        // op: Ii
12394
        return 2;
12395
      }
12396
      break;
12397
    }
12398
    case Hexagon::J2_loop0i:
12399
    case Hexagon::J2_loop1i:
12400
    case Hexagon::J2_ploop1si:
12401
    case Hexagon::J2_ploop2si:
12402
    case Hexagon::J2_ploop3si: {
12403
      switch (OpNum) {
12404
      case 0:
12405
        // op: Ii
12406
        return 3;
12407
      case 1:
12408
        // op: II
12409
        return 0;
12410
      }
12411
      break;
12412
    }
12413
    case Hexagon::J2_loop0r:
12414
    case Hexagon::J2_loop1r:
12415
    case Hexagon::J2_ploop1sr:
12416
    case Hexagon::J2_ploop2sr:
12417
    case Hexagon::J2_ploop3sr: {
12418
      switch (OpNum) {
12419
      case 0:
12420
        // op: Ii
12421
        return 3;
12422
      case 1:
12423
        // op: Rs32
12424
        return 16;
12425
      }
12426
      break;
12427
    }
12428
    case Hexagon::SS2_stored_sp: {
12429
      switch (OpNum) {
12430
      case 0:
12431
        // op: Ii
12432
        return 3;
12433
      case 1:
12434
        // op: Rtt8
12435
        return 0;
12436
      }
12437
      break;
12438
    }
12439
    case Hexagon::SS2_storew_sp: {
12440
      switch (OpNum) {
12441
      case 0:
12442
        // op: Ii
12443
        return 4;
12444
      case 1:
12445
        // op: Rt16
12446
        return 0;
12447
      }
12448
      break;
12449
    }
12450
    case Hexagon::SS2_allocframe: {
12451
      switch (OpNum) {
12452
      case 0:
12453
        // op: Ii
12454
        return 4;
12455
      }
12456
      break;
12457
    }
12458
    case Hexagon::V6_vwhist128m: {
12459
      switch (OpNum) {
12460
      case 0:
12461
        // op: Ii
12462
        return 8;
12463
      }
12464
      break;
12465
    }
12466
    case Hexagon::Y2_setimask:
12467
    case Hexagon::Y2_setprio: {
12468
      switch (OpNum) {
12469
      case 0:
12470
        // op: Pt4
12471
        return 8;
12472
      case 1:
12473
        // op: Rs32
12474
        return 16;
12475
      }
12476
      break;
12477
    }
12478
    case Hexagon::J2_callrf:
12479
    case Hexagon::J2_callrt:
12480
    case Hexagon::J2_jumprf:
12481
    case Hexagon::J2_jumprfnew:
12482
    case Hexagon::J2_jumprfnewpt:
12483
    case Hexagon::J2_jumprfpt:
12484
    case Hexagon::J2_jumprt:
12485
    case Hexagon::J2_jumprtnew:
12486
    case Hexagon::J2_jumprtnewpt:
12487
    case Hexagon::J2_jumprtpt: {
12488
      switch (OpNum) {
12489
      case 0:
12490
        // op: Pu4
12491
        return 8;
12492
      case 1:
12493
        // op: Rs32
12494
        return 16;
12495
      }
12496
      break;
12497
    }
12498
    case Hexagon::V6_vgathermhq:
12499
    case Hexagon::V6_vgathermwq: {
12500
      switch (OpNum) {
12501
      case 0:
12502
        // op: Qs4
12503
        return 5;
12504
      case 1:
12505
        // op: Rt32
12506
        return 16;
12507
      case 2:
12508
        // op: Mu2
12509
        return 13;
12510
      case 3:
12511
        // op: Vv32
12512
        return 0;
12513
      }
12514
      break;
12515
    }
12516
    case Hexagon::V6_vscattermhq:
12517
    case Hexagon::V6_vscattermwq: {
12518
      switch (OpNum) {
12519
      case 0:
12520
        // op: Qs4
12521
        return 5;
12522
      case 1:
12523
        // op: Rt32
12524
        return 16;
12525
      case 2:
12526
        // op: Mu2
12527
        return 13;
12528
      case 3:
12529
        // op: Vv32
12530
        return 8;
12531
      case 4:
12532
        // op: Vw32
12533
        return 0;
12534
      }
12535
      break;
12536
    }
12537
    case Hexagon::V6_vgathermhwq: {
12538
      switch (OpNum) {
12539
      case 0:
12540
        // op: Qs4
12541
        return 5;
12542
      case 1:
12543
        // op: Rt32
12544
        return 16;
12545
      case 2:
12546
        // op: Mu2
12547
        return 13;
12548
      case 3:
12549
        // op: Vvv32
12550
        return 0;
12551
      }
12552
      break;
12553
    }
12554
    case Hexagon::V6_vscattermhwq: {
12555
      switch (OpNum) {
12556
      case 0:
12557
        // op: Qs4
12558
        return 5;
12559
      case 1:
12560
        // op: Rt32
12561
        return 16;
12562
      case 2:
12563
        // op: Mu2
12564
        return 13;
12565
      case 3:
12566
        // op: Vvv32
12567
        return 8;
12568
      case 4:
12569
        // op: Vw32
12570
        return 0;
12571
      }
12572
      break;
12573
    }
12574
    case Hexagon::V6_vhistq:
12575
    case Hexagon::V6_vwhist128q:
12576
    case Hexagon::V6_vwhist256q:
12577
    case Hexagon::V6_vwhist256q_sat: {
12578
      switch (OpNum) {
12579
      case 0:
12580
        // op: Qv4
12581
        return 22;
12582
      }
12583
      break;
12584
    }
12585
    case Hexagon::SA1_clrf:
12586
    case Hexagon::SA1_clrfnew:
12587
    case Hexagon::SA1_clrt:
12588
    case Hexagon::SA1_clrtnew:
12589
    case Hexagon::SA1_setin1: {
12590
      switch (OpNum) {
12591
      case 0:
12592
        // op: Rd16
12593
        return 0;
12594
      }
12595
      break;
12596
    }
12597
    case Hexagon::Y6_dmpause:
12598
    case Hexagon::Y6_dmpoll:
12599
    case Hexagon::Y6_dmwait: {
12600
      switch (OpNum) {
12601
      case 0:
12602
        // op: Rd32
12603
        return 0;
12604
      }
12605
      break;
12606
    }
12607
    case Hexagon::PS_callr_nr: {
12608
      switch (OpNum) {
12609
      case 0:
12610
        // op: Rs
12611
        return 16;
12612
      }
12613
      break;
12614
    }
12615
    case Hexagon::L6_memcpy: {
12616
      switch (OpNum) {
12617
      case 0:
12618
        // op: Rs32
12619
        return 16;
12620
      case 1:
12621
        // op: Rt32
12622
        return 8;
12623
      case 2:
12624
        // op: Mu2
12625
        return 13;
12626
      }
12627
      break;
12628
    }
12629
    case Hexagon::S2_storew_rl_at_vi:
12630
    case Hexagon::S2_storew_rl_st_vi:
12631
    case Hexagon::Y2_dctagw:
12632
    case Hexagon::Y2_icdataw:
12633
    case Hexagon::Y2_ictagw:
12634
    case Hexagon::Y4_l2fetch:
12635
    case Hexagon::Y4_l2tagw:
12636
    case Hexagon::Y6_dmlink: {
12637
      switch (OpNum) {
12638
      case 0:
12639
        // op: Rs32
12640
        return 16;
12641
      case 1:
12642
        // op: Rt32
12643
        return 8;
12644
      }
12645
      break;
12646
    }
12647
    case Hexagon::S4_stored_rl_at_vi:
12648
    case Hexagon::S4_stored_rl_st_vi:
12649
    case Hexagon::Y5_l2fetch: {
12650
      switch (OpNum) {
12651
      case 0:
12652
        // op: Rs32
12653
        return 16;
12654
      case 1:
12655
        // op: Rtt32
12656
        return 8;
12657
      }
12658
      break;
12659
    }
12660
    case Hexagon::J2_callr:
12661
    case Hexagon::J2_callrh:
12662
    case Hexagon::J2_jumpr:
12663
    case Hexagon::J2_jumprh:
12664
    case Hexagon::J4_hintjumpr:
12665
    case Hexagon::R6_release_at_vi:
12666
    case Hexagon::R6_release_st_vi:
12667
    case Hexagon::Y2_ciad:
12668
    case Hexagon::Y2_cswi:
12669
    case Hexagon::Y2_dccleana:
12670
    case Hexagon::Y2_dccleanidx:
12671
    case Hexagon::Y2_dccleaninva:
12672
    case Hexagon::Y2_dccleaninvidx:
12673
    case Hexagon::Y2_dcinva:
12674
    case Hexagon::Y2_dcinvidx:
12675
    case Hexagon::Y2_dczeroa:
12676
    case Hexagon::Y2_iassignw:
12677
    case Hexagon::Y2_icinva:
12678
    case Hexagon::Y2_icinvidx:
12679
    case Hexagon::Y2_l2cleaninvidx:
12680
    case Hexagon::Y2_resume:
12681
    case Hexagon::Y2_start:
12682
    case Hexagon::Y2_stop:
12683
    case Hexagon::Y2_swi:
12684
    case Hexagon::Y2_wait:
12685
    case Hexagon::Y4_nmi:
12686
    case Hexagon::Y4_siad:
12687
    case Hexagon::Y4_trace:
12688
    case Hexagon::Y5_l2cleanidx:
12689
    case Hexagon::Y5_l2invidx:
12690
    case Hexagon::Y5_l2unlocka:
12691
    case Hexagon::Y5_tlbasidi:
12692
    case Hexagon::Y6_diag:
12693
    case Hexagon::Y6_dmresume:
12694
    case Hexagon::Y6_dmstart: {
12695
      switch (OpNum) {
12696
      case 0:
12697
        // op: Rs32
12698
        return 16;
12699
      }
12700
      break;
12701
    }
12702
    case Hexagon::Y2_tlbw: {
12703
      switch (OpNum) {
12704
      case 0:
12705
        // op: Rss32
12706
        return 16;
12707
      case 1:
12708
        // op: Rt32
12709
        return 8;
12710
      }
12711
      break;
12712
    }
12713
    case Hexagon::Y6_diag0:
12714
    case Hexagon::Y6_diag1: {
12715
      switch (OpNum) {
12716
      case 0:
12717
        // op: Rss32
12718
        return 16;
12719
      case 1:
12720
        // op: Rtt32
12721
        return 8;
12722
      }
12723
      break;
12724
    }
12725
    case Hexagon::V6_vgathermh:
12726
    case Hexagon::V6_vgathermw: {
12727
      switch (OpNum) {
12728
      case 0:
12729
        // op: Rt32
12730
        return 16;
12731
      case 1:
12732
        // op: Mu2
12733
        return 13;
12734
      case 2:
12735
        // op: Vv32
12736
        return 0;
12737
      }
12738
      break;
12739
    }
12740
    case Hexagon::V6_vscattermh:
12741
    case Hexagon::V6_vscattermh_add:
12742
    case Hexagon::V6_vscattermw:
12743
    case Hexagon::V6_vscattermw_add: {
12744
      switch (OpNum) {
12745
      case 0:
12746
        // op: Rt32
12747
        return 16;
12748
      case 1:
12749
        // op: Mu2
12750
        return 13;
12751
      case 2:
12752
        // op: Vv32
12753
        return 8;
12754
      case 3:
12755
        // op: Vw32
12756
        return 0;
12757
      }
12758
      break;
12759
    }
12760
    case Hexagon::V6_vgathermhw: {
12761
      switch (OpNum) {
12762
      case 0:
12763
        // op: Rt32
12764
        return 16;
12765
      case 1:
12766
        // op: Mu2
12767
        return 13;
12768
      case 2:
12769
        // op: Vvv32
12770
        return 0;
12771
      }
12772
      break;
12773
    }
12774
    case Hexagon::V6_vscattermhw:
12775
    case Hexagon::V6_vscattermhw_add: {
12776
      switch (OpNum) {
12777
      case 0:
12778
        // op: Rt32
12779
        return 16;
12780
      case 1:
12781
        // op: Mu2
12782
        return 13;
12783
      case 2:
12784
        // op: Vvv32
12785
        return 8;
12786
      case 3:
12787
        // op: Vw32
12788
        return 0;
12789
      }
12790
      break;
12791
    }
12792
    case Hexagon::Y6_l2gcleaninvpa:
12793
    case Hexagon::Y6_l2gcleanpa: {
12794
      switch (OpNum) {
12795
      case 0:
12796
        // op: Rtt32
12797
        return 8;
12798
      }
12799
      break;
12800
    }
12801
    case Hexagon::Y2_crswap0:
12802
    case Hexagon::Y4_crswap1: {
12803
      switch (OpNum) {
12804
      case 0:
12805
        // op: Rx32
12806
        return 16;
12807
      }
12808
      break;
12809
    }
12810
    case Hexagon::Y4_crswap10: {
12811
      switch (OpNum) {
12812
      case 0:
12813
        // op: Rxx32
12814
        return 16;
12815
      }
12816
      break;
12817
    }
12818
    case Hexagon::HI:
12819
    case Hexagon::LO: {
12820
      switch (OpNum) {
12821
      case 0:
12822
        // op: dst
12823
        return 16;
12824
      case 1:
12825
        // op: imm_value
12826
        return 0;
12827
      }
12828
      break;
12829
    }
12830
    case Hexagon::EH_RETURN_JMPR:
12831
    case Hexagon::PS_jmpret: {
12832
      switch (OpNum) {
12833
      case 0:
12834
        // op: dst
12835
        return 16;
12836
      }
12837
      break;
12838
    }
12839
    case Hexagon::CALLProfile:
12840
    case Hexagon::PS_call_stk:
12841
    case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4:
12842
    case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT:
12843
    case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC:
12844
    case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC:
12845
    case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
12846
    case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT:
12847
    case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC:
12848
    case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
12849
    case Hexagon::SAVE_REGISTERS_CALL_V4:
12850
    case Hexagon::SAVE_REGISTERS_CALL_V4STK:
12851
    case Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT:
12852
    case Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT_PIC:
12853
    case Hexagon::SAVE_REGISTERS_CALL_V4STK_PIC:
12854
    case Hexagon::SAVE_REGISTERS_CALL_V4_EXT:
12855
    case Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC:
12856
    case Hexagon::SAVE_REGISTERS_CALL_V4_PIC: {
12857
      switch (OpNum) {
12858
      case 0:
12859
        // op: dst
12860
        return 1;
12861
      }
12862
      break;
12863
    }
12864
    case Hexagon::J2_loop0iext:
12865
    case Hexagon::J2_loop1iext: {
12866
      switch (OpNum) {
12867
      case 0:
12868
        // op: offset
12869
        return 3;
12870
      case 1:
12871
        // op: src2
12872
        return 0;
12873
      }
12874
      break;
12875
    }
12876
    case Hexagon::J2_loop0rext:
12877
    case Hexagon::J2_loop1rext: {
12878
      switch (OpNum) {
12879
      case 0:
12880
        // op: offset
12881
        return 3;
12882
      case 1:
12883
        // op: src2
12884
        return 16;
12885
      }
12886
      break;
12887
    }
12888
    case Hexagon::PS_jmpretf:
12889
    case Hexagon::PS_jmpretfnew:
12890
    case Hexagon::PS_jmpretfnewpt:
12891
    case Hexagon::PS_jmprett:
12892
    case Hexagon::PS_jmprettnew:
12893
    case Hexagon::PS_jmprettnewpt: {
12894
      switch (OpNum) {
12895
      case 0:
12896
        // op: src
12897
        return 8;
12898
      case 1:
12899
        // op: dst
12900
        return 16;
12901
      }
12902
      break;
12903
    }
12904
    case Hexagon::A2_tfrcrr: {
12905
      switch (OpNum) {
12906
      case 1:
12907
        // op: Cs32
12908
        return 16;
12909
      case 0:
12910
        // op: Rd32
12911
        return 0;
12912
      }
12913
      break;
12914
    }
12915
    case Hexagon::A4_tfrcpp: {
12916
      switch (OpNum) {
12917
      case 1:
12918
        // op: Css32
12919
        return 16;
12920
      case 0:
12921
        // op: Rdd32
12922
        return 0;
12923
      }
12924
      break;
12925
    }
12926
    case Hexagon::G4_tfrgcrr: {
12927
      switch (OpNum) {
12928
      case 1:
12929
        // op: Gs32
12930
        return 16;
12931
      case 0:
12932
        // op: Rd32
12933
        return 0;
12934
      }
12935
      break;
12936
    }
12937
    case Hexagon::G4_tfrgcpp: {
12938
      switch (OpNum) {
12939
      case 1:
12940
        // op: Gss32
12941
        return 16;
12942
      case 0:
12943
        // op: Rdd32
12944
        return 0;
12945
      }
12946
      break;
12947
    }
12948
    case Hexagon::S4_storerbnew_ap:
12949
    case Hexagon::S4_storerhnew_ap:
12950
    case Hexagon::S4_storerinew_ap: {
12951
      switch (OpNum) {
12952
      case 1:
12953
        // op: II
12954
        return 0;
12955
      case 2:
12956
        // op: Nt8
12957
        return 8;
12958
      case 0:
12959
        // op: Re32
12960
        return 16;
12961
      }
12962
      break;
12963
    }
12964
    case Hexagon::S4_storerb_ap:
12965
    case Hexagon::S4_storerf_ap:
12966
    case Hexagon::S4_storerh_ap:
12967
    case Hexagon::S4_storeri_ap: {
12968
      switch (OpNum) {
12969
      case 1:
12970
        // op: II
12971
        return 0;
12972
      case 2:
12973
        // op: Rt32
12974
        return 8;
12975
      case 0:
12976
        // op: Re32
12977
        return 16;
12978
      }
12979
      break;
12980
    }
12981
    case Hexagon::S4_storerd_ap: {
12982
      switch (OpNum) {
12983
      case 1:
12984
        // op: II
12985
        return 0;
12986
      case 2:
12987
        // op: Rtt32
12988
        return 8;
12989
      case 0:
12990
        // op: Re32
12991
        return 16;
12992
      }
12993
      break;
12994
    }
12995
    case Hexagon::J4_cmpeqi_f_jumpnv_nt:
12996
    case Hexagon::J4_cmpeqi_f_jumpnv_t:
12997
    case Hexagon::J4_cmpeqi_t_jumpnv_nt:
12998
    case Hexagon::J4_cmpeqi_t_jumpnv_t:
12999
    case Hexagon::J4_cmpgti_f_jumpnv_nt:
13000
    case Hexagon::J4_cmpgti_f_jumpnv_t:
13001
    case Hexagon::J4_cmpgti_t_jumpnv_nt:
13002
    case Hexagon::J4_cmpgti_t_jumpnv_t:
13003
    case Hexagon::J4_cmpgtui_f_jumpnv_nt:
13004
    case Hexagon::J4_cmpgtui_f_jumpnv_t:
13005
    case Hexagon::J4_cmpgtui_t_jumpnv_nt:
13006
    case Hexagon::J4_cmpgtui_t_jumpnv_t: {
13007
      switch (OpNum) {
13008
      case 1:
13009
        // op: II
13010
        return 8;
13011
      case 2:
13012
        // op: Ii
13013
        return 1;
13014
      case 0:
13015
        // op: Ns8
13016
        return 16;
13017
      }
13018
      break;
13019
    }
13020
    case Hexagon::J4_jumpseti: {
13021
      switch (OpNum) {
13022
      case 1:
13023
        // op: II
13024
        return 8;
13025
      case 2:
13026
        // op: Ii
13027
        return 1;
13028
      case 0:
13029
        // op: Rd16
13030
        return 16;
13031
      }
13032
      break;
13033
    }
13034
    case Hexagon::J4_cmpeqi_fp0_jump_nt:
13035
    case Hexagon::J4_cmpeqi_fp0_jump_t:
13036
    case Hexagon::J4_cmpeqi_fp1_jump_nt:
13037
    case Hexagon::J4_cmpeqi_fp1_jump_t:
13038
    case Hexagon::J4_cmpeqi_tp0_jump_nt:
13039
    case Hexagon::J4_cmpeqi_tp0_jump_t:
13040
    case Hexagon::J4_cmpeqi_tp1_jump_nt:
13041
    case Hexagon::J4_cmpeqi_tp1_jump_t:
13042
    case Hexagon::J4_cmpgti_fp0_jump_nt:
13043
    case Hexagon::J4_cmpgti_fp0_jump_t:
13044
    case Hexagon::J4_cmpgti_fp1_jump_nt:
13045
    case Hexagon::J4_cmpgti_fp1_jump_t:
13046
    case Hexagon::J4_cmpgti_tp0_jump_nt:
13047
    case Hexagon::J4_cmpgti_tp0_jump_t:
13048
    case Hexagon::J4_cmpgti_tp1_jump_nt:
13049
    case Hexagon::J4_cmpgti_tp1_jump_t:
13050
    case Hexagon::J4_cmpgtui_fp0_jump_nt:
13051
    case Hexagon::J4_cmpgtui_fp0_jump_t:
13052
    case Hexagon::J4_cmpgtui_fp1_jump_nt:
13053
    case Hexagon::J4_cmpgtui_fp1_jump_t:
13054
    case Hexagon::J4_cmpgtui_tp0_jump_nt:
13055
    case Hexagon::J4_cmpgtui_tp0_jump_t:
13056
    case Hexagon::J4_cmpgtui_tp1_jump_nt:
13057
    case Hexagon::J4_cmpgtui_tp1_jump_t: {
13058
      switch (OpNum) {
13059
      case 1:
13060
        // op: II
13061
        return 8;
13062
      case 2:
13063
        // op: Ii
13064
        return 1;
13065
      case 0:
13066
        // op: Rs16
13067
        return 16;
13068
      }
13069
      break;
13070
    }
13071
    case Hexagon::SA1_cmpeqi:
13072
    case Hexagon::SS2_storebi0:
13073
    case Hexagon::SS2_storebi1:
13074
    case Hexagon::SS2_storewi0:
13075
    case Hexagon::SS2_storewi1: {
13076
      switch (OpNum) {
13077
      case 1:
13078
        // op: Ii
13079
        return 0;
13080
      case 0:
13081
        // op: Rs16
13082
        return 4;
13083
      }
13084
      break;
13085
    }
13086
    case Hexagon::S2_storerbnew_io:
13087
    case Hexagon::S2_storerhnew_io:
13088
    case Hexagon::S2_storerinew_io: {
13089
      switch (OpNum) {
13090
      case 1:
13091
        // op: Ii
13092
        return 0;
13093
      case 0:
13094
        // op: Rs32
13095
        return 16;
13096
      case 2:
13097
        // op: Nt8
13098
        return 8;
13099
      }
13100
      break;
13101
    }
13102
    case Hexagon::S2_storerb_io:
13103
    case Hexagon::S2_storerf_io:
13104
    case Hexagon::S2_storerh_io:
13105
    case Hexagon::S2_storeri_io: {
13106
      switch (OpNum) {
13107
      case 1:
13108
        // op: Ii
13109
        return 0;
13110
      case 0:
13111
        // op: Rs32
13112
        return 16;
13113
      case 2:
13114
        // op: Rt32
13115
        return 8;
13116
      }
13117
      break;
13118
    }
13119
    case Hexagon::S2_storerd_io: {
13120
      switch (OpNum) {
13121
      case 1:
13122
        // op: Ii
13123
        return 0;
13124
      case 0:
13125
        // op: Rs32
13126
        return 16;
13127
      case 2:
13128
        // op: Rtt32
13129
        return 8;
13130
      }
13131
      break;
13132
    }
13133
    case Hexagon::Y2_dcfetchbo: {
13134
      switch (OpNum) {
13135
      case 1:
13136
        // op: Ii
13137
        return 0;
13138
      case 0:
13139
        // op: Rs32
13140
        return 16;
13141
      }
13142
      break;
13143
    }
13144
    case Hexagon::J4_tstbit0_f_jumpnv_nt:
13145
    case Hexagon::J4_tstbit0_f_jumpnv_t:
13146
    case Hexagon::J4_tstbit0_t_jumpnv_nt:
13147
    case Hexagon::J4_tstbit0_t_jumpnv_t: {
13148
      switch (OpNum) {
13149
      case 1:
13150
        // op: Ii
13151
        return 1;
13152
      case 0:
13153
        // op: Ns8
13154
        return 16;
13155
      }
13156
      break;
13157
    }
13158
    case Hexagon::J2_callf:
13159
    case Hexagon::J2_callt:
13160
    case Hexagon::J2_jumpf:
13161
    case Hexagon::J2_jumpfnew:
13162
    case Hexagon::J2_jumpfnewpt:
13163
    case Hexagon::J2_jumpfpt:
13164
    case Hexagon::J2_jumpt:
13165
    case Hexagon::J2_jumptnew:
13166
    case Hexagon::J2_jumptnewpt:
13167
    case Hexagon::J2_jumptpt: {
13168
      switch (OpNum) {
13169
      case 1:
13170
        // op: Ii
13171
        return 1;
13172
      case 0:
13173
        // op: Pu4
13174
        return 8;
13175
      }
13176
      break;
13177
    }
13178
    case Hexagon::J4_tstbit0_fp0_jump_nt:
13179
    case Hexagon::J4_tstbit0_fp0_jump_t:
13180
    case Hexagon::J4_tstbit0_fp1_jump_nt:
13181
    case Hexagon::J4_tstbit0_fp1_jump_t:
13182
    case Hexagon::J4_tstbit0_tp0_jump_nt:
13183
    case Hexagon::J4_tstbit0_tp0_jump_t:
13184
    case Hexagon::J4_tstbit0_tp1_jump_nt:
13185
    case Hexagon::J4_tstbit0_tp1_jump_t: {
13186
      switch (OpNum) {
13187
      case 1:
13188
        // op: Ii
13189
        return 1;
13190
      case 0:
13191
        // op: Rs16
13192
        return 16;
13193
      }
13194
      break;
13195
    }
13196
    case Hexagon::J2_jumprgtez:
13197
    case Hexagon::J2_jumprgtezpt:
13198
    case Hexagon::J2_jumprltez:
13199
    case Hexagon::J2_jumprltezpt:
13200
    case Hexagon::J2_jumprnz:
13201
    case Hexagon::J2_jumprnzpt:
13202
    case Hexagon::J2_jumprz:
13203
    case Hexagon::J2_jumprzpt: {
13204
      switch (OpNum) {
13205
      case 1:
13206
        // op: Ii
13207
        return 1;
13208
      case 0:
13209
        // op: Rs32
13210
        return 16;
13211
      }
13212
      break;
13213
    }
13214
    case Hexagon::S4_pstorerbnewf_abs:
13215
    case Hexagon::S4_pstorerbnewfnew_abs:
13216
    case Hexagon::S4_pstorerbnewt_abs:
13217
    case Hexagon::S4_pstorerbnewtnew_abs:
13218
    case Hexagon::S4_pstorerhnewf_abs:
13219
    case Hexagon::S4_pstorerhnewfnew_abs:
13220
    case Hexagon::S4_pstorerhnewt_abs:
13221
    case Hexagon::S4_pstorerhnewtnew_abs:
13222
    case Hexagon::S4_pstorerinewf_abs:
13223
    case Hexagon::S4_pstorerinewfnew_abs:
13224
    case Hexagon::S4_pstorerinewt_abs:
13225
    case Hexagon::S4_pstorerinewtnew_abs: {
13226
      switch (OpNum) {
13227
      case 1:
13228
        // op: Ii
13229
        return 3;
13230
      case 0:
13231
        // op: Pv4
13232
        return 0;
13233
      case 2:
13234
        // op: Nt8
13235
        return 8;
13236
      }
13237
      break;
13238
    }
13239
    case Hexagon::S4_pstorerbf_abs:
13240
    case Hexagon::S4_pstorerbfnew_abs:
13241
    case Hexagon::S4_pstorerbt_abs:
13242
    case Hexagon::S4_pstorerbtnew_abs:
13243
    case Hexagon::S4_pstorerff_abs:
13244
    case Hexagon::S4_pstorerffnew_abs:
13245
    case Hexagon::S4_pstorerft_abs:
13246
    case Hexagon::S4_pstorerftnew_abs:
13247
    case Hexagon::S4_pstorerhf_abs:
13248
    case Hexagon::S4_pstorerhfnew_abs:
13249
    case Hexagon::S4_pstorerht_abs:
13250
    case Hexagon::S4_pstorerhtnew_abs:
13251
    case Hexagon::S4_pstorerif_abs:
13252
    case Hexagon::S4_pstorerifnew_abs:
13253
    case Hexagon::S4_pstorerit_abs:
13254
    case Hexagon::S4_pstoreritnew_abs: {
13255
      switch (OpNum) {
13256
      case 1:
13257
        // op: Ii
13258
        return 3;
13259
      case 0:
13260
        // op: Pv4
13261
        return 0;
13262
      case 2:
13263
        // op: Rt32
13264
        return 8;
13265
      }
13266
      break;
13267
    }
13268
    case Hexagon::S4_pstorerdf_abs:
13269
    case Hexagon::S4_pstorerdfnew_abs:
13270
    case Hexagon::S4_pstorerdt_abs:
13271
    case Hexagon::S4_pstorerdtnew_abs: {
13272
      switch (OpNum) {
13273
      case 1:
13274
        // op: Ii
13275
        return 3;
13276
      case 0:
13277
        // op: Pv4
13278
        return 0;
13279
      case 2:
13280
        // op: Rtt32
13281
        return 8;
13282
      }
13283
      break;
13284
    }
13285
    case Hexagon::SL2_loadrd_sp: {
13286
      switch (OpNum) {
13287
      case 1:
13288
        // op: Ii
13289
        return 3;
13290
      case 0:
13291
        // op: Rdd8
13292
        return 0;
13293
      }
13294
      break;
13295
    }
13296
    case Hexagon::S4_addi_asl_ri:
13297
    case Hexagon::S4_addi_lsr_ri:
13298
    case Hexagon::S4_andi_asl_ri:
13299
    case Hexagon::S4_andi_lsr_ri:
13300
    case Hexagon::S4_ori_asl_ri:
13301
    case Hexagon::S4_ori_lsr_ri:
13302
    case Hexagon::S4_subi_asl_ri:
13303
    case Hexagon::S4_subi_lsr_ri: {
13304
      switch (OpNum) {
13305
      case 1:
13306
        // op: Ii
13307
        return 3;
13308
      case 3:
13309
        // op: II
13310
        return 8;
13311
      case 0:
13312
        // op: Rx32
13313
        return 16;
13314
      }
13315
      break;
13316
    }
13317
    case Hexagon::SA1_addsp:
13318
    case Hexagon::SA1_seti:
13319
    case Hexagon::SL2_loadri_sp: {
13320
      switch (OpNum) {
13321
      case 1:
13322
        // op: Ii
13323
        return 4;
13324
      case 0:
13325
        // op: Rd16
13326
        return 0;
13327
      }
13328
      break;
13329
    }
13330
    case Hexagon::A2_tfrsi:
13331
    case Hexagon::F2_sfimm_n:
13332
    case Hexagon::F2_sfimm_p:
13333
    case Hexagon::L2_loadrbgp:
13334
    case Hexagon::L2_loadrhgp:
13335
    case Hexagon::L2_loadrigp:
13336
    case Hexagon::L2_loadrubgp:
13337
    case Hexagon::L2_loadruhgp:
13338
    case Hexagon::PS_loadrbabs:
13339
    case Hexagon::PS_loadrhabs:
13340
    case Hexagon::PS_loadriabs:
13341
    case Hexagon::PS_loadrubabs:
13342
    case Hexagon::PS_loadruhabs: {
13343
      switch (OpNum) {
13344
      case 1:
13345
        // op: Ii
13346
        return 5;
13347
      case 0:
13348
        // op: Rd32
13349
        return 0;
13350
      }
13351
      break;
13352
    }
13353
    case Hexagon::F2_dfimm_n:
13354
    case Hexagon::F2_dfimm_p:
13355
    case Hexagon::L2_loadrdgp:
13356
    case Hexagon::PS_loadrdabs: {
13357
      switch (OpNum) {
13358
      case 1:
13359
        // op: Ii
13360
        return 5;
13361
      case 0:
13362
        // op: Rdd32
13363
        return 0;
13364
      }
13365
      break;
13366
    }
13367
    case Hexagon::SA1_combine0i:
13368
    case Hexagon::SA1_combine1i:
13369
    case Hexagon::SA1_combine2i:
13370
    case Hexagon::SA1_combine3i: {
13371
      switch (OpNum) {
13372
      case 1:
13373
        // op: Ii
13374
        return 5;
13375
      case 0:
13376
        // op: Rdd8
13377
        return 0;
13378
      }
13379
      break;
13380
    }
13381
    case Hexagon::A2_combineii:
13382
    case Hexagon::A4_combineii: {
13383
      switch (OpNum) {
13384
      case 1:
13385
        // op: Ii
13386
        return 5;
13387
      case 2:
13388
        // op: II
13389
        return 13;
13390
      case 0:
13391
        // op: Rdd32
13392
        return 0;
13393
      }
13394
      break;
13395
    }
13396
    case Hexagon::A2_subri: {
13397
      switch (OpNum) {
13398
      case 1:
13399
        // op: Ii
13400
        return 5;
13401
      case 2:
13402
        // op: Rs32
13403
        return 16;
13404
      case 0:
13405
        // op: Rd32
13406
        return 0;
13407
      }
13408
      break;
13409
    }
13410
    case Hexagon::A4_combineir: {
13411
      switch (OpNum) {
13412
      case 1:
13413
        // op: Ii
13414
        return 5;
13415
      case 2:
13416
        // op: Rs32
13417
        return 16;
13418
      case 0:
13419
        // op: Rdd32
13420
        return 0;
13421
      }
13422
      break;
13423
    }
13424
    case Hexagon::M4_mpyrr_addi: {
13425
      switch (OpNum) {
13426
      case 1:
13427
        // op: Ii
13428
        return 5;
13429
      case 2:
13430
        // op: Rs32
13431
        return 16;
13432
      case 3:
13433
        // op: Rt32
13434
        return 8;
13435
      case 0:
13436
        // op: Rd32
13437
        return 0;
13438
      }
13439
      break;
13440
    }
13441
    case Hexagon::S4_lsli: {
13442
      switch (OpNum) {
13443
      case 1:
13444
        // op: Ii
13445
        return 5;
13446
      case 2:
13447
        // op: Rt32
13448
        return 8;
13449
      case 0:
13450
        // op: Rd32
13451
        return 0;
13452
      }
13453
      break;
13454
    }
13455
    case Hexagon::M4_mpyri_addi: {
13456
      switch (OpNum) {
13457
      case 1:
13458
        // op: Ii
13459
        return 5;
13460
      case 3:
13461
        // op: II
13462
        return 0;
13463
      case 2:
13464
        // op: Rs32
13465
        return 16;
13466
      case 0:
13467
        // op: Rd32
13468
        return 8;
13469
      }
13470
      break;
13471
    }
13472
    case Hexagon::S4_storerbnew_ur:
13473
    case Hexagon::S4_storerhnew_ur:
13474
    case Hexagon::S4_storerinew_ur: {
13475
      switch (OpNum) {
13476
      case 1:
13477
        // op: Ii
13478
        return 6;
13479
      case 2:
13480
        // op: II
13481
        return 0;
13482
      case 0:
13483
        // op: Ru32
13484
        return 16;
13485
      case 3:
13486
        // op: Nt8
13487
        return 8;
13488
      }
13489
      break;
13490
    }
13491
    case Hexagon::S4_storerb_ur:
13492
    case Hexagon::S4_storerf_ur:
13493
    case Hexagon::S4_storerh_ur:
13494
    case Hexagon::S4_storeri_ur: {
13495
      switch (OpNum) {
13496
      case 1:
13497
        // op: Ii
13498
        return 6;
13499
      case 2:
13500
        // op: II
13501
        return 0;
13502
      case 0:
13503
        // op: Ru32
13504
        return 16;
13505
      case 3:
13506
        // op: Rt32
13507
        return 8;
13508
      }
13509
      break;
13510
    }
13511
    case Hexagon::S4_storerd_ur: {
13512
      switch (OpNum) {
13513
      case 1:
13514
        // op: Ii
13515
        return 6;
13516
      case 2:
13517
        // op: II
13518
        return 0;
13519
      case 0:
13520
        // op: Ru32
13521
        return 16;
13522
      case 3:
13523
        // op: Rtt32
13524
        return 8;
13525
      }
13526
      break;
13527
    }
13528
    case Hexagon::C4_addipc: {
13529
      switch (OpNum) {
13530
      case 1:
13531
        // op: Ii
13532
        return 7;
13533
      case 0:
13534
        // op: Rd32
13535
        return 0;
13536
      }
13537
      break;
13538
    }
13539
    case Hexagon::L4_add_memopb_io:
13540
    case Hexagon::L4_add_memoph_io:
13541
    case Hexagon::L4_add_memopw_io:
13542
    case Hexagon::L4_and_memopb_io:
13543
    case Hexagon::L4_and_memoph_io:
13544
    case Hexagon::L4_and_memopw_io:
13545
    case Hexagon::L4_or_memopb_io:
13546
    case Hexagon::L4_or_memoph_io:
13547
    case Hexagon::L4_or_memopw_io:
13548
    case Hexagon::L4_sub_memopb_io:
13549
    case Hexagon::L4_sub_memoph_io:
13550
    case Hexagon::L4_sub_memopw_io: {
13551
      switch (OpNum) {
13552
      case 1:
13553
        // op: Ii
13554
        return 7;
13555
      case 0:
13556
        // op: Rs32
13557
        return 16;
13558
      case 2:
13559
        // op: Rt32
13560
        return 0;
13561
      }
13562
      break;
13563
    }
13564
    case Hexagon::L4_iadd_memopb_io:
13565
    case Hexagon::L4_iadd_memoph_io:
13566
    case Hexagon::L4_iadd_memopw_io:
13567
    case Hexagon::L4_iand_memopb_io:
13568
    case Hexagon::L4_iand_memoph_io:
13569
    case Hexagon::L4_iand_memopw_io:
13570
    case Hexagon::L4_ior_memopb_io:
13571
    case Hexagon::L4_ior_memoph_io:
13572
    case Hexagon::L4_ior_memopw_io:
13573
    case Hexagon::L4_isub_memopb_io:
13574
    case Hexagon::L4_isub_memoph_io:
13575
    case Hexagon::L4_isub_memopw_io:
13576
    case Hexagon::S4_storeirb_io:
13577
    case Hexagon::S4_storeirh_io:
13578
    case Hexagon::S4_storeiri_io: {
13579
      switch (OpNum) {
13580
      case 1:
13581
        // op: Ii
13582
        return 7;
13583
      case 2:
13584
        // op: II
13585
        return 0;
13586
      case 0:
13587
        // op: Rs32
13588
        return 16;
13589
      }
13590
      break;
13591
    }
13592
    case Hexagon::V6_vwhist128qm: {
13593
      switch (OpNum) {
13594
      case 1:
13595
        // op: Ii
13596
        return 8;
13597
      case 0:
13598
        // op: Qv4
13599
        return 22;
13600
      }
13601
      break;
13602
    }
13603
    case Hexagon::SS1_storeb_io:
13604
    case Hexagon::SS1_storew_io:
13605
    case Hexagon::SS2_storeh_io: {
13606
      switch (OpNum) {
13607
      case 1:
13608
        // op: Ii
13609
        return 8;
13610
      case 0:
13611
        // op: Rs16
13612
        return 4;
13613
      case 2:
13614
        // op: Rt16
13615
        return 0;
13616
      }
13617
      break;
13618
    }
13619
    case Hexagon::V6_vS32b_new_ai:
13620
    case Hexagon::V6_vS32b_nt_new_ai: {
13621
      switch (OpNum) {
13622
      case 1:
13623
        // op: Ii
13624
        return 8;
13625
      case 0:
13626
        // op: Rt32
13627
        return 16;
13628
      case 2:
13629
        // op: Os8
13630
        return 0;
13631
      }
13632
      break;
13633
    }
13634
    case Hexagon::V6_vS32Ub_ai:
13635
    case Hexagon::V6_vS32b_ai:
13636
    case Hexagon::V6_vS32b_nt_ai: {
13637
      switch (OpNum) {
13638
      case 1:
13639
        // op: Ii
13640
        return 8;
13641
      case 0:
13642
        // op: Rt32
13643
        return 16;
13644
      case 2:
13645
        // op: Vs32
13646
        return 0;
13647
      }
13648
      break;
13649
    }
13650
    case Hexagon::V6_vS32b_srls_ai:
13651
    case Hexagon::V6_zLd_ai: {
13652
      switch (OpNum) {
13653
      case 1:
13654
        // op: Ii
13655
        return 8;
13656
      case 0:
13657
        // op: Rt32
13658
        return 16;
13659
      }
13660
      break;
13661
    }
13662
    case Hexagon::S2_mask: {
13663
      switch (OpNum) {
13664
      case 1:
13665
        // op: Ii
13666
        return 8;
13667
      case 2:
13668
        // op: II
13669
        return 5;
13670
      case 0:
13671
        // op: Rd32
13672
        return 0;
13673
      }
13674
      break;
13675
    }
13676
    case Hexagon::C2_all8:
13677
    case Hexagon::C2_any8:
13678
    case Hexagon::C2_not: {
13679
      switch (OpNum) {
13680
      case 1:
13681
        // op: Ps4
13682
        return 16;
13683
      case 0:
13684
        // op: Pd4
13685
        return 0;
13686
      }
13687
      break;
13688
    }
13689
    case Hexagon::C2_tfrpr: {
13690
      switch (OpNum) {
13691
      case 1:
13692
        // op: Ps4
13693
        return 16;
13694
      case 0:
13695
        // op: Rd32
13696
        return 0;
13697
      }
13698
      break;
13699
    }
13700
    case Hexagon::C2_xor:
13701
    case Hexagon::C4_fastcorner9:
13702
    case Hexagon::C4_fastcorner9_not: {
13703
      switch (OpNum) {
13704
      case 1:
13705
        // op: Ps4
13706
        return 16;
13707
      case 2:
13708
        // op: Pt4
13709
        return 8;
13710
      case 0:
13711
        // op: Pd4
13712
        return 0;
13713
      }
13714
      break;
13715
    }
13716
    case Hexagon::C2_vitpack: {
13717
      switch (OpNum) {
13718
      case 1:
13719
        // op: Ps4
13720
        return 16;
13721
      case 2:
13722
        // op: Pt4
13723
        return 8;
13724
      case 0:
13725
        // op: Rd32
13726
        return 0;
13727
      }
13728
      break;
13729
    }
13730
    case Hexagon::C4_and_and:
13731
    case Hexagon::C4_and_andn:
13732
    case Hexagon::C4_and_or:
13733
    case Hexagon::C4_and_orn:
13734
    case Hexagon::C4_or_and:
13735
    case Hexagon::C4_or_andn:
13736
    case Hexagon::C4_or_or:
13737
    case Hexagon::C4_or_orn: {
13738
      switch (OpNum) {
13739
      case 1:
13740
        // op: Ps4
13741
        return 16;
13742
      case 2:
13743
        // op: Pt4
13744
        return 8;
13745
      case 3:
13746
        // op: Pu4
13747
        return 6;
13748
      case 0:
13749
        // op: Pd4
13750
        return 0;
13751
      }
13752
      break;
13753
    }
13754
    case Hexagon::V6_vcmov:
13755
    case Hexagon::V6_vncmov: {
13756
      switch (OpNum) {
13757
      case 1:
13758
        // op: Ps4
13759
        return 5;
13760
      case 2:
13761
        // op: Vu32
13762
        return 8;
13763
      case 0:
13764
        // op: Vd32
13765
        return 0;
13766
      }
13767
      break;
13768
    }
13769
    case Hexagon::V6_vccombine:
13770
    case Hexagon::V6_vnccombine: {
13771
      switch (OpNum) {
13772
      case 1:
13773
        // op: Ps4
13774
        return 5;
13775
      case 2:
13776
        // op: Vu32
13777
        return 8;
13778
      case 3:
13779
        // op: Vv32
13780
        return 16;
13781
      case 0:
13782
        // op: Vdd32
13783
        return 0;
13784
      }
13785
      break;
13786
    }
13787
    case Hexagon::C2_mask: {
13788
      switch (OpNum) {
13789
      case 1:
13790
        // op: Pt4
13791
        return 8;
13792
      case 0:
13793
        // op: Rdd32
13794
        return 0;
13795
      }
13796
      break;
13797
    }
13798
    case Hexagon::C2_and:
13799
    case Hexagon::C2_andn:
13800
    case Hexagon::C2_or:
13801
    case Hexagon::C2_orn: {
13802
      switch (OpNum) {
13803
      case 1:
13804
        // op: Pt4
13805
        return 8;
13806
      case 2:
13807
        // op: Ps4
13808
        return 16;
13809
      case 0:
13810
        // op: Pd4
13811
        return 0;
13812
      }
13813
      break;
13814
    }
13815
    case Hexagon::A2_paddf:
13816
    case Hexagon::A2_paddfnew:
13817
    case Hexagon::A2_paddt:
13818
    case Hexagon::A2_paddtnew:
13819
    case Hexagon::A2_pandf:
13820
    case Hexagon::A2_pandfnew:
13821
    case Hexagon::A2_pandt:
13822
    case Hexagon::A2_pandtnew:
13823
    case Hexagon::A2_porf:
13824
    case Hexagon::A2_porfnew:
13825
    case Hexagon::A2_port:
13826
    case Hexagon::A2_portnew:
13827
    case Hexagon::A2_pxorf:
13828
    case Hexagon::A2_pxorfnew:
13829
    case Hexagon::A2_pxort:
13830
    case Hexagon::A2_pxortnew:
13831
    case Hexagon::C2_mux: {
13832
      switch (OpNum) {
13833
      case 1:
13834
        // op: Pu4
13835
        return 5;
13836
      case 2:
13837
        // op: Rs32
13838
        return 16;
13839
      case 3:
13840
        // op: Rt32
13841
        return 8;
13842
      case 0:
13843
        // op: Rd32
13844
        return 0;
13845
      }
13846
      break;
13847
    }
13848
    case Hexagon::C2_ccombinewf:
13849
    case Hexagon::C2_ccombinewnewf:
13850
    case Hexagon::C2_ccombinewnewt:
13851
    case Hexagon::C2_ccombinewt: {
13852
      switch (OpNum) {
13853
      case 1:
13854
        // op: Pu4
13855
        return 5;
13856
      case 2:
13857
        // op: Rs32
13858
        return 16;
13859
      case 3:
13860
        // op: Rt32
13861
        return 8;
13862
      case 0:
13863
        // op: Rdd32
13864
        return 0;
13865
      }
13866
      break;
13867
    }
13868
    case Hexagon::C2_vmux: {
13869
      switch (OpNum) {
13870
      case 1:
13871
        // op: Pu4
13872
        return 5;
13873
      case 2:
13874
        // op: Rss32
13875
        return 16;
13876
      case 3:
13877
        // op: Rtt32
13878
        return 8;
13879
      case 0:
13880
        // op: Rdd32
13881
        return 0;
13882
      }
13883
      break;
13884
    }
13885
    case Hexagon::A2_psubf:
13886
    case Hexagon::A2_psubfnew:
13887
    case Hexagon::A2_psubt:
13888
    case Hexagon::A2_psubtnew: {
13889
      switch (OpNum) {
13890
      case 1:
13891
        // op: Pu4
13892
        return 5;
13893
      case 2:
13894
        // op: Rt32
13895
        return 8;
13896
      case 3:
13897
        // op: Rs32
13898
        return 16;
13899
      case 0:
13900
        // op: Rd32
13901
        return 0;
13902
      }
13903
      break;
13904
    }
13905
    case Hexagon::A4_paslhf:
13906
    case Hexagon::A4_paslhfnew:
13907
    case Hexagon::A4_paslht:
13908
    case Hexagon::A4_paslhtnew:
13909
    case Hexagon::A4_pasrhf:
13910
    case Hexagon::A4_pasrhfnew:
13911
    case Hexagon::A4_pasrht:
13912
    case Hexagon::A4_pasrhtnew:
13913
    case Hexagon::A4_psxtbf:
13914
    case Hexagon::A4_psxtbfnew:
13915
    case Hexagon::A4_psxtbt:
13916
    case Hexagon::A4_psxtbtnew:
13917
    case Hexagon::A4_psxthf:
13918
    case Hexagon::A4_psxthfnew:
13919
    case Hexagon::A4_psxtht:
13920
    case Hexagon::A4_psxthtnew:
13921
    case Hexagon::A4_pzxtbf:
13922
    case Hexagon::A4_pzxtbfnew:
13923
    case Hexagon::A4_pzxtbt:
13924
    case Hexagon::A4_pzxtbtnew:
13925
    case Hexagon::A4_pzxthf:
13926
    case Hexagon::A4_pzxthfnew:
13927
    case Hexagon::A4_pzxtht:
13928
    case Hexagon::A4_pzxthtnew: {
13929
      switch (OpNum) {
13930
      case 1:
13931
        // op: Pu4
13932
        return 8;
13933
      case 2:
13934
        // op: Rs32
13935
        return 16;
13936
      case 0:
13937
        // op: Rd32
13938
        return 0;
13939
      }
13940
      break;
13941
    }
13942
    case Hexagon::V6_zLd_pred_ppu: {
13943
      switch (OpNum) {
13944
      case 1:
13945
        // op: Pv4
13946
        return 11;
13947
      case 3:
13948
        // op: Mu2
13949
        return 13;
13950
      case 0:
13951
        // op: Rx32
13952
        return 16;
13953
      }
13954
      break;
13955
    }
13956
    case Hexagon::V6_vS32b_new_npred_ppu:
13957
    case Hexagon::V6_vS32b_new_pred_ppu:
13958
    case Hexagon::V6_vS32b_nt_new_npred_ppu:
13959
    case Hexagon::V6_vS32b_nt_new_pred_ppu: {
13960
      switch (OpNum) {
13961
      case 1:
13962
        // op: Pv4
13963
        return 11;
13964
      case 3:
13965
        // op: Mu2
13966
        return 13;
13967
      case 4:
13968
        // op: Os8
13969
        return 0;
13970
      case 0:
13971
        // op: Rx32
13972
        return 16;
13973
      }
13974
      break;
13975
    }
13976
    case Hexagon::V6_vS32Ub_npred_ppu:
13977
    case Hexagon::V6_vS32Ub_pred_ppu:
13978
    case Hexagon::V6_vS32b_npred_ppu:
13979
    case Hexagon::V6_vS32b_nt_npred_ppu:
13980
    case Hexagon::V6_vS32b_nt_pred_ppu:
13981
    case Hexagon::V6_vS32b_pred_ppu: {
13982
      switch (OpNum) {
13983
      case 1:
13984
        // op: Pv4
13985
        return 11;
13986
      case 3:
13987
        // op: Mu2
13988
        return 13;
13989
      case 4:
13990
        // op: Vs32
13991
        return 0;
13992
      case 0:
13993
        // op: Rx32
13994
        return 16;
13995
      }
13996
      break;
13997
    }
13998
    case Hexagon::L4_return_f:
13999
    case Hexagon::L4_return_fnew_pnt:
14000
    case Hexagon::L4_return_fnew_pt:
14001
    case Hexagon::L4_return_t:
14002
    case Hexagon::L4_return_tnew_pnt:
14003
    case Hexagon::L4_return_tnew_pt: {
14004
      switch (OpNum) {
14005
      case 1:
14006
        // op: Pv4
14007
        return 8;
14008
      case 2:
14009
        // op: Rs32
14010
        return 16;
14011
      case 0:
14012
        // op: Rdd32
14013
        return 0;
14014
      }
14015
      break;
14016
    }
14017
    case Hexagon::V6_pred_not: {
14018
      switch (OpNum) {
14019
      case 1:
14020
        // op: Qs4
14021
        return 8;
14022
      case 0:
14023
        // op: Qd4
14024
        return 0;
14025
      }
14026
      break;
14027
    }
14028
    case Hexagon::V6_pred_and:
14029
    case Hexagon::V6_pred_and_n:
14030
    case Hexagon::V6_pred_or:
14031
    case Hexagon::V6_pred_or_n:
14032
    case Hexagon::V6_pred_xor:
14033
    case Hexagon::V6_shuffeqh:
14034
    case Hexagon::V6_shuffeqw: {
14035
      switch (OpNum) {
14036
      case 1:
14037
        // op: Qs4
14038
        return 8;
14039
      case 2:
14040
        // op: Qt4
14041
        return 22;
14042
      case 0:
14043
        // op: Qd4
14044
        return 0;
14045
      }
14046
      break;
14047
    }
14048
    case Hexagon::V6_vmux: {
14049
      switch (OpNum) {
14050
      case 1:
14051
        // op: Qt4
14052
        return 5;
14053
      case 2:
14054
        // op: Vu32
14055
        return 8;
14056
      case 3:
14057
        // op: Vv32
14058
        return 16;
14059
      case 0:
14060
        // op: Vd32
14061
        return 0;
14062
      }
14063
      break;
14064
    }
14065
    case Hexagon::V6_vswap: {
14066
      switch (OpNum) {
14067
      case 1:
14068
        // op: Qt4
14069
        return 5;
14070
      case 2:
14071
        // op: Vu32
14072
        return 8;
14073
      case 3:
14074
        // op: Vv32
14075
        return 16;
14076
      case 0:
14077
        // op: Vdd32
14078
        return 0;
14079
      }
14080
      break;
14081
    }
14082
    case Hexagon::V6_vandnqrt:
14083
    case Hexagon::V6_vandqrt: {
14084
      switch (OpNum) {
14085
      case 1:
14086
        // op: Qu4
14087
        return 8;
14088
      case 2:
14089
        // op: Rt32
14090
        return 16;
14091
      case 0:
14092
        // op: Vd32
14093
        return 0;
14094
      }
14095
      break;
14096
    }
14097
    case Hexagon::V6_vS32b_nqpred_ppu:
14098
    case Hexagon::V6_vS32b_nt_nqpred_ppu:
14099
    case Hexagon::V6_vS32b_nt_qpred_ppu:
14100
    case Hexagon::V6_vS32b_qpred_ppu: {
14101
      switch (OpNum) {
14102
      case 1:
14103
        // op: Qv4
14104
        return 11;
14105
      case 3:
14106
        // op: Mu2
14107
        return 13;
14108
      case 4:
14109
        // op: Vs32
14110
        return 0;
14111
      case 0:
14112
        // op: Rx32
14113
        return 16;
14114
      }
14115
      break;
14116
    }
14117
    case Hexagon::V6_vprefixqb:
14118
    case Hexagon::V6_vprefixqh:
14119
    case Hexagon::V6_vprefixqw: {
14120
      switch (OpNum) {
14121
      case 1:
14122
        // op: Qv4
14123
        return 22;
14124
      case 0:
14125
        // op: Vd32
14126
        return 0;
14127
      }
14128
      break;
14129
    }
14130
    case Hexagon::V6_vandvnqv:
14131
    case Hexagon::V6_vandvqv: {
14132
      switch (OpNum) {
14133
      case 1:
14134
        // op: Qv4
14135
        return 22;
14136
      case 2:
14137
        // op: Vu32
14138
        return 8;
14139
      case 0:
14140
        // op: Vd32
14141
        return 0;
14142
      }
14143
      break;
14144
    }
14145
    case Hexagon::V6_vaddbnq:
14146
    case Hexagon::V6_vaddbq:
14147
    case Hexagon::V6_vaddhnq:
14148
    case Hexagon::V6_vaddhq:
14149
    case Hexagon::V6_vaddwnq:
14150
    case Hexagon::V6_vaddwq:
14151
    case Hexagon::V6_vsubbnq:
14152
    case Hexagon::V6_vsubbq:
14153
    case Hexagon::V6_vsubhnq:
14154
    case Hexagon::V6_vsubhq:
14155
    case Hexagon::V6_vsubwnq:
14156
    case Hexagon::V6_vsubwq: {
14157
      switch (OpNum) {
14158
      case 1:
14159
        // op: Qv4
14160
        return 22;
14161
      case 3:
14162
        // op: Vu32
14163
        return 8;
14164
      case 0:
14165
        // op: Vx32
14166
        return 0;
14167
      }
14168
      break;
14169
    }
14170
    case Hexagon::SA1_and1:
14171
    case Hexagon::SA1_dec:
14172
    case Hexagon::SA1_inc:
14173
    case Hexagon::SA1_sxtb:
14174
    case Hexagon::SA1_sxth:
14175
    case Hexagon::SA1_tfr:
14176
    case Hexagon::SA1_zxtb:
14177
    case Hexagon::SA1_zxth: {
14178
      switch (OpNum) {
14179
      case 1:
14180
        // op: Rs16
14181
        return 4;
14182
      case 0:
14183
        // op: Rd16
14184
        return 0;
14185
      }
14186
      break;
14187
    }
14188
    case Hexagon::SA1_combinerz:
14189
    case Hexagon::SA1_combinezr: {
14190
      switch (OpNum) {
14191
      case 1:
14192
        // op: Rs16
14193
        return 4;
14194
      case 0:
14195
        // op: Rdd8
14196
        return 0;
14197
      }
14198
      break;
14199
    }
14200
    case Hexagon::A2_tfrrcr: {
14201
      switch (OpNum) {
14202
      case 1:
14203
        // op: Rs32
14204
        return 16;
14205
      case 0:
14206
        // op: Cd32
14207
        return 0;
14208
      }
14209
      break;
14210
    }
14211
    case Hexagon::G4_tfrgrcr: {
14212
      switch (OpNum) {
14213
      case 1:
14214
        // op: Rs32
14215
        return 16;
14216
      case 0:
14217
        // op: Gd32
14218
        return 0;
14219
      }
14220
      break;
14221
    }
14222
    case Hexagon::C2_tfrrp:
14223
    case Hexagon::Y5_l2locka: {
14224
      switch (OpNum) {
14225
      case 1:
14226
        // op: Rs32
14227
        return 16;
14228
      case 0:
14229
        // op: Pd4
14230
        return 0;
14231
      }
14232
      break;
14233
    }
14234
    case Hexagon::A2_abs:
14235
    case Hexagon::A2_abssat:
14236
    case Hexagon::A2_aslh:
14237
    case Hexagon::A2_asrh:
14238
    case Hexagon::A2_negsat:
14239
    case Hexagon::A2_satb:
14240
    case Hexagon::A2_sath:
14241
    case Hexagon::A2_satub:
14242
    case Hexagon::A2_satuh:
14243
    case Hexagon::A2_swiz:
14244
    case Hexagon::A2_sxtb:
14245
    case Hexagon::A2_sxth:
14246
    case Hexagon::A2_tfr:
14247
    case Hexagon::A2_zxth:
14248
    case Hexagon::F2_conv_sf2uw:
14249
    case Hexagon::F2_conv_sf2uw_chop:
14250
    case Hexagon::F2_conv_sf2w:
14251
    case Hexagon::F2_conv_sf2w_chop:
14252
    case Hexagon::F2_conv_uw2sf:
14253
    case Hexagon::F2_conv_w2sf:
14254
    case Hexagon::F2_sffixupr:
14255
    case Hexagon::L2_loadw_aq:
14256
    case Hexagon::L2_loadw_locked:
14257
    case Hexagon::S2_brev:
14258
    case Hexagon::S2_cl0:
14259
    case Hexagon::S2_cl1:
14260
    case Hexagon::S2_clb:
14261
    case Hexagon::S2_clbnorm:
14262
    case Hexagon::S2_ct0:
14263
    case Hexagon::S2_ct1:
14264
    case Hexagon::S2_svsathb:
14265
    case Hexagon::S2_svsathub:
14266
    case Hexagon::S2_vsplatrb:
14267
    case Hexagon::Y2_dctagr:
14268
    case Hexagon::Y2_getimask:
14269
    case Hexagon::Y2_iassignr:
14270
    case Hexagon::Y2_icdatar:
14271
    case Hexagon::Y2_ictagr:
14272
    case Hexagon::Y2_tlbp:
14273
    case Hexagon::Y4_l2tagr: {
14274
      switch (OpNum) {
14275
      case 1:
14276
        // op: Rs32
14277
        return 16;
14278
      case 0:
14279
        // op: Rd32
14280
        return 0;
14281
      }
14282
      break;
14283
    }
14284
    case Hexagon::A2_sxtw:
14285
    case Hexagon::F2_conv_sf2d:
14286
    case Hexagon::F2_conv_sf2d_chop:
14287
    case Hexagon::F2_conv_sf2df:
14288
    case Hexagon::F2_conv_sf2ud:
14289
    case Hexagon::F2_conv_sf2ud_chop:
14290
    case Hexagon::F2_conv_uw2df:
14291
    case Hexagon::F2_conv_w2df:
14292
    case Hexagon::L2_deallocframe:
14293
    case Hexagon::L4_loadd_aq:
14294
    case Hexagon::L4_loadd_locked:
14295
    case Hexagon::L4_return:
14296
    case Hexagon::S2_vsplatrh:
14297
    case Hexagon::S2_vsxtbh:
14298
    case Hexagon::S2_vsxthw:
14299
    case Hexagon::S2_vzxtbh:
14300
    case Hexagon::S2_vzxthw:
14301
    case Hexagon::S6_vsplatrbp:
14302
    case Hexagon::Y2_tlbr: {
14303
      switch (OpNum) {
14304
      case 1:
14305
        // op: Rs32
14306
        return 16;
14307
      case 0:
14308
        // op: Rdd32
14309
        return 0;
14310
      }
14311
      break;
14312
    }
14313
    case Hexagon::Y2_tfrsrcr: {
14314
      switch (OpNum) {
14315
      case 1:
14316
        // op: Rs32
14317
        return 16;
14318
      case 0:
14319
        // op: Sd128
14320
        return 0;
14321
      }
14322
      break;
14323
    }
14324
    case Hexagon::A4_cmpbeq:
14325
    case Hexagon::A4_cmpbgt:
14326
    case Hexagon::A4_cmpbgtu:
14327
    case Hexagon::A4_cmpheq:
14328
    case Hexagon::A4_cmphgt:
14329
    case Hexagon::A4_cmphgtu:
14330
    case Hexagon::C2_bitsclr:
14331
    case Hexagon::C2_bitsset:
14332
    case Hexagon::C2_cmpeq:
14333
    case Hexagon::C2_cmpgt:
14334
    case Hexagon::C2_cmpgtu:
14335
    case Hexagon::C4_cmplte:
14336
    case Hexagon::C4_cmplteu:
14337
    case Hexagon::C4_cmpneq:
14338
    case Hexagon::C4_nbitsclr:
14339
    case Hexagon::C4_nbitsset:
14340
    case Hexagon::F2_sfcmpeq:
14341
    case Hexagon::F2_sfcmpge:
14342
    case Hexagon::F2_sfcmpgt:
14343
    case Hexagon::F2_sfcmpuo:
14344
    case Hexagon::S2_storew_locked:
14345
    case Hexagon::S2_tstbit_r:
14346
    case Hexagon::S4_ntstbit_r: {
14347
      switch (OpNum) {
14348
      case 1:
14349
        // op: Rs32
14350
        return 16;
14351
      case 2:
14352
        // op: Rt32
14353
        return 8;
14354
      case 0:
14355
        // op: Pd4
14356
        return 0;
14357
      }
14358
      break;
14359
    }
14360
    case Hexagon::A2_add:
14361
    case Hexagon::A2_addsat:
14362
    case Hexagon::A2_and:
14363
    case Hexagon::A2_max:
14364
    case Hexagon::A2_maxu:
14365
    case Hexagon::A2_or:
14366
    case Hexagon::A2_svaddh:
14367
    case Hexagon::A2_svaddhs:
14368
    case Hexagon::A2_svadduhs:
14369
    case Hexagon::A2_svavgh:
14370
    case Hexagon::A2_svavghs:
14371
    case Hexagon::A2_xor:
14372
    case Hexagon::A4_cround_rr:
14373
    case Hexagon::A4_modwrapu:
14374
    case Hexagon::A4_rcmpeq:
14375
    case Hexagon::A4_rcmpneq:
14376
    case Hexagon::A4_round_rr:
14377
    case Hexagon::A4_round_rr_sat:
14378
    case Hexagon::F2_sfadd:
14379
    case Hexagon::F2_sffixupd:
14380
    case Hexagon::F2_sffixupn:
14381
    case Hexagon::F2_sfmax:
14382
    case Hexagon::F2_sfmin:
14383
    case Hexagon::F2_sfmpy:
14384
    case Hexagon::F2_sfsub:
14385
    case Hexagon::L4_loadw_phys:
14386
    case Hexagon::M2_cmpyrs_s0:
14387
    case Hexagon::M2_cmpyrs_s1:
14388
    case Hexagon::M2_cmpyrsc_s0:
14389
    case Hexagon::M2_cmpyrsc_s1:
14390
    case Hexagon::M2_dpmpyss_rnd_s0:
14391
    case Hexagon::M2_hmmpyh_rs1:
14392
    case Hexagon::M2_hmmpyh_s1:
14393
    case Hexagon::M2_hmmpyl_rs1:
14394
    case Hexagon::M2_hmmpyl_s1:
14395
    case Hexagon::M2_mpy_hh_s0:
14396
    case Hexagon::M2_mpy_hh_s1:
14397
    case Hexagon::M2_mpy_hl_s0:
14398
    case Hexagon::M2_mpy_hl_s1:
14399
    case Hexagon::M2_mpy_lh_s0:
14400
    case Hexagon::M2_mpy_lh_s1:
14401
    case Hexagon::M2_mpy_ll_s0:
14402
    case Hexagon::M2_mpy_ll_s1:
14403
    case Hexagon::M2_mpy_rnd_hh_s0:
14404
    case Hexagon::M2_mpy_rnd_hh_s1:
14405
    case Hexagon::M2_mpy_rnd_hl_s0:
14406
    case Hexagon::M2_mpy_rnd_hl_s1:
14407
    case Hexagon::M2_mpy_rnd_lh_s0:
14408
    case Hexagon::M2_mpy_rnd_lh_s1:
14409
    case Hexagon::M2_mpy_rnd_ll_s0:
14410
    case Hexagon::M2_mpy_rnd_ll_s1:
14411
    case Hexagon::M2_mpy_sat_hh_s0:
14412
    case Hexagon::M2_mpy_sat_hh_s1:
14413
    case Hexagon::M2_mpy_sat_hl_s0:
14414
    case Hexagon::M2_mpy_sat_hl_s1:
14415
    case Hexagon::M2_mpy_sat_lh_s0:
14416
    case Hexagon::M2_mpy_sat_lh_s1:
14417
    case Hexagon::M2_mpy_sat_ll_s0:
14418
    case Hexagon::M2_mpy_sat_ll_s1:
14419
    case Hexagon::M2_mpy_sat_rnd_hh_s0:
14420
    case Hexagon::M2_mpy_sat_rnd_hh_s1:
14421
    case Hexagon::M2_mpy_sat_rnd_hl_s0:
14422
    case Hexagon::M2_mpy_sat_rnd_hl_s1:
14423
    case Hexagon::M2_mpy_sat_rnd_lh_s0:
14424
    case Hexagon::M2_mpy_sat_rnd_lh_s1:
14425
    case Hexagon::M2_mpy_sat_rnd_ll_s0:
14426
    case Hexagon::M2_mpy_sat_rnd_ll_s1:
14427
    case Hexagon::M2_mpy_up:
14428
    case Hexagon::M2_mpy_up_s1:
14429
    case Hexagon::M2_mpy_up_s1_sat:
14430
    case Hexagon::M2_mpyi:
14431
    case Hexagon::M2_mpysu_up:
14432
    case Hexagon::M2_mpyu_hh_s0:
14433
    case Hexagon::M2_mpyu_hh_s1:
14434
    case Hexagon::M2_mpyu_hl_s0:
14435
    case Hexagon::M2_mpyu_hl_s1:
14436
    case Hexagon::M2_mpyu_lh_s0:
14437
    case Hexagon::M2_mpyu_lh_s1:
14438
    case Hexagon::M2_mpyu_ll_s0:
14439
    case Hexagon::M2_mpyu_ll_s1:
14440
    case Hexagon::M2_mpyu_up:
14441
    case Hexagon::M2_vmpy2s_s0pack:
14442
    case Hexagon::M2_vmpy2s_s1pack:
14443
    case Hexagon::S2_asl_r_r:
14444
    case Hexagon::S2_asl_r_r_sat:
14445
    case Hexagon::S2_asr_r_r:
14446
    case Hexagon::S2_asr_r_r_sat:
14447
    case Hexagon::S2_clrbit_r:
14448
    case Hexagon::S2_lsl_r_r:
14449
    case Hexagon::S2_lsr_r_r:
14450
    case Hexagon::S2_setbit_r:
14451
    case Hexagon::S2_togglebit_r:
14452
    case Hexagon::S4_parity:
14453
    case Hexagon::dep_A2_addsat: {
14454
      switch (OpNum) {
14455
      case 1:
14456
        // op: Rs32
14457
        return 16;
14458
      case 2:
14459
        // op: Rt32
14460
        return 8;
14461
      case 0:
14462
        // op: Rd32
14463
        return 0;
14464
      }
14465
      break;
14466
    }
14467
    case Hexagon::A2_combinew:
14468
    case Hexagon::A4_bitsplit:
14469
    case Hexagon::M2_cmpyi_s0:
14470
    case Hexagon::M2_cmpyr_s0:
14471
    case Hexagon::M2_cmpys_s0:
14472
    case Hexagon::M2_cmpys_s1:
14473
    case Hexagon::M2_cmpysc_s0:
14474
    case Hexagon::M2_cmpysc_s1:
14475
    case Hexagon::M2_dpmpyss_s0:
14476
    case Hexagon::M2_dpmpyuu_s0:
14477
    case Hexagon::M2_mpyd_hh_s0:
14478
    case Hexagon::M2_mpyd_hh_s1:
14479
    case Hexagon::M2_mpyd_hl_s0:
14480
    case Hexagon::M2_mpyd_hl_s1:
14481
    case Hexagon::M2_mpyd_lh_s0:
14482
    case Hexagon::M2_mpyd_lh_s1:
14483
    case Hexagon::M2_mpyd_ll_s0:
14484
    case Hexagon::M2_mpyd_ll_s1:
14485
    case Hexagon::M2_mpyd_rnd_hh_s0:
14486
    case Hexagon::M2_mpyd_rnd_hh_s1:
14487
    case Hexagon::M2_mpyd_rnd_hl_s0:
14488
    case Hexagon::M2_mpyd_rnd_hl_s1:
14489
    case Hexagon::M2_mpyd_rnd_lh_s0:
14490
    case Hexagon::M2_mpyd_rnd_lh_s1:
14491
    case Hexagon::M2_mpyd_rnd_ll_s0:
14492
    case Hexagon::M2_mpyd_rnd_ll_s1:
14493
    case Hexagon::M2_mpyud_hh_s0:
14494
    case Hexagon::M2_mpyud_hh_s1:
14495
    case Hexagon::M2_mpyud_hl_s0:
14496
    case Hexagon::M2_mpyud_hl_s1:
14497
    case Hexagon::M2_mpyud_lh_s0:
14498
    case Hexagon::M2_mpyud_lh_s1:
14499
    case Hexagon::M2_mpyud_ll_s0:
14500
    case Hexagon::M2_mpyud_ll_s1:
14501
    case Hexagon::M2_vmpy2s_s0:
14502
    case Hexagon::M2_vmpy2s_s1:
14503
    case Hexagon::M2_vmpy2su_s0:
14504
    case Hexagon::M2_vmpy2su_s1:
14505
    case Hexagon::M4_pmpyw:
14506
    case Hexagon::M4_vpmpyh:
14507
    case Hexagon::M5_vmpybsu:
14508
    case Hexagon::M5_vmpybuu:
14509
    case Hexagon::S2_packhl:
14510
    case Hexagon::dep_S2_packhl: {
14511
      switch (OpNum) {
14512
      case 1:
14513
        // op: Rs32
14514
        return 16;
14515
      case 2:
14516
        // op: Rt32
14517
        return 8;
14518
      case 0:
14519
        // op: Rdd32
14520
        return 0;
14521
      }
14522
      break;
14523
    }
14524
    case Hexagon::S4_stored_locked: {
14525
      switch (OpNum) {
14526
      case 1:
14527
        // op: Rs32
14528
        return 16;
14529
      case 2:
14530
        // op: Rtt32
14531
        return 8;
14532
      case 0:
14533
        // op: Pd4
14534
        return 0;
14535
      }
14536
      break;
14537
    }
14538
    case Hexagon::S2_extractu_rp:
14539
    case Hexagon::S4_extract_rp: {
14540
      switch (OpNum) {
14541
      case 1:
14542
        // op: Rs32
14543
        return 16;
14544
      case 2:
14545
        // op: Rtt32
14546
        return 8;
14547
      case 0:
14548
        // op: Rd32
14549
        return 0;
14550
      }
14551
      break;
14552
    }
14553
    case Hexagon::A4_tfrpcp: {
14554
      switch (OpNum) {
14555
      case 1:
14556
        // op: Rss32
14557
        return 16;
14558
      case 0:
14559
        // op: Cdd32
14560
        return 0;
14561
      }
14562
      break;
14563
    }
14564
    case Hexagon::G4_tfrgpcp: {
14565
      switch (OpNum) {
14566
      case 1:
14567
        // op: Rss32
14568
        return 16;
14569
      case 0:
14570
        // op: Gdd32
14571
        return 0;
14572
      }
14573
      break;
14574
    }
14575
    case Hexagon::A2_roundsat:
14576
    case Hexagon::A2_sat:
14577
    case Hexagon::F2_conv_d2sf:
14578
    case Hexagon::F2_conv_df2sf:
14579
    case Hexagon::F2_conv_df2uw:
14580
    case Hexagon::F2_conv_df2uw_chop:
14581
    case Hexagon::F2_conv_df2w:
14582
    case Hexagon::F2_conv_df2w_chop:
14583
    case Hexagon::F2_conv_ud2sf:
14584
    case Hexagon::S2_cl0p:
14585
    case Hexagon::S2_cl1p:
14586
    case Hexagon::S2_clbp:
14587
    case Hexagon::S2_ct0p:
14588
    case Hexagon::S2_ct1p:
14589
    case Hexagon::S2_vrndpackwh:
14590
    case Hexagon::S2_vrndpackwhs:
14591
    case Hexagon::S2_vsathb:
14592
    case Hexagon::S2_vsathub:
14593
    case Hexagon::S2_vsatwh:
14594
    case Hexagon::S2_vsatwuh:
14595
    case Hexagon::S2_vtrunehb:
14596
    case Hexagon::S2_vtrunohb:
14597
    case Hexagon::S4_clbpnorm:
14598
    case Hexagon::S5_popcountp:
14599
    case Hexagon::Y5_tlboc: {
14600
      switch (OpNum) {
14601
      case 1:
14602
        // op: Rss32
14603
        return 16;
14604
      case 0:
14605
        // op: Rd32
14606
        return 0;
14607
      }
14608
      break;
14609
    }
14610
    case Hexagon::A2_absp:
14611
    case Hexagon::A2_negp:
14612
    case Hexagon::A2_notp:
14613
    case Hexagon::A2_vabsh:
14614
    case Hexagon::A2_vabshsat:
14615
    case Hexagon::A2_vabsw:
14616
    case Hexagon::A2_vabswsat:
14617
    case Hexagon::A2_vconj:
14618
    case Hexagon::F2_conv_d2df:
14619
    case Hexagon::F2_conv_df2d:
14620
    case Hexagon::F2_conv_df2d_chop:
14621
    case Hexagon::F2_conv_df2ud:
14622
    case Hexagon::F2_conv_df2ud_chop:
14623
    case Hexagon::F2_conv_ud2df:
14624
    case Hexagon::S2_brevp:
14625
    case Hexagon::S2_deinterleave:
14626
    case Hexagon::S2_interleave:
14627
    case Hexagon::S2_vsathb_nopack:
14628
    case Hexagon::S2_vsathub_nopack:
14629
    case Hexagon::S2_vsatwh_nopack:
14630
    case Hexagon::S2_vsatwuh_nopack: {
14631
      switch (OpNum) {
14632
      case 1:
14633
        // op: Rss32
14634
        return 16;
14635
      case 0:
14636
        // op: Rdd32
14637
        return 0;
14638
      }
14639
      break;
14640
    }
14641
    case Hexagon::Y4_tfrspcp: {
14642
      switch (OpNum) {
14643
      case 1:
14644
        // op: Rss32
14645
        return 16;
14646
      case 0:
14647
        // op: Sdd128
14648
        return 0;
14649
      }
14650
      break;
14651
    }
14652
    case Hexagon::A4_tlbmatch: {
14653
      switch (OpNum) {
14654
      case 1:
14655
        // op: Rss32
14656
        return 16;
14657
      case 2:
14658
        // op: Rt32
14659
        return 8;
14660
      case 0:
14661
        // op: Pd4
14662
        return 0;
14663
      }
14664
      break;
14665
    }
14666
    case Hexagon::M4_cmpyi_wh:
14667
    case Hexagon::M4_cmpyi_whc:
14668
    case Hexagon::M4_cmpyr_wh:
14669
    case Hexagon::M4_cmpyr_whc:
14670
    case Hexagon::S2_asr_r_svw_trun:
14671
    case Hexagon::Y5_ctlbw: {
14672
      switch (OpNum) {
14673
      case 1:
14674
        // op: Rss32
14675
        return 16;
14676
      case 2:
14677
        // op: Rt32
14678
        return 8;
14679
      case 0:
14680
        // op: Rd32
14681
        return 0;
14682
      }
14683
      break;
14684
    }
14685
    case Hexagon::A7_croundd_rr:
14686
    case Hexagon::S2_asl_r_p:
14687
    case Hexagon::S2_asl_r_vh:
14688
    case Hexagon::S2_asl_r_vw:
14689
    case Hexagon::S2_asr_r_p:
14690
    case Hexagon::S2_asr_r_vh:
14691
    case Hexagon::S2_asr_r_vw:
14692
    case Hexagon::S2_lsl_r_p:
14693
    case Hexagon::S2_lsl_r_vh:
14694
    case Hexagon::S2_lsl_r_vw:
14695
    case Hexagon::S2_lsr_r_p:
14696
    case Hexagon::S2_lsr_r_vh:
14697
    case Hexagon::S2_lsr_r_vw:
14698
    case Hexagon::S2_vcnegh:
14699
    case Hexagon::S2_vcrotate: {
14700
      switch (OpNum) {
14701
      case 1:
14702
        // op: Rss32
14703
        return 16;
14704
      case 2:
14705
        // op: Rt32
14706
        return 8;
14707
      case 0:
14708
        // op: Rdd32
14709
        return 0;
14710
      }
14711
      break;
14712
    }
14713
    case Hexagon::A2_vcmpbeq:
14714
    case Hexagon::A2_vcmpbgtu:
14715
    case Hexagon::A2_vcmpheq:
14716
    case Hexagon::A2_vcmphgt:
14717
    case Hexagon::A2_vcmphgtu:
14718
    case Hexagon::A2_vcmpweq:
14719
    case Hexagon::A2_vcmpwgt:
14720
    case Hexagon::A2_vcmpwgtu:
14721
    case Hexagon::A4_boundscheck_hi:
14722
    case Hexagon::A4_boundscheck_lo:
14723
    case Hexagon::A4_vcmpbeq_any:
14724
    case Hexagon::A4_vcmpbgt:
14725
    case Hexagon::A6_vcmpbeq_notany:
14726
    case Hexagon::C2_cmpeqp:
14727
    case Hexagon::C2_cmpgtp:
14728
    case Hexagon::C2_cmpgtup:
14729
    case Hexagon::F2_dfcmpeq:
14730
    case Hexagon::F2_dfcmpge:
14731
    case Hexagon::F2_dfcmpgt:
14732
    case Hexagon::F2_dfcmpuo: {
14733
      switch (OpNum) {
14734
      case 1:
14735
        // op: Rss32
14736
        return 16;
14737
      case 2:
14738
        // op: Rtt32
14739
        return 8;
14740
      case 0:
14741
        // op: Pd4
14742
        return 0;
14743
      }
14744
      break;
14745
    }
14746
    case Hexagon::A5_vaddhubs:
14747
    case Hexagon::M2_vdmpyrs_s0:
14748
    case Hexagon::M2_vdmpyrs_s1:
14749
    case Hexagon::M2_vraddh:
14750
    case Hexagon::M2_vradduh:
14751
    case Hexagon::M2_vrcmpys_s1rp_h:
14752
    case Hexagon::M2_vrcmpys_s1rp_l:
14753
    case Hexagon::M7_wcmpyiw:
14754
    case Hexagon::M7_wcmpyiw_rnd:
14755
    case Hexagon::M7_wcmpyiwc:
14756
    case Hexagon::M7_wcmpyiwc_rnd:
14757
    case Hexagon::M7_wcmpyrw:
14758
    case Hexagon::M7_wcmpyrw_rnd:
14759
    case Hexagon::M7_wcmpyrwc:
14760
    case Hexagon::M7_wcmpyrwc_rnd:
14761
    case Hexagon::S2_parityp: {
14762
      switch (OpNum) {
14763
      case 1:
14764
        // op: Rss32
14765
        return 16;
14766
      case 2:
14767
        // op: Rtt32
14768
        return 8;
14769
      case 0:
14770
        // op: Rd32
14771
        return 0;
14772
      }
14773
      break;
14774
    }
14775
    case Hexagon::A2_addp:
14776
    case Hexagon::A2_addpsat:
14777
    case Hexagon::A2_addsph:
14778
    case Hexagon::A2_addspl:
14779
    case Hexagon::A2_andp:
14780
    case Hexagon::A2_maxp:
14781
    case Hexagon::A2_maxup:
14782
    case Hexagon::A2_orp:
14783
    case Hexagon::A2_vaddh:
14784
    case Hexagon::A2_vaddhs:
14785
    case Hexagon::A2_vaddub:
14786
    case Hexagon::A2_vaddubs:
14787
    case Hexagon::A2_vadduhs:
14788
    case Hexagon::A2_vaddw:
14789
    case Hexagon::A2_vaddws:
14790
    case Hexagon::A2_vavgh:
14791
    case Hexagon::A2_vavghcr:
14792
    case Hexagon::A2_vavghr:
14793
    case Hexagon::A2_vavgub:
14794
    case Hexagon::A2_vavgubr:
14795
    case Hexagon::A2_vavguh:
14796
    case Hexagon::A2_vavguhr:
14797
    case Hexagon::A2_vavguw:
14798
    case Hexagon::A2_vavguwr:
14799
    case Hexagon::A2_vavgw:
14800
    case Hexagon::A2_vavgwcr:
14801
    case Hexagon::A2_vavgwr:
14802
    case Hexagon::A2_vraddub:
14803
    case Hexagon::A2_vrsadub:
14804
    case Hexagon::A2_xorp:
14805
    case Hexagon::F2_dfadd:
14806
    case Hexagon::F2_dfmax:
14807
    case Hexagon::F2_dfmin:
14808
    case Hexagon::F2_dfmpyfix:
14809
    case Hexagon::F2_dfmpyll:
14810
    case Hexagon::F2_dfsub:
14811
    case Hexagon::M2_mmpyh_rs0:
14812
    case Hexagon::M2_mmpyh_rs1:
14813
    case Hexagon::M2_mmpyh_s0:
14814
    case Hexagon::M2_mmpyh_s1:
14815
    case Hexagon::M2_mmpyl_rs0:
14816
    case Hexagon::M2_mmpyl_rs1:
14817
    case Hexagon::M2_mmpyl_s0:
14818
    case Hexagon::M2_mmpyl_s1:
14819
    case Hexagon::M2_mmpyuh_rs0:
14820
    case Hexagon::M2_mmpyuh_rs1:
14821
    case Hexagon::M2_mmpyuh_s0:
14822
    case Hexagon::M2_mmpyuh_s1:
14823
    case Hexagon::M2_mmpyul_rs0:
14824
    case Hexagon::M2_mmpyul_rs1:
14825
    case Hexagon::M2_mmpyul_s0:
14826
    case Hexagon::M2_mmpyul_s1:
14827
    case Hexagon::M2_vcmpy_s0_sat_i:
14828
    case Hexagon::M2_vcmpy_s0_sat_r:
14829
    case Hexagon::M2_vcmpy_s1_sat_i:
14830
    case Hexagon::M2_vcmpy_s1_sat_r:
14831
    case Hexagon::M2_vdmpys_s0:
14832
    case Hexagon::M2_vdmpys_s1:
14833
    case Hexagon::M2_vmpy2es_s0:
14834
    case Hexagon::M2_vmpy2es_s1:
14835
    case Hexagon::M2_vrcmpyi_s0:
14836
    case Hexagon::M2_vrcmpyi_s0c:
14837
    case Hexagon::M2_vrcmpyr_s0:
14838
    case Hexagon::M2_vrcmpyr_s0c:
14839
    case Hexagon::M2_vrcmpys_s1_h:
14840
    case Hexagon::M2_vrcmpys_s1_l:
14841
    case Hexagon::M2_vrmpy_s0:
14842
    case Hexagon::M4_vrmpyeh_s0:
14843
    case Hexagon::M4_vrmpyeh_s1:
14844
    case Hexagon::M4_vrmpyoh_s0:
14845
    case Hexagon::M4_vrmpyoh_s1:
14846
    case Hexagon::M5_vdmpybsu:
14847
    case Hexagon::M5_vrmpybsu:
14848
    case Hexagon::M5_vrmpybuu:
14849
    case Hexagon::M7_dcmpyiw:
14850
    case Hexagon::M7_dcmpyiwc:
14851
    case Hexagon::M7_dcmpyrw:
14852
    case Hexagon::M7_dcmpyrwc:
14853
    case Hexagon::S2_cabacdecbin:
14854
    case Hexagon::S2_extractup_rp:
14855
    case Hexagon::S2_lfsp:
14856
    case Hexagon::S2_shuffeb:
14857
    case Hexagon::S2_shuffeh:
14858
    case Hexagon::S2_vtrunewh:
14859
    case Hexagon::S2_vtrunowh:
14860
    case Hexagon::S4_extractp_rp:
14861
    case Hexagon::S4_vxaddsubh:
14862
    case Hexagon::S4_vxaddsubhr:
14863
    case Hexagon::S4_vxaddsubw:
14864
    case Hexagon::S4_vxsubaddh:
14865
    case Hexagon::S4_vxsubaddhr:
14866
    case Hexagon::S4_vxsubaddw:
14867
    case Hexagon::S6_vtrunehb_ppp:
14868
    case Hexagon::S6_vtrunohb_ppp: {
14869
      switch (OpNum) {
14870
      case 1:
14871
        // op: Rss32
14872
        return 16;
14873
      case 2:
14874
        // op: Rtt32
14875
        return 8;
14876
      case 0:
14877
        // op: Rdd32
14878
        return 0;
14879
      }
14880
      break;
14881
    }
14882
    case Hexagon::S2_vsplicerb: {
14883
      switch (OpNum) {
14884
      case 1:
14885
        // op: Rss32
14886
        return 16;
14887
      case 2:
14888
        // op: Rtt32
14889
        return 8;
14890
      case 3:
14891
        // op: Pu4
14892
        return 5;
14893
      case 0:
14894
        // op: Rdd32
14895
        return 0;
14896
      }
14897
      break;
14898
    }
14899
    case Hexagon::V6_pred_scalar2:
14900
    case Hexagon::V6_pred_scalar2v2: {
14901
      switch (OpNum) {
14902
      case 1:
14903
        // op: Rt32
14904
        return 16;
14905
      case 0:
14906
        // op: Qd4
14907
        return 0;
14908
      }
14909
      break;
14910
    }
14911
    case Hexagon::V6_lvsplatb:
14912
    case Hexagon::V6_lvsplath:
14913
    case Hexagon::V6_lvsplatw:
14914
    case Hexagon::V6_zextract: {
14915
      switch (OpNum) {
14916
      case 1:
14917
        // op: Rt32
14918
        return 16;
14919
      case 0:
14920
        // op: Vd32
14921
        return 0;
14922
      }
14923
      break;
14924
    }
14925
    case Hexagon::A2_addh_h16_hh:
14926
    case Hexagon::A2_addh_h16_hl:
14927
    case Hexagon::A2_addh_h16_lh:
14928
    case Hexagon::A2_addh_h16_ll:
14929
    case Hexagon::A2_addh_h16_sat_hh:
14930
    case Hexagon::A2_addh_h16_sat_hl:
14931
    case Hexagon::A2_addh_h16_sat_lh:
14932
    case Hexagon::A2_addh_h16_sat_ll:
14933
    case Hexagon::A2_addh_l16_hl:
14934
    case Hexagon::A2_addh_l16_ll:
14935
    case Hexagon::A2_addh_l16_sat_hl:
14936
    case Hexagon::A2_addh_l16_sat_ll:
14937
    case Hexagon::A2_combine_hh:
14938
    case Hexagon::A2_combine_hl:
14939
    case Hexagon::A2_combine_lh:
14940
    case Hexagon::A2_combine_ll:
14941
    case Hexagon::A2_min:
14942
    case Hexagon::A2_minu:
14943
    case Hexagon::A2_sub:
14944
    case Hexagon::A2_subh_h16_hh:
14945
    case Hexagon::A2_subh_h16_hl:
14946
    case Hexagon::A2_subh_h16_lh:
14947
    case Hexagon::A2_subh_h16_ll:
14948
    case Hexagon::A2_subh_h16_sat_hh:
14949
    case Hexagon::A2_subh_h16_sat_hl:
14950
    case Hexagon::A2_subh_h16_sat_lh:
14951
    case Hexagon::A2_subh_h16_sat_ll:
14952
    case Hexagon::A2_subh_l16_hl:
14953
    case Hexagon::A2_subh_l16_ll:
14954
    case Hexagon::A2_subh_l16_sat_hl:
14955
    case Hexagon::A2_subh_l16_sat_ll:
14956
    case Hexagon::A2_subsat:
14957
    case Hexagon::A2_svnavgh:
14958
    case Hexagon::A2_svsubh:
14959
    case Hexagon::A2_svsubhs:
14960
    case Hexagon::A2_svsubuhs:
14961
    case Hexagon::A4_andn:
14962
    case Hexagon::A4_orn:
14963
    case Hexagon::dep_A2_subsat: {
14964
      switch (OpNum) {
14965
      case 1:
14966
        // op: Rt32
14967
        return 8;
14968
      case 2:
14969
        // op: Rs32
14970
        return 16;
14971
      case 0:
14972
        // op: Rd32
14973
        return 0;
14974
      }
14975
      break;
14976
    }
14977
    case Hexagon::A2_minp:
14978
    case Hexagon::A2_minup:
14979
    case Hexagon::A2_subp:
14980
    case Hexagon::A2_vmaxb:
14981
    case Hexagon::A2_vmaxh:
14982
    case Hexagon::A2_vmaxub:
14983
    case Hexagon::A2_vmaxuh:
14984
    case Hexagon::A2_vmaxuw:
14985
    case Hexagon::A2_vmaxw:
14986
    case Hexagon::A2_vminb:
14987
    case Hexagon::A2_vminh:
14988
    case Hexagon::A2_vminub:
14989
    case Hexagon::A2_vminuh:
14990
    case Hexagon::A2_vminuw:
14991
    case Hexagon::A2_vminw:
14992
    case Hexagon::A2_vnavgh:
14993
    case Hexagon::A2_vnavghcr:
14994
    case Hexagon::A2_vnavghr:
14995
    case Hexagon::A2_vnavgw:
14996
    case Hexagon::A2_vnavgwcr:
14997
    case Hexagon::A2_vnavgwr:
14998
    case Hexagon::A2_vsubh:
14999
    case Hexagon::A2_vsubhs:
15000
    case Hexagon::A2_vsubub:
15001
    case Hexagon::A2_vsububs:
15002
    case Hexagon::A2_vsubuhs:
15003
    case Hexagon::A2_vsubw:
15004
    case Hexagon::A2_vsubws:
15005
    case Hexagon::A4_andnp:
15006
    case Hexagon::A4_ornp:
15007
    case Hexagon::M2_vabsdiffh:
15008
    case Hexagon::M2_vabsdiffw:
15009
    case Hexagon::M6_vabsdiffb:
15010
    case Hexagon::M6_vabsdiffub:
15011
    case Hexagon::S2_shuffob:
15012
    case Hexagon::S2_shuffoh: {
15013
      switch (OpNum) {
15014
      case 1:
15015
        // op: Rtt32
15016
        return 8;
15017
      case 2:
15018
        // op: Rss32
15019
        return 16;
15020
      case 0:
15021
        // op: Rdd32
15022
        return 0;
15023
      }
15024
      break;
15025
    }
15026
    case Hexagon::S2_valignrb: {
15027
      switch (OpNum) {
15028
      case 1:
15029
        // op: Rtt32
15030
        return 8;
15031
      case 2:
15032
        // op: Rss32
15033
        return 16;
15034
      case 3:
15035
        // op: Pu4
15036
        return 5;
15037
      case 0:
15038
        // op: Rdd32
15039
        return 0;
15040
      }
15041
      break;
15042
    }
15043
    case Hexagon::M4_mpyrr_addr: {
15044
      switch (OpNum) {
15045
      case 1:
15046
        // op: Ru32
15047
        return 0;
15048
      case 3:
15049
        // op: Rs32
15050
        return 16;
15051
      case 0:
15052
        // op: Ry32
15053
        return 8;
15054
      }
15055
      break;
15056
    }
15057
    case Hexagon::Y2_tfrscrr: {
15058
      switch (OpNum) {
15059
      case 1:
15060
        // op: Ss128
15061
        return 16;
15062
      case 0:
15063
        // op: Rd32
15064
        return 0;
15065
      }
15066
      break;
15067
    }
15068
    case Hexagon::Y4_tfrscpp: {
15069
      switch (OpNum) {
15070
      case 1:
15071
        // op: Sss128
15072
        return 16;
15073
      case 0:
15074
        // op: Rdd32
15075
        return 0;
15076
      }
15077
      break;
15078
    }
15079
    case Hexagon::V6_vabs_hf:
15080
    case Hexagon::V6_vabs_sf:
15081
    case Hexagon::V6_vabsb:
15082
    case Hexagon::V6_vabsb_sat:
15083
    case Hexagon::V6_vabsh:
15084
    case Hexagon::V6_vabsh_sat:
15085
    case Hexagon::V6_vabsw:
15086
    case Hexagon::V6_vabsw_sat:
15087
    case Hexagon::V6_vassign:
15088
    case Hexagon::V6_vassign_fp:
15089
    case Hexagon::V6_vassign_tmp:
15090
    case Hexagon::V6_vcl0h:
15091
    case Hexagon::V6_vcl0w:
15092
    case Hexagon::V6_vconv_h_hf:
15093
    case Hexagon::V6_vconv_hf_h:
15094
    case Hexagon::V6_vconv_hf_qf16:
15095
    case Hexagon::V6_vconv_sf_qf32:
15096
    case Hexagon::V6_vconv_sf_w:
15097
    case Hexagon::V6_vconv_w_sf:
15098
    case Hexagon::V6_vcvt_h_hf:
15099
    case Hexagon::V6_vcvt_hf_h:
15100
    case Hexagon::V6_vcvt_hf_uh:
15101
    case Hexagon::V6_vcvt_uh_hf:
15102
    case Hexagon::V6_vdealb:
15103
    case Hexagon::V6_vdealh:
15104
    case Hexagon::V6_vfneg_hf:
15105
    case Hexagon::V6_vfneg_sf:
15106
    case Hexagon::V6_vnormamth:
15107
    case Hexagon::V6_vnormamtw:
15108
    case Hexagon::V6_vnot:
15109
    case Hexagon::V6_vpopcounth:
15110
    case Hexagon::V6_vshuffb:
15111
    case Hexagon::V6_vshuffh: {
15112
      switch (OpNum) {
15113
      case 1:
15114
        // op: Vu32
15115
        return 8;
15116
      case 0:
15117
        // op: Vd32
15118
        return 0;
15119
      }
15120
      break;
15121
    }
15122
    case Hexagon::V6_vcvt_hf_b:
15123
    case Hexagon::V6_vcvt_hf_ub:
15124
    case Hexagon::V6_vcvt_sf_hf:
15125
    case Hexagon::V6_vsb:
15126
    case Hexagon::V6_vsh:
15127
    case Hexagon::V6_vunpackb:
15128
    case Hexagon::V6_vunpackh:
15129
    case Hexagon::V6_vunpackub:
15130
    case Hexagon::V6_vunpackuh:
15131
    case Hexagon::V6_vzb:
15132
    case Hexagon::V6_vzh: {
15133
      switch (OpNum) {
15134
      case 1:
15135
        // op: Vu32
15136
        return 8;
15137
      case 0:
15138
        // op: Vdd32
15139
        return 0;
15140
      }
15141
      break;
15142
    }
15143
    case Hexagon::V6_extractw: {
15144
      switch (OpNum) {
15145
      case 1:
15146
        // op: Vu32
15147
        return 8;
15148
      case 2:
15149
        // op: Rs32
15150
        return 16;
15151
      case 0:
15152
        // op: Rd32
15153
        return 0;
15154
      }
15155
      break;
15156
    }
15157
    case Hexagon::V6_vandvrt: {
15158
      switch (OpNum) {
15159
      case 1:
15160
        // op: Vu32
15161
        return 8;
15162
      case 2:
15163
        // op: Rt32
15164
        return 16;
15165
      case 0:
15166
        // op: Qd4
15167
        return 0;
15168
      }
15169
      break;
15170
    }
15171
    case Hexagon::V6_vaslh:
15172
    case Hexagon::V6_vaslw:
15173
    case Hexagon::V6_vasrh:
15174
    case Hexagon::V6_vasrw:
15175
    case Hexagon::V6_vdmpybus:
15176
    case Hexagon::V6_vdmpyhb:
15177
    case Hexagon::V6_vdmpyhsat:
15178
    case Hexagon::V6_vdmpyhsusat:
15179
    case Hexagon::V6_vlsrb:
15180
    case Hexagon::V6_vlsrh:
15181
    case Hexagon::V6_vlsrw:
15182
    case Hexagon::V6_vmpyhsrs:
15183
    case Hexagon::V6_vmpyhss:
15184
    case Hexagon::V6_vmpyihb:
15185
    case Hexagon::V6_vmpyiwb:
15186
    case Hexagon::V6_vmpyiwh:
15187
    case Hexagon::V6_vmpyiwub:
15188
    case Hexagon::V6_vmpyuhe:
15189
    case Hexagon::V6_vrmpybus:
15190
    case Hexagon::V6_vrmpyub:
15191
    case Hexagon::V6_vror: {
15192
      switch (OpNum) {
15193
      case 1:
15194
        // op: Vu32
15195
        return 8;
15196
      case 2:
15197
        // op: Rt32
15198
        return 16;
15199
      case 0:
15200
        // op: Vd32
15201
        return 0;
15202
      }
15203
      break;
15204
    }
15205
    case Hexagon::V6_vmpybus:
15206
    case Hexagon::V6_vmpyh:
15207
    case Hexagon::V6_vmpyub:
15208
    case Hexagon::V6_vmpyuh: {
15209
      switch (OpNum) {
15210
      case 1:
15211
        // op: Vu32
15212
        return 8;
15213
      case 2:
15214
        // op: Rt32
15215
        return 16;
15216
      case 0:
15217
        // op: Vdd32
15218
        return 0;
15219
      }
15220
      break;
15221
    }
15222
    case Hexagon::V6_vrmpyzbb_rt:
15223
    case Hexagon::V6_vrmpyzbub_rt:
15224
    case Hexagon::V6_vrmpyzcb_rt:
15225
    case Hexagon::V6_vrmpyzcbs_rt:
15226
    case Hexagon::V6_vrmpyznb_rt: {
15227
      switch (OpNum) {
15228
      case 1:
15229
        // op: Vu32
15230
        return 8;
15231
      case 2:
15232
        // op: Rt8
15233
        return 16;
15234
      case 0:
15235
        // op: Vdddd32
15236
        return 0;
15237
      }
15238
      break;
15239
    }
15240
    case Hexagon::V6_vlut4: {
15241
      switch (OpNum) {
15242
      case 1:
15243
        // op: Vu32
15244
        return 8;
15245
      case 2:
15246
        // op: Rtt32
15247
        return 16;
15248
      case 0:
15249
        // op: Vd32
15250
        return 0;
15251
      }
15252
      break;
15253
    }
15254
    case Hexagon::V6_vrmpybub_rtt:
15255
    case Hexagon::V6_vrmpyub_rtt: {
15256
      switch (OpNum) {
15257
      case 1:
15258
        // op: Vu32
15259
        return 8;
15260
      case 2:
15261
        // op: Rtt32
15262
        return 16;
15263
      case 0:
15264
        // op: Vdd32
15265
        return 0;
15266
      }
15267
      break;
15268
    }
15269
    case Hexagon::V6_veqb:
15270
    case Hexagon::V6_veqh:
15271
    case Hexagon::V6_veqw:
15272
    case Hexagon::V6_vgtb:
15273
    case Hexagon::V6_vgtbf:
15274
    case Hexagon::V6_vgth:
15275
    case Hexagon::V6_vgthf:
15276
    case Hexagon::V6_vgtsf:
15277
    case Hexagon::V6_vgtub:
15278
    case Hexagon::V6_vgtuh:
15279
    case Hexagon::V6_vgtuw:
15280
    case Hexagon::V6_vgtw: {
15281
      switch (OpNum) {
15282
      case 1:
15283
        // op: Vu32
15284
        return 8;
15285
      case 2:
15286
        // op: Vv32
15287
        return 16;
15288
      case 0:
15289
        // op: Qd4
15290
        return 0;
15291
      }
15292
      break;
15293
    }
15294
    case Hexagon::V6_vabsdiffh:
15295
    case Hexagon::V6_vabsdiffub:
15296
    case Hexagon::V6_vabsdiffuh:
15297
    case Hexagon::V6_vabsdiffw:
15298
    case Hexagon::V6_vadd_hf:
15299
    case Hexagon::V6_vadd_hf_hf:
15300
    case Hexagon::V6_vadd_qf16:
15301
    case Hexagon::V6_vadd_qf16_mix:
15302
    case Hexagon::V6_vadd_qf32:
15303
    case Hexagon::V6_vadd_qf32_mix:
15304
    case Hexagon::V6_vadd_sf:
15305
    case Hexagon::V6_vadd_sf_sf:
15306
    case Hexagon::V6_vaddb:
15307
    case Hexagon::V6_vaddbsat:
15308
    case Hexagon::V6_vaddclbh:
15309
    case Hexagon::V6_vaddclbw:
15310
    case Hexagon::V6_vaddh:
15311
    case Hexagon::V6_vaddhsat:
15312
    case Hexagon::V6_vaddubsat:
15313
    case Hexagon::V6_vaddububb_sat:
15314
    case Hexagon::V6_vadduhsat:
15315
    case Hexagon::V6_vadduwsat:
15316
    case Hexagon::V6_vaddw:
15317
    case Hexagon::V6_vaddwsat:
15318
    case Hexagon::V6_vand:
15319
    case Hexagon::V6_vaslhv:
15320
    case Hexagon::V6_vaslwv:
15321
    case Hexagon::V6_vasrhv:
15322
    case Hexagon::V6_vasrwv:
15323
    case Hexagon::V6_vavgb:
15324
    case Hexagon::V6_vavgbrnd:
15325
    case Hexagon::V6_vavgh:
15326
    case Hexagon::V6_vavghrnd:
15327
    case Hexagon::V6_vavgub:
15328
    case Hexagon::V6_vavgubrnd:
15329
    case Hexagon::V6_vavguh:
15330
    case Hexagon::V6_vavguhrnd:
15331
    case Hexagon::V6_vavguw:
15332
    case Hexagon::V6_vavguwrnd:
15333
    case Hexagon::V6_vavgw:
15334
    case Hexagon::V6_vavgwrnd:
15335
    case Hexagon::V6_vcvt_b_hf:
15336
    case Hexagon::V6_vcvt_bf_sf:
15337
    case Hexagon::V6_vcvt_hf_sf:
15338
    case Hexagon::V6_vcvt_ub_hf:
15339
    case Hexagon::V6_vdealb4w:
15340
    case Hexagon::V6_vdelta:
15341
    case Hexagon::V6_vdmpy_sf_hf:
15342
    case Hexagon::V6_vdmpyhvsat:
15343
    case Hexagon::V6_vfmax_hf:
15344
    case Hexagon::V6_vfmax_sf:
15345
    case Hexagon::V6_vfmin_hf:
15346
    case Hexagon::V6_vfmin_sf:
15347
    case Hexagon::V6_vlsrhv:
15348
    case Hexagon::V6_vlsrwv:
15349
    case Hexagon::V6_vmax_bf:
15350
    case Hexagon::V6_vmax_hf:
15351
    case Hexagon::V6_vmax_sf:
15352
    case Hexagon::V6_vmaxb:
15353
    case Hexagon::V6_vmaxh:
15354
    case Hexagon::V6_vmaxub:
15355
    case Hexagon::V6_vmaxuh:
15356
    case Hexagon::V6_vmaxw:
15357
    case Hexagon::V6_vmin_bf:
15358
    case Hexagon::V6_vmin_hf:
15359
    case Hexagon::V6_vmin_sf:
15360
    case Hexagon::V6_vminb:
15361
    case Hexagon::V6_vminh:
15362
    case Hexagon::V6_vminub:
15363
    case Hexagon::V6_vminuh:
15364
    case Hexagon::V6_vminw:
15365
    case Hexagon::V6_vmpy_hf_hf:
15366
    case Hexagon::V6_vmpy_qf16:
15367
    case Hexagon::V6_vmpy_qf16_hf:
15368
    case Hexagon::V6_vmpy_qf16_mix_hf:
15369
    case Hexagon::V6_vmpy_qf32:
15370
    case Hexagon::V6_vmpy_qf32_sf:
15371
    case Hexagon::V6_vmpy_sf_sf:
15372
    case Hexagon::V6_vmpyewuh:
15373
    case Hexagon::V6_vmpyhvsrs:
15374
    case Hexagon::V6_vmpyieoh:
15375
    case Hexagon::V6_vmpyiewuh:
15376
    case Hexagon::V6_vmpyih:
15377
    case Hexagon::V6_vmpyiowh:
15378
    case Hexagon::V6_vmpyowh:
15379
    case Hexagon::V6_vmpyowh_rnd:
15380
    case Hexagon::V6_vmpyuhvs:
15381
    case Hexagon::V6_vnavgb:
15382
    case Hexagon::V6_vnavgh:
15383
    case Hexagon::V6_vnavgub:
15384
    case Hexagon::V6_vnavgw:
15385
    case Hexagon::V6_vor:
15386
    case Hexagon::V6_vpackeb:
15387
    case Hexagon::V6_vpackeh:
15388
    case Hexagon::V6_vpackhb_sat:
15389
    case Hexagon::V6_vpackhub_sat:
15390
    case Hexagon::V6_vpackob:
15391
    case Hexagon::V6_vpackoh:
15392
    case Hexagon::V6_vpackwh_sat:
15393
    case Hexagon::V6_vpackwuh_sat:
15394
    case Hexagon::V6_vrdelta:
15395
    case Hexagon::V6_vrmpybusv:
15396
    case Hexagon::V6_vrmpybv:
15397
    case Hexagon::V6_vrmpyubv:
15398
    case Hexagon::V6_vrotr:
15399
    case Hexagon::V6_vroundhb:
15400
    case Hexagon::V6_vroundhub:
15401
    case Hexagon::V6_vrounduhub:
15402
    case Hexagon::V6_vrounduwuh:
15403
    case Hexagon::V6_vroundwh:
15404
    case Hexagon::V6_vroundwuh:
15405
    case Hexagon::V6_vsatdw:
15406
    case Hexagon::V6_vsathub:
15407
    case Hexagon::V6_vsatuwuh:
15408
    case Hexagon::V6_vsatwh:
15409
    case Hexagon::V6_vshufeh:
15410
    case Hexagon::V6_vshuffeb:
15411
    case Hexagon::V6_vshuffob:
15412
    case Hexagon::V6_vshufoh:
15413
    case Hexagon::V6_vsub_hf:
15414
    case Hexagon::V6_vsub_hf_hf:
15415
    case Hexagon::V6_vsub_qf16:
15416
    case Hexagon::V6_vsub_qf16_mix:
15417
    case Hexagon::V6_vsub_qf32:
15418
    case Hexagon::V6_vsub_qf32_mix:
15419
    case Hexagon::V6_vsub_sf:
15420
    case Hexagon::V6_vsub_sf_sf:
15421
    case Hexagon::V6_vsubb:
15422
    case Hexagon::V6_vsubbsat:
15423
    case Hexagon::V6_vsubh:
15424
    case Hexagon::V6_vsubhsat:
15425
    case Hexagon::V6_vsububsat:
15426
    case Hexagon::V6_vsubububb_sat:
15427
    case Hexagon::V6_vsubuhsat:
15428
    case Hexagon::V6_vsubuwsat:
15429
    case Hexagon::V6_vsubw:
15430
    case Hexagon::V6_vsubwsat:
15431
    case Hexagon::V6_vxor: {
15432
      switch (OpNum) {
15433
      case 1:
15434
        // op: Vu32
15435
        return 8;
15436
      case 2:
15437
        // op: Vv32
15438
        return 16;
15439
      case 0:
15440
        // op: Vd32
15441
        return 0;
15442
      }
15443
      break;
15444
    }
15445
    case Hexagon::V6_vadd_sf_bf:
15446
    case Hexagon::V6_vadd_sf_hf:
15447
    case Hexagon::V6_vaddhw:
15448
    case Hexagon::V6_vaddubh:
15449
    case Hexagon::V6_vadduhw:
15450
    case Hexagon::V6_vcombine:
15451
    case Hexagon::V6_vcombine_tmp:
15452
    case Hexagon::V6_vmpy_qf32_hf:
15453
    case Hexagon::V6_vmpy_qf32_mix_hf:
15454
    case Hexagon::V6_vmpy_qf32_qf16:
15455
    case Hexagon::V6_vmpy_sf_bf:
15456
    case Hexagon::V6_vmpy_sf_hf:
15457
    case Hexagon::V6_vmpybusv:
15458
    case Hexagon::V6_vmpybv:
15459
    case Hexagon::V6_vmpyewuh_64:
15460
    case Hexagon::V6_vmpyhus:
15461
    case Hexagon::V6_vmpyhv:
15462
    case Hexagon::V6_vmpyubv:
15463
    case Hexagon::V6_vmpyuhv:
15464
    case Hexagon::V6_vshufoeb:
15465
    case Hexagon::V6_vshufoeh:
15466
    case Hexagon::V6_vsub_sf_bf:
15467
    case Hexagon::V6_vsub_sf_hf:
15468
    case Hexagon::V6_vsubhw:
15469
    case Hexagon::V6_vsububh:
15470
    case Hexagon::V6_vsubuhw: {
15471
      switch (OpNum) {
15472
      case 1:
15473
        // op: Vu32
15474
        return 8;
15475
      case 2:
15476
        // op: Vv32
15477
        return 16;
15478
      case 0:
15479
        // op: Vdd32
15480
        return 0;
15481
      }
15482
      break;
15483
    }
15484
    case Hexagon::V6_vaddcarrysat: {
15485
      switch (OpNum) {
15486
      case 1:
15487
        // op: Vu32
15488
        return 8;
15489
      case 2:
15490
        // op: Vv32
15491
        return 16;
15492
      case 3:
15493
        // op: Qs4
15494
        return 5;
15495
      case 0:
15496
        // op: Vd32
15497
        return 0;
15498
      }
15499
      break;
15500
    }
15501
    case Hexagon::V6_valignb:
15502
    case Hexagon::V6_vasrhbrndsat:
15503
    case Hexagon::V6_vasrhbsat:
15504
    case Hexagon::V6_vasrhubrndsat:
15505
    case Hexagon::V6_vasrhubsat:
15506
    case Hexagon::V6_vasruhubrndsat:
15507
    case Hexagon::V6_vasruhubsat:
15508
    case Hexagon::V6_vasruwuhrndsat:
15509
    case Hexagon::V6_vasruwuhsat:
15510
    case Hexagon::V6_vasrwh:
15511
    case Hexagon::V6_vasrwhrndsat:
15512
    case Hexagon::V6_vasrwhsat:
15513
    case Hexagon::V6_vasrwuhrndsat:
15514
    case Hexagon::V6_vasrwuhsat:
15515
    case Hexagon::V6_vlalignb:
15516
    case Hexagon::V6_vlutvvb:
15517
    case Hexagon::V6_vlutvvb_nm: {
15518
      switch (OpNum) {
15519
      case 1:
15520
        // op: Vu32
15521
        return 8;
15522
      case 2:
15523
        // op: Vv32
15524
        return 19;
15525
      case 3:
15526
        // op: Rt8
15527
        return 16;
15528
      case 0:
15529
        // op: Vd32
15530
        return 0;
15531
      }
15532
      break;
15533
    }
15534
    case Hexagon::V6_vdealvdd:
15535
    case Hexagon::V6_vlutvwh:
15536
    case Hexagon::V6_vlutvwh_nm:
15537
    case Hexagon::V6_vshuffvdd: {
15538
      switch (OpNum) {
15539
      case 1:
15540
        // op: Vu32
15541
        return 8;
15542
      case 2:
15543
        // op: Vv32
15544
        return 19;
15545
      case 3:
15546
        // op: Rt8
15547
        return 16;
15548
      case 0:
15549
        // op: Vdd32
15550
        return 0;
15551
      }
15552
      break;
15553
    }
15554
    case Hexagon::V6_vconv_hf_qf32: {
15555
      switch (OpNum) {
15556
      case 1:
15557
        // op: Vuu32
15558
        return 8;
15559
      case 0:
15560
        // op: Vd32
15561
        return 0;
15562
      }
15563
      break;
15564
    }
15565
    case Hexagon::V6_vdmpyhisat:
15566
    case Hexagon::V6_vdmpyhsuisat: {
15567
      switch (OpNum) {
15568
      case 1:
15569
        // op: Vuu32
15570
        return 8;
15571
      case 2:
15572
        // op: Rt32
15573
        return 16;
15574
      case 0:
15575
        // op: Vd32
15576
        return 0;
15577
      }
15578
      break;
15579
    }
15580
    case Hexagon::V6_vdmpybus_dv:
15581
    case Hexagon::V6_vdmpyhb_dv:
15582
    case Hexagon::V6_vdsaduh:
15583
    case Hexagon::V6_vmpabus:
15584
    case Hexagon::V6_vmpabuu:
15585
    case Hexagon::V6_vmpahb:
15586
    case Hexagon::V6_vmpauhb:
15587
    case Hexagon::V6_vtmpyb:
15588
    case Hexagon::V6_vtmpybus:
15589
    case Hexagon::V6_vtmpyhb: {
15590
      switch (OpNum) {
15591
      case 1:
15592
        // op: Vuu32
15593
        return 8;
15594
      case 2:
15595
        // op: Rt32
15596
        return 16;
15597
      case 0:
15598
        // op: Vdd32
15599
        return 0;
15600
      }
15601
      break;
15602
    }
15603
    case Hexagon::V6_vasrvuhubrndsat:
15604
    case Hexagon::V6_vasrvuhubsat:
15605
    case Hexagon::V6_vasrvwuhrndsat:
15606
    case Hexagon::V6_vasrvwuhsat: {
15607
      switch (OpNum) {
15608
      case 1:
15609
        // op: Vuu32
15610
        return 8;
15611
      case 2:
15612
        // op: Vv32
15613
        return 16;
15614
      case 0:
15615
        // op: Vd32
15616
        return 0;
15617
      }
15618
      break;
15619
    }
15620
    case Hexagon::V6_vaddb_dv:
15621
    case Hexagon::V6_vaddbsat_dv:
15622
    case Hexagon::V6_vaddh_dv:
15623
    case Hexagon::V6_vaddhsat_dv:
15624
    case Hexagon::V6_vaddubsat_dv:
15625
    case Hexagon::V6_vadduhsat_dv:
15626
    case Hexagon::V6_vadduwsat_dv:
15627
    case Hexagon::V6_vaddw_dv:
15628
    case Hexagon::V6_vaddwsat_dv:
15629
    case Hexagon::V6_vmpabusv:
15630
    case Hexagon::V6_vmpabuuv:
15631
    case Hexagon::V6_vsubb_dv:
15632
    case Hexagon::V6_vsubbsat_dv:
15633
    case Hexagon::V6_vsubh_dv:
15634
    case Hexagon::V6_vsubhsat_dv:
15635
    case Hexagon::V6_vsububsat_dv:
15636
    case Hexagon::V6_vsubuhsat_dv:
15637
    case Hexagon::V6_vsubuwsat_dv:
15638
    case Hexagon::V6_vsubw_dv:
15639
    case Hexagon::V6_vsubwsat_dv: {
15640
      switch (OpNum) {
15641
      case 1:
15642
        // op: Vuu32
15643
        return 8;
15644
      case 2:
15645
        // op: Vvv32
15646
        return 16;
15647
      case 0:
15648
        // op: Vdd32
15649
        return 0;
15650
      }
15651
      break;
15652
    }
15653
    case Hexagon::L4_loadbsw2_ap:
15654
    case Hexagon::L4_loadbzw2_ap:
15655
    case Hexagon::L4_loadrb_ap:
15656
    case Hexagon::L4_loadrh_ap:
15657
    case Hexagon::L4_loadri_ap:
15658
    case Hexagon::L4_loadrub_ap:
15659
    case Hexagon::L4_loadruh_ap: {
15660
      switch (OpNum) {
15661
      case 2:
15662
        // op: II
15663
        return 5;
15664
      case 0:
15665
        // op: Rd32
15666
        return 0;
15667
      case 1:
15668
        // op: Re32
15669
        return 16;
15670
      }
15671
      break;
15672
    }
15673
    case Hexagon::L4_loadbsw4_ap:
15674
    case Hexagon::L4_loadbzw4_ap:
15675
    case Hexagon::L4_loadrd_ap: {
15676
      switch (OpNum) {
15677
      case 2:
15678
        // op: II
15679
        return 5;
15680
      case 0:
15681
        // op: Rdd32
15682
        return 0;
15683
      case 1:
15684
        // op: Re32
15685
        return 16;
15686
      }
15687
      break;
15688
    }
15689
    case Hexagon::A2_tfrih:
15690
    case Hexagon::A2_tfril:
15691
    case Hexagon::S2_allocframe: {
15692
      switch (OpNum) {
15693
      case 2:
15694
        // op: Ii
15695
        return 0;
15696
      case 0:
15697
        // op: Rx32
15698
        return 16;
15699
      }
15700
      break;
15701
    }
15702
    case Hexagon::J4_cmpeq_f_jumpnv_nt:
15703
    case Hexagon::J4_cmpeq_f_jumpnv_t:
15704
    case Hexagon::J4_cmpeq_t_jumpnv_nt:
15705
    case Hexagon::J4_cmpeq_t_jumpnv_t:
15706
    case Hexagon::J4_cmpgt_f_jumpnv_nt:
15707
    case Hexagon::J4_cmpgt_f_jumpnv_t:
15708
    case Hexagon::J4_cmpgt_t_jumpnv_nt:
15709
    case Hexagon::J4_cmpgt_t_jumpnv_t:
15710
    case Hexagon::J4_cmpgtu_f_jumpnv_nt:
15711
    case Hexagon::J4_cmpgtu_f_jumpnv_t:
15712
    case Hexagon::J4_cmpgtu_t_jumpnv_nt:
15713
    case Hexagon::J4_cmpgtu_t_jumpnv_t: {
15714
      switch (OpNum) {
15715
      case 2:
15716
        // op: Ii
15717
        return 1;
15718
      case 0:
15719
        // op: Ns8
15720
        return 16;
15721
      case 1:
15722
        // op: Rt32
15723
        return 8;
15724
      }
15725
      break;
15726
    }
15727
    case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
15728
    case Hexagon::J4_cmpeqn1_f_jumpnv_t:
15729
    case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
15730
    case Hexagon::J4_cmpeqn1_t_jumpnv_t:
15731
    case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
15732
    case Hexagon::J4_cmpgtn1_f_jumpnv_t:
15733
    case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
15734
    case Hexagon::J4_cmpgtn1_t_jumpnv_t: {
15735
      switch (OpNum) {
15736
      case 2:
15737
        // op: Ii
15738
        return 1;
15739
      case 0:
15740
        // op: Ns8
15741
        return 16;
15742
      }
15743
      break;
15744
    }
15745
    case Hexagon::J4_cmpeq_fp0_jump_nt:
15746
    case Hexagon::J4_cmpeq_fp0_jump_t:
15747
    case Hexagon::J4_cmpeq_fp1_jump_nt:
15748
    case Hexagon::J4_cmpeq_fp1_jump_t:
15749
    case Hexagon::J4_cmpeq_tp0_jump_nt:
15750
    case Hexagon::J4_cmpeq_tp0_jump_t:
15751
    case Hexagon::J4_cmpeq_tp1_jump_nt:
15752
    case Hexagon::J4_cmpeq_tp1_jump_t:
15753
    case Hexagon::J4_cmpgt_fp0_jump_nt:
15754
    case Hexagon::J4_cmpgt_fp0_jump_t:
15755
    case Hexagon::J4_cmpgt_fp1_jump_nt:
15756
    case Hexagon::J4_cmpgt_fp1_jump_t:
15757
    case Hexagon::J4_cmpgt_tp0_jump_nt:
15758
    case Hexagon::J4_cmpgt_tp0_jump_t:
15759
    case Hexagon::J4_cmpgt_tp1_jump_nt:
15760
    case Hexagon::J4_cmpgt_tp1_jump_t:
15761
    case Hexagon::J4_cmpgtu_fp0_jump_nt:
15762
    case Hexagon::J4_cmpgtu_fp0_jump_t:
15763
    case Hexagon::J4_cmpgtu_fp1_jump_nt:
15764
    case Hexagon::J4_cmpgtu_fp1_jump_t:
15765
    case Hexagon::J4_cmpgtu_tp0_jump_nt:
15766
    case Hexagon::J4_cmpgtu_tp0_jump_t:
15767
    case Hexagon::J4_cmpgtu_tp1_jump_nt:
15768
    case Hexagon::J4_cmpgtu_tp1_jump_t: {
15769
      switch (OpNum) {
15770
      case 2:
15771
        // op: Ii
15772
        return 1;
15773
      case 0:
15774
        // op: Rs16
15775
        return 16;
15776
      case 1:
15777
        // op: Rt16
15778
        return 8;
15779
      }
15780
      break;
15781
    }
15782
    case Hexagon::J4_cmpeqn1_fp0_jump_nt:
15783
    case Hexagon::J4_cmpeqn1_fp0_jump_t:
15784
    case Hexagon::J4_cmpeqn1_fp1_jump_nt:
15785
    case Hexagon::J4_cmpeqn1_fp1_jump_t:
15786
    case Hexagon::J4_cmpeqn1_tp0_jump_nt:
15787
    case Hexagon::J4_cmpeqn1_tp0_jump_t:
15788
    case Hexagon::J4_cmpeqn1_tp1_jump_nt:
15789
    case Hexagon::J4_cmpeqn1_tp1_jump_t:
15790
    case Hexagon::J4_cmpgtn1_fp0_jump_nt:
15791
    case Hexagon::J4_cmpgtn1_fp0_jump_t:
15792
    case Hexagon::J4_cmpgtn1_fp1_jump_nt:
15793
    case Hexagon::J4_cmpgtn1_fp1_jump_t:
15794
    case Hexagon::J4_cmpgtn1_tp0_jump_nt:
15795
    case Hexagon::J4_cmpgtn1_tp0_jump_t:
15796
    case Hexagon::J4_cmpgtn1_tp1_jump_nt:
15797
    case Hexagon::J4_cmpgtn1_tp1_jump_t: {
15798
      switch (OpNum) {
15799
      case 2:
15800
        // op: Ii
15801
        return 1;
15802
      case 0:
15803
        // op: Rs16
15804
        return 16;
15805
      }
15806
      break;
15807
    }
15808
    case Hexagon::J4_cmplt_f_jumpnv_nt:
15809
    case Hexagon::J4_cmplt_f_jumpnv_t:
15810
    case Hexagon::J4_cmplt_t_jumpnv_nt:
15811
    case Hexagon::J4_cmplt_t_jumpnv_t:
15812
    case Hexagon::J4_cmpltu_f_jumpnv_nt:
15813
    case Hexagon::J4_cmpltu_f_jumpnv_t:
15814
    case Hexagon::J4_cmpltu_t_jumpnv_nt:
15815
    case Hexagon::J4_cmpltu_t_jumpnv_t: {
15816
      switch (OpNum) {
15817
      case 2:
15818
        // op: Ii
15819
        return 1;
15820
      case 0:
15821
        // op: Rt32
15822
        return 8;
15823
      case 1:
15824
        // op: Ns8
15825
        return 16;
15826
      }
15827
      break;
15828
    }
15829
    case Hexagon::J4_jumpsetr: {
15830
      switch (OpNum) {
15831
      case 2:
15832
        // op: Ii
15833
        return 1;
15834
      case 1:
15835
        // op: Rs16
15836
        return 16;
15837
      case 0:
15838
        // op: Rd16
15839
        return 8;
15840
      }
15841
      break;
15842
    }
15843
    case Hexagon::J2_trap1: {
15844
      switch (OpNum) {
15845
      case 2:
15846
        // op: Ii
15847
        return 2;
15848
      case 0:
15849
        // op: Rx32
15850
        return 16;
15851
      }
15852
      break;
15853
    }
15854
    case Hexagon::S2_pstorerbnewf_io:
15855
    case Hexagon::S2_pstorerbnewt_io:
15856
    case Hexagon::S2_pstorerhnewf_io:
15857
    case Hexagon::S2_pstorerhnewt_io:
15858
    case Hexagon::S2_pstorerinewf_io:
15859
    case Hexagon::S2_pstorerinewt_io:
15860
    case Hexagon::S4_pstorerbnewfnew_io:
15861
    case Hexagon::S4_pstorerbnewtnew_io:
15862
    case Hexagon::S4_pstorerhnewfnew_io:
15863
    case Hexagon::S4_pstorerhnewtnew_io:
15864
    case Hexagon::S4_pstorerinewfnew_io:
15865
    case Hexagon::S4_pstorerinewtnew_io: {
15866
      switch (OpNum) {
15867
      case 2:
15868
        // op: Ii
15869
        return 3;
15870
      case 0:
15871
        // op: Pv4
15872
        return 0;
15873
      case 1:
15874
        // op: Rs32
15875
        return 16;
15876
      case 3:
15877
        // op: Nt8
15878
        return 8;
15879
      }
15880
      break;
15881
    }
15882
    case Hexagon::S2_pstorerbf_io:
15883
    case Hexagon::S2_pstorerbt_io:
15884
    case Hexagon::S2_pstorerff_io:
15885
    case Hexagon::S2_pstorerft_io:
15886
    case Hexagon::S2_pstorerhf_io:
15887
    case Hexagon::S2_pstorerht_io:
15888
    case Hexagon::S2_pstorerif_io:
15889
    case Hexagon::S2_pstorerit_io:
15890
    case Hexagon::S4_pstorerbfnew_io:
15891
    case Hexagon::S4_pstorerbtnew_io:
15892
    case Hexagon::S4_pstorerffnew_io:
15893
    case Hexagon::S4_pstorerftnew_io:
15894
    case Hexagon::S4_pstorerhfnew_io:
15895
    case Hexagon::S4_pstorerhtnew_io:
15896
    case Hexagon::S4_pstorerifnew_io:
15897
    case Hexagon::S4_pstoreritnew_io: {
15898
      switch (OpNum) {
15899
      case 2:
15900
        // op: Ii
15901
        return 3;
15902
      case 0:
15903
        // op: Pv4
15904
        return 0;
15905
      case 1:
15906
        // op: Rs32
15907
        return 16;
15908
      case 3:
15909
        // op: Rt32
15910
        return 8;
15911
      }
15912
      break;
15913
    }
15914
    case Hexagon::S2_pstorerdf_io:
15915
    case Hexagon::S2_pstorerdt_io:
15916
    case Hexagon::S4_pstorerdfnew_io:
15917
    case Hexagon::S4_pstorerdtnew_io: {
15918
      switch (OpNum) {
15919
      case 2:
15920
        // op: Ii
15921
        return 3;
15922
      case 0:
15923
        // op: Pv4
15924
        return 0;
15925
      case 1:
15926
        // op: Rs32
15927
        return 16;
15928
      case 3:
15929
        // op: Rtt32
15930
        return 8;
15931
      }
15932
      break;
15933
    }
15934
    case Hexagon::S2_storerbnew_pci:
15935
    case Hexagon::S2_storerhnew_pci:
15936
    case Hexagon::S2_storerinew_pci: {
15937
      switch (OpNum) {
15938
      case 2:
15939
        // op: Ii
15940
        return 3;
15941
      case 3:
15942
        // op: Mu2
15943
        return 13;
15944
      case 4:
15945
        // op: Nt8
15946
        return 8;
15947
      case 0:
15948
        // op: Rx32
15949
        return 16;
15950
      }
15951
      break;
15952
    }
15953
    case Hexagon::S2_storerb_pci:
15954
    case Hexagon::S2_storerf_pci:
15955
    case Hexagon::S2_storerh_pci:
15956
    case Hexagon::S2_storeri_pci: {
15957
      switch (OpNum) {
15958
      case 2:
15959
        // op: Ii
15960
        return 3;
15961
      case 3:
15962
        // op: Mu2
15963
        return 13;
15964
      case 4:
15965
        // op: Rt32
15966
        return 8;
15967
      case 0:
15968
        // op: Rx32
15969
        return 16;
15970
      }
15971
      break;
15972
    }
15973
    case Hexagon::S2_storerd_pci: {
15974
      switch (OpNum) {
15975
      case 2:
15976
        // op: Ii
15977
        return 3;
15978
      case 3:
15979
        // op: Mu2
15980
        return 13;
15981
      case 4:
15982
        // op: Rtt32
15983
        return 8;
15984
      case 0:
15985
        // op: Rx32
15986
        return 16;
15987
      }
15988
      break;
15989
    }
15990
    case Hexagon::S2_storerbnew_pi:
15991
    case Hexagon::S2_storerhnew_pi:
15992
    case Hexagon::S2_storerinew_pi: {
15993
      switch (OpNum) {
15994
      case 2:
15995
        // op: Ii
15996
        return 3;
15997
      case 3:
15998
        // op: Nt8
15999
        return 8;
16000
      case 0:
16001
        // op: Rx32
16002
        return 16;
16003
      }
16004
      break;
16005
    }
16006
    case Hexagon::S2_storerb_pi:
16007
    case Hexagon::S2_storerf_pi:
16008
    case Hexagon::S2_storerh_pi:
16009
    case Hexagon::S2_storeri_pi: {
16010
      switch (OpNum) {
16011
      case 2:
16012
        // op: Ii
16013
        return 3;
16014
      case 3:
16015
        // op: Rt32
16016
        return 8;
16017
      case 0:
16018
        // op: Rx32
16019
        return 16;
16020
      }
16021
      break;
16022
    }
16023
    case Hexagon::S2_storerd_pi: {
16024
      switch (OpNum) {
16025
      case 2:
16026
        // op: Ii
16027
        return 3;
16028
      case 3:
16029
        // op: Rtt32
16030
        return 8;
16031
      case 0:
16032
        // op: Rx32
16033
        return 16;
16034
      }
16035
      break;
16036
    }
16037
    case Hexagon::SA1_addi: {
16038
      switch (OpNum) {
16039
      case 2:
16040
        // op: Ii
16041
        return 4;
16042
      case 0:
16043
        // op: Rx16
16044
        return 0;
16045
      }
16046
      break;
16047
    }
16048
    case Hexagon::C2_cmoveif:
16049
    case Hexagon::C2_cmoveit:
16050
    case Hexagon::C2_cmovenewif:
16051
    case Hexagon::C2_cmovenewit: {
16052
      switch (OpNum) {
16053
      case 2:
16054
        // op: Ii
16055
        return 5;
16056
      case 1:
16057
        // op: Pu4
16058
        return 21;
16059
      case 0:
16060
        // op: Rd32
16061
        return 0;
16062
      }
16063
      break;
16064
    }
16065
    case Hexagon::C2_muxri: {
16066
      switch (OpNum) {
16067
      case 2:
16068
        // op: Ii
16069
        return 5;
16070
      case 1:
16071
        // op: Pu4
16072
        return 21;
16073
      case 3:
16074
        // op: Rs32
16075
        return 16;
16076
      case 0:
16077
        // op: Rd32
16078
        return 0;
16079
      }
16080
      break;
16081
    }
16082
    case Hexagon::A4_cmpbeqi:
16083
    case Hexagon::A4_cmpbgti:
16084
    case Hexagon::A4_cmpbgtui:
16085
    case Hexagon::A4_cmpheqi:
16086
    case Hexagon::A4_cmphgti:
16087
    case Hexagon::A4_cmphgtui:
16088
    case Hexagon::C2_cmpeqi:
16089
    case Hexagon::C2_cmpgti:
16090
    case Hexagon::C2_cmpgtui:
16091
    case Hexagon::C4_cmpltei:
16092
    case Hexagon::C4_cmplteui:
16093
    case Hexagon::C4_cmpneqi: {
16094
      switch (OpNum) {
16095
      case 2:
16096
        // op: Ii
16097
        return 5;
16098
      case 1:
16099
        // op: Rs32
16100
        return 16;
16101
      case 0:
16102
        // op: Pd4
16103
        return 0;
16104
      }
16105
      break;
16106
    }
16107
    case Hexagon::A2_addi:
16108
    case Hexagon::A2_andir:
16109
    case Hexagon::A2_orir:
16110
    case Hexagon::A4_rcmpeqi:
16111
    case Hexagon::A4_rcmpneqi:
16112
    case Hexagon::L2_loadbsw2_io:
16113
    case Hexagon::L2_loadbzw2_io:
16114
    case Hexagon::L2_loadrb_io:
16115
    case Hexagon::L2_loadrh_io:
16116
    case Hexagon::L2_loadri_io:
16117
    case Hexagon::L2_loadrub_io:
16118
    case Hexagon::L2_loadruh_io:
16119
    case Hexagon::M2_mpysin:
16120
    case Hexagon::M2_mpysip: {
16121
      switch (OpNum) {
16122
      case 2:
16123
        // op: Ii
16124
        return 5;
16125
      case 1:
16126
        // op: Rs32
16127
        return 16;
16128
      case 0:
16129
        // op: Rd32
16130
        return 0;
16131
      }
16132
      break;
16133
    }
16134
    case Hexagon::A4_combineri:
16135
    case Hexagon::L2_loadbsw4_io:
16136
    case Hexagon::L2_loadbzw4_io:
16137
    case Hexagon::L2_loadrd_io: {
16138
      switch (OpNum) {
16139
      case 2:
16140
        // op: Ii
16141
        return 5;
16142
      case 1:
16143
        // op: Rs32
16144
        return 16;
16145
      case 0:
16146
        // op: Rdd32
16147
        return 0;
16148
      }
16149
      break;
16150
    }
16151
    case Hexagon::S4_subaddi: {
16152
      switch (OpNum) {
16153
      case 2:
16154
        // op: Ii
16155
        return 5;
16156
      case 1:
16157
        // op: Rs32
16158
        return 16;
16159
      case 3:
16160
        // op: Ru32
16161
        return 0;
16162
      case 0:
16163
        // op: Rd32
16164
        return 8;
16165
      }
16166
      break;
16167
    }
16168
    case Hexagon::A4_vcmpbeqi:
16169
    case Hexagon::A4_vcmpbgti:
16170
    case Hexagon::A4_vcmpbgtui:
16171
    case Hexagon::A4_vcmpheqi:
16172
    case Hexagon::A4_vcmphgti:
16173
    case Hexagon::A4_vcmphgtui:
16174
    case Hexagon::A4_vcmpweqi:
16175
    case Hexagon::A4_vcmpwgti:
16176
    case Hexagon::A4_vcmpwgtui:
16177
    case Hexagon::F2_dfclass: {
16178
      switch (OpNum) {
16179
      case 2:
16180
        // op: Ii
16181
        return 5;
16182
      case 1:
16183
        // op: Rss32
16184
        return 16;
16185
      case 0:
16186
        // op: Pd4
16187
        return 0;
16188
      }
16189
      break;
16190
    }
16191
    case Hexagon::M4_mpyri_addr_u2: {
16192
      switch (OpNum) {
16193
      case 2:
16194
        // op: Ii
16195
        return 5;
16196
      case 1:
16197
        // op: Ru32
16198
        return 0;
16199
      case 3:
16200
        // op: Rs32
16201
        return 16;
16202
      case 0:
16203
        // op: Rd32
16204
        return 8;
16205
      }
16206
      break;
16207
    }
16208
    case Hexagon::C2_muxii: {
16209
      switch (OpNum) {
16210
      case 2:
16211
        // op: Ii
16212
        return 5;
16213
      case 3:
16214
        // op: II
16215
        return 13;
16216
      case 1:
16217
        // op: Pu4
16218
        return 23;
16219
      case 0:
16220
        // op: Rd32
16221
        return 0;
16222
      }
16223
      break;
16224
    }
16225
    case Hexagon::S4_storerbnew_rr:
16226
    case Hexagon::S4_storerhnew_rr:
16227
    case Hexagon::S4_storerinew_rr: {
16228
      switch (OpNum) {
16229
      case 2:
16230
        // op: Ii
16231
        return 7;
16232
      case 0:
16233
        // op: Rs32
16234
        return 16;
16235
      case 1:
16236
        // op: Ru32
16237
        return 8;
16238
      case 3:
16239
        // op: Nt8
16240
        return 0;
16241
      }
16242
      break;
16243
    }
16244
    case Hexagon::S4_storerb_rr:
16245
    case Hexagon::S4_storerf_rr:
16246
    case Hexagon::S4_storerh_rr:
16247
    case Hexagon::S4_storeri_rr: {
16248
      switch (OpNum) {
16249
      case 2:
16250
        // op: Ii
16251
        return 7;
16252
      case 0:
16253
        // op: Rs32
16254
        return 16;
16255
      case 1:
16256
        // op: Ru32
16257
        return 8;
16258
      case 3:
16259
        // op: Rt32
16260
        return 0;
16261
      }
16262
      break;
16263
    }
16264
    case Hexagon::S4_storerd_rr: {
16265
      switch (OpNum) {
16266
      case 2:
16267
        // op: Ii
16268
        return 7;
16269
      case 0:
16270
        // op: Rs32
16271
        return 16;
16272
      case 1:
16273
        // op: Ru32
16274
        return 8;
16275
      case 3:
16276
        // op: Rtt32
16277
        return 0;
16278
      }
16279
      break;
16280
    }
16281
    case Hexagon::S4_storeirbf_io:
16282
    case Hexagon::S4_storeirbfnew_io:
16283
    case Hexagon::S4_storeirbt_io:
16284
    case Hexagon::S4_storeirbtnew_io:
16285
    case Hexagon::S4_storeirhf_io:
16286
    case Hexagon::S4_storeirhfnew_io:
16287
    case Hexagon::S4_storeirht_io:
16288
    case Hexagon::S4_storeirhtnew_io:
16289
    case Hexagon::S4_storeirif_io:
16290
    case Hexagon::S4_storeirifnew_io:
16291
    case Hexagon::S4_storeirit_io:
16292
    case Hexagon::S4_storeiritnew_io: {
16293
      switch (OpNum) {
16294
      case 2:
16295
        // op: Ii
16296
        return 7;
16297
      case 3:
16298
        // op: II
16299
        return 0;
16300
      case 0:
16301
        // op: Pv4
16302
        return 5;
16303
      case 1:
16304
        // op: Rs32
16305
        return 16;
16306
      }
16307
      break;
16308
    }
16309
    case Hexagon::L4_loadbsw2_ur:
16310
    case Hexagon::L4_loadbzw2_ur:
16311
    case Hexagon::L4_loadrb_ur:
16312
    case Hexagon::L4_loadrh_ur:
16313
    case Hexagon::L4_loadri_ur:
16314
    case Hexagon::L4_loadrub_ur:
16315
    case Hexagon::L4_loadruh_ur: {
16316
      switch (OpNum) {
16317
      case 2:
16318
        // op: Ii
16319
        return 7;
16320
      case 3:
16321
        // op: II
16322
        return 5;
16323
      case 1:
16324
        // op: Rt32
16325
        return 16;
16326
      case 0:
16327
        // op: Rd32
16328
        return 0;
16329
      }
16330
      break;
16331
    }
16332
    case Hexagon::L4_loadbsw4_ur:
16333
    case Hexagon::L4_loadbzw4_ur:
16334
    case Hexagon::L4_loadrd_ur: {
16335
      switch (OpNum) {
16336
      case 2:
16337
        // op: Ii
16338
        return 7;
16339
      case 3:
16340
        // op: II
16341
        return 5;
16342
      case 1:
16343
        // op: Rt32
16344
        return 16;
16345
      case 0:
16346
        // op: Rdd32
16347
        return 0;
16348
      }
16349
      break;
16350
    }
16351
    case Hexagon::V6_vS32b_new_npred_ai:
16352
    case Hexagon::V6_vS32b_new_pred_ai:
16353
    case Hexagon::V6_vS32b_nt_new_npred_ai:
16354
    case Hexagon::V6_vS32b_nt_new_pred_ai: {
16355
      switch (OpNum) {
16356
      case 2:
16357
        // op: Ii
16358
        return 8;
16359
      case 0:
16360
        // op: Pv4
16361
        return 11;
16362
      case 1:
16363
        // op: Rt32
16364
        return 16;
16365
      case 3:
16366
        // op: Os8
16367
        return 0;
16368
      }
16369
      break;
16370
    }
16371
    case Hexagon::V6_vS32Ub_npred_ai:
16372
    case Hexagon::V6_vS32Ub_pred_ai:
16373
    case Hexagon::V6_vS32b_npred_ai:
16374
    case Hexagon::V6_vS32b_nt_npred_ai:
16375
    case Hexagon::V6_vS32b_nt_pred_ai:
16376
    case Hexagon::V6_vS32b_pred_ai: {
16377
      switch (OpNum) {
16378
      case 2:
16379
        // op: Ii
16380
        return 8;
16381
      case 0:
16382
        // op: Pv4
16383
        return 11;
16384
      case 1:
16385
        // op: Rt32
16386
        return 16;
16387
      case 3:
16388
        // op: Vs32
16389
        return 0;
16390
      }
16391
      break;
16392
    }
16393
    case Hexagon::V6_zLd_pred_ai: {
16394
      switch (OpNum) {
16395
      case 2:
16396
        // op: Ii
16397
        return 8;
16398
      case 0:
16399
        // op: Pv4
16400
        return 11;
16401
      case 1:
16402
        // op: Rt32
16403
        return 16;
16404
      }
16405
      break;
16406
    }
16407
    case Hexagon::V6_vS32b_nqpred_ai:
16408
    case Hexagon::V6_vS32b_nt_nqpred_ai:
16409
    case Hexagon::V6_vS32b_nt_qpred_ai:
16410
    case Hexagon::V6_vS32b_qpred_ai: {
16411
      switch (OpNum) {
16412
      case 2:
16413
        // op: Ii
16414
        return 8;
16415
      case 0:
16416
        // op: Qv4
16417
        return 11;
16418
      case 1:
16419
        // op: Rt32
16420
        return 16;
16421
      case 3:
16422
        // op: Vs32
16423
        return 0;
16424
      }
16425
      break;
16426
    }
16427
    case Hexagon::V6_vS32b_srls_pi:
16428
    case Hexagon::V6_zLd_pi: {
16429
      switch (OpNum) {
16430
      case 2:
16431
        // op: Ii
16432
        return 8;
16433
      case 0:
16434
        // op: Rx32
16435
        return 16;
16436
      }
16437
      break;
16438
    }
16439
    case Hexagon::L4_ploadrbf_abs:
16440
    case Hexagon::L4_ploadrbfnew_abs:
16441
    case Hexagon::L4_ploadrbt_abs:
16442
    case Hexagon::L4_ploadrbtnew_abs:
16443
    case Hexagon::L4_ploadrhf_abs:
16444
    case Hexagon::L4_ploadrhfnew_abs:
16445
    case Hexagon::L4_ploadrht_abs:
16446
    case Hexagon::L4_ploadrhtnew_abs:
16447
    case Hexagon::L4_ploadrif_abs:
16448
    case Hexagon::L4_ploadrifnew_abs:
16449
    case Hexagon::L4_ploadrit_abs:
16450
    case Hexagon::L4_ploadritnew_abs:
16451
    case Hexagon::L4_ploadrubf_abs:
16452
    case Hexagon::L4_ploadrubfnew_abs:
16453
    case Hexagon::L4_ploadrubt_abs:
16454
    case Hexagon::L4_ploadrubtnew_abs:
16455
    case Hexagon::L4_ploadruhf_abs:
16456
    case Hexagon::L4_ploadruhfnew_abs:
16457
    case Hexagon::L4_ploadruht_abs:
16458
    case Hexagon::L4_ploadruhtnew_abs: {
16459
      switch (OpNum) {
16460
      case 2:
16461
        // op: Ii
16462
        return 8;
16463
      case 1:
16464
        // op: Pt4
16465
        return 9;
16466
      case 0:
16467
        // op: Rd32
16468
        return 0;
16469
      }
16470
      break;
16471
    }
16472
    case Hexagon::L4_ploadrdf_abs:
16473
    case Hexagon::L4_ploadrdfnew_abs:
16474
    case Hexagon::L4_ploadrdt_abs:
16475
    case Hexagon::L4_ploadrdtnew_abs: {
16476
      switch (OpNum) {
16477
      case 2:
16478
        // op: Ii
16479
        return 8;
16480
      case 1:
16481
        // op: Pt4
16482
        return 9;
16483
      case 0:
16484
        // op: Rdd32
16485
        return 0;
16486
      }
16487
      break;
16488
    }
16489
    case Hexagon::SL1_loadri_io:
16490
    case Hexagon::SL1_loadrub_io:
16491
    case Hexagon::SL2_loadrb_io:
16492
    case Hexagon::SL2_loadrh_io:
16493
    case Hexagon::SL2_loadruh_io: {
16494
      switch (OpNum) {
16495
      case 2:
16496
        // op: Ii
16497
        return 8;
16498
      case 1:
16499
        // op: Rs16
16500
        return 4;
16501
      case 0:
16502
        // op: Rd16
16503
        return 0;
16504
      }
16505
      break;
16506
    }
16507
    case Hexagon::C2_bitsclri:
16508
    case Hexagon::C4_nbitsclri:
16509
    case Hexagon::F2_sfclass:
16510
    case Hexagon::S2_tstbit_i:
16511
    case Hexagon::S4_ntstbit_i: {
16512
      switch (OpNum) {
16513
      case 2:
16514
        // op: Ii
16515
        return 8;
16516
      case 1:
16517
        // op: Rs32
16518
        return 16;
16519
      case 0:
16520
        // op: Pd4
16521
        return 0;
16522
      }
16523
      break;
16524
    }
16525
    case Hexagon::A4_cround_ri:
16526
    case Hexagon::A4_round_ri:
16527
    case Hexagon::A4_round_ri_sat:
16528
    case Hexagon::A7_clip:
16529
    case Hexagon::S2_asl_i_r:
16530
    case Hexagon::S2_asl_i_r_sat:
16531
    case Hexagon::S2_asr_i_r:
16532
    case Hexagon::S2_asr_i_r_rnd:
16533
    case Hexagon::S2_clrbit_i:
16534
    case Hexagon::S2_lsr_i_r:
16535
    case Hexagon::S2_setbit_i:
16536
    case Hexagon::S2_togglebit_i:
16537
    case Hexagon::S4_clbaddi:
16538
    case Hexagon::S6_rol_i_r: {
16539
      switch (OpNum) {
16540
      case 2:
16541
        // op: Ii
16542
        return 8;
16543
      case 1:
16544
        // op: Rs32
16545
        return 16;
16546
      case 0:
16547
        // op: Rd32
16548
        return 0;
16549
      }
16550
      break;
16551
    }
16552
    case Hexagon::A4_bitspliti: {
16553
      switch (OpNum) {
16554
      case 2:
16555
        // op: Ii
16556
        return 8;
16557
      case 1:
16558
        // op: Rs32
16559
        return 16;
16560
      case 0:
16561
        // op: Rdd32
16562
        return 0;
16563
      }
16564
      break;
16565
    }
16566
    case Hexagon::S2_asr_i_svw_trun:
16567
    case Hexagon::S4_clbpaddi:
16568
    case Hexagon::S5_asrhub_rnd_sat:
16569
    case Hexagon::S5_asrhub_sat: {
16570
      switch (OpNum) {
16571
      case 2:
16572
        // op: Ii
16573
        return 8;
16574
      case 1:
16575
        // op: Rss32
16576
        return 16;
16577
      case 0:
16578
        // op: Rd32
16579
        return 0;
16580
      }
16581
      break;
16582
    }
16583
    case Hexagon::A7_croundd_ri:
16584
    case Hexagon::A7_vclip:
16585
    case Hexagon::S2_asl_i_p:
16586
    case Hexagon::S2_asl_i_vh:
16587
    case Hexagon::S2_asl_i_vw:
16588
    case Hexagon::S2_asr_i_p:
16589
    case Hexagon::S2_asr_i_p_rnd:
16590
    case Hexagon::S2_asr_i_vh:
16591
    case Hexagon::S2_asr_i_vw:
16592
    case Hexagon::S2_lsr_i_p:
16593
    case Hexagon::S2_lsr_i_vh:
16594
    case Hexagon::S2_lsr_i_vw:
16595
    case Hexagon::S5_vasrhrnd:
16596
    case Hexagon::S6_rol_i_p: {
16597
      switch (OpNum) {
16598
      case 2:
16599
        // op: Ii
16600
        return 8;
16601
      case 1:
16602
        // op: Rss32
16603
        return 16;
16604
      case 0:
16605
        // op: Rdd32
16606
        return 0;
16607
      }
16608
      break;
16609
    }
16610
    case Hexagon::V6_vL32Ub_ai:
16611
    case Hexagon::V6_vL32b_ai:
16612
    case Hexagon::V6_vL32b_cur_ai:
16613
    case Hexagon::V6_vL32b_nt_ai:
16614
    case Hexagon::V6_vL32b_nt_cur_ai:
16615
    case Hexagon::V6_vL32b_nt_tmp_ai:
16616
    case Hexagon::V6_vL32b_tmp_ai: {
16617
      switch (OpNum) {
16618
      case 2:
16619
        // op: Ii
16620
        return 8;
16621
      case 1:
16622
        // op: Rt32
16623
        return 16;
16624
      case 0:
16625
        // op: Vd32
16626
        return 0;
16627
      }
16628
      break;
16629
    }
16630
    case Hexagon::S2_extractu:
16631
    case Hexagon::S4_extract: {
16632
      switch (OpNum) {
16633
      case 2:
16634
        // op: Ii
16635
        return 8;
16636
      case 3:
16637
        // op: II
16638
        return 5;
16639
      case 1:
16640
        // op: Rs32
16641
        return 16;
16642
      case 0:
16643
        // op: Rd32
16644
        return 0;
16645
      }
16646
      break;
16647
    }
16648
    case Hexagon::S2_extractup:
16649
    case Hexagon::S4_extractp: {
16650
      switch (OpNum) {
16651
      case 2:
16652
        // op: Ii
16653
        return 8;
16654
      case 3:
16655
        // op: II
16656
        return 5;
16657
      case 1:
16658
        // op: Rss32
16659
        return 16;
16660
      case 0:
16661
        // op: Rdd32
16662
        return 0;
16663
      }
16664
      break;
16665
    }
16666
    case Hexagon::V6_vS32b_new_pi:
16667
    case Hexagon::V6_vS32b_nt_new_pi: {
16668
      switch (OpNum) {
16669
      case 2:
16670
        // op: Ii
16671
        return 8;
16672
      case 3:
16673
        // op: Os8
16674
        return 0;
16675
      case 0:
16676
        // op: Rx32
16677
        return 16;
16678
      }
16679
      break;
16680
    }
16681
    case Hexagon::V6_vS32Ub_pi:
16682
    case Hexagon::V6_vS32b_nt_pi:
16683
    case Hexagon::V6_vS32b_pi: {
16684
      switch (OpNum) {
16685
      case 2:
16686
        // op: Ii
16687
        return 8;
16688
      case 3:
16689
        // op: Vs32
16690
        return 0;
16691
      case 0:
16692
        // op: Rx32
16693
        return 16;
16694
      }
16695
      break;
16696
    }
16697
    case Hexagon::V6_vS32b_srls_ppu:
16698
    case Hexagon::V6_zLd_ppu: {
16699
      switch (OpNum) {
16700
      case 2:
16701
        // op: Mu2
16702
        return 13;
16703
      case 0:
16704
        // op: Rx32
16705
        return 16;
16706
      }
16707
      break;
16708
    }
16709
    case Hexagon::S2_storerbnew_pbr:
16710
    case Hexagon::S2_storerbnew_pcr:
16711
    case Hexagon::S2_storerbnew_pr:
16712
    case Hexagon::S2_storerhnew_pbr:
16713
    case Hexagon::S2_storerhnew_pcr:
16714
    case Hexagon::S2_storerhnew_pr:
16715
    case Hexagon::S2_storerinew_pbr:
16716
    case Hexagon::S2_storerinew_pcr:
16717
    case Hexagon::S2_storerinew_pr: {
16718
      switch (OpNum) {
16719
      case 2:
16720
        // op: Mu2
16721
        return 13;
16722
      case 3:
16723
        // op: Nt8
16724
        return 8;
16725
      case 0:
16726
        // op: Rx32
16727
        return 16;
16728
      }
16729
      break;
16730
    }
16731
    case Hexagon::V6_vS32b_new_ppu:
16732
    case Hexagon::V6_vS32b_nt_new_ppu: {
16733
      switch (OpNum) {
16734
      case 2:
16735
        // op: Mu2
16736
        return 13;
16737
      case 3:
16738
        // op: Os8
16739
        return 0;
16740
      case 0:
16741
        // op: Rx32
16742
        return 16;
16743
      }
16744
      break;
16745
    }
16746
    case Hexagon::S2_storerb_pbr:
16747
    case Hexagon::S2_storerb_pcr:
16748
    case Hexagon::S2_storerb_pr:
16749
    case Hexagon::S2_storerf_pbr:
16750
    case Hexagon::S2_storerf_pcr:
16751
    case Hexagon::S2_storerf_pr:
16752
    case Hexagon::S2_storerh_pbr:
16753
    case Hexagon::S2_storerh_pcr:
16754
    case Hexagon::S2_storerh_pr:
16755
    case Hexagon::S2_storeri_pbr:
16756
    case Hexagon::S2_storeri_pcr:
16757
    case Hexagon::S2_storeri_pr: {
16758
      switch (OpNum) {
16759
      case 2:
16760
        // op: Mu2
16761
        return 13;
16762
      case 3:
16763
        // op: Rt32
16764
        return 8;
16765
      case 0:
16766
        // op: Rx32
16767
        return 16;
16768
      }
16769
      break;
16770
    }
16771
    case Hexagon::S2_storerd_pbr:
16772
    case Hexagon::S2_storerd_pcr:
16773
    case Hexagon::S2_storerd_pr: {
16774
      switch (OpNum) {
16775
      case 2:
16776
        // op: Mu2
16777
        return 13;
16778
      case 3:
16779
        // op: Rtt32
16780
        return 8;
16781
      case 0:
16782
        // op: Rx32
16783
        return 16;
16784
      }
16785
      break;
16786
    }
16787
    case Hexagon::V6_vS32Ub_ppu:
16788
    case Hexagon::V6_vS32b_nt_ppu:
16789
    case Hexagon::V6_vS32b_ppu: {
16790
      switch (OpNum) {
16791
      case 2:
16792
        // op: Mu2
16793
        return 13;
16794
      case 3:
16795
        // op: Vs32
16796
        return 0;
16797
      case 0:
16798
        // op: Rx32
16799
        return 16;
16800
      }
16801
      break;
16802
    }
16803
    case Hexagon::V6_vL32b_cur_npred_ppu:
16804
    case Hexagon::V6_vL32b_cur_pred_ppu:
16805
    case Hexagon::V6_vL32b_npred_ppu:
16806
    case Hexagon::V6_vL32b_nt_cur_npred_ppu:
16807
    case Hexagon::V6_vL32b_nt_cur_pred_ppu:
16808
    case Hexagon::V6_vL32b_nt_npred_ppu:
16809
    case Hexagon::V6_vL32b_nt_pred_ppu:
16810
    case Hexagon::V6_vL32b_nt_tmp_npred_ppu:
16811
    case Hexagon::V6_vL32b_nt_tmp_pred_ppu:
16812
    case Hexagon::V6_vL32b_pred_ppu:
16813
    case Hexagon::V6_vL32b_tmp_npred_ppu:
16814
    case Hexagon::V6_vL32b_tmp_pred_ppu: {
16815
      switch (OpNum) {
16816
      case 2:
16817
        // op: Pv4
16818
        return 11;
16819
      case 4:
16820
        // op: Mu2
16821
        return 13;
16822
      case 0:
16823
        // op: Vd32
16824
        return 0;
16825
      case 1:
16826
        // op: Rx32
16827
        return 16;
16828
      }
16829
      break;
16830
    }
16831
    case Hexagon::V6_vandnqrt_acc:
16832
    case Hexagon::V6_vandqrt_acc: {
16833
      switch (OpNum) {
16834
      case 2:
16835
        // op: Qu4
16836
        return 8;
16837
      case 3:
16838
        // op: Rt32
16839
        return 16;
16840
      case 0:
16841
        // op: Vx32
16842
        return 0;
16843
      }
16844
      break;
16845
    }
16846
    case Hexagon::SA1_addrx: {
16847
      switch (OpNum) {
16848
      case 2:
16849
        // op: Rs16
16850
        return 4;
16851
      case 0:
16852
        // op: Rx16
16853
        return 0;
16854
      }
16855
      break;
16856
    }
16857
    case Hexagon::F2_sfinvsqrta: {
16858
      switch (OpNum) {
16859
      case 2:
16860
        // op: Rs32
16861
        return 16;
16862
      case 0:
16863
        // op: Rd32
16864
        return 0;
16865
      case 1:
16866
        // op: Pe4
16867
        return 5;
16868
      }
16869
      break;
16870
    }
16871
    case Hexagon::F2_sfrecipa: {
16872
      switch (OpNum) {
16873
      case 2:
16874
        // op: Rs32
16875
        return 16;
16876
      case 3:
16877
        // op: Rt32
16878
        return 8;
16879
      case 0:
16880
        // op: Rd32
16881
        return 0;
16882
      case 1:
16883
        // op: Pe4
16884
        return 5;
16885
      }
16886
      break;
16887
    }
16888
    case Hexagon::F2_sffma:
16889
    case Hexagon::F2_sffma_lib:
16890
    case Hexagon::F2_sffms:
16891
    case Hexagon::F2_sffms_lib:
16892
    case Hexagon::M2_acci:
16893
    case Hexagon::M2_maci:
16894
    case Hexagon::M2_mnaci:
16895
    case Hexagon::M2_mpy_acc_hh_s0:
16896
    case Hexagon::M2_mpy_acc_hh_s1:
16897
    case Hexagon::M2_mpy_acc_hl_s0:
16898
    case Hexagon::M2_mpy_acc_hl_s1:
16899
    case Hexagon::M2_mpy_acc_lh_s0:
16900
    case Hexagon::M2_mpy_acc_lh_s1:
16901
    case Hexagon::M2_mpy_acc_ll_s0:
16902
    case Hexagon::M2_mpy_acc_ll_s1:
16903
    case Hexagon::M2_mpy_acc_sat_hh_s0:
16904
    case Hexagon::M2_mpy_acc_sat_hh_s1:
16905
    case Hexagon::M2_mpy_acc_sat_hl_s0:
16906
    case Hexagon::M2_mpy_acc_sat_hl_s1:
16907
    case Hexagon::M2_mpy_acc_sat_lh_s0:
16908
    case Hexagon::M2_mpy_acc_sat_lh_s1:
16909
    case Hexagon::M2_mpy_acc_sat_ll_s0:
16910
    case Hexagon::M2_mpy_acc_sat_ll_s1:
16911
    case Hexagon::M2_mpy_nac_hh_s0:
16912
    case Hexagon::M2_mpy_nac_hh_s1:
16913
    case Hexagon::M2_mpy_nac_hl_s0:
16914
    case Hexagon::M2_mpy_nac_hl_s1:
16915
    case Hexagon::M2_mpy_nac_lh_s0:
16916
    case Hexagon::M2_mpy_nac_lh_s1:
16917
    case Hexagon::M2_mpy_nac_ll_s0:
16918
    case Hexagon::M2_mpy_nac_ll_s1:
16919
    case Hexagon::M2_mpy_nac_sat_hh_s0:
16920
    case Hexagon::M2_mpy_nac_sat_hh_s1:
16921
    case Hexagon::M2_mpy_nac_sat_hl_s0:
16922
    case Hexagon::M2_mpy_nac_sat_hl_s1:
16923
    case Hexagon::M2_mpy_nac_sat_lh_s0:
16924
    case Hexagon::M2_mpy_nac_sat_lh_s1:
16925
    case Hexagon::M2_mpy_nac_sat_ll_s0:
16926
    case Hexagon::M2_mpy_nac_sat_ll_s1:
16927
    case Hexagon::M2_mpyu_acc_hh_s0:
16928
    case Hexagon::M2_mpyu_acc_hh_s1:
16929
    case Hexagon::M2_mpyu_acc_hl_s0:
16930
    case Hexagon::M2_mpyu_acc_hl_s1:
16931
    case Hexagon::M2_mpyu_acc_lh_s0:
16932
    case Hexagon::M2_mpyu_acc_lh_s1:
16933
    case Hexagon::M2_mpyu_acc_ll_s0:
16934
    case Hexagon::M2_mpyu_acc_ll_s1:
16935
    case Hexagon::M2_mpyu_nac_hh_s0:
16936
    case Hexagon::M2_mpyu_nac_hh_s1:
16937
    case Hexagon::M2_mpyu_nac_hl_s0:
16938
    case Hexagon::M2_mpyu_nac_hl_s1:
16939
    case Hexagon::M2_mpyu_nac_lh_s0:
16940
    case Hexagon::M2_mpyu_nac_lh_s1:
16941
    case Hexagon::M2_mpyu_nac_ll_s0:
16942
    case Hexagon::M2_mpyu_nac_ll_s1:
16943
    case Hexagon::M2_nacci:
16944
    case Hexagon::M2_xor_xacc:
16945
    case Hexagon::M4_and_and:
16946
    case Hexagon::M4_and_andn:
16947
    case Hexagon::M4_and_or:
16948
    case Hexagon::M4_and_xor:
16949
    case Hexagon::M4_mac_up_s1_sat:
16950
    case Hexagon::M4_nac_up_s1_sat:
16951
    case Hexagon::M4_or_and:
16952
    case Hexagon::M4_or_andn:
16953
    case Hexagon::M4_or_or:
16954
    case Hexagon::M4_or_xor:
16955
    case Hexagon::M4_xor_and:
16956
    case Hexagon::M4_xor_andn:
16957
    case Hexagon::M4_xor_or:
16958
    case Hexagon::S2_asl_r_r_acc:
16959
    case Hexagon::S2_asl_r_r_and:
16960
    case Hexagon::S2_asl_r_r_nac:
16961
    case Hexagon::S2_asl_r_r_or:
16962
    case Hexagon::S2_asr_r_r_acc:
16963
    case Hexagon::S2_asr_r_r_and:
16964
    case Hexagon::S2_asr_r_r_nac:
16965
    case Hexagon::S2_asr_r_r_or:
16966
    case Hexagon::S2_lsl_r_r_acc:
16967
    case Hexagon::S2_lsl_r_r_and:
16968
    case Hexagon::S2_lsl_r_r_nac:
16969
    case Hexagon::S2_lsl_r_r_or:
16970
    case Hexagon::S2_lsr_r_r_acc:
16971
    case Hexagon::S2_lsr_r_r_and:
16972
    case Hexagon::S2_lsr_r_r_nac:
16973
    case Hexagon::S2_lsr_r_r_or: {
16974
      switch (OpNum) {
16975
      case 2:
16976
        // op: Rs32
16977
        return 16;
16978
      case 3:
16979
        // op: Rt32
16980
        return 8;
16981
      case 0:
16982
        // op: Rx32
16983
        return 0;
16984
      }
16985
      break;
16986
    }
16987
    case Hexagon::M2_cmaci_s0:
16988
    case Hexagon::M2_cmacr_s0:
16989
    case Hexagon::M2_cmacs_s0:
16990
    case Hexagon::M2_cmacs_s1:
16991
    case Hexagon::M2_cmacsc_s0:
16992
    case Hexagon::M2_cmacsc_s1:
16993
    case Hexagon::M2_cnacs_s0:
16994
    case Hexagon::M2_cnacs_s1:
16995
    case Hexagon::M2_cnacsc_s0:
16996
    case Hexagon::M2_cnacsc_s1:
16997
    case Hexagon::M2_dpmpyss_acc_s0:
16998
    case Hexagon::M2_dpmpyss_nac_s0:
16999
    case Hexagon::M2_dpmpyuu_acc_s0:
17000
    case Hexagon::M2_dpmpyuu_nac_s0:
17001
    case Hexagon::M2_mpyd_acc_hh_s0:
17002
    case Hexagon::M2_mpyd_acc_hh_s1:
17003
    case Hexagon::M2_mpyd_acc_hl_s0:
17004
    case Hexagon::M2_mpyd_acc_hl_s1:
17005
    case Hexagon::M2_mpyd_acc_lh_s0:
17006
    case Hexagon::M2_mpyd_acc_lh_s1:
17007
    case Hexagon::M2_mpyd_acc_ll_s0:
17008
    case Hexagon::M2_mpyd_acc_ll_s1:
17009
    case Hexagon::M2_mpyd_nac_hh_s0:
17010
    case Hexagon::M2_mpyd_nac_hh_s1:
17011
    case Hexagon::M2_mpyd_nac_hl_s0:
17012
    case Hexagon::M2_mpyd_nac_hl_s1:
17013
    case Hexagon::M2_mpyd_nac_lh_s0:
17014
    case Hexagon::M2_mpyd_nac_lh_s1:
17015
    case Hexagon::M2_mpyd_nac_ll_s0:
17016
    case Hexagon::M2_mpyd_nac_ll_s1:
17017
    case Hexagon::M2_mpyud_acc_hh_s0:
17018
    case Hexagon::M2_mpyud_acc_hh_s1:
17019
    case Hexagon::M2_mpyud_acc_hl_s0:
17020
    case Hexagon::M2_mpyud_acc_hl_s1:
17021
    case Hexagon::M2_mpyud_acc_lh_s0:
17022
    case Hexagon::M2_mpyud_acc_lh_s1:
17023
    case Hexagon::M2_mpyud_acc_ll_s0:
17024
    case Hexagon::M2_mpyud_acc_ll_s1:
17025
    case Hexagon::M2_mpyud_nac_hh_s0:
17026
    case Hexagon::M2_mpyud_nac_hh_s1:
17027
    case Hexagon::M2_mpyud_nac_hl_s0:
17028
    case Hexagon::M2_mpyud_nac_hl_s1:
17029
    case Hexagon::M2_mpyud_nac_lh_s0:
17030
    case Hexagon::M2_mpyud_nac_lh_s1:
17031
    case Hexagon::M2_mpyud_nac_ll_s0:
17032
    case Hexagon::M2_mpyud_nac_ll_s1:
17033
    case Hexagon::M2_vmac2:
17034
    case Hexagon::M2_vmac2s_s0:
17035
    case Hexagon::M2_vmac2s_s1:
17036
    case Hexagon::M2_vmac2su_s0:
17037
    case Hexagon::M2_vmac2su_s1:
17038
    case Hexagon::M4_pmpyw_acc:
17039
    case Hexagon::M4_vpmpyh_acc:
17040
    case Hexagon::M5_vmacbsu:
17041
    case Hexagon::M5_vmacbuu: {
17042
      switch (OpNum) {
17043
      case 2:
17044
        // op: Rs32
17045
        return 16;
17046
      case 3:
17047
        // op: Rt32
17048
        return 8;
17049
      case 0:
17050
        // op: Rxx32
17051
        return 0;
17052
      }
17053
      break;
17054
    }
17055
    case Hexagon::F2_sffma_sc: {
17056
      switch (OpNum) {
17057
      case 2:
17058
        // op: Rs32
17059
        return 16;
17060
      case 3:
17061
        // op: Rt32
17062
        return 8;
17063
      case 4:
17064
        // op: Pu4
17065
        return 5;
17066
      case 0:
17067
        // op: Rx32
17068
        return 0;
17069
      }
17070
      break;
17071
    }
17072
    case Hexagon::S2_insert_rp: {
17073
      switch (OpNum) {
17074
      case 2:
17075
        // op: Rs32
17076
        return 16;
17077
      case 3:
17078
        // op: Rtt32
17079
        return 8;
17080
      case 0:
17081
        // op: Rx32
17082
        return 0;
17083
      }
17084
      break;
17085
    }
17086
    case Hexagon::S2_asl_r_p_acc:
17087
    case Hexagon::S2_asl_r_p_and:
17088
    case Hexagon::S2_asl_r_p_nac:
17089
    case Hexagon::S2_asl_r_p_or:
17090
    case Hexagon::S2_asl_r_p_xor:
17091
    case Hexagon::S2_asr_r_p_acc:
17092
    case Hexagon::S2_asr_r_p_and:
17093
    case Hexagon::S2_asr_r_p_nac:
17094
    case Hexagon::S2_asr_r_p_or:
17095
    case Hexagon::S2_asr_r_p_xor:
17096
    case Hexagon::S2_lsl_r_p_acc:
17097
    case Hexagon::S2_lsl_r_p_and:
17098
    case Hexagon::S2_lsl_r_p_nac:
17099
    case Hexagon::S2_lsl_r_p_or:
17100
    case Hexagon::S2_lsl_r_p_xor:
17101
    case Hexagon::S2_lsr_r_p_acc:
17102
    case Hexagon::S2_lsr_r_p_and:
17103
    case Hexagon::S2_lsr_r_p_nac:
17104
    case Hexagon::S2_lsr_r_p_or:
17105
    case Hexagon::S2_lsr_r_p_xor:
17106
    case Hexagon::S2_vrcnegh: {
17107
      switch (OpNum) {
17108
      case 2:
17109
        // op: Rss32
17110
        return 16;
17111
      case 3:
17112
        // op: Rt32
17113
        return 8;
17114
      case 0:
17115
        // op: Rxx32
17116
        return 0;
17117
      }
17118
      break;
17119
    }
17120
    case Hexagon::A4_addp_c:
17121
    case Hexagon::A4_subp_c: {
17122
      switch (OpNum) {
17123
      case 2:
17124
        // op: Rss32
17125
        return 16;
17126
      case 3:
17127
        // op: Rtt32
17128
        return 8;
17129
      case 0:
17130
        // op: Rdd32
17131
        return 0;
17132
      case 1:
17133
        // op: Px4
17134
        return 5;
17135
      }
17136
      break;
17137
    }
17138
    case Hexagon::A2_vraddub_acc:
17139
    case Hexagon::A2_vrsadub_acc:
17140
    case Hexagon::F2_dfmpyhh:
17141
    case Hexagon::F2_dfmpylh:
17142
    case Hexagon::M2_mmachs_rs0:
17143
    case Hexagon::M2_mmachs_rs1:
17144
    case Hexagon::M2_mmachs_s0:
17145
    case Hexagon::M2_mmachs_s1:
17146
    case Hexagon::M2_mmacls_rs0:
17147
    case Hexagon::M2_mmacls_rs1:
17148
    case Hexagon::M2_mmacls_s0:
17149
    case Hexagon::M2_mmacls_s1:
17150
    case Hexagon::M2_mmacuhs_rs0:
17151
    case Hexagon::M2_mmacuhs_rs1:
17152
    case Hexagon::M2_mmacuhs_s0:
17153
    case Hexagon::M2_mmacuhs_s1:
17154
    case Hexagon::M2_mmaculs_rs0:
17155
    case Hexagon::M2_mmaculs_rs1:
17156
    case Hexagon::M2_mmaculs_s0:
17157
    case Hexagon::M2_mmaculs_s1:
17158
    case Hexagon::M2_vcmac_s0_sat_i:
17159
    case Hexagon::M2_vcmac_s0_sat_r:
17160
    case Hexagon::M2_vdmacs_s0:
17161
    case Hexagon::M2_vdmacs_s1:
17162
    case Hexagon::M2_vmac2es:
17163
    case Hexagon::M2_vmac2es_s0:
17164
    case Hexagon::M2_vmac2es_s1:
17165
    case Hexagon::M2_vrcmaci_s0:
17166
    case Hexagon::M2_vrcmaci_s0c:
17167
    case Hexagon::M2_vrcmacr_s0:
17168
    case Hexagon::M2_vrcmacr_s0c:
17169
    case Hexagon::M2_vrcmpys_acc_s1_h:
17170
    case Hexagon::M2_vrcmpys_acc_s1_l:
17171
    case Hexagon::M2_vrmac_s0:
17172
    case Hexagon::M4_vrmpyeh_acc_s0:
17173
    case Hexagon::M4_vrmpyeh_acc_s1:
17174
    case Hexagon::M4_vrmpyoh_acc_s0:
17175
    case Hexagon::M4_vrmpyoh_acc_s1:
17176
    case Hexagon::M4_xor_xacc:
17177
    case Hexagon::M5_vdmacbsu:
17178
    case Hexagon::M5_vrmacbsu:
17179
    case Hexagon::M5_vrmacbuu:
17180
    case Hexagon::M7_dcmpyiw_acc:
17181
    case Hexagon::M7_dcmpyiwc_acc:
17182
    case Hexagon::M7_dcmpyrw_acc:
17183
    case Hexagon::M7_dcmpyrwc_acc:
17184
    case Hexagon::S2_insertp_rp: {
17185
      switch (OpNum) {
17186
      case 2:
17187
        // op: Rss32
17188
        return 16;
17189
      case 3:
17190
        // op: Rtt32
17191
        return 8;
17192
      case 0:
17193
        // op: Rxx32
17194
        return 0;
17195
      }
17196
      break;
17197
    }
17198
    case Hexagon::A4_vrmaxh:
17199
    case Hexagon::A4_vrmaxuh:
17200
    case Hexagon::A4_vrmaxuw:
17201
    case Hexagon::A4_vrmaxw:
17202
    case Hexagon::A4_vrminh:
17203
    case Hexagon::A4_vrminuh:
17204
    case Hexagon::A4_vrminuw:
17205
    case Hexagon::A4_vrminw: {
17206
      switch (OpNum) {
17207
      case 2:
17208
        // op: Rss32
17209
        return 16;
17210
      case 3:
17211
        // op: Ru32
17212
        return 0;
17213
      case 0:
17214
        // op: Rxx32
17215
        return 8;
17216
      }
17217
      break;
17218
    }
17219
    case Hexagon::V6_vinsertwr: {
17220
      switch (OpNum) {
17221
      case 2:
17222
        // op: Rt32
17223
        return 16;
17224
      case 0:
17225
        // op: Vx32
17226
        return 0;
17227
      }
17228
      break;
17229
    }
17230
    case Hexagon::M2_subacc: {
17231
      switch (OpNum) {
17232
      case 2:
17233
        // op: Rt32
17234
        return 8;
17235
      case 3:
17236
        // op: Rs32
17237
        return 16;
17238
      case 0:
17239
        // op: Rx32
17240
        return 0;
17241
      }
17242
      break;
17243
    }
17244
    case Hexagon::A6_vminub_RdP: {
17245
      switch (OpNum) {
17246
      case 2:
17247
        // op: Rtt32
17248
        return 8;
17249
      case 3:
17250
        // op: Rss32
17251
        return 16;
17252
      case 0:
17253
        // op: Rdd32
17254
        return 0;
17255
      case 1:
17256
        // op: Pe4
17257
        return 5;
17258
      }
17259
      break;
17260
    }
17261
    case Hexagon::V6_vrmpyzbb_rx:
17262
    case Hexagon::V6_vrmpyzbub_rx:
17263
    case Hexagon::V6_vrmpyzcb_rx:
17264
    case Hexagon::V6_vrmpyzcbs_rx:
17265
    case Hexagon::V6_vrmpyznb_rx: {
17266
      switch (OpNum) {
17267
      case 2:
17268
        // op: Vu32
17269
        return 8;
17270
      case 0:
17271
        // op: Vdddd32
17272
        return 0;
17273
      case 1:
17274
        // op: Rx8
17275
        return 16;
17276
      }
17277
      break;
17278
    }
17279
    case Hexagon::V6_vunpackob:
17280
    case Hexagon::V6_vunpackoh: {
17281
      switch (OpNum) {
17282
      case 2:
17283
        // op: Vu32
17284
        return 8;
17285
      case 0:
17286
        // op: Vxx32
17287
        return 0;
17288
      }
17289
      break;
17290
    }
17291
    case Hexagon::V6_vandvrt_acc: {
17292
      switch (OpNum) {
17293
      case 2:
17294
        // op: Vu32
17295
        return 8;
17296
      case 3:
17297
        // op: Rt32
17298
        return 16;
17299
      case 0:
17300
        // op: Qx4
17301
        return 0;
17302
      }
17303
      break;
17304
    }
17305
    case Hexagon::V6_vaslh_acc:
17306
    case Hexagon::V6_vaslw_acc:
17307
    case Hexagon::V6_vasrh_acc:
17308
    case Hexagon::V6_vasrw_acc:
17309
    case Hexagon::V6_vdmpybus_acc:
17310
    case Hexagon::V6_vdmpyhb_acc:
17311
    case Hexagon::V6_vdmpyhsat_acc:
17312
    case Hexagon::V6_vdmpyhsusat_acc:
17313
    case Hexagon::V6_vmpyihb_acc:
17314
    case Hexagon::V6_vmpyiwb_acc:
17315
    case Hexagon::V6_vmpyiwh_acc:
17316
    case Hexagon::V6_vmpyiwub_acc:
17317
    case Hexagon::V6_vmpyuhe_acc:
17318
    case Hexagon::V6_vrmpybus_acc:
17319
    case Hexagon::V6_vrmpyub_acc: {
17320
      switch (OpNum) {
17321
      case 2:
17322
        // op: Vu32
17323
        return 8;
17324
      case 3:
17325
        // op: Rt32
17326
        return 16;
17327
      case 0:
17328
        // op: Vx32
17329
        return 0;
17330
      }
17331
      break;
17332
    }
17333
    case Hexagon::V6_vmpybus_acc:
17334
    case Hexagon::V6_vmpyh_acc:
17335
    case Hexagon::V6_vmpyhsat_acc:
17336
    case Hexagon::V6_vmpyub_acc:
17337
    case Hexagon::V6_vmpyuh_acc: {
17338
      switch (OpNum) {
17339
      case 2:
17340
        // op: Vu32
17341
        return 8;
17342
      case 3:
17343
        // op: Rt32
17344
        return 16;
17345
      case 0:
17346
        // op: Vxx32
17347
        return 0;
17348
      }
17349
      break;
17350
    }
17351
    case Hexagon::V6_vrmpyzbb_rt_acc:
17352
    case Hexagon::V6_vrmpyzbub_rt_acc:
17353
    case Hexagon::V6_vrmpyzcb_rt_acc:
17354
    case Hexagon::V6_vrmpyzcbs_rt_acc:
17355
    case Hexagon::V6_vrmpyznb_rt_acc: {
17356
      switch (OpNum) {
17357
      case 2:
17358
        // op: Vu32
17359
        return 8;
17360
      case 3:
17361
        // op: Rt8
17362
        return 16;
17363
      case 0:
17364
        // op: Vyyyy32
17365
        return 0;
17366
      }
17367
      break;
17368
    }
17369
    case Hexagon::V6_vmpahhsat:
17370
    case Hexagon::V6_vmpauhuhsat:
17371
    case Hexagon::V6_vmpsuhuhsat: {
17372
      switch (OpNum) {
17373
      case 2:
17374
        // op: Vu32
17375
        return 8;
17376
      case 3:
17377
        // op: Rtt32
17378
        return 16;
17379
      case 0:
17380
        // op: Vx32
17381
        return 0;
17382
      }
17383
      break;
17384
    }
17385
    case Hexagon::V6_vrmpybub_rtt_acc:
17386
    case Hexagon::V6_vrmpyub_rtt_acc: {
17387
      switch (OpNum) {
17388
      case 2:
17389
        // op: Vu32
17390
        return 8;
17391
      case 3:
17392
        // op: Rtt32
17393
        return 16;
17394
      case 0:
17395
        // op: Vxx32
17396
        return 0;
17397
      }
17398
      break;
17399
    }
17400
    case Hexagon::V6_veqb_and:
17401
    case Hexagon::V6_veqb_or:
17402
    case Hexagon::V6_veqb_xor:
17403
    case Hexagon::V6_veqh_and:
17404
    case Hexagon::V6_veqh_or:
17405
    case Hexagon::V6_veqh_xor:
17406
    case Hexagon::V6_veqw_and:
17407
    case Hexagon::V6_veqw_or:
17408
    case Hexagon::V6_veqw_xor:
17409
    case Hexagon::V6_vgtb_and:
17410
    case Hexagon::V6_vgtb_or:
17411
    case Hexagon::V6_vgtb_xor:
17412
    case Hexagon::V6_vgtbf_and:
17413
    case Hexagon::V6_vgtbf_or:
17414
    case Hexagon::V6_vgtbf_xor:
17415
    case Hexagon::V6_vgth_and:
17416
    case Hexagon::V6_vgth_or:
17417
    case Hexagon::V6_vgth_xor:
17418
    case Hexagon::V6_vgthf_and:
17419
    case Hexagon::V6_vgthf_or:
17420
    case Hexagon::V6_vgthf_xor:
17421
    case Hexagon::V6_vgtsf_and:
17422
    case Hexagon::V6_vgtsf_or:
17423
    case Hexagon::V6_vgtsf_xor:
17424
    case Hexagon::V6_vgtub_and:
17425
    case Hexagon::V6_vgtub_or:
17426
    case Hexagon::V6_vgtub_xor:
17427
    case Hexagon::V6_vgtuh_and:
17428
    case Hexagon::V6_vgtuh_or:
17429
    case Hexagon::V6_vgtuh_xor:
17430
    case Hexagon::V6_vgtuw_and:
17431
    case Hexagon::V6_vgtuw_or:
17432
    case Hexagon::V6_vgtuw_xor:
17433
    case Hexagon::V6_vgtw_and:
17434
    case Hexagon::V6_vgtw_or:
17435
    case Hexagon::V6_vgtw_xor: {
17436
      switch (OpNum) {
17437
      case 2:
17438
        // op: Vu32
17439
        return 8;
17440
      case 3:
17441
        // op: Vv32
17442
        return 16;
17443
      case 0:
17444
        // op: Qx4
17445
        return 0;
17446
      }
17447
      break;
17448
    }
17449
    case Hexagon::V6_vaddcarryo:
17450
    case Hexagon::V6_vsubcarryo: {
17451
      switch (OpNum) {
17452
      case 2:
17453
        // op: Vu32
17454
        return 8;
17455
      case 3:
17456
        // op: Vv32
17457
        return 16;
17458
      case 0:
17459
        // op: Vd32
17460
        return 0;
17461
      case 1:
17462
        // op: Qe4
17463
        return 5;
17464
      }
17465
      break;
17466
    }
17467
    case Hexagon::V6_vaddcarry:
17468
    case Hexagon::V6_vsubcarry: {
17469
      switch (OpNum) {
17470
      case 2:
17471
        // op: Vu32
17472
        return 8;
17473
      case 3:
17474
        // op: Vv32
17475
        return 16;
17476
      case 0:
17477
        // op: Vd32
17478
        return 0;
17479
      case 1:
17480
        // op: Qx4
17481
        return 5;
17482
      }
17483
      break;
17484
    }
17485
    case Hexagon::V6_vdmpy_sf_hf_acc:
17486
    case Hexagon::V6_vdmpyhvsat_acc:
17487
    case Hexagon::V6_vmpy_hf_hf_acc:
17488
    case Hexagon::V6_vmpyiewh_acc:
17489
    case Hexagon::V6_vmpyiewuh_acc:
17490
    case Hexagon::V6_vmpyih_acc:
17491
    case Hexagon::V6_vmpyowh_rnd_sacc:
17492
    case Hexagon::V6_vmpyowh_sacc:
17493
    case Hexagon::V6_vrmpybusv_acc:
17494
    case Hexagon::V6_vrmpybv_acc:
17495
    case Hexagon::V6_vrmpyubv_acc: {
17496
      switch (OpNum) {
17497
      case 2:
17498
        // op: Vu32
17499
        return 8;
17500
      case 3:
17501
        // op: Vv32
17502
        return 16;
17503
      case 0:
17504
        // op: Vx32
17505
        return 0;
17506
      }
17507
      break;
17508
    }
17509
    case Hexagon::V6_vaddhw_acc:
17510
    case Hexagon::V6_vaddubh_acc:
17511
    case Hexagon::V6_vadduhw_acc:
17512
    case Hexagon::V6_vasr_into:
17513
    case Hexagon::V6_vmpy_sf_bf_acc:
17514
    case Hexagon::V6_vmpy_sf_hf_acc:
17515
    case Hexagon::V6_vmpybusv_acc:
17516
    case Hexagon::V6_vmpybv_acc:
17517
    case Hexagon::V6_vmpyhus_acc:
17518
    case Hexagon::V6_vmpyhv_acc:
17519
    case Hexagon::V6_vmpyowh_64_acc:
17520
    case Hexagon::V6_vmpyubv_acc:
17521
    case Hexagon::V6_vmpyuhv_acc: {
17522
      switch (OpNum) {
17523
      case 2:
17524
        // op: Vu32
17525
        return 8;
17526
      case 3:
17527
        // op: Vv32
17528
        return 16;
17529
      case 0:
17530
        // op: Vxx32
17531
        return 0;
17532
      }
17533
      break;
17534
    }
17535
    case Hexagon::V6_vlutvvb_oracc: {
17536
      switch (OpNum) {
17537
      case 2:
17538
        // op: Vu32
17539
        return 8;
17540
      case 3:
17541
        // op: Vv32
17542
        return 19;
17543
      case 4:
17544
        // op: Rt8
17545
        return 16;
17546
      case 0:
17547
        // op: Vx32
17548
        return 0;
17549
      }
17550
      break;
17551
    }
17552
    case Hexagon::V6_vlutvwh_oracc: {
17553
      switch (OpNum) {
17554
      case 2:
17555
        // op: Vu32
17556
        return 8;
17557
      case 3:
17558
        // op: Vv32
17559
        return 19;
17560
      case 4:
17561
        // op: Rt8
17562
        return 16;
17563
      case 0:
17564
        // op: Vxx32
17565
        return 0;
17566
      }
17567
      break;
17568
    }
17569
    case Hexagon::V6_vdmpyhisat_acc:
17570
    case Hexagon::V6_vdmpyhsuisat_acc: {
17571
      switch (OpNum) {
17572
      case 2:
17573
        // op: Vuu32
17574
        return 8;
17575
      case 3:
17576
        // op: Rt32
17577
        return 16;
17578
      case 0:
17579
        // op: Vx32
17580
        return 0;
17581
      }
17582
      break;
17583
    }
17584
    case Hexagon::V6_vdmpybus_dv_acc:
17585
    case Hexagon::V6_vdmpyhb_dv_acc:
17586
    case Hexagon::V6_vdsaduh_acc:
17587
    case Hexagon::V6_vmpabus_acc:
17588
    case Hexagon::V6_vmpabuu_acc:
17589
    case Hexagon::V6_vmpahb_acc:
17590
    case Hexagon::V6_vmpauhb_acc:
17591
    case Hexagon::V6_vtmpyb_acc:
17592
    case Hexagon::V6_vtmpybus_acc:
17593
    case Hexagon::V6_vtmpyhb_acc: {
17594
      switch (OpNum) {
17595
      case 2:
17596
        // op: Vuu32
17597
        return 8;
17598
      case 3:
17599
        // op: Rt32
17600
        return 16;
17601
      case 0:
17602
        // op: Vxx32
17603
        return 0;
17604
      }
17605
      break;
17606
    }
17607
    case Hexagon::L4_loadalignb_ap:
17608
    case Hexagon::L4_loadalignh_ap: {
17609
      switch (OpNum) {
17610
      case 3:
17611
        // op: II
17612
        return 5;
17613
      case 0:
17614
        // op: Ryy32
17615
        return 0;
17616
      case 1:
17617
        // op: Re32
17618
        return 16;
17619
      }
17620
      break;
17621
    }
17622
    case Hexagon::S2_pstorerbnewf_pi:
17623
    case Hexagon::S2_pstorerbnewfnew_pi:
17624
    case Hexagon::S2_pstorerbnewt_pi:
17625
    case Hexagon::S2_pstorerbnewtnew_pi:
17626
    case Hexagon::S2_pstorerhnewf_pi:
17627
    case Hexagon::S2_pstorerhnewfnew_pi:
17628
    case Hexagon::S2_pstorerhnewt_pi:
17629
    case Hexagon::S2_pstorerhnewtnew_pi:
17630
    case Hexagon::S2_pstorerinewf_pi:
17631
    case Hexagon::S2_pstorerinewfnew_pi:
17632
    case Hexagon::S2_pstorerinewt_pi:
17633
    case Hexagon::S2_pstorerinewtnew_pi: {
17634
      switch (OpNum) {
17635
      case 3:
17636
        // op: Ii
17637
        return 3;
17638
      case 1:
17639
        // op: Pv4
17640
        return 0;
17641
      case 4:
17642
        // op: Nt8
17643
        return 8;
17644
      case 0:
17645
        // op: Rx32
17646
        return 16;
17647
      }
17648
      break;
17649
    }
17650
    case Hexagon::S2_pstorerbf_pi:
17651
    case Hexagon::S2_pstorerbfnew_pi:
17652
    case Hexagon::S2_pstorerbt_pi:
17653
    case Hexagon::S2_pstorerbtnew_pi:
17654
    case Hexagon::S2_pstorerff_pi:
17655
    case Hexagon::S2_pstorerffnew_pi:
17656
    case Hexagon::S2_pstorerft_pi:
17657
    case Hexagon::S2_pstorerftnew_pi:
17658
    case Hexagon::S2_pstorerhf_pi:
17659
    case Hexagon::S2_pstorerhfnew_pi:
17660
    case Hexagon::S2_pstorerht_pi:
17661
    case Hexagon::S2_pstorerhtnew_pi:
17662
    case Hexagon::S2_pstorerif_pi:
17663
    case Hexagon::S2_pstorerifnew_pi:
17664
    case Hexagon::S2_pstorerit_pi:
17665
    case Hexagon::S2_pstoreritnew_pi: {
17666
      switch (OpNum) {
17667
      case 3:
17668
        // op: Ii
17669
        return 3;
17670
      case 1:
17671
        // op: Pv4
17672
        return 0;
17673
      case 4:
17674
        // op: Rt32
17675
        return 8;
17676
      case 0:
17677
        // op: Rx32
17678
        return 16;
17679
      }
17680
      break;
17681
    }
17682
    case Hexagon::S2_pstorerdf_pi:
17683
    case Hexagon::S2_pstorerdfnew_pi:
17684
    case Hexagon::S2_pstorerdt_pi:
17685
    case Hexagon::S2_pstorerdtnew_pi: {
17686
      switch (OpNum) {
17687
      case 3:
17688
        // op: Ii
17689
        return 3;
17690
      case 1:
17691
        // op: Pv4
17692
        return 0;
17693
      case 4:
17694
        // op: Rtt32
17695
        return 8;
17696
      case 0:
17697
        // op: Rx32
17698
        return 16;
17699
      }
17700
      break;
17701
    }
17702
    case Hexagon::L2_loadbsw2_pi:
17703
    case Hexagon::L2_loadbzw2_pi:
17704
    case Hexagon::L2_loadrb_pi:
17705
    case Hexagon::L2_loadrh_pi:
17706
    case Hexagon::L2_loadri_pi:
17707
    case Hexagon::L2_loadrub_pi:
17708
    case Hexagon::L2_loadruh_pi: {
17709
      switch (OpNum) {
17710
      case 3:
17711
        // op: Ii
17712
        return 5;
17713
      case 0:
17714
        // op: Rd32
17715
        return 0;
17716
      case 1:
17717
        // op: Rx32
17718
        return 16;
17719
      }
17720
      break;
17721
    }
17722
    case Hexagon::L2_loadbsw4_pi:
17723
    case Hexagon::L2_loadbzw4_pi:
17724
    case Hexagon::L2_loadrd_pi: {
17725
      switch (OpNum) {
17726
      case 3:
17727
        // op: Ii
17728
        return 5;
17729
      case 0:
17730
        // op: Rdd32
17731
        return 0;
17732
      case 1:
17733
        // op: Rx32
17734
        return 16;
17735
      }
17736
      break;
17737
    }
17738
    case Hexagon::L2_ploadrbf_io:
17739
    case Hexagon::L2_ploadrbfnew_io:
17740
    case Hexagon::L2_ploadrbt_io:
17741
    case Hexagon::L2_ploadrbtnew_io:
17742
    case Hexagon::L2_ploadrhf_io:
17743
    case Hexagon::L2_ploadrhfnew_io:
17744
    case Hexagon::L2_ploadrht_io:
17745
    case Hexagon::L2_ploadrhtnew_io:
17746
    case Hexagon::L2_ploadrif_io:
17747
    case Hexagon::L2_ploadrifnew_io:
17748
    case Hexagon::L2_ploadrit_io:
17749
    case Hexagon::L2_ploadritnew_io:
17750
    case Hexagon::L2_ploadrubf_io:
17751
    case Hexagon::L2_ploadrubfnew_io:
17752
    case Hexagon::L2_ploadrubt_io:
17753
    case Hexagon::L2_ploadrubtnew_io:
17754
    case Hexagon::L2_ploadruhf_io:
17755
    case Hexagon::L2_ploadruhfnew_io:
17756
    case Hexagon::L2_ploadruht_io:
17757
    case Hexagon::L2_ploadruhtnew_io: {
17758
      switch (OpNum) {
17759
      case 3:
17760
        // op: Ii
17761
        return 5;
17762
      case 1:
17763
        // op: Pt4
17764
        return 11;
17765
      case 2:
17766
        // op: Rs32
17767
        return 16;
17768
      case 0:
17769
        // op: Rd32
17770
        return 0;
17771
      }
17772
      break;
17773
    }
17774
    case Hexagon::L2_ploadrdf_io:
17775
    case Hexagon::L2_ploadrdfnew_io:
17776
    case Hexagon::L2_ploadrdt_io:
17777
    case Hexagon::L2_ploadrdtnew_io: {
17778
      switch (OpNum) {
17779
      case 3:
17780
        // op: Ii
17781
        return 5;
17782
      case 1:
17783
        // op: Pt4
17784
        return 11;
17785
      case 2:
17786
        // op: Rs32
17787
        return 16;
17788
      case 0:
17789
        // op: Rdd32
17790
        return 0;
17791
      }
17792
      break;
17793
    }
17794
    case Hexagon::A2_paddif:
17795
    case Hexagon::A2_paddifnew:
17796
    case Hexagon::A2_paddit:
17797
    case Hexagon::A2_padditnew:
17798
    case Hexagon::C2_muxir: {
17799
      switch (OpNum) {
17800
      case 3:
17801
        // op: Ii
17802
        return 5;
17803
      case 1:
17804
        // op: Pu4
17805
        return 21;
17806
      case 2:
17807
        // op: Rs32
17808
        return 16;
17809
      case 0:
17810
        // op: Rd32
17811
        return 0;
17812
      }
17813
      break;
17814
    }
17815
    case Hexagon::S4_addaddi: {
17816
      switch (OpNum) {
17817
      case 3:
17818
        // op: Ii
17819
        return 5;
17820
      case 1:
17821
        // op: Rs32
17822
        return 16;
17823
      case 2:
17824
        // op: Ru32
17825
        return 0;
17826
      case 0:
17827
        // op: Rd32
17828
        return 8;
17829
      }
17830
      break;
17831
    }
17832
    case Hexagon::S4_vrcrotate: {
17833
      switch (OpNum) {
17834
      case 3:
17835
        // op: Ii
17836
        return 5;
17837
      case 1:
17838
        // op: Rss32
17839
        return 16;
17840
      case 2:
17841
        // op: Rt32
17842
        return 8;
17843
      case 0:
17844
        // op: Rdd32
17845
        return 0;
17846
      }
17847
      break;
17848
    }
17849
    case Hexagon::S2_vspliceib: {
17850
      switch (OpNum) {
17851
      case 3:
17852
        // op: Ii
17853
        return 5;
17854
      case 1:
17855
        // op: Rss32
17856
        return 16;
17857
      case 2:
17858
        // op: Rtt32
17859
        return 8;
17860
      case 0:
17861
        // op: Rdd32
17862
        return 0;
17863
      }
17864
      break;
17865
    }
17866
    case Hexagon::S2_addasl_rrri: {
17867
      switch (OpNum) {
17868
      case 3:
17869
        // op: Ii
17870
        return 5;
17871
      case 1:
17872
        // op: Rt32
17873
        return 8;
17874
      case 2:
17875
        // op: Rs32
17876
        return 16;
17877
      case 0:
17878
        // op: Rd32
17879
        return 0;
17880
      }
17881
      break;
17882
    }
17883
    case Hexagon::S2_valignib: {
17884
      switch (OpNum) {
17885
      case 3:
17886
        // op: Ii
17887
        return 5;
17888
      case 1:
17889
        // op: Rtt32
17890
        return 8;
17891
      case 2:
17892
        // op: Rss32
17893
        return 16;
17894
      case 0:
17895
        // op: Rdd32
17896
        return 0;
17897
      }
17898
      break;
17899
    }
17900
    case Hexagon::S4_or_andix: {
17901
      switch (OpNum) {
17902
      case 3:
17903
        // op: Ii
17904
        return 5;
17905
      case 1:
17906
        // op: Ru32
17907
        return 0;
17908
      case 0:
17909
        // op: Rx32
17910
        return 16;
17911
      }
17912
      break;
17913
    }
17914
    case Hexagon::M4_mpyri_addr: {
17915
      switch (OpNum) {
17916
      case 3:
17917
        // op: Ii
17918
        return 5;
17919
      case 1:
17920
        // op: Ru32
17921
        return 0;
17922
      case 2:
17923
        // op: Rs32
17924
        return 16;
17925
      case 0:
17926
        // op: Rd32
17927
        return 8;
17928
      }
17929
      break;
17930
    }
17931
    case Hexagon::V6_valignbi:
17932
    case Hexagon::V6_vlalignbi:
17933
    case Hexagon::V6_vlutvvbi: {
17934
      switch (OpNum) {
17935
      case 3:
17936
        // op: Ii
17937
        return 5;
17938
      case 1:
17939
        // op: Vu32
17940
        return 8;
17941
      case 2:
17942
        // op: Vv32
17943
        return 16;
17944
      case 0:
17945
        // op: Vd32
17946
        return 0;
17947
      }
17948
      break;
17949
    }
17950
    case Hexagon::V6_vlutvwhi: {
17951
      switch (OpNum) {
17952
      case 3:
17953
        // op: Ii
17954
        return 5;
17955
      case 1:
17956
        // op: Vu32
17957
        return 8;
17958
      case 2:
17959
        // op: Vv32
17960
        return 16;
17961
      case 0:
17962
        // op: Vdd32
17963
        return 0;
17964
      }
17965
      break;
17966
    }
17967
    case Hexagon::V6_vrmpybusi:
17968
    case Hexagon::V6_vrmpyubi:
17969
    case Hexagon::V6_vrsadubi: {
17970
      switch (OpNum) {
17971
      case 3:
17972
        // op: Ii
17973
        return 5;
17974
      case 1:
17975
        // op: Vuu32
17976
        return 8;
17977
      case 2:
17978
        // op: Rt32
17979
        return 16;
17980
      case 0:
17981
        // op: Vdd32
17982
        return 0;
17983
      }
17984
      break;
17985
    }
17986
    case Hexagon::V6_v6mpyhubs10:
17987
    case Hexagon::V6_v6mpyvubs10: {
17988
      switch (OpNum) {
17989
      case 3:
17990
        // op: Ii
17991
        return 5;
17992
      case 1:
17993
        // op: Vuu32
17994
        return 8;
17995
      case 2:
17996
        // op: Vvv32
17997
        return 16;
17998
      case 0:
17999
        // op: Vdd32
18000
        return 0;
18001
      }
18002
      break;
18003
    }
18004
    case Hexagon::M2_accii:
18005
    case Hexagon::M2_macsin:
18006
    case Hexagon::M2_macsip:
18007
    case Hexagon::M2_naccii:
18008
    case Hexagon::S4_or_andi:
18009
    case Hexagon::S4_or_ori: {
18010
      switch (OpNum) {
18011
      case 3:
18012
        // op: Ii
18013
        return 5;
18014
      case 2:
18015
        // op: Rs32
18016
        return 16;
18017
      case 0:
18018
        // op: Rx32
18019
        return 0;
18020
      }
18021
      break;
18022
    }
18023
    case Hexagon::L2_loadalignb_io:
18024
    case Hexagon::L2_loadalignh_io: {
18025
      switch (OpNum) {
18026
      case 3:
18027
        // op: Ii
18028
        return 5;
18029
      case 2:
18030
        // op: Rs32
18031
        return 16;
18032
      case 0:
18033
        // op: Ryy32
18034
        return 0;
18035
      }
18036
      break;
18037
    }
18038
    case Hexagon::S2_tableidxb:
18039
    case Hexagon::S2_tableidxd:
18040
    case Hexagon::S2_tableidxh:
18041
    case Hexagon::S2_tableidxw: {
18042
      switch (OpNum) {
18043
      case 3:
18044
        // op: Ii
18045
        return 5;
18046
      case 4:
18047
        // op: II
18048
        return 8;
18049
      case 2:
18050
        // op: Rs32
18051
        return 16;
18052
      case 0:
18053
        // op: Rx32
18054
        return 0;
18055
      }
18056
      break;
18057
    }
18058
    case Hexagon::L2_loadbsw2_pci:
18059
    case Hexagon::L2_loadbzw2_pci:
18060
    case Hexagon::L2_loadrb_pci:
18061
    case Hexagon::L2_loadrh_pci:
18062
    case Hexagon::L2_loadri_pci:
18063
    case Hexagon::L2_loadrub_pci:
18064
    case Hexagon::L2_loadruh_pci: {
18065
      switch (OpNum) {
18066
      case 3:
18067
        // op: Ii
18068
        return 5;
18069
      case 4:
18070
        // op: Mu2
18071
        return 13;
18072
      case 0:
18073
        // op: Rd32
18074
        return 0;
18075
      case 1:
18076
        // op: Rx32
18077
        return 16;
18078
      }
18079
      break;
18080
    }
18081
    case Hexagon::L2_loadbsw4_pci:
18082
    case Hexagon::L2_loadbzw4_pci:
18083
    case Hexagon::L2_loadrd_pci: {
18084
      switch (OpNum) {
18085
      case 3:
18086
        // op: Ii
18087
        return 5;
18088
      case 4:
18089
        // op: Mu2
18090
        return 13;
18091
      case 0:
18092
        // op: Rdd32
18093
        return 0;
18094
      case 1:
18095
        // op: Rx32
18096
        return 16;
18097
      }
18098
      break;
18099
    }
18100
    case Hexagon::S4_pstorerbnewf_rr:
18101
    case Hexagon::S4_pstorerbnewfnew_rr:
18102
    case Hexagon::S4_pstorerbnewt_rr:
18103
    case Hexagon::S4_pstorerbnewtnew_rr:
18104
    case Hexagon::S4_pstorerhnewf_rr:
18105
    case Hexagon::S4_pstorerhnewfnew_rr:
18106
    case Hexagon::S4_pstorerhnewt_rr:
18107
    case Hexagon::S4_pstorerhnewtnew_rr:
18108
    case Hexagon::S4_pstorerinewf_rr:
18109
    case Hexagon::S4_pstorerinewfnew_rr:
18110
    case Hexagon::S4_pstorerinewt_rr:
18111
    case Hexagon::S4_pstorerinewtnew_rr: {
18112
      switch (OpNum) {
18113
      case 3:
18114
        // op: Ii
18115
        return 7;
18116
      case 0:
18117
        // op: Pv4
18118
        return 5;
18119
      case 1:
18120
        // op: Rs32
18121
        return 16;
18122
      case 2:
18123
        // op: Ru32
18124
        return 8;
18125
      case 4:
18126
        // op: Nt8
18127
        return 0;
18128
      }
18129
      break;
18130
    }
18131
    case Hexagon::S4_pstorerbf_rr:
18132
    case Hexagon::S4_pstorerbfnew_rr:
18133
    case Hexagon::S4_pstorerbt_rr:
18134
    case Hexagon::S4_pstorerbtnew_rr:
18135
    case Hexagon::S4_pstorerff_rr:
18136
    case Hexagon::S4_pstorerffnew_rr:
18137
    case Hexagon::S4_pstorerft_rr:
18138
    case Hexagon::S4_pstorerftnew_rr:
18139
    case Hexagon::S4_pstorerhf_rr:
18140
    case Hexagon::S4_pstorerhfnew_rr:
18141
    case Hexagon::S4_pstorerht_rr:
18142
    case Hexagon::S4_pstorerhtnew_rr:
18143
    case Hexagon::S4_pstorerif_rr:
18144
    case Hexagon::S4_pstorerifnew_rr:
18145
    case Hexagon::S4_pstorerit_rr:
18146
    case Hexagon::S4_pstoreritnew_rr: {
18147
      switch (OpNum) {
18148
      case 3:
18149
        // op: Ii
18150
        return 7;
18151
      case 0:
18152
        // op: Pv4
18153
        return 5;
18154
      case 1:
18155
        // op: Rs32
18156
        return 16;
18157
      case 2:
18158
        // op: Ru32
18159
        return 8;
18160
      case 4:
18161
        // op: Rt32
18162
        return 0;
18163
      }
18164
      break;
18165
    }
18166
    case Hexagon::S4_pstorerdf_rr:
18167
    case Hexagon::S4_pstorerdfnew_rr:
18168
    case Hexagon::S4_pstorerdt_rr:
18169
    case Hexagon::S4_pstorerdtnew_rr: {
18170
      switch (OpNum) {
18171
      case 3:
18172
        // op: Ii
18173
        return 7;
18174
      case 0:
18175
        // op: Pv4
18176
        return 5;
18177
      case 1:
18178
        // op: Rs32
18179
        return 16;
18180
      case 2:
18181
        // op: Ru32
18182
        return 8;
18183
      case 4:
18184
        // op: Rtt32
18185
        return 0;
18186
      }
18187
      break;
18188
    }
18189
    case Hexagon::L4_loadrb_rr:
18190
    case Hexagon::L4_loadrh_rr:
18191
    case Hexagon::L4_loadri_rr:
18192
    case Hexagon::L4_loadrub_rr:
18193
    case Hexagon::L4_loadruh_rr: {
18194
      switch (OpNum) {
18195
      case 3:
18196
        // op: Ii
18197
        return 7;
18198
      case 1:
18199
        // op: Rs32
18200
        return 16;
18201
      case 2:
18202
        // op: Rt32
18203
        return 8;
18204
      case 0:
18205
        // op: Rd32
18206
        return 0;
18207
      }
18208
      break;
18209
    }
18210
    case Hexagon::L4_loadrd_rr: {
18211
      switch (OpNum) {
18212
      case 3:
18213
        // op: Ii
18214
        return 7;
18215
      case 1:
18216
        // op: Rs32
18217
        return 16;
18218
      case 2:
18219
        // op: Rt32
18220
        return 8;
18221
      case 0:
18222
        // op: Rdd32
18223
        return 0;
18224
      }
18225
      break;
18226
    }
18227
    case Hexagon::L4_loadalignb_ur:
18228
    case Hexagon::L4_loadalignh_ur: {
18229
      switch (OpNum) {
18230
      case 3:
18231
        // op: Ii
18232
        return 7;
18233
      case 4:
18234
        // op: II
18235
        return 5;
18236
      case 2:
18237
        // op: Rt32
18238
        return 16;
18239
      case 0:
18240
        // op: Ryy32
18241
        return 0;
18242
      }
18243
      break;
18244
    }
18245
    case Hexagon::V6_vL32Ub_pi:
18246
    case Hexagon::V6_vL32b_cur_pi:
18247
    case Hexagon::V6_vL32b_nt_cur_pi:
18248
    case Hexagon::V6_vL32b_nt_pi:
18249
    case Hexagon::V6_vL32b_nt_tmp_pi:
18250
    case Hexagon::V6_vL32b_pi:
18251
    case Hexagon::V6_vL32b_tmp_pi: {
18252
      switch (OpNum) {
18253
      case 3:
18254
        // op: Ii
18255
        return 8;
18256
      case 0:
18257
        // op: Vd32
18258
        return 0;
18259
      case 1:
18260
        // op: Rx32
18261
        return 16;
18262
      }
18263
      break;
18264
    }
18265
    case Hexagon::V6_zLd_pred_pi: {
18266
      switch (OpNum) {
18267
      case 3:
18268
        // op: Ii
18269
        return 8;
18270
      case 1:
18271
        // op: Pv4
18272
        return 11;
18273
      case 0:
18274
        // op: Rx32
18275
        return 16;
18276
      }
18277
      break;
18278
    }
18279
    case Hexagon::V6_vL32b_cur_npred_ai:
18280
    case Hexagon::V6_vL32b_cur_pred_ai:
18281
    case Hexagon::V6_vL32b_npred_ai:
18282
    case Hexagon::V6_vL32b_nt_cur_npred_ai:
18283
    case Hexagon::V6_vL32b_nt_cur_pred_ai:
18284
    case Hexagon::V6_vL32b_nt_npred_ai:
18285
    case Hexagon::V6_vL32b_nt_pred_ai:
18286
    case Hexagon::V6_vL32b_nt_tmp_npred_ai:
18287
    case Hexagon::V6_vL32b_nt_tmp_pred_ai:
18288
    case Hexagon::V6_vL32b_pred_ai:
18289
    case Hexagon::V6_vL32b_tmp_npred_ai:
18290
    case Hexagon::V6_vL32b_tmp_pred_ai: {
18291
      switch (OpNum) {
18292
      case 3:
18293
        // op: Ii
18294
        return 8;
18295
      case 1:
18296
        // op: Pv4
18297
        return 11;
18298
      case 2:
18299
        // op: Rt32
18300
        return 16;
18301
      case 0:
18302
        // op: Vd32
18303
        return 0;
18304
      }
18305
      break;
18306
    }
18307
    case Hexagon::V6_vS32b_new_npred_pi:
18308
    case Hexagon::V6_vS32b_new_pred_pi:
18309
    case Hexagon::V6_vS32b_nt_new_npred_pi:
18310
    case Hexagon::V6_vS32b_nt_new_pred_pi: {
18311
      switch (OpNum) {
18312
      case 3:
18313
        // op: Ii
18314
        return 8;
18315
      case 1:
18316
        // op: Pv4
18317
        return 11;
18318
      case 4:
18319
        // op: Os8
18320
        return 0;
18321
      case 0:
18322
        // op: Rx32
18323
        return 16;
18324
      }
18325
      break;
18326
    }
18327
    case Hexagon::V6_vS32Ub_npred_pi:
18328
    case Hexagon::V6_vS32Ub_pred_pi:
18329
    case Hexagon::V6_vS32b_npred_pi:
18330
    case Hexagon::V6_vS32b_nt_npred_pi:
18331
    case Hexagon::V6_vS32b_nt_pred_pi:
18332
    case Hexagon::V6_vS32b_pred_pi: {
18333
      switch (OpNum) {
18334
      case 3:
18335
        // op: Ii
18336
        return 8;
18337
      case 1:
18338
        // op: Pv4
18339
        return 11;
18340
      case 4:
18341
        // op: Vs32
18342
        return 0;
18343
      case 0:
18344
        // op: Rx32
18345
        return 16;
18346
      }
18347
      break;
18348
    }
18349
    case Hexagon::V6_vS32b_nqpred_pi:
18350
    case Hexagon::V6_vS32b_nt_nqpred_pi:
18351
    case Hexagon::V6_vS32b_nt_qpred_pi:
18352
    case Hexagon::V6_vS32b_qpred_pi: {
18353
      switch (OpNum) {
18354
      case 3:
18355
        // op: Ii
18356
        return 8;
18357
      case 1:
18358
        // op: Qv4
18359
        return 11;
18360
      case 4:
18361
        // op: Vs32
18362
        return 0;
18363
      case 0:
18364
        // op: Rx32
18365
        return 16;
18366
      }
18367
      break;
18368
    }
18369
    case Hexagon::S2_asl_i_r_acc:
18370
    case Hexagon::S2_asl_i_r_and:
18371
    case Hexagon::S2_asl_i_r_nac:
18372
    case Hexagon::S2_asl_i_r_or:
18373
    case Hexagon::S2_asl_i_r_xacc:
18374
    case Hexagon::S2_asr_i_r_acc:
18375
    case Hexagon::S2_asr_i_r_and:
18376
    case Hexagon::S2_asr_i_r_nac:
18377
    case Hexagon::S2_asr_i_r_or:
18378
    case Hexagon::S2_lsr_i_r_acc:
18379
    case Hexagon::S2_lsr_i_r_and:
18380
    case Hexagon::S2_lsr_i_r_nac:
18381
    case Hexagon::S2_lsr_i_r_or:
18382
    case Hexagon::S2_lsr_i_r_xacc:
18383
    case Hexagon::S6_rol_i_r_acc:
18384
    case Hexagon::S6_rol_i_r_and:
18385
    case Hexagon::S6_rol_i_r_nac:
18386
    case Hexagon::S6_rol_i_r_or:
18387
    case Hexagon::S6_rol_i_r_xacc: {
18388
      switch (OpNum) {
18389
      case 3:
18390
        // op: Ii
18391
        return 8;
18392
      case 2:
18393
        // op: Rs32
18394
        return 16;
18395
      case 0:
18396
        // op: Rx32
18397
        return 0;
18398
      }
18399
      break;
18400
    }
18401
    case Hexagon::S2_asl_i_p_acc:
18402
    case Hexagon::S2_asl_i_p_and:
18403
    case Hexagon::S2_asl_i_p_nac:
18404
    case Hexagon::S2_asl_i_p_or:
18405
    case Hexagon::S2_asl_i_p_xacc:
18406
    case Hexagon::S2_asr_i_p_acc:
18407
    case Hexagon::S2_asr_i_p_and:
18408
    case Hexagon::S2_asr_i_p_nac:
18409
    case Hexagon::S2_asr_i_p_or:
18410
    case Hexagon::S2_lsr_i_p_acc:
18411
    case Hexagon::S2_lsr_i_p_and:
18412
    case Hexagon::S2_lsr_i_p_nac:
18413
    case Hexagon::S2_lsr_i_p_or:
18414
    case Hexagon::S2_lsr_i_p_xacc:
18415
    case Hexagon::S6_rol_i_p_acc:
18416
    case Hexagon::S6_rol_i_p_and:
18417
    case Hexagon::S6_rol_i_p_nac:
18418
    case Hexagon::S6_rol_i_p_or:
18419
    case Hexagon::S6_rol_i_p_xacc: {
18420
      switch (OpNum) {
18421
      case 3:
18422
        // op: Ii
18423
        return 8;
18424
      case 2:
18425
        // op: Rss32
18426
        return 16;
18427
      case 0:
18428
        // op: Rxx32
18429
        return 0;
18430
      }
18431
      break;
18432
    }
18433
    case Hexagon::S2_insert: {
18434
      switch (OpNum) {
18435
      case 3:
18436
        // op: Ii
18437
        return 8;
18438
      case 4:
18439
        // op: II
18440
        return 5;
18441
      case 2:
18442
        // op: Rs32
18443
        return 16;
18444
      case 0:
18445
        // op: Rx32
18446
        return 0;
18447
      }
18448
      break;
18449
    }
18450
    case Hexagon::S2_insertp: {
18451
      switch (OpNum) {
18452
      case 3:
18453
        // op: Ii
18454
        return 8;
18455
      case 4:
18456
        // op: II
18457
        return 5;
18458
      case 2:
18459
        // op: Rss32
18460
        return 16;
18461
      case 0:
18462
        // op: Rxx32
18463
        return 0;
18464
      }
18465
      break;
18466
    }
18467
    case Hexagon::L2_loadbsw2_pbr:
18468
    case Hexagon::L2_loadbsw2_pcr:
18469
    case Hexagon::L2_loadbsw2_pr:
18470
    case Hexagon::L2_loadbzw2_pbr:
18471
    case Hexagon::L2_loadbzw2_pcr:
18472
    case Hexagon::L2_loadbzw2_pr:
18473
    case Hexagon::L2_loadrb_pbr:
18474
    case Hexagon::L2_loadrb_pcr:
18475
    case Hexagon::L2_loadrb_pr:
18476
    case Hexagon::L2_loadrh_pbr:
18477
    case Hexagon::L2_loadrh_pcr:
18478
    case Hexagon::L2_loadrh_pr:
18479
    case Hexagon::L2_loadri_pbr:
18480
    case Hexagon::L2_loadri_pcr:
18481
    case Hexagon::L2_loadri_pr:
18482
    case Hexagon::L2_loadrub_pbr:
18483
    case Hexagon::L2_loadrub_pcr:
18484
    case Hexagon::L2_loadrub_pr:
18485
    case Hexagon::L2_loadruh_pbr:
18486
    case Hexagon::L2_loadruh_pcr:
18487
    case Hexagon::L2_loadruh_pr: {
18488
      switch (OpNum) {
18489
      case 3:
18490
        // op: Mu2
18491
        return 13;
18492
      case 0:
18493
        // op: Rd32
18494
        return 0;
18495
      case 1:
18496
        // op: Rx32
18497
        return 16;
18498
      }
18499
      break;
18500
    }
18501
    case Hexagon::L2_loadbsw4_pbr:
18502
    case Hexagon::L2_loadbsw4_pcr:
18503
    case Hexagon::L2_loadbsw4_pr:
18504
    case Hexagon::L2_loadbzw4_pbr:
18505
    case Hexagon::L2_loadbzw4_pcr:
18506
    case Hexagon::L2_loadbzw4_pr:
18507
    case Hexagon::L2_loadrd_pbr:
18508
    case Hexagon::L2_loadrd_pcr:
18509
    case Hexagon::L2_loadrd_pr: {
18510
      switch (OpNum) {
18511
      case 3:
18512
        // op: Mu2
18513
        return 13;
18514
      case 0:
18515
        // op: Rdd32
18516
        return 0;
18517
      case 1:
18518
        // op: Rx32
18519
        return 16;
18520
      }
18521
      break;
18522
    }
18523
    case Hexagon::V6_vL32Ub_ppu:
18524
    case Hexagon::V6_vL32b_cur_ppu:
18525
    case Hexagon::V6_vL32b_nt_cur_ppu:
18526
    case Hexagon::V6_vL32b_nt_ppu:
18527
    case Hexagon::V6_vL32b_nt_tmp_ppu:
18528
    case Hexagon::V6_vL32b_ppu:
18529
    case Hexagon::V6_vL32b_tmp_ppu: {
18530
      switch (OpNum) {
18531
      case 3:
18532
        // op: Mu2
18533
        return 13;
18534
      case 0:
18535
        // op: Vd32
18536
        return 0;
18537
      case 1:
18538
        // op: Rx32
18539
        return 16;
18540
      }
18541
      break;
18542
    }
18543
    case Hexagon::A5_ACS: {
18544
      switch (OpNum) {
18545
      case 3:
18546
        // op: Rss32
18547
        return 16;
18548
      case 4:
18549
        // op: Rtt32
18550
        return 8;
18551
      case 0:
18552
        // op: Rxx32
18553
        return 0;
18554
      case 1:
18555
        // op: Pe4
18556
        return 5;
18557
      }
18558
      break;
18559
    }
18560
    case Hexagon::V6_vrmpyzbb_rx_acc:
18561
    case Hexagon::V6_vrmpyzbub_rx_acc:
18562
    case Hexagon::V6_vrmpyzcb_rx_acc:
18563
    case Hexagon::V6_vrmpyzcbs_rx_acc:
18564
    case Hexagon::V6_vrmpyznb_rx_acc: {
18565
      switch (OpNum) {
18566
      case 3:
18567
        // op: Vu32
18568
        return 8;
18569
      case 0:
18570
        // op: Vyyyy32
18571
        return 0;
18572
      case 1:
18573
        // op: Rx8
18574
        return 16;
18575
      }
18576
      break;
18577
    }
18578
    case Hexagon::L2_loadalignb_pi:
18579
    case Hexagon::L2_loadalignh_pi: {
18580
      switch (OpNum) {
18581
      case 4:
18582
        // op: Ii
18583
        return 5;
18584
      case 0:
18585
        // op: Ryy32
18586
        return 0;
18587
      case 1:
18588
        // op: Rx32
18589
        return 16;
18590
      }
18591
      break;
18592
    }
18593
    case Hexagon::L2_ploadrbf_pi:
18594
    case Hexagon::L2_ploadrbfnew_pi:
18595
    case Hexagon::L2_ploadrbt_pi:
18596
    case Hexagon::L2_ploadrbtnew_pi:
18597
    case Hexagon::L2_ploadrhf_pi:
18598
    case Hexagon::L2_ploadrhfnew_pi:
18599
    case Hexagon::L2_ploadrht_pi:
18600
    case Hexagon::L2_ploadrhtnew_pi:
18601
    case Hexagon::L2_ploadrif_pi:
18602
    case Hexagon::L2_ploadrifnew_pi:
18603
    case Hexagon::L2_ploadrit_pi:
18604
    case Hexagon::L2_ploadritnew_pi:
18605
    case Hexagon::L2_ploadrubf_pi:
18606
    case Hexagon::L2_ploadrubfnew_pi:
18607
    case Hexagon::L2_ploadrubt_pi:
18608
    case Hexagon::L2_ploadrubtnew_pi:
18609
    case Hexagon::L2_ploadruhf_pi:
18610
    case Hexagon::L2_ploadruhfnew_pi:
18611
    case Hexagon::L2_ploadruht_pi:
18612
    case Hexagon::L2_ploadruhtnew_pi: {
18613
      switch (OpNum) {
18614
      case 4:
18615
        // op: Ii
18616
        return 5;
18617
      case 2:
18618
        // op: Pt4
18619
        return 9;
18620
      case 0:
18621
        // op: Rd32
18622
        return 0;
18623
      case 1:
18624
        // op: Rx32
18625
        return 16;
18626
      }
18627
      break;
18628
    }
18629
    case Hexagon::L2_ploadrdf_pi:
18630
    case Hexagon::L2_ploadrdfnew_pi:
18631
    case Hexagon::L2_ploadrdt_pi:
18632
    case Hexagon::L2_ploadrdtnew_pi: {
18633
      switch (OpNum) {
18634
      case 4:
18635
        // op: Ii
18636
        return 5;
18637
      case 2:
18638
        // op: Pt4
18639
        return 9;
18640
      case 0:
18641
        // op: Rdd32
18642
        return 0;
18643
      case 1:
18644
        // op: Rx32
18645
        return 16;
18646
      }
18647
      break;
18648
    }
18649
    case Hexagon::S4_vrcrotate_acc: {
18650
      switch (OpNum) {
18651
      case 4:
18652
        // op: Ii
18653
        return 5;
18654
      case 2:
18655
        // op: Rss32
18656
        return 16;
18657
      case 3:
18658
        // op: Rt32
18659
        return 8;
18660
      case 0:
18661
        // op: Rxx32
18662
        return 0;
18663
      }
18664
      break;
18665
    }
18666
    case Hexagon::V6_vlutvvb_oracci: {
18667
      switch (OpNum) {
18668
      case 4:
18669
        // op: Ii
18670
        return 5;
18671
      case 2:
18672
        // op: Vu32
18673
        return 8;
18674
      case 3:
18675
        // op: Vv32
18676
        return 16;
18677
      case 0:
18678
        // op: Vx32
18679
        return 0;
18680
      }
18681
      break;
18682
    }
18683
    case Hexagon::V6_vlutvwh_oracci: {
18684
      switch (OpNum) {
18685
      case 4:
18686
        // op: Ii
18687
        return 5;
18688
      case 2:
18689
        // op: Vu32
18690
        return 8;
18691
      case 3:
18692
        // op: Vv32
18693
        return 16;
18694
      case 0:
18695
        // op: Vxx32
18696
        return 0;
18697
      }
18698
      break;
18699
    }
18700
    case Hexagon::V6_vrmpybusi_acc:
18701
    case Hexagon::V6_vrmpyubi_acc:
18702
    case Hexagon::V6_vrsadubi_acc: {
18703
      switch (OpNum) {
18704
      case 4:
18705
        // op: Ii
18706
        return 5;
18707
      case 2:
18708
        // op: Vuu32
18709
        return 8;
18710
      case 3:
18711
        // op: Rt32
18712
        return 16;
18713
      case 0:
18714
        // op: Vxx32
18715
        return 0;
18716
      }
18717
      break;
18718
    }
18719
    case Hexagon::V6_v6mpyhubs10_vxx:
18720
    case Hexagon::V6_v6mpyvubs10_vxx: {
18721
      switch (OpNum) {
18722
      case 4:
18723
        // op: Ii
18724
        return 5;
18725
      case 2:
18726
        // op: Vuu32
18727
        return 8;
18728
      case 3:
18729
        // op: Vvv32
18730
        return 16;
18731
      case 0:
18732
        // op: Vxx32
18733
        return 0;
18734
      }
18735
      break;
18736
    }
18737
    case Hexagon::L2_loadalignb_pci:
18738
    case Hexagon::L2_loadalignh_pci: {
18739
      switch (OpNum) {
18740
      case 4:
18741
        // op: Ii
18742
        return 5;
18743
      case 5:
18744
        // op: Mu2
18745
        return 13;
18746
      case 0:
18747
        // op: Ryy32
18748
        return 0;
18749
      case 1:
18750
        // op: Rx32
18751
        return 16;
18752
      }
18753
      break;
18754
    }
18755
    case Hexagon::L4_ploadrbf_rr:
18756
    case Hexagon::L4_ploadrbfnew_rr:
18757
    case Hexagon::L4_ploadrbt_rr:
18758
    case Hexagon::L4_ploadrbtnew_rr:
18759
    case Hexagon::L4_ploadrhf_rr:
18760
    case Hexagon::L4_ploadrhfnew_rr:
18761
    case Hexagon::L4_ploadrht_rr:
18762
    case Hexagon::L4_ploadrhtnew_rr:
18763
    case Hexagon::L4_ploadrif_rr:
18764
    case Hexagon::L4_ploadrifnew_rr:
18765
    case Hexagon::L4_ploadrit_rr:
18766
    case Hexagon::L4_ploadritnew_rr:
18767
    case Hexagon::L4_ploadrubf_rr:
18768
    case Hexagon::L4_ploadrubfnew_rr:
18769
    case Hexagon::L4_ploadrubt_rr:
18770
    case Hexagon::L4_ploadrubtnew_rr:
18771
    case Hexagon::L4_ploadruhf_rr:
18772
    case Hexagon::L4_ploadruhfnew_rr:
18773
    case Hexagon::L4_ploadruht_rr:
18774
    case Hexagon::L4_ploadruhtnew_rr: {
18775
      switch (OpNum) {
18776
      case 4:
18777
        // op: Ii
18778
        return 7;
18779
      case 1:
18780
        // op: Pv4
18781
        return 5;
18782
      case 2:
18783
        // op: Rs32
18784
        return 16;
18785
      case 3:
18786
        // op: Rt32
18787
        return 8;
18788
      case 0:
18789
        // op: Rd32
18790
        return 0;
18791
      }
18792
      break;
18793
    }
18794
    case Hexagon::L4_ploadrdf_rr:
18795
    case Hexagon::L4_ploadrdfnew_rr:
18796
    case Hexagon::L4_ploadrdt_rr:
18797
    case Hexagon::L4_ploadrdtnew_rr: {
18798
      switch (OpNum) {
18799
      case 4:
18800
        // op: Ii
18801
        return 7;
18802
      case 1:
18803
        // op: Pv4
18804
        return 5;
18805
      case 2:
18806
        // op: Rs32
18807
        return 16;
18808
      case 3:
18809
        // op: Rt32
18810
        return 8;
18811
      case 0:
18812
        // op: Rdd32
18813
        return 0;
18814
      }
18815
      break;
18816
    }
18817
    case Hexagon::V6_vL32b_cur_npred_pi:
18818
    case Hexagon::V6_vL32b_cur_pred_pi:
18819
    case Hexagon::V6_vL32b_npred_pi:
18820
    case Hexagon::V6_vL32b_nt_cur_npred_pi:
18821
    case Hexagon::V6_vL32b_nt_cur_pred_pi:
18822
    case Hexagon::V6_vL32b_nt_npred_pi:
18823
    case Hexagon::V6_vL32b_nt_pred_pi:
18824
    case Hexagon::V6_vL32b_nt_tmp_npred_pi:
18825
    case Hexagon::V6_vL32b_nt_tmp_pred_pi:
18826
    case Hexagon::V6_vL32b_pred_pi:
18827
    case Hexagon::V6_vL32b_tmp_npred_pi:
18828
    case Hexagon::V6_vL32b_tmp_pred_pi: {
18829
      switch (OpNum) {
18830
      case 4:
18831
        // op: Ii
18832
        return 8;
18833
      case 2:
18834
        // op: Pv4
18835
        return 11;
18836
      case 0:
18837
        // op: Vd32
18838
        return 0;
18839
      case 1:
18840
        // op: Rx32
18841
        return 16;
18842
      }
18843
      break;
18844
    }
18845
    case Hexagon::L2_loadalignb_pbr:
18846
    case Hexagon::L2_loadalignb_pcr:
18847
    case Hexagon::L2_loadalignb_pr:
18848
    case Hexagon::L2_loadalignh_pbr:
18849
    case Hexagon::L2_loadalignh_pcr:
18850
    case Hexagon::L2_loadalignh_pr: {
18851
      switch (OpNum) {
18852
      case 4:
18853
        // op: Mu2
18854
        return 13;
18855
      case 0:
18856
        // op: Ryy32
18857
        return 0;
18858
      case 1:
18859
        // op: Rx32
18860
        return 16;
18861
      }
18862
      break;
18863
    }
18864
    case Hexagon::V6_vdeal:
18865
    case Hexagon::V6_vshuff: {
18866
      switch (OpNum) {
18867
      case 4:
18868
        // op: Rt32
18869
        return 16;
18870
      case 0:
18871
        // op: Vy32
18872
        return 8;
18873
      case 1:
18874
        // op: Vx32
18875
        return 0;
18876
      }
18877
      break;
18878
    }
18879
  }
18880
  std::string msg;
18881
  raw_string_ostream Msg(msg);
18882
  Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
18883
  report_fatal_error(Msg.str().c_str());
18884
}
18885
18886
#endif // GET_OPERAND_BIT_OFFSET
18887