/src/build/lib/Target/Hexagon/HexagonGenRegisterInfo.inc

Source (jump to first uncovered line)
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register Enum Values                                                *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM

namespace llvm {

class MCRegisterClass;
extern const MCRegisterClass HexagonMCRegisterClasses[];

namespace Hexagon {
enum {
  NoRegister,
  BADVA = 1,
  CCR = 2,
  CFGBASE = 3,
  CS = 4,
  DIAG = 5,
  ELR = 6,
  EVB = 7,
  FRAMEKEY = 8,
  FRAMELIMIT = 9,
  GELR = 10,
  GOSP = 11,
  GP = 12,
  GPCYCLEHI = 13,
  GPCYCLELO = 14,
  GSR = 15,
  HTID = 16,
  IMASK = 17,
  ISDBEN = 18,
  ISDBGPR = 19,
  ISDBMBXIN = 20,
  ISDBMBXOUT = 21,
  ISDBST = 22,
  MODECTL = 23,
  PC = 24,
  PCYCLEHI = 25,
  PCYCLELO = 26,
  PKTCOUNT = 27,
  PKTCOUNTHI = 28,
  PKTCOUNTLO = 29,
  PMUCFG = 30,
  PMUEVTCFG = 31,
  REV = 32,
  SSR = 33,
  STID = 34,
  SYSCFG = 35,
  UGP = 36,
  UPCYCLE = 37,
  UPCYCLEHI = 38,
  UPCYCLELO = 39,
  USR = 40,
  USR_OVF = 41,
  UTIMER = 42,
  UTIMERHI = 43,
  UTIMERLO = 44,
  VID = 45,
  VTMP = 46,
  BADVA0 = 47,
  BADVA1 = 48,
  BRKPTCFG0 = 49,
  BRKPTCFG1 = 50,
  BRKPTPC0 = 51,
  BRKPTPC1 = 52,
  C5 = 53,
  C8 = 54,
  CS0 = 55,
  CS1 = 56,
  D0 = 57,
  D1 = 58,
  D2 = 59,
  D3 = 60,
  D4 = 61,
  D5 = 62,
  D6 = 63,
  D7 = 64,
  D8 = 65,
  D9 = 66,
  D10 = 67,
  D11 = 68,
  D12 = 69,
  D13 = 70,
  D14 = 71,
  D15 = 72,
  G3 = 73,
  G4 = 74,
  G5 = 75,
  G6 = 76,
  G7 = 77,
  G8 = 78,
  G9 = 79,
  G10 = 80,
  G11 = 81,
  G12 = 82,
  G13 = 83,
  G14 = 84,
  G15 = 85,
  G20 = 86,
  G21 = 87,
  G22 = 88,
  G23 = 89,
  G30 = 90,
  G31 = 91,
  GPMUCNT0 = 92,
  GPMUCNT1 = 93,
  GPMUCNT2 = 94,
  GPMUCNT3 = 95,
  GPMUCNT4 = 96,
  GPMUCNT5 = 97,
  GPMUCNT6 = 98,
  GPMUCNT7 = 99,
  ISDBCFG0 = 100,
  ISDBCFG1 = 101,
  LC0 = 102,
  LC1 = 103,
  M0 = 104,
  M1 = 105,
  P0 = 106,
  P1 = 107,
  P2 = 108,
  P3 = 109,
  PMUCNT0 = 110,
  PMUCNT1 = 111,
  PMUCNT2 = 112,
  PMUCNT3 = 113,
  Q0 = 114,
  Q1 = 115,
  Q2 = 116,
  Q3 = 117,
  R0 = 118,
  R1 = 119,
  R2 = 120,
  R3 = 121,
  R4 = 122,
  R5 = 123,
  R6 = 124,
  R7 = 125,
  R8 = 126,
  R9 = 127,
  R10 = 128,
  R11 = 129,
  R12 = 130,
  R13 = 131,
  R14 = 132,
  R15 = 133,
  R16 = 134,
  R17 = 135,
  R18 = 136,
  R19 = 137,
  R20 = 138,
  R21 = 139,
  R22 = 140,
  R23 = 141,
  R24 = 142,
  R25 = 143,
  R26 = 144,
  R27 = 145,
  R28 = 146,
  R29 = 147,
  R30 = 148,
  R31 = 149,
  S11 = 150,
  S12 = 151,
  S13 = 152,
  S14 = 153,
  S15 = 154,
  S19 = 155,
  S20 = 156,
  S22 = 157,
  S23 = 158,
  S24 = 159,
  S25 = 160,
  S26 = 161,
  S35 = 162,
  S44 = 163,
  S45 = 164,
  S46 = 165,
  S47 = 166,
  S54 = 167,
  S55 = 168,
  S56 = 169,
  S57 = 170,
  S58 = 171,
  S59 = 172,
  S60 = 173,
  S61 = 174,
  S62 = 175,
  S63 = 176,
  S64 = 177,
  S65 = 178,
  S66 = 179,
  S67 = 180,
  S68 = 181,
  S69 = 182,
  S70 = 183,
  S71 = 184,
  S72 = 185,
  S73 = 186,
  S74 = 187,
  S75 = 188,
  S76 = 189,
  S77 = 190,
  S78 = 191,
  S79 = 192,
  S80 = 193,
  SA0 = 194,
  SA1 = 195,
  SGP0 = 196,
  SGP1 = 197,
  V0 = 198,
  V1 = 199,
  V2 = 200,
  V3 = 201,
  V4 = 202,
  V5 = 203,
  V6 = 204,
  V7 = 205,
  V8 = 206,
  V9 = 207,
  V10 = 208,
  V11 = 209,
  V12 = 210,
  V13 = 211,
  V14 = 212,
  V15 = 213,
  V16 = 214,
  V17 = 215,
  V18 = 216,
  V19 = 217,
  V20 = 218,
  V21 = 219,
  V22 = 220,
  V23 = 221,
  V24 = 222,
  V25 = 223,
  V26 = 224,
  V27 = 225,
  V28 = 226,
  V29 = 227,
  V30 = 228,
  V31 = 229,
  VF0 = 230,
  VF1 = 231,
  VF2 = 232,
  VF3 = 233,
  VF4 = 234,
  VF5 = 235,
  VF6 = 236,
  VF7 = 237,
  VF8 = 238,
  VF9 = 239,
  VF10 = 240,
  VF11 = 241,
  VF12 = 242,
  VF13 = 243,
  VF14 = 244,
  VF15 = 245,
  VF16 = 246,
  VF17 = 247,
  VF18 = 248,
  VF19 = 249,
  VF20 = 250,
  VF21 = 251,
  VF22 = 252,
  VF23 = 253,
  VF24 = 254,
  VF25 = 255,
  VF26 = 256,
  VF27 = 257,
  VF28 = 258,
  VF29 = 259,
  VF30 = 260,
  VF31 = 261,
  VFR0 = 262,
  VFR1 = 263,
  VFR2 = 264,
  VFR3 = 265,
  VFR4 = 266,
  VFR5 = 267,
  VFR6 = 268,
  VFR7 = 269,
  VFR8 = 270,
  VFR9 = 271,
  VFR10 = 272,
  VFR11 = 273,
  VFR12 = 274,
  VFR13 = 275,
  VFR14 = 276,
  VFR15 = 277,
  VFR16 = 278,
  VFR17 = 279,
  VFR18 = 280,
  VFR19 = 281,
  VFR20 = 282,
  VFR21 = 283,
  VFR22 = 284,
  VFR23 = 285,
  VFR24 = 286,
  VFR25 = 287,
  VFR26 = 288,
  VFR27 = 289,
  VFR28 = 290,
  VFR29 = 291,
  VFR30 = 292,
  VFR31 = 293,
  VQ0 = 294,
  VQ1 = 295,
  VQ2 = 296,
  VQ3 = 297,
  VQ4 = 298,
  VQ5 = 299,
  VQ6 = 300,
  VQ7 = 301,
  W0 = 302,
  W1 = 303,
  W2 = 304,
  W3 = 305,
  W4 = 306,
  W5 = 307,
  W6 = 308,
  W7 = 309,
  W8 = 310,
  W9 = 311,
  W10 = 312,
  W11 = 313,
  W12 = 314,
  W13 = 315,
  W14 = 316,
  W15 = 317,
  WR0 = 318,
  WR1 = 319,
  WR2 = 320,
  WR3 = 321,
  WR4 = 322,
  WR5 = 323,
  WR6 = 324,
  WR7 = 325,
  WR8 = 326,
  WR9 = 327,
  WR10 = 328,
  WR11 = 329,
  WR12 = 330,
  WR13 = 331,
  WR14 = 332,
  WR15 = 333,
  C1_0 = 334,
  C3_2 = 335,
  C5_4 = 336,
  C7_6 = 337,
  C9_8 = 338,
  C11_10 = 339,
  C17_16 = 340,
  G1_0 = 341,
  G3_2 = 342,
  G5_4 = 343,
  G7_6 = 344,
  G9_8 = 345,
  G11_10 = 346,
  G13_12 = 347,
  G15_14 = 348,
  G17_16 = 349,
  G19_18 = 350,
  G21_20 = 351,
  G23_22 = 352,
  G25_24 = 353,
  G27_26 = 354,
  G29_28 = 355,
  G31_30 = 356,
  P3_0 = 357,
  S3_2 = 358,
  S5_4 = 359,
  S7_6 = 360,
  S9_8 = 361,
  S11_10 = 362,
  S13_12 = 363,
  S15_14 = 364,
  S17_16 = 365,
  S19_18 = 366,
  S21_20 = 367,
  S23_22 = 368,
  S25_24 = 369,
  S27_26 = 370,
  S29_28 = 371,
  S31_30 = 372,
  S33_32 = 373,
  S35_34 = 374,
  S37_36 = 375,
  S39_38 = 376,
  S41_40 = 377,
  S43_42 = 378,
  S45_44 = 379,
  S47_46 = 380,
  S49_48 = 381,
  S51_50 = 382,
  S53_52 = 383,
  S55_54 = 384,
  S57_56 = 385,
  S59_58 = 386,
  S61_60 = 387,
  S63_62 = 388,
  S65_64 = 389,
  S67_66 = 390,
  S69_68 = 391,
  S71_70 = 392,
  S73_72 = 393,
  S75_74 = 394,
  S77_76 = 395,
  S79_78 = 396,
  SGP1_0 = 397,
  NUM_TARGET_REGS // 398
};
} // end namespace Hexagon

// Register classes

namespace Hexagon {
enum {
  UsrBitsRegClassID = 0,
  SysRegsRegClassID = 1,
  GuestRegsRegClassID = 2,
  IntRegsRegClassID = 3,
  CtrRegsRegClassID = 4,
  GeneralSubRegsRegClassID = 5,
  V62RegsRegClassID = 6,
  IntRegsLow8RegClassID = 7,
  CtrRegs_and_V62RegsRegClassID = 8,
  PredRegsRegClassID = 9,
  V62Regs_with_isub_hiRegClassID = 10,
  ModRegsRegClassID = 11,
  CtrRegs_with_subreg_overflowRegClassID = 12,
  V65RegsRegClassID = 13,
  SysRegs64RegClassID = 14,
  DoubleRegsRegClassID = 15,
  GuestRegs64RegClassID = 16,
  VectRegRevRegClassID = 17,
  CtrRegs64RegClassID = 18,
  GeneralDoubleLow8RegsRegClassID = 19,
  DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID = 20,
  CtrRegs64_and_V62RegsRegClassID = 21,
  CtrRegs64_with_isub_hi_in_ModRegsRegClassID = 22,
  HvxQRRegClassID = 23,
  HvxVRRegClassID = 24,
  HvxVR_and_V65RegsRegClassID = 25,
  HvxWRRegClassID = 26,
  HvxWR_and_VectRegRevRegClassID = 27,
  HvxVQRRegClassID = 28,

};
} // end namespace Hexagon


// Subregister indices

namespace Hexagon {
enum : uint16_t {
  NoSubRegister,
  isub_hi,  // 1
  isub_lo,  // 2
  subreg_overflow,  // 3
  vsub_fake,  // 4
  vsub_hi,  // 5
  vsub_lo,  // 6
  wsub_hi,  // 7
  wsub_lo,  // 8
  wsub_hi_then_vsub_fake, // 9
  wsub_hi_then_vsub_hi, // 10
  wsub_hi_then_vsub_lo, // 11
  NUM_TARGET_SUBREGS
};
} // end namespace Hexagon

// Register pressure sets enum.
namespace Hexagon {
enum RegisterPressureSets {
  HvxVR_and_V65Regs = 0,
  ModRegs = 1,
  PredRegs = 2,
  HvxQR = 3,
  IntRegsLow8 = 4,
  GeneralSubRegs = 5,
  IntRegs = 6,
  HvxVR = 7,
};
} // end namespace Hexagon

} // end namespace llvm

#endif // GET_REGINFO_ENUM

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* MC Register Information                                                    *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC

namespace llvm {

extern const int16_t HexagonRegDiffLists[] = {
  /* 0 */ 21, -304, 0,
  /* 3 */ -209, -158, 0,
  /* 6 */ -211, -111, 0,
  /* 9 */ -140, -92, 0,
  /* 12 */ -77, 0,
  /* 14 */ -76, 0,
  /* 16 */ -75, 0,
  /* 18 */ -74, 0,
  /* 20 */ -73, 0,
  /* 22 */ -72, 0,
  /* 24 */ -71, 0,
  /* 26 */ -70, 0,
  /* 28 */ -69, 0,
  /* 30 */ -68, 0,
  /* 32 */ -67, 0,
  /* 34 */ -66, 0,
  /* 36 */ -65, 0,
  /* 38 */ -64, 0,
  /* 40 */ -63, 0,
  /* 42 */ -62, 0,
  /* 44 */ -61, 0,
  /* 46 */ -52, 0,
  /* 48 */ -51, 0,
  /* 50 */ -327, -31, 0,
  /* 53 */ -284, -30, 0,
  /* 56 */ -324, -28, 0,
  /* 59 */ -303, -24, 0,
  /* 62 */ -21, 0,
  /* 64 */ 72, -16, 0,
  /* 67 */ -345, -15, 0,
  /* 70 */ 72, -15, 0,
  /* 73 */ 72, -14, 0,
  /* 76 */ 72, -13, 0,
  /* 79 */ 72, -12, 0,
  /* 82 */ 72, -11, 0,
  /* 85 */ 72, -10, 0,
  /* 88 */ 72, -9, 0,
  /* 91 */ 72, -8, 0,
  /* 94 */ -324, -2, 0,
  /* 97 */ -352, -1, 0,
  /* 100 */ -346, -1, 0,
  /* 103 */ -339, -1, 0,
  /* 106 */ -331, -1, 0,
  /* 109 */ -205, -1, 0,
  /* 112 */ -204, -1, 0,
  /* 115 */ 2, -1, 0,
  /* 118 */ -360, 1, 0,
  /* 121 */ -357, 1, 0,
  /* 124 */ -312, 1, 0,
  /* 127 */ -271, 1, 0,
  /* 130 */ -270, 1, 0,
  /* 133 */ -269, 1, 0,
  /* 136 */ -268, 1, 0,
  /* 139 */ -267, 1, 0,
  /* 142 */ -266, 1, 0,
  /* 145 */ -265, 1, 0,
  /* 148 */ -264, 1, 0,
  /* 151 */ -262, 1, 0,
  /* 154 */ -261, 1, 0,
  /* 157 */ -253, 1, 0,
  /* 160 */ -252, 1, 0,
  /* 163 */ -233, 1, 0,
  /* 166 */ -217, 1, 0,
  /* 169 */ -216, 1, 0,
  /* 172 */ -215, 1, 0,
  /* 175 */ -214, 1, 0,
  /* 178 */ -213, 1, 0,
  /* 181 */ -212, 1, 0,
  /* 184 */ -211, 1, 0,
  /* 187 */ -210, 1, 0,
  /* 190 */ -209, 1, 0,
  /* 193 */ -208, 1, 0,
  /* 196 */ -207, 1, 0,
  /* 199 */ -201, 1, 0,
  /* 202 */ 66, 1, 1, 1, 0,
  /* 207 */ 1, 1, 1, 15, 1, 0,
  /* 213 */ 1, 1, 1, 17, 1, 0,
  /* 219 */ 1, 1, 1, 19, 1, 0,
  /* 225 */ 1, 1, 1, 21, 1, 0,
  /* 231 */ 1, 1, 1, 23, 1, 0,
  /* 237 */ 1, 1, 1, 25, 1, 0,
  /* 243 */ 1, 1, 1, 27, 1, 0,
  /* 249 */ 1, 1, 1, 29, 1, 0,
  /* 255 */ 51, 1, 0,
  /* 258 */ 61, 1, 0,
  /* 261 */ 62, 1, 0,
  /* 264 */ 63, 1, 0,
  /* 267 */ 64, 1, 0,
  /* 270 */ 65, 1, 0,
  /* 273 */ 66, 1, 0,
  /* 276 */ 67, 1, 0,
  /* 279 */ 68, 1, 0,
  /* 282 */ 69, 1, 0,
  /* 285 */ 70, 1, 0,
  /* 288 */ 71, 1, 0,
  /* 291 */ 72, 1, 0,
  /* 294 */ 73, 1, 0,
  /* 297 */ 74, 1, 0,
  /* 300 */ 75, 1, 0,
  /* 303 */ 76, 1, 0,
  /* 306 */ 2, 0,
  /* 308 */ -331, 5, 0,
  /* 311 */ 15, 0,
  /* 313 */ -358, 16, 0,
  /* 316 */ 15, -90, 1, 17, 73, -89, 1, 16, 0,
  /* 325 */ -90, 1, 17, 0,
  /* 329 */ 14, -92, 1, 19, 73, -91, 1, 18, 0,
  /* 338 */ -92, 1, 19, 0,
  /* 342 */ 13, -94, 1, 21, 73, -93, 1, 20, 0,
  /* 351 */ -94, 1, 21, 0,
  /* 355 */ 12, -96, 1, 23, 73, -95, 1, 22, 0,
  /* 364 */ -96, 1, 23, 0,
  /* 368 */ 103, -8, 24, 0,
  /* 372 */ 104, -8, 24, 0,
  /* 376 */ 11, -98, 1, 25, 73, -97, 1, 24, 0,
  /* 385 */ 101, -9, 25, 0,
  /* 389 */ 102, -9, 25, 0,
  /* 393 */ 103, -9, 25, 0,
  /* 397 */ -98, 1, 25, 0,
  /* 401 */ 99, -10, 26, 0,
  /* 405 */ 100, -10, 26, 0,
  /* 409 */ 101, -10, 26, 0,
  /* 413 */ 10, -100, 1, 27, 73, -99, 1, 26, 0,
  /* 422 */ -366, 27, 0,
  /* 425 */ 97, -11, 27, 0,
  /* 429 */ 98, -11, 27, 0,
  /* 433 */ 99, -11, 27, 0,
  /* 437 */ -100, 1, 27, 0,
  /* 441 */ 95, -12, 28, 0,
  /* 445 */ 96, -12, 28, 0,
  /* 449 */ 97, -12, 28, 0,
  /* 453 */ 9, -102, 1, 29, 73, -101, 1, 28, 0,
  /* 462 */ 93, -13, 29, 0,
  /* 466 */ 94, -13, 29, 0,
  /* 470 */ 95, -13, 29, 0,
  /* 474 */ -102, 1, 29, 0,
  /* 478 */ 91, -14, 30, 0,
  /* 482 */ 92, -14, 30, 0,
  /* 486 */ 93, -14, 30, 0,
  /* 490 */ 8, -104, 1, 31, 73, -103, 1, 30, 0,
  /* 499 */ 89, -15, 31, 0,
  /* 503 */ 90, -15, 31, 0,
  /* 507 */ 91, -15, 31, 0,
  /* 511 */ -104, 1, 31, 0,
  /* 515 */ 88, -16, 32, 0,
  /* 519 */ 89, -16, 32, 0,
  /* 523 */ -105, 1, 48, 0,
  /* 527 */ -106, 1, 49, 0,
  /* 531 */ -107, 1, 50, 0,
  /* 535 */ -108, 1, 51, 0,
  /* 539 */ -109, 1, 52, 0,
  /* 543 */ -110, 1, 53, 0,
  /* 547 */ -111, 1, 54, 0,
  /* 551 */ -112, 1, 55, 0,
  /* 555 */ -113, 1, 56, 0,
  /* 559 */ -114, 1, 57, 0,
  /* 563 */ -115, 1, 58, 0,
  /* 567 */ -116, 1, 59, 0,
  /* 571 */ -117, 1, 60, 0,
  /* 575 */ -273, 61, 0,
  /* 578 */ -118, 1, 61, 0,
  /* 582 */ -331, 62, 0,
  /* 585 */ -119, 1, 62, 0,
  /* 589 */ -120, 1, 63, 0,
  /* 593 */ 72, 0,
  /* 595 */ -351, 78, 0,
  /* 598 */ 88, 0,
  /* 600 */ 92, 0,
  /* 602 */ 99, 0,
  /* 604 */ 111, 0,
  /* 606 */ -331, 120, 0,
  /* 609 */ -345, 133, 0,
  /* 612 */ 137, 0,
  /* 614 */ 140, 0,
  /* 616 */ 200, 0,
  /* 618 */ 201, 0,
  /* 620 */ 204, 0,
  /* 622 */ 205, 0,
  /* 624 */ 206, 0,
  /* 626 */ 207, 0,
  /* 628 */ 208, 0,
  /* 630 */ 209, 0,
  /* 632 */ 210, 0,
  /* 634 */ 211, 0,
  /* 636 */ 212, 0,
  /* 638 */ 213, 0,
  /* 640 */ 214, 0,
  /* 642 */ 215, 0,
  /* 644 */ 216, 0,
  /* 646 */ 217, 0,
  /* 648 */ 232, 0,
  /* 650 */ 233, 0,
  /* 652 */ 251, 0,
  /* 654 */ 252, 0,
  /* 656 */ 253, 0,
  /* 658 */ 260, 0,
  /* 660 */ 261, 0,
  /* 662 */ 262, 0,
  /* 664 */ 263, 0,
  /* 666 */ 264, 0,
  /* 668 */ 265, 0,
  /* 670 */ 266, 0,
  /* 672 */ 267, 0,
  /* 674 */ 268, 0,
  /* 676 */ 269, 0,
  /* 678 */ 270, 0,
  /* 680 */ 271, 0,
  /* 682 */ 273, 0,
  /* 684 */ 283, 0,
  /* 686 */ 284, 0,
  /* 688 */ 303, 0,
  /* 690 */ 311, 0,
  /* 692 */ 312, 0,
  /* 694 */ 314, 0,
  /* 696 */ 322, 0,
  /* 698 */ 324, 0,
  /* 700 */ 326, 0,
  /* 702 */ 327, 0,
  /* 704 */ 331, 0,
  /* 706 */ 332, 0,
  /* 708 */ 339, 0,
  /* 710 */ 340, 0,
  /* 712 */ 342, 0,
  /* 714 */ 345, 0,
  /* 716 */ 346, 0,
  /* 718 */ 347, 0,
  /* 720 */ 351, 0,
  /* 722 */ 352, 0,
  /* 724 */ 353, 0,
  /* 726 */ 356, 0,
  /* 728 */ 357, 0,
  /* 730 */ 358, 0,
  /* 732 */ 359, 0,
  /* 734 */ 360, 0,
  /* 736 */ 366, 0,
  /* 738 */ 367, 0,
};

extern const LaneBitmask HexagonLaneMaskLists[] = {
  /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
  /* 3 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), LaneBitmask::getAll(),
  /* 6 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000002), LaneBitmask::getAll(),
  /* 12 */ LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000008), LaneBitmask::getAll(),
  /* 16 */ LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask::getAll(),
  /* 23 */ LaneBitmask(0x0000000000000004), LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
  /* 26 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
};

extern const uint16_t HexagonSubRegIdxLists[] = {
  /* 0 */ 2, 1, 0,
  /* 3 */ 3, 0,
  /* 5 */ 6, 5, 4, 0,
  /* 9 */ 8, 6, 5, 4, 7, 11, 10, 9, 0,
};

extern const MCRegisterInfo::SubRegCoveredBits HexagonSubRegIdxRanges[] = {
  { 65535, 65535 },
  { 32, 32 }, // isub_hi
  { 0, 32 },  // isub_lo
  { 0, 1 }, // subreg_overflow
  { 65535, 65535 }, // vsub_fake
  { 65535, 65535 }, // vsub_hi
  { 65535, 65535 }, // vsub_lo
  { 65535, 65535 }, // wsub_hi
  { 65535, 65535 }, // wsub_lo
  { 65535, 65535 }, // wsub_hi_then_vsub_fake
  { 65535, 65535 }, // wsub_hi_then_vsub_hi
  { 65535, 65535 }, // wsub_hi_then_vsub_lo
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char HexagonRegStrings[] = {
  /* 0 */ "D10\0"
  /* 4 */ "VF10\0"
  /* 9 */ "G10\0"
  /* 13 */ "VFR10\0"
  /* 19 */ "WR10\0"
  /* 24 */ "V10\0"
  /* 28 */ "W10\0"
  /* 32 */ "C11_10\0"
  /* 39 */ "G11_10\0"
  /* 46 */ "S11_10\0"
  /* 53 */ "VF20\0"
  /* 58 */ "G20\0"
  /* 62 */ "VFR20\0"
  /* 68 */ "S20\0"
  /* 72 */ "V20\0"
  /* 76 */ "G21_20\0"
  /* 83 */ "S21_20\0"
  /* 90 */ "VF30\0"
  /* 95 */ "G30\0"
  /* 99 */ "VFR30\0"
  /* 105 */ "V30\0"
  /* 109 */ "G31_30\0"
  /* 116 */ "S31_30\0"
  /* 123 */ "S41_40\0"
  /* 130 */ "S51_50\0"
  /* 137 */ "S60\0"
  /* 141 */ "S61_60\0"
  /* 148 */ "S70\0"
  /* 152 */ "S71_70\0"
  /* 159 */ "S80\0"
  /* 163 */ "SA0\0"
  /* 167 */ "BADVA0\0"
  /* 174 */ "LC0\0"
  /* 178 */ "BRKPTPC0\0"
  /* 187 */ "D0\0"
  /* 190 */ "VF0\0"
  /* 194 */ "ISDBCFG0\0"
  /* 203 */ "BRKPTCFG0\0"
  /* 213 */ "M0\0"
  /* 216 */ "SGP0\0"
  /* 221 */ "VQ0\0"
  /* 225 */ "VFR0\0"
  /* 230 */ "WR0\0"
  /* 234 */ "CS0\0"
  /* 238 */ "GPMUCNT0\0"
  /* 247 */ "V0\0"
  /* 250 */ "W0\0"
  /* 253 */ "C1_0\0"
  /* 258 */ "G1_0\0"
  /* 263 */ "SGP1_0\0"
  /* 270 */ "P3_0\0"
  /* 275 */ "D11\0"
  /* 279 */ "VF11\0"
  /* 284 */ "G11\0"
  /* 288 */ "VFR11\0"
  /* 294 */ "WR11\0"
  /* 299 */ "S11\0"
  /* 303 */ "V11\0"
  /* 307 */ "W11\0"
  /* 311 */ "VF21\0"
  /* 316 */ "G21\0"
  /* 320 */ "VFR21\0"
  /* 326 */ "V21\0"
  /* 330 */ "VF31\0"
  /* 335 */ "G31\0"
  /* 339 */ "VFR31\0"
  /* 345 */ "V31\0"
  /* 349 */ "S61\0"
  /* 353 */ "S71\0"
  /* 357 */ "SA1\0"
  /* 361 */ "BADVA1\0"
  /* 368 */ "LC1\0"
  /* 372 */ "BRKPTPC1\0"
  /* 381 */ "D1\0"
  /* 384 */ "VF1\0"
  /* 388 */ "ISDBCFG1\0"
  /* 397 */ "BRKPTCFG1\0"
  /* 407 */ "M1\0"
  /* 410 */ "SGP1\0"
  /* 415 */ "VQ1\0"
  /* 419 */ "VFR1\0"
  /* 424 */ "WR1\0"
  /* 428 */ "CS1\0"
  /* 432 */ "GPMUCNT1\0"
  /* 441 */ "V1\0"
  /* 444 */ "W1\0"
  /* 447 */ "D12\0"
  /* 451 */ "VF12\0"
  /* 456 */ "G12\0"
  /* 460 */ "VFR12\0"
  /* 466 */ "WR12\0"
  /* 471 */ "S12\0"
  /* 475 */ "V12\0"
  /* 479 */ "W12\0"
  /* 483 */ "G13_12\0"
  /* 490 */ "S13_12\0"
  /* 497 */ "VF22\0"
  /* 502 */ "G22\0"
  /* 506 */ "VFR22\0"
  /* 512 */ "S22\0"
  /* 516 */ "V22\0"
  /* 520 */ "G23_22\0"
  /* 527 */ "S23_22\0"
  /* 534 */ "S33_32\0"
  /* 541 */ "S43_42\0"
  /* 548 */ "S53_52\0"
  /* 555 */ "S62\0"
  /* 559 */ "S63_62\0"
  /* 566 */ "S72\0"
  /* 570 */ "S73_72\0"
  /* 577 */ "D2\0"
  /* 580 */ "VF2\0"
  /* 584 */ "P2\0"
  /* 587 */ "VQ2\0"
  /* 591 */ "VFR2\0"
  /* 596 */ "WR2\0"
  /* 600 */ "GPMUCNT2\0"
  /* 609 */ "V2\0"
  /* 612 */ "W2\0"
  /* 615 */ "C3_2\0"
  /* 620 */ "G3_2\0"
  /* 625 */ "S3_2\0"
  /* 630 */ "D13\0"
  /* 634 */ "VF13\0"
  /* 639 */ "G13\0"
  /* 643 */ "VFR13\0"
  /* 649 */ "WR13\0"
  /* 654 */ "S13\0"
  /* 658 */ "V13\0"
  /* 662 */ "W13\0"
  /* 666 */ "VF23\0"
  /* 671 */ "G23\0"
  /* 675 */ "VFR23\0"
  /* 681 */ "S23\0"
  /* 685 */ "V23\0"
  /* 689 */ "S63\0"
  /* 693 */ "S73\0"
  /* 697 */ "D3\0"
  /* 700 */ "VF3\0"
  /* 704 */ "G3\0"
  /* 707 */ "P3\0"
  /* 710 */ "VQ3\0"
  /* 714 */ "VFR3\0"
  /* 719 */ "WR3\0"
  /* 723 */ "GPMUCNT3\0"
  /* 732 */ "V3\0"
  /* 735 */ "W3\0"
  /* 738 */ "D14\0"
  /* 742 */ "VF14\0"
  /* 747 */ "G14\0"
  /* 751 */ "VFR14\0"
  /* 757 */ "WR14\0"
  /* 762 */ "S14\0"
  /* 766 */ "V14\0"
  /* 770 */ "W14\0"
  /* 774 */ "G15_14\0"
  /* 781 */ "S15_14\0"
  /* 788 */ "VF24\0"
  /* 793 */ "VFR24\0"
  /* 799 */ "S24\0"
  /* 803 */ "V24\0"
  /* 807 */ "G25_24\0"
  /* 814 */ "S25_24\0"
  /* 821 */ "S35_34\0"
  /* 828 */ "S44\0"
  /* 832 */ "S45_44\0"
  /* 839 */ "S54\0"
  /* 843 */ "S55_54\0"
  /* 850 */ "S64\0"
  /* 854 */ "S65_64\0"
  /* 861 */ "S74\0"
  /* 865 */ "S75_74\0"
  /* 872 */ "D4\0"
  /* 875 */ "VF4\0"
  /* 879 */ "G4\0"
  /* 882 */ "VQ4\0"
  /* 886 */ "VFR4\0"
  /* 891 */ "WR4\0"
  /* 895 */ "GPMUCNT4\0"
  /* 904 */ "V4\0"
  /* 907 */ "W4\0"
  /* 910 */ "C5_4\0"
  /* 915 */ "G5_4\0"
  /* 920 */ "S5_4\0"
  /* 925 */ "D15\0"
  /* 929 */ "VF15\0"
  /* 934 */ "G15\0"
  /* 938 */ "VFR15\0"
  /* 944 */ "WR15\0"
  /* 949 */ "S15\0"
  /* 953 */ "V15\0"
  /* 957 */ "W15\0"
  /* 961 */ "VF25\0"
  /* 966 */ "VFR25\0"
  /* 972 */ "S25\0"
  /* 976 */ "V25\0"
  /* 980 */ "S35\0"
  /* 984 */ "S45\0"
  /* 988 */ "S55\0"
  /* 992 */ "S65\0"
  /* 996 */ "S75\0"
  /* 1000 */ "C5\0"
  /* 1003 */ "D5\0"
  /* 1006 */ "VF5\0"
  /* 1010 */ "G5\0"
  /* 1013 */ "VQ5\0"
  /* 1017 */ "VFR5\0"
  /* 1022 */ "WR5\0"
  /* 1026 */ "GPMUCNT5\0"
  /* 1035 */ "V5\0"
  /* 1038 */ "W5\0"
  /* 1041 */ "VF16\0"
  /* 1046 */ "VFR16\0"
  /* 1052 */ "V16\0"
  /* 1056 */ "C17_16\0"
  /* 1063 */ "G17_16\0"
  /* 1070 */ "S17_16\0"
  /* 1077 */ "VF26\0"
  /* 1082 */ "VFR26\0"
  /* 1088 */ "S26\0"
  /* 1092 */ "V26\0"
  /* 1096 */ "G27_26\0"
  /* 1103 */ "S27_26\0"
  /* 1110 */ "S37_36\0"
  /* 1117 */ "S46\0"
  /* 1121 */ "S47_46\0"
  /* 1128 */ "S56\0"
  /* 1132 */ "S57_56\0"
  /* 1139 */ "S66\0"
  /* 1143 */ "S67_66\0"
  /* 1150 */ "S76\0"
  /* 1154 */ "S77_76\0"
  /* 1161 */ "D6\0"
  /* 1164 */ "VF6\0"
  /* 1168 */ "G6\0"
  /* 1171 */ "VQ6\0"
  /* 1175 */ "VFR6\0"
  /* 1180 */ "WR6\0"
  /* 1184 */ "GPMUCNT6\0"
  /* 1193 */ "V6\0"
  /* 1196 */ "W6\0"
  /* 1199 */ "C7_6\0"
  /* 1204 */ "G7_6\0"
  /* 1209 */ "S7_6\0"
  /* 1214 */ "VF17\0"
  /* 1219 */ "VFR17\0"
  /* 1225 */ "V17\0"
  /* 1229 */ "VF27\0"
  /* 1234 */ "VFR27\0"
  /* 1240 */ "V27\0"
  /* 1244 */ "S47\0"
  /* 1248 */ "S57\0"
  /* 1252 */ "S67\0"
  /* 1256 */ "S77\0"
  /* 1260 */ "D7\0"
  /* 1263 */ "VF7\0"
  /* 1267 */ "G7\0"
  /* 1270 */ "VQ7\0"
  /* 1274 */ "VFR7\0"
  /* 1279 */ "WR7\0"
  /* 1283 */ "GPMUCNT7\0"
  /* 1292 */ "V7\0"
  /* 1295 */ "W7\0"
  /* 1298 */ "VF18\0"
  /* 1303 */ "VFR18\0"
  /* 1309 */ "V18\0"
  /* 1313 */ "G19_18\0"
  /* 1320 */ "S19_18\0"
  /* 1327 */ "VF28\0"
  /* 1332 */ "VFR28\0"
  /* 1338 */ "V28\0"
  /* 1342 */ "G29_28\0"
  /* 1349 */ "S29_28\0"
  /* 1356 */ "S39_38\0"
  /* 1363 */ "S49_48\0"
  /* 1370 */ "S58\0"
  /* 1374 */ "S59_58\0"
  /* 1381 */ "S68\0"
  /* 1385 */ "S69_68\0"
  /* 1392 */ "S78\0"
  /* 1396 */ "S79_78\0"
  /* 1403 */ "C8\0"
  /* 1406 */ "D8\0"
  /* 1409 */ "VF8\0"
  /* 1413 */ "G8\0"
  /* 1416 */ "VFR8\0"
  /* 1421 */ "WR8\0"
  /* 1425 */ "V8\0"
  /* 1428 */ "W8\0"
  /* 1431 */ "C9_8\0"
  /* 1436 */ "G9_8\0"
  /* 1441 */ "S9_8\0"
  /* 1446 */ "VF19\0"
  /* 1451 */ "VFR19\0"
  /* 1457 */ "S19\0"
  /* 1461 */ "V19\0"
  /* 1465 */ "VF29\0"
  /* 1470 */ "VFR29\0"
  /* 1476 */ "V29\0"
  /* 1480 */ "S59\0"
  /* 1484 */ "S69\0"
  /* 1488 */ "S79\0"
  /* 1492 */ "D9\0"
  /* 1495 */ "VF9\0"
  /* 1499 */ "G9\0"
  /* 1502 */ "VFR9\0"
  /* 1507 */ "WR9\0"
  /* 1511 */ "V9\0"
  /* 1514 */ "W9\0"
  /* 1517 */ "BADVA\0"
  /* 1523 */ "EVB\0"
  /* 1527 */ "PC\0"
  /* 1530 */ "HTID\0"
  /* 1535 */ "STID\0"
  /* 1540 */ "VID\0"
  /* 1544 */ "UPCYCLE\0"
  /* 1552 */ "CFGBASE\0"
  /* 1560 */ "USR_OVF\0"
  /* 1568 */ "DIAG\0"
  /* 1573 */ "SYSCFG\0"
  /* 1580 */ "PMUEVTCFG\0"
  /* 1590 */ "PMUCFG\0"
  /* 1597 */ "GPCYCLEHI\0"
  /* 1607 */ "UPCYCLEHI\0"
  /* 1617 */ "UTIMERHI\0"
  /* 1626 */ "PKTCOUNTHI\0"
  /* 1637 */ "IMASK\0"
  /* 1643 */ "MODECTL\0"
  /* 1651 */ "ISDBEN\0"
  /* 1658 */ "ISDBMBXIN\0"
  /* 1668 */ "GPCYCLELO\0"
  /* 1678 */ "UPCYCLELO\0"
  /* 1688 */ "UTIMERLO\0"
  /* 1697 */ "PKTCOUNTLO\0"
  /* 1708 */ "UGP\0"
  /* 1712 */ "VTMP\0"
  /* 1717 */ "GOSP\0"
  /* 1722 */ "CCR\0"
  /* 1726 */ "UTIMER\0"
  /* 1733 */ "GELR\0"
  /* 1738 */ "ISDBGPR\0"
  /* 1746 */ "GSR\0"
  /* 1750 */ "SSR\0"
  /* 1754 */ "USR\0"
  /* 1758 */ "CS\0"
  /* 1761 */ "FRAMELIMIT\0"
  /* 1772 */ "PKTCOUNT\0"
  /* 1781 */ "ISDBST\0"
  /* 1788 */ "ISDBMBXOUT\0"
  /* 1799 */ "REV\0"
  /* 1803 */ "FRAMEKEY\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const MCRegisterDesc HexagonRegDesc[] = { // Descriptors
  { 3, 0, 0, 0, 0, 0 },
  { 1517, 2, 734, 2, 8192, 24 },
  { 1722, 2, 730, 2, 8193, 24 },
  { 1552, 2, 738, 2, 8194, 24 },
  { 1758, 255, 2, 0, 487427, 0 },
  { 1568, 2, 736, 2, 8197, 24 },
  { 1734, 2, 722, 2, 8198, 24 },
  { 1523, 2, 730, 2, 8199, 24 },
  { 1803, 2, 706, 2, 8200, 24 },
  { 1761, 2, 704, 2, 8201, 24 },
  { 1733, 2, 704, 2, 8202, 24 },
  { 1717, 2, 704, 2, 8203, 24 },
  { 1709, 2, 702, 2, 8204, 24 },
  { 1597, 2, 710, 2, 8205, 24 },
  { 1668, 2, 708, 2, 8206, 24 },
  { 1746, 2, 700, 2, 8207, 24 },
  { 1530, 2, 714, 2, 8208, 24 },
  { 1637, 2, 714, 2, 8209, 24 },
  { 1651, 2, 734, 2, 8210, 24 },
  { 1738, 2, 732, 2, 8211, 24 },
  { 1658, 2, 728, 2, 8212, 24 },
  { 1788, 2, 726, 2, 8213, 24 },
  { 1781, 2, 720, 2, 8214, 24 },
  { 1643, 2, 712, 2, 8215, 24 },
  { 1527, 2, 694, 2, 8216, 24 },
  { 1598, 2, 718, 2, 8217, 24 },
  { 1669, 2, 716, 2, 8218, 24 },
  { 1772, 115, 2, 0, 487451, 0 },
  { 1626, 2, 98, 2, 8220, 24 },
  { 1697, 2, 95, 2, 8219, 24 },
  { 1590, 2, 724, 2, 8221, 24 },
  { 1580, 2, 722, 2, 8222, 24 },
  { 1799, 2, 708, 2, 8223, 24 },
  { 1750, 2, 702, 2, 8224, 24 },
  { 1535, 2, 698, 2, 8225, 24 },
  { 1573, 2, 704, 2, 8226, 24 },
  { 1708, 2, 688, 2, 8227, 24 },
  { 1544, 115, 2, 0, 487460, 0 },
  { 1607, 2, 98, 2, 8229, 24 },
  { 1678, 2, 95, 2, 8228, 24 },
  { 1754, 119, 2, 3, 487462, 23 },
  { 1560, 2, 98, 2, 8230, 24 },
  { 1726, 115, 2, 0, 487464, 0 },
  { 1617, 2, 98, 2, 8233, 24 },
  { 1688, 2, 95, 2, 8232, 24 },
  { 1540, 2, 696, 2, 8234, 24 },
  { 1712, 2, 2, 2, 8235, 24 },
  { 167, 2, 692, 2, 8236, 24 },
  { 361, 2, 690, 2, 8237, 24 },
  { 203, 2, 700, 2, 8238, 24 },
  { 397, 2, 700, 2, 8239, 24 },
  { 178, 2, 698, 2, 8240, 24 },
  { 372, 2, 698, 2, 8241, 24 },
  { 1000, 2, 684, 2, 8242, 24 },
  { 1403, 2, 686, 2, 8231, 24 },
  { 234, 2, 48, 2, 8195, 24 },
  { 428, 2, 46, 2, 8196, 24 },
  { 187, 258, 2, 0, 487475, 0 },
  { 381, 261, 2, 0, 487477, 0 },
  { 577, 264, 2, 0, 487479, 0 },
  { 697, 267, 2, 0, 487481, 0 },
  { 872, 270, 2, 0, 487483, 0 },
  { 1003, 273, 2, 0, 487485, 0 },
  { 1161, 276, 2, 0, 487487, 0 },
  { 1260, 279, 2, 0, 487489, 0 },
  { 1406, 282, 2, 0, 487491, 0 },
  { 1492, 285, 2, 0, 487493, 0 },
  { 0, 288, 2, 0, 487495, 0 },
  { 275, 291, 2, 0, 487497, 0 },
  { 447, 294, 2, 0, 487499, 0 },
  { 630, 297, 2, 0, 487501, 0 },
  { 738, 300, 2, 0, 487503, 0 },
  { 925, 303, 2, 0, 487505, 0 },
  { 704, 2, 676, 2, 8275, 24 },
  { 879, 2, 676, 2, 8276, 24 },
  { 1010, 2, 674, 2, 8277, 24 },
  { 1168, 2, 674, 2, 8278, 24 },
  { 1267, 2, 672, 2, 8279, 24 },
  { 1413, 2, 672, 2, 8280, 24 },
  { 1499, 2, 670, 2, 8281, 24 },
  { 9, 2, 670, 2, 8282, 24 },
  { 284, 2, 668, 2, 8283, 24 },
  { 456, 2, 668, 2, 8284, 24 },
  { 639, 2, 666, 2, 8285, 24 },
  { 747, 2, 666, 2, 8286, 24 },
  { 934, 2, 664, 2, 8287, 24 },
  { 58, 2, 668, 2, 8288, 24 },
  { 316, 2, 666, 2, 8289, 24 },
  { 502, 2, 666, 2, 8290, 24 },
  { 671, 2, 664, 2, 8291, 24 },
  { 95, 2, 670, 2, 8292, 24 },
  { 335, 2, 668, 2, 8293, 24 },
  { 238, 2, 662, 2, 8294, 24 },
  { 432, 2, 660, 2, 8295, 24 },
  { 600, 2, 660, 2, 8296, 24 },
  { 723, 2, 658, 2, 8297, 24 },
  { 895, 2, 656, 2, 8298, 24 },
  { 1026, 2, 654, 2, 8299, 24 },
  { 1184, 2, 654, 2, 8300, 24 },
  { 1283, 2, 652, 2, 8301, 24 },
  { 194, 2, 682, 2, 8302, 24 },
  { 388, 2, 682, 2, 8303, 24 },
  { 174, 2, 648, 2, 8304, 24 },
  { 368, 2, 648, 2, 8305, 24 },
  { 213, 2, 650, 2, 8306, 24 },
  { 407, 2, 648, 2, 8307, 24 },
  { 218, 2, 2, 2, 8308, 24 },
  { 412, 2, 2, 2, 8309, 24 },
  { 584, 2, 2, 2, 8310, 24 },
  { 707, 2, 2, 2, 8311, 24 },
  { 239, 2, 680, 2, 8312, 24 },
  { 433, 2, 678, 2, 8313, 24 },
  { 601, 2, 678, 2, 8314, 24 },
  { 724, 2, 676, 2, 8315, 24 },
  { 222, 2, 2, 2, 8316, 24 },
  { 416, 2, 2, 2, 8317, 24 },
  { 588, 2, 2, 2, 8318, 24 },
  { 711, 2, 2, 2, 8319, 24 },
  { 227, 2, 44, 2, 8243, 24 },
  { 421, 2, 42, 2, 8244, 24 },
  { 593, 2, 42, 2, 8245, 24 },
  { 716, 2, 40, 2, 8246, 24 },
  { 888, 2, 40, 2, 8247, 24 },
  { 1019, 2, 38, 2, 8248, 24 },
  { 1177, 2, 38, 2, 8249, 24 },
  { 1276, 2, 36, 2, 8250, 24 },
  { 1418, 2, 36, 2, 8251, 24 },
  { 1504, 2, 34, 2, 8252, 24 },
  { 15, 2, 34, 2, 8253, 24 },
  { 290, 2, 32, 2, 8254, 24 },
  { 462, 2, 32, 2, 8255, 24 },
  { 645, 2, 30, 2, 8256, 24 },
  { 753, 2, 30, 2, 8257, 24 },
  { 940, 2, 28, 2, 8258, 24 },
  { 1048, 2, 28, 2, 8259, 24 },
  { 1221, 2, 26, 2, 8260, 24 },
  { 1305, 2, 26, 2, 8261, 24 },
  { 1453, 2, 24, 2, 8262, 24 },
  { 64, 2, 24, 2, 8263, 24 },
  { 322, 2, 22, 2, 8264, 24 },
  { 508, 2, 22, 2, 8265, 24 },
  { 677, 2, 20, 2, 8266, 24 },
  { 795, 2, 20, 2, 8267, 24 },
  { 968, 2, 18, 2, 8268, 24 },
  { 1084, 2, 18, 2, 8269, 24 },
  { 1236, 2, 16, 2, 8270, 24 },
  { 1334, 2, 16, 2, 8271, 24 },
  { 1472, 2, 14, 2, 8272, 24 },
  { 101, 2, 14, 2, 8273, 24 },
  { 341, 2, 12, 2, 8274, 24 },
  { 299, 2, 636, 2, 8320, 24 },
  { 471, 2, 636, 2, 8321, 24 },
  { 654, 2, 634, 2, 8322, 24 },
  { 762, 2, 634, 2, 8323, 24 },
  { 949, 2, 632, 2, 8324, 24 },
  { 1457, 2, 634, 2, 8325, 24 },
  { 68, 2, 634, 2, 8326, 24 },
  { 512, 2, 634, 2, 8327, 24 },
  { 681, 2, 632, 2, 8328, 24 },
  { 799, 2, 632, 2, 8329, 24 },
  { 972, 2, 630, 2, 8330, 24 },
  { 1088, 2, 630, 2, 8331, 24 },
  { 980, 2, 636, 2, 8332, 24 },
  { 828, 2, 644, 2, 8333, 24 },
  { 984, 2, 642, 2, 8334, 24 },
  { 1117, 2, 642, 2, 8335, 24 },
  { 1244, 2, 640, 2, 8336, 24 },
  { 839, 2, 646, 2, 8337, 24 },
  { 988, 2, 644, 2, 8338, 24 },
  { 1128, 2, 644, 2, 8339, 24 },
  { 1248, 2, 642, 2, 8340, 24 },
  { 1370, 2, 642, 2, 8341, 24 },
  { 1480, 2, 640, 2, 8342, 24 },
  { 137, 2, 640, 2, 8343, 24 },
  { 349, 2, 638, 2, 8344, 24 },
  { 555, 2, 638, 2, 8345, 24 },
  { 689, 2, 636, 2, 8346, 24 },
  { 850, 2, 636, 2, 8347, 24 },
  { 992, 2, 634, 2, 8348, 24 },
  { 1139, 2, 634, 2, 8349, 24 },
  { 1252, 2, 632, 2, 8350, 24 },
  { 1381, 2, 632, 2, 8351, 24 },
  { 1484, 2, 630, 2, 8352, 24 },
  { 148, 2, 630, 2, 8353, 24 },
  { 353, 2, 628, 2, 8354, 24 },
  { 566, 2, 628, 2, 8355, 24 },
  { 693, 2, 626, 2, 8356, 24 },
  { 861, 2, 626, 2, 8357, 24 },
  { 996, 2, 624, 2, 8358, 24 },
  { 1150, 2, 624, 2, 8359, 24 },
  { 1256, 2, 622, 2, 8360, 24 },
  { 1392, 2, 622, 2, 8361, 24 },
  { 1488, 2, 620, 2, 8362, 24 },
  { 159, 2, 2, 2, 8363, 24 },
  { 163, 2, 614, 2, 8364, 24 },
  { 357, 2, 614, 2, 8365, 24 },
  { 216, 2, 618, 2, 8366, 24 },
  { 410, 2, 616, 2, 8367, 24 },
  { 247, 2, 372, 2, 8368, 24 },
  { 441, 2, 368, 2, 8369, 24 },
  { 609, 2, 393, 2, 8370, 24 },
  { 732, 2, 389, 2, 8371, 24 },
  { 904, 2, 389, 2, 8372, 24 },
  { 1035, 2, 385, 2, 8373, 24 },
  { 1193, 2, 409, 2, 8374, 24 },
  { 1292, 2, 405, 2, 8375, 24 },
  { 1425, 2, 405, 2, 8376, 24 },
  { 1511, 2, 401, 2, 8377, 24 },
  { 24, 2, 433, 2, 8378, 24 },
  { 303, 2, 429, 2, 8379, 24 },
  { 475, 2, 429, 2, 8380, 24 },
  { 658, 2, 425, 2, 8381, 24 },
  { 766, 2, 449, 2, 8382, 24 },
  { 953, 2, 445, 2, 8383, 24 },
  { 1052, 2, 445, 2, 8384, 24 },
  { 1225, 2, 441, 2, 8385, 24 },
  { 1309, 2, 470, 2, 8386, 24 },
  { 1461, 2, 466, 2, 8387, 24 },
  { 72, 2, 466, 2, 8388, 24 },
  { 326, 2, 462, 2, 8389, 24 },
  { 516, 2, 486, 2, 8390, 24 },
  { 685, 2, 482, 2, 8391, 24 },
  { 803, 2, 482, 2, 8392, 24 },
  { 976, 2, 478, 2, 8393, 24 },
  { 1092, 2, 507, 2, 8394, 24 },
  { 1240, 2, 503, 2, 8395, 24 },
  { 1338, 2, 503, 2, 8396, 24 },
  { 1476, 2, 499, 2, 8397, 24 },
  { 105, 2, 519, 2, 8398, 24 },
  { 345, 2, 515, 2, 8399, 24 },
  { 190, 2, 91, 2, 8400, 24 },
  { 384, 2, 88, 2, 8401, 24 },
  { 580, 2, 88, 2, 8402, 24 },
  { 700, 2, 85, 2, 8403, 24 },
  { 875, 2, 85, 2, 8404, 24 },
  { 1006, 2, 82, 2, 8405, 24 },
  { 1164, 2, 82, 2, 8406, 24 },
  { 1263, 2, 79, 2, 8407, 24 },
  { 1409, 2, 79, 2, 8408, 24 },
  { 1495, 2, 76, 2, 8409, 24 },
  { 4, 2, 76, 2, 8410, 24 },
  { 279, 2, 73, 2, 8411, 24 },
  { 451, 2, 73, 2, 8412, 24 },
  { 634, 2, 70, 2, 8413, 24 },
  { 742, 2, 70, 2, 8414, 24 },
  { 929, 2, 64, 2, 8415, 24 },
  { 1041, 2, 2, 2, 8416, 24 },
  { 1214, 2, 2, 2, 8417, 24 },
  { 1298, 2, 2, 2, 8418, 24 },
  { 1446, 2, 2, 2, 8419, 24 },
  { 53, 2, 2, 2, 8420, 24 },
  { 311, 2, 2, 2, 8421, 24 },
  { 497, 2, 2, 2, 8422, 24 },
  { 666, 2, 2, 2, 8423, 24 },
  { 788, 2, 2, 2, 8424, 24 },
  { 961, 2, 2, 2, 8425, 24 },
  { 1077, 2, 2, 2, 8426, 24 },
  { 1229, 2, 2, 2, 8427, 24 },
  { 1327, 2, 2, 2, 8428, 24 },
  { 1465, 2, 2, 2, 8429, 24 },
  { 90, 2, 2, 2, 8430, 24 },
  { 330, 2, 2, 2, 8431, 24 },
  { 225, 2, 557, 2, 8432, 24 },
  { 419, 2, 557, 2, 8433, 24 },
  { 591, 2, 557, 2, 8434, 24 },
  { 714, 2, 557, 2, 8435, 24 },
  { 886, 2, 557, 2, 8436, 24 },
  { 1017, 2, 557, 2, 8437, 24 },
  { 1175, 2, 557, 2, 8438, 24 },
  { 1274, 2, 557, 2, 8439, 24 },
  { 1416, 2, 557, 2, 8440, 24 },
  { 1502, 2, 557, 2, 8441, 24 },
  { 13, 2, 557, 2, 8442, 24 },
  { 288, 2, 557, 2, 8443, 24 },
  { 460, 2, 557, 2, 8444, 24 },
  { 643, 2, 557, 2, 8445, 24 },
  { 751, 2, 557, 2, 8446, 24 },
  { 938, 2, 557, 2, 8447, 24 },
  { 1046, 2, 2, 2, 8448, 24 },
  { 1219, 2, 2, 2, 8449, 24 },
  { 1303, 2, 2, 2, 8450, 24 },
  { 1451, 2, 2, 2, 8451, 24 },
  { 62, 2, 2, 2, 8452, 24 },
  { 320, 2, 2, 2, 8453, 24 },
  { 506, 2, 2, 2, 8454, 24 },
  { 675, 2, 2, 2, 8455, 24 },
  { 793, 2, 2, 2, 8456, 24 },
  { 966, 2, 2, 2, 8457, 24 },
  { 1082, 2, 2, 2, 8458, 24 },
  { 1234, 2, 2, 2, 8459, 24 },
  { 1332, 2, 2, 2, 8460, 24 },
  { 1470, 2, 2, 2, 8461, 24 },
  { 99, 2, 2, 2, 8462, 24 },
  { 339, 2, 2, 2, 8463, 24 },
  { 221, 490, 2, 9, 1020080, 16 },
  { 415, 453, 2, 9, 995508, 16 },
  { 587, 413, 2, 9, 970936, 16 },
  { 710, 376, 2, 9, 946364, 16 },
  { 882, 355, 2, 9, 921792, 16 },
  { 1013, 342, 2, 9, 897220, 16 },
  { 1171, 329, 2, 9, 872648, 16 },
  { 1270, 316, 2, 9, 848076, 16 },
  { 250, 511, 92, 5, 2097328, 12 },
  { 444, 495, 89, 5, 2031794, 12 },
  { 612, 474, 89, 5, 1945780, 12 },
  { 735, 458, 86, 5, 1880246, 12 },
  { 907, 437, 86, 5, 1794232, 12 },
  { 1038, 418, 83, 5, 1716410, 12 },
  { 1196, 397, 83, 5, 1630396, 12 },
  { 1295, 381, 80, 5, 1564862, 12 },
  { 1428, 364, 80, 5, 1495232, 12 },
  { 1514, 360, 77, 5, 1478850, 12 },
  { 28, 351, 77, 5, 1441988, 12 },
  { 307, 347, 74, 5, 1425606, 12 },
  { 479, 338, 74, 5, 1388744, 12 },
  { 662, 334, 68, 5, 1372362, 12 },
  { 770, 325, 68, 5, 1335500, 12 },
  { 957, 321, 65, 5, 1319118, 12 },
  { 230, 589, 2, 5, 2416816, 12 },
  { 424, 585, 2, 5, 2400434, 12 },
  { 596, 578, 2, 5, 2371764, 12 },
  { 719, 571, 2, 5, 2343094, 12 },
  { 891, 567, 2, 5, 2326712, 12 },
  { 1022, 563, 2, 5, 2310330, 12 },
  { 1180, 559, 2, 5, 2293948, 12 },
  { 1279, 555, 2, 5, 2277566, 12 },
  { 1421, 551, 2, 5, 2261184, 12 },
  { 1507, 547, 2, 5, 2244802, 12 },
  { 19, 543, 2, 5, 2228420, 12 },
  { 294, 539, 2, 5, 2212038, 12 },
  { 466, 535, 2, 5, 2195656, 12 },
  { 649, 531, 2, 5, 2179274, 12 },
  { 757, 527, 2, 5, 2162892, 12 },
  { 944, 523, 2, 5, 2146510, 12 },
  { 253, 9, 2, 0, 2347120, 3 },
  { 615, 9, 2, 0, 2347121, 3 },
  { 910, 0, 2, 0, 827442, 6 },
  { 1199, 163, 2, 0, 487538, 0 },
  { 1431, 53, 2, 0, 1273880, 3 },
  { 32, 59, 2, 0, 1499148, 3 },
  { 1056, 106, 2, 0, 487432, 3 },
  { 258, 308, 2, 0, 1265674, 0 },
  { 620, 582, 2, 0, 2428939, 0 },
  { 915, 133, 2, 0, 487508, 0 },
  { 1204, 136, 2, 0, 487510, 0 },
  { 1436, 139, 2, 0, 487512, 0 },
  { 39, 142, 2, 0, 487514, 0 },
  { 483, 145, 2, 0, 487516, 0 },
  { 774, 148, 2, 0, 487518, 0 },
  { 1063, 157, 2, 0, 487530, 0 },
  { 1313, 160, 2, 0, 487532, 0 },
  { 76, 145, 2, 0, 487520, 0 },
  { 520, 148, 2, 0, 487522, 0 },
  { 807, 103, 2, 0, 487437, 3 },
  { 1096, 151, 2, 0, 487526, 0 },
  { 1342, 154, 2, 0, 487528, 0 },
  { 109, 142, 2, 0, 487524, 0 },
  { 270, 2, 62, 2, 831604, 26 },
  { 625, 56, 2, 0, 1732614, 3 },
  { 920, 124, 2, 0, 487468, 0 },
  { 1209, 50, 2, 0, 2052097, 3 },
  { 1441, 67, 2, 0, 1286144, 3 },
  { 46, 609, 2, 0, 2474001, 0 },
  { 490, 181, 2, 0, 487553, 0 },
  { 781, 184, 2, 0, 487555, 0 },
  { 1070, 313, 2, 0, 1286151, 0 },
  { 1320, 606, 2, 0, 2465826, 0 },
  { 83, 6, 2, 0, 2457642, 3 },
  { 527, 184, 2, 0, 487559, 0 },
  { 814, 187, 2, 0, 487561, 0 },
  { 1103, 3, 2, 0, 2506754, 3 },
  { 1349, 422, 2, 0, 1650693, 0 },
  { 116, 100, 2, 0, 487449, 3 },
  { 534, 595, 2, 0, 2449430, 0 },
  { 821, 575, 2, 0, 1900655, 0 },
  { 1110, 94, 2, 0, 1253422, 3 },
  { 1356, 94, 2, 0, 1253423, 3 },
  { 123, 121, 2, 0, 487444, 0 },
  { 541, 118, 2, 0, 487442, 0 },
  { 832, 169, 2, 0, 487565, 0 },
  { 1121, 172, 2, 0, 487567, 0 },
  { 1363, 127, 2, 0, 487544, 0 },
  { 130, 130, 2, 0, 487546, 0 },
  { 548, 97, 2, 0, 487453, 3 },
  { 843, 166, 2, 0, 487569, 0 },
  { 1132, 169, 2, 0, 487571, 0 },
  { 1374, 172, 2, 0, 487573, 0 },
  { 141, 175, 2, 0, 487575, 0 },
  { 559, 178, 2, 0, 487577, 0 },
  { 854, 181, 2, 0, 487579, 0 },
  { 1143, 184, 2, 0, 487581, 0 },
  { 1385, 187, 2, 0, 487583, 0 },
  { 152, 190, 2, 0, 487585, 0 },
  { 570, 193, 2, 0, 487587, 0 },
  { 865, 196, 2, 0, 487589, 0 },
  { 1154, 109, 2, 0, 487591, 3 },
  { 1396, 112, 2, 0, 487593, 3 },
  { 263, 199, 2, 0, 487598, 0 },
};

extern const MCPhysReg HexagonRegUnitRoots[][2] = {
  { Hexagon::BADVA },
  { Hexagon::CCR },
  { Hexagon::CFGBASE },
  { Hexagon::CS0 },
  { Hexagon::CS1 },
  { Hexagon::DIAG },
  { Hexagon::ELR },
  { Hexagon::EVB },
  { Hexagon::FRAMEKEY },
  { Hexagon::FRAMELIMIT },
  { Hexagon::GELR },
  { Hexagon::GOSP },
  { Hexagon::GP },
  { Hexagon::GPCYCLEHI },
  { Hexagon::GPCYCLELO },
  { Hexagon::GSR },
  { Hexagon::HTID },
  { Hexagon::IMASK },
  { Hexagon::ISDBEN },
  { Hexagon::ISDBGPR },
  { Hexagon::ISDBMBXIN },
  { Hexagon::ISDBMBXOUT },
  { Hexagon::ISDBST },
  { Hexagon::MODECTL },
  { Hexagon::PC },
  { Hexagon::PCYCLEHI },
  { Hexagon::PCYCLELO },
  { Hexagon::PKTCOUNTLO },
  { Hexagon::PKTCOUNTHI },
  { Hexagon::PMUCFG },
  { Hexagon::PMUEVTCFG },
  { Hexagon::REV },
  { Hexagon::SSR },
  { Hexagon::STID },
  { Hexagon::SYSCFG },
  { Hexagon::UGP },
  { Hexagon::UPCYCLELO },
  { Hexagon::UPCYCLEHI },
  { Hexagon::USR_OVF },
  { Hexagon::USR, Hexagon::C8 },
  { Hexagon::UTIMERLO },
  { Hexagon::UTIMERHI },
  { Hexagon::VID },
  { Hexagon::VTMP },
  { Hexagon::BADVA0 },
  { Hexagon::BADVA1 },
  { Hexagon::BRKPTCFG0 },
  { Hexagon::BRKPTCFG1 },
  { Hexagon::BRKPTPC0 },
  { Hexagon::BRKPTPC1 },
  { Hexagon::C5 },
  { Hexagon::R0 },
  { Hexagon::R1 },
  { Hexagon::R2 },
  { Hexagon::R3 },
  { Hexagon::R4 },
  { Hexagon::R5 },
  { Hexagon::R6 },
  { Hexagon::R7 },
  { Hexagon::R8 },
  { Hexagon::R9 },
  { Hexagon::R10 },
  { Hexagon::R11 },
  { Hexagon::R12 },
  { Hexagon::R13 },
  { Hexagon::R14 },
  { Hexagon::R15 },
  { Hexagon::R16 },
  { Hexagon::R17 },
  { Hexagon::R18 },
  { Hexagon::R19 },
  { Hexagon::R20 },
  { Hexagon::R21 },
  { Hexagon::R22 },
  { Hexagon::R23 },
  { Hexagon::R24 },
  { Hexagon::R25 },
  { Hexagon::R26 },
  { Hexagon::R27 },
  { Hexagon::R28 },
  { Hexagon::R29 },
  { Hexagon::R30 },
  { Hexagon::R31 },
  { Hexagon::G3 },
  { Hexagon::G4 },
  { Hexagon::G5 },
  { Hexagon::G6 },
  { Hexagon::G7 },
  { Hexagon::G8 },
  { Hexagon::G9 },
  { Hexagon::G10 },
  { Hexagon::G11 },
  { Hexagon::G12 },
  { Hexagon::G13 },
  { Hexagon::G14 },
  { Hexagon::G15 },
  { Hexagon::G20 },
  { Hexagon::G21 },
  { Hexagon::G22 },
  { Hexagon::G23 },
  { Hexagon::G30 },
  { Hexagon::G31 },
  { Hexagon::GPMUCNT0 },
  { Hexagon::GPMUCNT1 },
  { Hexagon::GPMUCNT2 },
  { Hexagon::GPMUCNT3 },
  { Hexagon::GPMUCNT4 },
  { Hexagon::GPMUCNT5 },
  { Hexagon::GPMUCNT6 },
  { Hexagon::GPMUCNT7 },
  { Hexagon::ISDBCFG0 },
  { Hexagon::ISDBCFG1 },
  { Hexagon::LC0 },
  { Hexagon::LC1 },
  { Hexagon::M0 },
  { Hexagon::M1 },
  { Hexagon::P0, Hexagon::P3_0 },
  { Hexagon::P1, Hexagon::P3_0 },
  { Hexagon::P2, Hexagon::P3_0 },
  { Hexagon::P3, Hexagon::P3_0 },
  { Hexagon::PMUCNT0 },
  { Hexagon::PMUCNT1 },
  { Hexagon::PMUCNT2 },
  { Hexagon::PMUCNT3 },
  { Hexagon::Q0 },
  { Hexagon::Q1 },
  { Hexagon::Q2 },
  { Hexagon::Q3 },
  { Hexagon::S11 },
  { Hexagon::S12 },
  { Hexagon::S13 },
  { Hexagon::S14 },
  { Hexagon::S15 },
  { Hexagon::S19 },
  { Hexagon::S20 },
  { Hexagon::S22 },
  { Hexagon::S23 },
  { Hexagon::S24 },
  { Hexagon::S25 },
  { Hexagon::S26 },
  { Hexagon::S35 },
  { Hexagon::S44 },
  { Hexagon::S45 },
  { Hexagon::S46 },
  { Hexagon::S47 },
  { Hexagon::S54 },
  { Hexagon::S55 },
  { Hexagon::S56 },
  { Hexagon::S57 },
  { Hexagon::S58 },
  { Hexagon::S59 },
  { Hexagon::S60 },
  { Hexagon::S61 },
  { Hexagon::S62 },
  { Hexagon::S63 },
  { Hexagon::S64 },
  { Hexagon::S65 },
  { Hexagon::S66 },
  { Hexagon::S67 },
  { Hexagon::S68 },
  { Hexagon::S69 },
  { Hexagon::S70 },
  { Hexagon::S71 },
  { Hexagon::S72 },
  { Hexagon::S73 },
  { Hexagon::S74 },
  { Hexagon::S75 },
  { Hexagon::S76 },
  { Hexagon::S77 },
  { Hexagon::S78 },
  { Hexagon::S79 },
  { Hexagon::S80 },
  { Hexagon::SA0 },
  { Hexagon::SA1 },
  { Hexagon::SGP0 },
  { Hexagon::SGP1 },
  { Hexagon::V0 },
  { Hexagon::V1 },
  { Hexagon::V2 },
  { Hexagon::V3 },
  { Hexagon::V4 },
  { Hexagon::V5 },
  { Hexagon::V6 },
  { Hexagon::V7 },
  { Hexagon::V8 },
  { Hexagon::V9 },
  { Hexagon::V10 },
  { Hexagon::V11 },
  { Hexagon::V12 },
  { Hexagon::V13 },
  { Hexagon::V14 },
  { Hexagon::V15 },
  { Hexagon::V16 },
  { Hexagon::V17 },
  { Hexagon::V18 },
  { Hexagon::V19 },
  { Hexagon::V20 },
  { Hexagon::V21 },
  { Hexagon::V22 },
  { Hexagon::V23 },
  { Hexagon::V24 },
  { Hexagon::V25 },
  { Hexagon::V26 },
  { Hexagon::V27 },
  { Hexagon::V28 },
  { Hexagon::V29 },
  { Hexagon::V30 },
  { Hexagon::V31 },
  { Hexagon::VF0 },
  { Hexagon::VF1 },
  { Hexagon::VF2 },
  { Hexagon::VF3 },
  { Hexagon::VF4 },
  { Hexagon::VF5 },
  { Hexagon::VF6 },
  { Hexagon::VF7 },
  { Hexagon::VF8 },
  { Hexagon::VF9 },
  { Hexagon::VF10 },
  { Hexagon::VF11 },
  { Hexagon::VF12 },
  { Hexagon::VF13 },
  { Hexagon::VF14 },
  { Hexagon::VF15 },
  { Hexagon::VF16 },
  { Hexagon::VF17 },
  { Hexagon::VF18 },
  { Hexagon::VF19 },
  { Hexagon::VF20 },
  { Hexagon::VF21 },
  { Hexagon::VF22 },
  { Hexagon::VF23 },
  { Hexagon::VF24 },
  { Hexagon::VF25 },
  { Hexagon::VF26 },
  { Hexagon::VF27 },
  { Hexagon::VF28 },
  { Hexagon::VF29 },
  { Hexagon::VF30 },
  { Hexagon::VF31 },
  { Hexagon::VFR0 },
  { Hexagon::VFR1 },
  { Hexagon::VFR2 },
  { Hexagon::VFR3 },
  { Hexagon::VFR4 },
  { Hexagon::VFR5 },
  { Hexagon::VFR6 },
  { Hexagon::VFR7 },
  { Hexagon::VFR8 },
  { Hexagon::VFR9 },
  { Hexagon::VFR10 },
  { Hexagon::VFR11 },
  { Hexagon::VFR12 },
  { Hexagon::VFR13 },
  { Hexagon::VFR14 },
  { Hexagon::VFR15 },
  { Hexagon::VFR16 },
  { Hexagon::VFR17 },
  { Hexagon::VFR18 },
  { Hexagon::VFR19 },
  { Hexagon::VFR20 },
  { Hexagon::VFR21 },
  { Hexagon::VFR22 },
  { Hexagon::VFR23 },
  { Hexagon::VFR24 },
  { Hexagon::VFR25 },
  { Hexagon::VFR26 },
  { Hexagon::VFR27 },
  { Hexagon::VFR28 },
  { Hexagon::VFR29 },
  { Hexagon::VFR30 },
  { Hexagon::VFR31 },
};

namespace {     // Register classes...
  // UsrBits Register Class...
  const MCPhysReg UsrBits[] = {
    Hexagon::USR_OVF, 
  };

  // UsrBits Bit set.
  const uint8_t UsrBitsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 
  };

  // SysRegs Register Class...
  const MCPhysReg SysRegs[] = {
    Hexagon::SGP0, Hexagon::SGP1, Hexagon::STID, Hexagon::ELR, Hexagon::BADVA0, Hexagon::BADVA1, Hexagon::SSR, Hexagon::CCR, Hexagon::HTID, Hexagon::BADVA, Hexagon::IMASK, Hexagon::S11, Hexagon::S12, Hexagon::S13, Hexagon::S14, Hexagon::S15, Hexagon::S19, Hexagon::S23, Hexagon::S25, Hexagon::EVB, Hexagon::MODECTL, Hexagon::SYSCFG, Hexagon::S20, Hexagon::VID, Hexagon::S22, Hexagon::S24, Hexagon::S26, Hexagon::CFGBASE, Hexagon::DIAG, Hexagon::REV, Hexagon::PCYCLEHI, Hexagon::PCYCLELO, Hexagon::ISDBST, Hexagon::ISDBCFG0, Hexagon::ISDBCFG1, Hexagon::S35, Hexagon::BRKPTPC0, Hexagon::BRKPTCFG0, Hexagon::BRKPTPC1, Hexagon::BRKPTCFG1, Hexagon::ISDBMBXIN, Hexagon::ISDBMBXOUT, Hexagon::ISDBEN, Hexagon::ISDBGPR, Hexagon::S44, Hexagon::S45, Hexagon::S46, Hexagon::S47, Hexagon::PMUCNT0, Hexagon::PMUCNT1, Hexagon::PMUCNT2, Hexagon::PMUCNT3, Hexagon::PMUEVTCFG, Hexagon::PMUCFG, Hexagon::S54, Hexagon::S55, Hexagon::S56, Hexagon::S57, Hexagon::S58, Hexagon::S59, Hexagon::S60, Hexagon::S61, Hexagon::S62, Hexagon::S63, Hexagon::S64, Hexagon::S65, Hexagon::S66, Hexagon::S67, Hexagon::S68, Hexagon::S69, Hexagon::S70, Hexagon::S71, Hexagon::S72, Hexagon::S73, Hexagon::S74, Hexagon::S75, Hexagon::S76, Hexagon::S77, Hexagon::S78, Hexagon::S79, Hexagon::S80, 
  };

  // SysRegs Bit set.
  const uint8_t SysRegsBits[] = {
    0xee, 0x00, 0xff, 0xc6, 0x0f, 0xa0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xc0, 0x03, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x33, 
  };

  // GuestRegs Register Class...
  const MCPhysReg GuestRegs[] = {
    Hexagon::GELR, Hexagon::GSR, Hexagon::GOSP, Hexagon::G3, Hexagon::G4, Hexagon::G5, Hexagon::G6, Hexagon::G7, Hexagon::G8, Hexagon::G9, Hexagon::G10, Hexagon::G11, Hexagon::G12, Hexagon::G13, Hexagon::G14, Hexagon::G15, Hexagon::GPMUCNT4, Hexagon::GPMUCNT5, Hexagon::GPMUCNT6, Hexagon::GPMUCNT7, Hexagon::G20, Hexagon::G21, Hexagon::G22, Hexagon::G23, Hexagon::GPCYCLELO, Hexagon::GPCYCLEHI, Hexagon::GPMUCNT0, Hexagon::GPMUCNT1, Hexagon::GPMUCNT2, Hexagon::GPMUCNT3, Hexagon::G30, Hexagon::G31, 
  };

  // GuestRegs Bit set.
  const uint8_t GuestRegsBits[] = {
    0x00, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x0f, 
  };

  // IntRegs Register Class...
  const MCPhysReg IntRegs[] = {
    Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, Hexagon::R12, Hexagon::R13, Hexagon::R14, Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R10, Hexagon::R11, Hexagon::R29, Hexagon::R30, Hexagon::R31, 
  };

  // IntRegs Bit set.
  const uint8_t IntRegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
  };

  // CtrRegs Register Class...
  const MCPhysReg CtrRegs[] = {
    Hexagon::LC0, Hexagon::SA0, Hexagon::LC1, Hexagon::SA1, Hexagon::P3_0, Hexagon::C5, Hexagon::C8, Hexagon::PC, Hexagon::UGP, Hexagon::GP, Hexagon::CS0, Hexagon::CS1, Hexagon::UPCYCLELO, Hexagon::UPCYCLEHI, Hexagon::FRAMELIMIT, Hexagon::FRAMEKEY, Hexagon::PKTCOUNTLO, Hexagon::PKTCOUNTHI, Hexagon::UTIMERLO, Hexagon::UTIMERHI, Hexagon::M0, Hexagon::M1, Hexagon::USR, 
  };

  // CtrRegs Bit set.
  const uint8_t CtrRegsBits[] = {
    0x00, 0x13, 0x00, 0x31, 0xd0, 0x19, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 
  };

  // GeneralSubRegs Register Class...
  const MCPhysReg GeneralSubRegs[] = {
    Hexagon::R23, Hexagon::R22, Hexagon::R21, Hexagon::R20, Hexagon::R19, Hexagon::R18, Hexagon::R17, Hexagon::R16, Hexagon::R7, Hexagon::R6, Hexagon::R5, Hexagon::R4, Hexagon::R3, Hexagon::R2, Hexagon::R1, Hexagon::R0, 
  };

  // GeneralSubRegs Bit set.
  const uint8_t GeneralSubRegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 0xc0, 0x3f, 
  };

  // V62Regs Register Class...
  const MCPhysReg V62Regs[] = {
    Hexagon::FRAMELIMIT, Hexagon::FRAMEKEY, Hexagon::C17_16, Hexagon::PKTCOUNTLO, Hexagon::PKTCOUNTHI, Hexagon::PKTCOUNT, Hexagon::UTIMERLO, Hexagon::UTIMERHI, Hexagon::UTIMER, 
  };

  // V62Regs Bit set.
  const uint8_t V62RegsBits[] = {
    0x00, 0x03, 0x00, 0x38, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
  };

  // IntRegsLow8 Register Class...
  const MCPhysReg IntRegsLow8[] = {
    Hexagon::R7, Hexagon::R6, Hexagon::R5, Hexagon::R4, Hexagon::R3, Hexagon::R2, Hexagon::R1, Hexagon::R0, 
  };

  // IntRegsLow8 Bit set.
  const uint8_t IntRegsLow8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
  };

  // CtrRegs_and_V62Regs Register Class...
  const MCPhysReg CtrRegs_and_V62Regs[] = {
    Hexagon::FRAMELIMIT, Hexagon::FRAMEKEY, Hexagon::PKTCOUNTLO, Hexagon::PKTCOUNTHI, Hexagon::UTIMERLO, Hexagon::UTIMERHI, 
  };

  // CtrRegs_and_V62Regs Bit set.
  const uint8_t CtrRegs_and_V62RegsBits[] = {
    0x00, 0x03, 0x00, 0x30, 0x00, 0x18, 
  };

  // PredRegs Register Class...
  const MCPhysReg PredRegs[] = {
    Hexagon::P0, Hexagon::P1, Hexagon::P2, Hexagon::P3, 
  };

  // PredRegs Bit set.
  const uint8_t PredRegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
  };

  // V62Regs_with_isub_hi Register Class...
  const MCPhysReg V62Regs_with_isub_hi[] = {
    Hexagon::C17_16, Hexagon::PKTCOUNT, Hexagon::UTIMER, 
  };

  // V62Regs_with_isub_hi Bit set.
  const uint8_t V62Regs_with_isub_hiBits[] = {
    0x00, 0x00, 0x00, 0x08, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
  };

  // ModRegs Register Class...
  const MCPhysReg ModRegs[] = {
    Hexagon::M0, Hexagon::M1, 
  };

  // ModRegs Bit set.
  const uint8_t ModRegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 
  };

  // CtrRegs_with_subreg_overflow Register Class...
  const MCPhysReg CtrRegs_with_subreg_overflow[] = {
    Hexagon::USR, 
  };

  // CtrRegs_with_subreg_overflow Bit set.
  const uint8_t CtrRegs_with_subreg_overflowBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 
  };

  // V65Regs Register Class...
  const MCPhysReg V65Regs[] = {
    Hexagon::VTMP, 
  };

  // V65Regs Bit set.
  const uint8_t V65RegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 
  };

  // SysRegs64 Register Class...
  const MCPhysReg SysRegs64[] = {
    Hexagon::SGP1_0, Hexagon::S3_2, Hexagon::S5_4, Hexagon::S7_6, Hexagon::S9_8, Hexagon::S11_10, Hexagon::S13_12, Hexagon::S15_14, Hexagon::S17_16, Hexagon::S19_18, Hexagon::S21_20, Hexagon::S23_22, Hexagon::S25_24, Hexagon::S27_26, Hexagon::S29_28, Hexagon::S31_30, Hexagon::S33_32, Hexagon::S35_34, Hexagon::S37_36, Hexagon::S39_38, Hexagon::S41_40, Hexagon::S43_42, Hexagon::S45_44, Hexagon::S47_46, Hexagon::S49_48, Hexagon::S51_50, Hexagon::S53_52, Hexagon::S55_54, Hexagon::S57_56, Hexagon::S59_58, Hexagon::S61_60, Hexagon::S63_62, Hexagon::S65_64, Hexagon::S67_66, Hexagon::S69_68, Hexagon::S71_70, Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78, 
  };

  // SysRegs64 Bit set.
  const uint8_t SysRegs64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0xff, 0x3f, 
  };

  // DoubleRegs Register Class...
  const MCPhysReg DoubleRegs[] = {
    Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, Hexagon::D4, Hexagon::D6, Hexagon::D7, Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, Hexagon::D12, Hexagon::D13, Hexagon::D5, Hexagon::D14, Hexagon::D15, 
  };

  // DoubleRegs Bit set.
  const uint8_t DoubleRegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01, 
  };

  // GuestRegs64 Register Class...
  const MCPhysReg GuestRegs64[] = {
    Hexagon::G1_0, Hexagon::G3_2, Hexagon::G5_4, Hexagon::G7_6, Hexagon::G9_8, Hexagon::G11_10, Hexagon::G13_12, Hexagon::G15_14, Hexagon::G17_16, Hexagon::G19_18, Hexagon::G21_20, Hexagon::G23_22, Hexagon::G25_24, Hexagon::G27_26, Hexagon::G29_28, Hexagon::G31_30, 
  };

  // GuestRegs64 Bit set.
  const uint8_t GuestRegs64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
  };

  // VectRegRev Register Class...
  const MCPhysReg VectRegRev[] = {
    Hexagon::WR0, Hexagon::WR1, Hexagon::WR2, Hexagon::WR3, Hexagon::WR4, Hexagon::WR5, Hexagon::WR6, Hexagon::WR7, Hexagon::WR8, Hexagon::WR9, Hexagon::WR10, Hexagon::WR11, Hexagon::WR12, Hexagon::WR13, Hexagon::WR14, Hexagon::WR15, 
  };

  // VectRegRev Bit set.
  const uint8_t VectRegRevBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
  };

  // CtrRegs64 Register Class...
  const MCPhysReg CtrRegs64[] = {
    Hexagon::C1_0, Hexagon::C3_2, Hexagon::C5_4, Hexagon::C7_6, Hexagon::C9_8, Hexagon::C11_10, Hexagon::CS, Hexagon::UPCYCLE, Hexagon::C17_16, Hexagon::PKTCOUNT, Hexagon::UTIMER, 
  };

  // CtrRegs64 Bit set.
  const uint8_t CtrRegs64Bits[] = {
    0x10, 0x00, 0x00, 0x08, 0x20, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
  };

  // GeneralDoubleLow8Regs Register Class...
  const MCPhysReg GeneralDoubleLow8Regs[] = {
    Hexagon::D11, Hexagon::D10, Hexagon::D9, Hexagon::D8, Hexagon::D3, Hexagon::D2, Hexagon::D1, Hexagon::D0, 
  };

  // GeneralDoubleLow8Regs Bit set.
  const uint8_t GeneralDoubleLow8RegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x1e, 
  };

  // DoubleRegs_with_isub_hi_in_IntRegsLow8 Register Class...
  const MCPhysReg DoubleRegs_with_isub_hi_in_IntRegsLow8[] = {
    Hexagon::D3, Hexagon::D2, Hexagon::D1, Hexagon::D0, 
  };

  // DoubleRegs_with_isub_hi_in_IntRegsLow8 Bit set.
  const uint8_t DoubleRegs_with_isub_hi_in_IntRegsLow8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 
  };

  // CtrRegs64_and_V62Regs Register Class...
  const MCPhysReg CtrRegs64_and_V62Regs[] = {
    Hexagon::C17_16, Hexagon::PKTCOUNT, Hexagon::UTIMER, 
  };

  // CtrRegs64_and_V62Regs Bit set.
  const uint8_t CtrRegs64_and_V62RegsBits[] = {
    0x00, 0x00, 0x00, 0x08, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
  };

  // CtrRegs64_with_isub_hi_in_ModRegs Register Class...
  const MCPhysReg CtrRegs64_with_isub_hi_in_ModRegs[] = {
    Hexagon::C7_6, 
  };

  // CtrRegs64_with_isub_hi_in_ModRegs Bit set.
  const uint8_t CtrRegs64_with_isub_hi_in_ModRegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 
  };

  // HvxQR Register Class...
  const MCPhysReg HvxQR[] = {
    Hexagon::Q0, Hexagon::Q1, Hexagon::Q2, Hexagon::Q3, 
  };

  // HvxQR Bit set.
  const uint8_t HvxQRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
  };

  // HvxVR Register Class...
  const MCPhysReg HvxVR[] = {
    Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, Hexagon::V30, Hexagon::V31, Hexagon::VTMP, 
  };

  // HvxVR Bit set.
  const uint8_t HvxVRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
  };

  // HvxVR_and_V65Regs Register Class...
  const MCPhysReg HvxVR_and_V65Regs[] = {
    Hexagon::VTMP, 
  };

  // HvxVR_and_V65Regs Bit set.
  const uint8_t HvxVR_and_V65RegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 
  };

  // HvxWR Register Class...
  const MCPhysReg HvxWR[] = {
    Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15, Hexagon::WR0, Hexagon::WR1, Hexagon::WR2, Hexagon::WR3, Hexagon::WR4, Hexagon::WR5, Hexagon::WR6, Hexagon::WR7, Hexagon::WR8, Hexagon::WR9, Hexagon::WR10, Hexagon::WR11, Hexagon::WR12, Hexagon::WR13, Hexagon::WR14, Hexagon::WR15, 
  };

  // HvxWR Bit set.
  const uint8_t HvxWRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
  };

  // HvxWR_and_VectRegRev Register Class...
  const MCPhysReg HvxWR_and_VectRegRev[] = {
    Hexagon::WR0, Hexagon::WR1, Hexagon::WR2, Hexagon::WR3, Hexagon::WR4, Hexagon::WR5, Hexagon::WR6, Hexagon::WR7, Hexagon::WR8, Hexagon::WR9, Hexagon::WR10, Hexagon::WR11, Hexagon::WR12, Hexagon::WR13, Hexagon::WR14, Hexagon::WR15, 
  };

  // HvxWR_and_VectRegRev Bit set.
  const uint8_t HvxWR_and_VectRegRevBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
  };

  // HvxVQR Register Class...
  const MCPhysReg HvxVQR[] = {
    Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3, Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7, 
  };

  // HvxVQR Bit set.
  const uint8_t HvxVQRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
  };

} // end anonymous namespace


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char HexagonRegClassStrings[] = {
  /* 0 */ "CtrRegs64\0"
  /* 10 */ "SysRegs64\0"
  /* 20 */ "GuestRegs64\0"
  /* 32 */ "DoubleRegs_with_isub_hi_in_IntRegsLow8\0"
  /* 71 */ "HvxVQR\0"
  /* 78 */ "HvxQR\0"
  /* 84 */ "HvxVR\0"
  /* 90 */ "HvxWR\0"
  /* 96 */ "V62Regs_with_isub_hi\0"
  /* 117 */ "CtrRegs64_and_V62Regs\0"
  /* 139 */ "CtrRegs_and_V62Regs\0"
  /* 159 */ "HvxVR_and_V65Regs\0"
  /* 177 */ "GeneralDoubleLow8Regs\0"
  /* 199 */ "GeneralSubRegs\0"
  /* 214 */ "PredRegs\0"
  /* 223 */ "CtrRegs64_with_isub_hi_in_ModRegs\0"
  /* 257 */ "DoubleRegs\0"
  /* 268 */ "CtrRegs\0"
  /* 276 */ "SysRegs\0"
  /* 284 */ "IntRegs\0"
  /* 292 */ "GuestRegs\0"
  /* 302 */ "UsrBits\0"
  /* 310 */ "HvxWR_and_VectRegRev\0"
  /* 331 */ "CtrRegs_with_subreg_overflow\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const MCRegisterClass HexagonMCRegisterClasses[] = {
  { UsrBits, UsrBitsBits, 302, 1, sizeof(UsrBitsBits), Hexagon::UsrBitsRegClassID, 1, 1, false },
  { SysRegs, SysRegsBits, 276, 81, sizeof(SysRegsBits), Hexagon::SysRegsRegClassID, 32, 1, false },
  { GuestRegs, GuestRegsBits, 292, 32, sizeof(GuestRegsBits), Hexagon::GuestRegsRegClassID, 32, 1, false },
  { IntRegs, IntRegsBits, 284, 32, sizeof(IntRegsBits), Hexagon::IntRegsRegClassID, 32, 1, true },
  { CtrRegs, CtrRegsBits, 268, 23, sizeof(CtrRegsBits), Hexagon::CtrRegsRegClassID, 32, 1, false },
  { GeneralSubRegs, GeneralSubRegsBits, 199, 16, sizeof(GeneralSubRegsBits), Hexagon::GeneralSubRegsRegClassID, 32, 1, true },
  { V62Regs, V62RegsBits, 131, 9, sizeof(V62RegsBits), Hexagon::V62RegsRegClassID, 32, 1, false },
  { IntRegsLow8, IntRegsLow8Bits, 59, 8, sizeof(IntRegsLow8Bits), Hexagon::IntRegsLow8RegClassID, 32, 1, true },
  { CtrRegs_and_V62Regs, CtrRegs_and_V62RegsBits, 139, 6, sizeof(CtrRegs_and_V62RegsBits), Hexagon::CtrRegs_and_V62RegsRegClassID, 32, 1, false },
  { PredRegs, PredRegsBits, 214, 4, sizeof(PredRegsBits), Hexagon::PredRegsRegClassID, 32, 1, true },
  { V62Regs_with_isub_hi, V62Regs_with_isub_hiBits, 96, 3, sizeof(V62Regs_with_isub_hiBits), Hexagon::V62Regs_with_isub_hiRegClassID, 32, 1, false },
  { ModRegs, ModRegsBits, 249, 2, sizeof(ModRegsBits), Hexagon::ModRegsRegClassID, 32, 1, true },
  { CtrRegs_with_subreg_overflow, CtrRegs_with_subreg_overflowBits, 331, 1, sizeof(CtrRegs_with_subreg_overflowBits), Hexagon::CtrRegs_with_subreg_overflowRegClassID, 32, 1, false },
  { V65Regs, V65RegsBits, 169, 1, sizeof(V65RegsBits), Hexagon::V65RegsRegClassID, 32, 1, false },
  { SysRegs64, SysRegs64Bits, 10, 40, sizeof(SysRegs64Bits), Hexagon::SysRegs64RegClassID, 64, 1, false },
  { DoubleRegs, DoubleRegsBits, 257, 16, sizeof(DoubleRegsBits), Hexagon::DoubleRegsRegClassID, 64, 1, true },
  { GuestRegs64, GuestRegs64Bits, 20, 16, sizeof(GuestRegs64Bits), Hexagon::GuestRegs64RegClassID, 64, 1, false },
  { VectRegRev, VectRegRevBits, 320, 16, sizeof(VectRegRevBits), Hexagon::VectRegRevRegClassID, 64, 1, true },
  { CtrRegs64, CtrRegs64Bits, 0, 11, sizeof(CtrRegs64Bits), Hexagon::CtrRegs64RegClassID, 64, 1, false },
  { GeneralDoubleLow8Regs, GeneralDoubleLow8RegsBits, 177, 8, sizeof(GeneralDoubleLow8RegsBits), Hexagon::GeneralDoubleLow8RegsRegClassID, 64, 1, true },
  { DoubleRegs_with_isub_hi_in_IntRegsLow8, DoubleRegs_with_isub_hi_in_IntRegsLow8Bits, 32, 4, sizeof(DoubleRegs_with_isub_hi_in_IntRegsLow8Bits), Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID, 64, 1, true },
  { CtrRegs64_and_V62Regs, CtrRegs64_and_V62RegsBits, 117, 3, sizeof(CtrRegs64_and_V62RegsBits), Hexagon::CtrRegs64_and_V62RegsRegClassID, 64, 1, false },
  { CtrRegs64_with_isub_hi_in_ModRegs, CtrRegs64_with_isub_hi_in_ModRegsBits, 223, 1, sizeof(CtrRegs64_with_isub_hi_in_ModRegsBits), Hexagon::CtrRegs64_with_isub_hi_in_ModRegsRegClassID, 64, 1, false },
  { HvxQR, HvxQRBits, 78, 4, sizeof(HvxQRBits), Hexagon::HvxQRRegClassID, 0, 1, true },
  { HvxVR, HvxVRBits, 84, 33, sizeof(HvxVRBits), Hexagon::HvxVRRegClassID, 0, 1, true },
  { HvxVR_and_V65Regs, HvxVR_and_V65RegsBits, 159, 1, sizeof(HvxVR_and_V65RegsBits), Hexagon::HvxVR_and_V65RegsRegClassID, 0, 1, true },
  { HvxWR, HvxWRBits, 90, 32, sizeof(HvxWRBits), Hexagon::HvxWRRegClassID, 0, 1, true },
  { HvxWR_and_VectRegRev, HvxWR_and_VectRegRevBits, 310, 16, sizeof(HvxWR_and_VectRegRevBits), Hexagon::HvxWR_and_VectRegRevRegClassID, 0, 1, true },
  { HvxVQR, HvxVQRBits, 71, 8, sizeof(HvxVQRBits), Hexagon::HvxVQRRegClassID, 0, 1, true },
};

// Hexagon Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0Dwarf2L[] = {
  { 0U, Hexagon::R0 },
  { 1U, Hexagon::R1 },
  { 2U, Hexagon::R2 },
  { 3U, Hexagon::R3 },
  { 4U, Hexagon::R4 },
  { 5U, Hexagon::R5 },
  { 6U, Hexagon::R6 },
  { 7U, Hexagon::R7 },
  { 8U, Hexagon::R8 },
  { 9U, Hexagon::R9 },
  { 10U, Hexagon::R10 },
  { 11U, Hexagon::R11 },
  { 12U, Hexagon::R12 },
  { 13U, Hexagon::R13 },
  { 14U, Hexagon::R14 },
  { 15U, Hexagon::R15 },
  { 16U, Hexagon::R16 },
  { 17U, Hexagon::R17 },
  { 18U, Hexagon::R18 },
  { 19U, Hexagon::R19 },
  { 20U, Hexagon::R20 },
  { 21U, Hexagon::R21 },
  { 22U, Hexagon::R22 },
  { 23U, Hexagon::R23 },
  { 24U, Hexagon::R24 },
  { 25U, Hexagon::R25 },
  { 26U, Hexagon::R26 },
  { 27U, Hexagon::R27 },
  { 28U, Hexagon::R28 },
  { 29U, Hexagon::R29 },
  { 30U, Hexagon::R30 },
  { 31U, Hexagon::R31 },
  { 32U, Hexagon::D0 },
  { 34U, Hexagon::D1 },
  { 36U, Hexagon::D2 },
  { 38U, Hexagon::D3 },
  { 40U, Hexagon::D4 },
  { 42U, Hexagon::D5 },
  { 44U, Hexagon::D6 },
  { 46U, Hexagon::D7 },
  { 48U, Hexagon::D8 },
  { 50U, Hexagon::D9 },
  { 52U, Hexagon::D10 },
  { 54U, Hexagon::D11 },
  { 56U, Hexagon::D12 },
  { 58U, Hexagon::D13 },
  { 60U, Hexagon::D14 },
  { 62U, Hexagon::D15 },
  { 63U, Hexagon::P0 },
  { 64U, Hexagon::P1 },
  { 65U, Hexagon::P2 },
  { 66U, Hexagon::P3 },
  { 67U, Hexagon::C1_0 },
  { 68U, Hexagon::LC0 },
  { 69U, Hexagon::C3_2 },
  { 70U, Hexagon::LC1 },
  { 71U, Hexagon::P3_0 },
  { 72U, Hexagon::C7_6 },
  { 73U, Hexagon::M0 },
  { 74U, Hexagon::C9_8 },
  { 75U, Hexagon::C8 },
  { 76U, Hexagon::C11_10 },
  { 77U, Hexagon::UGP },
  { 78U, Hexagon::GP },
  { 79U, Hexagon::CS0 },
  { 80U, Hexagon::CS1 },
  { 81U, Hexagon::UPCYCLELO },
  { 82U, Hexagon::UPCYCLEHI },
  { 83U, Hexagon::C17_16 },
  { 84U, Hexagon::FRAMEKEY },
  { 85U, Hexagon::PKTCOUNTLO },
  { 86U, Hexagon::PKTCOUNTHI },
  { 97U, Hexagon::UTIMERLO },
  { 98U, Hexagon::UTIMERHI },
  { 99U, Hexagon::W0 },
  { 100U, Hexagon::V1 },
  { 101U, Hexagon::W1 },
  { 102U, Hexagon::V3 },
  { 103U, Hexagon::W2 },
  { 104U, Hexagon::V5 },
  { 105U, Hexagon::W3 },
  { 106U, Hexagon::V7 },
  { 107U, Hexagon::W4 },
  { 108U, Hexagon::V9 },
  { 109U, Hexagon::W5 },
  { 110U, Hexagon::V11 },
  { 111U, Hexagon::W6 },
  { 112U, Hexagon::V13 },
  { 113U, Hexagon::W7 },
  { 114U, Hexagon::V15 },
  { 115U, Hexagon::W8 },
  { 116U, Hexagon::V17 },
  { 117U, Hexagon::W9 },
  { 118U, Hexagon::V19 },
  { 119U, Hexagon::W10 },
  { 120U, Hexagon::V21 },
  { 121U, Hexagon::W11 },
  { 122U, Hexagon::V23 },
  { 123U, Hexagon::W12 },
  { 124U, Hexagon::V25 },
  { 125U, Hexagon::W13 },
  { 126U, Hexagon::V27 },
  { 127U, Hexagon::W14 },
  { 128U, Hexagon::V29 },
  { 129U, Hexagon::W15 },
  { 130U, Hexagon::V31 },
  { 131U, Hexagon::Q0 },
  { 132U, Hexagon::Q1 },
  { 133U, Hexagon::Q2 },
  { 134U, Hexagon::Q3 },
  { 144U, Hexagon::SGP1_0 },
  { 145U, Hexagon::SGP1 },
  { 146U, Hexagon::S3_2 },
  { 147U, Hexagon::ELR },
  { 148U, Hexagon::S5_4 },
  { 149U, Hexagon::BADVA1 },
  { 150U, Hexagon::S7_6 },
  { 151U, Hexagon::CCR },
  { 152U, Hexagon::S9_8 },
  { 153U, Hexagon::BADVA },
  { 154U, Hexagon::S11_10 },
  { 155U, Hexagon::S11 },
  { 156U, Hexagon::S13_12 },
  { 157U, Hexagon::S13 },
  { 158U, Hexagon::S15_14 },
  { 159U, Hexagon::S15 },
  { 160U, Hexagon::S17_16 },
  { 161U, Hexagon::WR0 },
  { 162U, Hexagon::S19_18 },
  { 163U, Hexagon::WR2 },
  { 164U, Hexagon::S21_20 },
  { 165U, Hexagon::WR4 },
  { 166U, Hexagon::S23_22 },
  { 167U, Hexagon::WR6 },
  { 168U, Hexagon::S25_24 },
  { 169U, Hexagon::WR8 },
  { 170U, Hexagon::S27_26 },
  { 171U, Hexagon::WR10 },
  { 172U, Hexagon::S29_28 },
  { 173U, Hexagon::WR12 },
  { 174U, Hexagon::S31_30 },
  { 175U, Hexagon::WR14 },
  { 176U, Hexagon::S33_32 },
  { 177U, Hexagon::ISDBCFG0 },
  { 178U, Hexagon::S35_34 },
  { 179U, Hexagon::S35 },
  { 180U, Hexagon::S37_36 },
  { 181U, Hexagon::BRKPTCFG0 },
  { 182U, Hexagon::S39_38 },
  { 183U, Hexagon::BRKPTCFG1 },
  { 184U, Hexagon::S41_40 },
  { 185U, Hexagon::ISDBMBXOUT },
  { 186U, Hexagon::S43_42 },
  { 187U, Hexagon::ISDBGPR },
  { 188U, Hexagon::S45_44 },
  { 189U, Hexagon::S45 },
  { 190U, Hexagon::S47_46 },
  { 191U, Hexagon::S47 },
  { 192U, Hexagon::S49_48 },
  { 193U, Hexagon::PMUCNT1 },
  { 194U, Hexagon::S51_50 },
  { 195U, Hexagon::PMUCNT3 },
  { 196U, Hexagon::S53_52 },
  { 197U, Hexagon::PMUCFG },
  { 198U, Hexagon::S55_54 },
  { 199U, Hexagon::S55 },
  { 200U, Hexagon::S57_56 },
  { 201U, Hexagon::S57 },
  { 202U, Hexagon::S59_58 },
  { 203U, Hexagon::S59 },
  { 204U, Hexagon::S61_60 },
  { 205U, Hexagon::S61 },
  { 206U, Hexagon::S63_62 },
  { 207U, Hexagon::S63 },
  { 208U, Hexagon::S65_64 },
  { 209U, Hexagon::S65 },
  { 210U, Hexagon::S67_66 },
  { 211U, Hexagon::S67 },
  { 212U, Hexagon::S69_68 },
  { 213U, Hexagon::S69 },
  { 214U, Hexagon::S71_70 },
  { 215U, Hexagon::S71 },
  { 216U, Hexagon::S73_72 },
  { 217U, Hexagon::S73 },
  { 218U, Hexagon::S75_74 },
  { 219U, Hexagon::S77_76 },
  { 220U, Hexagon::S79_78 },
  { 221U, Hexagon::S77 },
  { 222U, Hexagon::G3_2 },
  { 223U, Hexagon::S79 },
  { 224U, Hexagon::G5_4 },
  { 225U, Hexagon::G5 },
  { 226U, Hexagon::G7_6 },
  { 227U, Hexagon::G7 },
  { 228U, Hexagon::G9_8 },
  { 229U, Hexagon::G9 },
  { 230U, Hexagon::G11_10 },
  { 231U, Hexagon::G11 },
  { 232U, Hexagon::G13_12 },
  { 233U, Hexagon::G13 },
  { 234U, Hexagon::G15_14 },
  { 235U, Hexagon::G15 },
  { 236U, Hexagon::G17_16 },
  { 237U, Hexagon::GPMUCNT5 },
  { 238U, Hexagon::G19_18 },
  { 239U, Hexagon::GPMUCNT7 },
  { 240U, Hexagon::G21_20 },
  { 241U, Hexagon::G21 },
  { 242U, Hexagon::G23_22 },
  { 243U, Hexagon::G23 },
  { 244U, Hexagon::G25_24 },
  { 245U, Hexagon::GPCYCLEHI },
  { 246U, Hexagon::G27_26 },
  { 247U, Hexagon::GPMUCNT1 },
  { 248U, Hexagon::G29_28 },
  { 249U, Hexagon::GPMUCNT3 },
  { 250U, Hexagon::G31_30 },
  { 251U, Hexagon::G31 },
  { 252U, Hexagon::VQ0 },
  { 253U, Hexagon::VQ1 },
  { 254U, Hexagon::VQ2 },
  { 255U, Hexagon::VQ3 },
  { 256U, Hexagon::VQ4 },
  { 257U, Hexagon::VQ5 },
  { 258U, Hexagon::VQ6 },
  { 259U, Hexagon::VQ7 },
  { 999999U, Hexagon::VF0 },
  { 1000000U, Hexagon::VF1 },
  { 1000001U, Hexagon::VF2 },
  { 1000002U, Hexagon::VF3 },
  { 1000003U, Hexagon::VF4 },
  { 1000004U, Hexagon::VF5 },
  { 1000005U, Hexagon::VF6 },
  { 1000006U, Hexagon::VF7 },
  { 1000007U, Hexagon::VF8 },
  { 1000008U, Hexagon::VF9 },
  { 1000009U, Hexagon::VF10 },
  { 1000010U, Hexagon::VF11 },
  { 1000011U, Hexagon::VF12 },
  { 1000012U, Hexagon::VF13 },
  { 1000013U, Hexagon::VF14 },
  { 1000014U, Hexagon::VF15 },
  { 1000015U, Hexagon::VF16 },
  { 1000016U, Hexagon::VF17 },
  { 1000017U, Hexagon::VF18 },
  { 1000018U, Hexagon::VF19 },
  { 1000019U, Hexagon::VF20 },
  { 1000020U, Hexagon::VF21 },
  { 1000021U, Hexagon::VF22 },
  { 1000022U, Hexagon::VF23 },
  { 1000023U, Hexagon::VF24 },
  { 1000024U, Hexagon::VF25 },
  { 1000025U, Hexagon::VF26 },
  { 1000026U, Hexagon::VF27 },
  { 1000027U, Hexagon::VF28 },
  { 1000028U, Hexagon::VF29 },
  { 1000029U, Hexagon::VF30 },
  { 1000030U, Hexagon::VF31 },
  { 9999999U, Hexagon::VFR0 },
  { 10000000U, Hexagon::VFR1 },
  { 10000001U, Hexagon::VFR2 },
  { 10000002U, Hexagon::VFR3 },
  { 10000003U, Hexagon::VFR4 },
  { 10000004U, Hexagon::VFR5 },
  { 10000005U, Hexagon::VFR6 },
  { 10000006U, Hexagon::VFR7 },
  { 10000007U, Hexagon::VFR8 },
  { 10000008U, Hexagon::VFR9 },
  { 10000009U, Hexagon::VFR10 },
  { 10000010U, Hexagon::VFR11 },
  { 10000011U, Hexagon::VFR12 },
  { 10000012U, Hexagon::VFR13 },
  { 10000013U, Hexagon::VFR14 },
  { 10000014U, Hexagon::VFR15 },
  { 10000015U, Hexagon::VFR16 },
  { 10000016U, Hexagon::VFR17 },
  { 10000017U, Hexagon::VFR18 },
  { 10000018U, Hexagon::VFR19 },
  { 10000019U, Hexagon::VFR20 },
  { 10000020U, Hexagon::VFR21 },
  { 10000021U, Hexagon::VFR22 },
  { 10000022U, Hexagon::VFR23 },
  { 10000023U, Hexagon::VFR24 },
  { 10000024U, Hexagon::VFR25 },
  { 10000025U, Hexagon::VFR26 },
  { 10000026U, Hexagon::VFR27 },
  { 10000027U, Hexagon::VFR28 },
  { 10000028U, Hexagon::VFR29 },
  { 10000029U, Hexagon::VFR30 },
  { 10000030U, Hexagon::VFR31 },
};
extern const unsigned HexagonDwarfFlavour0Dwarf2LSize = std::size(HexagonDwarfFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0Dwarf2L[] = {
  { 0U, Hexagon::R0 },
  { 1U, Hexagon::R1 },
  { 2U, Hexagon::R2 },
  { 3U, Hexagon::R3 },
  { 4U, Hexagon::R4 },
  { 5U, Hexagon::R5 },
  { 6U, Hexagon::R6 },
  { 7U, Hexagon::R7 },
  { 8U, Hexagon::R8 },
  { 9U, Hexagon::R9 },
  { 10U, Hexagon::R10 },
  { 11U, Hexagon::R11 },
  { 12U, Hexagon::R12 },
  { 13U, Hexagon::R13 },
  { 14U, Hexagon::R14 },
  { 15U, Hexagon::R15 },
  { 16U, Hexagon::R16 },
  { 17U, Hexagon::R17 },
  { 18U, Hexagon::R18 },
  { 19U, Hexagon::R19 },
  { 20U, Hexagon::R20 },
  { 21U, Hexagon::R21 },
  { 22U, Hexagon::R22 },
  { 23U, Hexagon::R23 },
  { 24U, Hexagon::R24 },
  { 25U, Hexagon::R25 },
  { 26U, Hexagon::R26 },
  { 27U, Hexagon::R27 },
  { 28U, Hexagon::R28 },
  { 29U, Hexagon::R29 },
  { 30U, Hexagon::R30 },
  { 31U, Hexagon::R31 },
  { 32U, Hexagon::D0 },
  { 34U, Hexagon::D1 },
  { 36U, Hexagon::D2 },
  { 38U, Hexagon::D3 },
  { 40U, Hexagon::D4 },
  { 42U, Hexagon::D5 },
  { 44U, Hexagon::D6 },
  { 46U, Hexagon::D7 },
  { 48U, Hexagon::D8 },
  { 50U, Hexagon::D9 },
  { 52U, Hexagon::D10 },
  { 54U, Hexagon::D11 },
  { 56U, Hexagon::D12 },
  { 58U, Hexagon::D13 },
  { 60U, Hexagon::D14 },
  { 62U, Hexagon::D15 },
  { 63U, Hexagon::P0 },
  { 64U, Hexagon::P1 },
  { 65U, Hexagon::P2 },
  { 66U, Hexagon::P3 },
  { 67U, Hexagon::C1_0 },
  { 68U, Hexagon::LC0 },
  { 69U, Hexagon::C3_2 },
  { 70U, Hexagon::LC1 },
  { 71U, Hexagon::P3_0 },
  { 72U, Hexagon::C7_6 },
  { 73U, Hexagon::M0 },
  { 74U, Hexagon::C9_8 },
  { 75U, Hexagon::C8 },
  { 76U, Hexagon::C11_10 },
  { 77U, Hexagon::UGP },
  { 78U, Hexagon::GP },
  { 79U, Hexagon::CS0 },
  { 80U, Hexagon::CS1 },
  { 81U, Hexagon::UPCYCLELO },
  { 82U, Hexagon::UPCYCLEHI },
  { 83U, Hexagon::C17_16 },
  { 84U, Hexagon::FRAMEKEY },
  { 85U, Hexagon::PKTCOUNTLO },
  { 86U, Hexagon::PKTCOUNTHI },
  { 97U, Hexagon::UTIMERLO },
  { 98U, Hexagon::UTIMERHI },
  { 99U, Hexagon::W0 },
  { 100U, Hexagon::V1 },
  { 101U, Hexagon::W1 },
  { 102U, Hexagon::V3 },
  { 103U, Hexagon::W2 },
  { 104U, Hexagon::V5 },
  { 105U, Hexagon::W3 },
  { 106U, Hexagon::V7 },
  { 107U, Hexagon::W4 },
  { 108U, Hexagon::V9 },
  { 109U, Hexagon::W5 },
  { 110U, Hexagon::V11 },
  { 111U, Hexagon::W6 },
  { 112U, Hexagon::V13 },
  { 113U, Hexagon::W7 },
  { 114U, Hexagon::V15 },
  { 115U, Hexagon::W8 },
  { 116U, Hexagon::V17 },
  { 117U, Hexagon::W9 },
  { 118U, Hexagon::V19 },
  { 119U, Hexagon::W10 },
  { 120U, Hexagon::V21 },
  { 121U, Hexagon::W11 },
  { 122U, Hexagon::V23 },
  { 123U, Hexagon::W12 },
  { 124U, Hexagon::V25 },
  { 125U, Hexagon::W13 },
  { 126U, Hexagon::V27 },
  { 127U, Hexagon::W14 },
  { 128U, Hexagon::V29 },
  { 129U, Hexagon::W15 },
  { 130U, Hexagon::V31 },
  { 131U, Hexagon::Q0 },
  { 132U, Hexagon::Q1 },
  { 133U, Hexagon::Q2 },
  { 134U, Hexagon::Q3 },
  { 144U, Hexagon::SGP1_0 },
  { 145U, Hexagon::SGP1 },
  { 146U, Hexagon::S3_2 },
  { 147U, Hexagon::ELR },
  { 148U, Hexagon::S5_4 },
  { 149U, Hexagon::BADVA1 },
  { 150U, Hexagon::S7_6 },
  { 151U, Hexagon::CCR },
  { 152U, Hexagon::S9_8 },
  { 153U, Hexagon::BADVA },
  { 154U, Hexagon::S11_10 },
  { 155U, Hexagon::S11 },
  { 156U, Hexagon::S13_12 },
  { 157U, Hexagon::S13 },
  { 158U, Hexagon::S15_14 },
  { 159U, Hexagon::S15 },
  { 160U, Hexagon::S17_16 },
  { 161U, Hexagon::WR0 },
  { 162U, Hexagon::S19_18 },
  { 163U, Hexagon::WR2 },
  { 164U, Hexagon::S21_20 },
  { 165U, Hexagon::WR4 },
  { 166U, Hexagon::S23_22 },
  { 167U, Hexagon::WR6 },
  { 168U, Hexagon::S25_24 },
  { 169U, Hexagon::WR8 },
  { 170U, Hexagon::S27_26 },
  { 171U, Hexagon::WR10 },
  { 172U, Hexagon::S29_28 },
  { 173U, Hexagon::WR12 },
  { 174U, Hexagon::S31_30 },
  { 175U, Hexagon::WR14 },
  { 176U, Hexagon::S33_32 },
  { 177U, Hexagon::ISDBCFG0 },
  { 178U, Hexagon::S35_34 },
  { 179U, Hexagon::S35 },
  { 180U, Hexagon::S37_36 },
  { 181U, Hexagon::BRKPTCFG0 },
  { 182U, Hexagon::S39_38 },
  { 183U, Hexagon::BRKPTCFG1 },
  { 184U, Hexagon::S41_40 },
  { 185U, Hexagon::ISDBMBXOUT },
  { 186U, Hexagon::S43_42 },
  { 187U, Hexagon::ISDBGPR },
  { 188U, Hexagon::S45_44 },
  { 189U, Hexagon::S45 },
  { 190U, Hexagon::S47_46 },
  { 191U, Hexagon::S47 },
  { 192U, Hexagon::S49_48 },
  { 193U, Hexagon::PMUCNT1 },
  { 194U, Hexagon::S51_50 },
  { 195U, Hexagon::PMUCNT3 },
  { 196U, Hexagon::S53_52 },
  { 197U, Hexagon::PMUCFG },
  { 198U, Hexagon::S55_54 },
  { 199U, Hexagon::S55 },
  { 200U, Hexagon::S57_56 },
  { 201U, Hexagon::S57 },
  { 202U, Hexagon::S59_58 },
  { 203U, Hexagon::S59 },
  { 204U, Hexagon::S61_60 },
  { 205U, Hexagon::S61 },
  { 206U, Hexagon::S63_62 },
  { 207U, Hexagon::S63 },
  { 208U, Hexagon::S65_64 },
  { 209U, Hexagon::S65 },
  { 210U, Hexagon::S67_66 },
  { 211U, Hexagon::S67 },
  { 212U, Hexagon::S69_68 },
  { 213U, Hexagon::S69 },
  { 214U, Hexagon::S71_70 },
  { 215U, Hexagon::S71 },
  { 216U, Hexagon::S73_72 },
  { 217U, Hexagon::S73 },
  { 218U, Hexagon::S75_74 },
  { 219U, Hexagon::S77_76 },
  { 220U, Hexagon::S79_78 },
  { 221U, Hexagon::S77 },
  { 222U, Hexagon::G3_2 },
  { 223U, Hexagon::S79 },
  { 224U, Hexagon::G5_4 },
  { 225U, Hexagon::G5 },
  { 226U, Hexagon::G7_6 },
  { 227U, Hexagon::G7 },
  { 228U, Hexagon::G9_8 },
  { 229U, Hexagon::G9 },
  { 230U, Hexagon::G11_10 },
  { 231U, Hexagon::G11 },
  { 232U, Hexagon::G13_12 },
  { 233U, Hexagon::G13 },
  { 234U, Hexagon::G15_14 },
  { 235U, Hexagon::G15 },
  { 236U, Hexagon::G17_16 },
  { 237U, Hexagon::GPMUCNT5 },
  { 238U, Hexagon::G19_18 },
  { 239U, Hexagon::GPMUCNT7 },
  { 240U, Hexagon::G21_20 },
  { 241U, Hexagon::G21 },
  { 242U, Hexagon::G23_22 },
  { 243U, Hexagon::G23 },
  { 244U, Hexagon::G25_24 },
  { 245U, Hexagon::GPCYCLEHI },
  { 246U, Hexagon::G27_26 },
  { 247U, Hexagon::GPMUCNT1 },
  { 248U, Hexagon::G29_28 },
  { 249U, Hexagon::GPMUCNT3 },
  { 250U, Hexagon::G31_30 },
  { 251U, Hexagon::G31 },
  { 252U, Hexagon::VQ0 },
  { 253U, Hexagon::VQ1 },
  { 254U, Hexagon::VQ2 },
  { 255U, Hexagon::VQ3 },
  { 256U, Hexagon::VQ4 },
  { 257U, Hexagon::VQ5 },
  { 258U, Hexagon::VQ6 },
  { 259U, Hexagon::VQ7 },
  { 999999U, Hexagon::VF0 },
  { 1000000U, Hexagon::VF1 },
  { 1000001U, Hexagon::VF2 },
  { 1000002U, Hexagon::VF3 },
  { 1000003U, Hexagon::VF4 },
  { 1000004U, Hexagon::VF5 },
  { 1000005U, Hexagon::VF6 },
  { 1000006U, Hexagon::VF7 },
  { 1000007U, Hexagon::VF8 },
  { 1000008U, Hexagon::VF9 },
  { 1000009U, Hexagon::VF10 },
  { 1000010U, Hexagon::VF11 },
  { 1000011U, Hexagon::VF12 },
  { 1000012U, Hexagon::VF13 },
  { 1000013U, Hexagon::VF14 },
  { 1000014U, Hexagon::VF15 },
  { 1000015U, Hexagon::VF16 },
  { 1000016U, Hexagon::VF17 },
  { 1000017U, Hexagon::VF18 },
  { 1000018U, Hexagon::VF19 },
  { 1000019U, Hexagon::VF20 },
  { 1000020U, Hexagon::VF21 },
  { 1000021U, Hexagon::VF22 },
  { 1000022U, Hexagon::VF23 },
  { 1000023U, Hexagon::VF24 },
  { 1000024U, Hexagon::VF25 },
  { 1000025U, Hexagon::VF26 },
  { 1000026U, Hexagon::VF27 },
  { 1000027U, Hexagon::VF28 },
  { 1000028U, Hexagon::VF29 },
  { 1000029U, Hexagon::VF30 },
  { 1000030U, Hexagon::VF31 },
  { 9999999U, Hexagon::VFR0 },
  { 10000000U, Hexagon::VFR1 },
  { 10000001U, Hexagon::VFR2 },
  { 10000002U, Hexagon::VFR3 },
  { 10000003U, Hexagon::VFR4 },
  { 10000004U, Hexagon::VFR5 },
  { 10000005U, Hexagon::VFR6 },
  { 10000006U, Hexagon::VFR7 },
  { 10000007U, Hexagon::VFR8 },
  { 10000008U, Hexagon::VFR9 },
  { 10000009U, Hexagon::VFR10 },
  { 10000010U, Hexagon::VFR11 },
  { 10000011U, Hexagon::VFR12 },
  { 10000012U, Hexagon::VFR13 },
  { 10000013U, Hexagon::VFR14 },
  { 10000014U, Hexagon::VFR15 },
  { 10000015U, Hexagon::VFR16 },
  { 10000016U, Hexagon::VFR17 },
  { 10000017U, Hexagon::VFR18 },
  { 10000018U, Hexagon::VFR19 },
  { 10000019U, Hexagon::VFR20 },
  { 10000020U, Hexagon::VFR21 },
  { 10000021U, Hexagon::VFR22 },
  { 10000022U, Hexagon::VFR23 },
  { 10000023U, Hexagon::VFR24 },
  { 10000024U, Hexagon::VFR25 },
  { 10000025U, Hexagon::VFR26 },
  { 10000026U, Hexagon::VFR27 },
  { 10000027U, Hexagon::VFR28 },
  { 10000028U, Hexagon::VFR29 },
  { 10000029U, Hexagon::VFR30 },
  { 10000030U, Hexagon::VFR31 },
};
extern const unsigned HexagonEHFlavour0Dwarf2LSize = std::size(HexagonEHFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0L2Dwarf[] = {
  { Hexagon::BADVA, 153U },
  { Hexagon::CCR, 151U },
  { Hexagon::CFGBASE, 171U },
  { Hexagon::CS, 78U },
  { Hexagon::DIAG, 172U },
  { Hexagon::ELR, 147U },
  { Hexagon::EVB, 160U },
  { Hexagon::FRAMEKEY, 84U },
  { Hexagon::FRAMELIMIT, 83U },
  { Hexagon::GELR, 220U },
  { Hexagon::GOSP, 222U },
  { Hexagon::GP, 78U },
  { Hexagon::GPCYCLEHI, 245U },
  { Hexagon::GPCYCLELO, 244U },
  { Hexagon::GSR, 221U },
  { Hexagon::HTID, 152U },
  { Hexagon::IMASK, 154U },
  { Hexagon::ISDBEN, 186U },
  { Hexagon::ISDBGPR, 187U },
  { Hexagon::ISDBMBXIN, 184U },
  { Hexagon::ISDBMBXOUT, 185U },
  { Hexagon::ISDBST, 176U },
  { Hexagon::MODECTL, 161U },
  { Hexagon::PC, 76U },
  { Hexagon::PCYCLEHI, 175U },
  { Hexagon::PCYCLELO, 174U },
  { Hexagon::PKTCOUNT, 85U },
  { Hexagon::PKTCOUNTHI, 86U },
  { Hexagon::PKTCOUNTLO, 85U },
  { Hexagon::PMUCFG, 197U },
  { Hexagon::PMUEVTCFG, 196U },
  { Hexagon::REV, 173U },
  { Hexagon::SSR, 150U },
  { Hexagon::STID, 146U },
  { Hexagon::SYSCFG, 162U },
  { Hexagon::UGP, 77U },
  { Hexagon::UPCYCLE, 80U },
  { Hexagon::UPCYCLEHI, 82U },
  { Hexagon::UPCYCLELO, 81U },
  { Hexagon::USR, 75U },
  { Hexagon::UTIMER, 97U },
  { Hexagon::UTIMERHI, 98U },
  { Hexagon::UTIMERLO, 97U },
  { Hexagon::VID, 165U },
  { Hexagon::VTMP, 131U },
  { Hexagon::BADVA0, 148U },
  { Hexagon::BADVA1, 149U },
  { Hexagon::BRKPTCFG0, 181U },
  { Hexagon::BRKPTCFG1, 183U },
  { Hexagon::BRKPTPC0, 180U },
  { Hexagon::BRKPTPC1, 182U },
  { Hexagon::C5, 72U },
  { Hexagon::C8, 75U },
  { Hexagon::CS0, 79U },
  { Hexagon::CS1, 80U },
  { Hexagon::D0, 32U },
  { Hexagon::D1, 34U },
  { Hexagon::D2, 36U },
  { Hexagon::D3, 38U },
  { Hexagon::D4, 40U },
  { Hexagon::D5, 42U },
  { Hexagon::D6, 44U },
  { Hexagon::D7, 46U },
  { Hexagon::D8, 48U },
  { Hexagon::D9, 50U },
  { Hexagon::D10, 52U },
  { Hexagon::D11, 54U },
  { Hexagon::D12, 56U },
  { Hexagon::D13, 58U },
  { Hexagon::D14, 60U },
  { Hexagon::D15, 62U },
  { Hexagon::G3, 223U },
  { Hexagon::G4, 224U },
  { Hexagon::G5, 225U },
  { Hexagon::G6, 226U },
  { Hexagon::G7, 227U },
  { Hexagon::G8, 228U },
  { Hexagon::G9, 229U },
  { Hexagon::G10, 230U },
  { Hexagon::G11, 231U },
  { Hexagon::G12, 232U },
  { Hexagon::G13, 233U },
  { Hexagon::G14, 234U },
  { Hexagon::G15, 235U },
  { Hexagon::G20, 240U },
  { Hexagon::G21, 241U },
  { Hexagon::G22, 242U },
  { Hexagon::G23, 243U },
  { Hexagon::G30, 250U },
  { Hexagon::G31, 251U },
  { Hexagon::GPMUCNT0, 246U },
  { Hexagon::GPMUCNT1, 247U },
  { Hexagon::GPMUCNT2, 248U },
  { Hexagon::GPMUCNT3, 249U },
  { Hexagon::GPMUCNT4, 236U },
  { Hexagon::GPMUCNT5, 237U },
  { Hexagon::GPMUCNT6, 238U },
  { Hexagon::GPMUCNT7, 239U },
  { Hexagon::ISDBCFG0, 177U },
  { Hexagon::ISDBCFG1, 178U },
  { Hexagon::LC0, 68U },
  { Hexagon::LC1, 70U },
  { Hexagon::M0, 73U },
  { Hexagon::M1, 74U },
  { Hexagon::P0, 63U },
  { Hexagon::P1, 64U },
  { Hexagon::P2, 65U },
  { Hexagon::P3, 66U },
  { Hexagon::PMUCNT0, 192U },
  { Hexagon::PMUCNT1, 193U },
  { Hexagon::PMUCNT2, 194U },
  { Hexagon::PMUCNT3, 195U },
  { Hexagon::Q0, 131U },
  { Hexagon::Q1, 132U },
  { Hexagon::Q2, 133U },
  { Hexagon::Q3, 134U },
  { Hexagon::R0, 0U },
  { Hexagon::R1, 1U },
  { Hexagon::R2, 2U },
  { Hexagon::R3, 3U },
  { Hexagon::R4, 4U },
  { Hexagon::R5, 5U },
  { Hexagon::R6, 6U },
  { Hexagon::R7, 7U },
  { Hexagon::R8, 8U },
  { Hexagon::R9, 9U },
  { Hexagon::R10, 10U },
  { Hexagon::R11, 11U },
  { Hexagon::R12, 12U },
  { Hexagon::R13, 13U },
  { Hexagon::R14, 14U },
  { Hexagon::R15, 15U },
  { Hexagon::R16, 16U },
  { Hexagon::R17, 17U },
  { Hexagon::R18, 18U },
  { Hexagon::R19, 19U },
  { Hexagon::R20, 20U },
  { Hexagon::R21, 21U },
  { Hexagon::R22, 22U },
  { Hexagon::R23, 23U },
  { Hexagon::R24, 24U },
  { Hexagon::R25, 25U },
  { Hexagon::R26, 26U },
  { Hexagon::R27, 27U },
  { Hexagon::R28, 28U },
  { Hexagon::R29, 29U },
  { Hexagon::R30, 30U },
  { Hexagon::R31, 31U },
  { Hexagon::S11, 155U },
  { Hexagon::S12, 156U },
  { Hexagon::S13, 157U },
  { Hexagon::S14, 158U },
  { Hexagon::S15, 159U },
  { Hexagon::S19, 163U },
  { Hexagon::S20, 164U },
  { Hexagon::S22, 166U },
  { Hexagon::S23, 167U },
  { Hexagon::S24, 168U },
  { Hexagon::S25, 169U },
  { Hexagon::S26, 170U },
  { Hexagon::S35, 179U },
  { Hexagon::S44, 188U },
  { Hexagon::S45, 189U },
  { Hexagon::S46, 190U },
  { Hexagon::S47, 191U },
  { Hexagon::S54, 198U },
  { Hexagon::S55, 199U },
  { Hexagon::S56, 200U },
  { Hexagon::S57, 201U },
  { Hexagon::S58, 202U },
  { Hexagon::S59, 203U },
  { Hexagon::S60, 204U },
  { Hexagon::S61, 205U },
  { Hexagon::S62, 206U },
  { Hexagon::S63, 207U },
  { Hexagon::S64, 208U },
  { Hexagon::S65, 209U },
  { Hexagon::S66, 210U },
  { Hexagon::S67, 211U },
  { Hexagon::S68, 212U },
  { Hexagon::S69, 213U },
  { Hexagon::S70, 214U },
  { Hexagon::S71, 215U },
  { Hexagon::S72, 216U },
  { Hexagon::S73, 217U },
  { Hexagon::S74, 218U },
  { Hexagon::S75, 219U },
  { Hexagon::S76, 220U },
  { Hexagon::S77, 221U },
  { Hexagon::S78, 222U },
  { Hexagon::S79, 223U },
  { Hexagon::S80, 224U },
  { Hexagon::SA0, 67U },
  { Hexagon::SA1, 69U },
  { Hexagon::SGP0, 144U },
  { Hexagon::SGP1, 145U },
  { Hexagon::V0, 99U },
  { Hexagon::V1, 100U },
  { Hexagon::V2, 101U },
  { Hexagon::V3, 102U },
  { Hexagon::V4, 103U },
  { Hexagon::V5, 104U },
  { Hexagon::V6, 105U },
  { Hexagon::V7, 106U },
  { Hexagon::V8, 107U },
  { Hexagon::V9, 108U },
  { Hexagon::V10, 109U },
  { Hexagon::V11, 110U },
  { Hexagon::V12, 111U },
  { Hexagon::V13, 112U },
  { Hexagon::V14, 113U },
  { Hexagon::V15, 114U },
  { Hexagon::V16, 115U },
  { Hexagon::V17, 116U },
  { Hexagon::V18, 117U },
  { Hexagon::V19, 118U },
  { Hexagon::V20, 119U },
  { Hexagon::V21, 120U },
  { Hexagon::V22, 121U },
  { Hexagon::V23, 122U },
  { Hexagon::V24, 123U },
  { Hexagon::V25, 124U },
  { Hexagon::V26, 125U },
  { Hexagon::V27, 126U },
  { Hexagon::V28, 127U },
  { Hexagon::V29, 128U },
  { Hexagon::V30, 129U },
  { Hexagon::V31, 130U },
  { Hexagon::VF0, 999999U },
  { Hexagon::VF1, 1000000U },
  { Hexagon::VF2, 1000001U },
  { Hexagon::VF3, 1000002U },
  { Hexagon::VF4, 1000003U },
  { Hexagon::VF5, 1000004U },
  { Hexagon::VF6, 1000005U },
  { Hexagon::VF7, 1000006U },
  { Hexagon::VF8, 1000007U },
  { Hexagon::VF9, 1000008U },
  { Hexagon::VF10, 1000009U },
  { Hexagon::VF11, 1000010U },
  { Hexagon::VF12, 1000011U },
  { Hexagon::VF13, 1000012U },
  { Hexagon::VF14, 1000013U },
  { Hexagon::VF15, 1000014U },
  { Hexagon::VF16, 1000015U },
  { Hexagon::VF17, 1000016U },
  { Hexagon::VF18, 1000017U },
  { Hexagon::VF19, 1000018U },
  { Hexagon::VF20, 1000019U },
  { Hexagon::VF21, 1000020U },
  { Hexagon::VF22, 1000021U },
  { Hexagon::VF23, 1000022U },
  { Hexagon::VF24, 1000023U },
  { Hexagon::VF25, 1000024U },
  { Hexagon::VF26, 1000025U },
  { Hexagon::VF27, 1000026U },
  { Hexagon::VF28, 1000027U },
  { Hexagon::VF29, 1000028U },
  { Hexagon::VF30, 1000029U },
  { Hexagon::VF31, 1000030U },
  { Hexagon::VFR0, 9999999U },
  { Hexagon::VFR1, 10000000U },
  { Hexagon::VFR2, 10000001U },
  { Hexagon::VFR3, 10000002U },
  { Hexagon::VFR4, 10000003U },
  { Hexagon::VFR5, 10000004U },
  { Hexagon::VFR6, 10000005U },
  { Hexagon::VFR7, 10000006U },
  { Hexagon::VFR8, 10000007U },
  { Hexagon::VFR9, 10000008U },
  { Hexagon::VFR10, 10000009U },
  { Hexagon::VFR11, 10000010U },
  { Hexagon::VFR12, 10000011U },
  { Hexagon::VFR13, 10000012U },
  { Hexagon::VFR14, 10000013U },
  { Hexagon::VFR15, 10000014U },
  { Hexagon::VFR16, 10000015U },
  { Hexagon::VFR17, 10000016U },
  { Hexagon::VFR18, 10000017U },
  { Hexagon::VFR19, 10000018U },
  { Hexagon::VFR20, 10000019U },
  { Hexagon::VFR21, 10000020U },
  { Hexagon::VFR22, 10000021U },
  { Hexagon::VFR23, 10000022U },
  { Hexagon::VFR24, 10000023U },
  { Hexagon::VFR25, 10000024U },
  { Hexagon::VFR26, 10000025U },
  { Hexagon::VFR27, 10000026U },
  { Hexagon::VFR28, 10000027U },
  { Hexagon::VFR29, 10000028U },
  { Hexagon::VFR30, 10000029U },
  { Hexagon::VFR31, 10000030U },
  { Hexagon::VQ0, 252U },
  { Hexagon::VQ1, 253U },
  { Hexagon::VQ2, 254U },
  { Hexagon::VQ3, 255U },
  { Hexagon::VQ4, 256U },
  { Hexagon::VQ5, 257U },
  { Hexagon::VQ6, 258U },
  { Hexagon::VQ7, 259U },
  { Hexagon::W0, 99U },
  { Hexagon::W1, 101U },
  { Hexagon::W2, 103U },
  { Hexagon::W3, 105U },
  { Hexagon::W4, 107U },
  { Hexagon::W5, 109U },
  { Hexagon::W6, 111U },
  { Hexagon::W7, 113U },
  { Hexagon::W8, 115U },
  { Hexagon::W9, 117U },
  { Hexagon::W10, 119U },
  { Hexagon::W11, 121U },
  { Hexagon::W12, 123U },
  { Hexagon::W13, 125U },
  { Hexagon::W14, 127U },
  { Hexagon::W15, 129U },
  { Hexagon::WR0, 161U },
  { Hexagon::WR1, 162U },
  { Hexagon::WR2, 163U },
  { Hexagon::WR3, 164U },
  { Hexagon::WR4, 165U },
  { Hexagon::WR5, 166U },
  { Hexagon::WR6, 167U },
  { Hexagon::WR7, 168U },
  { Hexagon::WR8, 169U },
  { Hexagon::WR9, 170U },
  { Hexagon::WR10, 171U },
  { Hexagon::WR11, 172U },
  { Hexagon::WR12, 173U },
  { Hexagon::WR13, 174U },
  { Hexagon::WR14, 175U },
  { Hexagon::WR15, 176U },
  { Hexagon::C1_0, 67U },
  { Hexagon::C3_2, 69U },
  { Hexagon::C5_4, 71U },
  { Hexagon::C7_6, 72U },
  { Hexagon::C9_8, 74U },
  { Hexagon::C11_10, 76U },
  { Hexagon::C17_16, 83U },
  { Hexagon::G1_0, 220U },
  { Hexagon::G3_2, 222U },
  { Hexagon::G5_4, 224U },
  { Hexagon::G7_6, 226U },
  { Hexagon::G9_8, 228U },
  { Hexagon::G11_10, 230U },
  { Hexagon::G13_12, 232U },
  { Hexagon::G15_14, 234U },
  { Hexagon::G17_16, 236U },
  { Hexagon::G19_18, 238U },
  { Hexagon::G21_20, 240U },
  { Hexagon::G23_22, 242U },
  { Hexagon::G25_24, 244U },
  { Hexagon::G27_26, 246U },
  { Hexagon::G29_28, 248U },
  { Hexagon::G31_30, 250U },
  { Hexagon::P3_0, 71U },
  { Hexagon::S3_2, 146U },
  { Hexagon::S5_4, 148U },
  { Hexagon::S7_6, 150U },
  { Hexagon::S9_8, 152U },
  { Hexagon::S11_10, 154U },
  { Hexagon::S13_12, 156U },
  { Hexagon::S15_14, 158U },
  { Hexagon::S17_16, 160U },
  { Hexagon::S19_18, 162U },
  { Hexagon::S21_20, 164U },
  { Hexagon::S23_22, 166U },
  { Hexagon::S25_24, 168U },
  { Hexagon::S27_26, 170U },
  { Hexagon::S29_28, 172U },
  { Hexagon::S31_30, 174U },
  { Hexagon::S33_32, 176U },
  { Hexagon::S35_34, 178U },
  { Hexagon::S37_36, 180U },
  { Hexagon::S39_38, 182U },
  { Hexagon::S41_40, 184U },
  { Hexagon::S43_42, 186U },
  { Hexagon::S45_44, 188U },
  { Hexagon::S47_46, 190U },
  { Hexagon::S49_48, 192U },
  { Hexagon::S51_50, 194U },
  { Hexagon::S53_52, 196U },
  { Hexagon::S55_54, 198U },
  { Hexagon::S57_56, 200U },
  { Hexagon::S59_58, 202U },
  { Hexagon::S61_60, 204U },
  { Hexagon::S63_62, 206U },
  { Hexagon::S65_64, 208U },
  { Hexagon::S67_66, 210U },
  { Hexagon::S69_68, 212U },
  { Hexagon::S71_70, 214U },
  { Hexagon::S73_72, 216U },
  { Hexagon::S75_74, 218U },
  { Hexagon::S77_76, 219U },
  { Hexagon::S79_78, 220U },
  { Hexagon::SGP1_0, 144U },
};
extern const unsigned HexagonDwarfFlavour0L2DwarfSize = std::size(HexagonDwarfFlavour0L2Dwarf);

extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0L2Dwarf[] = {
  { Hexagon::BADVA, 153U },
  { Hexagon::CCR, 151U },
  { Hexagon::CFGBASE, 171U },
  { Hexagon::CS, 78U },
  { Hexagon::DIAG, 172U },
  { Hexagon::ELR, 147U },
  { Hexagon::EVB, 160U },
  { Hexagon::FRAMEKEY, 84U },
  { Hexagon::FRAMELIMIT, 83U },
  { Hexagon::GELR, 220U },
  { Hexagon::GOSP, 222U },
  { Hexagon::GP, 78U },
  { Hexagon::GPCYCLEHI, 245U },
  { Hexagon::GPCYCLELO, 244U },
  { Hexagon::GSR, 221U },
  { Hexagon::HTID, 152U },
  { Hexagon::IMASK, 154U },
  { Hexagon::ISDBEN, 186U },
  { Hexagon::ISDBGPR, 187U },
  { Hexagon::ISDBMBXIN, 184U },
  { Hexagon::ISDBMBXOUT, 185U },
  { Hexagon::ISDBST, 176U },
  { Hexagon::MODECTL, 161U },
  { Hexagon::PC, 76U },
  { Hexagon::PCYCLEHI, 175U },
  { Hexagon::PCYCLELO, 174U },
  { Hexagon::PKTCOUNT, 85U },
  { Hexagon::PKTCOUNTHI, 86U },
  { Hexagon::PKTCOUNTLO, 85U },
  { Hexagon::PMUCFG, 197U },
  { Hexagon::PMUEVTCFG, 196U },
  { Hexagon::REV, 173U },
  { Hexagon::SSR, 150U },
  { Hexagon::STID, 146U },
  { Hexagon::SYSCFG, 162U },
  { Hexagon::UGP, 77U },
  { Hexagon::UPCYCLE, 80U },
  { Hexagon::UPCYCLEHI, 82U },
  { Hexagon::UPCYCLELO, 81U },
  { Hexagon::USR, 75U },
  { Hexagon::UTIMER, 97U },
  { Hexagon::UTIMERHI, 98U },
  { Hexagon::UTIMERLO, 97U },
  { Hexagon::VID, 165U },
  { Hexagon::VTMP, 131U },
  { Hexagon::BADVA0, 148U },
  { Hexagon::BADVA1, 149U },
  { Hexagon::BRKPTCFG0, 181U },
  { Hexagon::BRKPTCFG1, 183U },
  { Hexagon::BRKPTPC0, 180U },
  { Hexagon::BRKPTPC1, 182U },
  { Hexagon::C5, 72U },
  { Hexagon::C8, 75U },
  { Hexagon::CS0, 79U },
  { Hexagon::CS1, 80U },
  { Hexagon::D0, 32U },
  { Hexagon::D1, 34U },
  { Hexagon::D2, 36U },
  { Hexagon::D3, 38U },
  { Hexagon::D4, 40U },
  { Hexagon::D5, 42U },
  { Hexagon::D6, 44U },
  { Hexagon::D7, 46U },
  { Hexagon::D8, 48U },
  { Hexagon::D9, 50U },
  { Hexagon::D10, 52U },
  { Hexagon::D11, 54U },
  { Hexagon::D12, 56U },
  { Hexagon::D13, 58U },
  { Hexagon::D14, 60U },
  { Hexagon::D15, 62U },
  { Hexagon::G3, 223U },
  { Hexagon::G4, 224U },
  { Hexagon::G5, 225U },
  { Hexagon::G6, 226U },
  { Hexagon::G7, 227U },
  { Hexagon::G8, 228U },
  { Hexagon::G9, 229U },
  { Hexagon::G10, 230U },
  { Hexagon::G11, 231U },
  { Hexagon::G12, 232U },
  { Hexagon::G13, 233U },
  { Hexagon::G14, 234U },
  { Hexagon::G15, 235U },
  { Hexagon::G20, 240U },
  { Hexagon::G21, 241U },
  { Hexagon::G22, 242U },
  { Hexagon::G23, 243U },
  { Hexagon::G30, 250U },
  { Hexagon::G31, 251U },
  { Hexagon::GPMUCNT0, 246U },
  { Hexagon::GPMUCNT1, 247U },
  { Hexagon::GPMUCNT2, 248U },
  { Hexagon::GPMUCNT3, 249U },
  { Hexagon::GPMUCNT4, 236U },
  { Hexagon::GPMUCNT5, 237U },
  { Hexagon::GPMUCNT6, 238U },
  { Hexagon::GPMUCNT7, 239U },
  { Hexagon::ISDBCFG0, 177U },
  { Hexagon::ISDBCFG1, 178U },
  { Hexagon::LC0, 68U },
  { Hexagon::LC1, 70U },
  { Hexagon::M0, 73U },
  { Hexagon::M1, 74U },
  { Hexagon::P0, 63U },
  { Hexagon::P1, 64U },
  { Hexagon::P2, 65U },
  { Hexagon::P3, 66U },
  { Hexagon::PMUCNT0, 192U },
  { Hexagon::PMUCNT1, 193U },
  { Hexagon::PMUCNT2, 194U },
  { Hexagon::PMUCNT3, 195U },
  { Hexagon::Q0, 131U },
  { Hexagon::Q1, 132U },
  { Hexagon::Q2, 133U },
  { Hexagon::Q3, 134U },
  { Hexagon::R0, 0U },
  { Hexagon::R1, 1U },
  { Hexagon::R2, 2U },
  { Hexagon::R3, 3U },
  { Hexagon::R4, 4U },
  { Hexagon::R5, 5U },
  { Hexagon::R6, 6U },
  { Hexagon::R7, 7U },
  { Hexagon::R8, 8U },
  { Hexagon::R9, 9U },
  { Hexagon::R10, 10U },
  { Hexagon::R11, 11U },
  { Hexagon::R12, 12U },
  { Hexagon::R13, 13U },
  { Hexagon::R14, 14U },
  { Hexagon::R15, 15U },
  { Hexagon::R16, 16U },
  { Hexagon::R17, 17U },
  { Hexagon::R18, 18U },
  { Hexagon::R19, 19U },
  { Hexagon::R20, 20U },
  { Hexagon::R21, 21U },
  { Hexagon::R22, 22U },
  { Hexagon::R23, 23U },
  { Hexagon::R24, 24U },
  { Hexagon::R25, 25U },
  { Hexagon::R26, 26U },
  { Hexagon::R27, 27U },
  { Hexagon::R28, 28U },
  { Hexagon::R29, 29U },
  { Hexagon::R30, 30U },
  { Hexagon::R31, 31U },
  { Hexagon::S11, 155U },
  { Hexagon::S12, 156U },
  { Hexagon::S13, 157U },
  { Hexagon::S14, 158U },
  { Hexagon::S15, 159U },
  { Hexagon::S19, 163U },
  { Hexagon::S20, 164U },
  { Hexagon::S22, 166U },
  { Hexagon::S23, 167U },
  { Hexagon::S24, 168U },
  { Hexagon::S25, 169U },
  { Hexagon::S26, 170U },
  { Hexagon::S35, 179U },
  { Hexagon::S44, 188U },
  { Hexagon::S45, 189U },
  { Hexagon::S46, 190U },
  { Hexagon::S47, 191U },
  { Hexagon::S54, 198U },
  { Hexagon::S55, 199U },
  { Hexagon::S56, 200U },
  { Hexagon::S57, 201U },
  { Hexagon::S58, 202U },
  { Hexagon::S59, 203U },
  { Hexagon::S60, 204U },
  { Hexagon::S61, 205U },
  { Hexagon::S62, 206U },
  { Hexagon::S63, 207U },
  { Hexagon::S64, 208U },
  { Hexagon::S65, 209U },
  { Hexagon::S66, 210U },
  { Hexagon::S67, 211U },
  { Hexagon::S68, 212U },
  { Hexagon::S69, 213U },
  { Hexagon::S70, 214U },
  { Hexagon::S71, 215U },
  { Hexagon::S72, 216U },
  { Hexagon::S73, 217U },
  { Hexagon::S74, 218U },
  { Hexagon::S75, 219U },
  { Hexagon::S76, 220U },
  { Hexagon::S77, 221U },
  { Hexagon::S78, 222U },
  { Hexagon::S79, 223U },
  { Hexagon::S80, 224U },
  { Hexagon::SA0, 67U },
  { Hexagon::SA1, 69U },
  { Hexagon::SGP0, 144U },
  { Hexagon::SGP1, 145U },
  { Hexagon::V0, 99U },
  { Hexagon::V1, 100U },
  { Hexagon::V2, 101U },
  { Hexagon::V3, 102U },
  { Hexagon::V4, 103U },
  { Hexagon::V5, 104U },
  { Hexagon::V6, 105U },
  { Hexagon::V7, 106U },
  { Hexagon::V8, 107U },
  { Hexagon::V9, 108U },
  { Hexagon::V10, 109U },
  { Hexagon::V11, 110U },
  { Hexagon::V12, 111U },
  { Hexagon::V13, 112U },
  { Hexagon::V14, 113U },
  { Hexagon::V15, 114U },
  { Hexagon::V16, 115U },
  { Hexagon::V17, 116U },
  { Hexagon::V18, 117U },
  { Hexagon::V19, 118U },
  { Hexagon::V20, 119U },
  { Hexagon::V21, 120U },
  { Hexagon::V22, 121U },
  { Hexagon::V23, 122U },
  { Hexagon::V24, 123U },
  { Hexagon::V25, 124U },
  { Hexagon::V26, 125U },
  { Hexagon::V27, 126U },
  { Hexagon::V28, 127U },
  { Hexagon::V29, 128U },
  { Hexagon::V30, 129U },
  { Hexagon::V31, 130U },
  { Hexagon::VF0, 999999U },
  { Hexagon::VF1, 1000000U },
  { Hexagon::VF2, 1000001U },
  { Hexagon::VF3, 1000002U },
  { Hexagon::VF4, 1000003U },
  { Hexagon::VF5, 1000004U },
  { Hexagon::VF6, 1000005U },
  { Hexagon::VF7, 1000006U },
  { Hexagon::VF8, 1000007U },
  { Hexagon::VF9, 1000008U },
  { Hexagon::VF10, 1000009U },
  { Hexagon::VF11, 1000010U },
  { Hexagon::VF12, 1000011U },
  { Hexagon::VF13, 1000012U },
  { Hexagon::VF14, 1000013U },
  { Hexagon::VF15, 1000014U },
  { Hexagon::VF16, 1000015U },
  { Hexagon::VF17, 1000016U },
  { Hexagon::VF18, 1000017U },
  { Hexagon::VF19, 1000018U },
  { Hexagon::VF20, 1000019U },
  { Hexagon::VF21, 1000020U },
  { Hexagon::VF22, 1000021U },
  { Hexagon::VF23, 1000022U },
  { Hexagon::VF24, 1000023U },
  { Hexagon::VF25, 1000024U },
  { Hexagon::VF26, 1000025U },
  { Hexagon::VF27, 1000026U },
  { Hexagon::VF28, 1000027U },
  { Hexagon::VF29, 1000028U },
  { Hexagon::VF30, 1000029U },
  { Hexagon::VF31, 1000030U },
  { Hexagon::VFR0, 9999999U },
  { Hexagon::VFR1, 10000000U },
  { Hexagon::VFR2, 10000001U },
  { Hexagon::VFR3, 10000002U },
  { Hexagon::VFR4, 10000003U },
  { Hexagon::VFR5, 10000004U },
  { Hexagon::VFR6, 10000005U },
  { Hexagon::VFR7, 10000006U },
  { Hexagon::VFR8, 10000007U },
  { Hexagon::VFR9, 10000008U },
  { Hexagon::VFR10, 10000009U },
  { Hexagon::VFR11, 10000010U },
  { Hexagon::VFR12, 10000011U },
  { Hexagon::VFR13, 10000012U },
  { Hexagon::VFR14, 10000013U },
  { Hexagon::VFR15, 10000014U },
  { Hexagon::VFR16, 10000015U },
  { Hexagon::VFR17, 10000016U },
  { Hexagon::VFR18, 10000017U },
  { Hexagon::VFR19, 10000018U },
  { Hexagon::VFR20, 10000019U },
  { Hexagon::VFR21, 10000020U },
  { Hexagon::VFR22, 10000021U },
  { Hexagon::VFR23, 10000022U },
  { Hexagon::VFR24, 10000023U },
  { Hexagon::VFR25, 10000024U },
  { Hexagon::VFR26, 10000025U },
  { Hexagon::VFR27, 10000026U },
  { Hexagon::VFR28, 10000027U },
  { Hexagon::VFR29, 10000028U },
  { Hexagon::VFR30, 10000029U },
  { Hexagon::VFR31, 10000030U },
  { Hexagon::VQ0, 252U },
  { Hexagon::VQ1, 253U },
  { Hexagon::VQ2, 254U },
  { Hexagon::VQ3, 255U },
  { Hexagon::VQ4, 256U },
  { Hexagon::VQ5, 257U },
  { Hexagon::VQ6, 258U },
  { Hexagon::VQ7, 259U },
  { Hexagon::W0, 99U },
  { Hexagon::W1, 101U },
  { Hexagon::W2, 103U },
  { Hexagon::W3, 105U },
  { Hexagon::W4, 107U },
  { Hexagon::W5, 109U },
  { Hexagon::W6, 111U },
  { Hexagon::W7, 113U },
  { Hexagon::W8, 115U },
  { Hexagon::W9, 117U },
  { Hexagon::W10, 119U },
  { Hexagon::W11, 121U },
  { Hexagon::W12, 123U },
  { Hexagon::W13, 125U },
  { Hexagon::W14, 127U },
  { Hexagon::W15, 129U },
  { Hexagon::WR0, 161U },
  { Hexagon::WR1, 162U },
  { Hexagon::WR2, 163U },
  { Hexagon::WR3, 164U },
  { Hexagon::WR4, 165U },
  { Hexagon::WR5, 166U },
  { Hexagon::WR6, 167U },
  { Hexagon::WR7, 168U },
  { Hexagon::WR8, 169U },
  { Hexagon::WR9, 170U },
  { Hexagon::WR10, 171U },
  { Hexagon::WR11, 172U },
  { Hexagon::WR12, 173U },
  { Hexagon::WR13, 174U },
  { Hexagon::WR14, 175U },
  { Hexagon::WR15, 176U },
  { Hexagon::C1_0, 67U },
  { Hexagon::C3_2, 69U },
  { Hexagon::C5_4, 71U },
  { Hexagon::C7_6, 72U },
  { Hexagon::C9_8, 74U },
  { Hexagon::C11_10, 76U },
  { Hexagon::C17_16, 83U },
  { Hexagon::G1_0, 220U },
  { Hexagon::G3_2, 222U },
  { Hexagon::G5_4, 224U },
  { Hexagon::G7_6, 226U },
  { Hexagon::G9_8, 228U },
  { Hexagon::G11_10, 230U },
  { Hexagon::G13_12, 232U },
  { Hexagon::G15_14, 234U },
  { Hexagon::G17_16, 236U },
  { Hexagon::G19_18, 238U },
  { Hexagon::G21_20, 240U },
  { Hexagon::G23_22, 242U },
  { Hexagon::G25_24, 244U },
  { Hexagon::G27_26, 246U },
  { Hexagon::G29_28, 248U },
  { Hexagon::G31_30, 250U },
  { Hexagon::P3_0, 71U },
  { Hexagon::S3_2, 146U },
  { Hexagon::S5_4, 148U },
  { Hexagon::S7_6, 150U },
  { Hexagon::S9_8, 152U },
  { Hexagon::S11_10, 154U },
  { Hexagon::S13_12, 156U },
  { Hexagon::S15_14, 158U },
  { Hexagon::S17_16, 160U },
  { Hexagon::S19_18, 162U },
  { Hexagon::S21_20, 164U },
  { Hexagon::S23_22, 166U },
  { Hexagon::S25_24, 168U },
  { Hexagon::S27_26, 170U },
  { Hexagon::S29_28, 172U },
  { Hexagon::S31_30, 174U },
  { Hexagon::S33_32, 176U },
  { Hexagon::S35_34, 178U },
  { Hexagon::S37_36, 180U },
  { Hexagon::S39_38, 182U },
  { Hexagon::S41_40, 184U },
  { Hexagon::S43_42, 186U },
  { Hexagon::S45_44, 188U },
  { Hexagon::S47_46, 190U },
  { Hexagon::S49_48, 192U },
  { Hexagon::S51_50, 194U },
  { Hexagon::S53_52, 196U },
  { Hexagon::S55_54, 198U },
  { Hexagon::S57_56, 200U },
  { Hexagon::S59_58, 202U },
  { Hexagon::S61_60, 204U },
  { Hexagon::S63_62, 206U },
  { Hexagon::S65_64, 208U },
  { Hexagon::S67_66, 210U },
  { Hexagon::S69_68, 212U },
  { Hexagon::S71_70, 214U },
  { Hexagon::S73_72, 216U },
  { Hexagon::S75_74, 218U },
  { Hexagon::S77_76, 219U },
  { Hexagon::S79_78, 220U },
  { Hexagon::SGP1_0, 144U },
};
extern const unsigned HexagonEHFlavour0L2DwarfSize = std::size(HexagonEHFlavour0L2Dwarf);

extern const uint16_t HexagonRegEncodingTable[] = {
  0,
  9,
  7,
  27,
  12,
  28,
  3,
  16,
  17,
  16,
  0,
  2,
  11,
  25,
  24,
  1,
  8,
  10,
  42,
  43,
  40,
  41,
  32,
  17,
  9,
  31,
  30,
  18,
  19,
  18,
  53,
  52,
  29,
  6,
  2,
  18,
  10,
  14,
  15,
  14,
  8,
  0,
  30,
  31,
  30,
  21,
  0,
  4,
  5,
  37,
  39,
  36,
  38,
  5,
  8,
  12,
  13,
  0,
  2,
  4,
  6,
  8,
  10,
  12,
  14,
  16,
  18,
  20,
  22,
  24,
  26,
  28,
  30,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  20,
  21,
  22,
  23,
  30,
  31,
  26,
  27,
  28,
  29,
  16,
  17,
  18,
  19,
  33,
  34,
  1,
  3,
  6,
  7,
  0,
  1,
  2,
  3,
  48,
  49,
  50,
  51,
  0,
  1,
  2,
  3,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  11,
  12,
  13,
  14,
  15,
  19,
  20,
  22,
  23,
  24,
  25,
  26,
  35,
  44,
  45,
  46,
  47,
  54,
  55,
  56,
  57,
  58,
  59,
  60,
  61,
  62,
  63,
  64,
  65,
  66,
  67,
  68,
  69,
  70,
  71,
  72,
  73,
  74,
  75,
  76,
  77,
  78,
  79,
  80,
  0,
  2,
  0,
  1,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  4,
  8,
  12,
  16,
  20,
  24,
  28,
  0,
  2,
  4,
  6,
  8,
  10,
  12,
  14,
  16,
  18,
  20,
  22,
  24,
  26,
  28,
  30,
  1,
  3,
  5,
  7,
  9,
  11,
  13,
  15,
  17,
  19,
  21,
  23,
  25,
  27,
  29,
  31,
  0,
  2,
  4,
  6,
  8,
  10,
  16,
  0,
  2,
  4,
  6,
  8,
  10,
  12,
  14,
  16,
  18,
  20,
  22,
  24,
  26,
  28,
  30,
  4,
  2,
  4,
  6,
  8,
  10,
  12,
  14,
  16,
  18,
  20,
  22,
  24,
  26,
  28,
  30,
  32,
  34,
  36,
  38,
  40,
  42,
  44,
  46,
  48,
  50,
  52,
  54,
  56,
  58,
  60,
  62,
  64,
  66,
  68,
  70,
  72,
  74,
  76,
  78,
  0,
};
static inline void InitHexagonMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
  RI->InitMCRegisterInfo(HexagonRegDesc, 398, RA, PC, HexagonMCRegisterClasses, 29, HexagonRegUnitRoots, 272, HexagonRegDiffLists, HexagonLaneMaskLists, HexagonRegStrings, HexagonRegClassStrings, HexagonSubRegIdxLists, 12,
HexagonSubRegIdxRanges, HexagonRegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(HexagonDwarfFlavour0Dwarf2L, HexagonDwarfFlavour0Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(HexagonEHFlavour0Dwarf2L, HexagonEHFlavour0Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(HexagonDwarfFlavour0L2Dwarf, HexagonDwarfFlavour0L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(HexagonEHFlavour0L2Dwarf, HexagonEHFlavour0L2DwarfSize, true);
    break;
  }
}

} // end namespace llvm

#endif // GET_REGINFO_MC_DESC

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Register Information Header Fragment                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_HEADER
#undef GET_REGINFO_HEADER

#include "llvm/CodeGen/TargetRegisterInfo.h"

namespace llvm {

class HexagonFrameLowering;

struct HexagonGenRegisterInfo : public TargetRegisterInfo {
  explicit HexagonGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
      unsigned PC = 0, unsigned HwMode = 0);
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
  const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
  unsigned getNumRegPressureSets() const override;
  const char *getRegPressureSetName(unsigned Idx) const override;
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
  ArrayRef<const char *> getRegMaskNames() const override;
  ArrayRef<const uint32_t *> getRegMasks() const override;
  bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
  bool isFixedRegister(const MachineFunction &, MCRegister) const override;
  bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
  bool isConstantPhysReg(MCRegister PhysReg) const override final;
  /// Devirtualized TargetFrameLowering.
  static const HexagonFrameLowering *getFrameLowering(
      const MachineFunction &MF);
};

namespace Hexagon { // Register classes
  extern const TargetRegisterClass UsrBitsRegClass;
  extern const TargetRegisterClass SysRegsRegClass;
  extern const TargetRegisterClass GuestRegsRegClass;
  extern const TargetRegisterClass IntRegsRegClass;
  extern const TargetRegisterClass CtrRegsRegClass;
  extern const TargetRegisterClass GeneralSubRegsRegClass;
  extern const TargetRegisterClass V62RegsRegClass;
  extern const TargetRegisterClass IntRegsLow8RegClass;
  extern const TargetRegisterClass CtrRegs_and_V62RegsRegClass;
  extern const TargetRegisterClass PredRegsRegClass;
  extern const TargetRegisterClass V62Regs_with_isub_hiRegClass;
  extern const TargetRegisterClass ModRegsRegClass;
  extern const TargetRegisterClass CtrRegs_with_subreg_overflowRegClass;
  extern const TargetRegisterClass V65RegsRegClass;
  extern const TargetRegisterClass SysRegs64RegClass;
  extern const TargetRegisterClass DoubleRegsRegClass;
  extern const TargetRegisterClass GuestRegs64RegClass;
  extern const TargetRegisterClass VectRegRevRegClass;
  extern const TargetRegisterClass CtrRegs64RegClass;
  extern const TargetRegisterClass GeneralDoubleLow8RegsRegClass;
  extern const TargetRegisterClass DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass;
  extern const TargetRegisterClass CtrRegs64_and_V62RegsRegClass;
  extern const TargetRegisterClass CtrRegs64_with_isub_hi_in_ModRegsRegClass;
  extern const TargetRegisterClass HvxQRRegClass;
  extern const TargetRegisterClass HvxVRRegClass;
  extern const TargetRegisterClass HvxVR_and_V65RegsRegClass;
  extern const TargetRegisterClass HvxWRRegClass;
  extern const TargetRegisterClass HvxWR_and_VectRegRevRegClass;
  extern const TargetRegisterClass HvxVQRRegClass;
} // end namespace Hexagon

} // end namespace llvm

#endif // GET_REGINFO_HEADER

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register and Register Classes Information                           *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_TARGET_DESC
#undef GET_REGINFO_TARGET_DESC

namespace llvm {

extern const MCRegisterClass HexagonMCRegisterClasses[];

static const MVT::SimpleValueType VTLists[] = {
  /* 0 */ MVT::i1, MVT::Other,
  /* 2 */ MVT::i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v4i8, MVT::v2i16, MVT::i32, MVT::Other,
  /* 10 */ MVT::i64, MVT::Other,
  /* 12 */ MVT::v64i1, MVT::v64i1, MVT::v32i1, MVT::v16i1, MVT::Other,
  /* 17 */ MVT::v128i1, MVT::v128i1, MVT::v64i1, MVT::v32i1, MVT::Other,
  /* 22 */ MVT::i32, MVT::f32, MVT::v4i8, MVT::v2i16, MVT::Other,
  /* 27 */ MVT::i64, MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::Other,
  /* 33 */ MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v32f16, MVT::v16f32, MVT::Other,
  /* 39 */ MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v64f16, MVT::v32f32, MVT::Other,
  /* 45 */ MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::v128f16, MVT::v64f32, MVT::Other,
  /* 51 */ MVT::Untyped, MVT::Other,
};

static const char *SubRegIndexNameTable[] = { "isub_hi", "isub_lo", "subreg_overflow", "vsub_fake", "vsub_hi", "vsub_lo", "wsub_hi", "wsub_lo", "wsub_hi_then_vsub_fake", "wsub_hi_then_vsub_hi", "wsub_hi_then_vsub_lo", "" };


static const LaneBitmask SubRegIndexLaneMaskTable[] = {
  LaneBitmask::getAll(),
  LaneBitmask(0x0000000000000001), // isub_hi
  LaneBitmask(0x0000000000000002), // isub_lo
  LaneBitmask(0x0000000000000004), // subreg_overflow
  LaneBitmask(0x0000000000000008), // vsub_fake
  LaneBitmask(0x0000000000000010), // vsub_hi
  LaneBitmask(0x0000000000000020), // vsub_lo
  LaneBitmask(0x00000000000001C0), // wsub_hi
  LaneBitmask(0x0000000000000038), // wsub_lo
  LaneBitmask(0x0000000000000040), // wsub_hi_then_vsub_fake
  LaneBitmask(0x0000000000000080), // wsub_hi_then_vsub_hi
  LaneBitmask(0x0000000000000100), // wsub_hi_then_vsub_lo
 };



static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
  // Mode = 0 (Default)
  { 1, 1, 0, /*VTLists+*/0 },    // UsrBits
  { 32, 32, 32, /*VTLists+*/8 },    // SysRegs
  { 32, 32, 32, /*VTLists+*/8 },    // GuestRegs
  { 32, 32, 32, /*VTLists+*/22 },    // IntRegs
  { 32, 32, 32, /*VTLists+*/8 },    // CtrRegs
  { 32, 32, 32, /*VTLists+*/8 },    // GeneralSubRegs
  { 32, 32, 32, /*VTLists+*/8 },    // V62Regs
  { 32, 32, 32, /*VTLists+*/8 },    // IntRegsLow8
  { 32, 32, 32, /*VTLists+*/8 },    // CtrRegs_and_V62Regs
  { 32, 32, 32, /*VTLists+*/2 },    // PredRegs
  { 32, 32, 32, /*VTLists+*/8 },    // V62Regs_with_isub_hi
  { 32, 32, 32, /*VTLists+*/8 },    // ModRegs
  { 32, 32, 32, /*VTLists+*/8 },    // CtrRegs_with_subreg_overflow
  { 32, 32, 32, /*VTLists+*/8 },    // V65Regs
  { 64, 64, 64, /*VTLists+*/10 },    // SysRegs64
  { 64, 64, 64, /*VTLists+*/27 },    // DoubleRegs
  { 64, 64, 64, /*VTLists+*/10 },    // GuestRegs64
  { 64, 64, 64, /*VTLists+*/10 },    // VectRegRev
  { 64, 64, 64, /*VTLists+*/10 },    // CtrRegs64
  { 64, 64, 64, /*VTLists+*/10 },    // GeneralDoubleLow8Regs
  { 64, 64, 64, /*VTLists+*/10 },    // DoubleRegs_with_isub_hi_in_IntRegsLow8
  { 64, 64, 64, /*VTLists+*/10 },    // CtrRegs64_and_V62Regs
  { 64, 64, 64, /*VTLists+*/10 },    // CtrRegs64_with_isub_hi_in_ModRegs
  { 64, 512, 512, /*VTLists+*/12 },    // HvxQR
  { 512, 512, 512, /*VTLists+*/33 },    // HvxVR
  { 512, 512, 512, /*VTLists+*/33 },    // HvxVR_and_V65Regs
  { 1024, 1024, 512, /*VTLists+*/39 },    // HvxWR
  { 1024, 1024, 512, /*VTLists+*/39 },    // HvxWR_and_VectRegRev
  { 2048, 2048, 512, /*VTLists+*/51 },    // HvxVQR
  // Mode = 1 (Hvx64)
  { 1, 1, 0, /*VTLists+*/0 },    // UsrBits
  { 32, 32, 32, /*VTLists+*/8 },    // SysRegs
  { 32, 32, 32, /*VTLists+*/8 },    // GuestRegs
  { 32, 32, 32, /*VTLists+*/22 },    // IntRegs
  { 32, 32, 32, /*VTLists+*/8 },    // CtrRegs
  { 32, 32, 32, /*VTLists+*/8 },    // GeneralSubRegs
  { 32, 32, 32, /*VTLists+*/8 },    // V62Regs
  { 32, 32, 32, /*VTLists+*/8 },    // IntRegsLow8
  { 32, 32, 32, /*VTLists+*/8 },    // CtrRegs_and_V62Regs
  { 32, 32, 32, /*VTLists+*/2 },    // PredRegs
  { 32, 32, 32, /*VTLists+*/8 },    // V62Regs_with_isub_hi
  { 32, 32, 32, /*VTLists+*/8 },    // ModRegs
  { 32, 32, 32, /*VTLists+*/8 },    // CtrRegs_with_subreg_overflow
  { 32, 32, 32, /*VTLists+*/8 },    // V65Regs
  { 64, 64, 64, /*VTLists+*/10 },    // SysRegs64
  { 64, 64, 64, /*VTLists+*/27 },    // DoubleRegs
  { 64, 64, 64, /*VTLists+*/10 },    // GuestRegs64
  { 64, 64, 64, /*VTLists+*/10 },    // VectRegRev
  { 64, 64, 64, /*VTLists+*/10 },    // CtrRegs64
  { 64, 64, 64, /*VTLists+*/10 },    // GeneralDoubleLow8Regs
  { 64, 64, 64, /*VTLists+*/10 },    // DoubleRegs_with_isub_hi_in_IntRegsLow8
  { 64, 64, 64, /*VTLists+*/10 },    // CtrRegs64_and_V62Regs
  { 64, 64, 64, /*VTLists+*/10 },    // CtrRegs64_with_isub_hi_in_ModRegs
  { 64, 512, 512, /*VTLists+*/12 },    // HvxQR
  { 512, 512, 512, /*VTLists+*/33 },    // HvxVR
  { 512, 512, 512, /*VTLists+*/33 },    // HvxVR_and_V65Regs
  { 1024, 1024, 512, /*VTLists+*/39 },    // HvxWR
  { 1024, 1024, 512, /*VTLists+*/39 },    // HvxWR_and_VectRegRev
  { 2048, 2048, 512, /*VTLists+*/51 },    // HvxVQR
  // Mode = 2 (Hvx128)
  { 1, 1, 0, /*VTLists+*/0 },    // UsrBits
  { 32, 32, 32, /*VTLists+*/8 },    // SysRegs
  { 32, 32, 32, /*VTLists+*/8 },    // GuestRegs
  { 32, 32, 32, /*VTLists+*/22 },    // IntRegs
  { 32, 32, 32, /*VTLists+*/8 },    // CtrRegs
  { 32, 32, 32, /*VTLists+*/8 },    // GeneralSubRegs
  { 32, 32, 32, /*VTLists+*/8 },    // V62Regs
  { 32, 32, 32, /*VTLists+*/8 },    // IntRegsLow8
  { 32, 32, 32, /*VTLists+*/8 },    // CtrRegs_and_V62Regs
  { 32, 32, 32, /*VTLists+*/2 },    // PredRegs
  { 32, 32, 32, /*VTLists+*/8 },    // V62Regs_with_isub_hi
  { 32, 32, 32, /*VTLists+*/8 },    // ModRegs
  { 32, 32, 32, /*VTLists+*/8 },    // CtrRegs_with_subreg_overflow
  { 32, 32, 32, /*VTLists+*/8 },    // V65Regs
  { 64, 64, 64, /*VTLists+*/10 },    // SysRegs64
  { 64, 64, 64, /*VTLists+*/27 },    // DoubleRegs
  { 64, 64, 64, /*VTLists+*/10 },    // GuestRegs64
  { 64, 64, 64, /*VTLists+*/10 },    // VectRegRev
  { 64, 64, 64, /*VTLists+*/10 },    // CtrRegs64
  { 64, 64, 64, /*VTLists+*/10 },    // GeneralDoubleLow8Regs
  { 64, 64, 64, /*VTLists+*/10 },    // DoubleRegs_with_isub_hi_in_IntRegsLow8
  { 64, 64, 64, /*VTLists+*/10 },    // CtrRegs64_and_V62Regs
  { 64, 64, 64, /*VTLists+*/10 },    // CtrRegs64_with_isub_hi_in_ModRegs
  { 128, 1024, 1024, /*VTLists+*/17 },    // HvxQR
  { 1024, 1024, 1024, /*VTLists+*/39 },    // HvxVR
  { 1024, 1024, 1024, /*VTLists+*/39 },    // HvxVR_and_V65Regs
  { 2048, 2048, 1024, /*VTLists+*/45 },    // HvxWR
  { 2048, 2048, 1024, /*VTLists+*/45 },    // HvxWR_and_VectRegRev
  { 4096, 4096, 1024, /*VTLists+*/51 },    // HvxVQR
};

static const TargetRegisterClass *const NullRegClasses[] = { nullptr };

static const uint32_t UsrBitsSubClassMask[] = {
  0x00000001, 
  0x00001000, // subreg_overflow
};

static const uint32_t SysRegsSubClassMask[] = {
  0x00000002, 
  0x00004000, // isub_hi
  0x00004000, // isub_lo
};

static const uint32_t GuestRegsSubClassMask[] = {
  0x00000004, 
  0x00010000, // isub_hi
  0x00010000, // isub_lo
};

static const uint32_t IntRegsSubClassMask[] = {
  0x000000a8, 
  0x00188000, // isub_hi
  0x00188000, // isub_lo
};

static const uint32_t CtrRegsSubClassMask[] = {
  0x00001910, 
  0x00640400, // isub_hi
  0x00640400, // isub_lo
};

static const uint32_t GeneralSubRegsSubClassMask[] = {
  0x000000a0, 
  0x00180000, // isub_hi
  0x00180000, // isub_lo
};

static const uint32_t V62RegsSubClassMask[] = {
  0x00200540, 
  0x00200400, // isub_hi
  0x00200400, // isub_lo
};

static const uint32_t IntRegsLow8SubClassMask[] = {
  0x00000080, 
  0x00100000, // isub_hi
  0x00100000, // isub_lo
};

static const uint32_t CtrRegs_and_V62RegsSubClassMask[] = {
  0x00000100, 
  0x00200400, // isub_hi
  0x00200400, // isub_lo
};

static const uint32_t PredRegsSubClassMask[] = {
  0x00000200, 
};

static const uint32_t V62Regs_with_isub_hiSubClassMask[] = {
  0x00200400, 
};

static const uint32_t ModRegsSubClassMask[] = {
  0x00000800, 
  0x00400000, // isub_hi
  0x00400000, // isub_lo
};

static const uint32_t CtrRegs_with_subreg_overflowSubClassMask[] = {
  0x00001000, 
};

static const uint32_t V65RegsSubClassMask[] = {
  0x02002000, 
};

static const uint32_t SysRegs64SubClassMask[] = {
  0x00004000, 
};

static const uint32_t DoubleRegsSubClassMask[] = {
  0x00188000, 
};

static const uint32_t GuestRegs64SubClassMask[] = {
  0x00010000, 
};

static const uint32_t VectRegRevSubClassMask[] = {
  0x08020000, 
};

static const uint32_t CtrRegs64SubClassMask[] = {
  0x00640000, 
};

static const uint32_t GeneralDoubleLow8RegsSubClassMask[] = {
  0x00180000, 
};

static const uint32_t DoubleRegs_with_isub_hi_in_IntRegsLow8SubClassMask[] = {
  0x00100000, 
};

static const uint32_t CtrRegs64_and_V62RegsSubClassMask[] = {
  0x00200000, 
};

static const uint32_t CtrRegs64_with_isub_hi_in_ModRegsSubClassMask[] = {
  0x00400000, 
};

static const uint32_t HvxQRSubClassMask[] = {
  0x00800000, 
};

static const uint32_t HvxVRSubClassMask[] = {
  0x03000000, 
  0x1c020000, // vsub_hi
  0x1c020000, // vsub_lo
  0x10000000, // wsub_hi_then_vsub_hi
  0x10000000, // wsub_hi_then_vsub_lo
};

static const uint32_t HvxVR_and_V65RegsSubClassMask[] = {
  0x02000000, 
};

static const uint32_t HvxWRSubClassMask[] = {
  0x0c000000, 
  0x10000000, // wsub_hi
  0x10000000, // wsub_lo
};

static const uint32_t HvxWR_and_VectRegRevSubClassMask[] = {
  0x08000000, 
};

static const uint32_t HvxVQRSubClassMask[] = {
  0x10000000, 
};

static const uint16_t SuperRegIdxSeqs[] = {
  /* 0 */ 1, 2, 0,
  /* 3 */ 3, 0,
  /* 5 */ 7, 8, 0,
  /* 8 */ 5, 6, 10, 11, 0,
};

static const TargetRegisterClass *const GeneralSubRegsSuperclasses[] = {
  &Hexagon::IntRegsRegClass,
  nullptr
};

static const TargetRegisterClass *const IntRegsLow8Superclasses[] = {
  &Hexagon::IntRegsRegClass,
  &Hexagon::GeneralSubRegsRegClass,
  nullptr
};

static const TargetRegisterClass *const CtrRegs_and_V62RegsSuperclasses[] = {
  &Hexagon::CtrRegsRegClass,
  &Hexagon::V62RegsRegClass,
  nullptr
};

static const TargetRegisterClass *const V62Regs_with_isub_hiSuperclasses[] = {
  &Hexagon::V62RegsRegClass,
  nullptr
};

static const TargetRegisterClass *const ModRegsSuperclasses[] = {
  &Hexagon::CtrRegsRegClass,
  nullptr
};

static const TargetRegisterClass *const CtrRegs_with_subreg_overflowSuperclasses[] = {
  &Hexagon::CtrRegsRegClass,
  nullptr
};

static const TargetRegisterClass *const GeneralDoubleLow8RegsSuperclasses[] = {
  &Hexagon::DoubleRegsRegClass,
  nullptr
};

static const TargetRegisterClass *const DoubleRegs_with_isub_hi_in_IntRegsLow8Superclasses[] = {
  &Hexagon::DoubleRegsRegClass,
  &Hexagon::GeneralDoubleLow8RegsRegClass,
  nullptr
};

static const TargetRegisterClass *const CtrRegs64_and_V62RegsSuperclasses[] = {
  &Hexagon::V62RegsRegClass,
  &Hexagon::V62Regs_with_isub_hiRegClass,
  &Hexagon::CtrRegs64RegClass,
  nullptr
};

static const TargetRegisterClass *const CtrRegs64_with_isub_hi_in_ModRegsSuperclasses[] = {
  &Hexagon::CtrRegs64RegClass,
  nullptr
};

static const TargetRegisterClass *const HvxVR_and_V65RegsSuperclasses[] = {
  &Hexagon::V65RegsRegClass,
  &Hexagon::HvxVRRegClass,
  nullptr
};

static const TargetRegisterClass *const HvxWR_and_VectRegRevSuperclasses[] = {
  &Hexagon::VectRegRevRegClass,
  &Hexagon::HvxWRRegClass,
  nullptr
};


namespace Hexagon {   // Register class instances
  extern const TargetRegisterClass UsrBitsRegClass = {
    &HexagonMCRegisterClasses[UsrBitsRegClassID],
    UsrBitsSubClassMask,
    SuperRegIdxSeqs + 3,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass SysRegsRegClass = {
    &HexagonMCRegisterClasses[SysRegsRegClassID],
    SysRegsSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GuestRegsRegClass = {
    &HexagonMCRegisterClasses[GuestRegsRegClassID],
    GuestRegsSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass IntRegsRegClass = {
    &HexagonMCRegisterClasses[IntRegsRegClassID],
    IntRegsSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass CtrRegsRegClass = {
    &HexagonMCRegisterClasses[CtrRegsRegClassID],
    CtrRegsSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000004),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GeneralSubRegsRegClass = {
    &HexagonMCRegisterClasses[GeneralSubRegsRegClassID],
    GeneralSubRegsSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GeneralSubRegsSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass V62RegsRegClass = {
    &HexagonMCRegisterClasses[V62RegsRegClassID],
    V62RegsSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass IntRegsLow8RegClass = {
    &HexagonMCRegisterClasses[IntRegsLow8RegClassID],
    IntRegsLow8SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    IntRegsLow8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass CtrRegs_and_V62RegsRegClass = {
    &HexagonMCRegisterClasses[CtrRegs_and_V62RegsRegClassID],
    CtrRegs_and_V62RegsSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    CtrRegs_and_V62RegsSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass PredRegsRegClass = {
    &HexagonMCRegisterClasses[PredRegsRegClassID],
    PredRegsSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass V62Regs_with_isub_hiRegClass = {
    &HexagonMCRegisterClasses[V62Regs_with_isub_hiRegClassID],
    V62Regs_with_isub_hiSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    V62Regs_with_isub_hiSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass ModRegsRegClass = {
    &HexagonMCRegisterClasses[ModRegsRegClassID],
    ModRegsSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    ModRegsSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass CtrRegs_with_subreg_overflowRegClass = {
    &HexagonMCRegisterClasses[CtrRegs_with_subreg_overflowRegClassID],
    CtrRegs_with_subreg_overflowSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000004),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    CtrRegs_with_subreg_overflowSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass V65RegsRegClass = {
    &HexagonMCRegisterClasses[V65RegsRegClassID],
    V65RegsSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass SysRegs64RegClass = {
    &HexagonMCRegisterClasses[SysRegs64RegClassID],
    SysRegs64SubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass DoubleRegsRegClass = {
    &HexagonMCRegisterClasses[DoubleRegsRegClassID],
    DoubleRegsSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GuestRegs64RegClass = {
    &HexagonMCRegisterClasses[GuestRegs64RegClassID],
    GuestRegs64SubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VectRegRevRegClass = {
    &HexagonMCRegisterClasses[VectRegRevRegClassID],
    VectRegRevSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000030),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass CtrRegs64RegClass = {
    &HexagonMCRegisterClasses[CtrRegs64RegClassID],
    CtrRegs64SubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GeneralDoubleLow8RegsRegClass = {
    &HexagonMCRegisterClasses[GeneralDoubleLow8RegsRegClassID],
    GeneralDoubleLow8RegsSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GeneralDoubleLow8RegsSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass = {
    &HexagonMCRegisterClasses[DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID],
    DoubleRegs_with_isub_hi_in_IntRegsLow8SubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DoubleRegs_with_isub_hi_in_IntRegsLow8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass CtrRegs64_and_V62RegsRegClass = {
    &HexagonMCRegisterClasses[CtrRegs64_and_V62RegsRegClassID],
    CtrRegs64_and_V62RegsSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    CtrRegs64_and_V62RegsSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass CtrRegs64_with_isub_hi_in_ModRegsRegClass = {
    &HexagonMCRegisterClasses[CtrRegs64_with_isub_hi_in_ModRegsRegClassID],
    CtrRegs64_with_isub_hi_in_ModRegsSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    CtrRegs64_with_isub_hi_in_ModRegsSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass HvxQRRegClass = {
    &HexagonMCRegisterClasses[HvxQRRegClassID],
    HvxQRSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass HvxVRRegClass = {
    &HexagonMCRegisterClasses[HvxVRRegClassID],
    HvxVRSubClassMask,
    SuperRegIdxSeqs + 8,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass HvxVR_and_V65RegsRegClass = {
    &HexagonMCRegisterClasses[HvxVR_and_V65RegsRegClassID],
    HvxVR_and_V65RegsSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    HvxVR_and_V65RegsSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass HvxWRRegClass = {
    &HexagonMCRegisterClasses[HvxWRRegClassID],
    HvxWRSubClassMask,
    SuperRegIdxSeqs + 5,
    LaneBitmask(0x0000000000000030),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass HvxWR_and_VectRegRevRegClass = {
    &HexagonMCRegisterClasses[HvxWR_and_VectRegRevRegClassID],
    HvxWR_and_VectRegRevSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000030),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    HvxWR_and_VectRegRevSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass HvxVQRRegClass = {
    &HexagonMCRegisterClasses[HvxVQRRegClassID],
    HvxVQRSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x00000000000001F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

} // end namespace Hexagon

namespace {
  const TargetRegisterClass *const RegisterClasses[] = {
    &Hexagon::UsrBitsRegClass,
    &Hexagon::SysRegsRegClass,
    &Hexagon::GuestRegsRegClass,
    &Hexagon::IntRegsRegClass,
    &Hexagon::CtrRegsRegClass,
    &Hexagon::GeneralSubRegsRegClass,
    &Hexagon::V62RegsRegClass,
    &Hexagon::IntRegsLow8RegClass,
    &Hexagon::CtrRegs_and_V62RegsRegClass,
    &Hexagon::PredRegsRegClass,
    &Hexagon::V62Regs_with_isub_hiRegClass,
    &Hexagon::ModRegsRegClass,
    &Hexagon::CtrRegs_with_subreg_overflowRegClass,
    &Hexagon::V65RegsRegClass,
    &Hexagon::SysRegs64RegClass,
    &Hexagon::DoubleRegsRegClass,
    &Hexagon::GuestRegs64RegClass,
    &Hexagon::VectRegRevRegClass,
    &Hexagon::CtrRegs64RegClass,
    &Hexagon::GeneralDoubleLow8RegsRegClass,
    &Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass,
    &Hexagon::CtrRegs64_and_V62RegsRegClass,
    &Hexagon::CtrRegs64_with_isub_hi_in_ModRegsRegClass,
    &Hexagon::HvxQRRegClass,
    &Hexagon::HvxVRRegClass,
    &Hexagon::HvxVR_and_V65RegsRegClass,
    &Hexagon::HvxWRRegClass,
    &Hexagon::HvxWR_and_VectRegRevRegClass,
    &Hexagon::HvxVQRRegClass,
  };
} // end anonymous namespace

static const uint8_t CostPerUseTable[] = { 
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };


static const bool InAllocatableClassTable[] = { 
false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, };


static const TargetRegisterInfoDesc HexagonRegInfoDesc = { // Extra Descriptors
CostPerUseTable, 1, InAllocatableClassTable};

unsigned HexagonGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
  static const uint8_t RowMap[11] = {
    0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
  };
  static const uint8_t Rows[2][11] = {
    { 0, 0, 0, Hexagon::wsub_hi_then_vsub_fake, Hexagon::wsub_hi_then_vsub_hi, Hexagon::wsub_hi_then_vsub_lo, 0, 0, 0, 0, 0, },
    { 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, 0, 0, 0, 0, 0, },
  };

  --IdxA; assert(IdxA < 11); (void) IdxA;
  --IdxB; assert(IdxB < 11);
  return Rows[RowMap[IdxA]][IdxB];
}

  struct MaskRolOp {
    LaneBitmask Mask;
    uint8_t  RotateLeft;
  };
  static const MaskRolOp LaneMaskComposeSequences[] = {
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 6
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 8
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 10
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  6 }, { LaneBitmask::getNone(), 0 },   // Sequence 12
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  7 }, { LaneBitmask::getNone(), 0 },   // Sequence 14
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  8 }, { LaneBitmask::getNone(), 0 }  // Sequence 16
  };
  static const uint8_t CompositeSequences[] = {
    0, // to isub_hi
    2, // to isub_lo
    4, // to subreg_overflow
    6, // to vsub_fake
    8, // to vsub_hi
    10, // to vsub_lo
    6, // to wsub_hi
    0, // to wsub_lo
    12, // to wsub_hi_then_vsub_fake
    14, // to wsub_hi_then_vsub_hi
    16 // to wsub_hi_then_vsub_lo
  };

LaneBitmask HexagonGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
  --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops =
       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
       Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

LaneBitmask HexagonGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
  LaneMask &= getSubRegIndexLaneMask(IdxA);
  --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops =
       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
       Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

const TargetRegisterClass *HexagonGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
  static const uint8_t Table[29][11] = {
    { // UsrBits
      0,  // isub_hi
      0,  // isub_lo
      0,  // subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // SysRegs
      0,  // isub_hi
      0,  // isub_lo
      0,  // subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // GuestRegs
      0,  // isub_hi
      0,  // isub_lo
      0,  // subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // IntRegs
      0,  // isub_hi
      0,  // isub_lo
      0,  // subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // CtrRegs
      0,  // isub_hi
      0,  // isub_lo
      13, // subreg_overflow -> CtrRegs_with_subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // GeneralSubRegs
      0,  // isub_hi
      0,  // isub_lo
      0,  // subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // V62Regs
      11, // isub_hi -> V62Regs_with_isub_hi
      11, // isub_lo -> V62Regs_with_isub_hi
      0,  // subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // IntRegsLow8
      0,  // isub_hi
      0,  // isub_lo
      0,  // subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // CtrRegs_and_V62Regs
      0,  // isub_hi
      0,  // isub_lo
      0,  // subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // PredRegs
      0,  // isub_hi
      0,  // isub_lo
      0,  // subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // V62Regs_with_isub_hi
      11, // isub_hi -> V62Regs_with_isub_hi
      11, // isub_lo -> V62Regs_with_isub_hi
      0,  // subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // ModRegs
      0,  // isub_hi
      0,  // isub_lo
      0,  // subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // CtrRegs_with_subreg_overflow
      0,  // isub_hi
      0,  // isub_lo
      13, // subreg_overflow -> CtrRegs_with_subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // V65Regs
      0,  // isub_hi
      0,  // isub_lo
      0,  // subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // SysRegs64
      15, // isub_hi -> SysRegs64
      15, // isub_lo -> SysRegs64
      0,  // subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // DoubleRegs
      16, // isub_hi -> DoubleRegs
      16, // isub_lo -> DoubleRegs
      0,  // subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // GuestRegs64
      17, // isub_hi -> GuestRegs64
      17, // isub_lo -> GuestRegs64
      0,  // subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // VectRegRev
      0,  // isub_hi
      0,  // isub_lo
      0,  // subreg_overflow
      0,  // vsub_fake
      18, // vsub_hi -> VectRegRev
      18, // vsub_lo -> VectRegRev
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // CtrRegs64
      19, // isub_hi -> CtrRegs64
      19, // isub_lo -> CtrRegs64
      0,  // subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // GeneralDoubleLow8Regs
      20, // isub_hi -> GeneralDoubleLow8Regs
      20, // isub_lo -> GeneralDoubleLow8Regs
      0,  // subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // DoubleRegs_with_isub_hi_in_IntRegsLow8
      21, // isub_hi -> DoubleRegs_with_isub_hi_in_IntRegsLow8
      21, // isub_lo -> DoubleRegs_with_isub_hi_in_IntRegsLow8
      0,  // subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // CtrRegs64_and_V62Regs
      22, // isub_hi -> CtrRegs64_and_V62Regs
      22, // isub_lo -> CtrRegs64_and_V62Regs
      0,  // subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // CtrRegs64_with_isub_hi_in_ModRegs
      23, // isub_hi -> CtrRegs64_with_isub_hi_in_ModRegs
      23, // isub_lo -> CtrRegs64_with_isub_hi_in_ModRegs
      0,  // subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // HvxQR
      0,  // isub_hi
      0,  // isub_lo
      0,  // subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // HvxVR
      0,  // isub_hi
      0,  // isub_lo
      0,  // subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // HvxVR_and_V65Regs
      0,  // isub_hi
      0,  // isub_lo
      0,  // subreg_overflow
      0,  // vsub_fake
      0,  // vsub_hi
      0,  // vsub_lo
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // HvxWR
      0,  // isub_hi
      0,  // isub_lo
      0,  // subreg_overflow
      0,  // vsub_fake
      27, // vsub_hi -> HvxWR
      27, // vsub_lo -> HvxWR
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // HvxWR_and_VectRegRev
      0,  // isub_hi
      0,  // isub_lo
      0,  // subreg_overflow
      0,  // vsub_fake
      28, // vsub_hi -> HvxWR_and_VectRegRev
      28, // vsub_lo -> HvxWR_and_VectRegRev
      0,  // wsub_hi
      0,  // wsub_lo
      0,  // wsub_hi_then_vsub_fake
      0,  // wsub_hi_then_vsub_hi
      0,  // wsub_hi_then_vsub_lo
    },
    { // HvxVQR
      0,  // isub_hi
      0,  // isub_lo
      0,  // subreg_overflow
      0,  // vsub_fake
      29, // vsub_hi -> HvxVQR
      29, // vsub_lo -> HvxVQR
      29, // wsub_hi -> HvxVQR
      29, // wsub_lo -> HvxVQR
      0,  // wsub_hi_then_vsub_fake
      29, // wsub_hi_then_vsub_hi -> HvxVQR
      29, // wsub_hi_then_vsub_lo -> HvxVQR
    },
  };
  assert(RC && "Missing regclass");
  if (!Idx) return RC;
  --Idx;
  assert(Idx < 11 && "Bad subreg");
  unsigned TV = Table[RC->getID()][Idx];
  return TV ? getRegClass(TV - 1) : nullptr;
}

const TargetRegisterClass *HexagonGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
  static const uint8_t Table[29][11] = {
    { // UsrBits
      0,  // UsrBits:isub_hi
      0,  // UsrBits:isub_lo
      0,  // UsrBits:subreg_overflow
      0,  // UsrBits:vsub_fake
      0,  // UsrBits:vsub_hi
      0,  // UsrBits:vsub_lo
      0,  // UsrBits:wsub_hi
      0,  // UsrBits:wsub_lo
      0,  // UsrBits:wsub_hi_then_vsub_fake
      0,  // UsrBits:wsub_hi_then_vsub_hi
      0,  // UsrBits:wsub_hi_then_vsub_lo
    },
    { // SysRegs
      0,  // SysRegs:isub_hi
      0,  // SysRegs:isub_lo
      0,  // SysRegs:subreg_overflow
      0,  // SysRegs:vsub_fake
      0,  // SysRegs:vsub_hi
      0,  // SysRegs:vsub_lo
      0,  // SysRegs:wsub_hi
      0,  // SysRegs:wsub_lo
      0,  // SysRegs:wsub_hi_then_vsub_fake
      0,  // SysRegs:wsub_hi_then_vsub_hi
      0,  // SysRegs:wsub_hi_then_vsub_lo
    },
    { // GuestRegs
      0,  // GuestRegs:isub_hi
      0,  // GuestRegs:isub_lo
      0,  // GuestRegs:subreg_overflow
      0,  // GuestRegs:vsub_fake
      0,  // GuestRegs:vsub_hi
      0,  // GuestRegs:vsub_lo
      0,  // GuestRegs:wsub_hi
      0,  // GuestRegs:wsub_lo
      0,  // GuestRegs:wsub_hi_then_vsub_fake
      0,  // GuestRegs:wsub_hi_then_vsub_hi
      0,  // GuestRegs:wsub_hi_then_vsub_lo
    },
    { // IntRegs
      0,  // IntRegs:isub_hi
      0,  // IntRegs:isub_lo
      0,  // IntRegs:subreg_overflow
      0,  // IntRegs:vsub_fake
      0,  // IntRegs:vsub_hi
      0,  // IntRegs:vsub_lo
      0,  // IntRegs:wsub_hi
      0,  // IntRegs:wsub_lo
      0,  // IntRegs:wsub_hi_then_vsub_fake
      0,  // IntRegs:wsub_hi_then_vsub_hi
      0,  // IntRegs:wsub_hi_then_vsub_lo
    },
    { // CtrRegs
      0,  // CtrRegs:isub_hi
      0,  // CtrRegs:isub_lo
      1,  // CtrRegs:subreg_overflow -> UsrBits
      0,  // CtrRegs:vsub_fake
      0,  // CtrRegs:vsub_hi
      0,  // CtrRegs:vsub_lo
      0,  // CtrRegs:wsub_hi
      0,  // CtrRegs:wsub_lo
      0,  // CtrRegs:wsub_hi_then_vsub_fake
      0,  // CtrRegs:wsub_hi_then_vsub_hi
      0,  // CtrRegs:wsub_hi_then_vsub_lo
    },
    { // GeneralSubRegs
      0,  // GeneralSubRegs:isub_hi
      0,  // GeneralSubRegs:isub_lo
      0,  // GeneralSubRegs:subreg_overflow
      0,  // GeneralSubRegs:vsub_fake
      0,  // GeneralSubRegs:vsub_hi
      0,  // GeneralSubRegs:vsub_lo
      0,  // GeneralSubRegs:wsub_hi
      0,  // GeneralSubRegs:wsub_lo
      0,  // GeneralSubRegs:wsub_hi_then_vsub_fake
      0,  // GeneralSubRegs:wsub_hi_then_vsub_hi
      0,  // GeneralSubRegs:wsub_hi_then_vsub_lo
    },
    { // V62Regs
      9,  // V62Regs:isub_hi -> CtrRegs_and_V62Regs
      9,  // V62Regs:isub_lo -> CtrRegs_and_V62Regs
      0,  // V62Regs:subreg_overflow
      0,  // V62Regs:vsub_fake
      0,  // V62Regs:vsub_hi
      0,  // V62Regs:vsub_lo
      0,  // V62Regs:wsub_hi
      0,  // V62Regs:wsub_lo
      0,  // V62Regs:wsub_hi_then_vsub_fake
      0,  // V62Regs:wsub_hi_then_vsub_hi
      0,  // V62Regs:wsub_hi_then_vsub_lo
    },
    { // IntRegsLow8
      0,  // IntRegsLow8:isub_hi
      0,  // IntRegsLow8:isub_lo
      0,  // IntRegsLow8:subreg_overflow
      0,  // IntRegsLow8:vsub_fake
      0,  // IntRegsLow8:vsub_hi
      0,  // IntRegsLow8:vsub_lo
      0,  // IntRegsLow8:wsub_hi
      0,  // IntRegsLow8:wsub_lo
      0,  // IntRegsLow8:wsub_hi_then_vsub_fake
      0,  // IntRegsLow8:wsub_hi_then_vsub_hi
      0,  // IntRegsLow8:wsub_hi_then_vsub_lo
    },
    { // CtrRegs_and_V62Regs
      0,  // CtrRegs_and_V62Regs:isub_hi
      0,  // CtrRegs_and_V62Regs:isub_lo
      0,  // CtrRegs_and_V62Regs:subreg_overflow
      0,  // CtrRegs_and_V62Regs:vsub_fake
      0,  // CtrRegs_and_V62Regs:vsub_hi
      0,  // CtrRegs_and_V62Regs:vsub_lo
      0,  // CtrRegs_and_V62Regs:wsub_hi
      0,  // CtrRegs_and_V62Regs:wsub_lo
      0,  // CtrRegs_and_V62Regs:wsub_hi_then_vsub_fake
      0,  // CtrRegs_and_V62Regs:wsub_hi_then_vsub_hi
      0,  // CtrRegs_and_V62Regs:wsub_hi_then_vsub_lo
    },
    { // PredRegs
      0,  // PredRegs:isub_hi
      0,  // PredRegs:isub_lo
      0,  // PredRegs:subreg_overflow
      0,  // PredRegs:vsub_fake
      0,  // PredRegs:vsub_hi
      0,  // PredRegs:vsub_lo
      0,  // PredRegs:wsub_hi
      0,  // PredRegs:wsub_lo
      0,  // PredRegs:wsub_hi_then_vsub_fake
      0,  // PredRegs:wsub_hi_then_vsub_hi
      0,  // PredRegs:wsub_hi_then_vsub_lo
    },
    { // V62Regs_with_isub_hi
      9,  // V62Regs_with_isub_hi:isub_hi -> CtrRegs_and_V62Regs
      9,  // V62Regs_with_isub_hi:isub_lo -> CtrRegs_and_V62Regs
      0,  // V62Regs_with_isub_hi:subreg_overflow
      0,  // V62Regs_with_isub_hi:vsub_fake
      0,  // V62Regs_with_isub_hi:vsub_hi
      0,  // V62Regs_with_isub_hi:vsub_lo
      0,  // V62Regs_with_isub_hi:wsub_hi
      0,  // V62Regs_with_isub_hi:wsub_lo
      0,  // V62Regs_with_isub_hi:wsub_hi_then_vsub_fake
      0,  // V62Regs_with_isub_hi:wsub_hi_then_vsub_hi
      0,  // V62Regs_with_isub_hi:wsub_hi_then_vsub_lo
    },
    { // ModRegs
      0,  // ModRegs:isub_hi
      0,  // ModRegs:isub_lo
      0,  // ModRegs:subreg_overflow
      0,  // ModRegs:vsub_fake
      0,  // ModRegs:vsub_hi
      0,  // ModRegs:vsub_lo
      0,  // ModRegs:wsub_hi
      0,  // ModRegs:wsub_lo
      0,  // ModRegs:wsub_hi_then_vsub_fake
      0,  // ModRegs:wsub_hi_then_vsub_hi
      0,  // ModRegs:wsub_hi_then_vsub_lo
    },
    { // CtrRegs_with_subreg_overflow
      0,  // CtrRegs_with_subreg_overflow:isub_hi
      0,  // CtrRegs_with_subreg_overflow:isub_lo
      1,  // CtrRegs_with_subreg_overflow:subreg_overflow -> UsrBits
      0,  // CtrRegs_with_subreg_overflow:vsub_fake
      0,  // CtrRegs_with_subreg_overflow:vsub_hi
      0,  // CtrRegs_with_subreg_overflow:vsub_lo
      0,  // CtrRegs_with_subreg_overflow:wsub_hi
      0,  // CtrRegs_with_subreg_overflow:wsub_lo
      0,  // CtrRegs_with_subreg_overflow:wsub_hi_then_vsub_fake
      0,  // CtrRegs_with_subreg_overflow:wsub_hi_then_vsub_hi
      0,  // CtrRegs_with_subreg_overflow:wsub_hi_then_vsub_lo
    },
    { // V65Regs
      0,  // V65Regs:isub_hi
      0,  // V65Regs:isub_lo
      0,  // V65Regs:subreg_overflow
      0,  // V65Regs:vsub_fake
      0,  // V65Regs:vsub_hi
      0,  // V65Regs:vsub_lo
      0,  // V65Regs:wsub_hi
      0,  // V65Regs:wsub_lo
      0,  // V65Regs:wsub_hi_then_vsub_fake
      0,  // V65Regs:wsub_hi_then_vsub_hi
      0,  // V65Regs:wsub_hi_then_vsub_lo
    },
    { // SysRegs64
      2,  // SysRegs64:isub_hi -> SysRegs
      2,  // SysRegs64:isub_lo -> SysRegs
      0,  // SysRegs64:subreg_overflow
      0,  // SysRegs64:vsub_fake
      0,  // SysRegs64:vsub_hi
      0,  // SysRegs64:vsub_lo
      0,  // SysRegs64:wsub_hi
      0,  // SysRegs64:wsub_lo
      0,  // SysRegs64:wsub_hi_then_vsub_fake
      0,  // SysRegs64:wsub_hi_then_vsub_hi
      0,  // SysRegs64:wsub_hi_then_vsub_lo
    },
    { // DoubleRegs
      4,  // DoubleRegs:isub_hi -> IntRegs
      4,  // DoubleRegs:isub_lo -> IntRegs
      0,  // DoubleRegs:subreg_overflow
      0,  // DoubleRegs:vsub_fake
      0,  // DoubleRegs:vsub_hi
      0,  // DoubleRegs:vsub_lo
      0,  // DoubleRegs:wsub_hi
      0,  // DoubleRegs:wsub_lo
      0,  // DoubleRegs:wsub_hi_then_vsub_fake
      0,  // DoubleRegs:wsub_hi_then_vsub_hi
      0,  // DoubleRegs:wsub_hi_then_vsub_lo
    },
    { // GuestRegs64
      3,  // GuestRegs64:isub_hi -> GuestRegs
      3,  // GuestRegs64:isub_lo -> GuestRegs
      0,  // GuestRegs64:subreg_overflow
      0,  // GuestRegs64:vsub_fake
      0,  // GuestRegs64:vsub_hi
      0,  // GuestRegs64:vsub_lo
      0,  // GuestRegs64:wsub_hi
      0,  // GuestRegs64:wsub_lo
      0,  // GuestRegs64:wsub_hi_then_vsub_fake
      0,  // GuestRegs64:wsub_hi_then_vsub_hi
      0,  // GuestRegs64:wsub_hi_then_vsub_lo
    },
    { // VectRegRev
      0,  // VectRegRev:isub_hi
      0,  // VectRegRev:isub_lo
      0,  // VectRegRev:subreg_overflow
      0,  // VectRegRev:vsub_fake
      25, // VectRegRev:vsub_hi -> HvxVR
      25, // VectRegRev:vsub_lo -> HvxVR
      0,  // VectRegRev:wsub_hi
      0,  // VectRegRev:wsub_lo
      0,  // VectRegRev:wsub_hi_then_vsub_fake
      0,  // VectRegRev:wsub_hi_then_vsub_hi
      0,  // VectRegRev:wsub_hi_then_vsub_lo
    },
    { // CtrRegs64
      5,  // CtrRegs64:isub_hi -> CtrRegs
      5,  // CtrRegs64:isub_lo -> CtrRegs
      0,  // CtrRegs64:subreg_overflow
      0,  // CtrRegs64:vsub_fake
      0,  // CtrRegs64:vsub_hi
      0,  // CtrRegs64:vsub_lo
      0,  // CtrRegs64:wsub_hi
      0,  // CtrRegs64:wsub_lo
      0,  // CtrRegs64:wsub_hi_then_vsub_fake
      0,  // CtrRegs64:wsub_hi_then_vsub_hi
      0,  // CtrRegs64:wsub_hi_then_vsub_lo
    },
    { // GeneralDoubleLow8Regs
      6,  // GeneralDoubleLow8Regs:isub_hi -> GeneralSubRegs
      6,  // GeneralDoubleLow8Regs:isub_lo -> GeneralSubRegs
      0,  // GeneralDoubleLow8Regs:subreg_overflow
      0,  // GeneralDoubleLow8Regs:vsub_fake
      0,  // GeneralDoubleLow8Regs:vsub_hi
      0,  // GeneralDoubleLow8Regs:vsub_lo
      0,  // GeneralDoubleLow8Regs:wsub_hi
      0,  // GeneralDoubleLow8Regs:wsub_lo
      0,  // GeneralDoubleLow8Regs:wsub_hi_then_vsub_fake
      0,  // GeneralDoubleLow8Regs:wsub_hi_then_vsub_hi
      0,  // GeneralDoubleLow8Regs:wsub_hi_then_vsub_lo
    },
    { // DoubleRegs_with_isub_hi_in_IntRegsLow8
      8,  // DoubleRegs_with_isub_hi_in_IntRegsLow8:isub_hi -> IntRegsLow8
      8,  // DoubleRegs_with_isub_hi_in_IntRegsLow8:isub_lo -> IntRegsLow8
      0,  // DoubleRegs_with_isub_hi_in_IntRegsLow8:subreg_overflow
      0,  // DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_fake
      0,  // DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_hi
      0,  // DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_lo
      0,  // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi
      0,  // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_lo
      0,  // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi_then_vsub_fake
      0,  // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi_then_vsub_hi
      0,  // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi_then_vsub_lo
    },
    { // CtrRegs64_and_V62Regs
      9,  // CtrRegs64_and_V62Regs:isub_hi -> CtrRegs_and_V62Regs
      9,  // CtrRegs64_and_V62Regs:isub_lo -> CtrRegs_and_V62Regs
      0,  // CtrRegs64_and_V62Regs:subreg_overflow
      0,  // CtrRegs64_and_V62Regs:vsub_fake
      0,  // CtrRegs64_and_V62Regs:vsub_hi
      0,  // CtrRegs64_and_V62Regs:vsub_lo
      0,  // CtrRegs64_and_V62Regs:wsub_hi
      0,  // CtrRegs64_and_V62Regs:wsub_lo
      0,  // CtrRegs64_and_V62Regs:wsub_hi_then_vsub_fake
      0,  // CtrRegs64_and_V62Regs:wsub_hi_then_vsub_hi
      0,  // CtrRegs64_and_V62Regs:wsub_hi_then_vsub_lo
    },
    { // CtrRegs64_with_isub_hi_in_ModRegs
      12, // CtrRegs64_with_isub_hi_in_ModRegs:isub_hi -> ModRegs
      12, // CtrRegs64_with_isub_hi_in_ModRegs:isub_lo -> ModRegs
      0,  // CtrRegs64_with_isub_hi_in_ModRegs:subreg_overflow
      0,  // CtrRegs64_with_isub_hi_in_ModRegs:vsub_fake
      0,  // CtrRegs64_with_isub_hi_in_ModRegs:vsub_hi
      0,  // CtrRegs64_with_isub_hi_in_ModRegs:vsub_lo
      0,  // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi
      0,  // CtrRegs64_with_isub_hi_in_ModRegs:wsub_lo
      0,  // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi_then_vsub_fake
      0,  // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi_then_vsub_hi
      0,  // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi_then_vsub_lo
    },
    { // HvxQR
      0,  // HvxQR:isub_hi
      0,  // HvxQR:isub_lo
      0,  // HvxQR:subreg_overflow
      0,  // HvxQR:vsub_fake
      0,  // HvxQR:vsub_hi
      0,  // HvxQR:vsub_lo
      0,  // HvxQR:wsub_hi
      0,  // HvxQR:wsub_lo
      0,  // HvxQR:wsub_hi_then_vsub_fake
      0,  // HvxQR:wsub_hi_then_vsub_hi
      0,  // HvxQR:wsub_hi_then_vsub_lo
    },
    { // HvxVR
      0,  // HvxVR:isub_hi
      0,  // HvxVR:isub_lo
      0,  // HvxVR:subreg_overflow
      0,  // HvxVR:vsub_fake
      0,  // HvxVR:vsub_hi
      0,  // HvxVR:vsub_lo
      0,  // HvxVR:wsub_hi
      0,  // HvxVR:wsub_lo
      0,  // HvxVR:wsub_hi_then_vsub_fake
      0,  // HvxVR:wsub_hi_then_vsub_hi
      0,  // HvxVR:wsub_hi_then_vsub_lo
    },
    { // HvxVR_and_V65Regs
      0,  // HvxVR_and_V65Regs:isub_hi
      0,  // HvxVR_and_V65Regs:isub_lo
      0,  // HvxVR_and_V65Regs:subreg_overflow
      0,  // HvxVR_and_V65Regs:vsub_fake
      0,  // HvxVR_and_V65Regs:vsub_hi
      0,  // HvxVR_and_V65Regs:vsub_lo
      0,  // HvxVR_and_V65Regs:wsub_hi
      0,  // HvxVR_and_V65Regs:wsub_lo
      0,  // HvxVR_and_V65Regs:wsub_hi_then_vsub_fake
      0,  // HvxVR_and_V65Regs:wsub_hi_then_vsub_hi
      0,  // HvxVR_and_V65Regs:wsub_hi_then_vsub_lo
    },
    { // HvxWR
      0,  // HvxWR:isub_hi
      0,  // HvxWR:isub_lo
      0,  // HvxWR:subreg_overflow
      0,  // HvxWR:vsub_fake
      25, // HvxWR:vsub_hi -> HvxVR
      25, // HvxWR:vsub_lo -> HvxVR
      0,  // HvxWR:wsub_hi
      0,  // HvxWR:wsub_lo
      0,  // HvxWR:wsub_hi_then_vsub_fake
      0,  // HvxWR:wsub_hi_then_vsub_hi
      0,  // HvxWR:wsub_hi_then_vsub_lo
    },
    { // HvxWR_and_VectRegRev
      0,  // HvxWR_and_VectRegRev:isub_hi
      0,  // HvxWR_and_VectRegRev:isub_lo
      0,  // HvxWR_and_VectRegRev:subreg_overflow
      0,  // HvxWR_and_VectRegRev:vsub_fake
      25, // HvxWR_and_VectRegRev:vsub_hi -> HvxVR
      25, // HvxWR_and_VectRegRev:vsub_lo -> HvxVR
      0,  // HvxWR_and_VectRegRev:wsub_hi
      0,  // HvxWR_and_VectRegRev:wsub_lo
      0,  // HvxWR_and_VectRegRev:wsub_hi_then_vsub_fake
      0,  // HvxWR_and_VectRegRev:wsub_hi_then_vsub_hi
      0,  // HvxWR_and_VectRegRev:wsub_hi_then_vsub_lo
    },
    { // HvxVQR
      0,  // HvxVQR:isub_hi
      0,  // HvxVQR:isub_lo
      0,  // HvxVQR:subreg_overflow
      0,  // HvxVQR:vsub_fake
      25, // HvxVQR:vsub_hi -> HvxVR
      25, // HvxVQR:vsub_lo -> HvxVR
      27, // HvxVQR:wsub_hi -> HvxWR
      27, // HvxVQR:wsub_lo -> HvxWR
      0,  // HvxVQR:wsub_hi_then_vsub_fake
      25, // HvxVQR:wsub_hi_then_vsub_hi -> HvxVR
      25, // HvxVQR:wsub_hi_then_vsub_lo -> HvxVR
    },
  };
  assert(RC && "Missing regclass");
  if (!Idx) return RC;
  --Idx;
  assert(Idx < 11 && "Bad subreg");
  unsigned TV = Table[RC->getID()][Idx];
  return TV ? getRegClass(TV - 1) : nullptr;
}

/// Get the weight in units of pressure for this register class.
const RegClassWeight &HexagonGenRegisterInfo::
getRegClassWeight(const TargetRegisterClass *RC) const {
  static const RegClassWeight RCWeightTable[] = {
    {0, 0},   // UsrBits
    {0, 0},   // SysRegs
    {0, 0},   // GuestRegs
    {1, 32},    // IntRegs
    {0, 6},   // CtrRegs
    {1, 16},    // GeneralSubRegs
    {0, 0},   // V62Regs
    {1, 8},   // IntRegsLow8
    {0, 0},   // CtrRegs_and_V62Regs
    {1, 4},   // PredRegs
    {0, 0},   // V62Regs_with_isub_hi
    {1, 2},   // ModRegs
    {0, 0},   // CtrRegs_with_subreg_overflow
    {1, 1},   // V65Regs
    {0, 0},   // SysRegs64
    {2, 32},    // DoubleRegs
    {0, 0},   // GuestRegs64
    {2, 32},    // VectRegRev
    {0, 6},   // CtrRegs64
    {2, 16},    // GeneralDoubleLow8Regs
    {2, 8},   // DoubleRegs_with_isub_hi_in_IntRegsLow8
    {0, 0},   // CtrRegs64_and_V62Regs
    {2, 2},   // CtrRegs64_with_isub_hi_in_ModRegs
    {1, 4},   // HvxQR
    {1, 33},    // HvxVR
    {1, 1},   // HvxVR_and_V65Regs
    {2, 32},    // HvxWR
    {2, 32},    // HvxWR_and_VectRegRev
    {4, 32},    // HvxVQR
  };
  return RCWeightTable[RC->getID()];
}

/// Get the weight in units of pressure for this register unit.
unsigned HexagonGenRegisterInfo::
getRegUnitWeight(unsigned RegUnit) const {
  assert(RegUnit < 272 && "invalid register unit");
  // All register units have unit weight.
  return 1;
}


// Get the number of dimensions of register pressure.
unsigned HexagonGenRegisterInfo::getNumRegPressureSets() const {
  return 8;
}

// Get the name of this register unit pressure set.
const char *HexagonGenRegisterInfo::
getRegPressureSetName(unsigned Idx) const {
  static const char *PressureNameTable[] = {
    "HvxVR_and_V65Regs",
    "ModRegs",
    "PredRegs",
    "HvxQR",
    "IntRegsLow8",
    "GeneralSubRegs",
    "IntRegs",
    "HvxVR",
  };
  return PressureNameTable[Idx];
}

// Get the register unit pressure limit for this dimension.
// This limit must be adjusted dynamically for reserved registers.
unsigned HexagonGenRegisterInfo::
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
  static const uint8_t PressureLimitTable[] = {
    1,    // 0: HvxVR_and_V65Regs
    2,    // 1: ModRegs
    4,    // 2: PredRegs
    4,    // 3: HvxQR
    8,    // 4: IntRegsLow8
    16,   // 5: GeneralSubRegs
    32,   // 6: IntRegs
    33,   // 7: HvxVR
  };
  return PressureLimitTable[Idx];
}

/// Table of pressure sets per register class or unit.
static const int RCSetsTable[] = {
  /* 0 */ 1, -1,
  /* 2 */ 2, -1,
  /* 4 */ 3, -1,
  /* 6 */ 4, 5, 6, -1,
  /* 10 */ 0, 7, -1,
};

/// Get the dimensions of register pressure impacted by this register class.
/// Returns a -1 terminated array of pressure set IDs
const int *HexagonGenRegisterInfo::
getRegClassPressureSets(const TargetRegisterClass *RC) const {
  static const uint8_t RCSetStartTable[] = {
    1,1,1,8,1,7,1,6,1,2,1,0,1,1,1,8,1,11,1,7,6,1,1,4,11,10,11,11,11,};
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
}

/// Get the dimensions of register pressure impacted by this register unit.
/// Returns a -1 terminated array of pressure set IDs
const int *HexagonGenRegisterInfo::
getRegUnitPressureSets(unsigned RegUnit) const {
  assert(RegUnit < 272 && "invalid register unit");
  static const uint8_t RUSetStartTable[] = {
    1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,10,1,1,1,1,1,1,1,6,6,6,6,6,6,6,6,8,8,8,8,8,8,8,8,7,7,7,7,7,7,7,7,8,8,8,8,8,8,8,8,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,2,2,2,2,1,1,1,1,4,4,4,4,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,};
  return &RCSetsTable[RUSetStartTable[RegUnit]];
}

extern const MCRegisterDesc HexagonRegDesc[];
extern const int16_t HexagonRegDiffLists[];
extern const LaneBitmask HexagonLaneMaskLists[];
extern const char HexagonRegStrings[];
extern const char HexagonRegClassStrings[];
extern const MCPhysReg HexagonRegUnitRoots[][2];
extern const uint16_t HexagonSubRegIdxLists[];
extern const MCRegisterInfo::SubRegCoveredBits HexagonSubRegIdxRanges[];
extern const uint16_t HexagonRegEncodingTable[];
// Hexagon Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0Dwarf2L[];
extern const unsigned HexagonDwarfFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0Dwarf2L[];
extern const unsigned HexagonEHFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0L2Dwarf[];
extern const unsigned HexagonDwarfFlavour0L2DwarfSize;

extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0L2Dwarf[];
extern const unsigned HexagonEHFlavour0L2DwarfSize;

HexagonGenRegisterInfo::
HexagonGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
      unsigned PC, unsigned HwMode)
  : TargetRegisterInfo(&HexagonRegInfoDesc, RegisterClasses, RegisterClasses+29,
             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
             LaneBitmask(0xFFFFFFFFFFFFFFFB), RegClassInfos, VTLists, HwMode) {
  InitMCRegisterInfo(HexagonRegDesc, 398, RA, PC,
                     HexagonMCRegisterClasses, 29,
                     HexagonRegUnitRoots,
                     272,
                     HexagonRegDiffLists,
                     HexagonLaneMaskLists,
                     HexagonRegStrings,
                     HexagonRegClassStrings,
                     HexagonSubRegIdxLists,
                     12,
                     HexagonSubRegIdxRanges,
                     HexagonRegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(HexagonDwarfFlavour0Dwarf2L, HexagonDwarfFlavour0Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(HexagonEHFlavour0Dwarf2L, HexagonEHFlavour0Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(HexagonDwarfFlavour0L2Dwarf, HexagonDwarfFlavour0L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(HexagonEHFlavour0L2Dwarf, HexagonEHFlavour0L2DwarfSize, true);
    break;
  }
}

static const MCPhysReg HexagonCSR_SaveList[] = { Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 };
static const uint32_t HexagonCSR_RegMask[] = { 0x00000000, 0x00000000, 0x0000007e, 0x00000000, 0x0003ffc0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };


ArrayRef<const uint32_t *> HexagonGenRegisterInfo::getRegMasks() const {
  static const uint32_t *const Masks[] = {
    HexagonCSR_RegMask,
  };
  return ArrayRef(Masks);
}

bool HexagonGenRegisterInfo::
isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool HexagonGenRegisterInfo::
isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool HexagonGenRegisterInfo::
isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool HexagonGenRegisterInfo::
isConstantPhysReg(MCRegister PhysReg) const {
  return
      false;
}

ArrayRef<const char *> HexagonGenRegisterInfo::getRegMaskNames() const {
  static const char *Names[] = {
    "HexagonCSR",
  };
  return ArrayRef(Names);
}

const HexagonFrameLowering *
HexagonGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
  return static_cast<const HexagonFrameLowering *>(
      MF.getSubtarget().getFrameLowering());
}

} // end namespace llvm

#endif // GET_REGINFO_TARGET_DESC


Coverage Report

Created: 2024-01-17 10:31